tkgate-2.0-b10000777 001751 001751 00000000000 11257536675 013754 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/README000644 001751 001751 00000056054 11257530202 014675 0ustar00hansenhansen000000 000000 TkGate 2.0 Release notes. See INSTALL for installation instructions. ***************************************************************************** SAVE FILE DIFFERENCES WITH PAST VERSIONS 2.0-b5 and earlier The DEMUX device was redesigned in 2.0-b5. When reading earlier save files, any instance of DEMUX are translated to OLDDEMUX which have the original definition. 1.8.x and earlier Substantial changes in save file format were made in the transition from 1.8.x to 2.0. The new format is expected to be compliant with 3rd party verilog tools. TkGate 2.0 can read files from earlier versions of tkgate but can only write 2.0 format files which will be unreadable by earlier versions of tkgate. 1.6h and earlier These versions do not support the "extender bar" style of basic gates. Files saved by later versions may either not load properly, or may have input wires in odd places when loaded under old versions of tkgate. 1.5c and earlier Positions of wire "tap" elements have changed slightly due to the new method for drawing buses. When reading old files, the positions will be slightly modified to fit the new scheme, but if you save the file, wire positions will be slightly off when rereading from an old version of tkgate. Basic flip-flop elements do not exist in this version and lower. 1.4c and earlier Multi-technology delay specification, and per-gate delay specification is not supported. If any delays other than "default" are used, the file may not be readable by older versions of tkgate. ***************************************************************************** MULTI-LINGUAL SUPPORT (JAPANESE) As of TkGate 2.0, Japanese support is automatically compiled in. To use it, run tkgate with the -Lja option, or make sure your LANG environment variable is set to a Japanese locale (e.g., ja_JP.eucJP). Attempting to run TkGate with an invalid locality value could cause it to core dump in the tcl/tk initialization routines. You must also set up kanji conversion and input servers in order to input Japanese. Currently, Japanese is only supported in comments and "frames". There are many ways of configuring kanji conversion and input servers, so I will not go into all of them here. I have tested tkgate with canna. Make the following changes to enable Japanese input: In .xinitrc: kinput2 -canna -xim& In .cshrc: setenv XMODIFIERS "@im=kinput2" To enter switch between English input and Japanese input use the command . While Japanese messages are enabled for any locale name that starts with "ja", the locale must be set to "ja_JP.eucJP" in order to enable Japanese input. Using the '-Lja' switch will also ensure that the environment variables are set correctly. ***************************************************************************** CREDITS * Thanks to Marc Lavallee for Linux rpm spec file. * Thanks to Peter Bartke for the German translation. * Thanks to Laurent Bonnaud for the French translation. * Thanks to Agustin Borrego for the Spanish translation. * Thanks to Kevin Donnelly for the Welsh translation. * Thanks to Jacques JANVILLE for the French translation and French tutorials. * Thanks to Marc Lavallee for Linux rpm spec file. * Thanks to Roman Valls for the Catalan translation. * Thanks to Anthony Winstanley for the cygwin patch. ***************************************************************************** VERSION HISTORY Version 2.0-b10 - September 26, 2009 * Fixed bug causing bar led to display wrong value when some bits are unknown. * Fixed bug making "Add" button inactive in port list dialog box for concat components. * Fixed bug in memory viewer for memories with 256 words or less. * Fixed bug causing initialization file specs. on memories not to be recognized. Version 2.0-b9 - May 5, 2009 * Fixed bug causing core dump when reversing port ordering on decoder. * Fixed bug in updating module tree when creating module instances. * Expanded components in the 74xx library. Version 2.0-b8 - April 25, 2009 * Fixed bug with libraries with no descriptions. * Fixed bug in freeing of memory in circuit properties editing which caused a core dump on some systems. * Fixed bug in module interface update when loading a module that overrides a library module of the same name. * Fixed bug in display of scope axis when non-standard timescale is used. Version 2.0-b7 - February 23, 2009 * Wire names can be displayed on switches/dips * Right click on wires now sensitive to label/size markings. * Added ability to supress timing violation notices. * Fixed bug causing excessive calls to html formatter in comments objects. * Fixed bug with cut/paste in HDL modules. * Fixed bug with module interface autogeneration of HDL modules. * Fixed bug with module properties not being saved properly Version 2.0-b6 - February 12, 2009 * Created new "Scripts" tab in Circuit Properties dialog box. Moved list of start-up scripts to the new page. * Moved the "Auto Start" option from the "General" page to the "Simulation" page in the Circuit Properties box. * Added a "Design Initialization Time" circuit property that can specify a time over which to ignore timing violations. Version 2.0-b6 - February 6, 2009 * Fixed detection of iconv.h * Fixed Japanese font problem in tk elements. * Fixed bugs with wire handling, library handling, simulation error handling. * Fixed bug with switches not updating in GUI when controlled by script. * Updated "Details" pages of several gate properties dialog boxes. * Improved handling of locales * Tabbing in dialog boxes added * Reorganized main menus * Renamed DEMUX as DECODER. Added a properly defined DEMUX. * Updated most of the Japanese locale strings * Updated all German locale strings and tutorials * Added JK Flip-Flop * Added "Script" component that allows you to include Verilog snippets in netlist modules. * Added memory content viewer * Added "current time" display when simulator is active. Version 2.0-b5 - Internal Only Version 2.0-b4 - January 10, 2009 * Fixed core dump bug caused by clicking in scope window below list of traces. * Cleaned up interface look. * Fixed sizing problem with dialog boxes that sometimes caused clipping of the dialog box elements. * Fixed simulator bug in register initialization. Registers were not being initialized until end of time step 0 and were triggering events. * Fixed problem with initial display of flip-flop type in properties dialog box. * Updated gmac to produce new-style memory files (-g can be used to get old-style files). * Fixed problem with entries in port box not getting highlighted when clicked on. * Fixed memory problem that happens when doing "new circuit" from menu. * Fixed bug with module copy/rename, etc. dialog boxes not going away on "OK" * Fixed bug with rename of currently viewed module. * Dialog titlebars now localizable. Version 2.0-b3 - January 2, 2009 * Grab and scroll tool (and auto grab with button 2) * New options setting dialog box * Mouse over highlighting for tabs * Wires with bit sizes greater than 32 bits * Fixed bug with warning reporting in simulation mode * Updated print dialog box * Updated library manager and added it to the circuit properies box * Fixed problem with display of Japanese in main edit window. * Additional minor bug fixes. Version 2.0-b2 - December 22, 2008 * Fixed problem with leds in modules * Fixed edge problem with ranges in scope window * Fixed display problem with scope print dialog box * Fixed problem with saving of wire merge devices * Fixed some problems with unnecessary setting of "modified" flag * Probe positions now remembered between simulation runs * You can now drag and reposition traces in scope. * Mouse over of signal names in scope will show full name. * Fixed simulator bug when assigning concat to a variable with a bit width larger than the source. Version 2.0-b1 - December 1, 2008 * Updated to work with tcl/tk 8.5 * Fixed bug in flip-flop device. * Create verilog template system for built-in devices (see primitives directory) * Fixed bug in "Delete Module" dialog box causing core dump when dialog was closed by pressing enter. Version 2.0-a12 - September 24, 2007 * Cleanup of some names in menus. * Added key bindings for interface update features. Version 2.0-a11 - September 24, 2007 * Fixed bugs and made minor feature enhancements to block port editing through popup menus. * Fixed bug causing delayed updates to graphical view in interface editor * Module instances can now be updated in place with new interfaces. * Slight redesign of the module interface type selector. Version 2.0-a10 - September 19, 2007 * Added mouse-over cursor change on edges of blocks. * Fixed problems with port names changing when wire is cut. * When connecting wires, oldest name is now given precedence in making name choice for merged wire. * Fixed problem with getting module edge popup menu when window has been scrolled. Version 2.0-a9 - September 12, 2007 * Fixed configure script to look in /opt/local for Tcl/Tk * Fixed bit-order problem in display of symbol modules on some platforms. * Fixed start-up crash on 64-bit machines. * Fixed bug in symbol editor that could cause loss of port information * Implement import/export of X bitmaps in symbol editor Version 2.0-a8 - August 18, 2007 * Fixed problem preventing hyperlinks from working when num-lock/scroll-lock was pressed. * Changed default install directory to /usr/local on all machines * Minor interface tweeks. Version 2.0-a7 - August 17, 2007 * Changed default install directory to /usr/local on non-FreeBSD machines. * Fixed some printing bugs * Fixed bugs with print dialog box * Fixed bug with display of gate name on "concat" elements * Fixed configuration problem with Italian locale * Ability to force TTY input from simulation script added. Version 2.0-a6 - July 13, 2007 * Made wire taps easier to select. * Fixed bug in layout of module interfaces. * Fixed bug allowing wires to be inappropriately manipulated in the interface display. * Initial draft of documentation for 2.0 Version 2.0-a5 - May 22, 2007 * Autoconf-based installation * Fixed bug preventing the shift-click sequence from being able to edit hyperlinks * Fixed some Japanese localization issues. Version 2.0-a1 - February 7, 2007 * Updated interface. * Support for textual Verilog module definitions. * All gates are now rotatable. Use Tab/Backtab to rotate selection. * Automatic interface generator. * Support for user defined symbols. * Hierarchical module browser. * Jump-to-module supported while in simulation mode. * Expanded and dockable toolbars. * Better library support. * Pinout options on concat, muxes, and demuxes. Version 1.8.4 - May 25, 2004 * Added memory of probes between invocations of the simulator. * Improved command-line printing capabilities. * Fixed a bug that resulted in a compilation error when compiling under a gcc version less than 3.0. * Fixed a bug that caused spurious warnings when printing a circuit directly from the command line. * Fixed another problem with EPSF output. * Fixed a bug with the critical path analysis of an empty circuit. * Fixed coding problem with Japanese messages file. * Fixed bug causing potential simulator core dump in critical path computation. Version 1.8.3 - March 18, 2004 * Fixed a bug occuring when creating or editing a comment after editing the ports on another circuit element. * Modules now printed in "hierarchical" order. * Updated German support and reorganized localization files. * Configure script now looks for MAC OS X directories. * Configure script is now more cygwin friendly. * Empty comments are no longer invisible. Version 1.8.2 - February 12 , 2004 * Fixed bug when loading library from command line. * Fixed bug when printing selected modules. * Fixed bug with '-V' circuit verify command. * Fixed bug in Edit menu with Algn Vert. and Algn Horz. being swapped. * Fixed bug with cut/paste of concat elements at 90/270 degree orientations. * Fixed bug with undo of wire taps. * Fixed bug with simulator error reporting. Version 1.8.1 - January 19, 2004 * Fixed bug occurring when clocks are used to drive adders. * Fixed bug with printing of partial scope traces. * Fixed bug in undo from edit module interface screen. * Added toolbar on scope window. * Added a "crosshair" feature to scopes. * Added a right-click selection capability on scopes for selecting print range. * Added capability to suppress sorting of traces on scope. Version 1.8 - January 7, 2004 * Fixed multiple bugs in the undo/redo code. * Updated toolbar icons and changed the behavior of the toolbar to be context sensitve. * Fixed compatability problems with tcl/tk 8.4. * Fixed printing problem with wire merge elements. * Fixed problem with very long clock cycle times. * Fixed problem with EPSF output. Version 1.7 - February 5, 2002 * Added multi-undo/-redo function. * Current technology of gates are now visible through popup menu. * Fixed bug allowing changes to anchor flag of gates in library modules. * Fixed bug occuring when doing "Edit Interfaces..." while currently editing a library module. Version 1.6i - February 5, 2002 * Added extender bars on multi-input (more than 2) AND, OR and XOR gates to avoid "crunching" of wires for gates with many inputs. This feature is off by default when loading save files for earlier versions of tkgate unless explicitly enabled. * Fixed problem with using some right mouse button popup commands when zoomed. * Increased delay between a mouse press and hold on a signal and the pop-up showing the signal value while in simulation mode. The previous short delay interfered with detection of a double click on some systems and thus made it difficult to set probes. It now also possible to customize this delay through the simulator page on options dialogue box. * Disabled bug allowing net options to be modified while in simulator mode. * Added alternate probe set/remove command using 'P' keyboard shortcut or menu. * Initial support for "hierarchy graph" for Postscript output added. This support is currently limited to graphs that fit on a single page. * Fixed several bugs that could sometimes cause a core dump and/or save file corruption when manipulating "wire tap" elements. * Fixed bug that sometimes resulted in a failure to determine the direction of concat (wire merge) elements. * Fixed a bug that caused calloc() to be called with nmemb=0. * Marked various popups as transient so they would not get buried under the main window. * Changed port add/editing so that an "*unnamed*" signal will be assigned a standard generated name. * Fixed bugs with port on editing through properties dialog box on modules. * Fixed problem with panic save feature. The panic save feature causes tkgate to attempt to save the current circuit in PANIC.v if a core dump is detected. * Produces less confusing messages when running under an unsupported locale. Version 1.6h - June 11, 2001 * Fixed printing problems with dips, muxes and registers. * Fixed Japanese in menus and tutorials. * Added bit selection feature for register codes to gmac. * Made '\r' a valid whitespace character. * Fixed bug that allowed creation of meaningless inverters on wire taps. * Fixed core dump bug with "replicating" wire taps. * Fixed serious problem with cut/paste causing internal data structures and save file data to become corrupt. The problem occured when gates attached to the same net were included in the cut, but one or more of the joints/taps on the net were not included in the cut causing a partitioning of the net. * Added a data structure integrity check feature. Version 1.6g - February 6, 2001 * Added zoom in/out feature. * Fixed core dump caused by start-up time errors on some platforms. * Fixed core dump caused by loading out-dated tkgate file while flashing critical path option is enabled. * Improved commenting of macrocode in "menagerie" example. * Minor change to scrollbar semantics Version 1.6f - November 30, 2000 * Fixed incorrect installation of Japanese tutorials. * Japanese Translation of tutorials partially completed. * Added support for Spanish. * Fixed problem with dialog windows being lowered when opening a subordinate load/save file box. * Fixed problem with setting label on frames. Version 1.6e - November 16, 2000 * Fixed problem with memories with less than 8-bit data lines. * Fixed possible direction problem with wire merge. Version 1.6d - October 19, 2000 * Fixed carry-out on 32-bit adders * Postscript generator now uses latin1 encoding to enable correct printing of accented characters. * Dip switch "value" boxes are now closed when exiting the simulation. * Fixed Japanese configure problem. Version 1.6c - October 16, 2000 * Improved multi-lingual support. * Added French support. Version 1.6b - October 4, 2000 * Fixed possible core dump problem when deleting gates. * Fixed configuration script problems. Version 1.6 - September 27, 2000 * Experimental support for critical path analysis * Highlighting of selected net * Smooth scrolling in edit window * Added a seprated "D flip-flop" element. * -P and -p switch allow printing without starting the GUI. * Fixed problem with non-functional output inverters on several gate types including registers, rams, roms and ttys. * Fixed hang problem with simulator when root module not at top of module stack. * Fixes problem with adding outputs to decoders. * Fixes extraneous "unknown version" messages when loading old save files. * Fixes problem with externally generated "destroy" events on scope windows. Version 1.5c - September 8, 2000 * Fixes an intermittent core dump problem in editor when manipulating wires. * Fixes problem with inverters in postscript output. * Fixes problem with configuration file in detecting existance of bison. Version 1.5b - June 27, 2000 * Fixes core dump problem in simulator. * Fixes possible core dump in editor when exiting simulator. Version 1.5 - June 26, 2000 * Support for multiple gate 'technologies' and per-gate delay specification added. * Menu and shortcut internals updated. Shortcuts and menus for gate definitions now contained in the gate definition files. This is a precursor to supporting user-definiable primitives. The new shortcut definition method allows keyboard shortcuts to be defined in .tkgaterc file. * Better recovery from syntax errors in input files. * Accedental editing of library modules disabled. An explicit "Claim" command was added to convert library modules to user modules. * Bug fixes - fixed slopy gate label positions - fixed slopy delete of mux/demux - fixed position of input numbers on mux/demux - fixed corruption of internal data structures when doing a cut/paste in Edit Interface page - fixed core dump when opeing "Edit Interfaces" while simulation was active (now disabled while in simulation mode). - fixed possible save file corruption due to null net names. - fixed multiple module instances on the Edit Interfaces page. - fixed erroneous setting of 'modified' flag when opening Edit Interfaces page. - fixed memory initialization problem in gsim causing periodic simulator crashes. - moved "Circuit Properties" command from "Module" menu to "Edit" menu. * NOTE: Save files from tkgate 1.5 may not be readable under earlier versions of tkgate if you use the new delay specification features. Version 1.4c - June 12, 2000 * Fixed Postscript output and bit tap problems (Applied patch tkgate-1.4b.patch1) * Added Postscript output of Japanese (works for printers with Japanese fonts only). * Made ports on modules easier to select. * Fixed problem with changing port type in external port dialog box. Version 1.4b - June 7, 2000 * Fixed the library module problem (applied tkgate-1.4.patch1) * Fixed problems with Japanese input * Created a seperate directory for Japanese tutorials. Selection of the tutorial directory depends on the selected interface language. Currently only a small portion of the tutorial have been translated. Version 1.4 - June 2, 2000 * Added LED devices (single bit, bar graph, 7-segment) * Added context sensitive popup menus (bound to right mouse button) * Added "add wire segment" feature to attach new wire segments in the middle of existing wires. * Bug fix (Simulator crashed when circuit contained anchored modules) * Bug fix (States of switches in modules sometimes not shown properly when there are multiples instances of that module) * Bug fix (Various objects still created with default name even when hitting 'cancel' in dialog box). * Bug fix (Y2K problem in Postscript output) * Bug fix (Connecting wires of different bit widths caused core dump) Verion 1.3b - May 4, 2000 * Fixed minor problem with compiling in some versions of Linux * Improved commenting in the Menagerie CPU example. * Fixed bug in editing comments (comment not saved when closing dialog box by hitting return in hyperlink entry box). Verion 1.3 - April 20, 2000 * Microcode/macrocode compiler (gmac) now generates a human readable symbol map. * Better delay model * Multi-lignual features added (English and Japanese) * Hyperlink comments * Improved tutorial (using hyperlinks) * Added 'zoom' command to simulator script to set zoom factor on scope. Version 1.2b - April 13, 2000 * Fixed problems with SunOS 5.7 Version 1.2 - April 13, 2000 * Hit test for gates now works better for long thin gates such as registers * Problem with deleting ports on primitive gates fixed * Horizontal/Vertical alignment feature added (see "Edit" menu) Version 1.1 - March 31, 2000 * Color interface implemented. * Smooth scrolling in scope implemented. * Fixed bugs under Solaris (SunOS 5.5) * Fixed verious other bugs. Version 1.0 - March 22, 2000 * Fixed bugs. Version 0.9 - May 28, 1999 * Initial public release. tkgate-2.0-b10/acinclude.m4000644 001751 001751 00000030670 11133543366 016212 0ustar00hansenhansen000000 000000 #-------------------------------------------------------------------- # TKG_SET_PREFIX # # Set the default prefix value base on the OS # # Arguments: # None. # # Results: # Sets the variable TKGATE_USESIGSET # #-------------------------------------------------------------------- AC_DEFUN([TKG_SET_PREFIX],[ AC_MSG_CHECKING([installation prefix]) os_name=`uname` case X$os_name in XFreeBSD) AC_PREFIX_DEFAULT(/usr/X11) install_dir=/usr/X11 ;; XLinux) AC_PREFIX_DEFAULT(/usr/local) install_dir=/usr/local ;; *) AC_PREFIX_DEFAULT(/usr/local) install_dir=/usr/local ;; esac AC_MSG_RESULT([$os_name ... $install_dir]) ]) #-------------------------------------------------------------------- # TKG_USE_SIGSET # # Check if we should use sigset() instead of signal() # # Arguments: # None. # # Results: # Sets the variable TKGATE_USESIGSET # #-------------------------------------------------------------------- AC_DEFUN([TKG_USE_SIGSET],[ AC_MSG_CHECKING([how to set signal handlers]) AC_CACHE_VAL(signal_ok, AC_TRY_COMPILE([#include ], [signal(0,0);], [signal_ok=yes], [signal_ok=no])) AC_CACHE_VAL(sigset_ok, AC_TRY_COMPILE([#include ], [sigset(0,0);], [sigset_ok=yes], [sigset_ok=no])) if test "$signal_ok" = "yes"; then AC_DEFINE(TKGATE_SIGSET, 0, [Use sigset instead of signal if set.]) AC_MSG_RESULT([signal()]) else if test "$sigset_ok" = "yes"; then AC_DEFINE(TKGATE_SIGSET, 1, [Use sigset instead of signal if set.]) AC_MSG_RESULT([sigset()]) else AC_MSG_ERROR([I can't figure out how to set signal handlers.]); fi fi ]) #-------------------------------------------------------------------- # TKG_CHECK_GECOS # # Check if struct passwd includes a gecos field. # # Arguments: # None. # # Results: # Sets the variable HAVE_PW_GECOS # #-------------------------------------------------------------------- AC_DEFUN([TKG_CHECK_GECOS],[ AC_CACHE_CHECK([pw_gecos in struct pwd], tcl_cv_pwd_pw_gecos, AC_TRY_COMPILE([#include ], [struct passwd pwd; pwd.pw_gecos;], tcl_cv_pwd_pw_gecos=yes, tcl_cv_pwd_pw_gecos=no)) if test $tcl_cv_pwd_pw_gecos = yes; then AC_DEFINE(HAVE_PW_GECOS, 1, [Does struct password have a pw_gecos field?]) else AC_DEFINE(HAVE_PW_GECOS, 0, [Does struct password have a pw_gecos field?]) fi ]) #-------------------------------------------------------------------- # TKG_CHECK_ICONV_H # # Check to see if we can find iconv.h # # Arguments: # None. # # Results: # HAVE_ICONV_H # ICONV_IPATH # ICONV_LPATH # ICONV_LIB # #-------------------------------------------------------------------- AC_DEFUN([TKG_CHECK_ICONV_H],[ AC_MSG_CHECKING([for iconv.h]) for p in $TKGATE_INCDIRS; do if test -f $p/iconv.h; then iconv_h_dir=$p fi done for p in $TKGATE_LIBDIRS; do if test -f $p/libiconv.a; then iconv_lib_dir=$p fi done if test "X$iconv_h_dir" = "X"; then AC_MSG_RESULT([not found]) else AC_MSG_RESULT([found in $iconv_h_dir]) AC_DEFINE(HAVE_ICONV_H, 1, [Does the iconv.h header exist on this machine?]) ICONV_IPATH="-I$iconv_h_dir" if test "X$iconv_lib_dir" != "X"; then ICONV_LPATH="-L$iconv_lib_dir" ICONV_LIB="-liconv" fi fi ]) #-------------------------------------------------------------------- # TKG_WORDSIZE # # Check the word size on the current machine # # Arguments: # None. # # Results: # Sets the variable TKGATE_WORDSIZE to 32 or 64 # #-------------------------------------------------------------------- AC_DEFUN([TKG_WORDSIZE],[ AC_CACHE_CHECK([word size], wordsize, AC_RUN_IFELSE(AC_LANG_PROGRAM([#include #include ], [return sizeof(unsigned) == 8 ? 0 : 1;]), [wordsize=64], [wordsize=32])) if test $wordsize = 32; then AC_DEFINE(TKGATE_WORDSIZE, 32, [Word size of machine.]) else AC_DEFINE(TKGATE_WORDSIZE, 64, [Word size of machine.]) fi ]) #-------------------------------------------------------------------- # TKG_MERGE # # Arguments: # var Variable to assign merged result to # values List to merge # # Results: # Sets the variable TKGATE_WORDSIZE to 32 or 64 # #-------------------------------------------------------------------- AC_DEFUN([TKG_MERGE],[ L="" for v in $2; do add_ok=1 for q in $L; do if test X$q = X$v; then add_ok=0 break fi done if test "$add_ok" = "1"; then L="$L $v" fi done $1=$L ]) #-------------------------------------------------------------------- # TKG_GETTCLTRYDIRS # # Arguments: # none # # Results: # try_dirs List of directories to look for tclConfig.sh # #-------------------------------------------------------------------- AC_DEFUN([TKG_GETTCLTRYDIRS],[ try_dirs="$TKGATE_LIBDIRS" for v in $TKGATE_TCLTK_VERSIONS; do alt_v=`echo $v | sed s/\\\\.//` for d in $TKGATE_LIBDIRS; do try_dirs="$try_dirs $d/tcl$v $d/tcl$alt_v" done done ]) #-------------------------------------------------------------------- # TKG_GETTKTRYDIRS # # Arguments: # ver Tcl version number being used # # Results: # try_dirs List of directories to look for tkConfig.sh # # We will try to find tkConfig.sh in the tcl directories as well since # some OSes might stuff it there. # #-------------------------------------------------------------------- AC_DEFUN([TKG_GETTKTRYDIRS],[ v=$1 alt_v=`echo $v | sed s/\\\\.//` try_dirs="$TKGATE_LIBDIRS" for d in $TKGATE_LIBDIRS; do try_dirs="$try_dirs $d/tk$v $d/tk$alt_v $d/tcl$v $d/tcl$alt_v" done ]) #-------------------------------------------------------------------- # TKG_FINDTCLTK # # Figure out where Tcl is installed and set paths to it. # # Arguments: # None. # # Results: # TCLTK_VERSION Version of Tcl being used # TCL_LIB Libraries (-l options) needed to link with tcl # TK_LIB Libraries (-l options) needed to link with tk # TCL_IPATH Include paths (-I options) needed to compile with tcl # TK_IPATH Include paths (-I options) needed to compile with tk # TCL_LPATH Library paths (-L options) needed to link with tcl # TK_LPATH Library paths (-L options) needed to link with tk # #-------------------------------------------------------------------- AC_DEFUN([TKG_FINDTCLTK],[ AC_MSG_CHECKING([tcl/tk version]) TKG_GETTCLTRYDIRS for d in $try_dirs; do if test -f $d/tclConfig.sh; then . $d/tclConfig.sh break fi done if test "X$TCL_VERSION" = "X"; then AC_MSG_ERROR([could not find tclConfig.sh]) else TKG_GETTKTRYDIRS($TCL_VERSION) for d in $try_dirs; do if test -f $d/tkConfig.sh; then . $d/tkConfig.sh break fi done if test "X$TK_VERSION" = "X"; then AC_MSG_ERROR([could not find tkConfig.sh]) else if test "X$TCL_VERSION" != "X$TK_VERSION"; then AC_MSG_ERROR([versions of tcl ($TCL_VERSION) and tk ($TK_VERSION) do not match.]) else TCLTK_VERSION=$TCL_VERSION TKG_SETTCLTK fi fi fi AC_MSG_RESULT([$TCLTK_VERSION]) ]) ]) #-------------------------------------------------------------------- # TKG_SETTCLTK # # Arguments: # ver Version number # dir Directory in which to look for package (tcl or tk) # pkg Which package to look for (tcl or tk) # # Results: # #-------------------------------------------------------------------- AC_DEFUN([TKG_FINDTCLTKIPATH],[ v=$1 alt_v=`echo $v | sed s/\\\\.//` ipath="" for d in $TKGATE_INCDIRS; do if test -f $d/$2$v/$3.h; then ipath=-I$d/$2$v else if test -f $d/$2$alt_v/$3.h; then ipath=-I$d/$2$alt_v else if test -f $d/$3.h; then ipath=-I$d fi fi fi done ]) #-------------------------------------------------------------------- # TKG_SETTCLTK # # Set the variables for tcl/tk (helping function for TKG_FINDTCLTK) # # Arguments: # None. # # Results: # TCL_LIB Libraries (-l options) needed to link with tcl # TK_LIB Libraries (-l options) needed to link with tk # TCL_IPATH Include paths (-I options) needed to compile with tcl # TK_IPATH Include paths (-I options) needed to compile with tk # TCL_LPATH Library paths (-L options) needed to link with tcl # TK_LPATH Library paths (-L options) needed to link with tk # #-------------------------------------------------------------------- AC_DEFUN([TKG_SETTCLTK],[ TCL_LIB=$TCL_LIB_SPEC TCL_LPATH="" TCL_IPATH=$TCL_INCLUDE_SPEC TK_LIB=$TK_LIB_SPEC TK_LPATH="" TK_IPATH=$TK_INCLUDE_SPEC if test "X$TCL_IPATH" = "X"; then TKG_FINDTCLTKIPATH($TCLTK_VERSION, 'tcl', 'tcl') TCL_IPATH=$ipath echo TCL_IPATH=$ipath fi if test "X$TK_IPATH" = "X"; then TKG_FINDTCLTKIPATH($TCLTK_VERSION, 'tk', 'tk') if test "X$ipath" = "X"; then TKG_FINDTCLTKIPATH($TCLTK_VERSION, 'tcl', 'tk') fi TK_IPATH=$ipath fi if test "X$TCL_IPATH" = "X-I/usr/include"; then TCL_IPATH="" fi if test "X$TK_IPATH" = "X-I/usr/include"; then TK_IPATH="" fi ]) #-------------------------------------------------------------------- # TKG_FINDTCLTK_OBSOLETE # # Figure out where Tcl is installed and set paths to it. # # Arguments: # None. # # Results: # TCLTK_VERSION Version of Tcl being used # TCL_LIBS Libraries (-l options) needed to link with tcl # TCL_IPATH Include paths (-I options) needed to compile with tcl # TCL_LPATH Library paths (-L options) needed to link with tcl # TK_LIBS Libraries (-l options) needed to link with tk # TK_IPATH Include paths (-I options) needed to compile with tk # TK_LPATH Library paths (-L options) needed to link with tk # #-------------------------------------------------------------------- AC_DEFUN([TKG_FINDTCLTK_OBSOLETE],[ AC_MSG_CHECKING([tcl/tk version]) for v in $TKGATE_TCLTK_VERSIONS; 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AC_INIT([tkgate],[2.0-b10]) AM_INIT_AUTOMAKE AC_PREREQ(2.57) AC_CONFIG_HEADER(config.h) AC_LANG(C) ############################################################################# # # TkGate version and identifying information. # AC_DEFINE(TKGATE_VERSION, "2.0", [Base TkGate version number]) AC_SUBST(TKGATE_VERSION, 2.0) AC_DEFINE(TKGATE_VERSION_SUFFIX,"-b10", [TkGate version suffix]) AC_DEFINE(TKGATE_FULL_VERSION, (TKGATE_VERSION TKGATE_VERSION_SUFFIX), [Full TkGate version number]) AC_DEFINE(TKGATE_DESCRIPTION, "Digital Circuit Editor and Simulator", [Tkgate short description]) AC_DEFINE(TKGATE_LOCALDOC, "file:@H/doc/index.html", [Local documentation location]) AC_DEFINE(TKGATE_COPYRIGHT, "Copyright (C) 1987-2009 by Jeffery P. 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AC_PROG_CXX AC_PROG_CC AC_PROG_YACC AM_PROG_LEX AC_PROG_LN_S AC_PROG_MAKE_SET AC_PROG_RANLIB AC_PROG_CPP AC_PROG_INSTALL AC_PROG_RANLIB AC_PROG_LIBTOOL # Checks for header files. AC_PATH_XTRA AC_FUNC_ALLOCA AC_HEADER_STDC AC_HEADER_SYS_WAIT AC_CHECK_HEADERS([limits.h malloc.h stdlib.h string.h sys/param.h sys/time.h unistd.h]) TKG_CHECK_ICONV_H # Checks for typedefs, structures, and compiler characteristics. AC_C_CONST AC_TYPE_SIZE_T AC_HEADER_TIME AC_STRUCT_TM AC_CHECK_TYPES(unsigned long long) # Checks for library functions. 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ORIGINAL_CONFIG_SHELL=${CONFIG_SHELL-/bin/sh} export ORIGINAL_CONFIG_SHELL CONFIG_SHELL=/bin/ksh export CONFIG_SHELL exec $CONFIG_SHELL "[$]0" --no-reexec ${1+"[$]@"} else # Try using printf. echo='printf %s\n' if test "X`($echo '\t') 2>/dev/null`" = 'X\t' && echo_testing_string=`($echo "$echo_test_string") 2>/dev/null` && test "X$echo_testing_string" = "X$echo_test_string"; then # Cool, printf works : elif echo_testing_string=`($ORIGINAL_CONFIG_SHELL "[$]0" --fallback-echo '\t') 2>/dev/null` && test "X$echo_testing_string" = 'X\t' && echo_testing_string=`($ORIGINAL_CONFIG_SHELL "[$]0" --fallback-echo "$echo_test_string") 2>/dev/null` && test "X$echo_testing_string" = "X$echo_test_string"; then CONFIG_SHELL=$ORIGINAL_CONFIG_SHELL export CONFIG_SHELL SHELL="$CONFIG_SHELL" export SHELL echo="$CONFIG_SHELL [$]0 --fallback-echo" elif echo_testing_string=`($CONFIG_SHELL "[$]0" --fallback-echo '\t') 2>/dev/null` && test "X$echo_testing_string" = 'X\t' && echo_testing_string=`($CONFIG_SHELL "[$]0" --fallback-echo "$echo_test_string") 2>/dev/null` && test "X$echo_testing_string" = "X$echo_test_string"; then echo="$CONFIG_SHELL [$]0 --fallback-echo" else # maybe with a smaller string... prev=: for cmd in 'echo test' 'sed 2q "[$]0"' 'sed 10q "[$]0"' 'sed 20q "[$]0"' 'sed 50q "[$]0"'; do if (test "X$echo_test_string" = "X`eval $cmd`") 2>/dev/null then break fi prev="$cmd" done if test "$prev" != 'sed 50q "[$]0"'; then echo_test_string=`eval $prev` export echo_test_string exec ${ORIGINAL_CONFIG_SHELL-${CONFIG_SHELL-/bin/sh}} "[$]0" ${1+"[$]@"} else # Oops. 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aCC*) _LT_AC_TAGVAR(archive_cmds, $1)='$rm $output_objdir/$soname~$CC -b ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | grep "[[-]]L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; echo $list' ;; *) if test "$GXX" = yes; then _LT_AC_TAGVAR(archive_cmds, $1)='$rm $output_objdir/$soname~$CC -shared -nostdlib -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else # FIXME: insert proper C++ library support _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; hpux10*|hpux11*) if test $with_gnu_ld = no; then _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_AC_TAGVAR(hardcode_libdir_separator, $1)=: case $host_cpu in hppa*64*|ia64*) ;; *) _LT_AC_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' ;; esac fi case $host_cpu in hppa*64*|ia64*) _LT_AC_TAGVAR(hardcode_direct, $1)=no _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) _LT_AC_TAGVAR(hardcode_direct, $1)=yes _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes # Not in the search PATH, # but as the default # location of the library. ;; esac case $cc_basename in CC*) # FIXME: insert proper C++ library support _LT_AC_TAGVAR(ld_shlibs, $1)=no ;; aCC*) case $host_cpu in hppa*64*) _LT_AC_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; ia64*) _LT_AC_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; *) _LT_AC_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; esac # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | grep "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; echo $list' ;; *) if test "$GXX" = yes; then if test $with_gnu_ld = no; then case $host_cpu in hppa*64*) _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib -fPIC ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; 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_LT_AC_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' ;; irix5* | irix6* | nonstopux*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # PIC (with -KPIC) is the default. _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; newsos6) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; linux* | k*bsd*-gnu) case $cc_basename in icc* | ecc*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-static' ;; pgcc* | pgf77* | pgf90* | pgf95*) # Portland Group compilers (*not* the Pentium gcc compiler, # which looks to be a dead project) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-fpic' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; ccc*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # All Alpha code is PIC. _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' ;; *Sun\ F*) # Sun Fortran 8.3 passes all unrecognized flags to the linker _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='' ;; esac ;; esac ;; osf3* | osf4* | osf5*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # All OSF/1 code is PIC. _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; rdos*) _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; solaris*) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' case $cc_basename in f77* | f90* | f95*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ';; *) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,';; esac ;; sunos4*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-PIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; sysv4 | sysv4.2uw2* | sysv4.3*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; sysv4*MP*) if test -d /usr/nec ;then _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-Kconform_pic' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' fi ;; sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; unicos*) _LT_AC_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_AC_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no ;; uts4*) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)='-pic' _LT_AC_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; *) _LT_AC_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no ;; esac fi ]) AC_MSG_RESULT([$_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)]) # # Check to make sure the PIC flag actually works. # if test -n "$_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)"; then AC_LIBTOOL_COMPILER_OPTION([if $compiler PIC flag $_LT_AC_TAGVAR(lt_prog_compiler_pic, $1) works], _LT_AC_TAGVAR(lt_prog_compiler_pic_works, $1), [$_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)ifelse([$1],[],[ -DPIC],[ifelse([$1],[CXX],[ -DPIC],[])])], [], [case $_LT_AC_TAGVAR(lt_prog_compiler_pic, $1) in "" | " "*) ;; *) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)=" $_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)" ;; esac], [_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)= _LT_AC_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no]) fi case $host_os in # For platforms which do not support PIC, -DPIC is meaningless: *djgpp*) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)= ;; *) _LT_AC_TAGVAR(lt_prog_compiler_pic, $1)="$_LT_AC_TAGVAR(lt_prog_compiler_pic, $1)ifelse([$1],[],[ -DPIC],[ifelse([$1],[CXX],[ -DPIC],[])])" ;; esac # # Check to make sure the static flag actually works. # wl=$_LT_AC_TAGVAR(lt_prog_compiler_wl, $1) eval lt_tmp_static_flag=\"$_LT_AC_TAGVAR(lt_prog_compiler_static, $1)\" AC_LIBTOOL_LINKER_OPTION([if $compiler static flag $lt_tmp_static_flag works], _LT_AC_TAGVAR(lt_prog_compiler_static_works, $1), $lt_tmp_static_flag, [], [_LT_AC_TAGVAR(lt_prog_compiler_static, $1)=]) ]) # AC_LIBTOOL_PROG_LD_SHLIBS([TAGNAME]) # ------------------------------------ # See if the linker supports building shared libraries. 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FIXME _LT_AC_TAGVAR(archive_cmds, $1)='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; cygwin* | mingw* | pw32*) # _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1) is actually meaningless, # as there is no search path for DLLs. _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_AC_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_AC_TAGVAR(always_export_symbols, $1)=no _LT_AC_TAGVAR(enable_shared_with_static_runtimes, $1)=yes _LT_AC_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1 DATA/'\'' -e '\''/^[[AITW]][[ ]]/s/.*[[ ]]//'\'' | sort | uniq > $export_symbols' if $LD --help 2>&1 | grep 'auto-import' > /dev/null; then _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' # If the export-symbols file already is a .def file (1st line # is EXPORTS), use it as is; otherwise, prepend... _LT_AC_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then cp $export_symbols $output_objdir/$soname.def; else echo EXPORTS > $output_objdir/$soname.def; cat $export_symbols >> $output_objdir/$soname.def; fi~ $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; interix[[3-9]]*) _LT_AC_TAGVAR(hardcode_direct, $1)=no _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_AC_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. # Instead, shared libraries are loaded at an image base (0x10000000 by # default) and relocated if they conflict, which is a slow very memory # consuming and fragmenting process. To avoid this, we pick a random, # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link # time. Moving up from 0x10000000 also allows more sbrk(2) space. _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' _LT_AC_TAGVAR(archive_expsym_cmds, $1)='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' ;; gnu* | linux* | k*bsd*-gnu) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then tmp_addflag= case $cc_basename,$host_cpu in pgcc*) # Portland Group C compiler _LT_AC_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag' ;; pgf77* | pgf90* | pgf95*) # Portland Group f77 and f90 compilers _LT_AC_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag -Mnomain' ;; ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 tmp_addflag=' -i_dynamic' ;; efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 tmp_addflag=' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=' -nofor_main' ;; esac case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 _LT_AC_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_sharedflag='-G' ;; *Sun\ F*) # Sun Fortran 8.3 tmp_sharedflag='-G' ;; *) tmp_sharedflag='-shared' ;; esac _LT_AC_TAGVAR(archive_cmds, $1)='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' if test $supports_anon_versioning = yes; then _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ $echo "local: *; };" >> $output_objdir/$libname.ver~ $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' fi else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then _LT_AC_TAGVAR(archive_cmds, $1)='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' wlarc= else _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' fi ;; solaris*) if $LD -v 2>&1 | grep 'BFD 2\.8' > /dev/null; then _LT_AC_TAGVAR(ld_shlibs, $1)=no cat <&2 *** Warning: The releases 2.8.* of the GNU linker cannot reliably *** create shared libraries on Solaris systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.9.1 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. EOF elif $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) case `$LD -v 2>&1` in *\ [[01]].* | *\ 2.[[0-9]].* | *\ 2.1[[0-5]].*) _LT_AC_TAGVAR(ld_shlibs, $1)=no cat <<_LT_EOF 1>&2 *** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not *** reliably create shared libraries on SCO systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.16.91.0.3 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF ;; *) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='`test -z "$SCOABSPATH" && echo ${wl}-rpath,$libdir`' _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib' _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname,\${SCOABSPATH:+${install_libdir}/}$soname,-retain-symbols-file,$export_symbols -o $lib' else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; sunos4*) _LT_AC_TAGVAR(archive_cmds, $1)='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' wlarc= _LT_AC_TAGVAR(hardcode_direct, $1)=yes _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then _LT_AC_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else _LT_AC_TAGVAR(ld_shlibs, $1)=no fi ;; esac if test "$_LT_AC_TAGVAR(ld_shlibs, $1)" = no; then runpath_var= _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_AC_TAGVAR(export_dynamic_flag_spec, $1)= _LT_AC_TAGVAR(whole_archive_flag_spec, $1)= fi else # PORTME fill in a description of your system's linker (not GNU ld) case $host_os in aix3*) _LT_AC_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_AC_TAGVAR(always_export_symbols, $1)=yes _LT_AC_TAGVAR(archive_expsym_cmds, $1)='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' # Note: this linker hardcodes the directories in LIBPATH if there # are no directories specified by -L. _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then # Neither direct hardcoding nor static linking is supported with a # broken collect2. _LT_AC_TAGVAR(hardcode_direct, $1)=unsupported fi ;; aix4* | aix5*) if test "$host_cpu" = ia64; then # On IA64, the linker does run time linking by default, so we don't # have to do anything special. aix_use_runtimelinking=no exp_sym_flag='-Bexport' no_entry_flag="" else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm if $NM -V 2>&1 | grep 'GNU' > /dev/null; then _LT_AC_TAGVAR(export_symbols_cmds, $1)='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\[$]2 == "T") || (\[$]2 == "D") || (\[$]2 == "B")) && ([substr](\[$]3,1,1) != ".")) { print \[$]3 } }'\'' | sort -u > $export_symbols' else _LT_AC_TAGVAR(export_symbols_cmds, $1)='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\[$]2 == "T") || (\[$]2 == "D") || (\[$]2 == "B")) && ([substr](\[$]3,1,1) != ".")) { print \[$]3 } }'\'' | sort -u > $export_symbols' fi aix_use_runtimelinking=no # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we # need to do runtime linking. case $host_os in aix4.[[23]]|aix4.[[23]].*|aix5*) for ld_flag in $LDFLAGS; do if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then aix_use_runtimelinking=yes break fi done ;; esac exp_sym_flag='-bexport' no_entry_flag='-bnoentry' fi # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library # or program results in "error TOC overflow" add -mminimal-toc to # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. _LT_AC_TAGVAR(archive_cmds, $1)='' _LT_AC_TAGVAR(hardcode_direct, $1)=yes _LT_AC_TAGVAR(hardcode_libdir_separator, $1)=':' _LT_AC_TAGVAR(link_all_deplibs, $1)=yes if test "$GCC" = yes; then case $host_os in aix4.[[012]]|aix4.[[012]].*) # We only want to do this on AIX 4.2 and lower, the check # below for broken collect2 doesn't work under 4.3+ collect2name=`${CC} -print-prog-name=collect2` if test -f "$collect2name" && \ strings "$collect2name" | grep resolve_lib_name >/dev/null then # We have reworked collect2 : else # We have old collect2 _LT_AC_TAGVAR(hardcode_direct, $1)=unsupported # It fails to find uninstalled libraries when the uninstalled # path is not listed in the libpath. Setting hardcode_minus_L # to unsupported forces relinking _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_AC_TAGVAR(hardcode_libdir_separator, $1)= fi ;; esac shared_flag='-shared' if test "$aix_use_runtimelinking" = yes; then shared_flag="$shared_flag "'${wl}-G' fi else # not using gcc if test "$host_cpu" = ia64; then # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release # chokes on -Wl,-G. The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to export. _LT_AC_TAGVAR(always_export_symbols, $1)=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. _LT_AC_TAGVAR(allow_undefined_flag, $1)='-berok' # Determine the default libpath from the value encoded in an empty executable. _LT_AC_SYS_LIBPATH_AIX _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" _LT_AC_TAGVAR(archive_expsym_cmds, $1)="\$CC"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then echo "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $libdir:/usr/lib:/lib' _LT_AC_TAGVAR(allow_undefined_flag, $1)="-z nodefs" _LT_AC_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an empty executable. _LT_AC_SYS_LIBPATH_AIX _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. _LT_AC_TAGVAR(no_undefined_flag, $1)=' ${wl}-bernotok' _LT_AC_TAGVAR(allow_undefined_flag, $1)=' ${wl}-berok' # Exported symbols can be pulled into shared objects from archives _LT_AC_TAGVAR(whole_archive_flag_spec, $1)='$convenience' _LT_AC_TAGVAR(archive_cmds_need_lc, $1)=yes # This is similar to how AIX traditionally builds its shared libraries. _LT_AC_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; amigaos*) _LT_AC_TAGVAR(archive_cmds, $1)='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes # see comment about different semantics on the GNU ld section _LT_AC_TAGVAR(ld_shlibs, $1)=no ;; bsdi[[45]]*) _LT_AC_TAGVAR(export_dynamic_flag_spec, $1)=-rdynamic ;; cygwin* | mingw* | pw32*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)=' ' _LT_AC_TAGVAR(allow_undefined_flag, $1)=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. _LT_AC_TAGVAR(archive_cmds, $1)='$CC -o $lib $libobjs $compiler_flags `echo "$deplibs" | $SED -e '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. _LT_AC_TAGVAR(old_archive_From_new_cmds, $1)='true' # FIXME: Should let the user specify the lib program. _LT_AC_TAGVAR(old_archive_cmds, $1)='lib -OUT:$oldlib$oldobjs$old_deplibs' _LT_AC_TAGVAR(fix_srcfile_path, $1)='`cygpath -w "$srcfile"`' _LT_AC_TAGVAR(enable_shared_with_static_runtimes, $1)=yes ;; darwin* | rhapsody*) case $host_os in rhapsody* | darwin1.[[012]]) _LT_AC_TAGVAR(allow_undefined_flag, $1)='${wl}-undefined ${wl}suppress' ;; *) # Darwin 1.3 on if test -z ${MACOSX_DEPLOYMENT_TARGET} ; then _LT_AC_TAGVAR(allow_undefined_flag, $1)='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' else case ${MACOSX_DEPLOYMENT_TARGET} in 10.[[012]]) _LT_AC_TAGVAR(allow_undefined_flag, $1)='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) _LT_AC_TAGVAR(allow_undefined_flag, $1)='${wl}-undefined ${wl}dynamic_lookup' ;; esac fi ;; esac _LT_AC_TAGVAR(archive_cmds_need_lc, $1)=no _LT_AC_TAGVAR(hardcode_direct, $1)=no _LT_AC_TAGVAR(hardcode_automatic, $1)=yes _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=unsupported _LT_AC_TAGVAR(whole_archive_flag_spec, $1)='' _LT_AC_TAGVAR(link_all_deplibs, $1)=yes if test "$GCC" = yes ; then output_verbose_link_cmd='echo' _LT_AC_TAGVAR(archive_cmds, $1)='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' _LT_AC_TAGVAR(module_cmds, $1)='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds _LT_AC_TAGVAR(archive_expsym_cmds, $1)='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' _LT_AC_TAGVAR(module_expsym_cmds, $1)='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' else case $cc_basename in xlc*) output_verbose_link_cmd='echo' _LT_AC_TAGVAR(archive_cmds, $1)='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`echo $rpath/$soname` $xlcverstring' _LT_AC_TAGVAR(module_cmds, $1)='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds _LT_AC_TAGVAR(archive_expsym_cmds, $1)='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $xlcverstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' _LT_AC_TAGVAR(module_expsym_cmds, $1)='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' ;; *) _LT_AC_TAGVAR(ld_shlibs, $1)=no ;; esac fi ;; dgux*) _LT_AC_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_AC_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no ;; freebsd1*) _LT_AC_TAGVAR(ld_shlibs, $1)=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. 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Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format. TkGate documentation can be found at: .PP http://www.tkgate.org .SH "OPTIONS" The options are as follows: .TP 15 \-X script Automaticaly start the simulator and execute the specified simulation script. .TP 15 \-p file Print circuit to file without starting GUI. .TP 15 \-P printer Print circuit to printer without starting GUI. .TP 15 \-l file Read the specified file as a library. .TP 15 \-x Automaticaly start the simulator. .TP 15 \-q Suppress startup messages. .TP 15 \-s Excute with a synchronous X server connection. This option is primarily for debugging. .TP 15 \-L lang Specify a locality to use if tkgate has been configued for Japanese support. The locality should be either "ASCII" for English, or "ja_JP.EUC" for Japanese. This option can also be set via the LANG environment variable. .SH "HISTORY & CREDITS" TkGate begin life as an undergraduate project at Carnegie Mellon University (CMU) in 1987. At that time it was called simply 'gate' and ran under the 'wm' window manager, a windowing system developed at CMU before X11 was widely used. In this incarnation it was used by students in the computer architecture course at CMU to develop a simple microprocessor (dubbed "The Bat Computer"). After laying dormant for several years, it was resurrected in 1991 and ported to run under X11 with the Xlib API. In this incarnation it was used several times by students in the introductory digital logic course, but after the author graduated and left CMU, it went into hibernation again. This Tcl/Tk incarnation was begun in 1998. While there is certainly some cruftyness in the implementation in places due to the multiple reincarnations, many new features have been added since the older wm and X11 versions, and the interface has been made much easier to use. .SH "SEE ALSO" gmac(1) .SH "AUTHOR" Jeffery Hansen (hansen@tkgate.org) .SH "COPYRIGHT" Copyright (c) 1987-2007 by Jeffery Hansen tkgate-2.0-b10/verga.1000644 001751 001751 00000005564 11145031036 015200 0ustar00hansenhansen000000 000000 .TH VERGA 1 .SH "NAME" verga \- VERrilog simulator for tkGAte .SH "SYNOPSIS" .B verga [\-eslqi] [\-d dtype] [\-S script] [\-P mods] [\-t mod] [\-B dir] [\-D hash] [\-W wmode] [files...] .SH "DESCRIPTION" \fIVerga \fR is a verilog simulator designed to be used with tkgate, but it can also be used as a stand-alone simulator. Verga documentation can be found at: .PP http://www.tkgate.org .SH "OPTIONS" The options are as follows: .TP 15 \-e Dump the list of error codes and associated messages that can be produced by verga. This option is primarily for developer purposes. .TP 15 \-s Scan a Verilog file and output information about its modules and nets. This option is primarily used internally by tkgate. .TP 15 \-l Show the verga license. .TP 15 \-q Run in 'quiet' mode, suppressing extraneous messages. .TP 15 \-i Run in 'interactive' mode. This mode is intended primarily for use when verga is being invoked by tkgate. .TP 15 \-d dtype Type of delays to use. Can be 'min', 'max' or 'typical'. .TP 15 \-S script Load simulation scripts for each '\-S' switch. .TP 15 \-P mod Print the named module from the parsed structure for each '\-P' specified. .TP 15 \-t mod Override the default and designate 'mod' as the top-level module. .TP 15 \-B dir Directory to use as base directory when loading files .TP 15 \-D hash Delete the input files after loading if 'hash' exactly matches a hash code computed on the file name. This option should only be used by tkgate which writes the file to simulate to a temporary file before invoking the simulator. .TP 15 \-W wmode Mode for warning message handling. Can be 1 for "ignore warnings", 2 for "report warnings only if there were errors", 3 for "always report warnings" or 4 for "always report warnings and stop simulator even if only warnings". .SH "HISTORY & CREDITS" TkGate begin life as an undergraduate project at Carnegie Mellon University (CMU) in 1987. At that time it was called simply 'gate' and ran under the 'wm' window manager, a windowing system developed at CMU before X11 was widely used. In this incarnation it was used by students in the computer architecture course at CMU to develop a simple microprocessor (dubbed "The Bat Computer"). After laying dormant for several years, it was resurrected in 1991 and ported to run under X11 with the Xlib API. In this incarnation it was used several times by students in the introductory digital logic course, but after the author graduated and left CMU, it went into hibernation again. This Tcl/Tk incarnation was begun in 1998. While there is certainly some cruftyness in the implementation in places due to the multiple reincarnations, many new features have been added since the older wm and X11 versions, and the interface has been made much easier to use. .SH "SEE ALSO" gmac(1), tkgate(1) .SH "AUTHOR" Jeffery Hansen (hansen@tkgate.org) .SH "COPYRIGHT" Copyright (c) 1987-2007 by Jeffery Hansen tkgate-2.0-b10/gmac.1000644 001751 001751 00000001000 11145031050 014754 0ustar00hansenhansen000000 000000 .TH GMAC 1 .SH "NAME" gmac \- Microcode and Macrocode Compiler for TkGate .SH "SYNOPSIS" .B gmac [\-o file] [files] .SH "DESCRIPTION" \fIgmac \fR is a microcode and macrocode compiler for tkgate. More complete documentation can be found at: .PP http://www.cs.cmu.edu/~hansen/tkgate .SH "OPTIONS" The options are as follows: .TP 15 \-o file Specifies the output file. .SH "SEE ALSO" tkgate(1), verga(1) .SH "AUTHOR" Jeffery Hansen (hansen@cmu.edu) .SH "COPYRIGHT" Copyright (c) 1999-2004 by Jeffery Hansen tkgate-2.0-b10/README.verga000644 001751 001751 00000003155 10624113233 015770 0ustar00hansenhansen000000 000000 This file contains notes on the internal commands sent between tkgate and the simulator verga. Commands recognized by simulator: $script Read a verilog script file $show Show current value of net $sendto Put value in named channel $cpath Do a critical path analysis $set Set a net to a value $break Create a breakpoint $delete_break Delete a breakpoint $probe [] Monitor a net $unprobe [] Remove a monitor from a net $memload [] Load a memory(s) from a file $memdump Dump a memory to a file. $time Report current time $step [] Step simulator a number of epochs. $addclock Register 'net' as a clock. $stepclock <+/-> [] Step simulator a number of clock cycles. $wait Wait for all events to be executed. $stop Pause simulator. $go Put simulator in continuos mode. $exit Exit the simulator Commands sent from simulator to tkgate: stop @ Indicate simulator is stopped break @ Indicate simulator is stopped at a breakpoint time @ Report of current simulator valueof @ Report value of a net to a tkgate listener comment Comment command. Ignored by tkgate. echo Text to be displayed as is. error file Error message with error gate Error occuring related to a gate/module error net Error occuring related to a net error run Run-time error report error command Error in command from tkgate tkgate-2.0-b10/COPYING000644 001751 001751 00000043063 10016416556 015053 0ustar00hansenhansen000000 000000 GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 675 Mass Ave, Cambridge, MA 02139, USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. 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If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) 19yy This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) 19yy name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Library General Public License instead of this License. tkgate-2.0-b10/INSTALL000644 001751 001751 00000003230 11126512220 015025 0ustar00hansenhansen000000 000000 ***************************************************************************** INSTALLATION To install tkgate follow the steps below: 1) Obtain and install tcl/tk 8.4 or later (preferably tcl/tk 8.5). 2) If you have already installed tkgate 1.* and do not wish to overwrite that installation, see "INSTALLING MULTIPLE VERSIONS" below. 3) cd to the directory in which you unpacked this distribution. 4) Run the configuration script: ./configure 5) Compile TkGate using the command: make 6) Become root so you can install files su 7) Install TkGate using the commands: make install ***************************************************************************** DEFAULT INSTALLATION On older versions of FreeBSD using Xfree86, the default directories into which files are installed are: /usr/X11R6/bin Binaries for tkgate, verga and gmac /usr/X11R6/man/man1 Man pages for tkgate and gmac /usr/X11R6/share/tkgate Data files used by tkgate On newer FreeBSD systems, Linux and other OSes, the default directories into which files are installed are: /usr/local/bin Binaries for tkgate, verga and gmac /usr/local/man/man1 Man pages for tkgate and gmac /usr/local/share/tkgate Data files used by tkgate ***************************************************************************** INSTALLING MULTIPLE VERSIONS To install tkgate-2.0 without affecting other installed versions do: ./configure --program-suffix=20 make pkgdatadir=/usr/local/share/tkgate-2.0 su make pkgdatadir=/usr/local/share/tkgate-2.0 install This will install tkgate with the executable name "tkgate20". tkgate-2.0-b10/TODO000644 001751 001751 00000003160 11125336254 014500 0ustar00hansenhansen000000 000000 ----------------------------------------------------------------------------- Features still needed for 2.0 before beta 3 release: - Print options - Hand tool scrolling - Copyright update ----------------------------------------------------------------------------- Features still needed for 2.0 before final release: - implement the anti-glitch algorithm from 1.8.5 - complete balloon help messages - translate new messages into Japanese (and request translators to update other locales) ----------------------------------------------------------------------------- Features for 2.1: - Debug symbol editor. - PDF output of designs. - EPSF output of scope traces. - Positioning of sig_names on wires: fix the position of names - Verilog "primitive" modules - manual simulation stimuli should be automatically logged in script format, "re-playable": one could start "by hand" and edit the logfile to a simulation script out of it; - Rename udev/TIP to VPD and check coke machine example. ----------------------------------------------------------------------------- Features not yet assigned to a release: - Other types of nets other than wire (e.g, wand, wor, trior, etc.) - TTY input from simulation script - Quick enable/disabled of probes - Zoom out for overview of large circuit - Drag-and-drop ports from port list box. - "Reverse" simulation (simulation checkpoints) - use ob_malloc in verga? - FPGA synthesis (or integration with existing synthesizer) - Export modules to separate files. - Export to synthesizable verilog (make it easy on synthesizers) - Support for defparam and modules using defparam tkgate-2.0-b10/site-preferences000644 001751 001751 00000013772 11150146140 017177 0ustar00hansenhansen000000 000000 # # Use this file to set site-wide defaults for option values. Options in this # file override the built-in option values defined in tkgate, but can be overridden # by values in user preferences files. # Option::version 2.0 ###################################################################### # # General settings # Option::setDefault siteName Earth Option::setDefault userName "" Option::setDefault noviceMode 1 Option::setDefault contVerify 0 Option::setDefault simDebugInterface 0 Option::setDefault doSafeSave 1 Option::setDefault saveWithCells 0 Option::setDefault checkpointEnabled 0 Option::setDefault checkpointFreq 300 Option::setDefault checkVersion 0 ###################################################################### # # Special settings # Option::setDefault enableBeakModes 0 Option::setDefault baderMode 0 Option::setDefault trekMode 0 Option::setDefault batMode 0 Option::setDefault batRate 200 Option::setDefault allowDebug 0 ###################################################################### # # Interface settings # Option::setDefault keyBindings emacs Option::setDefault smoothScroll 1 Option::setDefault regionUpdate 1 Option::setDefault showDialogImage 1 Option::setDefault fontSet normal Option::setDefault blockDropConnect 0 Option::setDefault undoLength 50 Option::setDefault helpBalloons 1 Option::setDefault tearawayMenus 0 ###################################################################### # # Circuit default settings # Option::setDefault extendBars 1 Option::setDefault showSwitchNets 1 ###################################################################### # # Toolbar options # Option::setDefault filetb 1 Option::setDefault edittb 1 Option::setDefault gateoptb 1 Option::setDefault gateprop 1 Option::setDefault undotb 1 Option::setDefault zoomtb 1 Option::setDefault modetb 1 Option::setDefault moduletb 1 Option::setDefault techtb 1 Option::setDefault simctltb 1 Option::setDefault simauxtb 1 Option::setDefault symmodestb 1 Option::setDefault symedittb 1 Option::setDefault zoomtb 1 Option::setDefault symporttb 1 Option::setDefault symshifttb 1 Option::setDefault symoprtb 1 ###################################################################### # # HDL text colors/fontification # Option::setDefault hdlColorize 1 Option::setDefault hdlIndenting 1 Option::setDefault hdlIndentLevel 2 Option::setDefault hdlIndentNoBegin 0 Option::setDefault hdlIndentReturn 1 Option::setDefault hdlDragSel 1 Option::setDefault hdlCommentColor "firebrick" Option::setDefault hdlCommentBold 0 Option::setDefault hdlCommentItalic 1 Option::setDefault hdlStringColor "RosyBrown" Option::setDefault hdlStringBold 0 Option::setDefault hdlStringItalic 0 Option::setDefault hdlReservedColor "magenta4" Option::setDefault hdlReservedBold 1 Option::setDefault hdlReservedItalic 0 Option::setDefault hdlGateWordColor "red" Option::setDefault hdlGateWordBold 1 Option::setDefault hdlGateWordItalic 0 Option::setDefault hdlInstWordColor "black" Option::setDefault hdlInstWordBold 1 Option::setDefault hdlInstWordItalic 0 Option::setDefault hdlTaskWordColor "green4" Option::setDefault hdlTaskWordBold 1 Option::setDefault hdlTaskWordItalic 0 ###################################################################### # # Simulator settings # Option::setDefault simSortTraces 1 Option::setDefault simStepSize 1 Option::setDefault simClockStepSize 1 Option::setDefault simClockOverStep 21 Option::setDefault simInitScript "" Option::setDefault simCustomDelay 0 Option::setDefault simDelayFile "" Option::setDefault valuePopUpDelay 333 Option::setDefault simLogFile "" Option::setDefault warningMode 3 Option::setDefault glitchSuppress 1 ###################################################################### # # Library Options # Option::setDefault simTIMPath "\${TKGATE_HOME}/tims" Option::setDefault simVLibPath "\${TKGATE_HOME}/vlib" Option::setDefault simVLibNames "" ###################################################################### # # Security Options # Option::setDefault securityHandling 1 Option::setDefault securityExec 1 Option::setDefault securityWriteMem 0 Option::setDefault securityOpen 0 Option::setDefault securitySend 0 Option::setDefault securityEnqueue 1 ###################################################################### # # HTML Options # Option::setDefault browserCommand "firefox %s" Option::setDefault emailCommand "thunderbird %s" ###################################################################### # # Critical Path Options # Option::setDefault flashCPath 1 Option::setDefault numCPath 10 ###################################################################### # # Default colors # Option::setDefault backgroundColor "white" Option::setDefault instColor "blue" Option::setDefault moduleColor "magenta4" Option::setDefault modulePortColor "cyan4" Option::setDefault frameColor "black" Option::setDefault commentColor "black" Option::setDefault hyperlinkColor "blue3" Option::setDefault wireColor "green4" Option::setDefault busColor "red" Option::setDefault toolColor "black" Option::setDefault cpathColor "red" Option::setDefault gridColor "black" Option::setDefault oneColor "green4" Option::setDefault zeroColor "magenta" Option::setDefault floatColor "blue" Option::setDefault unknownColor "red" Option::setDefault offLedColor "lavender" Option::setDefault onLedColor "red" Option::setDefault zLedColor "yellow" ###################################################################### # # Print options # Option::setDefault printer default Option::setDefault printDefCmdTmp "lpr" Option::setDefault printCmdTmp "lpr -P\${PRINTER}" Option::setDefault printCommands {} Option::setDefault printPgSize(US) Letter Option::setDefault printPgSize(*) A4 Option::setDefault printPgOrient landscape Option::setDefault printDuplex 0 Option::setDefault printStyle fit Option::setDefault printIndex 0 Option::setDefault printGraph 0 Option::setDefault printMergeSmall 1 tkgate-2.0-b10/license.txt000644 001751 001751 00000001300 10101620635 016155 0ustar00hansenhansen000000 000000 This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. tkgate-2.0-b10/pkg-comment000644 001751 001751 00000000064 07311226664 016161 0ustar00hansenhansen000000 000000 A Tcl/Tk based digital circuit editor and simulator tkgate-2.0-b10/pkg-descr000644 001751 001751 00000002131 07421612327 015611 0ustar00hansenhansen000000 000000 TkGate is a digital circuit editor and simulator with a Tcl/Tk based interface. TkGate includes a large number of built-in devices including basic gates, memories, ttys and modules for hierarchical design. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create tkgate memory files from a high-level description. The simulator supports continous simulation, single step simulation (by clock or epoch) and breakpoints. Save files are in a Verilog-like format. TkGate also includes a number of tutorial and example circuits which can be loaded through the "Help" menu. The examples range from a simple gate-level 3-bit adder to a 16-bit CPU programmed to play the "Animals" game. TkGate has a multi-langauge interface with support for English, Japanese, French and Spanish. For more information on TkGate, see the TkGate web site at: http://www.cs.cmu.edu/~hansen/tkgate Program and FreeBSD port by: Jeffery Hansen http://www.cs.cmu.edu/~hansen tkgate-2.0-b10/options.h000644 001751 001751 00000010330 11150663407 015652 0ustar00hansenhansen000000 000000 /**************************************************************************** Copyright (C) 1987-2005 by Jeffery P. Hansen This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ****************************************************************************/ #ifndef __options_h #define __options_h /****************************************************************************** * * Tcl Library - If TkGate can not find init.tcl, uncomment this line and set * it to the directory that contains the "init.tcl" file for your tcl * installation. * ******************************************************************************/ /* #define TCL_LIBRARY "/usr/lib/tcl8.4" */ /****************************************************************************** * * Tk Library - If TkGate can not find the Tk library, uncomment this line and * set it to the directory that contains the Tk library. This directory should * include files such as "tk.tcl", "button.tcl", etc. * ******************************************************************************/ /* #define TK_LIBRARY "/usr/lib/tk8.4" */ /****************************************************************************** * * Compiler "CFLAG" options. Need to rerun "./configure" to become effective. * ******************************************************************************/ #define TKGATE_CFLAGS -O2 -g /****************************************************************************** * * Set this to '1' if you get an error about Tk_ConfigureWidget * when running tkgate. * ******************************************************************************/ #define TKGATE_BROKENCONFIGWIDGET 0 /****************************************************************************** * * Maximum number of delay parameters for a gate * ******************************************************************************/ #define MAXDELAYS 16 /****************************************************************************** * * Maximum number of parameters (other than delay) for a module * ******************************************************************************/ #define MAXPARMS 16 /****************************************************************************** * * Maximum number of arguments in an error message * ******************************************************************************/ #define MAXARGS 16 /****************************************************************************** * * Bus width symbol adjustment. These values are used to tweek the position * of the bus width "slash" on vertical and horizontal busses due to variations * in X implementations. * ******************************************************************************/ #define TKGATE_BUSW_VERT 0 /* x tweek for vertical busses */ #define TKGATE_BUSW_HORZ 0 /* y tweek for horizontal busses */ /****************************************************************************** * * Wire tweeks. These tweeks are used to adjust the length of wire endpoints * to compensate for variations in X implementations. * ******************************************************************************/ #define TKGATE_WIRETWEEK_RIGHT 1 #define TKGATE_WIRETWEEK_LEFT 0 #define TKGATE_WIRETWEEK_TOP 0 #define TKGATE_WIRETWEEK_BOTTOM 1 /****************************************************************************** * * Default font encoding for display. * ******************************************************************************/ #define TKGATE_DEFAULT_FONT_CODE "iso8859-1" #endif tkgate-2.0-b10/Makefile.am000644 001751 001751 00000005400 11117116602 016035 0ustar00hansenhansen000000 000000 ## Process this file with automake to produce Makefile.in # # Copyright (C) 1987-2007 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # AUTOMAKE_OPTIONS = foreign # # List of directories that contain data files necessary for tkgate to run. # TKG_DATADIRS=scripts bindings doc gdf images locale povray primitives vlib vpd test # # Subdirectories in which more makefiles can be found # SUBDIRS = src # # List of data files in this directory that should be included with a tkgate distribution. # dist_pkgdata_DATA=README README.verga COPYING INSTALL TODO site-preferences license.txt pkg-comment pkg-descr # # List of man pages for tkgate # dist_man_MANS = tkgate.1 verga.1 gmac.1 # # List of header files that should not be automatically installed # noinst_HEADERS=options.h # # Update the release data for this compilation # release: echo 'char *release_date = "'`(LANG=; date "+%b %d %Y")`'";' > $(srcdir)/src/tkgate/release.c dist-hook: @echo Packaging data files... @for d in $(TKG_DATADIRS); do \ cp -pR $(srcdir)/$$d $(distdir); \ done tests: cd test/verga;./runtests.sh # # Make sure the libexec directory has symbolic links to the 'tkgate' and 'verga' executables. # install-exec-hook: @echo Creating symbolic links in libexec... $(mkinstalldirs) $(DESTDIR)$(pkgdatadir)/libexec @for p in tkgate verga; do \ f=`echo "$$p" | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'`; \ rm -f $(DESTDIR)$(pkgdatadir)/libexec/$$p; \ $(LN_S) `(cd $(DESTDIR)$(bindir);pwd)`/$$f $(DESTDIR)$(pkgdatadir)/libexec/$$p; \ done # # Copy all the data files we need # install-data-hook: @echo Installing data files... @for d in $(TKG_DATADIRS); do \ cp -pR $(srcdir)/$$d $(DESTDIR)$(pkgdatadir); \ done uninstall-local: @echo Uninstalling data files... @for d in $(TKG_DATADIRS); do \ chmod -R u+w $(DESTDIR)$(pkgdatadir)/$$d; \ rm -rf $(DESTDIR)$(pkgdatadir)/$$d; \ done @echo Uninstalling libexec links... chmod -R u+w $(DESTDIR)$(pkgdatadir)/libexec rm -f $(DESTDIR)$(pkgdatadir)/libexec/tkgate rm -f $(DESTDIR)$(pkgdatadir)/libexec/verga rmdir $(DESTDIR)$(pkgdatadir)/libexec tkgate-2.0-b10/Makefile.in000644 001751 001751 00000061763 11257530330 016067 0ustar00hansenhansen000000 000000 # Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # # Copyright (C) 1987-2007 by Jeffery P. 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grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_prog_cc_g=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ac_c_werror_flag=$ac_save_c_werror_flag fi { echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 echo "${ECHO_T}$ac_cv_prog_cc_g" >&6; } if test "$ac_test_CFLAGS" = set; then CFLAGS=$ac_save_CFLAGS elif test $ac_cv_prog_cc_g = yes; then if test "$GCC" = yes; then CFLAGS="-g -O2" else CFLAGS="-g" fi else if test "$GCC" = yes; then CFLAGS="-O2" else CFLAGS= fi fi { echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5 echo $ECHO_N "checking for $CC option to accept ISO C89... $ECHO_C" >&6; } if test "${ac_cv_prog_cc_c89+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_cv_prog_cc_c89=no ac_save_CC=$CC cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include #include /* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ struct buf { int x; }; FILE * (*rcsopen) (struct buf *, struct stat *, int); static char *e (p, i) char **p; int i; { return p[i]; } static char *f (char * (*g) (char **, int), char **p, ...) { char *s; va_list v; va_start (v,p); s = g (p, va_arg (v,int)); va_end (v); return s; } /* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has function prototypes and stuff, but not '\xHH' hex character constants. These don't provoke an error unfortunately, instead are silently treated as 'x'. The following induces an error, until -std is added to get proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an array size at least. 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Otherwise we can end up # making bogus files that we don't know about and never remove. For # instance it was reported that on HP-UX the gcc test will end up # making a dummy file named `D' -- because `-MD' means `put the output # in D'. mkdir conftest.dir # Copy depcomp to subdir because otherwise we won't find it if we're # using a relative directory. cp "$am_depcomp" conftest.dir cd conftest.dir # We will build objects and dependencies in a subdirectory because # it helps to detect inapplicable dependency modes. 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It turns out that the SunPro C++ compiler does not properly # handle `-M -o', and we need to detect this. if depmode=$depmode \ source=sub/conftest.c object=sub/conftest.${OBJEXT-o} \ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ $SHELL ./depcomp $depcc -c -o sub/conftest.${OBJEXT-o} sub/conftest.c \ >/dev/null 2>conftest.err && grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && grep sub/conftest.${OBJEXT-o} sub/conftest.Po > /dev/null 2>&1 && ${MAKE-make} -s -f confmf > /dev/null 2>&1; then # icc doesn't choke on unknown options, it will just issue warnings # or remarks (even with -Werror). So we grep stderr for any message # that says an option was ignored or not supported. # When given -MP, icc 7.0 and 7.1 complain thusly: # icc: Command line warning: ignoring option '-M'; no argument required # The diagnosis changed in icc 8.0: # icc: Command line remark: option '-MP' not supported if (grep 'ignoring option' conftest.err || grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else am_cv_CC_dependencies_compiler_type=$depmode break fi fi done cd .. rm -rf conftest.dir else am_cv_CC_dependencies_compiler_type=none fi fi { echo "$as_me:$LINENO: result: $am_cv_CC_dependencies_compiler_type" >&5 echo "${ECHO_T}$am_cv_CC_dependencies_compiler_type" >&6; } CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type if test "x$enable_dependency_tracking" != xno \ && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then am__fastdepCC_TRUE= am__fastdepCC_FALSE='#' else am__fastdepCC_TRUE='#' am__fastdepCC_FALSE= fi for ac_prog in 'bison -y' byacc do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_YACC+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$YACC"; then ac_cv_prog_YACC="$YACC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_YACC="$ac_prog" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi YACC=$ac_cv_prog_YACC if test -n "$YACC"; then { echo "$as_me:$LINENO: result: $YACC" >&5 echo "${ECHO_T}$YACC" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi test -n "$YACC" && break done test -n "$YACC" || YACC="yacc" for ac_prog in flex lex do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_LEX+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$LEX"; then ac_cv_prog_LEX="$LEX" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_LEX="$ac_prog" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi LEX=$ac_cv_prog_LEX if test -n "$LEX"; then { echo "$as_me:$LINENO: result: $LEX" >&5 echo "${ECHO_T}$LEX" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi test -n "$LEX" && break done test -n "$LEX" || LEX=":" if test "x$LEX" != "x:"; then cat >conftest.l <<_ACEOF %% a { ECHO; } b { REJECT; } c { yymore (); } d { yyless (1); } e { yyless (input () != 0); } f { unput (yytext[0]); } . { BEGIN INITIAL; } %% #ifdef YYTEXT_POINTER extern char *yytext; #endif int main (void) { return ! yylex () + ! yywrap (); } _ACEOF { (ac_try="$LEX conftest.l" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$LEX conftest.l") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } { echo "$as_me:$LINENO: checking lex output file root" >&5 echo $ECHO_N "checking lex output file root... $ECHO_C" >&6; } if test "${ac_cv_prog_lex_root+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -f lex.yy.c; then ac_cv_prog_lex_root=lex.yy elif test -f lexyy.c; then ac_cv_prog_lex_root=lexyy else { { echo "$as_me:$LINENO: error: cannot find output from $LEX; giving up" >&5 echo "$as_me: error: cannot find output from $LEX; giving up" >&2;} { (exit 1); exit 1; }; } fi fi { echo "$as_me:$LINENO: result: $ac_cv_prog_lex_root" >&5 echo "${ECHO_T}$ac_cv_prog_lex_root" >&6; } LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root if test -z "${LEXLIB+set}"; then { echo "$as_me:$LINENO: checking lex library" >&5 echo $ECHO_N "checking lex library... $ECHO_C" >&6; } if test "${ac_cv_lib_lex+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_save_LIBS=$LIBS ac_cv_lib_lex='none needed' for ac_lib in '' -lfl -ll; do LIBS="$ac_lib $ac_save_LIBS" cat >conftest.$ac_ext <<_ACEOF `cat $LEX_OUTPUT_ROOT.c` _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_lex=$ac_lib else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext test "$ac_cv_lib_lex" != 'none needed' && break done LIBS=$ac_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_lex" >&5 echo "${ECHO_T}$ac_cv_lib_lex" >&6; } test "$ac_cv_lib_lex" != 'none needed' && LEXLIB=$ac_cv_lib_lex fi { echo "$as_me:$LINENO: checking whether yytext is a pointer" >&5 echo $ECHO_N "checking whether yytext is a pointer... $ECHO_C" >&6; } if test "${ac_cv_prog_lex_yytext_pointer+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # POSIX says lex can declare yytext either as a pointer or an array; the # default is implementation-dependent. Figure out which it is, since # not all implementations provide the %pointer and %array declarations. ac_cv_prog_lex_yytext_pointer=no ac_save_LIBS=$LIBS LIBS="$LEXLIB $ac_save_LIBS" cat >conftest.$ac_ext <<_ACEOF #define YYTEXT_POINTER 1 `cat $LEX_OUTPUT_ROOT.c` _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_prog_lex_yytext_pointer=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_prog_lex_yytext_pointer" >&5 echo "${ECHO_T}$ac_cv_prog_lex_yytext_pointer" >&6; } if test $ac_cv_prog_lex_yytext_pointer = yes; then cat >>confdefs.h <<\_ACEOF #define YYTEXT_POINTER 1 _ACEOF fi rm -f conftest.l $LEX_OUTPUT_ROOT.c fi if test "$LEX" = :; then LEX=${am_missing_run}flex fi { echo "$as_me:$LINENO: checking whether ln -s works" >&5 echo $ECHO_N "checking whether ln -s works... $ECHO_C" >&6; } LN_S=$as_ln_s if test "$LN_S" = "ln -s"; then { echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6; } else { echo "$as_me:$LINENO: result: no, using $LN_S" >&5 echo "${ECHO_T}no, using $LN_S" >&6; } fi { echo "$as_me:$LINENO: checking whether ${MAKE-make} sets \$(MAKE)" >&5 echo $ECHO_N "checking whether ${MAKE-make} sets \$(MAKE)... $ECHO_C" >&6; } set x ${MAKE-make}; ac_make=`echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` if { as_var=ac_cv_prog_make_${ac_make}_set; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.make <<\_ACEOF SHELL = /bin/sh all: @echo '@@@%%%=$(MAKE)=@@@%%%' _ACEOF # GNU make sometimes prints "make[1]: Entering...", which would confuse us. case `${MAKE-make} -f conftest.make 2>/dev/null` in *@@@%%%=?*=@@@%%%*) eval ac_cv_prog_make_${ac_make}_set=yes;; *) eval ac_cv_prog_make_${ac_make}_set=no;; esac rm -f conftest.make fi if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then { echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6; } SET_MAKE= else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } SET_MAKE="MAKE=${MAKE-make}" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$RANLIB"; then ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi RANLIB=$ac_cv_prog_RANLIB if test -n "$RANLIB"; then { echo "$as_me:$LINENO: result: $RANLIB" >&5 echo "${ECHO_T}$RANLIB" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_RANLIB"; then ac_ct_RANLIB=$RANLIB # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_RANLIB"; then ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; 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} if test "${lt_cv_path_SED+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Loop through the user's path and test for sed and gsed. # Then use that list of sed's as ones to test for truncation. as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for lt_ac_prog in sed gsed; do for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$lt_ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$lt_ac_prog$ac_exec_ext"; }; then lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext" fi done done done IFS=$as_save_IFS lt_ac_max=0 lt_ac_count=0 # Add /usr/xpg4/bin/sed as it is typically found on Solaris # along with /bin/sed that truncates output. for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do test ! -f $lt_ac_sed && continue cat /dev/null > conftest.in lt_ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >conftest.in # Check for GNU sed and select it if it is found. if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then lt_cv_path_SED=$lt_ac_sed break fi while true; do cat conftest.in conftest.in >conftest.tmp mv conftest.tmp conftest.in cp conftest.in conftest.nl echo >>conftest.nl $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break cmp -s conftest.out conftest.nl || break # 10000 chars as input seems more than enough test $lt_ac_count -gt 10 && break lt_ac_count=`expr $lt_ac_count + 1` if test $lt_ac_count -gt $lt_ac_max; then lt_ac_max=$lt_ac_count lt_cv_path_SED=$lt_ac_sed fi done done fi SED=$lt_cv_path_SED { echo "$as_me:$LINENO: result: $SED" >&5 echo "${ECHO_T}$SED" >&6; } { echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 echo $ECHO_N "checking for grep that handles long lines and -e... $ECHO_C" >&6; } if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Extract the first word of "grep ggrep" to use in msg output if test -z "$GREP"; then set dummy grep ggrep; ac_prog_name=$2 if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS fi GREP="$ac_cv_path_GREP" if test -z "$GREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_GREP=$GREP fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 echo "${ECHO_T}$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { echo "$as_me:$LINENO: checking for egrep" >&5 echo $ECHO_N "checking for egrep... $ECHO_C" >&6; } if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else # Extract the first word of "egrep" to use in msg output if test -z "$EGREP"; then set dummy egrep; ac_prog_name=$2 if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS fi EGREP="$ac_cv_path_EGREP" if test -z "$EGREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_EGREP=$EGREP fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 echo "${ECHO_T}$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" # Check whether --with-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes else with_gnu_ld=no fi ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. { echo "$as_me:$LINENO: checking for ld used by $CC" >&5 echo $ECHO_N "checking for ld used by $CC... $ECHO_C" >&6; } case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; *) ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; esac case $ac_prog in # Accept absolute paths. [\\/]* | ?:[\\/]*) re_direlt='/[^/][^/]*/\.\./' # Canonicalize the pathname of ld ac_prog=`echo $ac_prog| $SED 's%\\\\%/%g'` while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do ac_prog=`echo $ac_prog| $SED "s%$re_direlt%/%"` done test -z "$LD" && LD="$ac_prog" ;; "") # If it fails, then pretend we aren't using GCC. ac_prog=ld ;; *) # If it is relative, then search for the first ld in PATH. with_gnu_ld=unknown ;; esac elif test "$with_gnu_ld" = yes; then { echo "$as_me:$LINENO: checking for GNU ld" >&5 echo $ECHO_N "checking for GNU ld... $ECHO_C" >&6; } else { echo "$as_me:$LINENO: checking for non-GNU ld" >&5 echo $ECHO_N "checking for non-GNU ld... $ECHO_C" >&6; } fi if test "${lt_cv_path_LD+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -z "$LD"; then lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then lt_cv_path_LD="$ac_dir/$ac_prog" # Check to see if the program is GNU ld. I'd rather use --version, # but apparently some variants of GNU ld only accept -v. # Break only if it was the GNU/non-GNU ld that we prefer. case `"$lt_cv_path_LD" -v 2>&1 &5 echo "${ECHO_T}$LD" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi test -z "$LD" && { { echo "$as_me:$LINENO: error: no acceptable ld found in \$PATH" >&5 echo "$as_me: error: no acceptable ld found in \$PATH" >&2;} { (exit 1); exit 1; }; } { echo "$as_me:$LINENO: checking if the linker ($LD) is GNU ld" >&5 echo $ECHO_N "checking if the linker ($LD) is GNU ld... $ECHO_C" >&6; } if test "${lt_cv_prog_gnu_ld+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # I'd rather use --version here, but apparently some GNU lds only accept -v. case `$LD -v 2>&1 &5 echo "${ECHO_T}$lt_cv_prog_gnu_ld" >&6; } with_gnu_ld=$lt_cv_prog_gnu_ld { echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5 echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6; } if test "${lt_cv_ld_reload_flag+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else lt_cv_ld_reload_flag='-r' fi { echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5 echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6; } reload_flag=$lt_cv_ld_reload_flag case $reload_flag in "" | " "*) ;; *) reload_flag=" $reload_flag" ;; esac reload_cmds='$LD$reload_flag -o $output$reload_objs' case $host_os in darwin*) if test "$GCC" = yes; then reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs' else reload_cmds='$LD$reload_flag -o $output$reload_objs' fi ;; esac { echo "$as_me:$LINENO: checking for BSD-compatible nm" >&5 echo $ECHO_N "checking for BSD-compatible nm... $ECHO_C" >&6; } if test "${lt_cv_path_NM+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$NM"; then # Let the user override the test. lt_cv_path_NM="$NM" else lt_nm_to_check="${ac_tool_prefix}nm" if test -n "$ac_tool_prefix" && test "$build" = "$host"; then lt_nm_to_check="$lt_nm_to_check nm" fi for lt_tmp_nm in $lt_nm_to_check; do lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. tmp_nm="$ac_dir/$lt_tmp_nm" if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then # Check to see if the nm accepts a BSD-compat flag. # Adding the `sed 1q' prevents false positives on HP-UX, which says: # nm: unknown option "B" ignored # Tru64's nm complains that /dev/null is an invalid object file case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in */dev/null* | *'Invalid file or object type'*) lt_cv_path_NM="$tmp_nm -B" break ;; *) case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in */dev/null*) lt_cv_path_NM="$tmp_nm -p" break ;; *) lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but continue # so that we can try to find one that supports BSD flags ;; esac ;; esac fi done IFS="$lt_save_ifs" done test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm fi fi { echo "$as_me:$LINENO: result: $lt_cv_path_NM" >&5 echo "${ECHO_T}$lt_cv_path_NM" >&6; } NM="$lt_cv_path_NM" { echo "$as_me:$LINENO: checking how to recognize dependent libraries" >&5 echo $ECHO_N "checking how to recognize dependent libraries... $ECHO_C" >&6; } if test "${lt_cv_deplibs_check_method+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else lt_cv_file_magic_cmd='$MAGIC_CMD' lt_cv_file_magic_test_file= lt_cv_deplibs_check_method='unknown' # Need to set the preceding variable on all platforms that support # interlibrary dependencies. # 'none' -- dependencies not supported. # `unknown' -- same as none, but documents that we really don't know. # 'pass_all' -- all dependencies passed with no checks. # 'test_compile' -- check by making test program. # 'file_magic [[regex]]' -- check by looking for files in library path # which responds to the $file_magic_cmd with a given extended regex. # If you have `file' or equivalent on your system and you're not sure # whether `pass_all' will *always* work, you probably want this one. case $host_os in aix4* | aix5*) lt_cv_deplibs_check_method=pass_all ;; beos*) lt_cv_deplibs_check_method=pass_all ;; bsdi[45]*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' lt_cv_file_magic_cmd='/usr/bin/file -L' lt_cv_file_magic_test_file=/shlib/libc.so ;; cygwin*) # func_win32_libid is a shell function defined in ltmain.sh lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' lt_cv_file_magic_cmd='func_win32_libid' ;; mingw* | pw32*) # Base MSYS/MinGW do not provide the 'file' command needed by # func_win32_libid shell function, so use a weaker test based on 'objdump', # unless we find 'file', for example because we are cross-compiling. if ( file / ) >/dev/null 2>&1; then lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' lt_cv_file_magic_cmd='func_win32_libid' else lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?' lt_cv_file_magic_cmd='$OBJDUMP -f' fi ;; darwin* | rhapsody*) lt_cv_deplibs_check_method=pass_all ;; freebsd* | dragonfly*) if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then case $host_cpu in i*86 ) # Not sure whether the presence of OpenBSD here was a mistake. # Let's accept both of them until this is cleared up. lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` ;; esac else lt_cv_deplibs_check_method=pass_all fi ;; gnu*) lt_cv_deplibs_check_method=pass_all ;; hpux10.20* | hpux11*) lt_cv_file_magic_cmd=/usr/bin/file case $host_cpu in ia64*) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so ;; hppa*64*) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - PA-RISC [0-9].[0-9]' lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl ;; *) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library' lt_cv_file_magic_test_file=/usr/lib/libc.sl ;; esac ;; interix[3-9]*) # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$' ;; irix5* | irix6* | nonstopux*) case $LD in *-32|*"-32 ") libmagic=32-bit;; *-n32|*"-n32 ") libmagic=N32;; *-64|*"-64 ") libmagic=64-bit;; *) libmagic=never-match;; esac lt_cv_deplibs_check_method=pass_all ;; # This must be Linux ELF. linux* | k*bsd*-gnu) lt_cv_deplibs_check_method=pass_all ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$' fi ;; newos6*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/libnls.so ;; nto-qnx*) lt_cv_deplibs_check_method=unknown ;; openbsd*) if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' fi ;; osf3* | osf4* | osf5*) lt_cv_deplibs_check_method=pass_all ;; rdos*) lt_cv_deplibs_check_method=pass_all ;; solaris*) lt_cv_deplibs_check_method=pass_all ;; sysv4 | sysv4.3*) case $host_vendor in motorola) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` ;; ncr) lt_cv_deplibs_check_method=pass_all ;; sequent) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;; sni) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib" lt_cv_file_magic_test_file=/lib/libc.so ;; siemens) lt_cv_deplibs_check_method=pass_all ;; pc) lt_cv_deplibs_check_method=pass_all ;; esac ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) lt_cv_deplibs_check_method=pass_all ;; esac fi { echo "$as_me:$LINENO: result: $lt_cv_deplibs_check_method" >&5 echo "${ECHO_T}$lt_cv_deplibs_check_method" >&6; } file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method test -z "$deplibs_check_method" && deplibs_check_method=unknown # If no C compiler was specified, use CC. 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What could be older than Ultrix?!! ;)] # Character class describing NM global symbol codes. symcode='[BCDEGRST]' # Regexp to match symbols that can be accessed directly from C. sympat='\([_A-Za-z][_A-Za-z0-9]*\)' # Transform an extracted symbol line into a proper C declaration lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^. .* \(.*\)$/extern int \1;/p'" # Transform an extracted symbol line into symbol name and symbol address lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (lt_ptr) 0},/p' -e 's/^$symcode \([^ ]*\) \([^ ]*\)$/ {\"\2\", (lt_ptr) \&\2},/p'" # Define system-specific variables. case $host_os in aix*) symcode='[BCDT]' ;; cygwin* | mingw* | pw32*) symcode='[ABCDGISTW]' ;; hpux*) # Its linker distinguishes data from code symbols if test "$host_cpu" = ia64; then symcode='[ABCDEGRST]' fi lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (lt_ptr) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (lt_ptr) \&\2},/p'" ;; linux* | k*bsd*-gnu) if test "$host_cpu" = ia64; then symcode='[ABCDGIRSTW]' lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (lt_ptr) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (lt_ptr) \&\2},/p'" fi ;; irix* | nonstopux*) symcode='[BCDEGRST]' ;; osf*) symcode='[BCDEGQRST]' ;; solaris*) symcode='[BDRT]' ;; sco3.2v5*) symcode='[DT]' ;; sysv4.2uw2*) symcode='[DT]' ;; sysv5* | sco5v6* | unixware* | OpenUNIX*) symcode='[ABDT]' ;; sysv4) symcode='[DFNSTU]' ;; esac # Handle CRLF in mingw tool chain opt_cr= case $build_os in mingw*) opt_cr=`echo 'x\{0,1\}' | tr x '\015'` # option cr in regexp ;; esac # If we're using GNU nm, then use its standard symbol codes. case `$NM -V 2>&1` in *GNU* | *'with BFD'*) symcode='[ABCDGIRSTW]' ;; esac # Try without a prefix undercore, then with it. for ac_symprfx in "" "_"; do # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. symxfrm="\\1 $ac_symprfx\\2 \\2" # Write the raw and C identifiers. lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[ ]\($symcode$symcode*\)[ ][ ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" # Check to see that the pipe works correctly. pipe_works=no rm -f conftest* cat > conftest.$ac_ext <&5 (eval $ac_compile) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; then # Now try to grab the symbols. nlist=conftest.nm if { (eval echo "$as_me:$LINENO: \"$NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist\"") >&5 (eval $NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && test -s "$nlist"; then # Try sorting and uniquifying the output. if sort "$nlist" | uniq > "$nlist"T; then mv -f "$nlist"T "$nlist" else rm -f "$nlist"T fi # Make sure that we snagged all the symbols we need. if grep ' nm_test_var$' "$nlist" >/dev/null; then if grep ' nm_test_func$' "$nlist" >/dev/null; then cat < conftest.$ac_ext #ifdef __cplusplus extern "C" { #endif EOF # Now generate the symbol file. eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | grep -v main >> conftest.$ac_ext' cat <> conftest.$ac_ext #if defined (__STDC__) && __STDC__ # define lt_ptr_t void * #else # define lt_ptr_t char * # define const #endif /* The mapping between symbol names and symbols. */ const struct { const char *name; lt_ptr_t address; } lt_preloaded_symbols[] = { EOF $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (lt_ptr_t) \&\2},/" < "$nlist" | grep -v main >> conftest.$ac_ext cat <<\EOF >> conftest.$ac_ext {0, (lt_ptr_t) 0} }; #ifdef __cplusplus } #endif EOF # Now try linking the two files. mv conftest.$ac_objext conftstm.$ac_objext lt_save_LIBS="$LIBS" lt_save_CFLAGS="$CFLAGS" LIBS="conftstm.$ac_objext" CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag" if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 (eval $ac_link) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && test -s conftest${ac_exeext}; then pipe_works=yes fi LIBS="$lt_save_LIBS" CFLAGS="$lt_save_CFLAGS" else echo "cannot find nm_test_func in $nlist" >&5 fi else echo "cannot find nm_test_var in $nlist" >&5 fi else echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5 fi else echo "$progname: failed program was:" >&5 cat conftest.$ac_ext >&5 fi rm -f conftest* conftst* # Do not use the global_symbol_pipe unless it works. if test "$pipe_works" = yes; then break else lt_cv_sys_global_symbol_pipe= fi done fi if test -z "$lt_cv_sys_global_symbol_pipe"; then lt_cv_sys_global_symbol_to_cdecl= fi if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then { echo "$as_me:$LINENO: result: failed" >&5 echo "${ECHO_T}failed" >&6; } else { echo "$as_me:$LINENO: result: ok" >&5 echo "${ECHO_T}ok" >&6; } fi { echo "$as_me:$LINENO: checking for objdir" >&5 echo $ECHO_N "checking for objdir... $ECHO_C" >&6; } if test "${lt_cv_objdir+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else rm -f .libs 2>/dev/null mkdir .libs 2>/dev/null if test -d .libs; then lt_cv_objdir=.libs else # MS-DOS does not allow filenames that begin with a dot. lt_cv_objdir=_libs fi rmdir .libs 2>/dev/null fi { echo "$as_me:$LINENO: result: $lt_cv_objdir" >&5 echo "${ECHO_T}$lt_cv_objdir" >&6; } objdir=$lt_cv_objdir case $host_os in aix3*) # AIX sometimes has problems with the GCC collect2 program. For some # reason, if we set the COLLECT_NAMES environment variable, the problems # vanish in a puff of smoke. if test "X${COLLECT_NAMES+set}" != Xset; then COLLECT_NAMES= export COLLECT_NAMES fi ;; esac # Sed substitution that helps us do robust quoting. It backslashifies # metacharacters that are still active within double-quoted strings. Xsed='sed -e 1s/^X//' sed_quote_subst='s/\([\\"\\`$\\\\]\)/\\\1/g' # Same as above, but do not quote variable references. double_quote_subst='s/\([\\"\\`\\\\]\)/\\\1/g' # Sed substitution to delay expansion of an escaped shell variable in a # double_quote_subst'ed string. delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' # Sed substitution to avoid accidental globbing in evaled expressions no_glob_subst='s/\*/\\\*/g' # Constants: rm="rm -f" # Global variables: default_ofile=libtool can_build_shared=yes # All known linkers require a `.a' archive for static linking (except MSVC, # which needs '.lib'). libext=a ltmain="$ac_aux_dir/ltmain.sh" ofile="$default_ofile" with_gnu_ld="$lt_cv_prog_gnu_ld" if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$AR"; then ac_cv_prog_AR="$AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_AR="${ac_tool_prefix}ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi AR=$ac_cv_prog_AR if test -n "$AR"; then { echo "$as_me:$LINENO: result: $AR" >&5 echo "${ECHO_T}$AR" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_AR"; then ac_ct_AR=$AR # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_AR"; then ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_AR="ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_AR=$ac_cv_prog_ac_ct_AR if test -n "$ac_ct_AR"; then { echo "$as_me:$LINENO: result: $ac_ct_AR" >&5 echo "${ECHO_T}$ac_ct_AR" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi if test "x$ac_ct_AR" = x; then AR="false" else case $cross_compiling:$ac_tool_warned in yes:) { echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&5 echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&2;} ac_tool_warned=yes ;; esac AR=$ac_ct_AR fi else AR="$ac_cv_prog_AR" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$RANLIB"; then ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi RANLIB=$ac_cv_prog_RANLIB if test -n "$RANLIB"; then { echo "$as_me:$LINENO: result: $RANLIB" >&5 echo "${ECHO_T}$RANLIB" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_RANLIB"; then ac_ct_RANLIB=$RANLIB # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_RANLIB"; then ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_RANLIB="ranlib" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB if test -n "$ac_ct_RANLIB"; then { echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 echo "${ECHO_T}$ac_ct_RANLIB" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi if test "x$ac_ct_RANLIB" = x; then RANLIB=":" else case $cross_compiling:$ac_tool_warned in yes:) { echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&5 echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&2;} ac_tool_warned=yes ;; esac RANLIB=$ac_ct_RANLIB fi else RANLIB="$ac_cv_prog_RANLIB" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_STRIP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$STRIP"; then ac_cv_prog_STRIP="$STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_STRIP="${ac_tool_prefix}strip" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi STRIP=$ac_cv_prog_STRIP if test -n "$STRIP"; then { echo "$as_me:$LINENO: result: $STRIP" >&5 echo "${ECHO_T}$STRIP" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_STRIP"; then ac_ct_STRIP=$STRIP # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_STRIP"; then ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_STRIP="strip" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP if test -n "$ac_ct_STRIP"; then { echo "$as_me:$LINENO: result: $ac_ct_STRIP" >&5 echo "${ECHO_T}$ac_ct_STRIP" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi if test "x$ac_ct_STRIP" = x; then STRIP=":" else case $cross_compiling:$ac_tool_warned in yes:) { echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&5 echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. 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amigaos*) archive_cmds='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' hardcode_libdir_flag_spec='-L$libdir' hardcode_minus_L=yes # see comment about different semantics on the GNU ld section ld_shlibs=no ;; bsdi[45]*) export_dynamic_flag_spec=-rdynamic ;; cygwin* | mingw* | pw32*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. hardcode_libdir_flag_spec=' ' allow_undefined_flag=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. archive_cmds='$CC -o $lib $libobjs $compiler_flags `echo "$deplibs" | $SED -e '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. old_archive_From_new_cmds='true' # FIXME: Should let the user specify the lib program. old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs' fix_srcfile_path='`cygpath -w "$srcfile"`' enable_shared_with_static_runtimes=yes ;; darwin* | rhapsody*) case $host_os in rhapsody* | darwin1.[012]) allow_undefined_flag='${wl}-undefined ${wl}suppress' ;; *) # Darwin 1.3 on if test -z ${MACOSX_DEPLOYMENT_TARGET} ; then allow_undefined_flag='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' else case ${MACOSX_DEPLOYMENT_TARGET} in 10.[012]) allow_undefined_flag='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) allow_undefined_flag='${wl}-undefined ${wl}dynamic_lookup' ;; esac fi ;; esac archive_cmds_need_lc=no hardcode_direct=no hardcode_automatic=yes hardcode_shlibpath_var=unsupported whole_archive_flag_spec='' link_all_deplibs=yes if test "$GCC" = yes ; then output_verbose_link_cmd='echo' archive_cmds='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' else case $cc_basename in xlc*) output_verbose_link_cmd='echo' archive_cmds='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`echo $rpath/$soname` $xlcverstring' module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $xlcverstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' ;; *) ld_shlibs=no ;; esac fi ;; dgux*) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec='-L$libdir' hardcode_shlibpath_var=no ;; freebsd1*) ld_shlibs=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. Future versions do this automatically, but an explicit c++rt0.o # does not break anything, and helps significantly (at the cost of a little # extra space). freebsd2.2*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; # Unfortunately, older versions of FreeBSD 2 do not have this feature. freebsd2*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes hardcode_minus_L=yes hardcode_shlibpath_var=no ;; # FreeBSD 3 and greater uses gcc -shared to do shared libraries. freebsd* | dragonfly*) archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; hpux9*) if test "$GCC" = yes; then archive_cmds='$rm $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else archive_cmds='$rm $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' fi hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_separator=: hardcode_direct=yes # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes export_dynamic_flag_spec='${wl}-E' ;; hpux10*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_separator=: hardcode_direct=yes export_dynamic_flag_spec='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes fi ;; hpux11*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then case $host_cpu in hppa*64*) archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac else case $host_cpu in hppa*64*) archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_separator=: case $host_cpu in hppa*64*|ia64*) hardcode_libdir_flag_spec_ld='+b $libdir' hardcode_direct=no hardcode_shlibpath_var=no ;; *) hardcode_direct=yes export_dynamic_flag_spec='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes ;; esac fi ;; irix5* | irix6* | nonstopux*) if test "$GCC" = yes; then archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else archive_cmds='$LD -shared $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec_ld='-rpath $libdir' fi hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: link_all_deplibs=yes ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out else archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF fi hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; newsos6) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: hardcode_shlibpath_var=no ;; openbsd*) if test -f /usr/libexec/ld.so; then hardcode_direct=yes hardcode_shlibpath_var=no if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' hardcode_libdir_flag_spec='${wl}-rpath,$libdir' export_dynamic_flag_spec='${wl}-E' else case $host_os in openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec='-R$libdir' ;; *) archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec='${wl}-rpath,$libdir' ;; esac fi else ld_shlibs=no fi ;; os2*) hardcode_libdir_flag_spec='-L$libdir' hardcode_minus_L=yes allow_undefined_flag=unsupported archive_cmds='$echo "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$echo "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$echo DATA >> $output_objdir/$libname.def~$echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~$echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' old_archive_From_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' ;; osf3*) if test "$GCC" = yes; then allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else allow_undefined_flag=' -expect_unresolved \*' archive_cmds='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' fi hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: ;; osf4* | osf5*) # as osf3* with the addition of -msym flag if test "$GCC" = yes; then allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' else allow_undefined_flag=' -expect_unresolved \*' archive_cmds='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -msym -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; echo "-hidden">> $lib.exp~ $LD -shared${allow_undefined_flag} -input $lib.exp $linker_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib~$rm $lib.exp' # Both c and cxx compiler support -rpath directly hardcode_libdir_flag_spec='-rpath $libdir' fi hardcode_libdir_separator=: ;; solaris*) no_undefined_flag=' -z text' if test "$GCC" = yes; then wlarc='${wl}' archive_cmds='$CC -shared ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $CC -shared ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$rm $lib.exp' else wlarc='' archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' archive_expsym_cmds='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$rm $lib.exp' fi hardcode_libdir_flag_spec='-R$libdir' hardcode_shlibpath_var=no case $host_os in solaris2.[0-5] | solaris2.[0-5].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. GCC discards it without `$wl', # but is careful enough not to reorder. # Supported since Solaris 2.6 (maybe 2.5.1?) if test "$GCC" = yes; then whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' else whole_archive_flag_spec='-z allextract$convenience -z defaultextract' fi ;; esac link_all_deplibs=yes ;; sunos4*) if test "x$host_vendor" = xsequent; then # Use $CC to link under sequent, because it throws in some extra .o # files that make .init and .fini sections work. archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' fi hardcode_libdir_flag_spec='-L$libdir' hardcode_direct=yes hardcode_minus_L=yes hardcode_shlibpath_var=no ;; sysv4) case $host_vendor in sni) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes # is this really true??? ;; siemens) ## LD is ld it makes a PLAMLIB ## CC just makes a GrossModule. archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags' reload_cmds='$CC -r -o $output$reload_objs' hardcode_direct=no ;; motorola) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=no #Motorola manual says yes, but my tests say they lie ;; esac runpath_var='LD_RUN_PATH' hardcode_shlibpath_var=no ;; sysv4.3*) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var=no export_dynamic_flag_spec='-Bexport' ;; sysv4*MP*) if test -d /usr/nec; then archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var=no runpath_var=LD_RUN_PATH hardcode_runpath_var=yes ld_shlibs=yes fi ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) no_undefined_flag='${wl}-z,text' archive_cmds_need_lc=no hardcode_shlibpath_var=no runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. 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sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) version_type=freebsd-elf need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH hardcode_into_libs=yes if test "$with_gnu_ld" = yes; then sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' shlibpath_overrides_runpath=no else sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' shlibpath_overrides_runpath=yes case $host_os in sco3.2v5*) sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" ;; esac fi sys_lib_dlsearch_path_spec='/usr/lib' ;; uts4*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH ;; *) dynamic_linker=no ;; esac { echo "$as_me:$LINENO: result: $dynamic_linker" >&5 echo "${ECHO_T}$dynamic_linker" >&6; } test "$dynamic_linker" = no && can_build_shared=no variables_saved_for_relink="PATH $shlibpath_var $runpath_var" if test "$GCC" = yes; then variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" fi { echo "$as_me:$LINENO: checking how to hardcode library paths into programs" >&5 echo $ECHO_N "checking how to hardcode library paths into programs... $ECHO_C" >&6; } hardcode_action= if test -n "$hardcode_libdir_flag_spec" || \ test -n "$runpath_var" || \ test "X$hardcode_automatic" = "Xyes" ; then # We can hardcode non-existant directories. if test "$hardcode_direct" != no && # If the only mechanism to avoid hardcoding is shlibpath_var, we # have to relink, otherwise we might link with an installed library # when we should be linking with a yet-to-be-installed one ## test "$_LT_AC_TAGVAR(hardcode_shlibpath_var, )" != no && test "$hardcode_minus_L" != no; then # Linking always hardcodes the temporary library directory. hardcode_action=relink else # We can link without hardcoding, and we can hardcode nonexisting dirs. hardcode_action=immediate fi else # We cannot hardcode anything, or else we can only hardcode existing # directories. hardcode_action=unsupported fi { echo "$as_me:$LINENO: result: $hardcode_action" >&5 echo "${ECHO_T}$hardcode_action" >&6; } if test "$hardcode_action" = relink; then # Fast installation is not supported enable_fast_install=no elif test "$shlibpath_overrides_runpath" = yes || test "$enable_shared" = no; then # Fast installation is not necessary enable_fast_install=needless fi striplib= old_striplib= { echo "$as_me:$LINENO: checking whether stripping libraries is possible" >&5 echo $ECHO_N "checking whether stripping libraries is possible... $ECHO_C" >&6; } if test -n "$STRIP" && $STRIP -V 2>&1 | grep "GNU strip" >/dev/null; then test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" test -z "$striplib" && striplib="$STRIP --strip-unneeded" { echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6; } else # FIXME - insert some real tests, host_os isn't really good enough case $host_os in darwin*) if test -n "$STRIP" ; then striplib="$STRIP -x" old_striplib="$STRIP -S" { echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi ;; *) { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } ;; esac fi if test "x$enable_dlopen" != xyes; then enable_dlopen=unknown enable_dlopen_self=unknown enable_dlopen_self_static=unknown else lt_cv_dlopen=no lt_cv_dlopen_libs= case $host_os in beos*) lt_cv_dlopen="load_add_on" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes ;; mingw* | pw32*) lt_cv_dlopen="LoadLibrary" lt_cv_dlopen_libs= ;; cygwin*) lt_cv_dlopen="dlopen" lt_cv_dlopen_libs= ;; darwin*) # if libdl is installed we need to link against it { echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5 echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6; } if test "${ac_cv_lib_dl_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_dl_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_dl_dlopen=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5 echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6; } if test $ac_cv_lib_dl_dlopen = yes; then lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" else lt_cv_dlopen="dyld" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes fi ;; *) { echo "$as_me:$LINENO: checking for shl_load" >&5 echo $ECHO_N "checking for shl_load... $ECHO_C" >&6; } if test "${ac_cv_func_shl_load+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define shl_load to an innocuous variant, in case declares shl_load. For example, HP-UX 11i declares gettimeofday. */ #define shl_load innocuous_shl_load /* System header to define __stub macros and hopefully few prototypes, which can conflict with char shl_load (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef shl_load /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shl_load (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_shl_load || defined __stub___shl_load choke me #endif int main () { return shl_load (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_shl_load=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_shl_load=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_shl_load" >&5 echo "${ECHO_T}$ac_cv_func_shl_load" >&6; } if test $ac_cv_func_shl_load = yes; then lt_cv_dlopen="shl_load" else { echo "$as_me:$LINENO: checking for shl_load in -ldld" >&5 echo $ECHO_N "checking for shl_load in -ldld... $ECHO_C" >&6; } if test "${ac_cv_lib_dld_shl_load+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldld $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shl_load (); int main () { return shl_load (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_dld_shl_load=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_dld_shl_load=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_dld_shl_load" >&5 echo "${ECHO_T}$ac_cv_lib_dld_shl_load" >&6; } if test $ac_cv_lib_dld_shl_load = yes; then lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-dld" else { echo "$as_me:$LINENO: checking for dlopen" >&5 echo $ECHO_N "checking for dlopen... $ECHO_C" >&6; } if test "${ac_cv_func_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define dlopen to an innocuous variant, in case declares dlopen. For example, HP-UX 11i declares gettimeofday. */ #define dlopen innocuous_dlopen /* System header to define __stub macros and hopefully few prototypes, which can conflict with char dlopen (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef dlopen /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_dlopen || defined __stub___dlopen choke me #endif int main () { return dlopen (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_dlopen=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_dlopen" >&5 echo "${ECHO_T}$ac_cv_func_dlopen" >&6; } if test $ac_cv_func_dlopen = yes; then lt_cv_dlopen="dlopen" else { echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5 echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6; } if test "${ac_cv_lib_dl_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_dl_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_dl_dlopen=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5 echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6; } if test $ac_cv_lib_dl_dlopen = yes; then lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" else { echo "$as_me:$LINENO: checking for dlopen in -lsvld" >&5 echo $ECHO_N "checking for dlopen in -lsvld... $ECHO_C" >&6; } if test "${ac_cv_lib_svld_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsvld $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_svld_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_svld_dlopen=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_svld_dlopen" >&5 echo "${ECHO_T}$ac_cv_lib_svld_dlopen" >&6; } if test $ac_cv_lib_svld_dlopen = yes; then lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" else { echo "$as_me:$LINENO: checking for dld_link in -ldld" >&5 echo $ECHO_N "checking for dld_link in -ldld... $ECHO_C" >&6; } if test "${ac_cv_lib_dld_dld_link+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldld $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. 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The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to export. always_export_symbols_F77=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. allow_undefined_flag_F77='-berok' # Determine the default libpath from the value encoded in an empty executable. cat >conftest.$ac_ext <<_ACEOF program main end _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_f77_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/ p } }' aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$aix_libpath"; then aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi hardcode_libdir_flag_spec_F77='${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds_F77="\$CC"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then echo "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then hardcode_libdir_flag_spec_F77='${wl}-R $libdir:/usr/lib:/lib' allow_undefined_flag_F77="-z nodefs" archive_expsym_cmds_F77="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an empty executable. cat >conftest.$ac_ext <<_ACEOF program main end _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_f77_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/ p } }' aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$aix_libpath"; then aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi hardcode_libdir_flag_spec_F77='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. no_undefined_flag_F77=' ${wl}-bernotok' allow_undefined_flag_F77=' ${wl}-berok' # Exported symbols can be pulled into shared objects from archives whole_archive_flag_spec_F77='$convenience' archive_cmds_need_lc_F77=yes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds_F77="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; amigaos*) archive_cmds_F77='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' hardcode_libdir_flag_spec_F77='-L$libdir' hardcode_minus_L_F77=yes # see comment about different semantics on the GNU ld section ld_shlibs_F77=no ;; bsdi[45]*) export_dynamic_flag_spec_F77=-rdynamic ;; cygwin* | mingw* | pw32*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. hardcode_libdir_flag_spec_F77=' ' allow_undefined_flag_F77=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. archive_cmds_F77='$CC -o $lib $libobjs $compiler_flags `echo "$deplibs" | $SED -e '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. old_archive_From_new_cmds_F77='true' # FIXME: Should let the user specify the lib program. old_archive_cmds_F77='lib -OUT:$oldlib$oldobjs$old_deplibs' fix_srcfile_path_F77='`cygpath -w "$srcfile"`' enable_shared_with_static_runtimes_F77=yes ;; darwin* | rhapsody*) case $host_os in rhapsody* | darwin1.[012]) allow_undefined_flag_F77='${wl}-undefined ${wl}suppress' ;; *) # Darwin 1.3 on if test -z ${MACOSX_DEPLOYMENT_TARGET} ; then allow_undefined_flag_F77='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' else case ${MACOSX_DEPLOYMENT_TARGET} in 10.[012]) allow_undefined_flag_F77='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) allow_undefined_flag_F77='${wl}-undefined ${wl}dynamic_lookup' ;; esac fi ;; esac archive_cmds_need_lc_F77=no hardcode_direct_F77=no hardcode_automatic_F77=yes hardcode_shlibpath_var_F77=unsupported whole_archive_flag_spec_F77='' link_all_deplibs_F77=yes if test "$GCC" = yes ; then output_verbose_link_cmd='echo' archive_cmds_F77='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' module_cmds_F77='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds_F77='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds_F77='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' else case $cc_basename in xlc*) output_verbose_link_cmd='echo' archive_cmds_F77='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`echo $rpath/$soname` $xlcverstring' module_cmds_F77='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds_F77='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $xlcverstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds_F77='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' ;; *) ld_shlibs_F77=no ;; esac fi ;; dgux*) archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec_F77='-L$libdir' hardcode_shlibpath_var_F77=no ;; freebsd1*) ld_shlibs_F77=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. Future versions do this automatically, but an explicit c++rt0.o # does not break anything, and helps significantly (at the cost of a little # extra space). freebsd2.2*) archive_cmds_F77='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' hardcode_libdir_flag_spec_F77='-R$libdir' hardcode_direct_F77=yes hardcode_shlibpath_var_F77=no ;; # Unfortunately, older versions of FreeBSD 2 do not have this feature. freebsd2*) archive_cmds_F77='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_F77=yes hardcode_minus_L_F77=yes hardcode_shlibpath_var_F77=no ;; # FreeBSD 3 and greater uses gcc -shared to do shared libraries. freebsd* | dragonfly*) archive_cmds_F77='$CC -shared -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec_F77='-R$libdir' hardcode_direct_F77=yes hardcode_shlibpath_var_F77=no ;; hpux9*) if test "$GCC" = yes; then archive_cmds_F77='$rm $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else archive_cmds_F77='$rm $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' fi hardcode_libdir_flag_spec_F77='${wl}+b ${wl}$libdir' hardcode_libdir_separator_F77=: hardcode_direct_F77=yes # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_F77=yes export_dynamic_flag_spec_F77='${wl}-E' ;; hpux10*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then archive_cmds_F77='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_F77='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec_F77='${wl}+b ${wl}$libdir' hardcode_libdir_separator_F77=: hardcode_direct_F77=yes export_dynamic_flag_spec_F77='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_F77=yes fi ;; hpux11*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then case $host_cpu in hppa*64*) archive_cmds_F77='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds_F77='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds_F77='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac else case $host_cpu in hppa*64*) archive_cmds_F77='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds_F77='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds_F77='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec_F77='${wl}+b ${wl}$libdir' hardcode_libdir_separator_F77=: case $host_cpu in hppa*64*|ia64*) hardcode_libdir_flag_spec_ld_F77='+b $libdir' hardcode_direct_F77=no hardcode_shlibpath_var_F77=no ;; *) hardcode_direct_F77=yes export_dynamic_flag_spec_F77='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_F77=yes ;; esac fi ;; irix5* | irix6* | nonstopux*) if test "$GCC" = yes; then archive_cmds_F77='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else archive_cmds_F77='$LD -shared $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec_ld_F77='-rpath $libdir' fi hardcode_libdir_flag_spec_F77='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_F77=: link_all_deplibs_F77=yes ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then archive_cmds_F77='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out else archive_cmds_F77='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF fi hardcode_libdir_flag_spec_F77='-R$libdir' hardcode_direct_F77=yes hardcode_shlibpath_var_F77=no ;; newsos6) archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_F77=yes hardcode_libdir_flag_spec_F77='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_F77=: hardcode_shlibpath_var_F77=no ;; openbsd*) if test -f /usr/libexec/ld.so; then hardcode_direct_F77=yes hardcode_shlibpath_var_F77=no if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then archive_cmds_F77='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_F77='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' hardcode_libdir_flag_spec_F77='${wl}-rpath,$libdir' export_dynamic_flag_spec_F77='${wl}-E' else case $host_os in openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) archive_cmds_F77='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec_F77='-R$libdir' ;; *) archive_cmds_F77='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec_F77='${wl}-rpath,$libdir' ;; esac fi else ld_shlibs_F77=no fi ;; os2*) hardcode_libdir_flag_spec_F77='-L$libdir' hardcode_minus_L_F77=yes allow_undefined_flag_F77=unsupported archive_cmds_F77='$echo "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$echo "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$echo DATA >> $output_objdir/$libname.def~$echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~$echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' old_archive_From_new_cmds_F77='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' ;; osf3*) if test "$GCC" = yes; then allow_undefined_flag_F77=' ${wl}-expect_unresolved ${wl}\*' archive_cmds_F77='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else allow_undefined_flag_F77=' -expect_unresolved \*' archive_cmds_F77='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' fi hardcode_libdir_flag_spec_F77='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_F77=: ;; osf4* | osf5*) # as osf3* with the addition of -msym flag if test "$GCC" = yes; then allow_undefined_flag_F77=' ${wl}-expect_unresolved ${wl}\*' archive_cmds_F77='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec_F77='${wl}-rpath ${wl}$libdir' else allow_undefined_flag_F77=' -expect_unresolved \*' archive_cmds_F77='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -msym -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' archive_expsym_cmds_F77='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; echo "-hidden">> $lib.exp~ $LD -shared${allow_undefined_flag} -input $lib.exp $linker_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib~$rm $lib.exp' # Both c and cxx compiler support -rpath directly hardcode_libdir_flag_spec_F77='-rpath $libdir' fi hardcode_libdir_separator_F77=: ;; solaris*) no_undefined_flag_F77=' -z text' if test "$GCC" = yes; then wlarc='${wl}' archive_cmds_F77='$CC -shared ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_F77='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $CC -shared ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$rm $lib.exp' else wlarc='' archive_cmds_F77='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' archive_expsym_cmds_F77='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$rm $lib.exp' fi hardcode_libdir_flag_spec_F77='-R$libdir' hardcode_shlibpath_var_F77=no case $host_os in solaris2.[0-5] | solaris2.[0-5].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. GCC discards it without `$wl', # but is careful enough not to reorder. # Supported since Solaris 2.6 (maybe 2.5.1?) if test "$GCC" = yes; then whole_archive_flag_spec_F77='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' else whole_archive_flag_spec_F77='-z allextract$convenience -z defaultextract' fi ;; esac link_all_deplibs_F77=yes ;; sunos4*) if test "x$host_vendor" = xsequent; then # Use $CC to link under sequent, because it throws in some extra .o # files that make .init and .fini sections work. archive_cmds_F77='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_F77='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' fi hardcode_libdir_flag_spec_F77='-L$libdir' hardcode_direct_F77=yes hardcode_minus_L_F77=yes hardcode_shlibpath_var_F77=no ;; sysv4) case $host_vendor in sni) archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_F77=yes # is this really true??? ;; siemens) ## LD is ld it makes a PLAMLIB ## CC just makes a GrossModule. archive_cmds_F77='$LD -G -o $lib $libobjs $deplibs $linker_flags' reload_cmds_F77='$CC -r -o $output$reload_objs' hardcode_direct_F77=no ;; motorola) archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_F77=no #Motorola manual says yes, but my tests say they lie ;; esac runpath_var='LD_RUN_PATH' hardcode_shlibpath_var_F77=no ;; sysv4.3*) archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var_F77=no export_dynamic_flag_spec_F77='-Bexport' ;; sysv4*MP*) if test -d /usr/nec; then archive_cmds_F77='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var_F77=no runpath_var=LD_RUN_PATH hardcode_runpath_var=yes ld_shlibs_F77=yes fi ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) no_undefined_flag_F77='${wl}-z,text' archive_cmds_need_lc_F77=no hardcode_shlibpath_var_F77=no runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds_F77='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_F77='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_F77='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_F77='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. 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When/if they implement a new # versioning mechanism, adjust this. if test -x /usr/bin/objformat; then objformat=`/usr/bin/objformat` else case $host_os in freebsd[123]*) objformat=aout ;; *) objformat=elf ;; esac fi version_type=freebsd-$objformat case $version_type in freebsd-elf*) library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' need_version=no need_lib_prefix=no ;; freebsd-*) library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' need_version=yes ;; esac shlibpath_var=LD_LIBRARY_PATH case $host_os in freebsd2*) shlibpath_overrides_runpath=yes ;; freebsd3.[01]* | freebsdelf3.[01]*) shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; *) # from 4.6 on, and DragonFly shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; esac ;; gnu*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH hardcode_into_libs=yes ;; hpux9* | hpux10* | hpux11*) # Give a soname corresponding to the major version so that dld.sl refuses to # link against other versions. version_type=sunos need_lib_prefix=no need_version=no case $host_cpu in ia64*) shrext_cmds='.so' hardcode_into_libs=yes dynamic_linker="$host_os dld.so" shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' if test "X$HPUX_IA64_MODE" = X32; then sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" else sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" fi sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; hppa*64*) shrext_cmds='.sl' hardcode_into_libs=yes dynamic_linker="$host_os dld.sl" shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; *) shrext_cmds='.sl' dynamic_linker="$host_os dld.sl" shlibpath_var=SHLIB_PATH shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' ;; esac # HP-UX runs *really* slowly unless shared libraries are mode 555. postinstall_cmds='chmod 555 $lib' ;; interix[3-9]*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; irix5* | irix6* | nonstopux*) case $host_os in nonstopux*) version_type=nonstopux ;; *) if test "$lt_cv_prog_gnu_ld" = yes; then version_type=linux else version_type=irix fi ;; esac need_lib_prefix=no need_version=no soname_spec='${libname}${release}${shared_ext}$major' library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' case $host_os in irix5* | nonstopux*) libsuff= shlibsuff= ;; *) case $LD in # libtool.m4 will add one of these switches to LD *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") libsuff= shlibsuff= libmagic=32-bit;; *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") libsuff=32 shlibsuff=N32 libmagic=N32;; *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") libsuff=64 shlibsuff=64 libmagic=64-bit;; *) libsuff= shlibsuff= libmagic=never-match;; esac ;; esac shlibpath_var=LD_LIBRARY${shlibsuff}_PATH shlibpath_overrides_runpath=no sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" hardcode_into_libs=yes ;; # No shared lib support for Linux oldld, aout, or coff. linux*oldld* | linux*aout* | linux*coff*) dynamic_linker=no ;; # This must be Linux ELF. linux* | k*bsd*-gnu) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no # This implies no fast_install, which is unacceptable. # Some rework will be needed to allow for fast_install # before this can be enabled. hardcode_into_libs=yes # Append ld.so.conf contents to the search path if test -f /etc/ld.so.conf; then lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;/^$/d' | tr '\n' ' '` sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" fi # We used to test for /lib/ld.so.1 and disable shared libraries on # powerpc, because MkLinux only supported shared libraries with the # GNU dynamic linker. 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cat conftest.err >&5 echo "$as_me:16981: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. $echo "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then lt_cv_prog_compiler_rtti_exceptions=yes fi fi $rm conftest* fi { echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_rtti_exceptions" >&5 echo "${ECHO_T}$lt_cv_prog_compiler_rtti_exceptions" >&6; } if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then lt_prog_compiler_no_builtin_flag_GCJ="$lt_prog_compiler_no_builtin_flag_GCJ -fno-rtti -fno-exceptions" else : fi fi lt_prog_compiler_wl_GCJ= lt_prog_compiler_pic_GCJ= lt_prog_compiler_static_GCJ= { echo "$as_me:$LINENO: checking for $compiler option to produce PIC" >&5 echo $ECHO_N "checking for $compiler option to produce PIC... $ECHO_C" >&6; } if test "$GCC" = yes; then lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_static_GCJ='-static' case $host_os in aix*) # All AIX code is PIC. if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor lt_prog_compiler_static_GCJ='-Bstatic' fi ;; amigaos*) # FIXME: we need at least 68020 code to build shared libraries, but # adding the `-m68020' flag to GCC prevents building anything better, # like `-m68040'. lt_prog_compiler_pic_GCJ='-m68020 -resident32 -malways-restore-a4' ;; beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) # PIC is the default for these OSes. ;; mingw* | cygwin* | pw32* | os2*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). # Although the cygwin gcc ignores -fPIC, still need this for old-style # (--disable-auto-import) libraries lt_prog_compiler_pic_GCJ='-DDLL_EXPORT' ;; darwin* | rhapsody*) # PIC is the default on this platform # Common symbols not allowed in MH_DYLIB files lt_prog_compiler_pic_GCJ='-fno-common' ;; interix[3-9]*) # Interix 3.x gcc -fpic/-fPIC options generate broken code. # Instead, we relocate shared libraries at runtime. ;; msdosdjgpp*) # Just because we use GCC doesn't mean we suddenly get shared libraries # on systems that don't support them. lt_prog_compiler_can_build_shared_GCJ=no enable_shared=no ;; sysv4*MP*) if test -d /usr/nec; then lt_prog_compiler_pic_GCJ=-Kconform_pic fi ;; hpux*) # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in hppa*64*|ia64*) # +Z the default ;; *) lt_prog_compiler_pic_GCJ='-fPIC' ;; esac ;; *) lt_prog_compiler_pic_GCJ='-fPIC' ;; esac else # PORTME Check for flag to pass linker flags through the system compiler. case $host_os in aix*) lt_prog_compiler_wl_GCJ='-Wl,' if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor lt_prog_compiler_static_GCJ='-Bstatic' else lt_prog_compiler_static_GCJ='-bnso -bI:/lib/syscalls.exp' fi ;; darwin*) # PIC is the default on this platform # Common symbols not allowed in MH_DYLIB files case $cc_basename in xlc*) lt_prog_compiler_pic_GCJ='-qnocommon' lt_prog_compiler_wl_GCJ='-Wl,' ;; esac ;; mingw* | cygwin* | pw32* | os2*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). lt_prog_compiler_pic_GCJ='-DDLL_EXPORT' ;; hpux9* | hpux10* | hpux11*) lt_prog_compiler_wl_GCJ='-Wl,' # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in hppa*64*|ia64*) # +Z the default ;; *) lt_prog_compiler_pic_GCJ='+Z' ;; esac # Is there a better lt_prog_compiler_static that works with the bundled CC? lt_prog_compiler_static_GCJ='${wl}-a ${wl}archive' ;; irix5* | irix6* | nonstopux*) lt_prog_compiler_wl_GCJ='-Wl,' # PIC (with -KPIC) is the default. lt_prog_compiler_static_GCJ='-non_shared' ;; newsos6) lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' ;; linux* | k*bsd*-gnu) case $cc_basename in icc* | ecc*) lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-static' ;; pgcc* | pgf77* | pgf90* | pgf95*) # Portland Group compilers (*not* the Pentium gcc compiler, # which looks to be a dead project) lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_pic_GCJ='-fpic' lt_prog_compiler_static_GCJ='-Bstatic' ;; ccc*) lt_prog_compiler_wl_GCJ='-Wl,' # All Alpha code is PIC. lt_prog_compiler_static_GCJ='-non_shared' ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' lt_prog_compiler_wl_GCJ='-Wl,' ;; *Sun\ F*) # Sun Fortran 8.3 passes all unrecognized flags to the linker lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' lt_prog_compiler_wl_GCJ='' ;; esac ;; esac ;; osf3* | osf4* | osf5*) lt_prog_compiler_wl_GCJ='-Wl,' # All OSF/1 code is PIC. lt_prog_compiler_static_GCJ='-non_shared' ;; rdos*) lt_prog_compiler_static_GCJ='-non_shared' ;; solaris*) lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' case $cc_basename in f77* | f90* | f95*) lt_prog_compiler_wl_GCJ='-Qoption ld ';; *) lt_prog_compiler_wl_GCJ='-Wl,';; esac ;; sunos4*) lt_prog_compiler_wl_GCJ='-Qoption ld ' lt_prog_compiler_pic_GCJ='-PIC' lt_prog_compiler_static_GCJ='-Bstatic' ;; sysv4 | sysv4.2uw2* | sysv4.3*) lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' ;; sysv4*MP*) if test -d /usr/nec ;then lt_prog_compiler_pic_GCJ='-Kconform_pic' lt_prog_compiler_static_GCJ='-Bstatic' fi ;; sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_pic_GCJ='-KPIC' lt_prog_compiler_static_GCJ='-Bstatic' ;; unicos*) lt_prog_compiler_wl_GCJ='-Wl,' lt_prog_compiler_can_build_shared_GCJ=no ;; uts4*) lt_prog_compiler_pic_GCJ='-pic' lt_prog_compiler_static_GCJ='-Bstatic' ;; *) lt_prog_compiler_can_build_shared_GCJ=no ;; esac fi { echo "$as_me:$LINENO: result: $lt_prog_compiler_pic_GCJ" >&5 echo "${ECHO_T}$lt_prog_compiler_pic_GCJ" >&6; } # # Check to make sure the PIC flag actually works. # if test -n "$lt_prog_compiler_pic_GCJ"; then { echo "$as_me:$LINENO: checking if $compiler PIC flag $lt_prog_compiler_pic_GCJ works" >&5 echo $ECHO_N "checking if $compiler PIC flag $lt_prog_compiler_pic_GCJ works... $ECHO_C" >&6; } if test "${lt_prog_compiler_pic_works_GCJ+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else lt_prog_compiler_pic_works_GCJ=no ac_outfile=conftest.$ac_objext echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="$lt_prog_compiler_pic_GCJ" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. # The option is referenced via a variable to avoid confusing sed. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:17267: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 echo "$as_me:17271: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. $echo "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then lt_prog_compiler_pic_works_GCJ=yes fi fi $rm conftest* fi { echo "$as_me:$LINENO: result: $lt_prog_compiler_pic_works_GCJ" >&5 echo "${ECHO_T}$lt_prog_compiler_pic_works_GCJ" >&6; } if test x"$lt_prog_compiler_pic_works_GCJ" = xyes; then case $lt_prog_compiler_pic_GCJ in "" | " "*) ;; *) lt_prog_compiler_pic_GCJ=" $lt_prog_compiler_pic_GCJ" ;; esac else lt_prog_compiler_pic_GCJ= lt_prog_compiler_can_build_shared_GCJ=no fi fi case $host_os in # For platforms which do not support PIC, -DPIC is meaningless: *djgpp*) lt_prog_compiler_pic_GCJ= ;; *) lt_prog_compiler_pic_GCJ="$lt_prog_compiler_pic_GCJ" ;; esac # # Check to make sure the static flag actually works. # wl=$lt_prog_compiler_wl_GCJ eval lt_tmp_static_flag=\"$lt_prog_compiler_static_GCJ\" { echo "$as_me:$LINENO: checking if $compiler static flag $lt_tmp_static_flag works" >&5 echo $ECHO_N "checking if $compiler static flag $lt_tmp_static_flag works... $ECHO_C" >&6; } if test "${lt_prog_compiler_static_works_GCJ+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else lt_prog_compiler_static_works_GCJ=no save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS $lt_tmp_static_flag" echo "$lt_simple_link_test_code" > conftest.$ac_ext if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then # The linker can only warn and ignore the option if not recognized # So say no if there are warnings if test -s conftest.err; then # Append any errors to the config.log. cat conftest.err 1>&5 $echo "X$_lt_linker_boilerplate" | $Xsed -e '/^$/d' > conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if diff conftest.exp conftest.er2 >/dev/null; then lt_prog_compiler_static_works_GCJ=yes fi else lt_prog_compiler_static_works_GCJ=yes fi fi $rm conftest* LDFLAGS="$save_LDFLAGS" fi { echo "$as_me:$LINENO: result: $lt_prog_compiler_static_works_GCJ" >&5 echo "${ECHO_T}$lt_prog_compiler_static_works_GCJ" >&6; } if test x"$lt_prog_compiler_static_works_GCJ" = xyes; then : else lt_prog_compiler_static_GCJ= fi { echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5 echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6; } if test "${lt_cv_prog_compiler_c_o_GCJ+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else lt_cv_prog_compiler_c_o_GCJ=no $rm -r conftest 2>/dev/null mkdir conftest cd conftest mkdir out echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="-o out/conftest2.$ac_objext" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:17371: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? 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FIXME archive_cmds_GCJ='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' else ld_shlibs_GCJ=no fi ;; cygwin* | mingw* | pw32*) # _LT_AC_TAGVAR(hardcode_libdir_flag_spec, GCJ) is actually meaningless, # as there is no search path for DLLs. hardcode_libdir_flag_spec_GCJ='-L$libdir' allow_undefined_flag_GCJ=unsupported always_export_symbols_GCJ=no enable_shared_with_static_runtimes_GCJ=yes export_symbols_cmds_GCJ='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols' if $LD --help 2>&1 | grep 'auto-import' > /dev/null; then archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' # If the export-symbols file already is a .def file (1st line # is EXPORTS), use it as is; otherwise, prepend... archive_expsym_cmds_GCJ='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then cp $export_symbols $output_objdir/$soname.def; else echo EXPORTS > $output_objdir/$soname.def; cat $export_symbols >> $output_objdir/$soname.def; fi~ $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' else ld_shlibs_GCJ=no fi ;; interix[3-9]*) hardcode_direct_GCJ=no hardcode_shlibpath_var_GCJ=no hardcode_libdir_flag_spec_GCJ='${wl}-rpath,$libdir' export_dynamic_flag_spec_GCJ='${wl}-E' # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. # Instead, shared libraries are loaded at an image base (0x10000000 by # default) and relocated if they conflict, which is a slow very memory # consuming and fragmenting process. To avoid this, we pick a random, # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link # time. Moving up from 0x10000000 also allows more sbrk(2) space. archive_cmds_GCJ='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' archive_expsym_cmds_GCJ='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' ;; gnu* | linux* | k*bsd*-gnu) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then tmp_addflag= case $cc_basename,$host_cpu in pgcc*) # Portland Group C compiler whole_archive_flag_spec_GCJ='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag' ;; pgf77* | pgf90* | pgf95*) # Portland Group f77 and f90 compilers whole_archive_flag_spec_GCJ='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag -Mnomain' ;; ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 tmp_addflag=' -i_dynamic' ;; efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 tmp_addflag=' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=' -nofor_main' ;; esac case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 whole_archive_flag_spec_GCJ='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; $echo \"$new_convenience\"` ${wl}--no-whole-archive' tmp_sharedflag='-G' ;; *Sun\ F*) # Sun Fortran 8.3 tmp_sharedflag='-G' ;; *) tmp_sharedflag='-shared' ;; esac archive_cmds_GCJ='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' if test $supports_anon_versioning = yes; then archive_expsym_cmds_GCJ='$echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ $echo "local: *; };" >> $output_objdir/$libname.ver~ $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' fi else ld_shlibs_GCJ=no fi ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then archive_cmds_GCJ='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' wlarc= else archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' fi ;; solaris*) if $LD -v 2>&1 | grep 'BFD 2\.8' > /dev/null; then ld_shlibs_GCJ=no cat <&2 *** Warning: The releases 2.8.* of the GNU linker cannot reliably *** create shared libraries on Solaris systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.9.1 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. EOF elif $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else ld_shlibs_GCJ=no fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) case `$LD -v 2>&1` in *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*) ld_shlibs_GCJ=no cat <<_LT_EOF 1>&2 *** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not *** reliably create shared libraries on SCO systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.16.91.0.3 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF ;; *) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then hardcode_libdir_flag_spec_GCJ='`test -z "$SCOABSPATH" && echo ${wl}-rpath,$libdir`' archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib' archive_expsym_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname,\${SCOABSPATH:+${install_libdir}/}$soname,-retain-symbols-file,$export_symbols -o $lib' else ld_shlibs_GCJ=no fi ;; esac ;; sunos4*) archive_cmds_GCJ='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' wlarc= hardcode_direct_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; *) if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else ld_shlibs_GCJ=no fi ;; esac if test "$ld_shlibs_GCJ" = no; then runpath_var= hardcode_libdir_flag_spec_GCJ= export_dynamic_flag_spec_GCJ= whole_archive_flag_spec_GCJ= fi else # PORTME fill in a description of your system's linker (not GNU ld) case $host_os in aix3*) allow_undefined_flag_GCJ=unsupported always_export_symbols_GCJ=yes archive_expsym_cmds_GCJ='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' # Note: this linker hardcodes the directories in LIBPATH if there # are no directories specified by -L. hardcode_minus_L_GCJ=yes if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then # Neither direct hardcoding nor static linking is supported with a # broken collect2. hardcode_direct_GCJ=unsupported fi ;; aix4* | aix5*) if test "$host_cpu" = ia64; then # On IA64, the linker does run time linking by default, so we don't # have to do anything special. aix_use_runtimelinking=no exp_sym_flag='-Bexport' no_entry_flag="" else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm if $NM -V 2>&1 | grep 'GNU' > /dev/null; then export_symbols_cmds_GCJ='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$2 == "T") || (\$2 == "D") || (\$2 == "B")) && (substr(\$3,1,1) != ".")) { print \$3 } }'\'' | sort -u > $export_symbols' else export_symbols_cmds_GCJ='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$2 == "T") || (\$2 == "D") || (\$2 == "B")) && (substr(\$3,1,1) != ".")) { print \$3 } }'\'' | sort -u > $export_symbols' fi aix_use_runtimelinking=no # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we # need to do runtime linking. case $host_os in aix4.[23]|aix4.[23].*|aix5*) for ld_flag in $LDFLAGS; do if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then aix_use_runtimelinking=yes break fi done ;; esac exp_sym_flag='-bexport' no_entry_flag='-bnoentry' fi # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library # or program results in "error TOC overflow" add -mminimal-toc to # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. archive_cmds_GCJ='' hardcode_direct_GCJ=yes hardcode_libdir_separator_GCJ=':' link_all_deplibs_GCJ=yes if test "$GCC" = yes; then case $host_os in aix4.[012]|aix4.[012].*) # We only want to do this on AIX 4.2 and lower, the check # below for broken collect2 doesn't work under 4.3+ collect2name=`${CC} -print-prog-name=collect2` if test -f "$collect2name" && \ strings "$collect2name" | grep resolve_lib_name >/dev/null then # We have reworked collect2 : else # We have old collect2 hardcode_direct_GCJ=unsupported # It fails to find uninstalled libraries when the uninstalled # path is not listed in the libpath. Setting hardcode_minus_L # to unsupported forces relinking hardcode_minus_L_GCJ=yes hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_libdir_separator_GCJ= fi ;; esac shared_flag='-shared' if test "$aix_use_runtimelinking" = yes; then shared_flag="$shared_flag "'${wl}-G' fi else # not using gcc if test "$host_cpu" = ia64; then # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release # chokes on -Wl,-G. The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to export. always_export_symbols_GCJ=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. allow_undefined_flag_GCJ='-berok' # Determine the default libpath from the value encoded in an empty executable. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/ p } }' aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$aix_libpath"; then aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi hardcode_libdir_flag_spec_GCJ='${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds_GCJ="\$CC"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then echo "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then hardcode_libdir_flag_spec_GCJ='${wl}-R $libdir:/usr/lib:/lib' allow_undefined_flag_GCJ="-z nodefs" archive_expsym_cmds_GCJ="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an empty executable. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/ p } }' aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$aix_libpath"; then aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi hardcode_libdir_flag_spec_GCJ='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. no_undefined_flag_GCJ=' ${wl}-bernotok' allow_undefined_flag_GCJ=' ${wl}-berok' # Exported symbols can be pulled into shared objects from archives whole_archive_flag_spec_GCJ='$convenience' archive_cmds_need_lc_GCJ=yes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds_GCJ="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; amigaos*) archive_cmds_GCJ='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_minus_L_GCJ=yes # see comment about different semantics on the GNU ld section ld_shlibs_GCJ=no ;; bsdi[45]*) export_dynamic_flag_spec_GCJ=-rdynamic ;; cygwin* | mingw* | pw32*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. hardcode_libdir_flag_spec_GCJ=' ' allow_undefined_flag_GCJ=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. archive_cmds_GCJ='$CC -o $lib $libobjs $compiler_flags `echo "$deplibs" | $SED -e '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. old_archive_From_new_cmds_GCJ='true' # FIXME: Should let the user specify the lib program. old_archive_cmds_GCJ='lib -OUT:$oldlib$oldobjs$old_deplibs' fix_srcfile_path_GCJ='`cygpath -w "$srcfile"`' enable_shared_with_static_runtimes_GCJ=yes ;; darwin* | rhapsody*) case $host_os in rhapsody* | darwin1.[012]) allow_undefined_flag_GCJ='${wl}-undefined ${wl}suppress' ;; *) # Darwin 1.3 on if test -z ${MACOSX_DEPLOYMENT_TARGET} ; then allow_undefined_flag_GCJ='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' else case ${MACOSX_DEPLOYMENT_TARGET} in 10.[012]) allow_undefined_flag_GCJ='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) allow_undefined_flag_GCJ='${wl}-undefined ${wl}dynamic_lookup' ;; esac fi ;; esac archive_cmds_need_lc_GCJ=no hardcode_direct_GCJ=no hardcode_automatic_GCJ=yes hardcode_shlibpath_var_GCJ=unsupported whole_archive_flag_spec_GCJ='' link_all_deplibs_GCJ=yes if test "$GCC" = yes ; then output_verbose_link_cmd='echo' archive_cmds_GCJ='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' module_cmds_GCJ='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds_GCJ='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds_GCJ='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' else case $cc_basename in xlc*) output_verbose_link_cmd='echo' archive_cmds_GCJ='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`echo $rpath/$soname` $xlcverstring' module_cmds_GCJ='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds archive_expsym_cmds_GCJ='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $xlcverstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' module_expsym_cmds_GCJ='sed -e "s,#.*,," -e "s,^[ ]*,," -e "s,^\(..*\),_&," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' ;; *) ld_shlibs_GCJ=no ;; esac fi ;; dgux*) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_shlibpath_var_GCJ=no ;; freebsd1*) ld_shlibs_GCJ=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. Future versions do this automatically, but an explicit c++rt0.o # does not break anything, and helps significantly (at the cost of a little # extra space). freebsd2.2*) archive_cmds_GCJ='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' hardcode_libdir_flag_spec_GCJ='-R$libdir' hardcode_direct_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; # Unfortunately, older versions of FreeBSD 2 do not have this feature. freebsd2*) archive_cmds_GCJ='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_GCJ=yes hardcode_minus_L_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; # FreeBSD 3 and greater uses gcc -shared to do shared libraries. freebsd* | dragonfly*) archive_cmds_GCJ='$CC -shared -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec_GCJ='-R$libdir' hardcode_direct_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; hpux9*) if test "$GCC" = yes; then archive_cmds_GCJ='$rm $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else archive_cmds_GCJ='$rm $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' fi hardcode_libdir_flag_spec_GCJ='${wl}+b ${wl}$libdir' hardcode_libdir_separator_GCJ=: hardcode_direct_GCJ=yes # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_GCJ=yes export_dynamic_flag_spec_GCJ='${wl}-E' ;; hpux10*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then archive_cmds_GCJ='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_GCJ='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec_GCJ='${wl}+b ${wl}$libdir' hardcode_libdir_separator_GCJ=: hardcode_direct_GCJ=yes export_dynamic_flag_spec_GCJ='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_GCJ=yes fi ;; hpux11*) if test "$GCC" = yes -a "$with_gnu_ld" = no; then case $host_cpu in hppa*64*) archive_cmds_GCJ='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds_GCJ='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds_GCJ='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac else case $host_cpu in hppa*64*) archive_cmds_GCJ='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds_GCJ='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds_GCJ='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec_GCJ='${wl}+b ${wl}$libdir' hardcode_libdir_separator_GCJ=: case $host_cpu in hppa*64*|ia64*) hardcode_libdir_flag_spec_ld_GCJ='+b $libdir' hardcode_direct_GCJ=no hardcode_shlibpath_var_GCJ=no ;; *) hardcode_direct_GCJ=yes export_dynamic_flag_spec_GCJ='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L_GCJ=yes ;; esac fi ;; irix5* | irix6* | nonstopux*) if test "$GCC" = yes; then archive_cmds_GCJ='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else archive_cmds_GCJ='$LD -shared $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec_ld_GCJ='-rpath $libdir' fi hardcode_libdir_flag_spec_GCJ='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_GCJ=: link_all_deplibs_GCJ=yes ;; netbsd*) if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then archive_cmds_GCJ='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out else archive_cmds_GCJ='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF fi hardcode_libdir_flag_spec_GCJ='-R$libdir' hardcode_direct_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; newsos6) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_GCJ=yes hardcode_libdir_flag_spec_GCJ='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_GCJ=: hardcode_shlibpath_var_GCJ=no ;; openbsd*) if test -f /usr/libexec/ld.so; then hardcode_direct_GCJ=yes hardcode_shlibpath_var_GCJ=no if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then archive_cmds_GCJ='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' hardcode_libdir_flag_spec_GCJ='${wl}-rpath,$libdir' export_dynamic_flag_spec_GCJ='${wl}-E' else case $host_os in openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) archive_cmds_GCJ='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec_GCJ='-R$libdir' ;; *) archive_cmds_GCJ='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec_GCJ='${wl}-rpath,$libdir' ;; esac fi else ld_shlibs_GCJ=no fi ;; os2*) hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_minus_L_GCJ=yes allow_undefined_flag_GCJ=unsupported archive_cmds_GCJ='$echo "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$echo "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$echo DATA >> $output_objdir/$libname.def~$echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~$echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' old_archive_From_new_cmds_GCJ='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' ;; osf3*) if test "$GCC" = yes; then allow_undefined_flag_GCJ=' ${wl}-expect_unresolved ${wl}\*' archive_cmds_GCJ='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else allow_undefined_flag_GCJ=' -expect_unresolved \*' archive_cmds_GCJ='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' fi hardcode_libdir_flag_spec_GCJ='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator_GCJ=: ;; osf4* | osf5*) # as osf3* with the addition of -msym flag if test "$GCC" = yes; then allow_undefined_flag_GCJ=' ${wl}-expect_unresolved ${wl}\*' archive_cmds_GCJ='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec_GCJ='${wl}-rpath ${wl}$libdir' else allow_undefined_flag_GCJ=' -expect_unresolved \*' archive_cmds_GCJ='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -msym -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib' archive_expsym_cmds_GCJ='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; echo "-hidden">> $lib.exp~ $LD -shared${allow_undefined_flag} -input $lib.exp $linker_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${output_objdir}/so_locations -o $lib~$rm $lib.exp' # Both c and cxx compiler support -rpath directly hardcode_libdir_flag_spec_GCJ='-rpath $libdir' fi hardcode_libdir_separator_GCJ=: ;; solaris*) no_undefined_flag_GCJ=' -z text' if test "$GCC" = yes; then wlarc='${wl}' archive_cmds_GCJ='$CC -shared ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $CC -shared ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$rm $lib.exp' else wlarc='' archive_cmds_GCJ='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' archive_expsym_cmds_GCJ='$echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~ $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$rm $lib.exp' fi hardcode_libdir_flag_spec_GCJ='-R$libdir' hardcode_shlibpath_var_GCJ=no case $host_os in solaris2.[0-5] | solaris2.[0-5].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. GCC discards it without `$wl', # but is careful enough not to reorder. # Supported since Solaris 2.6 (maybe 2.5.1?) if test "$GCC" = yes; then whole_archive_flag_spec_GCJ='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' else whole_archive_flag_spec_GCJ='-z allextract$convenience -z defaultextract' fi ;; esac link_all_deplibs_GCJ=yes ;; sunos4*) if test "x$host_vendor" = xsequent; then # Use $CC to link under sequent, because it throws in some extra .o # files that make .init and .fini sections work. archive_cmds_GCJ='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_GCJ='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' fi hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_direct_GCJ=yes hardcode_minus_L_GCJ=yes hardcode_shlibpath_var_GCJ=no ;; sysv4) case $host_vendor in sni) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_GCJ=yes # is this really true??? ;; siemens) ## LD is ld it makes a PLAMLIB ## CC just makes a GrossModule. archive_cmds_GCJ='$LD -G -o $lib $libobjs $deplibs $linker_flags' reload_cmds_GCJ='$CC -r -o $output$reload_objs' hardcode_direct_GCJ=no ;; motorola) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct_GCJ=no #Motorola manual says yes, but my tests say they lie ;; esac runpath_var='LD_RUN_PATH' hardcode_shlibpath_var_GCJ=no ;; sysv4.3*) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var_GCJ=no export_dynamic_flag_spec_GCJ='-Bexport' ;; sysv4*MP*) if test -d /usr/nec; then archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var_GCJ=no runpath_var=LD_RUN_PATH hardcode_runpath_var=yes ld_shlibs_GCJ=yes fi ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) no_undefined_flag_GCJ='${wl}-z,text' archive_cmds_need_lc_GCJ=no hardcode_shlibpath_var_GCJ=no runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds_GCJ='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_GCJ='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. If we're not using GNU ld we use -z text # though, which does catch some bad symbols but isn't as heavy-handed # as -z defs. no_undefined_flag_GCJ='${wl}-z,text' allow_undefined_flag_GCJ='${wl}-z,nodefs' archive_cmds_need_lc_GCJ=no hardcode_shlibpath_var_GCJ=no hardcode_libdir_flag_spec_GCJ='`test -z "$SCOABSPATH" && echo ${wl}-R,$libdir`' hardcode_libdir_separator_GCJ=':' link_all_deplibs_GCJ=yes export_dynamic_flag_spec_GCJ='${wl}-Bexport' runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds_GCJ='$CC -shared ${wl}-h,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds_GCJ='$CC -G ${wl}-h,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds_GCJ='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,\${SCOABSPATH:+${install_libdir}/}$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; uts4*) archive_cmds_GCJ='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec_GCJ='-L$libdir' hardcode_shlibpath_var_GCJ=no ;; *) ld_shlibs_GCJ=no ;; esac fi { echo "$as_me:$LINENO: result: $ld_shlibs_GCJ" >&5 echo "${ECHO_T}$ld_shlibs_GCJ" >&6; } test "$ld_shlibs_GCJ" = no && can_build_shared=no # # Do we need to explicitly link libc? # case "x$archive_cmds_need_lc_GCJ" in x|xyes) # Assume -lc should be added archive_cmds_need_lc_GCJ=yes if test "$enable_shared" = yes && test "$GCC" = yes; then case $archive_cmds_GCJ in *'~'*) # FIXME: we may have to deal with multi-command sequences. ;; '$CC '*) # Test whether the compiler implicitly links with -lc since on some # systems, -lgcc has to come before -lc. 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The import file would start with # the line `#! .'. This would cause the generated library to # depend on `.', always an invalid library. This was fixed in # development snapshots of GCC prior to 3.0. case $host_os in aix4 | aix4.[01] | aix4.[01].*) if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' echo ' yes ' echo '#endif'; } | ${CC} -E - | grep yes > /dev/null; then : else can_build_shared=no fi ;; esac # AIX (on Power*) has no versioning support, so currently we can not hardcode correct # soname into executable. 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They are # bogus both because they are the default anyway, and because # using them would break gcc on systems where it needs fixed includes. case $ac_im_incroot in /usr/include) ac_x_includes= ;; *) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;; esac case $ac_im_usrlibdir in /usr/lib | /lib) ;; *) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;; esac fi cd .. rm -f -r conftest.dir fi # Standard set of common directories for X headers. # Check X11 before X11Rn because it is often a symlink to the current release. ac_x_header_dirs=' /usr/X11/include /usr/X11R6/include /usr/X11R5/include /usr/X11R4/include /usr/include/X11 /usr/include/X11R6 /usr/include/X11R5 /usr/include/X11R4 /usr/local/X11/include /usr/local/X11R6/include /usr/local/X11R5/include /usr/local/X11R4/include /usr/local/include/X11 /usr/local/include/X11R6 /usr/local/include/X11R5 /usr/local/include/X11R4 /usr/X386/include /usr/x386/include /usr/XFree86/include/X11 /usr/include /usr/local/include /usr/unsupported/include /usr/athena/include /usr/local/x11r5/include /usr/lpp/Xamples/include /usr/openwin/include /usr/openwin/share/include' if test "$ac_x_includes" = no; then # Guess where to find include files, by looking for Xlib.h. # First, try using that file with no special directory specified. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then # We can compile using X headers with no special include directory. ac_x_includes= else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 for ac_dir in $ac_x_header_dirs; do if test -r "$ac_dir/X11/Xlib.h"; then ac_x_includes=$ac_dir break fi done fi rm -f conftest.err conftest.$ac_ext fi # $ac_x_includes = no if test "$ac_x_libraries" = no; then # Check for the libraries. # See if we find them without any special options. # Don't add to $LIBS permanently. ac_save_LIBS=$LIBS LIBS="-lX11 $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { XrmInitialize () ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then LIBS=$ac_save_LIBS # We can link X programs with no special library path. ac_x_libraries= else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 LIBS=$ac_save_LIBS for ac_dir in `echo "$ac_x_includes $ac_x_header_dirs" | sed s/include/lib/g` do # Don't even attempt the hair of trying to link an X program! for ac_extension in a so sl; do if test -r "$ac_dir/libX11.$ac_extension"; then ac_x_libraries=$ac_dir break 2 fi done done fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi # $ac_x_libraries = no case $ac_x_includes,$ac_x_libraries in #( no,* | *,no | *\'*) # Didn't find X, or a directory has "'" in its name. ac_cv_have_x="have_x=no";; #( *) # Record where we found X for the cache. ac_cv_have_x="have_x=yes\ ac_x_includes='$ac_x_includes'\ ac_x_libraries='$ac_x_libraries'" esac fi ;; #( *) have_x=yes;; esac eval "$ac_cv_have_x" fi # $with_x != no if test "$have_x" != yes; then { echo "$as_me:$LINENO: result: $have_x" >&5 echo "${ECHO_T}$have_x" >&6; } no_x=yes else # If each of the values was on the command line, it overrides each guess. test "x$x_includes" = xNONE && x_includes=$ac_x_includes test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries # Update the cache value to reflect the command line values. ac_cv_have_x="have_x=yes\ ac_x_includes='$x_includes'\ ac_x_libraries='$x_libraries'" { echo "$as_me:$LINENO: result: libraries $x_libraries, headers $x_includes" >&5 echo "${ECHO_T}libraries $x_libraries, headers $x_includes" >&6; } fi if test "$no_x" = yes; then # Not all programs may use this symbol, but it does not hurt to define it. cat >>confdefs.h <<\_ACEOF #define X_DISPLAY_MISSING 1 _ACEOF X_CFLAGS= X_PRE_LIBS= X_LIBS= X_EXTRA_LIBS= else if test -n "$x_includes"; then X_CFLAGS="$X_CFLAGS -I$x_includes" fi # It would also be nice to do this for all -L options, not just this one. if test -n "$x_libraries"; then X_LIBS="$X_LIBS -L$x_libraries" # For Solaris; some versions of Sun CC require a space after -R and # others require no space. Words are not sufficient . . . . { echo "$as_me:$LINENO: checking whether -R must be followed by a space" >&5 echo $ECHO_N "checking whether -R must be followed by a space... $ECHO_C" >&6; } ac_xsave_LIBS=$LIBS; LIBS="$LIBS -R$x_libraries" ac_xsave_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } X_LIBS="$X_LIBS -R$x_libraries" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 LIBS="$ac_xsave_LIBS -R $x_libraries" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then { echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6; } X_LIBS="$X_LIBS -R $x_libraries" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 { echo "$as_me:$LINENO: result: neither works" >&5 echo "${ECHO_T}neither works" >&6; } fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext ac_c_werror_flag=$ac_xsave_c_werror_flag LIBS=$ac_xsave_LIBS fi # Check for system-dependent libraries X programs must link with. # Do this before checking for the system-independent R6 libraries # (-lICE), since we may need -lsocket or whatever for X linking. if test "$ISC" = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl_s -linet" else # Martyn Johnson says this is needed for Ultrix, if the X # libraries were built with DECnet support. And Karl Berry says # the Alpha needs dnet_stub (dnet does not exist). ac_xsave_LIBS="$LIBS"; LIBS="$LIBS $X_LIBS -lX11" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char XOpenDisplay (); int main () { return XOpenDisplay (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 { echo "$as_me:$LINENO: checking for dnet_ntoa in -ldnet" >&5 echo $ECHO_N "checking for dnet_ntoa in -ldnet... $ECHO_C" >&6; } if test "${ac_cv_lib_dnet_dnet_ntoa+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_dnet_dnet_ntoa=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_dnet_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_dnet_dnet_ntoa" >&5 echo "${ECHO_T}$ac_cv_lib_dnet_dnet_ntoa" >&6; } if test $ac_cv_lib_dnet_dnet_ntoa = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet" fi if test $ac_cv_lib_dnet_dnet_ntoa = no; then { echo "$as_me:$LINENO: checking for dnet_ntoa in -ldnet_stub" >&5 echo $ECHO_N "checking for dnet_ntoa in -ldnet_stub... $ECHO_C" >&6; } if test "${ac_cv_lib_dnet_stub_dnet_ntoa+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet_stub $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_dnet_stub_dnet_ntoa=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_dnet_stub_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_dnet_stub_dnet_ntoa" >&5 echo "${ECHO_T}$ac_cv_lib_dnet_stub_dnet_ntoa" >&6; } if test $ac_cv_lib_dnet_stub_dnet_ntoa = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet_stub" fi fi fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS="$ac_xsave_LIBS" # msh@cis.ufl.edu says -lnsl (and -lsocket) are needed for his 386/AT, # to get the SysV transport functions. # Chad R. Larson says the Pyramis MIS-ES running DC/OSx (SVR4) # needs -lnsl. # The nsl library prevents programs from opening the X display # on Irix 5.2, according to T.E. Dickey. # The functions gethostbyname, getservbyname, and inet_addr are # in -lbsd on LynxOS 3.0.1/i386, according to Lars Hecking. { echo "$as_me:$LINENO: checking for gethostbyname" >&5 echo $ECHO_N "checking for gethostbyname... $ECHO_C" >&6; } if test "${ac_cv_func_gethostbyname+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define gethostbyname to an innocuous variant, in case declares gethostbyname. For example, HP-UX 11i declares gettimeofday. */ #define gethostbyname innocuous_gethostbyname /* System header to define __stub macros and hopefully few prototypes, which can conflict with char gethostbyname (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef gethostbyname /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_gethostbyname || defined __stub___gethostbyname choke me #endif int main () { return gethostbyname (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_gethostbyname=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_gethostbyname" >&5 echo "${ECHO_T}$ac_cv_func_gethostbyname" >&6; } if test $ac_cv_func_gethostbyname = no; then { echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5 echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6; } if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnsl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_nsl_gethostbyname=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_nsl_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5 echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6; } if test $ac_cv_lib_nsl_gethostbyname = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl" fi if test $ac_cv_lib_nsl_gethostbyname = no; then { echo "$as_me:$LINENO: checking for gethostbyname in -lbsd" >&5 echo $ECHO_N "checking for gethostbyname in -lbsd... $ECHO_C" >&6; } if test "${ac_cv_lib_bsd_gethostbyname+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbsd $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_bsd_gethostbyname=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_bsd_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_bsd_gethostbyname" >&5 echo "${ECHO_T}$ac_cv_lib_bsd_gethostbyname" >&6; } if test $ac_cv_lib_bsd_gethostbyname = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lbsd" fi fi fi # lieder@skyler.mavd.honeywell.com says without -lsocket, # socket/setsockopt and other routines are undefined under SCO ODT # 2.0. But -lsocket is broken on IRIX 5.2 (and is not necessary # on later versions), says Simon Leinen: it contains gethostby* # variants that don't use the name server (or something). -lsocket # must be given before -lnsl if both are needed. We assume that # if connect needs -lnsl, so does gethostbyname. { echo "$as_me:$LINENO: checking for connect" >&5 echo $ECHO_N "checking for connect... $ECHO_C" >&6; } if test "${ac_cv_func_connect+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define connect to an innocuous variant, in case declares connect. For example, HP-UX 11i declares gettimeofday. */ #define connect innocuous_connect /* System header to define __stub macros and hopefully few prototypes, which can conflict with char connect (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef connect /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char connect (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_connect || defined __stub___connect choke me #endif int main () { return connect (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_connect=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_connect=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_connect" >&5 echo "${ECHO_T}$ac_cv_func_connect" >&6; } if test $ac_cv_func_connect = no; then { echo "$as_me:$LINENO: checking for connect in -lsocket" >&5 echo $ECHO_N "checking for connect in -lsocket... $ECHO_C" >&6; } if test "${ac_cv_lib_socket_connect+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $X_EXTRA_LIBS $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char connect (); int main () { return connect (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_socket_connect=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_socket_connect=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_socket_connect" >&5 echo "${ECHO_T}$ac_cv_lib_socket_connect" >&6; } if test $ac_cv_lib_socket_connect = yes; then X_EXTRA_LIBS="-lsocket $X_EXTRA_LIBS" fi fi # Guillermo Gomez says -lposix is necessary on A/UX. { echo "$as_me:$LINENO: checking for remove" >&5 echo $ECHO_N "checking for remove... $ECHO_C" >&6; } if test "${ac_cv_func_remove+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define remove to an innocuous variant, in case declares remove. For example, HP-UX 11i declares gettimeofday. */ #define remove innocuous_remove /* System header to define __stub macros and hopefully few prototypes, which can conflict with char remove (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef remove /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char remove (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_remove || defined __stub___remove choke me #endif int main () { return remove (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_remove=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_remove=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_remove" >&5 echo "${ECHO_T}$ac_cv_func_remove" >&6; } if test $ac_cv_func_remove = no; then { echo "$as_me:$LINENO: checking for remove in -lposix" >&5 echo $ECHO_N "checking for remove in -lposix... $ECHO_C" >&6; } if test "${ac_cv_lib_posix_remove+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lposix $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char remove (); int main () { return remove (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_posix_remove=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_posix_remove=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_posix_remove" >&5 echo "${ECHO_T}$ac_cv_lib_posix_remove" >&6; } if test $ac_cv_lib_posix_remove = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lposix" fi fi # BSDI BSD/OS 2.1 needs -lipc for XOpenDisplay. { echo "$as_me:$LINENO: checking for shmat" >&5 echo $ECHO_N "checking for shmat... $ECHO_C" >&6; } if test "${ac_cv_func_shmat+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define shmat to an innocuous variant, in case declares shmat. For example, HP-UX 11i declares gettimeofday. */ #define shmat innocuous_shmat /* System header to define __stub macros and hopefully few prototypes, which can conflict with char shmat (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef shmat /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shmat (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_shmat || defined __stub___shmat choke me #endif int main () { return shmat (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_shmat=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_shmat=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_shmat" >&5 echo "${ECHO_T}$ac_cv_func_shmat" >&6; } if test $ac_cv_func_shmat = no; then { echo "$as_me:$LINENO: checking for shmat in -lipc" >&5 echo $ECHO_N "checking for shmat in -lipc... $ECHO_C" >&6; } if test "${ac_cv_lib_ipc_shmat+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lipc $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shmat (); int main () { return shmat (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_ipc_shmat=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_ipc_shmat=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_ipc_shmat" >&5 echo "${ECHO_T}$ac_cv_lib_ipc_shmat" >&6; } if test $ac_cv_lib_ipc_shmat = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lipc" fi fi fi # Check for libraries that X11R6 Xt/Xaw programs need. ac_save_LDFLAGS=$LDFLAGS test -n "$x_libraries" && LDFLAGS="$LDFLAGS -L$x_libraries" # SM needs ICE to (dynamically) link under SunOS 4.x (so we have to # check for ICE first), but we must link in the order -lSM -lICE or # we get undefined symbols. So assume we have SM if we have ICE. # These have to be linked with before -lX11, unlike the other # libraries we check for below, so use a different variable. # John Interrante, Karl Berry { echo "$as_me:$LINENO: checking for IceConnectionNumber in -lICE" >&5 echo $ECHO_N "checking for IceConnectionNumber in -lICE... $ECHO_C" >&6; } if test "${ac_cv_lib_ICE_IceConnectionNumber+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lICE $X_EXTRA_LIBS $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char IceConnectionNumber (); int main () { return IceConnectionNumber (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_ICE_IceConnectionNumber=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_lib_ICE_IceConnectionNumber=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_ICE_IceConnectionNumber" >&5 echo "${ECHO_T}$ac_cv_lib_ICE_IceConnectionNumber" >&6; } if test $ac_cv_lib_ICE_IceConnectionNumber = yes; then X_PRE_LIBS="$X_PRE_LIBS -lSM -lICE" fi LDFLAGS=$ac_save_LDFLAGS fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! { echo "$as_me:$LINENO: checking for working alloca.h" >&5 echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6; } if test "${ac_cv_working_alloca_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { char *p = (char *) alloca (2 * sizeof (int)); if (p) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_working_alloca_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_working_alloca_h=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5 echo "${ECHO_T}$ac_cv_working_alloca_h" >&6; } if test $ac_cv_working_alloca_h = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_ALLOCA_H 1 _ACEOF fi { echo "$as_me:$LINENO: checking for alloca" >&5 echo $ECHO_N "checking for alloca... $ECHO_C" >&6; } if test "${ac_cv_func_alloca_works+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifdef __GNUC__ # define alloca __builtin_alloca #else # ifdef _MSC_VER # include # define alloca _alloca # else # ifdef HAVE_ALLOCA_H # include # else # ifdef _AIX #pragma alloca # else # ifndef alloca /* predefined by HP cc +Olibcalls */ char *alloca (); # endif # endif # endif # endif #endif int main () { char *p = (char *) alloca (1); if (p) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func_alloca_works=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func_alloca_works=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5 echo "${ECHO_T}$ac_cv_func_alloca_works" >&6; } if test $ac_cv_func_alloca_works = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_ALLOCA 1 _ACEOF else # The SVR3 libPW and SVR4 libucb both contain incompatible functions # that cause trouble. Some versions do not even contain alloca or # contain a buggy version. If you still want to use their alloca, # use ar to extract alloca.o from them instead of compiling alloca.c. ALLOCA=\${LIBOBJDIR}alloca.$ac_objext cat >>confdefs.h <<\_ACEOF #define C_ALLOCA 1 _ACEOF { echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5 echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6; } if test "${ac_cv_os_cray+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined CRAY && ! defined CRAY2 webecray #else wenotbecray #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "webecray" >/dev/null 2>&1; then ac_cv_os_cray=yes else ac_cv_os_cray=no fi rm -f conftest* fi { echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5 echo "${ECHO_T}$ac_cv_os_cray" >&6; } if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF #define CRAY_STACKSEG_END $ac_func _ACEOF break fi done fi { echo "$as_me:$LINENO: checking stack direction for C alloca" >&5 echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6; } if test "${ac_cv_c_stack_direction+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_c_stack_direction=0 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int find_stack_direction () { static char *addr = 0; auto char dummy; if (addr == 0) { addr = &dummy; return find_stack_direction (); } else return (&dummy > addr) ? 1 : -1; } int main () { return find_stack_direction () < 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_c_stack_direction=1 else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_c_stack_direction=-1 fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5 echo "${ECHO_T}$ac_cv_c_stack_direction" >&6; } cat >>confdefs.h <<_ACEOF #define STACK_DIRECTION $ac_cv_c_stack_direction _ACEOF fi { echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6; } if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include #include int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then : else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 echo "${ECHO_T}$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then cat >>confdefs.h <<\_ACEOF #define STDC_HEADERS 1 _ACEOF fi { echo "$as_me:$LINENO: checking for sys/wait.h that is POSIX.1 compatible" >&5 echo $ECHO_N "checking for sys/wait.h that is POSIX.1 compatible... $ECHO_C" >&6; } if test "${ac_cv_header_sys_wait_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #ifndef WEXITSTATUS # define WEXITSTATUS(stat_val) ((unsigned int) (stat_val) >> 8) #endif #ifndef WIFEXITED # define WIFEXITED(stat_val) (((stat_val) & 255) == 0) #endif int main () { int s; wait (&s); s = WIFEXITED (s) ? WEXITSTATUS (s) : 1; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_sys_wait_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_sys_wait_h=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_sys_wait_h" >&5 echo "${ECHO_T}$ac_cv_header_sys_wait_h" >&6; } if test $ac_cv_header_sys_wait_h = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_SYS_WAIT_H 1 _ACEOF fi for ac_header in limits.h malloc.h stdlib.h string.h sys/param.h sys/time.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for iconv.h" >&5 echo $ECHO_N "checking for iconv.h... $ECHO_C" >&6; } for p in $TKGATE_INCDIRS; do if test -f $p/iconv.h; then iconv_h_dir=$p fi done for p in $TKGATE_LIBDIRS; do if test -f $p/libiconv.a; then iconv_lib_dir=$p fi done if test "X$iconv_h_dir" = "X"; then { echo "$as_me:$LINENO: result: not found" >&5 echo "${ECHO_T}not found" >&6; } else { echo "$as_me:$LINENO: result: found in $iconv_h_dir" >&5 echo "${ECHO_T}found in $iconv_h_dir" >&6; } cat >>confdefs.h <<\_ACEOF #define HAVE_ICONV_H 1 _ACEOF ICONV_IPATH="-I$iconv_h_dir" if test "X$iconv_lib_dir" != "X"; then ICONV_LPATH="-L$iconv_lib_dir" ICONV_LIB="-liconv" fi fi # Checks for typedefs, structures, and compiler characteristics. { echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6; } if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { /* FIXME: Include the comments suggested by Paul. */ #ifndef __cplusplus /* Ultrix mips cc rejects this. */ typedef int charset[2]; const charset cs; /* SunOS 4.1.1 cc rejects this. */ char const *const *pcpcc; char **ppc; /* NEC SVR4.0.2 mips cc rejects this. */ struct point {int x, y;}; static struct point const zero = {0,0}; /* AIX XL C 1.02.0.0 rejects this. It does not let you subtract one const X* pointer from another in an arm of an if-expression whose if-part is not a constant expression */ const char *g = "string"; pcpcc = &g + (g ? g-g : 0); /* HPUX 7.0 cc rejects these. */ ++pcpcc; ppc = (char**) pcpcc; pcpcc = (char const *const *) ppc; { /* SCO 3.2v4 cc rejects this. */ char *t; char const *s = 0 ? (char *) 0 : (char const *) 0; *t++ = 0; if (s) return 0; } { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ int x[] = {25, 17}; const int *foo = &x[0]; ++foo; } { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ typedef const int *iptr; iptr p = 0; ++p; } { /* AIX XL C 1.02.0.0 rejects this saying "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ struct s { int j; const int *ap[3]; }; struct s *b; b->j = 5; } { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ const int foo = 10; if (!foo) return 0; } return !cs[0] && !zero.x; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_const=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6; } if test $ac_cv_c_const = no; then cat >>confdefs.h <<\_ACEOF #define const _ACEOF fi { echo "$as_me:$LINENO: checking for size_t" >&5 echo $ECHO_N "checking for size_t... $ECHO_C" >&6; } if test "${ac_cv_type_size_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef size_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_size_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_size_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 echo "${ECHO_T}$ac_cv_type_size_t" >&6; } if test $ac_cv_type_size_t = yes; then : else cat >>confdefs.h <<_ACEOF #define size_t unsigned int _ACEOF fi { echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 echo $ECHO_N "checking whether time.h and sys/time.h may both be included... $ECHO_C" >&6; } if test "${ac_cv_header_time+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include int main () { if ((struct tm *) 0) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_time=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_time=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 echo "${ECHO_T}$ac_cv_header_time" >&6; } if test $ac_cv_header_time = yes; then cat >>confdefs.h <<\_ACEOF #define TIME_WITH_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 echo $ECHO_N "checking whether struct tm is in sys/time.h or time.h... $ECHO_C" >&6; } if test "${ac_cv_struct_tm+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { struct tm tm; int *p = &tm.tm_sec; return !p; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_struct_tm=time.h else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_struct_tm=sys/time.h fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 echo "${ECHO_T}$ac_cv_struct_tm" >&6; } if test $ac_cv_struct_tm = sys/time.h; then cat >>confdefs.h <<\_ACEOF #define TM_IN_SYS_TIME 1 _ACEOF fi { echo "$as_me:$LINENO: checking for unsigned long long" >&5 echo $ECHO_N "checking for unsigned long long... $ECHO_C" >&6; } if test "${ac_cv_type_unsigned_long_long+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef unsigned long long ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_unsigned_long_long=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_unsigned_long_long=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_unsigned_long_long" >&5 echo "${ECHO_T}$ac_cv_type_unsigned_long_long" >&6; } if test $ac_cv_type_unsigned_long_long = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_UNSIGNED_LONG_LONG 1 _ACEOF fi # Checks for library functions. { echo "$as_me:$LINENO: checking for pid_t" >&5 echo $ECHO_N "checking for pid_t... $ECHO_C" >&6; } if test "${ac_cv_type_pid_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef pid_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_pid_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_pid_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_pid_t" >&5 echo "${ECHO_T}$ac_cv_type_pid_t" >&6; } if test $ac_cv_type_pid_t = yes; then : else cat >>confdefs.h <<_ACEOF #define pid_t int _ACEOF fi for ac_header in vfork.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_func in fork vfork do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. 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What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking for GNU libc compatible malloc" >&5 echo $ECHO_N "checking for GNU libc compatible malloc... $ECHO_C" >&6; } if test "${ac_cv_func_malloc_0_nonnull+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "$cross_compiling" = yes; then ac_cv_func_malloc_0_nonnull=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #if defined STDC_HEADERS || defined HAVE_STDLIB_H # include #else char *malloc (); #endif int main () { return ! malloc (0); ; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then ac_cv_func_malloc_0_nonnull=yes else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_malloc_0_nonnull=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi { echo "$as_me:$LINENO: result: $ac_cv_func_malloc_0_nonnull" >&5 echo "${ECHO_T}$ac_cv_func_malloc_0_nonnull" >&6; } if test $ac_cv_func_malloc_0_nonnull = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_MALLOC 1 _ACEOF else cat >>confdefs.h <<\_ACEOF #define HAVE_MALLOC 0 _ACEOF case " $LIBOBJS " in *" malloc.$ac_objext "* ) ;; *) LIBOBJS="$LIBOBJS malloc.$ac_objext" ;; esac cat >>confdefs.h <<\_ACEOF #define malloc rpl_malloc _ACEOF fi { echo "$as_me:$LINENO: checking return type of signal handlers" >&5 echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6; } if test "${ac_cv_type_signal+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { return *(signal (0, 0)) (0) == 1; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_signal=int else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_signal=void fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5 echo "${ECHO_T}$ac_cv_type_signal" >&6; } cat >>confdefs.h <<_ACEOF #define RETSIGTYPE $ac_cv_type_signal _ACEOF { echo "$as_me:$LINENO: checking whether lstat dereferences a symlink specified with a trailing slash" >&5 echo $ECHO_N "checking whether lstat dereferences a symlink specified with a trailing slash... $ECHO_C" >&6; } if test "${ac_cv_func_lstat_dereferences_slashed_symlink+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else rm -f conftest.sym conftest.file echo >conftest.file if test "$as_ln_s" = "ln -s" && ln -s conftest.file conftest.sym; then if test "$cross_compiling" = yes; then ac_cv_func_lstat_dereferences_slashed_symlink=no else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { struct stat sbuf; /* Linux will dereference the symlink and fail. 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Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub__doprnt || defined __stub____doprnt choke me #endif int main () { return _doprnt (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_func__doprnt=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_func__doprnt=no fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_func__doprnt" >&5 echo "${ECHO_T}$ac_cv_func__doprnt" >&6; } if test $ac_cv_func__doprnt = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_DOPRNT 1 _ACEOF fi fi done for ac_func in getcwd gettimeofday memmove memset putenv select strcasecmp strchr strcspn strdup strncasecmp strrchr strspn strstr strcasestr do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. For example, HP-UX 11i declares gettimeofday. */ #define $ac_func innocuous_$ac_func /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $ac_func /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $ac_func (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$ac_func || defined __stub___$ac_func choke me #endif int main () { return $ac_func (); ; return 0; } _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then eval "$as_ac_var=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_var'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_var'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 _ACEOF fi done ############################################################################# # # Find out about Tcl/Tk and request substitutions # { echo "$as_me:$LINENO: checking tcl/tk version" >&5 echo $ECHO_N "checking tcl/tk version... $ECHO_C" >&6; } try_dirs="$TKGATE_LIBDIRS" for v in $TKGATE_TCLTK_VERSIONS; do alt_v=`echo $v | sed s/\\\\.//` for d in $TKGATE_LIBDIRS; do try_dirs="$try_dirs $d/tcl$v $d/tcl$alt_v" done done for d in $try_dirs; do if test -f $d/tclConfig.sh; then . $d/tclConfig.sh break fi done if test "X$TCL_VERSION" = "X"; then { { echo "$as_me:$LINENO: error: could not find tclConfig.sh" >&5 echo "$as_me: error: could not find tclConfig.sh" >&2;} { (exit 1); exit 1; }; } else v=$TCL_VERSION alt_v=`echo $v | sed s/\\\\.//` try_dirs="$TKGATE_LIBDIRS" for d in $TKGATE_LIBDIRS; do try_dirs="$try_dirs $d/tk$v $d/tk$alt_v $d/tcl$v $d/tcl$alt_v" done for d in $try_dirs; do if test -f $d/tkConfig.sh; then . $d/tkConfig.sh break fi done if test "X$TK_VERSION" = "X"; then { { echo "$as_me:$LINENO: error: could not find tkConfig.sh" >&5 echo "$as_me: error: could not find tkConfig.sh" >&2;} { (exit 1); exit 1; }; } else if test "X$TCL_VERSION" != "X$TK_VERSION"; then { { echo "$as_me:$LINENO: error: versions of tcl ($TCL_VERSION) and tk ($TK_VERSION) do not match." >&5 echo "$as_me: error: versions of tcl ($TCL_VERSION) and tk ($TK_VERSION) do not match." >&2;} { (exit 1); exit 1; }; } else TCLTK_VERSION=$TCL_VERSION TCL_LIB=$TCL_LIB_SPEC TCL_LPATH="" TCL_IPATH=$TCL_INCLUDE_SPEC TK_LIB=$TK_LIB_SPEC TK_LPATH="" TK_IPATH=$TK_INCLUDE_SPEC if test "X$TCL_IPATH" = "X"; then v=$TCLTK_VERSION alt_v=`echo $v | sed s/\\\\.//` ipath="" for d in $TKGATE_INCDIRS; do if test -f $d/'tcl'$v/'tcl'.h; then ipath=-I$d/'tcl'$v else if test -f $d/'tcl'$alt_v/'tcl'.h; then ipath=-I$d/'tcl'$alt_v else if test -f $d/'tcl'.h; then ipath=-I$d fi fi fi done TCL_IPATH=$ipath echo TCL_IPATH=$ipath fi if test "X$TK_IPATH" = "X"; then v=$TCLTK_VERSION alt_v=`echo $v | sed s/\\\\.//` ipath="" for d in $TKGATE_INCDIRS; do if test -f $d/'tk'$v/'tk'.h; then ipath=-I$d/'tk'$v else if test -f $d/'tk'$alt_v/'tk'.h; then ipath=-I$d/'tk'$alt_v else if test -f $d/'tk'.h; then ipath=-I$d fi fi fi done if test "X$ipath" = "X"; then v=$TCLTK_VERSION alt_v=`echo $v | sed s/\\\\.//` ipath="" for d in $TKGATE_INCDIRS; do if test -f $d/'tcl'$v/'tk'.h; then ipath=-I$d/'tcl'$v else if test -f $d/'tcl'$alt_v/'tk'.h; then ipath=-I$d/'tcl'$alt_v else if test -f $d/'tk'.h; then ipath=-I$d fi fi fi done fi TK_IPATH=$ipath fi if test "X$TCL_IPATH" = "X-I/usr/include"; then TCL_IPATH="" fi if test "X$TK_IPATH" = "X-I/usr/include"; then TK_IPATH="" fi fi fi fi { echo "$as_me:$LINENO: result: $TCLTK_VERSION" >&5 echo "${ECHO_T}$TCLTK_VERSION" >&6; } ############################################################################# # # Check for gecos field # { echo "$as_me:$LINENO: checking pw_gecos in struct pwd" >&5 echo $ECHO_N "checking pw_gecos in struct pwd... $ECHO_C" >&6; } if test "${tcl_cv_pwd_pw_gecos+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { struct passwd pwd; pwd.pw_gecos; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then tcl_cv_pwd_pw_gecos=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 tcl_cv_pwd_pw_gecos=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $tcl_cv_pwd_pw_gecos" >&5 echo "${ECHO_T}$tcl_cv_pwd_pw_gecos" >&6; } if test $tcl_cv_pwd_pw_gecos = yes; then cat >>confdefs.h <<\_ACEOF #define HAVE_PW_GECOS 1 _ACEOF else cat >>confdefs.h <<\_ACEOF #define HAVE_PW_GECOS 0 _ACEOF fi ############################################################################# # # Check for signal handler function # { echo "$as_me:$LINENO: checking how to set signal handlers" >&5 echo $ECHO_N "checking how to set signal handlers... $ECHO_C" >&6; } if test "${signal_ok+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { signal(0,0); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then signal_ok=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 signal_ok=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi if test "${sigset_ok+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include int main () { sigset(0,0); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then sigset_ok=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 sigset_ok=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi if test "$signal_ok" = "yes"; then cat >>confdefs.h <<\_ACEOF #define TKGATE_SIGSET 0 _ACEOF { echo "$as_me:$LINENO: result: signal()" >&5 echo "${ECHO_T}signal()" >&6; } else if test "$sigset_ok" = "yes"; then cat >>confdefs.h <<\_ACEOF #define TKGATE_SIGSET 1 _ACEOF { echo "$as_me:$LINENO: result: sigset()" >&5 echo "${ECHO_T}sigset()" >&6; } else { { echo "$as_me:$LINENO: error: I can't figure out how to set signal handlers." >&5 echo "$as_me: error: I can't figure out how to set signal handlers." >&2;} { (exit 1); exit 1; }; }; fi fi ############################################################################# # # Check for word size and Endianess # { echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5 echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6; } if test "${ac_cv_c_bigendian+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # See if sys/param.h defines the BYTE_ORDER macro. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { #if ! (defined BYTE_ORDER && defined BIG_ENDIAN && defined LITTLE_ENDIAN \ && BYTE_ORDER && BIG_ENDIAN && LITTLE_ENDIAN) bogus endian macros #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then # It does; now see whether it defined to BIG_ENDIAN or not. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { #if BYTE_ORDER != BIG_ENDIAN not big endian #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_bigendian=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_bigendian=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 # It does not; compile a test program. if test "$cross_compiling" = yes; then # try to guess the endianness by grepping values into an object file ac_cv_c_bigendian=unknown cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ short int ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; short int ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; } short int ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; short int ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; } int main () { _ascii (); _ebcdic (); ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then ac_cv_c_bigendian=yes fi if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then if test "$ac_cv_c_bigendian" = unknown; then ac_cv_c_bigendian=no else # finding both strings is unlikely to happen, but who knows? ac_cv_c_bigendian=unknown fi fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { /* Are we little or big endian? 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See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Per Bothner . # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # This script attempts to guess a canonical system name similar to # config.sub. If it succeeds, it prints the system name on stdout, and # exits with 0. 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But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit 0 ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit 0 ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit 0 ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit 0 ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit 0 ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit 0 ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit 0 ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit 0 ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c \ && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ && exit 0 echo mips-mips-riscos${UNAME_RELEASE} exit 0 ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit 0 ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit 0 ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit 0 ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit 0 ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit 0 ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit 0 ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit 0 ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit 0 ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit 0 ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit 0 ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit 0 ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit 0 ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo rs6000-ibm-aix3.2.5 elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit 0 ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:*:*) echo rs6000-ibm-aix exit 0 ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit 0 ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit 0 ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit 0 ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit 0 ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit 0 ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit 0 ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then # avoid double evaluation of $set_cc_for_build test -n "$CC_FOR_BUILD" || eval $set_cc_for_build if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit 0 ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit 0 ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo unknown-hitachi-hiuxwe2 exit 0 ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit 0 ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit 0 ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit 0 ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit 0 ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit 0 ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit 0 ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit 0 ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit 0 ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit 0 ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit 0 ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit 0 ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; *:UNICOS/mp:*:*) echo nv1-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit 0 ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit 0 ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:FreeBSD:*:*|*:GNU/FreeBSD:*:*) # Determine whether the default compiler uses glibc. eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #if __GLIBC__ >= 2 LIBC=gnu #else LIBC= #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` # GNU/FreeBSD systems have a "k" prefix to indicate we are using # FreeBSD's kernel, but not the complete OS. case ${LIBC} in gnu) kernel_only='k' ;; esac echo ${UNAME_MACHINE}-unknown-${kernel_only}freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`${LIBC:+-$LIBC} exit 0 ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit 0 ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit 0 ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit 0 ;; x86:Interix*:[34]*) echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//' exit 0 ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit 0 ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix exit 0 ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit 0 ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit 0 ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; *:GNU:*:*) echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit 0 ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit 0 ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit 0 ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit 0 ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit 0 ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit 0 ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit 0 ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit 0 ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit 0 ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit 0 ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit 0 ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" exit 0 ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit 0 ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #ifdef __INTEL_COMPILER LIBC=gnu #else LIBC=gnuaout #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit 0 ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit 0 ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit 0 ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit 0 ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit 0 ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit 0 ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit 0 ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit 0 ;; i*86:*:5:[78]*) case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit 0 ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit 0 ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit 0 ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit 0 ;; paragon:*:*:*) echo i860-intel-osf1 exit 0 ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit 0 ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit 0 ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv exit 0 ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix exit 0 ;; M68*:*:R3V[567]*:*) test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; 3[34]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4.3${OS_REL} && exit 0 /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4 && exit 0 ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit 0 ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit 0 ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit 0 ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit 0 ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit 0 ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 exit 0 ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit 0 ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit 0 ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit 0 ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit 0 ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit 0 ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit 0 ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit 0 ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit 0 ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit 0 ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit 0 ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit 0 ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} exit 0 ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Darwin:*:*) case `uname -p` in *86) UNAME_PROCESSOR=i686 ;; powerpc) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit 0 ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} exit 0 ;; *:QNX:*:4*) echo i386-pc-qnx exit 0 ;; NSR-[DGKLNPTVW]:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit 0 ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit 0 ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit 0 ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit 0 ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit 0 ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit 0 ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit 0 ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit 0 ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit 0 ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit 0 ;; *:ITS:*:*) echo pdp10-unknown-its exit 0 ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} exit 0 ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 eval $set_cc_for_build cat >$dummy.c < # include #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && exit 0 # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit 0 ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; c34*) echo c34-convex-bsd exit 0 ;; c38*) echo c38-convex-bsd exit 0 ;; c4*) echo c4-convex-bsd exit 0 ;; esac fi cat >&2 < in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: tkgate-2.0-b10/config.sub000555 001751 001751 00000073153 11117364051 015777 0ustar00hansenhansen000000 000000 #! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003 Free Software Foundation, Inc. timestamp='2003-07-04' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, # Boston, MA 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit 0;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | kfreebsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. We also ### recognize some manufacturers as not being operating systems, so we ### can provide default operating systems below. case $os in -sun*os*) # Prevent following clause from handling this invalid input. ;; -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -apple | -axis) os= basic_machine=$1 ;; -sim | -cisco | -oki | -wec | -winbond) os= basic_machine=$1 ;; -scout) ;; -wrs) os=-vxworks basic_machine=$1 ;; -chorusos*) os=-chorusos basic_machine=$1 ;; -chorusrdb) os=-chorusrdb basic_machine=$1 ;; -hiux*) os=-hiuxwe2 ;; -sco5) os=-sco3.2v5 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco4) os=-sco3.2v4 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2.[4-9]*) os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2v[4-9]*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco*) os=-sco3.2v2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -udk*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -isc) os=-isc2.2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -clix*) basic_machine=clipper-intergraph ;; -isc*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -lynx*) os=-lynxos ;; -ptx*) basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` ;; -windowsnt*) os=`echo $os | sed -e 's/windowsnt/winnt/'` ;; -psos*) os=-psos ;; -mint | -mint[0-9]*) basic_machine=m68k-atari os=-mint ;; esac # Decode aliases for certain CPU-COMPANY combinations. case $basic_machine in # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. 1750a | 580 \ | a29k \ | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | ip2k \ | m32r | m68000 | m68k | m88k | mcore \ | mips | mipsbe | mipseb | mipsel | mipsle \ | mips16 \ | mips64 | mips64el \ | mips64vr | mips64vrel \ | mips64orion | mips64orionel \ | mips64vr4100 | mips64vr4100el \ | mips64vr4300 | mips64vr4300el \ | mips64vr5000 | mips64vr5000el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ | mipsisa64 | mipsisa64el \ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ | mn10200 | mn10300 \ | msp430 \ | ns16k | ns32k \ | openrisc | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ | pyramid \ | sh | sh[1234] | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ | sh64 | sh64le \ | sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \ | strongarm \ | tahoe | thumb | tic4x | tic80 | tron \ | v850 | v850e \ | we32k \ | x86 | xscale | xstormy16 | xtensa \ | z8k) basic_machine=$basic_machine-unknown ;; m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | amd64-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* \ | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ | clipper-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* \ | m32r-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | mcore-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ | mips64vr-* | mips64vrel-* \ | mips64orion-* | mips64orionel-* \ | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | msp430-* \ | none-* | np1-* | nv1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \ | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \ | tahoe-* | thumb-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tron-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \ | xtensa-* \ | ymp-* \ | z8k-*) ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; c90) basic_machine=c90-cray os=-unicos ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; crds | unos) basic_machine=m68k-crds ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. Should this be sysv3.2? i*86v32) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv32 ;; i*86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv4 ;; i*86v) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv ;; i*86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-solaris2 ;; i386mach) basic_machine=i386-mach os=-mach ;; i386-vsta | vsta) basic_machine=i386-unknown os=-vsta ;; iris | iris4d) basic_machine=mips-sgi case $os in -irix*) ;; *) os=-irix4 ;; esac ;; isi68 | isi) basic_machine=m68k-isi os=-sysv ;; m88k-omron*) basic_machine=m88k-omron ;; magnum | m3230) basic_machine=mips-mips os=-sysv ;; merlin) basic_machine=ns32k-utek os=-sysv ;; mingw32) basic_machine=i386-pc os=-mingw32 ;; miniframe) basic_machine=m68000-convergent ;; *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) basic_machine=m68k-atari os=-mint ;; mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; mips3*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown ;; mmix*) basic_machine=mmix-knuth os=-mmixware ;; monitor) basic_machine=m68k-rom68k os=-coff ;; morphos) basic_machine=powerpc-unknown os=-morphos ;; msdos) basic_machine=i386-pc os=-msdos ;; mvs) basic_machine=i370-ibm os=-mvs ;; ncr3000) basic_machine=i486-ncr os=-sysv4 ;; netbsd386) basic_machine=i386-unknown os=-netbsd ;; netwinder) basic_machine=armv4l-rebel os=-linux ;; news | news700 | news800 | news900) basic_machine=m68k-sony os=-newsos ;; news1000) basic_machine=m68030-sony os=-newsos ;; news-3600 | risc-news) basic_machine=mips-sony os=-newsos ;; necv70) basic_machine=v70-nec os=-sysv ;; next | m*-next ) basic_machine=m68k-next case $os in -nextstep* ) ;; -ns2*) os=-nextstep2 ;; *) os=-nextstep3 ;; esac ;; nh3000) basic_machine=m68k-harris os=-cxux ;; nh[45]000) basic_machine=m88k-harris os=-cxux ;; nindy960) basic_machine=i960-intel os=-nindy ;; mon960) basic_machine=i960-intel os=-mon960 ;; nonstopux) basic_machine=mips-compaq os=-nonstopux ;; np1) basic_machine=np1-gould ;; nv1) basic_machine=nv1-cray os=-unicosmp ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; or32 | or32-*) basic_machine=or32-unknown os=-coff ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=alphaev5-cray os=-unicos ;; t90) basic_machine=t90-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tic55x | c55x*) basic_machine=tic55x-unknown os=-coff ;; tic6x | c6x*) basic_machine=tic6x-unknown os=-coff ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; toad1) basic_machine=pdp10-xkl os=-tops20 ;; tower | tower-32) basic_machine=m68k-ncr ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. It is in # some cases the only manufacturer, in others, it is the most popular. w89k) basic_machine=hppa1.1-winbond ;; op50n) basic_machine=hppa1.1-oki ;; op60c) basic_machine=hppa1.1-oki ;; romp) basic_machine=romp-ibm ;; rs6000) basic_machine=rs6000-ibm ;; vax) basic_machine=vax-dec ;; pdp10) # there are many clones, so DEC is not a safe bet basic_machine=pdp10-unknown ;; pdp11) basic_machine=pdp11-dec ;; we32k) basic_machine=we32k-att ;; sh3 | sh4 | sh[34]eb | sh[1234]le | sh[23]ele) basic_machine=sh-unknown ;; sh64) basic_machine=sh64-unknown ;; sparc | sparcv9 | sparcv9b) basic_machine=sparc-sun ;; cydra) basic_machine=cydra-cydrome ;; orion) basic_machine=orion-highlevel ;; orion105) basic_machine=clipper-highlevel ;; mac | mpw | mac-mpw) basic_machine=m68k-apple ;; pmac | pmac-mpw) basic_machine=powerpc-apple ;; *-unknown) # Make sure to match an already-canonicalized machine name. ;; *) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; esac # Here we canonicalize certain aliases for manufacturers. case $basic_machine in *-digital*) basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` ;; *-commodore*) basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` ;; *) ;; esac # Decode manufacturer-specific aliases for certain operating systems. if [ x"$os" != x"" ] then case $os in # First match some system type aliases # that might get confused with valid system types. # -solaris* is a basic system type, with this one exception. -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; -solaris) os=-solaris2 ;; -svr4*) os=-sysv4 ;; -unixware*) os=-sysv4.2uw ;; -gnu/linux*) os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` ;; # First accept the basic system types. # The portable systems comes first. # Each alternative MUST END IN A *, to match a version number. # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* \ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -netbsd* | -openbsd* | -kfreebsd* | -freebsd* | -riscix* \ | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* \ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | -mingw32* | -linux-gnu* | -uxpv* | -beos* | -mpeix* | -udk* \ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) case $basic_machine in x86-* | i*86-*) ;; *) os=-nto$os ;; esac ;; -nto-qnx*) ;; -nto*) os=`echo $os | sed -e 's|nto|nto-qnx|'` ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) os=`echo $os | sed -e 's|mac|macos|'` ;; -linux*) os=`echo $os | sed -e 's|linux|linux-gnu|'` ;; -sunos5*) os=`echo $os | sed -e 's|sunos5|solaris2|'` ;; -sunos6*) os=`echo $os | sed -e 's|sunos6|solaris3|'` ;; -opened*) os=-openedition ;; -wince*) os=-wince ;; -osfrose*) os=-osfrose ;; -osf*) os=-osf ;; -utek*) os=-bsd ;; -dynix*) os=-bsd ;; -acis*) os=-aos ;; -atheos*) os=-atheos ;; -386bsd) os=-bsd ;; -ctix* | -uts*) os=-sysv ;; -nova*) os=-rtmk-nova ;; -ns2 ) os=-nextstep2 ;; -nsk*) os=-nsk ;; # Preserve the version number of sinix5. -sinix5.*) os=`echo $os | sed -e 's|sinix|sysv|'` ;; -sinix*) os=-sysv4 ;; -triton*) os=-sysv3 ;; -oss*) os=-sysv3 ;; -svr4) os=-sysv4 ;; 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See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA # 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. DEPDIR directory where to store dependencies. depfile Dependency file to output. tmpdepfile Temporary file to use when outputing dependencies. libtool Whether libtool is used (yes/no). Report bugs to . EOF exit $? ;; -v | --v*) echo "depcomp $scriptversion" exit $? ;; esac if test -z "$depmode" || test -z "$source" || test -z "$object"; then echo "depcomp: Variables source, object and depmode must be set" 1>&2 exit 1 fi # Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. depfile=${depfile-`echo "$object" | sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} rm -f "$tmpdepfile" # Some modes work just like other modes, but use different flags. We # parameterize here, but still list the modes in the big case below, # to make depend.m4 easier to write. Note that we *cannot* use a case # here, because this file can only contain one case statement. if test "$depmode" = hp; then # HP compiler uses -M and no extra arg. gccflag=-M depmode=gcc fi if test "$depmode" = dashXmstdout; then # This is just like dashmstdout with a different argument. dashmflag=-xM depmode=dashmstdout fi case "$depmode" in gcc3) ## gcc 3 implements dependency tracking that does exactly what ## we want. Yay! Note: for some reason libtool 1.4 doesn't like ## it if -MD -MP comes after the -MF stuff. Hmm. "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi mv "$tmpdepfile" "$depfile" ;; gcc) ## There are various ways to get dependency output from gcc. Here's ## why we pick this rather obscure method: ## - Don't want to use -MD because we'd like the dependencies to end ## up in a subdir. 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"$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile" rm -f "$tmpdepfile" ;; none) exec "$@" ;; *) echo "Unknown depmode $depmode" 1>&2 exit 1 ;; esac exit 0 # Local Variables: # mode: shell-script # sh-indentation: 2 # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: tkgate-2.0-b10/install-sh000555 001751 001751 00000012671 10512610164 016013 0ustar00hansenhansen000000 000000 #!/bin/sh # # install - install a program, script, or datafile # This comes from X11R5 (mit/util/scripts/install.sh). # # Copyright 1991 by the Massachusetts Institute of Technology # # Permission to use, copy, modify, distribute, and sell this software and its # documentation for any purpose is hereby granted without fee, provided that # the above copyright notice appear in all copies and that both that # copyright notice and this permission notice appear in supporting # documentation, and that the name of M.I.T. not be used in advertising or # publicity pertaining to distribution of the software without specific, # written prior permission. M.I.T. makes no representations about the # suitability of this software for any purpose. It is provided "as is" # without express or implied warranty. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. 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If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $instcmd $src $dsttmp" command. if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else :;fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else :;fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else :;fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else :;fi && # Now rename the file to the real destination. $doit $rmcmd -f $dstdir/$dstfile && $doit $mvcmd $dsttmp $dstdir/$dstfile fi && exit 0 tkgate-2.0-b10/src000777 001751 001751 00000000000 11257536666 014543 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/ltmain.sh000444 001751 001751 00000607227 11135521057 015642 0ustar00hansenhansen000000 000000 # ltmain.sh - Provide generalized library-building support services. # NOTE: Changing this file will not affect anything until you rerun configure. # # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, # 2007 Free Software Foundation, Inc. # Originally by Gordon Matzigkeit , 1996 # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. basename="s,^.*/,,g" # Work around backward compatibility issue on IRIX 6.5. On IRIX 6.4+, sh # is ksh but when the shell is invoked as "sh" and the current value of # the _XPG environment variable is not equal to 1 (one), the special # positional parameter $0, within a function call, is the name of the # function. progpath="$0" # The name of this program: progname=`echo "$progpath" | $SED $basename` modename="$progname" # Global variables: EXIT_SUCCESS=0 EXIT_FAILURE=1 PROGRAM=ltmain.sh PACKAGE=libtool VERSION=1.5.24 TIMESTAMP=" (1.1220.2.455 2007/06/24 02:13:29)" # Be Bourne compatible (taken from Autoconf:_AS_BOURNE_COMPATIBLE). if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then emulate sh NULLCMD=: # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in *posix*) set -o posix;; esac fi BIN_SH=xpg4; export BIN_SH # for Tru64 DUALCASE=1; export DUALCASE # for MKS sh # Check that we have a working $echo. if test "X$1" = X--no-reexec; then # Discard the --no-reexec flag, and continue. shift elif test "X$1" = X--fallback-echo; then # Avoid inline document here, it may be left over : elif test "X`($echo '\t') 2>/dev/null`" = 'X\t'; then # Yippee, $echo works! : else # Restart under the correct shell, and then maybe $echo will work. exec $SHELL "$progpath" --no-reexec ${1+"$@"} fi if test "X$1" = X--fallback-echo; then # used as fallback echo shift cat <&2 $echo "Fatal configuration error. See the $PACKAGE docs for more information." 1>&2 exit $EXIT_FAILURE fi # Global variables. mode=$default_mode nonopt= prev= prevopt= run= show="$echo" show_help= execute_dlfiles= duplicate_deps=no preserve_args= lo2o="s/\\.lo\$/.${objext}/" o2lo="s/\\.${objext}\$/.lo/" extracted_archives= extracted_serial=0 ##################################### # Shell function definitions: # This seems to be the best place for them # func_mktempdir [string] # Make a temporary directory that won't clash with other running # libtool processes, and avoids race conditions if possible. If # given, STRING is the basename for that directory. func_mktempdir () { my_template="${TMPDIR-/tmp}/${1-$progname}" if test "$run" = ":"; then # Return a directory name, but don't create it in dry-run mode my_tmpdir="${my_template}-$$" else # If mktemp works, use that first and foremost my_tmpdir=`mktemp -d "${my_template}-XXXXXXXX" 2>/dev/null` if test ! -d "$my_tmpdir"; then # Failing that, at least try and use $RANDOM to avoid a race my_tmpdir="${my_template}-${RANDOM-0}$$" save_mktempdir_umask=`umask` umask 0077 $mkdir "$my_tmpdir" umask $save_mktempdir_umask fi # If we're not in dry-run mode, bomb out on failure test -d "$my_tmpdir" || { $echo "cannot create temporary directory \`$my_tmpdir'" 1>&2 exit $EXIT_FAILURE } fi $echo "X$my_tmpdir" | $Xsed } # func_win32_libid arg # return the library type of file 'arg' # # Need a lot of goo to handle *both* DLLs and import libs # Has to be a shell function in order to 'eat' the argument # that is supplied when $file_magic_command is called. func_win32_libid () { win32_libid_type="unknown" win32_fileres=`file -L $1 2>/dev/null` case $win32_fileres in *ar\ archive\ import\ library*) # definitely import win32_libid_type="x86 archive import" ;; *ar\ archive*) # could be an import, or static if eval $OBJDUMP -f $1 | $SED -e '10q' 2>/dev/null | \ $EGREP -e 'file format pe-i386(.*architecture: i386)?' >/dev/null ; then win32_nmres=`eval $NM -f posix -A $1 | \ $SED -n -e '1,100{ / I /{ s,.*,import, p q } }'` case $win32_nmres in import*) win32_libid_type="x86 archive import";; *) win32_libid_type="x86 archive static";; esac fi ;; *DLL*) win32_libid_type="x86 DLL" ;; *executable*) # but shell scripts are "executable" too... case $win32_fileres in *MS\ Windows\ PE\ Intel*) win32_libid_type="x86 DLL" ;; esac ;; esac $echo $win32_libid_type } # func_infer_tag arg # Infer tagged configuration to use if any are available and # if one wasn't chosen via the "--tag" command line option. # Only attempt this if the compiler in the base compile # command doesn't match the default compiler. # arg is usually of the form 'gcc ...' func_infer_tag () { # FreeBSD-specific: where we install compilers with non-standard names tag_compilers_CC="*cc cc* *gcc gcc*" tag_compilers_CXX="*c++ c++* *g++ g++*" base_compiler=`set -- "$@"; echo $1` # If $tagname isn't set, then try to infer if the default "CC" tag applies if test -z "$tagname"; then for zp in $tag_compilers_CC; do case $base_compiler in $zp) tagname="CC"; break;; esac done fi if test -n "$available_tags" && test -z "$tagname"; then CC_quoted= for arg in $CC; do case $arg in *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") arg="\"$arg\"" ;; esac CC_quoted="$CC_quoted $arg" done case $@ in # Blanks in the command may have been stripped by the calling shell, # but not from the CC environment variable when configure was run. " $CC "* | "$CC "* | " `$echo $CC` "* | "`$echo $CC` "* | " $CC_quoted"* | "$CC_quoted "* | " `$echo $CC_quoted` "* | "`$echo $CC_quoted` "*) ;; # Blanks at the start of $base_compile will cause this to fail # if we don't check for them as well. *) for z in $available_tags; do if grep "^# ### BEGIN LIBTOOL TAG CONFIG: $z$" < "$progpath" > /dev/null; then # Evaluate the configuration. eval "`${SED} -n -e '/^# ### BEGIN LIBTOOL TAG CONFIG: '$z'$/,/^# ### END LIBTOOL TAG CONFIG: '$z'$/p' < $progpath`" CC_quoted= for arg in $CC; do # Double-quote args containing other shell metacharacters. case $arg in *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") arg="\"$arg\"" ;; esac CC_quoted="$CC_quoted $arg" done case "$@ " in " $CC "* | "$CC "* | " `$echo $CC` "* | "`$echo $CC` "* | " $CC_quoted"* | "$CC_quoted "* | " `$echo $CC_quoted` "* | "`$echo $CC_quoted` "*) # The compiler in the base compile command matches # the one in the tagged configuration. # Assume this is the tagged configuration we want. tagname=$z break ;; esac # FreeBSD-specific: try compilers based on inferred tag if test -z "$tagname"; then eval "tag_compilers=\$tag_compilers_${z}" if test -n "$tag_compilers"; then for zp in $tag_compilers; do case $base_compiler in $zp) tagname=$z; break;; esac done if test -n "$tagname"; then break fi fi fi fi done # If $tagname still isn't set, then no tagged configuration # was found and let the user know that the "--tag" command # line option must be used. if test -z "$tagname"; then $echo "$modename: unable to infer tagged configuration" $echo "$modename: specify a tag with \`--tag'" 1>&2 exit $EXIT_FAILURE # else # $echo "$modename: using $tagname tagged configuration" fi ;; esac fi } # func_extract_an_archive dir oldlib func_extract_an_archive () { f_ex_an_ar_dir="$1"; shift f_ex_an_ar_oldlib="$1" $show "(cd $f_ex_an_ar_dir && $AR x $f_ex_an_ar_oldlib)" $run eval "(cd \$f_ex_an_ar_dir && $AR x \$f_ex_an_ar_oldlib)" || exit $? if ($AR t "$f_ex_an_ar_oldlib" | sort | sort -uc >/dev/null 2>&1); then : else $echo "$modename: ERROR: object name conflicts: $f_ex_an_ar_dir/$f_ex_an_ar_oldlib" 1>&2 exit $EXIT_FAILURE fi } # func_extract_archives gentop oldlib ... func_extract_archives () { my_gentop="$1"; shift my_oldlibs=${1+"$@"} my_oldobjs="" my_xlib="" my_xabs="" my_xdir="" my_status="" $show "${rm}r $my_gentop" $run ${rm}r "$my_gentop" $show "$mkdir $my_gentop" $run $mkdir "$my_gentop" my_status=$? if test "$my_status" -ne 0 && test ! -d "$my_gentop"; then exit $my_status fi for my_xlib in $my_oldlibs; do # Extract the objects. case $my_xlib in [\\/]* | [A-Za-z]:[\\/]*) my_xabs="$my_xlib" ;; *) my_xabs=`pwd`"/$my_xlib" ;; esac my_xlib=`$echo "X$my_xlib" | $Xsed -e 's%^.*/%%'` my_xlib_u=$my_xlib while :; do case " $extracted_archives " in *" $my_xlib_u "*) extracted_serial=`expr $extracted_serial + 1` my_xlib_u=lt$extracted_serial-$my_xlib ;; *) break ;; esac done extracted_archives="$extracted_archives $my_xlib_u" my_xdir="$my_gentop/$my_xlib_u" $show "${rm}r $my_xdir" $run ${rm}r "$my_xdir" $show "$mkdir $my_xdir" $run $mkdir "$my_xdir" exit_status=$? if test "$exit_status" -ne 0 && test ! -d "$my_xdir"; then exit $exit_status fi case $host in *-darwin*) $show "Extracting $my_xabs" # Do not bother doing anything if just a dry run if test -z "$run"; then darwin_orig_dir=`pwd` cd $my_xdir || exit $? darwin_archive=$my_xabs darwin_curdir=`pwd` darwin_base_archive=`$echo "X$darwin_archive" | $Xsed -e 's%^.*/%%'` darwin_arches=`lipo -info "$darwin_archive" 2>/dev/null | $EGREP Architectures 2>/dev/null` if test -n "$darwin_arches"; then darwin_arches=`echo "$darwin_arches" | $SED -e 's/.*are://'` darwin_arch= $show "$darwin_base_archive has multiple architectures $darwin_arches" for darwin_arch in $darwin_arches ; do mkdir -p "unfat-$$/${darwin_base_archive}-${darwin_arch}" lipo -thin $darwin_arch -output "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" "${darwin_archive}" cd "unfat-$$/${darwin_base_archive}-${darwin_arch}" func_extract_an_archive "`pwd`" "${darwin_base_archive}" cd "$darwin_curdir" $rm "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" done # $darwin_arches ## Okay now we have a bunch of thin objects, gotta fatten them up :) darwin_filelist=`find unfat-$$ -type f -name \*.o -print -o -name \*.lo -print| xargs basename | sort -u | $NL2SP` darwin_file= darwin_files= for darwin_file in $darwin_filelist; do darwin_files=`find unfat-$$ -name $darwin_file -print | $NL2SP` lipo -create -output "$darwin_file" $darwin_files done # $darwin_filelist ${rm}r unfat-$$ cd "$darwin_orig_dir" else cd "$darwin_orig_dir" func_extract_an_archive "$my_xdir" "$my_xabs" fi # $darwin_arches fi # $run ;; *) func_extract_an_archive "$my_xdir" "$my_xabs" ;; esac my_oldobjs="$my_oldobjs "`find $my_xdir -name \*.$objext -print -o -name \*.lo -print | $NL2SP` done func_extract_archives_result="$my_oldobjs" } # End of Shell function definitions ##################################### # Darwin sucks eval std_shrext=\"$shrext_cmds\" disable_libs=no # Parse our command line options once, thoroughly. while test "$#" -gt 0 do arg="$1" shift case $arg in -*=*) optarg=`$echo "X$arg" | $Xsed -e 's/[-_a-zA-Z0-9]*=//'` ;; *) optarg= ;; esac # If the previous option needs an argument, assign it. if test -n "$prev"; then case $prev in execute_dlfiles) execute_dlfiles="$execute_dlfiles $arg" ;; tag) tagname="$arg" preserve_args="${preserve_args}=$arg" # Check whether tagname contains only valid characters case $tagname in *[!-_A-Za-z0-9,/]*) $echo "$progname: invalid tag name: $tagname" 1>&2 exit $EXIT_FAILURE ;; esac case $tagname in CC) # Don't test for the "default" C tag, as we know, it's there, but # not specially marked. ;; *) if grep "^# ### BEGIN LIBTOOL TAG CONFIG: $tagname$" < "$progpath" > /dev/null; then taglist="$taglist $tagname" # Evaluate the configuration. eval "`${SED} -n -e '/^# ### BEGIN LIBTOOL TAG CONFIG: '$tagname'$/,/^# ### END LIBTOOL TAG CONFIG: '$tagname'$/p' < $progpath`" else $echo "$progname: ignoring unknown tag $tagname" 1>&2 fi ;; esac ;; *) eval "$prev=\$arg" ;; esac prev= prevopt= continue fi # Have we seen a non-optional argument yet? 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then case " $predeps $postdeps " in *" $deplib "*) if (${SED} -e '2q' $lib | grep "^# Generated by .*$PACKAGE") >/dev/null 2>&1; then library_names= old_library= case $lib in */* | *\\*) . $lib ;; *) . ./$lib ;; esac for l in $old_library $library_names; do ll="$l" done if test "X$ll" = "X$old_library" ; then # only static version available found=no ladir=`$echo "X$lib" | $Xsed -e 's%/[^/]*$%%'` test "X$ladir" = "X$lib" && ladir="." lib=$ladir/$old_library if test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else deplibs="$deplib $deplibs" test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" fi continue fi fi ;; *) ;; esac fi fi ;; # -l -L*) case $linkmode in lib) deplibs="$deplib $deplibs" test "$pass" = conv && continue newdependency_libs="$deplib $newdependency_libs" newlib_search_path="$newlib_search_path "`$echo "X$deplib" | $Xsed -e 's/^-L//'` ;; prog) if test "$pass" = conv; then deplibs="$deplib $deplibs" continue fi if test "$pass" = scan; then deplibs="$deplib $deplibs" else compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" fi newlib_search_path="$newlib_search_path "`$echo "X$deplib" | $Xsed -e 's/^-L//'` ;; *) $echo "$modename: warning: \`-L' is ignored for archives/objects" 1>&2 ;; esac # linkmode continue ;; # -L -R*) if test "$pass" = link; then dir=`$echo "X$deplib" | $Xsed -e 's/^-R//'` # Make sure the xrpath contains only unique directories. case "$xrpath " in *" $dir "*) ;; *) xrpath="$xrpath $dir" ;; esac fi deplibs="$deplib $deplibs" continue ;; *.la) lib="$deplib" ;; *.$libext) if test "$pass" = conv; then deplibs="$deplib $deplibs" continue fi case $linkmode in lib) valid_a_lib=no case $deplibs_check_method in match_pattern*) set dummy $deplibs_check_method match_pattern_regex=`expr "$deplibs_check_method" : "$2 \(.*\)"` if eval $echo \"$deplib\" 2>/dev/null \ | $SED 10q \ | $EGREP "$match_pattern_regex" > /dev/null; then valid_a_lib=yes fi ;; pass_all) valid_a_lib=yes ;; esac if test "$valid_a_lib" != yes; then $echo $echo "*** Warning: Trying to link with static lib archive $deplib." $echo "*** I have the capability to make that library automatically link in when" $echo "*** you link to this library. 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then $run eval '$EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T' $run eval '$mv "$nlist"T "$nlist"' fi if test -n "$export_symbols_regex"; then $run eval '$EGREP -e "$export_symbols_regex" "$nlist" > "$nlist"T' $run eval '$mv "$nlist"T "$nlist"' fi # Prepare the list of exported symbols if test -z "$export_symbols"; then export_symbols="$output_objdir/$outputname.exp" $run $rm $export_symbols $run eval "${SED} -n -e '/^: @PROGRAM@ $/d' -e 's/^.* \(.*\)$/\1/p' "'< "$nlist" > "$export_symbols"' case $host in *cygwin* | *mingw* ) $run eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' $run eval 'cat "$export_symbols" >> "$output_objdir/$outputname.def"' ;; esac else $run eval "${SED} -e 's/\([].[*^$]\)/\\\\\1/g' -e 's/^/ /' -e 's/$/$/'"' < "$export_symbols" > "$output_objdir/$outputname.exp"' $run eval 'grep -f "$output_objdir/$outputname.exp" < "$nlist" > "$nlist"T' $run eval 'mv "$nlist"T "$nlist"' case $host in *cygwin* | *mingw* ) $run eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' $run eval 'cat "$nlist" >> "$output_objdir/$outputname.def"' ;; esac fi fi for arg in $dlprefiles; do $show "extracting global C symbols from \`$arg'" name=`$echo "$arg" | ${SED} -e 's%^.*/%%'` $run eval '$echo ": $name " >> "$nlist"' $run eval "$NM $arg | $global_symbol_pipe >> '$nlist'" done if test -z "$run"; then # Make sure we have at least an empty file. test -f "$nlist" || : > "$nlist" if test -n "$exclude_expsyms"; then $EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T $mv "$nlist"T "$nlist" fi # Try sorting and uniquifying the output. if grep -v "^: " < "$nlist" | if sort -k 3 /dev/null 2>&1; then sort -k 3 else sort +2 fi | uniq > "$nlist"S; then : else grep -v "^: " < "$nlist" > "$nlist"S fi if test -f "$nlist"S; then eval "$global_symbol_to_cdecl"' < "$nlist"S >> "$output_objdir/$dlsyms"' else $echo '/* NONE */' >> "$output_objdir/$dlsyms" fi $echo >> "$output_objdir/$dlsyms" "\ #undef lt_preloaded_symbols #if defined (__STDC__) && __STDC__ # define lt_ptr void * #else # define lt_ptr char * # define const #endif /* The mapping between symbol names and symbols. */ " case $host in *cygwin* | *mingw* ) $echo >> "$output_objdir/$dlsyms" "\ /* DATA imports from DLLs on WIN32 can't be const, because runtime relocations are performed -- see ld's documentation on pseudo-relocs */ struct { " ;; * ) $echo >> "$output_objdir/$dlsyms" "\ const struct { " ;; esac $echo >> "$output_objdir/$dlsyms" "\ const char *name; lt_ptr address; } lt_preloaded_symbols[] = {\ " eval "$global_symbol_to_c_name_address" < "$nlist" >> "$output_objdir/$dlsyms" $echo >> "$output_objdir/$dlsyms" "\ {0, (lt_ptr) 0} }; /* This works around a problem in FreeBSD linker */ #ifdef FREEBSD_WORKAROUND static const void *lt_preloaded_setup() { return lt_preloaded_symbols; } #endif #ifdef __cplusplus } #endif\ " fi pic_flag_for_symtable= case $host in # compiling the symbol table file with pic_flag works around # a FreeBSD bug that causes programs to crash when -lm is # linked before any other PIC object. But we must not use # pic_flag when linking with -static. The problem exists in # FreeBSD 2.2.6 and is fixed in FreeBSD 3.1. *-*-freebsd2*|*-*-freebsd3.0*|*-*-freebsdelf3.0*) case "$compile_command " in *" -static "*) ;; *) pic_flag_for_symtable=" $pic_flag -DFREEBSD_WORKAROUND";; esac;; *-*-hpux*) case "$compile_command " in *" -static "*) ;; *) pic_flag_for_symtable=" $pic_flag";; esac esac # Now compile the dynamic symbol file. $show "(cd $output_objdir && $LTCC $LTCFLAGS -c$no_builtin_flag$pic_flag_for_symtable \"$dlsyms\")" $run eval '(cd $output_objdir && $LTCC $LTCFLAGS -c$no_builtin_flag$pic_flag_for_symtable "$dlsyms")' || exit $? # Clean up the generated files. $show "$rm $output_objdir/$dlsyms $nlist ${nlist}S ${nlist}T" $run $rm "$output_objdir/$dlsyms" "$nlist" "${nlist}S" "${nlist}T" # Transform the symbol file into the correct name. case $host in *cygwin* | *mingw* ) if test -f "$output_objdir/${outputname}.def" ; then compile_command=`$echo "X$compile_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}.def $output_objdir/${outputname}S.${objext}%" | $NL2SP` finalize_command=`$echo "X$finalize_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}.def $output_objdir/${outputname}S.${objext}%" | $NL2SP` else compile_command=`$echo "X$compile_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}S.${objext}%" | $NL2SP` finalize_command=`$echo "X$finalize_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}S.${objext}%" | $NL2SP` fi ;; * ) compile_command=`$echo "X$compile_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}S.${objext}%" | $NL2SP` finalize_command=`$echo "X$finalize_command" | $SP2NL | $Xsed -e "s%@SYMFILE@%$output_objdir/${outputname}S.${objext}%" | $NL2SP` ;; esac ;; *-*-freebsd*) # FreeBSD doesn't need this... ;; *) $echo "$modename: unknown suffix for \`$dlsyms'" 1>&2 exit $EXIT_FAILURE ;; esac else # We keep going just in case the user didn't refer to # lt_preloaded_symbols. The linker will fail if global_symbol_pipe # really was required. # Nullify the symbol file. compile_command=`$echo "X$compile_command" | $SP2NL | $Xsed -e "s% @SYMFILE@%%" | $NL2SP` finalize_command=`$echo "X$finalize_command" | $SP2NL | $Xsed -e "s% @SYMFILE@%%" | $NL2SP` fi if test "$need_relink" = no || test "$build_libtool_libs" != yes; then # Replace the output file specification. compile_command=`$echo "X$compile_command" | $SP2NL | $Xsed -e 's%@OUTPUT@%'"$output"'%g' | $NL2SP` link_command="$compile_command$compile_rpath" # We have no uninstalled library dependencies, so finalize right now. $show "$link_command" $run eval "$link_command" exit_status=$? # Delete the generated files. if test -n "$dlsyms"; then $show "$rm $output_objdir/${outputname}S.${objext}" $run $rm "$output_objdir/${outputname}S.${objext}" fi exit $exit_status fi if test -n "$shlibpath_var"; then # We should set the shlibpath_var rpath= for dir in $temp_rpath; do case $dir in [\\/]* | [A-Za-z]:[\\/]*) # Absolute path. rpath="$rpath$dir:" ;; *) # Relative path: add a thisdir entry. rpath="$rpath\$thisdir/$dir:" ;; esac done temp_rpath="$rpath" fi if test -n "$compile_shlibpath$finalize_shlibpath"; then compile_command="$shlibpath_var=\"$compile_shlibpath$finalize_shlibpath\$$shlibpath_var\" $compile_command" fi if test -n "$finalize_shlibpath"; then finalize_command="$shlibpath_var=\"$finalize_shlibpath\$$shlibpath_var\" $finalize_command" fi compile_var= finalize_var= if test -n "$runpath_var"; then if test -n "$perm_rpath"; then # We should set the runpath_var. rpath= for dir in $perm_rpath; do rpath="$rpath$dir:" done compile_var="$runpath_var=\"$rpath\$$runpath_var\" " fi if test -n "$finalize_perm_rpath"; then # We should set the runpath_var. rpath= for dir in $finalize_perm_rpath; do rpath="$rpath$dir:" done finalize_var="$runpath_var=\"$rpath\$$runpath_var\" " fi fi if test "$no_install" = yes; then # We don't need to create a wrapper script. link_command="$compile_var$compile_command$compile_rpath" # Replace the output file specification. link_command=`$echo "X$link_command" | $Xsed -e 's%@OUTPUT@%'"$output"'%g'` # Delete the old output file. $run $rm $output # Link the executable and exit $show "$link_command" $run eval "$link_command" || exit $? exit $EXIT_SUCCESS fi if test "$hardcode_action" = relink; then # Fast installation is not supported link_command="$compile_var$compile_command$compile_rpath" relink_command="$finalize_var$finalize_command$finalize_rpath" $echo "$modename: warning: this platform does not like uninstalled shared libraries" 1>&2 $echo "$modename: \`$output' will be relinked during installation" 1>&2 else if test "$fast_install" != no; then link_command="$finalize_var$compile_command$finalize_rpath" if test "$fast_install" = yes; then relink_command=`$echo "X$compile_var$compile_command$compile_rpath" | $SP2NL | $Xsed -e 's%@OUTPUT@%\$progdir/\$file%g' | $NL2SP` else # fast_install is set to needless relink_command= fi else link_command="$compile_var$compile_command$compile_rpath" relink_command="$finalize_var$finalize_command$finalize_rpath" fi fi # Replace the output file specification. link_command=`$echo "X$link_command" | $Xsed -e 's%@OUTPUT@%'"$output_objdir/$outputname"'%g'` # Delete the old output files. $run $rm $output $output_objdir/$outputname $output_objdir/lt-$outputname $show "$link_command" $run eval "$link_command" || exit $? # Now create the wrapper script. $show "creating $output" # Quote the relink command for shipping. if test -n "$relink_command"; then # Preserve any variables that may affect compiler behavior for var in $variables_saved_for_relink; do if eval test -z \"\${$var+set}\"; then relink_command="{ test -z \"\${$var+set}\" || unset $var || { $var=; export $var; }; }; $relink_command" elif eval var_value=\$$var; test -z "$var_value"; then relink_command="$var=; export $var; $relink_command" else var_value=`$echo "X$var_value" | $Xsed -e "$sed_quote_subst"` relink_command="$var=\"$var_value\"; export $var; $relink_command" fi done relink_command="(cd `pwd`; $relink_command)" relink_command=`$echo "X$relink_command" | $SP2NL | $Xsed -e "$sed_quote_subst" | $NL2SP` fi # Quote $echo for shipping. if test "X$echo" = "X$SHELL $progpath --fallback-echo"; then case $progpath in [\\/]* | [A-Za-z]:[\\/]*) qecho="$SHELL $progpath --fallback-echo";; *) qecho="$SHELL `pwd`/$progpath --fallback-echo";; esac qecho=`$echo "X$qecho" | $Xsed -e "$sed_quote_subst"` else qecho=`$echo "X$echo" | $Xsed -e "$sed_quote_subst"` fi # Only actually do things if our run command is non-null. if test -z "$run"; then # win32 will think the script is a binary if it has # a .exe suffix, so we strip it off here. case $output in *.exe) output=`$echo $output|${SED} 's,.exe$,,'` ;; esac # test for cygwin because mv fails w/o .exe extensions case $host in *cygwin*) exeext=.exe outputname=`$echo $outputname|${SED} 's,.exe$,,'` ;; *) exeext= ;; esac case $host in *cygwin* | *mingw* ) output_name=`basename $output` output_path=`dirname $output` cwrappersource="$output_path/$objdir/lt-$output_name.c" cwrapper="$output_path/$output_name.exe" $rm $cwrappersource $cwrapper trap "$rm $cwrappersource $cwrapper; exit $EXIT_FAILURE" 1 2 15 cat > $cwrappersource <> $cwrappersource<<"EOF" #include #include #include #include #include #include #include #include #include #if defined(PATH_MAX) # define LT_PATHMAX PATH_MAX #elif defined(MAXPATHLEN) # define LT_PATHMAX MAXPATHLEN #else # define LT_PATHMAX 1024 #endif #ifndef DIR_SEPARATOR # define DIR_SEPARATOR '/' # define PATH_SEPARATOR ':' #endif #if defined (_WIN32) || defined (__MSDOS__) || defined (__DJGPP__) || \ defined (__OS2__) # define HAVE_DOS_BASED_FILE_SYSTEM # ifndef DIR_SEPARATOR_2 # define DIR_SEPARATOR_2 '\\' # endif # ifndef PATH_SEPARATOR_2 # define PATH_SEPARATOR_2 ';' # endif #endif #ifndef DIR_SEPARATOR_2 # define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) #else /* DIR_SEPARATOR_2 */ # define IS_DIR_SEPARATOR(ch) \ (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) #endif /* DIR_SEPARATOR_2 */ #ifndef PATH_SEPARATOR_2 # define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR) #else /* PATH_SEPARATOR_2 */ # define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR_2) #endif /* PATH_SEPARATOR_2 */ #define XMALLOC(type, num) ((type *) xmalloc ((num) * sizeof(type))) #define XFREE(stale) do { \ if (stale) { free ((void *) stale); stale = 0; } \ } while (0) /* -DDEBUG is fairly common in CFLAGS. */ #undef DEBUG #if defined DEBUGWRAPPER # define DEBUG(format, ...) fprintf(stderr, format, __VA_ARGS__) #else # define DEBUG(format, ...) #endif const char *program_name = NULL; void * xmalloc (size_t num); char * xstrdup (const char *string); const char * base_name (const char *name); char * find_executable(const char *wrapper); int check_executable(const char *path); char * strendzap(char *str, const char *pat); void lt_fatal (const char *message, ...); int main (int argc, char *argv[]) { char **newargz; int i; program_name = (char *) xstrdup (base_name (argv[0])); DEBUG("(main) argv[0] : %s\n",argv[0]); DEBUG("(main) program_name : %s\n",program_name); newargz = XMALLOC(char *, argc+2); EOF cat >> $cwrappersource <> $cwrappersource <<"EOF" newargz[1] = find_executable(argv[0]); if (newargz[1] == NULL) lt_fatal("Couldn't find %s", argv[0]); DEBUG("(main) found exe at : %s\n",newargz[1]); /* we know the script has the same name, without the .exe */ /* so make sure newargz[1] doesn't end in .exe */ strendzap(newargz[1],".exe"); for (i = 1; i < argc; i++) newargz[i+1] = xstrdup(argv[i]); newargz[argc+1] = NULL; for (i=0; i> $cwrappersource <> $cwrappersource <> $cwrappersource <<"EOF" return 127; } void * xmalloc (size_t num) { void * p = (void *) malloc (num); if (!p) lt_fatal ("Memory exhausted"); return p; } char * xstrdup (const char *string) { return string ? strcpy ((char *) xmalloc (strlen (string) + 1), string) : NULL ; } const char * base_name (const char *name) { const char *base; #if defined (HAVE_DOS_BASED_FILE_SYSTEM) /* Skip over the disk name in MSDOS pathnames. */ if (isalpha ((unsigned char)name[0]) && name[1] == ':') name += 2; #endif for (base = name; *name; name++) if (IS_DIR_SEPARATOR (*name)) base = name + 1; return base; } int check_executable(const char * path) { struct stat st; DEBUG("(check_executable) : %s\n", path ? (*path ? path : "EMPTY!") : "NULL!"); if ((!path) || (!*path)) return 0; if ((stat (path, &st) >= 0) && ( /* MinGW & native WIN32 do not support S_IXOTH or S_IXGRP */ #if defined (S_IXOTH) ((st.st_mode & S_IXOTH) == S_IXOTH) || #endif #if defined (S_IXGRP) ((st.st_mode & S_IXGRP) == S_IXGRP) || #endif ((st.st_mode & S_IXUSR) == S_IXUSR)) ) return 1; else return 0; } /* Searches for the full path of the wrapper. Returns newly allocated full path name if found, NULL otherwise */ char * find_executable (const char* wrapper) { int has_slash = 0; const char* p; const char* p_next; /* static buffer for getcwd */ char tmp[LT_PATHMAX + 1]; int tmp_len; char* concat_name; DEBUG("(find_executable) : %s\n", wrapper ? (*wrapper ? wrapper : "EMPTY!") : "NULL!"); if ((wrapper == NULL) || (*wrapper == '\0')) return NULL; /* Absolute path? */ #if defined (HAVE_DOS_BASED_FILE_SYSTEM) if (isalpha ((unsigned char)wrapper[0]) && wrapper[1] == ':') { concat_name = xstrdup (wrapper); if (check_executable(concat_name)) return concat_name; XFREE(concat_name); } else { #endif if (IS_DIR_SEPARATOR (wrapper[0])) { concat_name = xstrdup (wrapper); if (check_executable(concat_name)) return concat_name; XFREE(concat_name); } #if defined (HAVE_DOS_BASED_FILE_SYSTEM) } #endif for (p = wrapper; *p; p++) if (*p == '/') { has_slash = 1; break; } if (!has_slash) { /* no slashes; search PATH */ const char* path = getenv ("PATH"); if (path != NULL) { for (p = path; *p; p = p_next) { const char* q; size_t p_len; for (q = p; *q; q++) if (IS_PATH_SEPARATOR(*q)) break; p_len = q - p; p_next = (*q == '\0' ? q : q + 1); if (p_len == 0) { /* empty path: current directory */ if (getcwd (tmp, LT_PATHMAX) == NULL) lt_fatal ("getcwd failed"); tmp_len = strlen(tmp); concat_name = XMALLOC(char, tmp_len + 1 + strlen(wrapper) + 1); memcpy (concat_name, tmp, tmp_len); concat_name[tmp_len] = '/'; strcpy (concat_name + tmp_len + 1, wrapper); } else { concat_name = XMALLOC(char, p_len + 1 + strlen(wrapper) + 1); memcpy (concat_name, p, p_len); concat_name[p_len] = '/'; strcpy (concat_name + p_len + 1, wrapper); } if (check_executable(concat_name)) return concat_name; XFREE(concat_name); } } /* not found in PATH; assume curdir */ } /* Relative path | not found in path: prepend cwd */ if (getcwd (tmp, LT_PATHMAX) == NULL) lt_fatal ("getcwd failed"); tmp_len = strlen(tmp); concat_name = XMALLOC(char, tmp_len + 1 + strlen(wrapper) + 1); memcpy (concat_name, tmp, tmp_len); concat_name[tmp_len] = '/'; strcpy (concat_name + tmp_len + 1, wrapper); if (check_executable(concat_name)) return concat_name; XFREE(concat_name); return NULL; } char * strendzap(char *str, const char *pat) { size_t len, patlen; assert(str != NULL); assert(pat != NULL); len = strlen(str); patlen = strlen(pat); if (patlen <= len) { str += len - patlen; if (strcmp(str, pat) == 0) *str = '\0'; } return str; } static void lt_error_core (int exit_status, const char * mode, const char * message, va_list ap) { fprintf (stderr, "%s: %s: ", program_name, mode); vfprintf (stderr, message, ap); fprintf (stderr, ".\n"); if (exit_status >= 0) exit (exit_status); } void lt_fatal (const char *message, ...) { va_list ap; va_start (ap, message); lt_error_core (EXIT_FAILURE, "FATAL", message, ap); va_end (ap); } EOF # we should really use a build-platform specific compiler # here, but OTOH, the wrappers (shell script and this C one) # are only useful if you want to execute the "real" binary. # Since the "real" binary is built for $host, then this # wrapper might as well be built for $host, too. $run $LTCC $LTCFLAGS -s -o $cwrapper $cwrappersource ;; esac $rm $output trap "$rm $output; exit $EXIT_FAILURE" 1 2 15 $echo > $output "\ #! $SHELL # $output - temporary wrapper script for $objdir/$outputname # Generated by $PROGRAM - GNU $PACKAGE $VERSION$TIMESTAMP # # The $output program cannot be directly executed until all the libtool # libraries that it depends on are installed. # # This wrapper script should never be moved out of the build directory. # If it is, it will not operate correctly. # Sed substitution that helps us do robust quoting. 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You may want to install GNU tar or Free paxutils, or check the command line arguments." exit 1 ;; *) echo 1>&2 "\ WARNING: \`$1' is needed, and is $msg. You might have modified some files without having the proper tools for further handling them. Check the \`README' file, it often tells you about the needed prerequisites for installing this package. You may also peek at any GNU archive site, in case some other package would contain this missing \`$1' program." exit 1 ;; esac exit 0 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: tkgate-2.0-b10/ylwrap000555 001751 001751 00000014061 11117364051 015251 0ustar00hansenhansen000000 000000 #! /bin/sh # ylwrap - wrapper for lex/yacc invocations. scriptversion=2005-05-14.22 # Copyright (C) 1996, 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. # # Written by Tom Tromey . # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA # 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # This file is maintained in Automake, please report # bugs to or send patches to # . case "$1" in '') echo "$0: No files given. Try \`$0 --help' for more information." 1>&2 exit 1 ;; --basedir) basedir=$2 shift 2 ;; -h|--h*) cat <<\EOF Usage: ylwrap [--help|--version] INPUT [OUTPUT DESIRED]... -- PROGRAM [ARGS]... Wrapper for lex/yacc invocations, renaming files as desired. INPUT is the input file OUTPUT is one file PROG generates DESIRED is the file we actually want instead of OUTPUT PROGRAM is program to run ARGS are passed to PROG Any number of OUTPUT,DESIRED pairs may be used. Report bugs to . EOF exit $? ;; -v|--v*) echo "ylwrap $scriptversion" exit $? ;; esac # The input. input="$1" shift case "$input" in [\\/]* | ?:[\\/]*) # Absolute path; do nothing. ;; *) # Relative path. Make it absolute. input="`pwd`/$input" ;; esac pairlist= while test "$#" -ne 0; do if test "$1" = "--"; then shift break fi pairlist="$pairlist $1" shift done # The program to run. prog="$1" shift # Make any relative path in $prog absolute. case "$prog" in [\\/]* | ?:[\\/]*) ;; *[\\/]*) prog="`pwd`/$prog" ;; esac # FIXME: add hostname here for parallel makes that run commands on # other machines. But that might take us over the 14-char limit. dirname=ylwrap$$ trap "cd `pwd`; rm -rf $dirname > /dev/null 2>&1" 1 2 3 15 mkdir $dirname || exit 1 cd $dirname case $# in 0) $prog "$input" ;; *) $prog "$@" "$input" ;; esac ret=$? if test $ret -eq 0; then set X $pairlist shift first=yes # Since DOS filename conventions don't allow two dots, # the DOS version of Bison writes out y_tab.c instead of y.tab.c # and y_tab.h instead of y.tab.h. Test to see if this is the case. y_tab_nodot="no" if test -f y_tab.c || test -f y_tab.h; then y_tab_nodot="yes" fi # The directory holding the input. input_dir=`echo "$input" | sed -e 's,\([\\/]\)[^\\/]*$,\1,'` # Quote $INPUT_DIR so we can use it in a regexp. # FIXME: really we should care about more than `.' and `\'. input_rx=`echo "$input_dir" | sed 's,\\\\,\\\\\\\\,g;s,\\.,\\\\.,g'` while test "$#" -ne 0; do from="$1" # Handle y_tab.c and y_tab.h output by DOS if test $y_tab_nodot = "yes"; then if test $from = "y.tab.c"; then from="y_tab.c" else if test $from = "y.tab.h"; then from="y_tab.h" fi fi fi if test -f "$from"; then # If $2 is an absolute path name, then just use that, # otherwise prepend `../'. case "$2" in [\\/]* | ?:[\\/]*) target="$2";; *) target="../$2";; esac # We do not want to overwrite a header file if it hasn't # changed. This avoid useless recompilations. However the # parser itself (the first file) should always be updated, # because it is the destination of the .y.c rule in the # Makefile. Divert the output of all other files to a temporary # file so we can compare them to existing versions. if test $first = no; then realtarget="$target" target="tmp-`echo $target | sed s/.*[\\/]//g`" fi # Edit out `#line' or `#' directives. # # We don't want the resulting debug information to point at # an absolute srcdir; it is better for it to just mention the # .y file with no path. # # We want to use the real output file name, not yy.lex.c for # instance. # # We want the include guards to be adjusted too. FROM=`echo "$from" | sed \ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'\ -e 's/[^ABCDEFGHIJKLMNOPQRSTUVWXYZ]/_/g'` TARGET=`echo "$2" | sed \ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'\ -e 's/[^ABCDEFGHIJKLMNOPQRSTUVWXYZ]/_/g'` sed -e "/^#/!b" -e "s,$input_rx,," -e "s,$from,$2," \ -e "s,$FROM,$TARGET," "$from" >"$target" || ret=$? # Check whether header files must be updated. if test $first = no; then if test -f "$realtarget" && cmp -s "$realtarget" "$target"; then echo "$2" is unchanged rm -f "$target" else echo updating "$2" mv -f "$target" "$realtarget" fi fi else # A missing file is only an error for the first file. This # is a blatant hack to let us support using "yacc -d". If -d # is not specified, we don't want an error when the header # file is "missing". if test $first = yes; then ret=1 fi fi shift shift first=no done else ret=$? fi # Remove the directory. cd .. rm -rf $dirname exit $ret # Local Variables: # mode: shell-script # sh-indentation: 2 # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: tkgate-2.0-b10/scripts000777 001751 001751 00000000000 11257511454 015427 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/bindings000777 001751 001751 00000000000 11150647175 015537 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/doc000777 001751 001751 00000000000 11117116466 014504 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/gdf000777 001751 001751 00000000000 11141041466 014471 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/images000777 001751 001751 00000000000 11150117453 015176 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale000777 001751 001751 00000000000 11200171144 015161 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/povray000777 001751 001751 00000000000 11141705062 015250 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/primitives000777 001751 001751 00000000000 11144654176 016137 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/vlib000777 001751 001751 00000000000 11176732642 014700 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/vpd000777 001751 001751 00000000000 11132630171 014517 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/test000777 001751 001751 00000000000 10653475634 014727 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/test/tkgate000777 001751 001751 00000000000 10653475634 016206 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/test/verga000777 001751 001751 00000000000 11140743765 016026 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/test/verga-realtime000777 001751 001751 00000000000 10521225424 017613 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/test/verga-realtime/timer2.v000644 001751 001751 00000000263 10504616357 021272 0ustar00hansenhansen000000 000000 module top; time t; initial begin t = $tkg$systime; forever begin $display("hello world %t",t); t = t + 1000; $tkg$waituntil(t); end end endmodule tkgate-2.0-b10/test/verga-realtime/README000644 001751 001751 00000000130 10504616357 020552 0ustar00hansenhansen000000 000000 The tests in this directory are modules that use one of the wall clock delay functions. tkgate-2.0-b10/test/verga-realtime/timer1.v000644 001751 001751 00000000157 10504616357 021273 0ustar00hansenhansen000000 000000 module top; always begin $display("hello world %t",$tkg$systime); $tkg$wait(1000); end endmodule tkgate-2.0-b10/test/verga/memory3.out000644 001751 001751 00000001130 11140743763 020216 0ustar00hansenhansen000000 000000 0: m[3]=8'h92 w=8'hz 0: w changed to 8'hx 0: w changed to 8'h92 1: m[3]=8'h92 w=8'h92 2: m[3]=8'h7 w=8'h92 2: w changed to 8'h7 3: m[3]=8'h37 w=8'h7 3: w changed to 8'h37 4: m[3]=8'h37 w=8'h37 5: m[3]=8'h37 w=8'h37 6: m[3]=8'h37 w=8'h37 6: w changed to 8'h99 7: m[3]=8'h99 w=8'h99 8: m[3]=8'h99 w=8'h99 9: m[3]=8'h42 w=8'h99 9: w changed to 8'h42 10: m[3]=8'h42 w=8'h42 11: m[3]=8'h42 w=8'h42 12: m[3]=8'h42 w=8'h42 13: m[3]=8'h42 w=8'h42 14: m[3]=8'h42 w=8'h42 15: m[3]=8'h42 w=8'h42 16: m[3]=8'h42 w=8'h42 17: m[3]=8'h42 w=8'h42 18: m[3]=8'h42 w=8'h42 19: m[3]=8'h42 w=8'h42 20: m[3]=8'h42 w=8'h42 tkgate-2.0-b10/test/verga/adder1.v000644 001751 001751 00000001204 10133373426 017417 0ustar00hansenhansen000000 000000 module top; wire s,co; reg a,b,ci; adder a1(s,co,a,b,ci); initial begin $monitor("%d: {%h,%h} = %h + %h + %h",$time,co,s,a,b,ci); #2 a = 1'b0; b = 1'b0; ci = 1'b0; #2 a = 1'b0; b = 1'b0; ci = 1'b1; #2 a = 1'b0; b = 1'b1; ci = 1'b0; #2 a = 1'b0; b = 1'b1; ci = 1'b1; #2 a = 1'b1; b = 1'b0; ci = 1'b0; #2 a = 1'b1; b = 1'b0; ci = 1'b1; #2 a = 1'b1; b = 1'b1; ci = 1'b0; #2 a = 1'b1; b = 1'b1; ci = 1'b1; end endmodule module adder(s,co,a,b,ci); output s,co; input a,b,ci; wire x1,w1,w2,w3; xor (x1,a,b); xor (s,x1,ci); and (w1,a,b); and (w2,a,ci); and (w3,b,ci); or (co, w1, w2, w3); endmodule tkgate-2.0-b10/test/verga/adder2.out000644 001751 001751 00000000125 10505463332 017762 0ustar00hansenhansen000000 000000 0: x = x + x + x 2: 0 = 0 + 0 + 0 4: 9 = 2 + 7 + 0 6: a = 2 + 7 + 1 8: d = 9 + 3 + 1 tkgate-2.0-b10/test/verga/adder2.v000644 001751 001751 00000001253 10133374062 017421 0ustar00hansenhansen000000 000000 module top; wire [3:0] s; wire [4:0] c; reg [3:0] a,b; reg ci; adder a1 (s[0], c[1], a[0], b[0], ci); adder a2 (s[1], c[2], a[1], b[1], c[1]); adder a3 (s[2], c[3], a[2], b[2], c[2]); adder a4 (s[3], c[4], a[3], b[3], c[3]); initial begin $monitor("%d: %h = %h + %h + %h",$time,{c[4],s},a,b,ci); #2 a = 4'b0; b = 4'b0; ci = 1'b0; #2 a = 4'h2; b = 4'h7; ci = 1'b0; #2 a = 4'h2; b = 4'h7; ci = 1'b1; #2 a = 4'h9; b = 4'h3; ci = 1'b1; end endmodule module adder(s,co,a,b,ci); output s,co; input a,b,ci; wire x1,w1,w2,w3; xor (x1,a,b); xor (s,x1,ci); and (w1,a,b); and (w2,a,ci); and (w3,b,ci); or (co, w1, w2, w3); endmodule tkgate-2.0-b10/test/verga/adder3.out000644 001751 001751 00000000150 10505463332 017761 0ustar00hansenhansen000000 000000 0: x = x + x + x 2: 0 = 0 + 0 + 0 4: 9 = 2 + 7 + 0 6: a = 2 + 7 + 1 8: d = 9 + 3 + 1 10: 12 = f + 3 + 0 tkgate-2.0-b10/test/verga/adder3.v000644 001751 001751 00000001275 10133375156 017433 0ustar00hansenhansen000000 000000 module top; wire [3:0] s; wire co; reg [3:0] a,b; reg ci; adder a1 (s, co, a, b, ci); initial begin $monitor("%d: %h = %h + %h + %h",$time,{co,s},a,b,ci); #2 a = 4'b0; b = 4'b0; ci = 1'b0; #2 a = 4'h2; b = 4'h7; ci = 1'b0; #2 a = 4'h2; b = 4'h7; ci = 1'b1; #2 a = 4'h9; b = 4'h3; ci = 1'b1; #2 a = 4'hf; b = 4'h3; ci = 1'b0; end endmodule module adder(s,co,a,b,ci); output [3:0] s; output co; input [3:0] a,b; input ci; wire [2:0] c; wire [3:0] x1,w1,w2,w3; xor g1[3:0] (x1,a,b); xor g1[3:0] (s,x1,{c[2:0],ci}); and g1[3:0] (w1,a,b); and g1[3:0] (w2,a,{c[2:0],ci}); and g1[3:0] (w3,b,{c[2:0],ci}); or g1[3:0] ({co,c}, w1, w2, w3); endmodule tkgate-2.0-b10/test/verga/always1.out000644 001751 001751 00000001123 10505463332 020201 0ustar00hansenhansen000000 000000 r=0 in @2 change in r=0 or b=x b=0 @3 change in r=0 or b=0 r=1 in @4 change in r=1 or b=0 b=1 r=2 in @6 change in r=2 or b=1 r=3 in @8 change in r=3 or b=1 b=2 @9 change in r=3 or b=2 r=4 in @10 change in r=4 or b=2 b=3 r=5 in @12 change in r=5 or b=3 r=6 in @14 change in r=6 or b=3 b=4 @15 change in r=6 or b=4 r=7 in @16 change in r=7 or b=4 b=5 r=8 in @18 change in r=8 or b=5 r=9 in @20 change in r=9 or b=5 b=6 @21 change in r=9 or b=6 b=14 @26 change in r=9 or b=14 b=16 @31 change in r=9 or b=16 b=18 @36 change in r=9 or b=18 tkgate-2.0-b10/test/verga/always1.v000644 001751 001751 00000000644 10124345265 017647 0ustar00hansenhansen000000 000000 module top; reg[31:0] r,b; integer i,j; initial for (i = 0;i < 10;i = i + 1) begin #2 r = i; $display("r=%d in <%m>",r); end initial for (j = 0;j < 10;j = j + 1) begin if (j < 7) #3 b = j; else #5 b = 2*j; $display("b=%d",b); end always @(r or b) begin $display("@%d change in r=%d or b=%d",$time,r,b); end endmodule tkgate-2.0-b10/test/verga/ashift.out000644 001751 001751 00000003153 10505463332 020103 0ustar00hansenhansen000000 000000 Starting ashift test i = deadbeef i = fdeadbee i = ffdeadbe i = fffdeadb i = ffffdead i = fffffdea i = ffffffde i = fffffffd big = 8123456789abcdefdeadbeefcafebabe big = f8123456789abcdefdeadbeefcafebab big = ff8123456789abcdefdeadbeefcafeba big = fff8123456789abcdefdeadbeefcafeb big = ffff8123456789abcdefdeadbeefcafe big = fffff8123456789abcdefdeadbeefcaf big = ffffff8123456789abcdefdeadbeefca big = fffffff8123456789abcdefdeadbeefc big = ffffffff8123456789abcdefdeadbeef big = fffffffff8123456789abcdefdeadbee big = ffffffffff8123456789abcdefdeadbe big = fffffffffff8123456789abcdefdeadb big = ffffffffffff8123456789abcdefdead big = fffffffffffff8123456789abcdefdea big = ffffffffffffff8123456789abcdefde big = fffffffffffffff8123456789abcdefd big = ffffffffffffffff8123456789abcdef big = fffffffffffffffff8123456789abcde big = ffffffffffffffffff8123456789abcd big = fffffffffffffffffff8123456789abc big = ffffffffffffffffffff8123456789ab big = fffffffffffffffffffff8123456789a big = ffffffffffffffffffffff8123456789 big = fffffffffffffffffffffff812345678 big = ffffffffffffffffffffffff81234567 big = fffffffffffffffffffffffff8123456 big = ffffffffffffffffffffffffff812345 big = fffffffffffffffffffffffffff81234 big = ffffffffffffffffffffffffffff8123 big = fffffffffffffffffffffffffffff812 big = ffffffffffffffffffffffffffffff81 big = fffffffffffffffffffffffffffffff8 big>>>4 = f8123456789abcdefdeadbeefcafebab big>>>32 = ffffffff8123456789abcdefdeadbeef big>>>39 = ffffffffff02468acf13579bdfbd5b7d big>>>64 = ffffffffffffffff8123456789abcdef big>>>68 = fffffffffffffffff8123456789abcde big>>>200 = ffffffffffffffffffffffffffffffff tkgate-2.0-b10/test/verga/ashift.v000644 001751 001751 00000001314 10223001226 017521 0ustar00hansenhansen000000 000000 module top; reg [127: 0] big; reg [31:0] i; integer j; initial begin $display("Starting ashift test"); i = 32'hdeadbeef; for (j=0; j<8; j = j + 1) begin $display("i = %08h", i); i = i >>> 4; end big = 128'h8123456789abcdefdeadbeefcafebabe; for (j=0; j<32; j = j + 1) begin $display("big = %032h", big); big = big >>> 4; end big = 128'h8123456789abcdefdeadbeefcafebabe; $display("big>>>4 = %032h", big>>>4); $display("big>>>32 = %032h", big>>>32); $display("big>>>39 = %032h", big>>>39); $display("big>>>64 = %032h", big>>>64); $display("big>>>68 = %032h", big>>>68); $display("big>>>200 = %032h", big>>>200); end endmodule tkgate-2.0-b10/test/verga/bitselect1.out000644 001751 001751 00000002474 10505463332 020671 0ustar00hansenhansen000000 000000 q=f1 q=ef q=de q=cd q=bc q=ab q=9a q=89 q=78 q=67 q=56 q=45 q=34 q=23 q=12 i= 0 a=00000000000000ff i= 4 a=0000000000000ff0 i= 8 a=000000000000ff00 i=12 a=00000000000ff000 i=16 a=0000000000ff0000 i=20 a=000000000ff00000 i=24 a=00000000ff000000 i=28 a=0000000ff0000000 i=32 a=000000ff00000000 i=36 a=00000ff000000000 i=40 a=0000ff0000000000 i=44 a=000ff00000000000 i=48 a=00ff000000000000 i=52 a=0ff0000000000000 i=56 a=ff00000000000000 ---- q=f1 q=ef q=de q=cd q=bc q=ab q=9a q=89 q=78 q=67 q=56 q=45 q=34 q=23 q=12 i= 0 b=00000000000000ff i= 4 b=0000000000000ff0 i= 8 b=000000000000ff00 i=12 b=00000000000ff000 i=16 b=0000000000ff0000 i=20 b=000000000ff00000 i=24 b=00000000ff000000 i=28 b=0000000ff0000000 i=32 b=000000ff00000000 i=36 b=00000ff000000000 i=40 b=0000ff0000000000 i=44 b=000ff00000000000 i=48 b=00ff000000000000 i=52 b=0ff0000000000000 i=56 b=ff00000000000000 ---- q=f1 q=ef q=de q=cd q=bc q=ab q=9a q=89 q=78 q=67 q=56 q=45 q=34 q=23 i= 0 c=00000000000000ff i= 4 c=0000000000000ff0 i= 8 c=000000000000ff00 i=12 c=00000000000ff000 i=16 c=0000000000ff0000 i=20 c=000000000ff00000 i=24 c=00000000ff000000 i=28 c=0000000ff0000000 i=32 c=000000ff00000000 i=36 c=00000ff000000000 i=40 c=0000ff0000000000 i=44 c=000ff00000000000 i=48 c=00ff000000000000 i=52 c=0ff0000000000000 tkgate-2.0-b10/test/verga/bitselect1.v000644 001751 001751 00000001651 10125166137 020324 0ustar00hansenhansen000000 000000 module top; reg [63:0] a; reg [64:0] b; reg [62:0] c; reg [7:0] q; integer i; initial begin a = 64'h123456789abcdef1; for (i = 0;i <= 56;i = i + 4) begin q = a[i +: 8]; $display("q=%h",q); end q = 8'hff; for (i = 0;i <= 56;i = i + 4) begin a = 0; a[i +: 8] = q; $display("i=%2d a=%016h",i,a); end $display(" ---- "); b = 64'h123456789abcdef1; for (i = 0;i <= 56;i = i + 4) begin q = b[i +: 8]; $display("q=%h",q); end q = 8'hff; for (i = 0;i <= 56;i = i + 4) begin b = 0; b[i +: 8] = q; $display("i=%2d b=%016h",i,b); end $display(" ---- "); c = 63'h123456789abcdef1; for (i = 0;i < 56;i = i + 4) begin q = c[i +: 8]; $display("q=%h",q); end q = 8'hff; for (i = 0;i < 56;i = i + 4) begin c = 0; c[i +: 8] = q; $display("i=%2d c=%016h",i,c); end end endmodule tkgate-2.0-b10/test/verga/bitselect2.out000644 001751 001751 00000000144 10505463332 020662 0ustar00hansenhansen000000 000000 b1=xxxxxxxxxxxxxxxx b2=0000000000000000 b3=0000ff0000000000 b4=0000000000000000 b5=000ff00000000000 tkgate-2.0-b10/test/verga/bitselect2.v000644 001751 001751 00000000535 10125166141 020320 0ustar00hansenhansen000000 000000 module top; reg [63:0] b; reg [7:0] c; integer i; initial begin $display("b1=%016h",b); b = 64'h0; $display("b2=%016h",b); b[40 +: 8] = 8'hff; $display("b3=%016h",b); b = 64'h0; b = 64'h0; $display("b4=%016h",b); b[44 +: 8] = 8'hff; $display("b5=%016h",b); end endmodule tkgate-2.0-b10/test/verga/bitselect3.out000644 001751 001751 00000000052 10505463332 020661 0ustar00hansenhansen000000 000000 n=12345678abcdef1 b1=8abcdef1 b1=8abf1ef1 tkgate-2.0-b10/test/verga/bitselect3.v000644 001751 001751 00000000316 10125167124 020320 0ustar00hansenhansen000000 000000 module top; reg [31:0] b; initial begin $display("n=%h",'h12345678abcdef1); b = 'h12345678abcdef1; $display("b1=%h",b); b[19:12] = 64'h12345678abcdef1; $display("b1=%h",b); end endmodule tkgate-2.0-b10/test/verga/buf.out000644 001751 001751 00000001060 10505463332 017374 0ustar00hansenhansen000000 000000 5: a=x : x=z y=z z=z : i=x j=x k=x 7: a=x : x=x y=x z=x : i=x j=x k=x 10: a=1 : x=x y=x z=x : i=x j=x k=x 15: a=1 : x=x y=x z=x : i=0 j=0 k=0 17: a=1 : x=1 y=1 z=1 : i=0 j=0 k=0 20: a=0 : x=1 y=1 z=1 : i=0 j=0 k=0 25: a=0 : x=1 y=1 z=1 : i=1 j=1 k=1 27: a=0 : x=0 y=0 z=0 : i=1 j=1 k=1 30: a=1 : x=0 y=0 z=0 : i=1 j=1 k=1 35: a=1 : x=0 y=0 z=0 : i=0 j=0 k=0 37: a=1 : x=1 y=1 z=1 : i=0 j=0 k=0 40: a=0 : x=1 y=1 z=1 : i=0 j=0 k=0 45: a=0 : x=1 y=1 z=1 : i=1 j=1 k=1 47: a=0 : x=0 y=0 z=0 : i=1 j=1 k=1 tkgate-2.0-b10/test/verga/buf.v000644 001751 001751 00000000413 10436367437 017047 0ustar00hansenhansen000000 000000 module top; reg a; wire x,y,z,i,j,k; initial $monitor("%4d: a=%b : x=%b y=%b z=%b : i=%b j=%b k=%b",$time,a,x,y,z,i,j,k); initial begin #10 a = 1; #10 a = 0; #10 a = 1; #10 a = 0; end buf #7 b(x,y,z,a); not #5 n(i,j,k,a); endmodule tkgate-2.0-b10/test/verga/bufif.out000644 001751 001751 00000003300 10505463332 017712 0ustar00hansenhansen000000 000000 0: a=0 c=0 : pmos=0 nmos=z bufif1=z bufif0=0 10: a=0 c=1 : pmos=z nmos=0 bufif1=0 bufif0=z 20: a=0 c=x : pmos=L nmos=L bufif1=L bufif0=L 30: a=0 c=z : pmos=L nmos=L bufif1=L bufif0=L 40: a=0 c=L : pmos=L nmos=L bufif1=L bufif0=L 50: a=0 c=H : pmos=L nmos=L bufif1=L bufif0=L 60: a=1 c=0 : pmos=1 nmos=z bufif1=z bufif0=1 70: a=1 c=1 : pmos=z nmos=1 bufif1=1 bufif0=z 80: a=1 c=x : pmos=H nmos=H bufif1=H bufif0=H 90: a=1 c=z : pmos=H nmos=H bufif1=H bufif0=H 100: a=1 c=L : pmos=H nmos=H bufif1=H bufif0=H 110: a=1 c=H : pmos=H nmos=H bufif1=H bufif0=H 120: a=x c=0 : pmos=x nmos=z bufif1=z bufif0=x 130: a=x c=1 : pmos=z nmos=x bufif1=x bufif0=z 140: a=x c=x : pmos=x nmos=x bufif1=x bufif0=x 150: a=x c=z : pmos=x nmos=x bufif1=x bufif0=x 160: a=x c=L : pmos=x nmos=x bufif1=x bufif0=x 170: a=x c=H : pmos=x nmos=x bufif1=x bufif0=x 180: a=z c=0 : pmos=z nmos=z bufif1=z bufif0=x 190: a=z c=1 : pmos=z nmos=z bufif1=x bufif0=z 200: a=z c=x : pmos=z nmos=z bufif1=x bufif0=x 210: a=z c=z : pmos=z nmos=z bufif1=x bufif0=x 220: a=z c=L : pmos=z nmos=z bufif1=x bufif0=x 230: a=z c=H : pmos=z nmos=z bufif1=x bufif0=x 240: a=L c=0 : pmos=L nmos=z bufif1=z bufif0=x 250: a=L c=1 : pmos=z nmos=L bufif1=x bufif0=z 260: a=L c=x : pmos=L nmos=L bufif1=x bufif0=x 270: a=L c=z : pmos=L nmos=L bufif1=x bufif0=x 280: a=L c=L : pmos=L nmos=L bufif1=x bufif0=x 290: a=L c=H : pmos=L nmos=L bufif1=x bufif0=x 300: a=H c=0 : pmos=H nmos=z bufif1=z bufif0=x 310: a=H c=1 : pmos=z nmos=H bufif1=x bufif0=z 320: a=H c=x : pmos=H nmos=H bufif1=x bufif0=x 330: a=H c=z : pmos=H nmos=H bufif1=x bufif0=x 340: a=H c=L : pmos=H nmos=H bufif1=x bufif0=x 350: a=H c=H : pmos=H nmos=H bufif1=x bufif0=x tkgate-2.0-b10/test/verga/bufif.v000644 001751 001751 00000001160 10436370354 017356 0ustar00hansenhansen000000 000000 module top; integer i,j; reg a,c; wire w,x,y,z; function getbit; input [31:0] i; case (i) 0: getbit = 1'b0; 1: getbit = 1'b1; 2: getbit = 1'bx; 3: getbit = 1'bz; 4: getbit = 1'bl; 5: getbit = 1'bh; endcase endfunction initial $monitor("%4d: a=%b c=%b : pmos=%b nmos=%b bufif1=%b bufif0=%b",$time,a,c,w,x,y,z); initial for (i = 0;i < 6;i = i + 1) begin a = getbit(i); for (j = 0;j < 6;j = j + 1) begin c = getbit(j); #10; end end pmos b(w,a,c); nmos b(x,a,c); bufif1 b(y,a,c); bufif0 b(z,a,c); endmodule tkgate-2.0-b10/test/verga/case1.out000644 001751 001751 00000000043 10505463332 017614 0ustar00hansenhansen000000 000000 default one two three four default tkgate-2.0-b10/test/verga/case1.v000644 001751 001751 00000000457 10125676744 017276 0ustar00hansenhansen000000 000000 //: beginnetlist top module top; integer i,q; initial begin q = 1 + 1; for (i = 0;i < 6;i = i + 1) case (i) 8'h1: $display("one"); 4'h2: $display("two"); (q+1): $display("three"); 4: $display("four"); default: $display("default"); endcase end endmodule //:endnetlist top tkgate-2.0-b10/test/verga/channel1.out000644 001751 001751 00000000264 10505463332 020316 0ustar00hansenhansen000000 000000 writting 0 read 0 writting 1 read 1 writting 2 read 2 writting 3 read 3 writting 4 read 4 writting 5 read 5 writting 6 read 6 writting 7 read 7 writting 8 read 8 writting 9 read 9 tkgate-2.0-b10/test/verga/fork1.v000644 001751 001751 00000000447 10647451417 017320 0ustar00hansenhansen000000 000000 //: beginnetlist top module top; reg [31:0] a,b,c; initial begin fork @(a) $display("got a"); @(b) $display("got b"); @(c) $display("got c"); join $display("done with fork"); end initial begin #1 a = 1; #1 b = 1; #1 c = 1; end endmodule //:endnetlist top tkgate-2.0-b10/test/verga/channel1.v000644 001751 001751 00000000407 10255403067 017754 0ustar00hansenhansen000000 000000 module top; integer i,j; reg DSR; initial for (i = 0;i < 10;i = i + 1) begin $display("writting %d",i); $tkg$send("xyz",i); #1 ; end always forever begin j = $tkg$recv("xyz"); $display("read %d",j); end endmodule tkgate-2.0-b10/test/verga/command1.out000644 001751 001751 00000000023 10505463332 020315 0ustar00hansenhansen000000 000000 exec TTY::post top tkgate-2.0-b10/test/verga/command1.v000644 001751 001751 00000000243 10255403010 017744 0ustar00hansenhansen000000 000000 module top; integer i,j; reg DSR; initial $tkg$command("exec TTY::post %m"); always @(DSR) $tkg$command("exec TTY::data %m 8'h40"); endmodule tkgate-2.0-b10/test/verga/define.out000644 001751 001751 00000000614 10505463332 020056 0ustar00hansenhansen000000 000000 FOO-A-1 was included. [ok] BAR-A-1 was included. [ok] ARG-B-2 was included. [ok] BAR-B-3 was included. [ok] FOO-B-2 was included. [ok] FOO-C-1 was included. [ok] FOO-D-1 was included. [ok] BAR-D-1 was included. [ok] BAR-E-1 was included. [ok] FOO-F-1 was included. [ok] else-G-1 was included. [ok] FOO-H-1 was included. [ok] BAR-H-1 was included. [ok] FOO-H-2 was included. [ok] FOO=1234 r=4'h5 tkgate-2.0-b10/test/verga/define.v000644 001751 001751 00000010467 10312432042 017511 0ustar00hansenhansen000000 000000 `define FOO 1234 `define BAR 1 `define REG4 reg [3:0] `define BAR 1234 \ More text here `timescale 100 ns / 1 ns module top; `REG4 r; ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-A-1 was included. [ok]"); `endif `ifdef BAR initial $display("BAR-A-1 was included. [ok]"); `endif `ifdef ARG initial $display("ARG-A-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO `ifdef ARG initial $display("ARG-B-1 was included. [fail]"); `ifdef BAR initial $display("BAR-B-1 was included. [fail]"); `else initial $display("BAR-B-2 was included. [fail]"); `endif `else initial $display("ARG-B-2 was included. [ok]"); `ifdef BAR initial $display("BAR-B-3 was included. [ok]"); `else initial $display("BAR-B-4 was included. [fail]"); `endif `endif initial $display("FOO-B-2 was included. [ok]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef ARG initial $display("ARG-C-1 was included. [fail]"); `elseif FOO initial $display("FOO-C-1 was included. [ok]"); `elseif BAR initial $display("BAR-C-1 was included. [fail]"); `else initial $display("else-C-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-D-1 was included. [ok]"); `endif `ifdef BAR initial $display("BAR-D-1 was included. [ok]"); `endif `ifdef ARG initial $display("ARG-D-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef ARG initial $display("ARG-E-1 was included. [fail]"); `elseif XYZ initial $display("XYZ-E-1 was included. [fail]"); `elseif BAR initial $display("BAR-E-1 was included. [ok]"); `else initial $display("else-E-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-F-1 was included. [ok]"); `elseif BAR initial $display("BAR-F-1 was included. [fail]"); `elseif FOO initial $display("FOO-F-2 was included. [fail]"); `else initial $display("else-F-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef XYZ initial $display("XYZ-G-1 was included. [fail]"); `elseif DFG initial $display("DFG-G-1 was included. [fail]"); `elseif QWE initial $display("QWE-G-1 was included. [fail]"); `else initial $display("else-G-1 was included. [ok]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef XYZ initial $display("XYZ-H-1 was included. [fail]"); `elseif FOO initial $display("FOO-H-1 was included. [ok]"); `ifdef BAR initial $display("BAR-H-1 was included. [ok]"); `ifdef FOO initial $display("FOO-H-2 was included. [ok]"); `else initial $display("FOO-H-3 was included. [fail]"); `endif `else initial $display("BAR-H-2 was included. [fail]"); `ifdef FOO initial $display("FOO-H-4 was included. [fail]"); `else initial $display("FOO-H-5 was included. [fail]"); `endif `endif `elseif QWE initial $display("QWE-H-1 was included. [fail]"); `ifdef BAR initial $display("BAR-H-3 was included. [fail]"); `ifdef FOO initial $display("FOO-H-6 was included. [fail]"); `else initial $display("FOO-H-7 was included. [fail]"); `endif `else initial $display("BAR-H-4 was included. [fail]"); `ifdef FOO initial $display("FOO-H-8 was included. [fail]"); `else initial $display("FOO-H-9 was included. [fail]"); `endif `endif `else initial $display("else-H-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// initial begin r=5; $display("FOO=%d r=",`FOO,r); end endmodule tkgate-2.0-b10/test/verga/display1.out000644 001751 001751 00000000006 10505463332 020345 0ustar00hansenhansen000000 000000 d 6 6 tkgate-2.0-b10/test/verga/display1.v000644 001751 001751 00000000306 10124623326 020004 0ustar00hansenhansen000000 000000 module top; reg [7:0] a,b,c,d; initial begin a = 8'h7a; b = 0; c = 1; d = a[4:2]; $display("%h",a[c +: 4]); $display("%h",a[4:2]); $display("%h",d); end endmodule tkgate-2.0-b10/test/verga/display2.out000644 001751 001751 00000000247 10505463332 020355 0ustar00hansenhansen000000 000000 32'd1652763623 1652763623 64'd1652762343623232 1652762343623232 96'd1652762343623231827368712362 192'd98723498232342349823741652762343623231827368712362 128'h62832be7 tkgate-2.0-b10/test/verga/display2.v000644 001751 001751 00000000477 10255610527 020022 0ustar00hansenhansen000000 000000 module top; reg [127:0] a; initial begin $display(1652763623); $display("%d",1652763623); $display(1652762343623232); $display("%d",1652762343623232); $display(1652762343623231827368712362); $display(98723498232342349823741652762343623231827368712362); a = 1652763623; $display(a); end endmodule tkgate-2.0-b10/test/verga/edges1.out000644 001751 001751 00000000135 10505463332 017772 0ustar00hansenhansen000000 000000 a = 0 a = 1 a = 2 a = 4 x=x 6: posedge x=1 7: negedge x=0 8: posedge x=1 9: negedge x=0 done tkgate-2.0-b10/test/verga/edges1.v000644 001751 001751 00000001000 10124170366 017417 0ustar00hansenhansen000000 000000 // // Non-blocking assignment test. // module top; reg[31:0] a,b,c; reg x; integer i; always @(*) begin a = b + c; end always @(posedge x) $display("%d: posedge x=%b",$time,x); always @(negedge x) $display("%d: negedge x=%b",$time,x); always @(a) $display("a = %d",a); initial begin b = 0; c = 0; #1 b = 1; #1 b = 2; #1 c = 2; #1 c = 2; #1 c = 2; $display("x=%b",x); #1 x = 1; #1 x = 0; #1 x = 1; #1 x = 0; #1 $display("done"); end endmodule tkgate-2.0-b10/test/verga/edges2.out000644 001751 001751 00000000125 10505463332 017772 0ustar00hansenhansen000000 000000 x=x vcc=1 gnd=0 x=x vcc=1 gnd=0 posedge x=1 negedge x=0 posedge x=1 negedge x=0 done tkgate-2.0-b10/test/verga/edges2.v000644 001751 001751 00000000637 10124170366 017437 0ustar00hansenhansen000000 000000 // // Non-blocking assignment test. // module top; reg x; supply1 vcc; supply0 gnd; always @(posedge x) $display("posedge x=%d",x); always @(negedge x) $display("negedge x=%d",x); initial begin $display("x=%d vcc=%d gnd=%d",x,vcc,gnd); vcc = 0; $display("x=%d vcc=%d gnd=%d",x,vcc,gnd); #1 x = vcc; #1 x = gnd; #1 x = vcc; #1 x = gnd; #1 x = gnd; #1 $display("done"); end endmodule tkgate-2.0-b10/test/verga/errors.out000644 001751 001751 00000000167 10505463332 020143 0ustar00hansenhansen000000 000000 <"errors.v", 7> Undefined task '$displa'. <"errors.v", 8> Undefined variable 'qq'. Total of 2 errors in input file(s). tkgate-2.0-b10/test/verga/errors.v000644 001751 001751 00000000466 10261567356 017615 0ustar00hansenhansen000000 000000 module top; reg [127:0] a; initial begin $displa(1652763623); $display("%d",qq); $display(1652762343623232); $display("%d",1652762343623232); $display(1652762343623231827368712362); $display(98723498232342349823741652762343623231827368712362); a = 1652763623; $display(a); end endmodule tkgate-2.0-b10/test/verga/events1.out000644 001751 001751 00000000047 10505463332 020211 0ustar00hansenhansen000000 000000 @0: triggered on e @10: triggered on e tkgate-2.0-b10/test/verga/events1.v000644 001751 001751 00000000241 10362764723 017654 0ustar00hansenhansen000000 000000 module top; event e; initial begin #0; -> e; -> e; #10; -> e; -> e; end always @(e) $display("@%d: triggered on e",$time); endmodule tkgate-2.0-b10/test/verga/fdisplay1.out000644 001751 001751 00000000261 11140744576 020526 0ustar00hansenhansen000000 000000 f=2 hello worldRuntime Error at 0: Write to closed descriptor. Runtime Error at 0: Write to closed descriptor. x=0 x=1 3: monitored x = 0 6: monitored x = 1 8: monitored x = 0 tkgate-2.0-b10/test/verga/fdisplay1.v000644 001751 001751 00000000676 10252206366 020167 0ustar00hansenhansen000000 000000 module top; integer f,g; reg x; initial begin f = $fopen("test1.out"); g = $fopen("test2.out"); $display("f=%d",f); $fdisplay(1|f|g|16,"hello world"); x = 0; # 1; $fstrobe(1|f|g,"x=%d",x); $fdisplay(1|f|g,"x=%d",x); x = 1; # 1; $fmonitor(1|f,"%d: monitored x = %d", $time, x); # 1; x = 0; # 3; x = 1; # 2; x = 0; end endmodule tkgate-2.0-b10/test/verga/fibonacci.out000644 001751 001751 00000000354 10505463332 020542 0ustar00hansenhansen000000 000000 starting Fibonacci m[0] = 1 m[1] = 1 m[2] = 2 m[3] = 3 m[4] = 5 m[5] = 8 m[6] = 13 m[7] = 21 m[8] = 34 m[9] = 55 m[10] = 89 m[11] = 144 m[12] = 233 m[13] = 377 m[14] = 610 m[15] = 987 m[16] = 1597 m[17] = 2584 m[18] = 4181 m[19] = 6765 tkgate-2.0-b10/test/verga/fibonacci.v000644 001751 001751 00000000474 10132521272 020175 0ustar00hansenhansen000000 000000 module top; integer i; reg [31:0] m[0:1024]; initial begin $display("starting Fibonacci"); m[0] = 1; m[1] = 1; for (i = 2;i < 20;i = i + 1) begin m[i] = m[i-1] + m[i-2]; end for (i = 0;i < 20;i = i + 1) begin $display("m[%d] = %d",i,m[i]); end end endmodule tkgate-2.0-b10/test/verga/fork1.out000644 001751 001751 00000000041 10505463332 017640 0ustar00hansenhansen000000 000000 got a got b got c done with fork tkgate-2.0-b10/test/verga/grammar.out000644 001751 001751 00000000000 10505463332 020237 0ustar00hansenhansen000000 000000 tkgate-2.0-b10/test/verga/grammar.v000644 001751 001751 00000001704 10124170366 017710 0ustar00hansenhansen000000 000000 module bar #(.delay1(4)) (a,b,c,z); assign #delay1 z = a & b & c; endmodule module var #(delay1 = 4) (a,b,c,z); assign #delay1 z = a & b & c; endmodule module foo(a,b,c,z); input [3:0] a,b,c; output z; reg [7:0] m[0:65536]; assign #1 a = b & c | d & e; foo #(.a(1), .b(3)) f1[3:0] (a,b), g1(.i(d), .o(e)); always @(a or b) begin:foo #3 b = c + 2; #4 a = 1 + 2; a = #6 1 + 2; z <= #6 1 + 2; if (a > b) begin a = b + c; v = x + c; end else h = a + k; case (s) 8'h7z: u = r + 4; 8'h?9: begin u = r + 9; r = u - 1; end default: u = r + 1; endcase end initial begin for (i = 0;i < 10;i = i + 1) x = x + i; while (e < a) e = w; @(posedge CLK) w = e; repeat (20) e = w; repeat (20) @ (posedge CLK); // fork // @ (posedge A); // @ (posedge B); // join end endmodule module \module ; endmoduletkgate-2.0-b10/test/verga/loops.out000644 001751 001751 00000001034 10505463332 017755 0ustar00hansenhansen000000 000000 starting top.f1 with delay 1. starting top.f2 with delay 2. This is a hello world test string 23. if statment got a 'then' because 9 > 5 . while i = 0 while i = 1 while i = 2 while i = 3 while i = 4 for i = 3 for i = 4 for i = 5 for i = 6 for i = 7 for i = 8 for i = 9 top done @0. in top.f1 i = 0 @ 1 in top.f2 i = 0 @ 2 in top.f1 i = 1 @ 2 in top.f1 i = 2 @ 3 in top.f2 i = 1 @ 4 in top.f1 i = 3 @ 4 in top.f1 i = 4 @ 5 in top.f2 i = 2 @ 6 in top.f1 i = 5 @ 6 in top.f2 i = 3 @ 8 in top.f2 i = 4 @ 10 in top.f2 i = 5 @ 12 tkgate-2.0-b10/test/verga/loops.v000644 001751 001751 00000002007 10126161555 017415 0ustar00hansenhansen000000 000000 module top #(.xyz(9)); integer i; reg [7:0] a,b,c; reg [63:0] s; reg q; initial begin a = xyz; b = 5; c = a + b + 11; s = "abcd" + 8 ; $display("This is a hello world test string <%s> %d.","string tester",23); if (a > b) $display("if statment got a 'then' because %d > %d .",a,b); i = 0; while (i < 5) begin $display("while i = %d",i); i = i + 1; end for (i = 3;i < 10;i = i + 1) begin $display("for i = %d",i); end $display("top done @%d.",$time); end foo #(.delay(1)) f1(); foo #(.delay(2)) f2(); endmodule module foo #(.delay(1)) (); integer i; initial begin $display("starting %m with delay %d.",delay); for (i = 0;i <= 5;i = i + 1) #delay $display("in %m i = %d @ %d",i,$time); end endmodule module bar(); reg [7:0] a,b,c; parameter y = 8'h6; parameter q = {4'h5,4'h9,x,4'h3}; parameter r = {6{1'b1}}; parameter h = 13*3; endmodule tkgate-2.0-b10/test/verga/macro1.out000644 001751 001751 00000000614 10505463332 020006 0ustar00hansenhansen000000 000000 FOO-A-1 was included. [ok] BAR-A-1 was included. [ok] ARG-B-2 was included. [ok] BAR-B-3 was included. [ok] FOO-B-2 was included. [ok] FOO-C-1 was included. [ok] FOO-D-1 was included. [ok] BAR-D-1 was included. [ok] BAR-E-1 was included. [ok] FOO-F-1 was included. [ok] else-G-1 was included. [ok] FOO-H-1 was included. [ok] BAR-H-1 was included. [ok] FOO-H-2 was included. [ok] FOO=1234 r=4'h5 tkgate-2.0-b10/test/verga/macro1.v000644 001751 001751 00000010467 10312432121 017437 0ustar00hansenhansen000000 000000 `define FOO 1234 `define BAR 1 `define REG4 reg [3:0] `define BAR 1234 \ More text here `timescale 100 ns / 1 ns module top; `REG4 r; ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-A-1 was included. [ok]"); `endif `ifdef BAR initial $display("BAR-A-1 was included. [ok]"); `endif `ifdef ARG initial $display("ARG-A-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO `ifdef ARG initial $display("ARG-B-1 was included. [fail]"); `ifdef BAR initial $display("BAR-B-1 was included. [fail]"); `else initial $display("BAR-B-2 was included. [fail]"); `endif `else initial $display("ARG-B-2 was included. [ok]"); `ifdef BAR initial $display("BAR-B-3 was included. [ok]"); `else initial $display("BAR-B-4 was included. [fail]"); `endif `endif initial $display("FOO-B-2 was included. [ok]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef ARG initial $display("ARG-C-1 was included. [fail]"); `elseif FOO initial $display("FOO-C-1 was included. [ok]"); `elseif BAR initial $display("BAR-C-1 was included. [fail]"); `else initial $display("else-C-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-D-1 was included. [ok]"); `endif `ifdef BAR initial $display("BAR-D-1 was included. [ok]"); `endif `ifdef ARG initial $display("ARG-D-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef ARG initial $display("ARG-E-1 was included. [fail]"); `elseif XYZ initial $display("XYZ-E-1 was included. [fail]"); `elseif BAR initial $display("BAR-E-1 was included. [ok]"); `else initial $display("else-E-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef FOO initial $display("FOO-F-1 was included. [ok]"); `elseif BAR initial $display("BAR-F-1 was included. [fail]"); `elseif FOO initial $display("FOO-F-2 was included. [fail]"); `else initial $display("else-F-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef XYZ initial $display("XYZ-G-1 was included. [fail]"); `elseif DFG initial $display("DFG-G-1 was included. [fail]"); `elseif QWE initial $display("QWE-G-1 was included. [fail]"); `else initial $display("else-G-1 was included. [ok]"); `endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// `ifdef XYZ initial $display("XYZ-H-1 was included. [fail]"); `elseif FOO initial $display("FOO-H-1 was included. [ok]"); `ifdef BAR initial $display("BAR-H-1 was included. [ok]"); `ifdef FOO initial $display("FOO-H-2 was included. [ok]"); `else initial $display("FOO-H-3 was included. [fail]"); `endif `else initial $display("BAR-H-2 was included. [fail]"); `ifdef FOO initial $display("FOO-H-4 was included. [fail]"); `else initial $display("FOO-H-5 was included. [fail]"); `endif `endif `elseif QWE initial $display("QWE-H-1 was included. [fail]"); `ifdef BAR initial $display("BAR-H-3 was included. [fail]"); `ifdef FOO initial $display("FOO-H-6 was included. [fail]"); `else initial $display("FOO-H-7 was included. [fail]"); `endif `else initial $display("BAR-H-4 was included. [fail]"); `ifdef FOO initial $display("FOO-H-8 was included. [fail]"); `else initial $display("FOO-H-9 was included. [fail]"); `endif `endif `else initial $display("else-H-1 was included. [fail]"); `endif ///////////////////////////////////////////////////////////////////////////// initial begin r=5; $display("FOO=%d r=",`FOO,r); end endmodule tkgate-2.0-b10/test/verga/maketests.sh000755 001751 001751 00000000133 10504616070 020424 0ustar00hansenhansen000000 000000 #!/bin/sh for f in *.v; do echo "making $f ... " ../verga -q $f > ${f%.v}.out done tkgate-2.0-b10/test/verga/memory1.out000644 001751 001751 00000000203 10505463332 020207 0ustar00hansenhansen000000 000000 #### starting memory bit-range #### m[0][7:0]=78 #### m[0][15:8]=56 #### r[7:0]=78 #### r[15:8]=56 #### m[0]=12aa5678 #### m[0]=aa tkgate-2.0-b10/test/verga/memory1.v000644 001751 001751 00000001106 10132715617 017652 0ustar00hansenhansen000000 000000 module top; parameter N = 32; reg [N-1:0] m[0:1024]; reg [N-1:0] r; initial begin $display("#### starting memory bit-range"); m[0] = 32'h12345678; r = 32'h12345678; $display("#### m[0][7:0]=%h",m[0][7:0]); $display("#### m[0][15:8]=%h",m[0][15:8]); $display("#### r[7:0]=%h",r[7:0]); $display("#### r[15:8]=%h",r[15:8]); m[0][23:16] = 16'haa; $display("#### m[0]=%h",m[0]); m[0] = 8'haa; $display("#### m[0]=%h",m[0]); end always @(m) begin $display("m event"); end endmodule tkgate-2.0-b10/test/verga/memory2.out000644 001751 001751 00000000313 10505463332 020212 0ustar00hansenhansen000000 000000 m[0] = 3 m[1] = 4 m[2] = 9 m[3] = 16 m[4] = 25 m[5] = 36 m[6] = 49 m[7] = 64 m[8] = 81 m[9] = x m[10] = x m[11] = x m[12] = 100 m[13] = x m[14] = x m[15] = 99 m[16] = z m[17] = 12 m[18] = x8 m[19] = z12 tkgate-2.0-b10/test/verga/memory2.v000644 001751 001751 00000000404 10132765240 017650 0ustar00hansenhansen000000 000000 module top; parameter N = 32; reg [N-1:0] m[0:1024]; integer i; initial begin $readmemh("test.mem"); for (i = 0;i < 20;i = i + 1) $display("m[%d] = %h",i,m[i]); end always @(m) begin $display("m event"); end endmodule tkgate-2.0-b10/test/verga/minmax.out000644 001751 001751 00000000010 10505463332 020103 0ustar00hansenhansen000000 000000 2: done tkgate-2.0-b10/test/verga/minmax.v000644 001751 001751 00000000150 10504606303 017542 0ustar00hansenhansen000000 000000 module top; real n,a,b,c; initial begin #1:2:3 $display("%t: done",$time); end endmodule tkgate-2.0-b10/test/verga/module1.out000644 001751 001751 00000000214 10505463332 020166 0ustar00hansenhansen000000 000000 hello from foo ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 ck=1 ck=0 tkgate-2.0-b10/test/verga/module1.v000644 001751 001751 00000000376 10126414576 017642 0ustar00hansenhansen000000 000000 module top; reg ck; always begin #20 ck = ~ck; end always @(ck) $display("ck=%b",ck); initial begin ck = 1'b0; #500 $finish; end foo f1; endmodule module foo; initial $display("hello from foo"); endmodule tkgate-2.0-b10/test/verga/module2.out000644 001751 001751 00000000202 10505463332 020164 0ustar00hansenhansen000000 000000 0 = 0 ^ 0 ^ 0 1 = 0 ^ 1 ^ 0 1 = 1 ^ 0 ^ 0 0 = 1 ^ 1 ^ 0 1 = 0 ^ 0 ^ 1 0 = 0 ^ 1 ^ 1 0 = 1 ^ 0 ^ 1 1 = 1 ^ 1 ^ 1 11 = 3 + 8 l=bz tkgate-2.0-b10/test/verga/module2.v000644 001751 001751 00000002077 10126414320 017626 0ustar00hansenhansen000000 000000 module top; wire w1,w2; reg p,q,r; reg [3:0] m,n; wire [1:0] s,v; wire [7:0] l; foo f1 (.z(w1),.b(w2),.a(r)); foo f2 (w2,p,q); bar b1 ({s,v},m,n); bar b2 (l[7:4],m,n); initial begin p = 1'b0; q = 1'b0; r= 1'b0; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b0; q = 1'b1; r= 1'b0; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b1; q = 1'b0; r= 1'b0; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b1; q = 1'b1; r= 1'b0; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b0; q = 1'b0; r= 1'b1; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b0; q = 1'b1; r= 1'b1; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b1; q = 1'b0; r= 1'b1; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); p = 1'b1; q = 1'b1; r= 1'b1; #1 $display("%b = %b ^ %b ^ %b",w1,p,q,r); m = 3; n = 8; #1 $display("%d = %d + %d l=%h",{s,v},m,n,l); end endmodule module foo(z,a,b); output z; input a; input b; assign z = a ^ b; endmodule module bar(z,a,b); output [3:0] z; input [3:0] a; input [3:0] b; assign z = a + b; endmodule tkgate-2.0-b10/test/verga/monitor1.out000644 001751 001751 00000000455 10505463332 020377 0ustar00hansenhansen000000 000000 0: &: 0 |: 0 ^: 0 ~&: 1 ~|: 1 ~^: 1 4: &: 0 |: 1 ^: 1 ~&: 1 ~|: 0 ~^: 0 7: &: 0 |: 1 ^: 1 ~&: 1 ~|: 0 ~^: 0 ff: &: 1 |: 1 ^: 0 ~&: 0 ~|: 0 ~^: 1 fz: &: x |: 1 ^: x ~&: x ~|: 0 ~^: x 8z: &: 0 |: 1 ^: x ~&: 1 ~|: 0 ~^: x 0z: &: 0 |: x ^: x ~&: 1 ~|: x ~^: x tkgate-2.0-b10/test/verga/monitor1.v000644 001751 001751 00000000607 10132335102 020021 0ustar00hansenhansen000000 000000 module top; reg [7:0] a,o,x,b,no,nx,na; assign a = & b; assign o = | b; assign x = ^ b; assign na = ~& b; assign no = ~| b; assign nx = ~^ b; initial $monitor("%2h: &:%2h |:%2h ^:%2h ~&:%2h ~|:%2h ~^:%2h",b,a,o,x,na,no,nx); initial begin #1 b = 8'h0; #1 b = 8'h4; #1 b = 8'h7; #1 b = 8'hff; #1 b = 8'hfz; #1 b = 8'h8z; #1 b = 8'h0z; end endmodule tkgate-2.0-b10/test/verga/multedge.out000644 001751 001751 00000000156 10505463332 020433 0ustar00hansenhansen000000 000000 0: Q=z D=42 EN=0 CLR=1 1: Q=x D=42 EN=0 CLR=1 5: Q=42 D=42 EN=0 CLR=1 6: Q=42 D=19 EN=1 CLR=1 tkgate-2.0-b10/test/verga/multedge.v000644 001751 001751 00000001152 10133215320 020053 0ustar00hansenhansen000000 000000 module top; wire [7:0] Q; reg [7:0] D; reg EN,CLR,CK; _GGREG8 g1(Q,D,EN,CLR,CK); initial begin $monitor("%2d: Q=%h D=%h EN=%h CLR=%h",$time,Q,D,EN,CLR); CLR = 1'b1; EN = 1'b0; CK = 1'b0; D = 7'h42; #3; #1 CK = 1'b1; #2 CK = 1'b0; D = 7'h99; EN = 1'b1; #1 CK = 1'b1; #2 CK = 1'b0; end endmodule module _GGREG8 #(Dsetup=1, Dhold=1, Dck_q=1) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (!CLR) Qreg = 0; else if (CK && ~EN) Qreg = D; endmodule tkgate-2.0-b10/test/verga/ndassign1.V000644 001751 001751 00000000453 10223001241 020072 0ustar00hansenhansen000000 000000 module top; reg[31:0] r,a,q; integer i; initial begin a = 0; // // Using this statment should result in r=0 // q <= 8; r = #2 a; // // Using this statment should result in r=2 // // #2 r = a; $display("r=%d",r); end initial begin #1 a = 2; end endmodule tkgate-2.0-b10/test/verga/ndassign2.out000644 001751 001751 00000000145 10505463332 020513 0ustar00hansenhansen000000 000000 2: a=1 b=2 3: a=2 b=1 4: a=2 b=1 5: a=2 b=1 6: a=1 b=1 7: a=1 b=2 8: a=1 c=1 9: a=3 c=2 10: a=3 c=2 tkgate-2.0-b10/test/verga/ndassign2.v000644 001751 001751 00000001167 10126574162 020161 0ustar00hansenhansen000000 000000 // // Non-blocking assignment test. // module top; reg[31:0] a,b,c; integer i; initial begin #1 a = 1; #1 b = 2; $display("%d: a=%d b=%d",$time,a,b); a <= b; b <= a; #1 $display("%d: a=%d b=%d",$time,a,b); a <= #2 b; b <= #3 a; #1 $display("%d: a=%d b=%d",$time,a,b); #1 $display("%d: a=%d b=%d",$time,a,b); #1 $display("%d: a=%d b=%d",$time,a,b); #1 $display("%d: a=%d b=%d",$time,a,b); $display(""); c = 1; c <= @(a) 2; a <= #2 3; #1 $display("%d: a=%d c=%d",$time,a,c); @(c) $display("%d: a=%d c=%d",$time,a,c); #1 $display("%d: a=%d c=%d",$time,a,c); end endmodule tkgate-2.0-b10/test/verga/ops1.out000644 001751 001751 00000001133 10505463332 017503 0ustar00hansenhansen000000 000000 1652763623*1287368762*2763876432 = 5880744822841760707820497632 x=18446462594437873665 x=fffeffff00000001 x=4294967296 x=100000000 1652763623 * 1287368762 / 2763876432 = 769830457 625376212786237651312 / 127834612723233768273 = 4 625376212786237651312 % 127834612723233768273 = 114037761893302578220 625376212786237651312 / 728176123827834612723233768273 = 0 625376212786237651312 % 728176123827834612723233768273 = 625376212786237651312 625376212786237651312 >> 2 = 156344053196559412828 625376212786237651312 << 2 = 2501504851144950605248 625376212786237651312 << 33 = 5371940763226455502537782984704 tkgate-2.0-b10/test/verga/ops1.v000644 001751 001751 00000001320 10255613123 017134 0ustar00hansenhansen000000 000000 module top; reg [127:0] x,a,b,c; reg[31:0] y; initial begin a = 1652763623; b = 1287368762; c = 2763876432; x = a*b*c; $display("%d*%d*%d = %d",a,b,c,x); x = 32'hffffffff * 32'hffffffff; $display("x=%d x=%h",x,x); x = 32'hffffffff + 1; $display("x=%d x=%h",x,x); $display("%d * %d / %d = %d",a,b,c,a*b/c); a = 625376212786237651312; b = 127834612723233768273; $display("%d / %d = %d",a,b,a/b); $display("%d %% %d = %d",a,b,a%b); a = 625376212786237651312; b = 728176123827834612723233768273; $display("%d / %d = %d",a,b,a/b); $display("%d %% %d = %d",a,b,a%b); $display("%d >> 2 = %d",a,a>>2); $display("%d << 2 = %d",a,a<<2); $display("%d << 33 = %d",a,a<<33); end endmodule tkgate-2.0-b10/test/verga/parmassign1.out000644 001751 001751 00000000422 10505463332 021046 0ustar00hansenhansen000000 000000 w1=x w2=x p=x q=x f1.v=0 f2.v=0 w1=0 w2=0 p=0 q=0 f1.v=0 f2.v=0 w1=1 w2=1 p=0 q=1 f1.v=0 f2.v=0 w1=1 w2=1 p=1 q=0 f1.v=0 f2.v=0 changeing f1.v w1=1 w2=0 p=1 q=1 f1.v=1 f2.v=0 w1=1 w2=0 p=0 q=0 f1.v=1 f2.v=0 w1=0 w2=1 p=0 q=1 f1.v=1 f2.v=0 tkgate-2.0-b10/test/verga/parmassign1.v000644 001751 001751 00000001157 10255404371 020512 0ustar00hansenhansen000000 000000 module top; wire w1,w2; reg p,q; foo f1 (.z(w1),.b(p),.a(q)); foo f2 (.z(w2),.b(p),.a(q)); initial $monitor("w1=%b w2=%b p=%b q=%b f1.v=%b f2.v=%b",w1,w2,p,q,top.f1.v,top.f2.v); initial $stop(7); initial begin #1 p = 1'b0; q = 1'b0; #1 p = 1'b0; q = 1'b1; #1 p = 1'b1; q = 1'b0; #1 p = 1'b1; q = 1'b1; $display("changeing f1.v"); top.f1.v = 1'b1; #1 p = 1'b0; q = 1'b0; #1 p = 1'b0; q = 1'b1; #1 p = 1'b1; q = 1'b0; #1 p = 1'b1; q = 1'b1; #1; end endmodule module foo(z,a,b); output z; input a; input b; reg v; initial v = 0; assign z = a ^ b ^ v; endmodule tkgate-2.0-b10/test/verga/probe1.out000644 001751 001751 00000001516 11150663304 020014 0ustar00hansenhansen000000 000000 valueof top.a 32'hx @ 0 valueof top.i 32'hx @ 0 tell bob top.i 32'h0 @ 0 tell bob top.a 32'h0 @ 0 tell bob top.i 32'h1 @ 1 tell bob top.i 32'h2 @ 2 tell bob top.a 32'h2 @ 2 tell bob top.i 32'h3 @ 3 tell bob top.i 32'h4 @ 4 tell bob top.a 32'h4 @ 4 tell bob top.i 32'h5 @ 5 tell bob top.i 32'h6 @ 6 tell bob top.a 32'h6 @ 6 tell bob top.i 32'h7 @ 7 tell bob top.i 32'h8 @ 8 tell bob top.a 32'h8 @ 8 tell bob top.i 32'h9 @ 9 tell bob top.i 32'ha @ 10 tell bob top.a 32'ha @ 10 tell bob top.i 32'hb @ 11 tell bob top.i 32'hc @ 12 tell bob top.a 32'hc @ 12 tell bob top.i 32'hd @ 13 tell bob top.i 32'he @ 14 tell bob top.a 32'he @ 14 tell bob top.i 32'hf @ 15 tell bob top.i 32'h10 @ 16 tell bob top.a 32'h10 @ 16 tell bob top.i 32'h11 @ 17 tell bob top.i 32'h12 @ 18 tell bob top.a 32'h12 @ 18 tell bob top.i 32'h13 @ 19 tell bob top.i 32'h14 @ 20 tkgate-2.0-b10/test/verga/probe1.v000644 001751 001751 00000000272 10476352510 017454 0ustar00hansenhansen000000 000000 module top; integer i,a; initial begin $tkg$probe("bob",a,i); for (i = 0;i < 20;i = i + 1) begin if ( (i & 1) == 0) a <= i; #1; end end endmodule tkgate-2.0-b10/test/verga/random.out000644 001751 001751 00000000315 10505463332 020102 0ustar00hansenhansen000000 000000 44994396 745292378 254439306 10387488 1043940580 803319250 1235240792 1971986270 910734285 968931565 1619240249 337416194 1816805055 2138790185 1228100076 188749511 907455839 734581784 539825845 606952975 tkgate-2.0-b10/test/verga/random.v000644 001751 001751 00000000146 10252207456 017544 0ustar00hansenhansen000000 000000 module top; initial begin $random(100); repeat (20) $display($random); end endmodule tkgate-2.0-b10/test/verga/real1.out000644 001751 001751 00000000514 10505463332 017627 0ustar00hansenhansen000000 000000 The number is 15 (should be 15) The number is 5.1 (should be 5.1) The number is 3.5 (should be 3.5) The number is 12.65 (should be 12.65) The number is 0.333333 (should be 0.333333) The number is -1 (should be -1) The number is 2 (should be 2) Expecting 1, got 1 Expecting 1.2, got 1.2 Expecting 32'h1, got 32'h1 Expecting 1, got 1 tkgate-2.0-b10/test/verga/real1.v000644 001751 001751 00000001322 10505463147 017267 0ustar00hansenhansen000000 000000 module top; real n,a,b,c; integer i; reg [31:0] r; initial begin n = 8'hf; $display("The number is %g (should be 15)",n); n = 1.1 + 4; $display("The number is %g (should be 5.1)",n); a = 1.2; b = 2.3; c = a + b; $display("The number is %g (should be 3.5)",c); $display("The number is %g (should be 12.65)",(1.2+1.1)*(2.3+3.2)); a = 1; b = 3; $display("The number is %g (should be 0.333333)",a/b); $display("The number is %g (should be -1)",-a); $display("The number is %g (should be 2)",b-a); a = 1.2; i = 1; $display("Expecting 1, got ",i); $display("Expecting 1.2, got ",a); r = 1.2; $display("Expecting 32'h1, got ",r); a = r; $display("Expecting 1, got ",a); end endmodule tkgate-2.0-b10/test/verga/runtests.sh000755 001751 001751 00000000521 10521265644 020322 0ustar00hansenhansen000000 000000 #!/bin/sh VERGA=../../src/verga/verga PASS=0 FAIL=0 for f in *.v; do echo -n "checking $f ... " $VERGA -q $f > verga.out if diff -q verga.out ${f%.v}.out 1> /dev/null; then echo "ok" PASS=`expr $PASS + 1` else echo "failed" FAIL=`expr $FAIL + 1` fi done echo ">>> $PASS tests passed. $FAIL tests failed." tkgate-2.0-b10/test/verga/shift.out000644 001751 001751 00000003752 10505463332 017747 0ustar00hansenhansen000000 000000 Starting shift test 1 << 0 == 00000001 1 << 1 == 00000002 1 << 2 == 00000004 1 << 3 == 00000008 1 << 4 == 00000010 1 << 5 == 00000020 1 << 6 == 00000040 1 << 7 == 00000080 1 << 8 == 00000100 1 << 9 == 00000200 1 << 10 == 00000400 1 << 11 == 00000800 1 << 12 == 00001000 1 << 13 == 00002000 1 << 14 == 00004000 1 << 15 == 00008000 1 << 16 == 00010000 1 << 17 == 00020000 1 << 18 == 00040000 1 << 19 == 00080000 1 << 20 == 00100000 1 << 21 == 00200000 1 << 22 == 00400000 1 << 23 == 00800000 1 << 24 == 01000000 1 << 25 == 02000000 1 << 26 == 04000000 1 << 27 == 08000000 1 << 28 == 10000000 1 << 29 == 20000000 1 << 30 == 40000000 1 << 31 == 80000000 1 << 32 == 00000000 1 << 33 == 00000000 1 << 34 == 00000000 1 << 35 == 00000000 1 << 36 == 00000000 1 << 37 == 00000000 1 << 38 == 00000000 1 << 39 == 00000000 1 << 40 == 00000000 1 << 41 == 00000000 1 << 42 == 00000000 1 << 43 == 00000000 1 << 44 == 00000000 1 << 45 == 00000000 1 << 46 == 00000000 1 << 47 == 00000000 1 << 48 == 00000000 1 << 49 == 00000000 1 << 50 == 00000000 1 << 51 == 00000000 1 << 52 == 00000000 1 << 53 == 00000000 1 << 54 == 00000000 1 << 55 == 00000000 1 << 56 == 00000000 1 << 57 == 00000000 1 << 58 == 00000000 1 << 59 == 00000000 1 << 60 == 00000000 1 << 61 == 00000000 1 << 62 == 00000000 1 << 63 == 00000000 i = deadbeef i = eadbeef0 i = adbeef00 i = dbeef000 i = beef0000 i = eef00000 i = ef000000 i = f0000000 i = deadbeef i = 0deadbee i = 00deadbe i = 000deadb i = 0000dead i = 00000dea i = 000000de i = 0000000d big<<4 = 123456789abcdefdeadbeefcafebabe0 big<<32 = 89abcdefdeadbeefcafebabe00000000 big<<39 = d5e6f7ef56df77e57f5d5f0000000000 big<<64 = deadbeefcafebabe0000000000000000 big<<68 = eadbeefcafebabe00000000000000000 big<<200 = 00000000000000000000000000000000 big>>4 = 00123456789abcdefdeadbeefcafebab big>>32 = 000000000123456789abcdefdeadbeef big>>39 = 000000000002468acf13579bdfbd5b7d big>>64 = 00000000000000000123456789abcdef big>>68 = 000000000000000000123456789abcde big>>200 = 00000000000000000000000000000000 tkgate-2.0-b10/test/verga/shift.v000644 001751 001751 00000001765 10223001226 017372 0ustar00hansenhansen000000 000000 module top; reg [127: 0] big; reg [31:0] i; integer j; initial begin $display("Starting shift test"); for (j=0; j<64; j = j + 1) begin $display("1 << %d == %08h", j, 1<> 4; end big = 128'h0123456789abcdefdeadbeefcafebabe; $display("big<<4 = %032h", big<<4); $display("big<<32 = %032h", big<<32); $display("big<<39 = %032h", big<<39); $display("big<<64 = %032h", big<<64); $display("big<<68 = %032h", big<<68); $display("big<<200 = %032h", big<<200); $display("big>>4 = %032h", big>>4); $display("big>>32 = %032h", big>>32); $display("big>>39 = %032h", big>>39); $display("big>>64 = %032h", big>>64); $display("big>>68 = %032h", big>>68); $display("big>>200 = %032h", big>>200); end endmodule tkgate-2.0-b10/test/verga/simple1.out000644 001751 001751 00000001116 10505463332 020174 0ustar00hansenhansen000000 000000 Starting SUM test s0=0 s1=0 c2=1 sum: 100 = 10 + 1 + 1 Starting tri-state z = buf(0)if(0) ++ buf(0)if(0) z = buf(1)if(0) ++ buf(0)if(0) 0 = buf(0)if(1) ++ buf(0)if(0) 1 = buf(1)if(1) ++ buf(0)if(0) z = buf(0)if(0) ++ buf(1)if(0) z = buf(1)if(0) ++ buf(1)if(0) 0 = buf(0)if(1) ++ buf(1)if(0) 1 = buf(1)if(1) ++ buf(1)if(0) 0 = buf(0)if(0) ++ buf(0)if(1) 0 = buf(1)if(0) ++ buf(0)if(1) 0 = buf(0)if(1) ++ buf(0)if(1) x = buf(1)if(1) ++ buf(0)if(1) 1 = buf(0)if(0) ++ buf(1)if(1) 1 = buf(1)if(0) ++ buf(1)if(1) x = buf(0)if(1) ++ buf(1)if(1) 1 = buf(1)if(1) ++ buf(1)if(1) tkgate-2.0-b10/test/verga/simple1.v000644 001751 001751 00000001555 10124543560 017640 0ustar00hansenhansen000000 000000 module top; reg c2; reg s1, a1, b1, c1; reg s0, a0, b0, c0; reg x; integer i; assign s0 = a0 ^ b0 ^ c0; assign s1 = a1 ^ b1 ^ c1; assign c1 = a0 & b0 | a0 & c0 | b0 & c0; assign c2 = a1 & b1 | a1 & c1 | b1 & c1; assign x = a1 ? a0 : 1'bz; assign x = b1 ? b0 : 1'bz; initial begin $display("Starting SUM test"); c0 = 1; a1 = 1; a0 = 0; b1 = 0; b0 = 1; #1 ; $display("s0=%b ",s0); $display("s1=%b ",s1); $display("c2=%b ",c2); $display("sum: %b = %b + %b + %b",{c2,s1,s0},{a1,a0},{b1,b0},c0); $display(""); $display("Starting tri-state"); for (i = 0;i < 16;i = i + 1) begin a0 = (i & 8'h1) != 0; a1 = (i & 8'h2) != 0; b0 = (i & 8'h4) != 0; b1 = (i & 8'h8) != 0; #1 ; $display("%b = buf(%b)if(%b) ++ buf(%b)if(%b)",x,a0,a1,b0,b1); end end endmodule tkgate-2.0-b10/test/verga/simple2.out000644 001751 001751 00000000023 10505463332 020171 0ustar00hansenhansen000000 000000 sum: 0 = 0 + 0 + 0 tkgate-2.0-b10/test/verga/simple2.v000644 001751 001751 00000000535 10124571150 017632 0ustar00hansenhansen000000 000000 module top; reg s1,s0; reg a1,a0,b1,b0,c2,c1,c0; assign s0 = a0 ^ b0 ^ c0; assign s1 = a1 ^ b1 ^ c1; assign c1 = a0 & b0 | a0 & c0 | b0 & c0; assign c2 = a1 & b1 | a1 & c1 | b1 & c1; initial begin a0 = 0; a1 = 0; b0 = 0; b1 = 0; c0 = 0; #1 $display("sum: %b = %b + %b + %b",{c2,s1,s0},{a1,a0},{b1,b0},c0); end endmodule tkgate-2.0-b10/test/verga/spec.out000644 001751 001751 00000001340 10505463332 017553 0ustar00hansenhansen000000 000000 0: a=0 b=0 c=0 - x=z y=z z=z 8: a=0 b=0 c=0 - x=x y=z z=z 11: a=0 b=0 c=0 - x=x y=0 z=z 12: a=0 b=0 c=0 - x=0 y=0 z=z 18: a=0 b=0 c=0 - x=0 y=0 z=0 50: a=0 b=0 c=1 - x=0 y=0 z=0 100: a=0 b=1 c=0 - x=0 y=0 z=0 112: a=0 b=1 c=0 - x=1 y=0 z=0 150: a=0 b=1 c=1 - x=1 y=0 z=0 168: a=0 b=1 c=1 - x=1 y=0 z=1 200: a=1 b=0 c=0 - x=1 y=0 z=1 211: a=1 b=0 c=0 - x=1 y=1 z=1 216: a=1 b=0 c=0 - x=1 y=0 z=1 218: a=1 b=0 c=0 - x=1 y=0 z=0 250: a=1 b=0 c=1 - x=1 y=0 z=0 266: a=1 b=0 c=1 - x=1 y=1 z=0 300: a=1 b=1 c=0 - x=1 y=1 z=0 312: a=1 b=1 c=0 - x=0 y=1 z=0 316: a=1 b=1 c=0 - x=0 y=0 z=0 350: a=1 b=1 c=1 - x=0 y=0 z=0 358: a=1 b=1 c=1 - x=1 y=0 z=0 366: a=1 b=1 c=1 - x=1 y=1 z=0 368: a=1 b=1 c=1 - x=1 y=1 z=1 tkgate-2.0-b10/test/verga/spec.v000644 001751 001751 00000001164 10436223406 017214 0ustar00hansenhansen000000 000000 module top; integer i; reg a,b,c; wire x,y,z; initial $monitor("%4d: a=%b b=%b c=%b - x=%b y=%b z=%b",$time,a,b,c,x,y,z); initial for (i = 0;i < 8;i = i + 1) begin {a,b,c} = i; #50; // $finish(); end foo f(a,b,c,x,y,z); endmodule module foo(a,b,c,x,y,z); input a,b,c; output x,y,z; wire q,r; specify (a,b *> x) = 12; (c *> x) = 8; (a *> y) = 11; (c *> y) = 16; (b *> z) = 23; (c *> z) = 18; endspecify // and (r, q, c); // xor (x, a, b, r); assign r = q & c; assign x = a ^ b ^ r; assign y = a & c; assign z = c & b; assign q = a & b; endmodule tkgate-2.0-b10/test/verga/spec1.out000644 001751 001751 00000000264 10505463332 017640 0ustar00hansenhansen000000 000000 0: a=0 b=0 - x=x 21: a=0 b=0 - x=0 50: a=0 b=1 - x=0 62: a=0 b=1 - x=1 100: a=1 b=0 - x=1 110: a=1 b=0 - x=0 112: a=1 b=0 - x=1 150: a=1 b=1 - x=1 162: a=1 b=1 - x=0 tkgate-2.0-b10/test/verga/spec1.v000644 001751 001751 00000000622 10436367656 017313 0ustar00hansenhansen000000 000000 module top; integer i; reg a,b; wire x; initial $monitor("%4d: a=%b b=%b - x=%b",$time,a,b,x); initial for (i = 0;i < 4;i = i + 1) begin {a,b} = i; #50; // $finish(); end foo f(a,b,x); endmodule module foo(a,b,x); input a,b; output x; specify if (a) (a *> x) = 10; if (!a) (a *> x) = 21; (b *> x) = 12; endspecify assign x = a ^ b; endmodule tkgate-2.0-b10/test/verga/spec4.out000644 001751 001751 00000002176 10505463332 017647 0ustar00hansenhansen000000 000000 Warning: <"spec4.v", 18> Port size mismatch on input port 'A'. Warning: <"spec4.v", 18> Port size mismatch on input port 'B'. Warning: <"spec4.v", 18> Port size mismatch on output port 'S'. 0: a=0 b=0 ci=0 - s=x co=x 1: a=0 b=0 ci=0 - s=0 co=0 100: a=0 b=1 ci=0 - s=0 co=0 101: a=0 b=1 ci=0 - s=1 co=0 200: a=0 b=2 ci=0 - s=1 co=0 201: a=0 b=2 ci=0 - s=2 co=0 300: a=0 b=3 ci=0 - s=2 co=0 301: a=0 b=3 ci=0 - s=3 co=0 400: a=1 b=0 ci=0 - s=3 co=0 401: a=1 b=0 ci=0 - s=1 co=0 500: a=1 b=1 ci=0 - s=1 co=0 501: a=1 b=1 ci=0 - s=2 co=0 600: a=1 b=2 ci=0 - s=2 co=0 601: a=1 b=2 ci=0 - s=3 co=0 700: a=1 b=3 ci=0 - s=3 co=0 701: a=1 b=3 ci=0 - s=0 co=0 800: a=2 b=0 ci=0 - s=0 co=0 801: a=2 b=0 ci=0 - s=2 co=0 900: a=2 b=1 ci=0 - s=2 co=0 901: a=2 b=1 ci=0 - s=3 co=0 1000: a=2 b=2 ci=0 - s=3 co=0 1001: a=2 b=2 ci=0 - s=0 co=0 1100: a=2 b=3 ci=0 - s=0 co=0 1101: a=2 b=3 ci=0 - s=1 co=0 1200: a=3 b=0 ci=0 - s=1 co=0 1201: a=3 b=0 ci=0 - s=3 co=0 1300: a=3 b=1 ci=0 - s=3 co=0 1301: a=3 b=1 ci=0 - s=0 co=0 1400: a=3 b=2 ci=0 - s=0 co=0 1401: a=3 b=2 ci=0 - s=1 co=0 1500: a=3 b=3 ci=0 - s=1 co=0 1501: a=3 b=3 ci=0 - s=2 co=0 tkgate-2.0-b10/test/verga/spec4.v000644 001751 001751 00000001014 10462030704 017266 0ustar00hansenhansen000000 000000 module top; integer i; reg ci = 1'b0; reg [1:0] a,b; wire [1:0] s; wire co; initial $monitor("%4d: a=%d b=%d ci=%d - s=%d co=%d",$time,a,b,ci,s,co); initial for (i = 0;i < 16;i = i + 1) begin {a,b} = i; #100; end _GGADD8 f(a,b,s,ci,co); endmodule module _GGADD8 (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = 1; (A,B *> CO) = 1; (CI *> S) = 1; (CI *> CO) = 1; endspecify assign {CO,S} = A + B + CI; endmodule tkgate-2.0-b10/test/verga/spec5.out000644 001751 001751 00000000410 10505463332 017635 0ustar00hansenhansen000000 000000 0: a=0 b=0 - x=x y=x 17: a=0 b=0 - x=x y=0 21: a=0 b=0 - x=0 y=0 100: a=0 b=1 - x=0 y=0 117: a=0 b=1 - x=0 y=1 200: a=1 b=0 - x=0 y=1 210: a=1 b=0 - x=1 y=1 212: a=1 b=0 - x=0 y=1 300: a=1 b=1 - x=0 y=1 312: a=1 b=1 - x=1 y=1 317: a=1 b=1 - x=1 y=0 tkgate-2.0-b10/test/verga/spec5.v000644 001751 001751 00000000704 10462030776 017305 0ustar00hansenhansen000000 000000 module top; integer i; reg a,b; wire x,y; initial $monitor("%4d: a=%d b=%d - x=%d y=%d",$time,a,b,x,y); initial for (i = 0;i < 4;i = i + 1) begin {a,b} = i; #100; end foo f(a,b,x,y); endmodule module foo #(.p1(10), .p2(21)) (a,b,x,y); input a,b; output x,y; specify if (a) (a *> x) = p1; if (!a) (a *> x) = p2; (b *> x) = 12; (a, b *> y) = 17; endspecify assign {x,y} = a + b; endmodule tkgate-2.0-b10/test/verga/string1.out000644 001751 001751 00000000434 10505463332 020213 0ustar00hansenhansen000000 000000 c=2 d=2 b=68 a=24 x=ABCDEFGHIJ x=4142434445464748494a x[7:0]=J x[15:8]=I x[23:16]=H x[31:24]=G x[39:32]=F x[47:40]=E x[55:48]=D x[63:56]=C x[71:64]=B x[79:72]=A x=64514031241910090401 y=01040910192431405164 hello i = 8 hello i = 14 hello i = 26 hello i = 50 hello i = 98 done hello tkgate-2.0-b10/test/verga/string1.v000644 001751 001751 00000001523 10125166135 017650 0ustar00hansenhansen000000 000000 module top; reg [7:0] a,b; reg [4:0] c,d; reg [10*8-1:0] x,y; integer i; initial begin a = 8'h42; {c,d} = a; $display("c=%h d=%h",c,d); b[7:4] = 4'h6; b[3:0] = 4'h8; $display("b=%h",b); {a[3:0],a[7:4]} = a & 8'hff; $display("a=%h",a); x = "ABCDEFGHIJ"; $display("x=%s x=%h",x,x); for (i = 0;i < 10;i = i+1) $display("x[%d:%d]=%s",8*i+7,8*i,x[8*i +: 8]); for (i = 0;i < 10;i = i+1) x[8*i +: 8] = (i+1)*(i+1); $display("x=%h",x); for (i = 0;i < 10;i = i+1) begin y[8*i +: 8] = x[8*(9-i) +: 8]; end $display("y=%020h",y); // // i should be read only on entering the loop so updates to i in // the body should not affect the number of iterations. // i = 5; repeat (i) begin i = 2*(i - 1); $display("hello i = %d",i); end $display("done hello"); end endmodule tkgate-2.0-b10/test/verga/string2.out000644 001751 001751 00000000504 10505463333 020213 0ustar00hansenhansen000000 000000 a=12345678 b=abcd0123 x=12345678abcd0123 c=12345678 d=abcd0123 a=345678 b=cd0123 x=345678cd0123 c=345678 d=cd0123 this is a test of some strings being concatenated. hello world! hello world! hello world! hello world! hello world! abcd abcd abcd abcd abcd abcd abcd abcd abcd abcd ABC:ABC:ABC:ABC: XYZ:XYZ:XYZ:XYZ: tkgate-2.0-b10/test/verga/string2.v000644 001751 001751 00000001517 10363166754 017667 0ustar00hansenhansen000000 000000 module top; M64 m64; M48 m48; S s; REP rep; endmodule module M64; reg [31:0] a,b,c,d; reg [63:0] x; initial begin a = 32'h12345678; b = 32'habcd0123; x = {a,b}; {c,d} = x; $display("a=%h b=%h x=%h c=%h d=%h",a,b,x,c,d); end endmodule module M48; reg [23:0] a,b,c,d; reg [47:0] x; initial begin a = 24'h345678; b = 24'hcd0123; x = {a,b}; {c,d} = x; $display("a=%h b=%h x=%h c=%h d=%h",a,b,x,c,d); end endmodule module S; initial begin $display("%s",{"this ","is ","a test"," of some strings"," being concatenated."}); end endmodule module REP; reg [159:0] s; wire [159:0] w; assign w = {4{"XYZ:"}}; initial begin $display("%s",{5{"hello world! "}}); $display("%s",{10{"abcd "}}); s = {4{"ABC:"}}; $display("%s",s); #1 $display("%s",w); end endmodule tkgate-2.0-b10/test/verga/strobe1.out000644 001751 001751 00000001553 10505463333 020207 0ustar00hansenhansen000000 000000 0: $display 2*a=x 0: $strobe 2*a=0 0: $monitor a=0 1: $display 2*a=0 1: $strobe 2*a=0 2: $display 2*a=0 2: $strobe 2*a=4 2: $monitor a=2 3: $display 2*a=4 3: $strobe 2*a=4 4: $display 2*a=4 4: $strobe 2*a=8 4: $monitor a=4 5: $display 2*a=8 5: $strobe 2*a=8 6: $display 2*a=8 6: $strobe 2*a=12 6: $monitor a=6 7: $display 2*a=12 7: $strobe 2*a=12 8: $display 2*a=12 8: $strobe 2*a=16 9: $display 2*a=16 9: $strobe 2*a=16 10: $display 2*a=16 10: $strobe 2*a=20 11: $display 2*a=20 11: $strobe 2*a=20 12: $display 2*a=20 12: $strobe 2*a=24 13: $display 2*a=24 13: $strobe 2*a=24 14: $display 2*a=24 14: $strobe 2*a=28 14: $monitor a=14 15: $display 2*a=28 15: $strobe 2*a=28 16: $display 2*a=28 16: $strobe 2*a=32 16: $monitor(2) 3*a=48 17: $display 2*a=32 17: $strobe 2*a=32 18: $display 2*a=32 18: $strobe 2*a=36 18: $monitor(2) 3*a=54 19: $display 2*a=36 19: $strobe 2*a=36 tkgate-2.0-b10/test/verga/strobe1.v000644 001751 001751 00000000644 10127034631 017640 0ustar00hansenhansen000000 000000 module top; integer i,a; initial begin $monitor("%d: $monitor a=%d",$time,a); for (i = 0;i < 20;i = i + 1) begin if ( (i & 1) == 0) a <= i; if (i == 8) $monitoroff; if (i == 14) $monitoron; if (i == 16) $monitor("%d: $monitor(2) 3*a=%d",$time,3*a); $display("%d: $display 2*a=%d",$time,2*a); $strobe("%d: $strobe 2*a=%d",$time,2*a); #1; end end endmodule tkgate-2.0-b10/test/verga/sum1.out000644 001751 001751 00000002422 10505463333 017511 0ustar00hansenhansen000000 000000 Starting SUM test sum: 0 = 0 + 0 + 0 (0=0+0+0) sum: 1 = 1 + 0 + 0 (1=1+0+0) sum: 10 = 10 + 0 + 0 (2=2+0+0) sum: 11 = 11 + 0 + 0 (3=3+0+0) sum: 1 = 0 + 1 + 0 (1=0+1+0) sum: 10 = 1 + 1 + 0 (2=1+1+0) sum: 11 = 10 + 1 + 0 (3=2+1+0) sum: 100 = 11 + 1 + 0 (4=3+1+0) sum: 10 = 0 + 10 + 0 (2=0+2+0) sum: 11 = 1 + 10 + 0 (3=1+2+0) sum: 100 = 10 + 10 + 0 (4=2+2+0) sum: 101 = 11 + 10 + 0 (5=3+2+0) sum: 11 = 0 + 11 + 0 (3=0+3+0) sum: 100 = 1 + 11 + 0 (4=1+3+0) sum: 101 = 10 + 11 + 0 (5=2+3+0) sum: 110 = 11 + 11 + 0 (6=3+3+0) sum: 1 = 0 + 0 + 1 (1=0+0+1) sum: 10 = 1 + 0 + 1 (2=1+0+1) sum: 11 = 10 + 0 + 1 (3=2+0+1) sum: 100 = 11 + 0 + 1 (4=3+0+1) sum: 10 = 0 + 1 + 1 (2=0+1+1) sum: 11 = 1 + 1 + 1 (3=1+1+1) sum: 100 = 10 + 1 + 1 (4=2+1+1) sum: 101 = 11 + 1 + 1 (5=3+1+1) sum: 11 = 0 + 10 + 1 (3=0+2+1) sum: 100 = 1 + 10 + 1 (4=1+2+1) sum: 101 = 10 + 10 + 1 (5=2+2+1) sum: 110 = 11 + 10 + 1 (6=3+2+1) sum: 100 = 0 + 11 + 1 (4=0+3+1) sum: 101 = 1 + 11 + 1 (5=1+3+1) sum: 110 = 10 + 11 + 1 (6=2+3+1) sum: 111 = 11 + 11 + 1 (7=3+3+1) tkgate-2.0-b10/test/verga/sum1.v000644 001751 001751 00000001242 10126065335 017145 0ustar00hansenhansen000000 000000 module top; reg a1, b1; reg a0, b0, c0; wire s1, s0, c1, c2; integer i; // assign s1 = a1 ^ b1 ^ c1; // assign s0 = a0 ^ b0 ^ c0; assign {s1,s0} = {a1,a0} ^ {b1,b0} ^ {c1,c0}; assign c1 = a0 & b0 | a0 & c0 | b0 & c0; assign c2 = a1 & b1 | a1 & c1 | b1 & c1; initial begin $display("Starting SUM test"); for (i = 0;i < 32;i = i + 1) begin a0 = (i & 8'h1) != 0; a1 = (i & 8'h2) != 0; b0 = (i & 8'h4) != 0; b1 = (i & 8'h8) != 0; c0 = (i & 8'h10) != 0; #1 $display("sum: %3b = %2b + %2b + %2b (%d=%d+%d+%d)", {c2,s1,s0},{a1,a0},{b1,b0},c0, {c2,s1,s0},{a1,a0},{b1,b0},c0); end end endmodule tkgate-2.0-b10/test/verga/sum2.out000644 001751 001751 00000002422 10505463333 017512 0ustar00hansenhansen000000 000000 Starting SUM test sum: 0 = 0 + 0 + 0 (0=0+0+0) sum: 1 = 1 + 0 + 0 (1=1+0+0) sum: 10 = 10 + 0 + 0 (2=2+0+0) sum: 11 = 11 + 0 + 0 (3=3+0+0) sum: 1 = 0 + 1 + 0 (1=0+1+0) sum: 10 = 1 + 1 + 0 (2=1+1+0) sum: 11 = 10 + 1 + 0 (3=2+1+0) sum: 100 = 11 + 1 + 0 (4=3+1+0) sum: 10 = 0 + 10 + 0 (2=0+2+0) sum: 11 = 1 + 10 + 0 (3=1+2+0) sum: 100 = 10 + 10 + 0 (4=2+2+0) sum: 101 = 11 + 10 + 0 (5=3+2+0) sum: 11 = 0 + 11 + 0 (3=0+3+0) sum: 100 = 1 + 11 + 0 (4=1+3+0) sum: 101 = 10 + 11 + 0 (5=2+3+0) sum: 110 = 11 + 11 + 0 (6=3+3+0) sum: 1 = 0 + 0 + 1 (1=0+0+1) sum: 10 = 1 + 0 + 1 (2=1+0+1) sum: 11 = 10 + 0 + 1 (3=2+0+1) sum: 100 = 11 + 0 + 1 (4=3+0+1) sum: 10 = 0 + 1 + 1 (2=0+1+1) sum: 11 = 1 + 1 + 1 (3=1+1+1) sum: 100 = 10 + 1 + 1 (4=2+1+1) sum: 101 = 11 + 1 + 1 (5=3+1+1) sum: 11 = 0 + 10 + 1 (3=0+2+1) sum: 100 = 1 + 10 + 1 (4=1+2+1) sum: 101 = 10 + 10 + 1 (5=2+2+1) sum: 110 = 11 + 10 + 1 (6=3+2+1) sum: 100 = 0 + 11 + 1 (4=0+3+1) sum: 101 = 1 + 11 + 1 (5=1+3+1) sum: 110 = 10 + 11 + 1 (6=2+3+1) sum: 111 = 11 + 11 + 1 (7=3+3+1) tkgate-2.0-b10/test/verga/sum2.v000644 001751 001751 00000001116 10126140537 017144 0ustar00hansenhansen000000 000000 module top; parameter n = 2; reg [n-1:0] a, b; reg ci; wire [n-1:0] s; wire [n:0] c; integer i; assign c[0] = ci; assign s = a ^ b ^ c[n-1:0]; assign c[n:1] = a & b | a & c[n-1:0] | b & c[n-1:0]; initial begin $display("Starting SUM test"); for (i = 0;i < 32;i = i + 1) begin a[0] = (i & 8'h1) != 0; a[1] = (i & 8'h2) != 0; b[0] = (i & 8'h4) != 0; b[1] = (i & 8'h8) != 0; ci = (i & 8'h10) != 0; #100 $display("sum: %3b = %2b + %2b + %2b (%d=%d+%d+%d)",{c[2],s},a,b,c[0],{c[2],s},a,b,c[0]); end end endmodule tkgate-2.0-b10/test/verga/sum3.out000644 001751 001751 00000002422 10505463333 017513 0ustar00hansenhansen000000 000000 Starting SUM test sum: 0 = 0 + 0 + 0 (0=0+0+0) sum: 1 = 1 + 0 + 0 (1=1+0+0) sum: 10 = 10 + 0 + 0 (2=2+0+0) sum: 11 = 11 + 0 + 0 (3=3+0+0) sum: 1 = 0 + 1 + 0 (1=0+1+0) sum: 10 = 1 + 1 + 0 (2=1+1+0) sum: 11 = 10 + 1 + 0 (3=2+1+0) sum: 100 = 11 + 1 + 0 (4=3+1+0) sum: 10 = 0 + 10 + 0 (2=0+2+0) sum: 11 = 1 + 10 + 0 (3=1+2+0) sum: 100 = 10 + 10 + 0 (4=2+2+0) sum: 101 = 11 + 10 + 0 (5=3+2+0) sum: 11 = 0 + 11 + 0 (3=0+3+0) sum: 100 = 1 + 11 + 0 (4=1+3+0) sum: 101 = 10 + 11 + 0 (5=2+3+0) sum: 110 = 11 + 11 + 0 (6=3+3+0) sum: 1 = 0 + 0 + 1 (1=0+0+1) sum: 10 = 1 + 0 + 1 (2=1+0+1) sum: 11 = 10 + 0 + 1 (3=2+0+1) sum: 100 = 11 + 0 + 1 (4=3+0+1) sum: 10 = 0 + 1 + 1 (2=0+1+1) sum: 11 = 1 + 1 + 1 (3=1+1+1) sum: 100 = 10 + 1 + 1 (4=2+1+1) sum: 101 = 11 + 1 + 1 (5=3+1+1) sum: 11 = 0 + 10 + 1 (3=0+2+1) sum: 100 = 1 + 10 + 1 (4=1+2+1) sum: 101 = 10 + 10 + 1 (5=2+2+1) sum: 110 = 11 + 10 + 1 (6=3+2+1) sum: 100 = 0 + 11 + 1 (4=0+3+1) sum: 101 = 1 + 11 + 1 (5=1+3+1) sum: 110 = 10 + 11 + 1 (6=2+3+1) sum: 111 = 11 + 11 + 1 (7=3+3+1) tkgate-2.0-b10/test/verga/sum3.v000644 001751 001751 00000001113 10126127047 017143 0ustar00hansenhansen000000 000000 module top; parameter n = 2; reg [n-1:0] a, b; reg ci; reg [n-1:0] s; reg [n:0] c; integer i,j; always @(*) begin c[n:1] <= a & b | a & c[n-1:0] | b & c[n-1:0]; s <= a ^ b ^ c[n-1:0]; end initial begin $display("Starting SUM test"); for (i = 0;i < 32;i = i + 1) begin a[0] = (i & 8'h1) != 0; a[1] = (i & 8'h2) != 0; b[0] = (i & 8'h4) != 0; b[1] = (i & 8'h8) != 0; c[0] = (i & 8'h10) != 0; #1 $display("sum: %3b = %2b + %2b + %2b (%d=%d+%d+%d)",{c[2],s},a,b,c[0],{c[2],s},a,b,c[0]); end end endmodule tkgate-2.0-b10/test/verga/supply1.out000644 001751 001751 00000000041 10505463333 020234 0ustar00hansenhansen000000 000000 1: z=x a=x 2: z=x a=1 3: z=1 a=1 tkgate-2.0-b10/test/verga/supply1.v000644 001751 001751 00000000362 10201213377 017672 0ustar00hansenhansen000000 000000 module top; supply0 gnd; reg a; wire z; AND2 g1(z, a, !gnd); initial begin $monitor("%d: z=%b a=%b",$time,z,a); #2 a = 1'b1; end endmodule module AND2(Z,A,B); output Z; input A,B; assign #1 Z = A & B; endmodule tkgate-2.0-b10/test/verga/supply2.out000644 001751 001751 00000000041 10505463333 020235 0ustar00hansenhansen000000 000000 1: z=x a=x 2: z=x a=1 3: z=1 a=1 tkgate-2.0-b10/test/verga/supply2.v000644 001751 001751 00000000404 10201203151 017655 0ustar00hansenhansen000000 000000 module top; supply0 gnd; wire vdd = !gnd; reg a; wire z; AND2 g1(z, a, vdd); initial begin $monitor("%d: z=%b a=%b",$time,z,a); #2 a = 1'b1; end endmodule module AND2(Z,A,B); output Z; input A,B; assign #1 Z = A & B; endmodule tkgate-2.0-b10/test/verga/task.out000644 001751 001751 00000000654 10505463333 017573 0ustar00hansenhansen000000 000000 in foo(8, 9) stating top. w1=9 in top (i=0, w1='h9, a='h12, r='h1). in mytask (i=0, w1='h9, a='h3). in top (i=10, w1='h9, a='h12, r='h1). in mytask (i=1, w1='h9, a='h3). in top (i=20, w1='h9, a='h12, r='h1). in mytask (i=2, w1='h9, a='h3). in top (i=30, w1='h9, a='h12, r='h1). in mytask (i=3, w1='h9, a='h3). in top (i=40, w1='h9, a='h12, r='h1). in mytask (i=4, w1='h9, a='h3). after call. start of fooby end of fooby r2=21. tkgate-2.0-b10/test/verga/task.v000644 001751 001751 00000001727 10330263567 017236 0ustar00hansenhansen000000 000000 module top; wire [3:0] w1 = 4'h9; wire [3:0] w2 = 4'h3; wire [7:0] a; reg [3:0] r; reg [7:0] r2; integer i; assign a = 1'h1 + foo(8,9); initial begin #0; r = 4'b1; $display("stating top. w1=%h",w1); mytask(w2); $display("after call."); fooby(3,7,r2); $display("r2=%d.",r2); end initial for (i = 0;i < 50;i = i + 10) #1 $display("in top (i=%d, w1='h%h, a='h%h, r='h%h).",i,w1,a,r); automatic function [7:0] foo(input [7:0] a,input [7:0] b); begin $display("in foo(%d, %d)",a,b); foo = a + b; end endfunction automatic task mytask(input [7:0] a); integer i; begin for (i = 0;i < 5;i = i + 1) #1 $display("in mytask (i=%d, w1='h%h, a='h%h).",i,w1,a); end endtask task fooby(input [7:0] a,input [7:0] b,output [7:0] c); integer i; begin $display("start of fooby"); c = a*b; $display("end of fooby"); end endtask endmodule tkgate-2.0-b10/test/verga/test.mem000644 001751 001751 00000000176 10312432475 017555 0ustar00hansenhansen000000 000000 @memory top.m @0 3 4 9 16 25 36 49 64 81 @C 100 x x 99 z 12 x8 z12 @100 4 3 9x x x11 @1000000 12 13 14 z 19 20 x x x 30 31 tkgate-2.0-b10/test/verga/test1.out000644 001751 001751 00000000115 11257536652 017673 0ustar00hansenhansen000000 000000 hello world x=0 x=1 3: monitored x = 0 6: monitored x = 1 8: monitored x = 0 tkgate-2.0-b10/test/verga/test2.out000644 001751 001751 00000000024 11257536652 017673 0ustar00hansenhansen000000 000000 hello world x=0 x=1 tkgate-2.0-b10/test/verga/timescale.out000644 001751 001751 00000000051 10505463333 020566 0ustar00hansenhansen000000 000000 5 (5): bar 5.0 (50): foo 5.50 (550): top tkgate-2.0-b10/test/verga/timescale.v000644 001751 001751 00000000511 10504201121 020205 0ustar00hansenhansen000000 000000 `timescale 1ns/10ps module top; foo f1; bar b1; initial #5.5 $display("%t (%d): top",$time,$time); endmodule `timescale 100ps/10ps module foo; initial #5 $display("%t (%d): foo",$time, $time); endmodule `timescale 10ps/10ps module bar; initial #5 $display("%t (%d): bar",$time, $time); endmodule tkgate-2.0-b10/test/verga/timing1.out000644 001751 001751 00000002374 11140744332 020177 0ustar00hansenhansen000000 000000 0: ck=1 data=0 en=1 - out=0 50: ck=0 data=0 en=1 - out=0 95: ck=0 data=1 en=1 - out=0 Expect $setup violation at time 100. Runtime Error at 100: Timing violation in top.l1[latch] $setup(data, (posedge ck) &&& en, 10). 100: ck=1 data=1 en=1 - out=1 150: ck=0 data=1 en=1 - out=1 185: ck=0 data=0 en=1 - out=1 Expect no violations at time 200. 200: ck=1 data=0 en=1 - out=0 250: ck=0 data=0 en=1 - out=0 291: ck=0 data=1 en=1 - out=0 Expect $setup violation at time 300. Runtime Error at 300: Timing violation in top.l1[latch] $setup(data, (posedge ck) &&& en, 10). 300: ck=1 data=1 en=1 - out=1 350: ck=0 data=0 en=1 - out=1 Expect no violations at time 400. 400: ck=1 data=0 en=1 - out=0 450: ck=0 data=0 en=1 - out=0 495: ck=0 data=1 en=0 - out=0 Expect no violations at time 500. 500: ck=1 data=1 en=0 - out=0 Expect no violations at time 502. 502: ck=1 data=1 en=1 - out=0 550: ck=0 data=1 en=1 - out=0 600: ck=1 data=1 en=1 - out=1 Expect $hold violation at time 602. Runtime Error at 602: Timing violation in top.l1[latch] $hold((posedge ck) &&& en, data, 10). 602: ck=1 data=0 en=1 - out=1 650: ck=0 data=0 en=1 - out=1 700: ck=1 data=0 en=1 - out=0 Expect no violation at time 711. 711: ck=1 data=1 en=1 - out=0 750: ck=0 data=1 en=1 - out=0 tkgate-2.0-b10/test/verga/timing1.v000644 001751 001751 00000002706 11132034367 017635 0ustar00hansenhansen000000 000000 module top; integer i; reg ck; reg data,en; wire out; initial $monitor("%4d: ck=%b data=%b en=%b - out=%b",$time,ck,data,en,out); always #50 ck = !ck; initial begin ck = 1'b1; data = 1'b0; en = 1'b1; #95; data = 1'b1; en = 1'b1; #5; $display("Expect $setup violation at time %d.",$time); #85; data = 1'b0; en = 1'b1; #15; $display("Expect no violations at time %d.",$time); #91; data = 1'b1; en = 1'b1; #9; $display("Expect $setup violation at time %d.",$time); #50; data = 1'b0; en = 1'b1; #50; $display("Expect no violations at time %d.",$time); #95; data = 1'b1; en = 1'b0; #5; $display("Expect no violations at time %d.",$time); #2; $display("Expect no violations at time %d.",$time); data = 1'b1; en = 1'b1; #98; #2; $display("Expect $hold violation at time %d.",$time); data = 1'b0; en = 1'b1; #98; #11; $display("Expect no violation at time %d.",$time); data = 1'b1; en = 1'b1; #89; $finish; end latch l1(ck,data,en,out); endmodule module latch(ck,data,en,out); input ck,data,en; output out; reg out = 1'bx; specify $setup(data, posedge ck &&& en, 10); $hold(posedge ck &&& en, data, 10); endspecify always @(posedge ck) if (en) begin out = data; end endmodule tkgate-2.0-b10/test/verga/timing2.out000644 001751 001751 00000001046 11140744351 020174 0ustar00hansenhansen000000 000000 0: ck=1 No violation expected at 50 50: ck=0 No violation expected at 100 100: ck=1 No violation expected at 150 150: ck=0 No violation expected at 200 200: ck=1 $width violation expected at 220 on posedge Runtime Error at 220: Timing violation in top[top] $width(posedge ck, 30). 220: ck=0 No violation expected at 300 300: ck=1 No violation expected at 390 390: ck=0 $width violation expected at 400 on negedge Runtime Error at 400: Timing violation in top[top] $width(negedge ck, 25). 400: ck=1 No violation expected at 450 450: ck=0 tkgate-2.0-b10/test/verga/timing2.v000644 001751 001751 00000001724 11132034426 017631 0ustar00hansenhansen000000 000000 module top; reg ck; specify $width(posedge ck, 30); $width(negedge ck, 25); endspecify initial $monitor("%4d: ck=%b",$time,ck); initial begin ck = 1'b1; #50; ck = 1'b0; $display("No violation expected at %d",$time); #50; ck = 1'b1; $display("No violation expected at %d",$time); #50; ck = 1'b0; $display("No violation expected at %d",$time); #50; ck = 1'b1; $display("No violation expected at %d",$time); #20; ck = 1'b0; $display("$width violation expected at %d on posedge",$time); #80; ck = 1'b1; $display("No violation expected at %d",$time); #90; ck = 1'b0; $display("No violation expected at %d",$time); #10; ck = 1'b1; $display("$width violation expected at %d on negedge",$time); #50; ck = 1'b0; $display("No violation expected at %d",$time); #50; end endmodule tkgate-2.0-b10/test/verga/trireg1.out000644 001751 001751 00000000402 10505463333 020175 0ustar00hansenhansen000000 000000 TRIREG 0 1 x z L H +----------- 0|0 1 x 0 0 x 1|0 1 x 1 x 1 x|0 1 x x x x Expect: TRIREG 0 1 x z L H +----------- 0|0 1 x 0 0 x 1|0 1 x 1 x 1 x|0 1 x x x x w2=x (expect x) w2=0 (expect 0) w2=0 (expect 0) w2=1 (expect 1) w2=1 (expect 1) tkgate-2.0-b10/test/verga/trireg1.v000644 001751 001751 00000003001 10363166371 017635 0ustar00hansenhansen000000 000000 module test; reg [35:0] a; trireg [35:0] w1 = 35'bz; trireg w2; reg b; assign w1 = a; assign w2 = b; integer i,j; function getbit; input [31:0] i; case (i) 0: getbit = 1'b0; 1: getbit = 1'b1; 2: getbit = 1'bx; 3: getbit = 1'bz; 4: getbit = 1'bl; 5: getbit = 1'bh; endcase endfunction initial begin // // Preset all trireg bits // for (i = 0;i < 6;i = i + 1) for (j = 0;j < 6;j = j + 1) begin #1 a[i*6+j] = getbit(i); #1 a[i*6+j] = 1'bz; end $display(" TRIREG "); $display(" 0 1 x z L H"); $display(" +-----------"); for (i = 0;i < 3;i = i + 1) begin $write("%b|",getbit(i)); for (j = 0;j < 6;j = j + 1) begin #1 a[i*6+j] = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w1[i*6+j]); end $write("\n"); end $display(""); $display("Expect:"); $display(" TRIREG "); $display(" 0 1 x z L H"); $display(" +-----------"); $display("0|0 1 x 0 0 x"); $display("1|0 1 x 1 x 1"); $display("x|0 1 x x x x"); /* $display("z|0 1 x z L H"); $display("L|0 1 x L L x"); $display("H|0 1 x H x H"); */ $display(""); #1 $display("w2=%b (expect x)",w2); b = 1'b0; #1 $display("w2=%b (expect 0)",w2); b = 1'bz; #1 $display("w2=%b (expect 0)",w2); b = 1'b1; #1 $display("w2=%b (expect 1)",w2); b = 1'bz; #1 $display("w2=%b (expect 1)",w2); end endmodule tkgate-2.0-b10/test/verga/tristate1.out000644 001751 001751 00000001023 10505463333 020540 0ustar00hansenhansen000000 000000 Starting tri-state z = buf(0)if(0) ++ buf(0)if(0) z = buf(1)if(0) ++ buf(0)if(0) 0 = buf(0)if(1) ++ buf(0)if(0) 1 = buf(1)if(1) ++ buf(0)if(0) z = buf(0)if(0) ++ buf(1)if(0) z = buf(1)if(0) ++ buf(1)if(0) 0 = buf(0)if(1) ++ buf(1)if(0) 1 = buf(1)if(1) ++ buf(1)if(0) 0 = buf(0)if(0) ++ buf(0)if(1) 0 = buf(1)if(0) ++ buf(0)if(1) 0 = buf(0)if(1) ++ buf(0)if(1) x = buf(1)if(1) ++ buf(0)if(1) 1 = buf(0)if(0) ++ buf(1)if(1) 1 = buf(1)if(0) ++ buf(1)if(1) x = buf(0)if(1) ++ buf(1)if(1) 1 = buf(1)if(1) ++ buf(1)if(1) tkgate-2.0-b10/test/verga/tristate1.v000644 001751 001751 00000000700 10126054643 020176 0ustar00hansenhansen000000 000000 module top; reg a1, b1; reg a0, b0; reg x; integer i; assign x = a1 ? a0 : 1'bz; assign x = b1 ? b0 : 1'bz; initial begin $display("Starting tri-state"); for (i = 0;i < 16;i = i + 1) begin a0 = (i & 8'h1) != 0; a1 = (i & 8'h2) != 0; b0 = (i & 8'h4) != 0; b1 = (i & 8'h8) != 0; #1 $display("%b = buf(%b)if(%b) ++ buf(%b)if(%b)",x,a0,a1,b0,b1); end end endmodule tkgate-2.0-b10/test/verga/uops.out000644 001751 001751 00000000072 10505463333 017611 0ustar00hansenhansen000000 000000 a=1 b=0 a is true. ~b is true. !b is true. r='hz r='oz tkgate-2.0-b10/test/verga/uops.v000644 001751 001751 00000000726 10133213432 017243 0ustar00hansenhansen000000 000000 module top; reg a,b; reg [31:0] x; reg [31:0] r; initial begin x = ~0; a = x; b = ~x; #1; $display("a=%h b=%h",a,b); if (a) $display("a is true."); if (~a) $display("~a is true."); if (!a) $display("!a is true."); if (b) $display("b is true."); if (~b) $display("~b is true."); if (!b) $display("!b is true."); r = 32'hz; $display("r='h%h r='o%o",r,r); end endmodule tkgate-2.0-b10/test/verga/verga.out000644 001751 001751 00000002555 11257536653 017752 0ustar00hansenhansen000000 000000 WIRE WOR WAND TRI0 TRI1 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H +----------- +----------- +----------- +----------- +----------- 0|0 x x 0 0 x 0|0 1 x 0 0 x 0|0 0 0 0 0 0 0|0 x x 0 0 x 0|0 x x 0 0 x 1|x 1 x 1 x 1 1|1 1 1 1 1 1 1|0 1 x 1 x 1 1|x 1 x 1 x 1 1|x 1 x 1 x 1 x|x x x x x x x|x 1 x x x x x|0 x x x x x x|x x x x x x x|x x x x x x z|0 1 x z L H z|0 1 x z L H z|0 1 x z L H z|0 1 x 0 0 x z|0 1 x 1 x 1 L|0 x x L L x L|0 1 x L L x L|0 x x L L x L|0 x x 0 0 x L|0 x x x x x H|x 1 x H x H H|x 1 x H x H H|0 1 x H x H H|x 1 x x x x H|x 1 x 1 x 1 Expect: WIRE WOR WAND TRI0 TRI1 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H +----------- +----------- +----------- +----------- +----------- 0|0 x x 0 0 x 0|0 1 x 0 0 x 0|0 0 0 0 0 0 0|0 x x 0 0 x 0|0 x x 0 0 x 1|x 1 x 1 x 1 1|1 1 1 1 1 1 1|0 1 x 1 x 1 1|x 1 x 1 x 1 1|x 1 x 1 x 1 x|x x x x x x x|x 1 x x x x x|0 x x x x x x|x x x x x x x|x x x x x x z|0 1 x z L H z|0 1 x z L H z|0 1 x z L H z|0 1 x 0 0 x z|0 1 x 1 x 1 L|0 x x L L x L|0 1 x L L x L|0 x x L L x L|0 x x 0 0 x L|0 x x x x x H|x 1 x H x H H|x 1 x H x H H|0 1 x H x H H|x 1 x x x x H|x 1 x 1 x 1 tkgate-2.0-b10/test/verga/wire1.out000644 001751 001751 00000002555 10505463333 017662 0ustar00hansenhansen000000 000000 WIRE WOR WAND TRI0 TRI1 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H +----------- +----------- +----------- +----------- +----------- 0|0 x x 0 0 x 0|0 1 x 0 0 x 0|0 0 0 0 0 0 0|0 x x 0 0 x 0|0 x x 0 0 x 1|x 1 x 1 x 1 1|1 1 1 1 1 1 1|0 1 x 1 x 1 1|x 1 x 1 x 1 1|x 1 x 1 x 1 x|x x x x x x x|x 1 x x x x x|0 x x x x x x|x x x x x x x|x x x x x x z|0 1 x z L H z|0 1 x z L H z|0 1 x z L H z|0 1 x 0 0 x z|0 1 x 1 x 1 L|0 x x L L x L|0 1 x L L x L|0 x x L L x L|0 x x 0 0 x L|0 x x x x x H|x 1 x H x H H|x 1 x H x H H|0 1 x H x H H|x 1 x x x x H|x 1 x 1 x 1 Expect: WIRE WOR WAND TRI0 TRI1 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H +----------- +----------- +----------- +----------- +----------- 0|0 x x 0 0 x 0|0 1 x 0 0 x 0|0 0 0 0 0 0 0|0 x x 0 0 x 0|0 x x 0 0 x 1|x 1 x 1 x 1 1|1 1 1 1 1 1 1|0 1 x 1 x 1 1|x 1 x 1 x 1 1|x 1 x 1 x 1 x|x x x x x x x|x 1 x x x x x|0 x x x x x x|x x x x x x x|x x x x x x z|0 1 x z L H z|0 1 x z L H z|0 1 x z L H z|0 1 x 0 0 x z|0 1 x 1 x 1 L|0 x x L L x L|0 1 x L L x L|0 x x L L x L|0 x x 0 0 x L|0 x x x x x H|x 1 x H x H H|x 1 x H x H H|0 1 x H x H H|x 1 x x x x H|x 1 x 1 x 1 tkgate-2.0-b10/test/verga/wire1.v000644 001751 001751 00000005112 10362764726 017323 0ustar00hansenhansen000000 000000 module test; reg a,b,e_wire,e_wor,e_wand,e_tri0,e_tri1; wire w1; wor w2; wand w3; tri0 w4; tri1 w5; assign w1 = a; assign w1 = b; assign w2 = a; assign w2 = b; assign w3 = a; assign w3 = b; assign w4 = a; assign w4 = b; assign w5 = a; assign w5 = b; integer i,j; function getbit; input [31:0] i; case (i) 0: getbit = 1'b0; 1: getbit = 1'b1; 2: getbit = 1'bx; 3: getbit = 1'bz; 4: getbit = 1'bl; 5: getbit = 1'bh; endcase endfunction initial begin $display(" WIRE WOR WAND TRI0 TRI1"); $display(" 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H"); $display(" +----------- +----------- +----------- +----------- +-----------"); for (i = 0;i < 6;i = i + 1) begin a = getbit(i); $write("%b|",a); for (j = 0;j < 6;j = j + 1) begin b = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w1); end $write(" %b|",a); for (j = 0;j < 6;j = j + 1) begin b = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w2); end $write(" %b|",a); for (j = 0;j < 6;j = j + 1) begin b = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w3); end $write(" %b|",a); for (j = 0;j < 6;j = j + 1) begin b = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w4); end $write(" %b|",a); for (j = 0;j < 6;j = j + 1) begin b = getbit(j); #1; if (j > 0) $write(" "); $write("%b",w5); end $write("\n"); end $display(""); $display("Expect:"); $display(" WIRE WOR WAND TRI0 TRI1 "); $display(" 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H 0 1 x z L H"); $display(" +----------- +----------- +----------- +----------- +-----------"); $display("0|0 x x 0 0 x 0|0 1 x 0 0 x 0|0 0 0 0 0 0 0|0 x x 0 0 x 0|0 x x 0 0 x"); $display("1|x 1 x 1 x 1 1|1 1 1 1 1 1 1|0 1 x 1 x 1 1|x 1 x 1 x 1 1|x 1 x 1 x 1"); $display("x|x x x x x x x|x 1 x x x x x|0 x x x x x x|x x x x x x x|x x x x x x"); $display("z|0 1 x z L H z|0 1 x z L H z|0 1 x z L H z|0 1 x 0 0 x z|0 1 x 1 x 1"); $display("L|0 x x L L x L|0 1 x L L x L|0 x x L L x L|0 x x 0 0 x L|0 x x x x x"); $display("H|x 1 x H x H H|x 1 x H x H H|0 1 x H x H H|x 1 x x x x H|x 1 x 1 x 1"); end endmodule tkgate-2.0-b10/test/verga/concat.v000644 001751 001751 00000001346 11124034727 017534 0ustar00hansenhansen000000 000000 module top; reg [127:0] a0,a1,a2,a3,a4,a5,a6,b1,b2,b3; initial begin a0 = {4'h4, 2'h0, 2'h2}; $display("a0=[%h]",a0); a1 = {17'h12,17'h12,17'h12}; $display("a1=[%h]",a1); a2 = {16'h12,16'h12,16'h12}; $display("a2=[%h]",a2); a3 = {15'h12,15'h12,15'h12}; $display("a3=[%h]",a3); a4 = {8'h41,8'h42,8'h43}; $display("a4=[%h]",a4); a5 = {11'h41,11'h42,11'h43}; $display("a5=[%h]",a5); a6 = {32'h41,32'h42,32'h43}; $display("a6=[%h]",a6); b1 = {3{17'h12}}; $display("b1=[%h]",b1); b2 = {3{16'h12}}; $display("b2=[%h]",b2); b3 = {3{15'h12}}; $display("b3=[%h]",b3); end endmodule tkgate-2.0-b10/test/verga/concat.out000644 001751 001751 00000000230 11124035054 020057 0ustar00hansenhansen000000 000000 a0=[42] a1=[4800240012] a2=[1200120012] a3=[480090012] a4=[414243] a5=[10421043] a6=[410000004200000043] b1=[4800240012] b2=[1200120012] b3=[480090012] tkgate-2.0-b10/test/verga/memory3.v000644 001751 001751 00000001076 11140743706 017662 0ustar00hansenhansen000000 000000 module top; reg [7:0] m[0:255]; reg [7:0] addr; reg x = 1'b0; integer i; wire [7:0] w; assign w = m[3]; always @(w) $display($time,": w changed to ",w); initial begin m[3][7:4] = 9; m[3][3:0] = 2; m[3] <= #2 7; m[3][7:4] <= #3 3; m[3] <= @(posedge x) 8'h99; $display($time,": m[3]=",m[3]," w=",w); for (i = 0;i < 20;i = i+1) #1 $display($time,": m[3]=",m[3]," w=",w); end // initial begin initial begin #6 x = 1'b1; #3 x = 1'b0; m[3] = 8'h42; #3 x = 1'b1; #3 m[4] = 9; end endmodule // top tkgate-2.0-b10/test/verga/adder1.out000644 001751 001751 00000000301 10505463332 017755 0ustar00hansenhansen000000 000000 0: {x,x} = x + x + x 2: {0,0} = 0 + 0 + 0 4: {0,1} = 0 + 0 + 1 6: {0,1} = 0 + 1 + 0 8: {1,0} = 0 + 1 + 1 10: {0,1} = 1 + 0 + 0 12: {1,0} = 1 + 0 + 1 14: {1,0} = 1 + 1 + 0 16: {1,1} = 1 + 1 + 1 tkgate-2.0-b10/test/tkgate/spec4.v000644 001751 001751 00000001014 10462037053 017445 0ustar00hansenhansen000000 000000 module top; integer i; reg ci = 1'b0; reg [7:0] a,b; wire [7:0] s; wire co; initial $monitor("%4d: a=%d b=%d ci=%d - s=%d co=%d",$time,a,b,ci,s,co); initial for (i = 0;i < 16;i = i + 1) begin {a,b} = i; #100; end _GGADD8 f(a,b,s,ci,co); endmodule module _GGADD8 (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = 1; (A,B *> CO) = 1; (CI *> S) = 1; (CI *> CO) = 1; endspecify assign {CO,S} = A + B + CI; endmodule tkgate-2.0-b10/test/tkgate/error.v000644 001751 001751 00000003332 10263652347 017575 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "error.v" //: /netlistBegin main module main; //: root_module reg w4; //: /sn:0 {0}(111,321)(191,321)(191,320)(201,320){1} reg w3; //: /sn:0 {0}(112,291)(201,291){1} reg w0; //: /sn:0 {0}(113,195)(201,195){1} reg w1; //: /sn:0 {0}(113,225)(201,225){1} reg w2; //: /sn:0 {0}(112,257)(202,257){1} reg w5; //: /sn:0 {0}(112,353)(191,353)(191,352)(201,352){1} //: enddecls //: SWITCH g4 (w2) @(95,257) /sn:0 /w:[ 0 ] /st:0 bar g3 (); //: @(-68, 129) /sz:(40, 40) /sn:0 /p:[ ] //: SWITCH g2 (w1) @(96,225) /sn:0 /w:[ 0 ] /st:0 //: SWITCH g1 (w0) @(96,195) /sn:0 /w:[ 0 ] /st:0 //: SWITCH g6 (w4) @(94,321) /sn:0 /w:[ 0 ] /st:0 //: SWITCH g7 (w5) @(95,353) /sn:0 /w:[ 0 ] /st:0 //: SWITCH g5 (w3) @(95,291) /sn:0 /w:[ 0 ] /st:0 foo g0 (.I4(w4), .I3(w3), .I3(w2), .I2(w1), .I1(w0), .I5(w5)); //: @(202, 177) /sz:(70, 207) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Lt0=1 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(I5, I4, I3, I9); //: interface /sz:(40, 40) /bd:[ ] input [1:0] I4; //: /sn:0 {0}(182,240)(197,240){1} inout [2:0] I5; //: /sn:0 /dp:1 {0}(198,294)(213,294){1} input I9; //: /sn:0 {0}(202,131)(217,131){1} input I3; //: /sn:0 {0}(187,178)(202,178){1} //: enddecls //: INOUT g3 (I5) @(192,294) /sn:0 /w:[ 0 ] //: IN g2 (I4) @(180,240) /sn:0 /w:[ 0 ] //: IN g1 (I3) @(185,178) /sn:0 /w:[ 0 ] //: IN g0 (I9) @(200,131) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /hdlBegin bar //: interface /sz:(40, 40) /bd:[ ] //: enddecls module bar; wire a; wire b; wire a; assign h = a; foo g1(.I1(a), .I2(b)); initial begin a = b + 1; x = y; end endmodule //: /hdlEnd tkgate-2.0-b10/test/tkgate/error2.v000644 001751 001751 00000000214 10263366024 017645 0ustar00hansenhansen000000 000000 module top; wire a; initial begin a = 1; $display("a=%b",a); a = 0; $display("a=%b",a); end endmodule tkgate-2.0-b10/test/tkgate/error3.v000644 001751 001751 00000001033 10265576603 017656 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: /netlistBegin main module main; //: root_module reg w0; //: /sn:0 {0}(150,141)(198,141)(198,178)(208,178){1} //: enddecls //: SWITCH g1 (w0) @(133,141) /sn:0 /w:[ 0 ] /st:0 foo g0 (.A(w0)); //: @(209, 153) /sz:(84, 95) /sn:0 /p:[ Li0>1 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(A); //: interface /sz:(40, 40) /bd:[ ] input [1:0] A; //: /sn:0 {0}(142,156)(157,156){1} //: enddecls //: IN g0 (A) @(140,156) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/error4.v000644 001751 001751 00000001254 10265577625 017671 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "error4.v" //: /netlistBegin main module main; //: root_module reg w0; //: /sn:0 {0}(150,141)(198,141)(198,178)(208,178){1} reg w1; //: /sn:0 {0}(129,228)(208,228){1} //: enddecls //: SWITCH g2 (w1) @(112,228) /sn:0 /w:[ 0 ] /st:0 //: SWITCH g1 (w0) @(133,141) /sn:0 /w:[ 0 ] /st:0 foo g0 (.B(w1), .A(w0)); //: @(209, 153) /sz:(84, 95) /sn:0 /p:[ Li0>1 Li1>1 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(A); //: interface /sz:(40, 40) /bd:[ ] input [1:0] A; //: /sn:0 {0}(142,156)(157,156){1} //: enddecls //: IN g0 (A) @(140,156) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/error5.v000644 001751 001751 00000002471 10270061431 017647 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "error5.v" //: /netlistBegin main module main; //: root_module wire w0; //: /sn:0 {0}(159,147)(174,147){1} wire w3; //: /sn:0 {0}(279,245)(291,245){1} wire w1; //: /sn:0 {0}(159,152)(174,152){1} wire w2; //: /sn:0 {0}(195,150)(210,150){1} //: enddecls foo g2 (); //: @(195, 289) /sz:(40, 40) /sn:0 /p:[ ] foo g1 (.A(w3)); //: @(292, 201) /sz:(100, 118) /sn:0 /p:[ Li0>1 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(185,150) /sn:0 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(A); //: interface /sz:(40, 40) /bd:[ ] input A; //: /sn:0 /dp:1 {0}(244,220)(198,220){1} wire bufout; //: /sn:0 /dp:1 {0}(260,220)(275,220){1} wire w0; //: /sn:0 {0}(233,349)(248,349){1} wire w1; //: /sn:0 {0}(264,349)(279,349){1} //: enddecls _GGBUF #(4) g2 (.I(w0), .Z(w1)); //: @(254,349) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g1 (.I(A), .Z(bufout)); //: @(250,220) /sn:0 /w:[ 0 0 ] //: IN g0 (A) @(196,220) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/hdl.v000644 001751 001751 00000007144 10301502504 017176 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "timer.v" //: /hdlBegin oneshot //: interface /sz:(40, 40) /bd:[ ] //: root_module //: enddecls // // This file is for testing the indentation code. // module oneshot; output Z; reg Z; initial begin Z = 0; $tkg$wait(1000); Z = !Z; k = u *l + j *k - 99*(y + 3)*(k l+); if (h) j = 9; k; case (w) 1: h = 9; 2: i = 8; 3: o = 99; 4: begin k = q; u = 22; end 5: k = 11; endcase begin if (a) if (j) begin j; k; if (k) l = 22; else if (l) if (m) q = 2; else k = 1; end m = 9; a = 1; end l; end always begin k = 0; if (q) if (u) if (k) if (g) h = 99 + o; else k = 99; else j = 22; else y = 3; k = 11 + l; u = 11; end always begin if (a == 1) k = 1; else if (a == 2) m = 1; else if (a == 7) l = 2; else z = 1; j = 99; end endmodule //: /hdlEnd //: /hdlBegin timer //: interface /sz:(40, 40) /bd:[ ] //: enddecls module timer; reg Z; initial begin Z = 0; forever begin $tkg$wait(250); Z = !Z; end end endmodule //: /hdlEnd //: /netlistBegin main module main(); //: interface /sz:(40, 40) /bd:[ ] supply0 w0; //: /sn:0 {0}(458,342)(458,326)(358,326){1} supply0 w2; //: /sn:0 {0}(357,271)(357,260)(343,260){1} reg [7:0] w5; //: /sn:0 {0}(255,203)(255,231)(303,231)(303,246){1} wire w6; //: /sn:0 {0}(184,321)(282,321){1} wire [7:0] w7; //: /sn:0 {0}(319,275)(319,311){1} wire w4; //: /sn:0 {0}(358,316)(582,316)(582,257)(525,257){1} wire [7:0] w1; //: /sn:0 {0}(319,332)(319,340){1} //: {2}(321,342)(390,342)(390,219)(335,219)(335,246){3} //: {4}(319,344)(319,425)(377,425)(377,412){5} wire w9; //: /sn:0 {0}(295,260)(280,260){1} //: enddecls timer g4 (.Z(w6)); //: @(121, 296) /sz:(62, 63) /sn:0 /p:[ Ro0<0 ] //: joint g8 (w1) @(319, 342) /w:[ 2 1 -1 4 ] _GGADD8 #(68, 70, 62, 64) g3 (.A(w5), .B(w1), .S(w7), .CI(w2), .CO(w9)); //: @(319,262) /sn:0 /w:[ 1 3 0 1 0 ] //: GROUND g2 (w0) @(458,348) /sn:0 /w:[ 0 ] oneshot g1 (.Z(w4)); //: @(455, 232) /sz:(69, 63) /sn:0 /p:[ Ro0<1 ] //: DIP g6 (w5) @(255,193) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (w1) @(377,405) /sn:0 /w:[ 5 ] /type:2 //: GROUND g5 (w2) @(357,277) /sn:0 /w:[ 0 ] _GGREG8 #(10, 10, 20) g0 (.Q(w1), .D(w7), .EN(w0), .CLR(w4), .CK(w6)); //: @(319,321) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/new.v000644 001751 001751 00000426346 10250672367 017253 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: require "timer" //: /symbolBegin: 140951056 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /symbolBegin: 140947728 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 141159184 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 140950544 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140844304 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140840976 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141158928 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port output Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141056272 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141055504 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 141054992 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0x01, 0xfc, 0xc0, 0x00," //: /data " 0x01, 0x04, 0x00, 0x03, 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x08," //: /data " 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x03, 0xf1, 0x07, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0x03, 0xfc, 0xf1, 0x00," //: /data " 0x03, 0xfc, 0xc0, 0x03, 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0x00, 0x0c," //: /data " 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0xc0, 0x03, 0xf3, 0x0f, 0xf0, 0x00," //: /data " 0xf3, 0x07, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /symbolBegin: 140949264 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140843280 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140983056 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 140980240 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140948240 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140672528 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140982288 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141158672 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 141057296 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140843536 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140980496 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0x01, 0xfc, 0xc0, 0x00," //: /data " 0x01, 0x04, 0x00, 0x03, 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x08," //: /data " 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x03, 0xf1, 0x07, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0x03, 0xfc, 0xf1, 0x00," //: /data " 0x03, 0xfc, 0xc0, 0x03, 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0x00, 0x0c," //: /data " 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0xc0, 0x03, 0xf3, 0x0f, 0xf0, 0x00," //: /data " 0xf3, 0x07, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /symbolBegin: 141156624 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140950032 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140615696 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140981008 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141159696 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 141158160 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141157648 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140950800 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 141056528 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140844560 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140841744 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140672784 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141249552 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 140949776 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port input Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 140947472 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port input Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 141156880 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140844816 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140842512 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140984080 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141158416 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /symbolBegin: 140947984 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141250064 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port output Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141057808 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141055248 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140842256 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141057040 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141054224 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port output Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140843024 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140982800 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140672272 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140983824 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141057552 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140841488 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140982544 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140982032 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140981776 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140981264 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141249296 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141157904 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /symbolBegin: 141248784 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141159440 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141053968 //: /iconBegin normal 836 5 5 //: /data "#define defaultSymbol_width 29" //: /data "#define defaultSymbol_height 29" //: /data "static unsigned char defaultSymbol_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x08, 0x11, 0x39, 0x18, 0x10, 0x11, 0x49, 0x24, 0x10," //: /data " 0x11, 0x89, 0x04, 0x10, 0x11, 0x89, 0x18, 0x10, 0x11, 0x89, 0x20, 0x10," //: /data " 0x11, 0x49, 0x24, 0x10, 0xe1, 0x38, 0x18, 0x10, 0x01, 0x00, 0x00, 0x10," //: /data " 0x01, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x08," //: /data " 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x02," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x00, 0x01, 0x00, 0x60, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /symbolEnd //: /symbolBegin: 140842768 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 25" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00," //: /data " 0x61, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00," //: /data " 0x01, 0x04, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x04, 0x00," //: /data " 0x01, 0x00, 0x18, 0x00, 0x01, 0x00, 0x20, 0x00, 0x01, 0x00, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0xc0, 0x00, 0x01, 0x00, 0x30, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x00," //: /data " 0x01, 0x60, 0x00, 0x00, 0x01, 0x18, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00," //: /data " 0x01, 0x01, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port output Z @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140951312 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 141249808 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140949008 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /symbolEnd //: /symbolBegin: 140948496 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 800 5 5 //: /data "#define y_width 29" //: /data "#define y_height 29" //: /data "static unsigned char y_bits[] = {" //: /data " 0xff, 0xff, 0x07, 0x00, 0xff, 0xff, 0x1f, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x0c, 0x33, 0x7b, 0x38, 0x18, 0x33, 0xdb, 0x6c, 0x18," //: /data " 0x33, 0x9b, 0x0d, 0x18, 0x33, 0x9b, 0x39, 0x18, 0x33, 0x9b, 0x61, 0x18," //: /data " 0x33, 0xdb, 0x6c, 0x18, 0xe3, 0x79, 0x38, 0x18, 0x03, 0x00, 0x00, 0x18," //: /data " 0x03, 0x00, 0x00, 0x18, 0x03, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x0c," //: /data " 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x06, 0x03, 0x00, 0x00, 0x03," //: /data " 0x03, 0x00, 0x80, 0x01, 0x03, 0x00, 0xe0, 0x00, 0x03, 0x00, 0x78, 0x00," //: /data " 0xff, 0xff, 0x1f, 0x00, 0xff, 0xff, 0x07, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(4, 24) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module wire w0; //: /sn:0 {0}(169,179)(202,179)(202,159){1} //: enddecls OSCILLATOR #(.HZ(200)) g2 (.Z(w0)); //: @(155, 179) /symbol:140951056 /sn:0 /w:[ 0 ] //: LED g0 (w0) @(202,152) /sn:0 /w:[ 1 ] /type:0 endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/symbol.v000644 001751 001751 00000060563 10302235006 017741 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: /symbolBegin: 140725520 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /symbolBegin: 140653072 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x5e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x40, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x01, 0xc0, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x03, 0x30," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x01, 0x0e, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x80, 0x03, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0xe0, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x04, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input AIN[7:0] @(31, 2) /r:1 //: /port input SA[1:0] @(2, 16) /r:2 //: /port input SB[1:0] @(2, 31) /r:2 //: /port input ck @(2, 46) /r:2 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port output COUT[7:0] @(45, 61) /r:3 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg [1:0] w21; //: /sn:0 /dp:1 {0}(314,343)(274,343)(274,308)(268,308){1} reg w28; //: /sn:0 {0}(247,148)(267,148)(267,148)(296,148){1} reg [1:0] w23; //: /sn:0 /dp:1 {0}(314,358)(304,358)(304,358)(268,358){1} reg [7:0] w25; //: /sn:0 {0}(268,88)(309,88)(309,132){1} reg [1:0] w26; //: /sn:0 /dp:1 {0}(268,211)(289,211)(289,248)(298,248){1} wire [7:0] w14; //: /sn:0 {0}(331,388)(331,425)(426,425)(426,117)(393,117){1} //: {2}(391,115)(391,98){3} //: {4}(389,117)(329,117)(329,132){5} wire [7:0] w30; //: /sn:0 {0}(358,388)(358,400)(406,400)(406,190)(393,190){1} //: {2}(391,188)(391,175){3} //: {4}(389,190)(366,190)(366,219){5} wire [7:0] w12; //: /sn:0 {0}(343,329)(343,301)(343,301)(343,286){1} wire w33; //: /sn:0 {0}(314,373)(264,373)(264,409)(237,409){1} wire [7:0] w29; //: /sn:0 /dp:1 {0}(319,219)(319,161){1} //: enddecls _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(224,409) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 REGS g2 (.SA(w21), .AIN(w12), .AOUT(w14), .SB(w23), .BOUT(w30), .ck(w33)); //: @(343, 359) /symbol:140725520 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(391,168) /sn:0 /w:[ 3 ] /type:2 //: joint g16 (w30) @(391, 190) /w:[ 1 2 4 -1 ] //: DIP sa (w21) @(230,308) /R:1 /w:[ 1 ] /st:0 _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(319,148) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 //: DIP sb (w23) @(230,358) /R:1 /w:[ 1 ] /st:1 ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(299, 220) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: DIP func (w26) @(230,211) /R:1 /w:[ 0 ] /st:0 //: LED g62 (w14) @(391,91) /sn:0 /w:[ 3 ] /type:2 //: joint g17 (w14) @(391, 117) /w:[ 1 2 4 -1 ] //: DIP data_in (w25) @(230,88) /R:1 /w:[ 0 ] /st:11 //: SWITCH data_select (w28) @(230,148) /w:[ 0 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](20/89) Ti1>B[7:0](67/89) Li0>F[1:0](28/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGNDEMUX4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; assign Zcat = 4'b1 << I; assign #1 Z0 = ~(E & Zcat[0]); assign #1 Z1 = ~(E & Zcat[1]); assign #1 Z2 = ~(E & Zcat[2]); assign #1 Z3 = ~(E & Zcat[3]); endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always @(*) begin case (S) 1'h0: Z <= #Dsz I0; 1'h1: Z <= #Dsz I1; default: Z <= #Dsz 1'h0; endcase end endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #100; Z = 1'b1; #100; end end endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/test.v000644 001751 001751 00000004725 10251223574 017423 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: require "timer" //: /symbolBegin: 140615696 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin main module main; //: root_module wire w0; //: /sn:0 {0}(169,178)(202,178)(202,159){1} //: enddecls OSCILLATOR #(.HZ("asdasd")) g2 (.Z(w0)); //: @(155, 178) /symbol:140615696 /sn:0 /w:[ 0 ] //: LED g0 (w0) @(202,152) /sn:0 /w:[ 1 ] /type:0 endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/timer.v000644 001751 001751 00000004742 10272050261 017555 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "timer.v" //: /netlistBegin main module main; //: root_module supply0 w0; //: /sn:0 {0}(458,342)(458,326)(358,326){1} supply0 w2; //: /sn:0 {0}(357,271)(357,260)(343,260){1} reg [7:0] w5; //: /sn:0 {0}(255,203)(255,231)(303,231)(303,246){1} wire w6; //: /sn:0 {0}(184,321)(282,321){1} wire [7:0] w7; //: /sn:0 {0}(319,275)(319,311){1} wire w4; //: /sn:0 {0}(358,316)(582,316)(582,257)(525,257){1} wire [7:0] w1; //: /sn:0 {0}(319,332)(319,340){1} //: {2}(321,342)(390,342)(390,219)(335,219)(335,246){3} //: {4}(319,344)(319,425)(377,425)(377,412){5} wire w9; //: /sn:0 {0}(295,260)(280,260){1} //: enddecls timer g4 (.Z(w6)); //: @(121, 296) /sz:(62, 63) /sn:0 /p:[ Ro0<0 ] //: joint g8 (w1) @(319, 342) /w:[ 2 1 -1 4 ] _GGADD8 #(68, 70, 62, 64) g3 (.A(w5), .B(w1), .S(w7), .CI(w2), .CO(w9)); //: @(319,262) /sn:0 /w:[ 1 3 0 1 0 ] //: GROUND g2 (w0) @(458,348) /sn:0 /w:[ 0 ] oneshot g1 (.Z(w4)); //: @(455, 232) /sz:(69, 63) /sn:0 /p:[ Ro0<1 ] //: DIP g6 (w5) @(255,193) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (w1) @(377,405) /sn:0 /w:[ 5 ] /type:2 //: GROUND g5 (w2) @(357,277) /sn:0 /w:[ 0 ] _GGREG8 #(10, 10, 20) g0 (.Q(w1), .D(w7), .EN(w0), .CLR(w4), .CK(w6)); //: @(319,321) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /hdlBegin timer //: interface /sz:(62, 63) /bd:[ Ro0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/timer2.v000644 001751 001751 00000014454 10270500157 017642 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "timer.v" //: require "timer" //: /symbolBegin: 140716048 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /symbolBegin: 140716560 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0x01, 0xfc, 0xc0, 0x00," //: /data " 0x01, 0x04, 0x00, 0x03, 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x08," //: /data " 0x01, 0x04, 0x00, 0x0c, 0x01, 0x04, 0x00, 0x03, 0xf1, 0x07, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0x03, 0xfc, 0xf1, 0x00," //: /data " 0x03, 0xfc, 0xc0, 0x03, 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0x00, 0x0c," //: /data " 0x03, 0x0c, 0x00, 0x0f, 0x03, 0x0c, 0xc0, 0x03, 0xf3, 0x0f, 0xf0, 0x00," //: /data " 0xf3, 0x07, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port input I @(4, 19) /r:2 //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin main module main; //: root_module supply0 w4; //: /sn:0 {0}(463,273)(463,257)(479,257){1} supply0 w0; //: /sn:0 {0}(458,342)(458,326)(358,326){1} supply0 w2; //: /sn:0 {0}(357,271)(357,260)(343,260){1} reg [7:0] w5; //: /sn:0 {0}(255,203)(255,231)(303,231)(303,246){1} wire [7:0] w7; //: /sn:0 {0}(319,275)(319,311){1} wire w3; //: /sn:0 {0}(166,321)(282,321){1} wire [7:0] w1; //: /sn:0 {0}(319,332)(319,340){1} //: {2}(321,342)(390,342)(390,219)(335,219)(335,246){3} //: {4}(319,344)(319,425)(377,425)(377,412){5} wire w8; //: /sn:0 {0}(508,257)(580,257)(580,316)(358,316){1} wire w9; //: /sn:0 {0}(295,260)(280,260){1} //: enddecls ONESHOT g4 (.I(w4), .Z(w8)); //: @(494, 257) /symbol:140716560 /sn:0 /w:[ 1 0 ] //: joint g8 (w1) @(319, 342) /w:[ 2 1 -1 4 ] _GGADD8 #(68, 70, 62, 64) g3 (.A(w5), .B(w1), .S(w7), .CI(w2), .CO(w9)); //: @(319,262) /sn:0 /w:[ 1 3 0 1 0 ] //: GROUND g2 (w0) @(458,348) /sn:0 /w:[ 0 ] //: GROUND g1 (w4) @(463,279) /sn:0 /w:[ 0 ] //: DIP g6 (w5) @(255,193) /sn:0 /w:[ 0 ] /st:1 OSCILLATOR #(.HZ(100)) g9 (.Z(w3)); //: @(152, 321) /symbol:140716048 /sn:0 /w:[ 0 ] //: LED g7 (w1) @(377,405) /sn:0 /w:[ 5 ] /type:2 //: GROUND g5 (w2) @(357,277) /sn:0 /w:[ 0 ] _GGREG8 #(10, 10, 20) g0 (.Q(w1), .D(w7), .EN(w0), .CLR(w8), .CK(w3)); //: @(319,321) /sn:0 /w:[ 0 1 1 1 1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/tiny.v000644 001751 001751 00000026615 10251464436 017435 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: /netlistBegin main module main; //: root_module wire w6; //: /sn:0 {0}(616,227)(607,227){1} wire [7:0] w7; //: /sn:0 {0}(447,45)(447,52){1} wire [7:0] w16; //: /sn:0 {0}(842,540)(842,562)(683,562){1} //: {2}(681,560)(681,541){3} //: {4}(679,562)(446,562)(446,351){5} //: {6}(446,347)(446,261){7} //: {8}(448,259)(519,259){9} //: {10}(446,257)(446,174){11} //: {12}(444,349)(335,349){13} wire w19; //: /sn:0 {0}(496,136)(486,136){1} wire [7:0] w15; //: /sn:0 {0}(202,348)(213,348){1} wire w4; //: /sn:0 {0}(612,195)(607,195){1} wire w0; //: /sn:0 {0}(493,93)(486,93){1} wire w3; //: /sn:0 {0}(297,301)(297,309){1} wire w1; //: /sn:0 {0}(621,243)(607,243){1} wire w8; //: /sn:0 {0}(842,399)(842,407){1} wire w18; //: /sn:0 {0}(646,400)(646,408){1} wire w17; //: /sn:0 {0}(617,259)(607,259){1} wire w11; //: /sn:0 {0}(807,402)(807,407){1} wire w12; //: /sn:0 {0}(611,401)(611,408){1} wire w2; //: /sn:0 {0}(612,211)(607,211){1} wire w10; //: /sn:0 {0}(681,408)(681,398){1} wire w13; //: /sn:0 {0}(772,402)(772,407){1} wire w5; //: /sn:0 {0}(254,301)(254,309){1} //: enddecls UREGISTER MAR (.CLK(w3), .WRITE(w5), .BUS(w16), .OUT(w15)); //: @(214, 310) /sz:(120, 64) /p:[ Ti0>1 Ti1>1 Ri0>13 Lo0<1 ] //: joint g4 (w16) @(446, 259) /w:[ 8 10 -1 7 ] //: joint g3 (w16) @(681, 562) /w:[ 1 2 4 -1 ] REGISTER regB (.WRITE(w13), .OUT(w11), .CLK(w8), .BUS(w16)); //: @(737, 408) /sz:(140, 131) /p:[ Ti0>1 Ti1>1 Ti2>1 Bt0=0 ] UREGISTER IR (.BUS(w16), .CLK(w19), .WRITE(w0), .OUT(w7)); //: @(421, 53) /sz:(64, 120) /p:[ Bi0>11 Ri0>1 Ri1>1 To0<1 ] //: joint g1 (w16) @(446, 349) /w:[ -1 6 12 5 ] REGISTER regA (.WRITE(w12), .OUT(w18), .CLK(w10), .BUS(w16)); //: @(576, 409) /sz:(140, 131) /p:[ Ti0>1 Ti1>1 Ti2>0 Bt0=3 ] PC g0 (.CLK(w17), .LOAD(w1), .OE(w6), .PLUS(w2), .RST(w4), .BUS(w16)); //: @(520, 179) /sz:(86, 96) /sn:0 /p:[ Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Lt0=9 ] endmodule //: /netlistEnd //: /netlistBegin PC module PC(PLUS, RST, LOAD, BUS, CLK, OE); //: interface /sz:(86, 96) /bd:[ Li0>CLK(16/96) Li1>LOAD(32/96) Li2>OE(48/96) Li3>PLUS(64/96) Li4>RST(80/96) Rt0=BUS[7:0](16/96) ] //: property prot_intf=1 reg [7:0] w6; //: /sn:0 /dp:1 {0}(417,165)(470,165){1} input LOAD; //: /sn:0 {0}(271,832)(271,767){1} //: {2}(273,765)(286,765)(286,749){3} //: {4}(271,763)(271,694){5} inout [7:0] BUS; //: /sn:0 {0}(578,362)(605,362){1} //: {2}(609,362)(725,362){3} //: {4}(607,364)(607,553)(212,553)(212,417)(246,417){5} supply0 w0; //: /sn:0 /dp:1 {0}(403,205)(403,254){1} supply0 w3; //: /sn:0 {0}(416,338)(416,373){1} input OE; //: /sn:0 {0}(570,282)(570,357){1} input RST; //: /sn:0 {0}(296,749)(296,779)(232,779){1} //: {2}(230,777)(230,694){3} //: {4}(230,781)(230,807){5} input CLK; //: /sn:0 {0}(411,509)(411,449){1} supply1 w11; //: /sn:0 {0}(406,311)(406,373){1} supply0 [7:0] w9; //: /sn:0 {0}(196,393)(246,393){1} input PLUS; //: /sn:0 {0}(250,819)(250,775){1} //: {2}(252,773)(291,773)(291,749){3} //: {4}(250,771)(250,694){5} wire [7:0] w7; //: /sn:0 /dp:1 {0}(421,411)(480,411)(480,364){1} //: {2}(482,362)(530,362){3} //: {4}(534,362)(562,362){5} //: {6}(532,364)(532,539)(236,539)(236,429)(246,429){7} //: {8}(480,360)(480,197)(417,197){9} wire w19; //: /sn:0 {0}(267,510)(267,567){1} wire w20; //: /sn:0 {0}(257,510)(257,567){1} wire [7:0] w8; //: /sn:0 {0}(388,181)(167,181)(167,405)(246,405){1} wire w18; //: /sn:0 {0}(291,728)(291,694){1} wire [1:0] w12; //: /sn:0 /dp:1 {0}(262,434)(262,504){1} wire w10; //: /sn:0 {0}(403,157)(403,142){1} wire [7:0] w13; //: /sn:0 {0}(275,411)(400,411){1} //: enddecls //: GROUND g4 (w0) @(403,260) /sn:0 /w:[ 1 ] //: comment g8 @(351,602) /sn:0 //: /line:"00 reset" //: /line:"01 increment" //: /line:"10 load" //: /line:"11 hold (by default)" //: /end _GGADD8 #(68, 70, 62, 64) g3 (.A(w6), .B(w7), .S(w8), .CI(w0), .CO(w10)); //: @(401,181) /sn:0 /R:3 /w:[ 0 9 0 0 0 ] //: IN g13 (PLUS) @(250,821) /sn:0 /R:1 /w:[ 0 ] //: GROUND g2 (w9) @(190,393) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g1 (.I0(w9), .I1(w8), .I2(BUS), .I3(w7), .S(w12), .Z(w13)); //: @(262,411) /sn:0 /R:1 /w:[ 1 1 5 7 0 0 ] /ss:0 /do:1 //: IN g11 (RST) @(230,809) /sn:0 /R:1 /w:[ 5 ] //: joint g16 (PLUS) @(250, 773) /w:[ 2 4 -1 1 ] assign w12 = {w20, w19}; //: CONCAT g10 @(262,505) /sn:0 /R:1 /w:[ 1 0 0 ] /dr:0 /tp:0 /drp:1 _GGBUFIF8 #(4, 6) g19 (.Z(BUS), .I(w7), .E(OE)); //: @(568,362) /sn:0 /w:[ 0 5 1 ] //: VDD g6 (w11) @(417,311) /sn:0 /w:[ 0 ] //: GROUND g7 (w3) @(416,332) /sn:0 /R:2 /w:[ 0 ] FourTwoEncoder g9 (.A(RST), .B(PLUS), .C(LOAD), .D(w18), .X(w20), .Y(w19)); //: @(210, 569) /sz:(102, 125) /sn:0 /p:[ Bi0>3 Bi1>5 Bi2>5 Bi3>1 To0<1 To1<1 ] //: joint g15 (LOAD) @(271, 765) /w:[ 2 4 -1 1 ] //: joint g20 (w7) @(480, 362) /w:[ 2 8 -1 1 ] //: joint g17 (RST) @(230, 779) /w:[ 1 2 -1 4 ] //: DIP g5 (w6) @(508,165) /sn:0 /R:3 /w:[ 1 ] /st:1 //: IN g14 (LOAD) @(271,834) /sn:0 /R:1 /w:[ 0 ] //: INOUT g24 (BUS) @(733,362) /sn:0 /R:2 /w:[ 3 ] //: joint g21 (w7) @(532, 362) /w:[ 4 -1 3 6 ] //: IN g23 (CLK) @(411,511) /sn:0 /R:1 /w:[ 0 ] _GGREG8 #(10, 10, 20) g0 (.Q(w7), .D(w13), .EN(w3), .CLR(w11), .CK(CLK)); //: @(411,411) /sn:0 /R:1 /w:[ 0 1 1 1 1 ] //: IN g22 (OE) @(570,280) /sn:0 /R:3 /w:[ 0 ] _GGNOR3 #(6) g12 (.I0(LOAD), .I1(PLUS), .I2(RST), .Z(w18)); //: @(291,738) /sn:0 /R:1 /w:[ 3 3 0 0 ] //: joint g18 (BUS) @(607, 362) /w:[ 2 -1 1 4 ] endmodule //: /netlistEnd //: /netlistBegin REGISTER module REGISTER(CLK, OUT, BUS, WRITE); //: interface /sz:(131, 140) /bd:[ Li0>CLK(35/140) Li1>OUT(70/140) Li2>WRITE(105/140) Rt0=BUS[7:0](35/140) ] //: property prot_intf=1 inout [7:0] BUS; //: /sn:0 {0}(681,302)(590,302){1} //: {2}(586,302)(577,302){3} //: {4}(588,304)(588,422)(260,422)(260,312)(321,312){5} supply0 w3; //: /sn:0 {0}(462,213)(462,264){1} supply1 w1; //: /sn:0 {0}(452,192)(452,264){1} input WRITE; //: /sn:0 {0}(337,325)(337,369){1} input CLK; //: /sn:0 {0}(457,340)(457,370){1} input OUT; //: /sn:0 {0}(569,210)(569,297){1} wire [7:0] w0; //: /sn:0 {0}(467,302)(490,302){1} //: {2}(494,302)(561,302){3} //: {4}(492,300)(492,142)(263,142)(263,292)(321,292){5} wire [7:0] w8; //: /sn:0 {0}(350,302)(446,302){1} //: enddecls //: joint g4 (w0) @(492, 302) /anc:1 /w:[ 2 4 1 -1 ] //: joint g8 (BUS) @(588, 302) /anc:1 /w:[ 1 -1 2 4 ] _GGBUFIF8 #(4, 6) g3 (.Z(BUS), .I(w0), .E(OUT)); //: @(567,302) /sn:0 /anc:1 /w:[ 3 3 1 ] //: IN g2 (CLK) @(457,372) /sn:0 /R:1 /anc:1 /w:[ 1 ] _GGMUX2x8 #(8, 8) g1 (.I0(w0), .I1(BUS), .S(WRITE), .Z(w8)); //: @(337,302) /sn:0 /R:1 /anc:1 /w:[ 5 5 0 0 ] /ss:0 /do:1 //: GROUND g10 (w3) @(462,207) /sn:0 /R:2 /anc:1 /w:[ 0 ] //: IN g6 (OUT) @(569,208) /sn:0 /R:3 /anc:1 /w:[ 0 ] //: INOUT g7 (BUS) @(689,302) /sn:0 /R:2 /anc:1 /w:[ 0 ] //: VDD g9 (w1) @(463,192) /sn:0 /anc:1 /w:[ 0 ] //: IN g5 (WRITE) @(337,371) /sn:0 /R:1 /anc:1 /w:[ 1 ] _GGREG8 #(10, 10, 20) g0 (.Q(w0), .D(w8), .EN(w3), .CLR(w1), .CK(CLK)); //: @(457,302) /sn:0 /R:1 /anc:1 /w:[ 0 1 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin UREGISTER module UREGISTER(OUT, WRITE, BUS, CLK); //: interface /sz:(120, 64) /bd:[ Li0>BUS[7:0](25/64) Bi0>WRITE(80/120) Bi1>CLK(37/120) Ro0A(16/80) Li1>B(32/80) Li2>C(48/80) Li3>D(64/80) Ro0 Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 1'bz; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/xx.v000644 001751 001751 00000000730 10251464313 017071 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "x.v" //: /netlistBegin main module main; //: root_module wire w0; //: /sn:0 {0}(155,118)(155,133){1} wire w3; //: /sn:0 {0}(165,162)(165,177){1} wire w1; //: /sn:0 {0}(175,118)(175,133){1} wire w2; //: /sn:0 {0}(127,149)(142,149){1} //: enddecls _GGMUX2 #(8, 8) g0 (.I0(w0), .I1(w1), .S(w2), .Z(w3)); //: @(165,149) /sn:0 /anc:1 /w:[ 1 1 1 0 ] /ss:0 /do:0 endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/y.v000644 001751 001751 00000001130 10270477533 016706 0ustar00hansenhansen000000 000000 module top; wire z; foo f1 (); foo #(4) f2(); foo #(5) f3(); OSCILLATOR g1(z); initial $monitor("z=%d",z); endmodule module foo #(.Z(2)); parameter Z2 = Z/2; parameter Z3 = Z2*3; initial $display("Z=%d Z2=%d",Z,Z2); endmodule module OSCILLATOR #(.HZ(1000)) (Z); parameter HZ0 = HZ/2; parameter HZ1 = HZ - HZ0; output Z; reg Z; time t; initial t = 0; always begin Z = 1'b0; if (t == 0) t = $tkg$systime; t = t + HZ0; $tkg$waituntil(t); Z = 1'b1; t = t + HZ1; $tkg$waituntil(t); end endmodule tkgate-2.0-b10/test/tkgate/VonNeumann.mem000644 001751 001751 00000007271 10373515715 021046 0ustar00hansenhansen000000 000000 memory MicrocodeROM 00/ 00000001 01860510 01860511 02890315 02890317 0186051a 0002001f 02890320 08/ 02890324 02890327 0289032a 0289032d 00000000 00000000 00000000 00000000 10/ 20000000 00080412 01b90313 80408714 00000001 80300016 00008701 80304218 18/ 00108f19 80400001 0008041b 0050021c 0289031d 8030001e 00100201 00040401 20/ 80304221 00008722 01860523 40000101 80304225 04908f26 80400001 80304228 28/ 07908f29 80400001 8030422b 05108f2c 80400001 8030422e 05908f2f 80400001 30/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 38/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 40/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 48/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 50/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 58/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 60/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 68/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 70/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 78/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 88/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 90/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 98/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 a0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 a8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 b0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 b8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 d0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 d8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 e0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 e8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 f0/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 f8/ 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 memory TextROM 00/ 2 3 2 2 9 7 9 6 08/ 2 6 9 0 0 0 0 0 10/ 0 0 0 0 0 0 0 0 18/ 0 0 0 0 0 0 0 0 20/ 0 0 0 0 0 0 0 0 28/ 0 0 0 0 0 0 0 0 30/ 0 0 0 0 0 0 0 0 38/ 0 0 0 0 0 0 0 0 40/ 0 0 0 0 0 0 0 0 48/ 0 0 0 0 0 0 0 0 50/ 0 0 0 0 0 0 0 0 58/ 0 0 0 0 0 0 0 0 60/ 0 0 0 0 0 0 0 0 68/ 0 0 0 0 0 0 0 0 70/ 0 0 0 0 0 0 0 0 78/ 0 0 0 0 0 0 0 0 80/ 0 0 0 0 0 0 0 0 88/ 0 0 0 0 0 0 0 0 90/ 0 0 0 0 0 0 0 0 98/ 0 0 0 0 0 0 0 0 a0/ 0 0 0 0 0 0 0 0 a8/ 0 0 0 0 0 0 0 0 b0/ 0 0 0 0 0 0 0 0 b8/ 0 0 0 0 0 0 0 0 c0/ 0 0 0 0 0 0 0 0 c8/ 0 0 0 0 0 0 0 0 d0/ 0 0 0 0 0 0 0 0 d8/ 0 0 0 0 0 0 0 0 e0/ 0 0 0 0 0 0 0 0 e8/ 0 0 0 0 0 0 0 0 f0/ 0 0 0 0 0 0 0 0 f8/ 0 0 0 0 0 0 0 0 memory DataRAM 00/ 11 51 1 3 0 0 0 0 08/ 0 0 0 0 0 0 0 0 10/ 0 0 0 0 0 0 0 0 18/ 0 0 0 0 0 0 0 0 20/ 0 0 0 0 0 0 0 0 28/ 0 0 0 0 0 0 0 0 30/ 0 0 0 0 0 0 0 0 38/ 0 0 0 0 0 0 0 0 40/ 0 0 0 0 0 0 0 0 48/ 0 0 0 0 0 0 0 0 50/ 0 0 0 0 0 0 0 0 58/ 0 0 0 0 0 0 0 0 60/ 0 0 0 0 0 0 0 0 68/ 0 0 0 0 0 0 0 0 70/ 0 0 0 0 0 0 0 0 78/ 0 0 0 0 0 0 0 0 80/ 0 0 0 0 0 0 0 0 88/ 0 0 0 0 0 0 0 0 90/ 0 0 0 0 0 0 0 0 98/ 0 0 0 0 0 0 0 0 a0/ 0 0 0 0 0 0 0 0 a8/ 0 0 0 0 0 0 0 0 b0/ 0 0 0 0 0 0 0 0 b8/ 0 0 0 0 0 0 0 0 c0/ 0 0 0 0 0 0 0 0 c8/ 0 0 0 0 0 0 0 0 d0/ 0 0 0 0 0 0 0 0 d8/ 0 0 0 0 0 0 0 0 e0/ 0 0 0 0 0 0 0 0 e8/ 0 0 0 0 0 0 0 0 f0/ 0 0 0 0 0 0 0 0 f8/ 0 0 0 0 0 0 0 0 tkgate-2.0-b10/test/tkgate/VonNeumann.v000644 001751 001751 00000110727 10373515700 020530 0ustar00hansenhansen000000 000000 //: version "1.6i" module ALU(F, B, N, C, A, Z); //: interface /sz:(180, 121) /bd:[ Ri0>B[7:0](21/121) Ri1>A[7:0](58/121) Ri2>F[3:0](105/121) Lo0rst(200/360) Li1>clk(166/360) Li2>PI[7:0](82/360) Ri0>MD[31:0](327/360) Ri1>DI[7:0](170/360) Lo01 Ri1>1 Ri2>1 Lo0<1 Lo1<1 Lo2<21 ] //: switch g5 (w3) @(415,100) /sn:0 /anc:1 /w:[ 0 ] /st:1 led g117 (.I(w49)); //: @(1950,-366) /sn:0 /anc:1 /w:[ 0 ] /type:0 led g95 (.I(w24)); //: @(1133,596) /sn:0 /R:2 /anc:1 /w:[ 9 ] /type:2 //: joint g94 (w28) @(1134, 449) /anc:1 /w:[ 5 -1 6 12 ] //: joint g44 (w7) @(744, 507) /anc:1 /w:[ 10 9 -1 12 ] //: comment g47 /dolink:0 /link:"" @(702,165) /sn:0 /R:1 //: /line:"C Bus" //: /end //: comment g80 /dolink:0 /link:"" @(1701,151) /sn:0 /anc:1 //: /line:"MBR addr" //: /end //: joint g79 (w45) @(2081, -25) /anc:1 /w:[ 30 29 -1 32 ] //: joint g21 (w25) @(985, 96) /anc:1 /w:[ -1 9 10 12 ] //: joint g92 (w30) @(1134, 335) /anc:1 /w:[ 3 -1 4 10 ] //: joint g36 (w45) @(784, 563) /anc:1 /w:[ 20 19 -1 22 ] //: joint g24 (w25) @(985, 213) /anc:1 /w:[ 14 13 16 18 ] //: joint g105 (w25) @(985, -63) /anc:1 /w:[ 2 -1 1 8 ] //: supply0 g84 (w36) @(2052,290) /sn:0 /anc:1 /w:[ 0 ] led g85 (.I(w35)); //: @(2057,369) /sn:0 /anc:1 /w:[ 1 ] /type:0 //: joint g23 (w45) @(784, 218) /anc:1 /w:[ 8 7 -1 10 ] //: joint g41 (w25) @(985, 558) /anc:1 /w:[ -1 29 30 32 ] //: comment g116 /dolink:0 /link:"" @(1445,-74) /sn:0 /anc:1 //: /line:"Delay to allow the" //: /line:"rest of the circuit" //: /line:"to catch up." //: /end or g101 (.I0(w18), .I1(rst), .Z(w25)); //: @(895,-63) /sn:0 /anc:1 /w:[ 1 1 0 ] led g93 (.I(w28)); //: @(1134,466) /sn:0 /R:2 /anc:1 /w:[ 13 ] /type:2 //: comment g81 /dolink:0 /link:"" @(840,966) /sn:0 /anc:1 //: /line:"0000 = A + B" //: /line:"0001 = A and B" //: /line:"0010 = A or B" //: /line:"0011 = INC A" //: /line:"0100 = INC B" //: /line:"0101 = DEC A" //: /line:"0110 = DEC B" //: /line:"0111 = Left shift A" //: /line:"1000 = Left shift B" //: /line:"1001 = A x B" //: /line:"1010 = B div A" //: /line:"1011 = B mod A" //: /line:"1100 = A xor B" //: /line:"1101 = NOT A" //: /line:"1110 = NOT B" //: /line:"1111 = B - A" //: /line:"" //: /end concat g60 (.I0(w23), .I1(w8), .I2(w12), .I3(w14), .I4(w57), .I5(w19), .I6(w17), .I7(w53), .I8(w37), .Z(w5)); //: @(1787,44) /sn:0 /anc:1 /w:[ 0 0 0 0 0 0 0 1 1 1 ] /dr:0 //: joint g40 (w25) @(985, 423) /anc:1 /w:[ -1 25 26 28 ] //: joint g54 (w30) @(1093, 335) /anc:1 /w:[ 5 -1 6 8 ] //: joint g90 (w42) @(1134, 234) /anc:1 /w:[ 4 -1 3 10 ] //: joint g35 (w45) @(784, 428) /anc:1 /w:[ 16 15 -1 18 ] //: comment g26 /dolink:0 /link:"" @(882,210) /sn:0 /anc:1 //: /line:"MAR" //: /end register g22 (.Q(w30), .D(w7), .EN(!w38), .CLR(!w25), .CK(w45)); //: @(887,319) /sn:0 /anc:1 /w:[ 7 0 1 23 13 ] //: joint g45 (w7) @(744, 641) /anc:1 /w:[ 14 13 -1 16 ] //: joint g46 (w7) @(744, 174) /anc:1 /w:[ 4 6 -1 3 ] //: joint g70 (w45) @(620, 101) /w:[ 2 28 1 -1 ] //: joint g0 (w42) @(1332, 234) /w:[ 6 -1 5 8 ] //: comment g120 /dolink:0 /link:"" @(1958,-337) /sn:0 /anc:1 //: /line:"N=0" //: /end //: joint g114 (w57) @(1487, -31) /anc:1 /w:[ 2 -1 1 4 ] led g97 (.I(w20)); //: @(1134,732) /sn:0 /R:2 /anc:1 /w:[ 9 ] /type:2 led g82 (.I(DO)); //: @(1135,135) /sn:0 /R:2 /anc:1 /w:[ 13 ] /type:2 //: comment g66 /dolink:0 /link:"" @(1700,120) /sn:0 /anc:1 //: /line:"NEXT_ADDR" //: /end //: input g12 (PI) @(851,395) /sn:0 /anc:1 /w:[ 1 ] //: input g18 (rst) @(846,-61) /sn:0 /anc:1 /w:[ 0 ] led g91 (.I(w30)); //: @(1134,353) /sn:0 /R:2 /anc:1 /w:[ 11 ] /type:2 register g33 (.Q(w15), .D(w7), .EN(!w6), .CLR(!w25), .CK(w45)); //: @(883,837) /sn:0 /anc:1 /w:[ 7 19 1 37 27 ] //: joint g30 (w45) @(784, 319) /anc:1 /w:[ 12 11 -1 14 ] //: dip g108 (w41) @(1669,385) /sn:0 /R:1 /anc:1 /w:[ 0 ] /st:0 and g118 (.I0(w54), .I1(w52), .Z(w46)); //: @(1852,-341) /sn:0 /w:[ 0 1 0 ] mux g49 (.I0(w0), .I1(w15), .I2(w20), .I3(w24), .I4(w28), .I5(w30), .I6(w42), .I7(DO), .S(w8), .Z(w33)); //: @(1316,953) /sn:0 /anc:1 /w:[ 0 0 0 0 0 13 9 0 1 0 ] endmodule module main; //: root_module supply0 w14; //: /sn:0 {0}(366,391)(366,408){1} supply0 w11; //: /sn:0 /dp:1 {0}(444,211)(444,197){1} supply0 w13; //: /sn:0 /dp:1 {0}(-14,183)(-14,199){1} wire [7:0] w6; //: /sn:0 {0}(178,364)(308,364){1} //: {2}(312,364)(348,364){3} //: {4}(310,366)(310,375){5} wire [7:0] w7; //: /sn:0 /dp:5 {0}(60,120)(-32,120){1} //: {2}(-34,118)(-34,96){3} //: {4}(-36,120)(-66,120)(-66,156)(-32,156){5} wire w4; //: /sn:0 {0}(458,197)(458,207){1} //: {2}(460,209)(478,209)(478,137)(453,137){3} //: {4}(451,135)(451,123){5} //: {6}(451,139)(451,147){7} //: {8}(458,211)(458,236)(424,236)(424,196)(389,196){9} //: {10}(385,196)(280,196)(280,162)(178,162){11} //: {12}(387,198)(387,275){13} wire [7:0] w0; //: /sn:0 /dp:5 {0}(178,121)(325,121){1} //: {2}(327,119)(327,78){3} //: {4}(327,123)(327,170)(433,170){5} wire [31:0] w20; //: /sn:0 {0}(484,376)(484,366){1} //: {2}(486,364)(598,364)(598,449)(266,449)(266,401)(178,401){3} //: {4}(482,364)(383,364){5} wire [7:0] w1; //: /sn:0 {0}(178,204)(253,204)(253,280)(379,280){1} wire [7:0] w8; //: /sn:0 /dp:7 {0}(395,280)(559,280)(559,172){1} //: {2}(561,170)(614,170)(614,314)(226,314)(226,244)(178,244){3} //: {4}(559,168)(559,93)(387,93)(387,78){5} //: {6}(557,170)(468,170){7} wire w12; //: /sn:0 {0}(15,274)(60,274){1} wire [7:0] w5; //: /sn:0 /dp:2 {0}(3,156)(19,156){1} //: {2}(23,156)(60,156){3} //: {4}(21,154)(21,96){5} wire w9; //: /sn:0 /dp:1 {0}(14,240)(60,240){1} //: enddecls //: joint g8 (w8) @(559, 170) /anc:1 /w:[ 2 4 6 1 ] //: supply0 g4 (w11) @(444,217) /sn:0 /anc:1 /w:[ 0 ] led g13 (.I(w5)); //: @(21,89) /sn:0 /anc:1 /w:[ 5 ] /type:2 bufif1 g3 (.Z(w8), .I(w1), .E(w4)); //: @(385,280) /sn:0 /anc:1 /w:[ 0 1 13 ] //: comment g2 /dolink:0 /link:"" @(481,183) /sn:0 /anc:1 //: /line:"DATA RAM" //: /end //: comment g1 /dolink:0 /link:"" @(385,347) /sn:0 /R:2 /anc:1 //: /line:"Microcode ROM" //: /end //: comment g16 /dolink:0 /link:"" @(-47,48) /sn:0 /anc:1 //: /line:"Addr" //: /end //: comment g11 /dolink:0 /link:"" @(-91,168) /sn:0 /anc:1 //: /line:"Text ROM" //: /end led g28 (.I(w4)); //: @(451,116) /sn:0 /anc:1 /w:[ 5 ] /type:0 cpu g10 (.rst(w12), .clk(w9), .PI(w5), .MD(w20), .DI(w8), .PA(w7), .DA(w0), .MA(w6), .DO(w1), .DWE(w4)); //: @(61, 74) /sz:(116, 360) /sn:0 /anc:1 /p:[ Li0>1 Li1>1 Li2>3 Ri0>3 Ri1>3 Lo0<0 Ro0<0 Ro1<0 Ro2<0 Ro3<11 ] //: joint g27 (w4) @(458, 209) /w:[ 2 1 -1 8 ] //: joint g19 (w0) @(327, 121) /anc:1 /w:[ -1 2 1 4 ] led g6 (.I(w8)); //: @(387,71) /sn:0 /anc:1 /w:[ 5 ] /type:2 //: switch g9 (w12) @(-2,274) /sn:0 /anc:1 /w:[ 0 ] /st:0 //: switch g7 (w9) @(-3,240) /sn:0 /anc:1 /w:[ 0 ] /st:1 //: comment g20 /dolink:0 /link:"" @(315,29) /sn:0 /anc:1 //: /line:"Addr" //: /end //: joint g15 (w5) @(21, 156) /anc:1 /w:[ 2 4 1 -1 ] //: joint g29 (w4) @(451, 137) /anc:1 /w:[ 3 4 -1 6 ] //: comment g17 /dolink:0 /link:"" @(6,48) /sn:0 /anc:1 //: /line:"Inst" //: /end //: joint g25 (w20) @(484, 364) /w:[ 2 -1 4 1 ] //: joint g14 (w7) @(-34, 120) /anc:1 /w:[ 1 2 4 -1 ] //: supply0 g5 (w14) @(366,414) /sn:0 /anc:1 /w:[ 1 ] rom MicrocodeROM (.A(w6), .D(w20), .OE(w14)); //: @(366,365) /sn:0 /anc:1 /w:[ 3 5 0 ] led g24 (.I(w20)); //: @(484,383) /sn:0 /R:2 /anc:1 /w:[ 0 ] /type:2 //: comment g21 /dolink:0 /link:"" @(371,29) /sn:0 /anc:1 //: /line:"Data" //: /end ram DataRAM (.A(w0), .D(w8), .WE(!w4), .OE(w4), .CS(w11)); //: @(451,171) /sn:0 /anc:1 /w:[ 5 7 7 0 1 ] //: joint g23 (w6) @(310, 364) /anc:1 /w:[ 2 -1 1 4 ] //: joint g0 (w4) @(387, 196) /w:[ 9 -1 10 12 ] led g22 (.I(w6)); //: @(310,382) /sn:0 /R:2 /anc:1 /w:[ 5 ] /type:2 //: supply0 g26 (w13) @(-14,205) /sn:0 /anc:1 /w:[ 1 ] led g18 (.I(w0)); //: @(327,71) /sn:0 /anc:1 /w:[ 3 ] /type:2 led g12 (.I(w7)); //: @(-34,89) /sn:0 /anc:1 /w:[ 3 ] /type:2 rom TextROM (.A(w7), .D(w5), .OE(w13)); //: @(-14,157) /sn:0 /anc:1 /w:[ 5 0 0 ] endmodule tkgate-2.0-b10/test/tkgate/adder.v000644 001751 001751 00000002204 10462036637 017517 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module reg [7:0] w19; //: /sn:0 {0}(#:330,184)(330,158)(281,158)(281,145){1} reg [7:0] w0; //: /sn:0 {0}(362,184)(362,143)(461,143)(#:461,132){1} supply0 w11; //: /sn:0 {0}(386,220)(386,198)(370,198){1} wire w24; //: /sn:0 {0}(322,198)(312,198){1} wire [7:0] w22; //: /sn:0 {0}(#:321,239)(321,225)(346,225)(346,213){1} //: enddecls //: GROUND g43 (w11) @(386,226) /sn:0 /w:[ 0 ] //: DIP g42 (w19) @(281,135) /sn:0 /w:[ 1 ] /st:248 //: DIP g0 (w0) @(461,122) /sn:0 /w:[ 1 ] /st:0 _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(w0), .S(w22), .CI(w11), .CO(w24)); //: @(346,200) /sn:0 /w:[ 0 0 1 1 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/adder.vs000644 001751 001751 00000000301 10462036617 017674 0ustar00hansenhansen000000 000000 initial begin $monitor("%d: a=%d b=%d ci=%d : s=%d co=%d",$time,w19,w0,w11,w22,w24); w19 = 8'h0; w0 = 8'h5; #100 ; w19 = 8'h7; w0 = 8'h8; #100 ; #100 ; end tkgate-2.0-b10/test/tkgate/greek.v000644 001751 001751 00000003274 10500342072 017527 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "greek.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g1 @(195,37) /sn:0 //: /line:"α alpha " //: /line:"β beta " //: /line:"γ gamma " //: /line:"δ delta " //: /line:"ε epsilon " //: /line:"ζ zeta " //: /line:"η eta " //: /line:"θ theta " //: /line:"ι iota " //: /line:"κ kappa " //: /line:"λ lambda " //: /line:"μ mu " //: /line:"ν nu " //: /line:"ξ xi " //: /line:"ο omicron " //: /line:"π pi " //: /line:"ρ rho " //: /line:"ς sigmaf " //: /line:"σ sigma " //: /line:"τ tau " //: /line:"υ upsilon " //: /line:"φ phi " //: /line:"χ chi " //: /line:"ψ psi " //: /line:"ω omega " //: /line:"ϑ thetasym " //: /line:"ϒ upsih " //: /line:"ϖ piv " //: /line:"" //: /end //: comment g0 @(61,55) /sn:0 //: /line:"Α Alpha " //: /line:"Β Beta " //: /line:"Γ Gamma " //: /line:"Δ Delta " //: /line:"Ε Epsilon " //: /line:"Ζ Zeta " //: /line:"Η Eta " //: /line:"Θ Theta " //: /line:"Ι Iota " //: /line:"Κ Kappa " //: /line:"Λ Lambda " //: /line:"Μ Mu " //: /line:"Ν Nu " //: /line:"Ξ Xi " //: /line:"Ο Omicron " //: /line:"Π Pi " //: /line:"Ρ Rho " //: /line:"Σ Sigma " //: /line:"Τ Tau " //: /line:"Υ Upsilon " //: /line:"Φ Phi " //: /line:"Χ Chi " //: /line:"Ψ Psi " //: /line:"Ω Omega " //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/hanoi.v000644 001751 001751 00000017453 10500711051 017531 0ustar00hansenhansen000000 000000 /****************************************************************************\ * * * The Towers of Hanoi * * * \****************************************************************************/ /* * Setup up some global parameters, for ease of change. */ `define clk_period 20 `define setup_time 4 `define hold_time 1 /****************************************************************************\ * * * 'Basic building block' module definitions * * * \****************************************************************************/ module toggle(q, qbar, clk, toggle, reset); /* * A mixed style model of a T-type (toggle) flip-flop, * with a reset line and delays on the outputs. * This first part is behavioural code. */ output q, qbar; input clk, toggle, reset; reg q; always @(posedge clk) if (reset == 1) #5 q = 0; else if (toggle == 1) #6 q = ~q; /* This part is dataflow-style */ assign #1 qbar = ~q; endmodule /* toggle */ module effr(q, clk, enable, reset, d); /* * A behavioural model of an E-type (enable) flip-flop * with a reset signal, and delays on the outputs. */ output q; input clk, enable, reset, d; reg q; /* * This next block checks for timing violations of the * flip-flop's setup and hold times. */ specify $setup(d, posedge clk, `setup_time); $hold(posedge clk, d, `hold_time); endspecify /* * This is the actual code for the E-type. */ always @(posedge clk) if (reset == 1) #5 q = 0; else if (enable == 1) #6 q = d; endmodule /* effr */ module effs(q, clk, enable, set, d); /* * Another behavioural model of an E-type, this time with * a set line, and delays on the outputs. The same timing * checks as before are implemented here, too. */ output q; input clk, enable, set, d; reg q; specify $setup(d, posedge clk, `setup_time); $hold(posedge clk, d, `hold_time); endspecify always @(posedge clk) if (set == 1) #5 q = 1; else if (enable == 1) #6 q = d; endmodule /* effs */ /****************************************************************************\ * * * Now, the more complex modules for implementing the actual solution * * * \****************************************************************************/ module evenSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn); /* * A dataflow model of one bit slice of the full moves generator. * The only differences between this module and the oddSlice one * are in the initialisation values. (Note the types of the * flip-flops used.) */ inout [3:0] bus; output oneOut, zeroOut; input clk, init, oneIn, zeroIn; wire enable, tq, tqbar; wire [1:0] toPeg, fromPeg, new; toggle tog (tq, tqbar, clk, oneIn, init); effr to0 (toPeg[0], clk, enable, init, new[0]); effs to1 (toPeg[1], clk, enable, init, new[1]); effs from0 (fromPeg[0], clk, enable, init, toPeg[0]); effr from1 (fromPeg[1], clk, enable, init, toPeg[1]); assign #2 oneOut = oneIn & tq; assign #2 zeroOut = zeroIn & tqbar; assign #2 enable = zeroIn & tq; assign #2 new[1] = ~(toPeg[1] & fromPeg[1]); assign #2 new[0] = ~(toPeg[0] & fromPeg[0]); assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz; endmodule /* evenSlice */ module oddSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn); /* * See the comments for the evenSlice module. */ inout [3:0] bus; output oneOut, zeroOut; input clk, init, oneIn, zeroIn; wire enable, tq, tqbar; wire [1:0] toPeg, fromPeg, new; toggle tog (tq, tqbar, clk, oneIn, init); effs to0 (toPeg[0], clk, enable, init, new[0]); effs to1 (toPeg[1], clk, enable, init, new[1]); effs from0 (fromPeg[0], clk, enable, init, toPeg[0]); effr from1 (fromPeg[1], clk, enable, init, toPeg[1]); assign #2 oneOut = oneIn & tq; assign #2 zeroOut = zeroIn & tqbar; assign #2 enable = zeroIn & tq; assign #2 new[1] = ~(toPeg[1] & fromPeg[1]); assign #2 new[0] = ~(toPeg[0] & fromPeg[0]); assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz; endmodule /* evenSlice */ module start_button(go, clk, press); /* * A gate level model of the start button, with the functionality * as described elsewhere. */ output go; input clk, press; wire e_out, not_press; supply1 vdd; /* * This block checks that the pulse with on the input line is * wider than 3, otherwise it is invalid. */ specify specparam X = 3; $width(posedge press, X); endspecify effs st_0 (e_out, clk, vdd, press, vdd); not #(1) n_0 (not_press, press); and #(1) a_0 (go, e_out, not_press); endmodule /* start_button */ module tower(from_peg, to_peg, done, clk, start); /* * This is a dataflow model of the actual move generator - to * be thought of as a stack (or tower) of modules, each of which * with one disk of the puzzle. * * It brings together all of the other modules, and presents a * clean interface to the outside world, taking a 'start' signal * and returning a 'done' signal, once the sequence has been * completed. */ output [1:0] from_peg, to_peg; output done; input clk, start; wire [4:0] oneOut, zeroOut; wire [3:0] bus; wire init; supply1 vdd; start_button st_0(init, clk, start); oddSlice rung0 (bus, oneOut[0], zeroOut[0], clk, ~init, vdd, vdd); evenSlice rung1 (bus, oneOut[1], zeroOut[1], clk, ~init, oneOut[0], zeroOut[0]); oddSlice rung2 (bus, oneOut[2], zeroOut[2], clk, ~init, oneOut[1], zeroOut[1]); evenSlice rung3 (bus, oneOut[3], zeroOut[3], clk, ~init, oneOut[2], zeroOut[2]); oddSlice rung4 (bus, oneOut[4], zeroOut[4], clk, ~init, oneOut[3], zeroOut[3]); assign from_peg = bus[3:2]; assign to_peg = bus[1:0]; assign done = oneOut[4]; endmodule /* tower */ /****************************************************************************\ * * * The final stimulus module is used to check that the tower module works * * properly * * * \****************************************************************************/ module stimulus; /* * This is a behavioural model. It simply instantiates the tower * module, provides it with inputs and monitors its outputs. */ reg clk; reg button; wire [1:0] from, to; wire done; tower t_0(from, to, done, clk, button); initial begin clk = 0; forever #(`clk_period / 2) clk = ~clk; end initial begin button = 0; #(`clk_period*2) button = 1; #(`clk_period*2) button = 0; end always @(posedge clk) #(`clk_period - 1) if ( $time > `clk_period*5 && !done) $display($time, " From peg %d To peg %d", from, to); always @(posedge clk) if (done == 1) #`clk_period $stop; endmodule /* stimulus */ tkgate-2.0-b10/test/tkgate/hanoi2.v000644 001751 001751 00000017271 10504602666 017630 0ustar00hansenhansen000000 000000 /****************************************************************************\ * * * The Towers of Hanoi * * * \****************************************************************************/ /* * Setup up some global parameters, for ease of change. */ `define setup_time 4 `define hold_time 1 /****************************************************************************\ * * * 'Basic building block' module definitions * * * \****************************************************************************/ module toggle(q, qbar, clk, toggle, reset); /* * A mixed style model of a T-type (toggle) flip-flop, * with a reset line and delays on the outputs. * This first part is behavioural code. */ output q, qbar; input clk, toggle, reset; reg q; always @(posedge clk) if (reset == 1) #5 q = 0; else if (toggle == 1) #6 q = ~q; /* This part is dataflow-style */ assign #1 qbar = ~q; endmodule /* toggle */ module effr(q, clk, enable, reset, d); /* * A behavioural model of an E-type (enable) flip-flop * with a reset signal, and delays on the outputs. */ output q; input clk, enable, reset, d; reg q; /* * This next block checks for timing violations of the * flip-flop's setup and hold times. */ specify $setup(d, posedge clk, 4); $hold(posedge clk, d, 1); endspecify /* * This is the actual code for the E-type. */ always @(posedge clk) if (reset == 1) #5 q = 0; else if (enable == 1) #6 q = d; endmodule /* effr */ module effs(q, clk, enable, set, d); /* * Another behavioural model of an E-type, this time with * a set line, and delays on the outputs. The same timing * checks as before are implemented here, too. */ output q; input clk, enable, set, d; reg q; specify $setup(d, posedge clk, 4); $hold(posedge clk, d, 1); endspecify always @(posedge clk) if (set == 1) #5 q = 1; else if (enable == 1) #6 q = d; endmodule /* effs */ /****************************************************************************\ * * * Now, the more complex modules for implementing the actual solution * * * \****************************************************************************/ module evenSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn); /* * A dataflow model of one bit slice of the full moves generator. * The only differences between this module and the oddSlice one * are in the initialisation values. (Note the types of the * flip-flops used.) */ inout [3:0] bus; output oneOut, zeroOut; input clk, init, oneIn, zeroIn; wire enable, tq, tqbar; wire [1:0] toPeg, fromPeg, new; toggle tog (tq, tqbar, clk, oneIn, init); effr to0 (toPeg[0], clk, enable, init, new[0]); effs to1 (toPeg[1], clk, enable, init, new[1]); effs from0 (fromPeg[0], clk, enable, init, toPeg[0]); effr from1 (fromPeg[1], clk, enable, init, toPeg[1]); assign #2 oneOut = oneIn & tq; assign #2 zeroOut = zeroIn & tqbar; assign #2 enable = zeroIn & tq; assign #2 new[1] = ~(toPeg[1] & fromPeg[1]); assign #2 new[0] = ~(toPeg[0] & fromPeg[0]); assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz; endmodule /* evenSlice */ module oddSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn); /* * See the comments for the evenSlice module. */ inout [3:0] bus; output oneOut, zeroOut; input clk, init, oneIn, zeroIn; wire enable, tq, tqbar; wire [1:0] toPeg, fromPeg, new; toggle tog (tq, tqbar, clk, oneIn, init); effs to0 (toPeg[0], clk, enable, init, new[0]); effs to1 (toPeg[1], clk, enable, init, new[1]); effs from0 (fromPeg[0], clk, enable, init, toPeg[0]); effr from1 (fromPeg[1], clk, enable, init, toPeg[1]); assign #2 oneOut = oneIn & tq; assign #2 zeroOut = zeroIn & tqbar; assign #2 enable = zeroIn & tq; assign #2 new[1] = ~(toPeg[1] & fromPeg[1]); assign #2 new[0] = ~(toPeg[0] & fromPeg[0]); assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz; endmodule /* evenSlice */ module start_button(go, clk, press); /* * A gate level model of the start button, with the functionality * as described elsewhere. */ output go; input clk, press; wire e_out, not_press; supply1 vdd; /* * This block checks that the pulse with on the input line is * wider than 3, otherwise it is invalid. */ specify specparam X = 3; $width(posedge press, X); endspecify effs st_0 (e_out, clk, vdd, press, vdd); not #(1) n_0 (not_press, press); and #(1) a_0 (go, e_out, not_press); endmodule /* start_button */ module tower(from_peg, to_peg, done, clk, start); /* * This is a dataflow model of the actual move generator - to * be thought of as a stack (or tower) of modules, each of which * with one disk of the puzzle. * * It brings together all of the other modules, and presents a * clean interface to the outside world, taking a 'start' signal * and returning a 'done' signal, once the sequence has been * completed. */ output [1:0] from_peg, to_peg; output done; input clk, start; wire [4:0] oneOut, zeroOut; wire [3:0] bus; wire init; supply1 vdd; start_button st_0(init, clk, start); oddSlice rung0 (bus, oneOut[0], zeroOut[0], clk, ~init, vdd, vdd); evenSlice rung1 (bus, oneOut[1], zeroOut[1], clk, ~init, oneOut[0], zeroOut[0]); oddSlice rung2 (bus, oneOut[2], zeroOut[2], clk, ~init, oneOut[1], zeroOut[1]); evenSlice rung3 (bus, oneOut[3], zeroOut[3], clk, ~init, oneOut[2], zeroOut[2]); oddSlice rung4 (bus, oneOut[4], zeroOut[4], clk, ~init, oneOut[3], zeroOut[3]); assign from_peg = bus[3:2]; assign to_peg = bus[1:0]; assign done = oneOut[4]; endmodule /* tower */ /****************************************************************************\ * * * The final stimulus module is used to check that the tower module works * * properly * * * \****************************************************************************/ module stimulus; /* * This is a behavioural model. It simply instantiates the tower * module, provides it with inputs and monitors its outputs. */ reg clk; reg button; wire [1:0] from, to; wire done; tower t_0(from, to, done, clk, button); initial begin clk = 0; forever #(20 / 2) clk = ~clk; end initial begin button = 0; #(20*2) button = 1; #(20*2) button = 0; end always @(posedge clk) #(20 - 1) if ( $time > 20*5 && !done) $display($time, " From peg %d To peg %d", from, to); always @(posedge clk) if (done == 1) #20 $stop; endmodule /* stimulus */ tkgate-2.0-b10/test/tkgate/l1.v000644 001751 001751 00000001040 10423010736 016736 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "l1.v" //: /netlistBegin main module main; //: root_module wire w0; //: {0}#[45](161,187)(263,187){1} wire w1; //: /sn:0 {0}#(248,192)(263,192){1} wire MyWire; //: {0}#[55](284,190)(451,190){1} //: enddecls _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(MyWire)); //: @(274,190) /sn:0 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/l2.v000644 001751 001751 00000003416 10422515076 016756 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "l2.v" //: /netlistBegin main module main; //: root_module wire [7:0] w6; //: /sn:0 {0}#(478,266)(478,281){1} wire w7; //: /sn:0 {0}#(374,112)(389,112){1} wire w4; //: /sn:0 {0}#(409,529)(424,529){1} wire [7:0] w3; //: /sn:0 {0}#(478,302)#(478,373)(537,373){1} wire w0; //: /sn:0 {0}#(74,134)(89,134){1} wire w1; //: /sn:0 {0}#(74,139)(89,139){1} wire w8; //: /sn:0 {0}#(532,296)(517,296){1} wire w2; //: /sn:0 {0}#(338,109)(353,109){1} wire w10; //: /sn:0 {0}#(426,291)(441,291){1} wire w5; //: /sn:0 {0}#(445,527)(460,527){1} wire w9; //: /sn:0 {0}#(532,286)(517,286){1} wire FOOBAR; //: {0}#[50](424,524)(187,524)(187,304){1} //: {2}(189,302)(234,302)(234,114)(353,114){3} //: {4}[68](185,302)(119,302)(119,137)(110,137){5} //: enddecls _GGREG8 #(10, 10, 20) g4 (.Q(w3), .D(w6), .EN(w8), .CLR(w9), .CK(w10)); //: @(478,291) /sn:0 /w:[ 0 1 1 1 1 ] //: joint g3 (FOOBAR) @(187, 302) /w:[ 2 -1 4 1 ] _GGAND2 #(6) g2 (.I0(w2), .I1(FOOBAR), .Z(w7)); //: @(364,112) /sn:0 /w:[ 1 3 0 ] _GGAND2 #(6) g1 (.I0(FOOBAR), .I1(w4), .Z(w5)); //: @(435,527) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(FOOBAR)); //: @(100,137) /sn:0 /w:[ 1 1 5 ] endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/test/tkgate/label.v000644 001751 001751 00000003360 10423712227 017514 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "label.v" //: /netlistBegin main module main; //: root_module wire w6; //: /sn:0 {0}(587,324)(587,339){1} wire w7; //: /sn:0 {0}(374,112)(389,112){1} wire w4; //: /sn:0 {0}(409,529)(424,529){1} wire w0; //: /sn:0 {0}(140,135)(155,135){1} wire w3; //: /sn:0 {0}(567,324)(567,339){1} wire w1; //: /sn:0 {0}(140,140)(155,140){1} wire w8; //: /sn:0 {0}(539,355)(554,355){1} wire w2; //: /sn:0 {0}(338,109)(353,109){1} wire w11; //: /sn:0 {0}(478,440)(478,455){1} wire w12; //: /sn:0 {0}(430,471)(445,471){1} wire w10; //: /sn:0 {0}(458,440)(458,455){1} wire w13; //: /sn:0 {0}(468,484)(468,499){1} wire w5; //: /sn:0 {0}(445,527)(460,527){1} wire w9; //: /sn:0 {0}(577,368)(577,383){1} wire FOOBAR; //: {0}(424,524)(-50:293,524)(293,384)(80:187,384)(187,304){1} //: {2}(189,302)(234,302)(234,114)(353,114){3} //: {4}(185,302)(175,302)(175,153)(186,153)(186,138)(176,138){5} //: enddecls _GGMUX2 #(4, 2) g4 (.I0(w3), .I1(w6), .S(w8), .Z(w9)); //: @(577,355) /sn:0 /delay:" 4 2" /w:[ 1 1 1 0 ] /ss:0 /do:0 //: joint g3 (FOOBAR) @(187, 302) /w:[ 2 -1 4 1 ] _GGAND2 #(3) g2 (.I0(w2), .I1(FOOBAR), .Z(w7)); //: @(364,112) /sn:0 /delay:" 3" /w:[ 1 3 0 ] _GGAND2 #(6) g1 (.I0(FOOBAR), .I1(w4), .Z(w5)); //: @(435,527) /sn:0 /w:[ 0 1 0 ] foo #(.B(42)) g6 (); //: @(307, 278) /sz:(40, 40) /sn:0 /p:[ ] _GGMUX2 #(8, 8) g5 (.I0(w10), .I1(w11), .S(w12), .Z(w13)); //: @(468,471) /sn:0 /w:[ 1 1 1 0 ] /ss:0 /do:0 _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(FOOBAR)); //: @(166,138) /sn:0 /w:[ 1 1 5 ] endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(40, 40) /bd:[ ] //: enddecls module foo #(.A(8), .B(99)) (X,Y,Z); endmodule //: /hdlEnd tkgate-2.0-b10/test/tkgate/size.v000644 001751 001751 00000003461 10421233130 017376 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "size.v" //: /netlistBegin main module main; //: root_module wire [7:0] w6; //: /sn:0 {0}#(693,390)(693,405){1} wire w7; //: /sn:0 {0}(374,112)(389,112){1} wire w14; //: /sn:0 {0}#(498,77)(483,77){1} wire w4; //: /sn:0 {0}(409,529)(424,529){1} wire w15; //: /sn:0 {0}#(392,82)(407,82){1} wire w0; //: /sn:0 {0}(140,135)(155,135){1} wire w1; //: /sn:0 {0}(140,140)(155,140){1} wire [7:0] w8; //: /sn:0 {0}#(677,434)(677,449){1} wire w2; //: /sn:0 {0}(338,109)(353,109){1} wire [7:0] w11; //: /sn:0 {0}#(444,93)#(444,185)#(500,185)(500,244)(432,244)(432,323)(487,323){1} //: {2}(491,323)(542,323)#(542,369)(661,369)(661,405){3} //: {4}#(489,325)#(489,419)(385,419){5} wire [7:0] w12; //: /sn:0 {0}#(444,57)(444,72){1} wire w10; //: /sn:0 {0}#(653,419)(638,419){1} wire w13; //: /sn:0 {0}#(498,87)(483,87){1} wire w5; //: /sn:0 {0}(445,527)(460,527){1} wire w9; //: /sn:0 {0}#(716,419)(701,419){1} wire FOOBAR; //: /dp:(1,2,0) {0}(424,524)(293,524)(293,384)(187,384)(187,304){1} //: {2}(189,302)(234,302)(234,114)(353,114){3} //: {4}(185,302)(175,302)(175,153)(186,153)(186,138)(176,138){5} //: enddecls _GGADD8 #(68, 70, 62, 64) g4 (.A(w11), .B(w6), .S(w8), .CI(w9), .CO(w10)); //: @(677,421) /sn:0 /w:[ 3 1 0 1 0 ] //: joint g3 (FOOBAR) @(187, 302) /w:[ 2 -1 4 1 ] _GGAND2 #(6) g2 (.I0(w2), .I1(FOOBAR), .Z(w7)); //: @(364,112) /sn:0 /w:[ 1 3 0 ] _GGAND2 #(6) g1 (.I0(FOOBAR), .I1(w4), .Z(w5)); //: @(435,527) /sn:0 /w:[ 0 1 0 ] //: joint g6 (w11) @(489, 323) /w:[ 2 -1 1 4 ] _GGREG8 #(10, 10, 20) g5 (.Q(w11), .D(w12), .EN(w13), .CLR(w14), .CK(w15)); //: @(444,82) /sn:0 /w:[ 0 1 1 1 1 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(FOOBAR)); //: @(166,138) /sn:0 /w:[ 1 1 5 ] endmodule //: /netlistEnd tkgate-2.0-b10/test/tkgate/clock.v000644 001751 001751 00000000765 10254175727 017550 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: /netlistBegin main module main; //: root_module wire w0; //: /sn:0 {0}(270,191)(285,191){1} //: enddecls _GGCLOCK_P100_0_50 g0 (.Z(w0)); //: @(257,191) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 endmodule //: /netlistEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/vpd/coke.tcl000644 001751 001751 00000125635 10651436453 016247 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2005 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Tue Jul 24 13:55:55 2007 font create title_f -family helvetica -weight bold -size 66 font create button_f -family helvetica -weight bold -size 10 font create empty_f -family helvetica -size 8 font create coin_f -family helvetica -size 8 ############################################################################# # # Allow all proceedures in the coke machine to be executed from verilog. # if {[info exists tkgate_isInitialized]} { VPD::register CokeMachine VPD::allow CokeMachine::* } ############################################################################# # # TkGate Interactive Module for Coke machine # namespace eval CokeMachine { # size of the coke machine (do not change) variable mWidth 300 variable mHeight 520 # options variable useDollar # colors of cans in slots variable canColors {red red gray50 orange blue darkred} # Array of windows for coke machines variable coke_w # number of each type of coin available for spending variable numQuarters variable numDimes variable numNickles variable numDollars variable numBogus # number of cans that have been bought variable numBought # number of each type of drink variable numCans # number of coins each type available for change variable numChange variable changeQuarters variable changeDimes variable changeNickles # number of coins each type held in machine variable holdQuarters variable holdDimes variable holdNickles variable holdDollars variable holdBogus # number of coins each type inserted into machine variable insertQuarters variable insertDimess variable insertNickles variable displayCost variable ENABLED ############################################################################# # # Input signals # # lights variable isEmpty variable noChange variable billLight # input to bill reader and bill in scanner variable readyBill variable scannerBill ############################################################################# # # Output signals # variable osigPRESS variable osigEMPTY variable osigINSQ variable osigINSD variable osigINSN variable osigNUMQ variable osigNUMD variable osigNUMN variable osigBILLSNS variable osigBILLOK variable osigBILLNG variable osigBILLACK variable osigCNRET ############################################################################# # # Pending insertions # variable pendingCoins ############################################################################# # # Initialize the coke machine. # proc initState {n} { variable coke_w variable numBought variable numQuarters variable numDimes variable numNickles variable changeQuarters variable changeDimes variable changeNickles variable holdQuarters variable holdDimes variable holdNickles variable holdDollars variable holdBogus variable insertQuarters variable insertDimes variable insertNickles variable numDollars variable numBogus variable isEmpty variable numCans variable numChange variable noChange variable billLight variable readyBill variable scannerBill variable osigPRESS variable osigEMPTY variable osigNUMQ variable osigNUMD variable osigNUMN variable osigINSQ variable osigINSD variable osigINSN variable osigBILLSNS variable osigBILLOK variable osigBILLNG variable osigBILLACK variable osigCNRET variable pendingCoins variable canColors # puts "CokeMachine::initState-1" set w "." catch { set w $coke_w($n) } set numQuarters($n) 20 # puts "CokeMachine::initState-1a" set numDimes($n) 20 set numNickles($n) 20 set numDollars($n) 20 set numBogus($n) 20 set isEmpty($n) {0 0 0 0 0 0} set numCans($n) {10 12 8 7 15 11} set numChange($n) {10 8 10} # puts "CokeMachine::initState-1b" set changeQuarters($n) 10 set changeDimes($n) 10 set changeNickles($n) 10 set holdQuarters($n) 0 set holdDimes($n) 0 set holdNickles($n) 0 set holdDollars($n) 0 set holdBogus($n) 0 # puts "CokeMachine::initState-1c" set insertQuarters($n) 0 set insertDimes($n) 0 set insertNickles($n) 0 set pendingCoins($n) {} # puts "CokeMachine::initState-1d" set noChange($n) 0 # puts "CokeMachine::initState-1e" set billLight($n) 0 # puts "CokeMachine::initState-1f" if {[catch { set readyBill($n) "" } xxx]} { puts "CokeMachine::xxx=$xxx" } # puts "CokeMachine::initState-1g" set scannerBill($n) "" # puts "CokeMachine::initState-2" set numBought($n) 0 catch { $w.c delete boughtCans } for {set i 0 } { $i < 6 } { incr i } { catch { reloadHopper $w.c.int.h$i $n -color [lindex $canColors $i] -column $i } } set osigPRESS($n) {0 0 0 0 0 0} set osigEMPTY($n) {0 0 0 0 0 0} set osigNUMQ($n) 7 set osigNUMD($n) 7 set osigNUMN($n) 7 set osigINSQ($n) 0 set osigINSD($n) 0 set osigINSN($n) 0 set osigBILLSNS($n) 0 set osigBILLOK($n) 0 set osigBILLNG($n) 0 set osigBILLACK($n) 0 set osigCNRET($n) 0 # puts "CokeMachine::initState-3" } ############################################################################# # # Respond to a change in the bill that is in the scanner. # proc seeScannerBill {n args} { variable coke_w variable scannerBill variable osigBILLOK variable osigBILLNG $coke_w($n).c.int delete scanBill switch $scannerBill($n) { D { makeDollar $coke_w($n).c.int 254 135 -tag scanBill } B { makeBogus $coke_w($n).c.int 254 135 -tag scanBill } } switch $scannerBill($n) { D { set osigBILLOK($n) 1; set osigBILLNG($n) 0 } B { set osigBILLOK($n) 0; set osigBILLNG($n) 1 } default { set osigBILLOK($n) 0; set osigBILLNG($n) 0 } } } ############################################################################# # # Pickup a bill that is in the "ready" slot. # proc pickupReady {n args} { set dw [Dragger::make -command "CokeMachine::dropCoin $n $CokeMachine::readyBill($n)" -bd 0] makeDragCoin $dw $n $CokeMachine::readyBill($n) set CokeMachine::readyBill($n) "" } ############################################################################# # # Respond to a change in the "ready" bill. The ready bill is the one that # is ready to be sucked into the scanner. # proc seeReadyBill {n args} { variable coke_w variable readyBill variable osigBILLSNS puts "CokeMachine::seeReadyBill" set w $coke_w($n).c.ext.dslot $w delete readyBill switch $readyBill($n) { D { makeDollar $w 25 22 -tag readyBill } B { makeBogus $w 25 22 -tag readyBill } } if { $readyBill($n) != "" } { $w bind readyBill <1> "CokeMachine::pickupReady $n" set osigBILLSNS($n) 1 } else { puts "CokeMachine::seeReadyBill-1" set osigBILLSNS($n) 0 puts "CokeMachine::seeReadyBill-2" } } ############################################################################# # # Make a coin/bill that can be dragged around. # proc makeDragCoin {dw n coin} { if { $dw != "" } { switch $coin { 25 { canvas $dw.c -width 25 -height 23 makeCoin $dw.c 12 12 -value 25 } 10 { canvas $dw.c -width 19 -height 18 makeCoin $dw.c 9 10 -value 10 } 5 { canvas $dw.c -width 22 -height 20 makeCoin $dw.c 10 11 -value 5 } D { canvas $dw.c -width 27 -height 17 makeDollar $dw.c 14 9 } B { canvas $dw.c -width 27 -height 17 makeBogus $dw.c 14 9 } A { canvas $dw.c -width 35 -height 35 makeCoin $dw.c 20 12 -value 25 makeCoin $dw.c 10 25 -value 10 makeCoin $dw.c 25 12 -value 5 } } pack $dw.c } } ############################################################################# # # Select a coin which has been selected with the mouse button # proc selectCoin {n coin x y} { variable numQuarters variable numDimes variable numNickles variable numDollars variable numBogus variable ENABLED if {!$ENABLED($n)} return set ok 0 # # check for availability of funds # switch $coin { 25 { if {$numQuarters($n) > 0} { set ok 1}} 10 { if {$numDimes($n) > 0} { set ok 1}} 5 { if {$numNickles($n) > 0} { set ok 1}} D { if {$numDollars($n) > 0} { set ok 1}} B { if {$numBogus($n) > 0} { set ok 1}} } if {!$ok} return set dw [Dragger::make -command "CokeMachine::dropCoin $n $coin" -bd 0] makeDragCoin $dw $n $coin switch $coin { 25 { incr numQuarters($n) -1 } 10 { incr numDimes($n) -1 } 5 { incr numNickles($n) -1 } D { incr numDollars($n) -1 } B { incr numBogus($n) -1 } } } ############################################################################# # # Return a coin (bill) that was not put into the slot (bill reader) # proc returnCoin {n coin w x y} { variable numQuarters variable numDimes variable numNickles variable numDollars variable numBogus switch $coin { 25 { incr numQuarters($n) } 10 { incr numDimes($n) } 5 { incr numNickles($n) } D { incr numDollars($n) } B { incr numBogus($n) } } } ############################################################################# # # Respond to a change in the acknowledge line # proc insertAck {n args} { variable osigINSQ variable osigINSD variable osigINSN variable pendingCoins variable ENABLED if {!$ENABLED($n)} return set value 1 parseargs $args {-value -tag} if { $value } { set osigINSQ($n) 0 set osigINSD($n) 0 set osigINSN($n) 0 } else { set pendingCoins($n) [lrange $pendingCoins($n) 1 end] if {[llength $pendingCoins($n)] > 0} { switch [lindex $pendingCoins($n) 0] { 25 { set osigINSQ($n) 1 } 10 { set osigINSD($n) 1 } 5 { set osigINSN($n) 1 } } } } } ############################################################################# # # Respond to a coin (or bill) dropped in the coin slot (or bill reader) # proc dropCoin {n coin w x y} { variable insertQuarters variable insertDimes variable insertNickles variable readyBill variable coke_w variable osigINSQ variable osigINSD variable osigINSN variable osigBILLSNS variable pendingCoins set ok 0 if { $w == "$coke_w($n).c.ext.cslot" || $w == "$coke_w($n).c.ext.cslot.e"} { switch $coin { 25 { incr insertQuarters($n) if {[llength $pendingCoins($n)] == 0} { set osigINSQ($n) 1 } lappend pendingCoins($n) 25 set ok 1 } 10 { incr insertDimes($n) if {[llength $pendingCoins($n)] == 0} { set osigINSD($n) 1 } lappend pendingCoins($n) 10 set ok 1 } 5 { incr insertNickles($n) if {[llength $pendingCoins($n)] == 0} { set osigINSN($n) 1 } lappend pendingCoins($n) 5 set ok 1 } } } if { $w == "$coke_w($n).c.ext.dslot" && $readyBill($n) == ""} { if { $coin == "D" } { set readyBill($n) "D"; set ok 1 } if { $coin == "B" } { set readyBill($n) "B"; set ok 1 } if { $readyBill($n) != ""} { set osigBILLSNS($n) 1 } } if {!$ok} { set x [expr $x + [winfo rootx $w]] set y [expr $y + [winfo rooty $w]] set X 20 switch $coin { 25 { set Y 30 } 10 { set Y 60 } 5 { set Y 90 } D { set Y 120 } B { set Y 150 } } set X [expr $X + [winfo rootx $coke_w($n)]] set Y [expr $Y + [winfo rooty $coke_w($n)]] set dw [Dragger::make -command "CokeMachine::returnCoin $n $coin" -bd 0 -interactive 0] makeDragCoin $dw $n $coin Dragger::animate -speed 10 Dragger::animate -step 30 Dragger::animate $x $y $X $Y } } ############################################################################# # # Make a coin of a particular demonination. # proc makeCoin {w x y args} { set size 10 set tag "" set value 25 parseargs $args {-value -tag} if {$value == 25 } { set size 10 } if {$value == 10 } { set size 8 } if {$value == 5 } { set size 9 } set x1 [expr $x - $size] set y1 [expr $y - $size] set x2 [expr $x + $size] set y2 [expr $y + $size] $w create oval $x1 $y1 $x2 $y2 -fill gray20 -tags $tag incr x1 2 incr y1 -1 incr x2 2 incr y2 -1 $w create oval $x1 $y1 $x2 $y2 -fill gray50 -tags $tag $w create text [expr $x + 2] $y -text $value -font coin_f -tags $tag } ############################################################################# # # Make a dollar bill # proc makeDollar {w x y args} { set tag "" parseargs $args {-tag} set x1 [expr $x - 13] set y1 [expr $y - 8] set x2 [expr $x + 13] set y2 [expr $y + 8] $w create rectangle $x1 $y1 $x2 $y2 -fill "\#008800" -tags $tag $w create text $x $y -text "\$1" -tags $tag } ############################################################################# # # Make a bogus bill # proc makeBogus {w x y args} { set tag "" parseargs $args {-tag} set x1 [expr $x - 13] set y1 [expr $y - 8] set x2 [expr $x + 13] set y2 [expr $y + 8] $w create rectangle $x1 $y1 $x2 $y2 -fill white -tags $tag $w create text $x $y -text "bogus" -font empty_f -tags $tag } ############################################################################# # # Make the list of coins that can be dragged and inserted into the machine. # proc makeCoinList {w n} { variable useDollar makeCoin $w 20 30 -value 25 -tag usrQuarter makeCoin $w 20 60 -value 10 -tag usrDime makeCoin $w 20 90 -value 5 -tag usrNickle $w bind usrQuarter <1> "CokeMachine::selectCoin $n 25 %x %y" $w bind usrDime <1> "CokeMachine::selectCoin $n 10 %x %y" $w bind usrNickle <1> "CokeMachine::selectCoin $n 5 %x %y" $w create text 40 30 -text "X" $w create text 40 60 -text "X" $w create text 40 90 -text "X" label $w.qcount -textvariable CokeMachine::numQuarters($n) $w create window 55 30 -window $w.qcount label $w.dcount -textvariable CokeMachine::numDimes($n) $w create window 55 60 -window $w.dcount label $w.ncount -textvariable CokeMachine::numNickles($n) $w create window 55 90 -window $w.ncount if {$useDollar($n)} { makeDollar $w 20 120 -tag usrDollar makeBogus $w 20 150 -tag usrBogus $w bind usrDollar <1> "CokeMachine::selectCoin $n D %x %y" $w bind usrBogus <1> "CokeMachine::selectCoin $n B %x %y" $w create text 40 120 -text "X" $w create text 40 150 -text "X" label $w.lcount -textvariable CokeMachine::numDollars($n) $w create window 55 120 -window $w.lcount label $w.bcount -textvariable CokeMachine::numBogus($n) $w create window 55 150 -window $w.bcount } } ############################################################################# # # See a change in cost # proc setCost {n value args} { variable displayCost set displayCost($n) [format "\$%0.2f" [expr $value * 0.05]] } ############################################################################# # # Respond to a change in the reset line. A falling edge resets the machine, # and a non-zero value allows the machine to operate. # proc resetMachine {n state args} { variable coke_w variable canColors variable ENABLED set w $coke_w($n) set ENABLED($n) $state if {$state == 0} { initState $n } } ############################################################################# # # See a change in any lights # proc seeLight {n args} { variable coke_w variable isEmpty variable noChange variable billLight variable useDollar for {set i 0 } { $i < 6 } { incr i } { if {[lindex $isEmpty($n) $i]} { $coke_w($n).c.ext.bbar.b$i.e configure -bg "\#ffcc40" -fg "\#904000" } else { $coke_w($n).c.ext.bbar.b$i.e configure -bg "\#a05010" -fg "\#904000" } } if {$noChange($n)} { $coke_w($n).c.ext.cslot.e configure -bg "\#ffcc40" -fg "\#904000" } else { $coke_w($n).c.ext.cslot.e configure -bg "\#a05010" -fg "\#904000" } if {$useDollar($n)} { if {$billLight($n)} { $coke_w($n).c.ext.dslot itemconfigure billok -fill green } else { $coke_w($n).c.ext.dslot itemconfigure billok -fill darkgreen } } } ############################################################################# # # Set the state of the empty light # proc setEmpty {n elist} { variable isEmpty set isEmpty($n) $elist } ############################################################################# # # Dispense product # proc dispense {n i} { variable coke_w variable canColors variable numBought variable mHeight variable osigEMPTY variable ENABLED if {!$ENABLED($n)} return set w $coke_w($n).c.int.h$i set L [winfo children $w] if {[llength $L] == 0 } return if {[llength $L] == 1 } { set osigEMPTY($n) [lreplace $osigEMPTY($n) $i $i 1] } set d [lindex $L [expr [llength $L]-1]] set w [winfo width $coke_w($n).c.int.h$i] set h [winfo height $coke_w($n).c.int.h$i] set x0 [expr [winfo rootx $coke_w($n).c.int.h$i] + $w/2] set y0 [expr [winfo rooty $coke_w($n).c.int.h$i] + $h] destroy $d set rX [winfo rootx $coke_w($n)] set rY [winfo rooty $coke_w($n)] set x1 [expr $rX + 500] set y1 [expr $rY + 460] set x2 [expr $rX + 200] set y2 [expr $rY + 460] set x3 [expr $rX + 25 + ($numBought($n) % 50)*14] set y3 [expr $rY + $mHeight + 45 + ($numBought($n) / 50)*30] set dw [Dragger::make -command "CokeMachine::drinkCan $n $i" -bd 0 -interactive 0] if {$dw != ""} { frame $dw.f -width 20 -height 15 -bg [lindex $canColors $i] pack $dw.f Dragger::animate -speed 10 Dragger::animate -step 10 Dragger::animate $x0 $y0 $x1 $y1 -jump $x2 $y2 $x3 $y3 } else { drinkCan $n $i } } ############################################################################# # # Add an empty can to the empties list # proc drinkCan {n i args} { variable coke_w variable numBought variable mHeight variable canColors set x [expr 25 + ($numBought($n) % 50)*14] set y [expr $mHeight + 45 + ($numBought($n) / 50)*30] $coke_w($n).c create rectangle $x $y [expr $x + 10] [expr $y + 18] -fill [lindex $canColors $i] -outline "" -tags boughtCans incr numBought($n) } ############################################################################# # # Dump coins into the coin hold # proc dumpInHold {n nQ nD nN args} { variable holdQuarters variable holdDimes variable holdNickles incr holdQuarters($n) $nQ incr holdDimes($n) $nD incr holdNickles($n) $nN } ############################################################################# # # Dump coins into the coin hold # proc dumpBack {n nQ nD nN args} { variable numQuarters variable numDimes variable numNickles incr numQuarters($n) $nQ incr numDimes($n) $nD incr numNickles($n) $nN } ############################################################################# # # Return inserted coins # proc returnInserted {n} { variable coke_w variable insertQuarters variable insertDimes variable insertNickles variable numQuarters variable numDimes variable numNickles variable ENABLED if {!$ENABLED($n)} return set L [list $insertQuarters($n) $insertDimes($n) $insertNickles($n)] if { $L == {0 0 0} } return set insertQuarters($n) 0 set insertDimes($n) 0 set insertNickles($n) 0 set X0 [winfo rootx $coke_w($n).c] set Y0 [winfo rooty $coke_w($n).c] set X1 [winfo rootx $coke_w($n).c.int] set Y1 [winfo rooty $coke_w($n).c.int] set dw [Dragger::make -command "CokeMachine::dumpBack $n $L" -bd 0 -interactive 0] if {$dw != ""} { makeDragCoin $dw $n A Dragger::animate -speed 10 Dragger::animate -step 40 Dragger::animate [expr $X1 + 250] [expr $Y1 + 200] [expr $X0 + 50] [expr $Y0 + 50] } else { set numQuarters($n) [lindex $L 0] set numDimes($n) [lindex $L 1] set numNickles($n) [lindex $L 2] } } ############################################################################# # # Commit inserted coins to buying a product # proc commitInserted {n} { variable insertQuarters variable insertDimes variable insertNickles variable holdQuarters variable holdDimes variable holdNickles variable coke_w variable ENABLED if {!$ENABLED($n)} return set L [list $insertQuarters($n) $insertDimes($n) $insertNickles($n)] if { $L == {0 0 0} } return set insertQuarters($n) 0 set insertDimes($n) 0 set insertNickles($n) 0 set X [winfo rootx $coke_w($n).c.int] set Y [winfo rooty $coke_w($n).c.int] set dw [Dragger::make -command "CokeMachine::dumpInHold $n $L" -bd 0 -interactive 0] if {$dw != ""} { makeDragCoin $dw $n A Dragger::animate -speed 20 Dragger::animate -step 20 Dragger::animate -offset $X $Y 250 200 200 250 200 350 250 450 } else { set holdQuarters($n) [lindex $L 0] set holdDimes($n) [lindex $L 1] set holdNickles($n) [lindex $L 2] } } ############################################################################# # # Eject change # proc ejectChange {n coin} { variable numQuarters variable numDimes variable numNickles variable changeQuarters variable changeDimes variable changeNickles variable osigNUMQ variable osigNUMD variable osigNUMN variable coke_w variable ENABLED if {!$ENABLED($n)} return set ok 0 switch $coin { 25 { if { $changeQuarters($n) > 0 } { incr changeQuarters($n) -1 incr numQuarters($n) set osigNUMQ($n) [min $changeQuarters($n) 7] set ok 1 } } 10 { if { $changeDimes($n) > 0 } { incr changeDimes($n) -1 incr numDimes($n) set osigNUMD($n) [min $changeDimes($n) 7] set ok 1 } } 5 { if { $changeNickles($n) > 0 } { incr changeNickles($n) -1 incr numNickles($n) set osigNUMN($n) [min $changeNickles($n) 7] set ok 1 } } } if {$ok} { set X [winfo rootx $coke_w($n)] set Y [winfo rooty $coke_w($n)] set dw [Dragger::make -bd 0 -interactive 0] if { $dw != "" } { makeDragCoin $dw $n $coin Dragger::animate -speed 20 Dragger::animate -step 20 Dragger::animate -offset $X $Y 300 400 20 50 } } } ############################################################################# # # Move bill into reader (and bill in reader into inserted coin bucket) # proc billIn {n args} { variable readyBill variable scannerBill variable holdDollars variable holdBogus variable osigBILLSNS variable osigBILLACK variable ENABLED if {!$ENABLED($n)} return set value 1 parseargs $args {-value} if {$value } { # Bill in signal is asserted switch $scannerBill($n) { D { incr holdDollars($n) } B { incr holdBogus($n) } } set scannerBill($n) $readyBill($n) set readyBill($n) "" set osigBILLSNS($n) 0 set osigBILLACK($n) 1 } else { # Bill in signal is unasserted set osigBILLACK($n) 0 } } ############################################################################# # # Reject bill in reader # proc billOut {n args} { variable readyBill variable scannerBill variable numDollars variable numBogus variable osigBILLSNS variable osigBILLACK variable ENABLED if {!$ENABLED($n)} return set value 1 parseargs $args {-value} if {$value} { switch $scannerBill($n) { D { incr numDollars($n) } B { incr numBogus($n) } } set scannerBill($n) "" switch $readyBill($n) { D { incr numDollars($n) } B { incr numBogus($n) } } set readyBill($n) "" set osigBILLSNS($n) 0 set osigBILLACK($n) 1 } else { set osigBILLACK($n) 0 } } ############################################################################# # # But a drink button into the "down" state. # proc buttonDown {w n id} { variable osigPRESS $w configure -relief sunken set osigPRESS($n) [lreplace $osigPRESS($n) $id $id 1] } ############################################################################# # # But a drink button into the "up" state. # proc buttonUp {w n id} { variable coke_w variable osigPRESS $w configure -relief raised set osigPRESS($n) [lreplace $osigPRESS($n) $id $id 0] } ############################################################################# # # Create a drink selection button # proc evButton {w n args} { set bcolor \#ffeedd set title "" set id 0 parseargs $args {-title -id} frame $w -bd 2 -relief raised -bg $bcolor label $w.e -text empty -font empty_f -bg "\#a05010" -fg "\#904000" -borderwidth 0 label $w.l -text $title -width 12 -font button_f -bg $bcolor pack $w.l -side bottom pack $w.e -side top -anchor w bind $w "CokeMachine::buttonDown $w $n $id" bind $w "CokeMachine::buttonUp $w $n $id" bind $w.e "CokeMachine::buttonDown $w $n $id" bind $w.e "CokeMachine::buttonUp $w $n $id" bind $w.l "CokeMachine::buttonDown $w $n $id" bind $w.l "CokeMachine::buttonUp $w $n $id" } ############################################################################# # # Create the button box # proc evButtonBox {w n args} { frame $w evButton $w.b0 $n -title Coke -id 0 evButton $w.b1 $n -title Coke -id 1 evButton $w.b2 $n -title "Diet Coke" -id 2 evButton $w.b3 $n -title "Root Beer" -id 3 evButton $w.b4 $n -title "Pocari Sweat" -id 4 evButton $w.b5 $n -title "Dr. Pepper" -id 5 pack $w.b0 pack $w.b1 pack $w.b2 pack $w.b3 pack $w.b4 pack $w.b5 } ############################################################################# # # Create the dollar bill reader external view # proc evDollarSlot {w args} { canvas $w -bg black -width 70 -height 30 -bg grey -bd 2 -relief raised $w create rectangle 10 10 40 25 -fill gray60 $w create rectangle 10 10 40 13 -fill gray40 $w create polygon 12 23 15 18 18 23 -fill green -tags billok $w create polygon 22 23 25 18 28 23 -fill green -tags billok $w create polygon 32 23 35 18 38 23 -fill green -tags billok $w create text 60 18 -text "\$1" } ############################################################################# # # Create the coin slot external view # proc evCoinSlot {w n args} { canvas $w -bg black -width 70 -height 60 -bg grey -bd 2 -relief raised # coin slot $w create line 65 10 65 32 -width 4 # label $w.e -text "no\nchange" -font empty_f -bg "\#a05010" -fg "\#904000" -borderwidth 0 $w create window 10 10 -window $w.e -anchor nw # coin return lever $w create polygon 10 40 35 40 35 45 20 45 15 50 10 45 -fill gray20 -tags coinReturnLev bind $w <1> "CokeMachine::setCRLever $n 1" bind $w "CokeMachine::setCRLever $n 0" # pack $w.slot -padx 10 -pady 20 } proc setCRLever {n state} { variable coke_w variable ENABLED variable osigCNRET if {!$ENABLED($n)} return set w $coke_w($n).c.ext.cslot set L {10 40 35 40 35 45 20 45 15 50 10 45} if { $state } { set R {} foreach {x y} $L { lappend R [expr -$y + 60] [expr $x + 25] } set osigCNRET($n) 1 eval "$w coords coinReturnLev $R" } else { set osigCNRET($n) 0 eval "$w coords coinReturnLev $L" } } ############################################################################# # # Create the coin return external view # proc evCoinReturn {w args} { canvas $w -bg black -width 35 -height 35 -bg grey -bd 2 -relief raised # coin return $w create rectangle 10 10 30 30 -fill gray20 } ############################################################################# # # Create the can out slot external view # proc evCanOutSlot {w args} { frame $w -bg black -width 175 -height 30 } ############################################################################# # # Create the drink cost window external view # proc evCostDisplay {w n} { variable displayCost frame $w -bd 2 -relief raised label $w.l -textvariable CokeMachine::displayCost($n) -width 5 -height 2 -bg white -fg red3 pack $w.l -padx 3 -pady 3 } proc reloadHopper {w n args} { variable numCans set width 25 set color red set column 0 parseargs $args {-width -height -color -column} set L [winfo children $w] set count [lindex $numCans($n) $column] for { set i [llength $L]} { $i < $count } { incr i } { frame $w.can$i -width [expr $width-4] -height [expr ($width-4)/2] -bd 0 -bg $color pack $w.can$i -padx 1 -pady 1 -side bottom } } ############################################################################# # # Create the can hopper internal view # proc ivCanHopper {w n args} { variable numCans set width 20 set height 250 set color red set column 0 parseargs $args {-width -height -color -column} frame $w -width $width -height $height -bd 2 -relief solid -bg white pack propagate $w 0 set count [lindex $numCans($n) $column] for { set i 0 } { $i < $count } { incr i } { frame $w.can$i -width [expr $width-4] -height [expr ($width-4)/2] -bd 0 -bg $color pack $w.can$i -padx 1 -pady 1 -side bottom } } ############################################################################# # # Create the bill reader internal view. # proc ivBillReader {w n} { variable mWidth variable mHeight # # copied from ivChangeHopper # set ch_w 50 set cs_x1 [expr $mWidth - 55] set cs_x2 [expr $mWidth - 35] set x_cent [expr ($cs_x1+$cs_x2)/2] set x1 [expr $x_cent - $ch_w/2] set x2 [expr $x_cent + $ch_w/2] set y1 120 set y2 150 $w create text $x_cent $y1 -text "Bill Scanner" -anchor s $w create rectangle $x1 $y1 $x2 $y2 -fill white -outline black -width 2 } ############################################################################# # # Create the money box internal view. # proc ivMoneyBox {w n} { variable mWidth variable mHeight variable useDollar # # copied from ivChangeHopper # set ch_w 75 set cs_x1 [expr $mWidth - 55] set cs_x2 [expr $mWidth - 35] set x_cent [expr ($cs_x1+$cs_x2)/2] set x3 [expr $x_cent - $ch_w/2] set x5 [expr $x_cent + $ch_w/2] set x1 [expr $x3 - 25] set x2 [expr $x3 - 5] set x4 [expr $x3 + 20] set y1 [expr $mHeight - 340] set y2 [expr $y1 + 58] set y3 [expr $y2 + 20] set y4 [expr $y3 + 25] set y5 [expr $mHeight - 142] set y6 [expr $mHeight - 117] set y7 [expr $mHeight - 5] $w create polygon $x3 $y1 $x3 $y3 $x1 $y4 $x1 $y5 $x3 $y6 $x3 $y7 $x5 $y7 $x5 $y6 \ $x4 $y6 $x2 $y5 $x2 $y4 $x4 $y3 $x5 $y3 $x5 $y1 -width 2 -fill white -outline black $w create text [expr $x_cent + 7] $y6 -text Collected -anchor s $w create text $x_cent $y1 -text Inserted -anchor s $w create text $x_cent 279 -text Change -anchor s # # Repository for money that has been used to purchase a product # set x [expr $x3 + 15] set y [expr $y6 + 15] if {$useDollar($n)} { set entries {D holdDollars B holdBogus 25 holdQuarters 10 holdDimes 5 holdNickles} } else { set entries {25 holdQuarters 10 holdDimes 5 holdNickles} } foreach {coin aname} $entries { if {$coin == "D"} { makeDollar $w $x $y } elseif {$coin == "B"} { makeBogus $w $x $y } else { makeCoin $w $x $y -value $coin } $w create text [expr $x + 20] $y -text "X" label $w.hld$coin -textvariable CokeMachine::${aname}($n) -bg white $w create window [expr $x + 35] $y -window $w.hld$coin incr y 21 } # # Repository for money that has been inserted but not committed # set x [expr $x3 + 15] set y [expr $y1 + 15] foreach {coin aname} {25 insertQuarters 10 insertDimes 5 insertNickles} { if {$coin == "D"} { makeDollar $w $x $y } elseif {$coin == "B"} { makeBogus $w $x $y } else { makeCoin $w $x $y -value $coin } $w create text [expr $x + 20] $y -text "X" label $w.ins$coin -textvariable CokeMachine::${aname}($n) -bg white $w create window [expr $x + 35] $y -window $w.ins$coin incr y 21 } } ############################################################################# # # Create the change hopper internal view # proc ivChangeHopper {w n} { variable mWidth variable mHeight # coin return slot set cs_x1 [expr $mWidth - 55] set cs_y1 [expr $mHeight - 155] set cs_x2 [expr $mWidth - 35] set cs_y2 [expr $mHeight - 135] # change box set ch_w 75 set ch_x1 [expr ($cs_x1+$cs_x2)/2 - $ch_w/2] set ch_x2 [expr ($cs_x1+$cs_x2)/2 + $ch_w/2] set ch_y1 281 set ch_y2 345 $w create polygon $cs_x1 $cs_y1 $ch_x1 $ch_y2 $ch_x1 $ch_y1 $ch_x2 $ch_y1 \ $ch_x2 $ch_y2 $cs_x2 $cs_y1 -width 2 -fill white -outline black set x [expr $ch_x1 + 15] set y [expr $ch_y1 + 15] foreach {coin aname} {25 changeQuarters 10 changeDimes 5 changeNickles} { makeCoin $w $x $y -value $coin $w create text [expr $x + 20] $y -text "X" label $w.chg$coin -textvariable CokeMachine::${aname}($n) -bg white $w create window [expr $x + 35] $y -window $w.chg$coin incr y 21 } $w create rectangle $cs_x1 $cs_y1 $cs_x2 $cs_y2 -fill gray20 } ############################################################################# # # External view of coke machine # proc externalView {w n} { variable mWidth variable mHeight variable useDollar set color "\#dd0000" frame $w -background $color -width $mWidth -height $mHeight # # "Soda" title on top of machine # label $w.title -text Soda -font title_f -background $color -foreground white place $w.title -x [expr $mWidth/2] -y 60 -anchor center # # Can out slot # evCanOutSlot $w.canout place $w.canout -x 25 -y [expr $mHeight - 80] -anchor w # # buttons # evButtonBox $w.bbar $n place $w.bbar -x 20 -y 120 -anchor nw # # Cost display # evCostDisplay $w.costwin $n place $w.costwin -x 120 -y 120 -anchor nw # # Dollar slot # if {$useDollar($n)} { evDollarSlot $w.dslot place $w.dslot -x [expr $mWidth - 20] -y 120 -anchor ne } # # Coin slot # evCoinSlot $w.cslot $n place $w.cslot -x [expr $mWidth - 20] -y 170 -anchor ne # # Coin return # evCoinReturn $w.creturn place $w.creturn -x [expr $mWidth - 20] -y [expr $mHeight - 120] -anchor se } ############################################################################# # # Create the internal view of the coke machine # proc internalView {w n args} { variable mWidth variable mHeight variable canColors variable useDollar canvas $w -width $mWidth -height $mHeight -bg tan set hwidth 25 for {set i 0 } { $i < 6 } { incr i } { ivCanHopper $w.h$i $n -width $hwidth -color [lindex $canColors $i] -column $i $w create window [expr 15 + ($hwidth+5) *$i] 70 -window $w.h$i -anchor nw } # change holder ivChangeHopper $w $n # change holder ivMoneyBox $w $n if {$useDollar($n)} { # Bill reader ivBillReader $w $n } # can output slot evCanOutSlot $w.co $w create window 25 [expr $mHeight - 80] -window $w.co -anchor w } ############################################################################# # # Unpost the coke machine and clean everything up # proc unpost {n} { variable coke_w variable useDollar set w $coke_w($n) unset coke_w($n) trace vdelete CokeMachine::isEmpty($n) w "CokeMachine::seeLight $n" trace vdelete CokeMachine::noChange($n) w "CokeMachine::seeLight $n" trace vdelete CokeMachine::billLight($n) w "CokeMachine::seeLight $n" if { $useDollar($n)} { trace vdelete CokeMachine::scannerBill($n) w "CokeMachine::seeScannerBill $n" trace vdelete CokeMachine::readyBill($n) w "CokeMachine::seeReadyBill $n" } destroy $w } ############################################################################# # # Post the coke machine window. # proc post {n args} { variable coke_w variable isEmpty variable mWidth variable mHeight variable useDollar variable displayCost variable ENABLED puts "CokeMachine::post $n $args" set displayCost($n) "" set ENABLED($n) 0 set dollar 1 parseargs $args {-dollar} set useDollar($n) $dollar # Initialize state to make sure all variables exist initState $n set i 0 set w "" set w [VPD::createWindow "Coke Machine $n" -shutdowncommand "CokeMachine::unpost $n"] set coke_w($n) $w canvas $w.c -width [expr 125 + 2*$mWidth] -height [expr 100 + $mHeight] pack $w.c externalView $w.c.ext $n internalView $w.c.int $n $w.c create window 75 25 -window $w.c.ext -anchor nw $w.c create window [expr 100 + $mWidth] 25 -window $w.c.int -anchor nw button $w.c.reset -text Reset -command "CokeMachine::resetMachine $n 0; CokeMachine::resetMachine $n 1" $w.c create window 4 [expr 25 + $mHeight] -window $w.c.reset -anchor sw makeCoinList $w.c $n trace variable CokeMachine::isEmpty($n) w "CokeMachine::seeLight $n" trace variable CokeMachine::noChange($n) w "CokeMachine::seeLight $n" trace variable CokeMachine::billLight($n) w "CokeMachine::seeLight $n" if { $useDollar($n)} { trace variable CokeMachine::scannerBill($n) w "CokeMachine::seeScannerBill $n" trace variable CokeMachine::readyBill($n) w "CokeMachine::seeReadyBill $n" } puts "CokeMachine::post-2 $n $args" if {[info exists ::tkgate_isInitialized]} { VPD::signal $n.PRESS CokeMachine::osigPRESS($n) VPD::signal $n.EMPTY CokeMachine::osigEMPTY($n) VPD::signal $n.INSQ CokeMachine::osigINSQ($n) VPD::signal $n.INSD CokeMachine::osigINSD($n) VPD::signal $n.INSN CokeMachine::osigINSN($n) VPD::signal $n.NUMQ CokeMachine::osigNUMQ($n) VPD::signal $n.NUMD CokeMachine::osigNUMD($n) VPD::signal $n.NUMN CokeMachine::osigNUMN($n) VPD::signal $n.BILLSNS CokeMachine::osigBILLSNS($n) VPD::signal $n.CNRET CokeMachine::osigCNRET($n) VPD::signal $n.BILLOK CokeMachine::osigBILLOK($n) VPD::signal $n.BILLNG CokeMachine::osigBILLNG($n) VPD::signal $n.BILLACK CokeMachine::osigBILLACK($n) VPD::insignal $n.NOCHG -variable CokeMachine::noChange($n) -format %d VPD::insignal $n.BILLLT -variable CokeMachine::billLight($n) -format %d } else { set ENABLED($n) 1 } puts "CokeMachine::post-3 $n $args" # Initialize state again to react to variable settings initState $n puts "CokeMachine::post-4 $n $args" } } ############################################################################# ############################################################################# # # Code from here down is used for debugging and is only invoked if this # script is run stand-alone. # if {![info exists tkgate_isInitialized]} { tk scaling 1 wm state . withdrawn source scripts/misc.tcl source scripts/simulator.tcl source scripts/udev.tcl source scripts/dragger.tcl proc updateEmpty {} { global emptyLight set L {} for {set i 0} { $i < 6 } { incr i } { lappend L $emptyLight($i) } set CokeMachine::isEmpty(test) $L } proc oDisplay {w vname} { frame $w label $w.l -text ${vname}: label $w.v -textvariable CokeMachine::${vname}(test) pack $w.l $w.v -side left pack $w -side left -padx 5 -pady 5 } CokeMachine::post test set w $CokeMachine::coke_w(test) frame $w.sep -bd 2 -relief sunken -height 6 pack $w.sep -padx 20 -fill x frame $w.b pack $w.b -fill both checkbutton $w.b.nochg -text "No Change" -variable CokeMachine::noChange(test) pack $w.b.nochg -side left -padx 5 -pady 5 if {$CokeMachine::useDollar(test)} { checkbutton $w.b.insdol -text "Insert Dollar" -variable CokeMachine::billLight(test) pack $w.b.insdol -side left -padx 5 -pady 5 } button $w.b.chg25 -text "Chg 25" -command "CokeMachine::ejectChange test 25" button $w.b.chg10 -text "Chg 10" -command "CokeMachine::ejectChange test 10" button $w.b.chg5 -text "Chg 5" -command "CokeMachine::ejectChange test 5" pack $w.b.chg25 $w.b.chg10 $w.b.chg5 -side left -padx 5 -pady 5 if {$CokeMachine::useDollar(test)} { button $w.b.billin -text "Bill In" -command "CokeMachine::billIn test" button $w.b.billout -text "Bill Out" -command "CokeMachine::billOut test" pack $w.b.billin $w.b.billout -side left -padx 5 -pady 5 } button $w.b.commit -text "Commit" -command "CokeMachine::commitInserted test" pack $w.b.commit -side left -padx 5 -pady 5 frame $w.b2 pack $w.b2 -fill both for {set i 0} { $i < 6 } { incr i } { checkbutton $w.b2.e$i -text "E$i" -variable emptyLight($i) -command updateEmpty pack $w.b2.e$i -side left -padx 5 -pady 5 } for {set i 0} { $i < 6 } { incr i } { button $w.b2.d$i -text "D$i" -command "CokeMachine::dispense test $i" pack $w.b2.d$i -side left -padx 5 -pady 5 } button $w.b2.rins -text "RETINS" -command "CokeMachine::returnInserted test" pack $w.b2.rins -padx 5 -pady 5 -side left ############################################################################# # # Output display # frame $w.sep2 -bd 2 -relief sunken -height 6 pack $w.sep2 -padx 20 -fill x frame $w.out1 pack $w.out1 -fill both oDisplay $w.out1.buttons osigPRESS oDisplay $w.out1.havecans osigEMPTY oDisplay $w.out1.numq osigNUMQ oDisplay $w.out1.numd osigNUMD oDisplay $w.out1.numn osigNUMN frame $w.out2 pack $w.out2 -fill both oDisplay $w.out2.insq osigINSQ oDisplay $w.out2.insd osigINSD oDisplay $w.out2.indn osigINSN if {$CokeMachine::useDollar(test)} { oDisplay $w.out2.billsns osigBILLSNS oDisplay $w.out2.billok osigBILLOK } oDisplay $w.out2.cnret osigCNRET } tkgate-2.0-b10/vpd/tty.tcl000644 001751 001751 00000005364 11117074274 016137 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Dec 7 20:30:36 2008 # #cut and paste into tty #bind $w " if { \[catch {selection get} sel\]==0 } { foreach c \[split \$sel \"\"\] { scan \$c %%c c; Simulator::cmdSend \"command $tkg_ttygat($w) key \$c\" } } " # # List of ttys # image create bitmap txtcurs -file "$bd/txtcurs.b" #Security::allow TTY::post #Security::allow TTY::data ############################################################################# # # Register the "safe" tty procedures # VPD::register TTY VPD::allow TTY::post VPD::allow TTY::data namespace eval TTY { variable tty_w variable TD proc post {n} { variable tty_w global simOn set w [VPD::createWindow "TTY $n" -shutdowncommand "TTY::unpost $n"] set tty_w($n) $w text $w.txt -state disabled pack $w.txt $w.txt image create end -image txtcurs bind $w "TTY::sendChar $n \"%A\"" if {[info exists ::tkgate_isInitialized]} { VPD::outsignal $n.TD TTY::TD($n) VPD::insignal $n.RD -command "TTY::data $n" -format %d VPD::insignal $n.FORCE -command "TTY::force $n" -format %s } } proc sendChar {n key} { variable TD if { [string length $key ] == 1 } { binary scan $key c c set TTY::TD($n) $c } } # # Send character c as if it were typed in the keyboard. # proc force {n c} { set L [string length $c] for { set i 0 } { $i < $L } { incr i } { TTY::sendChar $n [string range $c $i $i] } } proc unpost {n} { variable tty_w destroy $tty_w($n) unset tty_w($n) } proc data {n c} { variable tty_w set w $tty_w($n) catch { if { $c == 7 } { bell return } elseif { $c == 127 } { $w.txt configure -state normal $w.txt delete "end - 3 chars" $w.txt see end $w.txt configure -state disabled return } set x [format %c $c] $w.txt configure -state normal $w.txt insert "end - 2 chars" $x $w.txt see end $w.txt configure -state disabled } } } tkgate-2.0-b10/vlib/foo.v~000644 001751 001751 00000001433 11157673277 016133 0ustar00hansenhansen000000 000000 //: version "2.0-b8" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "Foo Library" //: property showSwitchNets = 0 //: property timingViolationMode = 2 //: property initTime = "0 ns" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module //: enddecls bar g0 (); //: @(254, 162) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin bar module bar(Z, A); //: interface /sz:(40, 40) /bd:[ Li0>A(16/40) Ro015 Li1>15 Li2>15 Li3>15 Li4>11 Li5>11 Li6>11 Li7>11 Ro0<0 Ro1<1 Ro2<1 Ro3<1 ] //: SWITCH g140 (w120) @(196,1771) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g37 (w34) @(513,393) /sn:0 /w:[ 0 ] /type:0 //: joint g13 (w38) @(250, 82) /w:[ 8 -1 10 7 ] //: joint g55 (w36) @(280, 727) /w:[ 18 17 -1 20 ] //: joint g58 (w39) @(234, 608) /w:[ 14 13 -1 16 ] //: LED g139 (w112) @(477,1584) /sn:0 /w:[ 1 ] /type:0 //: joint g112 (w2) @(195, 1180) /w:[ 22 21 -1 24 ] //: joint g111 (w1) @(209, 1164) /w:[ 22 21 -1 24 ] //: LED g76 (w55) @(893,572) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A3 (w38) @(36,134) /w:[ 11 ] /st:0 /dn:0 H7402 g1 (.B4(w3), .B3(w2), .B2(w1), .B1(w0), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y4(w23), .Y3(w22), .Y2(w21), .Y1(w20)); //: @(311, 220) /sz:(74, 144) /sn:0 /p:[ Li0>0 Li1>0 Li2>7 Li3>7 Li4>5 Li5>5 Li6>5 Li7>5 Ro0<1 Ro1<1 Ro2<0 Ro3<1 ] //: LED g64 (w53) @(436,887) /sn:0 /w:[ 1 ] /type:0 //: SWITCH A (w43) @(632,44) /w:[ 0 ] /st:1 /dn:0 //: joint g11 (w36) @(280, 50) /w:[ 8 -1 10 7 ] //: SWITCH g130 (w99) @(593,1466) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g121 (w100) @(947,1256) /sn:0 /w:[ 1 ] /type:0 //: SWITCH C3 (w13) @(38,918) /w:[ 0 ] /st:0 /dn:0 //: LED g50 (w26) @(440,699) /sn:0 /w:[ 0 ] /type:0 //: LED g28 (w11) @(488,29) /sn:0 /w:[ 0 ] /type:0 //: LED g132 (w119) @(316,1584) /sn:0 /w:[ 1 ] /type:0 //: joint g113 (w3) @(177, 1196) /w:[ 18 17 -1 20 ] //: SWITCH A6 (w40) @(36,524) /w:[ 0 ] /st:0 /dn:0 //: joint g19 (w36) @(280, 236) /w:[ 4 6 -1 3 ] //: SWITCH G (w49) @(631,322) /w:[ 0 ] /st:1 /dn:0 //: SWITCH A2 (w37) @(36,91) /w:[ 11 ] /st:0 /dn:0 //: SWITCH g115 (w59) @(128,1425) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g6 (w38) @(250, 445) /w:[ 1 2 -1 12 ] //: SWITCH B2 (w1) @(36,301) /w:[ 3 ] /st:0 /dn:0 //: LED g38 (w35) @(537,393) /sn:0 /w:[ 1 ] /type:0 //: LED g53 (w42) @(909,111) /sn:0 /w:[ 1 ] /type:0 //: joint g7 (w39) @(234, 461) /w:[ 1 2 -1 12 ] //: LED g75 (w56) @(871,572) /sn:0 /w:[ 1 ] /type:0 //: LED g135 (w116) @(385,1584) /sn:0 /w:[ 1 ] /type:0 //: LED g31 (w20) @(407,216) /sn:0 /w:[ 0 ] /type:0 //: joint g20 (w37) @(266, 252) /w:[ 4 6 -1 3 ] //: SWITCH g124 (w107) @(603,1271) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g39 (w18) @(434,534) /sn:0 /w:[ 0 ] /type:0 //: SWITCH B1 (w0) @(36,242) /w:[ 3 ] /st:0 /dn:0 //: SWITCH g68 (w58) @(618,543) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g48 (w2) @(195, 656) /w:[ 10 9 -1 12 ] //: LED g29 (w23) @(486,216) /sn:0 /w:[ 0 ] /type:0 //: LED g25 (w8) @(409,29) /sn:0 /w:[ 1 ] /type:0 //: joint g17 (w2) @(195, 146) /w:[ 4 -1 6 3 ] H7430 g52 (.A(w43), .B(w44), .C(w45), .D(w46), .E(w47), .F(w48), .G(w49), .H(w50), .Y(w42)); //: @(823, 119) /sz:(62, 144) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>0 Li4>0 Li5>1 Li6>1 Li7>1 Ro0<0 ] //: joint g106 (w36) @(280, 1084) /w:[ 26 25 -1 28 ] //: joint g107 (w37) @(266, 1100) /w:[ 26 25 -1 28 ] //: joint g83 (w39) @(234, 958) /w:[ 18 17 -1 20 ] //: LED g100 (w60) @(996,1004) /sn:0 /R:3 /w:[ 0 ] /type:1 //: joint g14 (w39) @(234, 98) /w:[ 8 -1 10 7 ] //: joint g47 (w1) @(209, 640) /w:[ 10 9 -1 12 ] //: joint g44 (w37) @(266, 576) /w:[ 14 13 -1 16 ] //: joint g80 (w36) @(280, 910) /w:[ 22 21 -1 24 ] //: SWITCH g94 (w85) @(620,905) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH D (w46) @(631,183) /w:[ 1 ] /st:1 /dn:0 //: SWITCH C (w45) @(630,135) /w:[ 1 ] /st:1 /dn:0 //: joint g21 (w38) @(250, 268) /w:[ 4 6 -1 3 ] //: joint g84 (w0) @(221, 974) /w:[ 18 17 -1 20 ] //: LED g105 (w95) @(478,1242) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g141 (w111) @(101,1570) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g41 (w16) @(485,534) /sn:0 /w:[ 0 ] /type:0 //: joint g23 (w3) @(177, 348) /w:[ 1 2 -1 8 ] H74163 g116 (.A(w105), .B(w106), .C(w107), .D(w108), ._CLR(w92), .ENP(w93), .ENT(w94), ._LOAD(w99), .CLK(w91), .QA(w104), .QB(w103), .QC(w102), .QD(w101), .RCO(w100)); //: @(694, 1264) /sz:(117, 160) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Li3>1 Li4>0 Li5>0 Li6>0 Li7>0 Bi0>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 Ro4<0 ] //: SWITCH g123 (w106) @(602,1241) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g40 (w17) @(458,534) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A1 (w36) @(36,50) /w:[ 11 ] /st:0 /dn:0 H7432 g54 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), .Y1(w54), .Y2(w53), .Y3(w52), .Y4(w51)); //: @(316, 894) /sz:(74, 144) /sn:0 /p:[ Li0>23 Li1>23 Li2>23 Li3>19 Li4>19 Li5>19 Li6>19 Li7>15 Ro0<0 Ro1<0 Ro2<1 Ro3<1 ] //: SWITCH g93 (w84) @(620,867) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g46 (w0) @(221, 624) /w:[ 10 9 -1 12 ] //: LED g26 (w9) @(436,29) /sn:0 /w:[ 0 ] /type:0 H7400 g0 (.B4(w3), .B3(w2), .B2(w1), .B1(w0), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y4(w11), .Y3(w10), .Y2(w9), .Y1(w8)); //: @(311, 34) /sz:(74, 144) /sn:0 /p:[ Li0>5 Li1>5 Li2>0 Li3>0 Li4>9 Li5>9 Li6>9 Li7>9 Ro0<1 Ro1<1 Ro2<1 Ro3<0 ] //: LED g90 (w67) @(455,1061) /sn:0 /w:[ 1 ] /type:0 //: SWITCH B4 (w3) @(36,404) /w:[ 7 ] /st:0 /dn:0 //: joint g82 (w38) @(250, 942) /w:[ 22 21 -1 24 ] //: LED g136 (w115) @(408,1584) /sn:0 /w:[ 1 ] /type:0 //: SWITCH g128 (w93) @(593,1399) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g33 (w31) @(437,392) /sn:0 /w:[ 0 ] /type:0 //: LED g91 (w66) @(477,1061) /sn:0 /w:[ 1 ] /type:0 //: LED g49 (w27) @(412,699) /sn:0 /w:[ 1 ] /type:0 //: LED g137 (w114) @(431,1584) /sn:0 /w:[ 1 ] /type:0 //: joint g61 (w2) @(195, 807) /w:[ 14 13 -1 16 ] //: SWITCH B (w44) @(631,91) /w:[ 1 ] /st:1 /dn:0 //: LED g51 (w25) @(464,699) /sn:0 /w:[ 1 ] /type:0 //: joint g3 (w36) @(280, 413) /w:[ 1 2 -1 12 ] //: LED g34 (w30) @(410,392) /sn:0 /w:[ 0 ] /type:0 //: joint g86 (w2) @(195, 1006) /w:[ 18 17 -1 20 ] //: SWITCH A5 (w41) @(36,477) /w:[ 0 ] /st:0 /dn:0 //: LED g89 (w68) @(432,1061) /sn:0 /w:[ 1 ] /type:0 //: joint g110 (w0) @(221, 1148) /w:[ 22 21 -1 24 ] H7404 g2 (.A6(w40), .A5(w41), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y6(w35), .Y5(w34), .Y4(w33), .Y3(w32), .Y2(w31), .Y1(w30)); //: @(310, 397) /sz:(74, 112) /sn:0 /p:[ Li0>1 Li1>1 Li2>0 Li3>0 Li4>0 Li5>0 Ro0<0 Ro1<1 Ro2<1 Ro3<1 Ro4<1 Ro5<1 ] //: LED g65 (w52) @(459,888) /sn:0 /w:[ 0 ] /type:0 //: LED g77 (w29) @(913,573) /sn:0 /w:[ 0 ] /type:0 //: SWITCH F (w48) @(631,275) /w:[ 0 ] /st:1 /dn:0 //: joint g59 (w0) @(221, 775) /w:[ 14 13 -1 16 ] //: SWITCH g72 (w6) @(618,690) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH g98 (w89) @(620,1049) /sn:0 /w:[ 0 ] /st:0 /dn:0 assign w60 = {w64, w65, w70, w71, w72, w73, w74, w75, w76, w77, w78, w79, w80, w81, w82, w83}; //: CONCAT g99 @(959,1004) /sn:0 /w:[ 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] /dr:1 /tp:0 /drp:1 //: joint g16 (w1) @(209, 130) /w:[ 1 -1 2 4 ] //: SWITCH g96 (w87) @(620,977) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH g122 (w105) @(602,1212) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g103 (w98) @(415,1242) /sn:0 /w:[ 0 ] /type:0 //: joint g10 (w2) @(195, 332) /w:[ 1 2 -1 8 ] //: joint g87 (w3) @(177, 1022) /w:[ 14 13 -1 16 ] //: SWITCH g78 (w4) @(704,768) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH g129 (w94) @(593,1431) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g32 (w21) @(434,216) /sn:0 /w:[ 1 ] /type:0 //: LED g27 (w10) @(461,29) /sn:0 /w:[ 0 ] /type:0 //: LED g102 (w97) @(433,1242) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g69 (w24) @(617,574) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g119 (w102) @(905,1256) /sn:0 /w:[ 0 ] /type:0 //: joint g9 (w1) @(209, 316) /w:[ 6 5 -1 8 ] //: joint g57 (w38) @(250, 759) /w:[ 18 17 -1 20 ] //: SWITCH g142 (w121) @(98,1604) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g15 (w0) @(221, 114) /w:[ 1 -1 2 4 ] //: SWITCH g71 (w14) @(617,658) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH C2 (w12) @(38,866) /w:[ 0 ] /st:0 /dn:0 H74175 g131 (.D1(w110), .D2(w109), .D3(w90), .D4(w63), ._PRE(w62), ._CLR(w28), .CLK(w120), .Q1(w119), .Q2(w118), .Q3(w117), .Q4(w116), ._Q1(w115), ._Q2(w114), ._Q3(w113), ._Q4(w112)); //: @(179, 1587) /sz:(105, 144) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Bi0>1 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 ] //: SWITCH g127 (w92) @(593,1366) /sn:0 /w:[ 1 ] /st:1 /dn:0 H7474 g67 (.D1(w58), ._PRE1(w24), ._CLR1(w15), .D2(w14), ._PRE2(w6), ._CLR2(w5), .CLK(w4), .Q1(w57), ._Q1(w56), .Q2(w55), ._Q2(w29)); //: @(719, 580) /sz:(110, 124) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Bi0>0 Ro0<0 Ro1<0 Ro2<1 Ro3<1 ] //: joint g43 (w36) @(280, 560) /w:[ 14 13 -1 16 ] //: joint g62 (w3) @(177, 672) /w:[ 10 9 -1 12 ] //: SWITCH g73 (w5) @(619,723) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g88 (w69) @(414,1061) /sn:0 /w:[ 1 ] /type:0 //: LED g104 (w96) @(456,1242) /sn:0 /w:[ 0 ] /type:0 //: LED g138 (w113) @(454,1584) /sn:0 /w:[ 1 ] /type:0 H7410 g42 (.A1(w36), .A2(w37), .A3(w38), .B1(w0), .B2(w1), .B3(w2), .C1(w7), .C2(w12), .C3(w13), .Y1(w27), .Y2(w26), .Y3(w25)); //: @(315, 711) /sz:(74, 160) /sn:0 /p:[ Li0>19 Li1>19 Li2>19 Li3>15 Li4>15 Li5>15 Li6>0 Li7>1 Li8>1 Ro0<0 Ro1<1 Ro2<0 ] //: LED g63 (w54) @(414,887) /sn:0 /w:[ 1 ] /type:0 //: joint g109 (w39) @(234, 1132) /w:[ 22 21 -1 24 ] //: LED g74 (w57) @(850,573) /sn:0 /w:[ 1 ] /type:0 //: LED g133 (w118) @(339,1584) /sn:0 /w:[ 1 ] /type:0 //: joint g5 (w37) @(266, 429) /w:[ 1 2 -1 12 ] //: joint g56 (w37) @(266, 743) /w:[ 18 17 -1 20 ] //: LED g117 (w104) @(864,1256) /sn:0 /w:[ 0 ] /type:0 //: SWITCH H (w50) @(631,368) /w:[ 0 ] /st:1 /dn:0 H7486 g79 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), .Y1(w69), .Y2(w68), .Y3(w67), .Y4(w66)); //: @(320, 1068) /sz:(74, 144) /sn:0 /p:[ Li0>27 Li1>27 Li2>27 Li3>23 Li4>23 Li5>23 Li6>23 Li7>19 Ro0<0 Ro1<0 Ro2<0 Ro3<0 ] //: SWITCH g95 (w86) @(620,941) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g24 (w19) @(410,534) /sn:0 /w:[ 1 ] /type:0 //: LED g36 (w32) @(462,392) /sn:0 /w:[ 0 ] /type:0 //: joint g85 (w1) @(209, 990) /w:[ 18 17 -1 20 ] H74154 g92 (.A(w84), .B(w85), .C(w86), .D(w87), ._G1(w88), ._G2(w89), ._Y1(w83), ._Y2(w82), ._Y3(w81), ._Y4(w80), ._Y5(w79), ._Y6(w78), ._Y7(w77), ._Y8(w76), ._Y9(w75), ._Y10(w74), ._Y11(w73), ._Y12(w72), ._Y13(w71), ._Y14(w70), ._Y15(w65), ._Y16(w64)); //: @(736, 868) /sz:(105, 272) /sn:0 /p:[ Li0>1 Li1>0 Li2>1 Li3>1 Li4>1 Li5>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 Ro4<1 Ro5<1 Ro6<1 Ro7<1 Ro8<1 Ro9<0 Ro10<1 Ro11<1 Ro12<1 Ro13<1 Ro14<1 Ro15<1 ] //: SWITCH g125 (w108) @(602,1300) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g60 (w1) @(209, 791) /w:[ 14 13 -1 16 ] //: joint g81 (w37) @(266, 926) /w:[ 22 21 -1 24 ] H74157 g101 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), ._G(w61), .S(w59), .Y1(w98), .Y2(w97), .Y3(w96), .Y4(w95)); //: @(317, 1249) /sz:(81, 176) /sn:0 /p:[ Li0>29 Li1>29 Li2>29 Li3>25 Li4>25 Li5>25 Li6>25 Li7>21 Li8>0 Li9>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] //: SWITCH g126 (w91) @(712,1495) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g45 (w38) @(250, 592) /w:[ 14 13 -1 16 ] //: LED g35 (w33) @(489,392) /sn:0 /w:[ 0 ] /type:0 //: joint g22 (w39) @(234, 284) /w:[ 4 6 -1 3 ] //: SWITCH g70 (w15) @(617,604) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g120 (w101) @(923,1256) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g97 (w88) @(620,1013) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g66 (w51) @(481,888) /sn:0 /w:[ 0 ] /type:0 //: SWITCH B3 (w2) @(36,353) /w:[ 7 ] /st:0 /dn:0 //: SWITCH g114 (w61) @(128,1393) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH E (w47) @(631,231) /w:[ 1 ] /st:1 /dn:0 //: SWITCH C1 (w7) @(39,823) /w:[ 1 ] /st:0 /dn:0 //: joint g12 (w37) @(266, 66) /w:[ 8 -1 10 7 ] //: joint g18 (w3) @(177, 162) /w:[ 4 -1 6 3 ] //: LED g30 (w22) @(459,216) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A4 (w39) @(36,187) /w:[ 11 ] /st:0 /dn:0 //: joint g108 (w38) @(250, 1116) /w:[ 26 25 -1 28 ] //: LED g134 (w117) @(362,1584) /sn:0 /w:[ 1 ] /type:0 //: LED g118 (w103) @(886,1256) /sn:0 /w:[ 0 ] /type:0 endmodule //: /netlistEnd //: /hdlBegin H7474 //: interface /sz:(110, 124) /bd:[ Li0>D1(16/124) Li1>_PRE1(32/124) Li2>_CLR1(48/124) Li3>D2(64/124) Li4>_PRE2(80/124) Li5>_CLR2(96/124) Bi0>CLK(54/110) Ro0A1(16/112) Li1>A2(32/112) Li2>A3(48/112) Li3>A4(64/112) Li4>A5(80/112) Li5>A6(96/112) Ro0B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A(16/272) Li1>B(32/272) Li2>C(48/272) Li3>D(64/272) Li4>_G1(80/272) Li5>_G2(96/272) Ro0<_Y1(16/272) Ro1<_Y2(32/272) Ro2<_Y3(48/272) Ro3<_Y4(64/272) Ro4<_Y5(80/272) Ro5<_Y6(96/272) Ro6<_Y7(112/272) Ro7<_Y8(128/272) Ro8<_Y9(144/272) Ro9<_Y10(160/272) Ro10<_Y11(176/272) Ro11<_Y12(192/272) Ro12<_Y13(208/272) Ro13<_Y14(224/272) Ro14<_Y15(240/272) Ro15<_Y16(256/272) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1 //: enddecls module H74154 #(.delay(20)) (A,B,C,D,_G1,_G2,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8, _Y9,_Y10,_Y11,_Y12,_Y13,_Y14,_Y15,_Y16); input A,B,C,D,_G1,_G2; output _Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,_Y9,_Y10,_Y11,_Y12,_Y13,_Y14,_Y15,_Y16; reg [15:0] R; assign #delay {_Y16,_Y15,_Y14,_Y13,_Y12,_Y11,_Y10,_Y9,_Y8,_Y7,_Y6,_Y5,_Y4,_Y3,_Y2,_Y1} = ~R; initial if (_G1 || _G2) R = 0; else R = 16'h1 << {D,C,B,A}; always @(_G1 or _G2 or A or B or C or D) if (_G1 || _G2) R = 0; else R = 16'h1 << {D,C,B,A}; endmodule //: /hdlEnd `timescale 1ns/1ns //: /hdlBegin H7408 //: interface /sz:(74, 144) /bd:[ Li0>B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A1(16/144) Li1>A2(32/144) Li2>A3(48/144) Li3>A4(64/144) Li4>B1(80/144) Li5>B2(96/144) Li6>B3(112/144) Li7>B4(128/144) Ro0A1(16/176) Li1>A2(32/176) Li2>A3(48/176) Li3>A4(64/176) Li4>B1(80/176) Li5>B2(96/176) Li6>B3(112/176) Li7>B4(128/176) Li8>_G(144/176) Li9>S(160/176) Ro0_LOAD(128/160) Li1>ENT(112/160) Li2>ENP(96/160) Li3>_CLR(80/160) Li4>D(64/160) Li5>C(48/160) Li6>B(32/160) Li7>A(16/160) Bi0>CLK(61/117) Ro0_CLR(96/144) Li1>_PRE(80/144) Li2>D4(64/144) Li3>D3(48/144) Li4>D2(32/144) Li5>D1(16/144) Bi0>CLK(52/105) Ro0<_Q4(128/144) Ro1<_Q3(112/144) Ro2<_Q2(96/144) Ro3<_Q1(80/144) Ro4C3(144/160) Li1>C2(128/160) Li2>C1(112/160) Li3>B3(96/160) Li4>B2(80/160) Li5>B1(64/160) Li6>A3(48/160) Li7>A2(32/160) Li8>A1(16/160) Ro0H(128/144) Li1>G(112/144) Li2>F(96/144) Li3>E(80/144) Li4>D(64/144) Li5>C(48/144) Li6>B(32/144) Li7>A(16/144) Ro0B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A1(16/144) Li1>A2(32/144) Li2>A3(48/144) Li3>A4(64/144) Li4>B1(80/144) Li5>B2(96/144) Li6>B3(112/144) Li7>B4(128/144) Ro00 Li1>0 Li2>0 Li3>0 Li4>0 Li5>0 Li6>0 Li7>0 Li8>0 Li9>0 Li10>0 Li11>0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 Ro14<0 ] endmodule //: /netlistEnd //: /hdlBegin cokemachine //: interface /sz:(181, 272) /bd:[ Li0>DISP[5:0](16/272) Li1>ELIGHT[5:0](32/272) Li2>CHGQ(48/272) Li3>CHGD(64/272) Li4>CHGN(80/272) Li5>NOCHG(96/272) Li6>BILLIN(112/272) Li7>BILLLT(128/272) Li8>BILLOUT(144/272) Li9>CHGCOM(160/272) Li10>RETINS(176/272) Li11>INSACK(192/272) Li12>COST[7:0](208/272) Bi0>_RESET(92/181) Ro015 Li1>15 Li2>15 Li3>15 Li4>11 Li5>11 Li6>11 Li7>11 Ro0<0 Ro1<1 Ro2<1 Ro3<1 ] //: LED g37 (w34) @(513,393) /sn:0 /w:[ 0 ] /type:0 //: joint g13 (w38) @(250, 82) /w:[ 8 -1 10 7 ] //: joint g55 (w36) @(280, 727) /w:[ 18 17 -1 20 ] //: joint g58 (w39) @(234, 608) /w:[ 14 13 -1 16 ] //: joint g112 (w2) @(195, 1180) /w:[ 22 21 -1 24 ] //: joint g111 (w1) @(209, 1164) /w:[ 22 21 -1 24 ] //: LED g76 (w55) @(893,572) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A3 (w38) @(36,134) /w:[ 11 ] /st:0 /dn:0 H7402 g1 (.B4(w3), .B3(w2), .B2(w1), .B1(w0), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y4(w23), .Y3(w22), .Y2(w21), .Y1(w20)); //: @(311, 220) /sz:(74, 144) /sn:0 /p:[ Li0>0 Li1>0 Li2>7 Li3>7 Li4>5 Li5>5 Li6>5 Li7>5 Ro0<1 Ro1<1 Ro2<0 Ro3<1 ] //: LED g64 (w53) @(436,887) /sn:0 /w:[ 1 ] /type:0 //: SWITCH A (w43) @(632,44) /w:[ 0 ] /st:1 /dn:0 //: joint g11 (w36) @(280, 50) /w:[ 8 -1 10 7 ] //: SWITCH g130 (w99) @(593,1466) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g121 (w100) @(947,1256) /sn:0 /w:[ 1 ] /type:0 //: SWITCH C3 (w13) @(38,918) /w:[ 0 ] /st:0 /dn:0 //: LED g50 (w26) @(440,699) /sn:0 /w:[ 0 ] /type:0 //: LED g28 (w11) @(488,29) /sn:0 /w:[ 0 ] /type:0 //: joint g113 (w3) @(177, 1196) /w:[ 18 17 -1 20 ] //: SWITCH A6 (w40) @(36,524) /w:[ 0 ] /st:0 /dn:0 //: joint g19 (w36) @(280, 236) /w:[ 4 6 -1 3 ] //: SWITCH G (w49) @(631,322) /w:[ 0 ] /st:1 /dn:0 //: SWITCH A2 (w37) @(36,91) /w:[ 11 ] /st:0 /dn:0 //: SWITCH g115 (w59) @(128,1425) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g6 (w38) @(250, 445) /w:[ 1 2 -1 12 ] //: SWITCH B2 (w1) @(36,301) /w:[ 3 ] /st:0 /dn:0 //: LED g38 (w35) @(537,393) /sn:0 /w:[ 1 ] /type:0 //: LED g53 (w42) @(909,111) /sn:0 /w:[ 1 ] /type:0 //: joint g7 (w39) @(234, 461) /w:[ 1 2 -1 12 ] //: LED g75 (w56) @(871,572) /sn:0 /w:[ 1 ] /type:0 //: LED g31 (w20) @(407,216) /sn:0 /w:[ 0 ] /type:0 //: joint g20 (w37) @(266, 252) /w:[ 4 6 -1 3 ] //: SWITCH g124 (w107) @(603,1271) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g39 (w18) @(434,534) /sn:0 /w:[ 0 ] /type:0 //: SWITCH B1 (w0) @(36,242) /w:[ 3 ] /st:0 /dn:0 //: SWITCH g68 (w58) @(618,543) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g48 (w2) @(195, 656) /w:[ 10 9 -1 12 ] //: LED g29 (w23) @(486,216) /sn:0 /w:[ 0 ] /type:0 //: LED g25 (w8) @(409,29) /sn:0 /w:[ 1 ] /type:0 //: joint g17 (w2) @(195, 146) /w:[ 4 -1 6 3 ] H7430 g52 (.A(w43), .B(w44), .C(w45), .D(w46), .E(w47), .F(w48), .G(w49), .H(w50), .Y(w42)); //: @(823, 119) /sz:(62, 144) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>0 Li4>0 Li5>1 Li6>1 Li7>1 Ro0<0 ] //: joint g106 (w36) @(280, 1084) /w:[ 26 25 -1 28 ] //: joint g107 (w37) @(266, 1100) /w:[ 26 25 -1 28 ] //: joint g83 (w39) @(234, 958) /w:[ 18 17 -1 20 ] //: LED g100 (w60) @(996,1004) /sn:0 /R:3 /w:[ 0 ] /type:1 //: joint g14 (w39) @(234, 98) /w:[ 8 -1 10 7 ] //: joint g47 (w1) @(209, 640) /w:[ 10 9 -1 12 ] //: joint g44 (w37) @(266, 576) /w:[ 14 13 -1 16 ] //: joint g80 (w36) @(280, 910) /w:[ 22 21 -1 24 ] //: SWITCH g94 (w85) @(620,905) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH D (w46) @(631,183) /w:[ 1 ] /st:1 /dn:0 //: SWITCH C (w45) @(630,135) /w:[ 1 ] /st:1 /dn:0 //: joint g21 (w38) @(250, 268) /w:[ 4 6 -1 3 ] //: joint g84 (w0) @(221, 974) /w:[ 18 17 -1 20 ] //: LED g105 (w95) @(478,1242) /sn:0 /w:[ 0 ] /type:0 //: LED g41 (w16) @(485,534) /sn:0 /w:[ 0 ] /type:0 //: joint g23 (w3) @(177, 348) /w:[ 1 2 -1 8 ] H74163 g116 (.A(w105), .B(w106), .C(w107), .D(w108), ._CLR(w92), .ENP(w93), .ENT(w94), ._LOAD(w99), .CLK(w91), .QA(w104), .QB(w103), .QC(w102), .QD(w101), .RCO(w100)); //: @(694, 1264) /sz:(117, 160) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Li3>1 Li4>0 Li5>0 Li6>0 Li7>0 Bi0>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 Ro4<0 ] //: SWITCH g123 (w106) @(602,1241) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g40 (w17) @(458,534) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A1 (w36) @(36,50) /w:[ 11 ] /st:0 /dn:0 H7432 g54 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), .Y1(w54), .Y2(w53), .Y3(w52), .Y4(w51)); //: @(316, 894) /sz:(74, 144) /sn:0 /p:[ Li0>23 Li1>23 Li2>23 Li3>19 Li4>19 Li5>19 Li6>19 Li7>15 Ro0<0 Ro1<0 Ro2<1 Ro3<1 ] //: SWITCH g93 (w84) @(620,867) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g46 (w0) @(221, 624) /w:[ 10 9 -1 12 ] //: LED g26 (w9) @(436,29) /sn:0 /w:[ 0 ] /type:0 H7400 g0 (.B4(w3), .B3(w2), .B2(w1), .B1(w0), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y4(w11), .Y3(w10), .Y2(w9), .Y1(w8)); //: @(311, 34) /sz:(74, 144) /sn:0 /p:[ Li0>5 Li1>5 Li2>0 Li3>0 Li4>9 Li5>9 Li6>9 Li7>9 Ro0<1 Ro1<1 Ro2<1 Ro3<0 ] //: LED g90 (w67) @(455,1061) /sn:0 /w:[ 1 ] /type:0 //: SWITCH B4 (w3) @(36,404) /w:[ 7 ] /st:0 /dn:0 //: joint g82 (w38) @(250, 942) /w:[ 22 21 -1 24 ] //: SWITCH g128 (w93) @(593,1399) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g33 (w31) @(437,392) /sn:0 /w:[ 0 ] /type:0 //: LED g91 (w66) @(477,1061) /sn:0 /w:[ 1 ] /type:0 //: LED g49 (w27) @(412,699) /sn:0 /w:[ 1 ] /type:0 //: joint g61 (w2) @(195, 807) /w:[ 14 13 -1 16 ] //: SWITCH B (w44) @(631,91) /w:[ 1 ] /st:1 /dn:0 //: LED g51 (w25) @(464,699) /sn:0 /w:[ 1 ] /type:0 //: joint g3 (w36) @(280, 413) /w:[ 1 2 -1 12 ] //: LED g34 (w30) @(410,392) /sn:0 /w:[ 0 ] /type:0 //: joint g86 (w2) @(195, 1006) /w:[ 18 17 -1 20 ] //: SWITCH A5 (w41) @(36,477) /w:[ 0 ] /st:0 /dn:0 //: LED g89 (w68) @(432,1061) /sn:0 /w:[ 1 ] /type:0 //: joint g110 (w0) @(221, 1148) /w:[ 22 21 -1 24 ] H7404 g2 (.A6(w40), .A5(w41), .A4(w39), .A3(w38), .A2(w37), .A1(w36), .Y6(w35), .Y5(w34), .Y4(w33), .Y3(w32), .Y2(w31), .Y1(w30)); //: @(310, 397) /sz:(74, 112) /sn:0 /p:[ Li0>1 Li1>1 Li2>0 Li3>0 Li4>0 Li5>0 Ro0<0 Ro1<1 Ro2<1 Ro3<1 Ro4<1 Ro5<1 ] //: LED g65 (w52) @(459,888) /sn:0 /w:[ 0 ] /type:0 //: LED g77 (w29) @(913,573) /sn:0 /w:[ 0 ] /type:0 //: SWITCH F (w48) @(631,275) /w:[ 0 ] /st:1 /dn:0 //: joint g59 (w0) @(221, 775) /w:[ 14 13 -1 16 ] //: SWITCH g72 (w6) @(618,690) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH g98 (w89) @(620,1049) /sn:0 /w:[ 0 ] /st:0 /dn:0 assign w60 = {w64, w65, w70, w71, w72, w73, w74, w75, w76, w77, w78, w79, w80, w81, w82, w83}; //: CONCAT g99 @(959,1004) /sn:0 /w:[ 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] /dr:1 /tp:0 /drp:1 //: joint g16 (w1) @(209, 130) /w:[ 1 -1 2 4 ] //: SWITCH g96 (w87) @(620,977) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH g122 (w105) @(602,1212) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g103 (w98) @(415,1242) /sn:0 /w:[ 0 ] /type:0 //: joint g10 (w2) @(195, 332) /w:[ 1 2 -1 8 ] //: joint g87 (w3) @(177, 1022) /w:[ 14 13 -1 16 ] //: SWITCH g78 (w4) @(704,768) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH g129 (w94) @(593,1431) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: LED g32 (w21) @(434,216) /sn:0 /w:[ 1 ] /type:0 //: LED g27 (w10) @(461,29) /sn:0 /w:[ 0 ] /type:0 //: LED g102 (w97) @(433,1242) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g69 (w24) @(617,574) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g119 (w102) @(905,1256) /sn:0 /w:[ 0 ] /type:0 //: joint g9 (w1) @(209, 316) /w:[ 6 5 -1 8 ] //: joint g57 (w38) @(250, 759) /w:[ 18 17 -1 20 ] //: joint g15 (w0) @(221, 114) /w:[ 1 -1 2 4 ] //: SWITCH g71 (w14) @(617,658) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: SWITCH C2 (w12) @(38,866) /w:[ 0 ] /st:0 /dn:0 H74175 g131 (.D1(w110), .D2(w109), .D3(w90), .D4(w63), ._PRE(w62), ._CLR(w28), .CLK(w111), .Q1(w119), .Q2(w118), .Q3(w117), .Q4(w116), ._Q1(w115), ._Q2(w114), ._Q3(w113), ._Q4(w112)); //: @(179, 1587) /sz:(105, 144) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Bi0>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 Ro4<1 Ro5<1 Ro6<1 Ro7<1 ] //: SWITCH g127 (w92) @(593,1366) /sn:0 /w:[ 1 ] /st:1 /dn:0 H7474 g67 (.D1(w58), ._PRE1(w24), ._CLR1(w15), .D2(w14), ._PRE2(w6), ._CLR2(w5), .CLK(w4), .Q1(w57), ._Q1(w56), .Q2(w55), ._Q2(w29)); //: @(719, 580) /sz:(110, 124) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Bi0>0 Ro0<0 Ro1<0 Ro2<1 Ro3<1 ] //: joint g43 (w36) @(280, 560) /w:[ 14 13 -1 16 ] //: joint g62 (w3) @(177, 672) /w:[ 10 9 -1 12 ] //: SWITCH g73 (w5) @(619,723) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g88 (w69) @(414,1061) /sn:0 /w:[ 1 ] /type:0 //: LED g104 (w96) @(456,1242) /sn:0 /w:[ 0 ] /type:0 H7410 g42 (.A1(w36), .A2(w37), .A3(w38), .B1(w0), .B2(w1), .B3(w2), .C1(w7), .C2(w12), .C3(w13), .Y1(w27), .Y2(w26), .Y3(w25)); //: @(315, 711) /sz:(74, 160) /sn:0 /p:[ Li0>19 Li1>19 Li2>19 Li3>15 Li4>15 Li5>15 Li6>0 Li7>1 Li8>1 Ro0<0 Ro1<1 Ro2<0 ] //: LED g63 (w54) @(414,887) /sn:0 /w:[ 1 ] /type:0 //: joint g109 (w39) @(234, 1132) /w:[ 22 21 -1 24 ] //: LED g74 (w57) @(850,573) /sn:0 /w:[ 1 ] /type:0 //: joint g5 (w37) @(266, 429) /w:[ 1 2 -1 12 ] //: joint g56 (w37) @(266, 743) /w:[ 18 17 -1 20 ] //: LED g117 (w104) @(864,1256) /sn:0 /w:[ 0 ] /type:0 //: SWITCH H (w50) @(631,368) /w:[ 0 ] /st:1 /dn:0 H7486 g79 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), .Y1(w69), .Y2(w68), .Y3(w67), .Y4(w66)); //: @(320, 1068) /sz:(74, 144) /sn:0 /p:[ Li0>27 Li1>27 Li2>27 Li3>23 Li4>23 Li5>23 Li6>23 Li7>19 Ro0<0 Ro1<0 Ro2<0 Ro3<0 ] //: SWITCH g95 (w86) @(620,941) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g24 (w19) @(410,534) /sn:0 /w:[ 1 ] /type:0 //: LED g36 (w32) @(462,392) /sn:0 /w:[ 0 ] /type:0 //: joint g85 (w1) @(209, 990) /w:[ 18 17 -1 20 ] H74154 g92 (.A(w84), .B(w85), .C(w86), .D(w87), ._G1(w88), ._G2(w89), ._Y1(w83), ._Y2(w82), ._Y3(w81), ._Y4(w80), ._Y5(w79), ._Y6(w78), ._Y7(w77), ._Y8(w76), ._Y9(w75), ._Y10(w74), ._Y11(w73), ._Y12(w72), ._Y13(w71), ._Y14(w70), ._Y15(w65), ._Y16(w64)); //: @(736, 868) /sz:(105, 272) /sn:0 /p:[ Li0>1 Li1>0 Li2>1 Li3>1 Li4>1 Li5>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 Ro4<1 Ro5<1 Ro6<1 Ro7<1 Ro8<1 Ro9<0 Ro10<1 Ro11<1 Ro12<1 Ro13<1 Ro14<1 Ro15<1 ] //: SWITCH g125 (w108) @(602,1300) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g60 (w1) @(209, 791) /w:[ 14 13 -1 16 ] //: joint g81 (w37) @(266, 926) /w:[ 22 21 -1 24 ] H74157 g101 (.A1(w36), .A2(w37), .A3(w38), .A4(w39), .B1(w0), .B2(w1), .B3(w2), .B4(w3), ._G(w61), .S(w59), .Y1(w98), .Y2(w97), .Y3(w96), .Y4(w95)); //: @(317, 1249) /sz:(81, 176) /sn:0 /p:[ Li0>29 Li1>29 Li2>29 Li3>25 Li4>25 Li5>25 Li6>25 Li7>21 Li8>0 Li9>1 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] //: SWITCH g126 (w91) @(712,1495) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: joint g45 (w38) @(250, 592) /w:[ 14 13 -1 16 ] //: LED g35 (w33) @(489,392) /sn:0 /w:[ 0 ] /type:0 //: joint g22 (w39) @(234, 284) /w:[ 4 6 -1 3 ] //: SWITCH g70 (w15) @(617,604) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g120 (w101) @(923,1256) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g97 (w88) @(620,1013) /sn:0 /w:[ 0 ] /st:0 /dn:0 //: LED g66 (w51) @(481,888) /sn:0 /w:[ 0 ] /type:0 //: SWITCH B3 (w2) @(36,353) /w:[ 7 ] /st:0 /dn:0 //: SWITCH g114 (w61) @(128,1393) /sn:0 /w:[ 1 ] /st:0 /dn:0 //: SWITCH E (w47) @(631,231) /w:[ 1 ] /st:1 /dn:0 //: SWITCH C1 (w7) @(39,823) /w:[ 1 ] /st:0 /dn:0 //: joint g12 (w37) @(266, 66) /w:[ 8 -1 10 7 ] //: joint g18 (w3) @(177, 162) /w:[ 4 -1 6 3 ] //: LED g30 (w22) @(459,216) /sn:0 /w:[ 0 ] /type:0 //: SWITCH A4 (w39) @(36,187) /w:[ 11 ] /st:0 /dn:0 //: joint g108 (w38) @(250, 1116) /w:[ 26 25 -1 28 ] //: LED g118 (w103) @(886,1256) /sn:0 /w:[ 0 ] /type:0 endmodule //: /netlistEnd //: /hdlBegin H7474 //: interface /sz:(110, 124) /bd:[ Li0>D1(16/124) Li1>_PRE1(32/124) Li2>_CLR1(48/124) Li3>D2(64/124) Li4>_PRE2(80/124) Li5>_CLR2(96/124) Bi0>CLK(54/110) Ro0A1(16/112) Li1>A2(32/112) Li2>A3(48/112) Li3>A4(64/112) Li4>A5(80/112) Li5>A6(96/112) Ro0B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A(16/272) Li1>B(32/272) Li2>C(48/272) Li3>D(64/272) Li4>_G1(80/272) Li5>_G2(96/272) Ro0<_Y1(16/272) Ro1<_Y2(32/272) Ro2<_Y3(48/272) Ro3<_Y4(64/272) Ro4<_Y5(80/272) Ro5<_Y6(96/272) Ro6<_Y7(112/272) Ro7<_Y8(128/272) Ro8<_Y9(144/272) Ro9<_Y10(160/272) Ro10<_Y11(176/272) Ro11<_Y12(192/272) Ro12<_Y13(208/272) Ro13<_Y14(224/272) Ro14<_Y15(240/272) Ro15<_Y16(256/272) ] /pd: 0 /pi: 0 /pe: 1 /pp: 1 //: enddecls module H74154 #(.delay(20)) (A,B,C,D,_G1,_G2,_Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8, _Y9,_Y10,_Y11,_Y12,_Y13,_Y14,_Y15,_Y16); input A,B,C,D,_G1,_G2; output _Y1,_Y2,_Y3,_Y4,_Y5,_Y6,_Y7,_Y8,_Y9,_Y10,_Y11,_Y12,_Y13,_Y14,_Y15,_Y16; reg [15:0] R; assign #delay {_Y16,_Y15,_Y14,_Y13,_Y12,_Y11,_Y10,_Y9,_Y8,_Y7,_Y6,_Y5,_Y4,_Y3,_Y2,_Y1} = ~R; initial if (_G1 || _G2) R = 0; else R = 16'h1 << {D,C,B,A}; always @(_G1 or _G2 or A or B or C or D) if (_G1 || _G2) R = 0; else R = 16'h1 << {D,C,B,A}; endmodule //: /hdlEnd `timescale 1ns/1ns //: /hdlBegin H7408 //: interface /sz:(74, 144) /bd:[ Li0>B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A1(16/144) Li1>A2(32/144) Li2>A3(48/144) Li3>A4(64/144) Li4>B1(80/144) Li5>B2(96/144) Li6>B3(112/144) Li7>B4(128/144) Ro0A1(16/176) Li1>A2(32/176) Li2>A3(48/176) Li3>A4(64/176) Li4>B1(80/176) Li5>B2(96/176) Li6>B3(112/176) Li7>B4(128/176) Li8>_G(144/176) Li9>S(160/176) Ro0_LOAD(128/160) Li1>ENT(112/160) Li2>ENP(96/160) Li3>_CLR(80/160) Li4>D(64/160) Li5>C(48/160) Li6>B(32/160) Li7>A(16/160) Bi0>CLK(61/117) Ro0_CLR(96/144) Li1>_PRE(80/144) Li2>D4(64/144) Li3>D3(48/144) Li4>D2(32/144) Li5>D1(16/144) Bi0>CLK(52/105) Ro0<_Q4(128/144) Ro1<_Q3(112/144) Ro2<_Q2(96/144) Ro3<_Q1(80/144) Ro4C3(144/160) Li1>C2(128/160) Li2>C1(112/160) Li3>B3(96/160) Li4>B2(80/160) Li5>B1(64/160) Li6>A3(48/160) Li7>A2(32/160) Li8>A1(16/160) Ro0H(128/144) Li1>G(112/144) Li2>F(96/144) Li3>E(80/144) Li4>D(64/144) Li5>C(48/144) Li6>B(32/144) Li7>A(16/144) Ro0B4(128/144) Li1>B3(112/144) Li2>B2(96/144) Li3>B1(80/144) Li4>A4(64/144) Li5>A3(48/144) Li6>A2(32/144) Li7>A1(16/144) Ro0A1(16/144) Li1>A2(32/144) Li2>A3(48/144) Li3>A4(64/144) Li4>B1(80/144) Li5>B2(96/144) Li6>B3(112/144) Li7>B4(128/144) Ro00 Li1>0 Li2>0 Li3>0 Li4>0 Li5>0 Li6>0 Li7>0 Li8>0 Li9>0 Li10>0 Li11>0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 Ro14<0 ] endmodule //: /netlistEnd //: /hdlBegin cokemachine //: interface /sz:(181, 272) /bd:[ Li0>COST[7:0](208/272) Li1>INSACK(192/272) Li2>RETINS(176/272) Li3>CHGCOM(160/272) Li4>BILLOUT(144/272) Li5>BILLLT(128/272) Li6>BILLIN(112/272) Li7>NOCHG(96/272) Li8>CHGN(80/272) Li9>CHGD(64/272) Li10>CHGQ(48/272) Li11>ELIGHT[5:0](32/272) Li12>DISP[5:0](16/272) Bi0>_RESET(92/181) Ro0 Z%) = Dez; } $${NUMOUT:\n: (F *> Z%) = Dfz; } $${NUMOUT:\n: (S *> Z%) = Dsz; } endspecify assign X = E ? F : ${F_BITS}'h0; $${NUMOUT:\n: assign Z% = (S == ${S_BITS}'d%) ? X : ${F_BITS}'h0;} endmodule // demux tkgate-2.0-b10/primitives/and.v000644 001751 001751 00000000303 11120635350 017122 0ustar00hansenhansen000000 000000 module and #(.Diz(1)) ($${NUMIN:I%, } Z); output ${Z_RANGE} Z; input ${I_RANGE} $${NUMIN:, :I%}; reg ${Z_RANGE} Z; assign #Diz Z = ${invZ}( $${NUMIN: & :I%} ); endmodule // and tkgate-2.0-b10/primitives/README000644 001751 001751 00000007563 11124273702 017073 0ustar00hansenhansen000000 000000 This directory contains verilog templates for all of the built-in gates. User editing of these templates is not currently supported because, but can be done subject to the following caveats: * the syntax is still subject to change across releases. * changing the order of module parameters in a template is not guaranteed to work. SUBSTITUTION: Variable substitutions are indicated with a sequence of the form "${NAME}". If "NAME" is a template parameter for a gate type, the value of that variable will be substituted. GENERATION: Generating sequences have the form "$${NAME:str}" or "$${NAME:sep:str}". The variable "NAME" is assumed to be a numeric value for the number of times to generate the string "str". If there is a "%" character in the string, it will be replaced with the decimal value of the count starting at "0". The second form is similar to the first except that the string "sep" will be placed between each instance of "sep" that is generated. The "sep" and "str" strings themselves may also contain variable substitution sequences. PARAMETER NAMING CONVENTIONS: By convention, parameter names that end in "_RANGE" are bit or memory range strings having the form "[msb:0]" or "[0:max]". Parameters that end in "_BITS" expand to numbers representing the number of bits in the corresponding "_RANGE" parameter. The parameters names "NUMIN" and "NUMOUT" are used for gates with a variable number of inputs or outputs, respectively. Finally, names of the form "invX" contain either a "~" or an empty string depending on whether the output "X" requires an inverter. LIST OF TEMPLATE PARAMETERS: and, or, xor: NUMIN Number of inputs Z_RANGE Bit range of output I_RANGE Bit range of input invZ Optional inverter on Z output rand, ror, rxor: Z_RANGE Bit range of output I_RANGE Bit range of input invZ Optional inverter on Z output flipflop: DQ_RANGE Bit range of D/Q input/output. DQ_BITS Number of bits on D/Q input/output. invQ Optional inverter on Q output. invNQ Optional inverter on _Q output. register: DQ_RANGE Bit range of D/Q input/output. DQ_BITS Number of bits on D/Q input/output. invQ Optional inverter on Q output. adder: ABS_RANGE Bit range of A, B and S inputs/output invCO Optional inverter on CO output. invS Optional inverter on S output. mult: AB_RANGE Bit range of A and B inputs P_RANGE Bit range of P output invP Optional inverter on P output. div: ABQR_RANGE Bit range of A, B, Q and R inputs/output invQ Optional inverter on Q output. invR Optional inverter on R output. lshift, rshift, arshift: IZ_RANGE Bit range of I/Z input/output S_RANGE Bit range of S input invZ Optional inverter on Z output. roll: IZ_RANGE Bit range of I/Z input/output IZ_BITS Number of bits of I/Z input/output S_RANGE Bit range of S input invZ Optional inverter on Z output. clock: PHASE Time to wait before entering loop INITIAL Initial value of clock ON_TIME Time clock is "on" OFF_TIME Time clock is "off" invZ Optional inverter on Z output. mux: NUMIN Number of data inputs IZ_RANGE Bit range of inputs/output S_RANGE Bit range of S input demux: NUMOUT Number of outputs OUT_RANGE Bit range of internal output net. I_RANGE Bit range of input I. invZ Bit-by-bit inversion for outputs ram: A_RANGE Bit range of address line D_RANGE Bit range of data line D_BITS Number of bits in data line MEM_RANGE Memory address range. rom: A_RANGE Bit range of address line D_RANGE Bit range of data line D_BITS Number of bits in data line. MEM_RANGE Memory address range. invD Optional inverter on D output. nmos_trans, pmos_trans: SGZ_RANGE Bit range of source, gate and drain. invZ Optional inverter on Z output. buf: IZ_RANGE Bit range of input/output invZ Optional inverter on Z output. tribuf: IZ_RANGE Bit range of inputs/output IZ_BITS Number of bits in inputs/output invZ Optional inverter on Z output. tkgate-2.0-b10/primitives/or.v000644 001751 001751 00000000256 11110103642 017000 0ustar00hansenhansen000000 000000 module or #(.Diz(1)) ($${NUMIN:I%, } Z); output ${Z_RANGE} Z; input ${I_RANGE} $${NUMIN:, :I%}; assign #Diz Z = ${invZ}( $${NUMIN: | :I%} ); endmodule // or tkgate-2.0-b10/primitives/jkff.v~000644 001751 001751 00000001463 11135246110 017504 0ustar00hansenhansen000000 000000 module jkff #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, _Q, J, K, PRE, CLR, CK); input CK,PRE,CLR; input ${JK_RANGE} J, K; output ${JK_RANGE} Q,_Q; reg ${JK_RANGE} Qreg; specify $setup(J,posedge CK, Dsetup); $setup(K,posedge CK, Dsetup); $hold(posedge CK,J, Dhold); $hold(posedge CK,K, Dhold); endspecify assign #Dck_q Q = ${invQ}Qreg; assign #Dck_q _Q = ${invNQ}Qreg; initial if (!PRE) Qreg = ${JK_BITS}'b0; else if (!CLR) Qreg = ~${JK_BITS}'b0; // // Handle preset and clear signals // always @ (PRE or CLR) if (!PRE) Qreg = ${JK_BITS}'b0; else if (!CLR) Qreg = ~${JK_BITS}'b0; always @(posedge CK) if (CLR === 1'b1 && PRE === 1'b1) Qreg = (J&~Qreg) | (J&~K) | (Qreg&~K); endmodule tkgate-2.0-b10/primitives/xor.v000644 001751 001751 00000000261 11110103653 017166 0ustar00hansenhansen000000 000000 module xor #(.Diz(1)) ($${NUMIN:I%, } Z); output ${Z_RANGE} Z; input ${I_RANGE} $${NUMIN:, :I%}; assign #Diz Z = ${invZ}( $${NUMIN: ^ :I%} ); endmodule // xor tkgate-2.0-b10/primitives/rom.v000644 001751 001751 00000000404 11140707243 017162 0ustar00hansenhansen000000 000000 module rom #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input ${A_RANGE} A; output ${D_RANGE} D; reg ${D_RANGE} m${MEM_RANGE}; wire ${D_RANGE} X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? ${invD}X : ${D_BITS}'bz; endmodule tkgate-2.0-b10/primitives/mux.v000644 001751 001751 00000000566 11123442423 017204 0ustar00hansenhansen000000 000000 module mux #(.Dsz(1), .Diz(1)) ($${NUMIN:I%, }S, Z); input ${IZ_RANGE} $${NUMIN:, :I%}; input ${S_RANGE} S; output ${IZ_RANGE} Z; reg ${IZ_RANGE} Z; always begin case (S) $${NUMIN:\n: ${S_BITS}'d%: Z <= #Dsz ${invZ} I%;} default: Z <= #Dsz ${invZ} ${IZ_BITS}'hx; endcase // case(S) @(S or $${NUMIN: or :I%}); end endmodule // mux tkgate-2.0-b10/primitives/lshift.v000644 001751 001751 00000000365 11110072675 017665 0ustar00hansenhansen000000 000000 module lshift #(.Dsz(1), .Diz(1)) (I, Z , S); input ${IZ_RANGE} I; input ${S_RANGE} S; output ${IZ_RANGE} Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ${invZ} (I << S); endmodule // lshift tkgate-2.0-b10/primitives/rshift.v000644 001751 001751 00000000365 11110073573 017671 0ustar00hansenhansen000000 000000 module rshift #(.Dsz(1), .Diz(1)) (I, Z , S); input ${IZ_RANGE} I; input ${S_RANGE} S; output ${IZ_RANGE} Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ${invZ} (I >> S); endmodule // rshift tkgate-2.0-b10/primitives/div.v000644 001751 001751 00000000320 11110163336 017140 0ustar00hansenhansen000000 000000 module div #(.Dab_q(1), .Dab_r(1)) (A, B, Q, R); input ${ABQR_RANGE} A,B; output ${ABQR_RANGE} Q,R; assign #Dab_q Q = ${invQ} (A / B); assign #Dab_r R = ${invR} (A % B); endmodule // div tkgate-2.0-b10/primitives/arshift.v000644 001751 001751 00000000370 11110073612 020020 0ustar00hansenhansen000000 000000 module arshift #(.Dsz(1), .Diz(1)) (I, Z , S); input ${IZ_RANGE} I; input ${S_RANGE} S; output ${IZ_RANGE} Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ${invZ} (I >>> S); endmodule // arshift tkgate-2.0-b10/primitives/register.v000644 001751 001751 00000000745 11140751536 020225 0ustar00hansenhansen000000 000000 module register #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input ${DQ_RANGE} D; output ${DQ_RANGE} Q; reg ${DQ_RANGE} Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = ${invQ}Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = ${DQ_BITS}'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule tkgate-2.0-b10/primitives/ram.v~000644 001751 001751 00000002206 11140470207 017341 0ustar00hansenhansen000000 000000 module ram #(.Dread(1), // Read time .Dwrite(1), // Write time .Daddr_setup(1), // Address setup time .Daddr_hold(1), // Address hold time .Ddata_hold(1)) // Data hold time (A, D, WE, OE, CS); input OE, WE, CS; input ${A_RANGE} A; inout ${D_RANGE} D; reg ${D_RANGE} m${MEM_RANGE}; wire ${D_RANGE} X; wire doRead, doWrite; specify $setup(A, posedge doWrite, Daddr_setup); $hold(negedge doWrite, A, Daddr_hold); $hold(negedge doWrite, D, Ddata_hold); $width(posedge doWrite, Dwrite); endspecify assign doRead = (!CS && !OE); assign doWrite = (!CS && !WE); // // Value read from addressed memory // assign #Dread X = m[A]; // // If chip-select and output-enable are asserted, output value from memory // assign D = doRead ? X : ${D_BITS}'bz; // // Look for conditions on which to write to memory // always @(doWrite or D or A) if (doWrite) m[A] <= #Dwrite D; always @(D) if (doWrite) $error("`RAMDCHG %m[%M]"); always @(A) if (doWrite) $error("`RAMACHG %m[%M]"); endmodule // ram tkgate-2.0-b10/primitives/ram.v000644 001751 001751 00000002254 11140707102 017143 0ustar00hansenhansen000000 000000 module ram #(.Dout(1), // Output time .Dread(1), // Read time .Dwrite(1), // Write time .Daddr_setup(1), // Address setup time .Daddr_hold(1), // Address hold time .Ddata_hold(1)) // Data hold time (A, D, WE, OE, CS); input OE, WE, CS; input ${A_RANGE} A; inout ${D_RANGE} D; reg ${D_RANGE} m${MEM_RANGE}; wire ${D_RANGE} X; wire doRead, doWrite; specify $setup(A, posedge doWrite, Daddr_setup); $hold(negedge doWrite, A, Daddr_hold); $hold(negedge doWrite, D, Ddata_hold); $width(posedge doWrite, Dwrite); endspecify assign doRead = (!CS && !OE); assign doWrite = (!CS && !WE); // // Value read from addressed memory // assign #Dread X = m[A]; // // If chip-select and output-enable are asserted, output value from memory // assign #Dout D = doRead ? X : ${D_BITS}'bz; // // Look for conditions on which to write to memory // always @(doWrite or D or A) if (doWrite) m[A] <= #Dwrite D; always @(D) if (doWrite) $error("`RAMDCHG %m[%M]"); always @(A) if (doWrite) $error("`RAMACHG %m[%M]"); endmodule // ram tkgate-2.0-b10/primitives/mult.v000644 001751 001751 00000000214 11126772523 017354 0ustar00hansenhansen000000 000000 module mult #(.Dab_p(1)) (A, B, P); input ${P_RANGE} A,B; output ${P_RANGE} P; assign #Dab_p P = ${invP} (A * B); endmodule tkgate-2.0-b10/primitives/adder.v000644 001751 001751 00000000671 11132244031 017442 0ustar00hansenhansen000000 000000 module adder #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input ${ABS_RANGE} A,B; output ${ABS_RANGE} S; wire ${ABS_RANGE} _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = ${invCO} _CO; assign S = ${invS} _S; endmodule tkgate-2.0-b10/primitives/rand.v000644 001751 001751 00000000211 11110103671 017275 0ustar00hansenhansen000000 000000 module rand #(.Diz(1)) (I0, Z); output ${Z_RANGE} Z; input ${I_RANGE} I0; assign #Diz Z = ${invZ} & I0; endmodule // rand tkgate-2.0-b10/primitives/ror.v000644 001751 001751 00000000207 11110103701 017152 0ustar00hansenhansen000000 000000 module ror #(.Diz(1)) (I0, Z); output ${Z_RANGE} Z; input ${I_RANGE} I0; assign #Diz Z = ${invZ} | I0; endmodule // ror tkgate-2.0-b10/primitives/newdemux.v000644 001751 001751 00000000640 11134723221 020220 0ustar00hansenhansen000000 000000 module newdemux #(.Dez(1), .Diz(1)) (I, S, $${NUMOUT:, :Z%}); input ${I_RANGE} I; input ${S_RANGE} S; output ${I_RANGE} $${NUMOUT:, :Z%}; wire ${OUT_RANGE} Zcat; specify $${NUMOUT:\n: (S *> Z%) = Dsz; } $${NUMOUT:\n: (I *> Z%) = Diz; } endspecify assign Zcat = ${invZ} ( ((${NUMOUT}'b1 << I) != 0) ? I : ${I_BITS}'h0; $${NUMOUT:\n: assign Z% = Zcat[%];} endmodule // demux tkgate-2.0-b10/primitives/rxor.v000644 001751 001751 00000000211 11110103712 017337 0ustar00hansenhansen000000 000000 module rxor #(.Diz(1)) (I0, Z); output ${Z_RANGE} Z; input ${I_RANGE} I0; assign #Diz Z = ${invZ} ^ I0; endmodule // rxor tkgate-2.0-b10/primitives/decoder.v000644 001751 001751 00000000602 11135006431 017765 0ustar00hansenhansen000000 000000 module decoder #(.Dez(1), .Diz(1)) (I, E, $${NUMOUT:, :Z%}); input ${I_RANGE} I; input E; output $${NUMOUT:, :Z%}; wire ${OUT_RANGE} Zcat; specify $${NUMOUT:\n: (E *> Z%) = Dez; } $${NUMOUT:\n: (I *> Z%) = Diz; } endspecify assign Zcat = ${invZ} ({${NUMOUT}{E}} & (${NUMOUT}'b1 << I)); $${NUMOUT:\n: assign Z% = Zcat[%];} endmodule // decoder tkgate-2.0-b10/primitives/nmos_trans.v000644 001751 001751 00000000376 11110077772 020564 0ustar00hansenhansen000000 000000 module nmos_trans #(.Diz(1), .Dgz(1)) (Z, S, G); input ${SGZ_RANGE} S, G; output ${SGZ_RANGE} Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos${SGZ_RANGE} (Z, ${invZ}S, G); endmodule // nmos_trans tkgate-2.0-b10/primitives/pmos_trans.v000644 001751 001751 00000000376 11110077776 020572 0ustar00hansenhansen000000 000000 module pmos_trans #(.Diz(1), .Dgz(1)) (Z, S, G); input ${SGZ_RANGE} S, G; output ${SGZ_RANGE} Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos${SGZ_RANGE} (Z, ${invZ}S, G); endmodule // pmos_trans tkgate-2.0-b10/primitives/buf.v000644 001751 001751 00000000202 11110100743 017122 0ustar00hansenhansen000000 000000 module buf #(.Diz(1)) (I, Z); input ${IZ_RANGE} I; output ${IZ_RANGE} Z; assign #Diz Z = ${invZ}I; endmodule // buf tkgate-2.0-b10/primitives/tribuf.v000644 001751 001751 00000000364 11110102076 017653 0ustar00hansenhansen000000 000000 module tribuf #(.Dez(1), .Diz(1)) (Z, I, E); input ${IZ_RANGE} I; input E; output ${IZ_RANGE} Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (${invZ}I) : ${IZ_BITS}'bz; endmodule // buf tkgate-2.0-b10/primitives/clock.v000644 001751 001751 00000000565 11144654154 017476 0ustar00hansenhansen000000 000000 module clock (Z); output Z; reg Z = ${invZ} 1'b${INITIAL}; initial #${PHASE} if (${INITIAL} == 0) forever begin Z = ${invZ} 1'b1; #${ON_TIME}; Z = ${invZ} 1'b0; #${OFF_TIME}; end else forever begin Z = ${invZ} 1'b0; #${OFF_TIME}; Z = ${invZ} 1'b1; #${ON_TIME}; end endmodule // clock tkgate-2.0-b10/primitives/roll.v000644 001751 001751 00000000455 11110112771 017334 0ustar00hansenhansen000000 000000 module roll #(.Dsz(1), .Diz(1)) (I, Z , S); input ${IZ_RANGE} I; input ${S_RANGE} S; output ${IZ_RANGE} Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ${invZ} ((I << (S % ${IZ_BITS})) | (I >> ((${IZ_BITS} - S) % ${IZ_BITS}))); endmodule // lshift tkgate-2.0-b10/primitives/register.v~000644 001751 001751 00000000703 11140470477 020417 0ustar00hansenhansen000000 000000 module register #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input ${DQ_RANGE} D; output ${DQ_RANGE} Q; reg ${DQ_RANGE} Qreg; specify $setup(D,posedge CK, Dsetup); $hold(posedge CK,D, Dhold); endspecify assign #Dck_q Q = ${invQ}Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = ${DQ_BITS}'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule tkgate-2.0-b10/primitives/rom.v~000644 001751 001751 00000000364 11140443153 017362 0ustar00hansenhansen000000 000000 module rom #(.Dread(1)) (A, D, OE); input OE; input ${A_RANGE} A; output ${D_RANGE} D; reg ${D_RANGE} m${MEM_RANGE}; wire ${D_RANGE} X; assign #Dread X = m[A]; assign D = (~OE) ? ${invD}X : ${D_BITS}'bz; endmodule tkgate-2.0-b10/primitives/jkff.v000644 001751 001751 00000001577 11140751234 017320 0ustar00hansenhansen000000 000000 module jkff #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, _Q, J, K, PRE, CLR, CK); input CK,PRE,CLR; input ${JK_RANGE} J, K; output ${JK_RANGE} Q,_Q; reg ${JK_RANGE} Qreg; specify $setup(J,posedge CK &&& (!PRE && !CLR), Dsetup); $setup(K,posedge CK &&& (!PRE && !CLR), Dsetup); $hold(posedge CK &&& (!PRE && !CLR),J, Dhold); $hold(posedge CK &&& (!PRE && !CLR),K, Dhold); endspecify assign #Dck_q Q = ${invQ}Qreg; assign #Dck_q _Q = ${invNQ}Qreg; initial if (!PRE) Qreg = ${JK_BITS}'b0; else if (!CLR) Qreg = ~${JK_BITS}'b0; // // Handle preset and clear signals // always @ (PRE or CLR) if (!PRE) Qreg = ${JK_BITS}'b0; else if (!CLR) Qreg = ~${JK_BITS}'b0; always @(posedge CK) if (CLR === 1'b1 && PRE === 1'b1) Qreg = (J&~Qreg) | (J&~K) | (Qreg&~K); endmodule tkgate-2.0-b10/povray/search.pov~000644 001751 001751 00000016404 10666701227 017533 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } //object { Paper } object { MagGlass rotate -45*x scale 0.6 translate <.2,.35,-0.9> } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -6> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *3 } tkgate-2.0-b10/povray/LEAF.gif000644 001751 001751 00000166164 07056125506 016550 0ustar00hansenhansen000000 000000 GIF89a,ë÷=E;Œ–¬¿¿¬ÒÞ²°ƒ£žv•‹Åîö–Á¿¢ÏѲß䘮¤}’ƒ•Ñиéì¬ÜÖÔ÷ö £ÛÒÎÄŽ¥•Ž¾¯Æ·•Í¿~£‘…À­²ž•Æ¶v³œ}º¥v«”n›ƒ†º¥v£‹³ÓÅÑ·vœƒ}Â¥•Ú¿ŸÛįë×n«‹=^B…Ë­v³”}ºœ†Â¥É­•Ñ¶–ƬvÁœn¤ƒw«‹~±“AV=ͳ†º›n”vn¾”n³‹vº”}ÂœŒÑ­nœ{¥èÈv¤ƒF^B^šrf£{’Ù³vš{V•j‚Ë¡n«ƒv³‹˜¿¡nº‹=fBvÄ”•Ñ«!^¤rn³ƒvº‹fœr}½’n¤{v«ƒe“lÌ£=nDn‹†Ä™NmKžÜ´~ f¯{EtJN{R^co‡h^«r^œjf¤rn«{=^;v³ƒEfB[„\+3 …á£oºv‰^µs^¤jf«rn³{~Í’]•bŒÚ¡-B&n¡rV{S5J-fŠcV²jmÄ€uˉN…Rgœjç°w¤xV¤b^«jf³rV’ZEnB‘¸‘VºjEƒJg»vNR^œbPvJ^µjg¤jn®rw«x_uS,^,N•RVž[=n;^¤bEvBg«jN}JV…Rw¶z^Z°~VnJV­^4`03V-g•b³ñ»¢Ú¦F^;cÅk_¬aN…JVR$;^•Zƒy™oEEhµi@f8gœb=U1ðúïWº[=x9E@NJV•R^œZg¤b=^3N–JTžQ^¤Z‹Ó‰NsBb¼`Ep;V}Jf‹YJ FuÃn/N€BV…J–ß”_ƒQU¬O(H/Q$VJ^‘R8h-©ê¡Nf>OŽBV•I^žQAn3h•XÍéÆI†;hœXg¨W N};V…B=^,Nv;Ef3V}BNn;VvBE^3"q¼\’´~[™B`‘Iu¦]Vˆ;V};^‚BVv;Om3E[,¨Å‹¼Ö£m†M^s>  ,,ëÿÿ H° Áƒ*\È`¸pJLN‚E"B(nÙ2vìĉۨ±¡É“(Sª\ɲ¥Ë—0O>,ΟHqQ¢,s¥†–4/@i‘*•'ŸyØ-‹Mš´j‰Ä@ªTiL›=¥\E#•åEî+WJZi´h¹ŠÉ¶­Û·pãÊ¥Å>y\éu•Ç–-5©Òc剌'4=hxêä…3P"°þrì 0:6rXÀ Ã A´¶adäA„S§>ÉÃÖªÍ1f<­pç27yÄÍÝÍ»·ïß%èÜ+%-ªI44‘—DÄ Ó…íQHvaºÓŒX:bÎØÿÈòËX«iØ´¡±Å p°aì¯Q‚¤v ¥]ˆ¤a 3¼h&DmRD>`¡Ç9‰ãIÀUhá…þ³ ^ìAÌ&‰üB &i´ÐÂw@òË/l$Òâ&ÆŒ#Ë.dáÉ+‚r‡9Ä4s‡QÞ%Á“ œ€,°ô­³Ë(v„xHBI(9(y04ÒÈv<ñGx$¡E9d„)±ì¡ÆyDáO†|öéçIì ÑF@TH+¤ÅË=(Á #c„HK"Љá3Àò%‚èÓð’F$`I:Óƒž!0`p‚@ÿ0A i°‚ȼa hž°@ =P‘Ä ,ð ÑÃM„Qˆ&\€‚Ô¦B_$‘ 'ü …"^¸ñç¸äòéO}|°Ag A{¤ÅÊS8bŒs´Æƾ‰ìÁ +²‚Á tC‹ž´Á EôÐ`3Ù#‰&V`Àd¬V2Ǽ`RÈ(< M`°À 3Ä‘„A<Â’F˜ EšpRG,hðrpÁ‚ t8¬-€$Ä }”‘G¹L7W8®8q† X „#ˆ rÇÐbL0ˆ@ç+ÚÂâ¾{tÒÉ1¬„ÑÃ#‰@²Ç  áÈ#…` /ÄÿÁ±þú‚›`òŽìÒK3$Á AüÐEIüp‚,ìúCvÔA7s EÂ,TÀ@-Pá†pñì6”p;39­ûî&‰#Í:TQE‰Wxr¨'¬“ ¬$B‹ˆ¿”R )Nì vÄ8Rˆ.´lÒIY¡CøÔx2&t(a†Ûn› Äð"Eí¦AGVaÇšPd  OxB|À…$ü p C–t‚/|b—X…Êb0ˆ>h/à0¬ X+:Á„³Œ›Pˆw($×N¢A‹@TÁBÀB PTW1F:ŽÑ}±AûÅPÿDd½DlâÍ0†1¼v†*Ü! 0Àΰ V\BkP‚ ®€ .øªº¸Äj`ƒ0¤S˜B/j1…Êùà|‚ \@*¤Q[×BV0! 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#declare TWIGS=70*BRANCHES; #declare BUNCHES=1*TWIGS; #declare LEAVES=1*BUNCHES; #declare BLOSSOMS=0*BUNCHES; #declare ROOTS=5; #declare BRANCH_RANDOM=13.77; #declare TWIG_RANDOM=77.37; #declare ROOT_RANDOM=13; //TRUNK #declare TRUNK_RADIUS=26; #declare TRUNK_STRENGTH=1; #declare TRUNK_BEND_X=-20; #declare TRUNK_BEND_Z=20; #declare TRUNK_BEND_X_FREQUENCY=1.5; #declare TRUNK_BEND_Z_FREQUENCY=1.5; #declare TRUNK_CURVE=5; #declare TRUNK_CURVE_FREQUENCY=3; #declare TRUNK_SNAG=0; #declare TRUNK_SNAG_FREQUENCY=10; #declare TRUNK_SPIRAL=35; #declare TRUNK_TAPER=.75; #declare FIRST_BRANCH_AT_TRUNK=700; #declare BRANCH_AREA_AT_TRUNK=50; //BRANCH #declare BRANCH_THICKNESS_CHANGE=.3; #declare BRANCH_STRENGTH=1; #declare BRANCH_BEND=120; #declare BRANCH_BEND_FREQUENCY=.75; #declare HORIZONTAL_BRANCH_BEND_SWITCH=0; #declare EXTRA_NOISE_SWITCH=0; #declare BRANCH_CURVE=0; #declare BRANCH_CURVE_FREQUENCY=3; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=1; #declare BRANCH_LONGITUDINAL_CURVE=1; #declare BRANCH_SNAG=0; #declare BRANCH_SNAG_FREQUENCY=5; #declare BRANCH_REDUCTION=.0; #declare BRANCH_TAPER=.6; #declare BRANCH_END_EQUALIZER=0; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=0; #declare BRANCH_ALTERNATE_SWITCH=0; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=-20; #declare BRANCH_ANGLE_SCOPE=10; #declare BRANCH_ALIGNMENT=.9; #declare STRAIGHTEN_TOWARDS_TOP=0.6; #declare FIRST_TWIG_AT_BRANCH=50; #declare TWIG_AREA_AT_BRANCH=350; //TWIG #declare TWIG_STRENGTH=.0; #declare TWIG_THICKNESS_CHANGE=1; #declare HORIZONTAL_TWIG_ANGLE=0; #declare VERTICAL_TWIG_ANGLE=30; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=10; #declare VERTICAL_TWIG_ANGLE_SCOPE=10; #declare HORIZONTAL_TWIG_ALIGNMENT=.9; #declare VERTICAL_TWIG_ALIGNMENT=1.5; #declare TWIG_TURN_SWITCH=0; #declare TWIG_ALTERNATE_SWITCH=1; #declare TWIG_CURVE_ADJUSTMENT=0; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=0; #declare TWIG_TAPER=1; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=0; #declare LAST_RAMIFICATION_NUMBER=5; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=.5; #declare FIRST_BUNCH_AT_TWIG=0; #declare BUNCH_AREA_AT_TWIG=1; //BUNCH #declare BUNCH_MAJOR_RADIUS=0; #declare BUNCH_MINOR_RADIUS=0; #declare HORIZONTAL_BUNCH_FUNNEL=5; #declare VERTICAL_BUNCH_FUNNEL=5; #declare ROTATION_BUNCH_FUNNEL=0; #declare HORIZONTAL_BUNCH_ANGLE=80; #declare VERTICAL_BUNCH_ANGLE=0; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=5; #declare VERTICAL_BUNCH_ANGLE_SCOPE=10; #declare BUNCH_TURN_SWITCH=0; #declare BUNCH_TURN_SHIFT=0; #declare BUNCH_ALTERNATE_SWITCH=1; #declare HORIZONTAL_BUNCH_ALIGNMENT=1; #declare VERTICAL_BUNCH_ALIGNMENT=.5; #declare BUNCH_TAPER_OFF_AT_TWIG=.0; #declare BUNCH_TAPER_OFF_AT_BRANCH=-1.; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0.25,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=HF_PALMLEAF #declare LEAF_LENGTH=80; #declare LEAF_BREADTH=15; #declare LEAF_HEIGHT=20; #declare MAX_LEAF_TILT=10; #declare MAX_LEAF_TURN=10; #declare LEAF_INCLINATION=35; #declare LEAF_INCLINATION_SCOPE=5; //BLOSSOM #declare BLOSSOM=BLOSSOM2 #declare BLOSSOM_LENGTH=15; #declare BLOSSOM_WIDTH=30; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<1,1,1>; //ROOT #declare FIRST_ROOT_AT_TRUNK=150; #declare ROOT_LENGTH=300; #declare ROOT_THICKNESS_CHANGE=.8; #declare ROOT_STRENGTH=2; #declare ROOT_BEND=50; #declare ROOT_BEND_FREQUENCY=1.5; #declare ROOT_CURVE=15; #declare ROOT_CURVE_FREQUENCY=5; #declare ROOT_SNAG=5; #declare ROOT_SNAG_FREQUENCY=10; #declare ROOT_TURN_SWITCH=1; #declare ROOT_ANGLE=70; #declare ROOT_ALIGNMENT=.0; //BARK #declare SUNKEN_TRUNK_COLOR=<-.2,-.1,0>; #declare RAISED_TRUNK_COLOR=<0.5,0.3,0>; #declare FOLIAGE_COLOR_AT_BRANCH_END=1; #declare TRUNK_SCAR_WIDTH=45; #declare TRUNK_SCAR_HEIGHT=10; #declare HORIZONTAL_SCAR_SHRINKING=.7; #declare VERTICAL_SCAR_SHRINKING=3; #declare SCAR_DEPTH=1; #declare PALM_TRUNK=0.9; #declare BARK_PROFILE=1; #declare BRANCH_BARK_PROFILE_CHANGE=1; #declare BRANCH_BARK_PROFILE_TAPER_OFF=1; #declare ROOT_BARK_PROFILE_CHANGE=.7; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.65,0.55,0>; #declare BOTTOM_COLOR_2=<0.4,0.3,0>; #declare TOP_COLOR_1=<0.3,0.4,0>; #declare TOP_COLOR_2=<.4,.7,0>; #declare COLOR_TURB=2; #declare TRANSITION_BOTTOM_TOP=0.5; #declare TRANSITION_TURB=.5; #declare FOLIAGE_GLOSS=0.25; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX126 tkgate-2.0-b10/povray/TESTTREE.inc000644 001751 001751 00000011227 07065623544 017276 0ustar00hansenhansen000000 000000 //XXXXXXXXXXXXXXXXXXXXX S E T T I N G S XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //TREE #declare BRANCHES=2; #declare TWIGS=2*BRANCHES; #declare BUNCHES=2*TWIGS; #declare LEAVES=1*BUNCHES; #declare BLOSSOMS=0*BUNCHES; #declare ROOTS=2; #declare BRANCH_RANDOM=5.4975; #declare TWIG_RANDOM=2.37; #declare ROOT_RANDOM=13; //TRUNK #declare TRUNK_RADIUS=20; #declare TRUNK_STRENGTH=1; #declare TRUNK_BEND_X=0; #declare TRUNK_BEND_Z=0; #declare TRUNK_BEND_X_FREQUENCY=0; #declare TRUNK_BEND_Z_FREQUENCY=0; #declare TRUNK_CURVE=0; #declare TRUNK_CURVE_FREQUENCY=0; #declare TRUNK_SNAG=0; #declare TRUNK_SNAG_FREQUENCY=0; #declare TRUNK_SPIRAL=0; #declare TRUNK_TAPER=0; #declare FIRST_BRANCH_AT_TRUNK=200; #declare BRANCH_AREA_AT_TRUNK=200; //BRANCH #declare BRANCH_THICKNESS_CHANGE=1; #declare BRANCH_STRENGTH=1; #declare BRANCH_BEND=0; #declare BRANCH_BEND_FREQUENCY=0; #declare HORIZONTAL_BRANCH_BEND_SWITCH=0; #declare EXTRA_NOISE_SWITCH=0; #declare BRANCH_CURVE=0; #declare BRANCH_CURVE_FREQUENCY=0; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=0; #declare BRANCH_LONGITUDINAL_CURVE=0; #declare BRANCH_SNAG=0; #declare BRANCH_SNAG_FREQUENCY=0; #declare BRANCH_REDUCTION=0; #declare BRANCH_TAPER=0; #declare BRANCH_END_EQUALIZER=0; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=0; #declare BRANCH_ALTERNATE_SWITCH=1; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=0; #declare BRANCH_ANGLE_SCOPE=0; #declare BRANCH_ALIGNMENT=0; #declare STRAIGHTEN_TOWARDS_TOP=0; #declare FIRST_TWIG_AT_BRANCH=200; #declare TWIG_AREA_AT_BRANCH=200; //TWIG #declare TWIG_STRENGTH=1; #declare TWIG_THICKNESS_CHANGE=1; #declare HORIZONTAL_TWIG_ANGLE=0; #declare VERTICAL_TWIG_ANGLE=90; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=0; #declare VERTICAL_TWIG_ANGLE_SCOPE=0; #declare HORIZONTAL_TWIG_ALIGNMENT=0; #declare VERTICAL_TWIG_ALIGNMENT=0; #declare TWIG_TURN_SWITCH=0; #declare TWIG_ALTERNATE_SWITCH=1; #declare TWIG_CURVE_ADJUSTMENT=1; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_TAPER=1; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=3; #declare LAST_RAMIFICATION_NUMBER=1; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=1; #declare FIRST_BUNCH_AT_TWIG=200; #declare BUNCH_AREA_AT_TWIG=200; //BUNCH #declare BUNCH_MAJOR_RADIUS=50; #declare BUNCH_MINOR_RADIUS=50; #declare HORIZONTAL_BUNCH_FUNNEL=0; #declare VERTICAL_BUNCH_FUNNEL=180; #declare ROTATION_BUNCH_FUNNEL=0; #declare HORIZONTAL_BUNCH_ANGLE=0; #declare VERTICAL_BUNCH_ANGLE=90; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=0; #declare VERTICAL_BUNCH_ANGLE_SCOPE=0; #declare BUNCH_TURN_SWITCH=0; #declare BUNCH_TURN_SHIFT=0; #declare BUNCH_ALTERNATE_SWITCH=1; #declare HORIZONTAL_BUNCH_ALIGNMENT=0; #declare VERTICAL_BUNCH_ALIGNMENT=0; #declare BUNCH_TAPER_OFF_AT_TWIG=0; #declare BUNCH_TAPER_OFF_AT_BRANCH=0; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=LEAF #declare LEAF_LENGTH=20; #declare LEAF_BREADTH=5; #declare LEAF_HEIGHT=5; #declare MAX_LEAF_TILT=0; #declare MAX_LEAF_TURN=0; #declare LEAF_INCLINATION=0; #declare LEAF_INCLINATION_SCOPE=0; //BLOSSOM #declare BLOSSOM=BLOSSOM2 #declare BLOSSOM_LENGTH=15; #declare BLOSSOM_WIDTH=30; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<1,1,1>; //ROOT #declare FIRST_ROOT_AT_TRUNK=50; #declare ROOT_LENGTH=200; #declare ROOT_THICKNESS_CHANGE=1; #declare ROOT_STRENGTH=1; #declare ROOT_BEND=0; #declare ROOT_BEND_FREQUENCY=0; #declare ROOT_CURVE=0; #declare ROOT_CURVE_FREQUENCY=0; #declare ROOT_SNAG=0; #declare ROOT_SNAG_FREQUENCY=0; #declare ROOT_TURN_SWITCH=0; #declare ROOT_ANGLE=0; #declare ROOT_ALIGNMENT=0; //BARK #declare SUNKEN_TRUNK_COLOR=<-.2,-.2,-.2>; #declare RAISED_TRUNK_COLOR=<0.5,0.3,0>; #declare FOLIAGE_COLOR_AT_BRANCH_END=1; #declare TRUNK_SCAR_WIDTH=5; #declare TRUNK_SCAR_HEIGHT=15; #declare HORIZONTAL_SCAR_SHRINKING=1; #declare VERTICAL_SCAR_SHRINKING=1; #declare SCAR_DEPTH=1; #declare PALM_TRUNK=0; #declare BARK_PROFILE=0; #declare BRANCH_BARK_PROFILE_CHANGE=0; #declare BRANCH_BARK_PROFILE_TAPER_OFF=0; #declare ROOT_BARK_PROFILE_CHANGE=0; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.5,0.3,0.1>; #declare BOTTOM_COLOR_2=<0.4,0.5,0.2>; #declare TOP_COLOR_1=<0.5,0.5,0>; #declare TOP_COLOR_2=<.2,0.6,0.3>; #declare COLOR_TURB=.5; #declare TRANSITION_BOTTOM_TOP=0.5; #declare TRANSITION_TURB=.5; #declare FOLIAGE_GLOSS=0.25; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX tkgate-2.0-b10/povray/TOMLEAF.inc000644 001751 001751 00000007746 07561631656 017145 0ustar00hansenhansen000000 000000 //these declarations are only the bodies for the leaves below #declare BODY= height_field { tga "LEAF.tga" water_level .01 smooth translate <0,0,-0.5> } #declare BODY_tex= object { BODY pigment { image_map { gif "LEAF.gif" interpolate 2 } rotate <90,0,0> translate <0,0,-.5> } } #declare BODY_cut= height_field { tga "LEAFx.tga" smooth water_level .001 scale <1,1.1,1> translate <0,0,-.5> } #declare BLOS_BODY= height_field { tga "BLOSSOM.tga" water_level .05 smooth translate <-.5,0,-0.5> } //XXXXXXXXXXXXX L E A V E S XXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //Simple leaves //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //LEAF - leaf for a good and faster preview and for small simple leaf-shapes; it's only a sphere #declare LEAF= sphere { <.5,0,0>,.5 } //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //CSG_LEAF - for small simple leaf-shapes; with concave underside; needs more memory than LEAF #declare CSG_LEAF= sphere { <.5,0,0>,.5 clipped_by { cylinder { <.5,0,0>,<.5,1.1,0>,.5 scale <1,1,2/3> } } scale <1,1,3/2> } //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //Better height-field-leaves //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //HF_LEAF - with natural outline; good for many leaf-types #declare HF_LEAF= object { BODY clipped_by { object { BODY_cut scale <.999,1,.99> } } } //HF_LEAF_tex - this leaf has the same shape than LEAF, but with a realistic texture; //the disadvantage is that all leaves at the tree get the same texture/coloring #declare HF_LEAF_tex= object { BODY_tex clipped_by { object { BODY_cut scale <.999,1,.99> } } } //HF_PALMLEAF - for long, slim leaves you better use the following PALMLEAVES because of better structure-scaling #declare HF_PALMLEAF= object { BODY clipped_by { object { BODY_cut scale <.999,1,.5> } } scale <1,1,2> } //HF_PALMLEAF_tex - this leaf has the same shape than PALMLEAF, but with a realistic texture; //the disadvantage is that all leaves at the tree get the same texture/coloring #declare HF_PALMLEAF_tex= object { BODY_tex clipped_by { object { BODY_cut scale <.999,1,.4> } } scale <1,1,2.5> } //HF_PALMLEAF1 - this leaf is equal to PALMLEAF, but with a round tip #declare HF_PALMLEAF1= object { BODY translate <-.5,0,0> scale <1,1,1> clipped_by { cylinder { <0,-2,0>,<0,2,0>,.5 scale <.99,1,.4> } } scale <1,1,2.5> translate <.5,0,0> } //HF_PALMLEAF1_tex - and again with its own texture #declare HF_PALMLEAF1_tex= object { BODY_tex translate <-.5,0,0> scale <1,1,1> clipped_by { cylinder { <0,-2,0>,<0,2,0>,.5 scale <.99,1,.4> } } scale <1,1,2.5> translate <.5,0,0> } //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //Some blossoms //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //BLOSSOM1 - with six round small leaves #declare BLOSSOM1= object { BLOS_BODY scale <1,.5,1> clipped_by { torus { .275,.24 scale <1.0,1.6,1.0> inverse } } scale <1,2,1> rotate <0,0,-90> translate <-.05,0,0> finish{ambient .2} } //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //BLOSSOM2 - with six slim small leaves #declare BLOSSOM2= object { BLOS_BODY scale <1,.5,1> clipped_by { torus { .275,.23 scale <1.0,1.85,1.0> inverse } } scale <1,2,1> rotate <0,0,-90> translate <-.05,0,0> finish{ambient .2} } tkgate-2.0-b10/povray/TOMTREE.inc000644 001751 001751 00000122310 07065067704 017152 0ustar00hansenhansen000000 000000 //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Persistence of Vision 3.1 Include File XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // File: TOMTREE.inc XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Desc: BAUMGENERATOR FÜR POVRAY XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Date: MARCH 2000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Auth: TOM AUST XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX #declare M_BL=LEAF_LENGTH; #declare M_BH=LEAF_HEIGHT; #declare M_BB=LEAF_BREADTH; #declare M_BN_X=MAX_LEAF_TILT; #declare M_BN_Y=MAX_LEAF_TURN; #declare M_BN_Z=LEAF_INCLINATION; #declare M_BN_Z_SCOPE=LEAF_INCLINATION_SCOPE; #declare BL_N_Z=BLOSSOM_INCLINATION; #declare M_BL_L=BLOSSOM_LENGTH; #declare M_BL_B=BLOSSOM_WIDTH; #declare BL_F=BLOSSOM_COLOR; #declare S_MA_R=BUNCH_MAJOR_RADIUS+0.000001; #declare S_MI_R=BUNCH_MINOR_RADIUS+0.000001; #declare V_S_T=VERTICAL_BUNCH_FUNNEL; #declare H_S_T=HORIZONTAL_BUNCH_FUNNEL; #declare S_R_T=ROTATION_BUNCH_FUNNEL; #declare BL_Z=BLOSSOMS; #declare BZ=LEAVES; #declare SZ=BUNCHES; #declare ZWZ=TWIGS; #declare AZ=BRANCHES; #if (ZWZ>0) #if (SZ/ZWZ>1) #declare B_A_T=BUNCH_AREA_AT_TWIG*((SZ/ZWZ)/((SZ/ZWZ)-1))+0.000001; #declare S_NEIG=HORIZONTAL_BUNCH_ALIGNMENT*((SZ/ZWZ)/((SZ/ZWZ)-1)); #declare V_S_NEIG=VERTICAL_BUNCH_ALIGNMENT*((SZ/ZWZ)/((SZ/ZWZ)-1)); #else #declare B_A_T=BUNCH_AREA_AT_TWIG+0.000001; #declare S_NEIG=HORIZONTAL_BUNCH_ALIGNMENT; #declare V_S_NEIG=VERTICAL_BUNCH_ALIGNMENT; #end #else #declare B_A_T=BUNCH_AREA_AT_TWIG+0.000001; #declare S_NEIG=HORIZONTAL_BUNCH_ALIGNMENT; #declare V_S_NEIG=VERTICAL_BUNCH_ALIGNMENT; #end #declare S_NEIG=S_NEIG*S_NEIG; #declare V_S_NEIG=V_S_NEIG*V_S_NEIG; #declare ZL=FIRST_BUNCH_AT_TWIG+B_A_T+1.1; #declare S_VJ_A=BUNCH_TAPER_OFF_AT_BRANCH; #declare S_VJ_B=BUNCH_TAPER_OFF_AT_TREE; #declare S_VJ_Z=BUNCH_TAPER_OFF_AT_TWIG; #declare S_W_S=BUNCH_ALTERNATE_SWITCH; #declare S_A=FIRST_BUNCH_AT_TWIG+0.000001; #declare Z_A=FIRST_TWIG_AT_BRANCH+0.000001; #if (AZ>0) #if (ZWZ/AZ>1) #declare Z_B=TWIG_AREA_AT_BRANCH*((ZWZ/AZ)/((ZWZ/AZ)-1))+0.000001; #declare ZW_NEIG=HORIZONTAL_TWIG_ALIGNMENT*((ZWZ/AZ)/((ZWZ/AZ)-1)); #declare V_ZW_NEIG=VERTICAL_TWIG_ALIGNMENT*((ZWZ/AZ)/((ZWZ/AZ)-1)); #else #declare Z_B=TWIG_AREA_AT_BRANCH+0.000001; #declare ZW_NEIG=HORIZONTAL_TWIG_ALIGNMENT; #declare V_ZW_NEIG=VERTICAL_TWIG_ALIGNMENT; #end #else #declare Z_B=TWIG_AREA_AT_BRANCH+0.000001; #declare ZW_NEIG=HORIZONTAL_TWIG_ALIGNMENT; #declare V_ZW_NEIG=VERTICAL_TWIG_ALIGNMENT; #end #declare ZW_NEIG=ZW_NEIG*ZW_NEIG; #declare V_ZW_NEIG=V_ZW_NEIG*V_ZW_NEIG; #declare H_S_N=HORIZONTAL_BUNCH_ANGLE; #declare V_S_N=VERTICAL_BUNCH_ANGLE; #declare H_S_N_SP=HORIZONTAL_BUNCH_ANGLE_SCOPE; #declare V_S_N_SP=VERTICAL_BUNCH_ANGLE_SCOPE; #declare S_DREH=BUNCH_TURN_SWITCH; #declare S_DREH_VERSCHIEBUNG=BUNCH_TURN_SHIFT; #declare H_ZW_N=HORIZONTAL_TWIG_ANGLE; #declare V_ZW_N=VERTICAL_TWIG_ANGLE; #declare H_ZW_N_SP=HORIZONTAL_TWIG_ANGLE_SCOPE; #declare V_ZW_N_SP=VERTICAL_TWIG_ANGLE_SCOPE; #declare ZW_W_S=TWIG_ALTERNATE_SWITCH; #declare ZW_DREH=TWIG_TURN_SWITCH; #declare AA=FIRST_BRANCH_AT_TRUNK; #if (AZ>1) #declare AB=BRANCH_AREA_AT_TRUNK*(AZ/(AZ-1))+0.000001; #else #declare AB=BRANCH_AREA_AT_TRUNK+0.000001; #end #declare BG_X=TRUNK_BEND_X; #declare BG_Z=TRUNK_BEND_Z; #declare FZ_X=TRUNK_BEND_X_FREQUENCY; #declare FZ_Z=TRUNK_BEND_Z_FREQUENCY; #declare SW=TRUNK_CURVE; #declare SWFZ=TRUNK_CURVE_FREQUENCY; #declare KK=TRUNK_SNAG; #declare SKKFZ=TRUNK_SNAG_FREQUENCY; #declare ZW_L=ZL+S_MA_R+S_MI_R; #declare ZE=TWIG_TIP; #declare AST_L=(Z_A+Z_B+ZW_L); #declare AST_ST=BRANCH_THICKNESS_CHANGE; #declare AST_VK=BRANCH_REDUCTION; #declare AST_VJ=BRANCH_TAPER; #declare AST_DREH=BRANCH_TURN_SWITCH; #declare A_W_S=BRANCH_ALTERNATE_SWITCH; #declare BH=(AA+AB+AST_L); #declare AW=BRANCH_CURVE*BH/AST_L; #declare A_KK=BRANCH_SNAG*BH/AST_L; #declare A_BG=BRANCH_BEND*BH/AST_L; #declare ABFZ=BRANCH_BEND_FREQUENCY*.7*(AST_L/(Z_A+Z_B+ZW_L*(1-AST_VJ))); #declare ZBFZA=TWIG_CURVE_FREQUENCY_ADJUSTMENT*(ZW_L/(ZL+(S_MA_R+S_MI_R)*(1-S_VJ_Z)))/(AST_L/(Z_A+Z_B+ZW_L*(1-AST_VJ))); #declare RFZA=RAMI_CURVE_FREQUENCY_ADJUSTMENT/(ZW_L/(ZL+(S_MA_R+S_MI_R)*(1-S_VJ_Z))); #declare AKKFZ=BRANCH_SNAG_FREQUENCY*1.75; #declare AWFZ=BRANCH_CURVE_FREQUENCY*1.6; #declare H_ABG_S=HORIZONTAL_BRANCH_BEND_SWITCH; #declare B_F_1=BOTTOM_COLOR_1; #declare B_F_2=BOTTOM_COLOR_2; #declare K_F_1=TOP_COLOR_1; #declare K_F_2=TOP_COLOR_2; #declare UE_B_K=TRANSITION_BOTTOM_TOP; #declare UE_T=TRANSITION_TURB; #declare ST_F_1=SUNKEN_TRUNK_COLOR; #declare ST_F_2=RAISED_TRUNK_COLOR; #declare ST_VJ=TRUNK_TAPER; #declare WA=FIRST_ROOT_AT_TRUNK; #declare W_BG=ROOT_BEND; #declare WBFZ=ROOT_BEND_FREQUENCY; #declare W_W=ROOT_CURVE; #declare WWFZ=ROOT_CURVE_FREQUENCY; #declare W_KK=ROOT_SNAG; #declare WKKFZ=ROOT_SNAG_FREQUENCY; #declare W_ST=ROOT_THICKNESS_CHANGE; #declare W_L=ROOT_LENGTH; #declare W_DREH=ROOT_TURN_SWITCH; #declare ZW_VST=TWIG_THICKNESS_CHANGE; #declare AST_E=BRANCH_TIP; #declare H_AW_S=HORIZONTAL_BRANCH_CURVE_SWITCH; #declare A_L_W=BRANCH_LONGITUDINAL_CURVE; #declare ZW_K_A=TWIG_CURVE_ADJUSTMENT; #declare AST_SPIEL=BRANCH_RANDOM; #declare ZW_SPIEL=TWIG_RANDOM; #declare ASTNEIGUNG=BRANCH_ANGLE; #declare A_N_SP=BRANCH_ANGLE_SCOPE; #if (AZ>1) #declare A_NEIG=BRANCH_ALIGNMENT*(AZ/(AZ-1)); #else #declare A_NEIG=BRANCH_ALIGNMENT; #end #declare L_R_NR=LAST_RAMIFICATION_NUMBER; #declare H_B_T=HORIZONTAL_SCAR_SHRINKING; #declare V_B_T=VERTICAL_SCAR_SHRINKING; #declare TRCA=TWIG_RAMIFICATION_CURVE_ADJUSTMENT; #declare R_A=ROOT_ALIGNMENT; #declare TT=TWIG_TAPER; #declare A_STR=STRAIGHTEN_TOWARDS_TOP; #declare T_STR=STRAIGHTEN_TOWARDS_BRANCH_END; #declare FCaBE=FOLIAGE_COLOR_AT_BRANCH_END; #declare BPTo=BRANCH_BARK_PROFILE_TAPER_OFF; #declare arcTaT=BUNCH_ARC_AT_TWIG; #declare arcTaB=BUNCH_ARC_AT_BRANCH; #declare BEE=BRANCH_END_EQUALIZER; #declare ANS=EXTRA_NOISE_SWITCH; #declare UNIT_1=AA+AB+(1-AST_VK)*(Z_A+Z_B+(1-AST_VJ)*(S_A+B_A_T+(S_MA_R+S_MI_R+M_BL)*(1-S_VJ_B)*(1-S_VJ_A)*(1-S_VJ_Z))); #declare RINDE= texture { pigment { granite cubic_wave color_map { [0 color rgb ST_F_1] [0.35 color rgb ST_F_2] [.5 color rgb ST_F_2*2] [0.65 color rgb ST_F_2] [1 color rgb ST_F_1] } scale *3 } #if (SCAR_DEPTH>0) normal { granite SCAR_DEPTH/5 rotate <0,0,0> scale *3 } #end finish { phong SCAR_DEPTH/5 phong_size 4 } } #declare RINDE1= texture { pigment { granite cubic_wave color_map { [0 color rgb ST_F_1] [0.35 color rgb (B_F_1+B_F_2+K_F_1+K_F_2)/4] [.5 color rgb (B_F_1+B_F_2+K_F_1+K_F_2)/2] [0.65 color rgb (B_F_1+B_F_2+K_F_1+K_F_2)/4] [1 color rgb ST_F_1] } scale *3 } #if (SCAR_DEPTH>0) normal { granite SCAR_DEPTH/5 rotate <0,0,0> scale *3 } #end finish { phong SCAR_DEPTH/5 phong_size 4 } } #declare BOZO1 = pigment { bozo color_map { [0 color rgb B_F_1] [1 color rgb B_F_2] } scale BH/(250*(COLOR_TURB+.1)*BH) } #declare BOZO2 = pigment { bozo color_map { [0 color rgb K_F_1] [1 color rgb K_F_2] } scale BH/(250*(COLOR_TURB+.1)*BH) } #declare LAUB= texture { pigment { gradient y cubic_wave turbulence UE_T omega UE_T pigment_map { [UE_B_K BOZO1] [1 BOZO2] } scale UNIT_1 } finish { phong 0.4*FOLIAGE_GLOSS phong_size 20*FOLIAGE_GLOSS } } #if (AZ>=1) #if (ZWZ>=1) #if (SZ>=1) #if (TWIG_RAMIFICATION_ORDER>0) #if (TWIG_RAMIFICATION_STRENGTH>0) #declare TWIGGI= blob { threshold TRUNK_RADIUS*3 #declare A=1; #while (A,TRUNK_RADIUS*5,TRUNK_RADIUS*10 scale TRUNK_RADIUS/90 scale (BH-A)/BH scale AST_ST scale BH/(S_MA_R+S_MI_R+M_BL) scale ZW_VST scale TWIG_RAMIFICATION_THICKNESS_CHANGE scale (BH-AA*ST_VJ)/BH scale (ZW_L-S_A)/ZW_L scale (AST_L-Z_A)/AST_L #if (S_VJ_A<0) scale 1/(1-S_VJ_A*(Z_A+Z_B)/AST_L) #end #if (S_VJ_B<0) scale 1/(1-S_VJ_B*(AA+AB)/BH) #end #if (S_VJ_Z<1) scale 1/(1-(S_VJ_Z-1)*(S_A+B_A_T)/ZW_L) #end scale 1/BUNCH_DEFORM scale 1/(1+arcTaT) scale 1/(1+arcTaB) translate *((BH-A)/BH)*ZW_K_A*TRCA translate *((BH-A)/BH)*ZW_K_A*TRCA translate * rotate <0,BRANCH_SPIRAL*sin(A/BH*(pi/2)),0> } #declare A=A+BH/TWIG_RAMIFICATION_STRENGTH/200; #end } #end #end #end #end #end #if (AZ>=1) #if (ZWZ>=1) #if (SZ>=1) #if (TWIG_RAMIFICATION_ORDER=1) #if (TWIG_RAMIFICATION_STRENGTH>0) #declare REISIG= object { TWIGGI bounded_by{cylinder{<0,0,0>,<0,BH,0>,BH}} } #end #end #end #end #end #if (AZ>=1) #if (ZWZ>=1) #if (SZ>=1) #if (TWIG_RAMIFICATION_ORDER=2) #if (TWIG_RAMIFICATION_STRENGTH>0) #if (LAST_RAMIFICATION_NUMBER>0) #declare REISIG= union { object{TWIGGI} #declare A=BH/(L_R_NR+1); #while (A #if (S_R_T>0) rotate <0,0,-(S_R_T/2)*(1-(A*A)/(BH*BH))>*(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) rotate <0,777*sin(2.37*A*pi),0> #else rotate <0,0,V_S_T/2*(1-(A*A)/(BH*BH))*(sin(A*pi/2) #if (sin(A*pi/2)<0) -(1+sin(A*pi/2)) #else +(1-sin(A*pi/2)) #end)>*(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) rotate *(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) #end translate *((BH-A)/BH)*ZW_K_A*TRCA translate *((BH-A)/BH)*ZW_K_A*TRCA translate * rotate <0,BRANCH_SPIRAL*sin(A/BH*(pi/2)),0> } #declare A=A+BH/(L_R_NR+1); #end bounded_by{cylinder{<0,0,0>,<0,BH,0>,BH}} } #end #end #end #end #end #end #if (AZ>=1) #if (ZWZ>=1) #if (SZ>=1) #if (TWIG_RAMIFICATION_ORDER=3) #if (TWIG_RAMIFICATION_STRENGTH>0) #if (LAST_RAMIFICATION_NUMBER>0) #declare REISIG= union { object{TWIGGI} #declare B=BH/(L_R_NR+1); #while (B #if (S_R_T>0) rotate <0,0,-S_R_T/2*(1-(A)/(BH))>*((L_R_NR+1)/L_R_NR) rotate <0,777*sin(2.37*A*pi),0> #else rotate <0,0,V_S_T/2*(1-(A)/(BH))*(sin(A*pi/2) #if (sin(A*pi/2)<0) -(1+sin(A*pi/2)) #else +(1-sin(A*pi/2)) #end)>*((L_R_NR+1)/L_R_NR) rotate *((L_R_NR+1)/L_R_NR) #end rotate <0,-1234.567*sin(B*4.56*pi)+180,0> translate *((BH-A)/BH)*ZW_K_A*TRCA translate *((BH-A)/BH)*ZW_K_A*TRCA translate * rotate <0,BRANCH_SPIRAL*sin(A/BH*(pi/2)),0> } #declare A=A+BH/(L_R_NR+1); #end scale 1-B/BH rotate <0,1234.567*sin(B*4.56*pi),0> #if (S_R_T>0) rotate <0,0,-S_R_T/2*(1-(B*B)/(BH*BH))>*(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) rotate <0,777*sin(2.37*B*pi),0> #else rotate <0,0,V_S_T/2*(1-(B*B)/(BH*BH))*(sin(B*pi/2) #if (sin(B*pi/2)<0) -(1+sin(B*pi/2)) #else +(1-sin(B*pi/2)) #end)>*(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) rotate *(((L_R_NR+1)*(L_R_NR+1))/(((L_R_NR+1)*(L_R_NR+1))-1)) #end translate *((BH-B)/BH)*ZW_K_A*TRCA translate *((BH-B)/BH)*ZW_K_A*TRCA translate * rotate <0,BRANCH_SPIRAL*sin(B/BH*(pi/2)),0> } #declare B=B+BH/(L_R_NR+1); #end bounded_by{sphere{<0,0,0>,BH}} } #end #end #end #end #end #end #declare TREE= union { #if (M_BL*M_BH*M_BB>0) #if (AZ>=1) #if (ZWZ>=1) #if (BZ>=1) #if (SZ>=1) #if (BZ/SZ>1) #declare STAUDE = union { #declare A=1; #while (A<100) object { LEAF_TYPE scale rotate rotate <0,M_BN_Y*sin(7.17*A*pi),0> translate #if (S_R_T>0) rotate <0,0,-S_R_T/4*(1+sin(sin(pi*2.37*A)*pi*12.3+pi/5))> rotate <777*sin(2.37*A*pi),0,0> #else rotate <0,0,V_S_T/2*sin(sin(pi*7.73*A)*pi*12.3+pi/3)> rotate <0,H_S_T/2*sin(sin(pi*2.37*A)*pi*12.3+pi/5),0> #end } #declare A=A+100/BZ*SZ; #end } #else #declare STAUDE = object { LEAF_TYPE scale rotate rotate <0,M_BN_Y,0> translate } #end union { #declare A=1; #while (A rotate <-1234*sin(7.77*C*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-1234*sin(7.77*A*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0,0> rotate <-1234*sin(ZW_SPIEL*4.77*B*pi),0,0>*(1-ZW_W_S) rotate <-BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0,0> rotate <0,(H_S_N_SP/2)*sin(7.77*C*pi),0> rotate <0,0,V_S_N_SP/2*sin(9.77*C*pi)>+<0,0,(V_S_N #if (SZ/ZWZ>1) -(V_S_N*(C*C)/(ZL*ZL)*V_S_NEIG) #end )> rotate <0, #if (SZ/ZWZ=1) (H_S_N-(H_S_N*(A*A)/(BH*BH)*S_NEIG))*((1-S_W_S)+(S_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) #else -(H_S_N*(C*C)/(ZL*ZL)*S_NEIG)*((1-S_W_S)+S_W_S*sin((C/(ZL/(SZ/ZWZ))-1/(ZL/(SZ/ZWZ)))*pi-pi/2)) #end ,0> rotate <1234*sin(7.77*C*pi),0,0>*S_DREH rotate <1234*sin(7.77*A*pi),0,0>*S_DREH scale (1-S_VJ_B*B/100) scale (1-S_VJ_Z*(C)/(ZL)) scale (1-S_VJ_A*(A)/(BH)) rotate <0,0,90> rotate <0,-1234*sin(4.77*A*pi),0>*ZW_DREH translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *(ZW_L/BH)*<1,1,H_ABG_S>**<1-B/100*A_STR,1,1-B/100*A_STR>*<(1-A/BH*T_STR),1,(1-A/BH*T_STR)> rotate <0,BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*A*pi),0>*ZW_DREH scale ((Z_A+Z_B+ZW_L*(1-AST_VJ))-Z_A*AST_VJ*AST_L/BH)/(Z_A+Z_B+ZW_L*(1-AST_VJ)) scale ((Z_B+ZW_L*(1-AST_VJ))-A*AST_VJ*Z_B/BH)/(Z_B+ZW_L*(1-AST_VJ)) scale BH/AST_L rotate <0,0,-90> rotate <0,0,V_ZW_N_SP*sin(9.77*A*A*pi)>+<0,0,(V_ZW_N-(V_ZW_N*(A*A)/(BH*BH)*V_ZW_NEIG))> rotate <0,H_ZW_N_SP*sin(7.77*A*A*pi),0>+<0,(H_ZW_N-(H_ZW_N*(A*A)/(BH*BH)*ZW_NEIG)),0>*((1-ZW_W_S)+(ZW_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) rotate <1456*cos(AST_SPIEL*7.19*A*pi)*(1-ZW_W_S),0,0> rotate <0,0,90> rotate <0,1234*sin(ZW_SPIEL*4.77*B*pi),0>*(1-ZW_W_S) rotate <0,-1234*sin(4.77*B*pi),0>*AST_DREH translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*(1-B/100*A_STR) translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*<1,A_L_W,H_AW_S>*(1-B/100*A_STR) translate *<-1,1,H_ABG_S>*<1-B/100*A_STR,1,1-B/100*A_STR> rotate <0,BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*B*pi),0>*AST_DREH rotate <0,0,-90> scale (AST_L/BH)*(1-B/100*AST_VK) rotate <0,0,ASTNEIGUNG+((B/100)*((90-ASTNEIGUNG)))*A_NEIG>+<0,0,A_N_SP*sin(9.77*B*B*pi)> rotate <0,1456*cos(AST_SPIEL*7.19*B*pi)*(1-A_W_S)+90*A_W_S*sin((B/(100/AZ)-1/(100/AZ))*pi-pi/2)+90,0> translate *((BH-(AA+(B*AB/100)))/BH) translate *((BH-(AA+(B*AB/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((AA+(B*AB/100))/(BH*3/5)),0> } #declare C=C+ZL/SZ*ZWZ; #end #declare B=B+100/AZ; #end #declare A=A+BH/ZWZ*AZ; #end texture{LAUB} } #end #end #end #end #end #if (M_BL_L*M_BL_B>0) #if (AZ>=1) #if (ZWZ>=1) #if (BL_Z>=1) #if (SZ>=1) #if (BL_Z/SZ>1) #declare B_STAUDE = union { #declare A=1; #while (A<100*BL_Z) object { BLOSSOM scale rotate rotate <0,M_BN_Y*sin(7.17*A*pi),0> translate #if (S_R_T>0) rotate <0,0,-S_R_T/4*(1+sin(sin(2.37*A*pi)*pi*12.3+pi/5))> rotate <777*sin(2.37*A*pi),0,0> #else rotate <0,0,V_S_T/2*sin(sin(7.73*A*pi)*pi*12.3+pi/3)> rotate <0,H_S_T/2*sin(sin(2.37*A*pi)*pi*12.3+pi/5),0> #end pigment{color rgb BL_F} } #declare A=A+100*SZ; #end } #else #declare B_STAUDE = object { BLOSSOM scale rotate rotate <0,M_BN_Y,0> translate pigment{color rgb BL_F} } #end union { #declare A=1; #while (A rotate <-1234*sin(7.77*C*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-1234*sin(7.77*A*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0,0> rotate <-1234*sin(ZW_SPIEL*4.77*B*pi),0,0>*(1-ZW_W_S) rotate <-BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0,0> rotate <0,H_S_N_SP/2*sin(7.77*C*pi),0> rotate <0,0,V_S_N_SP/2*sin(9.77*C*pi)>+<0,0,(V_S_N #if (SZ/ZWZ>1) -(V_S_N*(C*C)/(ZL*ZL)*V_S_NEIG) #end )> rotate <0, #if (SZ/ZWZ=1) (H_S_N-(H_S_N*(A*A)/(BH*BH)*S_NEIG))*((1-S_W_S)+(S_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) #else -(H_S_N*(C*C)/(ZL*ZL)*S_NEIG)*((1-S_W_S)+S_W_S*sin((C/(ZL/(SZ/ZWZ))-1/(ZL/(SZ/ZWZ)))*pi-pi/2)) #end ,0> rotate <1234*sin(7.77*C*pi),0,0>*S_DREH rotate <1234*sin(7.77*A*pi),0,0>*S_DREH scale (1-S_VJ_B*B/100) scale (1-S_VJ_Z*(C)/(ZL)) scale (1-S_VJ_A*(A)/(BH)) rotate <0,0,90> rotate <0,-1234*sin(4.77*A*pi),0>*ZW_DREH translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *(ZW_L/BH)*<1,1,H_ABG_S>**<1-B/100*A_STR,1,1-B/100*A_STR>*<(1-A/BH*T_STR),1,(1-A/BH*T_STR)> rotate <0,BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*A*pi),0>*ZW_DREH scale ((Z_A+Z_B+ZW_L*(1-AST_VJ))-Z_A*AST_VJ*AST_L/BH)/(Z_A+Z_B+ZW_L*(1-AST_VJ)) scale ((Z_B+ZW_L*(1-AST_VJ))-A*AST_VJ*Z_B/BH)/(Z_B+ZW_L*(1-AST_VJ)) scale BH/AST_L rotate <0,0,-90> rotate <0,0,V_ZW_N_SP*sin(9.77*A*A*pi)>+<0,0,(V_ZW_N-(V_ZW_N*(A*A)/(BH*BH)*V_ZW_NEIG))> rotate <0,H_ZW_N_SP*sin(7.77*A*A*pi),0>+<0,(H_ZW_N-(H_ZW_N*(A*A)/(BH*BH)*ZW_NEIG)),0>*((1-ZW_W_S)+(ZW_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) rotate <1456*cos(AST_SPIEL*7.19*A*pi)*(1-ZW_W_S),0,0> rotate <0,0,90> rotate <0,1234*sin(ZW_SPIEL*4.77*B*pi),0>*(1-ZW_W_S) rotate <0,-1234*sin(4.77*B*pi),0>*AST_DREH translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*(1-B/100*A_STR) translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*<1,A_L_W,H_AW_S>*(1-B/100*A_STR) translate *<-1,1,H_ABG_S>*<1-B/100*A_STR,1,1-B/100*A_STR> rotate <0,BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*B*pi),0>*AST_DREH rotate <0,0,-90> scale (AST_L/BH)*(1-B/100*AST_VK) rotate <0,0,ASTNEIGUNG+((B/100)*((90-ASTNEIGUNG)))*A_NEIG>+<0,0,A_N_SP*sin(9.77*B*B*pi)> rotate <0,1456*cos(AST_SPIEL*7.19*B*pi)*(1-A_W_S)+90*A_W_S*sin((B/(100/AZ)-1/(100/AZ))*pi-pi/2)+90,0> translate *((BH-(AA+(B*AB/100)))/BH) translate *((BH-(AA+(B*AB/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((AA+(B*AB/100))/(BH*3/5)),0> } #declare C=C+ZL/SZ*ZWZ; #end #declare B=B+100/AZ; #end #declare A=A+BH/ZWZ*AZ; #end } #end #end #end #end #end #if (AZ>=1) #if (ZWZ>=1) #if (SZ>=1) #if (TWIG_RAMIFICATION_ORDER>0) union { #declare A=1; #while (A scale BUNCH_DEFORM scale (1+arcTaT*sin(pi*(C*((SZ/ZWZ+1)/(SZ/ZWZ))/ZL))) scale (1+arcTaB*sin(pi*(A*((ZWZ/AZ+1)/(ZWZ/AZ))/BH))) rotate <-1456*cos(AST_SPIEL*7.19*A*pi)*(1-ZW_W_S),0,0> rotate <-1234*sin(7.77*C*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-1234*sin(7.77*A*pi),0,0>*S_DREH_VERSCHIEBUNG rotate <-BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0,0> rotate <-1234*sin(ZW_SPIEL*4.77*B*pi),0,0>*(1-ZW_W_S) rotate <-BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0,0> rotate <0,H_S_N_SP/2*sin(7.77*C*pi),0> rotate <0,0,V_S_N_SP/2*sin(9.77*C*pi)>+<0,0,(V_S_N #if (SZ/ZWZ>1) -(V_S_N*(C*C)/(ZL*ZL)*V_S_NEIG) #end )> rotate <0, #if (SZ/ZWZ=1) (H_S_N-(H_S_N*(A*A)/(BH*BH)*S_NEIG))*((1-S_W_S)+(S_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) #else -(H_S_N*(C*C)/(ZL*ZL)*S_NEIG)*((1-S_W_S)+S_W_S*sin((C/(ZL/(SZ/ZWZ))-1/(ZL/(SZ/ZWZ)))*pi-pi/2)) #end ,0> rotate <1234*sin(7.77*C*pi),0,0>*S_DREH rotate <1234*sin(7.77*A*pi),0,0>*S_DREH scale (1-S_VJ_B*B/100) scale (1-S_VJ_Z*(C)/(ZL)) scale (1-S_VJ_A*(A)/(BH)) rotate <0,0,90> rotate <0,-1234*sin(4.77*A*pi),0>*ZW_DREH translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *((BH-((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L)))/BH)*(ZW_L/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *<1,1,H_ABG_S>*(ZW_L/BH)**<1-B/100*A_STR,1,1-B/100*A_STR>*<(1-A/BH*T_STR),1,(1-A/BH*T_STR)> rotate <0,BRANCH_SPIRAL*sin(((S_A+((ZL-S_A)/ZL*C))*(BH/ZW_L))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*A*pi),0>*ZW_DREH scale ((Z_A+Z_B+ZW_L*(1-AST_VJ))-Z_A*AST_VJ*AST_L/BH)/(Z_A+Z_B+ZW_L*(1-AST_VJ)) scale ((Z_B+ZW_L*(1-AST_VJ))-A*AST_VJ*Z_B/BH)/(Z_B+ZW_L*(1-AST_VJ)) scale BH/AST_L rotate <0,0,-90> rotate <0,0,V_ZW_N_SP*sin(9.77*A*A*pi)>+<0,0,(V_ZW_N-(V_ZW_N*(A*A)/(BH*BH)*V_ZW_NEIG))> rotate <0,H_ZW_N_SP*sin(7.77*A*A*pi),0>+<0,(H_ZW_N-(H_ZW_N*(A*A)/(BH*BH)*ZW_NEIG)),0>*((1-ZW_W_S)+(ZW_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) rotate <1456*cos(AST_SPIEL*7.19*A*pi)*(1-ZW_W_S),0,0> rotate <0,0,90> rotate <0,1234*sin(ZW_SPIEL*4.77*B*pi),0>*(1-ZW_W_S) rotate <0,-1234*sin(4.77*B*pi),0>*AST_DREH translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*(1-B/100*A_STR) translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*<1,A_L_W,H_AW_S>*(1-B/100*A_STR) translate *<-1,1,H_ABG_S>*<1-B/100*A_STR,1,1-B/100*A_STR> rotate <0,BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*B*pi),0>*AST_DREH rotate <0,0,-90> scale (AST_L/BH)*(1-B/100*AST_VK) rotate <0,0,ASTNEIGUNG+((B/100)*((90-ASTNEIGUNG)))*A_NEIG>+<0,0,A_N_SP*sin(9.77*B*B*pi)> rotate <0,1456*cos(AST_SPIEL*7.19*B*pi)*(1-A_W_S)+90*A_W_S*sin((B/(100/AZ)-1/(100/AZ))*pi-pi/2)+90,0> translate *((BH-(AA+(B*AB/100)))/BH) translate *((BH-(AA+(B*AB/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((AA+(B*AB/100))/(BH*3/5)),0> } #declare C=C+ZL/SZ*ZWZ; #end #declare B=B+100/AZ; #end #declare A=A+BH/ZWZ*AZ; #end } #end #end #end #end blob { threshold TRUNK_RADIUS*3 #if (TRUNK_STRENGTH>0) #declare A=1; #while (A<=(AA+ #if (AZ>=1) ((AZ-1)/AZ)* #end AB)) sphere { <0,0,0>,TRUNK_RADIUS*5,TRUNK_RADIUS*10 scale TRUNK_RADIUS/90 scale (BH-A*ST_VJ)/BH #if (PALM_TRUNK=0) scale <1,1,1>+<-BARK_PROFILE*.9,BARK_PROFILE*.25,BARK_PROFILE*.25> rotate <0,0,20.3*sin(3.12*A*pi)> rotate <0,12347.3*sin(3.77*A*pi),0> #else scale <1,1,1>+<0,-PALM_TRUNK*.9,PALM_TRUNK*.5> rotate <35,12347.3*sin(4.77*A*pi),0> #end #if (A>AA) scale (1-(A-AA)/AB*AST_VK) scale 1-((A-AA)/( #if (AZ>1) ((AZ-1)/AZ)* #end AB))*(1-AST_ST) #else scale 1 #end translate *((BH-A)/BH) translate *((BH-A)/BH) translate rotate <0,TRUNK_SPIRAL*sin(A/(BH*3/5)),0> } #declare A=A+BH/TRUNK_STRENGTH/1000; #end #else sphere{<0,0,0>,TRUNK_RADIUS*.01,TRUNK_RADIUS*10} #end #if (BRANCH_STRENGTH>0) #if (AZ>=1) #declare A=1; #while (A<=(Z_A+ #if (ZWZ/AZ>1) ((ZWZ/AZ-1)/(ZWZ/AZ))* #end Z_B+ #if (ZWZ/AZ>1) (Z_B/(ZWZ/AZ))*AST_E+ #end AST_E*ZW_L*(1-AST_VJ))/AST_L*BH) #declare B=1; #while (B<100) sphere { <0,0,0>,TRUNK_RADIUS*5,TRUNK_RADIUS*10 scale TRUNK_RADIUS/90 scale ((Z_A+Z_B+ZW_L*(1-AST_VJ))-A*AST_VJ*AST_L/BH)/(Z_A+Z_B+ZW_L*(1-AST_VJ)) scale <1,1,1>+(1-BPTo*A/(Z_A+Z_B+ZL))*<-BARK_PROFILE*.9,BARK_PROFILE*.25,BARK_PROFILE*.25>*BRANCH_BARK_PROFILE_CHANGE scale (BH-AA*ST_VJ)/BH scale (BH-((AB)*(B/100))*ST_VJ)/BH scale 1/(AST_L/BH) scale AST_ST #if (A>Z_A/AST_L*BH & Z_B>=1 & AST_E=0) scale (1-BEE*((A-Z_A/AST_L*BH)/( #if (ZWZ/AZ>1) ((ZWZ/AZ-1)/(ZWZ/AZ))* #end (Z_B/AST_L*BH)))*(1-ZW_VST)) #else scale 1 #end rotate <0,12347.3*sin(3.77*A*A*pi),0> translate *((BH-A)/BH)*(1-B/100*A_STR) translate *((BH-A)/BH)*<1,A_L_W,H_AW_S>*(1-B/100*A_STR) translate *<-1,1,H_ABG_S>*<1-B/100*A_STR,1,1-B/100*A_STR> rotate <0,BRANCH_SPIRAL*sin(A/BH*(pi/2)),0> rotate <0,1234*sin(4.77*B*pi),0>*AST_DREH rotate <0,0,-90> scale (AST_L/BH)*(1-B/100*AST_VK) rotate <0,0,ASTNEIGUNG+((B/100)*((90-ASTNEIGUNG)))*A_NEIG>+<0,0,A_N_SP*sin(9.77*B*B*pi)> rotate <0,1456*cos(AST_SPIEL*7.19*B*pi)*(1-A_W_S)+90*A_W_S*sin((B/(100/AZ)-1/(100/AZ))*pi-pi/2)+90,0> translate *((BH-(AA+(B*AB/100)))/BH) translate *((BH-(AA+(B*AB/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((AA+(B*AB/100))/(BH*3/5)),0> } #declare B=B+100/AZ; #end #declare A=A+BH/BRANCH_STRENGTH/300; #end #end #end #if (TWIG_STRENGTH>0) #if (AZ>=1) #if (ZWZ>=1) #declare A=1; #while (A1) ((SZ/ZWZ-1)/(SZ/ZWZ))* #end B_A_T #if (SZ/ZWZ>1) +(B_A_T/(SZ/ZWZ))*ZE #end +ZE*(S_MA_R+S_MI_R)*(1-S_VJ_Z))/ZW_L*BH) sphere { <0,0,0>,TRUNK_RADIUS*5,TRUNK_RADIUS*10 scale TRUNK_RADIUS/90 scale ((S_A+B_A_T+(S_MA_R+S_MI_R)*(1-S_VJ_Z))-C*TT*ZW_L/BH)/((S_A+B_A_T+(S_MA_R+S_MI_R)*(1-S_VJ_Z))) scale (BH-((AB)*(B/100))*ST_VJ)/BH scale (BH-AA*ST_VJ)/BH scale BH/AST_L scale AST_L/ZW_L scale ZW_VST*AST_ST translate *((BH-C)/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *((BH-C)/BH)*ZW_K_A*(1-B/100*A_STR)*(1-A/BH*T_STR) translate *<1,1,H_ABG_S>**<1-B/100*A_STR,1,1-B/100*A_STR>*<(1-A/BH*T_STR),1,(1-A/BH*T_STR)> rotate <0,BRANCH_SPIRAL*sin(C/BH*(pi/2)),0> scale ((Z_A+Z_B+ZW_L*(1-AST_VJ))-Z_A*AST_VJ*AST_L/BH)/(Z_A+Z_B+ZW_L*(1-AST_VJ)) scale ((Z_B+ZW_L*(1-AST_VJ))-A*AST_VJ*Z_B/BH)/(Z_B+ZW_L*(1-AST_VJ)) rotate <0,1234*sin(4.77*A*pi),0>*ZW_DREH rotate <0,0,-90> scale ZW_L/BH scale BH/AST_L rotate <0,0,V_ZW_N_SP*sin(9.77*A*A*pi)>+<0,0,(V_ZW_N-(V_ZW_N*(A*A)/(BH*BH)*V_ZW_NEIG))> rotate <0,H_ZW_N_SP*sin(7.77*A*A*pi),0>+<0,(H_ZW_N-(H_ZW_N*(A*A)/(BH*BH)*ZW_NEIG)),0>*((1-ZW_W_S)+(ZW_W_S*sin((A/(BH/ZWZ*AZ)-1/(BH/ZWZ*AZ))*pi-pi/2))) rotate <1456*cos(AST_SPIEL*7.19*A*pi)*(1-ZW_W_S),0,0> rotate <0,0,90> rotate <0,1234*sin(ZW_SPIEL*4.77*B*pi),0>*(1-ZW_W_S) rotate <0,-1234*sin(4.77*B*pi),0>*AST_DREH translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*(1-B/100*A_STR) translate *((BH-(Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH)))/BH)*<1,A_L_W,H_AW_S>*(1-B/100*A_STR) translate *<-1,1,H_ABG_S>*<1-B/100*A_STR,1,1-B/100*A_STR> rotate <0,BRANCH_SPIRAL*sin((Z_A/AST_L*BH+(A*(Z_B/AST_L*BH)/BH))/BH*(pi/2)),0> rotate <0,1234*sin(4.77*B*pi),0>*AST_DREH rotate <0,0,-90> scale (AST_L/BH)*(1-B/100*AST_VK) rotate <0,0,ASTNEIGUNG+((B/100)*((90-ASTNEIGUNG)))*A_NEIG>+<0,0,A_N_SP*sin(9.77*B*B*pi)> rotate <0,1456*cos(AST_SPIEL*7.19*B*pi)*(1-A_W_S)+90*A_W_S*sin((B/(100/AZ)-1/(100/AZ))*pi-pi/2)+90,0> translate *((BH-(AA+(B*AB/100)))/BH) translate *((BH-(AA+(B*AB/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((AA+(B*AB/100))/(BH*3/5)),0> } #declare C=C+BH/200/TWIG_STRENGTH; #end #declare B=B+100/AZ; #end #declare A=A+BH/ZWZ*AZ; #end #end #end #end #if (ROOT_STRENGTH>0) #if (ROOTS>=1) #declare A=1; #while (A,TRUNK_RADIUS*5,TRUNK_RADIUS*10 scale (BH-A)/BH scale TRUNK_RADIUS/90 scale W_ST scale BH/W_L scale <1,1,1>+<-BARK_PROFILE*.9,BARK_PROFILE*.25,BARK_PROFILE*.25>*ROOT_BARK_PROFILE_CHANGE rotate <0,12347.3*sin(3.77*A*pi),0> translate *((BH-A)/BH) translate *((BH-A)/BH) translate rotate <0,1234.773*sin(4.77*B*pi),0>*W_DREH rotate <0,0,-90> rotate <0,180,0> scale W_L/BH rotate <0,0,ROOT_ANGLE+((B/100)*R_A*((90-ROOT_ANGLE)))> rotate <0,1456.371*sin(ROOT_RANDOM*71.19*B*pi)+180,0> translate *((BH-(WA-(WA*B/100)))/BH) translate *((BH-(WA-(WA*B/100)))/BH) translate rotate <0,TRUNK_SPIRAL*sin((WA-(WA*B/100))/(BH*3/5)),0> } #declare B=B+100/ROOTS; #end #declare A=A+BH/150/ROOT_STRENGTH; #end #end #end } texture { #if (H_B_T>0) onion texture_map { [0 RINDE scale 1/()] [H_B_T #if (FCaBE=1) RINDE1 #else RINDE #end scale .3/()] [1 #if (FCaBE=1) LAUB #else RINDE #end scale .1/()] } scale translate <0,0,0> #else RINDE #end } scale 1/UNIT_1 } //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX END //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXtkgate-2.0-b10/povray/TREE.pov000644 001751 001751 00000003010 07065624772 016624 0ustar00hansenhansen000000 000000 // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Persistence of Vision 3.1 Scene Description File // File: TREE.pov // Desc: TREEGENERATOR EXAMPLE SCENE FILE // Date: MARCH 2000 // Auth: AUST // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //**********************************************GLOBAL SETTINGS #default{texture{pigment{color rgb <1,1,1>}finish{ambient 0.0}}} sky_sphere{pigment{color rgb 1}} //*****************************************************INCLUDES //*****************************************************TEXTURES //*******************************************************BLOCKS //*******************************************************CAMERA camera { direction 1.5*z right 1*x location <0,500,-1700> look_at <0,500,0> } //********************************************************LIGHT light_source { <0,500,-1000> color rgb <.3,.25,.2> shadowless } light_source { <100000,180000,-100000> color rgb <2,2,2> } //***************************************************ATMOSPHERE //************************************************************* //************************************************************* //*******************************************************ACTION #include "PALM.inc" #include "TOMTREE.inc" object { TREE scale 1000 } //**********************************************************END //************************************************************* tkgate-2.0-b10/povray/chip.pov000644 001751 001751 00000000665 11141644667 017020 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "chip.inc" object { Chip } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.0, 0.0, -2.5> look_at <0.0, 0.0, 0.0> } light_source { <-30.0, 30.0, -15> colour White *5 } tkgate-2.0-b10/povray/colorprops.pov000644 001751 001751 00000002447 10076274132 020267 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #declare Paint_Finish = finish { specular 0.5 reflection 0.2 } #macro ColorDab(X,Y,C) sphere { <0,0,0>, PR scale <1,PH,1> translate texture { pigment { rgb C } finish { Paint_Finish } } } #end #declare Palate = union { #local W = 0.75; #local H = 1.0; #local D = 0.05; #local T = 0.1; #local PR = 0.15; #local PH = 0.2; intersection { cylinder { -D*y, 0*y, 1 scale } cylinder { -1*y, 1*y, 0.15 translate -0.7*z inverse } texture { T_Wood8 } } ColorDab(0.0, -0.1, <1,0,0>) ColorDab(0.3,0.1, <0,1,0>) ColorDab(-0.3,0.1, <0,0,1>) ColorDab(-0.4,-0.3, <0,0,0>) ColorDab(0.4,-0.3, <1,1,1>) ColorDab(-0.3,0.4, <0,1,1>) ColorDab(0.32,0.45, <1,0,1>) ColorDab(0.05,0.6, <1,1,0>) rotate x*-40 rotate y*20 rotate z*-30 } object { Palate } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.0, 0.0, -3> look_at <0.0, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *5 } tkgate-2.0-b10/povray/dragon.inc000644 001751 001751 00000071625 10662115776 017321 0ustar00hansenhansen000000 000000 // Dragon // by Jeffery P. Hansen // #include "glass.inc" #declare ShowHead = 1; #declare ShowWings = 1; #declare ShowBody = 1; #declare ShowLegs = 1; #declare ShowFrills = 1; #declare ShowGem = 1; #declare DrBodyR = 1.5; #declare DrBodyStart = -3; #declare DrBodyEnd = 3; #declare DrToe1Len = 1; #declare DrToe2Len = 0.8; #declare DrToeR = 0.35; #declare DrToeA1 = 20; #declare DrToeA2 = -40; #declare DrThumb1Len = 0.4; #declare DrThumb2Len = 0.4; #declare DrThumbR = 0.4; #declare DrThumbA1 = 5; #declare DrThumbA2 = -20; #declare DrClawStart = 0; #declare DrClawEnd = 1; #declare DrClawR = 0.2; #declare Pi = 3.1415926; // This can go in a "normal" // // slope_map { // [0 <0, 1>] // start at bottom and slope up // [0.5 <1, 1>] // halfway through reach top still climbing // [0.5 <1,-1>] // abruptly slope down // [1 <0,-1>] // finish on down slope at bottom // } #declare Gem_Texture = texture { NBglass pigment { rgbf <0.1, 1, 1, 0.9> } } #declare ClawText = texture { pigment { color Silver } normal { crackle 0.2 scale 0.2 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .2 } } #declare ChestPlate_Text = texture { pigment { rgb <.7,.7,.2> } normal { crackle 0.7 scale 0.5 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection 0.5 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } /* pigment { wrinkles scale 1 turbulence 1 color_map { [0.0 rgb <1,0,0>] [0.1 rgb <1,0,0>] [0.2 rgb <1,1,0>] [0.4 rgb <0,1,0>] [0.6 rgb <0,1,1>] [0.8 rgb <0,0,1>] } } */ normal { // crackle 0.7 crackle 0.1 scale 0.5 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare NostrilInsides = texture { pigment { rgb <.2,0,0> } normal { crackle 0.7 scale 0.5 } finish { specular 0 roughness 0.1 ambient 0.0 diffuse 0.1 } } #declare DragonWingText = texture { pigment { wrinkles scale .1 color_map { [0 rgbf <.8,.2,.2,.7>] [0.35 rgbf <.8,.2,.2,.7>] [0.75 rgbf <.1,.1,.1,.7>] } } // normal { // agate 5 // scale 2 // scale 0.05 // } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 // reflection 0.6 reflection 1 } } #declare DragonFrillText = texture { #local F = 0.1; pigment { wrinkles scale .1 turbulence 0.1 color_map { [0 rgbf <.4,.4,.6,F>] [0.1 rgbf <1,1,0,F>] [0.6 rgbf <1,0,0,F>] } } // normal { // agate 5 // scale 2 // scale 0.05 // } finish { // metallic // specular .05 // roughness 0.1 ambient 1 diffuse 0.5 reflection 0.1 } } #declare XDragonWingText = texture { pigment { rgbf <.8,.2,.2,.3> } normal { bozo 2 scale 0.05 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection 0.2 } } #declare DragonWingRibText = texture { pigment { rgb <.5,0,0> } normal { crackle 0.2 scale 0.01 } finish { ambient 0.2 diffuse 0.4 specular .1 reflection .1 } } #declare PlateText = texture { pigment { rgb <.4,0,0> } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare ToothText = texture { pigment { rgb <1,1,0.7> } finish { specular 0.1 ambient 0.5 diffuse 0.5 } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1.0; #local L1 = 4; // Thigh length #local L2 = 3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.5)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.8)*x translate -(1-FS)*y texture { PlateText } } translate DrBodyR*z } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,2,1.2,1.0,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,2,1,0.8,0.85) #end #declare DragonPlate = union { #local H = sqrt(0.75); #local R1 = 0.3; #local R2 = 0.15; intersection { box { <-0.5,0,-0.05>, <0.5,2,0.05> } plane {x, 0 inverse rotate -30*z translate -0.5*x } plane {x, 0 rotate 30*z translate 0.5*x } } difference { cylinder { -0.05*z, 0.05*z, R1 translate (H+R1-0.05)*y } cylinder { -0.06*z, 0.06*z, R2 translate(H+R1-0.05)*y } } texture { PlateText } } #macro DragonPlateSet() union { // // Body plates // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #declare S = 5.0; #while (X < DrBodyEnd) object { DragonPlate transform T translate BS*(DrBodyR*cos(X/6)-.2)*y } #declare i = 0; #while(i < (S + 0.01)) #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #declare X = X + 0.2; #declare i = i + 1; #end #end // // Tail plates // #declare TRStart = DrBodyR*cos(DrBodyStart/6); #declare TailRadius = TRStart; #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > .2) #declare PS = (TailRadius+2*TRStart)/(3*TRStart); object { DragonPlate scale PS transform T translate (BS*TailRadius-0.2)*y } #declare i = 0; #while(i < (S+0.01)) #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #declare i = i + 1; #end #end // // Neck plates // #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) #declare PS = (NeckRadius+3*TRStart)/(4*TRStart); object { DragonPlate scale PS transform T translate BS*(NeckRadius-0.2)*y } #declare i = 0; #while(i < (S+0.01)) #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #declare i = i + 1; #end #end } #end #macro MainBodyBlob() blob { threshold 0.05 // // Main body // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #while (X < DrBodyEnd) cylinder { 0*x, 0.1*x, DrBodyR*cos(X/6),1 scale <1,BS,1> transform T } #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #if (X < DrBodyEnd*0.5) #declare Twings = transform { transform T} #end #declare X = X + 0.2; #end #declare Tlegs = transform { transform T} // // Tail // #declare TailRadius = DrBodyR*cos(DrBodyStart/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > 0) cylinder { 0*x, 0.1*x, TailRadius,1 scale <1,BS,1> transform T } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #end // Neck #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) cylinder { 0*x, 0.1*x, NeckRadius,1 scale <1,BS,1> transform T } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #end #declare Thead = transform { transform T} texture { DragonHide } } #end #macro BodyChestPlates() union { #local PlateS = 0.85; #local PlateDY = -(1-PlateS); // // Main body // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #while (X < DrBodyEnd) cylinder { 0*x, 0.2*x, DrBodyR*cos(X/6) scale transform T translate PlateDY*y} #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #if (X < DrBodyEnd*0.5) #declare Twings = transform { transform T} #end #declare X = X + 0.2; #end #declare Tlegs = transform { transform T} // // Tail // #declare TailRadius = DrBodyR*cos(DrBodyStart/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > 0) cylinder { 0*x, 0.2*x, TailRadius scale transform T translate PlateDY*y } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #end // Neck #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) cylinder { 0*x, 0.2*x, NeckRadius scale transform T translate PlateDY*y } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #end #declare Thead = transform { transform T} texture { ChestPlate_Text } } #end // // Put the pieces of the dragon body together here. The local variables are // visible within the macros. // #macro DragonBody(N) union { #local BS = 1.5; #switch (N) #case(1) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.085; #local NeckVertStart = 0; #local NeckVertDD = 0.09; #local TailDDY = 0.08; #local TailDDZ = -0.09; #break #case(2) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.085; #local NeckVertStart = 0; #local NeckVertDD = 0.05; #local TailDDY = -0.04; #local TailDDZ = -0.09; #break #case(3) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.00; #local NeckVertStart = 0; #local NeckVertDD = 0.0; #local TailDDY = 0.08; #local TailDDZ = -0.09; #end MainBodyBlob() DragonPlateSet() BodyChestPlates() } #end #declare XMark = union { #local Q=0.02; #local L=1; box { <-L,-Q,-Q>, } box { <-Q,-L,-Q>, } box { <-Q,-Q,-L>, } } #declare Tooth = mesh { triangle { <-1,0,0>, <0,0,-1>, <0,1,0> } triangle { <-1,0,0>, <0,0,1>, <0,1,0> } triangle { <1,0,0>, <0,0,-1>, <0,1,0> } triangle { <1,0,0>, <0,0,1>, <0,1,0> } scale <0.06,0.3,0.1> texture { ToothText } } #macro UpperTeeth(ToothLen) union { #local FrontS = 0.6; #local A = 14; #local W1 = 0.98; #local W2 = 0.92; #local W3 = 0.82; #local X = 1.3; #while (X < ToothLen) object { Tooth rotate 90*y scale <0.8,-0.8,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,-0.8,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.2; #end object { Tooth rotate 90*y scale <0.8,-1.1,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,-1.1,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.1; object { Tooth rotate 90*y scale rotate 32*y translate X*x rotate A*y translate W2*z } object { Tooth rotate 90*y scale rotate -32*y translate X*x rotate -A*y translate -W2*z } #local X = X + 0.05; object { Tooth scale translate X*x rotate A*y translate W3*z } object { Tooth rotate 90*y scale rotate 92*y translate X*x rotate -A*y translate -W3*z } translate (HeadH*0.3+0.1)*y } #end #macro LowerTeeth(ToothStart,ToothLen) union { #local FrontS = 0.6; #local A = 13; #local W1 = 0.73; #local W2 = 0.62; #local W3 = 0.52; #local X = ToothStart; #while (X < ToothLen) object { Tooth rotate 90*y scale <0.8,0.8,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,0.8,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.2; #end object { Tooth rotate 90*y scale <0.8,1.1,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,1.1,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.15; object { Tooth rotate 90*y scale rotate 32*y translate X*x rotate A*y translate W2*z } object { Tooth rotate 90*y scale rotate -32*y translate X*x rotate -A*y translate -W2*z } #local X = X + 0.1; object { Tooth scale translate X*x rotate A*y translate W3*z } object { Tooth rotate 90*y scale rotate 92*y translate X*x rotate -A*y translate -W3*z } } #end #macro DragonJaw(A,JawStart,JawEnd,JawTop) object { #local X0 = JawStart/2; #local Y0 = JawTop*1.5; #local X1 = JawStart/2; #local Y1 = -JawTop*0.5; #local L = JawEnd-JawStart; #local JW = 0.7; #local JR = 0.6; #local JY = -Y1 - 0.1; #local JSY = 1; #local JSX = 0.8; #local JSZ = 0.35; #local JZR = 30; union { intersection { union { intersection { union { intersection { sphere { <0,0,0>, 1 scale translate } plane { z, 0 rotate 13*y translate 0.8*z } plane { z, 0 inverse rotate -13*y translate -0.8*z } plane { x, 0 inverse } plane { y, 0 } } // Under jaw balls sphere { <0,0,-0.3>, 0.5 } sphere { <0,0,0.3>, 0.5 } // Jaw sides sphere { <0,0,0>, 1 scale rotate -10*y translate } sphere { <0,0,0>, 1 scale rotate 10*y translate } } plane { y, 0 } } union { cylinder { -JW*z, JW*z, JR scale translate <-X1, JY, 0> } sphere { <0,0,0>, JR scale translate <-X1, JY, -JW> } sphere { <0,0,0>, JR scale translate <-X1, JY, JW> } rotate JZR*z } } // Mouth insides #local MD = 0.48; cone { , 0.3, <0,0,0>, 0.65 inverse scale <1,MD,1> } cylinder { 0.01*x, -2*x, 0.65 inverse scale <1,MD,1> } sphere { , 0.3 scale <1,MD,1> inverse } box { <-2,0,-0.65>, <0,2,0.65> inverse } } object { LowerTeeth(0,L-0.2) } translate } translate rotate -A*z } #end // // Basic arc (actually a ring) that is used as parts of the OR gate. // #macro DrGateArc(RT) difference { object { cylinder { 0.0*z, RT*z, 0.5+RT } } object { cylinder { z, -z, 0.5 } } } #end #macro XOrGateLine(RT,TT) union { intersection { box { <-2,0,-TT>, <0.7,0.5,TT> } plane { x, 0 rotate -60*z translate 0.3*x } plane { x, 0 rotate 55*z translate <0.3,0.5+2*RT,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <-0.5-RT,0.5/2+RT/2,0> } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.6-RT,0.5/2+RT/2,0> } texture { DragonFrillText } } intersection { box { <-2,0,-TT/2>, <0.7,0.5,TT/2> } plane { x, 0 rotate -60*z translate 0.3*x } plane { x, 0 rotate 55*z translate <0.3,0.5+2*RT,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <-0.39-RT,0.5/2+RT/2,0> } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.51-RT,0.5/2+RT/2,0> } texture { NBglass } } } #end #macro OrGateWingSurface(RT,TT) intersection { union { box { <0,RT/2,-TT>, <0.25,0.5+RT/2,TT> } intersection { box { <0,RT/2,-TT>, <0.7,0.5+RT/2,TT> } object { cylinder { 0.0*z, RT*z, 0.5+RT/2 } translate <0.25,0,-RT/2> } object { cylinder { 0.0*z, RT*z, 0.5+RT/2 } translate <0.25,0.5+RT,-RT/2> } } } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.4-RT,0.5/2+RT/2,0> } } #end #macro DrOrBack(RT) intersection { #local W = 0.5 + RT; object { DrGateArc(RT) } plane {x, 0 inverse } plane {y, -W/2 inverse } plane {y, W/2 } translate <-(0.5-RT*1.5),W/2,-RT/2> } #end #macro OrGateWingRibs(RT,doBack,doFront) union { box { <0,0.5,-RT/2>, <0.25,0.5+RT,RT/2> } box { <0,0.0,-RT/2>, <0.25,RT,RT/2> } // // The back of the OR gate // #if (doBack) object { DrOrBack(RT) } #end // // Top-half of OR curve. // intersection { intersection { object { DrGateArc(RT) } plane {x, 0 inverse } translate <0.25,0,-RT/2> } plane {y, 0.5/2 + RT/2 inverse } #if (!doFront) plane {x, 0.4 } #end } // // Bottom-half of OR curve. // intersection { intersection { object { DrGateArc(RT) } plane {x, 0 inverse } translate <0.25,0.5+RT,-RT/2> } plane {y, 0.5/2 + RT/2 } #if (!doFront) plane {x, 0.4 } #end } texture { DragonWingRibText } } #end #macro OrGateFrill() union { #local RT = 0.03; #local TT = 0.001; object { OrGateWingRibs(RT,0,1) } object { OrGateWingSurface(RT,TT) texture { DragonFrillText } } translate <-0.75,-0.25,0> } #end #macro XOrGateFrill() union { #local RT = 0.03; #local TT = 0.001; XOrGateLine(RT,TT) object { OrGateWingRibs(RT,0,1) } object { OrGateWingSurface(RT,TT) texture { DragonFrillText } } translate <-0.75,-0.25,0> } #end // // One section of the wing // #macro OrGateWingElement(RT,TT) union { object { OrGateWingRibs(RT,1,0) } object { OrGateWingSurface(RT,TT) texture { DragonWingText } } } #end // // A complete wing // #declare DragonWing = union { #local RT = 0.03; #local TT = 0.001; object { OrGateWingElement(RT,TT) } object { OrGateWingElement(RT,TT) translate (0.5)*y } object { OrGateWingElement(RT,TT) translate (1)*y } rotate 90*x #if (1) rotate 180*z #else translate -0.5*x #end scale 8 } #declare Eye = object { #local C1 = 0.16; #local C2 = 0.195; sphere { <0,0,0>, 0.2 } texture { pigment { gradient x color_map { [0 rgb <1,1,0.6>] // Milky white [C1 rgb <1,1,0.6>] // Milky white [C1 rgb <0.05,0.3,0.05>] [C2 rgb <0.05,0.3,0.05>] [C2 rgb <0,0,0>] [1 rgb <0,0,0>] // Black } } finish { specular 0.1 reflection 0.3 ambient 0.5 } } } #macro XYCord(X1,Y1,X2,Y2,S) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/Pi; object { cylinder { 0*x, D*x, S } rotate R*z translate } #end #macro DragonHead() union { #local HeadLen = 3; #local Hbase = 1; #local HeadW = 2; #local HeadH = 2; #local MouthRoof = (HeadH*0.3+0.1); #local EA = 35; #local NX = HeadLen-0.05; #local NY = 1.2; #local NZ = 0.15; #if (1) intersection { union { intersection { box { <0,0,-HeadW/2>, } // Side angles plane { z, 0 rotate 12*y rotate -5*x translate Hbase*z } plane { z, 0 inverse rotate 5*x rotate -12*y translate -Hbase*z } // Nose and back of head angle plane { y, 0 rotate -15*z translate HeadH*y } plane { y, 0 rotate 15*z translate (HeadH-0.4)*y } object { cylinder { -2*x, 4*x, 1 } rotate -15*z translate 0.9*y } } // // Eye ovals // sphere { <0,0, 0>, 1 scale <1,0.7,0.35> rotate -20*z rotate -EA*y translate <1.1, 1.2, -0.3> } sphere { <0,0, 0>, 1 scale <1,0.7,0.35> rotate -20*z rotate EA*y translate <1.1, 1.2, 0.3> } // // Middle nose ridges // sphere { <0,0,-0.9>, 1 scale <1.6,0.55,0.2> rotate -5*y translate <1.15,1.0,0> } sphere { <0,0, 0.9>, 1 scale <1.6,0.55,0.2> rotate 5*y translate <1.15,1.0,0> } // // Edge nose ridges // sphere { <0,0,0>, 1 scale <1.8,0.6,0.2> rotate -12*y translate <1.35,0.9,-0.6> } sphere { <0,0,0>, 1 scale <1.8,0.6,0.2> rotate 12*y translate <1.35,0.9,0.6> } // // Nose blob // blob { threshold 0.05 sphere { , 0.2, 1 } sphere { , 0.2, 1 } cylinder { 0*y, NY*y, 0.18,1 translate } cylinder { 0*y, NY*y, 0.18,1 translate } } } // // Eye socket cutouts // sphere { <0,0,0>, 1 inverse scale <0.5,0.2,0.2> rotate -20*z rotate -EA*y translate <1.1, 1.6, -0.5> } sphere { <0,0,0>, 1 inverse scale <0.5,0.2,0.2> rotate -20*z rotate EA*y translate <1.1, 1.6, 0.5> } // // Nostril cutouts // union { cylinder { -0.08*x, 1*x, 0.05 scale <1,1,1> } box { <-0.15,-0.05,-0.05>, <1,0.0,0.05> } inverse scale 1.5 rotate <-1,0,5> translate texture { NostrilInsides } } union { cylinder { -0.08*x, 1*x, 0.05 scale <1,1,1> } box { <-0.15,-0.05,-0.05>, <1,0.0,0.05> } inverse scale 1.5 rotate <1,0,5> translate texture { NostrilInsides } } // Mouth cut-out union { plane { y, MouthRoof inverse } plane { x, HeadLen/3 } } // // Mouth cavity cutout // cone { <-5,0,0>, 1.4, <0,0,0>, 0.2 inverse scale <1,0.7,1> translate(HeadLen-0.3)*x translate MouthRoof*y } sphere { <0,0,0>, 0.2 inverse translate(HeadLen-0.3)*x translate MouthRoof*y } // // Back of head plane // plane { x, 0 inverse } } // // Upper teeth // UpperTeeth(HeadLen-0.2) #if (ShowFrills) object { OrGateFrill() scale 2 rotate -60*y translate <0.3,1.2,-0.7> } object { OrGateFrill() scale 2 rotate 60*y translate <0.3,1.2,0.7> } object { XOrGateFrill() scale 2 rotate -60*y rotate 60*x translate <0.3,1.6,-0.5> } object { XOrGateFrill() scale 2 rotate 60*y rotate -60*x translate <0.3,1.6,0.5> } #end object { Eye translate <0.7, 1.6, -0.55> } object { Eye translate <0.7, 1.6, 0.55> } #end sphere { <0,0.5,0>, 1 } object { DragonJaw(20,HeadLen/3,HeadLen-0.3,MouthRoof) } texture { DragonHide } } #end #macro GemCut(TT) intersection { #local CutD = TT*0.7; #local A = 30; plane { y,0 rotate -A*x translate <0,0,-(TT-CutD)> } plane { y,0 rotate -2*A*x translate <0,-CutD,-TT> } plane { y,0 rotate A*x translate <0,0,(TT-CutD)> } plane { y,0 rotate 2*A*x translate <0,-CutD,TT> } } #end #macro GemHalfCut(TT) intersection { #local CutD = TT*0.7; #local A = 30; plane { y,0 rotate -A*x translate <0,0,CutD> } plane { y,0 rotate -2*A*x translate <0,-CutD,0> } } #end #declare GateGem = intersection { #local TT = 0.1; #local X0 = -0.45; #local R = 0.25; #local A = 30; #local CutD = 0.08; merge { box { , <0,R,TT> } cylinder { -TT*z, TT*z, R } } object { GemCut(TT) translate R*y } object { GemCut(TT) scale <1,-1,1> translate -R*y } object { GemCut(TT) rotate 90*z translate X0*x } object { GemHalfCut(TT) rotate 90*y translate } object { GemHalfCut(TT) scale <1,-1,1> rotate 90*y translate } #local Th = 60; #while (Th > -90) #local X = R*cos(Th*Pi/180); #local Y = R*sin(Th*Pi/180); object { GemCut(TT) rotate (Th-90)*z translate } #local Th = Th - 30; #end // plane { y,0 rotate A*z translate } // plane { y,0 rotate 2*A*z translate } // plane { y,0 inverse rotate -A*z translate } // plane { y,0 inverse rotate -2*A*z translate } scale 3 interior { ior 1.5 } texture { Gem_Texture } } #macro Dragon(N) union { #switch(N) #case(1) #local WingAngle = 40; #break #case(2) #local WingAngle = 55; #break #case(3) #local WingAngle = 40; #end #if (ShowBody) object { DragonBody(N) } #end #if (ShowLegs) #switch(N) // Left dragon #case(1) object { DragonFrontLeg(45,100) transform Tlegs } object { DragonFrontLeg(65,130) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(45,100) translate DrBodyStart*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate DrBodyStart*x } #break #case(2) object { DragonFrontLeg(45,108) transform Tlegs } object { DragonFrontLeg(65,130) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(45,108) translate DrBodyStart*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate DrBodyStart*x } #break #case(3) object { DragonFrontLeg(70,160) transform Tlegs } object { DragonFrontLeg(70,160) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(70,160) translate DrBodyStart*x } object { DragonBackLeg(70,160) scale <1,1,-1> translate DrBodyStart*x } #end #end #if (ShowWings) object { DragonWing scale <1,1,-1> transform Twings translate -1.5*z rotate WingAngle*x rotate -10*y} object { DragonWing scale <1,1,-1> transform Twings translate -1.5*z rotate WingAngle*x rotate -10*y scale <1,1,-1> } #end #if (ShowHead) object { DragonHead() scale 0.8 translate -0.5*y #switch(N) #case(1) rotate -70*z #break #case(2) rotate -50*z #break #case(3) rotate -0*z #end transform Thead } #end #if (ShowGem) #if (N != 3) object { GateGem translate <2.2,-4.2,-2.7> } #end #end translate 0.1*y } #end tkgate-2.0-b10/povray/dragongate.pov000644 001751 001751 00000057565 10345327432 020214 0ustar00hansenhansen000000 000000 // Gate scene with dragon // by Jeffery P. Hansen // // For full picture use // povray +SR230 +ER500 +W960 +H720 +A +D +P +i dragongate.pov // // For foot adjustment use: // povray +SR430 +ER500 +SC125 +EC350 +W960 +H720 +A +D +P +i dragongate.pov // #declare showTrees = 0; #declare showPosts = 1; #declare showFence = 1; #declare showDragons = 1; #declare showSign = 1; #declare showCacti = 1; #declare DGView = 1; /* 1 = regular view 2 = left dragon feet 3 = right dragon feet 4 = cactus view 5 = closeup? 6 = sign closeup 7 = gate closeup */ #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #if (showTrees) #include "OLIVE.inc" #include "TOMTREE.inc" #end #include "dragon.inc" #declare cactusRand = seed(42); #declare PostRadius = 0.35; // Radius of posts #declare AngleStart = 9; // Start angle of TkGate text #declare AngleSpan = 21.0; // Number of degrees though which to position text #declare AngleStep = -(AngleSpan/8.0); // Number of degrees per letter // // A texture for wrought iron. // #declare Wrought_Iron = texture { pigment { granite color_map { [0.0 1.0 colour red 0.2 green 0.2 blue 0.2 colour red 0.0 green 0.0 blue 0.0] } } finish { ambient 0 diffuse 0.6 metallic 1} normal { wrinkles 1 scale 0.11 } } #declare Cactus_Text = texture { pigment { rgb <.1,.57,.1> } normal { leopard 0.1 turbulence .1 scale <0.005,0.05,0.005> } finish { ambient 0.3 diffuse 0.6 } } #declare CactusSpine_Text = texture { pigment { rgb <.9,.9,.1> } finish { ambient 0.3 diffuse 0.6 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{White} normal{ granite 0.075 scale 0.24 } finish{phong 0.1 phong_size 200 diffuse 0.2 ambient 0.5 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } // // The ground // #declare SandDunes = intersection { // plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 0.2 diffuse 0.6 } } #declare OldGrassTexture = texture { pigment { bozo turbulence 0.1 colour_map { [0.0 1.0 colour red 0.2 green 1.0 blue 0.2 filter 0 colour red 0.2 green 0.8 blue 0.2 filter 0] } } normal{ wrinkles 0.1 scale 0.24 } finish { ambient 0.2 diffuse 0.2 } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare XGrassHill = union { // height_field { // png "hills2.png" // smooth // translate -0.5*x // translate 5*z // scale <200,50,200> // } height_field { png "hills2.png" smooth translate -0.5*x scale <50,3,50> } intersection { plane { y, 0 } plane { z, 0 inverse } } hollow on // texture { GrassTexture } texture { pigment { checker color Red, color Green } } } #declare GateGround = union { object { SandDunes } object { GrassHill } } #declare CowOrFlat=0.5; #declare CowHeight=1.1; #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } finish { ambient 0.2 } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare AndGateCow = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } texture { Cow_Texture } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } #declare OrGateCow = union { intersection { box { <0.0,0.0,0.0>, } object { cylinder { -2*z, 2*z, CowHeight inverse } translate <-CowHeight*0.85,CowHeight/2,0> } translate CowLegLength*y } intersection { object { cylinder { 0*z, CowThickness*z, CowHeight } translate } object { cylinder { -2*z, 2*z, CowHeight } translate } plane { x, 0.5 inverse } translate CowLegLength*y } object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } texture { Cow_Texture translate 10*x } } // // Define the posts that go on the sides of the gate. // #declare Post = union { // cylinder { 0*y, 4.25*y, PostRadius } intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 4.25*y } object { sphere { <0,0,0>, PostRadius } translate 4.75*y } // texture { White_Marble } texture { Post_Stone } // texture { PinkAlabaster } } // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, 0.05 } } merge { object { Sphere scale <0.05, 0.05, 0.05> translate 0.1*y } object { Cone_Y scale <0.05, 0.1, 0.05> translate 0.2*y } object { Cone_Y scale <0.05, 0.05, 0.05> translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 4.0*y, 0.05 } } merge { object { Sphere scale <0.05, 0.05, 0.05> translate 0.1*y } object { Cone_Y scale <0.05, 0.1, 0.05> translate 0.2*y } object { Cone_Y scale <0.05, 0.05, 0.05> translate 0.025*y } translate 4.0*y } } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare DoorBase = union { Spike(1.7) Spike(1.4) Spike(1.1) Spike(0.8) Spike(0.5) Spike(0.2) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <50.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <50.0,0.55,0.05> } translate 3.3*y } // // Fence // #local i = 0; #while (i < 60) object { FenceSpike translate (2.6+0.4*i)*x } #local i = i + 1; #end } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } // // This is the lettering in the logo. // #declare Lettering = intersection { union { union { object { char_T translate -2*x translate 88*y rotate (AngleStart+0*AngleStep)*z } object { char_K translate -2*x translate 88*y rotate (AngleStart+1*AngleStep)*z } object { char_G translate -2*x translate 88*y rotate (AngleStart+2*AngleStep)*z } object { char_A translate -2*x translate 88*y rotate (AngleStart+3*AngleStep)*z } object { char_T translate -2*x translate 88*y rotate (AngleStart+4*AngleStep)*z } object { char_E translate -2*x translate 88*y rotate (AngleStart+5*AngleStep)*z } object { char_2 translate -2*x translate 88*y rotate (AngleStart+6.5*AngleStep)*z } object { char_Period translate -2*x translate 88*y rotate (AngleStart+7.25*AngleStep)*z } object { char_0 translate -2*x translate 88*y rotate (AngleStart+8*AngleStep)*z } scale <1.0,1.0,0.5> } intersection { cylinder { 0*z, 0.05*z, 88 } cylinder { -.01*z, 0.06*z, 87 inverse } } intersection { cylinder { 0*z, 0.05*z, 94 } cylinder { -.01*z, 0.06*z, 93 inverse } } translate -90*y scale 0.1 } plane { x, -2 inverse } plane { x, 2 } } #declare LeftDoor = union { intersection { object { DoorBase scale <-1,1,1> } object { FlipFlopCutOutLeft translate <0,0,-0.05> inverse } } object { FlipFlopLeft translate <0,0,-0.05> } translate 1.9*x } #declare RightDoor = union { intersection { object { DoorBase } object { FlipFlopCutOutRight translate <0,0,-0.05> inverse } } object { FlipFlopRight translate <0,0,-0.05> } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.45> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.8,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { object { Lettering translate <0,4,-0.05> } object { Fence } object { Fence scale <-1,1,1> } object { Brackets translate -0.05*z } object { LeftDoor rotate -0*y translate -1.9*x } object { RightDoor rotate 0*y translate 1.9*x } texture { Wrought_Iron } } fog { distance 1500 color rgb<0.3, 0.4, 1.0> fog_type 2 fog_offset 100 fog_alt 1 turbulence 0.1 turb_depth 0.2 } sky_sphere { pigment { gradient y colour_map { // [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 // colour red 0.1 green 0.6 blue 1.0] // [0.0 1.0 colour red 0.4 green 0.4 blue 1.0 // colour red 0.6 green 0.7 blue 1.0] [0.0 1.0 colour red 0.3 green 0.5 blue 0.6 colour red 0.3 green 0.4 blue 1.0 ] // [0.0 1.0 colour red 0.0 green 0.0 blue 0.0 // colour red 0.0 green 0.0 blue 1.0] } scale 0.5 } } #declare BoardWidth=2.8; #declare BoardHeight=0.5; #declare BoardGap = 0.025; #declare Board = difference { box { <0,0,0>, } } #declare SignBase = union { object { Board translate (1.5+0*(BoardHeight+BoardGap))*y } object { Board translate (1.5+1*(BoardHeight+BoardGap))*y } object { Board translate (1.5+2*(BoardHeight+BoardGap))*y } box { <0.0,0,0.12>, <0.1,1.5+3*BoardHeight+2*BoardGap,0.22> } box { , } translate -BoardWidth/2*x //Other possible woods: 18, 19, 20, 29, 30, 31 texture { T_Wood31 scale 0.5 } } #declare CP_X = -BoardWidth/2+0.2; #declare CP_Y = 2.7; #macro newline() #declare CP_X = -BoardWidth/2+0.2; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + 0.22*C; #end #macro putchar(C) object { C scale <0.05,0.05,0.05> translate texture { T_Wood4 } } #declare CP_X = CP_X + 0.22; #end #macro putschar(C) object { C scale <0.04,0.04,0.04> translate texture { T_Wood4 } } #declare CP_X = CP_X + 0.22*0.04/0.05; #end ///////////////////////////////////////////////////////////////////////////// // // Put up the sign base and subtract out all of the letters. // ///////////////////////////////////////////////////////////////////////////// #declare Sign = difference { object { SignBase } //Opening Gates to //Digital Circuit //Simulation putchar(char_T) putschar(char_H) putschar(char_E) kern(0.8) putchar(char_G) putschar(char_A) putschar(char_T) putschar(char_E) putschar(char_W) putschar(char_A) putschar(char_Y) kern(0.8) putchar(char_T) putschar(char_O) newline() putchar(char_D) kern(-.15) putschar(char_I) kern(-.15) putschar(char_G) kern(-.15) putschar(char_I) kern(-.15) putschar(char_T) putschar(char_A) putschar(char_L) kern(0.8) putchar(char_C) kern(-.15) putschar(char_I) kern(-.15) putschar(char_R) putschar(char_C) putschar(char_U) kern(-.15) putschar(char_I) kern(-.15) putschar(char_T) newline() putchar(char_S) kern(-.15) putschar(char_I) kern(-.15) putschar(char_M) putschar(char_U) putschar(char_L) putschar(char_A) putschar(char_T) kern(-.15) putschar(char_I) kern(-.15) putschar(char_O) putschar(char_N) } #declare SpineSet = union { #local SpineR = 0.005; #local SpineLen = 0.1; object { cone { <0,0,0>, SpineR, , 0.0 } rotate 20*z } object { cone { <0,0,0>, SpineR, , 0.0 } rotate -20*z rotate 20*y } object { cone { <0,0,0>, SpineR, , 0.0 } rotate -20*z rotate -20*y } texture { CactusSpine_Text } } #macro SpineRow(X1,X2,Y) union { #local X = X1; #while (X <= X2) object { SpineSet rotate 90*y translate X*x } #local X = X + 0.05; #end translate Y*y } #end #declare CactusAndLeaf = union { #local TT = 0.05; union { box { <-0.35,-0.25,-TT>, <0,0.25,TT> } cylinder { -TT*z, TT*z, 0.25 } translate <-0.25,0,0> } object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.1,0.1) translate -TT*z } object { SpineRow(-0.55,-0.1,-0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,0.2) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.2) translate -TT*z } union { object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.1,0.1) translate -TT*z } object { SpineRow(-0.55,-0.1,-0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,0.2) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.2) translate -TT*z } scale <1,1,-1> } scale 0.9 } #declare CactusOrLeaf = union { #local TT = 0.05; intersection { union { box { <0,0,-TT>, <0.25,0.5,TT> } intersection { box { <0,0,-TT>, <0.7,0.5,TT> } object { cylinder { -1*z, 1*z, 0.5 } translate <0.25,0,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <0.25,0.5,0> } } } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.4,0.25,0> } translate <-.7,-.25,0> } object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.15,0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.1) translate -TT*z } object { SpineRow(-0.6,-0.3,0.2) translate -TT*z } object { SpineRow(-0.6,-0.3,-0.2) translate -TT*z } union { object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.15,0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.1) translate -TT*z } object { SpineRow(-0.6,-0.3,0.2) translate -TT*z } object { SpineRow(-0.6,-0.3,-0.2) translate -TT*z } scale <1,1,-1> } scale 0.9 } #macro Cactus() union { #local CW = 0.2; #local CH = 0.4; sphere { <0,0,0>, CW scale <1,CH/CW,1> } #local RZ1 = 20*(rand(cactusRand)-1)-5; #local RZ2 = 20*(rand(cactusRand)-0); #local RX1 = 20*(rand(cactusRand)-0.5); #local RX2 = 20*(rand(cactusRand)-0.5); #local RY = 60*(rand(cactusRand)-0.5); #local L1 = rand(cactusRand); #local L2 = rand(cactusRand); #if (L1 < 0.5) object { CactusOrLeaf rotate 30*x rotate RX1*z rotate RZ1*z translate <-0.15,-0.1,0> } #else object { CactusAndLeaf rotate 30*x rotate RX1*z rotate RZ1*z translate <-0.18,-0.1,0> } #end #if (L2 < 0.5) object { CactusOrLeaf rotate 180*z rotate RX2*x rotate RZ2*z translate <0.15,0.1,0> } #else object { CactusAndLeaf rotate 180*z rotate RX2*x rotate RZ2*z translate <0.18,0.1,0> } #end #local A = 0; #while (A < 360) #local B = -30; #while (B < 60) #local DX = CW*cos(B*Pi/180); #local DY = CH*sin(B*Pi/180); object { SpineSet rotate B*z translate rotate A*y } #local B = B + 10; #end #local A = A + 30; #end rotate RY*y texture { Cactus_Text } } #end #declare Cacti = union { object { Cactus() translate <-5,.45,-8> } object { Cactus() translate <-8.9,.7,-4.7> } // Wing reflecting object { Cactus() translate <5.5,.4,-7> } object { Cactus() translate <2,.42,-8> } object { Cactus() translate <8,.45,-6> } } // // Put it all together here. // object { GateGround } // The ground object { GateClouds } // The clouds #if (showPosts) object { Post translate -(1.95+PostRadius)*x } // The left gate post object { Post translate (1.95+PostRadius)*x } // The right gate post #end #if (showFence) object { IronWork } // The iron work #end #if (showDragons) #if (DGView = 7) object { Dragon(3) rotate 0*y scale 0.4 translate <2,11,20> } #else object { Dragon(1) rotate 30*y scale 0.4 translate <-4.5,2.3,-4> } object { Dragon(2) rotate 30*y scale <-0.4,0.4,0.4> translate <4.3,2.1,-4> } #end #end #if (showSign) object { Sign rotate -40*y translate <-3.8,0,-10> } #end #if (showCacti) object { Cacti } #end #if (showTrees) object { TREE scale 6 translate <-11,0.2,5> } object { TREE scale 6 translate <-4,0.8,7> } object { TREE scale 6 translate <10,1.3,7> } #end // // Where are we anyway? // camera { #switch (DGView) #case (1) location <0.0, 2.25, -20> // Full view look_at <0,2.25,0> #break #case (2) location <-4.5, 2, -8> // left dragon feet look_at <-4.5,0,-4> #break #case (3) location <4.3, 2, -8> // left dragon feet look_at <4.4,0,-4> #break #case (4) location <-5, 0.6, -9.5> // Cactus view look_at <-5,.6,-8> #break #case (5) location <0.0, 2.25, -8> // Closeup look_at <0,2.25,0> #break #case (6) // Sign closeup location <-3,2,-13> look_at <-3.8,2,-10> up <0,1,0> #break #case (7) // Gate closeup location <0,2.5,-6> look_at <0,2.5,0> up <0,1,0> #end } //light_source { <50.0, 40.0, -20.0> colour White *2 } //light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 5.0, -20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } // // Let there be light! // #if (DGView = 7) light_source { <200.0, 250.0, -250> colour White *3 shadowless } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } #else light_source { <200.0, 250.0, -250> colour White *3 } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } #end tkgate-2.0-b10/povray/gatelogo.pov000644 001751 001751 00000041010 10076274132 017653 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // // Designed to be 49x43 (old size 41x35) //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #declare PostRadius = 0.5; // Radius of posts #declare AngleStart = 9; // Start angle of TkGate text #declare AngleSpan = 21.0; // Number of degrees though which to position text #declare AngleStep = -(AngleSpan/8.0); // Number of degrees per letter #declare DrToe1Len = 0.1; #declare DrToe2Len = 0.08; #declare DrToeR = 0.035; #declare DrToeA1 = 20; #declare DrToeA2 = -40; #declare DrThumb1Len = 0.04; #declare DrThumb2Len = 0.04; #declare DrThumbR = 0.04; #declare DrThumbA1 = 5; #declare DrThumbA2 = -20; #declare DrClawStart = 0; #declare DrClawEnd = 0.1; #declare DrClawR = 0.02; #declare ClawText = texture { pigment { color Silver } normal { crackle 0.2 scale 0.2 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .2 } } #declare PlateText = texture { pigment { rgb <.4,0,0> } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } normal { crackle 0.7 scale 0.25 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 1 diffuse 0.6 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare GateGround = union { object { SandDunes } object { GrassHill } } // // A texture for wrought iron. // #declare Wrought_Iron = texture { pigment { granite color_map { [0.0 1.0 colour red 0.2 green 0.2 blue 0.2 colour red 0.0 green 0.0 blue 0.0] } } finish { ambient 0 diffuse 0.6 metallic 1} normal { wrinkles 1 scale 0.11 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{White} normal{ granite 0.05 scale 0.24 } finish{phong 0.8 phong_size 200 diffuse 0.4 } } // // The sky // #declare GateSky = sphere { <0.0, 0.0, 0.0>, 3500.0 hollow on pigment { onion colour_map { [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 colour red 0.1 green 0.6 blue 1.0] } quick_colour red 0.7 green 0.7 blue 1.0 scale <6000.0, 1700.0, 4000.0> translate <-1200.0, 220.0, 2500.0> } finish { ambient 0.9 diffuse 0.0 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1; #local L1 = 0.4; // Thiegh length #local L2 = 0.3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.05)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.08)*x translate -(1-FS)*y texture { DragonHide } } translate <0,0.7,0.1> } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,0.2,0.12,0.10,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,0.2,0.1,0.08,0.85) #end #declare AndGateDragon = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } /* object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } */ object { DragonBackLeg(45,100) translate 0.95*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.95*x } object { DragonBackLeg(45,100) translate 0.1*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.1*x } texture { DragonHide } } // // Define the posts that go on the sides of the gate. // #declare Post = union { intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 3.3*y } object { sphere { <0,0,0>, PostRadius } translate 3.8*y } texture { Post_Stone } } #declare SpikeR = 0.2; // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 3.0*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate 3.0*y } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end #declare DoorBase = union { Spike(1.5) Spike(0.9) Spike(0.3) Wire(0.05,2.75, 1.875,2.75) Wire(0.05,0.5, 1.875,0.5) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } translate 2.3*y } // // Fence // object { FenceSpike translate 2.6*x } object { FenceSpike translate 2.9*x } object { FenceSpike translate 3.2*x } object { FenceSpike translate 3.5*x } object { FenceSpike translate 3.8*x } } // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } #declare LeftDoor = union { object { DoorBase scale <-1,1,1> } translate 1.9*x } #declare RightDoor = union { object { DoorBase } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.8,0> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.45,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { #local A = 0; object { LeftDoor rotate -A*y translate -1.9*x } object { RightDoor rotate A*y translate 1.9*x } texture { Wrought_Iron } } // // Put it all together here. // object { GateGround } // The ground object { GateSky } // The sky object { GateClouds } // The clouds object { Post translate -(1.95+PostRadius)*x } // The left gate post object { Post translate (1.95+PostRadius)*x } // The right gate post object { IronWork } // The iron work //object { AndGateDragon scale 2.0 translate <0,0,-1> } // // Where are we anyway? // camera { location <0.1, 2.2, -4.9> // Full view // location <0.0, 1.7, -3.0> // 4 Gates // location <-1.1, 2.5, -1.5> // upper-left // location <0.9, 2.4, -1.5> // upper-right // location <-1.1, 0.5, -1.5> // lower-left // location <0.9, 0.5, -1.5> // lower-right // location <0, 2.5, -1> // top 2 // location <0, 0.5, -1> // bottom 2 // location <-1.9, 2.0, -0.5> // upper-left bracket // location <0.8, 2.5, -1> direction <0.0, 0.0, 1.0> // look_at <-2.125,2.8,0> // upper-left bracket // location <0.0, 6, -6> // Full view // look_at <0,2,0> // upper-left bracket } //light_source { <50.0, 40.0, -20.0> colour White *2 } //light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 5.0, -20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } // // Let there be light! // //light_source { <50.0, 90.0, -30> colour White *3 } //light_source { <-50.0, 90.0, -30> colour White } light_source { <200.0, 250.0, -250> colour White *3 } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } tkgate-2.0-b10/povray/hills.pov000644 001751 001751 00000001122 10076274132 017165 0ustar00hansenhansen000000 000000 #include "colors.inc" global_settings { assumed_gamma 2.2 hf_gray_16 } #declare PScale = 5.0; #declare FlatTexture = pigment { Black } #declare HillyTexture = pigment { bozo turbulence 0.1 colour_map { [0.0 0.1*White] [1.0 White] } scale (1.0/PScale)*y } object { plane { z, 0} hollow on texture { gradient y scale PScale*y texture_map { [0.0 HillyTexture] [0.7 HillyTexture] [0.95 FlatTexture] } } } camera { location <0, 0, -10> look_at 0 } light_source { <0, 20, -100> color White } tkgate-2.0-b10/povray/hills.png000644 001751 001751 00000224277 10076274132 017167 0ustar00hansenhansen000000 000000 ‰PNG  IHDR€àºƒ8gAMA† 1è–_sBITæ [™IDATxœìÁ  ÷OmÀ«ÿÿžT@ÔTIDATìVÑn#14UU*Nýÿ¥‰mf°Û׋•ìfw ÃÀæõy­×z­ÿwÙÛp¼ãzßñÆai·õý«uâèÆÁIoýSª>ÂØïBÿÞZa;ó¾6x»ßS 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˜&++ÁvÃÍt@††BÌK¤çT€EN„Y(Âø߯6ªŸ$ÄþóQ££äó¤Ó~Ë°ë÷B\§8ÈÉòÿÿm®ÔmIDATìÝ¿NÂPÇñßà paaëÌØÆÅ8À¦Žúþ™aêÀbt`tÁ„0eƒ&–ê膹4ZTÄšë÷3õOšÜíäœ{î)pEEº”.¤ò;/ó‡oH2µ¤¿¶0LÃð§eÊå­Xp pË¡t#dÏžg9ù-ÿû§¾ä­?kÓ¡áXJ¬[¿Ñ0ŒŒ†[À€‹Ž¤ké ½›>åíþJòö½/ÉÖë©ÛUnF›éئþ ÷€GU¤s)’ʺÜTÞEûU¾Õü¬Ãp&a§þ ÷p pßônš¼$£þHR2OfkÑ­T+Eó­æflk } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } normal { crackle 0.7 scale 0.25 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 1 diffuse 0.6 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare GateGround = union { object { SandDunes } object { GrassHill } } // // A texture for wrought iron. // #declare Wrought_Iron = texture { pigment { granite color_map { [0.0 1.0 colour red 0.2 green 0.2 blue 0.2 colour red 0.0 green 0.0 blue 0.0] } } finish { ambient 0 diffuse 0.6 metallic 1} normal { wrinkles 1 scale 0.11 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{White} normal{ granite 0.05 scale 0.24 } finish{phong 0.8 phong_size 200 diffuse 0.4 } } // // The sky // #declare GateSky = sphere { <0.0, 0.0, 0.0>, 3500.0 hollow on pigment { onion colour_map { [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 colour red 0.1 green 0.6 blue 1.0] } quick_colour red 0.7 green 0.7 blue 1.0 scale <6000.0, 1700.0, 4000.0> translate <-1200.0, 220.0, 2500.0> } finish { ambient 0.9 diffuse 0.0 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1; #local L1 = 0.4; // Thiegh length #local L2 = 0.3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.05)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.08)*x translate -(1-FS)*y texture { DragonHide } } translate <0,0.7,0.1> } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,0.2,0.12,0.10,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,0.2,0.1,0.08,0.85) #end #declare AndGateDragon = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } /* object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } */ object { DragonBackLeg(45,100) translate 0.95*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.95*x } object { DragonBackLeg(45,100) translate 0.1*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.1*x } texture { DragonHide } } // // Define the posts that go on the sides of the gate. // #declare Post = union { intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 3.3*y } object { sphere { <0,0,0>, PostRadius } translate 3.8*y } texture { Post_Stone } } #declare SpikeR = 0.2; // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 3.0*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate 3.0*y } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end #declare DoorBase = union { Spike(1.5) Spike(0.9) Spike(0.3) Wire(0.05,2.75, 1.875,2.75) Wire(0.05,0.5, 1.875,0.5) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } translate 2.3*y } // // Fence // object { FenceSpike translate 2.6*x } object { FenceSpike translate 2.9*x } object { FenceSpike translate 3.2*x } object { FenceSpike translate 3.5*x } object { FenceSpike translate 3.8*x } } // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } #declare LeftDoor = union { object { DoorBase scale <-1,1,1> } translate 1.9*x } #declare RightDoor = union { object { DoorBase } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.8,0> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.45,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { #local A = 85; object { LeftDoor rotate -A*y translate -1.9*x } object { RightDoor rotate A*y translate 1.9*x } texture { Wrought_Iron } } // // Put it all together here. // object { GateGround } // The ground object { GateSky } // The sky object { GateClouds } // The clouds object { Post translate -(1.95+PostRadius)*x } // The left gate post object { Post translate (1.95+PostRadius)*x } // The right gate post object { IronWork } // The iron work object { AndGateDragon scale 2.0 translate <9*clock-6,0,-1> } // // Where are we anyway? // camera { location <0.1, 2.2, -4.9> // Full view // location <0.0, 1.7, -3.0> // 4 Gates // location <-1.1, 2.5, -1.5> // upper-left // location <0.9, 2.4, -1.5> // upper-right // location <-1.1, 0.5, -1.5> // lower-left // location <0.9, 0.5, -1.5> // lower-right // location <0, 2.5, -1> // top 2 // location <0, 0.5, -1> // bottom 2 // location <-1.9, 2.0, -0.5> // upper-left bracket // location <0.8, 2.5, -1> direction <0.0, 0.0, 1.0> // look_at <-2.125,2.8,0> // upper-left bracket // location <0.0, 6, -6> // Full view // look_at <0,2,0> // upper-left bracket } //light_source { <50.0, 40.0, -20.0> colour White *2 } //light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 5.0, -20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } // // Let there be light! // //light_source { <50.0, 90.0, -30> colour White *3 } //light_source { <-50.0, 90.0, -30> colour White } light_source { <200.0, 250.0, -250> colour White *3 } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } tkgate-2.0-b10/povray/rungate.ini000644 001751 001751 00000000230 10076274132 017471 0ustar00hansenhansen000000 000000 ; ; ini file for run gate ; Width=41 Height=35 Initial_Clock = 0.0 Final_Clock = 1.0 Initial_Frame = 1 Final_Frame = 10 Input_File_Name=rungate.pov tkgate-2.0-b10/povray/mag.pov000644 001751 001751 00000003371 10076274132 016626 0ustar00hansenhansen000000 000000 // // Magnifying Glass // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "colors.inc" #include "textures.inc" #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.7> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } /* Back wall */ plane { z, 100 hollow on texture { pigment { color red 0.5 green 0.5 blue 1.0 } } } #declare Flat_Enough = 0.01; union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.8, 0.8, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 1.3 } texture { Sandalwood } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { object { Paraboloid_Z scale <1,1,0.2> translate -0.17*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.17*z } texture { LensGlass } } rotate <20, 40, -45> } camera { location <0.0, 0.0, -5.0> direction <0.0, 0.0, 1.0> up <0.0, 1.0, 0.0> // right <4/3, 0.0, 0.0> } light_source { <50.0, 40.0, -20.0> colour White *2 } light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } tkgate-2.0-b10/povray/simcontrol.pov000644 001751 001751 00000010677 10076274132 020262 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // sky_sphere { pigment { rgb <0.7, 0.7, 1.0> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.5; #macro ASquare(W,H) union { object { box { <-W,-H,-R>, } texture { MyAluminum1 } } union { object { cylinder { -W*x, W*x, R } translate H*y } object { cylinder { -W*x, W*x, R } translate -H*y } object { cylinder { -H*y, H*y, R } translate W*x } object { cylinder { -H*y, H*y, R } translate -W*x } object { sphere { , R } } object { sphere { <-W, H, 0>, R } } object { sphere { , R } } object { sphere { <-W, -H, 0>, R } } texture { MyAluminum2 } } scale 0.15 } #end #declare PlayButton = union { intersection { plane { z, R } plane { z, -R inverse } plane { x, 0 inverse } plane { x, 0 rotate 60*z translate sqrt(3)*x} plane { x, 0 rotate -60*z translate sqrt(3)*x} texture { MyAluminum1 } } union { object { cylinder { -1*y, 1*y, R } translate 0*x } object { cylinder { 0*y, 2*y, R rotate 60*z translate sqrt(3)*x} } object { cylinder { 0*y, 2*y, R rotate 120*z translate sqrt(3)*x} } object { sphere { , R } } object { sphere { <0, 1, 0>, R } } object { sphere { <0, -1, 0>, R } } texture { MyAluminum2 } } scale 0.15 } #declare FFPart = union { object { cylinder { 0*y, sqrt(2)*y, R rotate 45*z translate 1*x} } object { cylinder { 0*y, sqrt(2)*y, R rotate 135*z translate 1*x} } object { sphere { <1, 0, 0>, R } } object { sphere { <0, 1, 0>, R } } object { sphere { <0, -1, 0>, R } } } #declare FFButton = union { object { FFPart } object { FFPart translate 1.5*x } object { sphere { <0, 1, 0>, R } translate 3.5*x } object { sphere { <0, -1, 0>, R } translate 3.5*x } object { cylinder { -1*y, 1*y, R } translate 3.5*x } texture { MyAluminum2 } scale 0.15 } #declare FFButton2 = union { object { PlayButton } union { object { cylinder { -1*y, 1*y, R } translate (sqrt(3)+2.5*R)*x } object { cylinder { -1*y, 1*y, R } translate (sqrt(3)+5*R)*x } object { sphere { <0, 1, 0>, R } translate (sqrt(3)+2.5*R)*x } object { sphere { <0, -1, 0>, R } translate (sqrt(3)+2.5*R)*x } object { sphere { <0, 1, 0>, R } translate (sqrt(3)+5*R)*x } object { sphere { <0, -1, 0>, R } translate (sqrt(3)+5*R)*x } scale 0.15 } texture { MyAluminum2 } } #declare PlayButton2 = union { intersection { plane { z, R } plane { z, -R inverse } plane { x, -1 inverse } plane { y, -1 inverse } plane { y, 1 } plane { x, 0 rotate 45*z translate 1*x} plane { x, 0 rotate -45*z translate 1*x} texture { MyAluminum1 } } union { object { cylinder { -1*x, 0*x, R } translate 1*y } object { cylinder { -1*x, 0*x, R } translate -1*y } object { cylinder { -1*y, 1*y, R } translate -1*x } object { cylinder { 0*y, sqrt(2)*y, R rotate 45*z translate 1*x} } object { cylinder { 0*y, sqrt(2)*y, R rotate 135*z translate 1*x} } object { sphere { <1, 0, 0>, R } } object { sphere { <0, 1, 0>, R } } object { sphere { <0, -1, 0>, R } } object { sphere { <-1, 1, 0>, R } } object { sphere { <-1, -1, 0>, R } } texture { MyAluminum2 } } scale 0.15 } #declare StopButton = ASquare(1,1) #declare PauseButton = union { object { ASquare(0.13,1) translate -0.1*x } object { ASquare(0.13,1) translate 0.1*x } } union { object { PlayButton translate -1*x } object { PauseButton translate 0*x } object { StopButton translate 1*x } object { FFButton translate 2*x } } // // Where are we anyway? // camera { location <0, 0, -5> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-50.0, 50.0, -10> colour White*1.5 } light_source { <0, 0, -30> colour White*0.5 } tkgate-2.0-b10/povray/hills2.png000644 001751 001751 00000234451 10076274132 017244 0ustar00hansenhansen000000 000000 ‰PNG  IHDR~Ú»ÞÙgAMA± üaMtEXtSoftwareXV Version 3.10a Rev: 12/29/94 (jp-extension 5.3.3 + PNG patch 1.2d)Ü{0 IDATxœì½=š%É®$f¾o³ª”)Q¡@aD*¸‘+˜ÛéÀÄɬî~óZâ×QU™Y'ωðsÀðãpàŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëŸëÿoÿÛûÿÿïïúoŸ/üÇò1ÿã¯ÿü¸¿x}kÕ×_k诚÷×nòÇŸþÏÕŸÜó?3be€~}ýçþS£ÿ¸½ü_ê‡ÿúÓ”éÿ¿ýÑ=|}¾ôûúùßûëyy`5ª3>ÿúùø“†ÖõûŸ¾ãïòÇŸ¯Ï>¡!{ܾÝôs‚þx¸rŒþø£ÁY·­k¿·;ý˦Ls7yîùg€äÿÚ÷ù}>¹>õӬߦ-çOöÙÂûÑÞ\5õ|kÚÏ×·qÕ(ýÜ–óg÷»-}_ºéùøÿë#¿¸Å³>úü…¶|ŒÑÝ¿ËÇ…¿­ÿ†¢!ÇçDZù±ÃÝX5÷Ϧ¸ïòj~Îï†öÏrÿÛÍÜüèïø\¯NœjЙöýrTïþvñ1[Hü÷/[øýÚûžØïcõÇSþžñûñÛ5þçW7»óÁïÓÙÕ?Ø/›âs£ýu¨ìúÃáúà_Ào=iï¡™¦~ôyCnÍñ¯:ŽYþêÕRüZÛÿ÷ ä߯ü²¥àˆ½ìE~­Á´ŸÛõ½•^ßõOÝ_“¯1ý ,ðý6ë ×à ú£Î4 g?€Ç>îxéÜwô¾>yôñŸèýåâÅÝÄ/¬úãÑúà_9Dgøyé _Ý[lЩË,^>–É^,ø.ÑÔtþpÜ„àn°/ïN äeã~½ž³iúwßÂâ-³¥€|½óÆ úÅàÝná»IŸ<Ÿðyß]¨i öMŽÚ’ÏÁú%}õo0­_\ä}ý%úœ¦óm^BëÕå »×[õð[£§÷-Êf©üH ûâÿé9~~q€ó™ÔºÙœ‚žõ˜þé‚öù»eá[ ö?4ñãð5ô„ ñnÐÛ#÷jÏëÒk©}ë®îâŸÒ«Û"ÔéËÏüi¤0sÝ휟ŽÖ¿ðž™5=òì~~Ùf§×Ê·%³¸º¯%è ?ð[‹ùßá‡ã:î`_%úÎÁɹ0ìçy5í5¤óå­‘!¹‹‹¯©ç¾’ò©EXÂø=N«Aßñ÷†Í}­Ü¼šñØZk@ëV¾û9dý¯FêõqÎ-⇡ò5Ñù›‰À¥„5V}gëþ×üÄvíÕì?€ßk½¬™õF`/”ov|7ûyàp‡;Î'ÙÍ78¹ˆN‚/Ñ×#ºFÒº}9®þÔúÙà8¸õþsqîyÄÏÃú¯ÍzY÷˜½Gj)×å©E¬Zêçæ çâàŽ’ðì\kk ãýÐ~÷RÕ¨…Zlj÷8õÜÜàjqNÔ}ðõÛïÿúy¤„¾™µÏQÈ¡7ÿxmñ„ ¿Fß’ü‡éo}óƒkîÁ=÷ù:¸x¾üöF`ûwøøÜÝS ¶À—Ø÷“‹(%_þ3«‰ €ëJô9~oå"±óWË67j9 ™Àkõ=ↅw‹¶ ÎK„ϦÇ0_ÓQ=ˆð×íhä¨~¯˜Á{”vs¥£j¨J]ü€¿…¾œµY8>MÿÐñ­l‡+ôˆ²›‰ýÁ—fë^ó¹9þÎLþßá>wøõ%Þ{&ú>«]£º/¯æ:jEÇžîO:^ڪ峩oó»™À­%ÿ˜æø^ø{Ѷæ½Ü˜@zÝsг©Ö0ñןä·fÕXÕ­‰T,ÞR ^4÷û0ÕX=ÏIÑ÷&ꯧö—½M~=µÕÝÕ¶¡ã‘Ln+`]»ÅüÜCðs÷a€}‰@œžÌhF㨔½¢‡Íh<5¨¿C>Çpú  ƒ½b|6rokÅ…º8f£¸øÀ ÏKðø?-èÍŒcõöEÜ5Õ« ,U1óùV¾ë&!ù#£^ËåÀûÃ:}¡ï¼‰Ã¾~\-Ãô‰ï3ûûøK.üýÊÉýšמ·g)k^èø~\Í };p Žç?æ ¬ÆRªÐQ\0Yîˆ>„0–µña,Z¶ÙýCnI¥ŠPÁŠS ³ªÏ­þÂŽÑ@ah1 „ÍqN²7MiŠº†}? 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0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "chip.inc" #declare XMark = union { box { <-0.1,-1,0>, <0.1,1,0.1> } intersection { cylinder { 0*z, 0.1*z, 1} cylinder { -0.1*z, 0.2*z, 0.85 inverse } } texture { pigment { rgb <1,0,0> } finish { specular 0.2 diffuse 0.8 roughness 0.1 } } scale 0.8 rotate 45*z } object { Chip } object { XMark translate -0.5*z } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.0, 0.0, -2.5> look_at <0.0, 0.0, 0.0> } light_source { <-30.0, 30.0, -15> colour White *5 } tkgate-2.0-b10/povray/chip.inc000644 001751 001751 00000001511 10076274132 016744 0ustar00hansenhansen000000 000000 #declare Chip_Text = texture { pigment { rgb <.1,.1,.1> } finish { // metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { Silver } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Chip = union { box { <-0.5,-0.1,-1>, <0.5, 0.1, 1> texture { Chip_Text } } #local i = 0; #local Q = 0.3; #local W = 0.15; #local L = 0.3; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-0.45,0,Z-W>, <-0.45-L,-0.1,Z+W> texture { Pin_Text } } box { <0.45,0,Z-W>, <0.45+L,-0.1,Z+W> texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*0 } tkgate-2.0-b10/povray/moduleprops.png000644 001751 001751 00000023472 10143323564 020416 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®QIDATìÕ±NAÆñ™‹{ÈA,ˆÄ .æÞÔ§à9ìL vt&”bbL ¡0ÜÎÜØ\Ah’!߯Û-¦ùg0€aÀ0 `0 †€ CÀ†!`Ã0€aÀ0 `0 †€ CÀæ¹/m#UUÕsïÿ­uîàWTuø8Œ—ñþf_äE˜™HÈÂáú@DÌ|îáo!`ÛÚŸíxQkÛJæIòšU·U˜†"+d,! u»&ô|‰°aªÚê1Ñq›LnãÜÆ%ó„˜4RI¥•E^ȽH*èùb `øæä99:ŸŒ›®Ù¿{¿ò½y¯éùN$•0 aÊQ‰žíBÀ†Åo±[;bZ|/fëÙ ä<½J³NÖºÍ#>ýŸ¹f¿òþÃ÷_úMÏcÙ=ìªa&AF¢¬„žøÿÿ ™ÐéIDATìœOLÙÀ¿7c{<¶Á˜?Æc›Câ h@Ú"ØlQS"UJ.‘²Òªª”KµÚCª½5BU+µ{èªRöZí!ÒªŠ¢h©REbS)@ˆlx‰cŒqhÀk<žÛ3= ˜ ÿºm–Ø•æ'K¼ùÞ›yOh~óÍ<½Eà ‚œ˜È×Õq.—ˆaÿÑQ£F©<™V‰ªufýsë{øœ§[ç¦tT'ÙÙ¨iTj×ä7•FÒ¾Ðj#Z)(h®…c],çàrî_Ïo7S|®HÐÂÂB¹Ç €§R®«W@Ðh¿?çõæ::¸ÖV¡ªê@yƒ\ºTŒ*]L¿@â,°b«ˆ´^-æ‹ ÃtÇGú|zŸGï!qò™ù :u°l+ËÙ9†f da»wÅçÊ@ÉÀ•‚abB*`GNM‘SS h4¬×›õûù––lW—ˆa°#a̠ʪAp+X²´ }ÿ×ï·o1ŠEg¢KSK±¹X(’4iš|¤¯MßFèf]³©ßÇ›cF„ â;BÚ,E¶•åš¹\kŽ·ò|­’ŸËŒ’+Q›¯]#^¼8ª Ž³nwŽ¢¿?GӶߺ‰ >_ùü%û²Ô ×â}û®Ã¥Ã–âéd:üm8:ÎDó )¨Á4nÂM(ÚHSFªºªúàTŒ,ꋹÖgçØf–µ±C™ß-ŠÀ•—JEîÜáFGiž§TG6ñ”+üÊgñÏäUž!ÏÀŸö[$—™gø—3/ã¡x,‹<Ž0›Œ·TY<¿ÆO›héPaûžœ1Y*ðµ<×ÄYÆ\ç\ŠÆïEàJA,Ç0óÁàÚóçØ“ÉŸØ”¹ð!äFþ52º9*¯úë­ÏöCæÀJåÔ‹”t³Å—ç–¥ Žp¯ÑK™(·ÑÝ^ÝÞ@4eòÎfr+ùé?>õ÷ ^Ô4ŠÆÇ"pe!÷j}m-'ƒAõô´;“éh)Õq·AôÀptx£°Q ëõWþyå¿ÕFÞ)›a#H$‰ÍÆ¢3Ñ<›—âfÙcòtš;½Õ^§É©SëÔø«ÐWwîa&Îÿþ|ÛÙ6ÅácE¸r‘{õjuõy0¸1;KÎÎöfìÝÜ-@Î…o$nÈw9õËS}×úÞÆy§¢ &æ‘@$:"›ÉM)Žæ49}fUK¹«Ý6£m{Ê„OF>I³éÒ.Þ¸èé÷(Ê,tå"?ïë¬Ö:«€ø³î<Ê<Ú³‹gÈó#vŠTÈæ³Ù|¶3WÎÀÖë­x( D–¦—bó±¥ÈÒב¯»º¯¿w]øiò©Ü^„¡zªþ-Ç£p4ŠÀÿȳ"uÊX‘ nåÍêOÔ×Rµ{Ú¿%rŸI3IŸ¥é³4óÅågË‘@¤çYOiMÈd|R¾¯í”ÍÔdRÒï±¢\é¨Õj£Ñ†‰¢¨ÚTá¿Â“gÎmŠ¦Ú~©ÛÒa±X,°c]IcQB!éa„†a‚°½þY‡= „Òét>Ÿ/m–ªð*ÜqÊáô9ÝpC[dËùÈ;/tÛEaEàJG­V×ÖÖîn›®JÍ0pܽ3 ÃóüÁKÁ"çHŒÇ¤ ühù[`Kµ¸§©ãž‚òEŽJ§¼ßÙÀ°CÏQ O ¥)èéø´¼¶íl›®Z§Ü?7ŠÀ•Ny(‹‡U©7Õú½T~{=›œ•×ÒƒôñŽL+Ÿòfà#.äs‰HJ¿“±IAÜ]MÖ‘í´+é÷ <—Ò¼ÑÑìo³²²’J¥ºººÂá0¡ÓÙìöññq³Ùl0r¹Üüü¼Åb9yòäää¤Ûår´¶–vœ››s8ápØétÞ½{Çñ‹/Þ»w¦iÇWWWçææúûûFãâââÆÆÆÀÀK2Kƒ7M›v†Ñ „ÂN> )„)ö¾ ˃(Š¦o¾A‚éë+’ä&ïÉÀãããÑh´J­îêêzðàAMMÍ/ìö'Ož$‰K—.¥Óél6ÛÑÑ¡ÑhÖÖÖ¬V«|ßh4úðáêª*‹Å’L&{º»àþýû?þàܹÅp8N?~>4455Eµ·€4Y½mB«Ii¤ôÛŒÅ7ã¿3…ªx 5a†<ñ^#üà+”ÂÛ \P¡P÷å—ªL¦á‹/r4éíÍž>Í74ì?ãUª7–BçóùV‡caq1ŸÏó<¿¾¾z‚¸|ùr¡P`Y–çùD"ár¹ÔjõíÛ·iz÷Y”a˜ .ü}d„çùl6›J¥ÀÖÔ„ã8¡×@}}}£Õ ---Þöv8äZEòÙî?FÚTŒ]Å€QÝ¿ê7¿‚¿\çÿÖ˜£(–¦³~¾®î°C)¼%ÊRÊò@ÌÌ؇‡åÃx»=sæÌÖéÓ\s3ìœñ:®¹¹¹<£ˆÇã ÃìuO×]ø.eàï|üS,ô3Ã*XÎy‹Ez ’moçl6PdþñP2pEQ5;»'ˆA‹in޴ܼÉ75mõönõô°^oyÏõ{'¾#ð̶½¡d(ÃnöÕ¬ƒîÐ QõúºzlÌ86E½ž9q"GÓŒß/¿N)üoüÿÿK•3j IDATì[PYÇ¿¾$[wBb¹f‰¯ÈU(•qV”µÔ­’šÙy™âaª¶¶j´f÷iÊÚg_|Øšf«œu´¶kJKÖˆ “`p1bˆ äF ä~#½‰¡¹Z« UÓ¿7úœ/}’:N÷w¾ï;ØÙ³gs=†ß‚D÷ì™9tȃa¯W ­˜û˜ßÏþ\üว‡ƒ¢Ü††L“Ýnüø1Ç‹ÅZ­6 ÉårƒÁ044TTTÄårSÝ‚Á F£A$///c;33óŸÎN¡PˆaØŸ¶Z­*•*Ó:00pW­‡Ã%%%6›M*•€Ïç‹ÇãLÑ4-}(å¹Ó5´n>½é^˜O†]ø‚G$Øûh­¨¨P*•}:]IiiUUÓÖl6G#‘òŠŠ®®.™LvìØ1­Vëv»ÛÛÛq|É°bõ#‡Étø$€~ZÏ Ÿ$HbuæŸ[‹Š¶:~œN&§ÆÇûGG¯ Ü‘‘±Ø€J†˜¤î•—W²c»ü®+àM ç%‡7±ì¸··wÌj‘$SÀN§³¬¬Ì66æp:€X,æp8/=¹|™#)‘HܺuëܹsÁ`Ð::zòÔ)°Ûí'‰ˆD"XŲ ;4M)€tú‘Ö®eöÜ÷ù¾õ¿KFŠ†•*¥ Åá'Rbî2¦M&Ý^“H¨ô°ÿÈ‘~6™asCõPˆÙÄçó·µo¶‹RÄb1³Ù\PXˆaX"‘˜{ýÇq‘Ht»³“Ù Çñ²²2Š¢¢Ñ(IQ/&'   À·°àóù6 o†GxˆÔò;étûÜÌÖ]'ß#}yŠa¥ žøâÏ.|þÓOôùó7OŸÆ**ß÷é§ïþ¿YX'Ö慦鲿”eü˜³18Î@ ªÚ‘¯ÎÏ{”—r_]ºÚmíÎt“ÿNþõí¯ÿÿÇÝÌ‚ …xûü¼!ì ¼yáMðˆÄr9†Œ¢!‡I’t²ÿE?³Ûî?îþ ·Ë¬Ì¬zßVÀ›š¦Åj1Àªt µZ‹Å@ŸN§×ëÀb±Ü¹s'U¼Êï÷?zô(wÞ¾mµZ™†ƒÁápètºd2yãÆÁÁ•E-W“Q‘È"J? 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#local Q = 0.25; intersection { box { <-W/2,-H/2,-D/2>, } box { <-W/2+X,-H/2+X,-D/2+X>, inverse} texture { Plastic_Text } } box { <-W/2,H/2-Q,-D/2>, texture { NBglass } } object { Paper(W*.8,H*.8,D*.8) } } #end #macro OutputWell(W,H,D) union { #local Q = 5; #local HH1 = -0.5; #local HH2 = -2; intersection { plane { z, D/2 rotate -10*x } plane { z, -D/2 inverse } plane { y, -H/2 inverse rotate 30*x } plane { x, W/2 } plane { x, -W/2 inverse } plane { y, H/2 } } box { <-W/2*.9,HH1,D/2> , } } #end #macro RoundBox(W,H,D,R) union { sphere { <-W,-H,-D>, R } sphere { <-W,-H,D>, R } sphere { <-W,H,-D>, R } sphere { <-W,H,D>, R } sphere { , R } sphere { , R } sphere { , R } sphere { , R } cylinder { -W*x, W*x, R translate <0,H,D> } cylinder { -W*x, W*x, R translate <0,H,-D> } cylinder { -W*x, W*x, R translate <0,-H,D> } cylinder { -W*x, W*x, R translate <0,-H,-D> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,H,0> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,-H,0> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,D> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,-D> } box { <-W,-H-R,-D>, } box { <-W,-H,-D-R>, } box { <-W-R,-H,-D>, } } #end #macro Display(W,H,D) union { box { <-W/2, -H/2, -D/2>, texture { Plastic_Text } } union { // box { <-W/2,H/5 , -D/2>, <-W/2+2,-H/5,-D/2-0.25> texture { DarkPlastic_Text } } // box { , texture { DarkPlastic_Text } } box { <-W/2,H/5 , -D/2>, texture { DarkPlastic_Text } } box { <-W/2,H/5 , -D/2>, texture { NBglass } } translate 0.2*H*y } } #end #declare Buttons = union { sphere { <0,0,0>, 1 scale <0.6,0.3,1> translate <-1,0,0> texture {GreenPlastic_Text}} sphere { <0,0,0>, 1 scale <0.6,0.3,1> translate <-1,0,-3> texture {RedPlastic_Text}} #local d = 0; #while ( d < 4 ) sphere { <0,0,0>, 1 scale <0.6,0.3,0.1> translate <1,0,-d> texture { Plastic_Text}} #local d = d + 1; #end } #declare Printer = union { #local W = 20; #local H = 10; #local D = 20; #local TW = 12; #local TH = 2; #local TD = 10; #local Tout = -(D/2); #local T1y = 2; #local T2y = -2; #local Xshft = -2; #local R = 0.5; // main box intersection { RoundBox(W/2,H/2,D/2,R) // box { <-W/2,-H/2,-D/2>, } object { TrayForm(TW,TH,TD) inverse translate } object { TrayForm(TW,TH,TD) inverse translate } object { OutputWell(TW,H*0.7,D*0.5) inverse translate } texture { Plastic_Text } } object { Buttons translate } object { Display(5,3,3) rotate x*30 translate <(W/2-3),H/2,0> } object { Tray(TW,TH,TD) translate } object { Tray(TW,TH,TD) translate } } object { Printer } //OutputWell(20,10,20) sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 // colour red 0.0 green 0.0 blue 1.0 } } // // Where are we anyway? // camera { location <-10.0, 20.0, -35> // location <15.0, 30.0, 0> look_at <0.0, 0.0, 0.0> } light_source { <100,200, -300> colour White *1 } tkgate-2.0-b10/povray/printer.xpm000644 001751 001751 00000067234 10076274133 017556 0ustar00hansenhansen000000 000000 /* XPM */ static char * printer_xpm[] = { /* width height num_colors chars_per_pixel */ "125 100 174 2", /* colors */ " c magenta", ". c #cccacc", "X c #c4bebc", "o c #ccbab4", "O c #cccecc", "+ c #c4b2ac", "@ c #c4b6ac", "# c #d4bebc", "$ c #ccbeb4", "% c #d4c2bc", "& c #ccc2bc", "* c #ccb6b4", "= c #c4bab4", "- c #ccbebc", "; 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X o O ", " + @ # o o $ o o @ # o o o o % o o o o $ ", " & X o @ # $ * = * = # $ @ o - @ o ; $ $ $ o $ $ % # ; $ : * ", " . > - = + ; @ * @ + o $ % ; @ # @ o = $ $ o @ o @ , $ o @ - % o $ $ o o o $ $ * ; $ < : 1 o ; o $ ", " = o # @ o - , = $ % % o o - @ ; @ - o o o $ $ , ; % * $ o ; $ $ o - @ # : o ; # < o % * = o $ o $ 1 ; @ % 2 # o ", " O . & ; % $ o ; o o o $ o o $ $ o o # o < $ o $ o $ o $ @ @ $ @ # @ $ # % o < : * o - % $ $ - o o $ o * $ $ o $ , % % $ - o $ $ @ o ; @ o ; % @ o = @ # : . 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", " ) c 4.4.c c c 4.4.x 4.4.c 4.c c c 4.4.2.4.x x ", " p.c 4.2.c 4.4.' 2.c c 4.c c 4.2. ", " p.2.4.e c 4.2.4.c c x 2.4. ", " 3.o c 4.c c c ", " O c c c . . ", " ", " ", " "}; tkgate-2.0-b10/povray/port.pov000644 001751 001751 00000007266 10324742464 017061 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; intersection { // Outputs box { <-1, -1, 0.1>, <1, 1, -0.1> } box { <-1, -1, 1>, <1, 1, -1> scale 0.85 inverse} texture { Bus_Text } } union { #local Y = -0.7; sphere { <0,0,0> 1 scale <.09,.09,.09> translate <1,Y,0> } cylinder { 0*x, 5*x, 0.05 translate <1,Y,0> } union { starttext(0.6, Y-0.07, 0.03, 0.15) putchar(char_Z) putchar(char_7) translate <0,0,-.1> } texture { Gate_Text } } union { #local Y = -0.4; sphere { <0,0,0> 1 scale <.09,.09,.09> translate <1,Y,0> } cylinder { 0*x, 5*x, 0.05 translate <1,Y,0> } union { starttext(0.6, Y-0.07, 0.03, 0.15) putchar(char_Z) putchar(char_6) translate <0,0,-.1> } texture { Gate_Text } } union { #local Y = -0.1; sphere { <0,0,0> 1 scale <.09,.09,.09> translate <1,Y,0> } cylinder { 0*x, 5*x, 0.05 translate <1,Y,0> } union { starttext(0.6, Y-0.07, 0.03, 0.15) putchar(char_Z) putchar(char_5) translate <0,0,-.1> } texture { Gate_Text } } } union { intersection { object { Circuit } plane { x, 0 inverse } plane { x, 1.5 } plane { y, 0 } } rotate 55*y rotate 30*x } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.2, 0.0, -4.3> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *3 } tkgate-2.0-b10/povray/netprops.xpm000644 001751 001751 00000103022 10076274133 017727 0ustar00hansenhansen000000 000000 /* XPM */ static char * netprops_xpm[] = { /* width height num_colors chars_per_pixel */ "100 100 223 3", /* colors */ " c white", ". c #acd2ac", "X c #3cfe3c", "o c #44fe44", "O c #44f644", "+ c #3ce23c", "@ c #3cca3c", "# c #3cae3c", "$ c #349634", "% c #9cba9c", "& c #7cd67c", "* c #34f634", "= c #44f244", "- c #3caa3c", "; c #acc2ac", ": c #acd6ac", "> c #3cfa3d", ", c #3cde3c", "< c #3c963c", "1 c #8cd28c", "2 c #3ce63c", "3 c #3cd23c", "4 c #3cb23c", "5 c #6ca66c", "6 c #9cd29c", "7 c #3c9a3c", "8 c #bccebc", "9 c #3cee3c", "0 c #3cd63c", "q c #3cba3c", "w c #6caa6c", "e c #bcd2bc", "r c #44de44", "t c #34fa34", "y c #4cfe4c", "u c #3cea3c", "i c #3cc23c", "p c #9cd69c", "a c #349a34", "s c #54de54", "d c #3cc63c", "f c #3ca63c", "g c #bcc6bc", "h c #6cda6c", "j c #3cf63c", "k c #2c962c", "l c #44fa44", "z c #3cb63c", "x c #44e244", "c c #9cce9c", "v c #3cf23d", "b c #44d244", "n c #3cbe3c", "m c #4ce64c", "M c #3cda3c", "N c #3c9e3c", "B c #bcbec5", "V c #9cda9c", "C c #4ce24c", "Z c #7cae7c", "A c #5ca25c", "S c #7cda7c", "D c #4ca24c", "F c #8cde8c", "G c #3ca23c", "H c #8cd68c", "J c #3cce3c", "K c #8cb68c", "L c #6cde6c", "P c #5c9a64", "I c #4c9e4c", "U c #7cb6a4", "Y c #34969c", "T c #346ebc", "R c #2c5ac4", "E c #2442cc", "W c #2c4abc", "Q c #3c56b4", "! c #346284", "~ c #7c9a9c", "^ c #9c9edc", "/ c #5452f4", "( c #4442f4", ") c #3c3ef9", "_ c #3c3ee7", "` c #3c3ed8", "' c #3c3ec0", "] c #3c3ab4", "[ c #6c6ed4", "{ c #9c9ebc", "} c #44e644", "| c #5c5ef4", " . c #4442fc", "... c #343acc", "X.. c #3c3ecc", "o.. c #3432a4", "O.. c #7c7ec0", "+.. c #4442ec", "@.. c #4442e4", "#.. c #4442cc", "$.. c #343a94", "%.. c #7c7eac", "&.. c #4c4afc", "*.. c #5452fc", "=.. c #4c4aec", "-.. c #3c3aac", ";.. c #3c3a94", ":.. c #9c9ec4", ">.. c #4c9a4c", ",.. c #bcbed4", "<.. c #3432f4", "1.. c #4442dc", "2.. c #acaec4", "3.. c #2cf62c", "4.. c #7c7ee4", "5.. c #5456fc", "6.. c #4c4ef9", "7.. c #4c4ae4", "8.. c #4442d4", "9.. c #3c3ea9", "0.. c #3c3e95", "q.. c #acceac", "w.. c #acaed4", "e.. c #4c4eec", "r.. c #4446dc", "t.. c #344284", "y.. c #5cde5c", "u.. c #34e634", "i.. c #4c4af4", "p.. c #243e7c", "a.. c #24327c", "s.. c #3c3eb4", "d.. c #14366c", "f.. c #143e6c", "g.. c #14326c", "h.. c #7c7edc", "j.. c #142e6c", "k.. c #243aa4", "l.. c #5c5ec4", "z.. c #343eac", "x.. c #243694", "c.. c #1c3a80", "v.. c #243e84", "b.. c #244e84", "n.. c #144a7c", "m.. c #4c4a94", "M.. c #34727c", "N.. c #2cbe54", "B.. c #2cd244", "V.. c #24c634", "C.. c #1cae34", "Z.. c #2c7a5c", "A.. c #2c5264", "S.. c #5c5eb4", "D.. c #24e23c", "F.. c #44f64c", "G.. c #1c7a2c", "H.. c #3c4e94", "J.. c #6c6eac", "K.. c #4c4ea4", "L.. c #1caa44", "P.. c #249224", "I.. c #146a34", "U.. c #5c5ea6", "Y.. c #249624", "T.. c #2c6e4c", "R.. c #7c7eb4", "E.. c #3cca4c", "W.. c #4cf64c", "Q.. c #3c8254", "!.. c #4cee4c", "~.. c #5cea5c", "^.. c #5cee5c", "/.. c #4cf24c", "(.. c #4cfa4c", ").. c #54fe54", "_.. c #3cd664", "`.. c #34ae84", "'.. c #248294", "].. c #248a84", "[.. c #2c8e74", "{.. c #7c7ed4", "}.. c #3c52e4", "|.. c #142ecc", " X. c #142adc", ".X. c #1426c4", "XXX c #0c16bc", "oXX c #2c32c4", "OXX c #6c76b4", "+XX c #6c6eec", "@XX c #2c3ab4", "#XX c #3476b4", "$XX c #1c5abc", "%XX c #4446e7", "&XX c #1c52b4", "*XX c #8c8eb4", "=XX c #1442c4", "-XX c #3442e4", ";XX c #143abc", ":XX c #1436bc", ">XX c #143a9c", ",XX c #1c32bc", " o O , @ # < ; 1 * o o O 2 3 4 5 ", " 6 o o O + @ # 7 ; 8 9 > o o 2 0 q w ", " e > o O r @ 4 $ % 2 t y o u r i 7 ", " p > o O + @ # a % s X o o = , d f g ", " p o o O + @ # < ; h j o o = + @ - % ", " p > o O , @ 4 k % 1 j o o l 2 3 z 5 ", " p o o O x @ # $ % c v t y l 9 b n < ", " p X o O + @ 4 $ % 8 m * o o = M d N B ", " V l o O + @ 4 < % C o o o = , @ - % ", " p o o O + @ 4 7 % & * o y j + b 4 Z ", " p o o = x @ 4 $ % 6 j o y l 2 3 q A ", " S o o O + @ 4 $ % ; = t o o = 0 n D ", " F X o O x @ 4 $ Z 8 9 t y o 9 r d G B ", " H o y O + @ z $ % s X o y = + J # K ", " F X o O , b 4 k % L j o o O 2 b z P ", " V o o O + @ 4 a K 1 v o y o 2 0 n I ", " U Y T R E W Q ! ~ c v t o o = M i I ", " ^ / ( ) _ _ _ ` ` ' ] [ { } * o y 9 , @ f K ", " | . . ) ( ) _ _ ` ...` X..] o..O.. m X y o = x J - Z ", " / . . . . . +..@..` ` ` ] X..] #..$..%.. h O o y l 2 3 q A ", " ^ . . &..&..*..&..=..+..` ` X..X..' ] -..;..;..:..B 6 * o y o u 0 n >.. ", " ,..<.. . . *..*..*..*..=..@..1..X..X..] ] ] -..-..;..;..2.. c = 3..o y 9 r d f K ", " 4.. . . &..*..5..*..6..7..1..8..X..X..] ' 9..9..0..;..$..%.. q..9 t o y = , @ - Z ", " w..<.. . . &..*..*../ e..r..8..#..' ] #..-..9..0..0..0..t..;..< b r r y..0 r r b h M y..h 0 r r b r r b r r r b r r s 0 s b s M r r r s M s r u..+ + } 2 O + b z A ", " w..( ( ( i..i..i..=..7..1..#..#..] ' -..9..;..9..;..0..p..a..< r r M M r M r , r M M M r M r r M , r M M , r M M M r M r M M M M M , M M M M M , M , M , 3 q P ", " 4..<..+.._ +..=..7..r..8..#..X..] ' s..9..9..0..0..0..0..p..d..7 3 3 b 3 b 3 b J 3 b J b 3 b 3 3 b 3 3 J b J b J b J 3 J 3 J b b b J b J b J b J J J J J J @ 4 7 % ", " [ @.._ _ @..1..1..8..X..' #..' s..-..0..-..0..;..0..0..f..g..< < i i i i n i i i i i i n i n i n n i n i n i n i n i n i n i n n i n i n i n i i i i i i q f < K ", " h..@..` ` ` ` X..X..#..] ] s..-..9..9..0..0..0..0..;..g..j..< < < # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # 4 # # # # # # # # # # # # - < < K ", " [ ` ` ` ` X..#..' ] ' s..9..9..0..0..;..0..;..0..0..g..j..< < < N N N N N N 7 N 7 N N N N N 7 N 7 N N N N N N N N N N N N 7 N 7 N N N N N N 7 N 7 N 7 < < < 2.. ", " ^ ` ] 1..] X..] ' ] s..-..9..;..0..;..0..0..0..0..;..;..j..< < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < A ", " B ` ] X.....] k..9..s..9..0..o..9..0..0..0..0..;..0..0..0..a..< < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < < A g ", " l..] #..] ] z..x..c..v..b..n..p..;..0..;..0..0..0..;..0..m..% Z % K K % K K K K % K K K % % % % % % % % % % K % K Z Z K % K % K K K K Z K K % % K Z % K g ", " ^ ] ] ] s..-..-..M..N..B..V..C..Z..A..0..0..;..0..0..;..2.. ", " S..] -..9..9..M..D..j F..+ @ z G..H..0..0..0..0..J.. ", " K..-..0..;..L..> y O x J z P..I..;..0..;..m..B ", " B U..;..0..J X y O + J z Y..T..0..0..K..B ", " R..0..E..o y W.., b z P..Q..;..%..B ", " 2..!..X y l + @ z Y..< 2.. ", " !..o y O x J z 7 >.. ", " ~..o y O + J z 7 >.. ", " ^..o y O x @ q 7 5 ", " ~..X y l x J z 7 < ", " j o y O , b q 7 >.. ", " = o y l x @ z N >.. ", " j o y W..+ J q 7 >.. ", " = o y O x J z N < ", " /..o y O , b q 7 >.. ", " = o y (..+ @ q 7 < ", " j o y O , b q 7 < ", " = o y (..+ J z N < ", " j o y W.., b q 7 >.. ", " = o y l x J z G < ", " j o y W..+ J q N < ", " W..o y (..+ J q N < ", " > o y O r b q N < ", " j y y (..+ J q G < ", " > o y O x J q N < ", " l o )..(..+ J q G < ", " > o y l x J q N < ", " e > y y (..x 3 q G < ", " . > _..`..'..]..[..Z..Z..< % ", " w..{..}..<..|.. X.|...X.XXXoXXt..OXXB ", " +XX) ) _ ( _ _ _ 1..` ` @XX...o..l.. ", " ,../ . <.. . ) ) ) _ _ ` ` ` X..] z..] m.. ", " ,..&.. . . . . . ( +.._ _ ` ` ` X..' ' ] ] S.. ", " &..) . . . &..&..&..( +.._ ` ` X..' X..] ] -..o..U.. ", " 4..) . . &..*..*..*..&..=..+..1..` ` X..X..] ' ] -..;..;..J.. ", " ,..<.. . . . &..*..*..*..6..i..@..1..` X..X..' ] ' 9..-..;..;..;.. ", "c & 1 1 c c ; 1 c c 1 c q..c ; c c c c ; c [ ) . . &..*..5..5..*..6..=..@..1..` #..' ] #..-..9..9..;..;..;..J.. ", "} } 2 + 2 2 2 2 + + + + 2 2 2 } + } 2 2 2 #XX) ) . &..*..*..5..*..6..7..1..8..X..] X..] ] 9..9..;..0..;..;..m.. ", "2 } } } } } x } 2 } } 2 } x } 2 } + } + x $XX<.. . . &..&..*../ 6..%XX1..1..#..X..X..' -..#..9..9..9..0..9..;..;..2.. ", "x r x r x r x r r r r r r r r r r r r r r &XXE ( ( ( i..i..%XX=..r..1..` #..' ] ] s..-..;..9..;..0..;..0..;..*XX ", "b 3 b b 3 b 3 b 3 b b 3 b 3 b J b J J b 3 &XX=XX-XX+..+..%XX%XX%XX@..8..8..#..' ' ] #..9..9..9..0..0..0..0..;..;..R.. ", "i i i i n i n i n i n i n i i i i i i n i ;XX;XX;XX_ +..@..@..1..` 8..X..' ' ' ] -..-..0..;..0..;..0..;..0..;..R.. ", "4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 # 4 4 4 :XX|....._ ` ` ` ` 8..' X..' ] ] 9..9..9..9..0..0..0..0..0..;..;..J.. ", "G N G N G G G G G G G G G N G N G G G N G >XX,XX` ` ` 8..` ' X..' ' ] ' s..-..9..;..0..;..0..;..0..;..0..;..*XX ", "< < < < < < < < < < < < < < < < < < < < < >XX...` ` ` X..X..' #..] ' ' -..9..9..9..0..0..0..0..0..0..9..;..;..2.. ", "< < < < < < < < < < < < < < < < < < < < < ..5 ", " L t y )..l x 3 n - < 5 ", " ~..rXXy )..(..x 3 n f < 5 ", " aXX3..y )..(..+ 3 n - < 5 ", " uXXt y )..(..x b n - < P ", " ~..* y )..(..+ 3 n - < 5 ", " uXXpXXy )..(..x b n - >..P ", " m 3..y )..(..+ 3 n - < A ", " ~..t y )..(..x b n - < P "}; tkgate-2.0-b10/povray/BIRCH.inc000644 001751 001751 00000011305 07065103346 016654 0ustar00hansenhansen000000 000000 //XXXXXXXXXXXXXXXXXXXXX S E T T I N G S XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //TREE #declare BRANCHES=7; #declare TWIGS=5*BRANCHES; #declare BUNCHES=3*TWIGS; #declare LEAVES=200*BUNCHES; #declare BLOSSOMS=0*BUNCHES; #declare ROOTS=4; #declare BRANCH_RANDOM=15.397; #declare TWIG_RANDOM=77.37; #declare ROOT_RANDOM=173; //TRUNK #declare TRUNK_RADIUS=20; #declare TRUNK_STRENGTH=.5; #declare TRUNK_BEND_X=15; #declare TRUNK_BEND_Z=20; #declare TRUNK_BEND_X_FREQUENCY=1.5; #declare TRUNK_BEND_Z_FREQUENCY=1.5; #declare TRUNK_CURVE=10; #declare TRUNK_CURVE_FREQUENCY=5; #declare TRUNK_SNAG=5; #declare TRUNK_SNAG_FREQUENCY=10; #declare TRUNK_SPIRAL=50; #declare TRUNK_TAPER=0.2; #declare FIRST_BRANCH_AT_TRUNK=300; #declare BRANCH_AREA_AT_TRUNK=300; //BRANCH #declare BRANCH_THICKNESS_CHANGE=.7; #declare BRANCH_STRENGTH=1; #declare BRANCH_BEND=-30; #declare BRANCH_BEND_FREQUENCY=2; #declare HORIZONTAL_BRANCH_BEND_SWITCH=1; #declare EXTRA_NOISE_SWITCH=1; #declare BRANCH_CURVE=-5; #declare BRANCH_CURVE_FREQUENCY=2; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=1; #declare BRANCH_LONGITUDINAL_CURVE=.5; #declare BRANCH_SNAG=3; #declare BRANCH_SNAG_FREQUENCY=5; #declare BRANCH_REDUCTION=.0; #declare BRANCH_TAPER=.2; #declare BRANCH_END_EQUALIZER=1; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=1; #declare BRANCH_ALTERNATE_SWITCH=0; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=35; #declare BRANCH_ANGLE_SCOPE=0; #declare BRANCH_ALIGNMENT=.8; #declare STRAIGHTEN_TOWARDS_TOP=0.6; #declare FIRST_TWIG_AT_BRANCH=50; #declare TWIG_AREA_AT_BRANCH=100; //TWIG #declare TWIG_STRENGTH=.5; #declare TWIG_THICKNESS_CHANGE=.55; #declare HORIZONTAL_TWIG_ANGLE=0; #declare VERTICAL_TWIG_ANGLE=30; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=0; #declare VERTICAL_TWIG_ANGLE_SCOPE=0; #declare HORIZONTAL_TWIG_ALIGNMENT=1; #declare VERTICAL_TWIG_ALIGNMENT=1; #declare TWIG_TURN_SWITCH=1; #declare TWIG_ALTERNATE_SWITCH=0; #declare TWIG_CURVE_ADJUSTMENT=.8; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_TAPER=1; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=3; #declare LAST_RAMIFICATION_NUMBER=5; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=.5; #declare FIRST_BUNCH_AT_TWIG=100; #declare BUNCH_AREA_AT_TWIG=150; //BUNCH #declare BUNCH_MAJOR_RADIUS=150; #declare BUNCH_MINOR_RADIUS=50; #declare HORIZONTAL_BUNCH_FUNNEL=40; #declare VERTICAL_BUNCH_FUNNEL=40; #declare ROTATION_BUNCH_FUNNEL=0; #declare HORIZONTAL_BUNCH_ANGLE=0; #declare VERTICAL_BUNCH_ANGLE=30; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=5; #declare VERTICAL_BUNCH_ANGLE_SCOPE=5; #declare BUNCH_TURN_SWITCH=1; #declare BUNCH_TURN_SHIFT=1; #declare BUNCH_ALTERNATE_SWITCH=0; #declare HORIZONTAL_BUNCH_ALIGNMENT=1; #declare VERTICAL_BUNCH_ALIGNMENT=1; #declare BUNCH_TAPER_OFF_AT_TWIG=.3; #declare BUNCH_TAPER_OFF_AT_BRANCH=-.3; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=HF_SIMPLELEAF #declare LEAF_LENGTH=10; #declare LEAF_BREADTH=7; #declare LEAF_HEIGHT=1; #declare MAX_LEAF_TILT=30; #declare MAX_LEAF_TURN=30; #declare LEAF_INCLINATION=50; #declare LEAF_INCLINATION_SCOPE=10; //BLOSSOM #declare BLOSSOM=LEAF #declare BLOSSOM_LENGTH=50; #declare BLOSSOM_WIDTH=100; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<1,1,1>; //ROOT #declare FIRST_ROOT_AT_TRUNK=30; #declare ROOT_LENGTH=200; #declare ROOT_THICKNESS_CHANGE=.6; #declare ROOT_STRENGTH=1; #declare ROOT_BEND=50; #declare ROOT_BEND_FREQUENCY=1; #declare ROOT_CURVE=30; #declare ROOT_CURVE_FREQUENCY=5; #declare ROOT_SNAG=5; #declare ROOT_SNAG_FREQUENCY=15; #declare ROOT_TURN_SWITCH=1; #declare ROOT_ANGLE=30; #declare ROOT_ALIGNMENT=.6; //BARK #declare SUNKEN_TRUNK_COLOR=<-.1,-.1,-.1>; #declare RAISED_TRUNK_COLOR=<1,1,1>; #declare FOLIAGE_COLOR_AT_BRANCH_END=1; #declare TRUNK_SCAR_WIDTH=60; #declare TRUNK_SCAR_HEIGHT=15; #declare HORIZONTAL_SCAR_SHRINKING=.2; #declare VERTICAL_SCAR_SHRINKING=2; #declare SCAR_DEPTH=-1; #declare PALM_TRUNK=0.2; #declare BARK_PROFILE=0; #declare BRANCH_BARK_PROFILE_CHANGE=0; #declare BRANCH_BARK_PROFILE_TAPER_OFF=1; #declare ROOT_BARK_PROFILE_CHANGE=0; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.5,0.4,0>; #declare BOTTOM_COLOR_2=<0.4,0.5,0>; #declare TOP_COLOR_1=<0.5,0.5,0>; #declare TOP_COLOR_2=<.3,.8,0>; #declare COLOR_TURB=.5; #declare TRANSITION_BOTTOM_TOP=0.4; #declare TRANSITION_TURB=.25; #declare FOLIAGE_GLOSS=0.0; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX tkgate-2.0-b10/povray/search.pov000644 001751 001751 00000016404 11141647504 017331 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } //object { Paper } object { MagGlass rotate -45*x scale 0.6 translate <.2,.35,-0.9> } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -6> look_at 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«Þ€a}d<š¤ÔÕí­«7kBð„áÇà¿"Y95‘Oõ:…®™O#ì3ñ!è“õ*s"„±% ¿>ÑôðÄ ©¸w]ÓwIô`„qšˆœ§à>Ψ¦ŸÝ‰ÝZLmrPÄ(ÂóôŒïu鉙"½ Vöäå‰[Sû‡á÷©²~éBª@ô™¸ß–åb_yÖFh"‰â,·¶4ÉÀÿËèjV†ê¢3IEND®B`‚tkgate-2.0-b10/povray/netlist.pov000644 001751 001751 00000013564 10131662705 017550 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "stones.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.2 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 1.5; #local H = 2; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } #declare Desk = union { #local W = 4; #local H = 4; #local D = 1; box { <-W,-H,-D>, } texture { T_Grnt21 } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <1.2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <1.2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // Bus feed wire box { <1, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Gate_Text }} box { <1, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Gate_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Gate_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end } union { object { Circuit translate 0.01*y } object { Paper rotate x*-90 rotate y*90 translate <0.5,0,0.2> } object { Desk rotate x*-90 rotate y*90 translate <0.5,-0.01,0.2> } rotate x*-90 rotate y*40 rotate z*-20 translate -0.5*x } // sky_sphere { // pigment { // colour red 0.8 green 0.8 blue 0.8 // } // } // // Where are we anyway? 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "stones.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { specular 0.15 ambient 0.5 } } #declare Text_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.15 ambient 0.5 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.2 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 1.5; #local H = 2; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } #declare Desk = union { #local W = 4; #local H = 4; #local D = 1; box { <-W,-H,-D>, } texture { T_Grnt21 } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { starttext(-.9, 1.3, 0.03, 0.2) putchar(char_M) putchar(char_O) putchar(char_D) putchar(char_U) putchar(char_L) putchar(char_E) kern(1) putchar(char_M) putchar(char_A) putchar(char_I) putchar(char_N) texture { Text_Text } rotate 90*x } union { starttext(-.6, 1, 0.03, 0.2) putchar(char_R) putchar(char_E) putchar(char_G) kern(1) putchar(char_LSqu) putchar(char_7) putchar(char_Perc) putchar(char_0) putchar(char_RSqu) kern(1) putchar(char_A) kern(0.5) putchar(char_B) kern(0.5) putchar(char_C) kern(1) texture { Text_Text } rotate 90*x } union { starttext(-.6, 0.7, 0.03, 0.2) putchar(char_I) putchar(char_N) putchar(char_I) putchar(char_T) putchar(char_I) putchar(char_A) putchar(char_L) texture { Text_Text } rotate 90*x } union { starttext(-.3, 0.4, 0.03, 0.2) putchar(char_B) putchar(char_E) putchar(char_G) putchar(char_I) putchar(char_N) texture { Text_Text } rotate 90*x } union { starttext(0, 0.1, 0.03, 0.2) putchar(char_A) putchar(char_Perc) putchar(char_B) putchar(char_Astr) putchar(char_C) texture { Text_Text } rotate 90*x } union { starttext(0, -0.2, 0.03, 0.2) putchar(char_B) putchar(char_Perc) putchar(char_A) putchar(char_Astr) putchar(char_C) texture { Text_Text } rotate 90*x } union { starttext(-.3, -0.5, 0.03, 0.2) putchar(char_E) putchar(char_N) putchar(char_D) texture { Text_Text } rotate 90*x } union { starttext(-.9, -0.8, 0.03, 0.2) putchar(char_E) putchar(char_N) putchar(char_D) putchar(char_M) putchar(char_O) putchar(char_D) putchar(char_U) putchar(char_L) putchar(char_E) texture { Text_Text } rotate 90*x } } union { object { Circuit translate 0.01*y } object { Paper rotate x*-90 rotate y*90 translate <0.5,0,0.2> } object { Desk rotate x*-90 rotate y*90 translate <0.5,-0.01,0.2> } rotate x*-90 rotate y*40 rotate z*-20 translate -0.5*x } // sky_sphere { // pigment { // colour red 0.8 green 0.8 blue 0.8 // } // } // // Where are we anyway? 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } texture { LensGlass } } rotate <20, 40, -45> } #declare BugLeg = union { #local L = 0.1; object { cylinder { 0*z, L*z, 0.01 } } object { cylinder { 0*z, L*z, 0.01 } rotate 30*x translate L*z } } #macro Bug() union { // body object { sphere { <0,0,0>, 1} scale <0.3,0.1,.15> texture { BugShell_Text } } #local Q = 60; #local A1 = Q*(rand(rstate)-0.5); #local A2 = Q*(rand(rstate)-0.5); #local A3 = Q*(rand(rstate)-0.5); #local A4 = Q*(rand(rstate)-0.5); #local A5 = Q*(rand(rstate)-0.5); #local A6 = Q*(rand(rstate)-0.5); #local RA = 360*(rand(rstate)-0.5); // legs object { BugLeg rotate <20,A1,0> translate <0,0,0.15> } object { BugLeg rotate <20,A2,0> translate <0.1,0,0.15> } object { BugLeg rotate <20,A3,0> translate <-0.1,0,0.15> } object { BugLeg rotate <20,A4,0> scale <1,1,-1> translate <0,0,-0.15> } object { BugLeg rotate <20,A5,0> scale <1,1,-1> translate <0.1,0,-0.15> } object { BugLeg rotate <20,A6,0> scale <1,1,-1> translate <-0.1,0,-0.15> } //head object { sphere { <0,0,0>, 1} scale <0.1,0.1,.1> translate <.2,0,0> texture { BugHead_Text }} rotate RA*y } #end union { object { Circuit } #declare rstate = seed(42); object { Bug() translate <.3,.1,1.1> } #declare rstate = seed(88); object { Bug() translate <.8,.1,-0.5> } #declare rstate = seed(201); object { Bug() translate <-.4,.1,0.3> } rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare CV = 0.85098039215686274509; sky_sphere { pigment { // colour red 0.8 green 0.8 blue 0.8 // colour red 1 green 1 blue 1 colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.2, 0.0, -5> look_at <0.2, 0.0, 0.0> } light_source { <-10.0, 30.0, -30> colour White *3 } tkgate-2.0-b10/povray/bug.png000644 001751 001751 00000041025 10145306200 016602 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®©IDATìÚ¿Kaðç/ ’r° ¥±M›[]"ðð¿èèop¸©]"¤E¤Ñ7µyŠº^ z§¶߆ƒÆ²!Þ÷µïgz†¾Ë—ç9xY`"ƒ±ÀDc‰ ÆŒ&2 Ld0Ø$½^ ¨BºH¨@ëòö¼Æ~Ãëðá°„ÒÁîeYªC‘bÜÀfà¥= zSe{)Æ l†¥³\8 ‰†‘ó쨎Cºà6€z¦ˆDÃèòâRu"Ò l† ÄC8 ÙïgŠ±ÀðS~|?‡Ã0oçUÇ!°Àºà§|`Ò™sEÕ‰H#,°‚dÁûô=EÙ£,ïgúÂ뮓îÌy<ŸïŸ« Cºaµ ›êÆóãÝã¯îg>ØúX`­uSÝñö8¾ŸWÍÕ:÷3M»é>¹ýdŸ5Þl|È¡µEb%V4ŒÊgå¿àn»íöÔ›JQnïoOŽ¯œ«Œ•áŸóFâÖ€VºσëA!WøþûWyußÜÚKm¶5³l[lûÔ$¿ò÷aIOÿÿ2{¡øIDATì›]lSçÇÿωÇqlÇà¯|z„áC‰éŒ‘´Z!ObUB³ÝPÔ”í† ªLë&´NlWBÓ`B¢“˜D*õ"‚0´Ý4D0–ˆˆì8Kpµ‰!¶ãà8v°cû¼Ï.ÌÒZª]”ÚÑù]½¯ôêœ÷¼òÏÏó~EàÜÅ«÷f—¯áÄË/?ÿü33Ÿ‹œ»l¼L눆IÚ,‘ÈAèà ÇáÀ°’K¯Isfökýè|mø½”¾t“oÒ2‘ŠHMd%2ü B ]·º^H¯^4ŠÀ¹KŸ©/{þÙöÀÖàhxNËP&tŽÎ¡$¢u„Y [@ýt¯{§¼J^{(ç(Qu4kï‚oaÁ·ðœü™™/F/©ˆÊˆ¦ ë@$Ànf#c‚"øbß@áE œ‹0sŸ©/[ô¿røùíû ûð)P•ö3ob;ˆ(4úÆû­ðÂQ¶‘r”OLŸˆÁ¶¶ýÍ_ùù3_œ»8›£ÂÐw ÓàBF%x’y'sÃ>Í]áùt zÛ¶ØÖ­q½> @ÙXZ(ç"ÙðËàåðri]©_ëw$xF9f>õ—Sƒ?D5h‘(E˜ À,`ÆPq°ŠaÀý‰ëK33Ök׬Cº¢"YY™hlŒ<{[…<¢àرcßv¾3Xþa² I u±;pÛx{\7>®`[¶e›õôô8p`sñê8™ˆìDV¢i¢Í„Ià;~!B, bNÈa•|_.+{@*Uk&'uýýæ©)F#–—%½>­˜œwÐØØØ·Ý…/ÀÌG×-2VJӥƌqâà„ÇãéêêêŽvwtS’¤’ôX’F$j%%Ö²L²|WΔg2îL&”Iþ³(};­Õêvíú“Åò=® ²Î¡¢"ÑØÙ²%¦hœG(8ç ¢]³»JKä)ylrLW­uÀrÁòÔ)÷ßÝM÷šfm³W毈AåD O‰¶‚`?‹MB¾!‹‚?f¹D“z‹|x÷î³³WïÜù€ââÊÂB#ðÄáXLíó駦t©”T^žP4Î sFWKµ{4{ÞÔ½©õj£¾èèÈh‘¹H]¬NÞOÞrÝ2l7?¤u=$̃,D‹ (‡˜¼‰Å˜!&„¬‘å;öâT­ÝþýÚÚCÇ>ìÍjlµî>ñ˜zjJ7?¯QBq^ ¤Ð¹ÎÊé ¯ß{uéêÝSw‡‡p’U6•ñWÆM­'Š“I‚3°âBÞ%Ë·d¹T–å´Hÿàq«-Y F{{‡ªªšªªöÅã㣿·Xönßþs‹eïŠÃÙ«Á>tè¾21Îq󆓃Ñ`ïPoïPïÈÒHÉ%TF’A¢%’F$râ@ Ä¿…lå9Y—3K™ÔLÊtmÃéÓ¿u:Á`thÈßÛ;ÔÛ;@–?knþ³Ãñ:VÙ Åáé†É8hTGÕ){J.’‘Ûíöx<g¡q! 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À¨€a¼°Qf÷ÄÔY>Ï~!vT^°ËÌN*{azº˜H|>)Ì^×KZU¾Jl®ïíåJ¥?„ü¬Õ<þ*ð!`€Çq)–Ífù{>?§(îs7ÃSbý^'&á¹Åï/s¹z³¹¾±±N{·vð+Ô€žÆ¥þe&®ƒ9¿ ¥7Å«r¥üiÿ@Ú­;`TؼÄéñ‰IˆVSß-/¿žŸ÷z9à?Àà¼^À8BðÀ_ÿÿ¯æ.:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ:IDATìÕ±À ëaì)‰ À@À00  À@À00  À ÿÿ3žiÓ9IDATíÕ±À ëaì)‰ À@À00  À@À00  À $““i±E¸IEND®B`‚tkgate-2.0-b10/povray/delay.pov000644 001751 001751 00000021566 10145560725 017171 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Gold_Text = texture { pigment { rgb <0.6, 0.5, 0.05> } finish { metallic specular 0.3 // roughness 0.1 ambient 0.5 diffuse 0.2 reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.8 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #macro Put1Number(R,B,A,HH,C) union { starttext(0, 0, 0.03, 0.15) putchar(C) translate -HH*y rotate 90*x rotate -A*y translate B*y translate R*z rotate A*y } #end #macro Put2Number(R,B,A,HH,C1,C2) union { starttext(0, 0, 0.03, 0.15) kern(-0.4) putchar(C1) putchar(C2) translate -HH*y rotate 90*x rotate -A*y translate B*y translate R*z rotate A*y } #end #macro Numbers(R,B) union { #local HH = 0.07; Put2Number(R,B,0,HH,char_1,char_2) Put1Number(R,B,30,HH,char_1) Put1Number(R,B,60,HH,char_2) Put1Number(R,B,90,HH,char_3) Put1Number(R,B,120,HH,char_4) Put1Number(R,B,150,HH,char_5) Put1Number(R,B,180,HH,char_6) Put1Number(R,B,210,HH,char_7) Put1Number(R,B,240,HH,char_8) Put1Number(R,B,270,HH,char_9) Put2Number(R,B,300,HH,char_1,char_0) Put2Number(R,B,330,HH,char_1,char_1) texture { Ink_Text } } #end #macro Hand(H,L,A) union { #local R = 0.05; cylinder { (H-0.01)*y, H*y, R } box { <-.02,H-0.01,0>, <.02,H,L> } rotate A*y texture { Ink_Text } } #end #macro Lens(R) union { #local LT = 0.03; cylinder { -LT*y, 0*y, R } texture { LensGlass } } #end #declare Watch = union { #local T = 0.1; #local R = 1; #local IR = 0.95; #local B = 0.2*T; intersection { union { cylinder { T*y, -T*y, 1 } torus { R, T } } cylinder { T*(B-0.01)*y, T*1.1*y, R inverse } texture { Gold_Text } } cylinder { 0*y, T*B*y, R texture { Paper_Text } } // Center pin cylinder { 0*y, 0.1*y, 0.01 texture { Ink_Text } } Hand(0.1, 0.8, 65) Hand(0.1, 0.6, 272) Numbers(0.85*R,B) object { Circuit scale 0.15 translate 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #declare Pi = 3.1415926; #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Gold_Text = texture { pigment { rgb <0.8, 0.7, 0.05> } finish { metallic specular 0.3 // roughness 0.1 ambient 0.5 diffuse 0.2 reflection .2 } } #declare Inard_Text = texture { pigment { rgb <0.3, 0.3, 0.05> } finish { metallic specular 0.05 // roughness 0.1 ambient 0.3 diffuse 0.2 // reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.3*z, 0.5 } } object { cylinder { z, -z, 0.35 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.45,0.0>, <0.25,0.6,0.3> } box { <0.0,0.0,0.0>, <0.25,0.15,0.3> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #macro Gear(X,Y,R,N,A) union { #local T = 0.08; cylinder { 0*x, T*x, R } #local i = 0; #local w = (1.0/N)*Pi*R; #while (i < N) #local a = i*360.0/N; object { box { <0,0,-w/2>, <1*T,w,w/2> } rotate 0*x translate R*y rotate a*x} #local i = i + 1; #end rotate A*360.0/N*x translate <0, X, Y> texture { Gold_Text } } #end #declare Inards = union { Gear(0.14, 0.16, 0.03, 10, 0.5) Gear(0.12, 0.09, 0.03, 10, 0) Gear(0.03, 0.1, 0.05, 14, 0.25) } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { intersection { object { OrGate translate <0,-0.3,0> texture { Gate_Text }} object { box { <0.07,0,0>, <0.1,0.2,0.2> inverse rotate 45*z translate <.6, 0.02, 0.05> } texture { Inard_Text } } } object { Inards rotate 45*z translate <.6, 0.02, 0.05> } // Outputs // cylinder { 0*x, 0.25*x, 0.035 translate <0.83,0,0.05> texture { Wire_Text }} // Inputs // cylinder { 0*x, 0.25*x, 0.035 translate <-.25,-0.1,0.05> texture { Wire_Text }} // cylinder { 0*x, 0.25*x, 0.035 translate <-.25,0.1,0.05> texture { Wire_Text }} } } union { object { Circuit rotate 50*y} translate <0,0.1,0> } //#declare CV = 0.85098039215686274509; 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¬j˜ ’;/U–”0 #¹¹ëJ¸ â@±íê®gplþp½lP½]Ë®ƒK¸3Ààˆ+ˆ;| zŒÛ»¬º¤´ÄZ4P IÉ›£ª^ ¶üÛ¿…K»áÀ´Û;VºYI! õê¸¬Ê Á ¿ñëz ´ Pqð¹£^еÎû¿ßÀl¸|³¶ Š RI¡Ùi+D`¤öÓÁ!(P ´àA üÖ bj +±Ü 0½Ò›¬lÀ¢cð Š‚ï A ¾Ø@ ¸@±Àp À[’;¹o ¡„àúAz@q0   Ÿà—¹y ­™‘` 0 þ”`ÅNà Z¼Π¶3ü¾JÆ8,ùP Ã@ ÂàI0k¬€$àÆRðÉRïð›Ü P# HÐØ@>Ð\Ì2¼p ¯8L¹ª¾@í@’ HàÑàIàÈŒÌIÑà«, ’@´ðÊÈ"ðÅæp´šËu¡(€„+и€ >à´°ÎÒœÎ>€ ° ±P²LÌ°À°Í6ÜÍÞl ÎnÅDP " Œ`]Ð@×pÏ b¬„òÏý translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Gold_Text = texture { pigment { rgb <0.6, 0.5, 0.05> } finish { metallic specular 0.3 // roughness 0.1 ambient 0.5 diffuse 0.2 reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.8 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus feed wire box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <-1.2,0.3,0> texture { Bus_Text }} // Bus crossing box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <1.5, 0.035, 0.035> translate <-1.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #macro Put1Number(R,B,A,HH,C) union { starttext(0, 0, 0.03, 0.15) putchar(C) translate -HH*y rotate 90*x rotate -A*y translate B*y translate R*z rotate A*y } #end #macro Put2Number(R,B,A,HH,C1,C2) union { starttext(0, 0, 0.03, 0.15) kern(-0.4) putchar(C1) putchar(C2) translate -HH*y rotate 90*x rotate -A*y translate B*y translate R*z rotate A*y } #end #macro Numbers(R,B) union { #local HH = 0.07; Put2Number(R,B,0,HH,char_1,char_2) Put1Number(R,B,30,HH,char_1) Put1Number(R,B,60,HH,char_2) Put1Number(R,B,90,HH,char_3) Put1Number(R,B,120,HH,char_4) Put1Number(R,B,150,HH,char_5) Put1Number(R,B,180,HH,char_6) Put1Number(R,B,210,HH,char_7) Put1Number(R,B,240,HH,char_8) Put1Number(R,B,270,HH,char_9) Put2Number(R,B,300,HH,char_1,char_0) Put2Number(R,B,330,HH,char_1,char_1) texture { Ink_Text } } #end #macro Hand(H,L,A) union { #local R = 0.05; cylinder { (H-0.01)*y, H*y, R } box { <-.02,H-0.01,0>, <.02,H,L> } rotate A*y texture { Ink_Text } } #end #macro Lens(R) union { #local LT = 0.03; cylinder { -LT*y, 0*y, R } texture { LensGlass } } #end #declare Watch = union { #local T = 0.1; #local R = 1; #local IR = 0.95; #local B = 0.2*T; intersection { union { cylinder { T*y, -T*y, 1 } torus { R, T } } cylinder { T*(B-0.01)*y, T*1.1*y, R inverse } texture { Gold_Text } } cylinder { 0*y, T*B*y, R texture { Paper_Text } } // Center pin cylinder { 0*y, 0.1*y, 0.01 texture { Ink_Text } } Hand(0.1, 0.8, 65) Hand(0.1, 0.6, 272) Numbers(0.85*R,B) object { Circuit scale 0.15 translate <0,1.1*T*B,-.4> } object { Lens(R) translate (T-0.05)*y } } union { object { Circuit } object { Watch scale 0.4 translate <1.1,0.3,0.15>} object { Watch scale 0.4 translate <1.1,0.3,1.5>} rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.2, 0.0, -7.5> look_at <0.2, 0.0, 0.0> } light_source { <-10.0, 10.0, -30> colour White *3 } tkgate-2.0-b10/povray/module_copy.pov000644 001751 001751 00000020454 10146552224 020401 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Plastic_Text = texture { pigment { rgb <.87, .8, .77> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare GreenPlastic_Text = texture { pigment { rgb <.7, .87, .67> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare RedPlastic_Text = texture { pigment { rgb <.87, .5, .47> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare DarkPlastic_Text = texture { pigment { rgb <0.7*.87, 0.7*.8, 0.7*.77> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.8 diffuse 0.2 } } #declare Pencil = union { #local L = 1.5; #local R = 0.15; #local Q = 0.03; #local X = 10; #local D = 0.5; #local E = 0.3; intersection { intersection { box { <0,-R,-R>, } object { box { <0,-R,-R>, } rotate 45*x } texture { Yellow_Paint } } object { cone { <0.0,0,0> , 0, , R*X} texture { T_Wood3} } } intersection { object { cylinder { 0*x, L*x, Q } } object { cone { <-0.01,0,0> , 0, , R*X} } } object { cylinder { L*x, (L+E)*x, R } texture { Erase_Text } } object { cylinder { L*x, (L+E/2)*x, 1.01*R } texture { T_Silver_1A } } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } object { box { <-(W-T),-D,-(H-T)>, } texture { Paper_Text }} object { text { ttf "cyrvetic.ttf" "ALU32" 0.3, 0 } scale 0.3 rotate 90*x translate <-0.5,0.101,0.55> texture { Ink_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.3; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 } #macro Paper(W,H,D) union { box { <-W/2,-H/2,-D/2>, } texture { Paper_Text } } #end // // A cut-out the same size as a tray // #macro TrayForm(W,H,D) object { box { <-TW/2,-TH/2,-TD/2>, } } #end #macro Tray(W,H,D) union { #local X = 0.25; #local Q = 0.25; intersection { box { <-W/2,-H/2,-D/2>, } box { <-W/2+X,-H/2+X,-D/2+X>, inverse} texture { Plastic_Text } } box { <-W/2,H/2-Q,-D/2>, texture { NBglass } } object { Paper(W*.8,H*.8,D*.8) } } #end #macro OutTray(W,H,D) union { #local X = 0.25; #local Q = 0.25; intersection { box { <-W/2,-H/2,-D/2>, } box { <-W/2+X,-H/2+X,-D/2+X>, inverse} texture { Plastic_Text } } object { Chip rotate 90*x rotate 180*y scale 5 translate 1*z } } #end #macro OutputWell(W,H,D) union { #local Q = 5; #local HH1 = -0.5; #local HH2 = -2; intersection { plane { z, D/2 rotate -10*x } plane { z, -D/2 inverse } plane { y, -H/2 inverse rotate 30*x } plane { x, W/2 } plane { x, -W/2 inverse } plane { y, H/2 } } box { <-W/2*.9,HH1,D/2> , } } #end #macro RoundBox(W,H,D,R) union { sphere { <-W,-H,-D>, R } sphere { <-W,-H,D>, R } sphere { <-W,H,-D>, R } sphere { <-W,H,D>, R } sphere { , R } sphere { , R } sphere { , R } sphere { , R } cylinder { -W*x, W*x, R translate <0,H,D> } cylinder { -W*x, W*x, R translate <0,H,-D> } cylinder { -W*x, W*x, R translate <0,-H,D> } cylinder { -W*x, W*x, R translate <0,-H,-D> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,H,0> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,-H,0> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,D> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,-D> } box { <-W,-H-R,-D>, } box { <-W,-H,-D-R>, } box { <-W-R,-H,-D>, } } #end #macro Display(W,H,D) union { box { <-W/2, -H/2, -D/2>, texture { Plastic_Text } } union { // box { <-W/2,H/5 , -D/2>, <-W/2+2,-H/5,-D/2-0.25> texture { DarkPlastic_Text } } // box { , texture { DarkPlastic_Text } } box { <-W/2,H/5 , -D/2>, texture { DarkPlastic_Text } } box { <-W/2,H/5 , -D/2>, texture { NBglass } } translate 0.2*H*y } } #end #declare Buttons = union { sphere { <0,0,0>, 1 scale <0.6,0.3,1> translate <-1,0,0> texture {GreenPlastic_Text}} sphere { <0,0,0>, 1 scale <0.6,0.3,1> translate <-1,0,-3> texture {RedPlastic_Text}} #local d = 0; #while ( d < 4 ) sphere { <0,0,0>, 1 scale <0.6,0.3,0.1> translate <1,0,-d> texture { Plastic_Text}} #local d = d + 1; #end } #declare Copier = union { #local W = 20; #local H = 10; #local D = 20; #local TW = 12; #local TH = 2; #local TD = 10; #local Tout = -(D/2); #local T1y = 2; #local T2y = -2; #local Xshft = -2; #local R = 0.5; #local PW = 12; #local PD = 14; // main box intersection { RoundBox(W/2,H/2,D/2,R) // box { <-W/2,-H/2,-D/2>, } object { TrayForm(TW,TH,TD) inverse translate } object { TrayForm(TW,TH,TD) inverse translate } // object { OutputWell(TW,H*0.7,D*0.5) inverse translate } box { <-PW/2,0,-PD/2>, inverse translate <-3,1,0> } texture { Plastic_Text } } box { <-PW/2,H/2-Q,-PD/2>, texture { NBglass } translate <-3,0.5,0> } box { <-PW/2,H/2-Q,-PD>, texture { Plastic_Text } rotate 30*x translate <-3,0.5,PD/2> } object { Chip rotate 90*x rotate 180*y rotate 180*z scale 5 translate <-3,6,1> } object { Buttons translate } object { Display(5,3,3) rotate x*30 translate <(W/2-3),H/2,0> } object { OutTray(TW,TH/2,TD) translate } object { Tray(TW,TH,TD) translate } } union { object { Copier } // rotate y*40 // rotate z*-20 } #declare CV = 0.85098039215686274509; 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Text_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.15 ambient 0.5 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.01 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } union { union { object { text { ttf "cyrvetic.ttf" "Name: add8" 0.03, 0 } scale .3 } translate <-.9, 1.3,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Pos: (95,74)" 0.03, 0 } scale .3 } translate <-.9, 1,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Hide: Yes" 0.03, 0 } scale .3 } translate <-.9, 0.7,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Anch: No" 0.03, 0 } scale .3 } translate <-.9, 0.4,-0.02> } scale 0.4 translate -0.01*z texture { Text_Text } } texture { Paper_Text } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 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@ú¡Š ÓE¢aG0’ ÆpÖWe¨…ZtˆÇ@ r Cû°ú¡®à @ b#J¤¤r°Øà Ä@ ¢0¤Ðaã¥.2= \Ú¥®€  J¢Pf°rK€c þG°” Ÿ ÁŒ@£Xº`§®Ð¦$:”À ¾ Ø€ h@ Jz ƒxa‡p `Ved©ЪxŠ™¶%˜°¢Ä~ššn²pà7€:˜¥]Úª­ ñ¹ F ŽT@ : ›ÁìЉÙpŒ ‡ ¬ûÒ£‘j¬®š °ê]@ „šˆªÐÀùõ• k jŸØ¨âÚª* bü§šØ ž! iðv u}!P‡ðgrJùÚ*Ð öÚ›º* ºp‡`g…&Sâ&Œ €9 ®‡ KbJûb03±¬5œ  ÊŠ=Úª!›²*«> °~¶P!p‹³dpëÚ‡B»Ø™´L+;tkgate-2.0-b10/povray/general.pov000644 001751 001751 00000041252 10145506602 017474 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // // Designed to be 49x43 (old size 41x35) //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #declare PostRadius = 0.5; // Radius of posts #declare AngleStart = 9; // Start angle of TkGate text #declare AngleSpan = 21.0; // Number of degrees though which to position text #declare AngleStep = -(AngleSpan/8.0); // Number of degrees per letter #declare DrToe1Len = 0.1; #declare DrToe2Len = 0.08; #declare DrToeR = 0.035; #declare DrToeA1 = 20; #declare DrToeA2 = -40; #declare DrThumb1Len = 0.04; #declare DrThumb2Len = 0.04; #declare DrThumbR = 0.04; #declare DrThumbA1 = 5; #declare DrThumbA2 = -20; #declare DrClawStart = 0; #declare DrClawEnd = 0.1; #declare DrClawR = 0.02; #declare ClawText = texture { pigment { color Silver } normal { crackle 0.2 scale 0.2 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .2 } } #declare PlateText = texture { pigment { rgb <.4,0,0> } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } normal { crackle 0.7 scale 0.25 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 1 diffuse 0.6 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare GateGround = union { object { SandDunes } object { GrassHill } } // // A texture for wrought iron. // #declare Wrought_Iron = texture { pigment { granite color_map { [0.0 1.0 colour red 0.2 green 0.2 blue 0.2 colour red 0.0 green 0.0 blue 0.0] } } finish { ambient 0 diffuse 0.6 metallic 1} normal { wrinkles 1 scale 0.11 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{ colour red 0.95 green 0.95 blue 0.7 } normal{ granite 0.05 scale 0.24 } finish{phong 0.8 phong_size 200 diffuse 0.4 } } // // The sky // #declare GateSky = sphere { <0.0, 0.0, 0.0>, 3500.0 hollow on pigment { onion colour_map { [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 colour red 0.1 green 0.6 blue 1.0] } quick_colour red 0.7 green 0.7 blue 1.0 scale <6000.0, 1700.0, 4000.0> translate <-1200.0, 220.0, 2500.0> } finish { ambient 0.9 diffuse 0.0 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1; #local L1 = 0.4; // Thiegh length #local L2 = 0.3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.05)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.08)*x translate -(1-FS)*y texture { DragonHide } } translate <0,0.7,0.1> } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,0.2,0.12,0.10,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,0.2,0.1,0.08,0.85) #end #declare AndGateDragon = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } /* object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } */ object { DragonBackLeg(45,100) translate 0.95*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.95*x } object { DragonBackLeg(45,100) translate 0.1*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.1*x } texture { DragonHide } } // // Define the posts that go on the sides of the gate. // #declare Post = union { intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 3.3*y } object { sphere { <0,0,0>, PostRadius } translate 3.8*y } texture { Post_Stone } } #declare SpikeR = 0.2; // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 3.0*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate 3.0*y } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end #declare DoorBase = union { Spike(1.5) Spike(0.9) Spike(0.3) Wire(0.05,2.75, 1.875,2.75) Wire(0.05,0.5, 1.875,0.5) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } translate 2.3*y } // // Fence // object { FenceSpike translate 2.6*x } object { FenceSpike translate 2.9*x } object { FenceSpike translate 3.2*x } object { FenceSpike translate 3.5*x } object { FenceSpike translate 3.8*x } } // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } #declare LeftDoor = union { object { DoorBase scale <-1,1,1> } translate 1.9*x } #declare RightDoor = union { object { DoorBase } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.8,0> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.45,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { #local A = 0; object { LeftDoor rotate -A*y translate -1.9*x } object { RightDoor rotate A*y translate 1.9*x } texture { Wrought_Iron } } // // Put it all together here. // //object { GateGround } // The ground //object { GateSky } // The sky //object { GateClouds } // The clouds object { Post translate -(1.95+PostRadius)*x } // The left gate post object { Post translate (1.95+PostRadius)*x } // The right gate post object { IronWork } // The iron work //object { AndGateDragon scale 2.0 translate <0,0,-1> } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.1, 2.2, -12> // Full view // location <0.0, 1.7, -3.0> // 4 Gates // location <-1.1, 2.5, -1.5> // upper-left // location <0.9, 2.4, -1.5> // upper-right // location <-1.1, 0.5, -1.5> // lower-left // location <0.9, 0.5, -1.5> // lower-right // location <0, 2.5, -1> // top 2 // location <0, 0.5, -1> // bottom 2 // location <-1.9, 2.0, -0.5> // upper-left bracket // location <0.8, 2.5, -1> direction <0.0, 0.0, 1.0> // look_at <-2.125,2.8,0> // upper-left bracket // location <0.0, 6, -6> // Full view // look_at <0,2,0> // upper-left bracket } //light_source { <50.0, 40.0, -20.0> colour White *2 } //light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 5.0, -20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } // // Let there be light! // //light_source { <50.0, 90.0, -30> colour White *3 } //light_source { <-50.0, 90.0, -30> colour White } light_source { <200.0, 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P:B¿[Õs|~ñ„vƒë‰5‹^ŒWŒŒÞ‹ŒÓŒsŽW¹ŒöŒƒg¿Œô‹¿Šv‰ˆ¸‡]‡Á…Œ„Pƒr‚éÝ~;}ûzåxwÿt–rJp½mUjÕg7eÃa¢^‘[X©SOYJ7@j©'Ý:`A)GæK“PðT®Xž[_ëb e7h²jÖlŽoýqæs"u•v›wvy"{ý|H~ƒ‰€ü€f²‚¦ƒL„…©„Kƒ„“„’„ý„;…e…Ð……Žƒ‚ƒƒÀ‚#‚Ó¥f€à~ÓzÀsŸYÑÂc!¹2ÞX,m=xŒ„Y‡_‡Ÿ‡»‰ó‰‰Uˆ¥ˆ´ˆ°ˆ1ˆc‡-†Ô„„9„`ƒý€ÍI~§}|z2xÅuês¦rspn!kxDI*NFR¾UY\q^xaÖcåfi2kíl…np3q°r–sÛt9v—wŸxÿxºyz’z{w{Ð{|•{þzzÍxòy>ujp€jpIO.ut 6°í%ÑfÈx³}Õ~~x~ñ~Ô~~I}É|þ|þ{Iz~xMwvâtsþp?olâjªiöge×b#`]¶YôURKNÎI¤D?Ü8-¨ ùêé-˜8Œ<8BÛINWQØT9XÿZk]À_-bOd‹fŽh4j–kmxnWolp¯qÖrt!uµt×t[uÎuªv˜uDu¹kB#& #ÔI ©nå<ßGsH)^õi s®uxŠxgwBvuds r¸pJo>mk2iDge®c€aå^m\þX³U#R&NÓIŸE"@z:½0Á$ã %^ £Ú#Ü*î++S:*NfRìT†S$MàMúNÆW(]bÑerb ^•cÅe_gl_ošo¼oØg `F­._ õù<EVùgNlÇlÊm"l[kvh%h‚fÍd¿c“a‡^]’ZØW¾TYQ´MÀIE@]:‰2g ì ™ CxZ ƒqh¾­  `^( 7íH4LÉ$pRf¡Ÿ$2ˆ*‰,æ-š9Y<ûBýE‚<Ã<„DJOIHóF{BØ<ì2N'ƒŸ  Ý ’ ¿5• Ãtkgate-2.0-b10/povray/text.pov000644 001751 001751 00000040135 10145560353 017045 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // // Designed to be 49x43 (old size 41x35) //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #declare PostRadius = 0.5; // Radius of posts #declare AngleStart = 9; // Start angle of TkGate text #declare AngleSpan = 21.0; // Number of degrees though which to position text #declare AngleStep = -(AngleSpan/8.0); // Number of degrees per letter #declare DrToe1Len = 0.1; #declare DrToe2Len = 0.08; #declare DrToeR = 0.035; #declare DrToeA1 = 20; #declare DrToeA2 = -40; #declare DrThumb1Len = 0.04; #declare DrThumb2Len = 0.04; #declare DrThumbR = 0.04; #declare DrThumbA1 = 5; #declare DrThumbA2 = -20; #declare DrClawStart = 0; #declare DrClawEnd = 0.1; #declare DrClawR = 0.02; #declare ClawText = texture { pigment { color Silver } normal { crackle 0.2 scale 0.2 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .2 } } #declare PlateText = texture { pigment { rgb <.4,0,0> } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } normal { crackle 0.7 scale 0.25 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 1 diffuse 0.6 } } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare GateGround = union { object { SandDunes } object { GrassHill } } // // A texture for wrought iron. // #declare Wrought_Iron = texture { pigment { granite color_map { [0.0 1.0 colour red 0.2 green 0.2 blue 0.2 colour red 0.0 green 0.0 blue 0.0] } } finish { ambient 0 diffuse 0.6 metallic 1} normal { wrinkles 1 scale 0.11 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{ colour red 0.95 green 0.95 blue 0.7 } normal{ granite 0.05 scale 0.24 } finish{phong 0.8 phong_size 200 diffuse 0.4 } } // // The sky // #declare GateSky = sphere { <0.0, 0.0, 0.0>, 3500.0 hollow on pigment { onion colour_map { [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 colour red 0.1 green 0.6 blue 1.0] } quick_colour red 0.7 green 0.7 blue 1.0 scale <6000.0, 1700.0, 4000.0> translate <-1200.0, 220.0, 2500.0> } finish { ambient 0.9 diffuse 0.0 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1; #local L1 = 0.4; // Thiegh length #local L2 = 0.3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.05)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.08)*x translate -(1-FS)*y texture { DragonHide } } translate <0,0.7,0.1> } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,0.2,0.12,0.10,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,0.2,0.1,0.08,0.85) #end #declare AndGateDragon = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } /* object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } */ object { DragonBackLeg(45,100) translate 0.95*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.95*x } object { DragonBackLeg(45,100) translate 0.1*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate 0.1*x } texture { DragonHide } } // // Define the posts that go on the sides of the gate. // #declare Post = union { intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 3.3*y } object { sphere { <0,0,0>, PostRadius } translate 3.8*y } texture { Post_Stone } } #declare SpikeR = 0.2; // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 3.0*y, SpikeR } } merge { object { Sphere scale translate 0.1*y } object { Cone_Y scale translate 0.2*y } object { Cone_Y scale translate 0.025*y } translate 3.0*y } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end #declare DoorBase = union { Spike(1.5) Spike(0.9) Spike(0.3) Wire(0.05,2.75, 1.875,2.75) Wire(0.05,0.5, 1.875,0.5) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <4.0,0.55,0.05> } translate 2.3*y } // // Fence // object { FenceSpike translate 2.6*x } object { FenceSpike translate 2.9*x } object { FenceSpike translate 3.2*x } object { FenceSpike translate 3.5*x } object { FenceSpike translate 3.8*x } } // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } #declare LeftDoor = union { object { DoorBase scale <-1,1,1> } translate 1.9*x } #declare RightDoor = union { object { DoorBase } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.8,0> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.45,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { #local A = 0; object { LeftDoor rotate -A*y translate -1.9*x } object { RightDoor rotate A*y translate 1.9*x } texture { Wrought_Iron } } // // Put it all together here. // //object { GateGround } // The ground //object { GateSky } // The sky //object { GateClouds } // The clouds //object { Post translate -(1.95+PostRadius)*x } // The left gate post //object { Post translate (1.95+PostRadius)*x } // The right gate post //object { IronWork } // The iron work //object { AndGateDragon scale 2.0 translate <0,0,-1> } object { text { ttf "cyrvetic.ttf" "The balrog went to the store to buy apples." 0.25, .5*x } scale 2.2 rotate -60*y translate <-3.5,1,0> texture { Post_Stone} } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.1, 2.2, -6> // Full view direction <0.0, 0.0, 1.0> } // // Let there be light! // //light_source { <50.0, 90.0, -30> colour White *3 } //light_source { <-50.0, 90.0, -30> colour White } light_source { <200.0, 250.0, -250> colour White *3 } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } tkgate-2.0-b10/povray/text.png000644 001751 001751 00000032115 10145512104 017013 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™® 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B“ÈëúÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÇÁ«lH85.&&_¸ìùüÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿü¥YSšÊèøþÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿá‹zzyÐÿÿÿÿÿÿÿÿÿÿÿÿ›j`  :€ÂÁ~LGGGmXXXXZz8)""j~~HTRUEVISION-XFILE.tkgate-2.0-b10/povray/module_del.pov000644 001751 001751 00000006302 10145543054 020167 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Text_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.15 ambient 0.5 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Pencil = union { #local L = 1.7; #local R = 0.15; #local Q = 0.03; #local X = 10; #local D = 0.5; #local E = 0.3; intersection { intersection { box { <0,-R,-R>, } object { box { <0,-R,-R>, } rotate 45*x } texture { Yellow_Paint } } object { cone { <0.0,0,0> , 0, , R*X} texture { T_Wood3} } } intersection { object { cylinder { 0*x, L*x, Q } } object { cone { <-0.01,0,0> , 0, , R*X} } } object { cylinder { L*x, (L+E)*x, R } texture { Erase_Text } } object { cylinder { L*x, (L+E/2)*x, 1.01*R } texture { T_Silver_1A } } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } plane { x, 0 rotate -45*y translate <1.1,1.1,0> } texture { Chip_Text } } intersection { object { box { <-(W-T),-D,-(H-T)>, } } plane { x, 0 rotate -45*y translate <1.1,1.1,0> } texture { Paper_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 2) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end #local Z = -1 + Q + (3/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } rotate x*-90 } union { object { Chip } object { Pencil rotate -35*y rotate 60*z rotate 0*x translate <-0.4, -0.6, -1.4> } rotate y*40 rotate z*-20 } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.0, 0.0, -5.8> look_at <0.0, 0.0, 0.0> } light_source { <-20.0, 10.0, -30> colour White *5 } tkgate-2.0-b10/povray/module_del.png000644 001751 001751 00000020073 10145543057 020153 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®#IDATìÕ1JA‡ñÿ€ÙbŠ¸É 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Pencil = union { #local L = 1.5; #local R = 0.15; #local Q = 0.03; #local X = 10; #local D = 0.5; #local E = 0.3; intersection { intersection { box { <0,-R,-R>, } object { box { <0,-R,-R>, } rotate 45*x } texture { Yellow_Paint } } object { cone { <0.0,0,0> , 0, , R*X} texture { T_Wood3} } } intersection { object { cylinder { 0*x, L*x, Q } } object { cone { <-0.01,0,0> , 0, , R*X} } } object { cylinder { L*x, (L+E)*x, R } texture { Erase_Text } } object { cylinder { L*x, (L+E/2)*x, 1.01*R } texture { T_Silver_1A } } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } object { box { <-(W-T),-D,-(H-T)>, } texture { Paper_Text }} object { text { ttf "cyrvetic.ttf" "ALU32" 0.3, 0 } scale 0.3 rotate 90*x translate <-0.5,0.101,0.0> texture { Ink_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 } union { object { Chip } object { Pencil rotate 100*y rotate 60*z rotate 0*x translate <0.4, -0.0, 0> } rotate y*40 rotate z*-20 } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.0, 0.0, -5.8> look_at <0.0, 0.0, 0.0> } light_source { <-20.0, 10.0, -30> colour White *5 } tkgate-2.0-b10/povray/module_rename.png000644 001751 001751 00000020612 10145561676 020664 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®&IDATìÕAJÃ@‡ñÿ€Í"‹šöBí ,â^ðˆ^ÂSÔ…°PÌbSȃq‹µÝ)^ù~d5“„·ùx 8FÀ€c 8FÀ€c 8FÀ€c 8FÀ€c 8FÀ€c 8FÀ€c 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TRUNK_CURVE_FREQUENCY=3; #declare TRUNK_SNAG=5; #declare TRUNK_SNAG_FREQUENCY=10; #declare TRUNK_SPIRAL=0; #declare TRUNK_TAPER=.5; #declare FIRST_BRANCH_AT_TRUNK=150; #declare BRANCH_AREA_AT_TRUNK=150; //BRANCH #declare BRANCH_THICKNESS_CHANGE=.8; #declare BRANCH_STRENGTH=3; #declare BRANCH_BEND=-40; #declare BRANCH_BEND_FREQUENCY=3; #declare HORIZONTAL_BRANCH_BEND_SWITCH=1; #declare EXTRA_NOISE_SWITCH=1; #declare BRANCH_CURVE=10; #declare BRANCH_CURVE_FREQUENCY=5; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=1; #declare BRANCH_LONGITUDINAL_CURVE=.4; #declare BRANCH_SNAG=5; #declare BRANCH_SNAG_FREQUENCY=-10; #declare BRANCH_REDUCTION=.3; #declare BRANCH_TAPER=.3; #declare BRANCH_END_EQUALIZER=1; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=1; #declare BRANCH_ALTERNATE_SWITCH=0; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=20; #declare BRANCH_ANGLE_SCOPE=0; #declare BRANCH_ALIGNMENT=.8; #declare STRAIGHTEN_TOWARDS_TOP=0; #declare FIRST_TWIG_AT_BRANCH=50; #declare TWIG_AREA_AT_BRANCH=200; //TWIG #declare TWIG_STRENGTH=1; #declare TWIG_THICKNESS_CHANGE=.55; #declare HORIZONTAL_TWIG_ANGLE=40; #declare VERTICAL_TWIG_ANGLE=40; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=0; #declare VERTICAL_TWIG_ANGLE_SCOPE=0; #declare HORIZONTAL_TWIG_ALIGNMENT=.85; #declare VERTICAL_TWIG_ALIGNMENT=.85; #declare TWIG_TURN_SWITCH=1; #declare TWIG_ALTERNATE_SWITCH=0; #declare TWIG_CURVE_ADJUSTMENT=1.1; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=.75; #declare TWIG_TAPER=1; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=3; #declare LAST_RAMIFICATION_NUMBER=5; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=1; #declare FIRST_BUNCH_AT_TWIG=50; #declare BUNCH_AREA_AT_TWIG=200; //BUNCH #declare BUNCH_MAJOR_RADIUS=200; #declare BUNCH_MINOR_RADIUS=50; #declare HORIZONTAL_BUNCH_FUNNEL=0; #declare VERTICAL_BUNCH_FUNNEL=0; #declare ROTATION_BUNCH_FUNNEL=80; #declare HORIZONTAL_BUNCH_ANGLE=40; #declare VERTICAL_BUNCH_ANGLE=-35; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=0; #declare VERTICAL_BUNCH_ANGLE_SCOPE=0; #declare BUNCH_TURN_SWITCH=1; #declare BUNCH_TURN_SHIFT=0; #declare BUNCH_ALTERNATE_SWITCH=0; #declare HORIZONTAL_BUNCH_ALIGNMENT=.85; #declare VERTICAL_BUNCH_ALIGNMENT=.85; #declare BUNCH_TAPER_OFF_AT_TWIG=.3; #declare BUNCH_TAPER_OFF_AT_BRANCH=0; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=LEAF #declare LEAF_LENGTH=15; #declare LEAF_BREADTH=4; #declare LEAF_HEIGHT=2; #declare MAX_LEAF_TILT=20; #declare MAX_LEAF_TURN=30; #declare LEAF_INCLINATION=40; #declare LEAF_INCLINATION_SCOPE=30; //BLOSSOM #declare BLOSSOM=BLOSSOM2 #declare BLOSSOM_LENGTH=15; #declare BLOSSOM_WIDTH=30; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<1,1,1>; //ROOT #declare FIRST_ROOT_AT_TRUNK=70; #declare ROOT_LENGTH=200; #declare ROOT_THICKNESS_CHANGE=.7; #declare ROOT_STRENGTH=3; #declare ROOT_BEND=50; #declare ROOT_BEND_FREQUENCY=1; #declare ROOT_CURVE=15; #declare ROOT_CURVE_FREQUENCY=5; #declare ROOT_SNAG=5; #declare ROOT_SNAG_FREQUENCY=20; #declare ROOT_TURN_SWITCH=1; #declare ROOT_ANGLE=45; #declare ROOT_ALIGNMENT=.25; //BARK #declare SUNKEN_TRUNK_COLOR=<-.2,-.2,-.2>; #declare RAISED_TRUNK_COLOR=<0.5,0.3,0>; #declare FOLIAGE_COLOR_AT_BRANCH_END=1; #declare TRUNK_SCAR_WIDTH=8; #declare TRUNK_SCAR_HEIGHT=24; #declare HORIZONTAL_SCAR_SHRINKING=.3; #declare VERTICAL_SCAR_SHRINKING=1.5; #declare SCAR_DEPTH=-1; #declare PALM_TRUNK=0; #declare BARK_PROFILE=.95; #declare BRANCH_BARK_PROFILE_CHANGE=.95; #declare BRANCH_BARK_PROFILE_TAPER_OFF=1; #declare ROOT_BARK_PROFILE_CHANGE=.9; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.5,0.3,0.1>; #declare BOTTOM_COLOR_2=<0.4,0.5,0.2>; #declare TOP_COLOR_1=<0.5,0.5,0>; #declare TOP_COLOR_2=<.3,0.5,0.3>; #declare COLOR_TURB=.5; #declare TRANSITION_BOTTOM_TOP=0.5; #declare TRANSITION_TURB=.5; #declare FOLIAGE_GLOSS=0.25; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX tkgate-2.0-b10/povray/tomtree.txt000644 001751 001751 00000102000 07065625772 017557 0ustar00hansenhansen000000 000000 TOMTREE - Treegenerator for POVRAY version MAR.2000 by Tom Aust Aust-Anfertigungen www.aust-anfertigungen.de ___________________________________________________________________________ The tomtree.zip archive contains: ___________________________________________________________________________ TOMTREE.inc This is the generator. After copying it into your include-file path there is no reason to touch it. The settings will be made in seperate inc-files for each different trees. TOMLEAF.inc Here are some leaves, simple leaves and better height_field leaves. To keep tomtree.zip quite small I've added only a few variations of one typical HF-leaf and one HF-blossom. TESTTREE.inc This is a settINC to try, watch and learn what happens after changing the values. Now the values make a very straight, rather empty tree for better observation what's going on. BIRCH.inc An example settINC. OLIVE.inc Another example settINC. PALM.inc A third example settINC. TREE.pov A simple scene file to show how to use TomTree in your scene. If you want trees of DIFFERENT kind in your scene you should add both, the other settINC and - again - tomtree.inc. (The camera is adjusted in a ratio of 1 to 1) LEAF.tga Source-image for the HF-leaves in tomleaf.inc. LEAF.gif Source-image for the texture for the leaves "...LEAF_tex". If you use these own-textured leaves the global "FOLIAGE_COLOR" shows no effect and each leaf has the same texture. LEAFx.tga This is the source-image for cutting out the HF-leaf in a natural shape. BLOSSOM.tga Source-image for the HF-blossoms in tomleaf.inc. tomtree.txt This file. Below I will try to explain each option of the settINCs. __________________________________________________________________________________ __________________________________________________________________________________ TRIAL OF AN EXPLANATION __________________________________________________________________________________ __________________________________________________________________________________ Tomtrees have a TRUNK ROOTS at the trunk, BRANCHES at the trunk, TWIGS at the branches, BUNCHES at the twigs, and these bunches are made of TWIG_RAMIFICATION, LEAVES and BLOSSOMS. Although the TWIG_RAMIFICATION belongs structural to the wooden part of the tree it will be handled with the bunch, like the leaves. Each bunch has one TWIG_RAMIFICATION. The long measures of the parts of the tree are in relationship to each other. So, I recommend you think about a real tree with its real longmeasures and set the values perhaps in centimeter so the unit is good for the leaves as well as for the whole tree. Regardless of the unit you will choose, TomTree scales down every tree to 1 unit at the end of calculation, so that in your scenefile you can scale it up to your request. About the options: __________________ ___________________________________________________________________________________ // T R E E ___________________________________________________________________________________ BRANCHES Set the number of all branches at the tree. TWIGS Set the number for the twigs at a branch; multiplied by the number of branches results in all twigs at the tree. BUNCHES Set the number for the bunches at a twig; multiplied by all twigs results in all bunches at the tree. LEAVES Set the number for the leaves in a bunch; multiplied by all bunches results in all leaves at the tree. BLOSSOMS Set the number for the blossoms in a bunch; multiplied by all bunches results in all blossoms at the tree. ROOTS Set the number of all roots at the tree. BRANCH_RANDOM Any different value results in a different branch-arrangement of the same kind of tree. TWIG_RANDOM And if you are not satisfied with the arrangement of twigs at the branch, play here. ROOT_RANDOM The same possibility for the roots. ___________________________________________________________________________________ // T R U N K (Mathematical trunk-length: FIRST_BRANCH_AT_TRUNK + BRANCH_AREA_AT_TRUNK + mathematical branch-length) ___________________________________________________________________________________ TRUNK_RADIUS This, of course, is the radius of the trunk to determine its thickness. TRUNK_STRENGTH Decreasing this value saves parsingtime, increasing is needed if the trunk falls in pieces (in the case of very long trunk or/and very wide bend). It's a factor and 1 is a normal value. TRUNK_BEND_X TRUNK_BEND_Z In connection with the following TRUNK_CURVE and TRUNK_SNAG with their frequencies you have the chance of interlocked, irregular forming of the trunk. Play with their combinations. There are seperate values for the trunk-bend in the two lateral directions (X,Z). TRUNK_BEND_X/Z gives the width of the outer bend of the trunk, probably with about 1 or 2 archs (TRUNK_BEND_X/Z_FREQUENCY). TRUNK_BEND_X/Z has usually a higher value than TRUNK_CURVE, and TRUNK_CURVE is usually wider than TRUNK_SNAG. Then, by the way of contrast, TRUNK_BEND_X/Z_FREQUENCY should be smaller than the TRUNK_CURVE_FREQUENCY, which should be smaller than TRUNK_SNAG_FREQUENCY. TRUNK_BEND_X_FREQUENCY TRUNK_BEND_Z_FREQUENCY I have mentioned, TRUNK_BEND_X/Z_FREQUENCY is the number of outer arches of the trunk. You may set different values for the two lateral directions. TRUNK_CURVE It's the width of the inner bend of the trunk. Inside the outer bend, you have set with TRUNK_BEND_X/Z, you have a higher number (TRUNK_CURVE_FREQUENCY) of inner curve. TRUNK_CURVE_FREQUENCY Here you set the number of inner curves of the trunk. TRUNK_SNAG Inside the inner bend, here you set the width for the smallest bend, the snag. TRUNK_SNAG_FREQUENCY And the number of snags in the trunk. TRUNK_SPIRAL Additional to the bend of the trunk it's angle-value for a corkscrew looking trunk. 360 = one turn. TRUNK_TAPER Here you adjust how much the trunk tapers off towards its top-end. Example: 0 = trunk-top has the same thickness as the trunk-base. 1 = the trunk-top-end has no thickness and this is the mathematical top-end of the whole tree. Nevertheless the trunk is cut at the highest branch. FIRST_BRANCH_AT_TRUNK This is the distance from the base of the trunk (the ground) to the lowest/first branch at the tree. BRANCH_AREA_AT_TRUNK This is the distance between the lowest/first and the highest/last branch at the trunk. __________________________________________________________________________________ // B R A N C H (Mathematical branch-length: FIRST_TWIG_AT_BRANCH + TWIG_AREA_AT_BRANCH + mathematical twig-length) ___________________________________________________________________________________ BRANCH_THICKNESS_CHANGE The thickness of the branch depends on the thickness of the trunk, given by TRUNK_RADIUS. Here you can adjust the branch-thickness. It's a factor, so, 1 means that the branch-base has the same thickness as the trunk at this point. BRANCH_STRENGTH As for the trunk, decreasing this value saves parsingtime, increasing is needed if the branches fall in pieces (in the case of very long branches or/and very wide bend). It's a factor and 1 is a normal value. 0 makes the branches invisable (unlike to the BRANCH_NUMBER, 0 doesn't switch off following twigs, bunches and leaves). BRANCH_BEND In connection with the following BRANCH_CURVE and BRANCH_SNAG with their frequencies you have the chance of interlocked, irregular forming of your branches. Play with their combinations. BRANCH_BEND gives the width of the outer bend of the branch, probably with about 1 or 2 archs (BRANCH_BEND_FREQUENCY). BRANCH_BEND has usually a higher value than BRANCH_CURVE, and BRANCH_CURVE is usually wider than BRANCH_SNAG. Then, by the way of contrast, BRANCH_BEND_FREQUENCY should be smaller than the BRANCH_CURVE_FREQUENCY, which should be smaller than BRANCH_SNAG_FREQUENCY. BRANCH_BEND_FREQUENCY I have mentioned, BRANCH_BEND_FREQUENCY is the number of outer arches of the branch. HORIZONTAL_BRANCH_BEND_SWITCH Switch off (0) the main horizontal bend if you only want a vertical bend (perhaps the branch should grow at a wall). Otherwise the value is 1. Nevertheless other values are possible. For example, if you set 1.5, the horizontal bend is 50 percent wider than the vertical bend. EXTRA_NOISE_SWITCH Default is 1; Sometimes it's annoying, if you need more regular arcs in the branch, for example at the palmtree in PALM.inc. In this case set the value to 0 in order to switch this additional noise off. It only affects the BRANCH_BEND and twig-bend. BRANCH_CURVE It's the width of the inner bend of the branch. Inside the outer bend (BRANCH_BEND), you have a higher number (BRANCH_CURVE_FREQUENCY) of inner curve. BRANCH_CURVE_FREQUENCY Here you set the number of inner curves of the branch, as I've said above. HORIZONTAL_BRANCH_CURVE_SWITCH Like the HORIZONTAL_BRANCH_BEND_SWITCH 0 switches off the horizontal curve. BRANCH_LONGITUDINAL_CURVE An additional value for less or more lengthwise branch-irregularity. Examples: 0 = no lengthwise curve; 1=equal to lateral direction. BRANCH_SNAG It's the width for the innermost bend of the branch. Inside the inner bend, here you set the width for the smallest bend, the snag. BRANCH_SNAG_FREQUENCY And, of course, the number of snags at the branch. BRANCH_REDUCTION Towards the top of the tree usually the branches become smaller. Here is the value to adjust this. Examples: 0 = no reduction; 0.5 = the highest branch at the tree has about the half size from the lowest. The twigs and bunches of the branch will be reduced too towards the top of tree. If you want that the bunches with their leaves keep their size you can set a corresponding negative value for BUNCH_TAPER_OF_AT_TREE. BRANCH_TAPER Here you adjust how much the branch tapers off towards its end. Example: 0 = branch-end has the same thickness as the branch-base. 1 = the branch-end has no thickness. The twigs and bunches of the branch will be reduced towards the branch-end too. If you want that the bunches with their leaves keep their size you can set a corresponding negative value for BUNCH_TAPER_OF_AT_BRANCH. BRANCH_END_EQUALIZER It's not noticable if the TWIG_THICKNESS (TWIG_THICKNESS_CHANGE) is set to the same value as the BRANCH_THICKNESS. But if the twigs are set to be more thin than the branches and you set the BRANCH_END_EQUALIZER to 1 the branch will adapt to the same thickness as the last twig towards the end of the branch. This feature only works if the following BRANCH_TIP is 0. BRANCH_TIP BRANCH_TIP adjusts how long the branch will be continued after its last twig. For example, 0 means that the branch ends at its last/outermost twig (with the thickness of this twig). 1 = the branch ends at its mathematical end. BRANCH_TURN_SWITCH To switch on (1) or off (0) the random rotation of the branch around its longitudinal axis. BRANCH_ALTERNATE_SWITCH To switch on (1) the reciprocal position of the branches at the trunk. If it's set to 0, the branches rotate randomly around the trunk. BRANCH_SPIRAL Additional to the bend of the branch it's angle-value for a corkscrew looking branch. 360 = one turn. BRANCH_ANGLE This is the start-angle for the first/lowest branch at the trunk. 0 means that the lowest branch arises from the trunk in horizontal direction. Values greater than 0 result in upwards inclination. BRANCH_ANGLE_SCOPE For more irregularity this is a random oscillation-scope (angle) for each branch. BRANCH_ALIGNMENT After setting the angle for the lowest/first branch at the tree normally the branches towards the top of the tree align with the trunk (value = 1). Here you can change this alignment. For example 0 means, that there is no alignment and all branches have the same angle as the lowest branch. STRAIGHTEN_TOWARDS_TOP IF you have set a bend for your branches, but want to straighten them towards the top of the tree increase this value. 0 = no straightening; 1 = the highest branch is straight. FIRST_TWIG_AT_BRANCH This is the distance from the branch-base at the trunk to the first twig at the branch. TWIG_AREA_AT_THE_BRANCH The distance between the first and the last twig at the branch. ___________________________________________________________________________________ // T W I G (Mathematical twig-length: FIRST_BUNCH_AT_TWIG + BUNCH_AREA_AT_TWIG + mathematical bunch-length) ___________________________________________________________________________________ TWIG_STRENGTH The normal value is 1. If you have many twigs and want to decrease parsingtime you may try to decrease this value until the twigs fall in pieces. If you have very long twigs, and therefore the twigs fall in pieces, than increase the value for TWIG_STRENGTH (increases parsingtime too). If you don't need twigs but want to have leaves, set this value to 0. TWIG_THICKNESS_CHANGE The thickness of the twig depends on the thickness of the branch (the branch-thickness itself depends on the TRUNK_RADIUS). Here you can change the thickness of the twig with a factor. So, 1 = the base of the twig has the same thickness as the branch at this point. 0.5 = the base of the twig has the half of the size as the branch at this point. HORIZONTAL_TWIG_ANGLE It's the angle of the twig to the branch in horizontal direction. VERTICAL_TWIG_ANGLE And for the vertical direction. HORIZONTAL_TWIG_ANGLE_SCOPE In addition to the HORIZONTAL_TWIG_ANGLE this is a scope for a random oscillation of the angle for each twig at the branch. VERTICAL_TWIG_ANGLE_SCOPE And the scope for the VERTICAL_TWIG_ANGLE. HORIZONTAL_TWIG_ALIGNMENT If it is 0, than all twigs at the branch keep the angle which is determined by the HORIZONTAL_TWIG_ANGLE. If it is 1 for example, than this angle decreases with each twig towards the branch-end and the last twig at the branch is aligned with the branch. VERTICAL_TWIG_ALIGNMENT And the same for the vertical direction. TWIG_TURN_SWITCH To switch on (1) or off (0) the random rotation of the twig around its own longitudinal axis. TWIG_ALTERNATE_SWITCH If it's 0, than the twigs rotate automatically around the branch in a random manner. If it's 1, the twigs have a reciprocal horizontal direction with the given HORIZONTAL_ and VERTICAL_TWIG_ANGLE (like the leaves at the palmtree). TWIG_CURVE_ADJUSTMENT The bend, curve and snag of the twigs depend on the bend, curve and snag of the branches. Here you can increase or decrease it for the twigs. 1 = the same bend, curve and snag as for the branches. 0 = straight twigs. TWIG_CURVE_FREQUENCY_ADJUSTMENT To adjust the number of bends, curves and snags at the twig which depends on the branch. 1 = the same number of bends curves and snags at the twig. TWIG_TAPER 1 is the default and the twig ends in a tip. The lower this value the thicker the twig-end will be. With 0 you get the same thickness at the start and end of the twigs (what for?) TWIG_TIP Here you can lengthen or shorten the twig after the last bunch at the twig. 0 = the twig ends at the last bunch-base. Up to 1, which lengthen the twig up to the outermost leaf. STRAIGHTEN_TOWARDS_BRANCH_END Like the STRAIGHTEN_TOWARDS_TOP for the branches it's the straightening of the twigs towards each branch-end. TWIG_RAMIFICATION_ORDER Here you may set an additional ramification. It's a repetition of the twig (1. order), which may have a repetition itself (2. order) and a repetition at the repetition at the repetition (3. order) at the twigs. The size, orientation and quantity will be controlled by the bunches. There are 4 possible values for TWIG_RAMIFICATION_ORDER: 0 = no additional twig-ramification; 1 = each bunch gets a twig-ramification of 1. order (a twig-repetition) at the twig. 2 = each bunch gets a twig-ramification of 2. order at the twig. 3 = each bunch gets a twig-ramification of 3. order at the twig. (To create a very ramified tree doesn't need too much parsingtime because it doesn't need too many original branches and twigs to be calculated.) LAST_RAMIFICATION_NUMBER It's the number of 2.order-twig-ramifications at the 1.order-twig-ramification and also the number of 3.order-twig-ramis at each 2.order-twig-rami. So, for example, it is set to 4, than you have for each bunch one 1.order-rami, four 2.order-ramis and sixteen 3.order-ramis. TWIG_RAMIFICATION_THICKNESS_CHANGE Because the size of the twig-ramifications is controlled by the bunches it may be that the thickness of the twig-ramification must be adjusted here. It's a factor, so, 1 means no change of the thickness. TWIG_RAMIFICATION_CURVE_ADJUSTMENT This is for the ramis, the same as for the twigs with TWIG_CURVE_ADJUSTMENT. RAMI_CURVE_FREQUENCY_ADJUSTMENT This is for the ramis, the same as for the twigs with TWIG_CURVE_FREQUENCY_ADJUSTMENT. TWIG_RAMIFICATION_STRENGTH To save parsingtime decrease this value until the twig-ramification falls in pieces. If the twig-ramification falls in pieces increase this value. (Like for the twigs with TWIG_STRENGTH, for the branches with BRANCH_STRENGTH, for the trunk with TRUNK_STRENGTH and for the roots with ROOT_STRENGTH.) FIRST_BUNCH_AT_TWIG This is the distance from the base of the twig at the branch to the first bunch at the twig. BUNCH_AREA_AT_TWIG This is the distance between the first and last bunch at the twig. ___________________________________________________________________________________ // B U N C H Unlike the trunk, the root, the branch, the twig, the twig-ramification, the leaf or blossom the bunch is not a real element of the tree but only a combination of one twig-ramification and a partial quantity of the leaves and blossoms. (Mathematical bunch-length: BUNCH_MAJOR_RADIUS + BUNCH_MINOR_RADIUS + leaf-length) ___________________________________________________________________________________ BUNCH_MAJOR_RADIUS This is the distance from the bunch-base at the twig to the innermost leaf in the bunch. BUNCH_MINOR_RADIUS This is the distance between the innermost and outermost leaf in the bunch. HORIZONTAL_BUNCH_FUNNEL The bunch fans out up to this angle (degree) in horizontal direction. VERTICAL_BUNCH_FUNNEL And the oscillation between this angle in vertical direction. ROTATION_BUNCH_FUNNEL If you set here an angle (degree) greater than 0 the HORIZONTAL_BUNCH_FUNNEL and the VERTICAL_BUNCH_FUNNEL will be switched off and the leaves will turned around the longitudinal bunch-axis after the bunch fans out up to the given angle. So, for example if a value of 180 is set the leaves in the bunch describe a half- sphere. In this funneltype the leaves are placed in concentrical direction. Unlike this the HORIZONTAL_ and VERTICAL_BUNCH_FUNNEL lets fan out the leaves by keeping the direction of each leaf. (All three funnels determine, how much the twig-ramification will be spread out) HORIZONTAL_BUNCH_ANGLE The horizontal fixed angle of the first bunch at the twig to the twig. VERTICAL_BUNCH_ANGLE The vertical fixed angle of the first bunch at the twig to the twig. (Remember, the bunch contains the twig-ramification, so, it's the inclination-angle for the twig-ramification too.) HORIZONTAL_BUNCH_ANGLE_SCOPE This is the oscillation scope as addition to the HORIZONTAL_BUNCH_ANGLE for more irregularity among the bunches. VERTICAL_BUNCH_ANGLE_SCOPE And the additional oscillation scope for the VERTICAL_BUNCH_ANGLE. BUNCH_TURN_SWITCH To switch on (1) or off (0) the rotation of the bunch around the twig after the HORIZONTAL_ and/or VERTICAL_BUNCH_ANGLE. Each bunch has its own random value of rotation around the twig. BUNCH_TURN_SHIFT Although the bunches will turn around the twig after the BUNCH_TURN_SWITCH is on (1), the BUNCH_TURN_SHIFT determines if the leaves keep their upside up (1) or not (0). BUNCH_ALTERNATE_SWITCH In addition to the fixed HORIZONTAL_ and VERTICAL_BUNCH_ANGLE you can switch on (1) or off (0) the reciprocal directions of the bunches (like the leaves at the palmtree; in this example each bunch has one leaf). HORIZONTAL_BUNCH_ALIGNMENT If this value is set to 0 each bunch at the twig hold the angle to the twig you have set with the HORIZONTAL_BUNCH_ANGLE. If it is set to 1 the bunches decrease their angle to the twig towards the twig-end, so that the last bunch at the twig is aligned with the twig. You may use other values. Perhaps you have a HORIZONTAL_BUNCH_ANGLE of 90 (degrees) and set the HORIZONTAL_BUNCH_ALIGNMENT to 0.5 the last bunch at the twig has an angle of 45° towards the twig. VERTICAL_BUNCH_ALIGNMENT The same for the VERTICAL_BUNCH_ANGLE and the alignment towards twig. BUNCH_TAPER_OFF_AT_TWIG This makes the bunches smaller towards the twig-end if the value is greater than 0. 0 = same size for all bunches at the twig. 0.5 = the last bunch at the twig has the half size of the first one. 1 = the size of the last bunch at the twig goes to 0. BUNCH_TAPER_OFF_AT_BRANCH The same for the size-reduction of the bunches at the branch towards the branch-end. This has no effect to the twigs and branches, so it's often better to adjust the taper-off at the branches with BRANCH_TAPER. Than you have the possibility to set a negative value for the balance against the BRANCH_TAPER. BUNCH_TAPER_OFF_AT_TREE And, of course, the same for the size-reduction of the bunches towards the top of the tree. This has no effect to the twigs and branches, so it's often better to adjust the taper-off at the tree with BRANCH_REDUCTION. Than you have the possibility to set a negative value for the balance against the BRANCH_REDUCTION. BUNCH_ARC_AT_TWIG Normally tomtree lets shrink the bunches towards the twig-end in a linear manner. BUNCH_ARC_AT_TWIG is an additional factor of the given size value (BUNCH_MAJOR_RADIUS+ BUNCH_MINOR_RADIUS+LEAF_LENGTH) in x,y,z direction. If BUNCH_ARC_AT_TWIG is <0,0,0> there is no change. <2,0.5,1> for example says that the innermost bunch at the twig starts with the given size, then towards the middle of the BUNCH_AREA_AT_TWIG the bunch-size increases to the triple length (x), is 1.5 times higher (y), and has the double size of breadth. Then, the outermost bunch at the twig has the given size again with its normal shrinking. BUNCH_ARC_AT_BRANCH The same for the non-linear size-changing of the bunches along the branch. BUNCH_DEFORM I'm not sure if this is a real useful point?! It's for an additional distortion of the whole bunch. The values for the -factor (the longitudinal bunch-axis is the x-axis). But the leaves, blossoms and twig-ramification will be distorted too. Up to now I've never used it. ___________________________________________________________________________________ // L E A F ___________________________________________________________________________________ #include "TOMLEAF.INC" This is the source for the LEAF_TYPE. In TOMLEAF.INC are some simple leaves and some variations of a height_field leaf and a height_field blossom. I preferr the HF-leaves(blossoms), because of much more realistic shape without increasing parsing- and rendertime too much. If the amount of leaves goes beyond your RAMsize you better select a non-CSG leaftype. Of course, TOMLEAF.inc contains only a few examples in order to keep the downloadsize of TOMTREE.zip rather small. LEAF_TYPE The name of the leaf you have specified in your (TOM)LEAF.INC above. LEAF_LENGTH I have said it, I think it's the best way to think in real-life measure like cm. So a typical LEAF_LENGTH could be 10 (cm). There is a built-in scope of length. LEAF_BREADTH The width of the leaf, with a built-in scope. LEAF_HEIGHT It means the height of the arch the leaves describe. For normal leaves it may be not too high, but palmleaves for example should be not so straight. MAX_LEAF_TILT For the swinging irregularity of the leaves at the tree I have built in an oscillation. MAX_LEAF_TILT means this oscillation of turn around the longitudinal leaf-axis. MAX_LEAF_TURN The same for the oscillation of turn around the axis of leaf-height. LEAF_INCLINATION Before you set the oscillation of leaves around the lateral axis in the next point (MAX_INCLINATION_SCOPE) here you can set a fixed inclination, a turn around the lateral axis of the leaves or inclination to the longitudinal axis (perhaps you want all leaves in a bunch are hanging down). MAX_INCLINATION_SCOPE And, as I said, the oscillation of inclination added to the fixed inclination. __________________________________________________________________________________ // B L O S S O M ___________________________________________________________________________________ BLOSSOM The name of blossom you find in TOMLEAF.INC or your own LEAF.INCs. BLOSSOM_LENGTH Or height; the length of the blossom along its longitudinal axis. BLOSSOM_WIDTH This is the value for the lateral extension. BLOSSOM_INCLINATION Like the LEAF_INCLINATION it's a fixed inclination to the longitudinal axis. BLOSSOM_COLOR Set the RGB-values for your blossoms (perhaps there will be a better texturing in the future). ___________________________________________________________________________________ // R O O T ___________________________________________________________________________________ FIRST_ROOT_AT_TRUNK This is the distance from the trunk-base (the ground) to the uppermost root at the trunk. ROOT_LENGTH Unlike the twig, branch, trunk the root mustn't show consideration for any ramification and therefore you can set directly a length for the root. ROOT_THICKNESS_CHANGE The root-thickness depends on the thickness of the trunk, which is determined with the TRUNK_RADIUS. With ROOT_THICKNESS_CHANGE as a factor you adjust the root-thickness. So, 1 means that the root has at its base the same thickness as the trunk at this point. Or, for example, 0.5 = half thickness of the trunk. ROOT_STRENGTH As for the twigs(-ramis), branches and trunk, decreasing this value saves parsingtime, increasing is needed if the roots fall in pieces (in the case of very long roots or/and very wide bend). It's a factor and 1 is a normal value. 0 switches off the roots. ROOT_BEND And once more again: In connection with the following ROOT_CURVE and ROOT_SNAG and their frequencies you have the chance of interlocked, irregular forming of your roots. Play with the combinations. ROOT_BEND gives the width of the outer bend of the root, probably with about 1 or 2 archs (ROOT_BEND_FREQUENCY). ROOT_BEND has usually a higher value than ROOT_CURVE which has usually a higher value than ROOT_SNAG. Then, by the way of contrast, ROOT_BEND_FREQUENCY should be smaller than the ROOT_CURVE_FREQUENCY,... ROOT_BEND_FREQUENCY It's the number of outer arches of the root. ROOT_CURVE It's the width of the inner bend of the root. ROOT_CURVE_FREQUENCY It's the number of inner arches of the root. ROOT_SNAG Inside the inner bend, here you set the width for the innermost bend, the snag. ROOT_SNAG_FREQUENCY And the number of snags in the root. ROOT_TURN_SWITCH To switch on (1) or off (0) the random rotation of each root around its own longitudinal axis. ROOT_ANGLE This is the start-angle for the first/highest root at the trunk. 0 means that the first/highest root arises from the trunk in horizontal direction. Values greater than 0 result in downwards inclination. ROOT_ALIGNMENT If it is 0, than all roots have the same angle as it is determined by the ROOT_ANGLE. If it is 1 for example, than the last/lowest root points vertical downwards. ___________________________________________________________________________________ // B A R K ___________________________________________________________________________________ SUNKEN_TRUNK_COLOR RAISED_TRUNK_COLOR To simulate the bark, here you have two colors, may be light and dark. For example, for the bark of a birch (it's more a grain than a bark) it could be <1,1,1> and <0,0,0>. FOLIAGE_COLOR_AT_BRANCH_END If this point is switched on (1), the color of the bark (determined through the previous points) changes smoothly into the FOLIAGECOLOR towards the branch-end. Where the transition happens is determined with the following HORIZONTAL- and VERTICAL_SCAR_SHRINKING. TRUNK_SCAR_WIDTH TRUNK_SCAR_HEIGHT Typically the bark has a vertical direction, so the value for TRUNK_SCAR_HEIGHT is greater than the value for TRUNK_SCAR_WIDTH. But if we look at the grain of the birch again it shows a horizontal direction with the higher value for the TRUNK_SCAR_WIDTH. HORIZONTAL_SCAR_SHRINKING I have built in an automatically shrinking of the scar outwards to the whole tree. So the values for TRUNK_SCAR_WIDTH and TRUNK_SCAR_HEIGHT are mainly for the trunk. Towards the branchends the scar becomes smaller and smaller. This shrinking area discribes an halfsphere if HORIZONTAL_SCAR_SHRINKING is 1. This is good for a tree which are nearly spherical itself, but if you want to create a long, thin tree you may adjust the lateral shrinking by setting a lower value. So, for example 0.5 lets happen the lateral shrinking twice as fast as the shrinking towards the top of the tree. VERTICAL_SCAR_SHRINKING In addition to the previous point you can stretch the shrinking in vertical direction. SCAR_DEPTH In addition to the last points for the grain of the bark SCAR_DEPTH is a value for a normal, which simulates a three-dimensional appearance with the same width, height and turbulence as the grain has. PALM_TRUNK Look at the palmtree. It has a "real" bark in horizontal direction. 1 produces a very gnarled horizontal oriented bark (Use also the TRUNK_STRENGTH to influence the appearance). 0 disables the palm-trunk-bark. The birch for example, has a little PALM_TRUNK-value too which reduces the smooth appearance. If you want a "real" bark in vertical direction you find the possibility in the next point. In this case PALM_TRUNK must be set to 0, otherwise the following BARK_PROFILE is disabled for the trunk. BARK_PROFILE PALM_TRUNK must be 0 to enable this feature for the trunk. In addition to the TRUNK_COLORs and SCAR_DEPTH the BARK_PROFILE is a "real" bark. Use also the TRUNK_STRENGTH to influence the appearance. If you have a full BARK_PROFILE-value of 1 it may be necessary to increase the TRUNK_STRENGTH (perhaps up to 5 or more). BRANCH_BARK_PROFILE_CHANGE It depends on BARK_PROFILE for the trunk and allows to adjust the influence on the branches. It's a factor and if the value is 1 the branches have the same BARK_PROFILE as the trunk (in this case I fear you have to increase the BRANCH_STRENGTH, may be up to 5 or more). In any case the amount of BARK_PROFILE decreases automatically towards the end of the branches. BRANCH_BARK_PROFILE_TAPER_OFF AS I said above, the BARK_PROFILE for the branch decreases automatically towards its end. To change where this transition should happen you may increase or decrease this value. Default is 1. ROOT_BARK_PROFILE_CHANGE It depends on BARK_PROFILE for the trunk and allows to adjust the influence on the roots. It's a factor and if the value is 1 the roots have the same BARK_PROFILE as the trunk. (I think you have to increase the ROOT_STRENGTH too). __________________________________________________________________________________ // F O L I A G E C O L O R ___________________________________________________________________________________ BOTTOM_COLOR_1 BOTTOM_COLOR_2 Choose two RGB-values for the play of colors in the lower region of the foliage. TOP_COLOR_1 TOP_COLOR_2 Choose two RGB-values for the play of colors in the upper region of the foliage. COLOR_TURB Set the turbulence for the play of foliage-colors in lower and upper regions. TRANSITION_BOTTOM_TOP This value determines in which height the lower colors and thus the transition to the upper colors take place. The TOP_COLORs take place at the top of the tree anyway. If the center of the BOTTOM_COLORs should be at the bottom/origin (the ground) of the tree the TRANSITION_BOTTOM_TOP-value should be 0. If the center of the BOTTOM_COLORs should be in the middle of the tree than set 0.5, and so on... TRANSITION_TURB To avoid a straight transition of BOTTOM_- and TOP_COLORs you may increase the TRANSITION_TURB. It's a turbulence as you know it. FOLIAGE_GLOSS It's a phong-value to get less or more glossy leaves. _________________________________________________________________________________________ I hope my English is not too bad and you will enjoy Tomtree! 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.6 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { // metallic specular .6 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.3 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Pencil = union { #local L = 1.5; #local R = 0.15; #local Q = 0.03; #local X = 10; #local D = 0.5; #local E = 0.3; intersection { intersection { box { <0,-R,-R>, } object { box { <0,-R,-R>, } rotate 45*x } texture { Yellow_Paint } } object { cone { <0.0,0,0> , 0, , R*X} texture { T_Wood3} } } intersection { object { cylinder { 0*x, L*x, Q } } object { cone { <-0.01,0,0> , 0, , R*X} } } object { cylinder { L*x, (L+E)*x, R } texture { Erase_Text } } object { cylinder { L*x, (L+E/2)*x, 1.01*R } texture { T_Silver_1A } } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } object { box { <-(W-T),-D,-(H-T)>, } texture { Paper_Text }} object { text { ttf "cyrvetic.ttf" "NEW" 0.3, 0 } scale 0.3 rotate 90*x translate <-0.3,0.101,0.0> texture { Ink_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 } union { object { Chip } rotate y*40 rotate z*-20 } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.0, 0.0, -5.8> look_at <0.0, 0.0, 0.0> } light_source { <-20.0, 10.0, -30> colour White *5 } tkgate-2.0-b10/povray/module_new.png000644 001751 001751 00000016332 10145562764 020211 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®&IDATìÕÁJ1€áÙ®«kܮЪˆøþoá žñ X¥ÐK&˜@<¬õb=‰–)ÿGN sù Ž0àŽ0àŽ0àŽ0àŽ0àŽ0àŽ0à»7~—]Ï‚ÿv°ëð+¥”ÙíL_Õ®,Ÿf»´r;³c1#‘@UiE<6æ€4¾]` Øt¿ÃäˆÉ¬@ @ޗ劌 ¬¨eGl“˜†`˜M˱ÜÁsŸƒ‚  Ç©äóp5o··ÅB¬x\ëé1 S–Å7—kÖ iÿ+ö*ðx ¼Þ5¿ä¸4›xê¨@©@ň(GdDa – Óvlu_5öy²ÂòòrÐcà@TÓ^¶µ%í¿ww_\,T*¯·¶ºb±r¥ok«X»r_-HŽ}Ε$@nYà €m€^ý,pK¤Ú<¶BüžWŽÐHq¾øð‡‡ïWߧr© ìB“Þ+Î!<‡ïOšç§§‹óób©4(IYEébì@à—·±wù@¤oïOã ,üÖ=V™øybêþ–d£FS¹ÅM… jeþ°½½¶²¢½zÅ67ã=Yõ—Z¨üéÈàSdöÿÔõ L0&ŒyÏ}0Ú?ÒÏn|+ÔÞúrggÇ¥KnþI V§š:ši/€/=õUÿÚò‘ °ÕéÕº³yn6\à–Á5ÁqœÞRº6W|ë Gñ7?øgª7y>$•K±$;»áKø~àƒý˨F}Ë¿AQ‡üdÞÛß?ÒÌÀÎ\àVÂqyVöÙÛÜhˆÏÞºü™%ÙÍ‘›<n6\ࣶMþöûivý¿©&îNxû/&/òüù à·òœ'üž?{Âo©X*̼ý<>¸À-CmûB?ûÃïêLýüóðØ0ÏŸÏ.p`|îЉ›¢øV EøU}áÀÔ¯¾ùçá±áFu.áËHÁà8Ž¼°AØÄÉ6°x–Ã?»áwzµ0S¸÷ϽDOâéäÓÂLaht€ã8<7.p0P]—h¹¬ÝÑÓSW_ÿß™¿=sfÿfÿ«…¸¬©™ÕtoG¡ –Ïçóz½ÇÔT*rN_ñ—ùÿÇ~¤³"ãî¾¾õHd=ùüÆ “‰ÞÚ:Ó×GÂï®—/étÚúµ5~»wðÔÔÏón÷ö1Æ@ 088¸ŸSQÊWšüY›<h`öÜþ*¯ïW“Ó `!z3ÓŒPâF*_¨hd³óXE›Í&Š"A‚Á €@ 022"Â>L%7üøö³oµ×÷Ëý«ËÐHV¿ÅA\¦¤Óió÷ælñ¹¹Ðé«ÉÉI¿ß¿µµ@ÅS§N¸zõª,˧¿¿ddD’¤½ÏF}Ø `nz./ï{÷¢Þ"!><^ËL%¨šPM1ö£©©)›Í@¯×ày~``@»Ý>>>>;;ë÷ûˆ¢èóùö2ïdNòŒ—ºOw'ÝsJð!aå·îÜ1¬¬l¬­£dCØM¡ì\œâyþÒ¥KdY–$Éf³µ··ŽŽ*ºÀqÜÅ‹EQTÉ’$uvv¾Fj­ËÙþ.FóºOîZ&DÀ‡A:6ÏÌÐóó§¾üòùíÛ«³³d¼?#£ÞæËW’$MNNr§á`0èõz%IEÑãñø|>U¨<Ï«÷Ȳ¬|(ÂîaY—óºçÐ6š<{¡„ôü<=·ý¿§66~·¼üÇ{÷tŸ|²|çÎNYŸÐgÀ];ŽÌó¼×ëU_ƒAŽãDQdYöúõë<Ï­[·Ôû%IâyžeYeÃihhh—©'sÂ/^Úþm`w·²tHlÒ4•Lj ÀÎ/œ²üóÄIJÕkmµhê®tˆ¦â*5à¹pá‚úZI’ƒÁ ßïç8Žã8I’†°´´Äq\ÿðððµk×(Áy||¼ÐèºüpÞö/ÉŸK ðaoi‰·´Ÿ<1?x@?~¬}~·©ºÚ”Lbf&rÿþªË•:z´º¶–ž¥s¯yÇ‘Õý^ŽãX–=wîœ$IŠV•Ïõ ‚À²¬ 6›Ín·³,+IÒÐÐÐððð.SÏ°b?º¼pyï>û.•J‘ü¹´Ê_üY}}Øj¥’IóÇ5 T*¥½£¶¢¢öÑ£ÅH$n=nd”Ó\ì·Œ1 ÖÖÖúûûÝn·ÛíV,Š¢ÅbSÀ<Ï[,–¾¾¾B#ªç72ÜþÇíž¿ôums´µ½ß`ss3‹Åb1í/%d |¨ètº­7ÞxÒÖöã{ï…;;Sªï7sÙaµž|âÚ~ú€¦Bõç<­Þ½{×ëõò<ßÕÕ555@–åõõu¯×Ë0Œ"æ`086¶[g€Šüúsl)öîûïjo¡(Êjµ¶¶¶666Z­V½^ŸN§_·c.aÏ\”0•xûíxc#€·¦§ép8+ãèé¬ï§èð«…a†az{{APriåVoo/Y–•-%‡ÃQh”DþñÉOÿúiËZ”î“/c4F£ÙlN¥RJox<“˜ÿÿÿ~`„IDATìMLGÇß8Yâ%^ð®äbÇcC>i ¥QJ >$âR !¥í…Co9!.=F¹D94í!âÌ-¦sÁQ{I E¶Ú`×µQKüAøÈ*^c¯dÄö0`¯mp,íVšßÉÒÈžYÉ¿ç™÷þCú•G’$*ÖE£L:ToÀtí'*·o)ßþjáñ‚kÚ…Gà`b÷½o³ÛË1¾Â~W<Ï‹¢˜Édˆ’kI¡Õv¢9ÍËê7¾¨ËD87Â¥Ú4 ¹úñu½ÁÀ'¿,,X¬V›Ýnjo?éÃä~W‚ ðxDJLõ÷ÊÊŸKKKÏž‘“§Ê X-h£Úœzõ*ÊŸ‹/ï.óöPìb'¤R1ç¯wl|¼ _½ ®¬@/±¿ª"àz‘Ú١˶D•$‰õʶ¯lêÈŸ@‘ù”éž“+íÖ뇜N>‘XõùĽ=‹ÕÚ×ßËÏŸqŸ¬"ຠǛææD“)j±pÝÝT2%Pt”Ξ¸ÂxÖxï ÷Ÿ ¶¯*»¼?~»Í†_»fg;íößÜnø¬t9'¡$DÀµG’$Ë´FÛÛçwwžŸ™Í}““'ÉX’$Ö#sÏáT~qù¤|¼û«ìãã½ëé™™`PO¬Û«€¸öPÉäéd2[éìé‰&þ‡“Ö»w•±.pd W¸ÖxYøEO§ŸÊÇ«qŸ”“ÝÁ&æuUBv¡kOF§K:mT0ëõÎ F4šGü33©ü&~:JS *›²Âhã—|:&ËÇkå>™›¨·:H®=¡­›7‡ƒ]]eÖ׳2nÑj—.Fãyò䃡Íé亻€ñ39õ^SQþì™÷ï?É© "຀M¦˜ÑH¿}[ÜÄ?èp€Fã™›{ `¿ó-`;zÀ5å½+û: âžó€¸Ž „D£1ÖÖFíí±¯_³kkòÑÁžžÁS§¢‹~jïΡ{ØŽý¤†~¡È=gô;“{ÂñׄоN·58È÷ö²kkl ¿¼Û,~›ËŸªÉŸQÞåÝpòåƒe!n‡^ýýüÅ‹ŸÁ†û-°ß’ë^P0Þ)ÜöÎ{&¾úþËðrØýØÍ'ù³!n(XƱ7¨tš Yw4À*~å -‡ÂËá{?Ýã,g1L|žÉdü‹‹¨¹¹©µ•Äaõ@Ž‘!´ßܼuåŠÀ]ýûåJ¾­¾k*ììú´‹³äDQTß­[ú3gøp¸Ìû%õ†D`Å #4ãgr?¡ýÊ-e+?FàþÁM' h5[Ú¬Ö÷››ÑPè ©‰"YQþÿÿç´š7äIDATì_LEÇ¿£·ÀÂ-¸Ò#W8ˆáNS´Æ6mNÁ6’ø‡[MjèKSŸôAßLÓ—5ÁÛ¨oš´}!¤5m¢ åÁ wˆ­Bº·ÀzåβÄ=Ê&·íú°·{ ÈÞíç“ Ù»›™ ûÍoæ73¿µÀΠë:7iJö¸£¶"ŒrT†…,?–™:¯÷éC‡öƒ»jj¬¬lœ)†R<¨€£*ZµvE¿sýXÈö?¹Ë"#‘¾ûN‘SW?½šJ¥ Ý]ïóíÙ¿¿¥¹ù~"1 ј²%†¡›äØ(›ÉšýŽÃýÉ@ºl9?Hjˆ(Š,ËrÇóùýlÍûöh þºuëAeåýŠŠjzD¡$P;€®ël”Íl™ð—ûŠ t9”uüÈÈý«ªªªª²,WUUy<†arkªózë¼^w£ÑÅÙYEQKŸ,É/ù?Bì ü0Ÿ™¾ˆÀgÀûNÈ8j}®•½}Ò¼CÓ´d2©( Ã0<Ï2Èõ>_½Ï@„¦`F“-tìÜ„É}e<Õ"ð Ð Èî)Vó+Ü"7,Û'ó?"„hš–H$DQŒÇã«æ$OVZ<ÜÝÝÚÚJd924D§Ç¶C-p©ÑuN®u›d\Ìg€Và­MRŠ‰ÜäÝmGÚ6°œš¦-//˲l$U1âÅæå§þþ‘ÁApæÊjŠm„Z`çÈ}ŒOæ€óÀ%`®È²-ðõó–ñs­·Ö˜oŒ‰raaA’$#—Jn™¥ÅEA=Çn¨.5„é=‰²»ØÍ$ €’&€ç€–Rtli~Iž·Œà·züÈptÅãq–e=Ëå2|]4údñ vBˆÚ¬ŠŠÜçùÙì˜dœ%æ?€?g. Öö~ld~ÿsôà K’d8ºÜn÷¥Þ^{;:hôIÛ¡v BH²-©ìQøQžã™{Ö…ós> Lí@Ð>Ïdÿó…e¼Íãû뎮x<ÞÙÝ]QSó 5¿E€f'tÃ7ËÝæ×òÍëoŸ›ÏL7c&|и Œ =¯ô˜¿?ÙwÒ®ÀëÎgj~m‡:±œÇÈH’|*9ýÁ´PRîT¶w¦·¿ß¿l¯I!güüµ=ãç¼4¶ÔF1C‡Ðe!$ÖcVψ‡›MÙ¼ýM`xxÕž¦³Æ϶GŸ¤ jË BˆæÖb/Ǥ7%å %ýiÒ"ÐLl·ÑoäXÆÿ¼éò/¥| .G!jƒëŒI¯K«»VK¬¹t!€+@¦ºöikm‘pÄÿ‚ÿÑô.°‡\þ¥”TÀå !Dõ¨ÒkR¬#–bS@žÀ‘kü üüÜÞRÁÒüRøZ¸ë£®/¤o_:þH%ÂÞ¦©zw TÀå!$Ù’ßcÁ´Œ q·VèZ@ðxonz·ÿûÏ¥ÁºÊÔعswéý]FÚI¸V]îwÃtƒemÉUàâH¾*&ÓÒ¯³GÏN|yÂ\êŸ;wÂ/*ŠRë÷7µ·ÓùpÙB¼óÐu½q¼‘KpÑæ Øh§õæIË·ÂM¡çhÏé¡Óö@Þ¶B.ÄçæHuuàØ1*ã2ä_ÿÿ2ˆ¬D IDATìÏOÓpÆßW²d%t¤Ì-e@L£ô´¨æeNÜÈà@" 'þoøˆ1f'/ÄASÏ":—1$£ƒ kZt롶ÑñCHGÇûÉ.Û¾kzyò¼kžïómoô=gõ ®…4@`ö¸‡ñʈõ6 ° pãß UßJ3Rf9“û”cÚá¶MôJÅ[ýýj:ýyvöÇöve!/äÀ.Æ4MFg¸<Ǫ¬ýÖXqõäl½âBüàj=÷zF#BoÝåª$}œŸoí꺋Ū.äp1ˆhøŒMvÓóÛÓùµ“1˜cW×~°ö®*¼‘YÌìýÙK¥R¡PÈvgo8 G£¹dòå؉܉ÇdÜhÈ›Ó4¹ï«³Ì/¦®÷Ö<¾x’yØ¿!ˆÂЋ!K^¯÷ø ú¹dr)‘ØÞظ;œÜ>YÉA/´U²q´ÚÇó''[ûúžOL0~ÿ㙲b nrÊ-e¥M‘ÛäÒµÒÁƒè¥ùª³Nx·U²‘ÍfuÝÞÛÓ++*€²³sî'N øJ`´²W–=r K =«ŸÏt5k¨N¥RG‡êEI€Ô>é4B_Ñ@C6eȃ_ô{xž×µ¼‘xäÿÊë¬Ê«`0hÑðV’v¶¶€Ú'„|µ@DàkûbÏógµRƯ h÷û©}Ò1(ÈA\T^ç<äÀÄ…AºuzˆE.†L.†L.†L.†L.†L.æ/ÿÿL?²«KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATíÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`ÆC¿*ÌóûÑIEND®B`‚tkgate-2.0-b10/povray/module_root.pov000644 001751 001751 00000005455 10147516407 020422 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #include "ROOTS.inc" #include "TOMTREE.inc" #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bark_Text = texture { pigment { wrinkles turbulence 2 color_map { [0 rgb <.2,.1,.05>] [0.4 rgb <.2,.1,.05>] [0.7 rgb <0,0,0>] [1 rgb <0,0,0>] } } normal { wrinkles 1 scale .1 } finish { roughness 5 ambient 0.5 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } object { box { <-(W-T),-D,-(H-T)>, } texture { Paper_Text }} object { text { ttf "cyrvetic.ttf" "main" 0.3, 0 } scale 0.3 rotate 90*x translate <-0.5,0.101,0.0> texture { Ink_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 } union { object { Chip } intersection { object { TREE scale 5 } plane { y, 0 inverse } rotate 90*y rotate 180*x translate <0,-0.25,0> } rotate y*40 rotate z*-20 } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.0, 0.0, -8.2> look_at <0.0, 0.0, 0.0> } light_source { <-20.0, 10.0, -30> colour White *5 } tkgate-2.0-b10/povray/module_root.png000644 001751 001751 00000033076 10147516460 020401 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®IDATìÚOhWÀñï›Lt™I¶ACíÖ¤ㆬ:ºñîrµ=ÚKÏ…ì¥ôRè±·{)Eô& =-J'ؘlÖjdQzˆ m¡JÀÌïí6;¯‡MS“šZIÚÝY~ö2»ßÎåË{쎬T†iÀJe˜¬T†iÀJe˜¬T†iÀJe˜Ü;œs¾õó;}jw8ç|}`mxMŽ‹”ÄyÎÓé›Rÿ9 ¸Gä䆾€Áõ;9*«S«¶heRœ¯1÷, ¸8çò7ó—fÍ?ÁÝCº7•c"“"“"E¹×hÀYÐj9Ïûçð+ƒíí—Í«¼¦.†a-Äà|'%IŽ'ÉÑÄŽ[g4æÌÓ€»Ý¾Ë—÷]¹²Z.'Q”DQ³P¶„7p{À_ñÿJ×¼øeR,Áý }ÌNJ‰LŠ=l“R¢1g”ÜÕœsùJÅk4ãx0ŽÆȈDѳr9‰"çûÆçÜúö ¼C ßC~}ÑÐvÌ-Þ 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#declare TWIGS=4*BRANCHES; #declare BUNCHES=0*TWIGS; #declare LEAVES=200*BUNCHES; #declare BLOSSOMS=0*BUNCHES; #declare ROOTS=0; #declare BRANCH_RANDOM=16.397; #declare TWIG_RANDOM=77.37; #declare ROOT_RANDOM=173; //TRUNK #declare TRUNK_RADIUS=20; #declare TRUNK_STRENGTH=.5; #declare TRUNK_BEND_X=15; #declare TRUNK_BEND_Z=20; #declare TRUNK_BEND_X_FREQUENCY=1.5; #declare TRUNK_BEND_Z_FREQUENCY=1.5; #declare TRUNK_CURVE=10; #declare TRUNK_CURVE_FREQUENCY=5; #declare TRUNK_SNAG=5; #declare TRUNK_SNAG_FREQUENCY=10; #declare TRUNK_SPIRAL=50; #declare TRUNK_TAPER=0.2; #declare FIRST_BRANCH_AT_TRUNK=00; #declare BRANCH_AREA_AT_TRUNK=00; //BRANCH #declare BRANCH_THICKNESS_CHANGE=.7; #declare BRANCH_STRENGTH=1; #declare BRANCH_BEND=-30; #declare BRANCH_BEND_FREQUENCY=2; #declare HORIZONTAL_BRANCH_BEND_SWITCH=1; #declare EXTRA_NOISE_SWITCH=1; #declare BRANCH_CURVE=-5; #declare BRANCH_CURVE_FREQUENCY=2; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=1; #declare BRANCH_LONGITUDINAL_CURVE=.5; #declare BRANCH_SNAG=3; #declare BRANCH_SNAG_FREQUENCY=5; #declare BRANCH_REDUCTION=.0; #declare BRANCH_TAPER=.2; #declare BRANCH_END_EQUALIZER=1; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=1; #declare BRANCH_ALTERNATE_SWITCH=0; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=35; #declare BRANCH_ANGLE_SCOPE=0; #declare BRANCH_ALIGNMENT=.8; #declare STRAIGHTEN_TOWARDS_TOP=0.6; #declare FIRST_TWIG_AT_BRANCH=100; #declare TWIG_AREA_AT_BRANCH=25; //TWIG #declare TWIG_STRENGTH=.5; #declare TWIG_THICKNESS_CHANGE=.55; #declare HORIZONTAL_TWIG_ANGLE=0; #declare VERTICAL_TWIG_ANGLE=30; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=0; #declare VERTICAL_TWIG_ANGLE_SCOPE=0; #declare HORIZONTAL_TWIG_ALIGNMENT=1; #declare VERTICAL_TWIG_ALIGNMENT=1; #declare TWIG_TURN_SWITCH=1; #declare TWIG_ALTERNATE_SWITCH=0; #declare TWIG_CURVE_ADJUSTMENT=.8; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_TAPER=2; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=3; #declare LAST_RAMIFICATION_NUMBER=5; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=.5; #declare FIRST_BUNCH_AT_TWIG=100; #declare BUNCH_AREA_AT_TWIG=0; //BUNCH #declare BUNCH_MAJOR_RADIUS=150; #declare BUNCH_MINOR_RADIUS=50; #declare HORIZONTAL_BUNCH_FUNNEL=40; #declare VERTICAL_BUNCH_FUNNEL=40; #declare ROTATION_BUNCH_FUNNEL=0; #declare HORIZONTAL_BUNCH_ANGLE=0; #declare VERTICAL_BUNCH_ANGLE=30; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=5; #declare VERTICAL_BUNCH_ANGLE_SCOPE=5; #declare BUNCH_TURN_SWITCH=1; #declare BUNCH_TURN_SHIFT=1; #declare BUNCH_ALTERNATE_SWITCH=0; #declare HORIZONTAL_BUNCH_ALIGNMENT=1; #declare VERTICAL_BUNCH_ALIGNMENT=1; #declare BUNCH_TAPER_OFF_AT_TWIG=.3; #declare BUNCH_TAPER_OFF_AT_BRANCH=-.3; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=HF_LEAF #declare LEAF_LENGTH=10; #declare LEAF_BREADTH=7; #declare LEAF_HEIGHT=1; #declare MAX_LEAF_TILT=30; #declare MAX_LEAF_TURN=30; #declare LEAF_INCLINATION=50; #declare LEAF_INCLINATION_SCOPE=10; //BLOSSOM #declare BLOSSOM=LEAF #declare BLOSSOM_LENGTH=50; #declare BLOSSOM_WIDTH=100; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<1,1,1>; //ROOT #declare FIRST_ROOT_AT_TRUNK=30; #declare ROOT_LENGTH=200; #declare ROOT_THICKNESS_CHANGE=.6; #declare ROOT_STRENGTH=1; #declare ROOT_BEND=50; #declare ROOT_BEND_FREQUENCY=1; #declare ROOT_CURVE=30; #declare ROOT_CURVE_FREQUENCY=5; #declare ROOT_SNAG=5; #declare ROOT_SNAG_FREQUENCY=15; #declare ROOT_TURN_SWITCH=1; #declare ROOT_ANGLE=30; #declare ROOT_ALIGNMENT=.6; //BARK #declare SUNKEN_TRUNK_COLOR=<-.01,-.01,-.01>; #declare RAISED_TRUNK_COLOR=<.3,.1,0.05>; #declare FOLIAGE_COLOR_AT_BRANCH_END=1; #declare TRUNK_SCAR_WIDTH=60; #declare TRUNK_SCAR_HEIGHT=15; #declare HORIZONTAL_SCAR_SHRINKING=.2; #declare VERTICAL_SCAR_SHRINKING=2; #declare SCAR_DEPTH=-1; #declare PALM_TRUNK=0.2; #declare BARK_PROFILE=0; #declare BRANCH_BARK_PROFILE_CHANGE=0; #declare BRANCH_BARK_PROFILE_TAPER_OFF=1; #declare ROOT_BARK_PROFILE_CHANGE=0; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.3,0.1,0>; #declare BOTTOM_COLOR_2=<0.4,0.5,0>; #declare TOP_COLOR_1=<0.3,0.1,0>; #declare TOP_COLOR_2=<.3,.1,0>; #declare COLOR_TURB=.2; #declare TRANSITION_BOTTOM_TOP=0.4; #declare TRANSITION_TURB=.25; #declare FOLIAGE_GLOSS=0.0; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX tkgate-2.0-b10/povray/circuit_prop.pov000644 001751 001751 00000020127 10151246645 020564 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Text_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.15 ambient 0.5 } } #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } union { union { object { text { ttf "cyrvetic.ttf" "Name: beak" 0.03, 0 } scale .3 } translate <-.9, 1.3,-0.02> } union { object { text { ttf "cyrvetic.ttf" "File: beak.v" 0.03, 0 } scale .3 } translate <-.9, 1,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Ver.: 2.0" 0.03, 0 } scale .3 } translate <-.9, 0.7,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Change Warn: Yes" 0.03, 0 } scale .3 } translate <-.9, 0.4,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Ext Bar: Yes" 0.03, 0 } scale .3 } translate <-.9, 0.1,-0.02> } scale 0.4 translate -0.01*z texture { Text_Text } } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <1, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <1, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } object { Paper rotate x*20 rotate y*10 translate <-0.5,0.5,-1>} sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -7> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *3 } tkgate-2.0-b10/povray/circuit_prop.png000644 001751 001751 00000023311 10151246702 020534 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿´…>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùŸLKIDATìÓ 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ZOe™à m Ic+À9ÁhUij,à·¸éa l×Å(“@°a%5qIw`F°_`2ÎT Pó )°ŒJ‚”&aŒ1kðŠÉ˜ŠÑJò ™‚PZ_ b€w~ <2‡¨U|pYŒòaQvš©¹a«) `’)´ þ2{íðÑ`?¹Éú3.'Éhs0Zþ†š‹éY@ Ȩ"1‚œW€-`Ð’ +P…P–ü&9ÁFš^2pÆRúÙa, ž!ñ ™ÂP fPXnï2g<þ6ŠeqŸÃ©ŸeP þy   ¼± XA°9 [Óèkú£y7× Ù©skð Š©Ÿ–†i à•„ 1*™W€.e1BÀékª09+Ŷ¡QaÂÙaÆ–ÈÐpÐY&Ȇš ¯€± eð­“ Y›¦°"”u˜Œ¢¡¥) ¥¡zèWJl0¡¡à¡àè™@ c`þU›Û`+¡Ø¢NŠ‹ªp±¸wú 3ࡦp!:€ @¦; 2wvˆÂ¨+?—O ªWŠ’Z €!›0d$ÐËCi:9lšrjª È ‹ÚÑxðt𪰠JâP N †º"ûCŸÑ¬P)¬ÄêrP© « $±-PÀ™ÝT ¦ 0ª¤ˆ­Ê êÀà­n°$èéÒ*sW€%ÈS z +.ꮌ ¯zà­?º$µa®Ýªÿ( &°‹ ÝZ©½0 }² ±›«p%:“Få„ 4 ©˨ P©þ¢ÓÙ*W ":cJK)GxJ˜²1ÉÀ²—ú²}⇲%ãT³¯q²”²5ѳÀ_ ´$i(jZ.z0˜Vpð'ð«ÀJ¡À´} µ¡Y+Zrs„ù©ŸpÀ ¦‚­C Lû³b›8C¶à›ð3ÂZ§`¡~«µyú”K{°0·b )ò°Ы8H3PEè·’‹ Üð/&3ð=[©´ ·† ‰Ë"Ö 4¦­’+¹^aòõÀ´ nà¹@["+ œÚÉ {º~ 4—›ƒ&к,+™)»b{V²"½:¼JÏ‹¾û—þÖ¨qœÆ«¬J!ª »ü¦ (r(ôm Qað¹~ mØ›½C°²=ª,Aß ²0¾¡z¯È Š¡njð¡ðšò«‚ õ«¢'R+Š*¥;Ž5Ú¾:ÀIáŒt à®Ýä Œ%LÊ(Sš½j`#¥ )°hp 9± »ÐÁdd &RW¦Ðy¡éâ¸h < ™aŒ°  9Û`"‰{sת³Aó€³ Áu±{° j3£ÐLœ 0ÂyKÁP,Å&aqf¡ Zœ0W°}"½ÊµPì¾  wqïÁ Ûð´‘Çþ)b ÿÊ([Ç4ñ¾›áðQÛÀ±K² °(Ò› ”0 )lÈ4AÛ áÇÂpŽ|!WP%@³­ («É41h ŠìÈ¡ p~̪€Ê«ª­¼¿°@œ Æá!£! Û-²Â$»FÌI;Ìo:ÅÁÊP²nð£WÐÌ°(zÀ–}û¿”ÐKÍÄ<&`ËÙ"´@ ²r"#¬Ýé»PÎ9‹ÎÄ<&€ÌôáÐÏ:¨Ê Õ{Ï:ªÏQÌ ÐÎM%³âÄA]½˜PΫÐļ   !Ðú x›É=¬M xªŽÑļà°Ëñв¸ïjÒ¾{Ñ®LÆš,ÅhÀ 0­ôYÈ£µ·Õ ” ¬ÒÈ6Å"’úËvâhÐöl2ÀÃHÍRìTÒ¢çŒl{º5:ÍUý’\à@l$ìŸâ f¾a-&CÀ–Ð ,&] À8­ÐɶÂØë¸È0ÁoýÃ+¼Õ;tkgate-2.0-b10/povray/oldROOTS.inc000644 001751 001751 00000011274 10147271663 017442 0ustar00hansenhansen000000 000000 //XXXXXXXXXXXXXXXXXXXXX S E T T I N G S XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX //TREE #declare BRANCHES=3; #declare TWIGS=2*BRANCHES; #declare BUNCHES=0*TWIGS; #declare LEAVES=0*BUNCHES; #declare BLOSSOMS=0*BUNCHES; #declare ROOTS=4; #declare BRANCH_RANDOM=15.397; #declare TWIG_RANDOM=77.37; #declare ROOT_RANDOM=170; //TRUNK #declare TRUNK_RADIUS=20; #declare TRUNK_STRENGTH=.5; #declare TRUNK_BEND_X=15; #declare TRUNK_BEND_Z=20; #declare TRUNK_BEND_X_FREQUENCY=1.5; #declare TRUNK_BEND_Z_FREQUENCY=1.5; #declare TRUNK_CURVE=10; #declare TRUNK_CURVE_FREQUENCY=5; #declare TRUNK_SNAG=5; #declare TRUNK_SNAG_FREQUENCY=10; #declare TRUNK_SPIRAL=50; #declare TRUNK_TAPER=0.2; #declare FIRST_BRANCH_AT_TRUNK=0; #declare BRANCH_AREA_AT_TRUNK=0; //BRANCH #declare BRANCH_THICKNESS_CHANGE=.6; #declare BRANCH_STRENGTH=1; #declare BRANCH_BEND=-20; #declare BRANCH_BEND_FREQUENCY=2; #declare HORIZONTAL_BRANCH_BEND_SWITCH=1; #declare EXTRA_NOISE_SWITCH=1; #declare BRANCH_CURVE=-5; #declare BRANCH_CURVE_FREQUENCY=2; #declare HORIZONTAL_BRANCH_CURVE_SWITCH=1; #declare BRANCH_LONGITUDINAL_CURVE=.5; #declare BRANCH_SNAG=3; #declare BRANCH_SNAG_FREQUENCY=5; #declare BRANCH_REDUCTION=.0; #declare BRANCH_TAPER=.2; #declare BRANCH_END_EQUALIZER=1; #declare BRANCH_TIP=0; #declare BRANCH_TURN_SWITCH=1; #declare BRANCH_ALTERNATE_SWITCH=0; #declare BRANCH_SPIRAL=0; #declare BRANCH_ANGLE=35; #declare BRANCH_ANGLE_SCOPE=0; #declare BRANCH_ALIGNMENT=.8; #declare STRAIGHTEN_TOWARDS_TOP=0.6; #declare FIRST_TWIG_AT_BRANCH=50; #declare TWIG_AREA_AT_BRANCH=60; //TWIG #declare TWIG_STRENGTH=.5; #declare TWIG_THICKNESS_CHANGE=.55; #declare HORIZONTAL_TWIG_ANGLE=0; #declare VERTICAL_TWIG_ANGLE=30; #declare HORIZONTAL_TWIG_ANGLE_SCOPE=0; #declare VERTICAL_TWIG_ANGLE_SCOPE=0; #declare HORIZONTAL_TWIG_ALIGNMENT=1; #declare VERTICAL_TWIG_ALIGNMENT=1; #declare TWIG_TURN_SWITCH=1; #declare TWIG_ALTERNATE_SWITCH=0; #declare TWIG_CURVE_ADJUSTMENT=.8; #declare TWIG_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_TAPER=1; #declare TWIG_TIP=0; #declare STRAIGHTEN_TOWARDS_BRANCH_END=0; #declare TWIG_RAMIFICATION_ORDER=3; #declare LAST_RAMIFICATION_NUMBER=5; #declare TWIG_RAMIFICATION_THICKNESS_CHANGE=1; #declare TWIG_RAMIFICATION_CURVE_ADJUSTMENT=1; #declare RAMI_CURVE_FREQUENCY_ADJUSTMENT=1; #declare TWIG_RAMIFICATION_STRENGTH=.5; #declare FIRST_BUNCH_AT_TWIG=20; #declare BUNCH_AREA_AT_TWIG=30; //BUNCH #declare BUNCH_MAJOR_RADIUS=15; #declare BUNCH_MINOR_RADIUS=5; #declare HORIZONTAL_BUNCH_FUNNEL=40; #declare VERTICAL_BUNCH_FUNNEL=40; #declare ROTATION_BUNCH_FUNNEL=0; #declare HORIZONTAL_BUNCH_ANGLE=0; #declare VERTICAL_BUNCH_ANGLE=30; #declare HORIZONTAL_BUNCH_ANGLE_SCOPE=5; #declare VERTICAL_BUNCH_ANGLE_SCOPE=5; #declare BUNCH_TURN_SWITCH=1; #declare BUNCH_TURN_SHIFT=1; #declare BUNCH_ALTERNATE_SWITCH=0; #declare HORIZONTAL_BUNCH_ALIGNMENT=1; #declare VERTICAL_BUNCH_ALIGNMENT=1; #declare BUNCH_TAPER_OFF_AT_TWIG=.3; #declare BUNCH_TAPER_OFF_AT_BRANCH=-.3; #declare BUNCH_TAPER_OFF_AT_TREE=0; #declare BUNCH_ARC_AT_TWIG=<0,0,0>; #declare BUNCH_ARC_AT_BRANCH=<0,0,0>; #declare BUNCH_DEFORM=<1,1,1>; //LEAF #include "TOMLEAF.inc" #declare LEAF_TYPE=HF_LEAF #declare LEAF_LENGTH=10; #declare LEAF_BREADTH=7; #declare LEAF_HEIGHT=1; #declare MAX_LEAF_TILT=30; #declare MAX_LEAF_TURN=30; #declare LEAF_INCLINATION=50; #declare LEAF_INCLINATION_SCOPE=10; //BLOSSOM #declare BLOSSOM=LEAF #declare BLOSSOM_LENGTH=50; #declare BLOSSOM_WIDTH=100; #declare BLOSSOM_INCLINATION=0; #declare BLOSSOM_COLOR=<.4,.4,.4>; //ROOT #declare FIRST_ROOT_AT_TRUNK=30; #declare ROOT_LENGTH=150; #declare ROOT_THICKNESS_CHANGE=.8; #declare ROOT_STRENGTH=1; #declare ROOT_BEND=30; #declare ROOT_BEND_FREQUENCY=1; #declare ROOT_CURVE=30; #declare ROOT_CURVE_FREQUENCY=5; #declare ROOT_SNAG=5; #declare ROOT_SNAG_FREQUENCY=15; #declare ROOT_TURN_SWITCH=1; #declare ROOT_ANGLE=30; #declare ROOT_ALIGNMENT=.6; //BARK #declare SUNKEN_TRUNK_COLOR=<.1,.1,.1>; #declare RAISED_TRUNK_COLOR=<.6,.4,.3>; #declare FOLIAGE_COLOR_AT_BRANCH_END=.5; #declare TRUNK_SCAR_WIDTH=60; #declare TRUNK_SCAR_HEIGHT=15; #declare HORIZONTAL_SCAR_SHRINKING=.2; #declare VERTICAL_SCAR_SHRINKING=2; #declare SCAR_DEPTH=-1; #declare PALM_TRUNK=0.2; #declare BARK_PROFILE=1; #declare BRANCH_BARK_PROFILE_CHANGE=1; #declare BRANCH_BARK_PROFILE_TAPER_OFF=1; #declare ROOT_BARK_PROFILE_CHANGE=0; //FOLIAGECOLOR #declare BOTTOM_COLOR_1=<0.5,0.4,.4>; #declare BOTTOM_COLOR_2=<0.4,0.5,.4>; #declare TOP_COLOR_1=<0.5,0.5,.4>; #declare TOP_COLOR_2=<.8,.4,.4>; #declare COLOR_TURB=.2; #declare TRANSITION_BOTTOM_TOP=0.4; #declare TRANSITION_TURB=.25; #declare FOLIAGE_GLOSS=0.0; //XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX tkgate-2.0-b10/povray/module_root.gif000644 001751 001751 00000013541 10147516676 020366 0ustar00hansenhansen000000 000000 GIF89a}ƒ÷ÿÿÿÿÿØØØÿ++__ÿ(ÿÿ'ÿÿLÿÿNÿÿMÿÖÖÖÿKÿÿ&ÿæ?æìXX(ˆPîwj×ÖÖÁÁÀNC;j2ói#0Ç—<”I ]@4a0äœ.>' m§HX)b%ö!g:ÿzÿ>£A¬ ›&|?C¢dNƒE¥dÁ²œ¶G!dba~<f> ywu¾»¹‘‘?.דþûýÿ;ÿ߶BØÔÖ.%Î^, ž› {tkpU8ÈW‘@ ‚Qór#ÈuV.‹[H8#JvF¯T 9©¨§s;>"F ^% Ÿ<žH `,–`åW(YRI¶ªš]7ãgø­øÆŽ&<΂´¯«›W Î{`ùìøúSúJ&ÇÅÄŸtci-ÞʈéšP„8 h5z6 Ë¿¹­‡NƒrTÉP±and[­pùõ÷‡Ú«:æDhà°ÖªŽkïáëJ!M.Y%ÿCÿ2 æct Ö¸£  ú˜êÿ&ÐÐÏÜÏØÿÎÿè,,ÿ%ÿÿJÿÿIÿ ÓÓÒr1 ÐÍÌ »··ù&*ÿ)ÿœœü//ÓÐÐÿ#ÿÚ#*ý0àb^vez1 ˆ1ý5ýþGþ’ R‚UÿHÿv.(Ú«¡ÿ0ÿÿ+.ÿEÿ¸)¬ÿ@ÿggÿFÿ¶´¶ýAýÊÈǸ°³ú;;÷`÷èªþ9þòŒòÿ,ÿÿ`ÿÖÎ̪V,*ìa"‡‚|ÉÉÉY- ¤y‚cZÏǾR$£—šÙ½½kDÇkØɺơ’iGÿOÿˆA µžuª–|ÑÉË; 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Ink_Text = texture { pigment { rgb <0.05, 0.05, 0.05> } finish { specular 0.0 ambient 0.0 } } #declare Chip_Text = texture { pigment { rgb <.6,0,.6> } finish { // metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bark_Text = texture { pigment { wrinkles turbulence 2 color_map { [0 rgb <.2,.1,.05>] [0.4 rgb <.2,.1,.05>] [0.7 rgb <0,0,0>] [1 rgb <0,0,0>] } } normal { wrinkles 1 scale .1 } finish { roughness 5 ambient 0.5 } } #declare Erase_Text = texture { pigment { rgb <.6,.3,.3> } finish { specular 0 roughness 0.3 ambient 0.2 } } #declare Yellow_Paint = texture { pigment { rgb <.9,0.9,0.1> } finish { specular 0.2 ambient 0.1 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Chip = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.15; intersection { box { <-W,-D,-H>, } box { <-(W-T),-2*D,-(H-T)>, inverse } texture { Chip_Text } } object { box { <-(W-T),-D,-(H-T)>, } texture { Paper_Text }} object { text { ttf "cyrvetic.ttf" "ALU32" 0.3, 0 } scale 0.3 rotate 90*x translate <-0.5,0.101,0.0> texture { Ink_Text } } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 } #declare BoardWidth = 1.25; #declare BoardHeight = 0.5; #declare BoardThickness = 0.1; #declare PostWidth = 0.15; #declare PostHeight = 1.5; #declare Board = difference { box { <-BoardWidth/2,0,0>, } } #declare SignBase = union { object { Board translate (PostHeight-BoardHeight)*y} box { <-PostWidth/2,0,0>, translate BoardThickness*z } //Other possible woods: 18, 19, 20, 29, 30, 31 texture { T_Wood18 scale 0.5 } } ///////////////////////////////////////////////////////////////////////////// // // Put up the sign base and subtract out all of the letters. // ///////////////////////////////////////////////////////////////////////////// #declare Sign = union { object { SignBase } object { text { ttf "cyrvetic.ttf" "Mine!" 0.1, 0 } scale 0.4 translate <-0.4,1.101,-0.01> texture { Ink_Text } } } union { object { Chip } object { Sign rotate -30*y rotate -30*x rotate 30*z translate -0.75*y } rotate y*40 rotate z*-20 } #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.0, 0.0, -5.8> look_at <0.0, 0.0, 0.0> } light_source { <-20.0, 10.0, -30> colour White *5 } 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cc܉Õ`Öå?*•ŒbQ²6X(—57¡Ys”K.Š¢ îÕNÇû÷40fb`ÆLŒ̘‰q€310c&ÆfÌÄþÿÿ9dضKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATíÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æ4ðÿ`]ú]ÀIEND®B`‚tkgate-2.0-b10/povray/oldsearch.pov000644 001751 001751 00000016174 10150240154 020021 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <0, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <0, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } //object { Paper } object { MagGlass rotate -45*x scale 0.6 translate <.15,.3,-1> } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -3> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *3 } tkgate-2.0-b10/povray/newcircuit.pov000644 001751 001751 00000016317 10501703136 020234 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.3 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.3 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.3 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <1, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <1, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } sky_sphere { pigment { // colour red 0.8 green 0.8 blue 0.8 colour red 1 green 1 blue 1 } } // // Where are we anyway? // camera { location <0.2, 0.0, -7> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> 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RàLˆovç«@ºöá˜-0°\„ÌÐUïhmñp  0â+_Z ¡•˜EE7’‹xLC0)ÆmÕ»m¸6:Â#Î`à»ÂÞýn~÷‹½6¶ ÿ%BpKbb 9Bjlàf€¢÷•0…õŠáæÚ" L0‡9þf—˜ ˆ¦Š)ÜbæÄ FÈrªr7cÅ5ˆ]õ;Þ7Y iȲþø„#°AÉæ8DŸÂ\Øïw¹5„|pˆ.Ù lPó þLgœ"¿úÅó6=+$ÍY°  'VpHBÆ° †ðbÏ>¥rèiXàÔ©ø¡› ê&¥! £žl4¸À…1PÊ!Ðt½ -Ì”>+Ò‘Žhë!е²“P‡Qz¬ðƒÀÀ䇌ãÔØÎö ¤ŒÙ#dð‚¸ekÓšÖ pŇ0g×ÁÀÀî:"Å q±£ïÀüæô¨`ˆ\ÞóCL¡½‚œ`ˆxÄÁ GH\Ÿ5/X‘ƒÇ[Þuh†1þxáG°BÜ(—¶¡a«Ü£iccp¼ãÿ8Âé=†1Ð>7\@t”aî-n€ƒYˆºÔqîq{/áϺFPô®GÁ·„‡Æ …9ÃÆhÆÔµ` ST êT×B* YÔâîx¯EŽv©:Â0†)ÀaŒád 9»#š1g@²˜ƒä'/ù$BªÈÅ~ñdäÁݪ%¢‹Udãô¨WƒF!Æ ºâÆЂ}Nù¸¢çà°Hu’ˆ(¨þ÷ª/C€!Î6Ãc Æ,fÀ y¾vÅ~A‘DüA ÔE2ÚþÁýxßû£ÐFßA… -ü@ð¼Ð‚1ò{ŠÈ°~Añ}ïkàþeøÃøÛ„ŒÂ7à3` ‡Àm±1ðÇ€Þ²—'9  ÷7¸wŇ(±0+!(²À‰ð~óP(˜‚ù·{ˆr|ò@\î÷6  4 ™@=k€;$k( B¨D8 |k¡ 5 Ú`y²0R 5ðN· Q@„XH„eÐHHk k0Ç  ×aSyY¨eØ…± 1׃Xp ‘»€…@å† Q£t y<¥‡¡ Š@P‚ˆ9‡8!;tkgate-2.0-b10/povray/arrow90.pov000644 001751 001751 00000002752 10215444361 017365 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.25; #declare R2 = 0.6; #declare ArrowButton = union { object { cylinder { -0.65*x, 0*x, R } } object { cone { <0,0,0>, R2, <0.6,0,0>, 0 }} texture { MyAluminum3 } } union { object { ArrowButton rotate 90*z } } // // Where are we anyway? // camera { location <0, 0, -20> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-10.0, 10.0, -10> colour White*1.5 } light_source { <10, -20, -10> colour White*1 } tkgate-2.0-b10/povray/arrow0.pov000644 001751 001751 00000002754 10215466736 017310 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.25; #declare R2 = 0.6; #declare ArrowButton = union { object { cylinder { -0.65*x, 0*x, R } } object { cone { <0,0,0>, R2, <0.6,0,0>, 0 }} texture { MyAluminum3 } } union { object { ArrowButton translate 0*x } } // // Where are we anyway? // camera { location <0, 0, -20> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-10.0, 10.0, -10> colour White*1.5 } light_source { <10, -20, -10> colour White*1 } tkgate-2.0-b10/povray/arrow0.pov.orig000644 001751 001751 00000003136 10215443533 020230 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.75; #declare ArrowButton = intersection { object { cylinder { -1*x, 0*x, R } } plane { x, 0 rotate 45*z } plane { x, 0 rotate -45*z } box { <-2,0.25,-2>, < -0.5, 1, 2> inverse } box { <-2,-0.25,-2>, < -0.5, -1, 2> inverse } plane {z,-0.3 } texture { MyAluminum3 } } union { object { ArrowButton translate 0*x } } // // Where are we anyway? // camera { location <0, 0, -18> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-10.0, 10.0, -10> colour White*1.5 } light_source { <10, -20, -10> colour White*1 } tkgate-2.0-b10/povray/tire.pov000644 001751 001751 00000003047 10215467633 017032 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum = texture { pigment { rgb <0.7, 0.7, 0.7> } finish { ambient 0.3 diffuse 0.7 reflection 0.1 brilliance 1 specular 0.1 roughness 0 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // #declare Rubber = texture { pigment { rgb <0.458824, 0.458824, 0.458824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 3 specular 0.2 roughness 0.1 } normal { bumps -0.1 scale <1, 0.1, 0.1> } } #declare R = 1; #declare RI = 0.43; #declare RC = 0.7; #declare RIC = 0.2; #declare RotateButton = union { torus { R, RI rotate 90*x texture { Rubber } } cone { <0,0,-0.4>, RIC, <0,0,-.3>, RC texture { MyAluminum }} torus { RIC, 0.05 rotate 90*x translate -0.4*z texture { Rubber } } } union { object { RotateButton translate 0*x rotate 65*y} } // // Where are we anyway? // camera { location <0, 0, -44> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-50.0, 50.0, -10> colour White*1 } light_source { <-10, -10, -20> colour White*1 } tkgate-2.0-b10/povray/arrow180.pov000644 001751 001751 00000002753 10215444511 017443 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.25; #declare R2 = 0.6; #declare ArrowButton = union { object { cylinder { -0.65*x, 0*x, R } } object { cone { <0,0,0>, R2, <0.6,0,0>, 0 }} texture { MyAluminum3 } } union { object { ArrowButton rotate 180*z } } // // Where are we anyway? // camera { location <0, 0, -20> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-10.0, 10.0, -10> colour White*1.5 } light_source { <10, -20, -10> colour White*1 } tkgate-2.0-b10/povray/arrow0.png000644 001751 001751 00000003137 10215444213 017246 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®TIDATìÖ¿jÂPÇñ{‚iD¡…Nµ³/Ô‡pµÏàÒÁY|ƒ®N] %DH²è ÕHPRìMrO»uµÈ=ü>Op–/¿ƒ€,†€,†€,†€,†€,†€,†€,†€,†€,†€,†€,†€…cæKŸÿKÆÌA¡aÁ°pA ‡4,.Ž“ùü}0xBÃ"!`9ø¥T»í*ì°\äûþ¥o€3ØíÓé[©TÙlâf³á839Ëe°X,•R̪۽í÷NIƒ X`!βN–]7÷Ì7yÞIÓ«4u×너”RD* £ñø;, Xˆý^EQ~<~U«ucŒÖßÆy^Ìf/ž÷Z†è÷ÇnµÜÑèñT5Ø®téà } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 0.25; #declare R2 = 0.6; #declare ArrowButton = union { object { cylinder { -0.65*x, 0*x, R } } object { cone { <0,0,0>, R2, <0.6,0,0>, 0 }} texture { MyAluminum3 } } union { object { ArrowButton rotate 270*z } } // // Where are we anyway? // camera { location <0, 0, -20> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-10.0, 10.0, -10> colour White*1.5 } light_source { <10, -20, -10> colour White*1 } tkgate-2.0-b10/povray/arrow90.png000644 001751 001751 00000003157 10215444363 017347 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®XIDATìÖMNÂ@Æñ™é´2jXòd…ÇðœÎPÜ@½.I`G2 ¨b".JpS)…×…GÓÌäùàÙüó¾ÀbÀbÀbÀbÀbÀbÀbÀbÀbÀbÀbØqDTôøGØeÛm¦õvv­×Íñø½ßFîBÀn"¢ùIDATìÚ±jÂ@Àñï»^k!…€K¡UhFqïô|ÎÝú ´qpéR°ƒ±¡’ëp >€ ÷ñÿM d¸åÏÝ}„€PÕñøVä+¾./¯¯oÞû~eYÛ6³Ùã|þ|úý…VŠs"`;ŽM†êúGDº.„º®‘¢ÝšÃئ²|ïœSï}¼ñÖ5ógƒØmZ¯¿§Ó§²UÕ{U}l·Û¸Ãv`›TU$ˆ„øìœ+Šþ¥…ó#`›F£á~ß4Í®×ëÅ„9B›DÀ69wu8üyݶ¿ÎÅÑã+ƒt¹\^z 8¿ÕêSä&ϳͦVíšf—çÙdrÏÚ¶)NžUõô§+굇)´MÇV‰Ö6îÀ@ÂH #` a $Œ€„00FÀ@ÂHØ?ÿÿàN±3KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATíÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`ƘùááhL›IEND®B`‚tkgate-2.0-b10/povray/cwrotate.png000644 001751 001751 00000003530 10215213505 017657 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®äIDATìÙÍJQÆñsšD£ùž¡- J·Ò… “E«¥àfâFˆÔMîÃ+ð"ìô ’…nÄVK “:˜43Ú$2©:d|»¤Îáù­Â¬žÍŸw† `‰!`‰!`‰!`‰!`‰!`‰!`‰!`‰!`‰!`‰!`‰Å£Oˆˆ~pΣ]O+ˆˆ<ï®Ýÿº¸èd2Éùù™ååE†’•Ã…Qo€Q""!‚FÃöý®ã8®ëA`ÛmÏs×ÖJÕê:V .°Rˆ¨Ñxv}ý7‘ˆMM½š›Kéúôø8u:öÁÁçZí+c¬Z]g8ŪÀVÝßÞÞÛö¥eµ›Í–ë:¹¥¥R±XÒ4ÚÝýx||¸°ð’1*_—Ëo‘±ìpÕáûe âq&Dýäähsó½al1Æ®®ÜVë{·;[©lÔë?LÓ Ã¡a¬D½F«£×d2iÓ§§_*•w†ñæáÀêzNÓ¨Vû¶·gæó/nnaF=Fÿ+‚ˆ„¸ÌfŸÛvÓ÷½ryåñõ˜ˆvv>íïÿ+¤ÓZ*•åœéz.ÚÁ0Xý¾ŸLNöz¿ …ìÿÏ9çÛÛVW§û3&4m&KèzÀ øÿÿ Kd›IDATìÛMKAÇñF³\Y³EA=´!d *„»ù.zyð=øšÄ訲ŠQ’âúši¶h©0ÝB: 2ÓïsË\¾ÌÀüWh~8GF£‘R:~üY"„D£¡ht¯Xl¤ÓOv»{';„­3Æb±]ﶀ2¼ ‚ûàÀT¯?êú\Q.6ÏXBÈr¹/ËR$ré÷Ÿ¹ÝN` `~¬×ß …Î5MSÕ{³Ùd· ¡®/5ím6³öz_åòƒÃaq¹P/'0?$IÌåŠÁà•,{ÆãQ.WÊfÕRI«Õ†‚ -«V«™J¥ƒQ8¬ `>`ƒ+”Òdò9¸EZ(¨ÝnÓ`08N‹Å6™¼æów¢H‰[ÔË ÌJi&£éºèó)„á°7ŸÏ*µZ-)Š'¿A½ } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 1; #declare RI = 0.33; #declare RC = 0.7; #declare AA = 45; #declare AD = 0.5; #declare A = 30; #declare RotateButton = union { intersection { torus { R, RI rotate 90*x } union { plane { x,0 rotate (90-A)*z } plane { x,0 rotate (-90+A)*z } } // plane {z, -1 inverse} } object { cone { <0,0,0>, RC, <1,0,0>, 0 } rotate z*-90 translate R*x rotate z*A } texture { MyAluminum3 } } union { object { RotateButton translate 0*x } } // // Where are we anyway? // camera { location <2, -2, -44> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-50.0, 50.0, -10> colour White*1 } light_source { <-10, -10, -20> colour White*1 } tkgate-2.0-b10/povray/tire.png000644 001751 001751 00000003153 10661713136 017005 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàNIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ìÿÿ­Ì†ž@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£ÙIDATìÛÁëÁ`Çñ ϳ,!’³»pså¢üþ堖î.N’³‰“Üœ\¤\'²y2µV[öû'ö멧ïë/x×Ó§çi50Ïf³™¦i¬+À?/— ë¾ÅbJ¥RûýÞ4Í×ëµZ­XGðÁ ̧çóiY¥´V«É²Œêv»¬£@ø`ÀÇžç=BƸÙlF"pÐ|‚så$IŠ¢èºnšæ÷ûF£•JEEÖ] |0`e2UUA˜ÏçAضmÛv$W4`ÀJ§ÓãÍfÓn·)¥Ùl–’ËåXwðÁ€y£iBh¹\ªª:N)¥A‹ÅR©Ä: „Ìß÷ãñ¸ëº’$ ß÷1ÆÕju·Û±NáƒóFUUÇqz½ž¢(£Ñ!äyÞét‚Ñ\‚Cå(ŠNg»ÝÖëuA~¿ßáp€¯Ð\‚sȲ¬V«%‚®ë±X,™L6r¹¼^¯Y§ÅX€ðÝn7Œñp8Dɲlš¦aÇã‘uÜÀ †aB‰„ëºï÷ûz½AÀº „n`>Ýï÷|>ï8!ä|>SJáýÌ%ø‰gý~ÿóùL&Ö!à¿üÿÿ ÄGDIDATì×1 € þ­Íá<0Œy`0Œ Æ c†1Ø€aLÀ0&`0Œ Æ c†1Ø€a,ÿÿt '@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿõˆ£@IDATíÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`ÆÑÁ½dÑ8àöIEND®B`‚tkgate-2.0-b10/povray/arrow180.png000644 001751 001751 00000003213 10215444517 017421 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®dIDATìÖ½kÂ@Æñ»‹‘Ä:D!èPÐEšÎöow*¤Q_ 8H¬1F£1ùuèÖµJ¸ãùŒ7=p|¹CÀ CÀ CÀ CÀ CÀ CÀ CÀ CÀ CÀ CÀ CÀ CÀš#¢¢'À!`í÷§Å"+z<Ö ‡¥$‘x„5†€õDDãqÉq^›M\±Îp»"¢~_T*m×ey^û=ù£èp¥¢ÀEÑm:}’ò¹^gIÂF£÷åÒ‚°ÓiFy>ÿbŒÕjÕn÷¥ÝnpÎ‹Þ ÿ‚€µBDëµ+¥kšY䜋Ùl×ë}0ÆV«½ç½™fórIÂÐŒc|¾t€€õAD›M£\Ûí.Žã,K¯×sn…Dt<~{^ëp-Ë:ŸOŽSÅó«¬ "òýÕ`ð™¦ÎYžg¶]¹ÝR¢‹”2Ë2Ã0&߶-! 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "metals.inc" // // The sky // #declare CV = 0.85098039215686274509; sky_sphere { pigment { colour red CV green CV blue CV } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum1 = texture { Chrome_Metal normal { bumps -0.4 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum2 = texture { Chrome_Metal normal { bumps -0.1 scale <1, 0.001, 0.001> } } // // Based on Brushed_Alumium with slightly smaller bumps // #declare MyAluminum3 = texture { pigment { rgb <0.458824, 0.458824, 0.858824> } finish { ambient 0.3 diffuse 0.7 reflection 0.05 brilliance 8 specular 0.5 roughness 0.1 } normal { bumps -0.1 scale <1, 0.001, 0.001> } } #declare R = 1; #declare RI = 0.33; #declare RC = 0.7; #declare AA = 45; #declare AD = 0.5; #declare A = 30; #declare RotateButton = union { intersection { torus { R, RI rotate 90*x } union { plane { x,0 rotate (90-A)*z } plane { x,0 rotate (-90+A)*z } } // plane {z, -1 inverse} } object { cone { <0,0,0>, RC, <1,0,0>, 0 } rotate z*-90 translate R*x rotate z*A } texture { MyAluminum3 } } union { object { RotateButton translate 0*x scale <-1,1,1> } } // // Where are we anyway? // camera { location <2, -2, -44> // Full view look_at <0,0,0> } // // Let there be light! // light_source { <-50.0, 50.0, -10> colour White*1 } light_source { <-10, -10, -20> colour White*1 } tkgate-2.0-b10/povray/ccwrotate.png000644 001751 001751 00000003532 10215213623 020025 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàZIDATxœìÓA À0À¿Ásƒ>dI«`Ÿí™Y@Óù¼30„ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„Â.ÿÿùàÒÎKIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®êIDATìÙËJQÇñsÒ qlgºhë¢T M©tSBÁñBî¼<ƒ/â+ú–¨¢PB M!c3Ä»ÄNÌd0CsºJé:2œÃï³:Ëÿæ˹!`Ž!`Ž!`Ž!`Ž!`Ž!`Ž!`Ž!`Ž!`Ž!`Ž!`ŽI~ψ1ö´ ”ú; <, ÆX½Þ´¬;Ó´®®®Ãay`àu<%(Y8´P(ø=´c¬Xôòù3Ç©Ú¶ýðPó<ïâ¢bÛ¿‰øÒÒ  v`q<˜K¥nGGHQÞõ÷¿Ôõ7Á`ëööüð0½·—%„ a‘ `AìîfêõÎÁÁh¥’/—+¡P—eâõõ½m6;ç翬®~ØØØL§·cË˳hX Xª>>þ=:ú¾ÑÈ}¯VoVVæÆƆ5­›’J}UÕ IÓ,f³? cJ×{üÚßH‚$YîR”ÀÄÄL,ö)™ül“ºÞC)¥”FLUÏïï[ããSµZ#“ùñ÷¸†€¡ªaMÓ\·•Ë•L3·µu°¶¶ùï7R$òjÿÛÐЈ¢tŸœ”ýÚGhAôö*²,žš;;ë®{¹¸˜˜žžüiAÇq$)ˆû¯0þÿÿ¹1«À—IDATìÚ±KaÇq/ ¡ 4L ìt GmqÓíšÄÍ ­?CÜœ¤%òppsQ”@A—Ò¥ïNïT,ïih [yß~Ÿõ–wùòrïó `A8²,ÛZ­r<îF¯Ny£^]7çóO˲$IÒusWç„íBÀâX,–´Ùl•J=8 ….~u¹ŽÃáÓn÷…13•RwsDØ6ü‹Ãë=Z¯í¦é¨×ûùüc¿? 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Ïè!Ã\ýž ½þä&Ýz†‰i$Ë ‘Ë…,{ë |$ˆx5n’V„IDATŠ”í™þf}<,0M¦ž?´ 7ªœ)2ÚŽiär¡È!§ªñ£6Ø›`Æ¥”0]Ãç=›Ã@?ºY¤(È=§ŽnÀ{–5‡¤m»3!ä,î°Š3¯¤èùz°Ô'ÔD¥b{áóž™7ÝηƒØyàådAæJ!sÎlPwWcfhͬëQB†ý•×“ù¶fÑ‚u;iï°¬¨s^Oæu³ªÒœºežy¨Y¦JØ]’ } normal { leopard 0.1 turbulence .1 scale <0.005,0.05,0.005> } finish { ambient 0.3 diffuse 0.6 } } #declare CactusSpine_Text = texture { pigment { rgb <.9,.9,.1> } finish { ambient 0.3 diffuse 0.6 } } // // A period // #declare char_Period= cylinder {<0,0.5,0>,<0,0.5,1>,0.5} #declare Post_Stone = texture{ pigment{White} normal{ granite 0.075 scale 0.24 } finish{phong 0.1 phong_size 200 diffuse 0.2 ambient 0.5 } } #declare Sand_Text = texture { pigment { colour red 0.95 green 0.64 blue 0.38 } normal { crackle .25 turbulence 0.2 scale <1,0.05,0.1> rotate 30*y } finish { ambient 0.7 diffuse 0.4 } } // // The clouds // #declare GateClouds = plane { y, 300.0 hollow on pigment { bozo turbulence 1 colour_map { [0.0 0.4 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 1.0 green 1.0 blue 1.0 filter 1.0] [0.4 0.8 colour red 1.0 green 1.0 blue 1.0 filter 1.0 colour red 0.8 green 0.9 blue 0.9] [0.8 1.001 colour red 0.9 green 0.9 blue 0.9 colour red 0.8 green 0.8 blue 0.8] } quick_colour red 0.7 green 0.7 blue 1.0 scale <1000.0, 200.0, 800.0> } finish { ambient 0.7 diffuse 0.0 } translate -450*x rotate 6*y } // // The ground // #declare SandDunes = intersection { plane { z, 0 } height_field { png "hills.png" smooth translate <-0.5,0,-0.85> scale <40,0.5,40> } hollow on texture { Sand_Text } } #declare GrassTexture = texture { pigment { waves turbulence 0.01 colour_map{ [0.0 colour rgb <0.2,0.4,0.1>] [0.98 colour rgb <0.28,0.49,0.17>] [1.0 colour rgb <0.38,0.39,0.11>] } } scale <0.001,0.0001,.15> finish{ ambient 0.2 diffuse 0.6 } } #declare OldGrassTexture = texture { pigment { bozo turbulence 0.1 colour_map { [0.0 1.0 colour red 0.2 green 1.0 blue 0.2 filter 0 colour red 0.2 green 0.8 blue 0.2 filter 0] } } normal{ wrinkles 0.1 scale 0.24 } finish { ambient 0.2 diffuse 0.2 } } #declare GrassHill = intersection { plane { z, .1 inverse } height_field { png "hills.png" smooth translate -0.5*x scale <40,3,40> } hollow on texture { GrassTexture } } #declare XGrassHill = union { // height_field { // png "hills2.png" // smooth // translate -0.5*x // translate 5*z // scale <200,50,200> // } height_field { png "hills2.png" smooth translate -0.5*x scale <50,3,50> } intersection { plane { y, 0 } plane { z, 0 inverse } } hollow on // texture { GrassTexture } texture { pigment { checker color Red, color Green } } } #declare GateGround = union { object { SandDunes } object { GrassHill } } #declare CowOrFlat=0.5; #declare CowHeight=1.1; #declare CowThickness = 0.5; #declare CowLegLength = 0.5; #declare CowLegThickness = 0.1; #declare Cow_Texture = texture { pigment { bozo frequency 0.9 scale .15 color_map { [0.1 colour rgb <0,0,0> ] [0.2 colour rgb <1,1,1> ] } } finish { ambient 0.2 } } #declare CowLeg = union { cylinder { 0*y, CowLegLength*y, CowLegThickness } object { sphere { <0,CowLegLength,0>, CowLegThickness } } } #declare AndGateCow = union { union { box { <0.0,0.0,0.0>, <0.8,1.1,CowThickness> } object { cylinder { 0.0*z, CowThickness*z, 0.55 } translate <0.8,0.55,0.0> } translate CowLegLength*y } object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } texture { Cow_Texture } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } #declare OrGateCow = union { intersection { box { <0.0,0.0,0.0>, } object { cylinder { -2*z, 2*z, CowHeight inverse } translate <-CowHeight*0.85,CowHeight/2,0> } translate CowLegLength*y } intersection { object { cylinder { 0*z, CowThickness*z, CowHeight } translate } object { cylinder { -2*z, 2*z, CowHeight } translate } plane { x, 0.5 inverse } translate CowLegLength*y } object { CowLeg } object { CowLeg translate <0.75,0,0> } object { CowLeg translate <0,0,CowThickness> } object { CowLeg translate <0.75,0,CowThickness> } texture { Cow_Texture translate 10*x } } // // Define the posts that go on the sides of the gate. // #declare Post = union { // cylinder { 0*y, 4.25*y, PostRadius } intersection { object { box { <-PostRadius,0, -PostRadius>, } } object { box { <-PostRadius,0, -PostRadius>, } rotate 45*y } } object { sphere { <0,0,0>, PostRadius } translate 4.25*y } object { sphere { <0,0,0>, PostRadius } translate 4.75*y } // texture { White_Marble } texture { Post_Stone } // texture { PinkAlabaster } } // // A spike within the gate. D is the distance from the center and is used both // to place the spike and to compute its height. // #macro Spike(D) #local H = sin(acos(D/8.3))*8.3 - 5; union { object { cylinder { 0.2*y, H*y, 0.05 } } merge { object { Sphere scale <0.05, 0.05, 0.05> translate 0.1*y } object { Cone_Y scale <0.05, 0.1, 0.05> translate 0.2*y } object { Cone_Y scale <0.05, 0.05, 0.05> translate 0.025*y } translate H*y } translate D*x } #end // // A spike on the fence // #declare FenceSpike = union { object { cylinder { 0.2*y, 4.0*y, 0.05 } } merge { object { Sphere scale <0.05, 0.05, 0.05> translate 0.1*y } object { Cone_Y scale <0.05, 0.1, 0.05> translate 0.2*y } object { Cone_Y scale <0.05, 0.05, 0.05> translate 0.025*y } translate 4.0*y } } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } // // Cut out of NOR gate. // #declare UnNOrGate = union { intersection { box { <-0.001,0.1,0>, <0.25,0.5,0.1> } object { cylinder { -0.1*z, 0.2*z, 0.5 } translate <-0.4,0.3, 0.0> inverse} } intersection { object { cylinder { -0.001*z, 0.2*z, 0.4 } translate <0.25,0.5, 0> } object { cylinder { -0.1*z, 0.2*z, 0.4 } translate <0.25,0.1, 0> } plane {x, 0.25 inverse } } object { cylinder { -0.001*z, 0.1*z, 0.05 } translate <0.75, 0.3, 0> } } #declare NOrGate = union { box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare DoorBase = union { Spike(1.7) Spike(1.4) Spike(1.1) Spike(0.8) Spike(0.5) Spike(0.2) } #declare Fence = union { // // Fence cross beams // box { <2.0,0.5,-0.05>, <50.0,0.55,0.05> } object { box { <2.0,0.5,-0.05>, <50.0,0.55,0.05> } translate 3.3*y } // // Fence // #local i = 0; #while (i < 60) object { FenceSpike translate (2.6+0.4*i)*x } #local i = i + 1; #end } #macro Wire(X1,Y1,X2,Y2) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/3.1415926; object { box { <0,0,0>, } rotate R*z translate } #end // // Left half of the master/slave flip-flop circuit // #declare FlipFlopLeft = union { object { NOrGate translate < -1.2,2.3,0> } object { NOrGate translate < -1.2,0.4,0> } Wire(-1.875,0.5, -1.175,0.5) // Lower-left input B Wire(-1.875,2.75, -1.175 ,2.75) // Upper-left input A Wire(-0.4,2.575, -0.025,2.575) // Upper stage connect Wire(-0.4,0.675, -0.025,0.675) // Lower stage connect // // UL to LL feedback path // Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A // // LL to UL feedback path // union { Wire(-0.1,2.575, -0.1,2.075) // out/down from UL Wire(-0.08,2.125, -1.575,1.25) // Diagonal Wire(-1.575,1.25, -1.575,0.85) // Lower-left input A vertical Wire(-1.575,0.85, -1.175,0.85) // Lower-left input A scale <1,-1,1> translate 3.3*y } } // // Right half of the master/slave flip-flop circuit // #declare FlipFlopRight = union { object { NOrGate translate < 0.4,2.125,0> } object { NOrGate translate < 0.4,0.575,0> } Wire(1.3,2.4, 1.875,2.4) // Upper-right output Wire(1.3,0.85, 1.875,0.85) // Lower-right output Wire(0.025,2.575, 0.45,2.575) // Upper stage connect Wire(0.025,0.675, 0.45,0.675) // Lower stage connect // UR to LR feedback Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in union { Wire(1.525,2.4, 1.525,2.125) // UR Wire(1.545,2.155, 0.025,1.25) // diagonal Wire(0.025,1.25, 0.025,1.025) // LR vertical Wire(0.025,1.025, 0.45,1.025) // LR in scale <1,-1,1> translate 3.3*y } } #declare FlipFlopCutOutLeft = union { object { UnNOrGate translate < -1.2,2.3,0> } object { UnNOrGate translate < -1.2,0.4,0> } } #declare FlipFlopCutOutRight = union { object { UnNOrGate translate < 0.4,2.125,0> } object { UnNOrGate translate < 0.4,0.575,0> } } // // This is the lettering in the logo. // #declare Lettering = intersection { union { union { object { char_T translate -2*x translate 88*y rotate (AngleStart+0*AngleStep)*z } object { char_K translate -2*x translate 88*y rotate (AngleStart+1*AngleStep)*z } object { char_G translate -2*x translate 88*y rotate (AngleStart+2*AngleStep)*z } object { char_A translate -2*x translate 88*y rotate (AngleStart+3*AngleStep)*z } object { char_T translate -2*x translate 88*y rotate (AngleStart+4*AngleStep)*z } object { char_E translate -2*x translate 88*y rotate (AngleStart+5*AngleStep)*z } object { char_2 translate -2*x translate 88*y rotate (AngleStart+6.5*AngleStep)*z } object { char_Period translate -2*x translate 88*y rotate (AngleStart+7.25*AngleStep)*z } object { char_0 translate -2*x translate 88*y rotate (AngleStart+8*AngleStep)*z } scale <1.0,1.0,0.5> } intersection { cylinder { 0*z, 0.05*z, 88 } cylinder { -.01*z, 0.06*z, 87 inverse } } intersection { cylinder { 0*z, 0.05*z, 94 } cylinder { -.01*z, 0.06*z, 93 inverse } } translate -90*y scale 0.1 } plane { x, -2 inverse } plane { x, 2 } } #declare LeftDoor = union { intersection { object { DoorBase scale <-1,1,1> } object { FlipFlopCutOutLeft translate <0,0,-0.05> inverse } } object { FlipFlopLeft translate <0,0,-0.05> } translate 1.9*x } #declare RightDoor = union { intersection { object { DoorBase } object { FlipFlopCutOutRight translate <0,0,-0.05> inverse } } object { FlipFlopRight translate <0,0,-0.05> } translate -1.9*x } #declare Brackets = union { box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,2.8,0> } // Upper-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <-2.125,0.45,0> } // Lower-left bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,2.45> } // Upper-right bracket box { <0,0,0>, <0.3,0.05,0.1> translate <1.825,0.8,0> } // Lower-right bracket } // // This is all the ironwork in the gate // #declare IronWork = union { object { Lettering translate <0,4,-0.05> } object { Fence } object { Fence scale <-1,1,1> } object { Brackets translate -0.05*z } object { LeftDoor rotate -0*y translate -1.9*x } object { RightDoor rotate 0*y translate 1.9*x } texture { Wrought_Iron } } fog { distance 1500 color rgb<0.3, 0.4, 1.0> fog_type 2 fog_offset 100 fog_alt 1 turbulence 0.1 turb_depth 0.2 } sky_sphere { pigment { gradient y colour_map { // [0.0 1.0 colour red 0.1 green 0.3 blue 1.0 // colour red 0.1 green 0.6 blue 1.0] // [0.0 1.0 colour red 0.4 green 0.4 blue 1.0 // colour red 0.6 green 0.7 blue 1.0] [0.0 1.0 colour red 0.3 green 0.5 blue 0.6 colour red 0.3 green 0.4 blue 1.0 ] // [0.0 1.0 colour red 0.0 green 0.0 blue 0.0 // colour red 0.0 green 0.0 blue 1.0] } scale 0.5 } } #declare BoardWidth=2.8; #declare BoardHeight=0.5; #declare BoardGap = 0.025; #declare Board = difference { box { <0,0,0>, } } #declare SignBase = union { object { Board translate (1.5+0*(BoardHeight+BoardGap))*y } object { Board translate (1.5+1*(BoardHeight+BoardGap))*y } object { Board translate (1.5+2*(BoardHeight+BoardGap))*y } box { <0.0,0,0.12>, <0.1,1.5+3*BoardHeight+2*BoardGap,0.22> } box { , } translate -BoardWidth/2*x //Other possible woods: 18, 19, 20, 29, 30, 31 texture { T_Wood31 scale 0.5 } } #declare CP_X = -BoardWidth/2+0.2; #declare CP_Y = 2.7; #macro newline() #declare CP_X = -BoardWidth/2+0.2; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + 0.22*C; #end #macro putchar(C) object { C scale <0.05,0.05,0.05> translate texture { T_Wood4 } } #declare CP_X = CP_X + 0.22; #end #macro putschar(C) object { C scale <0.04,0.04,0.04> translate texture { T_Wood4 } } #declare CP_X = CP_X + 0.22*0.04/0.05; #end ///////////////////////////////////////////////////////////////////////////// // // Put up the sign base and subtract out all of the letters. // ///////////////////////////////////////////////////////////////////////////// #declare Sign = difference { object { SignBase } //Opening Gates to //Digital Circuit //Simulation putchar(char_T) putschar(char_H) putschar(char_E) kern(0.8) putchar(char_G) putschar(char_A) putschar(char_T) putschar(char_E) putschar(char_W) putschar(char_A) putschar(char_Y) kern(0.8) putchar(char_T) putschar(char_O) newline() putchar(char_D) kern(-.15) putschar(char_I) kern(-.15) putschar(char_G) kern(-.15) putschar(char_I) kern(-.15) putschar(char_T) putschar(char_A) putschar(char_L) kern(0.8) putchar(char_C) kern(-.15) putschar(char_I) kern(-.15) putschar(char_R) putschar(char_C) putschar(char_U) kern(-.15) putschar(char_I) kern(-.15) putschar(char_T) newline() putchar(char_S) kern(-.15) putschar(char_I) kern(-.15) putschar(char_M) putschar(char_U) putschar(char_L) putschar(char_A) putschar(char_T) kern(-.15) putschar(char_I) kern(-.15) putschar(char_O) putschar(char_N) } #declare SpineSet = union { #local SpineR = 0.005; #local SpineLen = 0.1; object { cone { <0,0,0>, SpineR, , 0.0 } rotate 20*z } object { cone { <0,0,0>, SpineR, , 0.0 } rotate -20*z rotate 20*y } object { cone { <0,0,0>, SpineR, , 0.0 } rotate -20*z rotate -20*y } texture { CactusSpine_Text } } #macro SpineRow(X1,X2,Y) union { #local X = X1; #while (X <= X2) object { SpineSet rotate 90*y translate X*x } #local X = X + 0.05; #end translate Y*y } #end #declare CactusAndLeaf = union { #local TT = 0.05; union { box { <-0.35,-0.25,-TT>, <0,0.25,TT> } cylinder { -TT*z, TT*z, 0.25 } translate <-0.25,0,0> } object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.1,0.1) translate -TT*z } object { SpineRow(-0.55,-0.1,-0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,0.2) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.2) translate -TT*z } union { object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.1,0.1) translate -TT*z } object { SpineRow(-0.55,-0.1,-0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,0.2) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.2) translate -TT*z } scale <1,1,-1> } scale 0.9 } #declare CactusOrLeaf = union { #local TT = 0.05; intersection { union { box { <0,0,-TT>, <0.25,0.5,TT> } intersection { box { <0,0,-TT>, <0.7,0.5,TT> } object { cylinder { -1*z, 1*z, 0.5 } translate <0.25,0,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <0.25,0.5,0> } } } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.4,0.25,0> } translate <-.7,-.25,0> } object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.15,0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.1) translate -TT*z } object { SpineRow(-0.6,-0.3,0.2) translate -TT*z } object { SpineRow(-0.6,-0.3,-0.2) translate -TT*z } union { object { SpineRow(-0.55,-0.1,0) translate -TT*z } object { SpineRow(-0.55,-0.15,0.1) translate -TT*z } object { SpineRow(-0.55,-0.15,-0.1) translate -TT*z } object { SpineRow(-0.6,-0.3,0.2) translate -TT*z } object { SpineRow(-0.6,-0.3,-0.2) translate -TT*z } scale <1,1,-1> } scale 0.9 } #macro Cactus() union { #local CW = 0.2; #local CH = 0.4; sphere { <0,0,0>, CW scale <1,CH/CW,1> } #local RZ1 = 20*(rand(cactusRand)-1)-5; #local RZ2 = 20*(rand(cactusRand)-0); #local RX1 = 20*(rand(cactusRand)-0.5); #local RX2 = 20*(rand(cactusRand)-0.5); #local RY = 60*(rand(cactusRand)-0.5); #local L1 = rand(cactusRand); #local L2 = rand(cactusRand); #if (L1 < 0.5) object { CactusOrLeaf rotate 30*x rotate RX1*z rotate RZ1*z translate <-0.15,-0.1,0> } #else object { CactusAndLeaf rotate 30*x rotate RX1*z rotate RZ1*z translate <-0.18,-0.1,0> } #end #if (L2 < 0.5) object { CactusOrLeaf rotate 180*z rotate RX2*x rotate RZ2*z translate <0.15,0.1,0> } #else object { CactusAndLeaf rotate 180*z rotate RX2*x rotate RZ2*z translate <0.18,0.1,0> } #end #local A = 0; #while (A < 360) #local B = -30; #while (B < 60) #local DX = CW*cos(B*Pi/180); #local DY = CH*sin(B*Pi/180); object { SpineSet rotate B*z translate rotate A*y } #local B = B + 10; #end #local A = A + 30; #end rotate RY*y texture { Cactus_Text } } #end #declare Cacti = union { object { Cactus() translate <-5,.45,-8> } object { Cactus() translate <-8.9,.7,-4.7> } // Wing reflecting object { Cactus() translate <5.5,.4,-7> } object { Cactus() translate <2,.42,-8> } object { Cactus() translate <8,.45,-6> } } // // Put it all together here. // object { GateGround } // The ground object { GateClouds } // The clouds #if (showPosts) object { Post translate -(1.95+PostRadius)*x } // The left gate post object { Post translate (1.95+PostRadius)*x } // The right gate post #end #if (showFence) object { IronWork } // The iron work #end #if (showDragons) #if (DGView = 7) object { Dragon(3) rotate 0*y scale 0.4 translate <2,11,20> } #else object { Dragon(1) rotate 30*y scale 0.4 translate <-4.5,2.3,-4> } object { Dragon(2) rotate 30*y scale <-0.4,0.4,0.4> translate <4.3,2.1,-4> } #end #end #if (showSign) object { Sign rotate -40*y translate <-3.8,0,-10> } #end #if (showCacti) object { Cacti } #end #if (showTrees) object { TREE scale 6 translate <-11,0.2,5> } object { TREE scale 6 translate <-4,0.8,7> } object { TREE scale 6 translate <10,1.3,7> } #end // // Where are we anyway? // camera { #switch (DGView) #case (1) location <6.0, 7.25, -20> // Full view look_at <0,2.25,0> #break #case (2) location <-4.5, 2, -8> // left dragon feet look_at <-4.5,0,-4> #break #case (3) location <4.3, 2, -8> // left dragon feet look_at <4.4,0,-4> #break #case (4) location <-5, 0.6, -9.5> // Cactus view look_at <-5,.6,-8> #break #case (5) location <0.0, 2.25, -8> // Closeup look_at <0,2.25,0> #break #case (6) // Sign closeup location <-3,2,-13> look_at <-3.8,2,-10> up <0,1,0> #break #case (7) // Gate closeup location <0,2.5,-6> look_at <0,2.5,0> up <0,1,0> #end } //light_source { <50.0, 40.0, -20.0> colour White *2 } //light_source { <-99.0, 79.0, 20.0> colour White *1 } //light_source { <0, 5.0, -20.0> colour White *1 } //light_source { <0, 20.0, 20.0> colour White *1 } // // Let there be light! // #if (DGView = 7) light_source { <200.0, 250.0, -250> colour White *3 shadowless } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } #else light_source { <200.0, 250.0, -250> colour White *3 } light_source { <-50.0, 90.0, -30> colour White*0.1 shadowless } #end tkgate-2.0-b10/povray/gatelogo.png000644 001751 001751 00000223325 10324340616 017643 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOà éIDATxœì\M‹K~žz;&¾3d†I&„AÉpáNÁôº®îFE7/‚Þ‹èo¸ø î]*‚ø±ü Ü%«É$éz\TÕ©SÝý~æäÎYÌ[Ý]uªª»ŸzÎ9uzøÅŸýUèÊÐÄ9hW5YcØP©H¦ÓJå\È•5hlÇí…a_ZxHF€D¢Ø#D±£BT`£¸h6Ó²Qå-ê¿zÃ+Òs-¯M´ìbèqªqe6?®*a¦tئÖ-§™Ë© &5,ØVE§ÌK[øæ§ÞÈ¢$Ï-iH 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specular 0.15 ambient 0.5 } } #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.2 } } #declare Paper = union { #local W = 0.5; #local H = 0.7; #local D = 0.01; box { <-W,-H,-D>, } union { union { object { text { ttf "cyrvetic.ttf" "Name: beak" 0.03, 0 } scale .3 } translate <-.9, 1.3,-0.02> } union { object { text { ttf "cyrvetic.ttf" "File: beak.v" 0.03, 0 } scale .3 } translate <-.9, 1,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Ver.: 2.0" 0.03, 0 } scale .3 } translate <-.9, 0.7,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Change Warn: Yes" 0.03, 0 } scale .3 } translate <-.9, 0.4,-0.02> } union { object { text { ttf "cyrvetic.ttf" "Ext Bar: Yes" 0.03, 0 } scale .3 } translate <-.9, 0.1,-0.02> } scale 0.4 translate -0.01*z texture { Text_Text } } texture { Paper_Text } } // // Basic arc (actually a ring) that is used as parts of the OR gate. // #declare GateArc= difference { object { cylinder { 0.0*z, 0.1*z, 0.5 } } object { cylinder { z, -z, 0.4 } } } // // Back arc of an OR gate // #declare OrBack = intersection { object { GateArc } plane {x, 0 inverse } plane {y, -0.3 inverse } plane {y, 0.3 } translate <-0.4,0.3,0.0> } // // Basic OR gate. // #declare OrGate = union { box { <0.0,0.5,0.0>, <0.25,0.6,0.1> } box { <0.0,0.0,0.0>, <0.25,0.1,0.1> } // // The back of the OR gate // object { OrBack } // // Top-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.1,0.0> } plane {y, 0.3 inverse } } // // Bottom-half of OR curve. // intersection { intersection { object { GateArc } plane {x, 0 inverse } translate <0.25,0.5,0.0> } plane {y,0.3 } } } #declare NOrGate = union { // box { <0,0,0>, <0.1,0.05,0.05> translate <0.9,0.275,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.45,0>} // box { <0,0,0>, <0.1,0.05,0.05> translate <-0.1,0.1,0>} object { OrGate } difference { object { cylinder { 0.0*z, 0.1*z, 0.15 } } object { cylinder { z, -z, 0.05 } } translate <0.75, 0.3, 0> } } #declare Circuit = union { #local W = 0.75; #local H = 1.0; #local D = 0.1; #local T = 0.1; union { object { NOrGate translate <0.3,0.7,0> texture { Gate_Text }} object { NOrGate translate <0.3,-0.7,0> texture { Gate_Text }} // Outputs box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,1,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <1, 0.05, 0.05> translate <1.13,-.4,0> texture { Bus_Text }} // Bus inputs box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,0.9,0> texture { Bus_Text }} box { <0, -0.05, 0.001>, <0.5, 0.05, 0.05> translate <-.2,-.3,0> texture { Bus_Text }} // Bus crossing box { <1, -0.05, 0.001>, <2, 0.05, 0.05> translate <-2.2,0.3,0> texture { Bus_Text }} // Bus feed wire box { <-0.05, -0.05, 0.001>, <1.25, 0.05, 0.05> rotate 90*z translate <-.2,-.3,0> texture { Bus_Text }} // 1-bit inputs box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> translate <-.2,1.1,0> texture { Wire_Text }} box { <1, -0.0355, 0.001>, <2.5, 0.035, 0.035> translate <-2.2,-.5,0> texture { Wire_Text }} box { <0, -0.035, 0.001>, <0.5, 0.035, 0.035> rotate 90*z translate <-.2,1.1-0.035,0> texture { Wire_Text }} union { starttext(0.4, 0.5, 0.03, 0.15) putchar(char_G) putchar(char_4) putchar(char_2) texture { Gate_Text } } union { starttext(0.4, -0.9, 0.03, 0.15) putchar(char_G) putchar(char_3) putchar(char_5) texture { Gate_Text } } union { starttext(1.4, -0.65, 0.03, 0.15) putchar(char_W) putchar(char_6) putchar(char_1) texture { Bus_Text } } union { starttext(1.4, 0.75, 0.03, 0.15) putchar(char_W) putchar(char_8) putchar(char_7) texture { Bus_Text } } rotate 90*x } #local i = 0; #local PS = W - 0.05; #local Q = 0.3; #local PW = 0.05; #local PD = 0.05; #local L = 0.7; #while (i <= 3) #local Z = -1 + Q + (i/3.0)*(2-2*Q); // box { <-PS,-PD,Z-PW>, <-(PS+L),PD,Z+PW> texture { Pin_Text } } // box { , texture { Pin_Text } } #local i = i + 1; #end rotate x*-90 rotate y*20 rotate z*-20 translate -0.5*x } #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } object { Circuit } //object { Paper rotate x*20 rotate y*10 translate <-0.5,0.5,-1>} sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "metals.inc" #declare Plastic_Text = texture { pigment { rgb <.87, .8, .77> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare GreenPlastic_Text = texture { pigment { rgb <.7, .87, .67> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare RedPlastic_Text = texture { pigment { rgb <.87, .5, .47> } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #declare DarkPlastic_Text = texture { #local X = 0.5; pigment { rgb } normal { bozo 0.05 scale .1 } finish { specular 0.05 roughness 0.1 ambient 0.6 // diffuse 0.9 reflection 0.01 } } #macro RoundBox(W,H,D,R) union { sphere { <-W,-H,-D>, R } sphere { <-W,-H,D>, R } sphere { <-W,H,-D>, R } sphere { <-W,H,D>, R } sphere { , R } sphere { , R } sphere { , R } sphere { , R } cylinder { -W*x, W*x, R translate <0,H,D> } cylinder { -W*x, W*x, R translate <0,H,-D> } cylinder { -W*x, W*x, R translate <0,-H,D> } cylinder { -W*x, W*x, R translate <0,-H,-D> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,H,0> } cylinder { -D*z, D*z, R translate } cylinder { -D*z, D*z, R translate <-W,-H,0> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,D> } cylinder { -H*y, H*y, R translate } cylinder { -H*y, H*y, R translate <-W,0,-D> } box { <-W,-H-R,-D>, } box { <-W,-H,-D-R>, } box { <-W-R,-H,-D>, } } #end #declare BlackBox = union { #local W = 10; #local H = 10; #local D = 10; #local R = 0.5; // main box RoundBox(W/2,H/2,D/2,R) texture { DarkPlastic_Text } } union { object { BlackBox } // rotate y*40 // rotate z*-20 } #declare CV = 1; sky_sphere { pigment { colour red CV green CV blue CV } } // // Where are we anyway? // #declare DX = 10.5; camera { location <-10.0*DX, 20.0*DX, -35*DX> look_at <0.0, 0.0, 0.0> } light_source { <100,200, -300> colour White *1.2 } tkgate-2.0-b10/povray/blackbox.png000644 001751 001751 00000002625 10475202116 017624 0ustar00hansenhansen000000 000000 ‰PNG  IHDR@ðþO*<gAMA± üasBITÛáOàXIDATxœìÓA À0À¿çò¤U°ÏöÌ, éüÞ a†0C˜!ÌÀf`30„ a†0C˜!ÌÀf`30„ aÿÿö`›^KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®öIDATìÖAJÃ@‡ñ÷JwV½€â ñ@®Ä­‹îz(]y<@(]JF“&–6˜aÆKŒ /|¿ü7ï0`†0`†0`†0`†0`†0`†0`†0`XUzþE×~oêúg¶›úìü¢kÛû‡ÇÒ£ÏošõêéÄ9UMITEU?ÞßnnïJOCf¼ÐóôÙxQ1&I""ª¯/ÏCߗޅ̸À3ä}s8Çq¼¾ºŒ1:çTd a?ô§Ëeéuȉ ±Ò´?ï·ëûõ'릙UU^”‹åjè¹Ð³ðÛ‘xÃpŒ€ÇpŒ€ÇpŒ€ÇpŒ€ÇpŒ€ÇpŒ€ÇpŒ€ÇpìÿÿÍÈJ!KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATìÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æÿÿ ™®KIDATíÓ € ÿ¯Ûè†1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Ɔ1aL`Æq§qÁ9•IEND®B`‚tkgate-2.0-b10/povray/textedit.pov000644 001751 001751 00000005643 10501705162 017713 0ustar00hansenhansen000000 000000 // // Gate Logo // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #macro starttext(xpos,ypos,size,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = size; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Gate_Text = texture { pigment { rgb <0.05, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugHead_Text = texture { pigment { rgb <0.05, 0.1, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Wire_Text = texture { pigment { rgb <0.05, 0.6, 0.05> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare BugShell_Text = texture { pigment { gradient z scale .03 color_map { [0.0, 1 color rgb <0.05, 0.2, 0.05> color rgb <0.05, 0.6, 0.05>] }} // pigment { } finish { metallic specular 0.2 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Bus_Text = texture { pigment { rgb <0.6, 0.05, 0.6> } finish { // metallic specular 0.15 // roughness 0.1 ambient 0.5 // diffuse 0.2 // reflection .2 } } #declare Pin_Text = texture { pigment { rgb <1,0,0> } finish { metallic specular 1 // roughness 0.1 // ambient 0.2 // diffuse 0.2 reflection .2 } } #declare VersionSave_Temp = version; #version 1.0; #declare Paper_Text = texture { image_map { <0, 0, 0> png "textedittext.png" } scale <1.38, 1.03, 1.3> translate <-0.7, 0.5, 0> ambient 0.2 diffuse 0.5 // phong 1.0 // phong_size 80 } #version VersionSave_Temp; #declare Paper = union { #local W = 0.7; #local H = 0.5; #local D = 0.01; box { <-W,-H,-D>, } texture { Paper_Text } } union { object { Paper } rotate x*30 rotate y*30 // rotate z*90 translate -0.5*x } //#declare CV = 0.85098039215686274509; #declare CV = 1; sky_sphere { pigment { // colour red 0.8 green 0.8 blue 0.8 // colour red 1 green 1 blue 1 colour red CV green CV blue CV } } // // Where are we anyway? // camera { location <0.2, 0.0, -3> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -3> colour White *2 } tkgate-2.0-b10/povray/textedittext.png000644 001751 001751 00000232056 10501705224 020577 0ustar00hansenhansen000000 000000 ‰PNG  IHDR) ²ægAMA± üaMtEXtSoftwareXV Version 3.10a Rev: 12/29/94 (jp-extension 5.3.3 + PNG patch 1.2d)Ü{0 IDATxœì½YsI–ïy|‰ @`!@ ¨LjÉE™Y’ÝꙪnk³kó’ ßçÌG™“ý4Öf=÷ªúÞéIfeV§R+%AHĈݗyp0ÂFpQ¦²Ê&ƒáî'<ñüýwGÿ×ÿñ–\·¹Ó‚k¢{ØQo®±NF£Ñh4F3Ï{ò½»‡‰çÑ’ëVkµëªz8¨7×X§F£Ñh4F£™ç=ùÞªÚ‰7¡ÍVs§õ»Ï¿`~ÈýèŠõ¾N¡gvhÑÙ»sëºêÔh4F£Ñh4ó¼'ß[U T}f~â£Áë=zý¢ßîX[5€[×U§F£Ñh4F£™ç=ùÞªÚn§3• Üâ£A÷çg“$ò’Ëk‘Îd8˜ ›[µá`pÂÑ£çÑñéÕÍÕh4F£Ñh43\¯ï]­Õ\Ó.™vt|Êü²¨‚b’DÉ°3^º/‰&I4 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Hansen // #include "glass.inc" #declare ShowHead = 1; #declare ShowWings = 1; #declare ShowBody = 1; #declare ShowLegs = 1; #declare ShowFrills = 1; #declare ShowGem = 1; #declare DrBodyR = 1.5; #declare DrBodyStart = -3; #declare DrBodyEnd = 3; #declare DrToe1Len = 1; #declare DrToe2Len = 0.8; #declare DrToeR = 0.35; #declare DrToeA1 = 20; #declare DrToeA2 = -40; #declare DrThumb1Len = 0.4; #declare DrThumb2Len = 0.4; #declare DrThumbR = 0.4; #declare DrThumbA1 = 5; #declare DrThumbA2 = -20; #declare DrClawStart = 0; #declare DrClawEnd = 1; #declare DrClawR = 0.2; #declare Pi = 3.1415926; // This can go in a "normal" // // slope_map { // [0 <0, 1>] // start at bottom and slope up // [0.5 <1, 1>] // halfway through reach top still climbing // [0.5 <1,-1>] // abruptly slope down // [1 <0,-1>] // finish on down slope at bottom // } #declare Gem_Texture = texture { NBglass pigment { rgbf <0.1, 1, 1, 0.9> } } #declare ClawText = texture { pigment { color Silver } normal { crackle 0.2 scale 0.2 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .2 } } #declare ChestPlate_Text = texture { pigment { rgb <.7,.7,.2> } normal { crackle 0.7 scale 0.5 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection 0.5 } } #declare DragonHide = texture { pigment { rgb <.8,.2,.2> } /* pigment { wrinkles scale 1 turbulence 1 color_map { [0.0 rgb <1,0,0>] [0.1 rgb <1,0,0>] [0.2 rgb <1,1,0>] [0.4 rgb <0,1,0>] [0.6 rgb <0,1,1>] [0.8 rgb <0,0,1>] } } */ normal { // crackle 0.7 crackle 0.1 scale 0.5 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 } } #declare NostrilInsides = texture { pigment { rgb <.2,0,0> } normal { crackle 0.7 scale 0.5 } finish { specular 0 roughness 0.1 ambient 0.0 diffuse 0.1 } } #declare DragonWingText = texture { pigment { wrinkles scale .1 color_map { [0 rgbf <.8,.2,.2,.7>] [0.35 rgbf <.8,.2,.2,.7>] [0.75 rgbf <.1,.1,.1,.7>] } } // normal { // agate 5 // scale 2 // scale 0.05 // } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 // reflection 0.6 reflection 1 } } #declare DragonFrillText = texture { #local F = 0.1; pigment { wrinkles scale .1 turbulence 0.1 color_map { [0 rgbf <.4,.4,.6,F>] [0.1 rgbf <1,1,0,F>] [0.6 rgbf <1,0,0,F>] } } // normal { // agate 5 // scale 2 // scale 0.05 // } finish { // metallic // specular .05 // roughness 0.1 ambient 1 diffuse 0.5 reflection 0.1 } } #declare XDragonWingText = texture { pigment { rgbf <.8,.2,.2,.3> } normal { bozo 2 scale 0.05 } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection 0.2 } } #declare DragonWingRibText = texture { pigment { rgb <.5,0,0> } normal { crackle 0.2 scale 0.01 } finish { ambient 0.2 diffuse 0.4 specular .1 reflection .1 } } #declare PlateText = texture { pigment { rgb <.4,0,0> } finish { metallic specular .05 roughness 0.1 ambient 0.2 diffuse 0.4 reflection .01 } } #declare ToothText = texture { pigment { rgb <1,1,0.7> } finish { specular 0.1 ambient 0.5 diffuse 0.5 } } #declare ClawPos = transform { rotate -5*y translate DrToe2Len*x rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y } #declare ThumbClawPos = transform { rotate -5*y translate DrThumb2Len*x rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y } #declare DragonFoot = union { #local SA = 25; #local SB = 85; blob { threshold 0.01 cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate 0*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate SA*z } cylinder { 0*x, DrToe1Len*x, DrToeR,1 rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrToe2Len*x, DrToeR,1 rotate DrToeA2*y translate DrToe1Len*x rotate DrToeA1*y rotate -SA*z } cylinder { 0*x, DrThumb1Len*x, DrThumbR,1 rotate DrThumbA1*y rotate -SB*z } cylinder { 0*x, DrThumb2Len*x, DrThumbR,1 rotate DrThumbA2*y translate DrThumb1Len*x rotate DrThumbA1*y rotate -SB*z } // scale <1,1,0.75> texture { DragonHide } } union { cone { , DrClawR , 0 transform ClawPos } cone { , DrClawR , 0 transform ClawPos rotate SA*z} cone { , DrClawR , 0 transform ClawPos rotate -SA*z} cone { , DrClawR , 0 transform ThumbClawPos rotate -SB*z} // scale <1,0.5,1> texture { ClawText } } rotate 0*y rotate 90*x } #macro DragonLeg(A1,A2,R1,R2,R3,FS) #local YS = 1.0; #local L1 = 4; // Thigh length #local L2 = 3; // Calf length union { blob { threshold 0.25 sphere { <0,0,0>, R1, 1 scale <1,1.3,1> translate -0.3*R1*y } cylinder { 0*y, -L1*y, R2, 1} cylinder { 0*y, -L2*y, R3, 1 rotate z*A2 translate -L1*y} scale <1,YS,0.5> rotate -A1*z texture { DragonHide } } object { DragonFoot scale FS rotate -(A2-A1)*z translate -(L2+0.5)*y rotate z*A2 translate -L1*y rotate -A1*z translate -(0.8)*x translate -(1-FS)*y texture { PlateText } } translate DrBodyR*z } #end #macro DragonBackLeg(A1,A2) DragonLeg(A1,A2,2,1.2,1.0,1.0) #end #macro DragonFrontLeg(A1,A2) DragonLeg(A1,A2,2,1,0.8,0.85) #end #declare DragonPlate = union { #local H = sqrt(0.75); #local R1 = 0.3; #local R2 = 0.15; intersection { box { <-0.5,0,-0.05>, <0.5,2,0.05> } plane {x, 0 inverse rotate -30*z translate -0.5*x } plane {x, 0 rotate 30*z translate 0.5*x } } difference { cylinder { -0.05*z, 0.05*z, R1 translate (H+R1-0.05)*y } cylinder { -0.06*z, 0.06*z, R2 translate(H+R1-0.05)*y } } texture { PlateText } } #macro DragonPlateSet() union { // // Body plates // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #declare S = 5.0; #while (X < DrBodyEnd) object { DragonPlate transform T translate BS*(DrBodyR*cos(X/6)-.2)*y } #declare i = 0; #while(i < (S + 0.01)) #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #declare X = X + 0.2; #declare i = i + 1; #end #end // // Tail plates // #declare TRStart = DrBodyR*cos(DrBodyStart/6); #declare TailRadius = TRStart; #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > .2) #declare PS = (TailRadius+2*TRStart)/(3*TRStart); object { DragonPlate scale PS transform T translate (BS*TailRadius-0.2)*y } #declare i = 0; #while(i < (S+0.01)) #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #declare i = i + 1; #end #end // // Neck plates // #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) #declare PS = (NeckRadius+3*TRStart)/(4*TRStart); object { DragonPlate scale PS transform T translate BS*(NeckRadius-0.2)*y } #declare i = 0; #while(i < (S+0.01)) #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #declare i = i + 1; #end #end } #end #macro MainBodyBlob() blob { threshold 0.05 // // Main body // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #while (X < DrBodyEnd) cylinder { 0*x, 0.1*x, DrBodyR*cos(X/6),1 scale <1,BS,1> transform T } #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #if (X < DrBodyEnd*0.5) #declare Twings = transform { transform T} #end #declare X = X + 0.2; #end #declare Tlegs = transform { transform T} // // Tail // #declare TailRadius = DrBodyR*cos(DrBodyStart/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > 0) cylinder { 0*x, 0.1*x, TailRadius,1 scale <1,BS,1> transform T } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #end // Neck #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) cylinder { 0*x, 0.1*x, NeckRadius,1 scale <1,BS,1> transform T } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #end #declare Thead = transform { transform T} texture { DragonHide } } #end #macro BodyChestPlates() union { #local PlateS = 0.85; #local PlateDY = -(1-PlateS); // // Main body // #declare X = DrBodyStart; #local T = transform { translate DrBodyStart*x } #while (X < DrBodyEnd) cylinder { 0*x, 0.2*x, DrBodyR*cos(X/6) scale transform T translate PlateDY*y} #local T = transform { translate 0.2*x rotate BodyRdeltaY*y transform T } #if (X < DrBodyEnd*0.5) #declare Twings = transform { transform T} #end #declare X = X + 0.2; #end #declare Tlegs = transform { transform T} // // Tail // #declare TailRadius = DrBodyR*cos(DrBodyStart/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = -2; #declare RZdelta = 2; #local T = transform { translate DrBodyStart*x } #while (TailRadius > 0) cylinder { 0*x, 0.2*x, TailRadius scale transform T translate PlateDY*y } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate -0.2*x transform T } #declare TailRadius = TailRadius - 0.02; #declare Rdelta = Rdelta + TailDDY; #declare RZdelta = RZdelta + TailDDZ; #end // Neck #declare NeckRadius = DrBodyR*cos(DrBodyEnd/6); #declare Y = 0; #declare X = DrBodyStart; #declare Rdelta = NeckHorzStart; #declare RZdelta = NeckVertStart; #local T = transform { transform Tlegs } #while (NeckRadius > .5) cylinder { 0*x, 0.2*x, NeckRadius scale transform T translate PlateDY*y } #local T = transform { rotate Rdelta*y rotate RZdelta*z translate 0.2*x transform T } #declare NeckRadius = NeckRadius - 0.02; #declare Rdelta = Rdelta + NeckHorzDD; #declare RZdelta = RZdelta + NeckVertDD; #end #declare Thead = transform { transform T} texture { ChestPlate_Text } } #end // // Put the pieces of the dragon body together here. The local variables are // visible within the macros. // #macro DragonBody(N) union { #local BS = 1.5; #switch (N) #case(1) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.085; #local NeckVertStart = 0; #local NeckVertDD = 0.09; #local TailDDY = 0.08; #local TailDDZ = -0.09; #break #case(2) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.085; #local NeckVertStart = 0; #local NeckVertDD = 0.05; #local TailDDY = -0.04; #local TailDDZ = -0.09; #break #case(3) #local BodyRdeltaY = 1; #local NeckHorzStart = -1; #local NeckHorzDD = 0.00; #local NeckVertStart = 0; #local NeckVertDD = 0.0; #local TailDDY = 0.08; #local TailDDZ = -0.09; #end MainBodyBlob() DragonPlateSet() BodyChestPlates() } #end #declare XMark = union { #local Q=0.02; #local L=1; box { <-L,-Q,-Q>, } box { <-Q,-L,-Q>, } box { <-Q,-Q,-L>, } } #declare Tooth = mesh { triangle { <-1,0,0>, <0,0,-1>, <0,1,0> } triangle { <-1,0,0>, <0,0,1>, <0,1,0> } triangle { <1,0,0>, <0,0,-1>, <0,1,0> } triangle { <1,0,0>, <0,0,1>, <0,1,0> } scale <0.06,0.3,0.1> texture { ToothText } } #macro UpperTeeth(ToothLen) union { #local FrontS = 0.6; #local A = 14; #local W1 = 0.98; #local W2 = 0.92; #local W3 = 0.82; #local X = 1.3; #while (X < ToothLen) object { Tooth rotate 90*y scale <0.8,-0.8,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,-0.8,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.2; #end object { Tooth rotate 90*y scale <0.8,-1.1,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,-1.1,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.1; object { Tooth rotate 90*y scale rotate 32*y translate X*x rotate A*y translate W2*z } object { Tooth rotate 90*y scale rotate -32*y translate X*x rotate -A*y translate -W2*z } #local X = X + 0.05; object { Tooth scale translate X*x rotate A*y translate W3*z } object { Tooth rotate 90*y scale rotate 92*y translate X*x rotate -A*y translate -W3*z } translate (HeadH*0.3+0.1)*y } #end #macro LowerTeeth(ToothStart,ToothLen) union { #local FrontS = 0.6; #local A = 13; #local W1 = 0.73; #local W2 = 0.62; #local W3 = 0.52; #local X = ToothStart; #while (X < ToothLen) object { Tooth rotate 90*y scale <0.8,0.8,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,0.8,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.2; #end object { Tooth rotate 90*y scale <0.8,1.1,0.8> translate X*x rotate A*y translate W1*z } object { Tooth rotate 90*y scale <0.8,1.1,0.8> translate X*x rotate -A*y translate -W1*z } #local X = X + 0.15; object { Tooth rotate 90*y scale rotate 32*y translate X*x rotate A*y translate W2*z } object { Tooth rotate 90*y scale rotate -32*y translate X*x rotate -A*y translate -W2*z } #local X = X + 0.1; object { Tooth scale translate X*x rotate A*y translate W3*z } object { Tooth rotate 90*y scale rotate 92*y translate X*x rotate -A*y translate -W3*z } } #end #macro DragonJaw(A,JawStart,JawEnd,JawTop) object { #local X0 = JawStart/2; #local Y0 = JawTop*1.5; #local X1 = JawStart/2; #local Y1 = -JawTop*0.5; #local L = JawEnd-JawStart; #local JW = 0.7; #local JR = 0.6; #local JY = -Y1 - 0.1; #local JSY = 1; #local JSX = 0.8; #local JSZ = 0.35; #local JZR = 30; union { intersection { union { intersection { union { intersection { sphere { <0,0,0>, 1 scale translate } plane { z, 0 rotate 13*y translate 0.8*z } plane { z, 0 inverse rotate -13*y translate -0.8*z } plane { x, 0 inverse } plane { y, 0 } } // Under jaw balls sphere { <0,0,-0.3>, 0.5 } sphere { <0,0,0.3>, 0.5 } // Jaw sides sphere { <0,0,0>, 1 scale rotate -10*y translate } sphere { <0,0,0>, 1 scale rotate 10*y translate } } plane { y, 0 } } union { cylinder { -JW*z, JW*z, JR scale translate <-X1, JY, 0> } sphere { <0,0,0>, JR scale translate <-X1, JY, -JW> } sphere { <0,0,0>, JR scale translate <-X1, JY, JW> } rotate JZR*z } } // Mouth insides #local MD = 0.48; cone { , 0.3, <0,0,0>, 0.65 inverse scale <1,MD,1> } cylinder { 0.01*x, -2*x, 0.65 inverse scale <1,MD,1> } sphere { , 0.3 scale <1,MD,1> inverse } box { <-2,0,-0.65>, <0,2,0.65> inverse } } object { LowerTeeth(0,L-0.2) } translate } translate rotate -A*z } #end // // Basic arc (actually a ring) that is used as parts of the OR gate. // #macro DrGateArc(RT) difference { object { cylinder { 0.0*z, RT*z, 0.5+RT } } object { cylinder { z, -z, 0.5 } } } #end #macro XOrGateLine(RT,TT) union { intersection { box { <-2,0,-TT>, <0.7,0.5,TT> } plane { x, 0 rotate -60*z translate 0.3*x } plane { x, 0 rotate 55*z translate <0.3,0.5+2*RT,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <-0.5-RT,0.5/2+RT/2,0> } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.6-RT,0.5/2+RT/2,0> } texture { DragonFrillText } } intersection { box { <-2,0,-TT/2>, <0.7,0.5,TT/2> } plane { x, 0 rotate -60*z translate 0.3*x } plane { x, 0 rotate 55*z translate <0.3,0.5+2*RT,0> } object { cylinder { -1*z, 1*z, 0.5 } translate <-0.39-RT,0.5/2+RT/2,0> } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.51-RT,0.5/2+RT/2,0> } texture { NBglass } } } #end #macro OrGateWingSurface(RT,TT) intersection { union { box { <0,RT/2,-TT>, <0.25,0.5+RT/2,TT> } intersection { box { <0,RT/2,-TT>, <0.7,0.5+RT/2,TT> } object { cylinder { 0.0*z, RT*z, 0.5+RT/2 } translate <0.25,0,-RT/2> } object { cylinder { 0.0*z, RT*z, 0.5+RT/2 } translate <0.25,0.5+RT,-RT/2> } } } object { cylinder { -1*z, 1*z, 0.5 } inverse translate <-0.4-RT,0.5/2+RT/2,0> } } #end #macro DrOrBack(RT) intersection { #local W = 0.5 + RT; object { DrGateArc(RT) } plane {x, 0 inverse } plane {y, -W/2 inverse } plane {y, W/2 } translate <-(0.5-RT*1.5),W/2,-RT/2> } #end #macro OrGateWingRibs(RT,doBack,doFront) union { box { <0,0.5,-RT/2>, <0.25,0.5+RT,RT/2> } box { <0,0.0,-RT/2>, <0.25,RT,RT/2> } // // The back of the OR gate // #if (doBack) object { DrOrBack(RT) } #end // // Top-half of OR curve. // intersection { intersection { object { DrGateArc(RT) } plane {x, 0 inverse } translate <0.25,0,-RT/2> } plane {y, 0.5/2 + RT/2 inverse } #if (!doFront) plane {x, 0.4 } #end } // // Bottom-half of OR curve. // intersection { intersection { object { DrGateArc(RT) } plane {x, 0 inverse } translate <0.25,0.5+RT,-RT/2> } plane {y, 0.5/2 + RT/2 } #if (!doFront) plane {x, 0.4 } #end } texture { DragonWingRibText } } #end #macro OrGateFrill() union { #local RT = 0.03; #local TT = 0.001; object { OrGateWingRibs(RT,0,1) } object { OrGateWingSurface(RT,TT) texture { DragonFrillText } } translate <-0.75,-0.25,0> } #end #macro XOrGateFrill() union { #local RT = 0.03; #local TT = 0.001; XOrGateLine(RT,TT) object { OrGateWingRibs(RT,0,1) } object { OrGateWingSurface(RT,TT) texture { DragonFrillText } } translate <-0.75,-0.25,0> } #end // // One section of the wing // #macro OrGateWingElement(RT,TT) union { object { OrGateWingRibs(RT,1,0) } object { OrGateWingSurface(RT,TT) texture { DragonWingText } } } #end // // A complete wing // #declare DragonWing = union { #local RT = 0.03; #local TT = 0.001; object { OrGateWingElement(RT,TT) } object { OrGateWingElement(RT,TT) translate (0.5)*y } object { OrGateWingElement(RT,TT) translate (1)*y } rotate 90*x #if (1) rotate 180*z #else translate -0.5*x #end scale 8 } #declare Eye = object { #local C1 = 0.16; #local C2 = 0.195; sphere { <0,0,0>, 0.2 } texture { pigment { gradient x color_map { [0 rgb <1,1,0.6>] // Milky white [C1 rgb <1,1,0.6>] // Milky white [C1 rgb <0.05,0.3,0.05>] [C2 rgb <0.05,0.3,0.05>] [C2 rgb <0,0,0>] [1 rgb <0,0,0>] // Black } } finish { specular 0.1 reflection 0.3 ambient 0.5 } } } #macro XYCord(X1,Y1,X2,Y2,S) #local D = sqrt((X1-X2)*(X1-X2) + (Y1-Y2)*(Y1-Y2)); #local R = 90-atan2((X2-X1),(Y2-Y1))*180/Pi; object { cylinder { 0*x, D*x, S } rotate R*z translate } #end #macro DragonHead() union { #local HeadLen = 3; #local Hbase = 1; #local HeadW = 2; #local HeadH = 2; #local MouthRoof = (HeadH*0.3+0.1); #local EA = 35; #local NX = HeadLen-0.05; #local NY = 1.2; #local NZ = 0.15; #if (1) intersection { union { intersection { box { <0,0,-HeadW/2>, } // Side angles plane { z, 0 rotate 12*y rotate -5*x translate Hbase*z } plane { z, 0 inverse rotate 5*x rotate -12*y translate -Hbase*z } // Nose and back of head angle plane { y, 0 rotate -15*z translate HeadH*y } plane { y, 0 rotate 15*z translate (HeadH-0.4)*y } object { cylinder { -2*x, 4*x, 1 } rotate -15*z translate 0.9*y } } // // Eye ovals // sphere { <0,0, 0>, 1 scale <1,0.7,0.35> rotate -20*z rotate -EA*y translate <1.1, 1.2, -0.3> } sphere { <0,0, 0>, 1 scale <1,0.7,0.35> rotate -20*z rotate EA*y translate <1.1, 1.2, 0.3> } // // Middle nose ridges // sphere { <0,0,-0.9>, 1 scale <1.6,0.55,0.2> rotate -5*y translate <1.15,1.0,0> } sphere { <0,0, 0.9>, 1 scale <1.6,0.55,0.2> rotate 5*y translate <1.15,1.0,0> } // // Edge nose ridges // sphere { <0,0,0>, 1 scale <1.8,0.6,0.2> rotate -12*y translate <1.35,0.9,-0.6> } sphere { <0,0,0>, 1 scale <1.8,0.6,0.2> rotate 12*y translate <1.35,0.9,0.6> } // // Nose blob // blob { threshold 0.05 sphere { , 0.2, 1 } sphere { , 0.2, 1 } cylinder { 0*y, NY*y, 0.18,1 translate } cylinder { 0*y, NY*y, 0.18,1 translate } } } // // Eye socket cutouts // sphere { <0,0,0>, 1 inverse scale <0.5,0.2,0.2> rotate -20*z rotate -EA*y translate <1.1, 1.6, -0.5> } sphere { <0,0,0>, 1 inverse scale <0.5,0.2,0.2> rotate -20*z rotate EA*y translate <1.1, 1.6, 0.5> } // // Nostril cutouts // union { cylinder { -0.08*x, 1*x, 0.05 scale <1,1,1> } box { <-0.15,-0.05,-0.05>, <1,0.0,0.05> } inverse scale 1.5 rotate <-1,0,5> translate texture { NostrilInsides } } union { cylinder { -0.08*x, 1*x, 0.05 scale <1,1,1> } box { <-0.15,-0.05,-0.05>, <1,0.0,0.05> } inverse scale 1.5 rotate <1,0,5> translate texture { NostrilInsides } } // Mouth cut-out union { plane { y, MouthRoof inverse } plane { x, HeadLen/3 } } // // Mouth cavity cutout // cone { <-5,0,0>, 1.4, <0,0,0>, 0.2 inverse scale <1,0.7,1> translate(HeadLen-0.3)*x translate MouthRoof*y } sphere { <0,0,0>, 0.2 inverse translate(HeadLen-0.3)*x translate MouthRoof*y } // // Back of head plane // plane { x, 0 inverse } } // // Upper teeth // UpperTeeth(HeadLen-0.2) #if (ShowFrills) object { OrGateFrill() scale 2 rotate -60*y translate <0.3,1.2,-0.7> } object { OrGateFrill() scale 2 rotate 60*y translate <0.3,1.2,0.7> } object { XOrGateFrill() scale 2 rotate -60*y rotate 60*x translate <0.3,1.6,-0.5> } object { XOrGateFrill() scale 2 rotate 60*y rotate -60*x translate <0.3,1.6,0.5> } #end object { Eye translate <0.7, 1.6, -0.55> } object { Eye translate <0.7, 1.6, 0.55> } #end sphere { <0,0.5,0>, 1 } object { DragonJaw(20,HeadLen/3,HeadLen-0.3,MouthRoof) } texture { DragonHide } } #end #macro GemCut(TT) intersection { #local CutD = TT*0.7; #local A = 30; plane { y,0 rotate -A*x translate <0,0,-(TT-CutD)> } plane { y,0 rotate -2*A*x translate <0,-CutD,-TT> } plane { y,0 rotate A*x translate <0,0,(TT-CutD)> } plane { y,0 rotate 2*A*x translate <0,-CutD,TT> } } #end #macro GemHalfCut(TT) intersection { #local CutD = TT*0.7; #local A = 30; plane { y,0 rotate -A*x translate <0,0,CutD> } plane { y,0 rotate -2*A*x translate <0,-CutD,0> } } #end #declare GateGem = intersection { #local TT = 0.1; #local X0 = -0.45; #local R = 0.25; #local A = 30; #local CutD = 0.08; merge { box { , <0,R,TT> } cylinder { -TT*z, TT*z, R } } object { GemCut(TT) translate R*y } object { GemCut(TT) scale <1,-1,1> translate -R*y } object { GemCut(TT) rotate 90*z translate X0*x } object { GemHalfCut(TT) rotate 90*y translate } object { GemHalfCut(TT) scale <1,-1,1> rotate 90*y translate } #local Th = 60; #while (Th > -90) #local X = R*cos(Th*Pi/180); #local Y = R*sin(Th*Pi/180); object { GemCut(TT) rotate (Th-90)*z translate } #local Th = Th - 30; #end // plane { y,0 rotate A*z translate } // plane { y,0 rotate 2*A*z translate } // plane { y,0 inverse rotate -A*z translate } // plane { y,0 inverse rotate -2*A*z translate } scale 3 interior { ior 1.5 } texture { Gem_Texture } } #macro Dragon(N) union { #switch(N) #case(1) #local WingAngle = 40; #break #case(2) #local WingAngle = 55; #break #case(3) #local WingAngle = 40; #end #if (ShowBody) object { DragonBody(N) } #end #if (ShowLegs) #switch(N) // Left dragon #case(1) object { DragonFrontLeg(45,100) transform Tlegs } object { DragonFrontLeg(65,130) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(45,100) translate DrBodyStart*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate DrBodyStart*x } #break #case(2) object { DragonFrontLeg(45,108) transform Tlegs } object { DragonFrontLeg(65,130) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(45,108) translate DrBodyStart*x } object { DragonBackLeg(45,100) scale <1,1,-1> translate DrBodyStart*x } #break #case(3) object { DragonFrontLeg(70,160) transform Tlegs } object { DragonFrontLeg(70,160) scale <1,1,-1> transform Tlegs } object { DragonBackLeg(70,160) translate DrBodyStart*x } object { DragonBackLeg(70,160) scale <1,1,-1> translate DrBodyStart*x } #end #end #if (ShowWings) object { DragonWing scale <1,1,-1> transform Twings translate -1.5*z rotate WingAngle*x rotate -10*y} object { DragonWing scale <1,1,-1> transform Twings translate -1.5*z rotate WingAngle*x rotate -10*y scale <1,1,-1> } #end #if (ShowHead) object { DragonHead() scale 0.8 translate -0.5*y #switch(N) #case(1) rotate -70*z #break #case(2) rotate -50*z #break #case(3) rotate -0*z #end transform Thead } #end #if (ShowGem) #if (N != 3) object { GateGem translate <2.2,-4.2,-2.7> } #end #end translate 0.1*y } #end tkgate-2.0-b10/povray/memory_view.pov000644 001751 001751 00000010603 11141705062 020413 0ustar00hansenhansen000000 000000 // // Memory chip with insides visible // by Jeffery P. Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #include "woods.inc" #include "chip.inc" #macro starttext(xpos,ypos,tsize,space) #declare CP_X = xpos; #declare CP_Y = ypos; #declare CP_LEFT = xpos; #declare CP_SPACE = space; #declare CP_SIZE = tsize; #end #macro newline() #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - (BoardHeight+BoardGap); #end #macro kern(C) #declare CP_X = CP_X + CP_SPACE*C; #end #macro putchar(C) object { C scale translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.6 } } #declare ChipHole = object { box { <-.4,-.5 , -0.05>, <0.4, 0.5, -0.2> } texture {Chip_Text } } #declare ChipContent = union { object { box { <-.4,-.5 , -0.05>, <0.4, 0.5, -.06> } texture {Paper_Text } } // // xxxxxxxxxxxxxxxxxx // You must be bored. // Y?u ??st ?e bored. // union { starttext(-.30, .3, 0.02, 0.1) putchar(char_5) putchar(char_9) kern(0.5) putchar(char_6) putchar(char_F) kern(0.5) putchar(char_7) putchar(char_5) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_2) putchar(char_0) kern(0.5) putchar(char_6) putchar(char_D) kern(0.5) putchar(char_7) putchar(char_5) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_7) putchar(char_3) kern(0.5) putchar(char_7) putchar(char_4) kern(0.5) putchar(char_2) putchar(char_0) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_2) kern(0.5) putchar(char_6) putchar(char_5) kern(0.5) putchar(char_2) putchar(char_0) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_2) kern(0.5) putchar(char_6) putchar(char_F) kern(0.5) putchar(char_7) putchar(char_2) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_5) kern(0.5) putchar(char_6) putchar(char_4) kern(0.5) putchar(char_2) putchar(char_E) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; translate -0.06*z } } union { difference { object { Chip} object { ChipHole }} object { ChipContent } scale 2 } object { MagGlass rotate -45*x scale 0.6 translate <.45,.6,-0.9> } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -6> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *2 } tkgate-2.0-b10/povray/memory_view.png000644 001751 001751 00000032630 11141705505 020401 0ustar00hansenhansen000000 000000 ‰PNG  IHDRð´%þ6¿gAMA± üasBITÛáOàJIDATxœìÒQ À@µ´Ê‚0îìc{fTœßð’¡I14)†&ÅФšC“bhR MŠ¡I14)†&ÅФšC“rÿÿg·¹ÆùIDATì–ͪ„0 Fq!n|TŸ^0Í]„)ÄŸ™a.éw%ib)娅Р„BƒP@h  B¡A( 4„¡€Ð „BƒPôwoà6ˆ¨NEDƒ®ëD$çœs&"m+UÓ|4sÙðîd)Ñ0 G  Q¡Çqœç™™™yÛ6®ÐTöUÿˆ¶yʼfÜ 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Ô—ÇÝ@¬(×m}Ü8Ã;m©æu¤3ÌÈ3vÕ6 Eýõ`cåA¯TÐ[èééùyÁëÆ{KRRrbâ”ÄĤ©ÉÓÃÂl^¯§Ç}7GüðÙg߬¿Ôëó[ €€¶ðˆUyëçdgÿÏô‘BHÚb±MO™<ÔYæ'ÄŒÁöȇÞÑÞO #–À—!¨_Û¶íÊÈœ§u¨Åbu8œ”‚ð¬qÇo‹Šd…ò„Ìœ›¹dã&GÜø¡Q ¤=Œsí/°+}%ÿáþg$J·1õyü³6µtffæÜ•+7gÅŠ‰)£ŠdùH#¤MûU¡ƒ @Ôœ~à¾É÷ ¸;›``° -<ûC/)0ukísÏÁ˜Aˆºßð5Ǻ Gõ„Qðé»*¦æ(¯‚!= ƒ™üﮎ1„¡¡`BÓÁ<´Ê1áþ+ / S8Èœ•ÊdÖá1Çéÿÿ•O¡!IDATìMOÃ0 †íllíçqGHp!®H]SsÈGÓÆIº6ÀÁ—Ù±3©ê³·n¶¥¢€F˜Sèþz]ÂÓF.+bíýe4¥Ín…§“4*¢E@Ó´=ù=à9³ÇìËݬì$¡& èaÐy ½_à|¶"¸Ë±6~¼å3ÙT=uk& hT¼B‡¾qh©Hç³{ù ¦IšÛCZÐÑ,Ðæµïû”H/¼ÁsŸ³°2ÿ÷¶ûÓ†^«J]‡ÿJ¹P-XWcOqèt{}´, QkXi‘fסS~E@7 sF§Í§3¨ó“’Ô ™& h ÿX‘,Ó³ýìnò÷+XžšÍn}XjTš( µî‰k0 @ãFân¼‚_ë 3©ø‹Ä®x 5öŒQ@CpÕM5¦Æ¬rÀ6¼î€o1œÙ\ª[»%”ô´eÌ0ÿÎxœU[¶W—±aî¦i<š3Q@›Í!Á4縻vë4r?|‹J_R¦YˆöVíd €~•Ã6 ‚]š=¸¿´ÔźJ**u8ŸÎæD¤µFŒ» þâÓ‚‰ºë¾_žŸìzôx.ý¾ã„¨Lòãýu{°ÊÅ‚Óéáry4¾yÁñxüú|3µÐ¼‰ìé'fÌzƒI†Û0utõÄ8dGÂ}+¥\ø²5i@ßj· äÝØMˆßœn£ýÿÿá=Ž^ÒIDATìÁ „0 ¡ÐÿÿÞ…¼üšhät•;9Ôˆ mßë|$)óßÞ= ¡V#û)¥|~3ôßãΚR²]opŠh‡þnê†pðÈ ¡@hBC(BÐ „†Plÿÿ%ðn translate } #declare CP_X = CP_X + CP_SPACE ; #end #declare Rim_Texture = texture { pigment { rgb <0.658824, 0.658824, 0.658824> } finish { ambient 0.3 diffuse 0.7 reflection 0.15 brilliance 6 specular 0.8 roughness 0.1 } } #declare LensGlass = texture { pigment { rgbf<1.0, 1.0, 1.0, 0.95> } finish { specular 1 roughness 0.001 ambient 0 diffuse 0 reflection 0.1 ior 1.5 } } #declare MagGlass = union { // Rim difference { intersection { object { Cylinder_Z scale <1.0, 1.0, 1.0> } plane { z, -0.1 inverse } plane { z, 0.1 } } intersection { object { Cylinder_Z scale <0.9, 0.9, 1.0> } } texture { Rim_Texture } } // Handle intersection { object { Cylinder_X scale <0.16, 0.16, 0.16> } plane { x, 0 inverse } plane { x, 2 } texture { T_Wood4 } translate 1*x } // sphere { <1,1,2> 1.5 texture { Sandalwood } } // Lens intersection { // object { Paraboloid_Z scale <1,1,0.25> translate -0.17*z } // object { Paraboloid_Z scale <1,1,-0.25> translate 0.17*z } // object { Paraboloid_Z scale <1,1,0.1> translate -0.105*z } // object { Paraboloid_Z scale <1,1,-0.1> translate 0.105*z } object { Paraboloid_Z scale <1,1,0.2> translate -0.15*z } object { Paraboloid_Z scale <1,1,-0.2> translate 0.15*z } texture { LensGlass } } rotate <20, 40, -45> } #declare Paper_Text = texture { pigment { rgb <1,0.95,0.95> } finish { specular 0.1 roughness 0.1 ambient 0.2 diffuse 0.6 } } #declare ChipHole = object { box { <-.4,-.5 , -0.05>, <0.4, 0.5, -0.2> } texture {Chip_Text } } #declare ChipContent = union { object { box { <-.4,-.5 , -0.05>, <0.4, 0.5, -.06> } texture {Paper_Text } } // // xxxxxxxxxxxxxxxxxx // You must be bored. // union { starttext(-.30, .3, 0.02, 0.1) putchar(char_5) putchar(char_9) kern(0.5) putchar(char_6) putchar(char_F) kern(0.5) putchar(char_7) putchar(char_5) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_2) putchar(char_0) kern(0.5) putchar(char_6) putchar(char_D) kern(0.5) putchar(char_7) putchar(char_5) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_7) putchar(char_3) kern(0.5) putchar(char_7) putchar(char_4) kern(0.5) putchar(char_2) putchar(char_0) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_2) kern(0.5) putchar(char_6) putchar(char_5) kern(0.5) putchar(char_2) putchar(char_0) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_2) kern(0.5) putchar(char_6) putchar(char_F) kern(0.5) putchar(char_7) putchar(char_2) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; putchar(char_6) putchar(char_5) kern(0.5) putchar(char_6) putchar(char_4) kern(0.5) putchar(char_2) putchar(char_E) #declare CP_X = CP_LEFT; #declare CP_Y = CP_Y - 0.15; translate -0.06*z } } union { difference { object { Chip} object { ChipHole }} object { ChipContent } scale 2 } object { MagGlass rotate -45*x scale 0.6 translate <.45,.6,-0.9> } sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } // // Where are we anyway? // camera { location <0.2, 0.0, -6> look_at <0.2, 0.0, 0.0> } light_source { <-30.0, 30.0, -30> colour White *2 } tkgate-2.0-b10/povray/chip.png000644 001751 001751 00000011744 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Hansen // //global_settings { assumed_gamma 2.2 } #include "shapes.inc" #include "chars.inc" #include "colors.inc" #include "textures.inc" #declare WireText = texture { pigment { rgb <0, 0.7, 0 > } finish { specular 0.1 reflection 0.3 ambient 0.8 } } #declare BlobText = texture { pigment { rgb <0, 0, 0.7 > } finish { specular 0.1 reflection 0.3 ambient 0.8 } } #declare WireNet = union { #local R = 0.075; #local R2 = 0.2; cylinder { -5*y, 5*y, R texture { WireText} } cylinder { -5*x, 0*x, R texture { WireText} translate -0.5*y } cylinder { 1*x, 0*x, R texture { WireText} translate 0.5*y } cylinder { 0.5*y, 5*y, R texture { WireText} translate 1*x } sphere { <1,0.5,0>, R texture { WireText} } sphere { <0,0.5,0>, R2 texture { BlobText} } sphere { <0,-0.5,0>, R2 texture { BlobText} } } object { WireNet rotate 40*x // rotate 30*y } /* sky_sphere { pigment { colour red 0.8 green 0.8 blue 0.8 } } */ // // Where are we anyway? // camera { location <0.0, 0.0, -4> look_at <0.0, 0.0, 0.0> } light_source { <-30.0, 30.0, -15> colour White *1 } tkgate-2.0-b10/locale/en000777 001751 001751 00000000000 11150371405 015571 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/ja000777 001751 001751 00000000000 11150362346 015565 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de000777 001751 001751 00000000000 11150636025 015561 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/ca000777 001751 001751 00000000000 11145151105 015547 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/cy000777 001751 001751 00000000000 11145151105 015577 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/es000777 001751 001751 00000000000 11145151105 015573 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/fr000777 001751 001751 00000000000 11145151105 015573 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/cs000777 001751 001751 00000000000 11145151105 015571 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it000777 001751 001751 00000000000 11145151105 015600 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18000777 001751 001751 00000000000 11145151105 017645 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/tutorials.18000777 001751 001751 00000000000 11145151105 020055 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/messages000644 001751 001751 00000073471 11134010406 017415 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Nov 29 14:37:44 2004 \language Italian ############################################################################## # # basic strings # b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel b.open Open... b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete b.deleteb Delete... b.apply Apply b.anchor Anchor b.tech Technology ############################################################################## # Menu strings # file File edit Edit tool Tool simulate Simulate module Module gate Gate make Make circ Circuit new New open Open... openlib Open Library... save Save saveas Save... print Print... options Options... quit Quit undo Undo redo Redo cut Cut copy Copy paste Paste selall Select All find Find... algnv Align Ver. algnh Align Horz. zoomin Zoom In zoomout Zoom Out move Move/Connect delg Delete Gate cutw Cut Wire inv Invert bitw Bit Width debug Debug rot0 Rot 0 rot90 Rot 90 rot180 Rot 180 rot270 Rot 270 simbegin Begin Simulation simend End Simulation simadprobe Add/Delete Probe simrun Run simpause Pause simstep Step Epoch(s) simcycle Step Cycle simbreak Breakpoint... simscript Exec. Script... simload Load Memory... simdump Dump Memory... modopen Open modclose Close modseti Set Interface modediti Edit Interfaces... modnew New... moddel Delete... modcopy Copy... modrename Rename... modclaim Claim... circprop Circuit Properties... cpath Critical Path... gataddin Add Input gataddout Add Output gataddinout Add BiDir gatiochg Change Type gatanchor Anchor Selected gatunanchor Unanchor Selected gatprop Properties... gatrep Replicate gatdel Delete gatsettech Set Technology gmswitch I/O gmgate Gate gmredgate Reduction gmmsi MSI gmalu ALU gmmem Memory gmmod Module gmcomment Comment gmframe Frame gmxswitch Switch gmdip DIP Switch gmground Ground gmvdd Vdd gmmerge Wire Merge gmclock Clock gm.led LED gm.ledbar LED Bar gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Direct) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Buffer gminv Inverter gmtribuf Tri-Buffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Adder gmmult Multiplier gmdiv Divider gmlshift Left Shift gmrshift Right Shift gmarshift Arith. Right Shift gmroll Roll gmreg Register gmff Flip-Flop gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decoder gm14dec 1-4 Decoder gm18dec 1-8 Decoder gmmodinst Module Instance gmmodin Module Input gmmodout Module Output gmmodinout Module InOut addwireseg Add Wire Segment help Help hlpabout About... hlplicense License... hlpdoc Documentation... hlptut Tutorials hlpexample Examples exampcomb Combinational Logic examp3bit 3-Bit Counter examp8bit 8-Bit Counter examptrff Transistor-Level FF exampcpu Menagerie CPU tutwelcome TkGate Intro tutcreate Creating a Circuit tutedit1 Editing a Circuit (1) tutedit2 Editing a Circuit (2) tutmods Using Modules tutsim Simulating a Circuit # Scope Menu menu.sc.prtrace Print Trace... menu.sc.close Close menu.sc.trace Trace menu.sc.zoomin Zoom In menu.sc.zoomout Zoom Out scope.emptymsg Doppio click su un collegamento per agganciare o togliere una sonda. comment.empty [Doppio click per aggiungere testo.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: ############################################################################# # Net Dialog Box # db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # Gate dialog box # db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.gtype Gate Type db.gate.gname Gate Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.memfilenam Memory File db.gate.modname Function db.gate.islink Text is Hyperlink db.gate.link Link to File db.gate.findw Search for wires only db.gate.findg Search for gates only db.gate.findwg Search for wires and gates db.gate.general General db.gate.details Details db.gate.ports Port db.gate.delay Delay db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.extbar Use extender bars db.led.type LED Type db.led.bit Bit db.led.bar Bar Graph db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Direct) ## - Italian localization - ## - April 2004 P. Ceppi; SUPSI-DTI ## - Will translate: ## - - instructive/helpful text only cpath.cloops -begin- Il circuito contiene loop combinatori! Per procedere ad analisi di ritardi in questo circuito devi interrompere i loop oppure indicare una porta per ogni loop come punto di interruzione: lo puoi fare nel form "Properties" della porta, usa il check box "Critical Path Partition". I collegamenti per i quali è stato trovato un loop sono elencati sotto. -end- ############################################################################## # Print dialog box # print.outto Output to print.printer Printer print.file File print.prcmd Print Command print.filename File Name print.epssave Save as Encapsulated Postscript. print.doctit Document Title print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.range Range Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.end End ############################################################################## # # Options dialog # opt.site Site Name opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.outmove Outline Move modules opt.balloon Enable Help Balloons opt.debug Enable Debugging opt.novice Novice Mode opt.ckpoint Do Checkpointing opt.freq Interval opt.beak Enable Special Modes opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Giuan opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.logfile Simulator Log File opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.rememberprobes Remember Probe Placement opt.vpopupdelay Value Pop-Up Delay opt.initscript Initialization script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Delay Files opt.general General opt.print Print opt.simulate Simulate opt.analysis Analysis opt.color Color opt.undolen Max Undo opt.cpopts Critical Path Options: opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.vercheck -begin- Controlla di tanto in tanto se ci sono nuove versioni di TkGate in rete. Non abilitare se non hai accesso continuo a Internet. -end- ############################################################################## # # Block list dialog boxes blklst.newmod New Module blklst.delmod Delete Module blklst.frommod Copy Module From blklst.tomod To blklst.oldname Old Name blklst.newname New Name blklst.claim Claim Module ############################################################################## # # Circuit Dialog box # circ.topmod Top-Level Module circ.discchg Discard Changes circ.iniscript Initialization Scripts circ.noscript No script files selected. circ.really1 Do you really want to remove circ.really2 from the list of initialization scripts circ.extbar Use Extender Bars ############################################################################## # Simulator # sim.breakpt Breakpoint ############################################################################## # # Command box # cmd.file File Name cmd.topname Top Module Name ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.verilog Errrori nel file: err.nopin Non posso modificare il pin selezionato. err.badhex Valore hex '%s' errato: viene ignorato. err.gatanchor Le porte sono ancorate: non possono essere spostate. err.libmode Operazione non ammessa su un modulo di libreria (convertilo in un modulo normale per editarlo). err.badfind Non trovo il target '%s'. err.badopendel Non posso cancellare un modulo aperto. err.nosrcmod Non ho trovato il modulo '%s'. err.noerr Non so localizzare l'errore. err.misserr Errore informazione incompleta (il simulatore è caduto?) err.pounimpl Errore non implementato in ParseOption err.badinadd Non posso aggiungere ulteriori pin di input alla porta selezionata. err.badoutadd Non posso aggiungere ulteriori pin di output alla porta selezionata. err.badinoutadd Non posso aggiungere ulteriori pin inout alla porta selezionata. err.badpinchg Non posso modificare il tipo di pin della porta selezionata. err.badnetname Carattere non ammesso cancellato dall'identificatore. err.netbcrename Identificatore rinominato con '%s' a causa di un carattere non ammesso. err.netconfnet Identificatore rinominato con '%s' a causa di un conflitto. err.netconfgat Identificatore rinominato per evitare conflitti con nomi di porte primitive. err.netconfkw Identificatore rinominato per evitare conflitti con parole riservate. err.badconsame Collegamento rifiutato perchè i fili appartengono allo stesso collegamento. err.badconptsp Collegamento rifiutato perchè ambedue i fili sono porte di moduli o alimentazioni. err.badconbitw Collegamento rifiutato perchè il numero di bit non coincide. err.badrange L'istante di inizio deve precedere quello di fine della stampa (Start < End)! err.badlprcmd Non posso eseguire il comando di stampa '%s'. err.badpsopen Non posso aprire il '%s' per output in postscript. err.badid Identificatore non ammesso '%s'. err.bkpt.badexp Errore di sintassi nell'espressione di breakpoint. Devi scegliere fra: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Errore nel nome del collegamento '%s'. I nomi devono iniziare con una lettera e contengono solo lettere, numeri e '.'. err.bkpt.badval Errore di sintassi nel valore '%s'. Deve essere un decimale o una costante in stile verilog. err.bkpt.toomany Troppi breakpoints. Al massimo %d. err.sim.badtmp Non ho potuto salvare il file temporaneo '%s' per il simulatore (disco pieno?) err.sim.syntx Errore di sintassi nel comando '%s'. err.sim.noincl Non trovo il file '%s' da includere. err.sim.clockbadedge Specifica di fianco '%c' non ammessa nel comando di avanzamento della simulazione. err.sim.nobkpt Il breakpoint '%s' non esiste. err.sim.nonet Non trovo il collegamento '%s'. err.sim.nogate Non trovo il gate '%s'. err.sim.badbin Carattere non ammesso nella costante binaria '%s'. err.sim.notswitch Il gate '%s' non è uno switch, un dip o un registro. Il comando "Set" si applica solo a questi componenti. err.sim.badcmd Comando sconosciuto '%s' nello script di simulazione. err.noteditpchg Le proprietà possono venir cambiata solo in modalità di edizione. err.badeditop Operazione non ammessa in modalità di edizione di interfaccia. err.badopen Impossibile aprire il file '%s'. err.badlibopen Impossibile aprire il file di libreria '%s'. err.nomark Posiziona un punto di riferimento con il tasto sinstro del mouse prima di scegliere un gate. err.badgate Tipo di gate sconosciuto. err.badmake Non posso a creare il gate. err.badportadd Impossibile aggiungere porte a un gate di questo tipo. err.badportdel La porta selezionata non può essere concellata. err.badportedit La porta selezionata non può essere modificata. err.noport Non è stata selezionato alcun port. err.manypages -begin- C'è una quantità tremenda di pagine in questo documento! Sei sicuro di volerlo stampare? -end- err.nojump -begin- L'opzione 'jump-to-module' non è disponibile nella modalità di simulazione o di analisi del percorso critico. Spostati manualmente nel blocco desiderato selezionando moduli e aprendoli con il carattere '>' da tastiera. Puoi abbandonare un modulo inserendo il carattere '<' da tastiera. -end- err.nomod Il modulo '%s' non è definito. err.modlock Il blocco logico è bloccato ("locked")! err.closeroot Non posso chiudere il modulo "top". Usa "quit". err.sim.isrun Il simulatore è già attivo (Usa 'Ctrl-s e' per terminare). err.sim.isnotrun Il simulatore non è attivo (Usa 'Ctrl-s b' per avviarlo). err.editonly Comando non ammesso in modalità di simulazione. err.simonly Comando ammesso solo in modalità di simulazione. err.nodel Non è selezionato alcun elemento cancellabile. err.modnotdef Il module '%s' non è definito. err.moddef Il blocco '%s' esiste già. err.noprop Il gate selezionato non ha proprietà editabili. err.openscript Non posso aprire lo script di simulazione '%s' err.oldversion Caricato un file con l'identificatore di versione obsoleta %s (la versione attuale è %s). err.futureversion Caricato un file salvato dalla versione futura %s di TkGate (questa versione è %s). err.badversion Numero di versione sconosciuto. Usa a tuo rischio. err.nodrive Il collegamento %s non ha driver nel modulo %s. err.noconn Il filo %s{%d} non ha collegamenti - cancellato. err.oldportact Clicca con il tasto destro sul port o sul bordo del modulo per aggiungere/modificare un port. err.backupfail Non riesco a creare il file di backup '%s'. err.corruptnewsave -begin- TkGate è riuscito a salvare il file '%s', ma sembra rovinato. Se hai abilitato la modalità "checkpointing" prova a caricare uno dei files di "checkpoint". Usa 'tkgate -V' per verificare l'integrità di un file di salvataggio. -end- err.corruptsave -begin- TkGate ha riscontrato un problema nel salvataggio del file '%s'. Il file esistente è stato lasciato intatto e il file danneggiato è stato salvato in '%s'. Se hai abilitato la modalità "checkpointing" puoi provare a caricare uno dei files di "checkpoint". Puoi anche usare 'tkgate -V' per verificare l'integrità di un file di salvataggio. -end- err.badsave -begin- C'è un problema ad aprire o a salvare il file '%s'. Controlla le protezioni del file/directory e/o lo spazio disco. -end- err.nosafesave -begin- C'è un problema a salvare '%s'. Se vuoi, puoi ritentare senza validazione. Se rispondi "no", il file originale rimane inalterato. Se rispondi "yes" il file originale verrà sovrascritto, ma potrebbe venir distrutto se si verifica un problema. Vuoi tentare un salvataggio senza validazione? -end- err.noback -begin- Il file è stato creato con TkGate %s. Se lo salvi, è probabile che non possa venir riletto da versioni precedenti a questa (%s). -end- ############################################################################## # Informational messages # msg.selwire Nome del collegamento: '%s' msg.selgate Hai selezionato %s con il nome '%s'. msg.selblock Hai selezionato il blocco %s denominato '%s'. msg.modoverwt Il modulo '%s' esiste già. Sovrascrivere? msg.foundgate Trovato una porta con il nome '%s'. msg.foundwire Trovato un collegamento con il nome '%s'. msg.searchagn Stringa '%s' non trovata. Inserisci 'find' per riavviare la ricerca. msg.sim.chgtoroot La modalità di simulazione richiede il modulo "root" in cima allo stack di edizione. msg.sim.nogatemod La modalità di simulazione richiede moduli istanziati ("Concrete module stack). msg.setinterface Impostato interfaccia per il modulo '%s' msg.needsel Seleziona un'istanza di modulo. msg.wroteckpt "Checkpointed" in %s... msg.save Circuito salvato in '%s' msg.reallynew Il circuito è stato modificato. Vuoi veramente scartare le tue modifiche e creare un circuito nuovo? msg.reallyquit Il circuito è stato modificato. Vuoi veramente uscire senza salvare? msg.notlib Il modulo '%s' non è un modulo di libreria. ############################################################################## # Messaggi par ul Giuan (Dupraa quant ul Giuan Bambela 'l dupera ul TkGate) # miles.msg1 Dumà un cücümar al metaresa ul %s%s lì, Giuan. miles.msg2 L'è propi un post stupit par met ul %s%s, Giuan. miles.msg3 L'è un pustasc par ul %s%s, Giuan; pesc d'inscì ta pudevat mia catà fö! miles.msg4 Ma no Giuan, lè mia ul post par ul %s%s linscì. miles.msg5 Propi dumà ti ta po met ul %s%s lì, Giuan. miles.msg6 S'al metat lì da fa 'stu %s%s?! Ta see propi dür da cumprendoni, Giuan. miles.msg7 Pianta lì Giuan, l'è propi un lavur da ciola. miles.msg8a L'è propi mia ul to mestee Giuan, lasa pert. miles.msg8b Ta se propi mia bun da met giò 'stu schema. ############################################################################## # Balloon Help # ho.new -begin- Abbandona il circuito attuale e inizia a disegnarne uno nuovo. -end- ho.open Carica (open) un circuito da un file. ho.save Salva il circuito nel file corrente. ho.print Stampa il circuito corrente. ho.move -begin- Move/Connect - By clicking and dragging you can: Scegliere la posizione per una nuova porta Spostare porte e collgamenti Collegare fili By double-clicking you can: Modificare le proprietà di porte logiche, collegamenti e ports Modificare commenti -end- ho.delgat -begin- Delete Gate - Elimina porte logiche. -end- ho.cutw -begin- Cut Wire - Interrompe collegamenti. -end- ho.inv -begin- Invert - Aggiunge o toglie inverters dalle entrate/uscite delle porte logiche. -end- ho.bitw -begin- Bit Width - Cambia la larghezza di un bus. Inserisci il numero di bits nel box in basso a destra della finestra. -end- ho.modopen Apre il modulo selezionato. ho.modclose Chiude il modulo attuale. ho.undo Annulla operazioni precedenti ("Undo") ho.redo Ripristina operazioni annullate ("Redo") ho.simstart -begin- Attiva il simulatore, apre l'analizzatore logico ed esegue eventuali script di inizializzazione. -end- ho.simgo -begin- Mette il simulatore in modalità di simulazione continua. Nota che per circuiti combinatori il simulatore calcola solo fino al raggiungimento dello stato stazionario. -end- ho.simpause -begin- Mette in pausa il simulatore. -end- ho.simstep -begin- Avanza per un intervallo di tempo fisso. Definisci la durata dell'intervallo ("Epoch Step Size") nel formulario di opzioni del simulatore. -end- ho.simclock -begin- Avanza per una quantità fissa di cicli di clock. Definisci la durata dell'intervallo ("Step size") nel formulario di opzioni del simulatore. -end- ho.simstop -begin- Termina la simulazione e torna alla modalità di disegno. -end- ho.simbreak -begin- Modifica i breakpoints. La simulazione viene sospesa non appena la condizione di un breakpoint è verificata. -end- ho.simexec Esegui uno script di simulzione. ho.simload -begin- Carica un file.mem in memoria. -end- ho.simdump -begin- Scarica il contenuto di una memoria in un file.mem. -end- ho.sim.break -begin- Inserisci un breakpoint per il simulatore. I breakpoints sono espressioni che causano la sospensione della simulazione quanto sono verificate. Attualmente sono supportate espressioni con un unico operatore relazionale come "w1 == 0" o "w7 != 8". Possono essere usate anche espressioni come "w8" o "!w2" per eseguire il test "diverso da zero", rispettivamente "uguale a zero". -end- ho.f.modlist -begin- Elenco di tutti i moduli caricati. Il modulo "top-level" è indicato con il segno "+". Moduli di libreria sono fra parentesi. -end- ho.netlist -begin- Elenco dei collegamenti nel modulo attuale. Collegamenti segnati con '@' hanno nomi nascosti. Collegamenti multi-bit sono mostrati con il range. -end- ho.ports -begin- Elenco delle porte del modulo attuale. Il segno '>' indica un input mentre '<' indica un output; il segno '=' indica inout. -end- ho.status.logo -begin- Indicatore di stato del simulatore. Se appare il cancello, TkGate è in modalità di disegno. Se si vede la porta AND a quattro zampe, TkGate si trova in modalità di simulazione: se la AND è ferma, la simulazione è in pausa mentre se cammina, la simulazione sta procedendo. -end- ho.status.msg Messaggi di TkGate vengono mostrati qui. ho.status.block La pila di moduli in lavorazione. ho.status.file -begin- Il file in lavorazione. Un '*' indica che il buffer è stato modificato dall'ultima volta che è stato salvato. -end- ho.print.selall Stampa tutti i moduli attualmente caricati in TKGate. ho.print.selcur Stampa solo il modulo attualmente nella finestra di edit. ho.print.seluse -begin- Stampa tutti i moduli "attivi". I moduli "attivi" sono quelli nella gerarchia del modulo "root". -end- ho.print.fulltrace Stampa tutta la traccia. ho.print.parttrace -begin- Stampa una parte della traccia. Inserisci gli istanti di inizio e di fine nei campi qui sotto o usa il bottone destro del mouse per selezionare una parte della finestra delle tracce (usa shift-right per selezionare pezzi lunghi). -end- ho.print.parttracestart Istante di inizio per la traccia da stampare. ho.print.parttraceend Istante finale per la traccia da stampare. ho.print.selsel -begin- Stampa solo i moduli selezionati qua sotto. Usa il tasto per selezionare più moduli. -end- ho.print.modlist Seleziona i moduli da stampare. ho.circuit.discchg -begin- TkGate non mostrerà avvertimenti se elimini cambiamenti senza salvare. -end- ho.circuit.extbar -begin- Porte logiche di base (AND, OR, XOR) useranno barre di estensione per dar posto a molti input. -end- ho.cmd.bitw -begin- Fili selezionati con il puntatore verranno trasformati in bus con questo numero di bit. -end- ho.edgat.extbar -begin- Se selezionato, porte logiche di base a più ingressi useranno barre di estensione man mano che vengono aggiunte entrate. -end- ho.edgat.signam -begin- Nome del segnale collegato al port selezionato. Qui puoi cambiare il nome del segnale. -end- ho.edgat.port -begin- Nome del port selezionato sul gate. Questo campo può venir modificato solo per istanze di moduli. -end- ho.edgat.iolab -begin- Direzione del port selezionato sul gate. Questo campo può venir modificato solo per istanze di moduli. -end- ho.edgat.bitlab -begin- Larghezza del port e del segnale. Qui puoi cambiare il numero di bit del segnale. -end- ho.edgat.cycle Il numero di epoche in un ciclo di clock. ho.edgat.phase L'inizio del ciclo (in percento). ho.edgat.duty La percentuale del ciclo, il clock è basso. ho.edgat.cname Nome del collegamento. ho.edgat.cport Port a cui è collegato il net. ho.edgat.ctype Tipo di collegamento. ho.edgat.cbitw Larghezza del collegamento (bit width). ho.edgat.cedit Modifica la porta selezionata. ho.edgat.cadd Aggiungi un port. ho.edgat.cdel Cancella il port selezionato. ho.edgat.hide -begin- Attiva questo flag per nascondere il nome della porta logica. -end- ho.edgat.gtype Tipo di porta. ho.edgat.gname Nome di questa istanza di porta logica. ho.edgat.ganchor Attiva questo flag per fissare la posizione di una porta logica. ho.edgat.gx Coordinata X del gate. ho.edgat.gy Coordinata Y del gate. ho.edgat.swstate -begin- Stato iniziale del commutatore da usare all'inizio della simulazione. -end- ho.edgat.dipstate -begin- Stato iniziale del dip switch da usare all'inizio della simulazione. -end- ho.edgat.range Il range di bits da estrarre dal bus. ho.edgat.memfile -begin- Il file con lo stato iniziale di questa memoria. Il file viene letto quando il simulatore viene attivato. -end- ho.edgat.func Il tipo di funzione di questo modulo. ho.edgat.frame L'etichetta del riquadro. ho.traceprint Stampa la traccia. ho.showxhair -begin- Se questo pulsante è attivato, nella finestra delle tracce il cursore è una linea verticale. -end- ho.opt.sorttraces -begin- Se questa opzione è abilitata, le tracce nella finestra del logic analyzer vengono ordinate in ordine alfabetico. Se l'opzione è disabilitata, le tracce vengono mostrate nell'ordine in cui sono state richiamate. -end- ho.opt.rememberprobes -begin- Se questa opzione è attiva, le sonde agganciate durante la simulazione verranno memorizzate e saranno riprese automaticamente al prossimo run di simulazione. -end- ho.opt.undolen -begin- Quantità massima di comandi da mantenere nella lista "undo". -end- ho.opt.site -begin- Nome del sito di istallazione di TkGate. Questo nome appare sui documenti stampati. -end- ho.opt.smooth -begin- Se questa opzione è abilitata, lo scrolling è ottimizzato usando copie bitmap invece di fare un redisplay completo. Spegni questa opzione se vi sono problemi con il tuo server. -end- ho.opt.clip -begin- Se questa opzione è abilitata, verrà usato il meccanismo di clipping per aggiornare solo la parte visibile della finestra in caso di un rinfresco. Altrimenti tutto il display viene ridisegnato. -end- ho.opt.outmove -begin- Se questa opzione è abilitata, in caso di spostamento di moduli ne verrà mostrata solo la sagoma. Usa questa opzione solo su macchine con grafica lenta. -end- ho.opt.bhelp -begin- Se questa opzione è abilitata, verranno mostrati messaggi di aiuto (balloons) sugli oggetti toccati dal puntatore. -end- ho.opt.novice -begin- Se non è specificato alcun circuito sulla linea di comando, all'inizio verrà caricato un tutorial di TkGate. -end- ho.opt.debug -begin- Abilita diverse opzioni di debugging utili solo per gli sviluppatori di TkGate. -end- ho.opt.ckpt Abilita checkpointing di circuiti non ancora salvati. ho.opt.ckptfreq Frequenza di checkpointing in secondi. ho.opt.beak -begin- Disabilita queste opzioni inutili! Se lo fai, questa rubrica e questo checkbox non appariranno più. Per riattivarle, dovrai editare il tuo file .tkgate-preferences. -end- ho.opt.miles -begin- Se questa opzione è attiva, TkGate commenterà periodicamente l'intelligenza delle operazioni dell'utente;-) -end- ho.opt.bat -begin- Se questa opzione è attiva, TkGate si predispone per progettare un computer di Batman... -end- ho.opt.trek Lanciami Scoty! (...da Star Trek...) ho.opt.normal Disabilita i divertimenti. ho.opt.simstep -begin- Quantità di epoche di avanzamento per il comando "Step Epoch(s)". -end- ho.opt.ckstep -begin- Quantità di cicli di clock di avanzamento per il comando "Step Cycle". -end- ho.opt.ckover -begin- La quantità di epoche da simulare oltre il fianco positivo del clock per il comando "Step Cycle". -end- ho.opt.vpopupdelay -begin- Il ritardo in millisecondi fra un click e la visualizzazione del valore di un segnale. Su alcuni sistemi, ritardi brevi compromettono la possibilità di riconoscere il doppio click. Se hai questo problema, aumenta questo valore. Sono ammessi valori fra 1 e 10000. -end- ho.opt.init -begin- Script da eseguire automaticamente quando si attiva la simulazione. -end- ho.opt.ckall -begin- Se questa opzione è abilitata, il comando "Step Cycle" mette in pausa il simulatore al fianco positivo di ogni clock del circuito. -end- ho.opt.ckspec -begin- Se questa opzione è abilitata, il comando "Step Cycle" mette in pausa il simulatore unicamente al fianco positivo del segnale di clock specificato. Fa stato il nome del gate, non del net! -end- ho.deftech -begin- Tecnologia di default per nuove porte logiche. Influenza il delay delle porte. Per cambiare la tecnologia di un gate specifico, apri il formulario delle sue proprietà (doppio click) e seleziona l'opzione "Delay". -end- ho.techbut -begin- Usa i ritardi codificati nel file di definizione della tecnologia standard. Per aggiungere tecnologie personalizzate, inseriscile nella lista nel menu "File -> Options -> Simulate". -end- ho.custbut -begin- Imposta valori di ritardo personalizzati per questa porta. -end- ho.contver -begin- Verifica continuamente l'integrità delle strutture dati interne dopo ogni operazione. -end- ho.simwatch -begin- Visualizza i comandi scambiati fra GUI e simulatore. -end- ho.simlog -begin- Annota in un logfile i comandi passati al simulatore. Il log può venir usato senza GUI per passare comandi al simulatore. Applicazione: debugginig di TkGate. -end- ho.cpathanal -begin- Trova i percorsi critici -end- ########################################### # Added to the swiss-italian localization # P. Ceppi; SUPSI-DTI - April 2004 ## ho.edgate.frame Etichetta del riquadro di commento msg.backupfail Non posso creare il file di backup (protezioni/disco pieno?) tkgate-2.0-b10/locale/it/messages.bak000644 001751 001751 00000073471 11134010127 020151 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Nov 29 14:37:44 2004 \language Italian ############################################################################## # # basic strings # b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel b.open Open... b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete b.deleteb Delete... b.apply Apply b.anchor Anchor b.tech Technology ############################################################################## # Menu strings # file File edit Edit tool Tool simulate Simulate module Module gate Gate make Make circ Circuit new New open Open... openlib Open Library... save Save saveas Save... print Print... options Options... quit Quit undo Undo redo Redo cut Cut copy Copy paste Paste selall Select All find Find... algnv Align Ver. algnh Align Horz. zoomin Zoom In zoomout Zoom Out move Move/Connect delg Delete Gate cutw Cut Wire inv Invert bitw Bit Width debug Debug rot0 Rot 0 rot90 Rot 90 rot180 Rot 180 rot270 Rot 270 simbegin Begin Simulation simend End Simulation simadprobe Add/Delete Probe simrun Run simpause Pause simstep Step Epoch(s) simcycle Step Cycle simbreak Breakpoint... simscript Exec. Script... simload Load Memory... simdump Dump Memory... modopen Open modclose Close modseti Set Interface modediti Edit Interfaces... modnew New... moddel Delete... modcopy Copy... modrename Rename... modclaim Claim... circprop Circuit Properties... cpath Critical Path... gataddin Add Input gataddout Add Output gataddinout Add BiDir gatiochg Change Type gatanchor Anchor Selected gatunanchor Unanchor Selected gatprop Properties... gatrep Replicate gatdel Delete gatsettech Set Technology gmswitch I/O gmgate Gate gmredgate Reduction gmmsi MSI gmalu ALU gmmem Memory gmmod Module gmcomment Comment gmframe Frame gmxswitch Switch gmdip DIP Switch gmground Ground gmvdd Vdd gmmerge Wire Merge gmclock Clock gm.led LED gm.ledbar LED Bar gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Direct) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Buffer gminv Inverter gmtribuf Tri-Buffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Adder gmmult Multiplier gmdiv Divider gmlshift Left Shift gmrshift Right Shift gmarshift Arith. Right Shift gmroll Roll gmreg Register gmff Flip-Flop gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decoder gm14dec 1-4 Decoder gm18dec 1-8 Decoder gmmodinst Module Instance gmmodin Module Input gmmodout Module Output gmmodinout Module InOut addwireseg Add Wire Segment help Help hlpabout About... hlplicense License... hlpdoc Documentation... hlptut Tutorials hlpexample Examples exampcomb Combinational Logic examp3bit 3-Bit Counter examp8bit 8-Bit Counter examptrff Transistor-Level FF exampcpu Menagerie CPU tutwelcome TkGate Intro tutcreate Creating a Circuit tutedit1 Editing a Circuit (1) tutedit2 Editing a Circuit (2) tutmods Using Modules tutsim Simulating a Circuit # Scope Menu menu.sc.prtrace Print Trace... menu.sc.close Close menu.sc.trace Trace menu.sc.zoomin Zoom In menu.sc.zoomout Zoom Out scope.emptymsg Doppio click su un collegamento per agganciare o togliere una sonda. comment.empty [Doppio click per aggiungere testo.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: ############################################################################# # Net Dialog Box # db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # Gate dialog box # db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.gtype Gate Type db.gate.gname Gate Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.memfilenam Memory File db.gate.modname Function db.gate.islink Text is Hyperlink db.gate.link Link to File db.gate.findw Search for wires only db.gate.findg Search for gates only db.gate.findwg Search for wires and gates db.gate.general General db.gate.details Details db.gate.ports Port db.gate.delay Delay db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.extbar Use extender bars db.led.type LED Type db.led.bit Bit db.led.bar Bar Graph db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Direct) ## - Italian localization - ## - April 2004 P. Ceppi; SUPSI-DTI ## - Will translate: ## - - instructive/helpful text only cpath.cloops -begin- Il circuito contiene loop combinatori! Per procedere ad analisi di ritardi in questo circuito devi interrompere i loop oppure indicare una porta per ogni loop come punto di interruzione: lo puoi fare nel form "Properties" della porta, usa il check box "Critical Path Partition". I collegamenti per i quali è stato trovato un loop sono elencati sotto. -end- ############################################################################## # Print dialog box # print.outto Output to print.printer Printer print.file File print.prcmd Print Command print.filename File Name print.epssave Save as Encapsulated Postscript. print.doctit Document Title print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.range Range Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.end End ############################################################################## # # Options dialog # opt.site Site Name opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.outmove Outline Move modules opt.balloon Enable Help Balloons opt.debug Enable Debugging opt.novice Novice Mode opt.ckpoint Do Checkpointing opt.freq Interval opt.beak Enable Special Modes opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Giuan opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.logfile Simulator Log File opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.rememberprobes Remember Probe Placement opt.vpopupdelay Value Pop-Up Delay opt.initscript Initialization script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Delay Files opt.general General opt.print Print opt.simulate Simulate opt.analysis Analysis opt.color Color opt.undolen Max Undo opt.cpopts Critical Path Options: opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.vercheck -begin- Controlla di tanto in tanto se ci sono nuove versioni di TkGate in rete. Non abilitare se non hai accesso continuo a Internet. -end- ############################################################################## # # Block list dialog boxes blklst.newmod New Module blklst.delmod Delete Module blklst.frommod Copy Module From blklst.tomod To blklst.oldname Old Name blklst.newname New Name blklst.claim Claim Module ############################################################################## # # Circuit Dialog box # circ.topmod Top-Level Module circ.discchg Discard Changes circ.iniscript Initialization Scripts circ.noscript No script files selected. circ.really1 Do you really want to remove circ.really2 from the list of initialization scripts circ.extbar Use Extender Bars ############################################################################## # Simulator # sim.breakpt Breakpoint ############################################################################## # # Command box # cmd.file File Name cmd.topname Top Module Name ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.verilog Errrori nel file: err.nopin Non posso modificare il pin selezionato. err.badhex Valore hex '%s' errato: viene ignorato. err.gatanchor Le porte sono ancorate: non possono essere spostate. err.libmode Operazione non ammessa su un modulo di libreria (convertilo in un modulo normale per editarlo). err.badfind Non trovo il target '%s'. err.badopendel Non posso cancellare un modulo aperto. err.nosrcmod Non ho trovato il modulo '%s'. err.noerr Non so localizzare l'errore. err.misserr Errore informazione incompleta (il simulatore è caduto?) err.pounimpl Errore non implementato in ParseOption err.badinadd Non posso aggiungere ulteriori pin di input alla porta selezionata. err.badoutadd Non posso aggiungere ulteriori pin di output alla porta selezionata. err.badinoutadd Non posso aggiungere ulteriori pin inout alla porta selezionata. err.badpinchg Non posso modificare il tipo di pin della porta selezionata. err.badnetname Carattere non ammesso cancellato dall'identificatore. err.netbcrename Identificatore rinominato con '%s' a causa di un carattere non ammesso. err.netconfnet Identificatore rinominato con '%s' a causa di un conflitto. err.netconfgat Identificatore rinominato per evitare conflitti con nomi di porte primitive. err.netconfkw Identificatore rinominato per evitare conflitti con parole riservate. err.badconsame Collegamento rifiutato perchè i fili appartengono allo stesso collegamento. err.badconptsp Collegamento rifiutato perchè ambedue i fili sono porte di moduli o alimentazioni. err.badconbitw Collegamento rifiutato perchè il numero di bit non coincide. err.badrange L'istante di inizio deve precedere quello di fine della stampa (Start < End)! err.badlprcmd Non posso eseguire il comando di stampa '%s'. err.badpsopen Non posso aprire il '%s' per output in postscript. err.badid Identificatore non ammesso '%s'. err.bkpt.badexp Errore di sintassi nell'espressione di breakpoint. Devi scegliere fra: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Errore nel nome del collegamento '%s'. I nomi devono iniziare con una lettera e contengono solo lettere, numeri e '.'. err.bkpt.badval Errore di sintassi nel valore '%s'. Deve essere un decimale o una costante in stile verilog. err.bkpt.toomany Troppi breakpoints. Al massimo %d. err.sim.badtmp Non ho potuto salvare il file temporaneo '%s' per il simulatore (disco pieno?) err.sim.syntx Errore di sintassi nel comando '%s'. err.sim.noincl Non trovo il file '%s' da includere. err.sim.clockbadedge Specifica di fianco '%c' non ammessa nel comando di avanzamento della simulazione. err.sim.nobkpt Il breakpoint '%s' non esiste. err.sim.nonet Non trovo il collegamento '%s'. err.sim.nogate Non trovo il gate '%s'. err.sim.badbin Carattere non ammesso nella costante binaria '%s'. err.sim.notswitch Il gate '%s' non è uno switch, un dip o un registro. Il comando "Set" si applica solo a questi componenti. err.sim.badcmd Comando sconosciuto '%s' nello script di simulazione. err.noteditpchg Le proprietà possono venir cambiata solo in modalità di edizione. err.badeditop Operazione non ammessa in modalità di edizione di interfaccia. err.badopen Impossibile aprire il file '%s'. err.badlibopen Impossibile aprire il file di libreria '%s'. err.nomark Posiziona un punto di riferimento con il tasto sinstro del mouse prima di scegliere un gate. err.badgate Tipo di gate sconosciuto. err.badmake Non posso a creare il gate. err.badportadd Impossibile aggiungere porte a un gate di questo tipo. err.badportdel La porta selezionata non può essere concellata. err.badportedit La porta selezionata non può essere modificata. err.noport Non è stata selezionato alcun port. err.manypages -begin- C'è una quantità tremenda di pagine in questo documento! Sei sicuro di volerlo stampare? -end- err.nojump -begin- L'opzione 'jump-to-module' non è disponibile nella modalità di simulazione o di analisi del percorso critico. Spostati manualmente nel blocco desiderato selezionando moduli e aprendoli con il carattere '>' da tastiera. Puoi abbandonare un modulo inserendo il carattere '<' da tastiera. -end- err.nomod Il modulo '%s' non è definito. err.modlock Il blocco logico è bloccato ("locked")! err.closeroot Non posso chiudere il modulo "top". Usa "quit". err.sim.isrun Il simulatore è già attivo (Usa 'Ctrl-s e' per terminare). err.sim.isnotrun Il simulatore non è attivo (Usa 'Ctrl-s b' per avviarlo). err.editonly Comando non ammesso in modalità di simulazione. err.simonly Comando ammesso solo in modalità di simulazione. err.nodel Non è selezionato alcun elemento cancellabile. err.modnotdef Il module '%s' non è definito. err.moddef Il blocco '%s' esiste già. err.noprop Il gate selezionato non ha proprietà editabili. err.openscript Non posso aprire lo script di simulazione '%s' err.oldversion Caricato un file con l'identificatore di versione obsoleta %s (la versione attuale è %s). err.futureversion Caricato un file salvato dalla versione futura %s di TkGate (questa versione è %s). err.badversion Numero di versione sconosciuto. Usa a tuo rischio. err.nodrive Il collegamento %s non ha driver nel modulo %s. err.noconn Il filo %s{%d} non ha collegamenti - cancellato. err.oldportact Clicca con il tasto destro sul port o sul bordo del modulo per aggiungere/modificare un port. err.backupfail Non riesco a creare il file di backup '%s'. err.corruptnewsave -begin- TkGate è riuscito a salvare il file '%s', ma sembra rovinato. Se hai abilitato la modalità "checkpointing" prova a caricare uno dei files di "checkpoint". Usa 'tkgate -V' per verificare l'integrità di un file di salvataggio. -end- err.corruptsave -begin- TkGate ha riscontrato un problema nel salvataggio del file '%s'. Il file esistente è stato lasciato intatto e il file danneggiato è stato salvato in '%s'. Se hai abilitato la modalità "checkpointing" puoi provare a caricare uno dei files di "checkpoint". Puoi anche usare 'tkgate -V' per verificare l'integrità di un file di salvataggio. -end- err.badsave -begin- C'è un problema ad aprire o a salvare il file '%s'. Controlla le protezioni del file/directory e/o lo spazio disco. -end- err.nosafesave -begin- C'è un problema a salvare '%s'. Se vuoi, puoi ritentare senza validazione. Se rispondi "no", il file originale rimane inalterato. Se rispondi "yes" il file originale verrà sovrascritto, ma potrebbe venir distrutto se si verifica un problema. Vuoi tentare un salvataggio senza validazione? -end- err.noback -begin- Il file è stato creato con TkGate %s. Se lo salvi, è probabile che non possa venir riletto da versioni precedenti a questa (%s). -end- ############################################################################## # Informational messages # msg.selwire Nome del collegamento: '%s' msg.selgate Hai selezionato %s con il nome '%s'. msg.selblock Hai selezionato il blocco %s denominato '%s'. msg.modoverwt Il modulo '%s' esiste già. Sovrascrivere? msg.foundgate Trovato una porta con il nome '%s'. msg.foundwire Trovato un collegamento con il nome '%s'. msg.searchagn Stringa '%s' non trovata. Inserisci 'find' per riavviare la ricerca. msg.sim.chgtoroot La modalità di simulazione richiede il modulo "root" in cima allo stack di edizione. msg.sim.nogatemod La modalità di simulazione richiede moduli istanziati ("Concrete module stack). msg.setinterface Impostato interfaccia per il modulo '%s' msg.needsel Seleziona un'istanza di modulo. msg.wroteckpt "Checkpointed" in %s... msg.save Circuito salvato in '%s' msg.reallynew Il circuito è stato modificato. Vuoi veramente scartare le tue modifiche e creare un circuito nuovo? msg.reallyquit Il circuito è stato modificato. Vuoi veramente uscire senza salvare? msg.notlib Il modulo '%s' non è un modulo di libreria. ############################################################################## # Messaggi par ul Giuan (Dupraa quant ul Giuan Bambela 'l dupera ul TkGate) # miles.msg1 Dumà un cücümar al metaresa ul %s%s lì, Giuan. miles.msg2 L'è propi un post stupit par met ul %s%s, Giuan. miles.msg3 L'è un pustasc par ul %s%s, Giuan; pesc d'inscì ta pudevat mia catà fö! miles.msg4 Ma no Giuan, lè mia ul post par ul %s%s linscì. miles.msg5 Propi dumà ti ta po met ul %s%s lì, Giuan. miles.msg6 S'al metat lì da fa 'stu %s%s?! Ta see propi dür da cumprendoni, Giuan. miles.msg7 Pianta lì Giuan, l'è propi un lavur da ciola. miles.msg8a L'è propi mia ul to mestee Giuan, lasa pert. miles.msg8b Ta se propi mia bun da met giò 'stu schema. ############################################################################## # Balloon Help # ho.new -begin- Abbandona il circuito attuale e inizia a disegnarne uno nuovo. -end- ho.open Carica (open) un circuito da un file. ho.save Salva il circuito nel file corrente. ho.print Stampa il circuito corrente. ho.move -begin- Move/Connect - By clicking and dragging you can: Scegliere la posizione per una nuova porta Spostare porte e collgamenti Collegare fili By double-clicking you can: Modificare le proprietà di porte logiche, collegamenti e ports Modificare commenti -end- ho.delgat -begin- Delete Gate - Elimina porte logiche. -end- ho.cutw -begin- Cut Wire - Interrompe collegamenti. -end- ho.inv -begin- Invert - Aggiunge o toglie inverters dalle entrate/uscite delle porte logiche. -end- ho.bitw -begin- Bit Width - Cambia la larghezza di un bus. Inserisci il numero di bits nel box in basso a destra della finestra. -end- ho.modopen Apre il modulo selezionato. ho.modclose Chiude il modulo attuale. ho.undo Annulla operazioni precedenti ("Undo") ho.redo Ripristina operazioni annullate ("Redo") ho.simstart -begin- Attiva il simulatore, apre l'analizzatore logico ed esegue eventuali script di inizializzazione. -end- ho.simgo -begin- Mette il simulatore in modalità di simulazione continua. Nota che per circuiti combinatori il simulatore calcola solo fino al raggiungimento dello stato stazionario. -end- ho.simpause -begin- Mette in pausa il simulatore. -end- ho.simstep -begin- Avanza per un intervallo di tempo fisso. Definisci la durata dell'intervallo ("Epoch Step Size") nel formulario di opzioni del simulatore. -end- ho.simclock -begin- Avanza per una quantità fissa di cicli di clock. Definisci la durata dell'intervallo ("Step size") nel formulario di opzioni del simulatore. -end- ho.simstop -begin- Termina la simulazione e torna alla modalità di disegno. -end- ho.simbreak -begin- Modifica i breakpoints. La simulazione viene sospesa non appena la condizione di un breakpoint è verificata. -end- ho.simexec Esegui uno script di simulzione. ho.simload -begin- Carica un file.mem in memoria. -end- ho.simdump -begin- Scarica il contenuto di una memoria in un file.mem. -end- ho.sim.break -begin- Inserisci un breakpoint per il simulatore. I breakpoints sono espressioni che causano la sospensione della simulazione quanto sono verificate. Attualmente sono supportate espressioni con un unico operatore relazionale come "w1 == 0" o "w7 != 8". Possono essere usate anche espressioni come "w8" o "!w2" per eseguire il test "diverso da zero", rispettivamente "uguale a zero". -end- ho.f.modlist -begin- Elenco di tutti i moduli caricati. Il modulo "top-level" è indicato con il segno "+". Moduli di libreria sono fra parentesi. -end- ho.netlist -begin- Elenco dei collegamenti nel modulo attuale. Collegamenti segnati con '@' hanno nomi nascosti. Collegamenti multi-bit sono mostrati con il range. -end- ho.ports -begin- Elenco delle porte del modulo attuale. Il segno '>' indica un input mentre '<' indica un output; il segno '=' indica inout. -end- ho.status.logo -begin- Indicatore di stato del simulatore. Se appare il cancello, TkGate è in modalità di disegno. Se si vede la porta AND a quattro zampe, TkGate si trova in modalità di simulazione: se la AND è ferma, la simulazione è in pausa mentre se cammina, la simulazione sta procedendo. -end- ho.status.msg Messaggi di TkGate vengono mostrati qui. ho.status.block La pila di moduli in lavorazione. ho.status.file -begin- Il file in lavorazione. Un '*' indica che il buffer è stato modificato dall'ultima volta che è stato salvato. -end- ho.print.selall Stampa tutti i moduli attualmente caricati in TKGate. ho.print.selcur Stampa solo il modulo attualmente nella finestra di edit. ho.print.seluse -begin- Stampa tutti i moduli "attivi". I moduli "attivi" sono quelli nella gerarchia del modulo "root". -end- ho.print.fulltrace Stampa tutta la traccia. ho.print.parttrace -begin- Stampa una parte della traccia. Inserisci gli istanti di inizio e di fine nei campi qui sotto o usa il bottone destro del mouse per selezionare una parte della finestra delle tracce (usa shift-right per selezionare pezzi lunghi). -end- ho.print.parttracestart Istante di inizio per la traccia da stampare. ho.print.parttraceend Istante finale per la traccia da stampare. ho.print.selsel -begin- Stampa solo i moduli selezionati qua sotto. Usa il tasto per selezionare più moduli. -end- ho.print.modlist Seleziona i moduli da stampare. ho.circuit.discchg -begin- TkGate non mostrerà avvertimenti se elimini cambiamenti senza salvare. -end- ho.circuit.extbar -begin- Porte logiche di base (AND, OR, XOR) useranno barre di estensione per dar posto a molti input. -end- ho.cmd.bitw -begin- Fili selezionati con il puntatore verranno trasformati in bus con questo numero di bit. -end- ho.edgat.extbar -begin- Se selezionato, porte logiche di base a più ingressi useranno barre di estensione man mano che vengono aggiunte entrate. -end- ho.edgat.signam -begin- Nome del segnale collegato al port selezionato. Qui puoi cambiare il nome del segnale. -end- ho.edgat.port -begin- Nome del port selezionato sul gate. Questo campo può venir modificato solo per istanze di moduli. -end- ho.edgat.iolab -begin- Direzione del port selezionato sul gate. Questo campo può venir modificato solo per istanze di moduli. -end- ho.edgat.bitlab -begin- Larghezza del port e del segnale. Qui puoi cambiare il numero di bit del segnale. -end- ho.edgat.cycle Il numero di epoche in un ciclo di clock. ho.edgat.phase L'inizio del ciclo (in percento). ho.edgat.duty La percentuale del ciclo, il clock è basso. ho.edgat.cname Nome del collegamento. ho.edgat.cport Port a cui è collegato il net. ho.edgat.ctype Tipo di collegamento. ho.edgat.cbitw Larghezza del collegamento (bit width). ho.edgat.cedit Modifica la porta selezionata. ho.edgat.cadd Aggiungi un port. ho.edgat.cdel Cancella il port selezionato. ho.edgat.hide -begin- Attiva questo flag per nascondere il nome della porta logica. -end- ho.edgat.gtype Tipo di porta. ho.edgat.gname Nome di questa istanza di porta logica. ho.edgat.ganchor Attiva questo flag per fissare la posizione di una porta logica. ho.edgat.gx Coordinata X del gate. ho.edgat.gy Coordinata Y del gate. ho.edgat.swstate -begin- Stato iniziale del commutatore da usare all'inizio della simulazione. -end- ho.edgat.dipstate -begin- Stato iniziale del dip switch da usare all'inizio della simulazione. -end- ho.edgat.range Il range di bits da estrarre dal bus. ho.edgat.memfile -begin- Il file con lo stato iniziale di questa memoria. Il file viene letto quando il simulatore viene attivato. -end- ho.edgat.func Il tipo di funzione di questo modulo. ho.edgat.frame L'etichetta del riquadro. ho.traceprint Stampa la traccia. ho.showxhair -begin- Se questo pulsante è attivato, nella finestra delle tracce il cursore è una linea verticale. -end- ho.opt.sorttraces -begin- Se questa opzione è abilitata, le tracce nella finestra del logic analyzer vengono ordinate in ordine alfabetico. Se l'opzione è disabilitata, le tracce vengono mostrate nell'ordine in cui sono state richiamate. -end- ho.opt.rememberprobes -begin- Se questa opzione è attiva, le sonde agganciate durante la simulazione verranno memorizzate e saranno riprese automaticamente al prossimo run di simulazione. -end- ho.opt.undolen -begin- Quantità massima di comandi da mantenere nella lista "undo". -end- ho.opt.site -begin- Nome del sito di istallazione di TkGate. Questo nome appare sui documenti stampati. -end- ho.opt.smooth -begin- Se questa opzione è abilitata, lo scrolling è ottimizzato usando copie bitmap invece di fare un redisplay completo. Spegni questa opzione se vi sono problemi con il tuo server. -end- ho.opt.clip -begin- Se questa opzione è abilitata, verrà usato il meccanismo di clipping per aggiornare solo la parte visibile della finestra in caso di un rinfresco. Altrimenti tutto il display viene ridisegnato. -end- ho.opt.outmove -begin- Se questa opzione è abilitata, in caso di spostamento di moduli ne verrà mostrata solo la sagoma. Usa questa opzione solo su macchine con grafica lenta. -end- ho.opt.bhelp -begin- Se questa opzione è abilitata, verranno mostrati messaggi di aiuto (balloons) sugli oggetti toccati dal puntatore. -end- ho.opt.novice -begin- Se non è specificato alcun circuito sulla linea di comando, all'inizio verrà caricato un tutorial di TkGate. -end- ho.opt.debug -begin- Abilita diverse opzioni di debugging utili solo per gli sviluppatori di TkGate. -end- ho.opt.ckpt Abilita checkpointing di circuiti non ancora salvati. ho.opt.ckptfreq Frequenza di checkpointing in secondi. ho.opt.beak -begin- Disabilita queste opzioni inutili! Se lo fai, questa rubrica e questo checkbox non appariranno più. Per riattivarle, dovrai editare il tuo file .tkgate-preferences. -end- ho.opt.miles -begin- Se questa opzione è attiva, TkGate commenterà periodicamente l'intelligenza delle operazioni dell'utente;-) -end- ho.opt.bat -begin- Se questa opzione è attiva, TkGate si predispone per progettare un computer di Batman... -end- ho.opt.trek Lanciami Scoty! (...da Star Trek...) ho.opt.normal Disabilita i divertimenti. ho.opt.simstep -begin- Quantità di epoche di avanzamento per il comando "Step Epoch(s)". -end- ho.opt.ckstep -begin- Quantità di cicli di clock di avanzamento per il comando "Step Cycle". -end- ho.opt.ckover -begin- La quantità di epoche da simulare oltre il fianco positivo del clock per il comando "Step Cycle". -end- ho.opt.vpopupdelay -begin- Il ritardo in millisecondi fra un click e la visualizzazione del valore di un segnale. Su alcuni sistemi, ritardi brevi compromettono la possibilità di riconoscere il doppio click. Se hai questo problema, aumenta questo valore. Sono ammessi valori fra 1 e 10000. -end- ho.opt.init -begin- Script da eseguire automaticamente quando si attiva la simulazione. -end- ho.opt.ckall -begin- Se questa opzione è abilitata, il comando "Step Cycle" mette in pausa il simulatore al fianco positivo di ogni clock del circuito. -end- ho.opt.ckspec -begin- Se questa opzione è abilitata, il comando "Step Cycle" mette in pausa il simulatore unicamente al fianco positivo del segnale di clock specificato. Fa stato il nome del gate, non del net! -end- ho.deftech -begin- Tecnologia di default per nuove porte logiche. Influenza il delay delle porte. Per cambiare la tecnologia di un gate specifico, apri il formulario delle sue proprietà (doppio click) e seleziona l'opzione "Delay". -end- ho.techbut -begin- Usa i ritardi codificati nel file di definizione della tecnologia standard. Per aggiungere tecnologie personalizzate, inseriscile nella lista nel menu "File -> Options -> Simulate". -end- ho.custbut -begin- Imposta valori di ritardo personalizzati per questa porta. -end- ho.contver -begin- Verifica continuamente l'integrità delle strutture dati interne dopo ogni operazione. -end- ho.simwatch -begin- Visualizza i comandi scambiati fra GUI e simulatore. -end- ho.simlog -begin- Annota in un logfile i comandi passati al simulatore. Il log può venir usato senza GUI per passare comandi al simulatore. Applicazione: debugginig di TkGate. -end- ho.cpathanal -begin- Trova i percorsi critici -end- ########################################### # Added to the swiss-italian localization # P. Ceppi; SUPSI-DTI - April 2004 ## ho.edgate.frame Etichetta del riquadro di commento msg.backupfail Non posso creare il file di backup (protezioni/disco pieno?) tkgate-2.0-b10/locale/it/tutorials.18/edwire_tut.v000644 001751 001751 00000023713 10152673133 022507 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 /dp:1 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 /dp:1 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g61 /dolink:0 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end xor g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: comment g4 /dolink:0 /link:"" @(536,248) /sn:0 /anc:1 //: /line:"<---" //: /end //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] or g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] and g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end and g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] buf g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] and g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] and g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] buf g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] and g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g6 /dolink:0 /link:"" @(22,11) /sn:0 /anc:1 //: /line:"Questo tutorial introduce al tracciamento dei collegamenti." //: /end //: comment g53 /dolink:0 /link:"" @(720,525) /sn:0 /anc:1 //: /line:"<---" //: /end //: comment g7 /dolink:0 /link:"" @(507,152) /sn:0 /anc:1 //: /line:"<---" //: /end //: comment g9 /dolink:0 /link:"" @(26,30) /anc:1 //: /line:"1) TkGate ha un meccanismo di \"gravità\" che elimina" //: /line:"automaticamente segmenti corti. Clicca sul collegamento" //: /line:"nel punto indicato dalla freccia nel circuito di Fig. 1 " //: /line:"e spostalo fin quasi ad allinearlo con l'altro segmento" //: /line:"verticale. Quando rilasci il tasto i segmenti verticali" //: /line:"si agganciano, eliminando lo scostamento orizzontale." //: /line:"" //: /line:"2) TkGate cancella automaticamente loop di collegamenti." //: /line:"Seleziona l'estremità  del filo indicato dalla freccia " //: /line:"in Fig. 2 e, pigiando il tasto sinistro del mouse," //: /line:"trascinala sul segmento di collegamento all'uscita della" //: /line:"porta XOR. Rilascia il tasto del mouse e osserva. " //: /line:"Questo comportemento può essere disattivato tenendo " //: /line:"pigiato il tasto Alt mentre si spostano i collegamenti." //: /line:"" //: /line:"3) TkGate cancella automaticamente anche giunzioni inutili." //: /line:"Seleziona il tronchesino e taglia il collegamento" //: /line:"nel punto indicato dalla freccia in Fig. 3a." //: /line:"Nota che la giunzione viene cancellata. " //: /line:"Ora taglia il collegamento nel punto indicato dalla" //: /line:"freccia in Fig. 3b. Il segmento morto viene cancellato." //: /line:"" //: /line:"4) Ritorna al puntatore di base (Move/Connect mode - F1)" //: /line:"e seleziona l'ingresso libero del buffer in basso " //: /line:"di Fig. 4a in modo da far apparire il saldatore. Sposta il " //: /line:"puntatore-saldatore vicino alla giunzione e rilascia il " //: /line:"tasto del mouse. Il collegamento si aggancia alla giunzione." //: /line:"Ora ripeti l'operazione in Fig. 4b, rilascia però il tasto" //: /line:"a metà  strada fra l'uscita della porta AND e la giunzione." //: /line:"Viene creata una nuova giunzione." //: /line:"" //: /line:"5) Aggiungi un segmento di filo per collegare l'uscita" //: /line:"della porta AND all'entrata dei due buffer sulla destra." //: /line:"In Fig. 5 clicca con il tasto destro sul collegamento nel" //: /line:"punto indicato dalla freccia e scegli \"Add Wire Segment\"." //: /line:"Ora puoi collegare l'estremità del segmento con l'entrata" //: /line:"dei buffer usando il saldatore." //: /line:"" //: /line:"6) Nelle figure 6a e 6b, seleziona i collegamenti nei" //: /line:"punti indicati dalle frecce e trascinali verso sinistra" //: /line:"oltre l'uscita della porta AND, rispettivamente oltre" //: /line:"la posizione della giunzione." //: /line:"In Fig. 6a verranno aggiunti segmenti in modo da assicurare" //: /line:"che il collegamento esca dalla porta verso destra." //: /line:"In Fig. 6b la posizione dei collegamenti attorno alla" //: /line:"giunzione viene aggiustato." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" and g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] buf g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" buf g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] and g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" and g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end and g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] buf g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] buf g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 /dolink:0 /link:"" @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" buf g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: comment g54 /dolink:0 /link:"" @(556,521) /sn:0 /anc:1 //: /line:"<---" //: /end //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" buf g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" buf g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] //: comment g22 /dolink:0 /link:"" @(605,100) /sn:0 /anc:1 //: /line:"->" //: /end and g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] //: comment g12 /dolink:0 /link:"" @(549,50) /sn:0 /anc:1 //: /line:"<---" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end and g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 /dolink:0 /link:"" @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end buf g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule tkgate-2.0-b10/locale/it/tutorials.18/create_tut.v000644 001751 001751 00000010442 10152673133 022466 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(232,502)(177,502){1} //: {2}(175,500)(175,466)(187,466){3} //: {4}(173,502)(141,502){5} wire w7; //: /sn:0 {0}(253,500)(263,500){1} wire w2; //: /sn:0 {0}(187,461)(141,461){1} wire w5; //: /sn:0 {0}(232,497)(218,497)(218,464)(208,464){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end //: comment g8 /dolink:0 /link:"" @(250,481) /anc:1 //: /line:"OR gate" //: /end or g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(243,500) /sn:0 /anc:1 /w:[ 0 0 0 ] and g3 (.I0(w2), .I1(w6), .Z(w5)); //: @(198,464) /sn:0 /anc:1 /w:[ 0 3 1 ] //: frame g13 @(428,388) /sn:0 /wi:381 /ht:177 /tx:"Disegna qui" //: switch g2 (w6) @(124,502) /sn:0 /anc:1 /w:[ 5 ] /st:0 //: switch g1 (w2) @(124,461) /sn:0 /anc:1 /w:[ 1 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: comment g10 /dolink:0 /link:"" @(12,249) /anc:1 //: /line:"5) Inserisci i due interruttori con la stessa procedura usata per le porte: " //: /line:" a) scegli la posizione;" //: /line:" b) seleziona \"Switch\" dal sottomenu \"I/O\" di \"Make\", oppure digita \"s\"." //: /line:"" //: /line:"6) Ripeti la procedura del punto 4 e collega le uscite degli interruttori con la porta AND, rispettivamente OR." //: /line:"" //: /line:"7) Sull'ingresso inferiore della porta AND clicca e mantieni premuto il tasto sinistro del mouse" //: /line:"in modo da far apparire il saldatore. Trascinalo a metà  del collegamento fra interruttore inferiore e porta OR." //: /line:"Rilascia il tasto." //: /line:"Un punto di giunzione viene inserito automaticamente." //: /end //: comment g6 /dolink:0 /link:"" @(101,427) /anc:1 //: /line:"Switches" //: /end //: comment g9 /dolink:0 /link:"" @(12,9) /anc:1 //: /line:"1) In questo esempio realizzerai un circuito come quello mostrato sotto. " //: /line:"Disegna il circuito nell'area incorniciata in basso a destra. " //: /line:"Per cominciare, definisci la posizione per la porta AND cliccando il tasto " //: /line:"destro del mouse nella posizione voluta. Apparirà  una \"X\" per indicare" //: /line:"il punto di inserimento." //: /line:"" //: /line:"2) Per inserire una porta AND nella posizione scelta, seleziona \"AND\"" //: /line:"dal sottomenu \"Gate\" del popup \"Make\" (o da \"Make\" della barra dei menu)." //: /line:"In alternativa puoi inserire il carattere \"a\" da tastiera." //: /line:"" //: /line:"3) Inserisci la porta OR sulla destra, un po' sotto la AND: " //: /line:" a) segna la posizione (\"X\");" //: /line:" b) inserisci la OR scegliendola dal sottomenu \"Gate\" del popup \"Make\" oppure" //: /line:" digita il carattere \"o\"." //: /line:"" //: /line:"4) Collega l'ingresso superiore della porta OR con l'uscita della AND:" //: /line:" a) clicca sull'uscita della porta AND e mantieni premuto il tasto sinistro " //: /line:" del mouse. Il cursore cambia aspetto e diventa un saldatore;" //: /line:" b) trascina il saldatore vicino al filo d'ingresso della porta OR e rilascia" //: /line:" il tasto. I fili si agganciano." //: /end //: comment g7 /dolink:0 /link:"" @(193,441) /anc:1 //: /line:"AND gate" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" //: comment g20 /dolink:0 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end //: joint g5 (w6) @(175, 502) /anc:1 /w:[ 1 2 4 -1 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: comment g22 /dolink:0 /link:"" @(605,55) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end endmodule tkgate-2.0-b10/locale/it/tutorials.18/welcome_tut.v000644 001751 001751 00000035465 10152677241 022676 0ustar00hansenhansen000000 000000 //: version "1.8.4" //: property discardChanges = 1 module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>B[7:0](67/89) Ti1>A[7:0](20/89) Li0>F[1:0](28/65) Bo0AIN[7:0](46/94) Li0>ck(56/80) Li1>SB[1:0](34/80) Li2>SA[1:0](14/80) Bo00 Ti1>0 Li0>1 Bo0<1 ] REGS regs (.AIN(w17), .ck(ck), .SB(w23), .SA(w21), .BOUT(w15), .AOUT(w6)); //: @(679, 457) /sz:(94, 80) /p:[ Ti0>0 Li0>1 Li1>0 Li2>1 Bo0<3 Bo1<3 ] //: supply0 g43 (w11) @(496,401) /sn:0 /w:[ 0 ] //: dip func (w26) @(599,356) /R:1 /w:[ 0 ] /st:0 led g48 (.I(reg_out)); //: @(468,549) /sn:0 /R:2 /w:[ 5 ] /type:1 led g62 (.I(w6)); //: @(773,245) /sn:0 /w:[ 5 ] /type:2 //: joint g29 (a) @(106, 456) /w:[ 2 -1 1 4 ] //: switch g25 (a) @(45,456) /sn:0 /w:[ 0 ] /st:0 //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: dip g42 (w14) @(440,322) /sn:0 /w:[ 1 ] /st:248 led g52 (.I(s)); //: @(230,486) /sn:0 /R:2 /w:[ 1 ] /type:0 //: dip data_in (w25) @(620,233) /R:1 /w:[ 0 ] /st:11 //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end led g56 (.I(w13)); //: @(295,374) /sn:0 /w:[ 5 ] /type:0 pmos g5 (.Z(w5), .S0(w13), .G0(w1)); //: @(250,367) /sn:0 /w:[ 1 9 3 ] //: comment g47 /dolink:0 /link:"" @(249,285) /sn:0 /anc:1 //: /line:" per iniziare." //: /end //: switch g44 (w19) @(344,430) /sn:0 /w:[ 1 ] /st:1 add g36 (.A(w14), .B(reg_out), .S(w16), .CI(w11), .CO(w18)); //: @(456,375) /sn:0 /w:[ 0 3 1 1 0 ] xor g24 (.I0(w8), .I1(ci), .Z(s)); //: @(202,462) /sn:0 /w:[ 0 3 0 ] /eb:0 //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: supply0 g41 (w9) @(387,401) /sn:0 /w:[ 0 ] xor g23 (.I0(a), .I1(b), .Z(w8)); //: @(127,459) /sn:0 /w:[ 3 3 3 ] /eb:0 //: joint g60 (w15) @(773, 335) /w:[ 2 4 1 -1 ] led g54 (.I(w1)); //: @(194,351) /sn:0 /w:[ 5 ] /type:0 mux g40 (.I0(w9), .I1(w16), .S(w19), .Z(w20)); //: @(421,430) /sn:0 /w:[ 1 0 0 0 ] //: comment g46 /dolink:1 /link:"@T/create_tut.v" @(105,285) /sn:0 /anc:1 //: /line:" \"Creare un circuito\" " //: /end //: comment g45 /dolink:0 /link:"" @(17,285) /sn:0 /anc:1 //: /line:"Ora clicca su " //: /end register g35 (.Q(reg_out), .D(w20), .EN(w12), .CLR(w10), .CK(clk)); //: @(421,476) /sn:0 /w:[ 0 1 1 0 1 ] //: switch g26 (b) @(45,491) /sn:0 /w:[ 0 ] /st:1 //: comment g0 /dolink:0 /link:"" @(13,16) /anc:1 //: /line:"Benvenuto in TkGate !" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; v. menu 'Help...License'" //: /line:" per dettagli di licenza e di garanzia. Segnalare problemi a " //: /line:"" //: /line:" * Questa introduzione guidata appare automaticamente" //: /line:" quando attivi per la prima volta TkGate. Puoi disabilitarla" //: /line:" selezionando \"Options...\" nel menu \"File\" e spegnendo \"Novice Mode\"." //: /line:"" //: /line:" * Puoi creare un circuito nuovo selezionando \"New\" dal menu \"File\" oppure" //: /line:" caricare un circuito esistente con \"Open...\"" //: /line:"" //: /line:" * Per la documentazione completa di TkGate, vedi " //: /line:"" //: /line:"Questa è una guida al primo uso di TkGate. " //: /line:"Per muoverti nella guida usa i collegamenti che trovi in alto a destra." //: /line:"In alternativa, puoi selezionare i tutorials dal menu \"Help\"." //: /line:"Nei tutorials esegui i passi nell'ordine in cui sono numerati." //: /line:"Quando avrai completato tutti i tutorials potrai selezionare gli altri esempi" //: /line:"del menu \"Help\"." //: /end //: comment g22 /dolink:0 /link:"" @(605,40) /sn:0 /anc:1 //: /line:"->" //: /end //: switch data_select (w28) @(620,293) /w:[ 0 ] /st:0 //: switch g12 (w1) @(139,367) /sn:0 /w:[ 0 ] /st:0 //: comment g18 /dolink:0 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end //: joint g33 (ci) @(166, 464) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(100, 491) /w:[ -1 2 1 4 ] //: joint g49 (reg_out) @(468, 523) /w:[ 2 -1 1 4 ] endmodule tkgate-2.0-b10/locale/it/tutorials.18/sim_tut.v000644 001751 001751 00000013434 10152673133 022017 0ustar00hansenhansen000000 000000 //: version "1.8.5" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(750,326)(678,326){1} wire w4; //: /sn:0 {0}(652,260)(620,260){1} //: {2}(618,258)(618,240)(588,240){3} //: {4}(586,238)(586,227){5} //: {6}(584,240)(571,240){7} //: {8}(618,262)(618,323)(657,323){9} wire w0; //: /sn:0 {0}(750,321)(707,321)(707,305){1} wire w3; //: /sn:0 {0}(687,225)(707,225){1} //: {2}(709,223)(709,214){3} //: {4}(709,227)(709,256){5} //: {6}(711,258)(749,258){7} //: {8}(709,260)(709,284){9} wire w1; //: /sn:0 {0}(749,263)(706,263){1} //: {2}(702,263)(673,263){3} //: {4}(704,265)(704,284){5} wire C; //: /dp:1 {0}(798,312)(798,324)(771,324){1} wire w5; //: /sn:0 {0}(569,288)(585,288){1} //: {2}(589,288)(607,288){3} //: {4}(609,286)(609,265)(652,265){5} //: {6}(609,290)(609,328)(657,328){7} //: {8}(587,286)(587,276){9} wire S; //: {0}(770,261)(795,261)(795,251){1} //: enddecls nand g8 (.I0(w0), .I1(w6), .Z(C)); //: @(761,324) /sn:0 /w:[ 0 0 1 ] xor g4 (.I0(w4), .I1(w5), .Z(w1)); //: @(663,263) /sn:0 /w:[ 0 5 3 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end //: switch g3 (w3) @(670,225) /sn:0 /w:[ 0 ] /st:1 //: comment g13 /dolink:0 /link:"" @(25,45) /anc:1 //: /line:"1) Clicca sull'icona del \"Logic analyzer\" nella barra di strumenti," //: /line:"o seleziona \"Begin Simulation\" nel menu \"Simulate\". Dovrebbe " //: /line:"apparire la finestra di visualizzazione del timing dei segnali." //: /line:"" //: /line:"2) Aggancia una sonda di misura sui segnali \"S\" e \"C\"" //: /line:"e sui collegamenti che escono dagli interruttori: fai doppio click" //: /line:"sui collegamenti. Nel visualizzatore di timing apparir" //: /line:"per ogni segnale." //: /line:"" //: /line:"3) Pigia pi" //: /line:"il tempo di simulazione." //: /line:"Ad ogni spazio il tempo avanza di una \"epoca\". " //: /line:"Nella terminologia di TkGate una \"epoca\" " //: /line:"" //: /line:"4) Scegli \"Options...\" dal menu \"File\" e clicca sulla selezione" //: /line:"\"Simulator\". Inserisci \"5\" nel campo \"Epoch Step Size\"; \"OK\"." //: /line:"Ora inserisci di nuovo degli spazi: ad ogni spazio la simulazione " //: /line:"avanza di 5 unit" //: /line:"" //: /line:"5) Clicca su uno degli interruttori per cambiarne il valore e fai" //: /line:"avanzare la simulazione (spazi)." //: /line:"I risultati di simulazione appaiono nella finestra dei timing." //: /line:"" //: /line:"6) Clicca e tieni premuto il tasto sinistro del mouse su qualsiasi " //: /line:"collegamento interno. Il valore trasportato dal collegamento viene" //: /line:"visualizzato in formato \"Verilog\"." //: /line:"Il primo numero indica la cardinalit" //: /line:"la lettera indica la base di numerazione (radix) e l'ultimo numero indica" //: /line:"il valore del segnale." //: /line:"Per esempio, la cifra \"1\" in \"1'b0\" indica che si tratta di un segnale " //: /line:"di un bit, la lettera \"b\" indica che il valore " //: /line:"\"0\" indica il valore del segnale." //: /line:"" //: /line:"7) Clicca sull'icona \"Play\" nella barra degli strumenti o seleziona \"Run\"" //: /line:"dal menu \"Simulate\". Il simulatore entra in modalit" //: /line:"continua. Prova a cliccare sugli interruttori del circuito." //: /line:"Ogni volta che commuti, il simulatore ricalcola il circuito finch" //: /line:"uscite ritornano stabili." //: /line:"L'icona \"Pause\" rimette il simulatore in modalit" //: /line:"" //: /line:"8) Per terminare la simulazione seleziona \"Stop\" nella barra degli" //: /line:"strumenti o \"End Simulation\" nel \"Simulate\"." //: /end nand g2 (.I0(w4), .I1(w5), .Z(w6)); //: @(668,326) /sn:0 /w:[ 9 7 1 ] //: switch g1 (w5) @(552,288) /sn:0 /w:[ 0 ] /st:0 //: joint g11 (w1) @(704, 263) /w:[ 1 -1 2 4 ] //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end led g28 (.I(w4)); //: @(586,220) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (w3) @(709, 258) /w:[ 6 5 -1 8 ] //: joint g27 (w3) @(709, 225) /w:[ -1 2 1 4 ] //: joint g6 (w5) @(609, 288) /w:[ -1 4 3 6 ] nand g9 (.I0(w1), .I1(w3), .Z(w0)); //: @(707,295) /sn:0 /R:3 /w:[ 5 9 1 ] xor g7 (.I0(w3), .I1(w1), .Z(S)); //: @(760,261) /sn:0 /w:[ 7 0 0 ] //: joint g31 (w4) @(586, 240) /w:[ 3 4 6 -1 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" led g29 (.I(w5)); //: @(587,269) /sn:0 /w:[ 9 ] /type:0 led g25 (.I(C)); //: @(798,305) /sn:0 /w:[ 0 ] /type:0 //: comment g17 /dolink:0 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: joint g5 (w4) @(618, 260) /w:[ 1 2 -1 8 ] //: comment g14 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end //: comment g21 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end //: comment g24 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end //: comment g23 /dolink:0 /link:"" @(605,130) /sn:0 /anc:1 //: /line:"->" //: /end led g26 (.I(w3)); //: @(709,207) /sn:0 /w:[ 3 ] /type:0 //: switch g0 (w4) @(554,240) /sn:0 /w:[ 7 ] /st:1 //: comment g22 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end led g18 (.I(S)); //: @(795,244) /sn:0 /w:[ 1 ] /type:0 //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"Questo tutorial introduce alla simulazione di circuiti combinatori in TkGate." //: /line:"" //: /end //: joint g30 (w5) @(587, 288) /w:[ 2 8 1 -1 ] endmodule tkgate-2.0-b10/locale/it/tutorials.18/edit1_tut.v000644 001751 001751 00000016077 10152673133 022243 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w7; //: /sn:0 {0}(682,363)(697,363)(697,375){1} wire s0; //: {0}(750,310)(780,310){1} wire w4; //: /sn:0 {0}(702,345)(702,375){1} wire c0; //: {0}(598,268)(704,268)(704,310){1} //: {2}(706,312)(729,312){3} //: {4}(704,314)(704,324){5} wire c1; //: {0}(700,396)(700,433){1} //: {2}(702,435)(725,435){3} //: {4}(700,437)(700,447){5} wire a1; //: {0}(598,427)(638,427){1} //: {2}(642,427)(650,427){3} //: {4}(640,429)(640,483)(657,483){5} wire s1; //: /dp:1 {0}(746,433)(781,433){1} wire w8; //: /sn:0 {0}(678,486)(693,486)(693,498){1} wire b1; //: {0}(598,462)(632,462){1} //: {2}(634,460)(634,432)(650,432){3} //: {4}(634,464)(634,488)(657,488){5} wire a0; //: /dp:1 {0}(598,304)(642,304){1} //: {2}(646,304)(654,304){3} //: {4}(644,306)(644,360)(661,360){5} wire b0; //: /dp:1 {0}(598,339)(636,339){1} //: {2}(638,337)(638,309)(654,309){3} //: {4}(638,341)(638,365)(661,365){5} wire c2; //: {0}(783,530)(696,530)(696,519){1} wire w10; //: /sn:0 {0}(725,430)(697,430){1} //: {2}(693,430)(671,430){3} //: {4}(695,432)(695,447){5} wire w5; //: /sn:0 {0}(698,468)(698,498){1} wire w9; //: /sn:0 {0}(729,307)(701,307){1} //: {2}(697,307)(675,307){3} //: {4}(699,309)(699,324){5} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end nand g4 (.I0(w8), .I1(w5), .Z(c2)); //: @(696,509) /sn:0 /R:3 /w:[ 1 1 1 ] //: joint g8 (c1) @(700, 435) /w:[ 2 1 -1 4 ] //: comment g3 /dolink:0 /link:"" @(28,262) /anc:1 //: /line:"5) Nel menu \"Tool\" selziona \"Bit Width\": il puntatore diventa " //: /line:"un cavo piatto." //: /line:"In basso a destra della finestra principale appare un campo di scrittura " //: /line:"con la dicitura \"Bits:\". Clicca sul campo e inserisci un numero" //: /line:"compreso fra 1 e 32. Se clicci ora su un collegamento, questo diventa un " //: /line:"bus della larghezza indicata." //: /line:"" //: /line:"6) Doppio click su un collegamento apre un formulario con le sue" //: /line:"proprietà: puoi cambiare il nome del segnale, renderlo visibile" //: /line:"o impostare la larghezza (numero di bit) del collegamento." //: /line:"Lo stesso formulario può essere ottenuto dal menu popup che appare" //: /line:"cliccando con il tasto destro sul collegamento." //: /line:"" //: /line:"7) Apri il menu \"Tool\" e seleziona \"Move/Connect\" per tornare al " //: /line:"cursore di edizione base." //: /line:"Ora clicca doppio (o clicca con il tasto destro e seleziona " //: /line:"\"Properties...\") su una porta XOR. Nel formulario che appare" //: /line:"puoi cambiare il nome della porta, renderlo visibile (cancella" //: /line:"l'opzione \"hide\"), aggiungere o eliminare ingressi." //: /line:"" //: /line:"8) Clicca con il tasto destro su una porta e attiva l'opzione" //: /line:"\"Anchor\". Ora prova a spostare la porta (non dovrebbe spostarsi). " //: /line:"Questa opzione può essere usata per evitare di spostare accidentalmente" //: /line:"oggetti che vuoi rimangano in una posizione fissa." //: /end //: comment g13 /dolink:0 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end xor g34 (.I0(w10), .I1(c1), .Z(s1)); //: @(736,433) /sn:0 /w:[ 0 3 0 ] led g37 (.I(s0)); //: @(787,310) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 /dolink:0 /link:"" @(29,38) /anc:1 //: /line:"1) Clicca su una porta logica con il tasto sinistro del mouse e trascinala" //: /line:"in una nuova posizione. Osserva come i fili si muovono con la porta." //: /line:"" //: /line:"2) Nel menu \"Tool\" seleziona \"Cut Wire\": il puntatore assume la forma" //: /line:"di un tronchesino." //: /line:"Per tagliare un filo clicca con il tronchesino sullo stesso. Segmenti flottanti" //: /line:"o segmanti collegati ad una giunzione verranno eliminati automaticamente." //: /line:"Puoi accedere alle opzioni del menu \"Tool\" attraverso il menu popup che" //: /line:"ottieni cliccando con il tasto destro del mouse in campo libero." //: /line:"" //: /line:"3) Nel menu \"Tool\" seleziona \"Invert\"." //: /line:"Clicca vicino ad un ingresso o un'uscita di una porta per inserire un inverter." //: /line:"" //: /line:"4) Nel menu \"Tool\" seleziona \"Delete Gate\": appare un estrattore di IC." //: /line:"Se clicchi su una porta con l'estrattore, questa viene cancellata. " //: /line:"La cancellazione può avvenire anche selezionando la/le porte" //: /line:"da cancellare e usando il tasto \"Delete\" o cliccando con il tasto destro" //: /line:"e selezionando \"Delete\"." //: /end nand g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(700,386) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: switch g11 (a1) @(581,427) /sn:0 /w:[ 0 ] /st:0 nand g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(672,363) /sn:0 /w:[ 5 5 0 ] //: joint g10 (a1) @(640, 427) /w:[ 2 -1 1 4 ] //: joint g32 (w9) @(699, 307) /w:[ 1 -1 2 4 ] //: switch g27 (c0) @(581,268) /sn:0 /w:[ 0 ] /st:0 led g19 (.I(s1)); //: @(788,433) /sn:0 /R:3 /w:[ 1 ] /type:0 nand g6 (.I0(a1), .I1(b1), .Z(w8)); //: @(668,486) /sn:0 /w:[ 5 5 0 ] //: joint g38 (b1) @(634, 462) /w:[ -1 2 1 4 ] //: joint g7 (w10) @(695, 430) /w:[ 1 -1 2 4 ] nand g9 (.I0(w10), .I1(c1), .Z(w5)); //: @(698,458) /sn:0 /R:3 /w:[ 5 5 0 ] nand g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(702,335) /sn:0 /R:3 /w:[ 5 5 0 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" led g39 (.I(c2)); //: @(790,530) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g29 (a0) @(644, 304) /w:[ 2 -1 1 4 ] //: switch g25 (a0) @(581,304) /sn:0 /w:[ 0 ] /st:0 //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: frame g5 @(550,216) /sn:0 /wi:266 /ht:355 /tx:"Modifica questo circuito" //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end xor g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(740,310) /sn:0 /w:[ 0 3 0 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: switch g36 (b1) @(581,462) /sn:0 /w:[ 0 ] /st:0 xor g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(665,307) /sn:0 /w:[ 3 3 3 ] //: switch g26 (b0) @(581,339) /sn:0 /w:[ 0 ] /st:0 //: comment g0 /dolink:0 /link:"" @(8,10) /anc:1 //: /line:"Questo tutorial introduce alle funzioni base per l'edizione di circuiti con TkGate." //: /end //: comment g22 /dolink:0 /link:"" @(605,70) /sn:0 /anc:1 //: /line:"->" //: /end xor g35 (.I0(a1), .I1(b1), .Z(w10)); //: @(661,430) /sn:0 /w:[ 3 3 3 ] //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end //: joint g33 (c0) @(704, 312) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(638, 339) /w:[ -1 2 1 4 ] endmodule tkgate-2.0-b10/locale/it/tutorials.18/module_tut.v000644 001751 001751 00000016051 10152673133 022512 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module foo(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 //: /line:"Collegamenti" //: /end //: comment g3 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 //: /line:"Manipolazioni base" //: /end //: frame g1 @(409,199) /sn:0 /wi:404 /ht:316 /tx:"Inserisci i riferimenti alle porte qui" //: comment g16 /dolink:0 /link:"@T/module_tut.v" @(630,115) /sn:0 //: /line:"Moduli" //: /end //: frame g15 @(600,25) /sn:0 /wi:213 /ht:149 /tx:"Tutorials" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 //: /line:"Creare un circuito" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 //: /line:"Simulazione combinatoria" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 //: /line:"Simulazione sequenziale" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 //: /line:"Gruppi di oggetti" //: /end //: comment g22 /dolink:0 /link:"" @(605,115) /sn:0 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(26,29) /anc:1 //: /line:"10) Questa è la definizione del modulo \"foo\"." //: /line:"Nell'elenco in basso a sinistra della finestra principale ritrovi i nomi " //: /line:"delle porte che hai definito nell'istanza del modulo." //: /line:"Per creare riferimenti alle porte dei moduli all'interno degli stessi, " //: /line:"clicca per posizionare un punto di riferimento nell'area di disegno e " //: /line:"seleziona \"Module Input\", \"Module Output\" o \"Module InOut\" dal sottomenu " //: /line:"\"Module\" in \"Make\"." //: /line:"Appare un formulario dove è possibile inserire il nome della porta." //: /line:"Inserisci uno dei nomi delle porte del modulo e seleziona \"OK\"." //: /line:"" //: /line:"11) Puoi anche creare la definizione di un nuovo modulo" //: /line:"senza crearne un'istanza se selezioni \"New...\" " //: /line:"nel menu \"Module\". " //: /line:"Apparirà  un formulario dove potrai inserire il nome " //: /line:"del nuovo modulo. Prova a inserire \"bar\" " //: /line:"e seleziona \"OK\" (tasto \"return\")." //: /line:"" //: /line:"12) Puoi cambiare il nome, copiare e cancellare" //: /line:"moduli usando gli altri comandi del menu \"Module\"." //: /line:"" //: /line:"13) Se hai aperto questo modulo con un doppio click" //: /line:"nell'elenco dei moduli, puoi tornare nel modulo " //: /line:"principale cliccando doppio ora su \"main\"." //: /line:"" //: /line:"Se hai aperto \"foo\" con il comando \"Open\", puoi " //: /line:"tornare al livello superiore selezionando \"Close\"" //: /line:"nel menu \"Module\" o cliccando doppio su \"main\"." //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 //: /line:"Introduzione a TkGate" //: /end endmodule module main; //: root_module //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end //: comment g3 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end //: frame g2 @(477,189) /sn:0 /wi:330 /ht:350 /tx:"Spazio per creare un'istanza del modulo" //: comment g1 /dolink:0 /link:"" @(11,34) /anc:1 //: /line:"1) Clicca il tasto sinistro al centro dell'area riservata per il disegno" //: /line:"in questo tutorial." //: /line:"Seleziona \"Module Instance\" dal sottomenu \"Module\" di \"Make\": appare un blocco" //: /line:"(sarà  un'istanza del nostro modulo) e si apre un formulario con la rubrica" //: /line:"\"Function\" attivata." //: /line:"Inserisci il nome \"foo\" in minuscolo e seleziona \"OK\"." //: /line:"" //: /line:"2) Premi il tasto sinistro del mouse sull'angolo in basso a destra dell'istanza" //: /line:"e trascina verso il basso e a destra per ottenere un box più grande." //: /line:"" //: /end //: comment g16 /dolink:0 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: comment g6 /dolink:0 /link:"" @(10,160) //: /line:"3) Clicca con il tasto destro sul bordo sinistro del blocco e " //: /line:"seleziona \"Add Input\" dal popup. Appare un formulario con la " //: /line:"rubrica \"Port Name\" attiva. Inserisci \"A\" e seleziona \"OK\"." //: /line:"Ripeti la procedura e aggiungi gli ingressi \"B\" and \"C\" dallo " //: /line:"stesso lato." //: /line:"Ripeti tutto selezionando ora \"Add Output\" per delle porte con" //: /line:"i nomi \"X\", \"Y\" e \"Z\" sul lato destro del blocco." //: /line:"" //: /line:"4) Clicca su una delle porte che hai aggiunto: la puoi spostare" //: /line:"lungo il lato a cui è agganciata; puoi aggiustarne la" //: /line:"posizione." //: /line:"" //: /line:"5) Clicca con il tasto destro vicino ad una delle porte " //: /line:"e seleziona \"Change Type\" dal popup. Se ripeti questa " //: /line:"operazione la direzione della porta cambia in modo ciclico " //: /line:"fra i tre tipi di porta previsti: input, output e inout. " //: /line:"" //: /line:"6) Seleziona \"Cut Wire\" dal menu \"Tool\" e clicca sulla porta \"Z\"" //: /line:"in prossimità  del bordo del blocco. La porta viene cancellata." //: /line:"" //: /line:"7) Seleziona \"Move/Connect\" dal menu \"Tool\" per tornare nella" //: /line:"modalità  base di edizione. Seleziona un'altra posizione nell'area" //: /line:"di disegno e crea una nuova istanza del modulo \"foo\". Nota che" //: /line:"le informazioni sulle porte e sulla dimensione del blocco non" //: /line:"vengono riportate." //: /line:"" //: /line:"8) Seleziona l'istanza di \"foo\" a cui hai aggiunto le porte" //: /line:"e attiva la voce \"Set Interface\" del menu \"Module\"." //: /line:"Crea un'altra istanza del modulo \"foo\". Ora il modulo \"foo\" " //: /line:"viene riprodotto con le sue porte e la dimensione " //: /line:"che gli hai dato." //: /line:"" //: /line:"9) \"Apri\" il modulo \"foo\": seleziona una delle istanze e scegli" //: /line:"\"Open\" dal menu \"Module\" (oppure clicca doppio su \"foo\" nell'elenco" //: /line:"di moduli a sinistra della finestra principale)." //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: comment g22 /dolink:0 /link:"" @(605,115) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(22,9) /anc:1 //: /line:"Questo tutorial descrive come creare ed usare moduli in TkGate." //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end endmodule tkgate-2.0-b10/locale/it/tutorials.18/edit2_tut.v000644 001751 001751 00000007171 10152673133 022237 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w3; //: /sn:0 {0}(744,264)(679,264){1} wire w1; //: /sn:0 {0}(744,259)(709,259)(709,224)(679,224){1} wire w2; //: /sn:0 {0}(685,302)(679,302){1} wire w5; //: /sn:0 {0}(765,261)(775,261){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end and g4 (.I0(w1), .I1(w3), .Z(w5)); //: @(755,261) /sn:0 /w:[ 0 0 0 ] //: switch g3 (w2) @(662,302) /sn:0 /w:[ 1 ] /st:0 //: switch g2 (w3) @(662,264) /sn:0 /w:[ 1 ] /st:0 //: switch g1 (w1) @(662,224) /sn:0 /w:[ 1 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: frame g11 @(434,347) /sn:0 /anc:1 /wi:373 /ht:230 /tx:"Copia qui" //: frame g10 @(22,347) /sn:0 /anc:1 /wi:394 /ht:227 /tx:"Trascina qui" //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end //: comment g5 /dolink:0 /link:"" @(38,36) /anc:1 //: /line:"1) Premi il tasto sinistro del mouse a sinistra sopra i tre interruttori" //: /line:"e la porta AND. Tieni premuto il tasto e trascina verso il basso a destra" //: /line:"in modo che il rettangolo di selezione che appare circondi tutto " //: /line:"il circuito. Rilascia il tasto. Gli interruttori e la porta logica risultano" //: /line:"evidenziati per indicare che sono selezionati." //: /line:"" //: /line:"2) Premi il tasto sinistro del mouse sopra una delle porte selezionate e" //: /line:"trascina. Tutto il gruppo selezionato segue: spostalo fino nel riquadro" //: /line:"etichettato con \"Trascina qui\". Clicca in campo libero (dove non ci sono né" //: /line:"porte né collegamenti) per disattivare la selezione." //: /line:"" //: /line:"3) Seleziona la AND, entra nel menu \"Gate\" e seleziona \"Add Input\". " //: /line:"Alla porta viene aggiunto un ingresso che ora puoi collegare al terzo interruttore." //: /line:"" //: /line:"4) Segui di nuovo le istruzioni del punto 1 per selezionare il circuito." //: /line:"Nel menu \"Edit\" seleziona \"Copy\": il gruppo di oggetti selezionati viene copiato " //: /line:"nel buffer di taglio." //: /line:"Clicca ora con il tasto sinistro al centro del riquadro etichettato \"Copia qui\" e " //: /line:"seleziona \"Paste\" dal menu \"Edit\". Verrà  creata una copia delle porte selezionate." //: /line:"È possibile eliminare un gruppo di oggetti selezionati con il tasto \"Delete\"." //: /line:"" //: /line:"5) Puoi creare un gruppo di oggetti cliccando su ogni oggetto che vuoi nel gruppo" //: /line:"mentre mantieni pigiato il tasto ." //: /line:"" //: /end //: comment g21 /dolink:0 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: comment g22 /dolink:0 /link:"" @(605,85) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(26,17) /anc:1 //: /line:"Questo tutorial introduce alle operazioni sui gruppi di oggetti." //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end //: comment g12 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end endmodule tkgate-2.0-b10/locale/it/tutorials.18/seqsim_tut.v000644 001751 001751 00000014107 10152673133 022526 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w0; //: /sn:0 /dp:1 {0}(707,320)(730,320)(730,335){1} supply0 w3; //: /sn:0 {0}(705,275)(705,265)(692,265){1} wire [7:0] w7; //: /sn:0 {0}(652,225)(652,251){1} wire w4; //: /sn:0 /dp:1 {0}(707,310)(718,310)(718,298)(728,298){1} wire [7:0] w2; //: /sn:0 /dp:1 {0}(668,305)(668,280){1} wire ck; //: /dp:1 {0}(631,315)(566,315){1} wire [7:0] reg_out; //: {0}(668,326)(668,368)(724,368){1} //: {2}(728,368)(784,368)(784,241)(684,241)(684,251){3} //: {4}(726,370)(726,400){5} wire w9; //: /sn:0 {0}(644,265)(634,265){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Collegamenti" //: /end //: supply0 g4 (w0) @(730,341) /sn:0 /w:[ 1 ] //: joint g8 (reg_out) @(726, 368) /w:[ 2 -1 1 4 ] //: comment g13 /dolink:0 /link:"" @(24,45) /anc:1 //: /line:"1) Clicca sull'icona del \"Logic Analyzer\" nella barra degli strumenti" //: /line:"o seleziona \"Begin Simulation\" dal menu \"Simulate\". Dovrebbe apparire" //: /line:"la finestra dei timing." //: /line:"" //: /line:"2) Aggancia una sonda alla linea del clock (indicata con il nome \"ck\")" //: /line:"e sull'uscita del registro (\"reg_out\") cliccando doppio sul rispettivo" //: /line:"collegamento. Nella finestra dei timing appare una traccia per ogni " //: /line:"segnale." //: /line:"" //: /line:"3) Inserisci spazi (tastiera) per far avanzare il tempo di simulazione." //: /line:"Ogni spazio fa avanzare il tempo di simulazione di un multiplo di epoche." //: /line:"Una \"epoca\" corrisponde alla risoluzione del simulatore (l'unità  di tempo" //: /line:"minima elaborata)." //: /line:"Vedi il tutorial sulla simulazione combinatoria per informazioni sulla " //: /line:"possibilità  di impostare il passo di simulazione (multipli di epoche)." //: /line:"" //: /line:"4) Puoi far avanzare la simulazione di un ciclo di clock inserendo " //: /line:"il carattere Tab o selezionando \"Step Cycle\" dal menu \"Simulate\". " //: /line:"La simulazione avanzerà  fino al primo fianco positivo di uno " //: /line:"qualsiasi dei segnali di clock del circuito (il primo che si verifica), " //: /line:"più un certo numero di epoche, dette di \"overstep\". " //: /line:"Il tempo di overstep è previsto per dare ai registri il " //: /line:"tempo per acquisire i nuovi valori prima di fermare" //: /line:"la simulazione. Puoi cambiare la quantità  di overstep, " //: /line:"il numero di cicli di avanzamento, o selezionare un solo" //: /line:"segnale di clock per il passo di simulazione usando il formulario " //: /line:"di opzioni (File - Options - ...)." //: /line:"" //: /line:"5) In questo esempio, imposta l'interruttore dell'entrata CLR su \"off\"" //: /line:"e fai avanzare la simulazione di un ciclo per azzerare il registro." //: /line:"Poi commuta su \"on\" e avanza alcuni cicli di clock per far avanzare il " //: /line:"contatore." //: /line:"" //: /line:"6) Clicca sull'interruttore a 8 vie (\"dip switch\"): si apre un " //: /line:"formulario che permette di inserire il valore dato dalla posizione" //: /line:"dei singoli contatti. Inserisci un valore in base esadecimale e " //: /line:"clicca \"Apply\" per cambiare il passo di conteggio." //: /line:"" //: /line:"7) Se clicchi e tieni pigiato il tasto su un collegamento qualsiasi, " //: /line:"potrai vedere il valore trasportato dal segnale." //: /line:"" //: /line:"8) Clicca sull'icona \"Play\" o seleziona \"Run\" dal menu \"Simulate\". " //: /line:"Attivi così la modalità  di simulazione continua." //: /line:"Con circuiti sequenziali il simulatore continua a calcolare finchè " //: /line:"non premi il pulsante \"Pause\". " //: /line:"Puoi cambiare il valore degli interruttori mentre la simulazione " //: /line:"è in atto." //: /end //: switch g3 (w4) @(746,298) /sn:0 /R:2 /w:[ 1 ] /st:1 register g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(668,315) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Manipolazioni base" //: /end //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Moduli" //: /end //: comment g10 /dolink:0 /link:"" @(528,451) /sn:0 /R:2 /anc:1 //: /line:"9) Puoi spostarti nelle tracce di simulazione" //: /line:"usando la barra di scrolling o cliccando" //: /line:"sulle tracce e trascinando l'immagine." //: /line:"Se clicchi tenendo pigiato il tasto " //: /line:"o otterrai l'azione di zoom in, " //: /line:"rispettivamente zoom out." //: /line:"Se trascini la barra di scrolling all'estremità " //: /line:"destra, la finestra mostrerà  continuamente " //: /line:"gli ultimi valori calcolati." //: /line:"" //: /end //: dip g6 (w7) @(652,215) /sn:0 /w:[ 0 ] /st:1 led g7 (.I(reg_out)); //: @(726,407) /sn:0 /R:2 /w:[ 5 ] /type:2 //: supply0 g9 (w3) @(705,281) /sn:0 /w:[ 0 ] //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorials" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Creare un circuito" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Simulazione combinatoria" //: /end //: comment g14 /dolink:0 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Simulazione sequenziale" //: /end add g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(668,267) /sn:0 /w:[ 1 3 1 1 0 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Gruppi di oggetti" //: /end //: comment g22 /dolink:0 /link:"" @(605,145) /sn:0 /anc:1 //: /line:"->" //: /end clock g0 (.Z(ck)); //: @(553,315) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"Introduzione a TkGate" //: /end //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"Questo tutorial introduce alla simulazione di circuiti sequenziali in TkGate." //: /line:"" //: /end endmodule tkgate-2.0-b10/locale/it/examples.18/ex1000777 001751 001751 00000000000 11145151105 020342 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18/ex2000777 001751 001751 00000000000 11145151105 020343 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18/ex3000777 001751 001751 00000000000 11145151105 020344 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18/ex4000777 001751 001751 00000000000 11145151105 020345 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18/ex5000777 001751 001751 00000000000 11145151105 020346 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/it/examples.18/index.v000644 001751 001751 00000004351 10521363130 021221 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "index.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g4 @(553,317) /sn:0 /anc:1 //: /line:"" //: /line:"This example uses TkGate's Viritual" //: /line:"Peripheral Device (VPD) mechanism to" //: /line:"create an interactive \"Coke Machine\"" //: /line:"that can be controlled by a user circuit." //: /line:"Only the coke machine device itself is" //: /line:"included. Can you build a controller" //: /line:"for it?" //: /line:"" //: /end //: comment g3 @(32,317) /sn:0 /anc:1 //: /line:"" //: /line:"

Transistor-Level FF

" //: /line:"A flop-flop implemented using" //: /line:"nmos and pmos devices." //: /line:"" //: /end //: comment g2 @(551,30) /sn:0 /anc:1 //: /line:"" //: /line:"

8-Bit Counter

" //: /line:"A counter implemented using the" //: /line:"register and adder devices." //: /end //: comment g1 @(299,30) /sn:0 /anc:1 //: /line:"" //: /line:"

3-Bit Counter

" //: /line:"A 3-bitcounter implemented using" //: /line:"three single-bit D-flip-flops." //: /end //: comment g6 @(20,552) /sn:0 //: /line:"Go back to the TkGate main page" //: /end //: comment g5 @(301,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Menagerie CPU

" //: /line:"A simple microcode-based CPU that" //: /line:"will play the \"Animals\" game on a" //: /line:"TTY device when simulated." //: /end //: comment g0 @(32,30) /sn:0 /anc:1 //: /line:"

" //: /line:"Combinational Logic

" //: /line:"A simple 3-bit adder that you" //: /line:"simulate. Push the play button" //: /line:"then click on the switches and" //: /line:"watch how the LEDs change." //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/it/examples.18/ex5/x-menagerie.mem000644 001751 001751 00000020634 10152673133 023336 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 40/ f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 48/ f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 50/ f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 58/ f82000 f82000 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fdf956 fbebf6 e7cfb4 7ffefe0 a0/ 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 a8/ f7cfb4 2fffd40 fdf956 fbebf6 f7ef74 ffe7e0 57eff4 ffefe0 b0/ ffe7e0 ffefe0 21f7cfb4 fffd40 fdf956 f7ef74 ffe7e0 ffefe0 b8/ 2fffd40 fdf956 fbebf6 f7cfb4 2fffd40 fdf956 fbebf6 f7cfb4 c0/ 15ffefe0 ffefe0 memory iunit.map 3e/ c0 0/ 9 2/ 1b 1d a0/ 2b 22 2d 2f 68/ b d b d 60/ 12 15 78/ 12 15 70/ 12 15 50/ b d 80/ 49 31 4b 4d 4/ 4f 84/ 5a 61 58 59 f0/ 6d 75 7a 84 f8/ 8c b2 a4 a6 97 bc a2 a0 e0/ 6b 70 7e 88 e8/ 90 a8 a3 a5 9b b8 a1 9f memory memory.m1 100/ e1 f0 0 0 e1 e0 0 0 108/ 81 0 0 0 12 1 bd 0 110/ e 1 e1 d0 f6 7 85 0 118/ 89 6 81 0 0 0 4e 4 120/ 69 f0 2 0 85 0 64 0 128/ 81 0 0 0 26 4 69 f0 130/ 2 0 ed 0 7a 6 7c 6 138/ ed 0 78 6 1 0 85 0 140/ 9f 6 81 0 0 0 4e 4 148/ 69 f0 2 0 e3 10 78 6 150/ 84 10 85 0 d8 6 81 0 158/ 0 0 4e 4 69 f0 4 0 160/ e3 10 7a 6 84 10 81 0 168/ 0 0 7a 1 69 f0 2 0 170/ ec 1 7a 6 bd 0 3e 1 178/ 4 0 6b f0 2 0 e3 1e 180/ 4 0 ec e1 fe ff e3 21 188/ 0 0 3 20 0 0 a1 0 190/ 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022546 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 //: script "menagerie.gss" module MEMORY(DATA, spc, _ldpc, _wrt, _rd, _ldmdr, _ldhmdr, _rdmdr, _rdpc, _CLR, _incmar, _ldmar, CK, _incpc); //: interface /sz:(125, 353) /bd:[ Ti0>CK(33/125) Ti1>_CLR(83/125) Bi0>DATA[15:0](60/125) Ri0>_ldpc(25/353) Ri1>_ldmar(42/353) Ri2>_ldmdr(57/353) Ri3>_incpc(73/353) Ri4>_rdmdr(88/353) Ri5>_wrt(104/353) Ri6>_rd(120/353) Ri7>spc(136/353) Ri8>_ldhmdr(155/353) Ri9>_rdpc(171/353) Ri10>_incmar(186/353) ] input _rdpc; //: /sn:0 {0}(259,285)(270,285)(270,306){1} input _rd; //: /sn:0 {0}(671,557)(671,614){1} //: {2}(673,616)(708,616)(708,273)(740,273){3} //: {4}(669,616)(512,616){5} //: {6}(510,614)(510,579){7} //: {8}(508,616)(482,616){9} supply0 [5:0] w16; //: /sn:0 {0}(545,861)(545,840){1} input CK; //: /sn:0 /dp:1 {0}(753,813)(742,813)(742,833)(618,833)(618,815){1} //: {2}(620,813)(631,813){3} //: {4}(616,813)(524,813)(524,438){5} //: {6}(526,436)(641,436)(641,334)(726,334){7} //: {8}(522,436)(130,436){9} //: {10}(128,434)(128,335){11} //: {12}(130,333)(321,333)(321,307)(326,307){13} //: {14}(128,331)(128,253)(151,253){15} //: {16}(126,436)(62,436){17} supply0 [7:0] w3; //: /sn:0 {0}(683,269)(683,251)(662,251){1} input _CLR; //: /sn:0 {0}(512,218)(512,201){1} //: {2}(514,199)(844,199)(844,327){3} //: {4}(842,329)(802,329){5} //: {6}(844,331)(844,770){7} //: {8}(842,772)(716,772)(716,808)(707,808){9} //: {10}(844,774)(844,808)(829,808){11} //: {12}(510,199)(409,199){13} //: {14}(405,199)(263,199)(263,248)(227,248){15} //: {16}(407,201)(407,302)(402,302){17} input _ldhmdr; //: /sn:0 {0}(673,103)(709,103){1} //: {2}(713,103)(871,103)(871,269){3} //: {4}(711,105)(711,137){5} input _wrt; //: /sn:0 {0}(691,706)(424,706){1} //: {2}(422,704)(422,510){3} //: {4}(424,508)(454,508){5} //: {6}(420,508)(399,508){7} //: {8}(422,708)(422,758)(692,758){9} input _ldmar; //: /sn:0 {0}(458,247)(458,314)(438,314){1} supply0 [15:0] w21; //: /sn:0 {0}(220,59)(220,42)(194,42)(194,69){1} input _ldpc; //: /sn:0 {0}(233,131)(217,131)(217,152)(148,152){1} //: {2}(144,152)(131,152){3} //: {4}(146,154)(146,204)(165,204){5} inout [15:0] DATA; //: /sn:0 /dp:13 {0}(278,311)(297,311)(297,213)(371,213){1} //: {2}(373,211)(373,167){3} //: {4}(375,165)(508,165){5} //: {6}(512,165)(547,165){7} //: {8}(551,165)(568,165){9} //: {10}(549,167)(549,246)(616,246){11} //: {12}(510,163)(510,134){13} //: {14}(371,165)(198,165)(198,188){15} //: {16}(373,215)(373,248){17} supply0 [7:0] w24; //: /sn:0 {0}(595,538)(595,523){1} supply1 w20; //: /sn:0 {0}(241,70)(241,83)(202,83){1} supply0 w23; //: /sn:0 {0}(829,818)(844,818)(844,836){1} supply0 [7:0] w1; //: /sn:0 {0}(800,724)(800,677)(825,677)(825,687){1} input _rdmdr; //: /sn:0 {0}(624,284)(624,251){1} input _incpc; //: /sn:0 {0}(233,126)(133,126){1} input spc; //: /sn:0 {0}(251,380)(207,380){1} supply0 w17; //: /sn:0 {0}(496,579)(496,592){1} input _ldmdr; //: /sn:0 /dp:1 {0}(876,269)(876,80)(673,80){1} input _incmar; //: /sn:0 {0}(438,309)(448,309)(448,281)(327,281){1} //: {2}(325,279)(325,266){3} //: {4}(327,264)(340,264){5} //: {6}(325,262)(325,243){7} //: {8}(325,283)(325,293)(313,293)(313,326)(223,326)(223,411)(96,411)(96,383){9} wire [15:0] w6; //: /sn:0 {0}(162,69)(162,47)(70,47)(70,360)(83,360){1} wire [7:0] mdrin; //: /sn:0 {0}(520,552)(557,552){1} //: {2}(561,552)(663,552){3} //: {4}(559,550)(559,523){5} wire w46; //: /sn:0 {0}(402,312)(417,312){1} wire w14; //: /sn:0 {0}(254,129)(272,129)(272,258)(227,258){1} wire w15; //: /sn:0 {0}(691,711)(645,711){1} //: {2}(643,709)(643,672){3} //: {4}(641,711)(436,711){5} //: {6}(434,709)(434,512)(454,512){7} //: {8}(432,711)(365,711){9} wire [15:0] w19; //: /sn:0 {0}(188,217)(188,243){1} wire [15:0] w4; //: /sn:0 {0}(584,165)(614,165){1} wire [15:0] w38; //: /sn:0 {0}(210,713)(300,713){1} wire [15:0] PC; //: /sn:0 {0}(188,264)(188,309){1} //: {2}(190,311)(262,311){3} //: {4}(188,313)(188,348){5} //: {6}(190,350)(264,350)(264,364){7} //: {8}(186,350)(112,350){9} wire w; //: /sn:0 {0}(802,339)(874,339)(874,290){1} wire DTR; //: /sn:0 {0}(451,982)(565,982)(565,840){1} wire w37; //: /sn:0 {0}(713,761)(722,761)(722,818)(707,818){1} wire [7:0] w34; //: /sn:0 {0}(555,834)(555,668)(571,668)(571,523){1} wire [15:0] w43; //: /sn:0 {0}(363,297)(363,277){1} wire RTS; //: /sn:0 {0}(451,958)(555,958)(555,840){1} wire w31; //: /sn:0 {0}(366,763)(446,763){1} //: {2}(450,763)(631,763){3} //: {4}(635,763)(692,763){5} //: {6}(633,761)(633,672){7} //: {8}(448,761)(448,515)(454,515){9} wire [15:0] w28; //: /sn:0 {0}(344,711)(321,711){1} wire DSR; //: /sn:0 {0}(451,974)(800,974)(800,858){1} wire [7:0] w36; //: /sn:0 {0}(790,753)(790,803){1} wire CTS; //: /sn:0 {0}(451,966)(790,966)(790,858){1} wire [7:0] w25; //: /sn:0 {0}(763,286)(763,324){1} wire [15:0] w40; //: /sn:0 {0}(212,765)(301,765){1} wire [5:0] w35; //: /sn:0 {0}(780,858)(780,881)(760,881){1} wire [7:0] w8; //: /sn:0 {0}(620,170)(695,170){1} wire [15:0] w18; //: /sn:0 {0}(274,393)(274,550){1} //: {2}(276,552)(485,552){3} //: {4}(274,554)(274,706){5} //: {6}(276,708)(300,708){7} //: {8}(274,710)(274,760)(301,760){9} wire [15:0] w30; //: /sn:0 {0}(345,763)(322,763){1} wire w22; //: /sn:0 {0}(154,83)(144,83){1} wire [7:0] RD; //: /sn:0 {0}(668,824)(668,949)(451,949){1} wire [7:0] mdr; //: /sn:0 {0}(780,724)(780,676)(724,676){1} //: {2}(722,674)(722,552)(699,552){3} //: {4}(697,550)(697,379){5} //: {6}(699,377)(763,377)(763,345){7} //: {8}(697,375)(697,241)(662,241){9} //: {10}(695,552)(679,552){11} //: {12}(720,676)(668,676)(668,803){13} wire [15:0] w2; //: /sn:0 {0}(656,246)(632,246){1} wire w11; //: /sn:0 {0}(503,529)(503,512)(475,512){1} wire [1:0] w27; //: /sn:0 {0}(600,507)(638,507)(638,666){1} wire [7:0] w13; //: /sn:0 {0}(753,257)(753,198)(577,198)(577,494){1} wire [15:0] mar; //: /sn:0 {0}(363,318)(363,349){1} //: {2}(361,351)(284,351)(284,364){3} //: {4}(363,353)(363,400)(136,400)(136,370)(112,370){5} wire [7:0] w33; //: /sn:0 {0}(790,852)(790,824){1} wire [7:0] w5; //: /sn:0 {0}(620,160)(661,160)(661,150)(695,150){1} wire [7:0] TD; //: /sn:0 {0}(451,941)(583,941)(583,523){1} wire [15:0] w9; //: /sn:0 {0}(178,188)(178,114){1} //: {2}(178,110)(178,98){3} //: {4}(180,112)(353,112)(353,248){5} wire [7:0] w42; //: /sn:0 {0}(773,257)(773,160)(724,160){1} wire w26; //: /sn:0 {0}(712,709)(745,709)(745,740)(767,740){1} //: enddecls //: joint g4 (_rd) @(510, 616) /w:[ 5 6 8 -1 ] //: inout g8 (DATA) @(510,128) /sn:0 /R:3 /w:[ 13 ] //: joint g61 (w31) @(448, 763) /w:[ 2 8 1 -1 ] //: joint g58 (_CLR) @(844, 772) /w:[ -1 7 8 10 ] register g51 (.Q(RD), .D(mdr), .EN(w37), .CLR(_CLR), .CK(CK)); //: @(668,813) /sn:0 /w:[ 0 13 1 9 3 ] //: input g37 (spc) @(205,380) /sn:0 /w:[ 1 ] //: input g34 (_ldpc) @(129,152) /sn:0 /w:[ 3 ] //: input g13 (_wrt) @(397,508) /sn:0 /w:[ 7 ] //: joint g86 (_wrt) @(422, 508) /w:[ 4 -1 6 3 ] //: joint g55 (CK) @(524, 436) /w:[ 6 -1 8 5 ] //: joint g3 (_CLR) @(512, 199) /w:[ 2 -1 12 1 ] //: comment g89 /dolink:0 /link:"" @(38,543) /sn:0 //: /line:"Questo è il bus di indirizzi" //: /line:"di memoria." //: /line:"L'indirizzo può essere dato dal" //: /line:"MAR (Memory Address Register) o " //: /line:"dal PC (Program Counter)." //: /end //: input g2 (_rd) @(480,616) /sn:0 /w:[ 9 ] //: joint g65 (mdr) @(722, 676) /w:[ 1 2 12 -1 ] //: joint g76 (w9) @(178, 112) /w:[ 2 1 4 -1 ] //: input g77 (_ldmdr) @(671,80) /sn:0 /w:[ 1 ] nand g59 (.I0(!_wrt), .I1(w31), .Z(w37)); //: @(703,761) /sn:0 /w:[ 9 5 0 ] bufif0 g72 (.Z(DATA), .I(PC), .E(_rdpc)); //: @(268,311) /sn:0 /w:[ 0 3 1 ] register PC (.Q(PC), .D(w19), .EN(w14), .CLR(_CLR), .CK(CK)); //: @(188,253) /w:[ 0 1 1 15 15 ] //: supply0 g1 (w17) @(496,598) /sn:0 /w:[ 1 ] //: joint g64 (_wrt) @(422, 706) /w:[ 1 2 -1 8 ] //: frame g16 @(110,659) /sn:0 /wi:762 /ht:347 /tx:"TTY Control" mux g11 (.I0(mdrin), .I1(w34), .I2(TD), .I3(w24), .S(w27), .Z(w13)); //: @(577,507) /sn:0 /R:2 /w:[ 5 1 1 1 0 1 ] concat g50 (.I0(DSR), .I1(CTS), .I2(w35), .Z(w33)); //: @(790,853) /sn:0 /R:1 /w:[ 1 1 0 0 ] /dr:0 add g28 (.A(w6), .B(w21), .S(w9), .CI(w20), .CO(w22)); //: @(178,85) /sn:0 /w:[ 0 1 3 1 0 ] //: joint g78 (PC) @(188, 350) /w:[ 6 5 8 -1 ] //: comment g87 /dolink:0 /link:"" @(210,776) //: /line:"Questi switches specificano" //: /line:"gli indirizzi per il registro" //: /line:"di stato e per quello dei dati" //: /line:"della tty." //: /end //: joint g10 (CK) @(128, 333) /w:[ 12 14 -1 11 ] //: joint g27 (DATA) @(373, 165) /w:[ 4 -1 14 3 ] //: joint g19 (mdr) @(697, 552) /w:[ 3 4 10 -1 ] mux g32 (.I0(w9), .I1(DATA), .S(_incmar), .Z(w43)); //: @(363,264) /sn:0 /w:[ 5 17 5 1 ] ram m1 (.A(w18), .D(mdrin), .WE(w11), .OE(_rd), .CS(w17)); //: @(503,553) /w:[ 3 0 0 7 0 ] //: joint g38 (DATA) @(549, 165) /w:[ 8 -1 7 10 ] //: input g69 (_ldhmdr) @(671,103) /sn:0 /w:[ 0 ] //: input g6 (_rdmdr) @(624,286) /sn:0 /R:1 /w:[ 0 ] //: joint g57 (_CLR) @(844, 329) /w:[ -1 3 4 6 ] register g53 (.Q(w33), .D(w36), .EN(w23), .CLR(_CLR), .CK(CK)); //: @(790,813) /sn:0 /w:[ 1 1 0 11 0 ] mux g9 (.I0(w13), .I1(w42), .S(_rd), .Z(w25)); //: @(763,273) /sn:0 /w:[ 0 0 3 0 ] bufif1 g7 (.Z(mdrin), .I(mdr), .E(_rd)); //: @(673,552) /sn:0 /R:2 /w:[ 3 11 0 ] //: joint g75 (DATA) @(373, 213) /w:[ -1 2 1 16 ] //: supply0 g20 (w3) @(683,275) /sn:0 /w:[ 0 ] concat g15 (.I0(w5), .I1(w8), .Z(w4)); //: @(615,165) /sn:0 /R:2 /w:[ 0 0 1 ] /dr:0 //: joint g71 (_ldhmdr) @(711, 103) /w:[ 2 -1 1 4 ] mux g31 (.I0(PC), .I1(mar), .S(!_incmar), .Z(w6)); //: @(96,360) /sn:0 /R:3 /w:[ 9 5 9 1 ] xor g39 (.I0(w18), .I1(w38), .Z(w28)); //: @(311,711) /sn:0 /w:[ 7 1 1 ] //: supply0 g67 (w23) @(844,842) /sn:0 /w:[ 1 ] mux g68 (.I0(w5), .I1(w8), .S(!_ldhmdr), .Z(w42)); //: @(711,160) /sn:0 /R:1 /w:[ 1 1 5 1 ] //: supply0 g48 (w16) @(545,867) /sn:0 /w:[ 0 ] //: joint g43 (w18) @(274, 552) /w:[ 2 1 -1 4 ] //: input g73 (_rdpc) @(257,285) /sn:0 /w:[ 0 ] nand g62 (.I0(!_wrt), .I1(w15), .Z(w26)); //: @(702,709) /sn:0 /w:[ 0 0 0 ] //: supply1 g29 (w20) @(252,70) /sn:0 /w:[ 0 ] mux g25 (.I0(PC), .I1(mar), .S(!spc), .Z(w18)); //: @(274,380) /sn:0 /w:[ 7 3 0 0 ] //: joint g17 (DATA) @(510, 165) /w:[ 6 12 5 -1 ] //: input g88 (_CLR) @(512,220) /sn:0 /R:1 /w:[ 0 ] //: joint g63 (w15) @(643, 711) /w:[ 1 2 4 -1 ] nor g42 (.I0(w30), .Z(w31)); //: @(356,763) /sn:0 /w:[ 0 0 ] //: joint g52 (mdr) @(697, 377) /w:[ 6 8 -1 5 ] nor g83 (.I0(!_incmar), .I1(!_ldmar), .Z(w46)); //: @(427,312) /sn:0 /R:2 /w:[ 0 1 1 ] //: joint g74 (PC) @(188, 311) /w:[ 2 1 -1 4 ] //: joint g56 (CK) @(618, 813) /w:[ 2 -1 4 1 ] //: frame g14 @(536,27) /sn:0 /wi:372 /ht:394 /tx:"MDR Control" //: joint g5 (_CLR) @(407, 199) /w:[ 13 -1 14 16 ] concat g47 (.I0(DTR), .I1(RTS), .I2(w16), .Z(w34)); //: @(555,835) /sn:0 /R:1 /w:[ 1 1 1 0 ] /dr:0 //: joint g44 (w18) @(274, 708) /w:[ 6 5 -1 8 ] //: joint g79 (mar) @(363, 351) /w:[ -1 1 2 4 ] //: input g80 (_incmar) @(325,241) /sn:0 /R:3 /w:[ 7 ] //: joint g36 (_ldpc) @(146, 152) /w:[ 1 -1 2 4 ] bufif0 g21 (.Z(DATA), .I(w2), .E(_rdmdr)); //: @(626,246) /sn:0 /R:2 /w:[ 11 1 1 ] register mdr (.Q(mdr), .D(w25), .EN(w), .CLR(_CLR), .CK(CK)); //: @(763,334) /w:[ 7 1 0 5 7 ] or g84 (.I0(_wrt), .I1(w15), .I2(w31), .Z(w11)); //: @(465,512) /sn:0 /w:[ 5 7 9 1 ] //: joint g85 (w15) @(434, 711) /w:[ 5 6 8 -1 ] //: joint g24 (CK) @(128, 436) /w:[ 9 10 16 -1 ] //: dip TTYSTATUS (w38) @(172,713) /R:1 /w:[ 0 ] /st:16 nor g41 (.I0(w28), .Z(w15)); //: @(355,711) /sn:0 /w:[ 0 9 ] //: input g23 (_ldmar) @(458,245) /sn:0 /R:3 /w:[ 0 ] //: joint g60 (w31) @(633, 763) /w:[ 4 6 3 -1 ] xor g40 (.I0(w18), .I1(w40), .Z(w30)); //: @(312,763) /sn:0 /w:[ 9 1 1 ] mux g54 (.I0(mdr), .I1(w1), .S(w26), .Z(w36)); //: @(790,740) /sn:0 /w:[ 0 0 1 0 ] //: joint g81 (_incmar) @(325, 264) /w:[ 4 6 -1 3 ] //: frame g93 @(354,466) /sn:0 /wi:421 /ht:164 /tx:"Main Memory" concat g46 (.I0(w15), .I1(w31), .Z(w27)); //: @(638,667) /sn:0 /R:1 /w:[ 3 7 1 ] /dr:0 //: joint g45 (mdrin) @(559, 552) /w:[ 2 4 1 -1 ] nor g35 (.I0(!_incpc), .I1(!_ldpc), .Z(w14)); //: @(244,129) /sn:0 /w:[ 0 0 0 ] mux g26 (.I0(w9), .I1(DATA), .S(!_ldpc), .Z(w19)); //: @(188,204) /sn:0 /w:[ 0 15 5 0 ] //: input g0 (CK) @(60,436) /sn:0 /w:[ 17 ] register mar (.Q(mar), .D(w43), .EN(w46), .CLR(_CLR), .CK(CK)); //: @(363,307) /w:[ 0 0 0 17 13 ] buf g22 (.I(DATA), .Z(w4)); //: @(574,165) /sn:0 /w:[ 9 0 ] nor g70 (.I0(!_ldhmdr), .I1(!_ldmdr), .Z(w)); //: @(874,280) /sn:0 /R:3 /w:[ 3 0 1 ] //: comment g90 /dolink:0 /link:"" @(211,844) /sn:0 //: /line:"Questa è la tty. Quando si attiva la " //: /line:"simulazione appare una finestra che " //: /line:"corrisponde a questo dispositivo." //: /line:"La CPU simulata accede alla tty con" //: /line:"operazioni di lettura e di scrittura" //: /line:"agli indirizzi indicati dagli switch" //: /line:"TTYSTATUS and TTYDATA." //: /end //: dip TTYDATA (w40) @(174,765) /R:1 /w:[ 0 ] /st:17 tty tty0 (.TD(TD), .RD(RD), .RTS(RTS), .CTS(CTS), .DSR(DSR), .DTR(DTR)); //: @(414,963) /w:[ 0 1 0 0 0 0 ] //: supply0 g66 (w1) @(825,693) /sn:0 /w:[ 1 ] //: joint g82 (_incmar) @(325, 281) /w:[ 1 2 -1 8 ] //: joint g12 (_rd) @(671, 616) /w:[ 2 1 4 -1 ] concat g18 (.I0(mdr), .I1(w3), .Z(w2)); //: @(657,246) /sn:0 /R:2 /w:[ 9 1 0 ] /dr:0 //: input g33 (_incpc) @(131,126) /sn:0 /w:[ 1 ] //: supply0 g30 (w21) @(220,65) /sn:0 /w:[ 0 ] //: frame g91 @(45,27) /sn:0 /wi:441 /ht:397 /tx:"Address Resolution" //: supply0 g49 (w24) @(595,544) /sn:0 /w:[ 0 ] endmodule module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>SA[1:0](17/138) Li1>SB[1:0](33/138) Li2>_CLR(51/138) Li3>_ENA(70/138) Li4>_ENB(88/138) Li5>_WA(106/138) Li6>CK(123/138) Bo0B[15:0](79/107) Ti1>A[15:0](31/107) Li0>CIN(95/127) Li1>FUNC[4:0](18/127) Bo0CK(37/132) Ti1>_CLR(86/132) Li0>_incmar(187/353) Bi0>IR[15:0](62/132) Ri0>_LT(258/353) Ri1>_GT(276/353) Ri2>_Z(296/353) Ri3>COUT(314/353) Lo0<_wrt(105/353) Lo1<_rdmdr(89/353) Lo2<_incpc(74/353) Lo3<_ldmdr(58/353) Lo4<_ldmar(43/353) Lo5<_ldpc(26/353) Lo6<_ldhmdr(156/353) Lo70 Ti1>0 Bo0<1 Ro0<1 Ro1<0 Ro2<1 Ro3<0 Ro4<1 Ro5<1 ] //: output g75 (_LDQH) @(701,1127) /sn:0 /w:[ 1 ] //: supply0 g9 (w5) @(368,751) /sn:0 /w:[ 0 ] //: output g57 (SB) @(766,890) /sn:0 /w:[ 0 ] //: output g53 (_ldmdr) @(701,1017) /sn:0 /w:[ 0 ] //: joint g7 (CK) @(102, 120) /w:[ 16 18 -1 15 ] mux g71 (.I0(w45), .I1(w46), .S(w47), .Z(SB)); //: @(725,890) /sn:0 /R:1 /w:[ 0 0 0 1 ] //: supply0 g15 (w15) @(205,723) /sn:0 /w:[ 1 ] mux g20 (.I0(IDATA), .I1(w27), .S(w35), .Z(w12)); //: @(393,390) /sn:0 /R:3 /w:[ 0 0 1 0 ] //: input g31 (IR) @(57,70) /sn:0 /w:[ 0 ] mux g68 (.I0(w41), .I1(w39), .S(w43), .Z(SA)); //: @(725,818) /sn:0 /R:1 /w:[ 0 1 0 0 ] //: supply1 g39 (w19) @(421,649) /sn:0 /w:[ 1 ] //: joint g67 (w6) @(151, 65) /w:[ 2 -1 1 4 ] //: supply0 g43 (w20) @(455,1042) /sn:0 /w:[ 1 ] //: joint g48 (IDATA) @(540, 654) /w:[ 2 1 4 -1 ] //: frame g88 @(176,317) /sn:0 /wi:311 /ht:239 /tx:"Microcode Next Address Generation" //: joint g29 (ww) @(945, 358) /w:[ 2 4 1 -1 ] mux g73 (.I0(w7), .I1(w49), .S(w42), .Z(FUNC)); //: @(725,956) /sn:0 /R:1 /w:[ 1 1 0 1 ] nor g25 (.I0(!w55), .I1(!w32), .Z(_SA0)); //: @(890,384) /sn:0 /R:2 /w:[ 13 0 0 ] //: supply0 g17 (w23) @(360,367) /sn:0 /w:[ 0 ] //: comment g62 /dolink:0 /link:"" @(370,940) //: /line:"Questa è la metà " //: /line:"superiore della memoria" //: /line:"delle microistruzioni." //: /end //: joint g63 (CK) @(264, 771) /w:[ 2 4 -1 1 ] //: supply0 g42 (w30) @(455,678) /sn:0 /w:[ 1 ] //: output g52 (_ldmar) @(701,1007) /sn:0 /w:[ 1 ] //: output g83 (_incmar) @(701,1177) /sn:0 /w:[ 0 ] //: output g74 (_LDQL) @(701,1117) /sn:0 /w:[ 1 ] //: output g56 (SA) @(766,818) /sn:0 /w:[ 1 ] //: joint g5 (mp_nxtaddr) @(331, 709) /w:[ 4 6 -1 3 ] //: supply1 g14 (w21) @(186,641) /sn:0 /w:[ 0 ] //: joint g80 (CK) @(102, 276) /w:[ 12 14 -1 11 ] concat g79 (.I0(w32), .I1(ww), .I2(w55), .I3(w4), .Z(w3)); //: @(1030,353) /sn:0 /w:[ 3 3 0 1 1 ] /dr:0 //: output g47 (IDATA) @(690,654) /sn:0 /w:[ 3 ] //: output g44 (_incpc) @(701,997) /sn:0 /w:[ 1 ] //: comment g85 /dolink:0 /link:"" @(-1,132) /sn:0 //: /line:"Questo blocco" //: /line:"decodifica" //: /line:"le istruzioni" //: /line:"e produce" //: /line:"un map index," //: /line:"numeri di" //: /line:"registri," //: /line:"un function" //: /line:"code e un" //: /line:"condition" //: /line:"code." //: /end //: output g36 (_LDDATA) @(690,734) /sn:0 /w:[ 0 ] //: input g21 (COUT) @(1163,375) /sn:0 /R:2 /w:[ 1 ] //: input g24 (_LT) @(1168,345) /sn:0 /R:2 /w:[ 0 ] //: comment g84 /dolink:0 /link:"" @(691,70) //: /line:"Questo è un esmpio semplice di un'unità di controllo." //: /line:"Il registro mpc è il \"micro-instruction program counter\";" //: /line:"i due registri alle uscite delle ROM m1 and m2 contengono" //: /line:"le micro-istruzioni correnti." //: /end //: input g23 (_Z) @(1164,361) /sn:0 /R:2 /w:[ 0 ] //: output g41 (spc) @(701,1067) /sn:0 /w:[ 1 ] //: supply1 g40 (w24) @(421,1016) /sn:0 /w:[ 1 ] //: output g54 (_ldpc) @(701,1027) /sn:0 /w:[ 1 ] //: output g60 (_wrt) @(701,1057) /sn:0 /w:[ 1 ] //: output g81 (_ldhmdr) @(701,1157) /sn:0 /w:[ 0 ] //: joint g22 (w55) @(879, 300) /w:[ 3 4 6 -1 ] concat g0 (.I0(w14), .I1(IDATA), .I2(w18), .I3(_ldir), .I4(AOP), .I5(BOP), .I6(CIN), .I7(_CLQ), .I8(_LDQ), .I9(_LDDATA), .I10(_ldopr), .I11(_WA), .I12(w39), .I13(w46), .Z(mp_wrd0)); //: @(483,709) /sn:0 /R:2 /w:[ 0 5 0 0 0 0 1 1 1 1 0 1 0 1 1 ] /dr:0 //: input g26 (_GT) @(1165,323) /sn:0 /R:2 /w:[ 0 ] register g35 (.Q(w8), .D(w10), .EN(w20), .CLR(w24), .CK(CK)); //: @(436,1087) /sn:0 /R:1 /w:[ 1 0 0 0 0 ] //: output g45 (AOP) @(690,684) /sn:0 /w:[ 1 ] //: output g46 (BOP) @(690,694) /sn:0 /w:[ 1 ] //: joint g70 (_CLR) @(385, 74) /w:[ 7 -1 8 10 ] //: output g82 (_rdpc) @(701,1167) /sn:0 /w:[ 1 ] concat g66 (.I0(w6), .I1(w25), .Z(IR)); //: @(85,70) /sn:0 /R:2 /w:[ 0 1 1 ] /dr:0 add g12 (.A(mp_nxtaddr), .B(w15), .S(w27), .CI(w21), .CO(w22)); //: @(221,657) /sn:0 /R:2 /w:[ 9 0 5 1 0 ] mux g18 (.I0(!w55), .I1(!w4), .I2(w55), .I3(ww), .I4(w32), .I5(_SA), .I6(_SA0), .I7(w28), .S(w44), .Z(w35)); //: @(797,311) /sn:0 /R:3 /w:[ 5 0 7 5 5 1 1 1 0 0 ] //: joint g30 (CK) @(102, 511) /w:[ 9 10 20 -1 ] //: joint g33 (w55) @(911, 353) /w:[ -1 9 10 12 ] //: output g49 (CIN) @(690,704) /sn:0 /w:[ 0 ] endmodule module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>SA[1:0](17/138) Li1>SB[1:0](33/138) Li2>_CLR(51/138) Li3>_ENA(70/138) Li4>_ENB(88/138) Li5>_WA(106/138) Li6>CK(123/138) Bo0IR[7:0](19/192) Ti1>OPR[7:0](148/192) Bo0DIN[15:0](53/108) Li0>_WA(101/138) Li1>_ENB(82/138) Li2>_ENA(66/138) Li3>_CLR(51/138) Li4>SB[3:0](33/138) Li5>SA[3:0](17/138) Li6>CK(118/138) Bo013 Li0>13 Li1>13 Li2>1 Li3>1 Li4>13 Li5>13 Li6>13 Bo0<13 Bo1<13 ] //: joint g38 (B) @(880, 435) /w:[ 5 6 8 -1 ] //: joint g6 (w50) @(690, 520) /w:[ 6 8 5 -1 ] //: joint g7 (w49) @(142, 623) /w:[ 2 12 1 -1 ] //: input g9 (SA) @(31,525) /sn:0 /w:[ 1 ] //: joint g31 (DIN) @(853, 156) /w:[ 6 -1 5 8 ] //: joint g15 (_CLR) @(465, 359) /w:[ 4 10 3 -1 ] //: joint g39 (B) @(1133, 435) /w:[ 1 2 4 -1 ] //: joint g29 (DIN) @(360, 156) /w:[ 2 -1 1 12 ] //: joint g25 (_WA) @(769, 379) /w:[ 6 8 5 -1 ] demux g17 (.I(w37), .E(!_ENA), .Z0(!w16), .Z1(!w9), .Z2(!w26), .Z3(!w47)); //: @(222,485) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] //: joint g14 (_CLR) @(163, 359) /w:[ 2 12 1 -1 ] concat g5 (.I0(w49), .I1(w15), .Z(SB)); //: @(79,628) /sn:0 /R:2 /w:[ 0 1 0 ] /dr:0 REG4 RF3 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w47), ._ENB(w46), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(1053, 197) /sz:(109, 138) /p:[ Ti0>7 Li0>7 Li1>7 Li2>7 Li3>1 Li4>1 Li5>7 Li6>7 Bo0<3 Bo1<3 ] //: joint g36 (A) @(1085, 467) /w:[ 1 2 4 -1 ] //: joint g24 (_WA) @(500, 379) /w:[ 4 10 3 -1 ] //: output g41 (A) @(1207,467) /sn:0 /w:[ 0 ] //: joint g23 (_WA) @(279, 379) /w:[ 2 12 1 -1 ] //: output g40 (B) @(1205,435) /sn:0 /w:[ 0 ] REG4 RF1 (.DIN(DIN), .CK(CK), ._WA(_WA), ._ENB(w10), ._ENA(w9), ._CLR(_CLR), .SB(w49), .SA(w50), .B(B), .A(A)); //: @(567, 198) /sz:(106, 138) /p:[ Ti0>11 Li0>11 Li1>11 Li2>1 Li3>1 Li4>11 Li5>11 Li6>11 Bo0<11 Bo1<11 ] //: joint g35 (A) @(832, 467) /w:[ 5 6 8 -1 ] //: joint g26 (CK) @(294, 403) /w:[ 2 12 1 -1 ] //: input g22 (CK) @(40,403) /sn:0 /w:[ 0 ] //: input g18 (_WA) @(40,379) /sn:0 /w:[ 0 ] //: input g12 (_CLR) @(41,359) /sn:0 /w:[ 0 ] //: input g33 (_ENB) @(33,555) /sn:0 /w:[ 1 ] //: joint g30 (DIN) @(619, 156) /w:[ 4 -1 3 10 ] REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(801, 198) /sz:(107, 138) /p:[ Ti0>9 Li0>9 Li1>9 Li2>9 Li3>1 Li4>1 Li5>9 Li6>9 Bo0<7 Bo1<7 ] endmodule module main; //: root_module wire w32; //: /sn:0 {0}(589,382)(659,382){1} wire [3:0] w45; //: /sn:0 {0}(589,142)(659,142){1} wire [3:0] w46; //: /sn:0 {0}(589,157)(659,157){1} wire w56; //: /sn:0 {0}(589,324)(659,324){1} wire w38; //: /sn:0 {0}(455,197)(394,197){1} wire [7:0] w51; //: /sn:0 {0}(589,237)(659,237){1} wire w0; //: /sn:0 {0}(455,310)(394,310){1} wire w37; //: /sn:0 {0}(455,212)(394,212){1} wire w34; //: /sn:0 {0}(589,420)(659,420){1} wire w43; //: /sn:0 {0}(455,260)(394,260){1} wire w54; //: /sn:0 {0}(589,289)(659,289){1} wire w58; //: /sn:0 {0}(589,363)(659,363){1} wire [15:0] DATA; //: /dp:5 {0}(727,478)(727,525)(519,525){1} //: {2}(517,523)(517,478){3} //: {4}(515,525)(328,525)(328,478){5} wire w41; //: /sn:0 {0}(455,149)(394,149){1} wire w36; //: /sn:0 {0}(455,228)(394,228){1} wire w40; //: /sn:0 {0}(455,166)(394,166){1} wire w35; //: /sn:0 {0}(589,438)(659,438){1} wire w59; //: /sn:0 {0}(455,295)(394,295){1} wire w53; //: /sn:0 {0}(589,275)(659,275){1} wire clk; //: /dp:4 {0}(694,123)(694,66)(494,66){1} //: {2}(490,66)(303,66){3} //: {4}(299,66)(148,66){5} //: {6}(301,68)(301,123){7} //: {8}(492,68)(492,123){9} wire w57; //: /sn:0 {0}(589,344)(659,344){1} wire [1:0] w49; //: /sn:0 {0}(589,205)(659,205){1} wire w44; //: /sn:0 {0}(455,244)(394,244){1} wire w52; //: /sn:0 {0}(589,257)(659,257){1} wire [1:0] w48; //: /sn:0 {0}(589,189)(659,189){1} wire w33; //: /sn:0 {0}(589,400)(659,400){1} wire _reset; //: /dp:4 {0}(749,123)(749,31)(543,31){1} //: {2}(539,31)(353,31){3} //: {4}(349,31)(154,31){5} //: {6}(351,33)(351,123){7} //: {8}(541,33)(541,123){9} wire w47; //: /sn:0 {0}(589,174)(659,174){1} wire [4:0] w50; //: /sn:0 {0}(589,219)(659,219){1} wire w42; //: /sn:0 {0}(455,279)(394,279){1} wire w55; //: /sn:0 {0}(589,306)(659,306){1} wire w39; //: /sn:0 {0}(455,181)(394,181){1} //: enddecls //: joint g4 (DATA) @(517, 525) /w:[ 1 2 4 -1 ] //: comment g8 /dolink:1 /link:"@C/menagerie.gm" @(17,366) /sn:0 //: /line:"* Microcode/Macrocode Definitions" //: /end //: joint g3 (_reset) @(541, 31) /w:[ 1 -1 2 8 ] //: comment g13 /dolink:0 /link:"" @(17,448) /sn:0 //: /line:"Particolarità  del circuito:" //: /end //: joint g2 (clk) @(492, 66) /w:[ 1 -1 2 8 ] //: comment g1 /dolink:0 /link:"" @(17,104) //: /line:"Questo circuito è un microprocessore" //: /line:"semplice." //: /line:"Uno script di simulazione lo " //: /line:"attiva e gli fa eseguire il gioco" //: /line:"\"Animals\"." //: /line:"Clicca sui vari blocchi e accedi" //: /line:"ai sotto-circuiti con il " //: /line:"carattere '>'. Risali i livelli " //: /line:"di gerarchia inserendo '<' da " //: /line:"tastiera. " //: /line:"Mentre simuli, clicca sui" //: /line:"collegamenti per vederne " //: /line:"il valore o clicca doppio " //: /line:"per visualizzarne la traccia." //: /line:"" //: /line:"Trovi files associati a questo" //: /line:"esempio nella directory" //: /line:"\"examples/ex5\" del dir delle " //: /line:"librerie di TkGate." //: /line:"Clicca sui link qui sotto per" //: /line:"vederne il contenuto." //: /end //: comment g16 /dolink:1 /link:"#eunit.alu" @(17,510) /sn:0 //: /line:"* ALU" //: /end //: comment g11 /dolink:1 /link:"@C/menagerie.gss" @(17,406) /sn:0 //: /line:"* Simulator Script" //: /end //: comment g10 /dolink:1 /link:"@C/menagerie.mem" @(17,386) /sn:0 //: /line:"* Memory Initialization File" //: /end IUNIT iunit (._CLR(_reset), .CK(clk), .IR(DATA), .COUT(w35), ._Z(w34), ._GT(w33), ._LT(w32), ._rdpc(w59), ._incmar(w0), ._rd(w44), .spc(w43), ._ldhmdr(w42), ._ldpc(w41), ._ldmar(w40), ._ldmdr(w39), ._incpc(w38), ._rdmdr(w37), ._wrt(w36), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), .SA(w45)); //: @(456, 124) /sz:(132, 353) /p:[ Ti0>9 Ti1>9 Bi0>3 Ri0>0 Ri1>0 Ri2>0 Ri3>0 Lo0<0 Lo1<0 Lo2<0 Lo3<0 Lo4<0 Lo5<0 Lo6<0 Lo7<0 Lo8<0 Lo9<0 Lo10<0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 ] //: joint g6 (_reset) @(351, 31) /w:[ 3 -1 4 6 ] //: comment g9 /dolink:0 /link:"" @(20,54) //: /line:"Clock" //: /line:"di sistema." //: /line:" " //: /end //: comment g7 /dolink:0 /link:"" @(20,17) /sn:0 //: /line:"Interruttore" //: /line:"di reset." //: /end //: comment g15 /dolink:1 /link:"#iunit.mpc" @(17,487) /sn:0 //: /line:"* Micro Program Counter" //: /end MEMORY memory (._CLR(_reset), .CK(clk), ._incmar(w0), ._rdpc(w59), ._ldhmdr(w42), .spc(w43), ._rd(w44), ._wrt(w36), ._rdmdr(w37), ._incpc(w38), ._ldmdr(w39), ._ldmar(w40), ._ldpc(w41), .DATA(DATA)); //: @(268, 124) /sz:(125, 353) /p:[ Ti0>7 Ti1>7 Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Ri5>1 Ri6>1 Ri7>1 Ri8>1 Ri9>1 Ri10>1 Bt0=5 ] //: comment g17 /dolink:1 /link:"#memory.m1" @(17,531) /sn:0 //: /line:"* Main Memory" //: /end EUNIT eunit (._CLR(_reset), .CK(clk), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .SA(w45), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), ._LT(w32), ._GT(w33), ._Z(w34), .COUT(w35), .DATA(DATA)); //: @(660, 124) /sz:(128, 353) /p:[ Ti0>0 Ti1>0 Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Li6>1 Li7>1 Li8>1 Li9>1 Li10>1 Li11>1 Li12>1 Li13>1 Lo0<1 Lo1<1 Lo2<1 Lo3<1 Bt0=0 ] //: joint g5 (clk) @(301, 66) /w:[ 3 -1 4 6 ] //: comment g14 /dolink:1 /link:"#memory.tty0" @(17,468) /sn:0 //: /line:"* TTY Device" //: /end clock g0 (.Z(clk)); //: @(135,66) /sn:0 /w:[ 5 ] /omega:300 /phi:0 /duty:50 //: comment g18 /dolink:1 /link:"#memory.PC" @(17,551) /sn:0 //: /line:"* Program Counter" //: /end //: switch reset (_reset) @(137,31) /sn:0 /w:[ 5 ] /st:1 //: comment g12 /dolink:1 /link:"@C/menagerie.map" @(17,426) /sn:0 //: /line:"* Symbol Map" //: /end endmodule module EUNIT(_LDDATA, _CLR, SB, SA, AOP, BOP, _GT, _LDQ, _Z, _WA, CK, _CLQ, DATA, FUNC, _LT, _LDQH, _LDQL, CIN, IDATA, COUT, _DOUT); //: interface /sz:(128, 353) /bd:[ Ti0>CK(34/128) Ti1>_CLR(89/128) Li0>SB[3:0](33/353) Li1>_WA(50/353) Li2>AOP[1:0](65/353) Li3>BOP[1:0](81/353) Li4>FUNC[4:0](95/353) Li5>IDATA[7:0](113/353) Li6>_CLQ(133/353) Li7>_LDQ(150/353) Li8>CIN(165/353) Li9>SA[3:0](18/353) Li10>_LDDATA(182/353) Li11>_LDQH(200/353) Li12>_LDQL(220/353) Li13>_DOUT(239/353) Lo01 Li0>0 Li1>1 Li2>1 Li3>3 Li4>0 Li5>3 Li6>0 Bo0<1 Bo1<1 ] tran g39(.Z(w12), .I(w1[15:8])); //: @(678,679) /sn:0 /R:3 /w:[ 0 7 8 ] /ss:0 ALU alu (.B(w31), .A(w38), .CIN(CIN), .FUNC(FUNC), .OUT(w1), .COUT(COUT), ._LT(_LT), ._GT(_GT), ._Z(_Z)); //: @(500, 523) /sz:(107, 127) /sn:0 /p:[ Ti0>1 Ti1>1 Li0>1 Li1>1 Bo0<9 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] nor g43 (.I0(!_LDQL), .I1(!_LDQ), .Z(w9)); //: @(706,783) /sn:0 /R:3 /w:[ 0 7 1 ] register QL (.Q(QL), .D(w8), .EN(w9), .CLR(w10), .CK(CK)); //: @(620,829) /w:[ 1 0 0 0 7 ] //: joint g48 (w1) @(844, 676) /w:[ 1 2 4 -1 ] register QH (.Q(QH), .D(w2), .EN(w7), .CLR(w10), .CK(CK)); //: @(761,855) /w:[ 1 1 1 3 9 ] bufif0 g17 (.Z(DATA), .I(w1), .E(_DOUT)); //: @(906,676) /sn:0 /cpc:1 /w:[ 13 0 0 ] //: input g25 (FUNC) @(475,541) /sn:0 /w:[ 0 ] //: output g29 (_LT) @(642,575) /sn:0 /w:[ 0 ] //: joint g42 (CK) @(537, 829) /w:[ 6 -1 5 8 ] //: joint g5 (w0) @(463, 316) /w:[ 2 1 -1 4 ] //: supply0 g14 (w30) @(299,394) /sn:0 /w:[ 0 ] //: joint g44 (_LDQ) @(708, 739) /w:[ 2 -1 1 4 ] //: joint g47 (DATA) @(959, 676) /w:[ 1 2 12 -1 ] //: joint g36 (w8) @(771, 710) /w:[ -1 2 1 4 ] //: input g24 (_LDQH) @(808,771) /sn:0 /w:[ 1 ] //: joint g21 (w35) @(486, 418) /w:[ 2 -1 4 1 ] //: joint g41 (CK) @(195, 409) /w:[ -1 1 2 4 ] //: input g23 (_LDQL) @(677,764) /sn:0 /w:[ 1 ] //: joint g40 (w10) @(669, 809) /w:[ 2 -1 4 1 ] //: joint g22 (DATA) @(608, 437) /w:[ 7 -1 8 10 ] //: joint g0 (DATA) @(864, 437) /w:[ 3 4 6 -1 ] //: joint g46 (_LDQ) @(708, 757) /w:[ 6 5 8 -1 ] nor g45 (.I0(!_LDQH), .I1(!_LDQ), .Z(w7)); //: @(840,809) /sn:0 /R:3 /w:[ 0 9 0 ] mux g35 (.I0(w12), .I1(w8), .S(_LDQ), .Z(w2)); //: @(761,739) /sn:0 /w:[ 1 5 3 0 ] //: input g26 (CIN) @(473,618) /sn:0 /w:[ 0 ] //: input g12 (IDATA) @(296,423) /sn:0 /w:[ 1 ] mux g18 (.I0(w21), .I1(DATA), .I2(w35), .I3(w28), .S(BOP), .Z(w31)); //: @(614,481) /sn:0 /w:[ 3 11 3 0 1 0 ] //: output g30 (COUT) @(642,592) /sn:0 /w:[ 0 ] //: input g49 (_DOUT) @(908,642) /sn:0 /R:3 /w:[ 1 ] endmodule tkgate-2.0-b10/locale/it/examples.18/ex5/menagerie.gss000644 001751 001751 00000001423 10152673133 023102 0ustar00hansenhansen000000 000000 # # This is the simulator script for the menagerie cpu example. It # is registered to run automatically when the example is simulated. # # # Initialize the memories with the data in the menagerie.mem file. # The menagerie.mem file was compiled using gmac from the menagerie.gm # file. # load "menagerie.mem" # # Set the zoom factor for the scope. This command will zoom out # three steps to show a larger time range. # zoom 3 # # Command such as these can be uncommented to set probes or # breakpoints. # #probe clk #break iunit.extra==8'h15 # # Set the reset (active low) line to '0', step two clocks and # then set the reset line back to '1'. This sequence resets # the cpu. # set reset 1'b0 clock +2 set reset 1'b1 # # Start simulating the circuit in continous mode. # run tkgate-2.0-b10/locale/it/examples.18/ex5/menagerie.map000644 001751 001751 00000012527 10152673133 023072 0ustar00hansenhansen000000 000000 Microcode Symbols (total=57): --------------------------------------- _mbdi 000000b3 _mbdr 0000008d _mbrd 0000007b _mwdi 000000a9 _mwdr 00000091 _mwrd 0000007f alu_ri 0000000d alu_rr 0000000b bdojmp 00000029 br_d 0000002d br_i 00000022 br_r 0000002b br_x 0000002f btest 00000025 call_di 0000004b call_ii 00000031 call_ri 00000049 call_xi 0000004d cmp_ri 0000001d cmp_rr 0000001b fetch 00000005 fetch1 00000006 fetch2 00000007 halt 00000009 movb_dd 000000a4 movb_di 000000b2 movb_dr 0000008c movb_dx 000000a6 movb_rd 0000007a movb_ri 00000075 movb_rr 0000006d movb_rx 00000084 movb_xd 000000a2 movb_xi 000000bc movb_xr 00000097 movb_xx 000000a0 movw_dd 000000a3 movw_di 000000a8 movw_dr 00000090 movw_dx 000000a5 movw_rd 0000007e movw_ri 00000070 movw_rr 0000006b movw_rx 00000088 movw_xd 000000a1 movw_xi 000000b8 movw_xr 0000009b movw_xx 0000009f nop 000000c0 pushw_d 00000058 pushw_i 00000061 pushw_r 0000005a pushw_x 00000059 ret 0000004f start 00000000 xalu_ri 00000015 xalu_rr 00000012 Macrocode Symbols (total=69): Global Local --------------------------------------- buf 000005f8 dscrim 00000795 find_animal 0000017a done 0000025e get_response 000001a6 say_no 0000023e say_yes 0000021e tree fffffffe get_final 00000264 L1 0000037c L2 000003e8 L3 00000404 animal_node fffffffc discrim_node fffffffa done 00000420 get_response 00000268 loose 000002f0 tree fffffffe win 000002de gets 00000570 bell 000005d4 cwait 00000576 del_char 000005b8 done 000005e6 isita 000006f7 known 00000678 loosemsg 0000075e main 00000112 loop 0000013e malloc 00000426 mend 000007f6 nl 000007f1 no 00000724 no_b 00000002 nprint 000004e8 zprint 000004fe nprint_aux 0000050c done 00000546 nsize 00000064 numk 000006d8 print 00000430 done 0000044c loop 00000434 printf 0000044e L1 00000474 L2 000004a2 arg fffffffc cout 000004d4 done 000004e6 loop 0000045c ptr fffffffe qprompt 000007f3 root 0000067a sdone 0000010e start 00000100 strcmp 00000548 done 0000056e loop 00000550 text 00000004 think 0000069f top_node 0000067c ttydata 00000011 ttystatus 00000010 welcome 00000689 which 000007d0 winmsg 00000743 yes 00000720 yes_b 00000000 yesno 00000727 tkgate-2.0-b10/locale/it/examples.18/ex5/menagerie.mem000644 001751 001751 00000020560 10152673133 023067 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 40/ f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 48/ f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 50/ f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 58/ f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 60/ f82000 f82000 d92000 d92000 f7ae008 fa2000 f82000 fa2000 68/ f82000 f83c17 f82000 7bfc1f f80000 fbe000 fabc1f 780000 70/ f82000 d92000 d92000 78fc17 f82000 f82000 d92000 fb2000 78/ 78fc17 f82000 fba000 f82000 583c17 fae000 fba000 f82000 80/ d92000 d92000 783c17 f82000 f82000 d92000 d93def fb2000 88/ f82000 d92000 d93dff fb2000 fae000 fba000 f83c17 f82000 90/ fae000 fba000 f82000 fba000 f82000 f83c17 f82000 f82000 98/ d92000 d93e37 f8e000 f82000 d92000 d93e47 f8e000 f82000 a0/ f82000 f82000 f82000 f82000 f82000 f82000 f82000 f82000 a8/ fa2000 f82000 d92000 d92000 f8a000 f82000 f8a000 f82000 b0/ f83c17 f82000 fae000 f82000 d92000 f8a000 f83c17 f82000 b8/ f82000 d92000 d93ea7 f8e000 f82000 d92000 d93ecf f8e000 c0/ f83c17 f82000 memory iunit.m2 0/ ffefe0 fbeff6 f7eef6 ffefe0 ffefe0 fffd40 fff940 ffebe0 8/ ffefe0 1ffefe0 1ffefe0 ef1d40 fff940 fffd40 fdf956 fbebf6 10/ ef4fe0 ffefe0 ff0fe0 ef1d40 fff940 fffd40 fdf956 fbebf6 18/ ff0fe0 ef4fe0 ffefe0 22ef8ff5 ffefe0 fffd40 fdf956 fbebf6 20/ efcff5 ffefe0 fffd40 fdf956 fbebf6 feefe0 ffefe0 ffefe0 28/ ffefe0 f7eef6 ffefe0 10ffcff4 ffefe0 ffefe0 ffefe0 ffefe0 30/ ffefe0 11f7efb5 bfeff4 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 38/ ffefe0 f7efb5 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 ffeff6 40/ fffd40 fdf956 fbebf6 ffeff4 fffd40 fdf956 fbebf6 f7eef6 48/ ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 12f7efb6 50/ 7fed74 7de976 fbebf6 7fed76 7de976 fbebf6 f7eef6 fffd40 58/ ffefe0 ffefe0 13f7efb5 f7cf74 ffe7e0 57cff4 ffefe0 ffe7e0 60/ ffefe0 2fffd40 fdf956 fbebf6 13f7efb5 f7ef74 ffe7e0 57eff4 68/ ffefe0 ffe7e0 ffefe0 1ef9d56 fff940 1edaff6 fbfd54 ffd956 70/ 2fffd40 fdf956 fbebf6 efcff6 ffefe0 2fffd40 fdf956 fbebf6 78/ efcff6 ffefe0 3f7afb4 ffed60 ffcbe0 efcff4 3f7afb4 7fed60 80/ fde976 fbebf6 efcff6 ffefe0 9fffd40 fdf956 fbebf6 f7afb4 88/ 9fffd40 fdf956 fbebf6 f7afb4 e7cfb4 f7af74 ffe7e0 ffefe0 90/ e7cfb4 f7af74 ffe7e0 57aff4 ffefe0 ffe7e0 ffefe0 9fffd40 98/ fdf956 fbebf6 e7cfb4 9fffd40 fdf956 fbebf6 e7cfb4 7ffefe0 a0/ 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 a8/ f7cfb4 2fffd40 fdf956 fbebf6 f7ef74 ffe7e0 57eff4 ffefe0 b0/ ffe7e0 ffefe0 21f7cfb4 fffd40 fdf956 f7ef74 ffe7e0 ffefe0 b8/ 2fffd40 fdf956 fbebf6 f7cfb4 2fffd40 fdf956 fbebf6 f7cfb4 c0/ 15ffefe0 ffefe0 memory iunit.map 3e/ c0 0/ 9 2/ 1b 1d a0/ 2b 22 2d 2f 68/ b d b d 60/ 12 15 78/ 12 15 70/ 12 15 50/ b d 80/ 49 31 4b 4d 4/ 4f 84/ 5a 61 58 59 f0/ 6d 75 7a 84 f8/ 8c b2 a4 a6 97 bc a2 a0 e0/ 6b 70 7e 88 e8/ 90 a8 a3 a5 9b b8 a1 9f memory memory.m1 100/ e1 f0 0 0 e1 e0 0 0 108/ 81 0 0 0 12 1 bd 0 110/ e 1 e1 d0 e6 7 85 0 118/ 79 6 81 0 0 0 3e 4 120/ 69 f0 2 0 ed 0 6a 6 128/ 6c 6 ed 0 68 6 1 0 130/ 85 0 8f 6 81 0 0 0 138/ 3e 4 69 f0 2 0 e3 10 140/ 68 6 84 10 85 0 c8 6 148/ 81 0 0 0 3e 4 69 f0 150/ 4 0 e3 10 6a 6 84 10 158/ 81 0 0 0 6c 1 69 f0 160/ 2 0 ec 1 6a 6 bd 0 168/ 30 1 4 0 6b f0 2 0 170/ e3 1e 4 0 ec e1 fe ff 178/ e3 21 0 0 3 20 0 0 180/ a1 0 98 1 84 10 81 0 188/ 0 0 56 2 69 f0 2 0 190/ ec e1 fe ff bd 0 50 2 198/ e3 1e fe ff e0 41 69 40 1a0/ 4 0 84 40 81 0 0 0 1a8/ 20 4 69 f0 2 0 85 0 1b0/ e3 7 81 0 0 0 20 4 1b8/ 69 f0 2 0 85 0 e8 5 1c0/ 81 0 0 0 60 5 69 f0 1c8/ 2 0 85 0 e8 5 85 0 1d0/ 10 7 81 0 0 0 34 5 1d8/ 69 f0 4 0 3 10 0 0 1e0/ a9 0 10 2 85 0 e8 5 1e8/ 85 0 14 7 81 0 0 0 1f0/ 34 5 69 f0 4 0 3 10 1f8/ 0 0 a9 0 30 2 85 0 200/ 17 7 81 0 0 0 20 4 208/ 69 f0 2 0 bd 0 98 1 210/ e3 1e fe ff e3 21 0 0 218/ 84 20 81 0 0 0 6c 1 220/ 69 f0 2 0 e3 2e fe ff 228/ ec 21 0 0 bd 0 50 2 230/ e3 1e fe ff e3 21 2 0 238/ 84 20 81 0 0 0 6c 1 240/ 69 f0 2 0 e3 2e fe ff 248/ ec 21 2 0 bd 0 50 2 250/ e3 1e fe ff 4 0 6b f0 258/ 6 0 e3 1e 4 0 ec e1 260/ fe ff e3 1e 4 0 69 10 268/ 4 0 84 10 85 0 e7 6 270/ 81 0 0 0 3e 4 69 f0 278/ 4 0 85 0 e8 5 81 0 280/ 0 0 60 5 69 f0 2 0 288/ 85 0 e8 5 85 0 10 7 290/ 81 0 0 0 34 5 69 f0 298/ 4 0 3 10 0 0 a9 0 2a0/ ce 2 85 0 e8 5 85 0 2a8/ 14 7 81 0 0 0 34 5 2b0/ 69 f0 4 0 3 10 0 0 2b8/ a9 0 e0 2 85 0 17 7 2c0/ 81 0 0 0 20 4 69 f0 2c8/ 2 0 bd 0 5a 2 85 0 2d0/ 33 7 81 0 0 0 3e 4 2d8/ 69 f0 2 0 bd 0 10 4 2e0/ 85 0 4e 7 81 0 0 0 2e8/ 3e 4 69 f0 2 0 85 0 2f0/ 68 0 81 0 0 0 16 4 2f8/ 69 f0 2 0 ec e1 fc ff 300/ ed 10 0 0 0 0 ed 10 308/ 2 0 0 0 69 10 4 0 310/ 84 10 81 0 0 0 60 5 318/ 69 f0 2 0 e3 1e fe ff 320/ 69 10 4 0 84 10 e3 1e 328/ fc ff 69 10 4 0 84 10 330/ 85 0 85 7 81 0 0 0 338/ 3e 4 69 f0 6 0 85 0 340/ 68 0 81 0 0 0 16 4 348/ 69 f0 2 0 ec e1 fa ff 350/ 69 10 4 0 84 10 81 0 358/ 0 0 60 5 69 f0 2 0 360/ e3 10 68 6 69 10 1 0 368/ ec 1 68 6 e3 1e fc ff 370/ 69 10 4 0 84 10 85 0 378/ c0 7 81 0 0 0 3e 4 380/ 69 f0 4 0 85 0 e8 5 388/ 81 0 0 0 60 5 69 f0 390/ 2 0 85 0 e8 5 85 0 398/ 10 7 81 0 0 0 34 5 3a0/ 69 f0 4 0 3 10 0 0 3a8/ a9 0 d8 3 85 0 e8 5 3b0/ 85 0 14 7 81 0 0 0 3b8/ 34 5 69 f0 4 0 3 10 3c0/ 0 0 a9 0 f4 3 85 0 3c8/ 17 7 81 0 0 0 3e 4 3d0/ 69 f0 2 0 bd 0 6c 3 3d8/ e3 1e fa ff e3 2e fe ff 3e0/ e3 3e fc ff ec 13 0 0 3e8/ ec 12 2 0 ec e1 fe ff 3f0/ bd 0 10 4 e3 1e fa ff 3f8/ e3 2e fe ff e3 3e fc ff 400/ ec 12 0 0 ec 13 2 0 408/ ec e1 fe ff bd 0 10 4 410/ e3 1e fe ff 4 0 e3 2e 418/ 4 0 e0 1d 68 d2 4 0 420/ e3 1e 4 0 f2 21 a9 0 428/ 3c 4 fc 2 11 0 fd 0 430/ 10 0 1 0 69 10 1 0 438/ bd 0 24 4 4 0 6b f0 440/ 4 0 e0 3e 69 30 6 0 448/ e3 1e 4 0 f2 21 a9 0 450/ d2 4 3 20 25 0 a1 0 458/ c0 4 69 10 1 0 f2 21 460/ 69 10 1 0 3 20 73 0 468/ a1 0 92 4 ec e1 fe ff 470/ ec e3 fc ff e2 23 84 20 478/ 81 0 0 0 20 4 69 f0 480/ 2 0 e3 1e fe ff e3 3e 488/ fc ff 69 30 2 0 bd 0 490/ 4c 4 3 20 64 0 a1 0 498/ 4c 4 ec e1 fe ff ec e3 4a0/ fc ff e2 23 84 20 81 0 4a8/ 0 0 d4 4 69 f0 2 0 4b0/ e3 1e fe ff e3 3e fc ff 4b8/ 69 30 2 0 bd 0 4c 4 4c0/ fc 2 11 0 fd 0 10 0 4c8/ 1 0 69 10 1 0 bd 0 4d0/ 4c 4 4 0 e3 1e 4 0 4d8/ a9 0 ea 4 84 10 81 0 4e0/ 0 0 f8 4 69 f0 2 0 4e8/ 4 0 fd 0 11 0 30 0 4f0/ fd 0 10 0 1 0 4 0 4f8/ 6b f0 2 0 e3 1e 4 0 500/ a9 0 32 5 e0 21 79 20 508/ a 0 e0 31 71 30 a 0 510/ ec e3 fe ff 84 20 81 0 518/ 0 0 f8 4 69 f0 2 0 520/ e3 3e fe ff 69 30 30 0 528/ fc 3 11 0 fd 0 10 0 530/ 1 0 4 0 e3 2e 4 0 538/ e3 3e 6 0 f2 12 a9 0 540/ 5a 5 f2 43 a9 0 5a 5 548/ 6a 14 a1 0 5e 5 69 20 550/ 1 0 69 30 1 0 bd 0 558/ 3c 5 f2 43 6a 14 4 0 560/ e3 1e 4 0 e0 41 f3 20 568/ 10 0 51 20 2 0 a9 0 570/ 66 5 f3 30 11 0 fd 0 578/ 10 0 2 0 3 30 d 0 580/ a9 0 d6 5 3 30 8 0 588/ a9 0 a8 5 3 30 7f 0 590/ a9 0 a8 5 fc 3 11 0 598/ fd 0 10 0 1 0 f8 13 5a0/ 69 10 1 0 bd 0 66 5 5a8/ 2 14 b5 0 c4 5 f1 30 5b0/ 7f 0 6b 10 1 0 fc 3 5b8/ 11 0 fd 0 10 0 1 0 5c0/ bd 0 66 5 f1 30 7 0 5c8/ fc 3 11 0 fd 0 10 0 5d0/ 1 0 bd 0 66 5 fd 0 5d8/ 11 0 a 0 fd 0 10 0 5e0/ 1 0 f9 10 0 0 4 0 66c/ 0 0 0 0 61 61 72 64 674/ 76 61 72 6b 0 a 57 65 67c/ 6c 63 6f 6d 65 20 74 6f 684/ 20 41 6e 69 6d 61 6c 73 68c/ 2e a 0 a 54 68 69 6e 694/ 6b 20 6f 66 20 61 6e 20 69c/ 61 6e 69 6d 61 6c 20 61 6a4/ 6e 64 20 49 20 77 69 6c 6ac/ 6c 20 74 72 79 20 74 6f 6b4/ 20 67 75 65 73 73 20 77 6bc/ 68 61 74 20 69 74 20 69 6c4/ 73 2e a 0 49 20 63 75 6cc/ 72 72 65 6e 74 6c 79 20 6d4/ 6b 6e 6f 77 20 25 64 20 6dc/ 61 6e 69 6d 61 6c 73 2e 6e4/ a a 0 49 73 20 74 68 6ec/ 65 20 61 6e 69 6d 61 6c 6f4/ 20 79 6f 75 20 61 72 65 6fc/ 20 74 68 69 6e 6b 69 6e 704/ 67 20 6f 66 20 61 20 25 70c/ 73 3f 20 0 79 65 73 0 714/ 6e 6f 0 50 6c 65 61 73 71c/ 65 20 74 79 70 65 20 27 724/ 79 65 73 27 20 6f 72 20 72c/ 27 6e 6f 27 2e a 0 49 734/ 20 67 75 65 73 73 65 64 73c/ 20 79 6f 75 72 20 61 6e 744/ 69 6d 61 6c 21 21 21 a 74c/ a 0 49 20 63 6f 75 6c 754/ 64 20 6e 6f 74 20 67 75 75c/ 65 73 73 20 79 6f 75 72 764/ 20 61 6e 69 6d 61 6c 2e 76c/ 20 20 57 68 61 74 20 77 774/ 61 73 20 79 6f 75 72 20 77c/ 61 6e 69 6d 61 6c 3f 20 784/ 0 45 6e 74 65 72 20 61 78c/ 20 71 75 65 73 74 69 6f 794/ 6e 20 74 68 61 74 20 77 79c/ 6f 75 6c 64 20 64 69 73 7a4/ 74 69 6e 67 75 69 73 68 7ac/ 20 61 20 25 73 20 66 72 7b4/ 6f 6d 20 61 20 25 73 2e 7bc/ a 3e 20 0 54 68 65 20 7c4/ 63 6f 72 72 65 63 74 20 7cc/ 61 6e 73 77 65 72 20 66 7d4/ 6f 72 20 61 20 25 73 20 7dc/ 69 73 3f 20 0 a 0 3f 7e4/ 20 0 tkgate-2.0-b10/locale/it/examples.18/ex5/menagerie.gm000644 001751 001751 00000132563 10152673133 022723 0ustar00hansenhansen000000 000000 // // Copyright (C) 1987-2000 by Jeffery P. Hansen // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. // // Last edit by hansen on Fri Dec 1 14:34:44 2000 // // Microcode memory bank declarations microcode bank[31:0] iunit.m1; microcode bank[63:32] iunit.m2; map bank[7:0] iunit.map; macrocode bank[7:0] memory.m1; // Microcode field declarations // // Microcode branching. mpcop specifies the basic operation. // field mpcop[1:0]={ next=0, // Increment mpc reinit=1, // Restart CPU jmap=2, // Jump from map value jump=3 // Jump from condition }; // // Specifies the condition on which to jump if mpcop is "jump". // field mpccond[12:10]={ jne=0, // Jump if not equal jcarry=1, // Jump on carry jeq=2, // Jump if equal jlt=3, // Jump if less than jgt=4, // Jump if greater than jle=5, // Jump if less than or equal jge=6, // Jump if greater than or equal jmp=7 // Jump always }; // // Address to jump to if mpcop is "jump" and condition specified // by mpccond is true. This field can not be used at the same // time as the idata field. // field mpcaddr[9:2]; // // Specifies 8 bits of data to be used by the EUNIT. This field // can not be used on jump microinstructions. // field idata[9:2]; // // Specifies the A and B operands of the ALU. // // qreg Use Q register // din Use data in // idata Use idata field from microinstruction // reg Use register file // field aop[15:14]={qreg=0, din=1, idata=2, reg=3}; field bop[17:16]={qreg=0, din=1, idata=2, reg=3}; field ~ldir[13]; // Load instruction register field cin[18]; // Carry in field ~clq[19]; // Clear Q register field ~ldq[20]; // 16-bit load of Q register field ~lddata[21]; // Load EUNIT data from external bus field ~ldopr[22]; // Load operand register field ~wa[23]; // Write register file on SA field sa[27:24]; // Register address A field sb[31:28]; // Register address B // // These fields specify the ALU function. // field ALU_FUNC[36:32]; field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3}; field ALU_BCOMP[32]; field ALU_AZERO[33]; field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7}; field ~incpc[37]; // Increment PC field ~ldmar[38]; // Load MAR field ~ldmdr[39]; // Load MDR field ~ldpc[40]; // Load PC field ~rd[41]; // Read main memory field ~rdmdr[42]; // Read MDR onto external data bus field ~wrt[43]; // Write main memory field spc[44]; // Address main memory from PC field ~isa[45]; // Use sa address from macro instruction field ~isb[46]; // Use sb address from macro instruction field ~ifunc[47]; // Use function code from macro instruction field ~icond[48]; // Use branch condition from macro instruction field ~ldql[49]; // 8-bit load of lower half of Q register field ~ldqh[50]; // 8-bit load of upper half of Q register field ~dout[51]; // Output EUNIT data to external bus field ~ldcc[52]; // Load condition code register field ~ldhmdr[53]; // Load mdr from high byte of data bus field ~rdpc[54]; // Read PC onto external bus field ~incmar[55]; // Increment mar (can't use with incpc) field extra[63:56]; // Extra bits ////////////////////////////////////////////////////////////////////// // // +-+-+-+-+-+-+-+-+ // |7|6|5|4|3|2|1|0| // +-+-+-+-+-+-+-+-+ // // Basic instruction types are encoded by the high two bits of the // first byte of the instruction. For certain types (e.g., ALU // types) some bits are masked when forming the map address. Bits // contributing to the map vector are marked with a *. // // Move Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 1 1 s|a a|b b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // s = size (1 = byte, 0 = word) // aa = operand mode 1 // bb = operand mode 2 // // Single operand instruction (push, pop, call, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0| op |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // // Branch instruction (jmp, jne, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|cond |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * // // // ALU Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1| func |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * // // func = ALU function // a = operand mode // // Other instructions // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0| op |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15; operands basic { %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands runiop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; #1 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands wuniop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; // // Operands for move instructions // operands movoprs { %1,%2 = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; %1,(%2) = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; %1,#3(%2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; %1,(#2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),%2 = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#2 = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),(%2) = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#3(%2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; (%1),(#2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; #1(%2),%3 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#3 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; #1(%2),(%3) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; }; #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),%2 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#2 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; (#1),(%2) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),(#2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|1 1 1 1 1|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op nop { map nop : 0x3e; +0=0x3e; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op halt { map halt : 0x0; +0=0; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 1|0| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op cmp { map cmp_rr : 0x2; map cmp_ri : 0x3; +0[7:1]=0x1; operands basic; }; // Generic branch operation // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|x x x|b b| |0 0 0 0| reg1 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // br #7, loop // // Jump always to loop. 7 is a code indicating the condition always. // op jp { map br_r : 0xa0; map br_i : 0xa1; map br_d : 0xa2; map br_x : 0xa3; +0[7:5] = 0x5; operands { #1,%2 = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#2 = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; }; }; }; op jne { +0[7:5] = 0x5; +0[4:2] = 0x0; operands runiop; }; op jcarry { +0[7:5] = 0x5; +0[4:2] = 0x1; operands runiop; }; op jeq { +0[7:5] = 0x5; +0[4:2] = 0x2; operands runiop; }; op jlt { +0[7:5] = 0x5; +0[4:2] = 0x3; operands runiop; }; op jgt { +0[7:5] = 0x5; +0[4:2] = 0x4; operands runiop; }; op jle { +0[7:5] = 0x5; +0[4:2] = 0x5; operands runiop; }; op jge { +0[7:5] = 0x5; +0[4:2] = 0x6; operands runiop; }; op jmp { +0[7:5] = 0x5; +0[4:2] = 0x7; operands runiop; }; // Generic ALU operation // // Note this is not a real instruction but is here for illustrative // purposes only. Map entries must be made for each function code // to use this instruction for real. // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|x x x x x|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // alu #0x14, R1, R2 // // Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1. // //op alu { // map alu_rr : 0x40; // map alu_ri : 0x41; // +0[7:6] = 0x1; // operands { // #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; }; // #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; // }; //}; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op add { map alu_rr : 0x68; map alu_ri : 0x69; +0[7:0]=0x68; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 1|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op sub { map alu_rr : 0x6a; map alu_ri : 0x6b; +0[7:0]=0x6a; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mul { map xalu_rr : 0x60; map xalu_ri : 0x61; +0[7:0]=0x60; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op div { map xalu_rr : 0x78; map xalu_ri : 0x79; +0[7:0]=0x78; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mod { map xalu_rr : 0x70; map xalu_ri : 0x71; +0[7:0]=0x70; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|0 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op and { map alu_rr : 0x50; map alu_ri : 0x51; +0[7:0]=0x50; operands basic; }; // Call subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 0|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // call foo, #8 // // This will perform the following actions: // sp = sp - 2 // [sp] = pc // sp = sp - 2 // [sp] = fp // fp = sp // sp = sp+8 // pc = foo // op call { map call_ri : 0x80; map call_ii : 0x81; map call_di : 0x82; map call_xi : 0x83; +0[7:4] = 0x8; operands { #1,%2 = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1 = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; }; }; }; // Return from subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 1 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // ret // // This will perform the following actions: // sp = fp // fp = [sp] // sp = sp + 2 // pc = [sp] // sp = sp + 2 // // op ret { map ret : 0x4; +0=4; operands { - = { +1=0; }; }; }; // Push a word on the stack // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 1|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // pushw R1 // op pushw { map pushw_r : 0x84; map pushw_i : 0x85; map pushw_d : 0x86; map pushw_x : 0x87; +0[7:2]=0x21; operands runiop; }; op movb { map movb_rr : 0xf0; map movb_ri : 0xf1; map movb_rd : 0xf2; map movb_rx : 0xf3; map movb_dr : 0xf8; map movb_di : 0xf9; map movb_dd : 0xfa; map movb_dx : 0xfb; map movb_xr : 0xfc; map movb_xi : 0xfd; map movb_xd : 0xfe; map movb_xx : 0xff; +0[7:4]=0xf; operands movoprs; }; op movw { map movw_rr : 0xe0; map movw_ri : 0xe1; map movw_rd : 0xe2; map movw_rx : 0xe3; map movw_dr : 0xe8; map movw_di : 0xe9; map movw_dd : 0xea; map movw_dx : 0xeb; map movw_xr : 0xec; map movw_xi : 0xed; map movw_xd : 0xee; map movw_xx : 0xef; +0[7:4]=0xe; operands movoprs; }; ///////////////////////////////////////////////////////////////////////////// // // The microcode for the Menagerie CPU begins here. // // The CPU begins executing microinstuctions at address 0. The instructions // in the start block are executed only once. The next block consists of // the instuction fetch sequnce. The multiple labels account for partial // fetches that are done by some of the macrocode routines. // // For macro instructions which have no operands or have only only one operand, // there is usually a plain label for that instruction. For example the // microinstruction labeled 'ret' implements the 'ret' macroinstruction. This // mapping is defined by the 'map ret : 0x4;' line in the operand declaration // for the ret macroinstruction. // // For macro instructions with multiple addressing modes, labels are generally // of the form 'op_??' where each character after the '_' denotes an addressing // mode for an operand. By convension, the characters: // // r register direct // i immediate // d register indirect // x indexed // // are used. // begin microcode @ 0 start: clq; // Q <- 0 idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh; // Q.H <- 1 ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to 'fetch' mpcop=next; fetch: incpc spc rd ldmdr; // mdr <- [PC]; PC++; fetch1: incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; fetch2: mpcop=jmap rdmdr ldopr; // opr <- mdr; jump to opcode mpcop=next; halt: mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; // // Standard ALU operations (add, sub, and, or, etc.) // alu_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; alu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; // // 2-cycle ALU operations (mul, div, mod). These are the same as the alu_?? // ops except the ALU inputs and function code are held for 2 clock cycles // due to the longer delay in computing these functions. // xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg; // Ra (op) Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; xalu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=next ifunc isa isb aop=reg bop=qreg; // Ra (op) Q; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; cmp_rr: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22 isa isb aop=reg bop=reg ldcc; // Ra - Rb; CC; jump to fetch mpcop=next; cmp_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP aop=reg bop=qreg isa ldcc; // Ra - Q; CC; jump to fetch mpcop=next; br_i: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; btest: mpcop=jump mpcaddr=bdojmp icond; // jump to bdojmp if cond mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to fetch mpcop=next; bdojmp: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q, jump to fetch mpcop=next; br_r: mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10 isa aop=reg sb=0 bop=reg ALU_OP=add ldq; // Q <- Ra; jump to btest mpcop=next; br_d: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; br_x: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; call_ii: // Push the PC aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa extra=0x11; // SP-2 -> mar; SP = SP - 2; rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq; // Q = PC+4 ALU_AZERO ALU_OP=add bop=qreg dout ldmdr; // Q.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr; // Q.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; mpcop=next; // Push the FP aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa; // SP-2 -> mar; SP = SP - 2; ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr; // FP.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldhmdr; // SP.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; aop=reg sa=0xe bop=reg sb=0xf ALU_AZERO ALU_OP=add wa; // FP <- SP // Dec SP incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=qreg ALU_OP=add wa; // SP = SP + Q // PC = branch address incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q mpcop=next; call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_di: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; ret: ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12; // SP <- FP; mar <- FP; aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr; // SP <- SP+4; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr; // FP <- Q; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch1 ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q; jump fetch1 incpc spc rd ldmdr; // mdr <- [PC]; PC++; pushw_d: mpcop=next; pushw_x: mpcop=next; pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Rb.L; wrt; // [mar] <- mdr; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; pushw_i: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Q.L; wrt; // [mar] <- mdr; aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add isa isb wa aop=reg bop=reg ldcc extra=1 incpc spc rd ldmdr; // Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql; // Q.L <- Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata ALU_OP=add ldqh incpc spc rd ldmdr; // Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++; ALU_AZERO ALU_OP=add bop=qreg isa wa incpc spc rd ldmdr rdmdr ldir; // Ra <- Q; mdr <- [PC]; PC++; ir <- mdr; movw_ri: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_ri:incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0; // Q.H = 0; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mbrd: rd ldmdr; // mdr <- [mar] mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa; // Ra <- mdr ALU_OP=add idata=0 bop=idata aop=reg isa ldcc; // CC movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mwrd: rd ldmdr incmar; // mdr <- [mar++] rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql; // Q.L <- mdr; mdr <- [mar++] lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add isa wa ldcc; // Ra <- Q; CC mpcop=next; movb_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mbrd isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q; movw_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mbdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mwdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb.L wrt; // [mar] <- mdr; isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mbdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mwdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xx: mpcop=next extra=7; movb_xx: mpcop=next extra=7; movw_xd: mpcop=next extra=7; movb_xd: mpcop=next extra=7; movw_dd: mpcop=next extra=7; movb_dd: mpcop=next extra=7; movw_dx: mpcop=next extra=7; movb_dx: mpcop=next extra=7; mpcop=next extra=7; movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar; // mar <- Ra _mwdi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L wrt; // [mar] <- mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra _mbdi: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q movb_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q nop: mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15; mpcop=next; end ///////////////////////////////////////////////////////////////////////////// // // General notes on assembler // Registers are not saved accross function calls unless explicitly saved. // Functions return values in R1. // The register R0 is a special "always 0" register. Writing to R0 will have no // effect other than to set condition codes. // // begin macrocode @ 0x100 ttydata: .symbol 0x11 // tty data in/out register ttystatus: .symbol 0x10 // tty status register // // Nodes have the format (note that pointers are two bytes): // // struct node { // struct node *yes_b; // struct node *no_b; // char text[100]; // }; // nsize: .symbol 104 // Size of a tree node. That is "sizeof(struct node)". yes_b: .symbol 0 // Pointer to yes side no_b: .symbol 2 // Pointer to no side text: .symbol 4 // Text of node (animal name or question) // // Execution starts here. // start: movw SP, 0 // Initialize stack pointer movw FP, 0 // Initialize frame pointer call main // Call main program sdone: jmp sdone // Infinite loop when main ends //////////////////// // main() // .proc main movw R13, mend // Use R13 as a sort of heap pointer pushw welcome // Push the "Welcome to" message call printf // Print the message add SP,2 // Restore stack pointer movw (root),top_node // Initialize root node movw (known),1 // Know one animal loop: pushw think // Push the "Think of an animal..." message call printf // Print the message add SP,2 // Restore stack pointer movw R1, (known) // Put number of known animals in R1 pushw R1 // Push that number on the stack pushw numk // Push the "I know %d animals" message call printf // Call printf to print message add SP,4 // Restore stack movw R1,(root) // Put the root pointer in R1 pushw R1 // Push the pointer on the stack call find_animal // Ask questions to find animal add SP,2 // Restore the stack movw (root),R1 // Save new root jmp loop // Go back and guess another animal ret // Return to call (actually we should never get here) .end //////////////////// // find_animal(p) Find the animal. p is the root node in question tree // .proc find_animal tree: .symbol -2 // Local variable for tree pointer sub SP,2 // Allocate space for local variables movw R1, 4(FP) // Get the pointer to top node movw tree(FP),R1 // Store it in "tree" movw R2,yes_b(R1) // Get pointer in "yes" branch of tree cmp R2,0 // Compare against 0 jne get_response // If not 0, then treat as question node pushw R1 // Push pointer to top node call get_final // As the final question, and insert new node if necessary add SP,2 // Restore stack movw tree(FP),R1 // Save new root node in "tree" jmp done // All done, go to final cleanup get_response: movw R1,tree(FP) // Put current node pointer in R1 movw R4,R1 // R4 = R1 add R4,text // Add offset to make R4 pointer to question pushw R4 // Push text of question call print // Print question in tree node add SP,2 // Restore stack pushw qprompt // Push "?" prompt call print // Print the "? " add SP,2 // Restore stack pushw buf // Push address of buffer in which to get response call gets // Read response from user add SP,2 // Restore stack pushw buf // Push users response on stack pushw yes // Push "yes" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_yes // If so, user answered "yes", goto say_yes pushw buf // Push users response on stack pushw no // Push "no" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_no // If so, user answered "no", goto say_no pushw yesno // Push the "yes or no" error message call print // Print error message add SP,2 // Restore stack jmp get_response // Go back and ask again say_yes: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,yes_b(R1) // Put "yes" branch pointer in R2 pushw R2 // Push the yes branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw yes_b(R2),R1 // Update the "yes" branch jmp done // Finish up and prepare to return to caller say_no: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,no_b(R1) // Put "no" branch pointer in R2 pushw R2 // Push the no branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw no_b(R2),R1 // Update the "no" branch jmp done // Finish up and prepare to return to caller done: movw R1,tree(FP) // Put new root node in R1 ret // Return to caller .end //////////////////// // get_final(p) Ask final question (at node p), and update tree if necessary. // .proc get_final tree: .symbol -2 // Local variable for tree pointer animal_node: .symbol -4 // Local variable for new animal node pointer discrim_node: .symbol -6 // Local variable for new question node pointer sub SP,6 // Allocate space for local variables get_response: movw R1, 4(FP) // Get pointer to current node movw tree(FP),R1 // Save it in the 'tree' variable movw R1, 4(FP) // Put pointer to tree in R1 add R1,text // Advance R1 to animal name text pushw R1 // Push pointer to animal name on stack pushw isita // Push the "is it a..." string pointer call printf // Print the final question add SP,4 // Restore stack pushw buf // Push buffer for response call gets // Get the response add SP,2 // Restore the stack pushw buf // Push response on stack pushw yes // Push "yes" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq win // If so, we guessed the animal pushw buf // Push response on stack pushw no // Push "no" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq loose // If so, we did not guess the animal pushw yesno // Push the "yes or no" error message call print // Print it add SP,2 // Restore stack jmp get_response // Go back and ask again win: pushw winmsg // Push the (computer) win message call printf // Print it add SP,2 // Restore stack jmp done // All done, go finish up and return loose: pushw loosemsg // Push the (computer) loose message call printf // Print it add SP,2 // Restore stack pushw nsize // Push number of bytes in a node call malloc // Allocate memory for new animal node add SP,2 // Restore stack movw animal_node(FP),R1 // Put address of new node in animal_node movw yes_b(R1),0 // Intialize yes branches movw no_b(R1),0 // Intialize no branches add R1,text // Move R1 to point to text area pushw R1 // Push text buffer call gets // Get animal name add SP,2 // Restore stack movw R1,tree(FP) // Put pointer to exiting node in R1 add R1,text // Advance to the text field pushw R1 // Push pointer to old animal name movw R1,animal_node(FP) // Put pointer to new node in R1 add R1,text // Advance to the text field pushw R1 // Push new animal name on stack pushw dscrim // Push "what is difference" question call printf // Print the question add SP,6 // Restore pointer pushw nsize // Allocate memory for discrimination node call malloc // Allocate memory for new discrimination node add SP,2 // Restore stack movw discrim_node(FP),R1 // Put address of new node in discrim_node add R1,text // Advance pointer to text field of discrimination node pushw R1 // Push pointer to text buffer to input question call gets // Input the question add SP,2 // Restore pointer movw R1, (known) // Put number of known animals in R1 add R1,1 // Increment R1 movw (known),R1 // Store number of known animals back in "known" L1: movw R1,animal_node(FP) // Put pointer to new animal node in R1 add R1,text // Advance R1 to the text field pushw R1 // Push new animal name on stack pushw which // Push the "..correct answer for..." message. call printf // Print the message add SP,4 // Restore stack pushw buf // Push text buffer on stack call gets // Input a "yes" or "no" add SP,2 // Restore stack pushw buf // Push user response pushw yes // Push string "yes" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L2 // If so, goto L2. New animal is on "yes" branch pushw buf // Push user response pushw no // Push string "no" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L3 // If so, goto L3. New animal is on "no" branch pushw yesno // Push the "yes or no" error message call printf // Print it add SP,2 // Restore stack jmp L1 // Go back and ask again // // Insert new animal on yes branch of new question // L2: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R3 // Set yes branch to new node movw no_b(R1),R2 // Set no branch to old node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return // // Insert new animal on no branch of new question // L3: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R2 // Set yes branch to old node movw no_b(R1),R3 // Set no branch to new node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return done: movw R1,tree(FP) // Put tree pointer into return register R1 ret // Return to caller .end //////////////////// // malloc(n) -> p Allocate n bytes and return address in R1. Allocated memory // can not be freed. // .proc malloc movw R2, 4(FP) // Get number of bytes movw R1,R13 // Pointer to block of memory add R13,R2 // Update heap pointer ret .end //////////////////// // print(s) Print the string s // .proc print movw R1, 4(FP) // Get parameter (string address) loop: movb R2, (R1) // Put character R1 is pointing to in R2 jeq done // If it was a 0, this is the end of the string movb (ttydata),R2 // Move char to the tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Move pointer to next char jmp loop // Go back and print more done: ret .end //////////////////// // printf(s,...) Print the format string // .proc printf ptr: .symbol -2 // Local var for string pointer arg: .symbol -4 // Local var for argument pointer sub SP,4 // Allocate 4 bytes for local variables movw R3,FP // Assign R3 and add an offset so that it points add R3,6 // to the argument after the control string movw R1, 4(FP) // Put the control string pointer in R1 loop: movb R2, (R1) // Get the next char from control string jeq done // If it was a 0, this is the end of the string cmp R2, '%' // See if it is the '%' character jne cout // If not goto cout, and simply print it add R1,1 // Advance the string pointer movb R2,(R1) // Get the next char add R1,1 // Advance the string pointer again //switch (R2) L1: cmp R2,'s' // See if this is a "%s" conversion jne L2 // If not, goto L2 // case 's' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get address of string (from arguments) to print pushw R2 // Push it on the stack call print // Print the string add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more L2: cmp R2,'d' // See if this is a "%d" conversion jne loop // If not, ignore unknown conversion // case 'd' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get number (from arguments) to print pushw R2 // Push it on the stack call nprint // Go print the decimal number add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more cout: movb (ttydata),R2 // Put character in tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Advance to next char in control string jmp loop // Go back and print more done: ret // All done, return to caller .end //////////////////// // nprint(d) Print the number d in decimal // .proc nprint movw R1, 4(FP) // Move argument value to R1 jeq zprint // If it was zero, goto zprint pushw R1 // Push value to print on stack call nprint_aux // Call aux function to print number add SP,2 // Restore stack pointer ret // All done, return to caller zprint: movb (ttydata), '0' // Put the ascii value of '0' in tty data register movb (ttystatus), #1 // Signal tty controller to print character ret // All done, return to caller .end //////////////////// // nprint_aux(d) Print the number d in decimal (but prints nothing if d is zero) // .proc nprint_aux digit: .symbol -2 // Digit to print sub SP, 2 // Allocate space for local variables movw R1, 4(FP) // Get argument jeq done // If zero, return // To print the number n we compute // R2 = n / 10, and // R3 = n % 10 // We can then recursively call nprint_aux to print all // but the lowest digit, then print the lowest digit ourselves // movw R2, R1 // R2 = R1 div R2, 10 // R2 = R2 / 10 movw R3, R1 // R3 = R1 mod R3, 10 // R3 = R3 % 10 movw digit(FP),R3 // save lowest digit value pushw R2 // Push the higher digits call nprint_aux // Recursively call ourselves to print them add SP,2 // Restore stack pointer movw R3,digit(FP) // Restore digit value add R3, '0' // Add ascii for '0' to get ascii for digit movb (ttydata),R3 // Put char in tty data register movb (ttystatus),#1 // Signal tty controller to print character done: ret // All done, resturn to caller .end //////////////////// // strcmp(a,b) Compare strings a and b // .proc strcmp movw R2,4(FP) // Get pointer to first string movw R3,6(FP) // Get pointer to second string loop: movb R1,(R2) // Get next char from R2 jeq eos // If end of string, goto eos movb R4,(R3) // Get next char from R3 jeq eos // If end of string, goto eos sub R1,R4 // Compute difference in R1 jne done // If difference was not 0, we are done add R2,1 // Advance to next char in R2 add R3,1 // Advance to next char in R3 jmp loop // Go compare more eos: movb R4,(R3) // Get next char from R3 again (in case R1 was eos) sub R1,R4 // Compute difference in R1 done: ret // Return to caller, result is in R1 .end //////////////////// // gets(b) Reads chars from tty into b. // .proc gets movw R1, 4(FP) // Get pointer to buffer movw R4,R1 // Save starting pointer in R4 // // Poll for a characcter // cwait: movb R2,(ttystatus) // Get ready status and R2, #2 // Test if a char is ready jeq cwait // If not, go back and wait some more movb R3,(ttydata) // Get char from tty data register movb (ttystatus),#2 // Signal char received cmp R3,'\r' // Compare against return char jeq done // Exit if return received cmp R3,'\b' // Compare against backspace char jeq del_char // Delete char if backspace cmp R3,0x7f // Compare against delete char jeq del_char // Delete char if delete character movb (ttydata),R3 // Put char to echo in tty data register movb (ttystatus),#1 // Signal tty controller to print character movb (R1),R3 // Save in buffer add R1,1 // increment pointer jmp cwait // Go back and get another char del_char: cmp R1,R4 // Compare current pointer against start of line jle bell // If already at start of line, ring bell movb R3, 0x7f // Make sure delete char is in R3 sub R1,1 // Decrement pointer movb (ttydata),R3 // Echo backspace movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char bell: movb R3, 7 // Put bell char in R3 movb (ttydata),R3 // Echo bell movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char done: movb (ttydata),'\n' // Output newline movb (ttystatus),#1 // Signal tty controller to print character movb (R1),0 // Put eos in the string we just read ret // Return to caller .end buf: .bss 128 // Buffer for input known: .bss 2 // Number of animals known root: .bss 2 // root of animals tree top_node: .short 0 // Pointer to "yes" node .short 0 // Pointer to "no" node .byte "aardvark",0 // Animal name or question text welcome: .byte "\nWelcome to Animals.\n", 0 think: .byte "\nThink of an animal and I will try to guess what it is.\n", 0 numk: .byte "I currently know %d animals.\n\n", 0 isita: .byte "Is the animal you are thinking of a %s? ",0 yes: .byte "yes",0 no: .byte "no",0 yesno: .byte "Please type 'yes' or 'no'.\n",0 winmsg: .byte "I guessed your animal!!!\n\n",0 loosemsg: .byte "I could not guess your animal. What was your animal? ",0 dscrim: .byte "Enter a question that would distinguish a %s from a %s.\n> ",0 which: .byte "The correct answer for a %s is? ",0 nl: .byte "\n",0 qprompt: .byte "? ",0 mend: end tkgate-2.0-b10/locale/it/examples.18/ex4/trff.v000644 001751 001751 00000011743 10152673133 021565 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w14; //: /sn:0 {0}(654,415)(654,436)(603,436){1} //: {2}(599,436)(566,436)(566,415){3} //: {4}(601,438)(601,455){5} supply1 w17; //: /sn:0 {0}(620,315)(620,292){1} supply1 w12; //: /sn:0 {0}(625,86)(625,63){1} supply0 w13; //: /sn:0 {0}(650,191)(650,213)(608,213){1} //: {2}(604,213)(571,213)(571,191){3} //: {4}(606,215)(606,231){5} wire w6; //: /sn:0 {0}(625,119)(625,103){1} wire w16; //: /sn:0 {0}(620,345)(620,332){1} wire Q; //: {0}(765,383)(656,383){1} //: {2}(654,381)(654,273)(532,273)(532,184){3} //: {4}(534,182)(557,182){5} //: {6}(532,180)(532,127)(611,127){7} //: {8}(652,383)(622,383){9} //: {10}(620,381)(620,362){11} //: {12}(618,383)(566,383)(566,398){13} //: {14}(654,385)(654,398){15} wire _Q; //: /dp:1 {0}(759,159)(694,159){1} //: {2}(690,159)(652,159){3} //: {4}(648,159)(627,159){5} //: {6}(625,157)(625,136){7} //: {8}(623,159)(571,159)(571,174){9} //: {10}(650,161)(650,174){11} //: {12}(692,161)(692,252)(584,252)(584,321){13} //: {14}(586,323)(606,323){15} //: {16}(584,325)(584,406)(640,406){17} wire R; //: /dp:7 {0}(606,353)(535,353){1} //: {2}(531,353)(503,353){3} //: {4}(501,351)(501,336){5} //: {6}(499,353)(442,353){7} //: {8}(533,355)(533,406)(552,406){9} wire S; //: /dp:7 {0}(611,94)(591,94){1} //: {2}(587,94)(505,94){3} //: {4}(503,92)(503,81){5} //: {6}(501,94)(436,94){7} //: {8}(589,96)(589,182)(636,182){9} //: enddecls //: supply1 g4 (w12) @(636,63) /sn:0 /anc:1 /w:[ 1 ] //: joint g8 (w13) @(606, 213) /anc:1 /w:[ 1 -1 2 4 ] //: joint g34 (S) @(503, 94) /w:[ 3 4 6 -1 ] pmos g3 (.Z(w12), .S0(w6), .G0(S)); //: @(619,94) /sn:0 /anc:1 /w:[ 0 1 0 ] nmos g13 (.Z(w14), .S0(Q), .G0(_Q)); //: @(648,406) /sn:0 /anc:1 /w:[ 0 15 17 ] pmos g2 (.Z(w6), .S0(_Q), .G0(Q)); //: @(619,127) /sn:0 /anc:1 /w:[ 0 7 7 ] nmos g1 (.Z(w13), .S0(_Q), .G0(S)); //: @(644,182) /sn:0 /anc:1 /w:[ 0 11 9 ] //: joint g11 (S) @(589, 94) /anc:1 /w:[ 1 -1 2 8 ] //: supply1 g16 (w17) @(631,292) /sn:0 /anc:1 /w:[ 1 ] //: comment g28 /dolink:0 /link:"" @(26,299) /anc:1 //: /line:"3) Rimetti l'interruttore \"S\" in posizione \"off\"" //: /line:"e inserisci di nuovo 10 .. 20 spazi. " //: /line:"\"Q\" e \"_Q\" mantengono il loro valore." //: /end //: joint g10 (Q) @(654, 383) /anc:1 /w:[ 1 2 8 14 ] led g32 (.I(Q)); //: @(772,383) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g19 (R) @(425,353) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: comment g27 /dolink:0 /link:"" @(25,193) /anc:1 //: /line:"2) Inserisci da 10 a 20 spazi per far avanzare" //: /line:"la simulazione." //: /line:"Osserva che sia \"Q\" che \"_Q\" hanno valore" //: /line:"sconosciuto." //: /line:"Ora clicca sull'interruttore \"S\" e inserisci " //: /line:"di nuovo fra 10 e 20 spazi. " //: /line:"\"Q\" passa al livello alto e \"_Q\" a quello basso." //: /end //: switch g6 (S) @(419,94) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: joint g9 (_Q) @(692, 159) /anc:1 /w:[ 1 -1 2 12 ] //: joint g7 (Q) @(620, 383) /anc:1 /w:[ 9 10 12 -1 ] led g31 (.I(_Q)); //: @(766,159) /sn:0 /R:3 /w:[ 0 ] /type:0 pmos g15 (.Z(w17), .S0(w16), .G0(_Q)); //: @(614,323) /sn:0 /anc:1 /w:[ 0 1 15 ] //: joint g20 (w14) @(601, 436) /anc:1 /w:[ 1 -1 2 4 ] //: comment g29 /dolink:0 /link:"" @(26,355) /anc:1 //: /line:"4) Ora metti \"R\" il posizione \"on\" (click)" //: /line:"e inserisci ancora 10 .. 20 spazi." //: /line:"\"_Q\" commuta allo stato alto mentre \"Q\"" //: /line:"a quello basso." //: /end //: supply0 g17 (w14) @(601,461) /sn:0 /anc:1 /w:[ 5 ] //: comment g25 /dolink:0 /link:"" @(35,22) /anc:1 //: /line:"Questo circuito è un semplice flip-flop realizzato " //: /line:"a livello di transistor con due porte NOR in tecnica CMOS." //: /line:"" //: /end //: supply0 g5 (w13) @(606,237) /sn:0 /anc:1 /w:[ 5 ] pmos g14 (.Z(w16), .S0(Q), .G0(R)); //: @(614,353) /sn:0 /anc:1 /w:[ 0 11 0 ] //: joint g36 (R) @(501, 353) /w:[ 3 4 6 -1 ] //: joint g24 (_Q) @(625, 159) /anc:1 /w:[ 5 6 8 -1 ] //: joint g21 (Q) @(532, 182) /anc:1 /w:[ 4 6 -1 3 ] //: joint g23 (_Q) @(650, 159) /anc:1 /w:[ 3 -1 4 10 ] led g35 (.I(R)); //: @(501,329) /sn:0 /w:[ 5 ] /type:0 nmos g0 (.Z(w13), .S0(_Q), .G0(Q)); //: @(565,182) /sn:0 /anc:1 /w:[ 3 9 5 ] //: joint g22 (R) @(533, 353) /anc:1 /w:[ 1 -1 2 8 ] //: comment g26 /dolink:0 /link:"" @(26,101) /anc:1 //: /line:"1) Attiva la simulazione e aggancia" //: /line:"delle sonde ai segnali \"S\", \"R\", \"Q\" e \"_Q\"." //: /line:"Il segnale \"_Q\" è \"Q\" sopralineato." //: /line:"" //: /end nmos g12 (.Z(w14), .S0(Q), .G0(R)); //: @(560,406) /sn:0 /anc:1 /w:[ 3 13 9 ] //: joint g18 (_Q) @(584, 323) /anc:1 /w:[ 14 13 -1 16 ] led g33 (.I(S)); //: @(503,74) /sn:0 /w:[ 5 ] /type:0 //: comment g30 /dolink:0 /link:"" @(23,420) /anc:1 //: /line:"5) Ritorna con \"R\" in posizione \"off\"" //: /line:"e inserisci 10 .. 20 spazi." //: /line:"\"Q\" e \"_Q\" mantengono il loro valore." //: /end endmodule tkgate-2.0-b10/locale/it/examples.18/ex3/counter.v000644 001751 001751 00000005737 10152673133 022310 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w11; //: /sn:0 {0}(269,197)(269,181)(248,181){1} wire [7:0] w4; //: /sn:0 {0}(208,114)(208,167){1} wire w8; //: /sn:0 {0}(263,269)(325,269)(325,283){1} wire w12; //: /sn:0 {0}(200,181)(190,181){1} wire ck; //: /dp:1 {0}(187,264)(56,264){1} wire [7:0] w5; //: /sn:0 {0}(224,196)(224,254){1} wire [7:0] reg_out; //: {0}(224,275)(224,332)(297,332)(297,173){1} //: {2}(299,171)(379,171){3} //: {4}(297,169)(297,145)(240,145)(240,167){5} wire w9; //: /sn:0 {0}(263,259)(324,259)(324,245){1} //: enddecls //: comment g8 /dolink:0 /link:"" @(19,191) //: /line:"2) Aggancia una sonda" //: /line:"alla linea del clock" //: /line:"cliccando doppio" //: /line:"sul collegamento." //: /end clock g4 (.Z(ck)); //: @(43,264) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g13 /dolink:0 /link:"" @(23,412) //: /line:"7) Inserisci Tab per far avanzare la simulazione di un ciclo di clock." //: /line:"Siccome la linea CLR è attiva bassa, il registro viene azzerato." //: /line:"Imposta ora la linea CLR su \"on\" (commuta l'interruttore)" //: /line:"e continua la simulazione con il tasto Tab." //: /line:"Osserva il valore del registro che incrementa ad ogni ciclo di clock." //: /end //: dip g3 (w4) @(208,104) /sn:0 /w:[ 0 ] /st:1 add g2 (.A(w4), .B(reg_out), .S(w5), .CI(w11), .CO(w12)); //: @(224,183) /sn:0 /w:[ 1 5 0 1 0 ] //: switch g1 (w8) @(325,297) /sn:0 /R:1 /w:[ 1 ] /st:0 //: comment g11 /dolink:0 /link:"" @(348,218) //: /line:"5) Assicurati che " //: /line:"la linea CLR sia \"off\"" //: /line:"per azzerare il registro." //: /end //: comment g10 /dolink:0 /link:"" @(251,90) //: /line:"4) Clicca sull'interruttore e imposta il valore 1" //: /line:"nel form che appare. Conferma con \"Apply\"." //: /end //: supply0 g6 (w11) @(269,203) /sn:0 /w:[ 0 ] //: comment g9 /dolink:0 /link:"" @(170,337) //: /line:"3) Aggancia una sonda " //: /line:"all'uscita del registro" //: /line:"cliccando doppio" //: /line:"sul collegamento." //: /end //: switch g7 (w9) @(324,232) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g15 /dolink:0 /link:"" @(25,501) /sn:0 //: /line:"8) Modifica il valore dato dall'interruttore ad 8 vie: inserisci 2." //: /line:"Continua la simulazione per alcuni cicli di clock e osserva come" //: /line:"il registro ora incrementa a passi di 2." //: /end led g17 (.I(reg_out)); //: @(386,171) /sn:0 /R:3 /w:[ 3 ] /type:2 //: joint g14 (reg_out) @(297, 171) /w:[ 2 4 -1 1 ] //: comment g5 /dolink:0 /link:"" @(15,11) //: /line:"Contatore a 8-Bit" //: /line:"" //: /line:"1) Attiva la simulazione con \"Ctl-S b\"" //: /line:"" //: /end register g0 (.Q(reg_out), .D(w5), .EN(w8), .CLR(w9), .CK(ck)); //: @(224,264) /sn:0 /w:[ 0 1 0 0 0 ] //: comment g12 /dolink:0 /link:"" @(350,285) //: /line:"6) Assicurati che" //: /line:"la linea EN sia \"off\"." //: /end endmodule tkgate-2.0-b10/locale/it/examples.18/ex2/flipflop.v000644 001751 001751 00000010435 10152673133 022432 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 module main; //: root_module supply0 w4; //: /sn:0 {0}(661,215)(661,212)(640,212)(640,229){1} supply0 w3; //: /sn:0 {0}(499,211)(499,207)(483,207)(483,226){1} supply0 w0; //: /sn:0 {0}(346,226)(346,200)(362,200)(362,210){1} wire w7; //: /sn:0 {0}(494,247)(504,247){1} wire ww; //: /sn:0 /dp:9 {0}(336,226)(336,171){1} //: {2}(338,169)(471,169){3} //: {4}(475,169)(630,169)(630,229){5} //: {6}(473,171)(473,226){7} //: {8}(334,169)(178,169){9} wire w16; //: /sn:0 {0}(435,235)(446,235)(446,242)(462,242){1} wire w19; //: /sn:0 {0}(555,270)(564,270)(564,247)(574,247){1} wire w15; //: /sn:0 {0}(458,122)(458,139)(380,139)(380,235){1} //: {2}(382,237)(414,237){3} //: {4}(378,237)(357,237){5} //: {6}(380,239)(380,272)(534,272){7} wire zz; //: /sn:0 /dp:1 {0}(175,344)(339,344){1} //: {2}(343,344)(476,344){3} //: {4}(480,344)(635,344)(635,261){5} //: {6}(478,342)(478,258){7} //: {8}(341,342)(341,258){9} wire w1; //: /sn:0 {0}(357,247)(367,247)(367,277)(312,277)(312,242)(325,242){1} wire [2:0] w17; //: /sn:0 {0}(448,116)(448,91){1} wire w12; //: /sn:0 {0}(595,245)(619,245){1} wire w11; //: /sn:0 {0}(438,122)(438,152)(677,152)(677,188){1} //: {2}(675,190)(564,190)(564,242)(574,242){3} //: {4}(677,192)(677,240)(651,240){5} wire w13; //: /sn:0 {0}(651,250)(661,250){1} wire w5; //: /sn:0 {0}(494,237)(518,237){1} //: {2}(520,235)(520,194){3} //: {4}(520,190)(520,133)(448,133)(448,122){5} //: {6}(518,192)(404,192)(404,232)(414,232){7} //: {8}(520,239)(520,267)(534,267){9} //: enddecls //: supply0 g8 (w3) @(499,217) /sn:0 /w:[ 0 ] clock g4 (.Z(zz)); //: @(162,344) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: supply0 g3 (w0) @(362,216) /sn:0 /w:[ 1 ] led g13 (.I(w17)); //: @(448,84) /sn:0 /w:[ 1 ] /type:1 ff g2 (.Q(w11), ._Q(w13), .D(w12), .EN(w4), .CLR(ww), .CK(zz)); //: @(635,245) /sn:0 /w:[ 5 0 1 1 5 5 ] ff g1 (.Q(w5), ._Q(w7), .D(w16), .EN(w3), .CLR(ww), .CK(zz)); //: @(478,242) /sn:0 /w:[ 0 0 1 1 7 7 ] //: joint g16 (w5) @(520, 192) /w:[ -1 4 6 3 ] //: joint g11 (zz) @(341, 344) /w:[ 2 8 1 -1 ] //: comment g10 /dolink:0 /link:"" @(103,373) /sn:0 //: /line:"Simulazione di un circuito sequenziale" //: /line:"" //: /line:"1) Clicca con il tasto destro sul collegamento del clock e scegli \"Properties\"." //: /line:" Nel formulario che appare inserisci il nome \"ck\" e disattiva il pulsante \"Hide Name\"." //: /line:" \"OK\"" //: /line:"2) Fai lo stesso sul collegamento dell'interruttore, inserisci il nome \"_clr\" e " //: /line:" disattiva \"Hide Name\". \"OK\"" //: /line:" Nota come il carattere \"_\" che precede il nome di un segnale viene rappresentato come " //: /line:" sopralineatura (segnale attivo basso)." //: /line:"3) Attiva la simulazione e aggancia le sonde ai segnali \"ck\", \"clr\" e a quelli che vanno" //: /line:" al visualizzatore. " //: /line:" Clicca su \"Play per entrare in modalità  di simulazione continua." //: /line:" Il visualizzatore di timing traccia i segnali senza fermarsi." //: /line:"4) Ritorna in modo \"ciclo singolo\" cliccando sull'icona \"Pause\" oppure inserendo il " //: /line:" carattere Tab." //: /line:" Inserisci ora qualche carattere Tab e osserva come la simulazione avanza di un ciclo" //: /line:" per ogni Tab." //: /line:" Nota il tempo di \"overstep\": la simulazione continua per un certo tempo oltre " //: /line:" il fianco attivo del clock." //: /line:" " //: /end and g19 (.I0(w5), .I1(w15), .Z(w19)); //: @(545,270) /sn:0 /w:[ 9 7 0 ] //: joint g6 (ww) @(336, 169) /w:[ 2 -1 8 1 ] //: supply0 g9 (w4) @(661,221) /sn:0 /w:[ 0 ] //: joint g7 (ww) @(473, 169) /w:[ 4 -1 3 6 ] //: joint g20 (w5) @(520, 237) /w:[ -1 2 1 8 ] xor g15 (.I0(w5), .I1(w15), .Z(w16)); //: @(425,235) /sn:0 /w:[ 7 3 0 ] //: joint g17 (w15) @(380, 237) /w:[ 2 1 4 6 ] concat g14 (.I0(w15), .I1(w5), .I2(w11), .Z(w17)); //: @(448,117) /sn:0 /R:1 /w:[ 0 5 0 0 ] /dr:0 //: switch g5 (ww) @(161,169) /sn:0 /w:[ 9 ] /st:1 //: joint g21 (w11) @(677, 190) /w:[ -1 1 2 4 ] ff g0 (.Q(w15), ._Q(w1), .D(w1), .EN(w0), .CLR(ww), .CK(zz)); //: @(341,242) /sn:0 /w:[ 5 0 1 0 0 9 ] xor g18 (.I0(w11), .I1(w19), .Z(w12)); //: @(585,245) /sn:0 /w:[ 3 1 0 ] //: joint g12 (zz) @(478, 344) /w:[ 4 6 3 -1 ] endmodule tkgate-2.0-b10/locale/it/examples.18/ex1/combinational.v000644 001751 001751 00000011747 10152673133 023444 0ustar00hansenhansen000000 000000 //: version "1.8.3" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire A0; //: /dp:3 {0}(173,94)(163,94){1} //: {2}(159,94)(95,94){3} //: {4}(161,96)(161,154)(173,154){5} wire w6; //: /sn:0 {0}(215,171)(215,138){1} wire S1; //: {0}(303,253)(257,253){1} wire w14; //: /sn:0 {0}(211,329)(211,296){1} wire w4; //: /sn:0 {0}(239,97)(214,97){1} //: {2}(210,97)(194,97){3} //: {4}(212,99)(212,117){5} wire w19; //: /sn:0 {0}(231,413)(211,413){1} //: {2}(209,411)(209,350){3} //: {4}(209,415)(209,438){5} wire w0; //: /sn:0 {0}(239,92)(219,92){1} //: {2}(217,90)(217,50){3} //: {4}(217,94)(217,117){5} wire w3; //: /sn:0 {0}(210,171)(210,157)(194,157){1} wire C3; //: {0}(303,533)(205,533)(205,513){1} wire w21; //: /sn:0 {0}(202,492)(202,478)(186,478){1} wire A2; //: /dp:3 {0}(165,415)(155,415){1} //: {2}(151,415)(96,415){3} //: {4}(153,417)(153,475)(165,475){5} wire B2; //: {0}(100,480)(142,480){1} //: {2}(146,480)(165,480){3} //: {4}(144,478)(144,420)(165,420){5} wire B1; //: {0}(98,317)(142,317){1} //: {2}(146,317)(169,317){3} //: {4}(144,315)(144,257)(169,257){5} wire S0; //: {0}(303,95)(260,95){1} wire w18; //: /sn:0 {0}(231,418)(206,418){1} //: {2}(202,418)(186,418){3} //: {4}(204,420)(204,438){5} wire w22; //: /sn:0 {0}(207,492)(207,459){1} wire w11; //: /sn:0 {0}(236,250)(215,250){1} //: {2}(213,248)(213,192){3} //: {4}(213,252)(213,275){5} wire A1; //: /dp:3 {0}(169,252)(159,252){1} //: {2}(155,252)(96,252){3} //: {4}(157,254)(157,312)(169,312){5} wire w10; //: /sn:0 {0}(236,255)(210,255){1} //: {2}(206,255)(190,255){3} //: {4}(208,257)(208,275){5} wire w13; //: /sn:0 {0}(206,329)(206,315)(190,315){1} wire B0; //: {0}(93,159)(144,159){1} //: {2}(148,159)(173,159){3} //: {4}(146,157)(146,99)(173,99){5} wire S2; //: {0}(303,416)(252,416){1} //: enddecls //: switch g4 (B0) @(76,159) /sn:0 /w:[ 0 ] /st:1 nand g8 (.I0(w4), .I1(w0), .Z(w6)); //: @(215,128) /sn:0 /R:3 /w:[ 5 5 1 ] //: switch g3 (w0) @(217,37) /sn:0 /R:3 /w:[ 3 ] /st:0 xor g13 (.I0(A1), .I1(B1), .Z(w10)); //: @(180,255) /sn:0 /w:[ 0 5 3 ] //: comment g34 /dolink:0 /link:"" @(352,22) //: /line:"Questo circuito è un sommatore da tre bit." //: /line:"" //: /line:"Attiva la simulazione cliccando sull'icona" //: /line:"del \"Logic Analyzer\"." //: /line:"Con un doppio click, aggancia sonde ai segnali " //: /line:"S0, S1, S2 e C3 ed a tutti gli altri segnali" //: /line:"che vuoi visualizzare. " //: /line:"Attiva la simulazione continua cliccando " //: /line:"su \"Play\". In questa modalità  di funzionamento, " //: /line:"appena commuti uno degli interruttori (click " //: /line:"sull'interruttore), il simulatore si riattiva " //: /line:"e calcola finchè tutti i valori sono di nuovo " //: /line:"stabili." //: /line:"Termina la simulazione con un click su \"stop\"" //: /line:"nella barra degli utensili." //: /end led g37 (.I(S2)); //: @(310,416) /sn:0 /R:3 /w:[ 0 ] /type:0 xor g2 (.I0(w0), .I1(w4), .Z(S0)); //: @(250,95) /sn:0 /w:[ 0 0 1 ] xor g1 (.I0(A0), .I1(B0), .Z(w4)); //: @(184,97) /sn:0 /w:[ 0 5 3 ] nand g11 (.I0(w3), .I1(w6), .Z(w11)); //: @(213,182) /sn:0 /R:3 /w:[ 0 0 3 ] nand g16 (.I0(A1), .I1(B1), .Z(w13)); //: @(180,315) /sn:0 /w:[ 5 3 1 ] //: joint g10 (w4) @(212, 97) /w:[ 1 -1 2 4 ] //: joint g28 (A2) @(153, 415) /w:[ 1 -1 2 4 ] nand g19 (.I0(w10), .I1(w11), .Z(w14)); //: @(211,286) /sn:0 /R:3 /w:[ 5 5 1 ] nand g27 (.I0(A2), .I1(B2), .Z(w21)); //: @(176,478) /sn:0 /w:[ 5 3 1 ] //: joint g32 (w18) @(204, 418) /w:[ 1 -1 2 4 ] //: joint g6 (A0) @(161, 94) /w:[ 1 -1 2 4 ] led g38 (.I(C3)); //: @(310,533) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g7 (B0) @(146, 159) /w:[ 2 4 1 -1 ] //: joint g9 (w0) @(217, 92) /w:[ 1 2 -1 4 ] //: switch g15 (B1) @(81,317) /sn:0 /w:[ 0 ] /st:1 //: joint g20 (w11) @(213, 250) /w:[ 1 2 -1 4 ] //: joint g31 (w19) @(209, 413) /w:[ 1 2 -1 4 ] //: joint g17 (A1) @(157, 252) /w:[ 1 -1 2 4 ] xor g25 (.I0(w19), .I1(w18), .Z(S2)); //: @(242,416) /sn:0 /w:[ 0 0 1 ] //: joint g29 (B2) @(144, 480) /w:[ 2 4 1 -1 ] nand g5 (.I0(A0), .I1(B0), .Z(w3)); //: @(184,157) /sn:0 /w:[ 5 3 1 ] xor g14 (.I0(w11), .I1(w10), .Z(S1)); //: @(247,253) /sn:0 /w:[ 0 0 1 ] //: joint g21 (w10) @(208, 255) /w:[ 1 -1 2 4 ] xor g24 (.I0(A2), .I1(B2), .Z(w18)); //: @(176,418) /sn:0 /w:[ 0 5 3 ] led g36 (.I(S1)); //: @(310,253) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g23 (A2) @(79,415) /sn:0 /w:[ 3 ] /st:0 //: switch g0 (A0) @(78,94) /sn:0 /w:[ 3 ] /st:0 nand g22 (.I0(w13), .I1(w14), .Z(w19)); //: @(209,340) /sn:0 /R:3 /w:[ 0 0 3 ] //: switch g26 (B2) @(83,480) /sn:0 /w:[ 0 ] /st:0 led g35 (.I(S0)); //: @(310,95) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g12 (A1) @(79,252) /sn:0 /w:[ 3 ] /st:0 //: joint g18 (B1) @(144, 317) /w:[ 2 4 1 -1 ] nand g30 (.I0(w18), .I1(w19), .Z(w22)); //: @(207,449) /sn:0 /R:3 /w:[ 5 5 1 ] nand g33 (.I0(w21), .I1(w22), .Z(C3)); //: @(205,503) /sn:0 /R:3 /w:[ 0 0 1 ] endmodule tkgate-2.0-b10/locale/cs/messages000644 001751 001751 00000074652 11134010406 017410 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Aug 5 11:24:01 2004 # Do ÄeÅ¡tiny pÅ™eložila Katarína Bubli Machálková (K.Machalkova@pod.cvut.cz) # Poslední aktualizace 3.srpna 2004 \font-encoding iso8859-2 \messages-encoding utf-8 \verilog-encoding iso8859-2 \language Czech ############################################################################## # # basic strings # b.dismiss ZruÅ¡it b.close Zavřít b.ok OK b.clear Znova b.cancel ZruÅ¡it b.open Otevřít... b.bitw Bitová Šířka b.in Vstup b.out Výstup b.inout Vst./Výst. b.browse Procházet... b.label Popisek b.find Najít b.edit Upravit... b.add PÅ™idat... b.delete Smazat b.deleteb Smazat... b.apply Použít b.anchor Ukotvit b.tech Technologie ############################################################################## # Menu strings # file Soubor edit Úpravy tool Nástroje simulate Simulace module Modul gate Hradlo make PÅ™idat circ Obvod new Nový open Otevřít... openlib Otevřít Knihovnu... save Uložit saveas Uložit Jako... print Tisk... options Možnosti... quit UkonÄit undo ZpÄ›t redo Znovu cut Vyjmout copy Kopírovat paste Vložit selall Vybrat VÅ¡e find Najít... algnv Uspořádat Ver. algnh Uspořádat Horiz. zoomin ZvÄ›tÅ¡it zoomout ZmenÅ¡it move PÅ™esunout/Spojit delg Smazat Hradlo cutw PÅ™eruÅ¡it VodiÄ inv Invertovat bitw Bitová Šířka debug Debug rot0 OtoÄit 0 rot90 OtoÄit 90 rot180 OtoÄit 180 rot270 OtoÄit 270 simbegin ZaÄít Simulaci simend UkonÄit Simulaci simadprobe PÅ™idat/Smazat Sondu simrun Spustit simpause PÅ™eruÅ¡it simstep Posun o Jednotku(y) ÄŒasu simcycle Posun o Hodinový Cyklus simbreak Kontrolní Bod... simscript Spustit Skript... simload Nahrát Obraz PamÄ›ti... simdump Uložit Obraz PamÄ›ti... modopen Otevřít modclose Zavřít modseti Nastavit Rozhraní modediti Upravit Rozhraní... modnew Nový... moddel Smazat... modcopy Kopírovat... modrename PÅ™ejmenovat... modclaim Konvertovat... circprop Vlastnosti Obvodu... cpath Citlivá Cesta... gataddin PÅ™idat Vstup gataddout PÅ™idat Výstup gataddinout PÅ™idat Vst./Výst. gatiochg ZmÄ›nit Typ gatanchor Ukotvit Vybrané gatunanchor Uvolnit Vybrané gatprop Vlastnosti... gatrep VytvoÅ™it Kopii gatdel Smazat gatsettech Nastavit Technologii gmswitch I/O gmgate Hradlo gmredgate Redukce gmmsi MSI gmalu ALU gmmem Paměť gmmod Modul gmcomment Komentář gmframe Rámec gmxswitch SpínaÄ gmdip DIP SpínaÄ gmground UzemnÄ›ní gmvdd Vdd gmmerge Spojení VodiÄů gmclock Hodiny gm.led LED gm.ledbar LED Panel gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Přímý kód) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf BudiÄ SbÄ›rnice gminv Invertor gmtribuf 3stav. BudiÄ SbÄ›rnice gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd SÄítaÄka gmmult NásobiÄka gmdiv DÄ›liÄka gmlshift Posun Doleva gmrshift Posun Doprava gmarshift Arit.Posun Doprava gmroll Rotace gmreg Registr gmff Klopný Obvod gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Dekodér gm14dec 1-4 Dekodér gm18dec 1-8 Dekodér gmmodinst Instance Modulu gmmodin Vstup Modulu gmmodout Výstup Module gmmodinout Vst./Výst. Modulu addwireseg PÅ™idat Segment VodiÄe help NápovÄ›da hlpabout O programu... hlplicense Licence... hlpdoc Dokumentace... hlptut Návody hlpexample Příklady exampcomb KombinaÄní Logika examp3bit 3-Bitový ČítaÄ examp8bit 8-Bitový ČítaÄ examptrff Transistorový KO exampcpu CviÄný CPU tutwelcome TkGate Intro tutcreate VytvoÅ™ení Obvodu tutedit1 Úpravy Obvodu (1) tutedit2 Úpravy Obvodu (2) tutmods Použití Modulů tutsim Simulace Obvodu # Scope Menu menu.sc.prtrace Tisknout Stopu... menu.sc.close Zavřít menu.sc.trace Stopa menu.sc.zoomin ZvÄ›tÅ¡it menu.sc.zoomout ZmenÅ¡it scope.emptymsg Dvojitým kliknutím na vodiÄ pÅ™idejte nebo smažte stopu. comment.empty [Dvojitým kliknutím pÅ™idejte text.] ############################################################################## # Interface strings # ifile Soubor imodule Modul iblmodule Moduly iports Konektory ibits Bity ############################################################################# # Net Dialog Box # db.net.name Název SítÄ› db.net.hide Skrýt Jméno db.net.bits Bitová Šířka db.net.port Typ Konektoru db.net.in Vstup db.net.out Výstup db.net.inout Vst./Výst. db.net.inets SítÄ› ############################################################################## # Gate dialog box # db.gate.signam Název Signálu db.gate.portnam Název Konektoru db.gate.iotype Typ db.gate.bitw Bitová Šířka db.gate.cyclew Šířka Cyklu db.gate.phase Fáze db.gate.duty Střída db.gate.port Konektor db.gate.bitws Bity db.gate.gtype Typ Hradla db.gate.gname Název Hradla db.gate.hidenam Skrýt Název db.gate.anchor Ukotvit db.gate.cpbreak PÅ™eruÅ¡ení Citlivé Cesty db.gate.butstate Stav TlaÄítka db.gate.dipval Hodnota PÅ™epínaÄe db.gate.memfilenam Soubor s Obsahem PamÄ›ti db.gate.modname Funkce db.gate.islink Text Je Hypertextový Odkaz db.gate.link Odkaz na Soubor db.gate.findw Hledat Pouze VodiÄe db.gate.findg Hledat Pouze Hradla db.gate.findwg Hledat VodiÄe i Hradla db.gate.general Obecné db.gate.details Detaily db.gate.ports Konektory db.gate.delay ZpoždÄ›ní db.gate.stddelay Standardní ZpoždÄ›ní db.gate.custdelay Definované ZpoždÄ›ní db.gate.extbar Použít RozÅ¡iÅ™ující LiÅ¡ty db.led.type Typ LED db.led.bit Dioda db.led.bar Panel diod db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Přímý kód) cpath.cloops -begin- Ve vaÅ¡em obvodu byla zjiÅ¡tÄ›na kombinaÄní smyÄka. Aby bylo možno provést analýzu zpoždÄ›ni v obvodu, musíte buÄ pÅ™eruÅ¡it smyÄku, nebo oznaÄit nÄ›které z hradel ve smyÄce jako bod "PÅ™eruÅ¡ení citlivé cesty". SítÄ›, v nichž byla zjiÅ¡tÄ›na smyÄka, jsou vypsány níže. -end- ############################################################################## # Print dialog box # print.outto Výstup do print.printer Tiskárna print.file Soubor print.prcmd Příkaz k Tisku print.filename Název Souboru print.epssave Uložit jako Encapsulated Postscript print.doctit Název Dokumentu print.prmod Tisknout Moduly print.epcm Jedn. Äasu/cm print.estpg Odhad PoÄtu Stránek print.all VÅ¡echny print.cur Aktuální print.use Použité print.sel Vybrané print.inclib Vložit Knihovní Moduly. print.papsz Velikost Papíru print.orient Orientace print.portrait Na Výšku print.landscape Na Šířku print.2side Tisknout OboustrannÄ› print.opts Možnosti print.scale PÅ™izpůsobit velké moduly velikosti stránky. print.partition RozdÄ›lit velké moduly do více stránek. print.incidx Vložit index. print.incgraph Vložit graf hierarchie. print.4up Tisknout malé moduly 4 na stránku. print.range VýbÄ›r Rozsahu print.fulltr Úplná Stopa print.parttr Část Stopy print.start Start print.end Konec ############################################################################## # # Options dialog # opt.site Název Organizace opt.inst Instance opt.mods Moduly opt.modports Konektory modulů opt.frames Rámce opt.comment Komentáře opt.hlink Hypertextové odkazy opt.wire 1-bitové vodiÄe opt.bus Vícebitové vodiÄe opt.tools Nástroje pro práci s hradly opt.cpath Citlivá cesta opt.grid Mřížka v simulátoru opt.logic1 Logická 1 opt.logic0 Logická 0 opt.float Plovoucí opt.unknown Nedefinována/Konfliktní opt.offled Nesvítící LED opt.onled Svítící LED opt.zled Plovoucí LED opt.restdef Obnovit původní nastavení opt.regudate Aktualizace oblastí opt.smoothscroll Plynulé posouvání opt.outmove Pohyb popisků modulu opt.balloon Povolit bublinovou nápovÄ›du opt.debug Povolit debugování opt.novice ZaÄáteÄnický režim opt.ckpoint ProvádÄ›t průběžné ukládání opt.freq Interval opt.beak Povolit speciální režimy opt.mode Režim opt.normal Normální opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatická kontrola integrity opt.showsimcmd Zaznamenat průbÄ›h simulace opt.logfile Logovací soubor simulátoru opt.estepsz Jednotky Äasu/krok opt.cstepsz Hodinové cykly/krok opt.overstep PÅ™esah hodin opt.sorttraces SeÅ™adit stopy podle abecedy opt.rememberprobes Pamatovat si umístÄ›ní sond opt.vpopupdelay ZpoždÄ›ní zobrazení hodnoty opt.initscript InicializaÄní skript opt.posedge UkonÄit hodinový cyklus na vzestupné hranÄ› opt.setclock UkonÄit hodinový cyklus na opt.delayfilepath Soubor se zpoždÄ›ními opt.general Obecné opt.print Tisk opt.simulate Simulace opt.analysis Analýza opt.color Barvy opt.undolen Max poÄet kroků zpÄ›t (Undo) opt.cpopts Možnosti citlivé cesty: opt.maxpath Maximální poÄet cest: opt.cpflash Zobrazit blikající cestu opt.vercheck -begin- PravidelnÄ› kontrolovat přítomnost nové verze TkGate na Internetu. Nevybírejte tuto možnost pokud nemáte stálý přístup k Internetu. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nový Modul blklst.delmod Smazat Modul blklst.frommod Kopírovat Modul Z blklst.tomod Do blklst.oldname Starý Název blklst.newname Nový Název blklst.claim Konvertovat Modul ############################################################################## # # Circuit Dialog box # circ.topmod Hlavní Modul circ.discchg ZruÅ¡it ZmÄ›ny circ.iniscript InicializaÄní Skripty circ.noscript Nebyli vybrány žádné soubory se skripty. circ.really1 Opravdu chcete odstranit circ.really2 ze seznamu inicializaÄních skriptů. circ.extbar Použít RozÅ¡iÅ™ující LiÅ¡ty ############################################################################## # Simulator # sim.breakpt Kontrolní Bod ############################################################################## # # Command box # cmd.file Název Souboru cmd.topname Název Hlavního Modulu ############################################################################## # # Critical path messages # cp.delay ZpoždÄ›ní Cesty: cp.pathl Seznam Cest: cp.numpath PoÄet Cest: cp.recompute PÅ™epoÄítat ############################################################################## # Error messages # err.verilog Chyby v souboru: err.nopin Vybraný konektor není možno zmÄ›nit. err.badhex Neplatná hexadecimální hodnota '%s' byla ignorována. err.gatanchor Hradlo(a) jsou ukotveny a nelze je pÅ™emístit. err.libmode Neplatná operace s knihovním modulem (pro úpravy jej změňtÄ› na uživatelský modul). err.badfind Nelze najít cíl '%s'. err.badopendel Nelze smazat otevÅ™ený modul. err.nosrcmod Zdrojový modul '%s' nebyl nalezen. err.noerr Chybu nelze lokalizovat. err.misserr Informace o chybÄ› nejsou kompletní (spadl simulátor?). err.pounimpl Neimplementovaná chyba v ParseOption err.badinadd Nelze pÅ™idat další vstup k vybranému hradlu. err.badoutadd Nelze pÅ™idat další výstup z vybraného hradla. err.badinoutadd Nelze pÅ™idat další vst./výst. konektory k vybranému hradlu. err.badpinchg Nelze zmÄ›nit typ konektoru na vybraném hradlu. err.badnetname Neplatné znaky v identifikátoru byly smazány. err.netbcrename Identifikátor pÅ™ejmenován na '%s' kvůli neplatným znakům. err.netconfnet Identifikátor pÅ™ejmenován na '%s' kvůli konfliktu. err.netconfgat Identifikátor pÅ™ejmenován kvůli konfliktu s primitivním názvem hradla. err.netconfkw Identifikátor pÅ™ejmenován kvůli konfliktu s rezervovaným slovem. err.badconsame Spojení nepovoleno. VodiÄe jsou souÄástí stejné sítÄ›. err.badconptsp Spojení nepovoleno. VodiÄe jsou konektory modulu nebo jeho napájení. err.badconbitw Spojení nepovoleno. Bitové šířky vodiÄů nejsou stejné. err.badrange Záporný rozsah stop není povolen. err.badlprcmd Nelze vykonat příkaz k tisku '%s'. err.badpsopen Nelze otevřít soubor '%s' pro postskriptový výstup. err.badid Neplatný identifikátor '%s'. err.bkpt.badexp Syntaktická chyba ve výrazu pro kontrolní bod. Výraz musí být jedno z: 'net', '!net', 'net==hodnota', 'net!=hodnota' err.bkpt.badnet Neplatný název sítÄ› '%s'. Názvy musí zaÄínat písmenem a obsahovat jenom písmena, Äíslice a '.'. err.bkpt.badval Syntaktická chyba v hodnotÄ› '%s'. Hodnota musí být desítkové Äíslo nebo verilog-style konstanta. err.bkpt.toomany PříliÅ¡ mnoho kontrolních bodů. Maximální poÄet je %d. err.sim.badtmp Nelze uložit doÄasný soubor '%s' simulátoru (plný disk?). err.sim.syntx Syntaktická chyba v příkazu '%s'. err.sim.noincl Vkládaný soubor '%s' nenalezen. err.sim.clockbadedge Neplatná definice hrany '%c' v příkazu pro hodiny. err.sim.nobkpt Neexistující kontrolní bod '%s'. err.sim.nonet Síť '%s' nebyla nalezena. err.sim.nogate Hradlo '%s' nebylo nalezeno. err.sim.badbin Neplatný znak v binární konstantÄ› '%s'. err.sim.notswitch Hradlo '%s' není pÅ™epínaÄ, dip nebo registr. err.sim.badcmd Neznámý příkaz '%s' v simulaÄním skriptu. err.noteditpchg Vlastnosti mohou být mÄ›nÄ›ny pouze v režimu úprav. err.badeditop Neplatná operace v režimu úprav rozhraní. err.badopen Nelze otevřít vstupní soubor '%s'. err.badlibopen Nelze otevřít knihovní soubor '%s'. err.nomark PÅ™ed výbÄ›rem typu hradla nastavte znaÄku levým tlaÄítkem myÅ¡i. err.badgate Neznámý typ hradla. err.badmake Hradlo nelze vytvoÅ™it. err.badportadd Nelze pÅ™idat konektory k hradlům tohoto typu. err.badportdel Vybraný konektor nelze smazat. err.badportedit Vybraný konektor nelze upravovat. err.noport Nebyly vybrány žádné konektory. err.manypages -begin- V tomto dokumentu je příšernÄ› mnoho stránek. Jste si jisti, že je chcete vÅ¡echny tisknout? -end- err.nojump -begin- Vlastnost 'jump-to-module' nemůže být použita v režimu simulace nebo analýzy citlivé cesty. PÅ™emístÄ›te se prosím ruÄnÄ› do cílového bloku tak, že vyberete přísluÅ¡né moduly a otevÅ™ete je stiskem klávesy '>'. Z modulu, ve kterém se nacházíte, je možno vyskoÄit stiskem klávesy '<'. -end- err.nomod Modul '%s' není definován. err.modlock Logický blok je uzamÄen! err.closeroot Nelze zavřít hlavní modul. Použijte funkci 'UkonÄit' v hlavním menu. err.sim.isrun Simulátor už běží (Použijte 'Ctrl-s e' pro ukonÄení). err.sim.isnotrun Simulátor neběží (Použijte 'Ctrl-s b' pro start). err.editonly Neplatný příkaz v režimu simulace. err.simonly Příkaz platný jen v režimu simulace. err.nodel Nebyly vybrány objekty, které by bylo možno smazat. err.modnotdef Modul '%s' není definován. err.moddef Blok '%s' již existuje. err.noprop Zvolené hradlo nemá vlastnosti, které by Å¡lo mÄ›nit. err.openscript Soubor se simulaÄním skriptem '%s' nelze otevřít. err.oldversion Nahrán soubor uložený ve starší verzi TkGate %s (aktuální verze je %s). err.futureversion Nahraný soubor byl uložen novÄ›jší verzí TkGate %s (tato verze je %s). err.badversion Neznámé Äíslo verze TkGate. Používejte na vlastní riziko err.nodrive Síť %s nemá žádný driver v modulu %s. err.noconn VodiÄ %s{%d} není nikam pÅ™ipojen - byl smazán. err.oldportact Pro pÅ™idání/úpravu konektoru kliknÄ›te pravým tlaÄítkem na konektor nebo okraj modulu. err.backupfail Nelze vytvoÅ™it záložní soubor '%s'. err.corruptnewsave -begin- Aplikace TkGate uložila váš soubor jako '%s', ale zdá se být poÅ¡kozený. Pokud máte povoleno průběžné ukládání, zkuste nahrát nÄ›který z průběžnÄ› uložených souboru. Pro kontrolu integrity uloženého souboru použijte příkaz 'TkGate -V' -end- err.corruptsave -begin- Pří pokusu uložit soubor '%s' aplikace TkGate zjistila problém. Existující soubor nebyl zmÄ›nÄ›n a poÅ¡kozený soubor byl zapsán jako '%s'. Pokud máte povoleno průběžné ukládání, zkuste nahrát nÄ›který z průběžnÄ› uložených souboru. Pro kontrolu integrity uloženého souboru můžete použít příkaz 'TkGate -V'. -end- err.badsave -begin- PÅ™i pokusu otevřít nebo uložit soubor '%s' doÅ¡lo k chybÄ›. Zkontrolujte přístupová práva souboru/adresáře a/nebo místo na disku. -end- err.nosafesave -begin- PÅ™i pokusu uložit soubor '%s' se vyskytl problém. Pokud chcete, zkuste to znova bez ověření korektnosti uložení. Pokud stisknete "ne", původní soubor zůstane nezmÄ›nÄ›n. Pokus stisknete "ano", původní soubor bude pÅ™epsán, ale může být zniÄen, pokud se vyskytnou problémy. Chcete zkusit soubor uložit bez ověření korektnosti uložení? -end- err.noback -begin- Soubor byl vytvoÅ™en v TkGate verze %s, a nemusí být Äitelný verzemi staršími než aktuální verze (%s) bude-li uložen. -end- ############################################################################## # Informational messages # msg.selwire Vybrán vodiÄ s názvem '%s'. msg.selgate Vybráno hradlo s názvem '%s'. msg.selblock Vybrán %s blok s názvem '%s'. msg.modoverwt Cílový modul '%s' již existuje. PÅ™epsat? msg.foundgate Nalezeno hradlo '%s'. msg.foundwire Nalezen vodiÄ '%s'. msg.searchagn Cílový Å™etÄ›zec '%s' nenalezen. KliknÄ›te na 'Najít' pro nové hledání. msg.sim.chgtoroot Režim simulace vyžaduje koÅ™enový modul na vrcholu editovacího zásobníku. msg.sim.nogatemod Režim simulace vyžaduje konkrétní zásobník modulů. msg.setinterface Nastavení rozhraní modulu pro '%s'. msg.needsel Zvolte prosím instanci modulu. msg.wroteckpt Průběžné ukládání %s... msg.save Obvod uložen jako '%s'. msg.reallynew Obvod byl zmÄ›nÄ›n. Opravdu chcete zruÅ¡it vÅ¡echny zmÄ›ny a vytvoÅ™it nový obvod? msg.reallyquit Obvod byl zmÄ›nÄ›n. Opravdu chcete ukonÄit aplikaci? msg.notlib Modul '%s' není knihovní modul. ############################################################################## # Miles messages (Activated when Miles Bader uses TkGate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help # ho.new -begin- Smazat aktuální obvod a zaÄít editovat nový. -end- ho.open Otevřít obvod ze souboru. ho.save Uložit obvod do aktuálního souboru. ho.print Tisk aktuálního obvodu. ho.move -begin- Move/Connect - Kliknutím myší a pÅ™etáhnutím můžete: Nastavit novou pozici hradla PÅ™emístit hradla a vodiÄe Spojit vodiÄe Dvojitým kliknutím můžete : Upravit vlastnosti hradla, vodiÄe a konektoru Upravit text komentáře -end- ho.delgat -begin- Smazat hradlo - Použijte tento nástroj na smazání hradel. -end- ho.cutw -begin- PÅ™eruÅ¡it vodiÄ - Použijte tento nástroj na pÅ™eruÅ¡ení vodiÄů. -end- ho.inv -begin- Invertovat - Použijte tento nástroj na pÅ™idání nebo odebrání invertorů z konektorů hradel. -end- ho.bitw -begin- Bitová šířka - Použijte tento nástroj na zmÄ›nu bitové šířky vodiÄů. Vložte poÄet bitů do políÄka v pravém dolním rohu okna. -end- ho.modopen Otevřít vybraný modul. ho.modclose Zavřít aktuální modul. ho.undo ZpÄ›t o pÅ™edchozí krok(y). ho.redo VpÅ™ed o zruÅ¡ený krok(y). ho.simstart -begin- Spustit simulátor, otevřít logický analyzátor a vykonat inicializaÄní skripty, pokud jsou definovány. -end- ho.simgo -begin- Spustit simulátor v režimu stálého bÄ›hu. Poznámka: Simulace kombinaÄních obvodů probíhá jen dokud obvod nedosáhne ustálený stav -end- ho.simpause -begin- Pozastavit právÄ› běžící simulaci. -end- ho.simstep -begin- Posunout se o pevný poÄet jednotek Äasu. OtevÅ™ete okno s možnostmi simulace pro nastavení velikosti kroku. -end- ho.simclock -begin- Posunout se o pevný poÄet hodinových cyklů. OtevÅ™ete okno s možnostmi simulace pro nastavení velikosti kroku. -end- ho.simstop -begin- UkonÄit právÄ› běžící simulaci a vrátit se do editovacího režimu. -end- ho.simbreak -begin- Upravit aktuální kontrolní body. Simulace se zastaví ve chvíli, kdy se podmínka v kontrolním bodÄ› stane pravdivou. -end- ho.simexec Vykonat simulaÄní skript. ho.simload -begin- Nahrát obsah pamÄ›ti z .mem souboru. -end- ho.simdump -begin- Uložit obsah pamÄ›ti do .mem souboru. -end- ho.sim.break -begin- Vložit kontrolní bod simulace. Kontrolní body jsou výrazy, které, pokud se stanou pravdivými, způsobí zastavení simulace. MomentálnÄ› jsou podporovány jenom jednoduché výrazy s jediným relaÄním operátorem jako tÅ™eba "w1 == 0" nebo "w7 != 8". Výrazy jako "w8" nebo "!w2" můžou být rovněž použity pro test na nenulovou resp. nulovou hodnotu. -end- ho.f.modlist -begin- Seznam vÅ¡ech aktuálnÄ› nahraných modulů. Hlavní modul je oznaÄen znaménkém "+", knihovní moduly jsou v závorkách. -end- ho.netlist -begin- Seznam vÅ¡ech sítí v aktuálním modulu. SítÄ› oznaÄeny '@' mají skrytá jména Vícebitové sítÄ› jsou zobrazeny s bitovou šířkou na konci. -end- ho.ports -begin- Seznam vÅ¡ech konektorů aktuálního modulu. ZnaÄka'>' oznaÄuje vstup, '<' oznaÄuje výstup a znaÄka '=' vstup-výstup." -end- ho.status.logo -begin- Indikátor stavu simulace. Pokud ukazuje železnou bránu, TkGate je v editovacím režimu. Pokud ukazuje AND hradlo na ÄtyÅ™ech nožiÄkách, TkGate je v režimu simulace. Pokud hradlo AND stojí, simulace je pozastavena a pokud kráÄí, simulace běží -end- ho.status.msg Zde se zobrazují zprávy TkGate. ho.status.block Zásobník editovaných modulů. ho.status.file -begin- AktuálnÄ› editovaný soubor. Znak '*' ukazuje, že od posledního uložení byl soubor zmÄ›nÄ›n. -end- ho.print.selall Vytisknout vÅ¡echny moduly v aplikaci TkGate. ho.print.selcur Vytisknout jen aktuální modul v editovacím oknÄ› aplikace TkGate. ho.print.seluse -begin- Vytisknout vÅ¡echny "používané" moduly. Používané moduly jsou takové, které jsou potomky koÅ™enového modulu. -end- ho.print.fulltrace Vytisknout celou stopu. ho.print.parttrace -begin- Vytisknout Äást stopy. Vložte Äas zaÄátku a konce stopy v okénku dole, nebo použijte pravé tlaÄítko myÅ¡i pro výbÄ›r rozsahu v oknÄ› simulace (použijte klávesy shift-pravá Å¡ipka pro výbÄ›r velkých rozsahů). -end- ho.print.parttracestart ÄŒas zaÄátku výstupu stopy. ho.print.parttraceend ÄŒas konce výstupu stopy. ho.print.selsel -begin- Vytisknout jenom níže vybrané moduly. Použijte klávesu Ctrl pro výbÄ›r více modulů. -end- ho.print.modlist Vybrat moduly pro tisk. ho.circuit.discchg -begin- TkGate nezobrazí varování pokud zrušíte zmÄ›ny bez toho, aby byly uloženy. -end- ho.circuit.extbar -begin- Základní hradla (AND, OR, XOR) použijí rozÅ¡iÅ™ující liÅ¡ty pro manipulaci s více vstupy. -end- ho.cmd.bitw -begin- VodiÄe vybrané kurzorem budou nastaveny na tuto bitovou šířku -end- ho.edgat.extbar -begin- PÅ™i této volbÄ› budou vícevstupová základní hradla používat rozÅ¡iÅ™ující liÅ¡ty pÅ™i pÅ™idání dalších vstupů k hradlu. -end- ho.edgat.signam -begin- Název vybraného signálu na vybraném hradlu. Zde můžete zmÄ›nit název signálu. -end- ho.edgat.port -begin- Název konektoru pro tento signál na tomto hradle. Toto pole může být upravováno pouze pro instance modulu. -end- ho.edgat.iolab -begin- SmÄ›r vybraného signálu na vybraném hradle Toto pole může být upravováno pouze pro instance modulu. -end- ho.edgat.bitlab -begin- Bitová šířka vybraného signálu na vybraném hradle. Zde můžete zmÄ›nit bitovou šířku signálu. -end- ho.edgat.cycle Celkový poÄet Äasových jednotek v hodinovém cyklu. ho.edgat.phase PoÄáteÄní bod cyklu (v procentech). ho.edgat.duty Část cyklu kde jsou hodiny na nižší hodnotÄ›. ho.edgat.cname Název pÅ™ipojené sítÄ›. ho.edgat.cport Konektor ke kterému je pÅ™ipojena síť. ho.edgat.ctype Typ pÅ™ipojení. ho.edgat.cbitw Bitová šířka pÅ™ipojené sítÄ›. ho.edgat.cedit Upravit vybraný konektor. ho.edgat.cadd PÅ™idat konektor. ho.edgat.cdel Smazat vybraný konektor. ho.edgat.hide -begin- Nastavte tento příznak pro zakázání zobrazení názvu hradla. -end- ho.edgat.gtype Typ hradla. ho.edgat.gname Název této instance hradla. ho.edgat.ganchor Nastavte tento příznak pro ukotvení pozice hradla. ho.edgat.gx X souÅ™adnice hradla. ho.edgat.gy Y souÅ™adnice hradla. ho.edgat.swstate -begin- Výchozí stav spínaÄe, který bude použit na zaÄátku simulace. -end- ho.edgat.dipstate -begin- Výchozí stav dip spínaÄe, který bude použit na zaÄátku simulace. -end- ho.edgat.range Bitový rozsah sbÄ›rnice. ho.edgat.memfile -begin- Soubor s výchozím stavem pamÄ›ti. Tento soubor je naÄten na zaÄátku simulace. -end- ho.edgat.func Typ funkce tohoto modulu. ho.edgat.frame Popisek rámce. ho.traceprint Vytisknout logickou stopu ho.showxhair -begin- Je-li toto tlaÄítko aktivní, v oknÄ› simulace se objeví vertikální Äára. -end- ho.opt.sorttraces -begin- Je-li tato možnost aktivní, stopy v oknÄ› simulace se zobrazí v setřídÄ›ném poÅ™adí. Není-li tato možnost aktivní, stopy v oknÄ› simulace se zobrazí v tom poÅ™adí, v jakém byly nastaveny sondy. -end- ho.opt.rememberprobes -begin- Je-li tato možnost aktivní, vÅ¡echny sondy nastaveny v režimu simulace se zapamatují a budou automaticky pÅ™idány pÅ™i opÄ›tovném spuÅ¡tÄ›ní simulace. -end- ho.opt.undolen -begin- Maximální poÄet kroků zpátky, které se budou pamatovat. -end- ho.opt.site -begin- Jméno organizace, kde je TkGate nainstalováno. Toto jméno se použije na vÅ¡ech výstupech na tiskárnu nebo do postskriptového souboru. -end- ho.opt.smooth -begin- Je-li tato možnost aktivní, posouvání okna bude optimalizováno použitím kopie bitmapy místo úplného znovuzobrazení. Můžete tuto možnost vypnout, pokud máte jakékoliv problémy s vaším serverem. -end- ho.opt.clip -begin- Je-li tato možnost aktivní, pÅ™i pÅ™ekreslování bude aktualizována jenom ta Äást okna, která se momentálnÄ› mÄ›ní. Jinak bude pÅ™ekreslována vždy celá obrazovka. -end- ho.opt.outmove -begin- Je-li tato možnost aktivní, pÅ™i pÅ™etahování bude zobrazen pouze popisek instance modulu, která se právÄ› pÅ™emísÅ¥uje. Používejte tuto vlastnost na poÄítaÄích s pomalým displejem. -end- ho.opt.bhelp -begin- Je-li tato možnost aktivní, budou používány bubliny s nápovÄ›dou. Bubliny s nápovÄ›dou (jako tato) obsahují vysvÄ›tlení k jednotlivým položkám, když je nad nimi kurzor myÅ¡i. -end- ho.opt.novice -begin- Pokud není na příkazovém řádku specifikován jiný obvod, pÅ™i spuÅ¡tÄ›ní aplikace bude jako výchozí obvod zobrazen TkGate tutoriál. -end- ho.opt.debug -begin- Povolit nÄ›kolik debugovacích prvků (užiteÄné pouze pro TkGate vývojáře). -end- ho.opt.ckpt Povolit průběžné ukládání neuložených obvodů. ho.opt.ckptfreq Frekvence průběžného ukládání v sekundách. ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .TkGate-preferences file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- PoÄet jednotek Äasu, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.ckstep -begin- PoÄet hodinových cyklů, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.ckover -begin- PoÄet jednotek Äasu bezprostÅ™ednÄ› po vzestupné hranÄ› hodin, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.vpopupdelay -begin- ZpoždÄ›ní v milisekundách mezi stisknutím a pÅ™idržením tlaÄítka myÅ¡i a zobrazením hodnoty signálu. Na nÄ›kterých systémech jsou hodnoty zpoždÄ›ní v konfliktu se schopností rozpoznat dvouklik. Pokud máte tento problém, zvyÅ¡te tuto hodnotu. Jsou povoleny hodnoty mezi 1 and 10000. -end- ho.opt.init -begin- Soubor se simulaÄním skriptem, který bude automaticky vykonán pÅ™i spuÅ¡tÄ›ní simulace. -end- ho.opt.ckall -begin- Pokud je tento režim aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranÄ› kterýchkoliv hodin v obvodu. -end- ho.opt.ckspec -begin- Pokud je tento režim aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranÄ› specifikovaných hodin v obvodu. -end- ho.deftech -begin- PÅ™ednastavená technologie pro nová hradla. Ovlivňuje zpoždÄ›ní hradel. Pro zmÄ›nu technologie konkrétního hradla otevÅ™ete okno s jeho vlastnostmi (dvouklikem) a vyberte záložku "ZpoždÄ›ní". -end- ho.techbut -begin- Použít zpoždÄ›ní ze souboru definujícího standardní technologii. Nové technologie můžete pÅ™idat v menu "Soubor -> Možnosti -> Simulace". -end- ho.custbut -begin- Nastavit vlastní hodnoty zpoždÄ›ní pro toto hradlo. -end- ho.contver -begin- Stále ověřovat integritu vnitÅ™ních datových struktur po každé operaci. -end- ho.simwatch -begin- Zaznamenat příkazy zasílané mezi GUI a simulátorem. -end- ho.simlog -begin- Zapsat příkaz použitý v simulátoru do logovacího souboru. Logovací soubor může být potom použit jako vstup simulátoru v debugovacím režimu. -end- ho.cpathanal -begin- Najít citlivou cestu v obvodu. -end- tkgate-2.0-b10/locale/cs/messages.iso-8859-2000644 001751 001751 00000070051 10104445261 020747 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Jun 4 10:37:11 2004 ############################################################################## # # basic strings # .dismiss Zru¹it b.close Zavøít b.ok OK b.clear Znova b.cancel Zru¹it b.open Otevøít... b.bitw Bitová ¹íøka b.in vstup b.out výstup b.inout smí¹ený b.browse Procházet... b.label Návì¹tí b.find Najít b.edit Upravit... b.add Pøidat... b.delete Smazat b.deleteb Smazat... b.apply Pou¾ít b.anchor Ukotvit b.tech Technologie ############################################################################## # Menu strings # file Soubor edit Úpravy tool Nástroje simulate Simulace module Modul gate Hradlo make Pøidej circ Obvod new Nový open Otevøít... openlib Otevøít Knihovnu... save Ulo¾it saveas Ulo¾it jako... print Tisk... options Mo¾nosti... quit Ukonèit undo Zpìt redo Znovu cut Vyjmout copy Kopírovat paste Vlo¾it selall Vybrat v¹e find Najít... algnv Uspoøádat Ver. algnh Uspoøádat Horiz. zoomin Zvìt¹it zoomout Zmen¹it move Pøesunout/Spojit delg Smazat Hradlo cutw Pøeru¹it Vodiè inv Invertovat bitw Bitová ¹íøka debug Debug rot0 Otoèit 0 rot90 Otoèit 90 rot180 Otoèit 180 rot270 Otoèit 270 simbegin Zaèít Simulaci simend Ukonèit Simulaci simadprobe Pøidat/Smazat Sondu simrun Spustit simpause Pøeru¹it simstep Step Epoch(s) simcycle Step Cycle simbreak Kontrolní bod... simscript Spustit Skript... simload Load Memory... simdump Dump Memory... modopen Otevøít modclose Zavøít modseti Nastavit Rozhraní modediti Upravit Rozhraní... modnew Nový... moddel Smazat... modcopy Kopírovat... modrename Pøejmenovat... modclaim Claim... circprop Vlastnosti Obvodu... cpath Citlivá Cesta... gataddin Pøidat Vstup gataddout Pøidat Výstup gataddinout Add BiDir gatiochg Zmìnit Typ gatanchor Ukotvit Vybrané gatunanchor Uvolnit Vybrané gatprop Vlastnosti... gatrep Vytvoøit Kopii gatdel Smazat gatsettech Nastavit Technologii gmswitch I/O gmgate Hradlo gmredgate Redukce gmmsi MSI gmalu ALU gmmem Pamì» gmmod Modul gmcomment Komentáø gmframe Rámec gmxswitch Switch gmdip DIP Switch gmground Uzemnìní gmvdd Vdd gmmerge Wire Merge gmclock Hodiny gm.led LED gm.ledbar LED Panel gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Pøímý) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Buffer gminv Invertor gmtribuf Tri-Buffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Sèítaèka gmmult Násobièka gmdiv Dìlièka gmlshift Posun Doleva gmrshift Posun Doprava gmarshift Arit.Posun Doprava gmroll Rotace gmreg Registr gmff Klopný Obvod gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Dekodér gm14dec 1-4 Dekodér gm18dec 1-8 Dekodér gmmodinst Instance Modulu gmmodin Vstup Modulu gmmodout Výstup Module gmmodinout Module InOut addwireseg Pøidat Segment Vodièe help Nápovìda hlpabout O programu... hlplicense Licence... hlpdoc Dokumentace... hlptut Návody hlpexample Pøíklady exampcomb Kombinaèní Logika examp3bit 3-Bitový Èítaè examp8bit 8-Bitový Èítaè examptrff Transistor-Level FF exampcpu Menagerie CPU tutwelcome TkGate Intro tutcreate Vytvoøení Obvodu tutedit1 Úpravy Obvodu (1) tutedit2 Úpravy Obvodu (2) tutmods Pou¾ití Modulù tutsim Simulace Obvodu # Scope Menu menu.sc.prtrace Tisknout Stopu... menu.sc.close Zavøít menu.sc.trace Stopa menu.sc.zoomin Zvìt¹it menu.sc.zoomout Zmen¹it scope.emptymsg Poklepáním na vodiè pøidejte nebo sma¾te stopu. comment.empty [Poklepáním pøidejte text.] ############################################################################## # Interface strings # ifile Soubor imodule Modul iblmodule Moduly iports Porty ibits Bity ############################################################################# # Net Dialog Box # db.net.name Jméno Sitì db.net.hide Skrýt Jméno db.net.bits Bitová ¹íøka db.net.port Typ Portu db.net.in vstup db.net.out výstup db.net.inout inout db.net.inets Sitì ############################################################################## # Gate dialog box # db.gate.signam Název Signálu db.gate.portnam Název Portu db.gate.iotype Typ db.gate.bitw Bitová ¹íøka db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bity db.gate.gtype Typ Hradla db.gate.gname Název Hradla db.gate.hidenam Skrýt Název db.gate.anchor Ukotvit db.gate.cpbreak Critical Path Partition db.gate.butstate Stav tlaèítka db.gate.dipval Hodnota pøepínaèe db.gate.memfilenam Soubor s obsahem pamìti db.gate.modname Funkce db.gate.islink Text je Hypertextový Odkaz db.gate.link Odkaz na Soubor db.gate.findw Hledat pouze vodièe db.gate.findg Hledat pouze hradla db.gate.findwg Hledat vodièe i hradla db.gate.general Obecné db.gate.details Detaily db.gate.ports Port db.gate.delay Zpo¾dìní db.gate.stddelay Standartní Zpo¾dìní db.gate.custdelay Definované Zpo¾dìní db.gate.extbar Pou¾ít roz¹iøující li¹ty db.led.type Typ LED db.led.bit Bit db.led.bar Bar Graph db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Direct) cpath.cloops -begin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the gates in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # print.outto Výstup do print.printer Tiskárna print.file Soubor print.prcmd Pøíkaz k tisku print.filename Jméno Souboru print.epssave Ulo¾it jako Encapsulated Postscript print.doctit Název Dokumentu print.prmod Print Modules print.epcm Epochs/cm print.estpg Odhad poètu stránek print.all V¹echny print.cur Aktuální print.use Pou¾ité print.sel Vybrané print.inclib Vlo¾it knihovní moduly. print.papsz Velikost papíru print.orient Orientace print.portrait Na vý¹ku print.landscape Na ¹íøku print.2side Tisknout Oboustrannì print.opts Mo¾nosti print.scale Pøizpùsobit velké moduly velikosti stránky. print.partition Rozdìlit velké moduly do více stránek. print.incidx Vlo¾it index. print.incgraph Vlo¾it graf hierarchie. print.4up Tisknout malé moduly 4 na stránku. print.range Range Selection print.fulltr Úplná Stopa print.parttr Èást Stopy print.start Start print.end Konec ############################################################################## # # Options dialog # opt.site Název organizace opt.inst Instance opt.mods Moduly opt.modports Porty Modulù opt.frames Rámce opt.comment Komentáøe opt.hlink Hyperlinky opt.wire 1-bitové Vodièe opt.bus Vícebitové Vodièe opt.tools Nástroje pro práci s hradly opt.cpath Citlivá cesta opt.grid Scope Grid opt.logic1 Logická 1 opt.logic0 Logická 0 opt.float Float opt.unknown Nedefinována/Konfliktní opt.offled Nesvítící LED opt.onled Svítící LED opt.zled Floating LED opt.restdef Obnovit pùvodní nastavení opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.outmove Outline Move modules opt.balloon Povolit bublinovou nápovìdu opt.debug Enable Debugging opt.novice Novice Mode opt.ckpoint Do Checkpointing opt.freq Interval opt.beak Enable Special Modes opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatická Kontrola Integrity opt.showsimcmd Display Simulator Stream opt.logfile Simulator Log File opt.estepsz Poèet jednotek èasu/krok opt.cstepsz Poèet hodinových cyklù/krok opt.overstep Clock Overstep opt.sorttraces ¹˜adit stopy podle abecedy opt.rememberprobes Pamatovat si umístìní sond opt.vpopupdelay Value Pop-Up Delay opt.initscript Inicialièní skript opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Soubor se zpo¾dìními opt.general Obecné opt.print Tisk opt.simulate Simulace opt.analysis Analýza opt.color Barvy opt.undolen Max Poèet Krokù Zpìt (Undo) opt.cpopts Mo¾nosti citlivé cesty: opt.maxpath Maximální poèet cest: opt.cpflash Display with Flashing Path opt.vercheck -begin- Periodically check for new versions of tkgate over the Internet. Do not enable unless you have continuous access to the Internet. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nový Modul blklst.delmod Smazat Modul blklst.frommod Kopírovat Modul Z blklst.tomod Do blklst.oldname Starý Název blklst.newname Nový Název blklst.claim Claim Module ############################################################################## # # Circuit Dialog box # circ.topmod Top-Level Module circ.discchg Discard Changes circ.iniscript Inicializaèní Skripty circ.noscript Nebyli vybrány ¾ádné soubory se skripty. circ.really1 Opravdu chcete odstranit circ.really2 ze seznamu inicializaèních skriptù. circ.extbar Pou¾ít roz¹iøující li¹ty ############################################################################## # Simulator # sim.breakpt Kontrolní bod ############################################################################## # # Command box # cmd.file Název souboru cmd.topname Název Hlavního Modulu ############################################################################## # # Critical path messages # cp.delay Zpo¾dìní cesty: cp.pathl Seznam Cest: cp.numpath Poèet cest: cp.recompute Pøepoèítat ############################################################################## # Error messages # err.verilog Chyby v souboru: err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Hradlo(a) jsou ukotveny a nelze je pøemístit. err.libmode Neplatná operace s knihovním modulem(convert to normal module to edit). err.badfind Can't find target '%s'. err.badopendel Nelze smazat otevøený modul. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.pounimpl Unimplemented error in ParseOption err.badinadd Nelze pøidat dal¹í vstup k vybranému hradlu err.badoutadd Nelze pøidat dal¹í výstup k vybranému hradlu err.badinoutadd Can't add any more inout pins to selected gate. err.badpinchg Can't change pin types on selected gate. err.badnetname Neplatné znaky v identifikátoru byly smazány. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with primitive gate name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Spojení nepovoleno. Vodièe jsou souèástí stejné sítì err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Spojení nepovoleno. Bitové ¹íøky nejsou stejné err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Nelze vykonat pøíkaz k tisku '%s'. err.badpsopen Nelze otevøít soubor '%s' pro postskriptový výstup. err.badid Neplatný identifikátor '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Neplatný název sitì '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Pøíli¹ mnoho kontrolních bodù. Maximální mno¾stvi je %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.clockbadedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Si» '%s' nebyla nalezena. err.sim.nogate Hradlo '%s' nebylo nalezeno. err.sim.badbin Neplatný znak v binární konstantì '%s'. err.sim.notswitch Gate '%s' is not a switch, dip or register. err.sim.badcmd Neznámý pøíkaz '%s' v simulaèním skriptu. err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Nelze otevøít vstupní soubor '%s'. err.badlibopen Nelze otevøít knihovní soubor '%s'. err.nomark Please set a mark with the left mouse button before selecting a gate type. err.badgate Neznámý typ hradla. err.badmake Hradlo nelze vytvoøit. err.badportadd Can't add ports to gates of this type. err.badportdel Selected port can not be deleted. err.badportedit Selected port can not be edited. err.noport Nebyly vybráný ¾ádné porty. err.manypages -begin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -begin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot Can't close top-level module. Use quit. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.isnotrun Simulator is not running (Use 'Ctrl-s b' to start). err.editonly Neplatný pøíkaz v re¾imu simulace. err.simonly Pøíkaz platný jen v re¾imu simulace. err.nodel Nebyly vybrány objekty, které by bylo mo¾no smazat. err.modnotdef Modul '%s' není definovaný. err.moddef Blok '%s' ji¾ existuje. err.noprop Zvolené hradlo nemá vlastnosti, které by ¹lo mìnit. err.openscript Soubor se simulaèním skriptem '%s' nelze otevøít. err.oldversion Loaded file with obsolete version number %s (current version is %s). err.futureversion Loaded file saved by future tkgate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.backupfail Nelze vytvoøit zálo¾ný soubor '%s'. err.corruptnewsave -begin- Aplikace TkGate ulo¾ila vá¹ soubor jako '%s', ale zdá se být po¹kozený. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -begin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -begin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -begin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -begin- Soubor byl vytvoøen v tkgate verze %s, a nemusí být èitelný verzemi star¹ími ne¾ aktuální verze (%s) bude-li ulo¾en. -end- ############################################################################## # Informational messages # msg.selwire Selected wire named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Nalezeno hradlo '%s'. msg.foundwire Nalezen vodiè '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Obvod ulo¾en jako '%s'. msg.reallynew Obvod byl zmìnìn. Opravdu chcete zru¹it v¹echny zmìný a vytvoøit nový obvod? msg.reallyquit Obvod byl zmìnìn. Opravdu chcete ukonèit aplikaci? msg.notlib Modul '%s' není knihovní modul. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help # ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.print Tisk aktuálního obvodu. ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new gate Move gates and wires Connect wires By double-clicking you can: Upravit vlastnosti hradla, vodièe a portu Upravit text komentáøe -end- ho.delgat -begin- Smazat hradlo - Pou¾ijte tento nástroj na smazání hradel. -end- ho.cutw -begin- Pøeru¹it vodiè - Use this tool to cut wires. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from gate ports. -end- ho.bitw -begin- Bit Width - Use this tool to change the bit size of a wire. Enter the number of bits in the entry box in the lower right corner of the window. -end- ho.modopen Open the selected module. ho.modclose Zavøít the current module. ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.simstart -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. -end- ho.simexec Execute a simultion script. ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.sim.break -begin- Enter a simulator breakpoint. Breakpoints are expressions which cause the simulator to pause execution when they become true. Currently only simple expressions with a single relational operator such as "w1 == 0" or "w7 != 8" are supported. Expressions such as "w8" or "!w2" may also be used to test for non-zero and zero values respectively. -end- ho.f.modlist -begin- List of all modules currently loaded. The top-level module is indicated by a trailing "+", and library modules are shown in parentheses. -end- ho.netlist -begin- List of nets in the current module. Nets marked with a '@' have hidden names. Multi-bit nets are displayed with a range after them. -end- ho.ports -begin- List of ports on the current module. A '>' indicates an input, a '<' indicates an output, and a '=' indicates an inout." -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, tkgate is in edit mode. If the quadrapedal AND gate is shown, tkgate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from tkgate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TKGate. ho.print.selcur Print only the current module in the TKGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.cmd.bitw -begin- Wires selected with the cursor will be set to this bit width. -end- ho.edgat.extbar -begin- If selected, multi-input basic gates will use extender bars as inputs are added to the gate. -end- ho.edgat.signam -begin- The name of the selected signal on the selected gate. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the gate. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected gate. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected gate. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.cname Name of connected net. ho.edgat.cport Port to which net is connected. ho.edgat.ctype Type of connection. ho.edgat.cbitw Bit width of connected net. ho.edgat.cedit Edit the selected port. ho.edgat.cadd Add a port. ho.edgat.cdel Delete the selected port. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Type of the gate. ho.edgat.gname Name of this gate instance. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx X coordinate of gate. ho.edgat.gy Y coordinate of gate. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint Print logic trace. ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.rememberprobes -begin- If this option is enabled, any probes set while in simulation mode will be remembered and automatically added when restarting the simulation. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.site -begin- The name of the site where tkgate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .tkgate-preferences file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when the simulation is started. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. -end- ho.deftech -begin- Default technology for new gates. Affects delay of gates. To change the technology of a specific gate, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this gate. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.simlog -begin- Write commands issued to the simulator to a log file. The log file can then be used as input to the simulator in a debugger. -end- ho.cpathanal -begin- Find critical paths in a circuit. -end- tkgate-2.0-b10/locale/cs/x000644 001751 001751 00000071230 10104445261 016044 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Jun 4 10:37:11 2004 # Do èe¹tiny pøelo¾ila Katarína Bubli Machálková (K.Machalkova@pod.cvut.cz) # Poslední aktualizace 3.srpna 2004 ############################################################################## # # basic strings # b.dismiss Zru¹it b.close Zavøít b.ok OK b.clear Znova b.cancel Zru¹it b.open Otevøít... b.bitw Bitová ©íøka b.in Vstup b.out Výstup b.inout Vst./Výst. b.browse Procházet... b.label Popisek b.find Najít b.edit Upravit... b.add Pøidat... b.delete Smazat b.deleteb Smazat... b.apply Pou¾ít b.anchor Ukotvit b.tech Technologie ############################################################################## # Menu strings # file Soubor edit Úpravy tool Nástroje simulate Simulace module Modul gate Hradlo make Pøidat circ Obvod new Nový open Otevøít... openlib Otevøít Knihovnu... save Ulo¾it saveas Ulo¾it Jako... print Tisk... options Mo¾nosti... quit Ukonèit undo Zpìt redo Znovu cut Vyjmout copy Kopírovat paste Vlo¾it selall Vybrat V¹e find Najít... algnv Uspoøádat Ver. algnh Uspoøádat Horiz. zoomin Zvìt¹it zoomout Zmen¹it move Pøesunout/Spojit delg Smazat Hradlo cutw Pøeru¹it Vodiè inv Invertovat bitw Bitová ©íøka debug Debug rot0 Otoèit 0 rot90 Otoèit 90 rot180 Otoèit 180 rot270 Otoèit 270 simbegin Zaèít Simulaci simend Ukonèit Simulaci simadprobe Pøidat/Smazat Sondu simrun Spustit simpause Pøeru¹it simstep Posun o Jednotku(y) Èasu simcycle Posun o Hodinový Cyklus simbreak Kontrolní Bod... simscript Spustit Skript... simload Nahrát Obraz Pamìti... simdump Ulo¾it Obraz Pamìti... modopen Otevøít modclose Zavøít modseti Nastavit Rozhraní modediti Upravit Rozhraní... modnew Nový... moddel Smazat... modcopy Kopírovat... modrename Pøejmenovat... modclaim Konvertovat... circprop Vlastnosti Obvodu... cpath Citlivá Cesta... gataddin Pøidat Vstup gataddout Pøidat Výstup gataddinout Pøidat Vst./Výst. gatiochg Zmìnit Typ gatanchor Ukotvit Vybrané gatunanchor Uvolnit Vybrané gatprop Vlastnosti... gatrep Vytvoøit Kopii gatdel Smazat gatsettech Nastavit Technologii gmswitch I/O gmgate Hradlo gmredgate Redukce gmmsi MSI gmalu ALU gmmem Pamì» gmmod Modul gmcomment Komentáø gmframe Rámec gmxswitch Spínaè gmdip DIP Spínaè gmground Uzemnìní gmvdd Vdd gmmerge Spojení Vodièù gmclock Hodiny gm.led LED gm.ledbar LED Panel gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Pøímý kód) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Budiè Sbìrnice gminv Invertor gmtribuf 3stav. Budiè Sbìrnice gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Sèítaèka gmmult Násobièka gmdiv Dìlièka gmlshift Posun Doleva gmrshift Posun Doprava gmarshift Arit.Posun Doprava gmroll Rotace gmreg Registr gmff Klopný Obvod gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Dekodér gm14dec 1-4 Dekodér gm18dec 1-8 Dekodér gmmodinst Instance Modulu gmmodin Vstup Modulu gmmodout Výstup Module gmmodinout Vst./Výst. Modulu addwireseg Pøidat Segment Vodièe help Nápovìda hlpabout O programu... hlplicense Licence... hlpdoc Dokumentace... hlptut Návody hlpexample Pøíklady exampcomb Kombinaèní Logika examp3bit 3-Bitový Èítaè examp8bit 8-Bitový Èítaè examptrff Transistorový KO exampcpu Cvièný CPU tutwelcome TkGate Intro tutcreate Vytvoøení Obvodu tutedit1 Úpravy Obvodu (1) tutedit2 Úpravy Obvodu (2) tutmods Pou¾ití Modulù tutsim Simulace Obvodu # Scope Menu menu.sc.prtrace Tisknout Stopu... menu.sc.close Zavøít menu.sc.trace Stopa menu.sc.zoomin Zvìt¹it menu.sc.zoomout Zmen¹it scope.emptymsg Dvojitým kliknutím na vodiè pøidejte nebo sma¾te stopu. comment.empty [Dvojitým kliknutím pøidejte text.] ############################################################################## # Interface strings # ifile Soubor imodule Modul iblmodule Moduly iports Konektory ibits Bity ############################################################################# # Net Dialog Box # db.net.name Název Sítì db.net.hide Skrýt Jméno db.net.bits Bitová ©íøka db.net.port Typ Konektoru db.net.in Vstup db.net.out Výstup db.net.inout Vst./Výst. db.net.inets Sítì ############################################################################## # Gate dialog box # db.gate.signam Název Signálu db.gate.portnam Název Konektoru db.gate.iotype Typ db.gate.bitw Bitová ©íøka db.gate.cyclew ©íøka Cyklu db.gate.phase Fáze db.gate.duty Støída db.gate.port Konektor db.gate.bitws Bity db.gate.gtype Typ Hradla db.gate.gname Název Hradla db.gate.hidenam Skrýt Název db.gate.anchor Ukotvit db.gate.cpbreak Pøeru¹ení Citlivé Cesty db.gate.butstate Stav Tlaèítka db.gate.dipval Hodnota Pøepínaèe db.gate.memfilenam Soubor s Obsahem Pamìti db.gate.modname Funkce db.gate.islink Text Je Hypertextový Odkaz db.gate.link Odkaz na Soubor db.gate.findw Hledat Pouze Vodièe db.gate.findg Hledat Pouze Hradla db.gate.findwg Hledat Vodièe i Hradla db.gate.general Obecné db.gate.details Detaily db.gate.ports Konektory db.gate.delay Zpo¾dìní db.gate.stddelay Standardní Zpo¾dìní db.gate.custdelay Definované Zpo¾dìní db.gate.extbar Pou¾ít Roz¹iøující Li¹ty db.led.type Typ LED db.led.bit Dioda db.led.bar Panel diod db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Pøímý kód) cpath.cloops -begin- Ve va¹em obvodu byla zji¹tìna kombinaèní smyèka. Aby bylo mo¾no provést analýzu zpo¾dìni v obvodu, musíte buï pøeru¹it smyèku, nebo oznaèit nìkteré z hradel ve smyèce jako bod "Pøeru¹ení citlivé cesty". Sítì, v nich¾ byla zji¹tìna smyèka, jsou vypsány ní¾e. -end- ############################################################################## # Print dialog box # print.outto Výstup do print.printer Tiskárna print.file Soubor print.prcmd Pøíkaz k Tisku print.filename Název Souboru print.epssave Ulo¾it jako Encapsulated Postscript print.doctit Název Dokumentu print.prmod Tisknout Moduly print.epcm Jedn. èasu/cm print.estpg Odhad Poètu Stránek print.all V¹echny print.cur Aktuální print.use Pou¾ité print.sel Vybrané print.inclib Vlo¾it Knihovní Moduly. print.papsz Velikost Papíru print.orient Orientace print.portrait Na Vý¹ku print.landscape Na ©íøku print.2side Tisknout Oboustrannì print.opts Mo¾nosti print.scale Pøizpùsobit velké moduly velikosti stránky. print.partition Rozdìlit velké moduly do více stránek. print.incidx Vlo¾it index. print.incgraph Vlo¾it graf hierarchie. print.4up Tisknout malé moduly 4 na stránku. print.range Výbìr Rozsahu print.fulltr Úplná Stopa print.parttr Èást Stopy print.start Start print.end Konec ############################################################################## # # Options dialog # opt.site Název Organizace opt.inst Instance opt.mods Moduly opt.modports Konektory modulù opt.frames Rámce opt.comment Komentáøe opt.hlink Hypertextové odkazy opt.wire 1-bitové vodièe opt.bus Vícebitové vodièe opt.tools Nástroje pro práci s hradly opt.cpath Citlivá cesta opt.grid Møí¾ka v simulátoru opt.logic1 Logická 1 opt.logic0 Logická 0 opt.float Plovoucí opt.unknown Nedefinována/Konfliktní opt.offled Nesvítící LED opt.onled Svítící LED opt.zled Plovoucí LED opt.restdef Obnovit pùvodní nastavení opt.regudate Aktualizace oblastí opt.smoothscroll Plynulé posouvání opt.outmove Pohyb popiskù modulu opt.balloon Povolit bublinovou nápovìdu opt.debug Povolit debugování opt.novice Zaèáteènický re¾im opt.ckpoint Provádìt prùbì¾né ukládání opt.freq Interval opt.beak Povolit speciální re¾imy opt.mode Re¾im opt.normal Normální opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatická kontrola integrity opt.showsimcmd Zaznamenat prùbìh simulace opt.logfile Logovací soubor simulátoru opt.estepsz Jednotky èasu/krok opt.cstepsz Hodinové cykly/krok opt.overstep Pøesah hodin opt.sorttraces Seøadit stopy podle abecedy opt.rememberprobes Pamatovat si umístìní sond opt.vpopupdelay Zpo¾dìní zobrazení hodnoty opt.initscript Inicializaèní skript opt.posedge Ukonèit hodinový cyklus na vzestupné hranì opt.setclock Ukonèit hodinový cyklus na opt.delayfilepath Soubor se zpo¾dìními opt.general Obecné opt.print Tisk opt.simulate Simulace opt.analysis Analýza opt.color Barvy opt.undolen Max poèet krokù zpìt (Undo) opt.cpopts Mo¾nosti citlivé cesty: opt.maxpath Maximální poèet cest: opt.cpflash Zobrazit blikající cestu opt.vercheck -begin- Pravidelnì kontrolovat pøítomnost nové verze TkGate na Internetu. Nevybírejte tuto mo¾nost pokud nemáte stálý pøístup k Internetu. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nový Modul blklst.delmod Smazat Modul blklst.frommod Kopírovat Modul Z blklst.tomod Do blklst.oldname Starý Název blklst.newname Nový Název blklst.claim Konvertovat Modul ############################################################################## # # Circuit Dialog box # circ.topmod Hlavní Modul circ.discchg Zru¹it Zmìny circ.iniscript Inicializaèní Skripty circ.noscript Nebyli vybrány ¾ádné soubory se skripty. circ.really1 Opravdu chcete odstranit circ.really2 ze seznamu inicializaèních skriptù. circ.extbar Pou¾ít Roz¹iøující Li¹ty ############################################################################## # Simulator # sim.breakpt Kontrolní Bod ############################################################################## # # Command box # cmd.file Název Souboru cmd.topname Název Hlavního Modulu ############################################################################## # # Critical path messages # cp.delay Zpo¾dìní Cesty: cp.pathl Seznam Cest: cp.numpath Poèet Cest: cp.recompute Pøepoèítat ############################################################################## # Error messages # err.verilog Chyby v souboru: err.nopin Vybraný konektor není mo¾no zmìnit. err.badhex Neplatná hexadecimální hodnota '%s' byla ignorována. err.gatanchor Hradlo(a) jsou ukotveny a nelze je pøemístit. err.libmode Neplatná operace s knihovním modulem (pro úpravy jej zmìòtì na u¾ivatelský modul). err.badfind Nelze najít cíl '%s'. err.badopendel Nelze smazat otevøený modul. err.nosrcmod Zdrojový modul '%s' nebyl nalezen. err.noerr Chybu nelze lokalizovat. err.misserr Informace o chybì nejsou kompletní (spadl simulátor?). err.pounimpl Neimplementovaná chyba v ParseOption err.badinadd Nelze pøidat dal¹í vstup k vybranému hradlu. err.badoutadd Nelze pøidat dal¹í výstup z vybraného hradla. err.badinoutadd Nelze pøidat dal¹í vst./výst. konektory k vybranému hradlu. err.badpinchg Nelze zmìnit typ konektoru na vybraném hradlu. err.badnetname Neplatné znaky v identifikátoru byly smazány. err.netbcrename Identifikátor pøejmenován na '%s' kvùli neplatným znakùm. err.netconfnet Identifikátor pøejmenován na '%s' kvùli konfliktu. err.netconfgat Identifikátor pøejmenován kvùli konfliktu s primitivním názvem hradla. err.netconfkw Identifikátor pøejmenován kvùli konfliktu s rezervovaným slovem. err.badconsame Spojení nepovoleno. Vodièe jsou souèástí stejné sítì. err.badconptsp Spojení nepovoleno. Vodièe jsou konektory modulu nebo jeho napájení. err.badconbitw Spojení nepovoleno. Bitové ¹íøky vodièù nejsou stejné. err.badrange Záporný rozsah stop není povolen. err.badlprcmd Nelze vykonat pøíkaz k tisku '%s'. err.badpsopen Nelze otevøít soubor '%s' pro postskriptový výstup. err.badid Neplatný identifikátor '%s'. err.bkpt.badexp Syntaktická chyba ve výrazu pro kontrolní bod. Výraz musí být jedno z: 'net', '!net', 'net==hodnota', 'net!=hodnota' err.bkpt.badnet Neplatný název sítì '%s'. Názvy musí zaèínat písmenem a obsahovat jenom písmena, èíslice a '.'. err.bkpt.badval Syntaktická chyba v hodnotì '%s'. Hodnota musí být desítkové èíslo nebo verilog-style konstanta. err.bkpt.toomany Pøíli¹ mnoho kontrolních bodù. Maximální poèet je %d. err.sim.badtmp Nelze ulo¾it doèasný soubor '%s' simulátoru (plný disk?). err.sim.syntx Syntaktická chyba v pøíkazu '%s'. err.sim.noincl Vkládaný soubor '%s' nenalezen. err.sim.clockbadedge Neplatná definice hrany '%c' v pøíkazu pro hodiny. err.sim.nobkpt Neexistující kontrolní bod '%s'. err.sim.nonet Sí» '%s' nebyla nalezena. err.sim.nogate Hradlo '%s' nebylo nalezeno. err.sim.badbin Neplatný znak v binární konstantì '%s'. err.sim.notswitch Hradlo '%s' není pøepínaè, dip nebo registr. err.sim.badcmd Neznámý pøíkaz '%s' v simulaèním skriptu. err.noteditpchg Vlastnosti mohou být mìnìny pouze v re¾imu úprav. err.badeditop Neplatná operace v re¾imu úprav rozhraní. err.badopen Nelze otevøít vstupní soubor '%s'. err.badlibopen Nelze otevøít knihovní soubor '%s'. err.nomark Pøed výbìrem typu hradla nastavte znaèku levým tlaèítkem my¹i. err.badgate Neznámý typ hradla. err.badmake Hradlo nelze vytvoøit. err.badportadd Nelze pøidat konektory k hradlùm tohoto typu. err.badportdel Vybraný konektor nelze smazat. err.badportedit Vybraný konektor nelze upravovat. err.noport Nebyly vybrány ¾ádné konektory. err.manypages -begin- V tomto dokumentu je pøí¹ernì mnoho stránek. Jste si jisti, ¾e je chcete v¹echny tisknout? -end- err.nojump -begin- Vlastnost 'jump-to-module' nemù¾e být pou¾ita v re¾imu simulace nebo analýzy citlivé cesty. Pøemístìte se prosím ruènì do cílového bloku tak, ¾e vyberete pøíslu¹né moduly a otevøete je stiskem klávesy '>'. Z modulu, ve kterém se nacházíte, je mo¾no vyskoèit stiskem klávesy '<'. -end- err.nomod Modul '%s' není definován. err.modlock Logický blok je uzamèen! err.closeroot Nelze zavøít hlavní modul. Pou¾ijte funkci 'Ukonèit' v hlavním menu. err.sim.isrun Simulátor u¾ bì¾í (Pou¾ijte 'Ctrl-s e' pro ukonèení). err.sim.isnotrun Simulátor nebì¾í (Pou¾ijte 'Ctrl-s b' pro start). err.editonly Neplatný pøíkaz v re¾imu simulace. err.simonly Pøíkaz platný jen v re¾imu simulace. err.nodel Nebyly vybrány objekty, které by bylo mo¾no smazat. err.modnotdef Modul '%s' není definován. err.moddef Blok '%s' ji¾ existuje. err.noprop Zvolené hradlo nemá vlastnosti, které by ¹lo mìnit. err.openscript Soubor se simulaèním skriptem '%s' nelze otevøít. err.oldversion Nahrán soubor ulo¾ený ve star¹í verzi TkGate %s (aktuální verze je %s). err.futureversion Nahraný soubor byl ulo¾en novìj¹í verzí TkGate %s (tato verze je %s). err.badversion Neznámé èíslo verze TkGate. Pou¾ívejte na vlastní riziko err.nodrive Sí» %s nemá ¾ádný driver v modulu %s. err.noconn Vodiè %s{%d} není nikam pøipojen - byl smazán. err.oldportact Pro pøidání/úpravu konektoru kliknìte pravým tlaèítkem na konektor nebo okraj modulu. err.backupfail Nelze vytvoøit zálo¾ní soubor '%s'. err.corruptnewsave -begin- Aplikace TkGate ulo¾ila vá¹ soubor jako '%s', ale zdá se být po¹kozený. Pokud máte povoleno prùbì¾né ukládání, zkuste nahrát nìkterý z prùbì¾nì ulo¾ených souboru. Pro kontrolu integrity ulo¾eného souboru pou¾ijte pøíkaz 'TkGate -V' -end- err.corruptsave -begin- Pøí pokusu ulo¾it soubor '%s' aplikace TkGate zjistila problém. Existující soubor nebyl zmìnìn a po¹kozený soubor byl zapsán jako '%s'. Pokud máte povoleno prùbì¾né ukládání, zkuste nahrát nìkterý z prùbì¾nì ulo¾ených souboru. Pro kontrolu integrity ulo¾eného souboru mù¾ete pou¾ít pøíkaz 'TkGate -V'. -end- err.badsave -begin- Pøi pokusu otevøít nebo ulo¾it soubor '%s' do¹lo k chybì. Zkontrolujte pøístupová práva souboru/adresáøe a/nebo místo na disku. -end- err.nosafesave -begin- Pøi pokusu ulo¾it soubor '%s' se vyskytl problém. Pokud chcete, zkuste to znova bez ovìøení korektnosti ulo¾ení. Pokud stisknete "ne", pùvodní soubor zùstane nezmìnìn. Pokus stisknete "ano", pùvodní soubor bude pøepsán, ale mù¾e být znièen, pokud se vyskytnou problémy. Chcete zkusit soubor ulo¾it bez ovìøení korektnosti ulo¾ení? -end- err.noback -begin- Soubor byl vytvoøen v TkGate verze %s, a nemusí být èitelný verzemi star¹ími ne¾ aktuální verze (%s) bude-li ulo¾en. -end- ############################################################################## # Informational messages # msg.selwire Vybrán vodiè s názvem '%s'. msg.selgate Vybráno hradlo s názvem '%s'. msg.selblock Vybrán %s blok s názvem '%s'. msg.modoverwt Cílový modul '%s' ji¾ existuje. Pøepsat? msg.foundgate Nalezeno hradlo '%s'. msg.foundwire Nalezen vodiè '%s'. msg.searchagn Cílový øetìzec '%s' nenalezen. Kliknìte na 'Najít' pro nové hledání. msg.sim.chgtoroot Re¾im simulace vy¾aduje koøenový modul na vrcholu editovacího zásobníku. msg.sim.nogatemod Re¾im simulace vy¾aduje konkrétní zásobník modulù. msg.setinterface Nastavení rozhraní modulu pro '%s'. msg.needsel Zvolte prosím instanci modulu. msg.wroteckpt Prùbì¾né ukládání %s... msg.save Obvod ulo¾en jako '%s'. msg.reallynew Obvod byl zmìnìn. Opravdu chcete zru¹it v¹echny zmìny a vytvoøit nový obvod? msg.reallyquit Obvod byl zmìnìn. Opravdu chcete ukonèit aplikaci? msg.notlib Modul '%s' není knihovní modul. ############################################################################## # Miles messages (Activated when Miles Bader uses TkGate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help # ho.new -begin- Smazat aktuální obvod a zaèít editovat nový. -end- ho.open Otevøít obvod ze souboru. ho.save Ulo¾it obvod do aktuálního souboru. ho.print Tisk aktuálního obvodu. ho.move -begin- Move/Connect - Kliknutím my¹í a pøetáhnutím mù¾ete: Nastavit novou pozici hradla Pøemístit hradla a vodièe Spojit vodièe Dvojitým kliknutím mù¾ete : Upravit vlastnosti hradla, vodièe a konektoru Upravit text komentáøe -end- ho.delgat -begin- Smazat hradlo - Pou¾ijte tento nástroj na smazání hradel. -end- ho.cutw -begin- Pøeru¹it vodiè - Pou¾ijte tento nástroj na pøeru¹ení vodièù. -end- ho.inv -begin- Invertovat - Pou¾ijte tento nástroj na pøidání nebo odebrání invertorù z konektorù hradel. -end- ho.bitw -begin- Bitová ¹íøka - Pou¾ijte tento nástroj na zmìnu bitové ¹íøky vodièù. Vlo¾te poèet bitù do políèka v pravém dolním rohu okna. -end- ho.modopen Otevøít vybraný modul. ho.modclose Zavøít aktuální modul. ho.undo Zpìt o pøedchozí krok(y). ho.redo Vpøed o zru¹ený krok(y). ho.simstart -begin- Spustit simulátor, otevøít logický analyzátor a vykonat inicializaèní skripty, pokud jsou definovány. -end- ho.simgo -begin- Spustit simulátor v re¾imu stálého bìhu. Poznámka: Simulace kombinaèních obvodù probíhá jen dokud obvod nedosáhne ustálený stav -end- ho.simpause -begin- Pozastavit právì bì¾ící simulaci. -end- ho.simstep -begin- Posunout se o pevný poèet jednotek èasu. Otevøete okno s mo¾nostmi simulace pro nastavení velikosti kroku. -end- ho.simclock -begin- Posunout se o pevný poèet hodinových cyklù. Otevøete okno s mo¾nostmi simulace pro nastavení velikosti kroku. -end- ho.simstop -begin- Ukonèit právì bì¾ící simulaci a vrátit se do editovacího re¾imu. -end- ho.simbreak -begin- Upravit aktuální kontrolní body. Simulace se zastaví ve chvíli, kdy se podmínka v kontrolním bodì stane pravdivou. -end- ho.simexec Vykonat simulaèní skript. ho.simload -begin- Nahrát obsah pamìti z .mem souboru. -end- ho.simdump -begin- Ulo¾it obsah pamìti do .mem souboru. -end- ho.sim.break -begin- Vlo¾it kontrolní bod simulace. Kontrolní body jsou výrazy, které, pokud se stanou pravdivými, zpùsobí zastavení simulace. Momentálnì jsou podporovány jenom jednoduché výrazy s jediným relaèním operátorem jako tøeba "w1 == 0" nebo "w7 != 8". Výrazy jako "w8" nebo "!w2" mù¾ou být rovnì¾ pou¾ity pro test na nenulovou resp. nulovou hodnotu. -end- ho.f.modlist -begin- Seznam v¹ech aktuálnì nahraných modulù. Hlavní modul je oznaèen znaménkém "+", knihovní moduly jsou v závorkách. -end- ho.netlist -begin- Seznam v¹ech sítí v aktuálním modulu. Sítì oznaèeny '@' mají skrytá jména Vícebitové sítì jsou zobrazeny s bitovou ¹íøkou na konci. -end- ho.ports -begin- Seznam v¹ech konektorù aktuálního modulu. Znaèka'>' oznaèuje vstup, '<' oznaèuje výstup a znaèka '=' vstup-výstup." -end- ho.status.logo -begin- Indikátor stavu simulace. Pokud ukazuje ¾eleznou bránu, TkGate je v editovacím re¾imu. Pokud ukazuje AND hradlo na ètyøech no¾ièkách, TkGate je v re¾imu simulace. Pokud hradlo AND stojí, simulace je pozastavena a pokud kráèí, simulace bì¾í -end- ho.status.msg Zde se zobrazují zprávy TkGate. ho.status.block Zásobník editovaných modulù. ho.status.file -begin- Aktuálnì editovaný soubor. Znak '*' ukazuje, ¾e od posledního ulo¾ení byl soubor zmìnìn. -end- ho.print.selall Vytisknout v¹echny moduly v aplikaci TkGate. ho.print.selcur Vytisknout jen aktuální modul v editovacím oknì aplikace TkGate. ho.print.seluse -begin- Vytisknout v¹echny "pou¾ívané" moduly. Pou¾ívané moduly jsou takové, které jsou potomky koøenového modulu. -end- ho.print.fulltrace Vytisknout celou stopu. ho.print.parttrace -begin- Vytisknout èást stopy. Vlo¾te èas zaèátku a konce stopy v okénku dole, nebo pou¾ijte pravé tlaèítko my¹i pro výbìr rozsahu v oknì simulace (pou¾ijte klávesy shift-pravá ¹ipka pro výbìr velkých rozsahù). -end- ho.print.parttracestart Èas zaèátku výstupu stopy. ho.print.parttraceend Èas konce výstupu stopy. ho.print.selsel -begin- Vytisknout jenom ní¾e vybrané moduly. Pou¾ijte klávesu Ctrl pro výbìr více modulù. -end- ho.print.modlist Vybrat moduly pro tisk. ho.circuit.discchg -begin- TkGate nezobrazí varování pokud zru¹íte zmìny bez toho, aby byly ulo¾eny. -end- ho.circuit.extbar -begin- Základní hradla (AND, OR, XOR) pou¾ijí roz¹iøující li¹ty pro manipulaci s více vstupy. -end- ho.cmd.bitw -begin- Vodièe vybrané kurzorem budou nastaveny na tuto bitovou ¹íøku -end- ho.edgat.extbar -begin- Pøi této volbì budou vícevstupová základní hradla pou¾ívat roz¹iøující li¹ty pøi pøidání dal¹ích vstupù k hradlu. -end- ho.edgat.signam -begin- Název vybraného signálu na vybraném hradlu. Zde mù¾ete zmìnit název signálu. -end- ho.edgat.port -begin- Název konektoru pro tento signál na tomto hradle. Toto pole mù¾e být upravováno pouze pro instance modulu. -end- ho.edgat.iolab -begin- Smìr vybraného signálu na vybraném hradle Toto pole mù¾e být upravováno pouze pro instance modulu. -end- ho.edgat.bitlab -begin- Bitová ¹íøka vybraného signálu na vybraném hradle. Zde mù¾ete zmìnit bitovou ¹íøku signálu. -end- ho.edgat.cycle Celkový poèet èasových jednotek v hodinovém cyklu. ho.edgat.phase Poèáteèní bod cyklu (v procentech). ho.edgat.duty Èást cyklu kde jsou hodiny na ni¾¹í hodnotì. ho.edgat.cname Název pøipojené sítì. ho.edgat.cport Konektor ke kterému je pøipojena sí». ho.edgat.ctype Typ pøipojení. ho.edgat.cbitw Bitová ¹íøka pøipojené sítì. ho.edgat.cedit Upravit vybraný konektor. ho.edgat.cadd Pøidat konektor. ho.edgat.cdel Smazat vybraný konektor. ho.edgat.hide -begin- Nastavte tento pøíznak pro zakázání zobrazení názvu hradla. -end- ho.edgat.gtype Typ hradla. ho.edgat.gname Název této instance hradla. ho.edgat.ganchor Nastavte tento pøíznak pro ukotvení pozice hradla. ho.edgat.gx X souøadnice hradla. ho.edgat.gy Y souøadnice hradla. ho.edgat.swstate -begin- Výchozí stav spínaèe, který bude pou¾it na zaèátku simulace. -end- ho.edgat.dipstate -begin- Výchozí stav dip spínaèe, který bude pou¾it na zaèátku simulace. -end- ho.edgat.range Bitový rozsah sbìrnice. ho.edgat.memfile -begin- Soubor s výchozím stavem pamìti. Tento soubor je naèten na zaèátku simulace. -end- ho.edgat.func Typ funkce tohoto modulu. ho.edgat.frame Popisek rámce. ho.traceprint Vytisknout logickou stopu ho.showxhair -begin- Je-li toto tlaèítko aktivní, v oknì simulace se objeví vertikální èára. -end- ho.opt.sorttraces -begin- Je-li tato mo¾nost aktivní, stopy v oknì simulace se zobrazí v setøídìném poøadí. Není-li tato mo¾nost aktivní, stopy v oknì simulace se zobrazí v tom poøadí, v jakém byly nastaveny sondy. -end- ho.opt.rememberprobes -begin- Je-li tato mo¾nost aktivní, v¹echny sondy nastaveny v re¾imu simulace se zapamatují a budou automaticky pøidány pøi opìtovném spu¹tìní simulace. -end- ho.opt.undolen -begin- Maximální poèet krokù zpátky, které se budou pamatovat. -end- ho.opt.site -begin- Jméno organizace, kde je TkGate nainstalováno. Toto jméno se pou¾ije na v¹ech výstupech na tiskárnu nebo do postskriptového souboru. -end- ho.opt.smooth -begin- Je-li tato mo¾nost aktivní, posouvání okna bude optimalizováno pou¾itím kopie bitmapy místo úplného znovuzobrazení. Mù¾ete tuto mo¾nost vypnout, pokud máte jakékoliv problémy s va¹ím serverem. -end- ho.opt.clip -begin- Je-li tato mo¾nost aktivní, pøi pøekreslování bude aktualizována jenom ta èást okna, která se momentálnì mìní. Jinak bude pøekreslována v¾dy celá obrazovka. -end- ho.opt.outmove -begin- Je-li tato mo¾nost aktivní, pøi pøetahování bude zobrazen pouze popisek instance modulu, která se právì pøemís»uje. Pou¾ívejte tuto vlastnost na poèítaèích s pomalým displejem. -end- ho.opt.bhelp -begin- Je-li tato mo¾nost aktivní, budou pou¾ívány bubliny s nápovìdou. Bubliny s nápovìdou (jako tato) obsahují vysvìtlení k jednotlivým polo¾kám, kdy¾ je nad nimi kurzor my¹i. -end- ho.opt.novice -begin- Pokud není na pøíkazovém øádku specifikován jiný obvod, pøi spu¹tìní aplikace bude jako výchozí obvod zobrazen TkGate tutoriál. -end- ho.opt.debug -begin- Povolit nìkolik debugovacích prvkù (u¾iteèné pouze pro TkGate vývojáøe). -end- ho.opt.ckpt Povolit prùbì¾né ukládání neulo¾ených obvodù. ho.opt.ckptfreq Frekvence prùbì¾ného ukládání v sekundách. ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .TkGate-preferences file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- Poèet jednotek èasu, o které se pøi jednom kroku postoupí dopøedu. -end- ho.opt.ckstep -begin- Poèet hodinových cyklù, o které se pøi jednom kroku postoupí dopøedu. -end- ho.opt.ckover -begin- Poèet jednotek èasu bezprostøednì po vzestupné hranì hodin, o které se pøi jednom kroku postoupí dopøedu. -end- ho.opt.vpopupdelay -begin- Zpo¾dìní v milisekundách mezi stisknutím a pøidr¾ením tlaèítka my¹i a zobrazením hodnoty signálu. Na nìkterých systémech jsou hodnoty zpo¾dìní v konfliktu se schopností rozpoznat dvouklik. Pokud máte tento problém, zvy¹te tuto hodnotu. Jsou povoleny hodnoty mezi 1 and 10000. -end- ho.opt.init -begin- Soubor se simulaèním skriptem, který bude automaticky vykonán pøi spu¹tìní simulace. -end- ho.opt.ckall -begin- Pokud je tento re¾im aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranì kterýchkoliv hodin v obvodu. -end- ho.opt.ckspec -begin- Pokud je tento re¾im aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranì specifikovaných hodin v obvodu. -end- ho.deftech -begin- Pøednastavená technologie pro nová hradla. Ovlivòuje zpo¾dìní hradel. Pro zmìnu technologie konkrétního hradla otevøete okno s jeho vlastnostmi (dvouklikem) a vyberte zálo¾ku "Zpo¾dìní". -end- ho.techbut -begin- Pou¾ít zpo¾dìní ze souboru definujícího standardní technologii. Nové technologie mù¾ete pøidat v menu "Soubor -> Mo¾nosti -> Simulace". -end- ho.custbut -begin- Nastavit vlastní hodnoty zpo¾dìní pro toto hradlo. -end- ho.contver -begin- Stále ovìøovat integritu vnitøních datových struktur po ka¾dé operaci. -end- ho.simwatch -begin- Zaznamenat pøíkazy zasílané mezi GUI a simulátorem. -end- ho.simlog -begin- Zapsat pøíkaz pou¾itý v simulátoru do logovacího souboru. Logovací soubor mù¾e být potom pou¾it jako vstup simulátoru v debugovacím re¾imu. -end- ho.cpathanal -begin- Najít citlivou cestu v obvodu. -end- tkgate-2.0-b10/locale/cs/messages.bak000644 001751 001751 00000074652 11134010127 020144 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Aug 5 11:24:01 2004 # Do ÄeÅ¡tiny pÅ™eložila Katarína Bubli Machálková (K.Machalkova@pod.cvut.cz) # Poslední aktualizace 3.srpna 2004 \font-encoding iso8859-2 \messages-encoding utf-8 \verilog-encoding iso8859-2 \language Czech ############################################################################## # # basic strings # b.dismiss ZruÅ¡it b.close Zavřít b.ok OK b.clear Znova b.cancel ZruÅ¡it b.open Otevřít... b.bitw Bitová Šířka b.in Vstup b.out Výstup b.inout Vst./Výst. b.browse Procházet... b.label Popisek b.find Najít b.edit Upravit... b.add PÅ™idat... b.delete Smazat b.deleteb Smazat... b.apply Použít b.anchor Ukotvit b.tech Technologie ############################################################################## # Menu strings # file Soubor edit Úpravy tool Nástroje simulate Simulace module Modul gate Hradlo make PÅ™idat circ Obvod new Nový open Otevřít... openlib Otevřít Knihovnu... save Uložit saveas Uložit Jako... print Tisk... options Možnosti... quit UkonÄit undo ZpÄ›t redo Znovu cut Vyjmout copy Kopírovat paste Vložit selall Vybrat VÅ¡e find Najít... algnv Uspořádat Ver. algnh Uspořádat Horiz. zoomin ZvÄ›tÅ¡it zoomout ZmenÅ¡it move PÅ™esunout/Spojit delg Smazat Hradlo cutw PÅ™eruÅ¡it VodiÄ inv Invertovat bitw Bitová Šířka debug Debug rot0 OtoÄit 0 rot90 OtoÄit 90 rot180 OtoÄit 180 rot270 OtoÄit 270 simbegin ZaÄít Simulaci simend UkonÄit Simulaci simadprobe PÅ™idat/Smazat Sondu simrun Spustit simpause PÅ™eruÅ¡it simstep Posun o Jednotku(y) ÄŒasu simcycle Posun o Hodinový Cyklus simbreak Kontrolní Bod... simscript Spustit Skript... simload Nahrát Obraz PamÄ›ti... simdump Uložit Obraz PamÄ›ti... modopen Otevřít modclose Zavřít modseti Nastavit Rozhraní modediti Upravit Rozhraní... modnew Nový... moddel Smazat... modcopy Kopírovat... modrename PÅ™ejmenovat... modclaim Konvertovat... circprop Vlastnosti Obvodu... cpath Citlivá Cesta... gataddin PÅ™idat Vstup gataddout PÅ™idat Výstup gataddinout PÅ™idat Vst./Výst. gatiochg ZmÄ›nit Typ gatanchor Ukotvit Vybrané gatunanchor Uvolnit Vybrané gatprop Vlastnosti... gatrep VytvoÅ™it Kopii gatdel Smazat gatsettech Nastavit Technologii gmswitch I/O gmgate Hradlo gmredgate Redukce gmmsi MSI gmalu ALU gmmem Paměť gmmod Modul gmcomment Komentář gmframe Rámec gmxswitch SpínaÄ gmdip DIP SpínaÄ gmground UzemnÄ›ní gmvdd Vdd gmmerge Spojení VodiÄů gmclock Hodiny gm.led LED gm.ledbar LED Panel gm.ledhex 7-Seg. LED (HEX) gm.leddec 7-Seg. LED (DEC) gm.ledseg 7-Seg. LED (Přímý kód) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf BudiÄ SbÄ›rnice gminv Invertor gmtribuf 3stav. BudiÄ SbÄ›rnice gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd SÄítaÄka gmmult NásobiÄka gmdiv DÄ›liÄka gmlshift Posun Doleva gmrshift Posun Doprava gmarshift Arit.Posun Doprava gmroll Rotace gmreg Registr gmff Klopný Obvod gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Dekodér gm14dec 1-4 Dekodér gm18dec 1-8 Dekodér gmmodinst Instance Modulu gmmodin Vstup Modulu gmmodout Výstup Module gmmodinout Vst./Výst. Modulu addwireseg PÅ™idat Segment VodiÄe help NápovÄ›da hlpabout O programu... hlplicense Licence... hlpdoc Dokumentace... hlptut Návody hlpexample Příklady exampcomb KombinaÄní Logika examp3bit 3-Bitový ČítaÄ examp8bit 8-Bitový ČítaÄ examptrff Transistorový KO exampcpu CviÄný CPU tutwelcome TkGate Intro tutcreate VytvoÅ™ení Obvodu tutedit1 Úpravy Obvodu (1) tutedit2 Úpravy Obvodu (2) tutmods Použití Modulů tutsim Simulace Obvodu # Scope Menu menu.sc.prtrace Tisknout Stopu... menu.sc.close Zavřít menu.sc.trace Stopa menu.sc.zoomin ZvÄ›tÅ¡it menu.sc.zoomout ZmenÅ¡it scope.emptymsg Dvojitým kliknutím na vodiÄ pÅ™idejte nebo smažte stopu. comment.empty [Dvojitým kliknutím pÅ™idejte text.] ############################################################################## # Interface strings # ifile Soubor imodule Modul iblmodule Moduly iports Konektory ibits Bity ############################################################################# # Net Dialog Box # db.net.name Název SítÄ› db.net.hide Skrýt Jméno db.net.bits Bitová Šířka db.net.port Typ Konektoru db.net.in Vstup db.net.out Výstup db.net.inout Vst./Výst. db.net.inets SítÄ› ############################################################################## # Gate dialog box # db.gate.signam Název Signálu db.gate.portnam Název Konektoru db.gate.iotype Typ db.gate.bitw Bitová Šířka db.gate.cyclew Šířka Cyklu db.gate.phase Fáze db.gate.duty Střída db.gate.port Konektor db.gate.bitws Bity db.gate.gtype Typ Hradla db.gate.gname Název Hradla db.gate.hidenam Skrýt Název db.gate.anchor Ukotvit db.gate.cpbreak PÅ™eruÅ¡ení Citlivé Cesty db.gate.butstate Stav TlaÄítka db.gate.dipval Hodnota PÅ™epínaÄe db.gate.memfilenam Soubor s Obsahem PamÄ›ti db.gate.modname Funkce db.gate.islink Text Je Hypertextový Odkaz db.gate.link Odkaz na Soubor db.gate.findw Hledat Pouze VodiÄe db.gate.findg Hledat Pouze Hradla db.gate.findwg Hledat VodiÄe i Hradla db.gate.general Obecné db.gate.details Detaily db.gate.ports Konektory db.gate.delay ZpoždÄ›ní db.gate.stddelay Standardní ZpoždÄ›ní db.gate.custdelay Definované ZpoždÄ›ní db.gate.extbar Použít RozÅ¡iÅ™ující LiÅ¡ty db.led.type Typ LED db.led.bit Dioda db.led.bar Panel diod db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Přímý kód) cpath.cloops -begin- Ve vaÅ¡em obvodu byla zjiÅ¡tÄ›na kombinaÄní smyÄka. Aby bylo možno provést analýzu zpoždÄ›ni v obvodu, musíte buÄ pÅ™eruÅ¡it smyÄku, nebo oznaÄit nÄ›které z hradel ve smyÄce jako bod "PÅ™eruÅ¡ení citlivé cesty". SítÄ›, v nichž byla zjiÅ¡tÄ›na smyÄka, jsou vypsány níže. -end- ############################################################################## # Print dialog box # print.outto Výstup do print.printer Tiskárna print.file Soubor print.prcmd Příkaz k Tisku print.filename Název Souboru print.epssave Uložit jako Encapsulated Postscript print.doctit Název Dokumentu print.prmod Tisknout Moduly print.epcm Jedn. Äasu/cm print.estpg Odhad PoÄtu Stránek print.all VÅ¡echny print.cur Aktuální print.use Použité print.sel Vybrané print.inclib Vložit Knihovní Moduly. print.papsz Velikost Papíru print.orient Orientace print.portrait Na Výšku print.landscape Na Šířku print.2side Tisknout OboustrannÄ› print.opts Možnosti print.scale PÅ™izpůsobit velké moduly velikosti stránky. print.partition RozdÄ›lit velké moduly do více stránek. print.incidx Vložit index. print.incgraph Vložit graf hierarchie. print.4up Tisknout malé moduly 4 na stránku. print.range VýbÄ›r Rozsahu print.fulltr Úplná Stopa print.parttr Část Stopy print.start Start print.end Konec ############################################################################## # # Options dialog # opt.site Název Organizace opt.inst Instance opt.mods Moduly opt.modports Konektory modulů opt.frames Rámce opt.comment Komentáře opt.hlink Hypertextové odkazy opt.wire 1-bitové vodiÄe opt.bus Vícebitové vodiÄe opt.tools Nástroje pro práci s hradly opt.cpath Citlivá cesta opt.grid Mřížka v simulátoru opt.logic1 Logická 1 opt.logic0 Logická 0 opt.float Plovoucí opt.unknown Nedefinována/Konfliktní opt.offled Nesvítící LED opt.onled Svítící LED opt.zled Plovoucí LED opt.restdef Obnovit původní nastavení opt.regudate Aktualizace oblastí opt.smoothscroll Plynulé posouvání opt.outmove Pohyb popisků modulu opt.balloon Povolit bublinovou nápovÄ›du opt.debug Povolit debugování opt.novice ZaÄáteÄnický režim opt.ckpoint ProvádÄ›t průběžné ukládání opt.freq Interval opt.beak Povolit speciální režimy opt.mode Režim opt.normal Normální opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatická kontrola integrity opt.showsimcmd Zaznamenat průbÄ›h simulace opt.logfile Logovací soubor simulátoru opt.estepsz Jednotky Äasu/krok opt.cstepsz Hodinové cykly/krok opt.overstep PÅ™esah hodin opt.sorttraces SeÅ™adit stopy podle abecedy opt.rememberprobes Pamatovat si umístÄ›ní sond opt.vpopupdelay ZpoždÄ›ní zobrazení hodnoty opt.initscript InicializaÄní skript opt.posedge UkonÄit hodinový cyklus na vzestupné hranÄ› opt.setclock UkonÄit hodinový cyklus na opt.delayfilepath Soubor se zpoždÄ›ními opt.general Obecné opt.print Tisk opt.simulate Simulace opt.analysis Analýza opt.color Barvy opt.undolen Max poÄet kroků zpÄ›t (Undo) opt.cpopts Možnosti citlivé cesty: opt.maxpath Maximální poÄet cest: opt.cpflash Zobrazit blikající cestu opt.vercheck -begin- PravidelnÄ› kontrolovat přítomnost nové verze TkGate na Internetu. Nevybírejte tuto možnost pokud nemáte stálý přístup k Internetu. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nový Modul blklst.delmod Smazat Modul blklst.frommod Kopírovat Modul Z blklst.tomod Do blklst.oldname Starý Název blklst.newname Nový Název blklst.claim Konvertovat Modul ############################################################################## # # Circuit Dialog box # circ.topmod Hlavní Modul circ.discchg ZruÅ¡it ZmÄ›ny circ.iniscript InicializaÄní Skripty circ.noscript Nebyli vybrány žádné soubory se skripty. circ.really1 Opravdu chcete odstranit circ.really2 ze seznamu inicializaÄních skriptů. circ.extbar Použít RozÅ¡iÅ™ující LiÅ¡ty ############################################################################## # Simulator # sim.breakpt Kontrolní Bod ############################################################################## # # Command box # cmd.file Název Souboru cmd.topname Název Hlavního Modulu ############################################################################## # # Critical path messages # cp.delay ZpoždÄ›ní Cesty: cp.pathl Seznam Cest: cp.numpath PoÄet Cest: cp.recompute PÅ™epoÄítat ############################################################################## # Error messages # err.verilog Chyby v souboru: err.nopin Vybraný konektor není možno zmÄ›nit. err.badhex Neplatná hexadecimální hodnota '%s' byla ignorována. err.gatanchor Hradlo(a) jsou ukotveny a nelze je pÅ™emístit. err.libmode Neplatná operace s knihovním modulem (pro úpravy jej změňtÄ› na uživatelský modul). err.badfind Nelze najít cíl '%s'. err.badopendel Nelze smazat otevÅ™ený modul. err.nosrcmod Zdrojový modul '%s' nebyl nalezen. err.noerr Chybu nelze lokalizovat. err.misserr Informace o chybÄ› nejsou kompletní (spadl simulátor?). err.pounimpl Neimplementovaná chyba v ParseOption err.badinadd Nelze pÅ™idat další vstup k vybranému hradlu. err.badoutadd Nelze pÅ™idat další výstup z vybraného hradla. err.badinoutadd Nelze pÅ™idat další vst./výst. konektory k vybranému hradlu. err.badpinchg Nelze zmÄ›nit typ konektoru na vybraném hradlu. err.badnetname Neplatné znaky v identifikátoru byly smazány. err.netbcrename Identifikátor pÅ™ejmenován na '%s' kvůli neplatným znakům. err.netconfnet Identifikátor pÅ™ejmenován na '%s' kvůli konfliktu. err.netconfgat Identifikátor pÅ™ejmenován kvůli konfliktu s primitivním názvem hradla. err.netconfkw Identifikátor pÅ™ejmenován kvůli konfliktu s rezervovaným slovem. err.badconsame Spojení nepovoleno. VodiÄe jsou souÄástí stejné sítÄ›. err.badconptsp Spojení nepovoleno. VodiÄe jsou konektory modulu nebo jeho napájení. err.badconbitw Spojení nepovoleno. Bitové šířky vodiÄů nejsou stejné. err.badrange Záporný rozsah stop není povolen. err.badlprcmd Nelze vykonat příkaz k tisku '%s'. err.badpsopen Nelze otevřít soubor '%s' pro postskriptový výstup. err.badid Neplatný identifikátor '%s'. err.bkpt.badexp Syntaktická chyba ve výrazu pro kontrolní bod. Výraz musí být jedno z: 'net', '!net', 'net==hodnota', 'net!=hodnota' err.bkpt.badnet Neplatný název sítÄ› '%s'. Názvy musí zaÄínat písmenem a obsahovat jenom písmena, Äíslice a '.'. err.bkpt.badval Syntaktická chyba v hodnotÄ› '%s'. Hodnota musí být desítkové Äíslo nebo verilog-style konstanta. err.bkpt.toomany PříliÅ¡ mnoho kontrolních bodů. Maximální poÄet je %d. err.sim.badtmp Nelze uložit doÄasný soubor '%s' simulátoru (plný disk?). err.sim.syntx Syntaktická chyba v příkazu '%s'. err.sim.noincl Vkládaný soubor '%s' nenalezen. err.sim.clockbadedge Neplatná definice hrany '%c' v příkazu pro hodiny. err.sim.nobkpt Neexistující kontrolní bod '%s'. err.sim.nonet Síť '%s' nebyla nalezena. err.sim.nogate Hradlo '%s' nebylo nalezeno. err.sim.badbin Neplatný znak v binární konstantÄ› '%s'. err.sim.notswitch Hradlo '%s' není pÅ™epínaÄ, dip nebo registr. err.sim.badcmd Neznámý příkaz '%s' v simulaÄním skriptu. err.noteditpchg Vlastnosti mohou být mÄ›nÄ›ny pouze v režimu úprav. err.badeditop Neplatná operace v režimu úprav rozhraní. err.badopen Nelze otevřít vstupní soubor '%s'. err.badlibopen Nelze otevřít knihovní soubor '%s'. err.nomark PÅ™ed výbÄ›rem typu hradla nastavte znaÄku levým tlaÄítkem myÅ¡i. err.badgate Neznámý typ hradla. err.badmake Hradlo nelze vytvoÅ™it. err.badportadd Nelze pÅ™idat konektory k hradlům tohoto typu. err.badportdel Vybraný konektor nelze smazat. err.badportedit Vybraný konektor nelze upravovat. err.noport Nebyly vybrány žádné konektory. err.manypages -begin- V tomto dokumentu je příšernÄ› mnoho stránek. Jste si jisti, že je chcete vÅ¡echny tisknout? -end- err.nojump -begin- Vlastnost 'jump-to-module' nemůže být použita v režimu simulace nebo analýzy citlivé cesty. PÅ™emístÄ›te se prosím ruÄnÄ› do cílového bloku tak, že vyberete přísluÅ¡né moduly a otevÅ™ete je stiskem klávesy '>'. Z modulu, ve kterém se nacházíte, je možno vyskoÄit stiskem klávesy '<'. -end- err.nomod Modul '%s' není definován. err.modlock Logický blok je uzamÄen! err.closeroot Nelze zavřít hlavní modul. Použijte funkci 'UkonÄit' v hlavním menu. err.sim.isrun Simulátor už běží (Použijte 'Ctrl-s e' pro ukonÄení). err.sim.isnotrun Simulátor neběží (Použijte 'Ctrl-s b' pro start). err.editonly Neplatný příkaz v režimu simulace. err.simonly Příkaz platný jen v režimu simulace. err.nodel Nebyly vybrány objekty, které by bylo možno smazat. err.modnotdef Modul '%s' není definován. err.moddef Blok '%s' již existuje. err.noprop Zvolené hradlo nemá vlastnosti, které by Å¡lo mÄ›nit. err.openscript Soubor se simulaÄním skriptem '%s' nelze otevřít. err.oldversion Nahrán soubor uložený ve starší verzi TkGate %s (aktuální verze je %s). err.futureversion Nahraný soubor byl uložen novÄ›jší verzí TkGate %s (tato verze je %s). err.badversion Neznámé Äíslo verze TkGate. Používejte na vlastní riziko err.nodrive Síť %s nemá žádný driver v modulu %s. err.noconn VodiÄ %s{%d} není nikam pÅ™ipojen - byl smazán. err.oldportact Pro pÅ™idání/úpravu konektoru kliknÄ›te pravým tlaÄítkem na konektor nebo okraj modulu. err.backupfail Nelze vytvoÅ™it záložní soubor '%s'. err.corruptnewsave -begin- Aplikace TkGate uložila váš soubor jako '%s', ale zdá se být poÅ¡kozený. Pokud máte povoleno průběžné ukládání, zkuste nahrát nÄ›který z průběžnÄ› uložených souboru. Pro kontrolu integrity uloženého souboru použijte příkaz 'TkGate -V' -end- err.corruptsave -begin- Pří pokusu uložit soubor '%s' aplikace TkGate zjistila problém. Existující soubor nebyl zmÄ›nÄ›n a poÅ¡kozený soubor byl zapsán jako '%s'. Pokud máte povoleno průběžné ukládání, zkuste nahrát nÄ›který z průběžnÄ› uložených souboru. Pro kontrolu integrity uloženého souboru můžete použít příkaz 'TkGate -V'. -end- err.badsave -begin- PÅ™i pokusu otevřít nebo uložit soubor '%s' doÅ¡lo k chybÄ›. Zkontrolujte přístupová práva souboru/adresáře a/nebo místo na disku. -end- err.nosafesave -begin- PÅ™i pokusu uložit soubor '%s' se vyskytl problém. Pokud chcete, zkuste to znova bez ověření korektnosti uložení. Pokud stisknete "ne", původní soubor zůstane nezmÄ›nÄ›n. Pokus stisknete "ano", původní soubor bude pÅ™epsán, ale může být zniÄen, pokud se vyskytnou problémy. Chcete zkusit soubor uložit bez ověření korektnosti uložení? -end- err.noback -begin- Soubor byl vytvoÅ™en v TkGate verze %s, a nemusí být Äitelný verzemi staršími než aktuální verze (%s) bude-li uložen. -end- ############################################################################## # Informational messages # msg.selwire Vybrán vodiÄ s názvem '%s'. msg.selgate Vybráno hradlo s názvem '%s'. msg.selblock Vybrán %s blok s názvem '%s'. msg.modoverwt Cílový modul '%s' již existuje. PÅ™epsat? msg.foundgate Nalezeno hradlo '%s'. msg.foundwire Nalezen vodiÄ '%s'. msg.searchagn Cílový Å™etÄ›zec '%s' nenalezen. KliknÄ›te na 'Najít' pro nové hledání. msg.sim.chgtoroot Režim simulace vyžaduje koÅ™enový modul na vrcholu editovacího zásobníku. msg.sim.nogatemod Režim simulace vyžaduje konkrétní zásobník modulů. msg.setinterface Nastavení rozhraní modulu pro '%s'. msg.needsel Zvolte prosím instanci modulu. msg.wroteckpt Průběžné ukládání %s... msg.save Obvod uložen jako '%s'. msg.reallynew Obvod byl zmÄ›nÄ›n. Opravdu chcete zruÅ¡it vÅ¡echny zmÄ›ny a vytvoÅ™it nový obvod? msg.reallyquit Obvod byl zmÄ›nÄ›n. Opravdu chcete ukonÄit aplikaci? msg.notlib Modul '%s' není knihovní modul. ############################################################################## # Miles messages (Activated when Miles Bader uses TkGate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help # ho.new -begin- Smazat aktuální obvod a zaÄít editovat nový. -end- ho.open Otevřít obvod ze souboru. ho.save Uložit obvod do aktuálního souboru. ho.print Tisk aktuálního obvodu. ho.move -begin- Move/Connect - Kliknutím myší a pÅ™etáhnutím můžete: Nastavit novou pozici hradla PÅ™emístit hradla a vodiÄe Spojit vodiÄe Dvojitým kliknutím můžete : Upravit vlastnosti hradla, vodiÄe a konektoru Upravit text komentáře -end- ho.delgat -begin- Smazat hradlo - Použijte tento nástroj na smazání hradel. -end- ho.cutw -begin- PÅ™eruÅ¡it vodiÄ - Použijte tento nástroj na pÅ™eruÅ¡ení vodiÄů. -end- ho.inv -begin- Invertovat - Použijte tento nástroj na pÅ™idání nebo odebrání invertorů z konektorů hradel. -end- ho.bitw -begin- Bitová šířka - Použijte tento nástroj na zmÄ›nu bitové šířky vodiÄů. Vložte poÄet bitů do políÄka v pravém dolním rohu okna. -end- ho.modopen Otevřít vybraný modul. ho.modclose Zavřít aktuální modul. ho.undo ZpÄ›t o pÅ™edchozí krok(y). ho.redo VpÅ™ed o zruÅ¡ený krok(y). ho.simstart -begin- Spustit simulátor, otevřít logický analyzátor a vykonat inicializaÄní skripty, pokud jsou definovány. -end- ho.simgo -begin- Spustit simulátor v režimu stálého bÄ›hu. Poznámka: Simulace kombinaÄních obvodů probíhá jen dokud obvod nedosáhne ustálený stav -end- ho.simpause -begin- Pozastavit právÄ› běžící simulaci. -end- ho.simstep -begin- Posunout se o pevný poÄet jednotek Äasu. OtevÅ™ete okno s možnostmi simulace pro nastavení velikosti kroku. -end- ho.simclock -begin- Posunout se o pevný poÄet hodinových cyklů. OtevÅ™ete okno s možnostmi simulace pro nastavení velikosti kroku. -end- ho.simstop -begin- UkonÄit právÄ› běžící simulaci a vrátit se do editovacího režimu. -end- ho.simbreak -begin- Upravit aktuální kontrolní body. Simulace se zastaví ve chvíli, kdy se podmínka v kontrolním bodÄ› stane pravdivou. -end- ho.simexec Vykonat simulaÄní skript. ho.simload -begin- Nahrát obsah pamÄ›ti z .mem souboru. -end- ho.simdump -begin- Uložit obsah pamÄ›ti do .mem souboru. -end- ho.sim.break -begin- Vložit kontrolní bod simulace. Kontrolní body jsou výrazy, které, pokud se stanou pravdivými, způsobí zastavení simulace. MomentálnÄ› jsou podporovány jenom jednoduché výrazy s jediným relaÄním operátorem jako tÅ™eba "w1 == 0" nebo "w7 != 8". Výrazy jako "w8" nebo "!w2" můžou být rovněž použity pro test na nenulovou resp. nulovou hodnotu. -end- ho.f.modlist -begin- Seznam vÅ¡ech aktuálnÄ› nahraných modulů. Hlavní modul je oznaÄen znaménkém "+", knihovní moduly jsou v závorkách. -end- ho.netlist -begin- Seznam vÅ¡ech sítí v aktuálním modulu. SítÄ› oznaÄeny '@' mají skrytá jména Vícebitové sítÄ› jsou zobrazeny s bitovou šířkou na konci. -end- ho.ports -begin- Seznam vÅ¡ech konektorů aktuálního modulu. ZnaÄka'>' oznaÄuje vstup, '<' oznaÄuje výstup a znaÄka '=' vstup-výstup." -end- ho.status.logo -begin- Indikátor stavu simulace. Pokud ukazuje železnou bránu, TkGate je v editovacím režimu. Pokud ukazuje AND hradlo na ÄtyÅ™ech nožiÄkách, TkGate je v režimu simulace. Pokud hradlo AND stojí, simulace je pozastavena a pokud kráÄí, simulace běží -end- ho.status.msg Zde se zobrazují zprávy TkGate. ho.status.block Zásobník editovaných modulů. ho.status.file -begin- AktuálnÄ› editovaný soubor. Znak '*' ukazuje, že od posledního uložení byl soubor zmÄ›nÄ›n. -end- ho.print.selall Vytisknout vÅ¡echny moduly v aplikaci TkGate. ho.print.selcur Vytisknout jen aktuální modul v editovacím oknÄ› aplikace TkGate. ho.print.seluse -begin- Vytisknout vÅ¡echny "používané" moduly. Používané moduly jsou takové, které jsou potomky koÅ™enového modulu. -end- ho.print.fulltrace Vytisknout celou stopu. ho.print.parttrace -begin- Vytisknout Äást stopy. Vložte Äas zaÄátku a konce stopy v okénku dole, nebo použijte pravé tlaÄítko myÅ¡i pro výbÄ›r rozsahu v oknÄ› simulace (použijte klávesy shift-pravá Å¡ipka pro výbÄ›r velkých rozsahů). -end- ho.print.parttracestart ÄŒas zaÄátku výstupu stopy. ho.print.parttraceend ÄŒas konce výstupu stopy. ho.print.selsel -begin- Vytisknout jenom níže vybrané moduly. Použijte klávesu Ctrl pro výbÄ›r více modulů. -end- ho.print.modlist Vybrat moduly pro tisk. ho.circuit.discchg -begin- TkGate nezobrazí varování pokud zrušíte zmÄ›ny bez toho, aby byly uloženy. -end- ho.circuit.extbar -begin- Základní hradla (AND, OR, XOR) použijí rozÅ¡iÅ™ující liÅ¡ty pro manipulaci s více vstupy. -end- ho.cmd.bitw -begin- VodiÄe vybrané kurzorem budou nastaveny na tuto bitovou šířku -end- ho.edgat.extbar -begin- PÅ™i této volbÄ› budou vícevstupová základní hradla používat rozÅ¡iÅ™ující liÅ¡ty pÅ™i pÅ™idání dalších vstupů k hradlu. -end- ho.edgat.signam -begin- Název vybraného signálu na vybraném hradlu. Zde můžete zmÄ›nit název signálu. -end- ho.edgat.port -begin- Název konektoru pro tento signál na tomto hradle. Toto pole může být upravováno pouze pro instance modulu. -end- ho.edgat.iolab -begin- SmÄ›r vybraného signálu na vybraném hradle Toto pole může být upravováno pouze pro instance modulu. -end- ho.edgat.bitlab -begin- Bitová šířka vybraného signálu na vybraném hradle. Zde můžete zmÄ›nit bitovou šířku signálu. -end- ho.edgat.cycle Celkový poÄet Äasových jednotek v hodinovém cyklu. ho.edgat.phase PoÄáteÄní bod cyklu (v procentech). ho.edgat.duty Část cyklu kde jsou hodiny na nižší hodnotÄ›. ho.edgat.cname Název pÅ™ipojené sítÄ›. ho.edgat.cport Konektor ke kterému je pÅ™ipojena síť. ho.edgat.ctype Typ pÅ™ipojení. ho.edgat.cbitw Bitová šířka pÅ™ipojené sítÄ›. ho.edgat.cedit Upravit vybraný konektor. ho.edgat.cadd PÅ™idat konektor. ho.edgat.cdel Smazat vybraný konektor. ho.edgat.hide -begin- Nastavte tento příznak pro zakázání zobrazení názvu hradla. -end- ho.edgat.gtype Typ hradla. ho.edgat.gname Název této instance hradla. ho.edgat.ganchor Nastavte tento příznak pro ukotvení pozice hradla. ho.edgat.gx X souÅ™adnice hradla. ho.edgat.gy Y souÅ™adnice hradla. ho.edgat.swstate -begin- Výchozí stav spínaÄe, který bude použit na zaÄátku simulace. -end- ho.edgat.dipstate -begin- Výchozí stav dip spínaÄe, který bude použit na zaÄátku simulace. -end- ho.edgat.range Bitový rozsah sbÄ›rnice. ho.edgat.memfile -begin- Soubor s výchozím stavem pamÄ›ti. Tento soubor je naÄten na zaÄátku simulace. -end- ho.edgat.func Typ funkce tohoto modulu. ho.edgat.frame Popisek rámce. ho.traceprint Vytisknout logickou stopu ho.showxhair -begin- Je-li toto tlaÄítko aktivní, v oknÄ› simulace se objeví vertikální Äára. -end- ho.opt.sorttraces -begin- Je-li tato možnost aktivní, stopy v oknÄ› simulace se zobrazí v setřídÄ›ném poÅ™adí. Není-li tato možnost aktivní, stopy v oknÄ› simulace se zobrazí v tom poÅ™adí, v jakém byly nastaveny sondy. -end- ho.opt.rememberprobes -begin- Je-li tato možnost aktivní, vÅ¡echny sondy nastaveny v režimu simulace se zapamatují a budou automaticky pÅ™idány pÅ™i opÄ›tovném spuÅ¡tÄ›ní simulace. -end- ho.opt.undolen -begin- Maximální poÄet kroků zpátky, které se budou pamatovat. -end- ho.opt.site -begin- Jméno organizace, kde je TkGate nainstalováno. Toto jméno se použije na vÅ¡ech výstupech na tiskárnu nebo do postskriptového souboru. -end- ho.opt.smooth -begin- Je-li tato možnost aktivní, posouvání okna bude optimalizováno použitím kopie bitmapy místo úplného znovuzobrazení. Můžete tuto možnost vypnout, pokud máte jakékoliv problémy s vaším serverem. -end- ho.opt.clip -begin- Je-li tato možnost aktivní, pÅ™i pÅ™ekreslování bude aktualizována jenom ta Äást okna, která se momentálnÄ› mÄ›ní. Jinak bude pÅ™ekreslována vždy celá obrazovka. -end- ho.opt.outmove -begin- Je-li tato možnost aktivní, pÅ™i pÅ™etahování bude zobrazen pouze popisek instance modulu, která se právÄ› pÅ™emísÅ¥uje. Používejte tuto vlastnost na poÄítaÄích s pomalým displejem. -end- ho.opt.bhelp -begin- Je-li tato možnost aktivní, budou používány bubliny s nápovÄ›dou. Bubliny s nápovÄ›dou (jako tato) obsahují vysvÄ›tlení k jednotlivým položkám, když je nad nimi kurzor myÅ¡i. -end- ho.opt.novice -begin- Pokud není na příkazovém řádku specifikován jiný obvod, pÅ™i spuÅ¡tÄ›ní aplikace bude jako výchozí obvod zobrazen TkGate tutoriál. -end- ho.opt.debug -begin- Povolit nÄ›kolik debugovacích prvků (užiteÄné pouze pro TkGate vývojáře). -end- ho.opt.ckpt Povolit průběžné ukládání neuložených obvodů. ho.opt.ckptfreq Frekvence průběžného ukládání v sekundách. ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .TkGate-preferences file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- PoÄet jednotek Äasu, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.ckstep -begin- PoÄet hodinových cyklů, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.ckover -begin- PoÄet jednotek Äasu bezprostÅ™ednÄ› po vzestupné hranÄ› hodin, o které se pÅ™i jednom kroku postoupí dopÅ™edu. -end- ho.opt.vpopupdelay -begin- ZpoždÄ›ní v milisekundách mezi stisknutím a pÅ™idržením tlaÄítka myÅ¡i a zobrazením hodnoty signálu. Na nÄ›kterých systémech jsou hodnoty zpoždÄ›ní v konfliktu se schopností rozpoznat dvouklik. Pokud máte tento problém, zvyÅ¡te tuto hodnotu. Jsou povoleny hodnoty mezi 1 and 10000. -end- ho.opt.init -begin- Soubor se simulaÄním skriptem, který bude automaticky vykonán pÅ™i spuÅ¡tÄ›ní simulace. -end- ho.opt.ckall -begin- Pokud je tento režim aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranÄ› kterýchkoliv hodin v obvodu. -end- ho.opt.ckspec -begin- Pokud je tento režim aktivní, posunutí o hodinový cyklus zastaví simulaci na vzestupné hranÄ› specifikovaných hodin v obvodu. -end- ho.deftech -begin- PÅ™ednastavená technologie pro nová hradla. Ovlivňuje zpoždÄ›ní hradel. Pro zmÄ›nu technologie konkrétního hradla otevÅ™ete okno s jeho vlastnostmi (dvouklikem) a vyberte záložku "ZpoždÄ›ní". -end- ho.techbut -begin- Použít zpoždÄ›ní ze souboru definujícího standardní technologii. Nové technologie můžete pÅ™idat v menu "Soubor -> Možnosti -> Simulace". -end- ho.custbut -begin- Nastavit vlastní hodnoty zpoždÄ›ní pro toto hradlo. -end- ho.contver -begin- Stále ověřovat integritu vnitÅ™ních datových struktur po každé operaci. -end- ho.simwatch -begin- Zaznamenat příkazy zasílané mezi GUI a simulátorem. -end- ho.simlog -begin- Zapsat příkaz použitý v simulátoru do logovacího souboru. Logovací soubor může být potom použit jako vstup simulátoru v debugovacím režimu. -end- ho.cpathanal -begin- Najít citlivou cestu v obvodu. -end- tkgate-2.0-b10/locale/fr/messages000644 001751 001751 00000070157 11134010406 017406 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed Apr 6 23:43:13 2005 # # Traduction effectuée par Laurent.Bonnaud@iut2.upmf-grenoble.fr # \language French ############################################################################## # # basic strings # b.dismiss Annuler b.close Fermer b.ok OK b.clear Effacer b.cancel Annuler b.open Ouvrir... b.bitw Largeur de bus b.in entrée b.out sortie b.inout E/S b.browse Parcourir... b.label Étiquette b.find Chercher b.edit Éditer... b.add Ajouter... b.delete Supprimer b.deleteb Supprimer... b.apply Appliquer b.anchor Ancre b.tech Technologie ############################################################################## # Menu strings # menu.file Fichier menu.edit Éditer menu.tool Outils menu.simulate Simuler menu.module Module menu.format Élément menu.make Ajouter menu.circ Circuit menu.file.new Nouveau circuit menu.file.open Ouvrir... menu.file.openlib Ouvrir bibliothèque... menu.file.save Sauver menu.file.saveas Sauver... menu.file.print Imprimer... menu.tool.options Options... menu.file.quit Quitter menu.file.cprop Propriétés du circuit... menu.edit.cut Couper menu.edit.copy Copier menu.edit.paste Coller menu.edit.selall Tout sélectionner menu.edit.find Chercher... menu.format.algnv Aligner Vert. menu.format.algnh Aligner Horz. menu.edit.zoomin Zoom + menu.edit.zoomout Zoom - menu.tool.move Déplacer/Connecter menu.tool.delg Supprimer élément menu.tool.cutw Couper connexion menu.tool.inv Poser inverseurs menu.tool.bitw Largeur de connexion menu.tool.debug Debug menu.format.rot.0 Rot. 0 menu.format.rot.90 Rot. 90 menu.format.rot.180 Rot. 180 menu.format.rot.270 Rot. 270 menu.simulate.begin Commencer simulation menu.simulate.end Terminer simulation menu.simulate.run Lancer menu.simulate.pause Pause menu.simulate.step Avancer d'un quantum menu.simulate.cycle Avancer d'un cycle menu.simulate.break Point d'arrêt... menu.simulate.script Exécuter Script... menu.simulate.load Charger mémoire... menu.simulate.dump Sauver mémoire... menu.module.open Ouvrir menu.module.close Fermer menu.module.new Nouveau... menu.module.del Supprimer... menu.module.copy Copier... menu.module.rename Renommer... menu.module.claim Claim... menu.interface.set Appliquer interface menu.interface.edit Éditer interfaces... menu.circ.path Chemin critique... menu.gate.addin Ajouter entrée menu.gate.addout Ajouter sortie menu.gate.addinout Ajouter E/S menu.gate.iochg Changer type menu.format.anchor Ancrer la sélection menu.format.unanchor Dé-ancrer la sélection menu.format.prop Propriétés... menu.tool.rep Répliquer menu.format.del Supprimer menu.format.settech Choisir technologie # Scope Menu menu.scope.prtrace Imprimer chronogramme... menu.scope.close Fermer menu.scope.trace Chronogramme menu.scope.zoomin Zoom + menu.scope.zoomout Zoom - gm.switch E/S gm.gate Porte gm.rgate Réduction gm.msi MSI gm.alu UAL gm.mem Mémoire gm.mod Module gm.comment Commentaire gm.frame Cadre gm.io.switch Interrupteur gm.io.dip Interrupteurs gm.io.ground Terre gm.io.vdd Vdd gm.io.merge Fusionner connexions gm.io.clock Horloge gm.io.led Diode gm.io.ledbar Barre de diodes gm.io.ledhex chiffre (hexa) gm.io.leddec chiffre (décimal) gm.io.ledseg chiffre (direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Additionneur gm.alu.mult Multiplicateur gm.alu.div Diviseur gm.alu.lshift Décalage à gauche gm.alu.rshift Décalage à droite gm.alu.arshift Décalage à droite arithmétique gm.alu.roll Permutation circulaire gm.mem.reg Registre gm.mem.ff Bascule D gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexeur gm.msi.41mux 4-1 Multiplexeur gm.msi.81mux 8-1 Multiplexeur gm.msi.12dec 1-2 Décodeur gm.msi.14dec 1-4 Décodeur gm.msi.18dec 1-8 Décodeur gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut addwireseg Ajouter une dérivation help Aide hlpabout À propos... hlplicense License... hlpdoc Documentation... hlptut Didacticiel hlpexample Exemples exampcomb Logique combinatoire examp3bit Compteur 3 bits examp8bit Compteur 8 bits examptrff FF niveau transistor exampcpu Processeur "Ménagerie" tutwelcome Introduction à TkGate tutcreate Création d'un circuit tutedit1 Édition d'un circuit (1) tutedit2 Édition d'un circuit (2) tutmods Utilisation des modules tutsim Simulation d'un circuit ############################################################################## # Interface strings # ifile Fichier imodule Module iblmodule Modules : iports Ports : ibits Bits : ############################################################################# # Net Dialog Box # db.net.name Nom de la connexion db.net.hide Cacher le nom db.net.bits Largeur de bus db.net.port Type de port db.net.in entrée db.net.out sortie db.net.inout E/S db.net.inets Connexion ############################################################################## # Gate dialog box # db.gate.signam Nom du signal db.gate.portnam Nom du port db.gate.iotype Type db.gate.bitw Nombre de bits db.gate.cyclew Largeur de cycle db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.gtype Type d'élément db.gate.gname Nom de l'élément db.gate.hidenam Cacher le nom db.gate.anchor Ancré db.gate.cpbreak Partition du chemin critique db.gate.butstate État de l'interrupteur db.gate.dipval Valeur de l'interrupteur db.gate.memfilenam Fichier de la mémoire db.gate.modname Fonction db.gate.islink Hypertexte db.gate.link Lier au fichier db.gate.findw Chercher des connexions uniquement db.gate.findg Chercher des éléments uniquement db.gate.findwg Chercher des connexions et des éléments db.gate.general Général db.gate.details Détails db.gate.ports Port db.gate.delay Délai db.gate.stddelay Délai standard db.gate.custdelay Délai personnalisé db.led.type Type de diode db.led.bit Bit db.led.bar Bar Graph db.led.hex chiffre (hexa) db.led.dec chiffre (décimal) db.led.seg chiffre (Direct) cpath.cloops -begin- Une boucle a été détectée dans votre circuit. Afin de pouvoir effectuer une analyse des délais sur ce circuit, vous devez soit 1. faire disparaître cette boucle 2. marquer certaines portes de la boucle comme un point de "Partition du chemin critique". Les connexions formant une boucle sont listées ci-dessous. -end- ############################################################################## # Print dialog box # print.outto Imprimer vers print.printer Imprimante print.file Fichier print.prcmd Commande d'impression print.filename Nom de fichier print.epssave Sauver en Postscript encapsulé print.doctit Titre du document print.prmod Impression des modules : print.epcm Quanta/cm print.estpg Nombre de pages estimé print.all Tous print.cur Courant print.use Utilisé print.sel Sélectionné print.inclib Inclure les modules des bibliothèques print.papsz Format de papier print.orient Orientation print.portrait Portrait print.landscape Paysage print.2side Imprimer en double face (recto-verso) print.opts Options print.scale Réduction des gros modules pour tenir sur une page print.partition Impression des gros modules sur plusieurs pages print.incidx Inclure l'index print.incgraph Inclure le graphe de hiérarchie print.4up Impression des petits modules 4 par page print.range Sélection d'intervalle print.fulltr Trace complète print.parttr Trace partielle print.start Démarrer print.end Fin ############################################################################## # # Options dialog # opt.site Nom du site opt.inst Instances opt.mods Modules opt.modports Ports d'un module opt.frames Cadres opt.comment Commentaires opt.hlink Hyperliens opt.wire Connexions 1 bit opt.bus Connexions n bits opt.tools Outils pour porte opt.cpath Chemin critique opt.grid Scope Grid opt.logic1 1 logique opt.logic0 0 logique opt.float Flottant opt.unknown Inconnu/Conflit opt.offled Diode éteinte opt.onled Diode allumée opt.zled Floating LED opt.restdef Restaurer valeurs par défaut opt.regudate Réaffichage minimal opt.smoothscroll Défilement fluide opt.outmove Déplacement d'un fantôme opt.balloon Activer les infobulles opt.debug Activer la mise au point opt.novice Mode débutant opt.ckpoint Sauvegarde automatique opt.freq intervalle opt.beak Activer les modes spéciaux opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.showsimcmd Afficher les commandes du simulateur opt.logfile Fichier journal du simulateur opt.estepsz Avance rapide par quanta (nombre de quanta) opt.cstepsz Avance rapide par cycles d'horloges (nombre de cycles) opt.overstep Arrêt débordant sur cycle d'horloge (nombre de quanta) opt.initscript Script d'initialisation opt.posedge Le mode pas à pas sur les cycles d'horloge s'arrête sur tous les fronts montants opt.setclock Le mode pas à pas sur les cycles d'horloge s'arrête sur l'horloge opt.delayfilepath Fichiers contenant les délais opt.general Général opt.print Impression opt.simulate Simulation opt.analysis Analyse opt.color Couleurs opt.cpopts Options pour chemin critique : opt.maxpath Nombre maximal de chemins : opt.cpflash Affichage avec chemin clignotant opt.vercheck -begin- Vérifier automatiquement la sortie d'une nouvelle version de tkgate sur Internet. Ne pas activer à moins d'avoir une connexion permanente à Internet. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nouveau module blklst.delmod Supprimer module blklst.frommod Copier module depuis blklst.tomod Vers blklst.oldname Ancien nom blklst.newname Nouveau nom blklst.claim Claim Module ############################################################################## # # Circuit Dialog box # circ.topmod Module principal circ.discchg annuler changements circ.iniscript Scripts d'initialisation circ.noscript Pas de fichier script sélectionné. circ.really1 Voulez-vous vraiment supprimer circ.really2 de la liste des scripts d'initialisation ? ############################################################################## # Simulator # sim.breakpt Point d'arrêt ############################################################################## # # Command box # cmd.file Nom du fichier cmd.topname Nom du module principal ############################################################################## # # Critical path messages # cp.delay Délai sur chemin : cp.pathl Chemin : cp.numpath Nombre de chemins : cp.recompute Recalculer ############################################################################## # Error messages - Messages d'erreur # err.verilog Erreurs dans le fichier : err.nopin Impossible de changer la patte sélectionnée. err.badhex Valeur hexadécimale illégale ('%s') ignorée. err.gatanchor Les éléments sont ancrés et ne peuvent pas être déplacés. err.libmode Opération illégale sur un module de bibliothèque (convertir le module en module normal pour pouvoir l'éditer). err.badfind Impossible de trouver la cible '%s'. err.badopendel Impossible de supprimer un module ouvert. err.nosrcmod Module source '%s' non trouvé. err.noerr Impossible de trouver l'erreur. err.misserr Information sur l'erreur incomplète (plantage du simulateur ?) err.pounimpl Erreur non implémentée dans ParseOption err.badinadd Impossible d'ajouter plus d'entrées à l'élément sélectionné. err.badoutadd Impossible d'ajouter plus de sorties à l'élément sélectionné. err.badinoutadd Impossible d'ajouter plus de pattes d'E/S à l'élément sélectionné. err.badpinchg Impossible de changer le type de patte pour l'élément sélectionné. err.badnetname Caractères illégaux supprimés dans l'identificateur. err.netbcrename Identificateur renommé en '%s' à cause de caractères illégaux. err.netconfnet Identificateur renommé en '%s' à cause d'un conflit de noms. err.netconfgat Identificateur renommé pour éviter un conflit avec un nom d'élément. err.netconfkw Identificateur renommé pour éviter un conflit avec mot réservé. err.badconsame Connexion refusée car les fils font partie du même bus. err.badconptsp Connexion refusée car les deux fils sont des ports de modules ou des ??. err.badconbitw Connexion refusée car les largeurs des bus sont différentes. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Impossible d'exécuter la commande d'impression '%s'. err.badpsopen Impossible d'ouvrir le fichier '%s' pour une sortie PostScript. err.bkpt.badexp Erreur de syntaxe dans l'expression du point d'arrêt. Liste des expressions possibles : 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Nom de connexion invalide : '%s'. Les noms doivent commencer par une lettre et ne contenir que des lettres, des chifrres et '.'. err.bkpt.badval Erreur de syntaxe dans la valeur '%s'. Ce doit être une constante décimale ou Vérilog. err.bkpt.toomany Trop de points d'arrêt. Le maximum est %d. err.sim.badtmp Impossible de sauver dans le fichier temporaire '%s' (disque plein ?) err.sim.syntx Erreur de syntaxe dans la commande '%s'. err.sim.noincl Fichier include '%s' non trouvé. err.sim.clockbadedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt Point d'arrêt '%s' inconnu. err.sim.nonet Connexion '%s' inconnue. err.sim.nogate Élément '%s' inconnu. err.sim.badbin Caractère illégal dans la constante binaire '%s'. err.sim.notswitch L'élément '%s' n'est ni un interrupteur, ni un registre. err.sim.badcmd Commande '%s' non reconnue dans script de simulation. err.noteditpchg Les propriétés peuvent seulement être changées en mode d'édition. err.badeditop Opération illégale en mode d'édition. err.badopen Impossible d'ouvrir le fichier '%s'. err.badlibopen Impossible d'ouvrir la bibliothèque '%s'. err.nomark Poser une marque avec le bouton gauche de la souris avant de choisir un type d'élément, SVP. err.badgate Type d'élément inconnu. err.badmake Impossible de créer un élément. err.manypages -begin- Le document que vous voulez imprimer contient de très nombreuses pages. Êtes vous sur de vouloir l'imprimer ? -end- err.nojump -begin- La fonctionnalité de saut vers un module ne peut pas être utilisée en mode de simulation ou en mode d'analyse de chemin critique. Il est possible de naviguer manuellement vers le bloc cible en sélectionnant un module et en l'ouvrant avec la touche '>'. Pour fermer un module, utiliser la touche '<'. -end- err.nomod Le module '%s' n'est pas défini. err.modlock Ce bloc logique est vérouillé ! err.closeroot Impossible de fermer le module principal. Quitter tkgate. err.sim.isrun Le simulateur est déjà lancé (Taper 'Ctrl-s e' pour le tuer). err.sim.isnotrun Le simulateur ne tourne pas (Taper 'Ctrl-s b' pour le démarrer). err.editonly Commande invalide en mode de simulation. err.simonly Commande valide seulement en mode de simulation. err.nodel Pas de sélection supprimable. err.modnotdef Le module '%s' n'est pas défini. err.moddef Le bloc '%s' existe déjà. err.noprop L'élément sélectionné n'a pas de propriétés éditables. err.openscript Impossible d'ouvrir le script de simulation '%s' err.oldversion Chargement d'un fichier avec un numéro de version (%s) obsolète (la version actuelle est %s). err.futureversion Chargement d'un fichier avec un numéro de version (%s) futur (la version courante est %s). err.badversion Numéro de version inconnu. À vos risques et périls. err.nodrive Le réseau %s n'a pas de driver dans le module %s. err.noconn Le fil %s{%d} n'est pas connecté -> supprimé. err.noback -begin- Ce fichier a été créé avec tkgate %s, et peut ne pas être lisible par une version antérieure à la version actuelle (%s), si vous le sauvez. -end- ############################################################################## # Informational messages # msg.selwire Sélection de la connexion : '%s'. msg.selgate Sélection : %s nommé '%s'. msg.selblock Sélection du bloc %s nommé '%s'. msg.modoverwt Le module destination '%s' existe déjà. L'écraser ? msg.foundgate Élément '%s' trouvé. msg.foundwire Connexion '%s' trouvée. msg.searchagn Chaîne '%s' non trouvée. Cliquer sur 'chercher' pour chercher de nouveau. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface L'interface du module '%s' a été appliquée. msg.needsel Choisir une instance de module SVP. msg.wroteckpt Sauvegarde automatique dans %s... msg.save Circuit sauvé dans '%s'. msg.badsave Impossible de créer le fichier '%s'. msg.reallynew Le circuit a été modifié. Voulez-vous vraiment le supprimer et créer un nouveau circuit ? msg.reallyquit Le circuit a été modifié. Voulez-vous vraiment quitter ? msg.notlib Le module '%s' ne fait pas partie d'une bibliothèque. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help - Infobulles # ho.new -begin- Effacer le circuit courant et créer un nouveau circuit. -end- ho.open Lire un circuit dans fichier. ho.save Sauver le circuit dans le fichier courant. ho.print Imprimer le circuit courant. ho.move -begin- -> Déplacer/Connecter En cliquant et en faisant glisser : Choisir la position d'un nouvel élément Déplacer les éléments et les connexions Relier des connexions En double-cliquant : Éditer les propriétés d'un élément, d'une connexion ou d'un port Éditer le texte d'un commentaire -end- ho.delgat -begin- -> Supprimer élément Utiliser cet outil pour supprimer des éléments. -end- ho.cutw -begin- -> Couper connexion Utiliser cet outil pour couper des connexions. -end- ho.inv -begin- -> Poser inverseurs Utiliser cet outil pour ajouter ou enlever des inverseurs en entrée ou en sortie des portes ou des modules. -end- ho.bitw -begin- -> Largeur de connexion Utiliser cet outil pour changer le nombre de bits d'un bus. Entrer le nombre de bits souhaité dans la petite boîte en bas à droite de la fenêtre principale. -end- ho.modopen Ouvrir le module sélectionné. ho.modclose Fermer le module courant. ho.simgo -begin- Si la simulation n'est pas active, démarrer une simulation et exécuter les scripts d'initialisation. Si la simulation est active, faire avancer la simulation automatiquement. -end- ho.simpause -begin- Mettre en pause une simulation avançant automatiquement. -end- ho.simstep -begin- Avancer d'un nombre fixe de quanta de temps. Pour régler ce nombre, aller dans le menu Fichier->Options, choisir l'onglet des options de la simulation et régler l'avance rapide par quanta. -end- ho.simclock -begin- Avancer d'un nombre fixe de cycles d'horloge. Pour régler ce nombre, aller dans le menu Fichier->Options, choisir l'onglet des options de la simulation et régler l'avance rapide par cycles d'horloge. -end- ho.simstop -begin- Terminer la simulation en cours et revenir au mode d'édition. -end- ho.simbreak -begin- Éditer les points d'arrêts. La simulation sera stoppée si l'une des conditions des points d'arrêt devient vraie. -end- ho.simexec Exécuter un script de simulation. ho.simload -begin- Charger la mémoire avec le contenu d'un fichier ".mem". -end- ho.simdump -begin- Sauver le contenu d'une mémoire dans un fichier ".mem". -end- ho.sim.break -begin- Définir un point d'arrêt du simulateur. Un point d'arrêt est une expression qui si elle devient vraie, stoppe la simulation. Seules des expressions avec un seul opérateur relationnel sont supportées, par exemple "w1==0" ou "w7!=8". Des expressions comme "w8" ou "!w2" peuvent aussi être utilisée sur un signal booléen. -end- ho.f.modlist -begin- Les de tous les modules chargés. - Le module principal est indiqué par un + ajouté à son nom, - Les modules de bibliothèques sont indiqués entre parenthèses. -end- ho.netlist -begin- Liste des connexions dans le module courant. - Les connexions marquées avec un @ ont leur nom caché. - Les connexions à plusieurs bits (bus) sont accompagnées d'un intervalle. -end- ho.ports -begin- Liste des ports du module courant. - un > indique une sortie - un < indique une entrée - un = indique une entrée/sortie -end- ho.status.logo -begin- Affichage de l'état de la simulation. - Si un portail d'entrée est affiché, tkgate est en mode d'édition. - Si le quadrupède est affiché, tkgate est en mode de simulation. - Si le quadrupède est immobile, la simulation est en pause. - Si le quadrupède marche, la simulation avance automatiquement. -end- ho.status.msg Les messages de tkgate sont affichés ici. ho.status.block Le nom du module en cours d'édition. ho.status.file -begin- Le fichier en cours d'édition. Une * indique que le circuit a été modifié depuis la dernière sauvegarde. -end- ho.print.selall Imprimer tous les modules chargés actuellement dans TKGate. ho.print.selcur Imprimer uniquement le module dans la fenêtre d'édition de TKGate. ho.print.seluse -begin- Imprimer tous les modules "utilisés". Les modules "utilisés" sont ceux qui sont des descendants du module principal. -end- ho.print.selsel -begin- Imprimer uniquement les modules sélectionnés ci-dessous. Utiliser la touche "CTRL" pour sélectionner des modules. -end- ho.print.modlist Sélectionner les modules à imprimer. ho.circuit.discchg -begin- TkGate n'affichera pas d'avertissement si vous annulez les éditions sans sauver. -end- ho.cmd.bitw -begin- Les connexions sélectionnées avec le curseur auront pour largeur ce nombre de bits. -end- ho.edgat.signam -begin- Le nom du signal sélectionné sur l'élément sélectionné. Vous pouvez changer le nom du signal en le modifiant ici. -end- ho.edgat.port -begin- Le nom du port pour ce signal sur l'élément. Ce champ peut uniquement être édité pour des instances de modules. -end- ho.edgat.iolab -begin- La direction du signal sélectionné sur l'élément sélectionné. Ce champ peut uniquement être édité pour des instances de modules. -end- ho.edgat.bitlab -begin- Le nombre de bits du signal sélectionné sur l'élément sélectionné. Vous pouvez changer le nombre de bits en le modifiant ici. -end- ho.edgat.cycle Le nombre total de quanta de temps dans un cycle d'horloge. ho.edgat.phase Le point de départ du cycle (en pourcentage). ho.edgat.duty Le pourcentage du cycle pendant lequel le signal d'horloge est bas. ho.edgat.cname Nom de la connexion. ho.edgat.cport Port auquel la connexion est attachée. ho.edgat.ctype Type de connexion. ho.edgat.cbitw Nombre de bits de la connexion. ho.edgat.cedit Éditer le port sélectionné. ho.edgat.cadd Ajouter un port. ho.edgat.cdel Supprimer le port sélectionné. ho.edgat.hide -begin- Désactive l'affichage du nom de l'élément. -end- ho.edgat.gtype Type de l'élément. ho.edgat.gname Nom de cette instance d'élément. ho.edgat.ganchor Activer pour ancrer un élément. ho.edgat.gx Coordonnée X de l'élément. ho.edgat.gy Coordonnée Y de l'élément. ho.edgat.swstate -begin- L'état initial de l'interrupteur à utiliser au début d'une simulation. -end- ho.edgat.dipstate -begin- L'état initial d'un interrupteur DIP à utiliser au début d'une simulation. -end- ho.edgat.range L'intervalle des bits à extraire d'un bus. ho.edgat.memfile -begin- Le fichier contenant l'état initial de cette mémoire. Ce fichier est lu quand le simulateur démarre. -end- ho.edgat.func La fonction de ce module. ho.edgat.frame L'étiquette du cadre. ho.opt.site -begin- Le nom du site sur lequel tkgate est installé. Ce nom sera utilisé sur toutes les impressions. -end- ho.opt.smooth -begin- Quand cette option est activée, le défilement est optimisé pour utiliser des copies de morceaux d'écran au lieu de redessiner. Vous pouvez la désactiver en cas de problème avec votre serveur X11. -end- ho.opt.clip -begin- Si cette option est activée, du clipping est utilisé pour mettre à jour uniquement les zones découvertes de la fenêtre lors d'un réaffichage. Sinon, la fenêtre entière est redessinée. -end- ho.opt.outmove -begin- Si cette option est activée, seul le cadre d'un module en cours de déplacement sera affiché. Utiliser cette option sur des machines avec un affichage peu rapide. -end- ho.opt.bhelp -begin- Utiliser cette option pour activer les infobulles. Les infobulles, comme celle-ci, fournissent une aide sur les éléments de l'interface graphique de tkgate quand on positionne le curseur sur eux. -end- ho.opt.novice -begin- Si aucun circuit n'est spécifié sur la ligne de commande, un didacticiel de TkGate sera chargé comme circuit initial au démarrage de TkGate. -end- ho.opt.debug -begin- Activer quelques options de mise au point. C'est utile uniquement pour les développeurs de TkGate. -end- ho.opt.ckpt Activer la sauvegarde automatique des circuits non sauvés. ho.opt.ckptfreq Fréquence des sauvegardes automatiques (en secondes). ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .tkgate-properties file. -end- ho.opt.miles -begin- If this mode is enable, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enable, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- Le nombre de quanta de temps duquel avancer en mode d'avance rapide par quanta. -end- ho.opt.ckstep -begin- Le nombre de cycles d'horloge duquel avancer en mode d'avance rapide par cycles d'horloge. -end- ho.opt.ckover -begin- Le nombre de quanta de temps au delà du front montant de l'horloge, duquel avancer en mode pas à pas. -end- ho.opt.init -begin- Fichier de script de simulation à exécuter automatiquement au démarrage de la simulation. -end- ho.opt.ckall -begin- Si ce mode est activé, le mode avance rapide par cycles d'horloge mettra la simulation en pause à chaque front montant de chaque horloge. -end- ho.opt.ckspec -begin- Si ce mode est activé, le mode avance rapide par cycles d'horloge mettra la simulation en pause à chaque front montant, uniquement pour l'horloge spécifiée. -end- ho.deftech -begin- Technologie par défaut de tous les éléments nouvellement créés. La technologie affecte les délais des portes. Pour changer la technologie d'une porte en particulier, double-cliquer dessus pour ouvrir sa fenêtre de propriétés et cliquer sur l'onglet "Délai". -end- ho.techbut -begin- Utiliser les délais de la technologie standard. Pour ajouter une technologie personnalisée, utiliser le menu "Fichier -> Options -> Simulation". -end- ho.custbut -begin- Régler les délais pour cette porte. -end- ho.simwatch -begin- Affichage des commandes échangées entre le simulateur et l'interface graphique. -end- ho.simlog -begin- Écrire les commandes envoyées au simulateur dans un fichier journal. Le journal peut ensuite être utilisé en entrée du simulateur à des fins de mise au point. -end- ho.cpathanal -begin- Calculer les chemins critiques du circuit. -end- tkgate-2.0-b10/locale/fr/messages.bak000644 001751 001751 00000070153 11134010127 020136 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed Apr 6 23:43:13 2005 # # Traduction effectuée par Laurent.Bonnaud@iut2.upmf-grenoble.fr # \language French ############################################################################## # # basic strings # b.dismiss Annuler b.close Fermer b.ok OK b.clear Effacer b.cancel Annuler b.open Ouvrir... b.bitw Largeur de bus b.in entrée b.out sortie b.inout E/S b.browse Parcourir... b.label Étiquette b.find Chercher b.edit Éditer... b.add Ajouter... b.delete Supprimer b.deleteb Supprimer... b.apply Appliquer b.anchor Ancre b.tech Technologie ############################################################################## # Menu strings # menu.file Fichier menu.edit Éditer menu.tool Outils menu.simulate Simuler menu.module Module menu.format Élément menu.make Ajouter menu.circ Circuit menu.file.new Nouveau circuit menu.file.open Ouvrir... menu.file.openlib Ouvrir bibliothèque... menu.file.save Sauver menu.file.saveas Sauver... menu.file.print Imprimer... menu.file.options Options... menu.file.quit Quitter menu.file.cprop Propriétés du circuit... menu.edit.cut Couper menu.edit.copy Copier menu.edit.paste Coller menu.edit.selall Tout sélectionner menu.edit.find Chercher... menu.edit.algnv Aligner Vert. menu.edit.algnh Aligner Horz. menu.edit.zoomin Zoom + menu.edit.zoomout Zoom - menu.tool.move Déplacer/Connecter menu.tool.delg Supprimer élément menu.tool.cutw Couper connexion menu.tool.inv Poser inverseurs menu.tool.bitw Largeur de connexion menu.tool.debug Debug menu.format.rot.0 Rot. 0 menu.format.rot.90 Rot. 90 menu.format.rot.180 Rot. 180 menu.format.rot.270 Rot. 270 menu.simulate.begin Commencer simulation menu.simulate.end Terminer simulation menu.simulate.run Lancer menu.simulate.pause Pause menu.simulate.step Avancer d'un quantum menu.simulate.cycle Avancer d'un cycle menu.simulate.break Point d'arrêt... menu.simulate.script Exécuter Script... menu.simulate.load Charger mémoire... menu.simulate.dump Sauver mémoire... menu.module.open Ouvrir menu.module.close Fermer menu.module.new Nouveau... menu.module.del Supprimer... menu.module.copy Copier... menu.module.rename Renommer... menu.module.claim Claim... menu.interface.set Appliquer interface menu.interface.edit Éditer interfaces... menu.circ.path Chemin critique... menu.gate.addin Ajouter entrée menu.gate.addout Ajouter sortie menu.gate.addinout Ajouter E/S menu.gate.iochg Changer type menu.format.anchor Ancrer la sélection menu.format.unanchor Dé-ancrer la sélection menu.format.prop Propriétés... menu.tool.rep Répliquer menu.format.del Supprimer menu.format.settech Choisir technologie # Scope Menu menu.scope.prtrace Imprimer chronogramme... menu.scope.close Fermer menu.scope.trace Chronogramme menu.scope.zoomin Zoom + menu.scope.zoomout Zoom - gm.switch E/S gm.gate Porte gm.rgate Réduction gm.msi MSI gm.alu UAL gm.mem Mémoire gm.mod Module gm.comment Commentaire gm.frame Cadre gm.io.switch Interrupteur gm.io.dip Interrupteurs gm.io.ground Terre gm.io.vdd Vdd gm.io.merge Fusionner connexions gm.io.clock Horloge gm.io.led Diode gm.io.ledbar Barre de diodes gm.io.ledhex chiffre (hexa) gm.io.leddec chiffre (décimal) gm.io.ledseg chiffre (direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Additionneur gm.alu.mult Multiplicateur gm.alu.div Diviseur gm.alu.lshift Décalage à gauche gm.alu.rshift Décalage à droite gm.alu.arshift Décalage à droite arithmétique gm.alu.roll Permutation circulaire gm.mem.reg Registre gm.mem.ff Bascule D gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexeur gm.msi.41mux 4-1 Multiplexeur gm.msi.81mux 8-1 Multiplexeur gm.msi.12dec 1-2 Décodeur gm.msi.14dec 1-4 Décodeur gm.msi.18dec 1-8 Décodeur gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut addwireseg Ajouter une dérivation help Aide hlpabout À propos... hlplicense License... hlpdoc Documentation... hlptut Didacticiel hlpexample Exemples exampcomb Logique combinatoire examp3bit Compteur 3 bits examp8bit Compteur 8 bits examptrff FF niveau transistor exampcpu Processeur "Ménagerie" tutwelcome Introduction à TkGate tutcreate Création d'un circuit tutedit1 Édition d'un circuit (1) tutedit2 Édition d'un circuit (2) tutmods Utilisation des modules tutsim Simulation d'un circuit ############################################################################## # Interface strings # ifile Fichier imodule Module iblmodule Modules : iports Ports : ibits Bits : ############################################################################# # Net Dialog Box # db.net.name Nom de la connexion db.net.hide Cacher le nom db.net.bits Largeur de bus db.net.port Type de port db.net.in entrée db.net.out sortie db.net.inout E/S db.net.inets Connexion ############################################################################## # Gate dialog box # db.gate.signam Nom du signal db.gate.portnam Nom du port db.gate.iotype Type db.gate.bitw Nombre de bits db.gate.cyclew Largeur de cycle db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.gtype Type d'élément db.gate.gname Nom de l'élément db.gate.hidenam Cacher le nom db.gate.anchor Ancré db.gate.cpbreak Partition du chemin critique db.gate.butstate État de l'interrupteur db.gate.dipval Valeur de l'interrupteur db.gate.memfilenam Fichier de la mémoire db.gate.modname Fonction db.gate.islink Hypertexte db.gate.link Lier au fichier db.gate.findw Chercher des connexions uniquement db.gate.findg Chercher des éléments uniquement db.gate.findwg Chercher des connexions et des éléments db.gate.general Général db.gate.details Détails db.gate.ports Port db.gate.delay Délai db.gate.stddelay Délai standard db.gate.custdelay Délai personnalisé db.led.type Type de diode db.led.bit Bit db.led.bar Bar Graph db.led.hex chiffre (hexa) db.led.dec chiffre (décimal) db.led.seg chiffre (Direct) cpath.cloops -begin- Une boucle a été détectée dans votre circuit. Afin de pouvoir effectuer une analyse des délais sur ce circuit, vous devez soit 1. faire disparaître cette boucle 2. marquer certaines portes de la boucle comme un point de "Partition du chemin critique". Les connexions formant une boucle sont listées ci-dessous. -end- ############################################################################## # Print dialog box # print.outto Imprimer vers print.printer Imprimante print.file Fichier print.prcmd Commande d'impression print.filename Nom de fichier print.epssave Sauver en Postscript encapsulé print.doctit Titre du document print.prmod Impression des modules : print.epcm Quanta/cm print.estpg Nombre de pages estimé print.all Tous print.cur Courant print.use Utilisé print.sel Sélectionné print.inclib Inclure les modules des bibliothèques print.papsz Format de papier print.orient Orientation print.portrait Portrait print.landscape Paysage print.2side Imprimer en double face (recto-verso) print.opts Options print.scale Réduction des gros modules pour tenir sur une page print.partition Impression des gros modules sur plusieurs pages print.incidx Inclure l'index print.incgraph Inclure le graphe de hiérarchie print.4up Impression des petits modules 4 par page print.range Sélection d'intervalle print.fulltr Trace complète print.parttr Trace partielle print.start Démarrer print.end Fin ############################################################################## # # Options dialog # opt.site Nom du site opt.inst Instances opt.mods Modules opt.modports Ports d'un module opt.frames Cadres opt.comment Commentaires opt.hlink Hyperliens opt.wire Connexions 1 bit opt.bus Connexions n bits opt.tools Outils pour porte opt.cpath Chemin critique opt.grid Scope Grid opt.logic1 1 logique opt.logic0 0 logique opt.float Flottant opt.unknown Inconnu/Conflit opt.offled Diode éteinte opt.onled Diode allumée opt.zled Floating LED opt.restdef Restaurer valeurs par défaut opt.regudate Réaffichage minimal opt.smoothscroll Défilement fluide opt.outmove Déplacement d'un fantôme opt.balloon Activer les infobulles opt.debug Activer la mise au point opt.novice Mode débutant opt.ckpoint Sauvegarde automatique opt.freq intervalle opt.beak Activer les modes spéciaux opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.showsimcmd Afficher les commandes du simulateur opt.logfile Fichier journal du simulateur opt.estepsz Avance rapide par quanta (nombre de quanta) opt.cstepsz Avance rapide par cycles d'horloges (nombre de cycles) opt.overstep Arrêt débordant sur cycle d'horloge (nombre de quanta) opt.initscript Script d'initialisation opt.posedge Le mode pas à pas sur les cycles d'horloge s'arrête sur tous les fronts montants opt.setclock Le mode pas à pas sur les cycles d'horloge s'arrête sur l'horloge opt.delayfilepath Fichiers contenant les délais opt.general Général opt.print Impression opt.simulate Simulation opt.analysis Analyse opt.color Couleurs opt.cpopts Options pour chemin critique : opt.maxpath Nombre maximal de chemins : opt.cpflash Affichage avec chemin clignotant opt.vercheck -begin- Vérifier automatiquement la sortie d'une nouvelle version de tkgate sur Internet. Ne pas activer à moins d'avoir une connexion permanente à Internet. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Nouveau module blklst.delmod Supprimer module blklst.frommod Copier module depuis blklst.tomod Vers blklst.oldname Ancien nom blklst.newname Nouveau nom blklst.claim Claim Module ############################################################################## # # Circuit Dialog box # circ.topmod Module principal circ.discchg annuler changements circ.iniscript Scripts d'initialisation circ.noscript Pas de fichier script sélectionné. circ.really1 Voulez-vous vraiment supprimer circ.really2 de la liste des scripts d'initialisation ? ############################################################################## # Simulator # sim.breakpt Point d'arrêt ############################################################################## # # Command box # cmd.file Nom du fichier cmd.topname Nom du module principal ############################################################################## # # Critical path messages # cp.delay Délai sur chemin : cp.pathl Chemin : cp.numpath Nombre de chemins : cp.recompute Recalculer ############################################################################## # Error messages - Messages d'erreur # err.verilog Erreurs dans le fichier : err.nopin Impossible de changer la patte sélectionnée. err.badhex Valeur hexadécimale illégale ('%s') ignorée. err.gatanchor Les éléments sont ancrés et ne peuvent pas être déplacés. err.libmode Opération illégale sur un module de bibliothèque (convertir le module en module normal pour pouvoir l'éditer). err.badfind Impossible de trouver la cible '%s'. err.badopendel Impossible de supprimer un module ouvert. err.nosrcmod Module source '%s' non trouvé. err.noerr Impossible de trouver l'erreur. err.misserr Information sur l'erreur incomplète (plantage du simulateur ?) err.pounimpl Erreur non implémentée dans ParseOption err.badinadd Impossible d'ajouter plus d'entrées à l'élément sélectionné. err.badoutadd Impossible d'ajouter plus de sorties à l'élément sélectionné. err.badinoutadd Impossible d'ajouter plus de pattes d'E/S à l'élément sélectionné. err.badpinchg Impossible de changer le type de patte pour l'élément sélectionné. err.badnetname Caractères illégaux supprimés dans l'identificateur. err.netbcrename Identificateur renommé en '%s' à cause de caractères illégaux. err.netconfnet Identificateur renommé en '%s' à cause d'un conflit de noms. err.netconfgat Identificateur renommé pour éviter un conflit avec un nom d'élément. err.netconfkw Identificateur renommé pour éviter un conflit avec mot réservé. err.badconsame Connexion refusée car les fils font partie du même bus. err.badconptsp Connexion refusée car les deux fils sont des ports de modules ou des ??. err.badconbitw Connexion refusée car les largeurs des bus sont différentes. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Impossible d'exécuter la commande d'impression '%s'. err.badpsopen Impossible d'ouvrir le fichier '%s' pour une sortie PostScript. err.bkpt.badexp Erreur de syntaxe dans l'expression du point d'arrêt. Liste des expressions possibles : 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Nom de connexion invalide : '%s'. Les noms doivent commencer par une lettre et ne contenir que des lettres, des chifrres et '.'. err.bkpt.badval Erreur de syntaxe dans la valeur '%s'. Ce doit être une constante décimale ou Vérilog. err.bkpt.toomany Trop de points d'arrêt. Le maximum est %d. err.sim.badtmp Impossible de sauver dans le fichier temporaire '%s' (disque plein ?) err.sim.syntx Erreur de syntaxe dans la commande '%s'. err.sim.noincl Fichier include '%s' non trouvé. err.sim.clockbadedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt Point d'arrêt '%s' inconnu. err.sim.nonet Connexion '%s' inconnue. err.sim.nogate Élément '%s' inconnu. err.sim.badbin Caractère illégal dans la constante binaire '%s'. err.sim.notswitch L'élément '%s' n'est ni un interrupteur, ni un registre. err.sim.badcmd Commande '%s' non reconnue dans script de simulation. err.noteditpchg Les propriétés peuvent seulement être changées en mode d'édition. err.badeditop Opération illégale en mode d'édition. err.badopen Impossible d'ouvrir le fichier '%s'. err.badlibopen Impossible d'ouvrir la bibliothèque '%s'. err.nomark Poser une marque avec le bouton gauche de la souris avant de choisir un type d'élément, SVP. err.badgate Type d'élément inconnu. err.badmake Impossible de créer un élément. err.manypages -begin- Le document que vous voulez imprimer contient de très nombreuses pages. Êtes vous sur de vouloir l'imprimer ? -end- err.nojump -begin- La fonctionnalité de saut vers un module ne peut pas être utilisée en mode de simulation ou en mode d'analyse de chemin critique. Il est possible de naviguer manuellement vers le bloc cible en sélectionnant un module et en l'ouvrant avec la touche '>'. Pour fermer un module, utiliser la touche '<'. -end- err.nomod Le module '%s' n'est pas défini. err.modlock Ce bloc logique est vérouillé ! err.closeroot Impossible de fermer le module principal. Quitter tkgate. err.sim.isrun Le simulateur est déjà lancé (Taper 'Ctrl-s e' pour le tuer). err.sim.isnotrun Le simulateur ne tourne pas (Taper 'Ctrl-s b' pour le démarrer). err.editonly Commande invalide en mode de simulation. err.simonly Commande valide seulement en mode de simulation. err.nodel Pas de sélection supprimable. err.modnotdef Le module '%s' n'est pas défini. err.moddef Le bloc '%s' existe déjà. err.noprop L'élément sélectionné n'a pas de propriétés éditables. err.openscript Impossible d'ouvrir le script de simulation '%s' err.oldversion Chargement d'un fichier avec un numéro de version (%s) obsolète (la version actuelle est %s). err.futureversion Chargement d'un fichier avec un numéro de version (%s) futur (la version courante est %s). err.badversion Numéro de version inconnu. À vos risques et périls. err.nodrive Le réseau %s n'a pas de driver dans le module %s. err.noconn Le fil %s{%d} n'est pas connecté -> supprimé. err.noback -begin- Ce fichier a été créé avec tkgate %s, et peut ne pas être lisible par une version antérieure à la version actuelle (%s), si vous le sauvez. -end- ############################################################################## # Informational messages # msg.selwire Sélection de la connexion : '%s'. msg.selgate Sélection : %s nommé '%s'. msg.selblock Sélection du bloc %s nommé '%s'. msg.modoverwt Le module destination '%s' existe déjà. L'écraser ? msg.foundgate Élément '%s' trouvé. msg.foundwire Connexion '%s' trouvée. msg.searchagn Chaîne '%s' non trouvée. Cliquer sur 'chercher' pour chercher de nouveau. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface L'interface du module '%s' a été appliquée. msg.needsel Choisir une instance de module SVP. msg.wroteckpt Sauvegarde automatique dans %s... msg.save Circuit sauvé dans '%s'. msg.badsave Impossible de créer le fichier '%s'. msg.reallynew Le circuit a été modifié. Voulez-vous vraiment le supprimer et créer un nouveau circuit ? msg.reallyquit Le circuit a été modifié. Voulez-vous vraiment quitter ? msg.notlib Le module '%s' ne fait pas partie d'une bibliothèque. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help - Infobulles # ho.new -begin- Effacer le circuit courant et créer un nouveau circuit. -end- ho.open Lire un circuit dans fichier. ho.save Sauver le circuit dans le fichier courant. ho.print Imprimer le circuit courant. ho.move -begin- -> Déplacer/Connecter En cliquant et en faisant glisser : Choisir la position d'un nouvel élément Déplacer les éléments et les connexions Relier des connexions En double-cliquant : Éditer les propriétés d'un élément, d'une connexion ou d'un port Éditer le texte d'un commentaire -end- ho.delgat -begin- -> Supprimer élément Utiliser cet outil pour supprimer des éléments. -end- ho.cutw -begin- -> Couper connexion Utiliser cet outil pour couper des connexions. -end- ho.inv -begin- -> Poser inverseurs Utiliser cet outil pour ajouter ou enlever des inverseurs en entrée ou en sortie des portes ou des modules. -end- ho.bitw -begin- -> Largeur de connexion Utiliser cet outil pour changer le nombre de bits d'un bus. Entrer le nombre de bits souhaité dans la petite boîte en bas à droite de la fenêtre principale. -end- ho.modopen Ouvrir le module sélectionné. ho.modclose Fermer le module courant. ho.simgo -begin- Si la simulation n'est pas active, démarrer une simulation et exécuter les scripts d'initialisation. Si la simulation est active, faire avancer la simulation automatiquement. -end- ho.simpause -begin- Mettre en pause une simulation avançant automatiquement. -end- ho.simstep -begin- Avancer d'un nombre fixe de quanta de temps. Pour régler ce nombre, aller dans le menu Fichier->Options, choisir l'onglet des options de la simulation et régler l'avance rapide par quanta. -end- ho.simclock -begin- Avancer d'un nombre fixe de cycles d'horloge. Pour régler ce nombre, aller dans le menu Fichier->Options, choisir l'onglet des options de la simulation et régler l'avance rapide par cycles d'horloge. -end- ho.simstop -begin- Terminer la simulation en cours et revenir au mode d'édition. -end- ho.simbreak -begin- Éditer les points d'arrêts. La simulation sera stoppée si l'une des conditions des points d'arrêt devient vraie. -end- ho.simexec Exécuter un script de simulation. ho.simload -begin- Charger la mémoire avec le contenu d'un fichier ".mem". -end- ho.simdump -begin- Sauver le contenu d'une mémoire dans un fichier ".mem". -end- ho.sim.break -begin- Définir un point d'arrêt du simulateur. Un point d'arrêt est une expression qui si elle devient vraie, stoppe la simulation. Seules des expressions avec un seul opérateur relationnel sont supportées, par exemple "w1==0" ou "w7!=8". Des expressions comme "w8" ou "!w2" peuvent aussi être utilisée sur un signal booléen. -end- ho.f.modlist -begin- Les de tous les modules chargés. - Le module principal est indiqué par un + ajouté à son nom, - Les modules de bibliothèques sont indiqués entre parenthèses. -end- ho.netlist -begin- Liste des connexions dans le module courant. - Les connexions marquées avec un @ ont leur nom caché. - Les connexions à plusieurs bits (bus) sont accompagnées d'un intervalle. -end- ho.ports -begin- Liste des ports du module courant. - un > indique une sortie - un < indique une entrée - un = indique une entrée/sortie -end- ho.status.logo -begin- Affichage de l'état de la simulation. - Si un portail d'entrée est affiché, tkgate est en mode d'édition. - Si le quadrupède est affiché, tkgate est en mode de simulation. - Si le quadrupède est immobile, la simulation est en pause. - Si le quadrupède marche, la simulation avance automatiquement. -end- ho.status.msg Les messages de tkgate sont affichés ici. ho.status.block Le nom du module en cours d'édition. ho.status.file -begin- Le fichier en cours d'édition. Une * indique que le circuit a été modifié depuis la dernière sauvegarde. -end- ho.print.selall Imprimer tous les modules chargés actuellement dans TKGate. ho.print.selcur Imprimer uniquement le module dans la fenêtre d'édition de TKGate. ho.print.seluse -begin- Imprimer tous les modules "utilisés". Les modules "utilisés" sont ceux qui sont des descendants du module principal. -end- ho.print.selsel -begin- Imprimer uniquement les modules sélectionnés ci-dessous. Utiliser la touche "CTRL" pour sélectionner des modules. -end- ho.print.modlist Sélectionner les modules à imprimer. ho.circuit.discchg -begin- TkGate n'affichera pas d'avertissement si vous annulez les éditions sans sauver. -end- ho.cmd.bitw -begin- Les connexions sélectionnées avec le curseur auront pour largeur ce nombre de bits. -end- ho.edgat.signam -begin- Le nom du signal sélectionné sur l'élément sélectionné. Vous pouvez changer le nom du signal en le modifiant ici. -end- ho.edgat.port -begin- Le nom du port pour ce signal sur l'élément. Ce champ peut uniquement être édité pour des instances de modules. -end- ho.edgat.iolab -begin- La direction du signal sélectionné sur l'élément sélectionné. Ce champ peut uniquement être édité pour des instances de modules. -end- ho.edgat.bitlab -begin- Le nombre de bits du signal sélectionné sur l'élément sélectionné. Vous pouvez changer le nombre de bits en le modifiant ici. -end- ho.edgat.cycle Le nombre total de quanta de temps dans un cycle d'horloge. ho.edgat.phase Le point de départ du cycle (en pourcentage). ho.edgat.duty Le pourcentage du cycle pendant lequel le signal d'horloge est bas. ho.edgat.cname Nom de la connexion. ho.edgat.cport Port auquel la connexion est attachée. ho.edgat.ctype Type de connexion. ho.edgat.cbitw Nombre de bits de la connexion. ho.edgat.cedit Éditer le port sélectionné. ho.edgat.cadd Ajouter un port. ho.edgat.cdel Supprimer le port sélectionné. ho.edgat.hide -begin- Désactive l'affichage du nom de l'élément. -end- ho.edgat.gtype Type de l'élément. ho.edgat.gname Nom de cette instance d'élément. ho.edgat.ganchor Activer pour ancrer un élément. ho.edgat.gx Coordonnée X de l'élément. ho.edgat.gy Coordonnée Y de l'élément. ho.edgat.swstate -begin- L'état initial de l'interrupteur à utiliser au début d'une simulation. -end- ho.edgat.dipstate -begin- L'état initial d'un interrupteur DIP à utiliser au début d'une simulation. -end- ho.edgat.range L'intervalle des bits à extraire d'un bus. ho.edgat.memfile -begin- Le fichier contenant l'état initial de cette mémoire. Ce fichier est lu quand le simulateur démarre. -end- ho.edgat.func La fonction de ce module. ho.edgat.frame L'étiquette du cadre. ho.opt.site -begin- Le nom du site sur lequel tkgate est installé. Ce nom sera utilisé sur toutes les impressions. -end- ho.opt.smooth -begin- Quand cette option est activée, le défilement est optimisé pour utiliser des copies de morceaux d'écran au lieu de redessiner. Vous pouvez la désactiver en cas de problème avec votre serveur X11. -end- ho.opt.clip -begin- Si cette option est activée, du clipping est utilisé pour mettre à jour uniquement les zones découvertes de la fenêtre lors d'un réaffichage. Sinon, la fenêtre entière est redessinée. -end- ho.opt.outmove -begin- Si cette option est activée, seul le cadre d'un module en cours de déplacement sera affiché. Utiliser cette option sur des machines avec un affichage peu rapide. -end- ho.opt.bhelp -begin- Utiliser cette option pour activer les infobulles. Les infobulles, comme celle-ci, fournissent une aide sur les éléments de l'interface graphique de tkgate quand on positionne le curseur sur eux. -end- ho.opt.novice -begin- Si aucun circuit n'est spécifié sur la ligne de commande, un didacticiel de TkGate sera chargé comme circuit initial au démarrage de TkGate. -end- ho.opt.debug -begin- Activer quelques options de mise au point. C'est utile uniquement pour les développeurs de TkGate. -end- ho.opt.ckpt Activer la sauvegarde automatique des circuits non sauvés. ho.opt.ckptfreq Fréquence des sauvegardes automatiques (en secondes). ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .tkgate-properties file. -end- ho.opt.miles -begin- If this mode is enable, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enable, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- Le nombre de quanta de temps duquel avancer en mode d'avance rapide par quanta. -end- ho.opt.ckstep -begin- Le nombre de cycles d'horloge duquel avancer en mode d'avance rapide par cycles d'horloge. -end- ho.opt.ckover -begin- Le nombre de quanta de temps au delà du front montant de l'horloge, duquel avancer en mode pas à pas. -end- ho.opt.init -begin- Fichier de script de simulation à exécuter automatiquement au démarrage de la simulation. -end- ho.opt.ckall -begin- Si ce mode est activé, le mode avance rapide par cycles d'horloge mettra la simulation en pause à chaque front montant de chaque horloge. -end- ho.opt.ckspec -begin- Si ce mode est activé, le mode avance rapide par cycles d'horloge mettra la simulation en pause à chaque front montant, uniquement pour l'horloge spécifiée. -end- ho.deftech -begin- Technologie par défaut de tous les éléments nouvellement créés. La technologie affecte les délais des portes. Pour changer la technologie d'une porte en particulier, double-cliquer dessus pour ouvrir sa fenêtre de propriétés et cliquer sur l'onglet "Délai". -end- ho.techbut -begin- Utiliser les délais de la technologie standard. Pour ajouter une technologie personnalisée, utiliser le menu "Fichier -> Options -> Simulation". -end- ho.custbut -begin- Régler les délais pour cette porte. -end- ho.simwatch -begin- Affichage des commandes échangées entre le simulateur et l'interface graphique. -end- ho.simlog -begin- Écrire les commandes envoyées au simulateur dans un fichier journal. Le journal peut ensuite être utilisé en entrée du simulateur à des fins de mise au point. -end- ho.cpathanal -begin- Calculer les chemins critiques du circuit. -end- tkgate-2.0-b10/locale/es/messages000644 001751 001751 00000257005 11134010406 017405 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Jan 5 00:36:58 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## \language Spanish ############################################################################## # # basic strings # b.new Nuevo... b.dismiss Volver b.close Cerrar b.ok OK b.clear Borrar b.cancel Cancelar #b.open Open... #b.bitw Bit Width b.in entrada b.out salida b.inout bidireccional b.browse Visualizar... b.label Etiqueta b.find Buscar b.edit Editar... b.add Aadir... b.delete Borrar #b.deleteb Delete... b.remove TODO: Remove b.apply Aplicar b.anchor Anclar b.tech Tecnolog-Aía$)B #b.enable Enable #b.disable Disable #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editar tab.editintr TODO: Interface tab.simulate Simular tab.cpath TODO: Critical Path # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add TODO: Add... mm.delete TODO: Delete mm.edit TODO: Edit... mm.enable TODO: Enable mm.disable TODO: Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file Fichero menu.edit TODO: Edit menu.tool Herramientas menu.symbol TODO: 0:Symbol menu.simulate TODO: Simulate menu.module Mdulo menu.interface TODO: Interface menu.format Puerta menu.make Insertar menu.help Ayuda menu.file.new Nuevo menu.file.open TODO: Open... menu.file.openlib Abrir Libreria... menu.file.save Salvar menu.file.saveas TODO: Save As... menu.file.print Imprimir... menu.tool.options Opciones... menu.file.quit Salir menu.file.cprop TODO: 0:Circuit Properties... menu.file.import TODO: 0:Import Image... menu.file.export TODO: 0:Export Image... menu.edit.undo TODO: Undo menu.edit.redo TODO: Redo menu.edit.cut Cortar menu.edit.copy Copiar menu.edit.paste Pegar menu.edit.overlay TODO: 0:Overlay Paste menu.edit.selall Seleccionar Todo menu.edit.find Buscar... menu.format.algnv Situar en Columna menu.format.algnh Situar en Fila menu.format.rot.rotate TODO: Rotate menu.edit.zoomin Zoom Acercar menu.edit.zoomout Zoom Alejar menu.edit.rshift TODO: 10:Bit Shift Right menu.edit.lshift TODO: 10:Bit Shift Left menu.edit.ushift TODO: 10:Bit Shift Up menu.edit.dshift TODO: 10:Bit Shift Down menu.edit.cwrotate TODO: 11:Bit Rotate C-W menu.edit.ccwrotate TODO: 15:Bit Rotate C-C-W menu.edit.pcwrotate TODO: 12:Port Rotate C-C-W menu.edit.pccwrotate TODO: 16:Port Rotate C-C-W menu.edit.autobold TODO: Boldify Bits menu.edit.resize TODO: Resize Bitmap menu.tool.move Mover/Conectar menu.tool.delg Borrar puerta menu.tool.cutw Cortar cable menu.tool.inv Invertir menu.tool.bitw TODO: Bit Width menu.tool.debug Depurar menu.tool.point TODO: 0:Point menu.tool.line TODO: 0:Line menu.tool.rect TODO: 0:Rectangle menu.tool.fillrect TODO: 0:Fill Rectangle menu.tool.port TODO: 0:Port menu.tool.select TODO: 0:Select Region menu.format.rot.0 Orientacin 0-Aº$)B menu.format.rot.90 Orientacin 90-Aº$)B menu.format.rot.180 Orientacin 180-Aº$)B menu.format.rot.270 Orientacin 270-Aº$)B menu.tool.tclshell TODO: 0:Tcl Shell menu.simulate.begin Empezar Simulacin menu.simulate.end Terminar Simulacin menu.simulate.addprobe TODO: Add/Delete Probe menu.simulate.run Modo continuo menu.simulate.pause Pausa menu.simulate.step Paso a paso (tiempo) menu.simulate.cycle Paso a paso (n-Aº ciclos)$)B menu.simulate.break Punto de ruptura... menu.simulate.script Ejecutar Guin... menu.simulate.load Fichero -> Memoria... menu.simulate.dump Memoria -> Fichero... menu.module.open Abrir menu.module.close TODO: Close menu.module.new TODO: New... menu.module.del TODO: Delete... menu.module.copy Copia... menu.module.rename Renombra... menu.module.claim Mdulo libreria -> Mdulo usuario... menu.module.setroot TODO: Set As Root... menu.module.prop Propiedades... menu.module.interface TODO: 0:Interface menu.module.interface.set TODO: 0:Set As Default menu.module.interface.update TODO: 1:Sync. to Default menu.module.interface.updateall TODO: 6:Sync. All to Default... menu.module.interface.edit TODO: 0:Edit... menu.module.interface.auto TODO: 5:Auto Generate... menu.format.addport TODO: 4:Add Port menu.format.ioset TODO: Set Type menu.format.anchor Anclar Seleccin menu.format.unanchor Liberar Seleccin menu.format.prop TODO: Gate Properties... menu.tool.rep R-Aéplica$)B menu.format.del TODO: Delete menu.format.settech Seleccionar Tecnolog-Aía$)B menu.help.about Acerca de... menu.help.license Licencia... menu.help.doc Documentacin... menu.help.tut Tutoriales menu.help.home TODO: 1:Home Page menu.help.example Ejemplos ############################################################################# # Scope Menu # menu.scope_file TODO: 0:File menu.scope_sim TODO: 0:Simulate menu.scope_trace TODO: 0:Trace menu.scope_help TODO: 0:Help menu.scope_file.ptrace TODO: 0:Print Trace... menu.scope_file.close TODO: 0:Close menu.scope_trace.zoomin TODO: 5:Zoom In menu.scope_trace.zoomout TODO: 5:Zoom Out menu.scope_sim.addprobe TODO: 0:Add/Delete Probe menu.scope_sim.run TODO: 0:Run menu.scope_sim.pause TODO: 0:Pause menu.scope_sim.step TODO: 0:Step Epoch(s) menu.scope_sim.cycle TODO: 5:Step Cycle menu.scope_sim.break TODO: 0:Breakpoint... menu.scope_sim.script TODO: 1:Exec. Script... menu.scope_sim.load TODO: 1:Load Memory... menu.scope_sim.dump TODO: 1:Dump Memory... menu.scope_help.about TODO: 0:About... menu.scope_help.license TODO: 0:License... menu.scope_help.doc TODO: 0:Documentation... mod.intf TODO: Interface port.parms TODO: Port Parameters port.in TODO: In port.out TODO: Out port.inout TODO: InOut ############################################################################## # # Tags for built-in gate types # gm.io Entrada/Salida gm.gate TODO: Gate gm.rgate Reduccin gm.msi MSI gm.alu ALU gm.mem Memoria gm.mod TODO: Module gm.comment Comentario gm.frame Marco gm.io.switch Conmutador gm.io.dip Interruptores DIP gm.io.ground Masa gm.io.vdd Vdd gm.io.merge TODO: Concat gm.io.clock Seal de Reloj gm.io.led LED gm.io.ledbar Barra de LEDs gm.io.ledhex 7-Seg. LED (HEXADECIMAL) gm.io.leddec 7-Seg. LED (DECIMAL) gm.io.ledseg 7-Seg. LED (Directo) gm.io.tty TTY (Terminal) gm.gate.and AND (Y) gm.gate.nand NAND (NO-Y) gm.gate.or OR (O) gm.gate.nor NOR (NO-O) gm.gate.xor XOR (O-EX) gm.gate.xnor XNOR (NO-O-EX) gm.gate.buf Buffer gm.gate.inv Inversor gm.gate.tribuf Buffer-Triestado gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and TODO: AND gm.rgate.nand TODO: NAND gm.rgate.or TODO: OR gm.rgate.nor TODO: NOR gm.rgate.xor TODO: XOR gm.rgate.xnor TODO: XNOR gm.alu.add Sumador gm.alu.mult Multiplicador gm.alu.div Divisor gm.alu.lshift DespL. Izquierda gm.alu.rshift DespL. Derecha gm.alu.arshift DespL. Arit. Derecha gm.alu.roll DespL. c-Aíclico$)B gm.mem.reg Registro gm.mem.ff Flip-Flop D gm.mem.rff TODO: Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decodificador gm.msi.14dec 1-4 Decodificador gm.msi.18dec 1-8 Decodificador gm.mod.inst Inserta mdulo gm.mod.in Entrada Mdulo gm.mod.out Salida Mdulo gm.mod.inout Bidireccional Mdulo tutorial.prev TODO: PREVIOUS tutorial.next TODO: NEXT tutorial.chapter TODO: CHAPTER LIST tutorial.reload TODO: RELOAD ############################################################################## # # Popup menus # pop.make TODO: Make pop.tool TODO: Tool pop.edit.paste TODO: Paste pop.edit.cut TODO: Cut pop.edit.copy TODO: Copy pop.port.in TODO: In pop.port.out TODO: Out pop.port.inout TODO: InOut pop.wire.addseg Aadir segmento de cable pop.wire.prop TODO: Properties... pop.wire.hidesize TODO: Hide Bit Width pop.wire.showsize TODO: Show Bit Width pop.wire.hidelabel TODO: Hide Label pop.wire.hidealllabel TODO: Hide All Labels pop.wire.clearalllabel TODO: Clear All Labels pop.wire.showlabel TODO: Show Label pop.gate.open TODO: Open pop.gate.close TODO: Close pop.gate.prop TODO: Properties... pop.gate.addport TODO: Add Port pop.gate.addin TODO: Add Input pop.gate.addout TODO: Add Output pop.gate.addinout TODO: Add BiDir pop.gate.anchor TODO: Anchor pop.gate.settech TODO: Set Technology pop.gate.delete TODO: Delete pop.gate.ioset TODO: Set Type pop.module.new TODO: New... pop.module.del TODO: Delete... pop.module.copy TODO: Copy... pop.module.rename TODO: Rename... pop.module.claim TODO: Claim... pop.module.setroot TODO: Set As Root... pop.module.prop TODO: Properties... pop.module.int TODO: Edit Interface... pop.simulate.end TODO: End Simulation pop.simulate.begin TODO: Begin Simulation pop.simulate.addprobe TODO: Add/Delete Probe pop.simulate.delprobe TODO: Delete Probe pop.simulate.run TODO: Run pop.simulate.pause TODO: Pause pop.simulate.step TODO: Step Epoch(s) pop.simulate.cycle TODO: Step Cycle pop.simulate.break TODO: Breakpoint... pop.simulate.script TODO: Exec. Script... pop.simulate.load TODO: Load Memory... pop.simulate.dump TODO: Dump Memory... pop.interface TODO: Interface pop.interface.set TODO: Set as Default pop.interface.update TODO: Sync. to Default pop.interface.updateall TODO: Sync. All to Default... pop.interface.edit TODO: Edit Interface... pop.interface.auto TODO: Auto Generate... pop.interface.replace TODO: Replace pop.igen.type TODO: Type pop.igen.side TODO: Side pop.igen.size TODO: Size pop.igen.delete TODO: Delete pop.igen.in TODO: in pop.igen.out TODO: out pop.igen.inout TODO: inout pop.igen.left TODO: left pop.igen.right TODO: right pop.igen.top TODO: top pop.igen.bottom TODO: bottom pop.igen.other TODO: other ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit Edit #symed.edit.cut Cut #symed.edit.copy Copy #symed.edit.paste Paste #symed.edit.overlay Overlay Paste #symed.edit.rclock Rotate Clockwise #symed.edit.rcclock Rotate Counter-Clockwise #symed.module Module #symed.modes Modes #symed.cutpaste Cut/Paste #symed.rotate Port Rotation #symed.zoom Zoom #symed.cancel Cancel #symed.update Update symed.tab.normal TODO: UnSelected symed.tab.select TODO: Selected symed.link TODO: Link selected to unselected # width of symbol editor tabs @symed.tab.width 125 ############################################################################## scope.emptymsg TODO: Double-click on a wire to add or delete a trace. comment.empty TODO: [Double click to add text.] ############################################################################## # Interface strings # ifile Fichero imodule Mdulo iblmodule Mdulos: iports Puertos: ibits Bits: itype TODO: Type: ############################################################################# # Module Dialog Box # db.mod.name TODO: Name db.mod.file TODO: File Name db.mod.type TODO: Type db.mod.flags TODO: Flags db.mod.dataprot TODO: Disallow editing of module definition. db.mod.intfprot TODO: Disallow all interface changes. db.mod.edprot TODO: Disallow edit mode interface changes. db.mod.props TODO: Properties db.mod.inuse.0 TODO: Module is not in use. db.mod.inuse.1 TODO: Module is in use. db.mod.lmod.0 TODO: Module has not been modified since loading. db.mod.lmod.1 TODO: Module has been modified since loading. db.mod.smod.0 TODO: Module has not been modified since saving. db.mod.smod.1 TODO: Module has been modified since saving. db.mod.islib.1 TODO: Module is part of [%s] library. db.mod.islib.0 TODO: Module is not a library module. db.mod.netlist TODO: Netlist db.mod.hdl TODO: HDL db.mod.netexpl -begin- TODO: Modules of this type are described as a network of connected components. A graphical editor is used to edit the definition. -end- db.mod.hdlexpl -begin- TODO: Modules of this type are described in text format. A text editor is used to create the module definition. -end- ############################################################################# # Error List Dialog box # db.err.caption TODO: Error List db.err.explain -fillbegin- TODO: I am unable to enter simulation mode due to errors in your circuit. Select an error message to see the error location. -end- db.err.neededit -fillbegin- TODO: You must first switch to Edit mode before navigating to warnings. -end- ############################################################################# # Net Dialog Box # db.net.name Nombre Conexin db.net.hide Nombre Oculto db.net.bits Anchura Bus db.net.type TODO: Net Type db.net.port Tipo de Patilla db.net.in entrada db.net.out salida db.net.inout bidireccional db.net.inets Conexiones ############################################################################## # # New circuit dialog box # db.newcirc.directory TODO: Directory: db.newcirc.cap TODO: New Circuit db.newcirc.exp -fillbegin- TODO: Discard the current circuit and start editing a new circuit. -end- db.newcirc.file TODO: File Name db.newcirc.topname Nombre del mdulo principal ############################################################################## # Gate dialog box # @db.gate.tabwidth *80 @db.gate.width *600 @db.gate.height *400 @db.gate.comment.width *900 @db.gate.comment.height *500 db.gate.signam Nombre de la Seal db.gate.portnam Nombre de la Patilla db.gate.iotype Tipo db.gate.bitw Anchura Bus db.gate.cyclew Anchura Ciclo db.gate.phase Fase db.gate.duty Funcin db.gate.port Patilla db.gate.bitws Bits db.gate.side TODO: Side db.gate.gtype Tipo de Puerta db.gate.gname Nombre de la Puerta db.gate.hidenam Nombre Oculto db.gate.anchor Anclada db.gate.cpbreak Ruptura del camino cr-Aítico$)B db.gate.butstate Estado del Botn db.gate.dipval Valor del conmutador db.gate.range TODO: Bit Range db.gate.memfilenam Fichero de Memoria db.gate.modname Funcin db.gate.general General db.gate.details Detalles db.gate.text TODO: Text db.gate.ports Patilla db.gate.delay Retraso db.gate.parameters TODO: Parameters db.gate.stddelay Retraso Normal db.gate.custdelay Retraso Personalizado db.gate.catdiruse TODO: Port Placement db.gate.edit TODO: Edit db.gate.delete TODO: Delete db.gate.add TODO: Add db.gate.ff.type TODO: Flip-Flop Orientation db.gate.ff.normal.hdr TODO: Normal db.gate.ff.normal.exp -fillbegin- TODO: Flip-Flop with data flowing left to right. -end- db.gate.ff.reverse.hdr TODO: Reversed db.gate.ff.reverse.exp -fillbegin- TODO: Flip-Flop with data flowing right to left. -end- db.gate.cat.asc.hdr TODO: Ascending db.gate.cat.dec.hdr TODO: Decending db.gate.cat.asc.exp -fillbegin- TODO: Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- TODO: Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir TODO: Signal Direction db.gate.cat.auto.hdr TODO: Auto db.gate.cat.multin.hdr TODO: Multi-Input db.gate.cat.singin.hdr TODO: Single-Input db.gate.cat.tran.hdr TODO: Bidirectional db.gate.cat.auto.exp -fillbegin- TODO: Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- TODO: Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- TODO: Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- TODO: Allow bidirectional (tran) signal flow. Can not be connected to switches or registers. -end- db.gate.tab.General.cap TODO: General Properties db.gate.tab.Ports.cap TODO: Port Properties db.gate.tab.Delay.cap TODO: Delay Properties db.gate.tab.Parameters.cap TODO: Module Parameters db.gate.tab.CLOCK.cap TODO: Clock Properties db.gate.tab.SWITCH.cap TODO: Switch Properties db.gate.tab.DIP.cap TODO: DIP Properties db.gate.tab.TAP.cap TODO: Tran Properties db.gate.tab.RAM.cap TODO: RAM Properties db.gate.tab.ROM.cap TODO: ROM Properties db.gate.tab.MODULE.cap TODO: Module Properties db.gate.tab.FRAME.cap TODO: Frame Properties db.gate.tab.LED.cap TODO: LED Properties db.gate.tab.AND.cap TODO: AND Properties db.gate.tab.OR.cap TODO: OR Properties db.gate.tab.XOR.cap TODO: XOR Properties db.gate.tab.MUX.cap TODO: Mux Properties db.gate.tab.DEMUX.cap TODO: Demux Properties db.gate.tab.CONCAT.cap TODO: Concat Properties db.gate.tab.COMMENT.cap TODO: Text Properties db.gate.tab.FF.cap TODO: Flip-Flop Properties db.gate.tab.General.exp -fillbegin- TODO: View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- TODO: Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- TODO: Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- TODO: Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- TODO: Set detailed type specific properties of a gate here. -end- db.gate.tab.CLOCK.exp TODO: `db.gate.tab.details.exp db.gate.tab.SWITCH.exp TODO: `db.gate.tab.details.exp db.gate.tab.DIP.exp TODO: `db.gate.tab.details.exp db.gate.tab.TAP.exp TODO: `db.gate.tab.details.exp db.gate.tab.RAM.exp TODO: `db.gate.tab.details.exp db.gate.tab.ROM.exp TODO: `db.gate.tab.details.exp db.gate.tab.MODULE.exp TODO: `db.gate.tab.details.exp db.gate.tab.FRAME.exp TODO: `db.gate.tab.details.exp db.gate.tab.LED.exp TODO: `db.gate.tab.details.exp db.gate.tab.AND.exp TODO: `db.gate.tab.details.exp db.gate.tab.OR.exp TODO: `db.gate.tab.details.exp db.gate.tab.XOR.exp TODO: `db.gate.tab.details.exp db.gate.tab.MUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.DEMUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.CONCAT.exp TODO: `db.gate.tab.details.exp db.gate.tab.FF.exp TODO: `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- TODO: Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter TODO: Parameter db.gate.mparm.value TODO: Value db.gate.mparm.exampleA -begin- TODO: This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameter can be customized for each instance through this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- TODO: module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder TODO: Input Ordering db.gate.mux.ord1.hdr TODO: Left-to-Right db.gate.mux.ord2.hdr TODO: Right-to-Left db.gate.mux.ord1.exp -fillbegin- TODO: Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- TODO: Order MUX inputs from right to left. -end- db.gate.demux.dataorder TODO: Output Ordering db.gate.demux.ord1.hdr TODO: Left-to-Right db.gate.demux.ord2.hdr TODO: Right-to-Left db.gate.demux.ord1.exp -fillbegin- TODO: Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- TODO: Order DEMUX outputs from right to left. -end- db.gate.mux.select TODO: Selector Style db.gate.mux.sel1.hdr TODO: Selector on Left db.gate.mux.sel2.hdr TODO: Selector on Right db.gate.mux.sel1.exp -fillbegin- TODO: Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- TODO: Place the data selector on the right side of the gate. -end- db.gate.demux.select TODO: `db.gate.mux.select db.gate.demux.sel1.hdr TODO: `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr TODO: `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp TODO: `db.gate.mux.sel1.exp db.gate.demux.sel2.exp TODO: `db.gate.mux.sel2.exp db.gate.aox.extbaruse TODO: Extender Bar Use db.gate.aox.use.hdr TODO: Extender Bars db.gate.aox.nouse.hdr TODO: No Extender Bars db.gate.aox.use.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type Tipo de LED db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Barra Grafica db.gate.led.hex.hdr 7-Segment (HEXADECIMAL) db.gate.led.dec.hdr 7-Segment (DECIMAL) db.gate.led.seg.hdr 7-Segment (Directo) db.gate.led.bit.exp -fillbegin- TODO: Single-lamp led display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- TODO: LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- TODO: Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- TODO: Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- TODO: Signal bits directly control led segments. -end- db.seq.back TODO: db.hdl.savecap TODO: Multiple Modules db.hdl.saveexp -fillbegin- TODO: The text buffer for the module you have just edited appears to contain more than one module definition. Please select one of the three actions described to the right. -end- db.hdl.autoedit TODO: Auto Edit db.hdl.split TODO: Split db.hdl.comment TODO: Comment db.hdl.cancel TODO: Cancel db.hdl.ignore TODO: Ignore db.hdl.autoeditcap TODO: Name Mismatch db.hdl.autoeditexp -fillbegin- TODO: The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- Se ha detectado un bucle de realimentacin en su circuito. Para poder realizar un an-Aálisis de los retrasos en dicho circuito deberemos, o bién romper el bucle, o marcar alguna de las puertas en el bucle como punto de un "Camino crítico". Las conexiones detectadas como bucle se listan más abajo.$)B -end- ############################################################################## # Print dialog box # #print.outto Output to print.printer Impresora print.file Fichero print.prcmd Comando de Impresin print.prname TODO: Printer print.advanced TODO: Advanced... print.filename Nombre del Fichero print.epssave Salvar como Postscript Encapsulado. #print.doctit Document Title #print.prmod Print Modules print.epcm Periodo de tiempo/cm print.estpg P-Aáginas estimadas$)B print.all Todo print.cur Actual print.use Usados print.sel Seleccionados print.inclib Incluye mdulos de libreria. print.incunused TODO: Include unused modules. print.papsz Tamao del Papel print.orient Orientacin print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opciones print.scale Escalar mdulos hasta completar p-Aágina.$)B print.partition Dividir mdulos grandes en varias p-Aáginas.$)B print.incidx Incluye indice. print.incgraph Incluye gr-Aáfico de jerarquia.$)B print.4up Imprimir cuatro mdulos pequeos por p-Aágina.$)B print.rangeselection TODO: Range Selection print.scaleselect TODO: Scale Selection print.fulltr Trazado completo print.parttr Trazado parcial print.start Empezar print.range Rango print.linelen TODO: Line Length print.filesel TODO: Output to file print.printersel TODO: Output to printer print.defaultprinter TODO: Default Printer print.pageset TODO: Page Setup print.modulesel TODO: Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok TODO: Print print.printtrace.cap TODO: Print Trace print.printcirc.cap TODO: Print Schematic print.printcirc.out.exp -fillbegin- TODO: Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- TODO: Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- TODO: Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- TODO: Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output TODO: Output #print.tab.page Page print.tab.modules TODO: Modules print.tab.content TODO: Content print.tab.advanced TODO: Advanced # # Circuit print dialog box # @print.dlgbox.width *450 @print.dlgbox.height *450 @print.dlgbox.tabwidth *95 # # Scope print dialog box # @print.scopedlg.width *475 @print.scopedlg.height *400 @print.scopedlg.tabwidth *95 ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 700 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 95 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *170 # @opt.tree.width *135 opt.general General opt.interface TODO: Interface opt.toolbars TODO: Toolbars opt.toolbars.edit TODO: Editor opt.toolbars.sim TODO: Simulation opt.toolbars.symed TODO: Symbol Editor opt.editor TODO: Editor opt.print Imprimir opt.print.output TODO: Output opt.print.content TODO: Content opt.simulate Simular opt.simulate.basic TODO: Basic opt.simulate.tech TODO: Technology opt.simulate.error TODO: Error Handling opt.library TODO: Libraries opt.library.path TODO: Path opt.library.load TODO: Auto Loading opt.library.vpd TODO: VPD opt.analysis An-Aálisis$)B opt.color Color opt.color.edit TODO: Editor opt.color.scope TODO: Scope opt.color.hdl TODO: HDL Editor opt.html TODO: HTML opt.debug Habilitar Depuracin opt.lib.load.available TODO: Available Libraries opt.lib.load.selected TODO: Selected Libraries opt.identity TODO: Identity opt.site Nombre de la Empresa opt.username TODO: User Name opt.libname TODO: Library Name: opt.inst Instancias opt.mods Mdulos opt.modports Patillas de Mdulos opt.frames Marcos opt.comment Comentarios opt.hlink Hiperenlaces opt.wire Cables simples (1 Bit) opt.bus Buses opt.tools Herramientas de Puerta opt.background TODO: Background opt.cpath Caminos cr-Aíticos$)B opt.grid Visualizar Rejilla opt.logic1 Lgica '1' opt.logic0 Lgica '0' opt.float Flotante opt.unknown Conflicto Desconocido opt.offled LED apagado opt.onled LED encendido opt.zled LED flotante opt.restdef Restaura opciones por defecto opt.regudate Actualizar Regin opt.smoothscroll Desplazamiento Suave opt.balloon Habilitar Globos de Ayuda opt.safeSave TODO: Do safe file saving opt.saveCells TODO: Include cells in save files opt.showimage TODO: Show side-bar images in dialog boxes opt.novice Modo Novato opt.blockDropConnect TODO: Wire drop port creation opt.ckpoint.1 TODO: Do Checkpointing every opt.ckpoint.2 TODO: commands. opt.freq Frecuencia opt.beak Habilitar Modo Especial opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver TODO: Automatic Integrity Checking opt.showsimcmd Visualizar Cadena Simulada opt.estepsz Ajuste Tiempo (Simulacin paso a paso) opt.cstepsz Ajuste n-Aº ciclos (Simulacin paso a paso)$)B opt.overstep Exceder Reloj opt.sorttraces TODO: Sort traces alphabetically on scope opt.vpopupdelay TODO: Pop-Up Delay #opt.initscript Global Initialization Script opt.posedge El reloj para despu-Aés de todos los flancos$)B opt.setclock El reloj para en punto opt.delayfilepath Ficheros de Retraso opt.devfilepath TODO: VPD (Virtual Peripheral Device) File Path opt.vlibpath TODO: Verilog Library Path opt.vlibnames TODO: Base Libraries opt.display TODO: Display opt.interaction TODO: Interaction opt.input TODO: Input opt.security TODO: Security opt.undolen TODO: Max Undo opt.keybind TODO: Key Binding Style opt.useless TODO: Enable Useless Features opt.features TODO: Basic Features opt.simbase TODO: Basic Simulator Options opt.simclock TODO: Clock Options opt.cpopts Opciones de los caminos cr-Aíticos:$)B opt.maxpath M-Aáximo nº de caminos:$)B opt.cpflash Presentar como relampago opt.general.fontset TODO: Font Set opt.simulator.savetraces TODO: Save probe locations between simlation runs. opt.simulator.noglitch TODO: Enable simulator glitch suppression. opt.simulator.err TODO: Error Handling opt.simulator.stopany TODO: Cancel simulation on any warnings. opt.simulator.showall TODO: Always display warnings. opt.simulator.showiferr TODO: Display warnings only if with errors. opt.simulator.ignore TODO: Ignore all warnings. opt.tool.file TODO: File opt.tool.edit TODO: Edit opt.tool.gateopt TODO: Gate Operations opt.tool.gateprop TODO: Gate opt.tool.undo TODO: Undo/Redo opt.tool.zoom TODO: Zoom opt.tool.mode Modo opt.tool.module TODO: Module opt.tool.tech TODO: Technology opt.tool.simctl TODO: Simulator Control opt.tool.simaux TODO: Simulator Commands opt.tool.simmode TODO: Simulator Tools opt.tool.symmode TODO: Symbol Edit Mode opt.tool.symedit TODO: Symbol Edit Cut/Paste opt.tool.symport TODO: Symbol Edit Ports opt.tool.symshift TODO: Symbol Edit Bit Shift opt.tool.symopr TODO: Symbol Edit Bit Ops opt.editor.features TODO: Basic Editor Features opt.editor.format TODO: Enable automatic formatting opt.editor.colorize TODO: Enable code colorization opt.editor.comments TODO: Comments opt.editor.strings TODO: Strings opt.editor.reserved TODO: Reserved Words opt.editor.gateword TODO: Built-in Gates opt.editor.instword TODO: Module Instances opt.editor.taskword TODO: System Tasks opt.editor.color TODO: Color opt.editor.bold TODO: Bold opt.editor.italic TODO: Italic opt.editor.indentlevel TODO: Indentation per level: opt.editor.beginindent TODO: Make begin...end flush with enclosing level. opt.editor.movesel TODO: Enable drag-and-drop of selection. opt.editor.returntab TODO: Auto indent after return. opt.vercheck -begin- Chequea de forma peridica si existen nuevas versiones del programa TKGATE en Internet. No habilitarla si no se dispone de una conexin permanente a la RED. -end- opt.general.cap TODO: General Options opt.editor.cap TODO: HDL Text Editor opt.interface.cap TODO: Interface Options opt.toolbars.cap TODO: Toolbar Options opt.print.cap TODO: Print Options opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap TODO: Simulator Options opt.security.cap TODO: Security Options opt.color.cap TODO: Color Options opt.html.cap TODO: HTML/HTTP Options opt.debug.cap TODO: Debug Options opt.library.cap TODO: Library Options opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.debug.opt TODO: Debugging Options opt.color.editwin TODO: Edit Window Colors opt.color.scopewin TODO: Scope Window Colors opt.vlibadd.cap TODO: Add Library opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- TODO: Set personal identification and basic TkGate options on this page. The personal identification will be used on printed output. -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore TODO: Restore Page Defaults opt.bbar.restoreall TODO: Restore All Defaults ############################################################################## # # Interface generator # igen.port TODO: Port igen.type TODO: Type igen.side TODO: Side igen.size TODO: Size igen.bits TODO: Bits igen.modname TODO: Module Name: #igen.resort Re-sort igen.add TODO: Add igen.delete TODO: Delete igen.edit TODO: Edit igen.in TODO: in igen.out TODO: out igen.inout TODO: inout igen.left TODO: left igen.right TODO: right igen.top TODO: top igen.bottom TODO: bottom #igen.other other igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error TODO: Script Errors module.props TODO: Module Properties ipanel.plist TODO: Port List ipanel.props TODO: Interface Properties #ipanel.itype.change Change Type... #ipanel.itype.edsymbol Edit Symbol... ipanel.block TODO: Block ipanel.symbol TODO: Symbol ipanel.autogen TODO: Auto Generate ipanel.updateall TODO: Synchronize All... ipanel.itype.select TODO: Interface Type #ipanel.block.description Standard Interface #ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label TODO: Block resize port handling: ipanel.ppos.fix TODO: Fixed positions ipanel.ppos.scale TODO: Scaled positions #ipanel.ppos.grid Grid ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim Mdulo libreria -> Mdulo ususario blklst.to a blklst.from TODO: From blklst.name TODO: Name blklst.new.cap TODO: Create New Module blklst.del.cap Borra Mdulo blklst.copy.cap TODO: Copy Module blklst.rename.cap TODO: Rename Module blklst.claim.cap TODO: Claim Module blklst.setroot.cap TODO: Set Root Module blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label TODO: Find Objects find.exp -fillbegin- TODO: Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase TODO: Ignore Case find.result.module TODO: Module find.result.type TODO: Type find.result.name TODO: Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options TODO: Search Options find.results TODO: Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains TODO: Contains... find.qual.begins TODO: Begins with... find.qual.ends TODO: Ends with... find.qual.matches TODO: Matches... find.dom.label TODO: Look for objects in: find.dom.gates TODO: Gates find.dom.nets TODO: Nets find.dom.text TODO: Comment Text find.search TODO: Find: find.target TODO: Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label TODO: Circuit Properties circ.ident TODO: Identification circ.filev TODO: File Version circ.file TODO: File Name circ.title TODO: Circuit Title circ.discchg Descartar cambios circ.extbar TODO: Use extender bars. circ.autostart TODO: Enable auto-start of simulation. circ.iniscript Guiones de Inicializacin #circ.noscript No script files selected. #circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: circ.reallyupdate -fillbegin- TODO: Do you really want to update the interface of all '%s' instances? -end- @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general TODO: General circ.library TODO: Libraries circ.script TODO: Script circ.simulator TODO: Simulation circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp.general -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- circ.exp.library -fillbegin- TODO: Select libraries required by this circuit. Library requirements are saved with the circuit and will be automatically loaded the next time you load this circuit. -end- circ.exp.simulator -fillbegin- TODO: View and modifiy simulation preferences for this circuit. -end- ############################################################################## # # Library Manager # libmgr.cap TODO: Library Manager libmgr.library TODO: Library libmgr.description TODO: Description libmgr.status TODO: Status libmgr.status.load TODO: Loaded libmgr.status.unload TODO: Not Loaded libmgr.status.loadp TODO: [Loaded] libmgr.status.unloadp TODO: [Not Loaded] libmgr.exp -fillbegin- TODO: Select libraries to be loaded or unloaded. -end- libmgr.load TODO: Load libmgr.unload TODO: Unload libmgr.unloadall TODO: Unload All libmgr.notedit -fillbegin- TODO: Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab TODO: Breakpoints break.id TODO: ID break.state TODO: S break.condition TODO: Condition break.value TODO: Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay Retraso del camino: cp.pathl Lista de caminos: cp.numpath Nmero de caminos: cp.recompute Recmputo ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin No puedo cambiar la patilla seleccionada. err.badhex Valor hexadecimal incorrecto. Ignoro '%s'. err.gatanchor Puertas Ancladas no pueden moverse. err.protdata TODO: Can not modify contents of protected or library module. err.badfind No puedo encontrar '%s' como destino. err.badopendel No puedo borrar el mdulo abierto. err.nosrcmod No puedo encontrar '%s' como mdulo fuente. err.noerr No puedo indicarle el error. err.misserr Error informacin incompleta (did the simulator crash?) err.badinadd No puedo aadir m-Aás entradas a la puerta seleccionada.$)B err.badoutadd No puedo aadir m-Aás salidas a la puerta seleccionada.$)B err.badinoutadd No puedo aadir m-Aás lineas bidireccionales a la puerta$)B err.badpinchg No puedo cambiar el tipo de patillas de la puerta. err.badnetname He borrado caracteres incorrectos en el identificador. err.netbcrename Identificador cambia a '%s' por caracteres incorrectos. err.netconfnet Identificador cambia a '%s' debido a un conflicto. err.netconfgat Identificador cambia debido a conflicto con nombre de puerta b-Aásica.$)B err.netconfkw Identificador cambia debido a conflicto con palabra reservada. err.badconsame Unin rechazada debido a que los cables forman parte de la misma conexin. err.badconptsp Unin rechazada debido a que ambos cables son patillas de mdulos o alimentacin. err.badconbitw Unin rechazada por no poderse emparejar la anchura de los dos buses. err.badrange No se permite visualizar el rango no positivo de la seal. err.badlprcmd No puedo ejecutar el comando '%s' de impresin. err.badpsopen No puedo abrir el fichero '%s' para salida postscript. err.badid TODO: Illegal identifier '%s'. err.noinvgate TODO: Inverters are not allowed on gates of this type. err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp Error de sintaxis en expresin para punto de ruptura. Debe ser una de las siguientes: 'conexin', '!conexin', 'conexin == valor', 'conexin != valor' err.bkpt.badnet '%s' es un nombre incorrecto de conexin. Los nombres v-Aálidos deben empezar por una letra y contener slo letras, nmeros y el signo '.'.$)B err.bkpt.badval Error de sintaxis en el valor '%s'. Debe ser decimal o una constante en el estilo Verilog. err.bkpt.toomany Demasiados puntos de ruptura. El m-Aáximo es de %d.$)B err.sim.badtmp No puedo salvar el fichero temporal '%s' para la simulacin ( -A¿ Disco lleno ? )$)B err.sim.syntx Error de sintaxis en el comando '%s'. err.sim.noincl El fichero Include '%s' no se encuentra. err.sim.badedge Ilegal indicador en el pulso '%c' del comando de reloj. err.sim.nobkpt No existe punto de ruptura '%s'. err.sim.nonet No puedo encontrar la conexin '%s'. err.sim.nogate No puedo encontrar la puerta '%s'. err.sim.badbin '%s' es un car-Aácter incorrecto en constante binaria.$)B err.sim.notswitch La puerta '%s' no es un conmutador, dip o registro. err.sim.badcmd No reconozco el comando '%s' en el guin de simulacin. err.sim.isrun El simulador est ejecutandose en estos momentos (Utiliza 'Ctrl-s e' para terminar). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg Las propiedades slo pueden cambiarse en modo Edicin. err.badeditop Operacin ilegal en el modo de Edicin. err.badopen No se puede abrir el fichero '%s'. err.badlibopen No puedo abrir la libreria '%s'. err.nomark Por favor marca con el botn izquierdo antes de seleccionar el tipo de puerta. err.badgate No conozco ese tipo de puerta. err.badportadd TODO: Can't add ports to gates of this type. err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- Hay un montn de p-Aáginas en este documento. ¿ Estás seguro de querer imprimirlo ?.$)B -end- err.nojump -fillbegin- La posibilidad de 'saltar al mdulo' no se puede utilizar en el modo de simulacin o en el an-Aálisis de un camino crítico. Por favor navega de forma manual hasta el bloque de destino seleccionando los mdulos adecuados y utilizando la opcin '>' del teclado. Se acceder al mdulo de nivel superior en la jerarquia actuando sobre la tecla '<'.$)B -end- err.nomod Mdulo '%s' no est definido. err.modlock !Este bloque lgico lo est visualizando! err.closeroot No puedo cerrar el mdulo principal. Utiliza la opcin Salir del men Fichero. err.editonly Comando incorrecto en el modo de Simulacin. err.simonly Comando slo v-Aálido en modo Simulacin.$)B err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel No se puede borrar lo seleccionado. err.modnotdef Mdulo '%s' no definido. err.moddef El bloque '%s' ya existe. err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop No se pueden editar las propiedades de la puerta seleccionada. err.openscript No puedo abrir el fichero de guin de simulacin '%s' err.oldversion Cargado fichero de la versin %s, obsoleta (la m-Aás reciente es la versin %s).$)B err.futureversion Fichero salvado en la versin %s, futura versin del programa tkgate (la versin actual es %s). err.badversion Se desconoce el nmero de versin. Usada bajo su responsabilidad. err.nodrive Conexin %s no posee entrada en el mdulo %s. err.noconn Cable %s{%d} no posee conexiones - lo borramos. err.oldportact TODO: Please right click on port or module edge to add/change port. err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail TODO: Unable to create backup file '%s'. err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TODO: TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TODO: TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- TODO: A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- TODO: A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- El fichero %s, se crear por el programa tkgate, y no puede leerse por versiones anteriores a la actual (%s), si decide salvarlo. -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Seleccionado cable denominado '%s'. msg.selgate Seleccionado %s denominado '%s'. msg.selblock Seleccionado bloque %s denominado '%s'. msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt Mdulo de destino '%s' existe. -A¿ Sobreescribir ?$)B msg.foundgate Encontrada puerta denominada '%s'. msg.foundwire Encontrado cable denominado '%s'. msg.searchagn Cadena destino '%s' no encontrada. Pulsa 'find' para reiniciar la bsqueda. msg.sim.chgtoroot El modo Simulacin requiere el mdulo principal en la cima de la pila de Edicin. msg.sim.nogatemod Modo SimulacinSimulation requiere un mdulo concreto de pila. msg.setinterface Ajustar el interfaz del mdulo para '%s'. msg.needsel Por favor selecciona una instancia de mdulo. msg.wroteckpt Chequea punto a %s... msg.save Salva circuito como '%s'. msg.reallynew El circuito se ha modificado. -A¿ Realmente desea perder los cambios y crear uno nuevo ?$)B msg.reallyquit El circuito se ha modificado. -A¿ Realmente desea salir ??$)B msg.notlib '%s' no es un mdulo de libreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Slo un loco colocaria %s%s aqu, Miles. miles.msg2 Es realmente un estpido lugar donde colocar %s%s, Miles. miles.msg3 Es un lugar horrible para colocar %s%s, Miles. miles.msg4 Miles, debes estar loco si colocas %s%s aqu. miles.msg5 Slo tu puedes colocar %s%s aqu, Miles. miles.msg6 Colocar %s%s aqu es un prueba m-Aás de que eres absolutamente estpido, Miles.$)B miles.msg7 No sabes lo que haces, Miles, es un circuito estpido. miles.msg8a Es intil continuar, Miles. miles.msg8b Es obvio que no puedes disear un circuito ############################################################################# # # Error messages generated by verga # verga.err.OK TODO: Don't worry, be happy. verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument '%s' in task '%s'. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task '%s' must be used in a specify block. verga.err.BADSPECTASK TODO: Task '%s' can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.PATHDCOND TODO: DelaMust set through both # expression and specify block. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declaration. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declaration. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.BADPORTTYPE TODO: Invalid type declaration used on port '%s' verga.err.BADVALUE TODO: Bad numeric value '%s'. verga.err.NONEXPCTL TODO: Event control @(*) applied to non-expression. verga.err.NONSTATCTL TODO: Event control @(*) applied to non-statment. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing TODO: Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule TODO: Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname TODO: Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname TODO: Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr TODO: Move all items to selected list. ho.setsel.alll TODO: Move all items to unselected list. ho.setsel.ltor TODO: Move highlighted items to selected list. ho.setsel.rtol TODO: Move highlighted items to unselected list. ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.simmode TODO: Choose between the select and scroll tool in simulator. ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Borra el circuito actual y, empieza a editar uno nuevo. -end- ho.open Fichero -> Circuito ho.save Circuito -> Fichero actual ho.saveas TODO: Save circuit to specified file. ho.print Circuito -> Impresora ho.library TODO: Load a library file. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- Move/Connect - Pulsando y arrastrando el ratn puedes: Ajustar la posicin de una puerta reci-Aén insertada Mover puertas y conexiones ya colocadas Conectar cables entre patillas de puertas Realizando una doble pulsacin puedes: Editar las propiedades de puertas, conexiones y puertos Editar el texto de los comentarios$)B -end- ho.delgat -begin- borrar puerta - Usa esta herramienta para borrar las puertas. -end- ho.cutw -begin- Corta cables - Usa esta herramienta para desconectar cables. -end- ho.inv -begin- Invertir - Usa esta herramienta para insertar o borrar inversiones de las patillas de las puertas. -end- ho.bitw -begin- Anchura del Bus - Usa esta herramienta para cambiar el nmero de lineas del Bus. Introduce dicho nmero en la parte inferior derecha de la ventana. -end- ho.ipanel.select -begin- TODO: Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- TODO: Add a port to the module. You can also double-click after the last item to add port. -end- ho.ipanel.deleteport -begin- TODO: Delete the selected port. -end- ho.ipanel.editport -begin- TODO: Edit the selected port. You can also double-click to edit a field in a port. -end- ho.ipanel.generate -begin- TODO: Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.ipanel.updateall -begin- TODO: Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Abre el mdulo seleccionado. ho.mod.close Cierra el mdulo actual. ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo TODO: Undo previous action(s) ho.redo TODO: Redo undone action(s) ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- TODO: Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Encuentra caminos cr-Aíticos en el circuito.$)B -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Si no estamos simulando, inicia la Simulacin y ejecuta cualquier guin de inicializacin. Si estamos simulando, se coloca en modo continuo o interactivo. -end- ho.simpause -begin- Para la simulacin en curso. -end- ho.simstep -begin- Avanza la simulacin un intervalo de tiempo fijo. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simclock -begin- Avanza la simulacin un nmero fijo de ciclos de reloj. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simstop -begin- Finaliza la simulacin en curso y vuelve al modo de Edicin. -end- ho.simbreak -begin- Edita los puntos de ruptura. La Simulacin se detendr cuando la condicin ajustada sea vuelva verdadera. -end- ho.simexec -begin- Ejecuta un guin de simulacin. -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- Carga la memoria con el contenido de un fichero con extensin mem. -end- ho.simdump -begin- Almacena el contenido de la memoria en un fichero con extensin mem. -end- ho.f.modlist -begin- Lista todos los mulos actualmente cargados. El mdulo principal, el superior en la jerarquia se indica con el signo "+", los mdulos de libreria se visualizan entre par-Aéntesis.$)B -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- Lista todas las conexiones del mdulo actual. Conexiones marcadas con el signo "@" no presentan su nombre en el esquema (conexiones ocultas). Las conexiones BUS van seguidas del nmero de lineas que poseen. -end- ho.ports -begin- Lista todas las patillas del mdulo actual El signo '>' indica entrada, '<' indica salida, y '=' indica linea bidireccional. -end- ho.status.logo -begin- Estado de la Simulacin. Si se presenta una puerta de hierro estamos en el modo de Edicin. Si se presenta una puerta AND con cuatro patas estamos en modo de simulacin. Si la puerta est parada, la simulacin est detenida y si est en movimiento, la simulacin est en pleno funcionamiento. -end- ho.status.msg Los mensajes del programa se presentan aqu. ho.status.block La pila de mdulos que est-Aán siendo editados.$)B ho.status.file -begin- Fichero actualmente editado. El signo '*' indica que el buffer se ha modificado desde la ltima vez que el fichero se salvo en disco. -end- ho.print.selall Imprimir todos los mdulos actualmente cargados en TKGate. ho.print.selcur Imprimir slo el mdulo presente en la ventana de Edicin de TKGate. ho.print.seluse -begin- Imprime todos los mdulos "en uso". Los mdulos en uso son aquellos que descienden del principal siguiendo la jerarquia arborescente. -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- Imprime slo los mdulos seleccionados m-Aás abajo. Usa la tecla CONTROL para seleccionar más de uno.$)B -end- ho.print.modlist Selecciona los mdulos a imprimir. ho.print.timegraph -begin- TODO: The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.circuit.discchg -begin- TkGate no presenta un aviso si descartas los cambios sin salvar. -end- ho.circuit.extbar -begin- TODO: Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- Cables seleccionados con el cursor pueden ajustarse a esta anchura de Bus. -end- ho.edgat.signam -begin- El nombre de la seal seleccionada en la puerta. Puedes cambiar este nombre editandolo aqu. -end- ho.edgat.port -begin- El nombre de la patilla para esta seal en esta puerta. Este campo slo puede ser editado para intancias de mdulos. -end- ho.edgat.iolab -begin- La direccin de la seal seleccionada de esta puerta. Este campo slo puede editarse en las instancias de mdulos. -end- ho.edgat.bitlab -begin- La anchura de Bus de la seal seleccionada de esta puerta. Se puede cambiar editandola aqu. -end- ho.edgat.cycle El nmero total de periodos de tiempo en un ciclo de reloj. ho.edgat.phase El punto inicial del ciclo (en %). ho.edgat.duty El % del ciclo que el reloj est en estado bajo. ho.edgat.hide -begin- Activa esta bandera para no visualizar el nombre de la puerta. -end- ho.edgat.gtype Tipo de puerta. ho.edgat.gname Nombre de esta instancia de puerta. ho.edgat.ganchor Activa esta bandera para anclar la posicin de la puerta. ho.edgat.gx Coordenada X de la puerta. ho.edgat.gy Coordenada Y de la puerta. ho.edgat.swstate -begin- El estado inicial del conmutador cuando se inicia una sesin de Simulacin. -end- ho.edgat.dipstate -begin- El estado inicial de los interruptores DIP cuando se inicia una sesin de Simulacin. -end- ho.edgat.range El rango de bits a colocar en un bus. ho.edgat.memfile -begin- El fichero con el estado inicial de esta memoria. Este fichero se lee cuando se inicia el Simulador. -end- ho.edgat.func El tipo de funcin de este mdulo. ho.edgat.frame La etiqueta del panel. ho.traceprint -begin- TODO: Print trace logic trace. -end- ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.savetraces -begin- TODO: Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- TODO: Maximum number of undo actions to retain. -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- El nombre del lugar donde tkgate se ha instalado. Se utiliza en la salida impresa o fichero postscript. -end- ho.opt.smooth -begin- Si esta opcin est habilitada, el desplazamiento se optimiza al usar copias bitmap en lugar de un completo redibujado. Puedes colocarla en off si hay problemas con su servidor. -end- ho.opt.clip -begin- Si esta opcin est habilitada, Se actualiza solo la regin actualmente expuesta del entorno de Edicin. De lo contrario se redibuja todo. -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Si esta opcin est habilitada, slo un recuadro que rodea a las instancias de mdulos se dibuja mientras se arrastra este. Usa esta opcin en las m-Aáquinas con micros y tarjetas gráficas lentas.$)B -end- ho.opt.bhelp -begin- Si esta opcin est habilitada, los globos de ayuda se activan. Los globos de ayuda, como este mismo, proporciona una ayuda resumida sobre los elementos del interfaz, cuando el ratn se situa encima de ellos. -end- ho.opt.novice -begin- Si no se especifica ningn circuito en la linea de comandos. El programa TkGate presenta un tutorial para iniciarse en el manejo del programa. -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Habilita algunas opciones de depuracin. Slo es util para desarrolladores del programa TkGate. -end- ho.opt.ckpt Habilitat puntos de chequeo para circuitos no salvados. ho.opt.ckptfreq Frecuencia de los puntos de chequeo en segundos. ho.opt.beak -begin- Habilitar todas estas opciones. Si deshabilita esta opcin, estos modos (y esta caja de di-Aálogo) no aparece en el men opciones. Slo puede recuperarse editando el fichero .tkgate-properties.$)B -end- ho.opt.miles -begin- Si este modo est habilitado, el programa insulta periodicamente la inteligencia del usuario. -end- ho.opt.bat -begin- Si este modo est habilitado, el programa activar el entorno para disear un computador sencillo a partir de mdulos. -end- ho.opt.trek Ayudame Scoty! ho.opt.simstep -begin- El nmero de periodos de tiempo que avanzamos si hemos activado el modo paso a paso por tiempo. -end- ho.opt.ckstep -begin- El nmero de ciclos de reloj que avanzamos si hemos activado el modo paso a paso por n-Aº de ciclos.$)B -end- ho.opt.ckover -begin- El nmero de periodos de tiempo despu-Aés de un flanco de bajada de reloj que avanzamos si hemos activado el modo paso a paso.$)B -end- ho.opt.vpopupdelay -begin- TODO: The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- El fichero de guin que se ejecuta de forma autom-Aática al iniciar la Simulacin.$)B -end- ho.opt.ckall -begin- Si este modo se habilita, el comando paso a paso parar la simulacin en el flanco de subida de cualquier reloj presente en el circuito. -end- ho.opt.ckspec -begin- Si este modo est habilitado, el comando paso a paso parar la simulacin es el flanco de subida de la seal de reloj especificada. -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- La tecnolog-Aía por defecto utilizada para las puertas recién creadas. Afecta al tiempo de retraso de las puertas. Para cambiar la tecnología de una puerta especifica, abrir la caja de propiedades ( doble click ) y selecciona "Retraso".$)B -end- ho.techbut -begin- Usa retrasos para la tecnolog-Aía standard de un fichero de definicin. Para aadir tecnologias personalizadas, aadirlas en la lista del men "Fichero -> Opciones -> Simulador".$)B -end- ho.custbut -begin- Ajustar valores de retrasos personalizados para esta puerta. -end- ho.contver -begin- TODO: Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Visualizar comandos enviados entre el entorno de visualizacin (GUI) y el Simulador. -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.symed.import TODO: Import image from file. ho.symed.export TODO: Export image to file. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin TODO: Zoom in ho.tool.zoomout TODO: Zoom out ho.tool.rotate TODO: Rotate selected gate(s) counter-clockwise. ho.tool.brotate TODO: Rotate selected gate(s) clockwise. ho.tool.valgn TODO: Align selected gate(s) vertically. ho.tool.halgn TODO: Align selected gate(s) horizontally. ho.tool.cut TODO: Cut selection. ho.tool.copy TODO: Copy selection. ho.tool.paste TODO: Paste from cut buffer. ho.tool.find TODO: Find gate, wire or text. ho.tool.addport TODO: Add a port to the selected gate. ho.tool.anchor TODO: Anchor the selected gate(s). ho.tool.unanchor TODO: Unanchor the selected gate(s). ho.tool.replicate TODO: Replicate a gate. ho.tool.delete TODO: Delete the selection. tkgate-2.0-b10/locale/es/messages.orig000644 001751 001751 00000066160 07311226664 020365 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Jan 26 11:08:13 2001 # # Translation by Agustn Borrego (agusbo@iponet.es) # ############################################################################## # # basic strings # b.dismiss Volver b.close Cerrar b.ok OK b.clear Borrar b.cancel Cancelar b.open Abrir... b.bitw Anchura Bus b.in entrada b.out salida b.inout bidireccional b.browse Visualizar... b.label Etiqueta b.find Buscar b.edit Editar... b.add Añadir... b.delete Borrar b.deleteb Borrar... b.apply Aplicar b.anchor Anclar b.tech Tecnología ############################################################################## # Menu strings # file Fichero edit Editar tool Herramientas simulate Simular module Módulo gate Puerta make Insertar circ Circuito new Nuevo open Abrir... openlib Abrir Libreria... save Salvar saveas Salvar como... print Imprimir... options Opciones... quit Salir cut Cortar copy Copiar paste Pegar selall Seleccionar Todo find Buscar... algnv Situar en Columna algnh Situar en Fila zoomin Zoom Acercar zoomout Zoom Alejar move Mover/Conectar delg Borrar puerta cutw Cortar cable inv Invertir bitw Anchura del bus debug Depurar rot0 Orientación 0º rot90 Orientación 90º rot180 Orientación 180º rot270 Orientación 270º simbegin Empezar Simulación simend Terminar Simulación simrun Modo continuo simpause Pausa simstep Paso a paso (tiempo) simcycle Paso a paso (nº ciclos) simbreak Punto de ruptura... simscript Ejecutar Guión... simload Fichero -> Memoria... simdump Memoria -> Fichero... modopen Abrir modclose Cerrar modseti Ajustar Interface modediti Editar Interfaces... modnew Nuevo... moddel Borra... modcopy Copia... modrename Renombra... modclaim Módulo libreria -> Módulo usuario... circprop Propiedades del circuito... cpath Camino crítico... gataddin Añade Entrada gataddout Añade Salida gataddinout Añade Bidireccional gatiochg Cambiar Tipo gatanchor Anclar Selección gatunanchor Liberar Selección gatprop Propiedades... gatrep Réplica gatdel Borrar gatsettech Seleccionar Tecnología gmswitch Entrada/Salida gmgate Puerta gmredgate Reducción gmmsi MSI gmalu ALU gmmem Memoria gmmod Módulo gmcomment Comentario gmframe Marco gmxswitch Conmutador gmdip Interruptores DIP gmground Masa gmvdd Vdd gmmerge Lineas <-> Bus gmclock Señal de Reloj gm.led LED gm.ledbar Barra de LEDs gm.ledhex 7-Seg. LED (HEXADECIMAL) gm.leddec 7-Seg. LED (DECIMAL) gm.ledseg 7-Seg. LED (Directo) gmtty TTY (Terminal) gmand AND (Y) gmnand NAND (NO-Y) gmor OR (O) gmnor NOR (NO-O) gmxor XOR (O-EX) gmxnor XNOR (NO-O-EX) gmbuf Buffer gminv Inversor gmtribuf Buffer-Triestado gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Sumador gmmult Multiplicador gmdiv Divisor gmlshift DespL. Izquierda gmrshift DespL. Derecha gmarshift DespL. Arit. Derecha gmroll DespL. cíclico gmreg Registro gmff Flip-Flop D gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decodificador gm14dec 1-4 Decodificador gm18dec 1-8 Decodificador gmmodinst Inserta módulo gmmodin Entrada Módulo gmmodout Salida Módulo gmmodinout Bidireccional Módulo addwireseg Añadir segmento de cable help Ayuda hlpabout Acerca de... hlplicense Licencia... hlpdoc Documentación... hlptut Tutoriales hlpexample Ejemplos exampcomb Lógica Combinacional examp3bit Contador de 3 bits examp8bit Contador de 8 bits examptrff FF a nivel de Transistores exampcpu CPU tutwelcome Introducción al TkGate tutcreate Creando un Circuito tutedit1 Editando un Circuito (1) tutedit2 Editando un Circuito (2) tutmods Usando los Módulos tutsim Simulando un Circuito # Scope Menu menu.sc.prtrace Visualizando Señal... menu.sc.close Cerrar menu.sc.trace Señal menu.sc.zoomin Acercar menu.sc.zoomout Alejar ############################################################################## # Interface strings # ifile Fichero imodule Módulo iblmodule Módulos: iports Puertos: ibits Bits: ############################################################################# # Net Dialog Box # db.net.name Nombre Conexión db.net.hide Nombre Oculto db.net.bits Anchura Bus db.net.port Tipo de Patilla db.net.in entrada db.net.out salida db.net.inout bidireccional db.net.inets Conexiones ############################################################################## # Gate dialog box # db.gate.signam Nombre de la Señal db.gate.portnam Nombre de la Patilla db.gate.iotype Tipo db.gate.bitw Anchura Bus db.gate.cyclew Anchura Ciclo db.gate.phase Fase db.gate.duty Función db.gate.port Patilla db.gate.bitws Bits db.gate.gtype Tipo de Puerta db.gate.gname Nombre de la Puerta db.gate.hidenam Nombre Oculto db.gate.anchor Anclada db.gate.cpbreak Ruptura del camino crítico db.gate.butstate Estado del Botón db.gate.dipval Valor del conmutador db.gate.memfilenam Fichero de Memoria db.gate.modname Función db.gate.islink El Texto es un Hiperenlace db.gate.link Enlace a Fichero db.gate.findw Busca sólo cables db.gate.findg Busca sólo puertas db.gate.findwg Busca cables y puertas db.gate.general General db.gate.details Detalles db.gate.ports Patilla db.gate.delay Retraso db.gate.stddelay Retraso Normal db.gate.custdelay Retraso Personalizado db.led.type Tipo de LED db.led.bit Bit db.led.bar Barra Grafica db.led.hex 7-Segment (HEXADECIMAL) db.led.dec 7-Segment (DECIMAL) db.led.seg 7-Segment (Directo) cpath.cloops -begin- Se ha detectado un bucle de realimentación en su circuito. Para poder realizar un análisis de los retrasos en dicho circuito deberemos, o bién romper el bucle, o marcar alguna de las puertas en el bucle como punto de un "Camino crítico". Las conexiones detectadas como bucle se listan más abajo. -end- ############################################################################## # Print dialog box # print.outto Salida a print.printer Impresora print.file Fichero print.prcmd Comando de Impresión print.filename Nombre del Fichero print.epssave Salvar como Postscript Encapsulado. print.doctit Título del Documento print.prmod Imprimir Módulos print.epcm Periodo de tiempo/cm print.estpg Páginas estimadas print.all Todo print.cur Actual print.use Usados print.sel Seleccionados print.inclib Incluye módulos de libreria. print.papsz Tamaño del Papel print.orient Orientación print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opciones print.scale Escalar módulos hasta completar página. print.partition Dividir módulos grandes en varias páginas. print.incidx Incluye indice. print.incgraph Incluye gráfico de jerarquia. print.4up Imprimir cuatro módulos pequeños por página. print.range Rango print.fulltr Trazado completo print.parttr Trazado parcial print.start Empezar print.end Fin ############################################################################## # # Options dialog # opt.site Nombre de la Empresa opt.inst Instancias opt.mods Módulos opt.modports Patillas de Módulos opt.frames Marcos opt.comment Comentarios opt.hlink Hiperenlaces opt.wire Cables simples (1 Bit) opt.bus Buses opt.tools Herramientas de Puerta opt.cpath Caminos críticos opt.grid Visualizar Rejilla opt.logic1 Lógica '1' opt.logic0 Lógica '0' opt.float Flotante opt.unknown Conflicto Desconocido opt.offled LED apagado opt.onled LED encendido opt.zled LED flotante opt.restdef Restaura opciones por defecto opt.regudate Actualizar Región opt.smoothscroll Desplazamiento Suave opt.outmove Recuadro en desplazamientos de Módulos opt.balloon Habilitar Globos de Ayuda opt.debug Habilitar Depuración opt.novice Modo Novato opt.ckpoint Realizar Chequeo de Puntos opt.freq Frecuencia opt.beak Habilitar Modo Especial opt.mode Modo opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.showsimcmd Visualizar Cadena Simulada opt.logfile Fichero de mensajes del Simulador opt.estepsz Ajuste Tiempo (Simulación paso a paso) opt.cstepsz Ajuste nº ciclos (Simulación paso a paso) opt.overstep Exceder Reloj opt.initscript Guión de inicialización opt.posedge El reloj para después de todos los flancos opt.setclock El reloj para en punto opt.delayfilepath Ficheros de Retraso opt.general General opt.print Imprimir opt.simulate Simular opt.analysis Análisis opt.color Color opt.cpopts Opciones de los caminos críticos: opt.maxpath Máximo nº de caminos: opt.cpflash Presentar como relampago opt.vercheck -begin- Chequea de forma periódica si existen nuevas versiones del programa TKGATE en Internet. No habilitarla si no se dispone de una conexión permanente a la RED. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Módulo nuevo blklst.delmod Borra Módulo blklst.frommod Copia Módulo de blklst.tomod a blklst.oldname Nombre anterior blklst.newname Nombre nuevo blklst.claim Módulo libreria -> Módulo ususario ############################################################################## # # Circuit Dialog box # circ.topmod Módulo principal circ.discchg Descartar cambios circ.iniscript Guiones de Inicialización circ.noscript No ha seleccionado ficheros de guión. circ.really1 Quiere realmente borrarlo circ.really2 de la lista de guiones de inicialización ############################################################################## # Simulator # sim.breakpt Punto de ruptura ############################################################################## # # Command box # cmd.file Nombre del fichero cmd.topname Nombre del módulo principal ############################################################################## # # Critical path messages # cp.delay Retraso del camino: cp.pathl Lista de caminos: cp.numpath Número de caminos: cp.recompute Recómputo ############################################################################## # Error messages # err.verilog Errores en fichero: err.nopin No puedo cambiar la patilla seleccionada. err.badhex Valor hexadecimal incorrecto. Ignoro '%s'. err.gatanchor Puertas Ancladas no pueden moverse. err.libmode Operación imposible en módulo de libreria (convertir a módulo normal para editar). err.badfind No puedo encontrar '%s' como destino. err.badopendel No puedo borrar el módulo abierto. err.nosrcmod No puedo encontrar '%s' como módulo fuente. err.noerr No puedo indicarle el error. err.misserr Error información incompleta (did the simulator crash?) err.pounimpl Información de error no implementada err.badinadd No puedo añadir más entradas a la puerta seleccionada. err.badoutadd No puedo añadir más salidas a la puerta seleccionada. err.badinoutadd No puedo añadir más lineas bidireccionales a la puerta err.badpinchg No puedo cambiar el tipo de patillas de la puerta. err.badnetname He borrado caracteres incorrectos en el identificador. err.netbcrename Identificador cambia a '%s' por caracteres incorrectos. err.netconfnet Identificador cambia a '%s' debido a un conflicto. err.netconfgat Identificador cambia debido a conflicto con nombre de puerta básica. err.netconfkw Identificador cambia debido a conflicto con palabra reservada. err.badconsame Unión rechazada debido a que los cables forman parte de la misma conexión. err.badconptsp Unión rechazada debido a que ambos cables son patillas de módulos o alimentación. err.badconbitw Unión rechazada por no poderse emparejar la anchura de los dos buses. err.badrange No se permite visualizar el rango no positivo de la señal. err.badlprcmd No puedo ejecutar el comando '%s' de impresión. err.badpsopen No puedo abrir el fichero '%s' para salida postscript. err.bkpt.badexp Error de sintaxis en expresión para punto de ruptura. Debe ser una de las siguientes: 'conexión', '!conexión', 'conexión == valor', 'conexión != valor' err.bkpt.badnet '%s' es un nombre incorrecto de conexión. Los nombres válidos deben empezar por una letra y contener sólo letras, números y el signo '.'. err.bkpt.badval Error de sintaxis en el valor '%s'. Debe ser decimal o una constante en el estilo Verilog. err.bkpt.toomany Demasiados puntos de ruptura. El máximo es de %d. err.sim.badtmp No puedo salvar el fichero temporal '%s' para la simulación ( ¿ Disco lleno ? ) err.sim.syntx Error de sintaxis en el comando '%s'. err.sim.noincl El fichero Include '%s' no se encuentra. err.sim.clockbadedge Ilegal indicador en el pulso '%c' del comando de reloj. err.sim.nobkpt No existe punto de ruptura '%s'. err.sim.nonet No puedo encontrar la conexión '%s'. err.sim.nogate No puedo encontrar la puerta '%s'. err.sim.badbin '%s' es un carácter incorrecto en constante binaria. err.sim.notswitch La puerta '%s' no es un conmutador, dip o registro. err.sim.badcmd No reconozco el comando '%s' en el guión de simulación. err.noteditpchg Las propiedades sólo pueden cambiarse en modo Edición. err.badeditop Operación ilegal en el modo de Edición. err.badopen No se puede abrir el fichero '%s'. err.badlibopen No puedo abrir la libreria '%s'. err.nomark Por favor marca con el botón izquierdo antes de seleccionar el tipo de puerta. err.badgate No conozco ese tipo de puerta. err.badmake No puedo crear la puerta. err.manypages -begin- Hay un montón de páginas en este documento. ¿ Estás seguro de querer imprimirlo ?. -end- err.nojump -begin- La posibilidad de 'saltar al módulo' no se puede utilizar en el modo de simulación o en el análisis de un camino crítico. Por favor navega de forma manual hasta el bloque de destino seleccionando los módulos adecuados y utilizando la opción '>' del teclado. Se acceder al módulo de nivel superior en la jerarquia actuando sobre la tecla '<'. -end- err.nomod Módulo '%s' no está definido. err.modlock !Este bloque lógico lo está visualizando! err.closeroot No puedo cerrar el módulo principal. Utiliza la opción Salir del menú Fichero. err.sim.isrun El simulador está ejecutandose en estos momentos (Utiliza 'Ctrl-s e' para terminar). err.sim.isnotrun El simulador no está funcionando (Utiliza 'Ctrl-s b' para empezar). err.editonly Comando incorrecto en el modo de Simulación. err.simonly Comando sólo válido en modo Simulación. err.nodel No se puede borrar lo seleccionado. err.modnotdef Módulo '%s' no definido. err.moddef El bloque '%s' ya existe. err.noprop No se pueden editar las propiedades de la puerta seleccionada. err.openscript No puedo abrir el fichero de guión de simulación '%s' err.oldversion Cargado fichero de la versión %s, obsoleta (la más reciente es la versión %s). err.futureversion Fichero salvado en la versión %s, futura versión del programa tkgate (la versión actual es %s). err.badversion Se desconoce el número de versión. Usada bajo su responsabilidad. err.nodrive Conexión %s no posee entrada en el módulo %s. err.noconn Cable %s{%d} no posee conexiones - lo borramos. err.noback -begin- El fichero %s, se creará por el programa tkgate, y no puede leerse por versiones anteriores a la actual (%s), si decide salvarlo. -end- ############################################################################## # Informational messages # msg.selwire Seleccionado cable denominado '%s'. msg.selgate Seleccionado %s denominado '%s'. msg.selblock Seleccionado bloque %s denominado '%s'. msg.modoverwt Módulo de destino '%s' existe. ¿ Sobreescribir ? msg.foundgate Encontrada puerta denominada '%s'. msg.foundwire Encontrado cable denominado '%s'. msg.searchagn Cadena destino '%s' no encontrada. Pulsa 'find' para reiniciar la búsqueda. msg.sim.chgtoroot El modo Simulación requiere el módulo principal en la cima de la pila de Edición. msg.sim.nogatemod Modo SimulaciónSimulation requiere un módulo concreto de pila. msg.setinterface Ajustar el interfaz del módulo para '%s'. msg.needsel Por favor selecciona una instancia de módulo. msg.wroteckpt Chequea punto a %s... msg.save Salva circuito como '%s'. msg.badsave Falla fichero de salida '%s'. msg.reallynew El circuito se ha modificado. ¿ Realmente desea perder los cambios y crear uno nuevo ? msg.reallyquit El circuito se ha modificado. ¿ Realmente desea salir ?? msg.notlib '%s' no es un módulo de libreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Sólo un loco colocaria %s%s aquí, Miles. miles.msg2 Es realmente un estúpido lugar donde colocar %s%s, Miles. miles.msg3 Es un lugar horrible para colocar %s%s, Miles. miles.msg4 Miles, debes estar loco si colocas %s%s aquí. miles.msg5 Sólo tu puedes colocar %s%s aquí, Miles. miles.msg6 Colocar %s%s aquí es un prueba más de que eres absolutamente estúpido, Miles. miles.msg7 No sabes lo que haces, Miles, es un circuito estúpido. miles.msg8a Es inútil continuar, Miles. miles.msg8b Es obvio que no puedes diseñar un circuito ############################################################################## # Balloon Help # ho.new -begin- Borra el circuito actual y, empieza a editar uno nuevo. -end- ho.open Fichero -> Circuito ho.save Circuito -> Fichero actual ho.print Circuito -> Impresora ho.move -begin- Move/Connect - Pulsando y arrastrando el ratón puedes: Ajustar la posición de una puerta recién insertada Mover puertas y conexiones ya colocadas Conectar cables entre patillas de puertas Realizando una doble pulsación puedes: Editar las propiedades de puertas, conexiones y puertos Editar el texto de los comentarios -end- ho.delgat -begin- borrar puerta - Usa esta herramienta para borrar las puertas. -end- ho.cutw -begin- Corta cables - Usa esta herramienta para desconectar cables. -end- ho.inv -begin- Invertir - Usa esta herramienta para insertar o borrar inversiones de las patillas de las puertas. -end- ho.bitw -begin- Anchura del Bus - Usa esta herramienta para cambiar el número de lineas del Bus. Introduce dicho número en la parte inferior derecha de la ventana. -end- ho.modopen Abre el módulo seleccionado. ho.modclose Cierra el módulo actual. ho.simgo -begin- Si no estamos simulando, inicia la Simulación y ejecuta cualquier guión de inicialización. Si estamos simulando, se coloca en modo continuo o interactivo. -end- ho.simpause -begin- Para la simulación en curso. -end- ho.simstep -begin- Avanza la simulación un intervalo de tiempo fijo. Abre el submenu Opciones de Simulación para ajustarlo. -end- ho.simclock -begin- Avanza la simulación un número fijo de ciclos de reloj. Abre el submenu Opciones de Simulación para ajustarlo. -end- ho.simstop -begin- Finaliza la simulación en curso y vuelve al modo de Edición. -end- ho.simbreak -begin- Edita los puntos de ruptura. La Simulación se detendrá cuando la condición ajustada sea vuelva verdadera. -end- ho.simexec Ejecuta un guión de simulación. ho.simload -begin- Carga la memoria con el contenido de un fichero con extensión mem. -end- ho.simdump -begin- Almacena el contenido de la memoria en un fichero con extensión mem. -end- ho.sim.break -begin- Introduce punto de ruptura. Punto de ruptura es una expresión que detiene la simulación cuando su evaluación resulta verdadera. Las Expresiones soportadas por el programa son del tipo operador relacional simple : "w1 == 0" o "w7 != 8". También se contempla expresiones en las que se niega la conexión: "!w2". -end- ho.f.modlist -begin- Lista todos los móulos actualmente cargados. El módulo principal, el superior en la jerarquia se indica con el signo "+", los módulos de libreria se visualizan entre paréntesis. -end- ho.netlist -begin- Lista todas las conexiones del módulo actual. Conexiones marcadas con el signo "@" no presentan su nombre en el esquema (conexiones ocultas). Las conexiones BUS van seguidas del número de lineas que poseen. -end- ho.ports -begin- Lista todas las patillas del módulo actual El signo '>' indica entrada, '<' indica salida, y '=' indica linea bidireccional. -end- ho.status.logo -begin- Estado de la Simulación. Si se presenta una puerta de hierro estamos en el modo de Edición. Si se presenta una puerta AND con cuatro patas estamos en modo de simulación. Si la puerta está parada, la simulación está detenida y si está en movimiento, la simulación está en pleno funcionamiento. -end- ho.status.msg Los mensajes del programa se presentan aquí. ho.status.block La pila de módulos que están siendo editados. ho.status.file -begin- Fichero actualmente editado. El signo '*' indica que el buffer se ha modificado desde la última vez que el fichero se salvo en disco. -end- ho.print.selall Imprimir todos los módulos actualmente cargados en TKGate. ho.print.selcur Imprimir sólo el módulo presente en la ventana de Edición de TKGate. ho.print.seluse -begin- Imprime todos los módulos "en uso". Los módulos en uso son aquellos que descienden del principal siguiendo la jerarquia arborescente. -end- ho.print.selsel -begin- Imprime sólo los módulos seleccionados más abajo. Usa la tecla CONTROL para seleccionar más de uno. -end- ho.print.modlist Selecciona los módulos a imprimir. ho.circuit.discchg -begin- TkGate no presenta un aviso si descartas los cambios sin salvar. -end- ho.cmd.bitw -begin- Cables seleccionados con el cursor pueden ajustarse a esta anchura de Bus. -end- ho.edgat.signam -begin- El nombre de la señal seleccionada en la puerta. Puedes cambiar este nombre editandolo aquí. -end- ho.edgat.port -begin- El nombre de la patilla para esta señal en esta puerta. Este campo sólo puede ser editado para intancias de módulos. -end- ho.edgat.iolab -begin- La dirección de la señal seleccionada de esta puerta. Este campo sólo puede editarse en las instancias de módulos. -end- ho.edgat.bitlab -begin- La anchura de Bus de la señal seleccionada de esta puerta. Se puede cambiar editandola aquí. -end- ho.edgat.cycle El número total de periodos de tiempo en un ciclo de reloj. ho.edgat.phase El punto inicial del ciclo (en %). ho.edgat.duty El % del ciclo que el reloj está en estado bajo. ho.edgat.cname Nombre de la conexión a la que se une. ho.edgat.cport Patilla de está conexión a la que se une. ho.edgat.ctype Tipo de conexión. ho.edgat.cbitw Anchura de Bus de la conexión a la que se une. ho.edgat.cedit Edita la patilla seleccionada. ho.edgat.cadd Añade una patilla. ho.edgat.cdel Borra la patilla seleccionada. ho.edgat.hide -begin- Activa esta bandera para no visualizar el nombre de la puerta. -end- ho.edgat.gtype Tipo de puerta. ho.edgat.gname Nombre de esta instancia de puerta. ho.edgat.ganchor Activa esta bandera para anclar la posición de la puerta. ho.edgat.gx Coordenada X de la puerta. ho.edgat.gy Coordenada Y de la puerta. ho.edgat.swstate -begin- El estado inicial del conmutador cuando se inicia una sesión de Simulación. -end- ho.edgat.dipstate -begin- El estado inicial de los interruptores DIP cuando se inicia una sesión de Simulación. -end- ho.edgat.range El rango de bits a colocar en un bus. ho.edgat.memfile -begin- El fichero con el estado inicial de esta memoria. Este fichero se lee cuando se inicia el Simulador. -end- ho.edgat.func El tipo de función de este módulo. ho.edgat.frame La etiqueta del panel. ho.opt.site -begin- El nombre del lugar donde tkgate se ha instalado. Se utiliza en la salida impresa o fichero postscript. -end- ho.opt.smooth -begin- Si esta opción está habilitada, el desplazamiento se optimiza al usar copias bitmap en lugar de un completo redibujado. Puedes colocarla en off si hay problemas con su servidor. -end- ho.opt.clip -begin- Si esta opción está habilitada, Se actualiza solo la región actualmente expuesta del entorno de Edición. De lo contrario se redibuja todo. -end- ho.opt.outmove -begin- Si esta opción está habilitada, sólo un recuadro que rodea a las instancias de módulos se dibuja mientras se arrastra este. Usa esta opción en las máquinas con micros y tarjetas gráficas lentas. -end- ho.opt.bhelp -begin- Si esta opción está habilitada, los globos de ayuda se activan. Los globos de ayuda, como este mismo, proporciona una ayuda resumida sobre los elementos del interfaz, cuando el ratón se situa encima de ellos. -end- ho.opt.novice -begin- Si no se especifica ningún circuito en la linea de comandos. El programa TkGate presenta un tutorial para iniciarse en el manejo del programa. -end- ho.opt.debug -begin- Habilita algunas opciones de depuración. Sólo es util para desarrolladores del programa TkGate. -end- ho.opt.ckpt Habilitat puntos de chequeo para circuitos no salvados. ho.opt.ckptfreq Frecuencia de los puntos de chequeo en segundos. ho.opt.beak -begin- Habilitar todas estas opciones. Si deshabilita esta opción, estos modos (y esta caja de diálogo) no aparece en el menú opciones. Sólo puede recuperarse editando el fichero .tkgate-properties. -end- ho.opt.miles -begin- Si este modo está habilitado, el programa insulta periodicamente la inteligencia del usuario. -end- ho.opt.bat -begin- Si este modo está habilitado, el programa activará el entorno para diseñar un computador sencillo a partir de módulos. -end- ho.opt.trek Ayudame Scoty! ho.opt.normal Descartar el cachondeo. ho.opt.simstep -begin- El número de periodos de tiempo que avanzamos si hemos activado el modo paso a paso por tiempo. -end- ho.opt.ckstep -begin- El número de ciclos de reloj que avanzamos si hemos activado el modo paso a paso por nº de ciclos. -end- ho.opt.ckover -begin- El número de periodos de tiempo después de un flanco de bajada de reloj que avanzamos si hemos activado el modo paso a paso. -end- ho.opt.init -begin- El fichero de guión que se ejecuta de forma automática al iniciar la Simulación. -end- ho.opt.ckall -begin- Si este modo se habilita, el comando paso a paso parará la simulación en el flanco de subida de cualquier reloj presente en el circuito. -end- ho.opt.ckspec -begin- Si este modo está habilitado, el comando paso a paso parará la simulación es el flanco de subida de la señal de reloj especificada. -end- ho.deftech -begin- La tecnología por defecto utilizada para las puertas recién creadas. Afecta al tiempo de retraso de las puertas. Para cambiar la tecnología de una puerta especifica, abrir la caja de propiedades ( doble click ) y selecciona "Retraso". -end- ho.techbut -begin- Usa retrasos para la tecnología standard de un fichero de definición. Para añadir tecnologias personalizadas, añadirlas en la lista del menú "Fichero -> Opciones -> Simulador". -end- ho.custbut -begin- Ajustar valores de retrasos personalizados para esta puerta. -end- ho.simwatch -begin- Visualizar comandos enviados entre el entorno de visualización (GUI) y el Simulador. -end- ho.simlog -begin- Escribe comandos emitidos por el simulador en un fichero de anotación. Este puede usarse como fichero de entrada al simulador en la depuración. -end- ho.cpathanal -begin- Encuentra caminos críticos en el circuito. -end- tkgate-2.0-b10/locale/es/messages.orig2000644 001751 001751 00000163726 10217547422 020452 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Mar 21 08:41:38 2005 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## ############################################################################## # # basic strings # b.new Nuevo... b.dismiss Volver b.close Cerrar b.ok OK b.clear Borrar b.cancel Cancelar b.open Abrir... b.bitw Anchura Bus b.in entrada b.out salida b.inout bidireccional b.browse Visualizar... b.label Etiqueta b.find Buscar b.edit Editar... b.add Aadir... b.delete Borrar b.deleteb Borrar... b.remove TODO: Remove b.apply Aplicar b.anchor Anclar b.tech Tecnología ############################################################################## # # Main tab strings # tab.edit Editar tab.editintr TODO: Interface tab.simulate Simular tab.cpath TODO: Critical Path # Width of mode selection tabs @tab.width 150 ############################################################################## # Menu strings # menu.file Fichero menu.edit TODO: Edit menu.tool Herramientas menu.simulate TODO: Simulate menu.module Mdulo menu.interface TODO: Interface menu.gate Puerta menu.make Insertar menu.circ Circuito menu.help Ayuda menu.file.new Nuevo menu.file.open TODO: Open... menu.file.openlib Abrir Libreria... menu.file.save Salvar menu.file.saveas TODO: Save As... menu.file.print Imprimir... menu.file.options Opciones... menu.file.quit Salir menu.edit.undo TODO: Undo menu.edit.redo TODO: Redo menu.edit.cut Cortar menu.edit.copy Copiar menu.edit.paste Pegar menu.edit.selall Seleccionar Todo menu.edit.find Buscar... menu.edit.algnv Situar en Columna menu.edit.algnh Situar en Fila menu.edit.rotate TODO: Rotate menu.edit.zoomin Zoom Acercar menu.edit.zoomout Zoom Alejar menu.tool.move Mover/Conectar menu.tool.delg Borrar puerta menu.tool.cutw Cortar cable menu.tool.inv Invertir menu.tool.bitw TODO: Bit Width menu.tool.debug Depurar menu.tool.rot0 Orientacin 0º menu.tool.rot90 Orientacin 90º menu.tool.rot180 Orientacin 180º menu.tool.rot270 Orientacin 270º menu.help.about Acerca de... menu.help.license Licencia... menu.help.doc Documentacin... menu.help.tut Tutoriales menu.help.example Ejemplos menu.help.example.comb Lgica Combinacional menu.help.example.3bit Contador de 3 bits menu.help.example.8bit Contador de 8 bits menu.help.example.trff FF a nivel de Transistores menu.help.example.cpu CPU menu.help.tut.welcome Introduccin al TkGate menu.help.tut.create Creando un Circuito menu.help.tut.edit1 Editando un Circuito (1) menu.help.tut.edit2 Editando un Circuito (2) menu.help.tut.mods Usando los Mdulos menu.help.tut.sim Simulando un Circuito menu.simulate.begin Empezar Simulacin menu.simulate.end Terminar Simulacin menu.simulate.addprobe TODO: Add/Delete Probe menu.simulate.run Modo continuo menu.simulate.pause Pausa menu.simulate.step Paso a paso (tiempo) menu.simulate.cycle Paso a paso (nº ciclos) menu.simulate.break Punto de ruptura... menu.simulate.script Ejecutar Guin... menu.simulate.load Fichero -> Memoria... menu.simulate.dump Memoria -> Fichero... menu.circ.prop Propiedades del circuito... menu.circ.cpath Camino crítico... menu.module.open Abrir menu.module.close TODO: Close menu.module.new TODO: New... menu.module.del TODO: Delete... menu.module.copy Copia... menu.module.rename Renombra... menu.module.claim Mdulo libreria -> Mdulo usuario... menu.module.setroot TODO: Set As Root... menu.module.prop Propiedades... menu.interface.set Ajustar Interface menu.interface.edit TODO: Edit Interface... menu.interface.generate TODO: Auto Generate... menu.gate.addin Aade Entrada menu.gate.addout Aade Salida menu.gate.addinout Aade Bidireccional menu.gate.ioset TODO: Set Type menu.gate.anchor Anclar Seleccin menu.gate.unanchor Liberar Seleccin menu.gate.prop TODO: Gate Properties... menu.gate.rep Réplica menu.gate.del TODO: Delete menu.gate.settech Seleccionar Tecnología mod.intf TODO: Interface port.parms TODO: Port Parameters port.in TODO: In port.out TODO: Out port.inout TODO: InOut ############################################################################## # # Tags for built-in gate types # gm.io Entrada/Salida gm.gate TODO: Gate gm.rgate Reduccin gm.msi MSI gm.alu ALU gm.mem Memoria gm.mod TODO: Module gm.comment Comentario gm.frame Marco gm.io.switch Conmutador gm.io.dip Interruptores DIP gm.io.ground Masa gm.io.vdd Vdd gm.io.merge TODO: Concat gm.io.clock Seal de Reloj gm.io.led LED gm.io.ledbar Barra de LEDs gm.io.ledhex 7-Seg. LED (HEXADECIMAL) gm.io.leddec 7-Seg. LED (DECIMAL) gm.io.ledseg 7-Seg. LED (Directo) gm.io.tty TTY (Terminal) gm.gate.and AND (Y) gm.gate.nand NAND (NO-Y) gm.gate.or OR (O) gm.gate.nor NOR (NO-O) gm.gate.xor XOR (O-EX) gm.gate.xnor XNOR (NO-O-EX) gm.gate.buf Buffer gm.gate.inv Inversor gm.gate.tribuf Buffer-Triestado gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and TODO: AND gm.rgate.nand TODO: NAND gm.rgate.or TODO: OR gm.rgate.nor TODO: NOR gm.rgate.xor TODO: XOR gm.rgate.xnor TODO: XNOR gm.alu.add Sumador gm.alu.mult Multiplicador gm.alu.div Divisor gm.alu.lshift DespL. Izquierda gm.alu.rshift DespL. Derecha gm.alu.arshift DespL. Arit. Derecha gm.alu.roll DespL. cíclico gm.mem.reg Registro gm.mem.ff Flip-Flop D gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decodificador gm.msi.14dec 1-4 Decodificador gm.msi.18dec 1-8 Decodificador gm.mod.inst Inserta mdulo gm.mod.in Entrada Mdulo gm.mod.out Salida Mdulo gm.mod.inout Bidireccional Mdulo # Scope Menu menu.sc.prtrace Visualizando Seal... menu.sc.close Cerrar menu.sc.trace Seal menu.sc.zoomin Acercar menu.sc.zoomout Alejar ############################################################################## # # Popup menus # pop.make TODO: Make pop.tool TODO: Tool pop.edit.paste TODO: Paste pop.edit.cut TODO: Cut pop.edit.copy TODO: Copy pop.port.in TODO: In pop.port.out TODO: Out pop.port.inout TODO: InOut pop.wire.addseg Aadir segmento de cable pop.wire.prop TODO: Properties... pop.gate.open TODO: Open pop.gate.close TODO: Close pop.gate.prop TODO: Properties... pop.gate.addin TODO: Add Input pop.gate.addout TODO: Add Output pop.gate.addinout TODO: Add BiDir pop.gate.anchor TODO: Anchor pop.gate.settech TODO: Set Technology pop.gate.delete TODO: Delete pop.gate.ioset TODO: Set Type pop.module.new TODO: New... pop.module.del TODO: Delete... pop.module.copy TODO: Copy... pop.module.rename TODO: Rename... pop.module.claim TODO: Claim... pop.module.setroot TODO: Set As Root... pop.module.prop TODO: Properties... pop.module.int TODO: Edit Interface... pop.simulate.end TODO: End Simulation pop.simulate.begin TODO: Begin Simulation pop.simulate.addprobe TODO: Add/Delete Probe pop.simulate.run TODO: Run pop.simulate.pause TODO: Pause pop.simulate.step TODO: Step Epoch(s) pop.simulate.cycle TODO: Step Cycle pop.simulate.break TODO: Breakpoint... pop.simulate.script TODO: Exec. Script... pop.simulate.load TODO: Load Memory... pop.simulate.dump TODO: Dump Memory... pop.interface TODO: Interface pop.interface.set TODO: Set as Default pop.interface.edit TODO: Edit Interface... pop.igen.type TODO: Type pop.igen.side TODO: Side pop.igen.size TODO: Size pop.igen.delete TODO: Delete pop.igen.in TODO: in pop.igen.out TODO: out pop.igen.inout TODO: inout pop.igen.left TODO: left pop.igen.right TODO: right pop.igen.top TODO: top pop.igen.bottom TODO: bottom pop.igen.other TODO: other ############################################################################## # # Symbol editor strings # symed.bsave TODO: Store symed.file TODO: File symed.file.load TODO: Load Bitmap... symed.file.save TODO: Save Bitmap... symed.file.updateclose TODO: Close and Update symed.file.discardclose TODO: Close and Discard symed.help TODO: Help symed.help.about TODO: About... symed.edit TODO: Edit symed.edit.cut TODO: Cut symed.edit.copy TODO: Copy symed.edit.paste TODO: Paste symed.edit.overlay TODO: Overlay Paste symed.edit.rclock TODO: Rotate Clockwise symed.edit.rcclock TODO: Rotate Counter-Clockwise symed.module TODO: Module symed.modes TODO: Modes symed.cutpaste TODO: Cut/Paste symed.rotate TODO: Port Rotation symed.zoom TODO: Zoom symed.update TODO: Update symed.cancel TODO: Cancel symed.tab.normal TODO: UnSelected symed.tab.select TODO: Selected # width of symbol editor tabs @symed.tab.width 125 ############################################################################## scope.emptymsg TODO: Double-click on a wire to add or delete a trace. comment.empty TODO: [Double click to add text.] ############################################################################## # Interface strings # ifile Fichero imodule Mdulo iblmodule Mdulos: iports Puertos: ibits Bits: ############################################################################# # Module Dialog Box # db.mod.name TODO: Name db.mod.file TODO: File Name db.mod.type TODO: Type db.mod.flags TODO: Flags db.mod.dataprot TODO: Disallow editing of module definition. db.mod.intfprot TODO: Disallow all interface changes. db.mod.edprot TODO: Disallow edit mode interface changes. db.mod.props TODO: Properties db.mod.inuse.0 TODO: Module is not in use. db.mod.inuse.1 TODO: Module is in use. db.mod.lmod.0 TODO: Module has not been modified since loading. db.mod.lmod.1 TODO: Module has been modified since loading. db.mod.smod.0 TODO: Module has not been modified since saving. db.mod.smod.1 TODO: Module has been modified since saving. db.mod.islib.1 TODO: Module is part of [%s] library. db.mod.islib.0 TODO: Module is not a library module. db.mod.netlist TODO: Netlist db.mod.hdl TODO: HDL db.mod.netexpl -begin- TODO: Modules of this type are described as a network of connected components. A graphical editor is used to edit the definition. -end- db.mod.hdlexpl -begin- TODO: Modules of this type are described in text format. A text editor is used to create the module definition. -end- ############################################################################# # Error List Dialog box # db.err.caption TODO: Error List db.err.explain -fillbegin- TODO: I am unable to enter simulation mode due to errors in your circuit. Select an error message to see the error location. -end- ############################################################################# # Net Dialog Box # db.net.name Nombre Conexin db.net.hide Nombre Oculto db.net.bits Anchura Bus db.net.port Tipo de Patilla db.net.in entrada db.net.out salida db.net.inout bidireccional db.net.inets Conexiones ############################################################################## # # New circuit dialog box # db.newcirc.cap TODO: New Circuit db.newcirc.exp -fillbegin- TODO: Discard the current circuit and start editing a new circuit. -end- db.newcirc.file TODO: File Name db.newcirc.topname Nombre del mdulo principal ############################################################################## # Gate dialog box # db.gate.signam Nombre de la Seal db.gate.portnam Nombre de la Patilla db.gate.iotype Tipo db.gate.bitw Anchura Bus db.gate.cyclew Anchura Ciclo db.gate.phase Fase db.gate.duty Funcin db.gate.port Patilla db.gate.bitws Bits db.gate.side TODO: Side db.gate.gtype Tipo de Puerta db.gate.gname Nombre de la Puerta db.gate.hidenam Nombre Oculto db.gate.anchor Anclada db.gate.cpbreak Ruptura del camino crítico db.gate.butstate Estado del Botn db.gate.dipval Valor del conmutador db.gate.range TODO: Bit Range db.gate.memfilenam Fichero de Memoria db.gate.modname Funcin db.gate.general General db.gate.details Detalles db.gate.text TODO: Text db.gate.ports Patilla db.gate.delay Retraso db.gate.stddelay Retraso Normal db.gate.custdelay Retraso Personalizado db.gate.catdiruse TODO: Port Placement db.gate.edit TODO: Edit db.gate.delete TODO: Delete db.gate.add TODO: Add db.gate.cat.asc.hdr TODO: Ascending db.gate.cat.dec.hdr TODO: Decending db.gate.cat.asc.exp -fillbegin- TODO: Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- TODO: Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir TODO: Signal Direction db.gate.cat.auto.hdr TODO: Auto db.gate.cat.multin.hdr TODO: Multi-Input db.gate.cat.singin.hdr TODO: Single-Input db.gate.cat.tran.hdr TODO: Bidirectional db.gate.cat.auto.exp -fillbegin- TODO: Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- TODO: Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- TODO: Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- TODO: Allow bidirectional (tran) signal flow. Can not be connected to switches or registers. -end- db.gate.tab.General.cap TODO: General Properties db.gate.tab.Ports.cap TODO: Port Properties db.gate.tab.Delay.cap TODO: Delay Properties db.gate.tab.CLOCK.cap TODO: Clock Properties db.gate.tab.SWITCH.cap TODO: Switch Properties db.gate.tab.DIP.cap TODO: DIP Properties db.gate.tab.TAP.cap TODO: Tran Properties db.gate.tab.RAM.cap TODO: RAM Properties db.gate.tab.ROM.cap TODO: ROM Properties db.gate.tab.BLOCK.cap TODO: Module Properties db.gate.tab.FRAME.cap TODO: Frame Properties db.gate.tab.LED.cap TODO: LED Properties db.gate.tab.AND.cap TODO: AND Properties db.gate.tab.OR.cap TODO: OR Properties db.gate.tab.XOR.cap TODO: XOR Properties db.gate.tab.MUX.cap TODO: Mux Properties db.gate.tab.DEMUX.cap TODO: Demux Properties db.gate.tab.CONCAT.cap TODO: Concat Properties db.gate.tab.COMMENT.cap TODO: Text Properties db.gate.tab.General.exp -fillbegin- TODO: View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- TODO: Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- TODO: Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.details.exp -fillbegin- TODO: Set detailed type specific properties of a gate here. -end- db.gate.tab.CLOCK.exp TODO: `db.gate.tab.details.exp db.gate.tab.SWITCH.exp TODO: `db.gate.tab.details.exp db.gate.tab.DIP.exp TODO: `db.gate.tab.details.exp db.gate.tab.TAP.exp TODO: `db.gate.tab.details.exp db.gate.tab.RAM.exp TODO: `db.gate.tab.details.exp db.gate.tab.ROM.exp TODO: `db.gate.tab.details.exp db.gate.tab.BLOCK.exp TODO: `db.gate.tab.details.exp db.gate.tab.FRAME.exp TODO: `db.gate.tab.details.exp db.gate.tab.LED.exp TODO: `db.gate.tab.details.exp db.gate.tab.AND.exp TODO: `db.gate.tab.details.exp db.gate.tab.OR.exp TODO: `db.gate.tab.details.exp db.gate.tab.XOR.exp TODO: `db.gate.tab.details.exp db.gate.tab.MUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.DEMUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.CONCAT.exp TODO: `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- TODO: Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mux.dataorder TODO: Input Ordering db.gate.mux.ord1.hdr TODO: Left-to-Right db.gate.mux.ord2.hdr TODO: Right-to-Left db.gate.mux.ord1.exp -fillbegin- TODO: Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- TODO: Order MUX inputs from right to left. -end- db.gate.demux.dataorder TODO: Output Ordering db.gate.demux.ord1.hdr TODO: Left-to-Right db.gate.demux.ord2.hdr TODO: Right-to-Left db.gate.demux.ord1.exp -fillbegin- TODO: Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- TODO: Order DEMUX outputs from right to left. -end- db.gate.mux.select TODO: Selector Style db.gate.mux.sel1.hdr TODO: Selector on Left db.gate.mux.sel2.hdr TODO: Selector on Right db.gate.mux.sel1.exp -fillbegin- TODO: Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- TODO: Place the data selector on the right side of the gate. -end- db.gate.demux.select TODO: `db.gate.mux.select db.gate.demux.sel1.hdr TODO: `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr TODO: `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp TODO: `db.gate.mux.sel1.exp db.gate.demux.sel2.exp TODO: `db.gate.mux.sel2.exp db.gate.aox.extbaruse TODO: Extender Bar Use db.gate.aox.use.hdr TODO: Extender Bars db.gate.aox.nouse.hdr TODO: No Extender Bars db.gate.aox.use.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type Tipo de LED db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Barra Grafica db.gate.led.hex.hdr 7-Segment (HEXADECIMAL) db.gate.led.dec.hdr 7-Segment (DECIMAL) db.gate.led.seg.hdr 7-Segment (Directo) db.gate.led.bit.exp -fillbegin- TODO: Single-lamp led display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- TODO: LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- TODO: Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- TODO: Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- TODO: Signal bits directly control led segments. -end- db.seq.back TODO: db.hdl.savecap TODO: Multiple Modules db.hdl.saveexp -fillbegin- TODO: The text buffer for the module you have just edited appears to contain more than one module definition. Please select one of the three actions described to the right. -end- db.hdl.autoedit TODO: Auto Edit db.hdl.split TODO: Split db.hdl.comment TODO: Comment db.hdl.cancel TODO: Cancel db.hdl.ignore TODO: Ignore db.hdl.autoeditcap TODO: Name Mismatch db.hdl.autoeditexp -fillbegin- TODO: The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- Se ha detectado un bucle de realimentacin en su circuito. Para poder realizar un análisis de los retrasos en dicho circuito deberemos, o bién romper el bucle, o marcar alguna de las puertas en el bucle como punto de un "Camino crítico". Las conexiones detectadas como bucle se listan más abajo. -end- ############################################################################## # Print dialog box # print.outto Salida a print.printer Impresora print.file Fichero print.prcmd Comando de Impresin print.prname TODO: Printer print.filename Nombre del Fichero print.epssave Salvar como Postscript Encapsulado. print.doctit Título del Documento #print.prmod Print Modules print.epcm Periodo de tiempo/cm print.estpg Páginas estimadas print.all Todo print.cur Actual print.use Usados print.sel Seleccionados print.inclib Incluye mdulos de libreria. print.papsz Tamao del Papel print.orient Orientacin print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opciones print.scale Escalar mdulos hasta completar página. print.partition Dividir mdulos grandes en varias páginas. print.incidx Incluye indice. print.incgraph Incluye gráfico de jerarquia. print.4up Imprimir cuatro mdulos pequeos por página. print.range Rango print.scaleselect TODO: Scale Selection print.fulltr Trazado completo print.parttr Trazado parcial print.start Empezar print.end Fin print.outsel TODO: Output Selection print.filesel TODO: Output to file print.printersel TODO: Output to printer print.pageset TODO: Page Setup print.modulesel TODO: Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok TODO: Print print.printtrace.cap TODO: Print Trace print.printcirc.cap TODO: Print Schematic print.printcirc.out.exp -fillbegin- TODO: Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- TODO: Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- TODO: Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- TODO: Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output TODO: Output print.tab.page TODO: Page print.tab.content TODO: Content ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 @opt.width 700 @opt.height 450 @opt.tabwidth 95 opt.general General opt.interface TODO: Interface opt.editor TODO: Editor opt.print Imprimir opt.simulate Simular opt.analysis Análisis opt.color Color opt.debug Habilitar Depuracin opt.identity TODO: Identity opt.site Nombre de la Empresa opt.username TODO: User Name opt.inst Instancias opt.mods Mdulos opt.modports Patillas de Mdulos opt.frames Marcos opt.comment Comentarios opt.hlink Hiperenlaces opt.wire Cables simples (1 Bit) opt.bus Buses opt.tools Herramientas de Puerta opt.cpath Caminos críticos opt.grid Visualizar Rejilla opt.logic1 Lgica '1' opt.logic0 Lgica '0' opt.float Flotante opt.unknown Conflicto Desconocido opt.offled LED apagado opt.onled LED encendido opt.zled LED flotante opt.restdef Restaura opciones por defecto opt.regudate Actualizar Regin opt.smoothscroll Desplazamiento Suave opt.balloon Habilitar Globos de Ayuda opt.safeSave TODO: Do safe file saving opt.saveCells TODO: Include cells in save files opt.showimage TODO: Show side-bar images in dialog boxes opt.novice Modo Novato opt.ckpoint Realizar Chequeo de Puntos opt.freq Frecuencia opt.beak Habilitar Modo Especial opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver TODO: Automatic Integrity Checking opt.showsimcmd Visualizar Cadena Simulada opt.estepsz Ajuste Tiempo (Simulacin paso a paso) opt.cstepsz Ajuste nº ciclos (Simulacin paso a paso) opt.overstep Exceder Reloj opt.sorttraces TODO: Sort traces alphabetically on scope opt.vpopupdelay TODO: Pop-Up Delay opt.initscript Guin de inicializacin opt.posedge El reloj para después de todos los flancos opt.setclock El reloj para en punto opt.delayfilepath Ficheros de Retraso opt.display TODO: Display opt.undolen TODO: Max Undo opt.keybind TODO: Key Binding Style opt.useless TODO: Enable Useless Features opt.features TODO: Basic Features opt.simbase TODO: Basic Simulator Options opt.simclock TODO: Clock Options opt.cpopts Opciones de los caminos críticos: opt.maxpath Máximo nº de caminos: opt.cpflash Presentar como relampago opt.general.fontset TODO: Font Set opt.simulator.noglitch TODO: Enable simulator glitch suppression. opt.simulator.err TODO: Error Handling opt.simulator.stopany TODO: Cancel simulation on any warnings. opt.simulator.showall TODO: Always display warnings. opt.simulator.showiferr TODO: Display warnings only if with errors. opt.simulator.ignore TODO: Ignore all warnings. opt.tool.file TODO: File opt.tool.edit TODO: Edit opt.tool.gateopt TODO: Gate Operations opt.tool.undo TODO: Undo/Redo opt.tool.zoom TODO: Zoom opt.tool.mode Modo opt.tool.module TODO: Module opt.tool.tech TODO: Technology opt.tool.simctl TODO: Simulator Control opt.tool.simaux TODO: Simulator Commands opt.tool.symmode TODO: Symbol Edit Mode opt.tool.symedit TODO: Symbol Edit Cut/Paste opt.tool.symport TODO: Symbol Edit Ports opt.tool.symshift TODO: Symbol Edit Bit Shift opt.tool.symopr TODO: Symbol Edit Bit Ops opt.editor.format TODO: Enable automatic formatting opt.editor.colorize TODO: Enable code colorization opt.editor.comments TODO: Comments opt.editor.strings TODO: Strings opt.editor.reserved TODO: Reserved Words opt.editor.color TODO: Color opt.editor.bold TODO: Bold opt.editor.italic TODO: Italic opt.editor.indentlevel TODO: Indentation per level: opt.vercheck -begin- Chequea de forma peridica si existen nuevas versiones del programa TKGATE en Internet. No habilitarla si no se dispone de una conexin permanente a la RED. -end- opt.general.cap TODO: General Options opt.editor.cap TODO: HDL Text Editor opt.interface.cap TODO: Interface Options opt.print.cap TODO: Print Options opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap TODO: Simulator Options opt.color.cap TODO: Color Options opt.debug.cap TODO: Debug Options opt.color.editwin TODO: Edit Window Colors opt.color.scopewin TODO: Scope Window Colors opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- TODO: Set personal identification and basic TkGate options on this page. The personal identification will be used on printed output. -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.toolbar TODO: Toolbar Options ############################################################################## # # Interface generator # igen.type TODO: Type igen.side TODO: Side igen.size TODO: Size igen.modname TODO: Module Name: igen.resort TODO: Re-sort igen.add TODO: Add igen.delete TODO: Delete igen.edit TODO: Edit igen.in TODO: in igen.out TODO: out igen.inout TODO: inout igen.left TODO: left igen.right TODO: right igen.top TODO: top igen.bottom TODO: bottom igen.other TODO: other igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- module.props TODO: Module Properties ipanel.plist TODO: Port List ipanel.props TODO: Interface Properties ipanel.itype.change TODO: Change Type... ipanel.itype.edsymbol TODO: Edit Symbol... ipanel.block TODO: Block ipanel.symbol TODO: Symbol ipanel.autogen TODO: Auto Generate ipanel.itype.select TODO: Interface Type ipanel.itype.selectexp -begin- TODO: Select one of the two basic inteface types for this module. -end- ipanel.block.description TODO: Block Interface ipanel.symbol.description TODO: Custom Symbol Interface ipanel.ppos.label TODO: Block resize port handling: ipanel.ppos.fix TODO: Fixed positions ipanel.ppos.scale TODO: Scaled positions ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim Mdulo libreria -> Mdulo ususario blklst.to a blklst.from TODO: From blklst.name TODO: Name blklst.new.cap TODO: Create New Module blklst.del.cap Borra Mdulo blklst.copy.cap TODO: Copy Module blklst.rename.cap TODO: Rename Module blklst.claim.cap TODO: Claim Module blklst.setroot.cap TODO: Set Root Module blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label TODO: Find Objects find.exp -fillbegin- TODO: Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.result.module TODO: Module find.result.type TODO: Type find.result.name TODO: Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options TODO: Search Options find.results TODO: Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains TODO: Contains... find.qual.begins TODO: Begins with... find.qual.ends TODO: Ends with... find.qual.matches TODO: Matches... find.dom.label TODO: Look for objects in: find.dom.gates TODO: Gates find.dom.nets TODO: Nets find.dom.text TODO: Comment Text find.search TODO: Find: find.target TODO: Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label TODO: Circuit Properties circ.ident TODO: Identification circ.filev TODO: File Version circ.file TODO: File Name circ.title TODO: Circuit Title circ.discchg Descartar cambios circ.extbar TODO: Use extender bars. circ.autostart TODO: Enable auto-start of simulation. circ.iniscript Guiones de Inicializacin circ.noscript No ha seleccionado ficheros de guin. circ.really TODO: Do you really want to remove '%s' from the list of initialization scripts. circ.editscript TODO: Edit script name: circ.scriptname TODO: Script Name circ.exp -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # Simulator # sim.breakpt Punto de ruptura sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- ############################################################################## # # Critical path messages # cp.delay Retraso del camino: cp.pathl Lista de caminos: cp.numpath Nmero de caminos: cp.recompute Recmputo ############################################################################## # Error messages # err.nopin No puedo cambiar la patilla seleccionada. err.badhex Valor hexadecimal incorrecto. Ignoro '%s'. err.gatanchor Puertas Ancladas no pueden moverse. err.protdata TODO: Can not modify contents of protected or library module. err.badfind No puedo encontrar '%s' como destino. err.badopendel No puedo borrar el mdulo abierto. err.nosrcmod No puedo encontrar '%s' como mdulo fuente. err.noerr No puedo indicarle el error. err.misserr Error informacin incompleta (did the simulator crash?) err.badinadd No puedo aadir más entradas a la puerta seleccionada. err.badoutadd No puedo aadir más salidas a la puerta seleccionada. err.badinoutadd No puedo aadir más lineas bidireccionales a la puerta err.badpinchg No puedo cambiar el tipo de patillas de la puerta. err.badnetname He borrado caracteres incorrectos en el identificador. err.netbcrename Identificador cambia a '%s' por caracteres incorrectos. err.netconfnet Identificador cambia a '%s' debido a un conflicto. err.netconfgat Identificador cambia debido a conflicto con nombre de puerta básica. err.netconfkw Identificador cambia debido a conflicto con palabra reservada. err.badconsame Unin rechazada debido a que los cables forman parte de la misma conexin. err.badconptsp Unin rechazada debido a que ambos cables son patillas de mdulos o alimentacin. err.badconbitw Unin rechazada por no poderse emparejar la anchura de los dos buses. err.badrange No se permite visualizar el rango no positivo de la seal. err.badlprcmd No puedo ejecutar el comando '%s' de impresin. err.badpsopen No puedo abrir el fichero '%s' para salida postscript. err.badid TODO: Illegal identifier '%s'. err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp Error de sintaxis en expresin para punto de ruptura. Debe ser una de las siguientes: 'conexin', '!conexin', 'conexin == valor', 'conexin != valor' err.bkpt.badnet '%s' es un nombre incorrecto de conexin. Los nombres válidos deben empezar por una letra y contener slo letras, nmeros y el signo '.'. err.bkpt.badval Error de sintaxis en el valor '%s'. Debe ser decimal o una constante en el estilo Verilog. err.bkpt.toomany Demasiados puntos de ruptura. El máximo es de %d. err.sim.badtmp No puedo salvar el fichero temporal '%s' para la simulacin ( ¿ Disco lleno ? ) err.sim.syntx Error de sintaxis en el comando '%s'. err.sim.noincl El fichero Include '%s' no se encuentra. err.sim.badedge Ilegal indicador en el pulso '%c' del comando de reloj. err.sim.nobkpt No existe punto de ruptura '%s'. err.sim.nonet No puedo encontrar la conexin '%s'. err.sim.nogate No puedo encontrar la puerta '%s'. err.sim.badbin '%s' es un carácter incorrecto en constante binaria. err.sim.notswitch La puerta '%s' no es un conmutador, dip o registro. err.sim.badcmd No reconozco el comando '%s' en el guin de simulacin. err.noteditpchg Las propiedades slo pueden cambiarse en modo Edicin. err.badeditop Operacin ilegal en el modo de Edicin. err.badopen No se puede abrir el fichero '%s'. err.badlibopen No puedo abrir la libreria '%s'. err.nomark Por favor marca con el botn izquierdo antes de seleccionar el tipo de puerta. err.badgate No conozco ese tipo de puerta. err.badportadd TODO: Can't add ports to gates of this type. err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- Hay un montn de páginas en este documento. ¿ Estás seguro de querer imprimirlo ?. -end- err.nojump -fillbegin- La posibilidad de 'saltar al mdulo' no se puede utilizar en el modo de simulacin o en el análisis de un camino crítico. Por favor navega de forma manual hasta el bloque de destino seleccionando los mdulos adecuados y utilizando la opcin '>' del teclado. Se acceder al mdulo de nivel superior en la jerarquia actuando sobre la tecla '<'. -end- err.nomod Mdulo '%s' no est definido. err.modlock !Este bloque lgico lo est visualizando! err.closeroot No puedo cerrar el mdulo principal. Utiliza la opcin Salir del men Fichero. err.sim.isrun El simulador est ejecutandose en estos momentos (Utiliza 'Ctrl-s e' para terminar). err.editonly Comando incorrecto en el modo de Simulacin. err.simonly Comando slo válido en modo Simulacin. err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel No se puede borrar lo seleccionado. err.modnotdef Mdulo '%s' no definido. err.moddef El bloque '%s' ya existe. err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop No se pueden editar las propiedades de la puerta seleccionada. err.openscript No puedo abrir el fichero de guin de simulacin '%s' err.oldversion Cargado fichero de la versin %s, obsoleta (la más reciente es la versin %s). err.futureversion Fichero salvado en la versin %s, futura versin del programa tkgate (la versin actual es %s). err.badversion Se desconoce el nmero de versin. Usada bajo su responsabilidad. err.nodrive Conexin %s no posee entrada en el mdulo %s. err.noconn Cable %s{%d} no posee conexiones - lo borramos. err.oldportact TODO: Please right click on port or module edge to add/change port. err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.backupfail TODO: Unable to create backup file '%s'. err.corruptnewsave -fillbegin- TODO: TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TODO: TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- TODO: A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- TODO: A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- El fichero %s, se crear por el programa tkgate, y no puede leerse por versiones anteriores a la actual (%s), si decide salvarlo. -end- ############################################################################## # Informational messages # msg.selwire Seleccionado cable denominado '%s'. msg.selgate Seleccionado %s denominado '%s'. msg.selblock Seleccionado bloque %s denominado '%s'. msg.modoverwt Mdulo de destino '%s' existe. ¿ Sobreescribir ? msg.foundgate Encontrada puerta denominada '%s'. msg.foundwire Encontrado cable denominado '%s'. msg.searchagn Cadena destino '%s' no encontrada. Pulsa 'find' para reiniciar la bsqueda. msg.sim.chgtoroot El modo Simulacin requiere el mdulo principal en la cima de la pila de Edicin. msg.sim.nogatemod Modo SimulacinSimulation requiere un mdulo concreto de pila. msg.setinterface Ajustar el interfaz del mdulo para '%s'. msg.needsel Por favor selecciona una instancia de mdulo. msg.wroteckpt Chequea punto a %s... msg.save Salva circuito como '%s'. msg.reallynew El circuito se ha modificado. ¿ Realmente desea perder los cambios y crear uno nuevo ? msg.reallyquit El circuito se ha modificado. ¿ Realmente desea salir ?? msg.notlib '%s' no es un mdulo de libreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Slo un loco colocaria %s%s aqu, Miles. miles.msg2 Es realmente un estpido lugar donde colocar %s%s, Miles. miles.msg3 Es un lugar horrible para colocar %s%s, Miles. miles.msg4 Miles, debes estar loco si colocas %s%s aqu. miles.msg5 Slo tu puedes colocar %s%s aqu, Miles. miles.msg6 Colocar %s%s aqu es un prueba más de que eres absolutamente estpido, Miles. miles.msg7 No sabes lo que haces, Miles, es un circuito estpido. miles.msg8a Es intil continuar, Miles. miles.msg8b Es obvio que no puedes disear un circuito ############################################################################## # Balloon Help # ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.renameexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Borra el circuito actual y, empieza a editar uno nuevo. -end- ho.open Fichero -> Circuito ho.save Circuito -> Fichero actual ho.print Circuito -> Impresora ho.library TODO: Load a library file. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- Move/Connect - Pulsando y arrastrando el ratn puedes: Ajustar la posicin de una puerta recién insertada Mover puertas y conexiones ya colocadas Conectar cables entre patillas de puertas Realizando una doble pulsacin puedes: Editar las propiedades de puertas, conexiones y puertos Editar el texto de los comentarios -end- ho.delgat -begin- borrar puerta - Usa esta herramienta para borrar las puertas. -end- ho.cutw -begin- Corta cables - Usa esta herramienta para desconectar cables. -end- ho.inv -begin- Invertir - Usa esta herramienta para insertar o borrar inversiones de las patillas de las puertas. -end- ho.bitw -begin- Anchura del Bus - Usa esta herramienta para cambiar el nmero de lineas del Bus. Introduce dicho nmero en la parte inferior derecha de la ventana. -end- ho.mod.open Abre el mdulo seleccionado. ho.mod.close Cierra el mdulo actual. ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo TODO: Undo previous action(s) ho.redo TODO: Redo undone action(s) ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- TODO: Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Encuentra caminos críticos en el circuito. -end- ho.simgo -begin- Si no estamos simulando, inicia la Simulacin y ejecuta cualquier guin de inicializacin. Si estamos simulando, se coloca en modo continuo o interactivo. -end- ho.simpause -begin- Para la simulacin en curso. -end- ho.simstep -begin- Avanza la simulacin un intervalo de tiempo fijo. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simclock -begin- Avanza la simulacin un nmero fijo de ciclos de reloj. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simstop -begin- Finaliza la simulacin en curso y vuelve al modo de Edicin. -end- ho.simbreak -begin- Edita los puntos de ruptura. La Simulacin se detendr cuando la condicin ajustada sea vuelva verdadera. -end- ho.simexec Ejecuta un guin de simulacin. ho.simload -begin- Carga la memoria con el contenido de un fichero con extensin mem. -end- ho.simdump -begin- Almacena el contenido de la memoria en un fichero con extensin mem. -end- ho.sim.break -begin- Introduce punto de ruptura. Punto de ruptura es una expresin que detiene la simulacin cuando su evaluacin resulta verdadera. Las Expresiones soportadas por el programa son del tipo operador relacional simple : "w1 == 0" o "w7 != 8". También se contempla expresiones en las que se niega la conexin: "!w2". -end- ho.f.modlist -begin- Lista todos los mulos actualmente cargados. El mdulo principal, el superior en la jerarquia se indica con el signo "+", los mdulos de libreria se visualizan entre paréntesis. -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- Lista todas las conexiones del mdulo actual. Conexiones marcadas con el signo "@" no presentan su nombre en el esquema (conexiones ocultas). Las conexiones BUS van seguidas del nmero de lineas que poseen. -end- ho.ports -begin- Lista todas las patillas del mdulo actual El signo '>' indica entrada, '<' indica salida, y '=' indica linea bidireccional. -end- ho.status.logo -begin- Estado de la Simulacin. Si se presenta una puerta de hierro estamos en el modo de Edicin. Si se presenta una puerta AND con cuatro patas estamos en modo de simulacin. Si la puerta est parada, la simulacin est detenida y si est en movimiento, la simulacin est en pleno funcionamiento. -end- ho.status.msg Los mensajes del programa se presentan aqu. ho.status.block La pila de mdulos que están siendo editados. ho.status.file -begin- Fichero actualmente editado. El signo '*' indica que el buffer se ha modificado desde la ltima vez que el fichero se salvo en disco. -end- ho.print.selall Imprimir todos los mdulos actualmente cargados en TKGate. ho.print.selcur Imprimir slo el mdulo presente en la ventana de Edicin de TKGate. ho.print.seluse -begin- Imprime todos los mdulos "en uso". Los mdulos en uso son aquellos que descienden del principal siguiendo la jerarquia arborescente. -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- Imprime slo los mdulos seleccionados más abajo. Usa la tecla CONTROL para seleccionar más de uno. -end- ho.print.modlist Selecciona los mdulos a imprimir. ho.circuit.discchg -begin- TkGate no presenta un aviso si descartas los cambios sin salvar. -end- ho.circuit.extbar -begin- TODO: Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- Cables seleccionados con el cursor pueden ajustarse a esta anchura de Bus. -end- ho.edgat.signam -begin- El nombre de la seal seleccionada en la puerta. Puedes cambiar este nombre editandolo aqu. -end- ho.edgat.port -begin- El nombre de la patilla para esta seal en esta puerta. Este campo slo puede ser editado para intancias de mdulos. -end- ho.edgat.iolab -begin- La direccin de la seal seleccionada de esta puerta. Este campo slo puede editarse en las instancias de mdulos. -end- ho.edgat.bitlab -begin- La anchura de Bus de la seal seleccionada de esta puerta. Se puede cambiar editandola aqu. -end- ho.edgat.cycle El nmero total de periodos de tiempo en un ciclo de reloj. ho.edgat.phase El punto inicial del ciclo (en %). ho.edgat.duty El % del ciclo que el reloj est en estado bajo. ho.edgat.hide -begin- Activa esta bandera para no visualizar el nombre de la puerta. -end- ho.edgat.gtype Tipo de puerta. ho.edgat.gname Nombre de esta instancia de puerta. ho.edgat.ganchor Activa esta bandera para anclar la posicin de la puerta. ho.edgat.gx Coordenada X de la puerta. ho.edgat.gy Coordenada Y de la puerta. ho.edgat.swstate -begin- El estado inicial del conmutador cuando se inicia una sesin de Simulacin. -end- ho.edgat.dipstate -begin- El estado inicial de los interruptores DIP cuando se inicia una sesin de Simulacin. -end- ho.edgat.range El rango de bits a colocar en un bus. ho.edgat.memfile -begin- El fichero con el estado inicial de esta memoria. Este fichero se lee cuando se inicia el Simulador. -end- ho.edgat.func El tipo de funcin de este mdulo. ho.edgat.frame La etiqueta del panel. ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.undolen -begin- TODO: Maximum number of undo actions to retain. -end- ho.opt.site -begin- El nombre del lugar donde tkgate se ha instalado. Se utiliza en la salida impresa o fichero postscript. -end- ho.opt.smooth -begin- Si esta opcin est habilitada, el desplazamiento se optimiza al usar copias bitmap en lugar de un completo redibujado. Puedes colocarla en off si hay problemas con su servidor. -end- ho.opt.clip -begin- Si esta opcin est habilitada, Se actualiza solo la regin actualmente expuesta del entorno de Edicin. De lo contrario se redibuja todo. -end- ho.opt.outmove -begin- Si esta opcin est habilitada, slo un recuadro que rodea a las instancias de mdulos se dibuja mientras se arrastra este. Usa esta opcin en las máquinas con micros y tarjetas gráficas lentas. -end- ho.opt.bhelp -begin- Si esta opcin est habilitada, los globos de ayuda se activan. Los globos de ayuda, como este mismo, proporciona una ayuda resumida sobre los elementos del interfaz, cuando el ratn se situa encima de ellos. -end- ho.opt.novice -begin- Si no se especifica ningn circuito en la linea de comandos. El programa TkGate presenta un tutorial para iniciarse en el manejo del programa. -end- ho.opt.debug -begin- Habilita algunas opciones de depuracin. Slo es util para desarrolladores del programa TkGate. -end- ho.opt.ckpt Habilitat puntos de chequeo para circuitos no salvados. ho.opt.ckptfreq Frecuencia de los puntos de chequeo en segundos. ho.opt.beak -begin- Habilitar todas estas opciones. Si deshabilita esta opcin, estos modos (y esta caja de diálogo) no aparece en el men opciones. Slo puede recuperarse editando el fichero .tkgate-properties. -end- ho.opt.miles -begin- Si este modo est habilitado, el programa insulta periodicamente la inteligencia del usuario. -end- ho.opt.bat -begin- Si este modo est habilitado, el programa activar el entorno para disear un computador sencillo a partir de mdulos. -end- ho.opt.trek Ayudame Scoty! ho.opt.simstep -begin- El nmero de periodos de tiempo que avanzamos si hemos activado el modo paso a paso por tiempo. -end- ho.opt.ckstep -begin- El nmero de ciclos de reloj que avanzamos si hemos activado el modo paso a paso por nº de ciclos. -end- ho.opt.ckover -begin- El nmero de periodos de tiempo después de un flanco de bajada de reloj que avanzamos si hemos activado el modo paso a paso. -end- ho.opt.vpopupdelay -begin- TODO: The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- El fichero de guin que se ejecuta de forma automática al iniciar la Simulacin. -end- ho.opt.ckall -begin- Si este modo se habilita, el comando paso a paso parar la simulacin en el flanco de subida de cualquier reloj presente en el circuito. -end- ho.opt.ckspec -begin- Si este modo est habilitado, el comando paso a paso parar la simulacin es el flanco de subida de la seal de reloj especificada. -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- La tecnología por defecto utilizada para las puertas recién creadas. Afecta al tiempo de retraso de las puertas. Para cambiar la tecnología de una puerta especifica, abrir la caja de propiedades ( doble click ) y selecciona "Retraso". -end- ho.techbut -begin- Usa retrasos para la tecnología standard de un fichero de definicin. Para aadir tecnologias personalizadas, aadirlas en la lista del men "Fichero -> Opciones -> Simulador". -end- ho.custbut -begin- Ajustar valores de retrasos personalizados para esta puerta. -end- ho.contver -begin- TODO: Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Visualizar comandos enviados entre el entorno de visualizacin (GUI) y el Simulador. -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin TODO: Zoom in ho.tool.zoomout TODO: Zoom out ho.tool.rotate TODO: Rotate selected gate(s) counter-clockwise. ho.tool.brotate TODO: Rotate selected gate(s) clockwise. ho.tool.valgn TODO: Align selected gate(s) vertically. ho.tool.halgn TODO: Align selected gate(s) horizontally. ho.tool.cut TODO: Cut selection. ho.tool.copy TODO: Copy selection. ho.tool.paste TODO: Paste from cut buffer. ho.tool.find TODO: Find gate, wire or text. tkgate-2.0-b10/locale/es/messages.bak000644 001751 001751 00000257001 11134010127 020135 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Jan 5 00:36:58 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## \language Spanish ############################################################################## # # basic strings # b.new Nuevo... b.dismiss Volver b.close Cerrar b.ok OK b.clear Borrar b.cancel Cancelar #b.open Open... #b.bitw Bit Width b.in entrada b.out salida b.inout bidireccional b.browse Visualizar... b.label Etiqueta b.find Buscar b.edit Editar... b.add Aadir... b.delete Borrar #b.deleteb Delete... b.remove TODO: Remove b.apply Aplicar b.anchor Anclar b.tech Tecnolog-Aía$)B #b.enable Enable #b.disable Disable #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editar tab.editintr TODO: Interface tab.simulate Simular tab.cpath TODO: Critical Path # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add TODO: Add... mm.delete TODO: Delete mm.edit TODO: Edit... mm.enable TODO: Enable mm.disable TODO: Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file Fichero menu.edit TODO: Edit menu.tool Herramientas menu.symbol TODO: 0:Symbol menu.simulate TODO: Simulate menu.module Mdulo menu.interface TODO: Interface menu.format Puerta menu.make Insertar menu.help Ayuda menu.file.new Nuevo menu.file.open TODO: Open... menu.file.openlib Abrir Libreria... menu.file.save Salvar menu.file.saveas TODO: Save As... menu.file.print Imprimir... menu.file.options Opciones... menu.file.quit Salir menu.file.cprop TODO: 0:Circuit Properties... menu.file.import TODO: 0:Import Image... menu.file.export TODO: 0:Export Image... menu.edit.undo TODO: Undo menu.edit.redo TODO: Redo menu.edit.cut Cortar menu.edit.copy Copiar menu.edit.paste Pegar menu.edit.overlay TODO: 0:Overlay Paste menu.edit.selall Seleccionar Todo menu.edit.find Buscar... menu.edit.algnv Situar en Columna menu.edit.algnh Situar en Fila menu.format.rot.rotate TODO: Rotate menu.edit.zoomin Zoom Acercar menu.edit.zoomout Zoom Alejar menu.edit.rshift TODO: 10:Bit Shift Right menu.edit.lshift TODO: 10:Bit Shift Left menu.edit.ushift TODO: 10:Bit Shift Up menu.edit.dshift TODO: 10:Bit Shift Down menu.edit.cwrotate TODO: 11:Bit Rotate C-W menu.edit.ccwrotate TODO: 15:Bit Rotate C-C-W menu.edit.pcwrotate TODO: 12:Port Rotate C-C-W menu.edit.pccwrotate TODO: 16:Port Rotate C-C-W menu.edit.autobold TODO: Boldify Bits menu.edit.resize TODO: Resize Bitmap menu.tool.move Mover/Conectar menu.tool.delg Borrar puerta menu.tool.cutw Cortar cable menu.tool.inv Invertir menu.tool.bitw TODO: Bit Width menu.tool.debug Depurar menu.tool.point TODO: 0:Point menu.tool.line TODO: 0:Line menu.tool.rect TODO: 0:Rectangle menu.tool.fillrect TODO: 0:Fill Rectangle menu.tool.port TODO: 0:Port menu.tool.select TODO: 0:Select Region menu.format.rot.0 Orientacin 0-Aº$)B menu.format.rot.90 Orientacin 90-Aº$)B menu.format.rot.180 Orientacin 180-Aº$)B menu.format.rot.270 Orientacin 270-Aº$)B menu.tool.tclshell TODO: 0:Tcl Shell menu.simulate.begin Empezar Simulacin menu.simulate.end Terminar Simulacin menu.simulate.addprobe TODO: Add/Delete Probe menu.simulate.run Modo continuo menu.simulate.pause Pausa menu.simulate.step Paso a paso (tiempo) menu.simulate.cycle Paso a paso (n-Aº ciclos)$)B menu.simulate.break Punto de ruptura... menu.simulate.script Ejecutar Guin... menu.simulate.load Fichero -> Memoria... menu.simulate.dump Memoria -> Fichero... menu.module.open Abrir menu.module.close TODO: Close menu.module.new TODO: New... menu.module.del TODO: Delete... menu.module.copy Copia... menu.module.rename Renombra... menu.module.claim Mdulo libreria -> Mdulo usuario... menu.module.setroot TODO: Set As Root... menu.module.prop Propiedades... menu.module.interface TODO: 0:Interface menu.module.interface.set TODO: 0:Set As Default menu.module.interface.update TODO: 1:Sync. to Default menu.module.interface.updateall TODO: 6:Sync. All to Default... menu.module.interface.edit TODO: 0:Edit... menu.module.interface.auto TODO: 5:Auto Generate... menu.format.addport TODO: 4:Add Port menu.format.ioset TODO: Set Type menu.format.anchor Anclar Seleccin menu.format.unanchor Liberar Seleccin menu.format.prop TODO: Gate Properties... menu.tool.rep R-Aéplica$)B menu.format.del TODO: Delete menu.format.settech Seleccionar Tecnolog-Aía$)B menu.help.about Acerca de... menu.help.license Licencia... menu.help.doc Documentacin... menu.help.tut Tutoriales menu.help.home TODO: 1:Home Page menu.help.example Ejemplos ############################################################################# # Scope Menu # menu.scope_file TODO: 0:File menu.scope_sim TODO: 0:Simulate menu.scope_trace TODO: 0:Trace menu.scope_help TODO: 0:Help menu.scope_file.ptrace TODO: 0:Print Trace... menu.scope_file.close TODO: 0:Close menu.scope_trace.zoomin TODO: 5:Zoom In menu.scope_trace.zoomout TODO: 5:Zoom Out menu.scope_sim.addprobe TODO: 0:Add/Delete Probe menu.scope_sim.run TODO: 0:Run menu.scope_sim.pause TODO: 0:Pause menu.scope_sim.step TODO: 0:Step Epoch(s) menu.scope_sim.cycle TODO: 5:Step Cycle menu.scope_sim.break TODO: 0:Breakpoint... menu.scope_sim.script TODO: 1:Exec. Script... menu.scope_sim.load TODO: 1:Load Memory... menu.scope_sim.dump TODO: 1:Dump Memory... menu.scope_help.about TODO: 0:About... menu.scope_help.license TODO: 0:License... menu.scope_help.doc TODO: 0:Documentation... mod.intf TODO: Interface port.parms TODO: Port Parameters port.in TODO: In port.out TODO: Out port.inout TODO: InOut ############################################################################## # # Tags for built-in gate types # gm.io Entrada/Salida gm.gate TODO: Gate gm.rgate Reduccin gm.msi MSI gm.alu ALU gm.mem Memoria gm.mod TODO: Module gm.comment Comentario gm.frame Marco gm.io.switch Conmutador gm.io.dip Interruptores DIP gm.io.ground Masa gm.io.vdd Vdd gm.io.merge TODO: Concat gm.io.clock Seal de Reloj gm.io.led LED gm.io.ledbar Barra de LEDs gm.io.ledhex 7-Seg. LED (HEXADECIMAL) gm.io.leddec 7-Seg. LED (DECIMAL) gm.io.ledseg 7-Seg. LED (Directo) gm.io.tty TTY (Terminal) gm.gate.and AND (Y) gm.gate.nand NAND (NO-Y) gm.gate.or OR (O) gm.gate.nor NOR (NO-O) gm.gate.xor XOR (O-EX) gm.gate.xnor XNOR (NO-O-EX) gm.gate.buf Buffer gm.gate.inv Inversor gm.gate.tribuf Buffer-Triestado gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and TODO: AND gm.rgate.nand TODO: NAND gm.rgate.or TODO: OR gm.rgate.nor TODO: NOR gm.rgate.xor TODO: XOR gm.rgate.xnor TODO: XNOR gm.alu.add Sumador gm.alu.mult Multiplicador gm.alu.div Divisor gm.alu.lshift DespL. Izquierda gm.alu.rshift DespL. Derecha gm.alu.arshift DespL. Arit. Derecha gm.alu.roll DespL. c-Aíclico$)B gm.mem.reg Registro gm.mem.ff Flip-Flop D gm.mem.rff TODO: Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decodificador gm.msi.14dec 1-4 Decodificador gm.msi.18dec 1-8 Decodificador gm.mod.inst Inserta mdulo gm.mod.in Entrada Mdulo gm.mod.out Salida Mdulo gm.mod.inout Bidireccional Mdulo tutorial.prev TODO: PREVIOUS tutorial.next TODO: NEXT tutorial.chapter TODO: CHAPTER LIST tutorial.reload TODO: RELOAD ############################################################################## # # Popup menus # pop.make TODO: Make pop.tool TODO: Tool pop.edit.paste TODO: Paste pop.edit.cut TODO: Cut pop.edit.copy TODO: Copy pop.port.in TODO: In pop.port.out TODO: Out pop.port.inout TODO: InOut pop.wire.addseg Aadir segmento de cable pop.wire.prop TODO: Properties... pop.wire.hidesize TODO: Hide Bit Width pop.wire.showsize TODO: Show Bit Width pop.wire.hidelabel TODO: Hide Label pop.wire.hidealllabel TODO: Hide All Labels pop.wire.clearalllabel TODO: Clear All Labels pop.wire.showlabel TODO: Show Label pop.gate.open TODO: Open pop.gate.close TODO: Close pop.gate.prop TODO: Properties... pop.gate.addport TODO: Add Port pop.gate.addin TODO: Add Input pop.gate.addout TODO: Add Output pop.gate.addinout TODO: Add BiDir pop.gate.anchor TODO: Anchor pop.gate.settech TODO: Set Technology pop.gate.delete TODO: Delete pop.gate.ioset TODO: Set Type pop.module.new TODO: New... pop.module.del TODO: Delete... pop.module.copy TODO: Copy... pop.module.rename TODO: Rename... pop.module.claim TODO: Claim... pop.module.setroot TODO: Set As Root... pop.module.prop TODO: Properties... pop.module.int TODO: Edit Interface... pop.simulate.end TODO: End Simulation pop.simulate.begin TODO: Begin Simulation pop.simulate.addprobe TODO: Add/Delete Probe pop.simulate.delprobe TODO: Delete Probe pop.simulate.run TODO: Run pop.simulate.pause TODO: Pause pop.simulate.step TODO: Step Epoch(s) pop.simulate.cycle TODO: Step Cycle pop.simulate.break TODO: Breakpoint... pop.simulate.script TODO: Exec. Script... pop.simulate.load TODO: Load Memory... pop.simulate.dump TODO: Dump Memory... pop.interface TODO: Interface pop.interface.set TODO: Set as Default pop.interface.update TODO: Sync. to Default pop.interface.updateall TODO: Sync. All to Default... pop.interface.edit TODO: Edit Interface... pop.interface.auto TODO: Auto Generate... pop.interface.replace TODO: Replace pop.igen.type TODO: Type pop.igen.side TODO: Side pop.igen.size TODO: Size pop.igen.delete TODO: Delete pop.igen.in TODO: in pop.igen.out TODO: out pop.igen.inout TODO: inout pop.igen.left TODO: left pop.igen.right TODO: right pop.igen.top TODO: top pop.igen.bottom TODO: bottom pop.igen.other TODO: other ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit Edit #symed.edit.cut Cut #symed.edit.copy Copy #symed.edit.paste Paste #symed.edit.overlay Overlay Paste #symed.edit.rclock Rotate Clockwise #symed.edit.rcclock Rotate Counter-Clockwise #symed.module Module #symed.modes Modes #symed.cutpaste Cut/Paste #symed.rotate Port Rotation #symed.zoom Zoom #symed.cancel Cancel #symed.update Update symed.tab.normal TODO: UnSelected symed.tab.select TODO: Selected symed.link TODO: Link selected to unselected # width of symbol editor tabs @symed.tab.width 125 ############################################################################## scope.emptymsg TODO: Double-click on a wire to add or delete a trace. comment.empty TODO: [Double click to add text.] ############################################################################## # Interface strings # ifile Fichero imodule Mdulo iblmodule Mdulos: iports Puertos: ibits Bits: itype TODO: Type: ############################################################################# # Module Dialog Box # db.mod.name TODO: Name db.mod.file TODO: File Name db.mod.type TODO: Type db.mod.flags TODO: Flags db.mod.dataprot TODO: Disallow editing of module definition. db.mod.intfprot TODO: Disallow all interface changes. db.mod.edprot TODO: Disallow edit mode interface changes. db.mod.props TODO: Properties db.mod.inuse.0 TODO: Module is not in use. db.mod.inuse.1 TODO: Module is in use. db.mod.lmod.0 TODO: Module has not been modified since loading. db.mod.lmod.1 TODO: Module has been modified since loading. db.mod.smod.0 TODO: Module has not been modified since saving. db.mod.smod.1 TODO: Module has been modified since saving. db.mod.islib.1 TODO: Module is part of [%s] library. db.mod.islib.0 TODO: Module is not a library module. db.mod.netlist TODO: Netlist db.mod.hdl TODO: HDL db.mod.netexpl -begin- TODO: Modules of this type are described as a network of connected components. A graphical editor is used to edit the definition. -end- db.mod.hdlexpl -begin- TODO: Modules of this type are described in text format. A text editor is used to create the module definition. -end- ############################################################################# # Error List Dialog box # db.err.caption TODO: Error List db.err.explain -fillbegin- TODO: I am unable to enter simulation mode due to errors in your circuit. Select an error message to see the error location. -end- db.err.neededit -fillbegin- TODO: You must first switch to Edit mode before navigating to warnings. -end- ############################################################################# # Net Dialog Box # db.net.name Nombre Conexin db.net.hide Nombre Oculto db.net.bits Anchura Bus db.net.type TODO: Net Type db.net.port Tipo de Patilla db.net.in entrada db.net.out salida db.net.inout bidireccional db.net.inets Conexiones ############################################################################## # # New circuit dialog box # db.newcirc.directory TODO: Directory: db.newcirc.cap TODO: New Circuit db.newcirc.exp -fillbegin- TODO: Discard the current circuit and start editing a new circuit. -end- db.newcirc.file TODO: File Name db.newcirc.topname Nombre del mdulo principal ############################################################################## # Gate dialog box # @db.gate.tabwidth *80 @db.gate.width *600 @db.gate.height *400 @db.gate.comment.width *900 @db.gate.comment.height *500 db.gate.signam Nombre de la Seal db.gate.portnam Nombre de la Patilla db.gate.iotype Tipo db.gate.bitw Anchura Bus db.gate.cyclew Anchura Ciclo db.gate.phase Fase db.gate.duty Funcin db.gate.port Patilla db.gate.bitws Bits db.gate.side TODO: Side db.gate.gtype Tipo de Puerta db.gate.gname Nombre de la Puerta db.gate.hidenam Nombre Oculto db.gate.anchor Anclada db.gate.cpbreak Ruptura del camino cr-Aítico$)B db.gate.butstate Estado del Botn db.gate.dipval Valor del conmutador db.gate.range TODO: Bit Range db.gate.memfilenam Fichero de Memoria db.gate.modname Funcin db.gate.general General db.gate.details Detalles db.gate.text TODO: Text db.gate.ports Patilla db.gate.delay Retraso db.gate.parameters TODO: Parameters db.gate.stddelay Retraso Normal db.gate.custdelay Retraso Personalizado db.gate.catdiruse TODO: Port Placement db.gate.edit TODO: Edit db.gate.delete TODO: Delete db.gate.add TODO: Add db.gate.ff.type TODO: Flip-Flop Orientation db.gate.ff.normal.hdr TODO: Normal db.gate.ff.normal.exp -fillbegin- TODO: Flip-Flop with data flowing left to right. -end- db.gate.ff.reverse.hdr TODO: Reversed db.gate.ff.reverse.exp -fillbegin- TODO: Flip-Flop with data flowing right to left. -end- db.gate.cat.asc.hdr TODO: Ascending db.gate.cat.dec.hdr TODO: Decending db.gate.cat.asc.exp -fillbegin- TODO: Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- TODO: Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir TODO: Signal Direction db.gate.cat.auto.hdr TODO: Auto db.gate.cat.multin.hdr TODO: Multi-Input db.gate.cat.singin.hdr TODO: Single-Input db.gate.cat.tran.hdr TODO: Bidirectional db.gate.cat.auto.exp -fillbegin- TODO: Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- TODO: Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- TODO: Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- TODO: Allow bidirectional (tran) signal flow. Can not be connected to switches or registers. -end- db.gate.tab.General.cap TODO: General Properties db.gate.tab.Ports.cap TODO: Port Properties db.gate.tab.Delay.cap TODO: Delay Properties db.gate.tab.Parameters.cap TODO: Module Parameters db.gate.tab.CLOCK.cap TODO: Clock Properties db.gate.tab.SWITCH.cap TODO: Switch Properties db.gate.tab.DIP.cap TODO: DIP Properties db.gate.tab.TAP.cap TODO: Tran Properties db.gate.tab.RAM.cap TODO: RAM Properties db.gate.tab.ROM.cap TODO: ROM Properties db.gate.tab.MODULE.cap TODO: Module Properties db.gate.tab.FRAME.cap TODO: Frame Properties db.gate.tab.LED.cap TODO: LED Properties db.gate.tab.AND.cap TODO: AND Properties db.gate.tab.OR.cap TODO: OR Properties db.gate.tab.XOR.cap TODO: XOR Properties db.gate.tab.MUX.cap TODO: Mux Properties db.gate.tab.DEMUX.cap TODO: Demux Properties db.gate.tab.CONCAT.cap TODO: Concat Properties db.gate.tab.COMMENT.cap TODO: Text Properties db.gate.tab.FF.cap TODO: Flip-Flop Properties db.gate.tab.General.exp -fillbegin- TODO: View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- TODO: Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- TODO: Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- TODO: Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- TODO: Set detailed type specific properties of a gate here. -end- db.gate.tab.CLOCK.exp TODO: `db.gate.tab.details.exp db.gate.tab.SWITCH.exp TODO: `db.gate.tab.details.exp db.gate.tab.DIP.exp TODO: `db.gate.tab.details.exp db.gate.tab.TAP.exp TODO: `db.gate.tab.details.exp db.gate.tab.RAM.exp TODO: `db.gate.tab.details.exp db.gate.tab.ROM.exp TODO: `db.gate.tab.details.exp db.gate.tab.MODULE.exp TODO: `db.gate.tab.details.exp db.gate.tab.FRAME.exp TODO: `db.gate.tab.details.exp db.gate.tab.LED.exp TODO: `db.gate.tab.details.exp db.gate.tab.AND.exp TODO: `db.gate.tab.details.exp db.gate.tab.OR.exp TODO: `db.gate.tab.details.exp db.gate.tab.XOR.exp TODO: `db.gate.tab.details.exp db.gate.tab.MUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.DEMUX.exp TODO: `db.gate.tab.details.exp db.gate.tab.CONCAT.exp TODO: `db.gate.tab.details.exp db.gate.tab.FF.exp TODO: `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- TODO: Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter TODO: Parameter db.gate.mparm.value TODO: Value db.gate.mparm.exampleA -begin- TODO: This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameter can be customized for each instance through this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- TODO: module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder TODO: Input Ordering db.gate.mux.ord1.hdr TODO: Left-to-Right db.gate.mux.ord2.hdr TODO: Right-to-Left db.gate.mux.ord1.exp -fillbegin- TODO: Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- TODO: Order MUX inputs from right to left. -end- db.gate.demux.dataorder TODO: Output Ordering db.gate.demux.ord1.hdr TODO: Left-to-Right db.gate.demux.ord2.hdr TODO: Right-to-Left db.gate.demux.ord1.exp -fillbegin- TODO: Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- TODO: Order DEMUX outputs from right to left. -end- db.gate.mux.select TODO: Selector Style db.gate.mux.sel1.hdr TODO: Selector on Left db.gate.mux.sel2.hdr TODO: Selector on Right db.gate.mux.sel1.exp -fillbegin- TODO: Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- TODO: Place the data selector on the right side of the gate. -end- db.gate.demux.select TODO: `db.gate.mux.select db.gate.demux.sel1.hdr TODO: `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr TODO: `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp TODO: `db.gate.mux.sel1.exp db.gate.demux.sel2.exp TODO: `db.gate.mux.sel2.exp db.gate.aox.extbaruse TODO: Extender Bar Use db.gate.aox.use.hdr TODO: Extender Bars db.gate.aox.nouse.hdr TODO: No Extender Bars db.gate.aox.use.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type Tipo de LED db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Barra Grafica db.gate.led.hex.hdr 7-Segment (HEXADECIMAL) db.gate.led.dec.hdr 7-Segment (DECIMAL) db.gate.led.seg.hdr 7-Segment (Directo) db.gate.led.bit.exp -fillbegin- TODO: Single-lamp led display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- TODO: LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- TODO: Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- TODO: Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- TODO: Signal bits directly control led segments. -end- db.seq.back TODO: db.hdl.savecap TODO: Multiple Modules db.hdl.saveexp -fillbegin- TODO: The text buffer for the module you have just edited appears to contain more than one module definition. Please select one of the three actions described to the right. -end- db.hdl.autoedit TODO: Auto Edit db.hdl.split TODO: Split db.hdl.comment TODO: Comment db.hdl.cancel TODO: Cancel db.hdl.ignore TODO: Ignore db.hdl.autoeditcap TODO: Name Mismatch db.hdl.autoeditexp -fillbegin- TODO: The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- Se ha detectado un bucle de realimentacin en su circuito. Para poder realizar un an-Aálisis de los retrasos en dicho circuito deberemos, o bién romper el bucle, o marcar alguna de las puertas en el bucle como punto de un "Camino crítico". Las conexiones detectadas como bucle se listan más abajo.$)B -end- ############################################################################## # Print dialog box # #print.outto Output to print.printer Impresora print.file Fichero print.prcmd Comando de Impresin print.prname TODO: Printer print.advanced TODO: Advanced... print.filename Nombre del Fichero print.epssave Salvar como Postscript Encapsulado. #print.doctit Document Title #print.prmod Print Modules print.epcm Periodo de tiempo/cm print.estpg P-Aáginas estimadas$)B print.all Todo print.cur Actual print.use Usados print.sel Seleccionados print.inclib Incluye mdulos de libreria. print.incunused TODO: Include unused modules. print.papsz Tamao del Papel print.orient Orientacin print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opciones print.scale Escalar mdulos hasta completar p-Aágina.$)B print.partition Dividir mdulos grandes en varias p-Aáginas.$)B print.incidx Incluye indice. print.incgraph Incluye gr-Aáfico de jerarquia.$)B print.4up Imprimir cuatro mdulos pequeos por p-Aágina.$)B print.rangeselection TODO: Range Selection print.scaleselect TODO: Scale Selection print.fulltr Trazado completo print.parttr Trazado parcial print.start Empezar print.range Rango print.linelen TODO: Line Length print.filesel TODO: Output to file print.printersel TODO: Output to printer print.defaultprinter TODO: Default Printer print.pageset TODO: Page Setup print.modulesel TODO: Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok TODO: Print print.printtrace.cap TODO: Print Trace print.printcirc.cap TODO: Print Schematic print.printcirc.out.exp -fillbegin- TODO: Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- TODO: Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- TODO: Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- TODO: Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output TODO: Output #print.tab.page Page print.tab.modules TODO: Modules print.tab.content TODO: Content print.tab.advanced TODO: Advanced # # Circuit print dialog box # @print.dlgbox.width *450 @print.dlgbox.height *450 @print.dlgbox.tabwidth *95 # # Scope print dialog box # @print.scopedlg.width *475 @print.scopedlg.height *400 @print.scopedlg.tabwidth *95 ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 700 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 95 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *170 # @opt.tree.width *135 opt.general General opt.interface TODO: Interface opt.toolbars TODO: Toolbars opt.toolbars.edit TODO: Editor opt.toolbars.sim TODO: Simulation opt.toolbars.symed TODO: Symbol Editor opt.editor TODO: Editor opt.print Imprimir opt.print.output TODO: Output opt.print.content TODO: Content opt.simulate Simular opt.simulate.basic TODO: Basic opt.simulate.tech TODO: Technology opt.simulate.error TODO: Error Handling opt.library TODO: Libraries opt.library.path TODO: Path opt.library.load TODO: Auto Loading opt.library.vpd TODO: VPD opt.analysis An-Aálisis$)B opt.color Color opt.color.edit TODO: Editor opt.color.scope TODO: Scope opt.color.hdl TODO: HDL Editor opt.html TODO: HTML opt.debug Habilitar Depuracin opt.lib.load.available TODO: Available Libraries opt.lib.load.selected TODO: Selected Libraries opt.identity TODO: Identity opt.site Nombre de la Empresa opt.username TODO: User Name opt.libname TODO: Library Name: opt.inst Instancias opt.mods Mdulos opt.modports Patillas de Mdulos opt.frames Marcos opt.comment Comentarios opt.hlink Hiperenlaces opt.wire Cables simples (1 Bit) opt.bus Buses opt.tools Herramientas de Puerta opt.background TODO: Background opt.cpath Caminos cr-Aíticos$)B opt.grid Visualizar Rejilla opt.logic1 Lgica '1' opt.logic0 Lgica '0' opt.float Flotante opt.unknown Conflicto Desconocido opt.offled LED apagado opt.onled LED encendido opt.zled LED flotante opt.restdef Restaura opciones por defecto opt.regudate Actualizar Regin opt.smoothscroll Desplazamiento Suave opt.balloon Habilitar Globos de Ayuda opt.safeSave TODO: Do safe file saving opt.saveCells TODO: Include cells in save files opt.showimage TODO: Show side-bar images in dialog boxes opt.novice Modo Novato opt.blockDropConnect TODO: Wire drop port creation opt.ckpoint.1 TODO: Do Checkpointing every opt.ckpoint.2 TODO: commands. opt.freq Frecuencia opt.beak Habilitar Modo Especial opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver TODO: Automatic Integrity Checking opt.showsimcmd Visualizar Cadena Simulada opt.estepsz Ajuste Tiempo (Simulacin paso a paso) opt.cstepsz Ajuste n-Aº ciclos (Simulacin paso a paso)$)B opt.overstep Exceder Reloj opt.sorttraces TODO: Sort traces alphabetically on scope opt.vpopupdelay TODO: Pop-Up Delay #opt.initscript Global Initialization Script opt.posedge El reloj para despu-Aés de todos los flancos$)B opt.setclock El reloj para en punto opt.delayfilepath Ficheros de Retraso opt.devfilepath TODO: VPD (Virtual Peripheral Device) File Path opt.vlibpath TODO: Verilog Library Path opt.vlibnames TODO: Base Libraries opt.display TODO: Display opt.interaction TODO: Interaction opt.input TODO: Input opt.security TODO: Security opt.undolen TODO: Max Undo opt.keybind TODO: Key Binding Style opt.useless TODO: Enable Useless Features opt.features TODO: Basic Features opt.simbase TODO: Basic Simulator Options opt.simclock TODO: Clock Options opt.cpopts Opciones de los caminos cr-Aíticos:$)B opt.maxpath M-Aáximo nº de caminos:$)B opt.cpflash Presentar como relampago opt.general.fontset TODO: Font Set opt.simulator.savetraces TODO: Save probe locations between simlation runs. opt.simulator.noglitch TODO: Enable simulator glitch suppression. opt.simulator.err TODO: Error Handling opt.simulator.stopany TODO: Cancel simulation on any warnings. opt.simulator.showall TODO: Always display warnings. opt.simulator.showiferr TODO: Display warnings only if with errors. opt.simulator.ignore TODO: Ignore all warnings. opt.tool.file TODO: File opt.tool.edit TODO: Edit opt.tool.gateopt TODO: Gate Operations opt.tool.gateprop TODO: Gate opt.tool.undo TODO: Undo/Redo opt.tool.zoom TODO: Zoom opt.tool.mode Modo opt.tool.module TODO: Module opt.tool.tech TODO: Technology opt.tool.simctl TODO: Simulator Control opt.tool.simaux TODO: Simulator Commands opt.tool.simmode TODO: Simulator Tools opt.tool.symmode TODO: Symbol Edit Mode opt.tool.symedit TODO: Symbol Edit Cut/Paste opt.tool.symport TODO: Symbol Edit Ports opt.tool.symshift TODO: Symbol Edit Bit Shift opt.tool.symopr TODO: Symbol Edit Bit Ops opt.editor.features TODO: Basic Editor Features opt.editor.format TODO: Enable automatic formatting opt.editor.colorize TODO: Enable code colorization opt.editor.comments TODO: Comments opt.editor.strings TODO: Strings opt.editor.reserved TODO: Reserved Words opt.editor.gateword TODO: Built-in Gates opt.editor.instword TODO: Module Instances opt.editor.taskword TODO: System Tasks opt.editor.color TODO: Color opt.editor.bold TODO: Bold opt.editor.italic TODO: Italic opt.editor.indentlevel TODO: Indentation per level: opt.editor.beginindent TODO: Make begin...end flush with enclosing level. opt.editor.movesel TODO: Enable drag-and-drop of selection. opt.editor.returntab TODO: Auto indent after return. opt.vercheck -begin- Chequea de forma peridica si existen nuevas versiones del programa TKGATE en Internet. No habilitarla si no se dispone de una conexin permanente a la RED. -end- opt.general.cap TODO: General Options opt.editor.cap TODO: HDL Text Editor opt.interface.cap TODO: Interface Options opt.toolbars.cap TODO: Toolbar Options opt.print.cap TODO: Print Options opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap TODO: Simulator Options opt.security.cap TODO: Security Options opt.color.cap TODO: Color Options opt.html.cap TODO: HTML/HTTP Options opt.debug.cap TODO: Debug Options opt.library.cap TODO: Library Options opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.debug.opt TODO: Debugging Options opt.color.editwin TODO: Edit Window Colors opt.color.scopewin TODO: Scope Window Colors opt.vlibadd.cap TODO: Add Library opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- TODO: Set personal identification and basic TkGate options on this page. The personal identification will be used on printed output. -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore TODO: Restore Page Defaults opt.bbar.restoreall TODO: Restore All Defaults ############################################################################## # # Interface generator # igen.port TODO: Port igen.type TODO: Type igen.side TODO: Side igen.size TODO: Size igen.bits TODO: Bits igen.modname TODO: Module Name: #igen.resort Re-sort igen.add TODO: Add igen.delete TODO: Delete igen.edit TODO: Edit igen.in TODO: in igen.out TODO: out igen.inout TODO: inout igen.left TODO: left igen.right TODO: right igen.top TODO: top igen.bottom TODO: bottom #igen.other other igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error TODO: Script Errors module.props TODO: Module Properties ipanel.plist TODO: Port List ipanel.props TODO: Interface Properties #ipanel.itype.change Change Type... #ipanel.itype.edsymbol Edit Symbol... ipanel.block TODO: Block ipanel.symbol TODO: Symbol ipanel.autogen TODO: Auto Generate ipanel.updateall TODO: Synchronize All... ipanel.itype.select TODO: Interface Type #ipanel.block.description Standard Interface #ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label TODO: Block resize port handling: ipanel.ppos.fix TODO: Fixed positions ipanel.ppos.scale TODO: Scaled positions #ipanel.ppos.grid Grid ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim Mdulo libreria -> Mdulo ususario blklst.to a blklst.from TODO: From blklst.name TODO: Name blklst.new.cap TODO: Create New Module blklst.del.cap Borra Mdulo blklst.copy.cap TODO: Copy Module blklst.rename.cap TODO: Rename Module blklst.claim.cap TODO: Claim Module blklst.setroot.cap TODO: Set Root Module blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label TODO: Find Objects find.exp -fillbegin- TODO: Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase TODO: Ignore Case find.result.module TODO: Module find.result.type TODO: Type find.result.name TODO: Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options TODO: Search Options find.results TODO: Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains TODO: Contains... find.qual.begins TODO: Begins with... find.qual.ends TODO: Ends with... find.qual.matches TODO: Matches... find.dom.label TODO: Look for objects in: find.dom.gates TODO: Gates find.dom.nets TODO: Nets find.dom.text TODO: Comment Text find.search TODO: Find: find.target TODO: Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label TODO: Circuit Properties circ.ident TODO: Identification circ.filev TODO: File Version circ.file TODO: File Name circ.title TODO: Circuit Title circ.discchg Descartar cambios circ.extbar TODO: Use extender bars. circ.autostart TODO: Enable auto-start of simulation. circ.iniscript Guiones de Inicializacin #circ.noscript No script files selected. #circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: circ.reallyupdate -fillbegin- TODO: Do you really want to update the interface of all '%s' instances? -end- @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general TODO: General circ.library TODO: Libraries circ.script TODO: Script circ.simulator TODO: Simulation circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp.general -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- circ.exp.library -fillbegin- TODO: Select libraries required by this circuit. Library requirements are saved with the circuit and will be automatically loaded the next time you load this circuit. -end- circ.exp.simulator -fillbegin- TODO: View and modifiy simulation preferences for this circuit. -end- ############################################################################## # # Library Manager # libmgr.cap TODO: Library Manager libmgr.library TODO: Library libmgr.description TODO: Description libmgr.status TODO: Status libmgr.status.load TODO: Loaded libmgr.status.unload TODO: Not Loaded libmgr.status.loadp TODO: [Loaded] libmgr.status.unloadp TODO: [Not Loaded] libmgr.exp -fillbegin- TODO: Select libraries to be loaded or unloaded. -end- libmgr.load TODO: Load libmgr.unload TODO: Unload libmgr.unloadall TODO: Unload All libmgr.notedit -fillbegin- TODO: Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab TODO: Breakpoints break.id TODO: ID break.state TODO: S break.condition TODO: Condition break.value TODO: Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay Retraso del camino: cp.pathl Lista de caminos: cp.numpath Nmero de caminos: cp.recompute Recmputo ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin No puedo cambiar la patilla seleccionada. err.badhex Valor hexadecimal incorrecto. Ignoro '%s'. err.gatanchor Puertas Ancladas no pueden moverse. err.protdata TODO: Can not modify contents of protected or library module. err.badfind No puedo encontrar '%s' como destino. err.badopendel No puedo borrar el mdulo abierto. err.nosrcmod No puedo encontrar '%s' como mdulo fuente. err.noerr No puedo indicarle el error. err.misserr Error informacin incompleta (did the simulator crash?) err.badinadd No puedo aadir m-Aás entradas a la puerta seleccionada.$)B err.badoutadd No puedo aadir m-Aás salidas a la puerta seleccionada.$)B err.badinoutadd No puedo aadir m-Aás lineas bidireccionales a la puerta$)B err.badpinchg No puedo cambiar el tipo de patillas de la puerta. err.badnetname He borrado caracteres incorrectos en el identificador. err.netbcrename Identificador cambia a '%s' por caracteres incorrectos. err.netconfnet Identificador cambia a '%s' debido a un conflicto. err.netconfgat Identificador cambia debido a conflicto con nombre de puerta b-Aásica.$)B err.netconfkw Identificador cambia debido a conflicto con palabra reservada. err.badconsame Unin rechazada debido a que los cables forman parte de la misma conexin. err.badconptsp Unin rechazada debido a que ambos cables son patillas de mdulos o alimentacin. err.badconbitw Unin rechazada por no poderse emparejar la anchura de los dos buses. err.badrange No se permite visualizar el rango no positivo de la seal. err.badlprcmd No puedo ejecutar el comando '%s' de impresin. err.badpsopen No puedo abrir el fichero '%s' para salida postscript. err.badid TODO: Illegal identifier '%s'. err.noinvgate TODO: Inverters are not allowed on gates of this type. err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp Error de sintaxis en expresin para punto de ruptura. Debe ser una de las siguientes: 'conexin', '!conexin', 'conexin == valor', 'conexin != valor' err.bkpt.badnet '%s' es un nombre incorrecto de conexin. Los nombres v-Aálidos deben empezar por una letra y contener slo letras, nmeros y el signo '.'.$)B err.bkpt.badval Error de sintaxis en el valor '%s'. Debe ser decimal o una constante en el estilo Verilog. err.bkpt.toomany Demasiados puntos de ruptura. El m-Aáximo es de %d.$)B err.sim.badtmp No puedo salvar el fichero temporal '%s' para la simulacin ( -A¿ Disco lleno ? )$)B err.sim.syntx Error de sintaxis en el comando '%s'. err.sim.noincl El fichero Include '%s' no se encuentra. err.sim.badedge Ilegal indicador en el pulso '%c' del comando de reloj. err.sim.nobkpt No existe punto de ruptura '%s'. err.sim.nonet No puedo encontrar la conexin '%s'. err.sim.nogate No puedo encontrar la puerta '%s'. err.sim.badbin '%s' es un car-Aácter incorrecto en constante binaria.$)B err.sim.notswitch La puerta '%s' no es un conmutador, dip o registro. err.sim.badcmd No reconozco el comando '%s' en el guin de simulacin. err.sim.isrun El simulador est ejecutandose en estos momentos (Utiliza 'Ctrl-s e' para terminar). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg Las propiedades slo pueden cambiarse en modo Edicin. err.badeditop Operacin ilegal en el modo de Edicin. err.badopen No se puede abrir el fichero '%s'. err.badlibopen No puedo abrir la libreria '%s'. err.nomark Por favor marca con el botn izquierdo antes de seleccionar el tipo de puerta. err.badgate No conozco ese tipo de puerta. err.badportadd TODO: Can't add ports to gates of this type. err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- Hay un montn de p-Aáginas en este documento. ¿ Estás seguro de querer imprimirlo ?.$)B -end- err.nojump -fillbegin- La posibilidad de 'saltar al mdulo' no se puede utilizar en el modo de simulacin o en el an-Aálisis de un camino crítico. Por favor navega de forma manual hasta el bloque de destino seleccionando los mdulos adecuados y utilizando la opcin '>' del teclado. Se acceder al mdulo de nivel superior en la jerarquia actuando sobre la tecla '<'.$)B -end- err.nomod Mdulo '%s' no est definido. err.modlock !Este bloque lgico lo est visualizando! err.closeroot No puedo cerrar el mdulo principal. Utiliza la opcin Salir del men Fichero. err.editonly Comando incorrecto en el modo de Simulacin. err.simonly Comando slo v-Aálido en modo Simulacin.$)B err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel No se puede borrar lo seleccionado. err.modnotdef Mdulo '%s' no definido. err.moddef El bloque '%s' ya existe. err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop No se pueden editar las propiedades de la puerta seleccionada. err.openscript No puedo abrir el fichero de guin de simulacin '%s' err.oldversion Cargado fichero de la versin %s, obsoleta (la m-Aás reciente es la versin %s).$)B err.futureversion Fichero salvado en la versin %s, futura versin del programa tkgate (la versin actual es %s). err.badversion Se desconoce el nmero de versin. Usada bajo su responsabilidad. err.nodrive Conexin %s no posee entrada en el mdulo %s. err.noconn Cable %s{%d} no posee conexiones - lo borramos. err.oldportact TODO: Please right click on port or module edge to add/change port. err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail TODO: Unable to create backup file '%s'. err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TODO: TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TODO: TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- TODO: A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- TODO: A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- El fichero %s, se crear por el programa tkgate, y no puede leerse por versiones anteriores a la actual (%s), si decide salvarlo. -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Seleccionado cable denominado '%s'. msg.selgate Seleccionado %s denominado '%s'. msg.selblock Seleccionado bloque %s denominado '%s'. msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt Mdulo de destino '%s' existe. -A¿ Sobreescribir ?$)B msg.foundgate Encontrada puerta denominada '%s'. msg.foundwire Encontrado cable denominado '%s'. msg.searchagn Cadena destino '%s' no encontrada. Pulsa 'find' para reiniciar la bsqueda. msg.sim.chgtoroot El modo Simulacin requiere el mdulo principal en la cima de la pila de Edicin. msg.sim.nogatemod Modo SimulacinSimulation requiere un mdulo concreto de pila. msg.setinterface Ajustar el interfaz del mdulo para '%s'. msg.needsel Por favor selecciona una instancia de mdulo. msg.wroteckpt Chequea punto a %s... msg.save Salva circuito como '%s'. msg.reallynew El circuito se ha modificado. -A¿ Realmente desea perder los cambios y crear uno nuevo ?$)B msg.reallyquit El circuito se ha modificado. -A¿ Realmente desea salir ??$)B msg.notlib '%s' no es un mdulo de libreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Slo un loco colocaria %s%s aqu, Miles. miles.msg2 Es realmente un estpido lugar donde colocar %s%s, Miles. miles.msg3 Es un lugar horrible para colocar %s%s, Miles. miles.msg4 Miles, debes estar loco si colocas %s%s aqu. miles.msg5 Slo tu puedes colocar %s%s aqu, Miles. miles.msg6 Colocar %s%s aqu es un prueba m-Aás de que eres absolutamente estpido, Miles.$)B miles.msg7 No sabes lo que haces, Miles, es un circuito estpido. miles.msg8a Es intil continuar, Miles. miles.msg8b Es obvio que no puedes disear un circuito ############################################################################# # # Error messages generated by verga # verga.err.OK TODO: Don't worry, be happy. verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument '%s' in task '%s'. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task '%s' must be used in a specify block. verga.err.BADSPECTASK TODO: Task '%s' can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.PATHDCOND TODO: DelaMust set through both # expression and specify block. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declaration. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declaration. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.BADPORTTYPE TODO: Invalid type declaration used on port '%s' verga.err.BADVALUE TODO: Bad numeric value '%s'. verga.err.NONEXPCTL TODO: Event control @(*) applied to non-expression. verga.err.NONSTATCTL TODO: Event control @(*) applied to non-statment. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing TODO: Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule TODO: Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname TODO: Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname TODO: Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr TODO: Move all items to selected list. ho.setsel.alll TODO: Move all items to unselected list. ho.setsel.ltor TODO: Move highlighted items to selected list. ho.setsel.rtol TODO: Move highlighted items to unselected list. ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.simmode TODO: Choose between the select and scroll tool in simulator. ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Borra el circuito actual y, empieza a editar uno nuevo. -end- ho.open Fichero -> Circuito ho.save Circuito -> Fichero actual ho.saveas TODO: Save circuit to specified file. ho.print Circuito -> Impresora ho.library TODO: Load a library file. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- Move/Connect - Pulsando y arrastrando el ratn puedes: Ajustar la posicin de una puerta reci-Aén insertada Mover puertas y conexiones ya colocadas Conectar cables entre patillas de puertas Realizando una doble pulsacin puedes: Editar las propiedades de puertas, conexiones y puertos Editar el texto de los comentarios$)B -end- ho.delgat -begin- borrar puerta - Usa esta herramienta para borrar las puertas. -end- ho.cutw -begin- Corta cables - Usa esta herramienta para desconectar cables. -end- ho.inv -begin- Invertir - Usa esta herramienta para insertar o borrar inversiones de las patillas de las puertas. -end- ho.bitw -begin- Anchura del Bus - Usa esta herramienta para cambiar el nmero de lineas del Bus. Introduce dicho nmero en la parte inferior derecha de la ventana. -end- ho.ipanel.select -begin- TODO: Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- TODO: Add a port to the module. You can also double-click after the last item to add port. -end- ho.ipanel.deleteport -begin- TODO: Delete the selected port. -end- ho.ipanel.editport -begin- TODO: Edit the selected port. You can also double-click to edit a field in a port. -end- ho.ipanel.generate -begin- TODO: Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.ipanel.updateall -begin- TODO: Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Abre el mdulo seleccionado. ho.mod.close Cierra el mdulo actual. ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo TODO: Undo previous action(s) ho.redo TODO: Redo undone action(s) ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- TODO: Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Encuentra caminos cr-Aíticos en el circuito.$)B -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Si no estamos simulando, inicia la Simulacin y ejecuta cualquier guin de inicializacin. Si estamos simulando, se coloca en modo continuo o interactivo. -end- ho.simpause -begin- Para la simulacin en curso. -end- ho.simstep -begin- Avanza la simulacin un intervalo de tiempo fijo. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simclock -begin- Avanza la simulacin un nmero fijo de ciclos de reloj. Abre el submenu Opciones de Simulacin para ajustarlo. -end- ho.simstop -begin- Finaliza la simulacin en curso y vuelve al modo de Edicin. -end- ho.simbreak -begin- Edita los puntos de ruptura. La Simulacin se detendr cuando la condicin ajustada sea vuelva verdadera. -end- ho.simexec -begin- Ejecuta un guin de simulacin. -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- Carga la memoria con el contenido de un fichero con extensin mem. -end- ho.simdump -begin- Almacena el contenido de la memoria en un fichero con extensin mem. -end- ho.f.modlist -begin- Lista todos los mulos actualmente cargados. El mdulo principal, el superior en la jerarquia se indica con el signo "+", los mdulos de libreria se visualizan entre par-Aéntesis.$)B -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- Lista todas las conexiones del mdulo actual. Conexiones marcadas con el signo "@" no presentan su nombre en el esquema (conexiones ocultas). Las conexiones BUS van seguidas del nmero de lineas que poseen. -end- ho.ports -begin- Lista todas las patillas del mdulo actual El signo '>' indica entrada, '<' indica salida, y '=' indica linea bidireccional. -end- ho.status.logo -begin- Estado de la Simulacin. Si se presenta una puerta de hierro estamos en el modo de Edicin. Si se presenta una puerta AND con cuatro patas estamos en modo de simulacin. Si la puerta est parada, la simulacin est detenida y si est en movimiento, la simulacin est en pleno funcionamiento. -end- ho.status.msg Los mensajes del programa se presentan aqu. ho.status.block La pila de mdulos que est-Aán siendo editados.$)B ho.status.file -begin- Fichero actualmente editado. El signo '*' indica que el buffer se ha modificado desde la ltima vez que el fichero se salvo en disco. -end- ho.print.selall Imprimir todos los mdulos actualmente cargados en TKGate. ho.print.selcur Imprimir slo el mdulo presente en la ventana de Edicin de TKGate. ho.print.seluse -begin- Imprime todos los mdulos "en uso". Los mdulos en uso son aquellos que descienden del principal siguiendo la jerarquia arborescente. -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- Imprime slo los mdulos seleccionados m-Aás abajo. Usa la tecla CONTROL para seleccionar más de uno.$)B -end- ho.print.modlist Selecciona los mdulos a imprimir. ho.print.timegraph -begin- TODO: The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.circuit.discchg -begin- TkGate no presenta un aviso si descartas los cambios sin salvar. -end- ho.circuit.extbar -begin- TODO: Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- Cables seleccionados con el cursor pueden ajustarse a esta anchura de Bus. -end- ho.edgat.signam -begin- El nombre de la seal seleccionada en la puerta. Puedes cambiar este nombre editandolo aqu. -end- ho.edgat.port -begin- El nombre de la patilla para esta seal en esta puerta. Este campo slo puede ser editado para intancias de mdulos. -end- ho.edgat.iolab -begin- La direccin de la seal seleccionada de esta puerta. Este campo slo puede editarse en las instancias de mdulos. -end- ho.edgat.bitlab -begin- La anchura de Bus de la seal seleccionada de esta puerta. Se puede cambiar editandola aqu. -end- ho.edgat.cycle El nmero total de periodos de tiempo en un ciclo de reloj. ho.edgat.phase El punto inicial del ciclo (en %). ho.edgat.duty El % del ciclo que el reloj est en estado bajo. ho.edgat.hide -begin- Activa esta bandera para no visualizar el nombre de la puerta. -end- ho.edgat.gtype Tipo de puerta. ho.edgat.gname Nombre de esta instancia de puerta. ho.edgat.ganchor Activa esta bandera para anclar la posicin de la puerta. ho.edgat.gx Coordenada X de la puerta. ho.edgat.gy Coordenada Y de la puerta. ho.edgat.swstate -begin- El estado inicial del conmutador cuando se inicia una sesin de Simulacin. -end- ho.edgat.dipstate -begin- El estado inicial de los interruptores DIP cuando se inicia una sesin de Simulacin. -end- ho.edgat.range El rango de bits a colocar en un bus. ho.edgat.memfile -begin- El fichero con el estado inicial de esta memoria. Este fichero se lee cuando se inicia el Simulador. -end- ho.edgat.func El tipo de funcin de este mdulo. ho.edgat.frame La etiqueta del panel. ho.traceprint -begin- TODO: Print trace logic trace. -end- ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.savetraces -begin- TODO: Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- TODO: Maximum number of undo actions to retain. -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- El nombre del lugar donde tkgate se ha instalado. Se utiliza en la salida impresa o fichero postscript. -end- ho.opt.smooth -begin- Si esta opcin est habilitada, el desplazamiento se optimiza al usar copias bitmap en lugar de un completo redibujado. Puedes colocarla en off si hay problemas con su servidor. -end- ho.opt.clip -begin- Si esta opcin est habilitada, Se actualiza solo la regin actualmente expuesta del entorno de Edicin. De lo contrario se redibuja todo. -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Si esta opcin est habilitada, slo un recuadro que rodea a las instancias de mdulos se dibuja mientras se arrastra este. Usa esta opcin en las m-Aáquinas con micros y tarjetas gráficas lentas.$)B -end- ho.opt.bhelp -begin- Si esta opcin est habilitada, los globos de ayuda se activan. Los globos de ayuda, como este mismo, proporciona una ayuda resumida sobre los elementos del interfaz, cuando el ratn se situa encima de ellos. -end- ho.opt.novice -begin- Si no se especifica ningn circuito en la linea de comandos. El programa TkGate presenta un tutorial para iniciarse en el manejo del programa. -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Habilita algunas opciones de depuracin. Slo es util para desarrolladores del programa TkGate. -end- ho.opt.ckpt Habilitat puntos de chequeo para circuitos no salvados. ho.opt.ckptfreq Frecuencia de los puntos de chequeo en segundos. ho.opt.beak -begin- Habilitar todas estas opciones. Si deshabilita esta opcin, estos modos (y esta caja de di-Aálogo) no aparece en el men opciones. Slo puede recuperarse editando el fichero .tkgate-properties.$)B -end- ho.opt.miles -begin- Si este modo est habilitado, el programa insulta periodicamente la inteligencia del usuario. -end- ho.opt.bat -begin- Si este modo est habilitado, el programa activar el entorno para disear un computador sencillo a partir de mdulos. -end- ho.opt.trek Ayudame Scoty! ho.opt.simstep -begin- El nmero de periodos de tiempo que avanzamos si hemos activado el modo paso a paso por tiempo. -end- ho.opt.ckstep -begin- El nmero de ciclos de reloj que avanzamos si hemos activado el modo paso a paso por n-Aº de ciclos.$)B -end- ho.opt.ckover -begin- El nmero de periodos de tiempo despu-Aés de un flanco de bajada de reloj que avanzamos si hemos activado el modo paso a paso.$)B -end- ho.opt.vpopupdelay -begin- TODO: The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- El fichero de guin que se ejecuta de forma autom-Aática al iniciar la Simulacin.$)B -end- ho.opt.ckall -begin- Si este modo se habilita, el comando paso a paso parar la simulacin en el flanco de subida de cualquier reloj presente en el circuito. -end- ho.opt.ckspec -begin- Si este modo est habilitado, el comando paso a paso parar la simulacin es el flanco de subida de la seal de reloj especificada. -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- La tecnolog-Aía por defecto utilizada para las puertas recién creadas. Afecta al tiempo de retraso de las puertas. Para cambiar la tecnología de una puerta especifica, abrir la caja de propiedades ( doble click ) y selecciona "Retraso".$)B -end- ho.techbut -begin- Usa retrasos para la tecnolog-Aía standard de un fichero de definicin. Para aadir tecnologias personalizadas, aadirlas en la lista del men "Fichero -> Opciones -> Simulador".$)B -end- ho.custbut -begin- Ajustar valores de retrasos personalizados para esta puerta. -end- ho.contver -begin- TODO: Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Visualizar comandos enviados entre el entorno de visualizacin (GUI) y el Simulador. -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.symed.import TODO: Import image from file. ho.symed.export TODO: Export image to file. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin TODO: Zoom in ho.tool.zoomout TODO: Zoom out ho.tool.rotate TODO: Rotate selected gate(s) counter-clockwise. ho.tool.brotate TODO: Rotate selected gate(s) clockwise. ho.tool.valgn TODO: Align selected gate(s) vertically. ho.tool.halgn TODO: Align selected gate(s) horizontally. ho.tool.cut TODO: Cut selection. ho.tool.copy TODO: Copy selection. ho.tool.paste TODO: Paste from cut buffer. ho.tool.find TODO: Find gate, wire or text. ho.tool.addport TODO: Add a port to the selected gate. ho.tool.anchor TODO: Anchor the selected gate(s). ho.tool.unanchor TODO: Unanchor the selected gate(s). ho.tool.replicate TODO: Replicate a gate. ho.tool.delete TODO: Delete the selection. tkgate-2.0-b10/locale/cy/messages000644 001751 001751 00000064700 11134010406 017407 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Feb 14 10:39:00 2002 # First pass translation by KD at www.kyfieithu.co.uk, 12-13 April 2003 \language Welsh ############################################################################## # # basic strings # b.dismiss Gwaredu b.close Cau b.ok Iawn b.clear Clirio b.cancel Diddymu b.open Agor... b.bitw Lled Did b.in i mewn b.out allan b.inout mewnallan b.browse Pori... b.label Label b.find Canfod b.edit Golygu... b.add Ychanegu... b.delete Dileu b.deleteb Dileu... b.apply Gweithredu b.anchor Angor b.tech Technoleg ############################################################################## # Menu strings # file Ffeil edit Golygu tool Erfyn simulate Efelychu module Modiwl gate Giat make Gwneud circ Cylched new Newydd open Agor... openlib Agor Rhaglengell... save Cadw saveas Cadw... print Argraffu... options Dewisiadau... quit Gadael undo Dadwneud redo Ailwneud cut Torri copy Copio paste Gludo selall Dewis Popeth find Canfod... algnv Cyfunio Fert. algnh Cyfunio Llor. zoomin Chwyddo zoomout Pellhau move Symud/Cysylltu delg Dileu Giat cutw Torri Gwifren inv Gwrth-droi bitw Lled Did debug Datnamu rot0 Cylchdroi 0 rot90 Cylchdroi 90 rot180 Cylchdroi 180 rot270 Cylchdroi 270 simbegin Dechrau Efelychiad simend Gorffen Efelychiad simadprobe Ychanegu/Dileu Holiad simrun Rhedeg simpause Seibio simstep Cam Cyfnod(au) simcycle Cam Cylchred simbreak Torbwynt... simscript Gweith. Sgript... simload Llwytho Cof... simdump Dadlwytho... modopen Agor modclose Cau modseti Gosod Rhyngwyneb modediti Golygu Rhyngwynebau... modnew Newydd... moddel Dileu... modcopy Copio... modrename Ailenwi... modclaim Honni... circprop Priodweddau Cylched... cpath Llwybr Allweddol... gataddin Ychwanegu Mewnbwn gataddout Ychwanegu Allbwn gataddinout Ychwanegu Deugyfeiriad gatiochg Newid Math gatanchor Anghori'r Dewis gatunanchor Dadanghori'r Dewis gatprop Priodweddau... gatrep Dyblygu gatdel Dileu gatsettech Gosod Technoleg gmswitch I/O gmgate Giat gmredgate Lleihad gmmsi MSI gmalu ALU gmmem Cof gmmod Modiwl gmcomment Sylwad gmframe Ffram gmxswitch Swits gmdip Swits DIP gmground Llawr gmvdd Vdd gmmerge Cyfunio Gwifren gmclock Cloc gm.led LED gm.ledbar Bar LED gm.ledhex LED 7-Rhan (HEX) gm.leddec LED 7-Rhan (DEC) gm.ledseg LED 7-Rhan (Syth) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Byffer gminv Gwrth-droydd gmtribuf Tri-Byffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Ychwanegydd gmmult Lluosydd gmdiv Rhannydd gmlshift Syfliad i'r Chwith gmrshift Syfliad i'r De gmarshift Syfliad Rhifyddol i'r De gmroll Rholio gmreg Cofrestru gmff Fflip-Fflop gmram RAM gmrom ROM gm21mux 2-1 Amlblygydd gm41mux 4-1 Amlblygydd gm81mux 8-1 Amlblygydd gm12dec 1-2 Datgodiwr gm14dec 1-4 Datgodiwr gm18dec 1-8 Datgodiwr gmmodinst Enghraifft y Modiwl gmmodin Mewnbwn y Modiwl gmmodout Allbwn y Modiwl gmmodinout Mewnallan y Modiwl addwireseg Ychwanegu Segment Gwifren help Cymorth hlpabout Ynghylch... hlplicense Trwydded... hlpdoc Dogfennaeth... hlptut Tiwtorialau hlpexample Enghraifftiau exampcomb Rhesymeg Gyfuniadol examp3bit Rhifydd 3-Did examp8bit Rhifydd 8-Did examptrff FF Safon-Transistor exampcpu Menagerie CPU tutwelcome Rhagymadrodd TkGate tutcreate Creu Cylched tutedit1 Golygu Cylched (1) tutedit2 Golygu Cylched (2) tutmods Defnyddio Modiwlau tutsim Efelychu Cylched # Scope Menu menu.sc.prtrace Argraffu Olin... menu.sc.close Cau menu.sc.trace Olinio menu.sc.zoomin Chwyddo menu.sc.zoomout Pellhau ############################################################################## # Interface strings # ifile Ffeil imodule Modiwl iblmodule Modiwlau: iports Pyrth: ibits Didau: ############################################################################# # Net Dialog Box # db.net.name Enw Rhwyd db.net.hide Cuddio'r Enw db.net.bits Lled Did db.net.port Math Porth db.net.in i mewn db.net.out allan db.net.inout mewnallan db.net.inets Rhwydau ############################################################################## # Gate dialog box # db.gate.signam Enw Signal db.gate.portnam Enw Porth db.gate.iotype Math db.gate.bitw Lled Did db.gate.cyclew Lled Cylch db.gate.phase Cydwedd db.gate.duty Dyletswydd db.gate.port Porth db.gate.bitws Didau db.gate.gtype Math Giat db.gate.gname Enw Giat db.gate.hidenam Cuddio Enw db.gate.anchor Angor db.gate.cpbreak Rhaniad Llwybr Allweddol db.gate.butstate Cyflwr Botwm db.gate.dipval Gwerth Swits db.gate.memfilenam Ffeil Cof db.gate.modname Ffwythiant db.gate.islink Gorgyswllt yw'r Testun db.gate.link Cyswllt i Ffeil db.gate.findw Chwilio am wifrau yn unig db.gate.findg Chwilio am giatiau yn unig db.gate.findwg Chwilio am wifrau a giatiau db.gate.general Cyffredinol db.gate.details Manylion db.gate.ports Porth db.gate.delay Oediad db.gate.stddelay Oediad Safonol db.gate.custdelay Oediad Dewisiadol db.gate.extbar Defnyddion bariau estynadol db.led.type Math LED db.led.bit Did db.led.bar Graff Bar db.led.hex LED 7-Rhan (HEX) db.led.dec LED 7-Rhan (DEC) db.led.seg LED 7-Rhan (Syth) cpath.cloops -begin- Darganfuwyd dolennau cyfuniadol yn eich cylched. Er mwyn gwneud dadansoddiad oedi ar y cyclched yma, bydd rhaid i chi ai torri'r ddolen, neu marcio rhai o'r giatiau yn y ddolen fel pwynt "Rhaniad Llwybr Allweddol". Mae'r rhwydau lle darganfuwyd dolen yn cael eu rhestru isod. -end- ############################################################################## # Print dialog box # print.outto Allbwn i print.printer Argraffydd print.file Ffeil print.prcmd Gorchymyn Argraffu print.filename Enw Ffeil print.epssave Cadw fel Encapsulated Postscript. print.doctit Teitl Dogfen print.prmod Modiwlau Argraffu print.epcm Cyfnodau/cm print.estpg Tudalennau (amcangyfrif) print.all Popeth print.cur Cyfredol print.use Defnyddiwyd print.sel Dewisiedig print.inclib Cynnwys Modiwlau Rhaglengell. print.papsz Maint Papur print.orient Cyfeiriadaeth print.portrait Darlun print.landscape Tirlun print.2side Argraffu ar y Ddwy Ochr print.opts Dewisiadau print.scale Graddio modiwlau mawr i ffitio ar y dudalen. print.partition Rhannu modiwlau mawr i wneud tudalennau lluosol. print.incidx Cynnwys mynegai. print.incgraph Cynnwys graff hierarchaeth. print.4up Argraffu modiwlau bach pedwar i'r dudalen. print.range Dewis Amrediad print.fulltr Oliniad Cyflawn print.parttr oliniad Rhannol print.start Dechrau print.end Diwedd ############################################################################## # # Options dialog # opt.site Enw Safle opt.inst Enghreifftiau opt.mods Modiwlau opt.modports Pyrth Modiwlau opt.frames Fframau opt.comment Sylwadau opt.hlink Gorgysylltau opt.wire Gwifrau Did-Sengl opt.bus Gwifrau Aml-Ddid opt.tools Offer Giat opt.cpath Llwybr Allweddol opt.grid Grid Sgop opt.logic1 Rhesymeg Un opt.logic0 Rhesymeg Sero opt.float Arnofio opt.unknown Anhysbys/Gwrthdaro opt.offled LED i Ffwrdd opt.onled LED Arnodd opt.zled LED Arnofio opt.restdef Adfer Rhagosodiadau opt.regudate Diweddaru Ardal opt.smoothscroll Sgrolio Llyfn opt.outmove Amlinellu Modiwlau Symud opt.balloon Alluogi Balwnau Cymorth opt.debug Alluogi Datnamu opt.novice Modd Dechreuwr opt.ckpoint Rheolfeydd opt.freq Saib opt.beak Alluogi Moddau Arbennig opt.mode Modd opt.normal Arferol opt.bat Bat opt.trek Star Trek opt.miles Milltiroedd opt.contver Cywiro Cyfanrwydd yn Awtomatig opt.showsimcmd Dangos Llif Efelychydd opt.logfile Ffeil Cofnod Efelychydd opt.estepsz Maint Cam Cyfnod opt.cstepsz Maint Cam Cylchred Cloc opt.overstep Drosgam Cloc opt.vpopupdelay Oediad Newidlen Gwerthoedd opt.initscript Sgript Ymgychwyn opt.posedge Mae'r cam cloc yn aros ar bob ymyl positif y cloc. opt.setclock Mae'r cam cloc yn aros ar gloc opt.delayfilepath Ffeiliau Oediad opt.general Cyffredinol opt.print Argraffu opt.simulate Efelychu opt.analysis Dadansoddiad opt.color Lliw opt.undolen Datwneud Uchafrif opt.cpopts Dewisiadau Llwybr Allweddol: opt.maxpath Uchafrif o Lwybrau: opt.cpflash Dangos efo Llwybr sy'n Fflachio opt.vercheck -begin- Chwilio dros y Rhyngrwyd bob hyn a hyn am fersiynau newydd o tkgate. Peidiwch a galluogi os nid oes ganddoch cyrchiad parhaol i'r Rhyngrwyd. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Modiwl Newydd blklst.delmod Dileu Modiwl blklst.frommod Copio Modiwl Oddiwrth blklst.tomod I blklst.oldname Hen Enw blklst.newname Enw Newydd blklst.claim Hawlio Modiwl ############################################################################## # # Circuit Dialog box # circ.topmod Modiwl Safon Pennaf circ.discchg Diddymu Newidiadau circ.iniscript Sgriptiau Ymgychwyn circ.noscript Ni ddewiswyd unrhyw ffeil sgript. circ.really1 Ydych wir eisiau gwaredu circ.really2 o'r rhestr sgriptiau ymgychwyn circ.extbar Defnyddio Bariau Estynnol ############################################################################## # Simulator # sim.breakpt Torbwynt ############################################################################## # # Command box # cmd.file Enw Ffeil cmd.topname Enw'r Modiwl Pennaf ############################################################################## # # Critical path messages # cp.delay Oediad Llwybr: cp.pathl Rhestr Llwybrau: cp.numpath Nifer Llwybrau: cp.recompute Ail-gyfrifiannu ############################################################################## # Error messages # err.verilog Gwallau yn y ffeil: err.nopin Methu newid pin penodol. err.badhex Gwerth hex annilys '%s' wedi ei anwybyddu. err.gatanchor Mae'r giat(iau) wedi'i anghori - ni ellir ei symud. err.libmode Gweithrediad annilys ar fodiwl rhaglengell (trosi i fodiwl areferol i'w olygu). err.badfind Methu canfod cyrchfan '%s'. err.badopendel Methu dileu modiwl ar agor. err.nosrcmod Methu canfod modiwl tarddiad '%s'. err.noerr Methu lleoli'r gwall. err.misserr Gwybodaeth gwall anghyflawn (chwalodd yr efelychydd?) err.pounimpl Gwall heb ei weithredu yn ParseOption err.badinadd Methu ychwanegu rhagor o fewnbynnau i'r giat penodol. err.badoutadd Methu ychwanegu rhagor o allbynnau i'r giat penodol. err.badinoutadd Methu ychwanegu rhagor o pinnau mewnallan i'r giat penodol. err.badpinchg Methu newid math y pin ar y giat penodol. err.badnetname Wedi dileu nodau annilys yn y dynodydd. err.netbcrename Dynodydd wedi eu ail-enwi i '%s' o achos nodau annilys. err.netconfnet Dynodydd wedi eu ail-enwi i '%s' o achos gwrthdaro. err.netconfgat Dynodydd wedi eu ail-enwi i osgoi gwrthdaro efo enw giat cyntefig. err.netconfkw Dynodydd wedi eu ail-enwi i osgoi gwrthdaro efo gair cadw. err.badconsame Gwrthodwyd y cysylltiad o achos mae gwifrau yn rhan o'r un un rhwyd. err.badconptsp Gwrthodwyd y cysylltiad o achos mae'r ddwy wifren yn byrth modiwl neu yn darparu. err.badconbitw Gwrthodwyd y cysylltiad o achos nid yw'r lledau did yn cydweddu. err.badrange Ni chaniateir amrediad di-bositif i oliniad sgop. err.badlprcmd Methu gweithredu gorchymyn argraffydd '%s'. err.badpsopen Methu agor ffeil '%s' am allbwn postscript. err.badid Dynodydd annilys '%s'. err.bkpt.badexp Gwall cystrawen yn y mynegiad torbwynt. Rhaid iddo fod yn un o: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Enw rhwyd annilys '%s'. Rhaid i enwau ddechrau efo llythyren a cynnwys dim ond llythrennau, digidau a '.'. err.bkpt.badval Gwall cystrawen yn y gwerth '%s'. Rhaid iddo fod yn gysonyn degol neu ardull verilog. err.bkpt.toomany Gormod o dorbwyntiau. Yr uchafswm yw %d. err.sim.badtmp Methu cadw ffeil dros dro '%s' am yr efelychydd (disg lawn?) err.sim.syntx Gwall cystrawen yn y gorchymyn '%s'. err.sim.noincl Methu canfod ffeil cynwysadwy '%s'. err.sim.clockbadedge Dynodydd ymyl annilys '%c' yn y gorchymyn cloc. err.sim.nobkpt Dim torbwynt '%s'. err.sim.nonet Methu canfod rhwyd '%s'. err.sim.nogate Methu canfod giat '%s'. err.sim.badbin Nod annilys mewn cysonyn deuaidd '%s'. err.sim.notswitch Nid yw giat '%s' yn swits, DIP neu cofrestr. err.sim.badcmd Gorchymyn di-adnabyddiedig '%s' yn y sgript efelychydd. err.noteditpchg Ni ellir newid priodweddau ond mewn modd golygu. err.badeditop Gweithrediad annilys mewn modd golygu rhyngwyneb. err.badopen Methu agor ffeil mewnbwn '%s'. err.badlibopen Methu agor ffeil rhaglengell '%s'. err.nomark Gosodwch nod efo botwm chwith y llygoden cyn dewis math o giat. err.badgate Math giat anhysbys. err.badmake Methu creu giat. err.badportadd Methu ychwanegu pyrth i giatiau o'r math yma. err.badportdel Methu dileu'r borth benodol. err.badportedit Methu golygu'r borth benodol. err.noport Dim porth wedi ei dewis. err.manypages -begin- Mae 'na gryn dipyn o dudalennau yn y ddogfen yma. Ydych yn sicr yr ydych eisiau ei argraffu? -end- err.nojump -begin- Ni ellir y nodwedd 'neidio-i-fodiwl' gael ei ddefnyddio mewn modd efelychu neu dadansoddiad llwybr allweddol. Symudwch a llaw i'r bloc cyrchfan gan ddewis modiwlau ac eu agor efo'r gorchymyn allweddell '>'. Cewch adael y modiwl lle rydych efo'r gorchymyn allwedell '<'. -end- err.nomod Ni ddiffinir y modiwl '%s'. err.modlock Mae'r y Bloc Rhesymeg ar glo! err.closeroot Methu cau modiwl safon fennaf. Defnyddiwch Gadael. err.sim.isrun Mae'r efelychydd yn rhedeg yn barod. (Defnyddiwch 'Ctrl-s e' i derfynu). err.sim.isnotrun Nid yw'r efelychydd yn rhedeg. (Defnyddiwch 'Ctrl-s b' i gychwyn). err.editonly Nid yw'r gorchymyn yn ddilys mewn modd efelychu. err.simonly Mae'r gorchymyn yn ddilys dim ond mewn modd efelychu. err.nodel Dim dewisiad a all ei ddileu. err.modnotdef Ni ddiffinir modiwl '%s'. err.moddef Mae'r bloc '%s' yn bodoli yn barod. err.noprop Nid oes gan y giat penodol priodweddau golygadwy. err.openscript Methu agor ffeil sgript efelychiad '%s' err.oldversion Wedi llwytho ffeil efo fersiwn anarferedig %s (%s yw'r fersiwn cyfredol). err.futureversion Wedi llwytho ffeil a chedwyd gan fersiwn tkgate dyfodol %s (mae'r fersiwn yma yn %s). err.badversion Rhif fersiwn anhysbys. Defnyddiwch ar eich menter eich hun. err.nodrive Nid oes gan rwyd %s yrrydd ym modiwl %s. err.noconn Nid oes gan y wifren %s{%d} gysylltiadau - dileuwyd. err.oldportact De-gliciwch ar ymyl y porth neu modiwl i ychwanegu/newid y porth. err.noback -begin- Creuwyd y ffeil gan tkgate %s, ac efallai nid yw'n ddarllenadwy gan fersiynau cynharach na'r fersiwn cyfredol (%s) os byddwch yn cadw. -end- ############################################################################## # Informational messages # msg.selwire Gwifren penodol o'r enw '%s'. msg.selgate %s penodol o'r enw '%s'. msg.selblock Bloc %s penodol o'r enw '%s'. msg.modoverwt Modiwl cyrchfan '%s' yn bodoli yn barod. Ysgrifennu drosto? msg.foundgate Wedi canfod giat o'r enw '%s'. msg.foundwire Wedi canfod gwifren o'r enw '%s'. msg.searchagn Methu canfod llinyn cyrchfan '%s'. Gwthio 'canfod' i ail-ddechrau'r chwiliad. msg.sim.chgtoroot Mae'r modd efelychu yn gorfod cael y modiwl gwraidd wrth pen y pentwr golygu. msg.sim.nogatemod Mae'r modd efelychu yn gorfod cael pentwr modiwl diriaethol. msg.setinterface Gosod rhyngrwyd modiwl am '%s'. msg.needsel Dewiswch enghraifft modiwl. msg.wroteckpt Rheolfa wrth %s... msg.save Wedi cadw cylched i '%s'. msg.badsave Methu agor ffeil allbwn '%s'. msg.reallynew Newidwyd y gylched. Ydych wir eisiau ei dileu a creu cylched newydd? msg.reallyquit Newidwyd y gylched. Ydych wir eisiau terfynnu? msg.notlib Nid yw modiwl '%s' yn fodiwl rhaglengell. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 'Mond twpsyn sy'n rhoi %s%s yna, Miles. miles.msg2 Dyna le wir dwp i roi %s%s, Miles. miles.msg3 Dyna le ofnadwy am %s%s, Miles. miles.msg4 Miles, roedd yn hollol dwp rhoi %s%s yna. miles.msg5 Neb ond ti fuasai'n rhoi %s%s yna, Miles. miles.msg6 Mae rhoi %s%s yna yn brawf o dy dwpdra, Miles. miles.msg7 Beth am roi'r ffidil yn y to, Miles, cylched gwirion yw hwn. miles.msg8a 'Sdim pwynt mynd ymlaen, Miles. miles.msg8b Mae'n amlwg na alli di ddylunio cylched. ############################################################################## # Balloon Help # ho.new -begin- Clirio'r cylched cyfredol, a dechrau golygu un newydd. -end- ho.open Agor cylched o ffeil. ho.save Cadw cylched i'r ffeil cyfredol. ho.print Argraffu cylched cyfredol. ho.move -begin- Symud/Cysylltu - Gan glicio a tynnu cewch: Gosod y safle i giat newydd Symud giatiau a gwifrau Cysylltu gwifrau Gan ddwbl-glicio cewch: Golygu priodweddau giat, gwifren a porth Golygu testun sylwad -end- ho.delgat -begin- Dileu Giat - Defnyddio'r efyn yma i ddileu giatiau. -end- ho.cutw -begin- Torri Gwifren - Defnyddio'r erfyn yma i dorri gwifrau. -end- ho.inv -begin- Gwrthdroi - Defnyddio'r erfyn i ychwanegu gwrthdroyddion i, neu eu gwaredu o, byrth giatiau. -end- ho.bitw -begin- Lled Did - Defnyddio'r erfyn yma i newid maint did gwifren. Mewnosodwch nifer y didau yn y blwch mewnosodi yng nghornel dde isaf y ffenest. -end- ho.modopen Agor y modiwl penodol. ho.modclose Cau y modiwl cyfredol. ho.undo Datwneud gweithrediad(au) cynt. ho.redo Ailwneud gweithrediad(au) a chafodd ei datwneud. ho.simgo -begin- Os nid oes efelychiad yn rhedeg, dechrau'r efelychiad a gweithredu unrhyw sgriptiau ymgychwyn. Os mae efelychiad yn rhedeg, rhedeg yr efelychiad yn barhaol. -end- ho.simpause -begin- Seibio efelychiad sy'n rhedeg yn barhaol. -end- ho.simstep -begin- Camu cyfnod penodol o amser. Agor y ffenest dewisiadau efelychiad er mwyn gosod maint y cam. -end- ho.simclock -begin- Camu rhif penodol o gylchredau cloc. Agor y ffenest dewisiadau efelychiad er mwyn gosod maint y cam. -end- ho.simstop -begin- Gorffen yr efelychiad cyfredol a dychwelyd i'r modd golygu. -end- ho.simbreak -begin- Golygu'r torbwyntiau cyfredol. Arhosir yr efelychiad pan bydd amod torbwynt yn dod yn wir. -end- ho.simexec Gweithredu sgript efelychiad. ho.simload -begin- Llwytho cof efo cynnwys ffeil .mem. -end- ho.simdump -begin- Dadlwytho cynnwys cof i ffeil .mem. -end- ho.sim.break -begin- Mewnosodwch torbwynt efelychiad. Mae torbwyntiau yn fynegiadau sy'n achosi'r efelychydd i seibio gweithredu pan y maent yn dod yn wir. Ar hyn o bryd, cynhelir dim ond mynegiadau syml efo gweithredydd perthynol syml fel "w1 == 0" or "w7 != 8". Cewch ddefnyddio hefyd mynegiadau fel "w8" neu "!w2" i arbrofi am werthoedd di-sero a sero yn eu tro. -end- ho.f.modlist -begin- Rhestr o bob modiwl sydd wedi ei lwytho ar hyn o bryd. Dynodir y modiwl safon pennaf gan "+" sy'n dilyn, a dangosir modiwlau rhaglengell mewn cromfachau. -end- ho.netlist -begin- Rhestr o rhwydau yn y modiwl cyfredol. Mae gan rwydau a ddynodir efo '@' enwau cudd. Dangosir rhwydau aml-did efo amrediad ar eu ol. -end- ho.ports -begin- Rhestr o byrth ar y modiwl cyfredol. Mae '>' yn dynodi mewnbwn, '<' yn dynodi allbwn, a '=' yn dynodi mewnallan. -end- ho.status.logo -begin- Dynodydd cyflwr yr efelychiad. Os dangosir y logo giat haearn, mae tkgate mewn modd golygu. Os dangosir y giat AND pedwartroed, mae tkgate mewn modd efelychu. Os mae'r giat AND yn stond, mae'r efelychiad wedi'i seibio, ac os mae'n cerdded, mae'r efelychiad yn rhedeg. -end- ho.status.msg Dangosir yma negeseuon oddiwrth TkGate. ho.status.block Pentwr y modiwlau sy'n cael eu golygu. ho.status.file -begin- Y ffeil cyfredol sy'n cael ei olygu. Mae '*' yn dynodi bod a byffer wedi ei newid ers y cadw diwethaf. -end- ho.print.selall Argraffu pob modiwl sydd wedi ei lwytho ar hyn o bryd gan TKGate. ho.print.selcur Argraffu dim ond y modiwl cyfredol yn y ffenest golygu TKGate. ho.print.seluse -begin- Argraffu pob modiwl sy'n "mewn defnydd". Modiwlau mewn defnydd yw'r rhain sy'n ddisgynnydd o'r modiwl gwraidd. -end- ho.print.selsel -begin- Argraffu dim ond y modiwlau dewisiedig isod. Defnyddiwch y fysell Control i ddewis modiwlau lluosol. -end- ho.print.modlist Dewis y modiwlau i gael eu argraffu. ho.circuit.discchg -begin- Ni fydd TkGate yn dangos rhybudd os byddwch yn taflu newidiadau heb gadw. -end- ho.circuit.extbar -begin- Bydd giatiau sylfaenol (AND, OR, XOR) yn defnyddio bariau estynnol i drin llawer o giatiau mewnbwn. -end- ho.cmd.bitw -begin- Bydd gwifrau a ddewisir efo'r cyrchwr yn cael eu gosod i'r lled did yma. -end- ho.edgat.extbar -begin- Os dewisir, bydd giatiau sylfaenol aml-fewnbwn yn defnyddio bariau estynnol fel ychwanegir mewnbynnau i'r giat. -end- ho.edgat.signam -begin- Enw'r signal penodol ar y giat penodol. Cewch newid y lled did gan ei olygu yma. -end- ho.edgat.port -begin- Cyfeiriad y porth am y signal yma ar y giat. Gellir golygu'r maes yma dim ond am enghreifftiau modiwl. -end- ho.edgat.iolab -begin- Cyfeiriad y signal penodol ar y giat penodol. Gellir golygu'r maes yma dim ond am enghreifftiau modiwl. -end- ho.edgat.bitlab -begin- Lled did y signal penodol ar y giat penodol. Cewch newid y lled did gan ei olygu yma. -end- ho.edgat.cycle Nifer cyflawn o gyfnodau mewn cylchred cloc. ho.edgat.phase Pwynt cychwyn y cylchred (y cant). ho.edgat.duty Canran y cylchred, mae'r cloc yn isel. ho.edgat.cname Enw'r rhwyd cysylltiedig. ho.edgat.cport Porth y mae'r rhwyd wedi'i cysylltu iddo. ho.edgat.ctype Math cysylltiad. ho.edgat.cbitw Lled did y rhwyd cysylltiedig. ho.edgat.cedit Golygu'r porth penodol. ho.edgat.cadd Ychanegu porth. ho.edgat.cdel Dileu'r porth penodol. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Math y giat. ho.edgat.gname Enw'r enghraifft yma o'r giat. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx Cyfesuryn X y giat. ho.edgat.gy Cyfesuryn Y y giat. ho.edgat.swstate -begin- Cyflwr cychwynnol y swits i ddefnyddio wrth ddechrau efelychiad. -end- ho.edgat.dipstate -begin- Cyflwr cychwynnol y swits DIP i ddefnyddio wrth ddechrau efelychiad. -end- ho.edgat.range Amrediad didau i dynnu oddiar fws. ho.edgat.memfile -begin- Y ffeil efo'r cyflwr cychwynnol i'r cof yma. Darllenir y ffeil yma pan ddechreuir yr efelychydd. -end- ho.edgat.func Math ffwythiant y modiwl yma. ho.edgat.frame Label y ffram. ho.opt.undolen -begin- Uchafrif gweithrediadau datwneud i gadw. -end- ho.opt.site -begin- Enw'r safle lle gosodir tkgate. Defnyddir yr enw yma ar unrhyw allbwn argraffydd neu postscript. -end- ho.opt.smooth -begin- Os alluogir y dewisiad yma, gwellheuir sgrolio gan ddefnyddio copiau didfap yn lle ail-ddangosiad cyflawn. Cewch analluogi hyn os oes problemau efo'ch gweinydd. -end- ho.opt.clip -begin- Os alluogir y dewisiad yma, defnyddir tocio i ddiweddaru dim ond y rhan agored o'r ffenest wrth ail-ddangos. Fel arall, ail-luniadir y dangosiad cyfan i bob rhan agored. -end- ho.opt.outmove -begin- Os alluogir y dewisiad yma, dangosir dim ond amlinelliad o enghreifftiau modiwl sy'n cael eu symud wrth dynnu. Defnyddiwch y nodwedd yma dim ond ar beiriannau efo dangosiadau araf. -end- ho.opt.bhelp -begin- Os alluogir y dewisiad yma, gweithredir balwnau cymorth. Mae balwnau cymorth, fel ur un yma, yn darparu cyngor ar elfennau rhyngwyneb pan mae'r llygoden drostynt. -end- ho.opt.novice -begin- Os ni phenodir unrhyw cylched arall ar y llinell gorchymyn, dangosir tiwtorial TkGate fel y cylched cychwynnol wrth ddechrau. -end- ho.opt.debug -begin- Alluogi rhai nodweddau datnamu. Mae hyn o ddefnydd i neb ond datblygwyr TkGate. -end- ho.opt.ckpt Alluogi rheolfeydd i gylchredau sy ddim wedi'w cadw. ho.opt.ckptfreq Amlder rheolfeydd mewn eiliadau. ho.opt.beak -begin- Alluogi'r nodweddau hollol di-ddefnydd yma. Os analluogir y nodwedd yma, ni ddangosir y moddau yma (neu'r blwch cywiro) yn y blwch dewisiadau. Yr unig ffordd o ail-alluogi nhw fydd golygu eich ffeil .tkgate-properties. -end- ho.opt.miles -begin- Os alluogir y modd yma, bydd TkGate yn sarhau deallusrwydd y defnyddiwr bob hyn a hyn. -end- ho.opt.bat -begin- Os alluogir y modd yma, bydd TkGate yn gosod amgylchedd i ddylunio cyfrifiadur bat. -end- ho.opt.trek Pelydra fi i fyny Scotty! ho.opt.normal Analluogi pethau hwyl. ho.opt.simstep -begin- Y nifer o gyfnodau i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.ckstep -begin- Y nifer o cylchredau cloc i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.ckover -begin- Y nifer o gyfnodau heibio'r ymyl codi o'r cloc i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.vpopupdelay -begin- Yr oediad mewn milfedau o eiliadau rhwng gwthio a gafael yn y botwm llygoden a dangos gwerth signal. Ar rai cysodau, bydd gwerthoedd oediad byr yn ymyrru efo'r gallu i adnabod clic dwbl. Os oes ganddoch y problem yma, cynyddwch y gwerth yma. Caniateir gwerthoedd rhwng 1 a 10000. -end- ho.opt.init -begin- Ffeil sgript efelychiad i weithredu yn awtomatig pan ddechreuir yr efelychiad. -end- ho.opt.ckall -begin- Os alluogir y modd yma, bydd y gorchymyn cam cloc yn seibio'r efelychiad ar yr ymyl positif o unrhyw cloc yn y cylched. -end- ho.opt.ckspec -begin- Os alluogir y modd yma, bydd y gorchymyn cam cloc yn seibio'r efelychiad dim ond ar yr ymyl positif o'r cloc penodol. -end- ho.deftech -begin- Technoleg rhagosodiedig am giatiau newydd. Er mwyn newid technoleg rhyw giat penodol, agorwch ei flwch priodweddau (clic dwbl) a dewiswch y tab "Oediad". -end- ho.techbut -begin- Defnyddio oediadau oddiwrth y ffeil diffiniad technoleg safonol. Er mwyn ychwanegu technolegau dewisiedig, ychwanegwch nhw at y rhestr yn y dewislen "Ffeil -> Dewisiadau -> Efelychu". -end- ho.custbut -begin- Gosod gwerthoedd oediad dewisiedig am y giat yma. -end- ho.contver -begin- Parhau i wirio cyfanrwydd yr adeileddau data mewnol ar ol pob gweithrediad. -end- ho.simwatch -begin- Dangos gorchymynau a anfonir rhwng y GUI a'r efelychydd. -end- ho.simlog -begin- Ysgrifennu'r gorchymynau a rhoir i'r efelychydd i ffeil cofnod. Gellir y ffeil cofnod ei ddefnyddio wedyn fel mewnbwn i'r efelychydd mewn datnamydd. -end- ho.cpathanal -begin- Canfod llwybrau allweddol mewn cylched. -end- tkgate-2.0-b10/locale/cy/messages.bak000644 001751 001751 00000064700 11134010127 020143 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Feb 14 10:39:00 2002 # First pass translation by KD at www.kyfieithu.co.uk, 12-13 April 2003 \language Welsh ############################################################################## # # basic strings # b.dismiss Gwaredu b.close Cau b.ok Iawn b.clear Clirio b.cancel Diddymu b.open Agor... b.bitw Lled Did b.in i mewn b.out allan b.inout mewnallan b.browse Pori... b.label Label b.find Canfod b.edit Golygu... b.add Ychanegu... b.delete Dileu b.deleteb Dileu... b.apply Gweithredu b.anchor Angor b.tech Technoleg ############################################################################## # Menu strings # file Ffeil edit Golygu tool Erfyn simulate Efelychu module Modiwl gate Giat make Gwneud circ Cylched new Newydd open Agor... openlib Agor Rhaglengell... save Cadw saveas Cadw... print Argraffu... options Dewisiadau... quit Gadael undo Dadwneud redo Ailwneud cut Torri copy Copio paste Gludo selall Dewis Popeth find Canfod... algnv Cyfunio Fert. algnh Cyfunio Llor. zoomin Chwyddo zoomout Pellhau move Symud/Cysylltu delg Dileu Giat cutw Torri Gwifren inv Gwrth-droi bitw Lled Did debug Datnamu rot0 Cylchdroi 0 rot90 Cylchdroi 90 rot180 Cylchdroi 180 rot270 Cylchdroi 270 simbegin Dechrau Efelychiad simend Gorffen Efelychiad simadprobe Ychanegu/Dileu Holiad simrun Rhedeg simpause Seibio simstep Cam Cyfnod(au) simcycle Cam Cylchred simbreak Torbwynt... simscript Gweith. Sgript... simload Llwytho Cof... simdump Dadlwytho... modopen Agor modclose Cau modseti Gosod Rhyngwyneb modediti Golygu Rhyngwynebau... modnew Newydd... moddel Dileu... modcopy Copio... modrename Ailenwi... modclaim Honni... circprop Priodweddau Cylched... cpath Llwybr Allweddol... gataddin Ychwanegu Mewnbwn gataddout Ychwanegu Allbwn gataddinout Ychwanegu Deugyfeiriad gatiochg Newid Math gatanchor Anghori'r Dewis gatunanchor Dadanghori'r Dewis gatprop Priodweddau... gatrep Dyblygu gatdel Dileu gatsettech Gosod Technoleg gmswitch I/O gmgate Giat gmredgate Lleihad gmmsi MSI gmalu ALU gmmem Cof gmmod Modiwl gmcomment Sylwad gmframe Ffram gmxswitch Swits gmdip Swits DIP gmground Llawr gmvdd Vdd gmmerge Cyfunio Gwifren gmclock Cloc gm.led LED gm.ledbar Bar LED gm.ledhex LED 7-Rhan (HEX) gm.leddec LED 7-Rhan (DEC) gm.ledseg LED 7-Rhan (Syth) gmtty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Byffer gminv Gwrth-droydd gmtribuf Tri-Byffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Ychwanegydd gmmult Lluosydd gmdiv Rhannydd gmlshift Syfliad i'r Chwith gmrshift Syfliad i'r De gmarshift Syfliad Rhifyddol i'r De gmroll Rholio gmreg Cofrestru gmff Fflip-Fflop gmram RAM gmrom ROM gm21mux 2-1 Amlblygydd gm41mux 4-1 Amlblygydd gm81mux 8-1 Amlblygydd gm12dec 1-2 Datgodiwr gm14dec 1-4 Datgodiwr gm18dec 1-8 Datgodiwr gmmodinst Enghraifft y Modiwl gmmodin Mewnbwn y Modiwl gmmodout Allbwn y Modiwl gmmodinout Mewnallan y Modiwl addwireseg Ychwanegu Segment Gwifren help Cymorth hlpabout Ynghylch... hlplicense Trwydded... hlpdoc Dogfennaeth... hlptut Tiwtorialau hlpexample Enghraifftiau exampcomb Rhesymeg Gyfuniadol examp3bit Rhifydd 3-Did examp8bit Rhifydd 8-Did examptrff FF Safon-Transistor exampcpu Menagerie CPU tutwelcome Rhagymadrodd TkGate tutcreate Creu Cylched tutedit1 Golygu Cylched (1) tutedit2 Golygu Cylched (2) tutmods Defnyddio Modiwlau tutsim Efelychu Cylched # Scope Menu menu.sc.prtrace Argraffu Olin... menu.sc.close Cau menu.sc.trace Olinio menu.sc.zoomin Chwyddo menu.sc.zoomout Pellhau ############################################################################## # Interface strings # ifile Ffeil imodule Modiwl iblmodule Modiwlau: iports Pyrth: ibits Didau: ############################################################################# # Net Dialog Box # db.net.name Enw Rhwyd db.net.hide Cuddio'r Enw db.net.bits Lled Did db.net.port Math Porth db.net.in i mewn db.net.out allan db.net.inout mewnallan db.net.inets Rhwydau ############################################################################## # Gate dialog box # db.gate.signam Enw Signal db.gate.portnam Enw Porth db.gate.iotype Math db.gate.bitw Lled Did db.gate.cyclew Lled Cylch db.gate.phase Cydwedd db.gate.duty Dyletswydd db.gate.port Porth db.gate.bitws Didau db.gate.gtype Math Giat db.gate.gname Enw Giat db.gate.hidenam Cuddio Enw db.gate.anchor Angor db.gate.cpbreak Rhaniad Llwybr Allweddol db.gate.butstate Cyflwr Botwm db.gate.dipval Gwerth Swits db.gate.memfilenam Ffeil Cof db.gate.modname Ffwythiant db.gate.islink Gorgyswllt yw'r Testun db.gate.link Cyswllt i Ffeil db.gate.findw Chwilio am wifrau yn unig db.gate.findg Chwilio am giatiau yn unig db.gate.findwg Chwilio am wifrau a giatiau db.gate.general Cyffredinol db.gate.details Manylion db.gate.ports Porth db.gate.delay Oediad db.gate.stddelay Oediad Safonol db.gate.custdelay Oediad Dewisiadol db.gate.extbar Defnyddion bariau estynadol db.led.type Math LED db.led.bit Did db.led.bar Graff Bar db.led.hex LED 7-Rhan (HEX) db.led.dec LED 7-Rhan (DEC) db.led.seg LED 7-Rhan (Syth) cpath.cloops -begin- Darganfuwyd dolennau cyfuniadol yn eich cylched. Er mwyn gwneud dadansoddiad oedi ar y cyclched yma, bydd rhaid i chi ai torri'r ddolen, neu marcio rhai o'r giatiau yn y ddolen fel pwynt "Rhaniad Llwybr Allweddol". Mae'r rhwydau lle darganfuwyd dolen yn cael eu rhestru isod. -end- ############################################################################## # Print dialog box # print.outto Allbwn i print.printer Argraffydd print.file Ffeil print.prcmd Gorchymyn Argraffu print.filename Enw Ffeil print.epssave Cadw fel Encapsulated Postscript. print.doctit Teitl Dogfen print.prmod Modiwlau Argraffu print.epcm Cyfnodau/cm print.estpg Tudalennau (amcangyfrif) print.all Popeth print.cur Cyfredol print.use Defnyddiwyd print.sel Dewisiedig print.inclib Cynnwys Modiwlau Rhaglengell. print.papsz Maint Papur print.orient Cyfeiriadaeth print.portrait Darlun print.landscape Tirlun print.2side Argraffu ar y Ddwy Ochr print.opts Dewisiadau print.scale Graddio modiwlau mawr i ffitio ar y dudalen. print.partition Rhannu modiwlau mawr i wneud tudalennau lluosol. print.incidx Cynnwys mynegai. print.incgraph Cynnwys graff hierarchaeth. print.4up Argraffu modiwlau bach pedwar i'r dudalen. print.range Dewis Amrediad print.fulltr Oliniad Cyflawn print.parttr oliniad Rhannol print.start Dechrau print.end Diwedd ############################################################################## # # Options dialog # opt.site Enw Safle opt.inst Enghreifftiau opt.mods Modiwlau opt.modports Pyrth Modiwlau opt.frames Fframau opt.comment Sylwadau opt.hlink Gorgysylltau opt.wire Gwifrau Did-Sengl opt.bus Gwifrau Aml-Ddid opt.tools Offer Giat opt.cpath Llwybr Allweddol opt.grid Grid Sgop opt.logic1 Rhesymeg Un opt.logic0 Rhesymeg Sero opt.float Arnofio opt.unknown Anhysbys/Gwrthdaro opt.offled LED i Ffwrdd opt.onled LED Arnodd opt.zled LED Arnofio opt.restdef Adfer Rhagosodiadau opt.regudate Diweddaru Ardal opt.smoothscroll Sgrolio Llyfn opt.outmove Amlinellu Modiwlau Symud opt.balloon Alluogi Balwnau Cymorth opt.debug Alluogi Datnamu opt.novice Modd Dechreuwr opt.ckpoint Rheolfeydd opt.freq Saib opt.beak Alluogi Moddau Arbennig opt.mode Modd opt.normal Arferol opt.bat Bat opt.trek Star Trek opt.miles Milltiroedd opt.contver Cywiro Cyfanrwydd yn Awtomatig opt.showsimcmd Dangos Llif Efelychydd opt.logfile Ffeil Cofnod Efelychydd opt.estepsz Maint Cam Cyfnod opt.cstepsz Maint Cam Cylchred Cloc opt.overstep Drosgam Cloc opt.vpopupdelay Oediad Newidlen Gwerthoedd opt.initscript Sgript Ymgychwyn opt.posedge Mae'r cam cloc yn aros ar bob ymyl positif y cloc. opt.setclock Mae'r cam cloc yn aros ar gloc opt.delayfilepath Ffeiliau Oediad opt.general Cyffredinol opt.print Argraffu opt.simulate Efelychu opt.analysis Dadansoddiad opt.color Lliw opt.undolen Datwneud Uchafrif opt.cpopts Dewisiadau Llwybr Allweddol: opt.maxpath Uchafrif o Lwybrau: opt.cpflash Dangos efo Llwybr sy'n Fflachio opt.vercheck -begin- Chwilio dros y Rhyngrwyd bob hyn a hyn am fersiynau newydd o tkgate. Peidiwch a galluogi os nid oes ganddoch cyrchiad parhaol i'r Rhyngrwyd. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Modiwl Newydd blklst.delmod Dileu Modiwl blklst.frommod Copio Modiwl Oddiwrth blklst.tomod I blklst.oldname Hen Enw blklst.newname Enw Newydd blklst.claim Hawlio Modiwl ############################################################################## # # Circuit Dialog box # circ.topmod Modiwl Safon Pennaf circ.discchg Diddymu Newidiadau circ.iniscript Sgriptiau Ymgychwyn circ.noscript Ni ddewiswyd unrhyw ffeil sgript. circ.really1 Ydych wir eisiau gwaredu circ.really2 o'r rhestr sgriptiau ymgychwyn circ.extbar Defnyddio Bariau Estynnol ############################################################################## # Simulator # sim.breakpt Torbwynt ############################################################################## # # Command box # cmd.file Enw Ffeil cmd.topname Enw'r Modiwl Pennaf ############################################################################## # # Critical path messages # cp.delay Oediad Llwybr: cp.pathl Rhestr Llwybrau: cp.numpath Nifer Llwybrau: cp.recompute Ail-gyfrifiannu ############################################################################## # Error messages # err.verilog Gwallau yn y ffeil: err.nopin Methu newid pin penodol. err.badhex Gwerth hex annilys '%s' wedi ei anwybyddu. err.gatanchor Mae'r giat(iau) wedi'i anghori - ni ellir ei symud. err.libmode Gweithrediad annilys ar fodiwl rhaglengell (trosi i fodiwl areferol i'w olygu). err.badfind Methu canfod cyrchfan '%s'. err.badopendel Methu dileu modiwl ar agor. err.nosrcmod Methu canfod modiwl tarddiad '%s'. err.noerr Methu lleoli'r gwall. err.misserr Gwybodaeth gwall anghyflawn (chwalodd yr efelychydd?) err.pounimpl Gwall heb ei weithredu yn ParseOption err.badinadd Methu ychwanegu rhagor o fewnbynnau i'r giat penodol. err.badoutadd Methu ychwanegu rhagor o allbynnau i'r giat penodol. err.badinoutadd Methu ychwanegu rhagor o pinnau mewnallan i'r giat penodol. err.badpinchg Methu newid math y pin ar y giat penodol. err.badnetname Wedi dileu nodau annilys yn y dynodydd. err.netbcrename Dynodydd wedi eu ail-enwi i '%s' o achos nodau annilys. err.netconfnet Dynodydd wedi eu ail-enwi i '%s' o achos gwrthdaro. err.netconfgat Dynodydd wedi eu ail-enwi i osgoi gwrthdaro efo enw giat cyntefig. err.netconfkw Dynodydd wedi eu ail-enwi i osgoi gwrthdaro efo gair cadw. err.badconsame Gwrthodwyd y cysylltiad o achos mae gwifrau yn rhan o'r un un rhwyd. err.badconptsp Gwrthodwyd y cysylltiad o achos mae'r ddwy wifren yn byrth modiwl neu yn darparu. err.badconbitw Gwrthodwyd y cysylltiad o achos nid yw'r lledau did yn cydweddu. err.badrange Ni chaniateir amrediad di-bositif i oliniad sgop. err.badlprcmd Methu gweithredu gorchymyn argraffydd '%s'. err.badpsopen Methu agor ffeil '%s' am allbwn postscript. err.badid Dynodydd annilys '%s'. err.bkpt.badexp Gwall cystrawen yn y mynegiad torbwynt. Rhaid iddo fod yn un o: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Enw rhwyd annilys '%s'. Rhaid i enwau ddechrau efo llythyren a cynnwys dim ond llythrennau, digidau a '.'. err.bkpt.badval Gwall cystrawen yn y gwerth '%s'. Rhaid iddo fod yn gysonyn degol neu ardull verilog. err.bkpt.toomany Gormod o dorbwyntiau. Yr uchafswm yw %d. err.sim.badtmp Methu cadw ffeil dros dro '%s' am yr efelychydd (disg lawn?) err.sim.syntx Gwall cystrawen yn y gorchymyn '%s'. err.sim.noincl Methu canfod ffeil cynwysadwy '%s'. err.sim.clockbadedge Dynodydd ymyl annilys '%c' yn y gorchymyn cloc. err.sim.nobkpt Dim torbwynt '%s'. err.sim.nonet Methu canfod rhwyd '%s'. err.sim.nogate Methu canfod giat '%s'. err.sim.badbin Nod annilys mewn cysonyn deuaidd '%s'. err.sim.notswitch Nid yw giat '%s' yn swits, DIP neu cofrestr. err.sim.badcmd Gorchymyn di-adnabyddiedig '%s' yn y sgript efelychydd. err.noteditpchg Ni ellir newid priodweddau ond mewn modd golygu. err.badeditop Gweithrediad annilys mewn modd golygu rhyngwyneb. err.badopen Methu agor ffeil mewnbwn '%s'. err.badlibopen Methu agor ffeil rhaglengell '%s'. err.nomark Gosodwch nod efo botwm chwith y llygoden cyn dewis math o giat. err.badgate Math giat anhysbys. err.badmake Methu creu giat. err.badportadd Methu ychwanegu pyrth i giatiau o'r math yma. err.badportdel Methu dileu'r borth benodol. err.badportedit Methu golygu'r borth benodol. err.noport Dim porth wedi ei dewis. err.manypages -begin- Mae 'na gryn dipyn o dudalennau yn y ddogfen yma. Ydych yn sicr yr ydych eisiau ei argraffu? -end- err.nojump -begin- Ni ellir y nodwedd 'neidio-i-fodiwl' gael ei ddefnyddio mewn modd efelychu neu dadansoddiad llwybr allweddol. Symudwch a llaw i'r bloc cyrchfan gan ddewis modiwlau ac eu agor efo'r gorchymyn allweddell '>'. Cewch adael y modiwl lle rydych efo'r gorchymyn allwedell '<'. -end- err.nomod Ni ddiffinir y modiwl '%s'. err.modlock Mae'r y Bloc Rhesymeg ar glo! err.closeroot Methu cau modiwl safon fennaf. Defnyddiwch Gadael. err.sim.isrun Mae'r efelychydd yn rhedeg yn barod. (Defnyddiwch 'Ctrl-s e' i derfynu). err.sim.isnotrun Nid yw'r efelychydd yn rhedeg. (Defnyddiwch 'Ctrl-s b' i gychwyn). err.editonly Nid yw'r gorchymyn yn ddilys mewn modd efelychu. err.simonly Mae'r gorchymyn yn ddilys dim ond mewn modd efelychu. err.nodel Dim dewisiad a all ei ddileu. err.modnotdef Ni ddiffinir modiwl '%s'. err.moddef Mae'r bloc '%s' yn bodoli yn barod. err.noprop Nid oes gan y giat penodol priodweddau golygadwy. err.openscript Methu agor ffeil sgript efelychiad '%s' err.oldversion Wedi llwytho ffeil efo fersiwn anarferedig %s (%s yw'r fersiwn cyfredol). err.futureversion Wedi llwytho ffeil a chedwyd gan fersiwn tkgate dyfodol %s (mae'r fersiwn yma yn %s). err.badversion Rhif fersiwn anhysbys. Defnyddiwch ar eich menter eich hun. err.nodrive Nid oes gan rwyd %s yrrydd ym modiwl %s. err.noconn Nid oes gan y wifren %s{%d} gysylltiadau - dileuwyd. err.oldportact De-gliciwch ar ymyl y porth neu modiwl i ychwanegu/newid y porth. err.noback -begin- Creuwyd y ffeil gan tkgate %s, ac efallai nid yw'n ddarllenadwy gan fersiynau cynharach na'r fersiwn cyfredol (%s) os byddwch yn cadw. -end- ############################################################################## # Informational messages # msg.selwire Gwifren penodol o'r enw '%s'. msg.selgate %s penodol o'r enw '%s'. msg.selblock Bloc %s penodol o'r enw '%s'. msg.modoverwt Modiwl cyrchfan '%s' yn bodoli yn barod. Ysgrifennu drosto? msg.foundgate Wedi canfod giat o'r enw '%s'. msg.foundwire Wedi canfod gwifren o'r enw '%s'. msg.searchagn Methu canfod llinyn cyrchfan '%s'. Gwthio 'canfod' i ail-ddechrau'r chwiliad. msg.sim.chgtoroot Mae'r modd efelychu yn gorfod cael y modiwl gwraidd wrth pen y pentwr golygu. msg.sim.nogatemod Mae'r modd efelychu yn gorfod cael pentwr modiwl diriaethol. msg.setinterface Gosod rhyngrwyd modiwl am '%s'. msg.needsel Dewiswch enghraifft modiwl. msg.wroteckpt Rheolfa wrth %s... msg.save Wedi cadw cylched i '%s'. msg.badsave Methu agor ffeil allbwn '%s'. msg.reallynew Newidwyd y gylched. Ydych wir eisiau ei dileu a creu cylched newydd? msg.reallyquit Newidwyd y gylched. Ydych wir eisiau terfynnu? msg.notlib Nid yw modiwl '%s' yn fodiwl rhaglengell. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 'Mond twpsyn sy'n rhoi %s%s yna, Miles. miles.msg2 Dyna le wir dwp i roi %s%s, Miles. miles.msg3 Dyna le ofnadwy am %s%s, Miles. miles.msg4 Miles, roedd yn hollol dwp rhoi %s%s yna. miles.msg5 Neb ond ti fuasai'n rhoi %s%s yna, Miles. miles.msg6 Mae rhoi %s%s yna yn brawf o dy dwpdra, Miles. miles.msg7 Beth am roi'r ffidil yn y to, Miles, cylched gwirion yw hwn. miles.msg8a 'Sdim pwynt mynd ymlaen, Miles. miles.msg8b Mae'n amlwg na alli di ddylunio cylched. ############################################################################## # Balloon Help # ho.new -begin- Clirio'r cylched cyfredol, a dechrau golygu un newydd. -end- ho.open Agor cylched o ffeil. ho.save Cadw cylched i'r ffeil cyfredol. ho.print Argraffu cylched cyfredol. ho.move -begin- Symud/Cysylltu - Gan glicio a tynnu cewch: Gosod y safle i giat newydd Symud giatiau a gwifrau Cysylltu gwifrau Gan ddwbl-glicio cewch: Golygu priodweddau giat, gwifren a porth Golygu testun sylwad -end- ho.delgat -begin- Dileu Giat - Defnyddio'r efyn yma i ddileu giatiau. -end- ho.cutw -begin- Torri Gwifren - Defnyddio'r erfyn yma i dorri gwifrau. -end- ho.inv -begin- Gwrthdroi - Defnyddio'r erfyn i ychwanegu gwrthdroyddion i, neu eu gwaredu o, byrth giatiau. -end- ho.bitw -begin- Lled Did - Defnyddio'r erfyn yma i newid maint did gwifren. Mewnosodwch nifer y didau yn y blwch mewnosodi yng nghornel dde isaf y ffenest. -end- ho.modopen Agor y modiwl penodol. ho.modclose Cau y modiwl cyfredol. ho.undo Datwneud gweithrediad(au) cynt. ho.redo Ailwneud gweithrediad(au) a chafodd ei datwneud. ho.simgo -begin- Os nid oes efelychiad yn rhedeg, dechrau'r efelychiad a gweithredu unrhyw sgriptiau ymgychwyn. Os mae efelychiad yn rhedeg, rhedeg yr efelychiad yn barhaol. -end- ho.simpause -begin- Seibio efelychiad sy'n rhedeg yn barhaol. -end- ho.simstep -begin- Camu cyfnod penodol o amser. Agor y ffenest dewisiadau efelychiad er mwyn gosod maint y cam. -end- ho.simclock -begin- Camu rhif penodol o gylchredau cloc. Agor y ffenest dewisiadau efelychiad er mwyn gosod maint y cam. -end- ho.simstop -begin- Gorffen yr efelychiad cyfredol a dychwelyd i'r modd golygu. -end- ho.simbreak -begin- Golygu'r torbwyntiau cyfredol. Arhosir yr efelychiad pan bydd amod torbwynt yn dod yn wir. -end- ho.simexec Gweithredu sgript efelychiad. ho.simload -begin- Llwytho cof efo cynnwys ffeil .mem. -end- ho.simdump -begin- Dadlwytho cynnwys cof i ffeil .mem. -end- ho.sim.break -begin- Mewnosodwch torbwynt efelychiad. Mae torbwyntiau yn fynegiadau sy'n achosi'r efelychydd i seibio gweithredu pan y maent yn dod yn wir. Ar hyn o bryd, cynhelir dim ond mynegiadau syml efo gweithredydd perthynol syml fel "w1 == 0" or "w7 != 8". Cewch ddefnyddio hefyd mynegiadau fel "w8" neu "!w2" i arbrofi am werthoedd di-sero a sero yn eu tro. -end- ho.f.modlist -begin- Rhestr o bob modiwl sydd wedi ei lwytho ar hyn o bryd. Dynodir y modiwl safon pennaf gan "+" sy'n dilyn, a dangosir modiwlau rhaglengell mewn cromfachau. -end- ho.netlist -begin- Rhestr o rhwydau yn y modiwl cyfredol. Mae gan rwydau a ddynodir efo '@' enwau cudd. Dangosir rhwydau aml-did efo amrediad ar eu ol. -end- ho.ports -begin- Rhestr o byrth ar y modiwl cyfredol. Mae '>' yn dynodi mewnbwn, '<' yn dynodi allbwn, a '=' yn dynodi mewnallan. -end- ho.status.logo -begin- Dynodydd cyflwr yr efelychiad. Os dangosir y logo giat haearn, mae tkgate mewn modd golygu. Os dangosir y giat AND pedwartroed, mae tkgate mewn modd efelychu. Os mae'r giat AND yn stond, mae'r efelychiad wedi'i seibio, ac os mae'n cerdded, mae'r efelychiad yn rhedeg. -end- ho.status.msg Dangosir yma negeseuon oddiwrth TkGate. ho.status.block Pentwr y modiwlau sy'n cael eu golygu. ho.status.file -begin- Y ffeil cyfredol sy'n cael ei olygu. Mae '*' yn dynodi bod a byffer wedi ei newid ers y cadw diwethaf. -end- ho.print.selall Argraffu pob modiwl sydd wedi ei lwytho ar hyn o bryd gan TKGate. ho.print.selcur Argraffu dim ond y modiwl cyfredol yn y ffenest golygu TKGate. ho.print.seluse -begin- Argraffu pob modiwl sy'n "mewn defnydd". Modiwlau mewn defnydd yw'r rhain sy'n ddisgynnydd o'r modiwl gwraidd. -end- ho.print.selsel -begin- Argraffu dim ond y modiwlau dewisiedig isod. Defnyddiwch y fysell Control i ddewis modiwlau lluosol. -end- ho.print.modlist Dewis y modiwlau i gael eu argraffu. ho.circuit.discchg -begin- Ni fydd TkGate yn dangos rhybudd os byddwch yn taflu newidiadau heb gadw. -end- ho.circuit.extbar -begin- Bydd giatiau sylfaenol (AND, OR, XOR) yn defnyddio bariau estynnol i drin llawer o giatiau mewnbwn. -end- ho.cmd.bitw -begin- Bydd gwifrau a ddewisir efo'r cyrchwr yn cael eu gosod i'r lled did yma. -end- ho.edgat.extbar -begin- Os dewisir, bydd giatiau sylfaenol aml-fewnbwn yn defnyddio bariau estynnol fel ychwanegir mewnbynnau i'r giat. -end- ho.edgat.signam -begin- Enw'r signal penodol ar y giat penodol. Cewch newid y lled did gan ei olygu yma. -end- ho.edgat.port -begin- Cyfeiriad y porth am y signal yma ar y giat. Gellir golygu'r maes yma dim ond am enghreifftiau modiwl. -end- ho.edgat.iolab -begin- Cyfeiriad y signal penodol ar y giat penodol. Gellir golygu'r maes yma dim ond am enghreifftiau modiwl. -end- ho.edgat.bitlab -begin- Lled did y signal penodol ar y giat penodol. Cewch newid y lled did gan ei olygu yma. -end- ho.edgat.cycle Nifer cyflawn o gyfnodau mewn cylchred cloc. ho.edgat.phase Pwynt cychwyn y cylchred (y cant). ho.edgat.duty Canran y cylchred, mae'r cloc yn isel. ho.edgat.cname Enw'r rhwyd cysylltiedig. ho.edgat.cport Porth y mae'r rhwyd wedi'i cysylltu iddo. ho.edgat.ctype Math cysylltiad. ho.edgat.cbitw Lled did y rhwyd cysylltiedig. ho.edgat.cedit Golygu'r porth penodol. ho.edgat.cadd Ychanegu porth. ho.edgat.cdel Dileu'r porth penodol. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Math y giat. ho.edgat.gname Enw'r enghraifft yma o'r giat. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx Cyfesuryn X y giat. ho.edgat.gy Cyfesuryn Y y giat. ho.edgat.swstate -begin- Cyflwr cychwynnol y swits i ddefnyddio wrth ddechrau efelychiad. -end- ho.edgat.dipstate -begin- Cyflwr cychwynnol y swits DIP i ddefnyddio wrth ddechrau efelychiad. -end- ho.edgat.range Amrediad didau i dynnu oddiar fws. ho.edgat.memfile -begin- Y ffeil efo'r cyflwr cychwynnol i'r cof yma. Darllenir y ffeil yma pan ddechreuir yr efelychydd. -end- ho.edgat.func Math ffwythiant y modiwl yma. ho.edgat.frame Label y ffram. ho.opt.undolen -begin- Uchafrif gweithrediadau datwneud i gadw. -end- ho.opt.site -begin- Enw'r safle lle gosodir tkgate. Defnyddir yr enw yma ar unrhyw allbwn argraffydd neu postscript. -end- ho.opt.smooth -begin- Os alluogir y dewisiad yma, gwellheuir sgrolio gan ddefnyddio copiau didfap yn lle ail-ddangosiad cyflawn. Cewch analluogi hyn os oes problemau efo'ch gweinydd. -end- ho.opt.clip -begin- Os alluogir y dewisiad yma, defnyddir tocio i ddiweddaru dim ond y rhan agored o'r ffenest wrth ail-ddangos. Fel arall, ail-luniadir y dangosiad cyfan i bob rhan agored. -end- ho.opt.outmove -begin- Os alluogir y dewisiad yma, dangosir dim ond amlinelliad o enghreifftiau modiwl sy'n cael eu symud wrth dynnu. Defnyddiwch y nodwedd yma dim ond ar beiriannau efo dangosiadau araf. -end- ho.opt.bhelp -begin- Os alluogir y dewisiad yma, gweithredir balwnau cymorth. Mae balwnau cymorth, fel ur un yma, yn darparu cyngor ar elfennau rhyngwyneb pan mae'r llygoden drostynt. -end- ho.opt.novice -begin- Os ni phenodir unrhyw cylched arall ar y llinell gorchymyn, dangosir tiwtorial TkGate fel y cylched cychwynnol wrth ddechrau. -end- ho.opt.debug -begin- Alluogi rhai nodweddau datnamu. Mae hyn o ddefnydd i neb ond datblygwyr TkGate. -end- ho.opt.ckpt Alluogi rheolfeydd i gylchredau sy ddim wedi'w cadw. ho.opt.ckptfreq Amlder rheolfeydd mewn eiliadau. ho.opt.beak -begin- Alluogi'r nodweddau hollol di-ddefnydd yma. Os analluogir y nodwedd yma, ni ddangosir y moddau yma (neu'r blwch cywiro) yn y blwch dewisiadau. Yr unig ffordd o ail-alluogi nhw fydd golygu eich ffeil .tkgate-properties. -end- ho.opt.miles -begin- Os alluogir y modd yma, bydd TkGate yn sarhau deallusrwydd y defnyddiwr bob hyn a hyn. -end- ho.opt.bat -begin- Os alluogir y modd yma, bydd TkGate yn gosod amgylchedd i ddylunio cyfrifiadur bat. -end- ho.opt.trek Pelydra fi i fyny Scotty! ho.opt.normal Analluogi pethau hwyl. ho.opt.simstep -begin- Y nifer o gyfnodau i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.ckstep -begin- Y nifer o cylchredau cloc i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.ckover -begin- Y nifer o gyfnodau heibio'r ymyl codi o'r cloc i flaenu pan rhoir y gorchymyn cam cloc. -end- ho.opt.vpopupdelay -begin- Yr oediad mewn milfedau o eiliadau rhwng gwthio a gafael yn y botwm llygoden a dangos gwerth signal. Ar rai cysodau, bydd gwerthoedd oediad byr yn ymyrru efo'r gallu i adnabod clic dwbl. Os oes ganddoch y problem yma, cynyddwch y gwerth yma. Caniateir gwerthoedd rhwng 1 a 10000. -end- ho.opt.init -begin- Ffeil sgript efelychiad i weithredu yn awtomatig pan ddechreuir yr efelychiad. -end- ho.opt.ckall -begin- Os alluogir y modd yma, bydd y gorchymyn cam cloc yn seibio'r efelychiad ar yr ymyl positif o unrhyw cloc yn y cylched. -end- ho.opt.ckspec -begin- Os alluogir y modd yma, bydd y gorchymyn cam cloc yn seibio'r efelychiad dim ond ar yr ymyl positif o'r cloc penodol. -end- ho.deftech -begin- Technoleg rhagosodiedig am giatiau newydd. Er mwyn newid technoleg rhyw giat penodol, agorwch ei flwch priodweddau (clic dwbl) a dewiswch y tab "Oediad". -end- ho.techbut -begin- Defnyddio oediadau oddiwrth y ffeil diffiniad technoleg safonol. Er mwyn ychwanegu technolegau dewisiedig, ychwanegwch nhw at y rhestr yn y dewislen "Ffeil -> Dewisiadau -> Efelychu". -end- ho.custbut -begin- Gosod gwerthoedd oediad dewisiedig am y giat yma. -end- ho.contver -begin- Parhau i wirio cyfanrwydd yr adeileddau data mewnol ar ol pob gweithrediad. -end- ho.simwatch -begin- Dangos gorchymynau a anfonir rhwng y GUI a'r efelychydd. -end- ho.simlog -begin- Ysgrifennu'r gorchymynau a rhoir i'r efelychydd i ffeil cofnod. Gellir y ffeil cofnod ei ddefnyddio wedyn fel mewnbwn i'r efelychydd mewn datnamydd. -end- ho.cpathanal -begin- Canfod llwybrau allweddol mewn cylched. -end- tkgate-2.0-b10/locale/ca/messages000644 001751 001751 00000070013 11134010406 017351 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # # Translation by Roman Valls (brainlinux@softhome.net) # \language Catalan ############################################################################## # # basic strings # b.dismiss Tornar b.close Tancar b.ok OK b.clear Esborrar b.cancel Cancel·lar b.open Obrir... b.bitw Amplada bus b.in entrada b.out sortida b.inout bidireccional b.browse Visualitzar... b.label Etiqueta b.find Cercar b.edit Editar... b.add Afegir... b.delete Esborrar b.deleteb Esborrar... b.apply Aplicar b.anchor Anclar b.tech Tecnologia ############################################################################## # Menú strings # file Fitxer edit Editar tool Eines simulate Simular module Mòdul gate Porta make Inserir circ Circuit new Nou open Obrir... openlib Obrir llibreria... save Guardar saveas Guardar com... print Imprimir... options Opcions... quit Sortir cut Tallar copy Copiar paste Enganxar selall Seleccionar tot find Cercar... algnv Situar en columna algnh Situar en fila zoomin Zoom + zoomout Zoom - move Moure/Connectar delg Esborrar porta cutw Tallar cable inv Invertir bitw Amplada del bus debug Depurar rot0 Orientació 0º rot90 Orientació 90º rot180 Orientació 180º rot270 Orientació 270º simbegin Començar simulació simend Acabar simulació simrun Mode continu simpause Pausa simstep Pas a pas (temps) simcycle Pas a pas (nº cicles) simbreak Punt de ruptura... simscript Executar Guió... simload Fitxer -> Memoria... simdump Memòria -> Fitxer... modopen Obrir modclose Tancar modseti Ajustar interficie modediti Editar interficies... modnew Nou... moddel Esborra... modcopy Copia... modrename Canvia el nom... modclaim Mòdul llibreria -> Mòdul usuari... circprop Propietats del circuit... cpath Camí crític... gataddin Afegeix entrada gataddout Afegeix sortida gataddinout Afegeix bidireccional gatiochg Canviar tipus gatanchor Fixar selecció gatunanchor Alliberar selecció gatprop Propietats... gatrep Rèplica gatdel Esborrar gatsettech Seleccionar tecnologia gmswitch Entrada/Sortida gmgate Porta gmredgate Reducció gmmsi MSI gmalu ALU gmmem Memòria gmmod Mòdul gmcomment Comentari gmframe Marc gmxswitch Commutador gmdip Interruptors DIP gmground Massa gmvdd Vdd gmmerge Línies <-> Bus gmclock Senyal de rellotge gm.led LED gm.ledbar Barra de LEDs gm.ledhex 7-Seg. LED (HEXADECIMAL) gm.leddec 7-Seg. LED (DECIMAL) gm.ledseg 7-Seg. LED (Directe) gmtty TTY (Terminal) gmand AND (Y) gmnand NAND (NO-Y) gmor OR (O) gmnor NOR (NO-O) gmxor XOR (O-EX) gmxnor XNOR (NO-O-EX) gmbuf Buffer gminv Inversor gmtribuf Buffer-Triestat gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Sumador gmmult Multiplicador gmdiv Divisor gmlshift Despl. Esquerra gmrshift Despl. Dreta gmarshift Despl. Arit. Dreta gmroll Despl. Cíclic gmreg Registre gmff Biestable D gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decodificador gm14dec 1-4 Decodificador gm18dec 1-8 Decodificador gmmodinst Insereix mòdul gmmodin Entrada mòdul gmmodout Sortida mòdul gmmodinout Mòdul bidireccional addwireseg Afegir segment de cable help Ajuda hlpabout A propòsit de... hlplicense Llicència... hlpdoc Documentació... hlptut Tutorials hlpexample Exemples exampcomb Lògica combinacional examp3bit Comptador de 3 bits examp8bit Comptador de 8 bits examptrff FF a nivell de transistors exampcpu CPU tutwelcome Introducció al TkGate tutcreate Creant un circuit tutedit1 Editant un circuit (1) tutedit2 Editant un circuit (2) tutmods Usant els mòduls tutsim Simulant un circuit # Scope Menu menu.sc.prtrace Visualizant senyal... menu.sc.close Tancar menu.sc.trace Senyal menu.sc.zoomin Apropar menu.sc.zoomout Allunyar ############################################################################## # Interface strings # ifile Fitxer imodule Mòdul iblmodule Mòduls: iports Ports: ibits Bits: ############################################################################# # Net Dialog Box # db.net.name Nom connexió db.net.hide Ocultar db.net.bits Amplada bus db.net.port Tipus de pota db.net.in entrada db.net.out sortida db.net.inout bidireccional db.net.inets Connexions ############################################################################## # Gate dialog box # db.gate.signam Nom del senyal db.gate.portnam Nom de la pota db.gate.iotype Tipus db.gate.bitw Amplada del bus db.gate.cyclew Amplada del cicle db.gate.phase Fase db.gate.duty Funció db.gate.port Pota db.gate.bitws Bits db.gate.gtype Tipus de porta db.gate.gname Nom de la porta db.gate.hidenam Ocultar db.gate.anchor Anclada db.gate.cpbreak Ruptura del camí crític db.gate.butstate Estat del botó db.gate.dipval Valor del commutador db.gate.memfilenam Fitxer de memòria db.gate.modname Funció db.gate.islink El text és un link db.gate.link Enllaç a fitxer db.gate.findw Cerca només cables db.gate.findg Cerca només portes db.gate.findwg Cerca cables i portes db.gate.general General db.gate.details Detalls db.gate.ports Pota db.gate.delay Retard db.gate.stddelay Retard normal db.gate.custdelay Retard personalitzat db.led.type Tipus de LED db.led.bit Bit db.led.bar Barra gràfica db.led.hex 7-Segments (HEXADECIMAL) db.led.dec 7-Segments (DECIMAL) db.led.seg 7-Segments (Directe) cpath.cloops -begin- S'ha detectat un bucle de realimentació en el seu circuit. Per a poder realitzar un anàlisi dels retards en aquest circuit, s'haurà de, o be trencar el bucle, o marcar alguna de les portes en el bucle com a punt d'un "Camí crític". Les connexions detectades com bucle es mostren a sota. -end- ############################################################################## # Print dialog box # print.outto Sortida a print.printer Impressora print.file Fitxer print.prcmd Comanda d'Impressió print.filename Nom del Fitxer print.epssave Salvar com a EPS. print.doctit Títol del Document print.prmod Imprimir Mòduls print.epcm Període de temps/cm print.estpg Pàgines estimades print.all Tot print.cur Actual print.use Usats print.sel Seleccionats print.inclib Inclou mòduls de llibreria. print.papsz Dimensions del paper print.orient Orientació print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opcions print.scale Escalar mòduls fins a completar pàgina. print.partition Dividir mòduls grans en varies pàgines. print.incidx Inclou índex. print.incgraph Inclou gràfic de jerarquia. print.4up Imprimir quatre pàgines en una. print.range Rang print.fulltr Traçat complet print.parttr Traçat parcial print.start Començar print.end Fi ############################################################################## # # Options dialog # opt.site Nom de l'empresa opt.inst Instàncies opt.mods Mòduls opt.modports Potes de mòduls opt.frames Marcs opt.comment Comentaris opt.hlink Hiperenllaços opt.wire Cables simples (1 Bit) opt.bus Busos opt.tools Eines de porta opt.cpath Camins crítics opt.grid Visualitzar Reixeta opt.logic1 Lògica '1' opt.logic0 Lògica '0' (negada) opt.float Flotant opt.unknown Conflicte Desconegut opt.offled LED apagat opt.onled LED encès opt.zled LED flotant opt.restdef Restaura opcions per defecte opt.regudate Refrescar Regió opt.smoothscroll Desplaçament Suau opt.outmove Mostra només el requadre al moure'l opt.balloon Habilitar globus d'ajuda opt.debug Habilitar depuració opt.novice Mode Principiant opt.ckpoint Realitzar comprovació de punts opt.freq Freqüència opt.beak Habilitar mode especial opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.showsimcmd Visualitzar cadena simulada opt.logfile Fitxer de missatges del simulador opt.estepsz Ajust de temps (simulació pas a pas) opt.cstepsz Ajust nº cicles (simulació pas a pas) opt.overstep Excedir rellotge opt.initscript Guió d'inicialització opt.posedge El rellotge s'atura després de cada flanc opt.setclock El rellotge s'atura a cada flanc opt.delayfilepath Fitxers de retard opt.general General opt.print Imprimir opt.simulate Simular opt.analysis Anàlisi opt.color Color opt.cpopts Opcions dels camins crítics: opt.maxpath Màxim nº de camins: opt.cpflash Veure amb ruta ressaltada opt.vercheck -begin- Comprova de forma periòdica si existeixen noves versions del programa TkGate a Internet. No activar si no es disposa d'una connexió permanent a la xarxa. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Mòdul nou blklst.delmod Borra mòdul blklst.frommod Copia mòdul de blklst.tomod a blklst.oldname Nombre anterior blklst.newname Nombre nou blklst.claim Mòdul llibreria -> Mòdul usuari ############################################################################## # # Circuit Dialog box # circ.topmod Mòdul principal circ.discchg Descartar canvis circ.iniscript Guions d'inicializació circ.noscript No ha seleccionat fitxers de guió. circ.really1 Realment vol esborrar-ho circ.really2 de la llista de guions d'inicializació ############################################################################## # Simulator # sim.breakpt Punt de ruptura ############################################################################## # # Command box # cmd.file Nom del fitxer cmd.topname Nom del mòdul principal ############################################################################## # # Critical path messages # cp.delay Retard del camí: cp.pathl Llista de camins: cp.numpath Nombre de camins: cp.recompute Recalcular ############################################################################## # Error messages # err.verilog Errors en fitxer: err.nopin No puc canviar la pota seleccionada. err.badhex Valor hexadecimal incorrecte. Ignoro '%s'. err.gatanchor Les portes anclades no poden moure's. err.libmode Operació il·legal en mòdul de llibreria (convertir a mòdul normal per editar). err.badfind No puc trobar '%s' com a destí. err.badopendel No puc esborrar un mòdul obert. err.nosrcmod No puc trobar '%s' com a mòdul font. err.noerr Error desconegut. err.misserr Error, informació incompleta (s'ha penjat el simulador?) err.pounimpl Informació d'error no implementada err.badinadd No puc afegir més entrades a la porta seleccionada. err.badoutadd No puc afegir més sortides a la porta seleccionada. err.badinoutadd No puc afegir més línies bidireccionals a la porta err.badpinchg No puc canviar el tipus de potes de la porta. err.badnetname He esborrat caràcters incorrectes en l'identificador. err.netbcrename Identificador canvia a '%s' per caràcters incorrectes. err.netconfnet Identificador canvia a '%s' degut a un conflicte. err.netconfgat Identificador canvia degut a conflicte amb nom de porta bàsica. err.netconfkw Identificador canvia degut a conflicte amb paraula reservada. err.badconsame Unió refusada degut a que els cables formen part de la mateixa connexió. err.badconptsp Unió refusada degut a que ambdós cables son potes de mòduls o alimentació. err.badconbitw Unió refusada per no poder-se aparellar l'amplada dels dos busos. err.badrange No es permet visualitzar el rang no positiu del senyal. err.badlprcmd No puc executar la comanda '%s' d'impressió. err.badpsopen No puc obrir el fitxer '%s' per sortida postscript. err.bkpt.badexp Error de sintaxis en expresió per punt de ruptura. Pot ésser una de les següents: 'connexió', '!connexió', 'connexió == valor', 'connexió != valor' err.bkpt.badnet '%s' es un nom incorrecte de connexió. Els noms vàlids han de començar per una lletra i contenir només lletres, nombres y el signe '.'. err.bkpt.badval Error de sintaxis en el valor '%s'. Ha de ser decimal o una constant de l'estil de Verilog. err.bkpt.toomany Masses punts de ruptura. El màxim és de %d. err.sim.badtmp No puc salvar el fitxer temporal '%s' per la simulació ( ¿ Disc ple ? ) err.sim.syntx Error de sintaxis en la comanda '%s'. err.sim.noincl El fitxer Include '%s' no es troba. err.sim.clockbadedge Indicador il·legal en el pols '%c' de rellotge. err.sim.nobkpt No existeix punt de ruptura '%s'. err.sim.nonet No puc trobar la connexió '%s'. err.sim.nogate No puc trobar la porta '%s'. err.sim.badbin '%s' es un caràcter incorrecte en constant binaria. err.sim.notswitch La porta '%s' no es un commutador, dip o registre. err.sim.badcmd No reconeixo la comanda '%s' en el guió de simulació. err.noteditpchg Les propietats només es poden canviar en mode Edició. err.badeditop Operació il·legal en el mode d'Edició. err.badopen No puc obrir el fitxer '%s'. err.badlibopen No puc obrir la llibreria '%s'. err.nomark Per favor marca amb el botó esquerra abans de seleccionar el tipus de porta. err.badgate No connexió aquest tipus de porta. err.badmake No puc crear la porta. err.manypages -begin- Hi ha MOLTES pàgines en aquest document. ¿ Estàs segur que vols imprimir-lo ?. -end- err.nojump -begin- La possibilitat de 'saltar al mòdul' no es pot usar en el mode de simulació o en l'anàlisi d'un camí crític. Per favor navega de forma manual fins al bloc de destí seleccionant els mòduls adequats y usant l'opció '>' del teclat. S'accedeix al mòdul de nivell superior en la jerarquia actuant sobre la tecla '<'. -end- err.nomod Mòdul '%s' no està definit. err.modlock !Aquest bloc lògic l'està visualitzant! err.closeroot No puc tancar el mòdul principal. Usa l'opció Sortir del menú Fitxer. err.sim.isrun El simulador està executant-se en aquests moments (Usa 'Ctrl-s e' per acabar). err.sim.isnotrun El simulador no està funcionant (Usa 'Ctrl-s b' per començar). err.editonly Comanda incorrecta en el mode de simulació. err.simonly Comanda només vàlida en mode simulació. err.nodel No es pot esborrar la selecció. err.modnotdef Mòdul '%s' no definit. err.moddef El bloc '%s' ja existeix. err.noprop No es poden editar les propietats de la porta seleccionada. err.openscript No puc obrir el fitxer de guió de simulació '%s' err.oldversion Carregat fitxer de la versió %s, obsoleta (la més recent es la versió %s). err.futureversion Fitxer salvat en la versió %s, futura versió del programa tkgate (la versió actual es %s). err.badversion Es desconeix el número de versió. Usada sota la seva responsabilitat. err.nodrive Connexió %s no posseeix entrada en el mòdul %s. err.noconn Cable %s{%d} no posseeix connexions - l'esborrem. err.noback -begin- El fitxer %s, es crearà per el programa tkgate, y no podrà llegir-se per a versions anteriors a l'actual (%s), si vol salvar-lo. -end- ############################################################################## # Informational messages # msg.selwire Seleccionat cable denominat '%s'. msg.selgate Seleccionat %s denominat '%s'. msg.selblock Seleccionat bloc %s denominat '%s'. msg.modoverwt Mòdul de destino '%s' existeix. ¿ Sobreescriure ? msg.foundgate Trobada porta denominada '%s'. msg.foundwire Trobat cable denominat '%s'. msg.searchagn Cadena destí '%s' no trobada. Fes clic a 'Cercar' per reiniciar la cerca. msg.sim.chgtoroot El mode simulació requereix el mòdul principal al capdamunt de la pila d'Edició. msg.sim.nogatemod Mode simulació requereix un mòdul concret de pila. msg.setinterface Ajustar l'interficie del mòdul per '%s'. msg.needsel Per favor selecciona una instància de mòdul. msg.wroteckpt Comprova punt a %s... msg.save Salva circuit com a '%s'. msg.badsave Falla fitxer de sortida '%s'. msg.reallynew El circuit s'ha modificat. ¿ Realment vols perdre els canvis i crear un de nou ? msg.reallyquit El circuit s'ha modificat. ¿ Realment vols sortir ? msg.notlib '%s' no és un mòdul de llibreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Només un tarat col·locaria %s%s aquí, Miles. miles.msg2 És realment un estúpid lloc on col·locar %s%s, Miles. miles.msg3 És un lloc horrible per a col·locar %s%s, Miles. miles.msg4 Miles, deus estar malament del cap si col·loques %s%s aquí. miles.msg5 Només tú pots col·locar %s%s aquí, Miles. miles.msg6 Col·locar %s%s aquí es una proba més de que ets absolutament estúpid, Miles. miles.msg7 No saps què coi fas, Miles, es un circuit estúpid. miles.msg8a És inútil continuar, Miles. miles.msg8b És obvi que no pots dissenyar un circuit. ############################################################################## # Balloon Help # ho.new -begin- Esborra el circuit actual i n'edita un de nou. -end- ho.open Fitxer -> Circuit ho.save Circuit -> Fitxer actual ho.print Circuit -> Impressora ho.move -begin- Move/Connect - Fent clic i arrossegant el mouse pots: Ajustar la posició d'una porta recent inserida. Moure portes y connexions ja col·locades Connectar cables entre potes de portes Fent doble-clic pots: Editar les propietats de portes, connexions i ports Editar el text dels comentaris -end- ho.delgat -begin- Esborrar porta - Usa aquesta eina per esborrar les portes. -end- ho.cutw -begin- Talla cables - Usa aquesta eina per desconnectar cables. -end- ho.inv -begin- Invertir - Usa aquesta eina per inserir o esborrar inversions de les potes de les portes. -end- ho.bitw -begin- Amplada del Bus - Usa aquesta eina per canviar el número de línies del Bus. Introdueix l'esmentat nombre en la part inferior dreta de la finestra. -end- ho.modopen Obre el mòdul seleccionat. ho.modclose Tanca el mòdul actual. ho.simgo -begin- Si no estem simulant, inicia la simulació y executa qualsevol guió d'inicializació. Si estem simulant, es col·loca en mode continu o interactiu. -end- ho.simpause -begin- Atura la simulació en curs. -end- ho.simstep -begin- Avança la simulació un interval de temps fix. Obre el submenú Opcions de simulació per ajustar-lo. -end- ho.simclock -begin- Avança la simulació un nombre fix de cicles de rellotge. Obre el submenú Opcions de simulació per ajustarlo. -end- ho.simstop -begin- Finalitza la simulació en curs i retorna al mode d'Edició. -end- ho.simbreak -begin- Edita els punts de ruptura. La simulació s'aturarà quan la condició especificada sigui certa. -end- ho.simexec Executa un guió de simulació. ho.simload -begin- Carrega la memòria amb el contingut d'un fitxer amb extensió .mem. -end- ho.simdump -begin- Emmagatzema el contingut de la memòria en un fitxer amb extensió .mem. -end- ho.sim.break -begin- Introdueix un punt de ruptura. Un punt de ruptura és una expressió que atura la simulació quan l'avaluació resulta certa. Les expressions suportades per el programa son del tipus operador lògic simple : "w1 == 0" o "w7 != 8". També es contemplen expressions en les que es nega la connexió: "!w2". -end- ho.f.modlist -begin- Llista tots els mòduls actualment carregats. El mòdul principal, el superior en la jerarquia, s'indica amb el signe "+". Els mòduls de llibreria es visualitzen entre parèntesi. -end- ho.netlist -begin- Llista totes les connexions del mòdul actual. Connexions marcades amb el signe "@" no presenten el seu nom en l'esquema (connexions ocultes). Les connexions BUS van seguides del nombre de línies que posseeixen. -end- ho.ports -begin- Llista totes les potes del mòdul actual El signe '>' indica l'entrada, '<' indica la sortida, i '=' indica línia bidireccional. -end- ho.status.logo -begin- Estat de la simulació. Si es presenta una porta de ferro estem en el mode d'Edició. Si es presenta una porta AND amb quatre potes estem en mode de simulació. Si la porta és estàtica, la simulació està aturada i si està en moviment, la simulació està en ple funcionamient. -end- ho.status.msg Els missatges del programa es presenten aquí. ho.status.block La pila de mòduls que estan essent editats. ho.status.file -begin- Fitxer actualment editat. El signe '*' indica que el buffer s'ha modificat des de l'últim cop que el fitxer que s'ha desat al disc. -end- ho.print.selall Imprimir tots els mòduls actualment carregats en TKGate. ho.print.selcur Imprimir només el mòdul present en la finestra d'Edició de TKGate. ho.print.seluse -begin- Imprimeix tots els mòduls "en ús". Els mòduls en ús son aquells que descendeixen del principal seguint la jerarquia d'arbre. -end- ho.print.selsel -begin- Imprimeix només els mòduls seleccionats més a sota. Usa la tecla CONTROL per seleccionar més d'un. -end- ho.print.modlist Selecciona els mòduls a imprimir. ho.circuit.discchg -begin- TkGate no presenta un avís si descartes els canvis sense salvar. -end- ho.cmd.bitw -begin- Els cables seleccionats amb el cursor poden ajustar-se a aquesta amplada de Bus. -end- ho.edgat.signam -begin- El nom del senyal seleccionat a la porta. Pots canviar aquest nom editant aquí. -end- ho.edgat.port -begin- El nom de la pota per aquesta senyal en aquesta porta. Aquest camp només pot ser editat per instàncies de mòduls. -end- ho.edgat.iolab -begin- La direcció del senyal seleccionat d'aquesta porta. Aquest camp només pot editar-se en les instàncies de mòduls. -end- ho.edgat.bitlab -begin- L'amplada del Bus de la senyal seleccionada d' aquesta porta. Es pot canviar editant aquí. -end- ho.edgat.cycle El nombre total de períodes de temps en un cicle de rellotge. ho.edgat.phase El punt inicial del cicle (en %). ho.edgat.duty El % del cicle que el rellotge està en flanc de baixada. ho.edgat.cname Nom de la connexió a la que s'uneix. ho.edgat.cport Pota de la connexió a la que s'uneix. ho.edgat.ctype Tipus de connexió. ho.edgat.cbitw Amplada del Bus de la connexió a la que s'uneix. ho.edgat.cedit Edita la pota seleccionada. ho.edgat.cadd Afegeix una pota. ho.edgat.cdel Borra la pota seleccionada. ho.edgat.hide -begin- Activa aquest flag per no visualitzar el nom de la porta. -end- ho.edgat.gtype Tipus de porta. ho.edgat.gname Nom d'aquesta instància de porta. ho.edgat.ganchor Activa aquest flag per anclar la posició de la porta. ho.edgat.gx Coordenada X de la porta. ho.edgat.gy Coordenada Y de la porta. ho.edgat.swstate -begin- Estat inicial del commutador quan s'inicia una sessió de simulació. -end- ho.edgat.dipstate -begin- Estat inicial dels interruptors DIP quan s'inicia una sessió de simulació. -end- ho.edgat.range El rang de bits a col·locar en un bus. ho.edgat.memfile -begin- El fitxer amb l'estat inicial d'aquesta memòria. Aquest fitxer es llegeix quan s'inicia el Simulador. -end- ho.edgat.func El tipus de funció d'aquest mòdul. ho.edgat.frame L'etiqueta del plafó. ho.opt.site -begin- El nom del lloc on tkgate s'ha instal·lat. S'usa en la sortida impresa o fitxer postscript. -end- ho.opt.smooth -begin- Si aquesta opció està habilitada, el desplaçament s'optimitza al usar copies bitmap en comptes d'un re-dibuixat complert. Pots desactivar-la si hi ha problemes amb el seu servidor. -end- ho.opt.clip -begin- Si aquesta opció està habilitada, s'actualitza només la regió realment exposada de l'entorno d'Edició. En cas contrari, es re-dibuixa tot. -end- ho.opt.outmove -begin- Si aquesta opció està habilitada, només un requadre que envolta a les instàncies de mòduls es dibuixa mentre s'arrossega aquest. Usa aquesta opció en les màquines amb microprocessadors i tarjes gràfiques lentes. -end- ho.opt.bhelp -begin- Si aquesta opció està habilitada, els globus d'ajuda s'activen. Els globus d'ajuda, com aquest mateix, proporcionen una ajuda resumida sobre els elements de la interficie, quan el mouse hi passa per sobre. -end- ho.opt.novice -begin- Si no s'especifica cap circuit en la línia de comandes, TkGate presenta un tutorial per iniciar-se amb l'ús del programa. -end- ho.opt.debug -begin- Habilita algunes opcions de depuració. Només es útil per a programadors del TkGate. -end- ho.opt.ckpt Habilitar els punts de chequeig per circuits no salvats. ho.opt.ckptfreq Freqüència dels punts de chequeig en segons. ho.opt.beak -begin- Habilitar totes aquestes opcions. Si deshabilita aquesta opció, aquests modes (i aquesta caixa de diàleg) no apareix en el menú opcions. Només pot recuperar-se editant el fitxer .tkgate-properties. -end- ho.opt.miles -begin- Si aquest mode està habilitat, el programa insulta periòdicament la intel·ligència de l'usuari. -end- ho.opt.bat -begin- Si aquest mode està habilitat, el programa activarà l'entorn per dissenyar un computador senzill a partir de mòduls. -end- ho.opt.trek Ajuda Scoty! ho.opt.normal Fora conyes. ho.opt.simstep -begin- El nombre de períodes de temps que avancem si hem activat el mode pas a pas per temps. -end- ho.opt.ckstep -begin- El nombre de cicles de rellotge que avancem si hem activat el mode pas a pas per nº de cicles. -end- ho.opt.ckover -begin- El nombre de períodes de temps després d'un flanc de baixada de rellotge que avancem si hem activat el mode pas a pas. -end- ho.opt.init -begin- El fitxer de guió que s'executa de forma automàtica al iniciar la simulació. -end- ho.opt.ckall -begin- Si aquest mode s'habilita, la comanda pas a pas ?¿?¿? la simulació en el flanc de pujada de qualssevol rellotge present en el circuit. -end- ho.opt.ckspec -begin- Si aquest mode està habilitat, la comanda pas a pas ?¿¿?¿ la simulació es el flanc de pujada de la senyal de rellotge especificada. -end- ho.deftech -begin- La tecnologia per defecte emprada per las portes recent creades. Afecta al temps de retard de les portes. Per canviar la tecnologia d'una porta específica, obrir la caixa de propietats (doble clic) i seleccionar "Retard". -end- ho.techbut -begin- Usa retards per la tecnologia estàndard d'un fitxer de definició. Per afegir tecnologies personalitzades, afegir-les a la llista del menú "Fitxer -> Opcions -> Simulador". -end- ho.custbut -begin- Ajustar valors de retards personalitzats per aquesta porta. -end- ho.simwatch -begin- Visualitzar comandes enviades entre l'entorn de visualització (GUI) i el simulador. -end- ho.simlog -begin- Escriu comandes emeses pel simulador a un log. Aquest log pot usar-se com a fitxer d'entrada al simulador en la depuració. -end- ho.cpathanal -begin- Toba camins crítics en el circuit. -end- undo Desfer redo Refer simadprobe Afegir/Esborrar Probe db.gate.exttbar Usar barres exteses opt.contver Comprovació d'integritat automàtica opt.vpopupdelay Retard en mostrar el valor opt.undolen Màx nivell de desfer circ.extbar Usar barres exteses err.badid Identificador '%s' Il·legal. err.badportadd No es poden afegir ports a portes d'aquest tipus. err.badportdel El port sel·leccionat no pot ser esborrat. err.badportedit El port sel·leccionat no pot ser editat. err.noport Cap port seleccionat. err.oldportact Siusplau, clica amb el botó dret al port o pestanya del mòdul per afegir/canviar port. ho.undo Desfés la/les acció(ns) anterior(s) ho.redo Refés la/les accio(ns). ho.edgat.extbar -begin- Si està activat, les portes bàsiques amb vàries entrades usaran barres extensores a les entrades. -end- ho.opt.undolen -begin- Defineix el màxim nombre de nivells de desfer. -end- db.gate.extbar Usar barres extensores ho.circuit.extbar -begin- Les portes bàsiques (AND, OR, XOR) usaran barres extensores per agrupar vàries portes d'entrada. -end- ho.opt.vpopupdelay -begin- El retard en milisegons que es triga a mostrar el valor del senyal. En alguns sistemes, valors petits poden causar problemes a l'hora de detectar el doble clic. Si tens aquest problema, augmenta el valor del retard. Es permeten valors entre 1 i 10000. -end- ho.contver -begin- Verificar contínuament la integritat de les estructures de dades internes despres de cada operació. -end- tkgate-2.0-b10/locale/ca/messages.bak000644 001751 001751 00000070013 11134010127 020105 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # # Translation by Roman Valls (brainlinux@softhome.net) # \language Catalan ############################################################################## # # basic strings # b.dismiss Tornar b.close Tancar b.ok OK b.clear Esborrar b.cancel Cancel·lar b.open Obrir... b.bitw Amplada bus b.in entrada b.out sortida b.inout bidireccional b.browse Visualitzar... b.label Etiqueta b.find Cercar b.edit Editar... b.add Afegir... b.delete Esborrar b.deleteb Esborrar... b.apply Aplicar b.anchor Anclar b.tech Tecnologia ############################################################################## # Menú strings # file Fitxer edit Editar tool Eines simulate Simular module Mòdul gate Porta make Inserir circ Circuit new Nou open Obrir... openlib Obrir llibreria... save Guardar saveas Guardar com... print Imprimir... options Opcions... quit Sortir cut Tallar copy Copiar paste Enganxar selall Seleccionar tot find Cercar... algnv Situar en columna algnh Situar en fila zoomin Zoom + zoomout Zoom - move Moure/Connectar delg Esborrar porta cutw Tallar cable inv Invertir bitw Amplada del bus debug Depurar rot0 Orientació 0º rot90 Orientació 90º rot180 Orientació 180º rot270 Orientació 270º simbegin Començar simulació simend Acabar simulació simrun Mode continu simpause Pausa simstep Pas a pas (temps) simcycle Pas a pas (nº cicles) simbreak Punt de ruptura... simscript Executar Guió... simload Fitxer -> Memoria... simdump Memòria -> Fitxer... modopen Obrir modclose Tancar modseti Ajustar interficie modediti Editar interficies... modnew Nou... moddel Esborra... modcopy Copia... modrename Canvia el nom... modclaim Mòdul llibreria -> Mòdul usuari... circprop Propietats del circuit... cpath Camí crític... gataddin Afegeix entrada gataddout Afegeix sortida gataddinout Afegeix bidireccional gatiochg Canviar tipus gatanchor Fixar selecció gatunanchor Alliberar selecció gatprop Propietats... gatrep Rèplica gatdel Esborrar gatsettech Seleccionar tecnologia gmswitch Entrada/Sortida gmgate Porta gmredgate Reducció gmmsi MSI gmalu ALU gmmem Memòria gmmod Mòdul gmcomment Comentari gmframe Marc gmxswitch Commutador gmdip Interruptors DIP gmground Massa gmvdd Vdd gmmerge Línies <-> Bus gmclock Senyal de rellotge gm.led LED gm.ledbar Barra de LEDs gm.ledhex 7-Seg. LED (HEXADECIMAL) gm.leddec 7-Seg. LED (DECIMAL) gm.ledseg 7-Seg. LED (Directe) gmtty TTY (Terminal) gmand AND (Y) gmnand NAND (NO-Y) gmor OR (O) gmnor NOR (NO-O) gmxor XOR (O-EX) gmxnor XNOR (NO-O-EX) gmbuf Buffer gminv Inversor gmtribuf Buffer-Triestat gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Sumador gmmult Multiplicador gmdiv Divisor gmlshift Despl. Esquerra gmrshift Despl. Dreta gmarshift Despl. Arit. Dreta gmroll Despl. Cíclic gmreg Registre gmff Biestable D gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decodificador gm14dec 1-4 Decodificador gm18dec 1-8 Decodificador gmmodinst Insereix mòdul gmmodin Entrada mòdul gmmodout Sortida mòdul gmmodinout Mòdul bidireccional addwireseg Afegir segment de cable help Ajuda hlpabout A propòsit de... hlplicense Llicència... hlpdoc Documentació... hlptut Tutorials hlpexample Exemples exampcomb Lògica combinacional examp3bit Comptador de 3 bits examp8bit Comptador de 8 bits examptrff FF a nivell de transistors exampcpu CPU tutwelcome Introducció al TkGate tutcreate Creant un circuit tutedit1 Editant un circuit (1) tutedit2 Editant un circuit (2) tutmods Usant els mòduls tutsim Simulant un circuit # Scope Menu menu.sc.prtrace Visualizant senyal... menu.sc.close Tancar menu.sc.trace Senyal menu.sc.zoomin Apropar menu.sc.zoomout Allunyar ############################################################################## # Interface strings # ifile Fitxer imodule Mòdul iblmodule Mòduls: iports Ports: ibits Bits: ############################################################################# # Net Dialog Box # db.net.name Nom connexió db.net.hide Ocultar db.net.bits Amplada bus db.net.port Tipus de pota db.net.in entrada db.net.out sortida db.net.inout bidireccional db.net.inets Connexions ############################################################################## # Gate dialog box # db.gate.signam Nom del senyal db.gate.portnam Nom de la pota db.gate.iotype Tipus db.gate.bitw Amplada del bus db.gate.cyclew Amplada del cicle db.gate.phase Fase db.gate.duty Funció db.gate.port Pota db.gate.bitws Bits db.gate.gtype Tipus de porta db.gate.gname Nom de la porta db.gate.hidenam Ocultar db.gate.anchor Anclada db.gate.cpbreak Ruptura del camí crític db.gate.butstate Estat del botó db.gate.dipval Valor del commutador db.gate.memfilenam Fitxer de memòria db.gate.modname Funció db.gate.islink El text és un link db.gate.link Enllaç a fitxer db.gate.findw Cerca només cables db.gate.findg Cerca només portes db.gate.findwg Cerca cables i portes db.gate.general General db.gate.details Detalls db.gate.ports Pota db.gate.delay Retard db.gate.stddelay Retard normal db.gate.custdelay Retard personalitzat db.led.type Tipus de LED db.led.bit Bit db.led.bar Barra gràfica db.led.hex 7-Segments (HEXADECIMAL) db.led.dec 7-Segments (DECIMAL) db.led.seg 7-Segments (Directe) cpath.cloops -begin- S'ha detectat un bucle de realimentació en el seu circuit. Per a poder realitzar un anàlisi dels retards en aquest circuit, s'haurà de, o be trencar el bucle, o marcar alguna de les portes en el bucle com a punt d'un "Camí crític". Les connexions detectades com bucle es mostren a sota. -end- ############################################################################## # Print dialog box # print.outto Sortida a print.printer Impressora print.file Fitxer print.prcmd Comanda d'Impressió print.filename Nom del Fitxer print.epssave Salvar com a EPS. print.doctit Títol del Document print.prmod Imprimir Mòduls print.epcm Període de temps/cm print.estpg Pàgines estimades print.all Tot print.cur Actual print.use Usats print.sel Seleccionats print.inclib Inclou mòduls de llibreria. print.papsz Dimensions del paper print.orient Orientació print.portrait Vertical print.landscape Apaisada print.2side Imprimir a doble cara print.opts Opcions print.scale Escalar mòduls fins a completar pàgina. print.partition Dividir mòduls grans en varies pàgines. print.incidx Inclou índex. print.incgraph Inclou gràfic de jerarquia. print.4up Imprimir quatre pàgines en una. print.range Rang print.fulltr Traçat complet print.parttr Traçat parcial print.start Començar print.end Fi ############################################################################## # # Options dialog # opt.site Nom de l'empresa opt.inst Instàncies opt.mods Mòduls opt.modports Potes de mòduls opt.frames Marcs opt.comment Comentaris opt.hlink Hiperenllaços opt.wire Cables simples (1 Bit) opt.bus Busos opt.tools Eines de porta opt.cpath Camins crítics opt.grid Visualitzar Reixeta opt.logic1 Lògica '1' opt.logic0 Lògica '0' (negada) opt.float Flotant opt.unknown Conflicte Desconegut opt.offled LED apagat opt.onled LED encès opt.zled LED flotant opt.restdef Restaura opcions per defecte opt.regudate Refrescar Regió opt.smoothscroll Desplaçament Suau opt.outmove Mostra només el requadre al moure'l opt.balloon Habilitar globus d'ajuda opt.debug Habilitar depuració opt.novice Mode Principiant opt.ckpoint Realitzar comprovació de punts opt.freq Freqüència opt.beak Habilitar mode especial opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.showsimcmd Visualitzar cadena simulada opt.logfile Fitxer de missatges del simulador opt.estepsz Ajust de temps (simulació pas a pas) opt.cstepsz Ajust nº cicles (simulació pas a pas) opt.overstep Excedir rellotge opt.initscript Guió d'inicialització opt.posedge El rellotge s'atura després de cada flanc opt.setclock El rellotge s'atura a cada flanc opt.delayfilepath Fitxers de retard opt.general General opt.print Imprimir opt.simulate Simular opt.analysis Anàlisi opt.color Color opt.cpopts Opcions dels camins crítics: opt.maxpath Màxim nº de camins: opt.cpflash Veure amb ruta ressaltada opt.vercheck -begin- Comprova de forma periòdica si existeixen noves versions del programa TkGate a Internet. No activar si no es disposa d'una connexió permanent a la xarxa. -end- ############################################################################## # # Block list dialog boxes blklst.newmod Mòdul nou blklst.delmod Borra mòdul blklst.frommod Copia mòdul de blklst.tomod a blklst.oldname Nombre anterior blklst.newname Nombre nou blklst.claim Mòdul llibreria -> Mòdul usuari ############################################################################## # # Circuit Dialog box # circ.topmod Mòdul principal circ.discchg Descartar canvis circ.iniscript Guions d'inicializació circ.noscript No ha seleccionat fitxers de guió. circ.really1 Realment vol esborrar-ho circ.really2 de la llista de guions d'inicializació ############################################################################## # Simulator # sim.breakpt Punt de ruptura ############################################################################## # # Command box # cmd.file Nom del fitxer cmd.topname Nom del mòdul principal ############################################################################## # # Critical path messages # cp.delay Retard del camí: cp.pathl Llista de camins: cp.numpath Nombre de camins: cp.recompute Recalcular ############################################################################## # Error messages # err.verilog Errors en fitxer: err.nopin No puc canviar la pota seleccionada. err.badhex Valor hexadecimal incorrecte. Ignoro '%s'. err.gatanchor Les portes anclades no poden moure's. err.libmode Operació il·legal en mòdul de llibreria (convertir a mòdul normal per editar). err.badfind No puc trobar '%s' com a destí. err.badopendel No puc esborrar un mòdul obert. err.nosrcmod No puc trobar '%s' com a mòdul font. err.noerr Error desconegut. err.misserr Error, informació incompleta (s'ha penjat el simulador?) err.pounimpl Informació d'error no implementada err.badinadd No puc afegir més entrades a la porta seleccionada. err.badoutadd No puc afegir més sortides a la porta seleccionada. err.badinoutadd No puc afegir més línies bidireccionals a la porta err.badpinchg No puc canviar el tipus de potes de la porta. err.badnetname He esborrat caràcters incorrectes en l'identificador. err.netbcrename Identificador canvia a '%s' per caràcters incorrectes. err.netconfnet Identificador canvia a '%s' degut a un conflicte. err.netconfgat Identificador canvia degut a conflicte amb nom de porta bàsica. err.netconfkw Identificador canvia degut a conflicte amb paraula reservada. err.badconsame Unió refusada degut a que els cables formen part de la mateixa connexió. err.badconptsp Unió refusada degut a que ambdós cables son potes de mòduls o alimentació. err.badconbitw Unió refusada per no poder-se aparellar l'amplada dels dos busos. err.badrange No es permet visualitzar el rang no positiu del senyal. err.badlprcmd No puc executar la comanda '%s' d'impressió. err.badpsopen No puc obrir el fitxer '%s' per sortida postscript. err.bkpt.badexp Error de sintaxis en expresió per punt de ruptura. Pot ésser una de les següents: 'connexió', '!connexió', 'connexió == valor', 'connexió != valor' err.bkpt.badnet '%s' es un nom incorrecte de connexió. Els noms vàlids han de començar per una lletra i contenir només lletres, nombres y el signe '.'. err.bkpt.badval Error de sintaxis en el valor '%s'. Ha de ser decimal o una constant de l'estil de Verilog. err.bkpt.toomany Masses punts de ruptura. El màxim és de %d. err.sim.badtmp No puc salvar el fitxer temporal '%s' per la simulació ( ¿ Disc ple ? ) err.sim.syntx Error de sintaxis en la comanda '%s'. err.sim.noincl El fitxer Include '%s' no es troba. err.sim.clockbadedge Indicador il·legal en el pols '%c' de rellotge. err.sim.nobkpt No existeix punt de ruptura '%s'. err.sim.nonet No puc trobar la connexió '%s'. err.sim.nogate No puc trobar la porta '%s'. err.sim.badbin '%s' es un caràcter incorrecte en constant binaria. err.sim.notswitch La porta '%s' no es un commutador, dip o registre. err.sim.badcmd No reconeixo la comanda '%s' en el guió de simulació. err.noteditpchg Les propietats només es poden canviar en mode Edició. err.badeditop Operació il·legal en el mode d'Edició. err.badopen No puc obrir el fitxer '%s'. err.badlibopen No puc obrir la llibreria '%s'. err.nomark Per favor marca amb el botó esquerra abans de seleccionar el tipus de porta. err.badgate No connexió aquest tipus de porta. err.badmake No puc crear la porta. err.manypages -begin- Hi ha MOLTES pàgines en aquest document. ¿ Estàs segur que vols imprimir-lo ?. -end- err.nojump -begin- La possibilitat de 'saltar al mòdul' no es pot usar en el mode de simulació o en l'anàlisi d'un camí crític. Per favor navega de forma manual fins al bloc de destí seleccionant els mòduls adequats y usant l'opció '>' del teclat. S'accedeix al mòdul de nivell superior en la jerarquia actuant sobre la tecla '<'. -end- err.nomod Mòdul '%s' no està definit. err.modlock !Aquest bloc lògic l'està visualitzant! err.closeroot No puc tancar el mòdul principal. Usa l'opció Sortir del menú Fitxer. err.sim.isrun El simulador està executant-se en aquests moments (Usa 'Ctrl-s e' per acabar). err.sim.isnotrun El simulador no està funcionant (Usa 'Ctrl-s b' per començar). err.editonly Comanda incorrecta en el mode de simulació. err.simonly Comanda només vàlida en mode simulació. err.nodel No es pot esborrar la selecció. err.modnotdef Mòdul '%s' no definit. err.moddef El bloc '%s' ja existeix. err.noprop No es poden editar les propietats de la porta seleccionada. err.openscript No puc obrir el fitxer de guió de simulació '%s' err.oldversion Carregat fitxer de la versió %s, obsoleta (la més recent es la versió %s). err.futureversion Fitxer salvat en la versió %s, futura versió del programa tkgate (la versió actual es %s). err.badversion Es desconeix el número de versió. Usada sota la seva responsabilitat. err.nodrive Connexió %s no posseeix entrada en el mòdul %s. err.noconn Cable %s{%d} no posseeix connexions - l'esborrem. err.noback -begin- El fitxer %s, es crearà per el programa tkgate, y no podrà llegir-se per a versions anteriors a l'actual (%s), si vol salvar-lo. -end- ############################################################################## # Informational messages # msg.selwire Seleccionat cable denominat '%s'. msg.selgate Seleccionat %s denominat '%s'. msg.selblock Seleccionat bloc %s denominat '%s'. msg.modoverwt Mòdul de destino '%s' existeix. ¿ Sobreescriure ? msg.foundgate Trobada porta denominada '%s'. msg.foundwire Trobat cable denominat '%s'. msg.searchagn Cadena destí '%s' no trobada. Fes clic a 'Cercar' per reiniciar la cerca. msg.sim.chgtoroot El mode simulació requereix el mòdul principal al capdamunt de la pila d'Edició. msg.sim.nogatemod Mode simulació requereix un mòdul concret de pila. msg.setinterface Ajustar l'interficie del mòdul per '%s'. msg.needsel Per favor selecciona una instància de mòdul. msg.wroteckpt Comprova punt a %s... msg.save Salva circuit com a '%s'. msg.badsave Falla fitxer de sortida '%s'. msg.reallynew El circuit s'ha modificat. ¿ Realment vols perdre els canvis i crear un de nou ? msg.reallyquit El circuit s'ha modificat. ¿ Realment vols sortir ? msg.notlib '%s' no és un mòdul de llibreria. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Només un tarat col·locaria %s%s aquí, Miles. miles.msg2 És realment un estúpid lloc on col·locar %s%s, Miles. miles.msg3 És un lloc horrible per a col·locar %s%s, Miles. miles.msg4 Miles, deus estar malament del cap si col·loques %s%s aquí. miles.msg5 Només tú pots col·locar %s%s aquí, Miles. miles.msg6 Col·locar %s%s aquí es una proba més de que ets absolutament estúpid, Miles. miles.msg7 No saps què coi fas, Miles, es un circuit estúpid. miles.msg8a És inútil continuar, Miles. miles.msg8b És obvi que no pots dissenyar un circuit. ############################################################################## # Balloon Help # ho.new -begin- Esborra el circuit actual i n'edita un de nou. -end- ho.open Fitxer -> Circuit ho.save Circuit -> Fitxer actual ho.print Circuit -> Impressora ho.move -begin- Move/Connect - Fent clic i arrossegant el mouse pots: Ajustar la posició d'una porta recent inserida. Moure portes y connexions ja col·locades Connectar cables entre potes de portes Fent doble-clic pots: Editar les propietats de portes, connexions i ports Editar el text dels comentaris -end- ho.delgat -begin- Esborrar porta - Usa aquesta eina per esborrar les portes. -end- ho.cutw -begin- Talla cables - Usa aquesta eina per desconnectar cables. -end- ho.inv -begin- Invertir - Usa aquesta eina per inserir o esborrar inversions de les potes de les portes. -end- ho.bitw -begin- Amplada del Bus - Usa aquesta eina per canviar el número de línies del Bus. Introdueix l'esmentat nombre en la part inferior dreta de la finestra. -end- ho.modopen Obre el mòdul seleccionat. ho.modclose Tanca el mòdul actual. ho.simgo -begin- Si no estem simulant, inicia la simulació y executa qualsevol guió d'inicializació. Si estem simulant, es col·loca en mode continu o interactiu. -end- ho.simpause -begin- Atura la simulació en curs. -end- ho.simstep -begin- Avança la simulació un interval de temps fix. Obre el submenú Opcions de simulació per ajustar-lo. -end- ho.simclock -begin- Avança la simulació un nombre fix de cicles de rellotge. Obre el submenú Opcions de simulació per ajustarlo. -end- ho.simstop -begin- Finalitza la simulació en curs i retorna al mode d'Edició. -end- ho.simbreak -begin- Edita els punts de ruptura. La simulació s'aturarà quan la condició especificada sigui certa. -end- ho.simexec Executa un guió de simulació. ho.simload -begin- Carrega la memòria amb el contingut d'un fitxer amb extensió .mem. -end- ho.simdump -begin- Emmagatzema el contingut de la memòria en un fitxer amb extensió .mem. -end- ho.sim.break -begin- Introdueix un punt de ruptura. Un punt de ruptura és una expressió que atura la simulació quan l'avaluació resulta certa. Les expressions suportades per el programa son del tipus operador lògic simple : "w1 == 0" o "w7 != 8". També es contemplen expressions en les que es nega la connexió: "!w2". -end- ho.f.modlist -begin- Llista tots els mòduls actualment carregats. El mòdul principal, el superior en la jerarquia, s'indica amb el signe "+". Els mòduls de llibreria es visualitzen entre parèntesi. -end- ho.netlist -begin- Llista totes les connexions del mòdul actual. Connexions marcades amb el signe "@" no presenten el seu nom en l'esquema (connexions ocultes). Les connexions BUS van seguides del nombre de línies que posseeixen. -end- ho.ports -begin- Llista totes les potes del mòdul actual El signe '>' indica l'entrada, '<' indica la sortida, i '=' indica línia bidireccional. -end- ho.status.logo -begin- Estat de la simulació. Si es presenta una porta de ferro estem en el mode d'Edició. Si es presenta una porta AND amb quatre potes estem en mode de simulació. Si la porta és estàtica, la simulació està aturada i si està en moviment, la simulació està en ple funcionamient. -end- ho.status.msg Els missatges del programa es presenten aquí. ho.status.block La pila de mòduls que estan essent editats. ho.status.file -begin- Fitxer actualment editat. El signe '*' indica que el buffer s'ha modificat des de l'últim cop que el fitxer que s'ha desat al disc. -end- ho.print.selall Imprimir tots els mòduls actualment carregats en TKGate. ho.print.selcur Imprimir només el mòdul present en la finestra d'Edició de TKGate. ho.print.seluse -begin- Imprimeix tots els mòduls "en ús". Els mòduls en ús son aquells que descendeixen del principal seguint la jerarquia d'arbre. -end- ho.print.selsel -begin- Imprimeix només els mòduls seleccionats més a sota. Usa la tecla CONTROL per seleccionar més d'un. -end- ho.print.modlist Selecciona els mòduls a imprimir. ho.circuit.discchg -begin- TkGate no presenta un avís si descartes els canvis sense salvar. -end- ho.cmd.bitw -begin- Els cables seleccionats amb el cursor poden ajustar-se a aquesta amplada de Bus. -end- ho.edgat.signam -begin- El nom del senyal seleccionat a la porta. Pots canviar aquest nom editant aquí. -end- ho.edgat.port -begin- El nom de la pota per aquesta senyal en aquesta porta. Aquest camp només pot ser editat per instàncies de mòduls. -end- ho.edgat.iolab -begin- La direcció del senyal seleccionat d'aquesta porta. Aquest camp només pot editar-se en les instàncies de mòduls. -end- ho.edgat.bitlab -begin- L'amplada del Bus de la senyal seleccionada d' aquesta porta. Es pot canviar editant aquí. -end- ho.edgat.cycle El nombre total de períodes de temps en un cicle de rellotge. ho.edgat.phase El punt inicial del cicle (en %). ho.edgat.duty El % del cicle que el rellotge està en flanc de baixada. ho.edgat.cname Nom de la connexió a la que s'uneix. ho.edgat.cport Pota de la connexió a la que s'uneix. ho.edgat.ctype Tipus de connexió. ho.edgat.cbitw Amplada del Bus de la connexió a la que s'uneix. ho.edgat.cedit Edita la pota seleccionada. ho.edgat.cadd Afegeix una pota. ho.edgat.cdel Borra la pota seleccionada. ho.edgat.hide -begin- Activa aquest flag per no visualitzar el nom de la porta. -end- ho.edgat.gtype Tipus de porta. ho.edgat.gname Nom d'aquesta instància de porta. ho.edgat.ganchor Activa aquest flag per anclar la posició de la porta. ho.edgat.gx Coordenada X de la porta. ho.edgat.gy Coordenada Y de la porta. ho.edgat.swstate -begin- Estat inicial del commutador quan s'inicia una sessió de simulació. -end- ho.edgat.dipstate -begin- Estat inicial dels interruptors DIP quan s'inicia una sessió de simulació. -end- ho.edgat.range El rang de bits a col·locar en un bus. ho.edgat.memfile -begin- El fitxer amb l'estat inicial d'aquesta memòria. Aquest fitxer es llegeix quan s'inicia el Simulador. -end- ho.edgat.func El tipus de funció d'aquest mòdul. ho.edgat.frame L'etiqueta del plafó. ho.opt.site -begin- El nom del lloc on tkgate s'ha instal·lat. S'usa en la sortida impresa o fitxer postscript. -end- ho.opt.smooth -begin- Si aquesta opció està habilitada, el desplaçament s'optimitza al usar copies bitmap en comptes d'un re-dibuixat complert. Pots desactivar-la si hi ha problemes amb el seu servidor. -end- ho.opt.clip -begin- Si aquesta opció està habilitada, s'actualitza només la regió realment exposada de l'entorno d'Edició. En cas contrari, es re-dibuixa tot. -end- ho.opt.outmove -begin- Si aquesta opció està habilitada, només un requadre que envolta a les instàncies de mòduls es dibuixa mentre s'arrossega aquest. Usa aquesta opció en les màquines amb microprocessadors i tarjes gràfiques lentes. -end- ho.opt.bhelp -begin- Si aquesta opció està habilitada, els globus d'ajuda s'activen. Els globus d'ajuda, com aquest mateix, proporcionen una ajuda resumida sobre els elements de la interficie, quan el mouse hi passa per sobre. -end- ho.opt.novice -begin- Si no s'especifica cap circuit en la línia de comandes, TkGate presenta un tutorial per iniciar-se amb l'ús del programa. -end- ho.opt.debug -begin- Habilita algunes opcions de depuració. Només es útil per a programadors del TkGate. -end- ho.opt.ckpt Habilitar els punts de chequeig per circuits no salvats. ho.opt.ckptfreq Freqüència dels punts de chequeig en segons. ho.opt.beak -begin- Habilitar totes aquestes opcions. Si deshabilita aquesta opció, aquests modes (i aquesta caixa de diàleg) no apareix en el menú opcions. Només pot recuperar-se editant el fitxer .tkgate-properties. -end- ho.opt.miles -begin- Si aquest mode està habilitat, el programa insulta periòdicament la intel·ligència de l'usuari. -end- ho.opt.bat -begin- Si aquest mode està habilitat, el programa activarà l'entorn per dissenyar un computador senzill a partir de mòduls. -end- ho.opt.trek Ajuda Scoty! ho.opt.normal Fora conyes. ho.opt.simstep -begin- El nombre de períodes de temps que avancem si hem activat el mode pas a pas per temps. -end- ho.opt.ckstep -begin- El nombre de cicles de rellotge que avancem si hem activat el mode pas a pas per nº de cicles. -end- ho.opt.ckover -begin- El nombre de períodes de temps després d'un flanc de baixada de rellotge que avancem si hem activat el mode pas a pas. -end- ho.opt.init -begin- El fitxer de guió que s'executa de forma automàtica al iniciar la simulació. -end- ho.opt.ckall -begin- Si aquest mode s'habilita, la comanda pas a pas ?¿?¿? la simulació en el flanc de pujada de qualssevol rellotge present en el circuit. -end- ho.opt.ckspec -begin- Si aquest mode està habilitat, la comanda pas a pas ?¿¿?¿ la simulació es el flanc de pujada de la senyal de rellotge especificada. -end- ho.deftech -begin- La tecnologia per defecte emprada per las portes recent creades. Afecta al temps de retard de les portes. Per canviar la tecnologia d'una porta específica, obrir la caixa de propietats (doble clic) i seleccionar "Retard". -end- ho.techbut -begin- Usa retards per la tecnologia estàndard d'un fitxer de definició. Per afegir tecnologies personalitzades, afegir-les a la llista del menú "Fitxer -> Opcions -> Simulador". -end- ho.custbut -begin- Ajustar valors de retards personalitzats per aquesta porta. -end- ho.simwatch -begin- Visualitzar comandes enviades entre l'entorn de visualització (GUI) i el simulador. -end- ho.simlog -begin- Escriu comandes emeses pel simulador a un log. Aquest log pot usar-se com a fitxer d'entrada al simulador en la depuració. -end- ho.cpathanal -begin- Toba camins crítics en el circuit. -end- undo Desfer redo Refer simadprobe Afegir/Esborrar Probe db.gate.exttbar Usar barres exteses opt.contver Comprovació d'integritat automàtica opt.vpopupdelay Retard en mostrar el valor opt.undolen Màx nivell de desfer circ.extbar Usar barres exteses err.badid Identificador '%s' Il·legal. err.badportadd No es poden afegir ports a portes d'aquest tipus. err.badportdel El port sel·leccionat no pot ser esborrat. err.badportedit El port sel·leccionat no pot ser editat. err.noport Cap port seleccionat. err.oldportact Siusplau, clica amb el botó dret al port o pestanya del mòdul per afegir/canviar port. ho.undo Desfés la/les acció(ns) anterior(s) ho.redo Refés la/les accio(ns). ho.edgat.extbar -begin- Si està activat, les portes bàsiques amb vàries entrades usaran barres extensores a les entrades. -end- ho.opt.undolen -begin- Defineix el màxim nombre de nivells de desfer. -end- db.gate.extbar Usar barres extensores ho.circuit.extbar -begin- Les portes bàsiques (AND, OR, XOR) usaran barres extensores per agrupar vàries portes d'entrada. -end- ho.opt.vpopupdelay -begin- El retard en milisegons que es triga a mostrar el valor del senyal. En alguns sistemes, valors petits poden causar problemes a l'hora de detectar el doble clic. Si tens aquest problema, augmenta el valor del retard. Es permeten valors entre 1 i 10000. -end- ho.contver -begin- Verificar contínuament la integritat de les estructures de dades internes despres de cada operació. -end- tkgate-2.0-b10/locale/de/tutorials000777 001751 001751 00000000000 11150636025 017607 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/tutorials.18000777 001751 001751 00000000000 11145151105 020031 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples000777 001751 001751 00000000000 11145151105 017372 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18000777 001751 001751 00000000000 11145151105 017621 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/messages.bak2000644 001751 001751 00000264523 11140052502 020207 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by bartke Mi 28. Jan 10:41:16 CET 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## \font-encoding iso8859-1 \messages-encoding utf-8 \verilog-encoding iso8859-1 \postscript-encoding iso8859-1 \display-encoding iso8859-1 \language German ############################################################################## # # basic strings # b.new Neu... b.dismiss Beenden b.close Schließen b.ok OK b.clear Clear b.cancel Abbrechen #b.open Öffnen... #b.bitw Bitbreite b.in Eingang b.out Ausgang b.inout Bidirektional b.browse Durchsuchen... b.label Marke b.find Suchen b.edit Editieren... b.add Hinzufügen... b.delete Löschen #b.deleteb Löschen... b.remove Entfernen b.apply Anwenden b.anchor Anker b.tech Technologie #b.enable Freischalten #b.disable Sperren #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editieren tab.editintr Schnittstelle tab.simulate Simulieren tab.cpath Kritischer Pfad ############################################################################ # # Module tabs # module.tree Baum module.list Liste module.box.libraries Bibliotheken ############################################################################ # # Tabs for Nets/Ports # sidetab.nets Netze sidetab.ports Ports ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Hinzufügen... mm.delete Löschen mm.edit Editieren... mm.enable Freischalten mm.disable Sperren ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:Datei menu.edit 0:Editieren menu.tool 0:Werkzeug menu.symbol 0:Symbol menu.simulate 0:Simulieren menu.module 0:Modul menu.interface 0:Schnittstelle menu.format 0:Gatter menu.make 0:Bausteine menu.help 0:Hilfe menu.file.new 0:Neu... menu.file.open 1:Öffnen... menu.file.openlib 3:Bibliotheksmanager... menu.file.save 0:Sichern menu.file.saveas 8:Sichern unter... menu.file.print 0:Drucken... menu.file.quit 0:Quit menu.file.cprop 10:Schaltungseigenschaften... menu.file.import 0:Bild Import... menu.file.export 0:Bild Export... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Trennen menu.edit.copy 0:Kopieren menu.edit.paste 0:Einfügen menu.edit.overlay 1:Overlay einfügen menu.edit.selall 1:Alles auswählen menu.edit.find 0:Suchen... menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 16:Bitverschiebung Rechts menu.edit.lshift 16:Bitverschiebung Links menu.edit.ushift 16:Bitverschiebung Auf menu.edit.dshift 17:Bitverschiebung Ab menu.edit.cwrotate 11:Bitrotieren rechts menu.edit.ccwrotate 15:Bitrotieren links menu.edit.pcwrotate 12:Portrotieren rechts menu.edit.pccwrotate 16:Portrotieren links menu.edit.autobold Bits fett anzeigen menu.edit.resize Bitmapgröße anpassen menu.tool.move 0:Bewegen/Verbinden menu.tool.delg 0:Gatter löschen menu.tool.cutw 0:Leitung trennen menu.tool.inv 0:Invertieren menu.tool.bitw 0:Bitbreite menu.tool.debug 0:Debug menu.tool.point 0:Punkt menu.tool.line 0:Gerade menu.tool.rect 0:Rechteck menu.tool.fillrect 0:Rechteck füllen menu.tool.port 0:Port menu.tool.select 0:Gebiet auswählen menu.tool.options 0:Optionen... menu.format.addport 4:Port hinzufügen menu.format.ioset 0:Typ setzen menu.format.anchor 0:Verankern (ausgewählt) menu.format.unanchor 0:Anker los (ausgewählt) menu.format.prop 0:Instanzeigenschaften... menu.format.del 0:Löschen menu.format.settech 0:Technologie festlegen menu.format.rot 0:Rotation menu.format.rot.0 15:Default Drehen 0 menu.format.rot.90 15:Default Drehen 90 menu.format.rot.180 15:Default Drehen 180 menu.format.rot.270 15:Default Drehen 270 menu.format.rot.rotate 0:Uhrzeigersinn drehen menu.format.rot.brotate 0:Gegenuhrzeigersinn drehen menu.format.algnv 11:Ausrichten Ver. menu.format.algnh 11:Ausrichten Hor. menu.tool.tclshell 0:Tcl Shell menu.tool.rep 0:Replizieren menu.simulate.begin 0:Beginn Simulation menu.simulate.end 0:Ende Simulation menu.simulate.addprobe 0:Tastkopf hinzufügen/löschen menu.simulate.run 0:Laufen lassen menu.simulate.pause 0:Pause menu.simulate.step 0:Epochenschritt(e) menu.simulate.cycle 5:Periodenschritt(e) menu.simulate.break 0:Haltepunkt... menu.simulate.script 1:Skript ausführen... menu.simulate.load 16:Speicherbereich laden... menu.simulate.dump 16:Speicherbereich ausgeben... menu.module.open 0:Öffnen menu.module.close 0:Schließen menu.module.new 0:Neu... menu.module.del 0:Löschen... menu.module.copy 0:Kopieren... menu.module.rename 0:Umbenennen... menu.module.claim 1:Aneignen... menu.module.setroot 1:Zur Wurzel machen... menu.module.prop 0:Eigenschaften... menu.module.interface 0:Schnittstelle menu.module.interface.set 0:Definieren menu.module.interface.update 0:Mit Standard synchr. menu.module.interface.updateall 0:Alles mit Std. synchr... menu.module.interface.edit 0:Editieren... menu.module.interface.auto 1:Automatisch erzeugen... menu.help.about 0:Autor... menu.help.license 0:Lizenz... menu.help.doc 0:Dokumentation... menu.help.tut 0:Tutorien menu.help.home 0:Startseite menu.help.example 0:Beispiele ############################################################################# # Scope Menu # menu.scope_file 0:Datei menu.scope_sim 0:Simulieren menu.scope_trace 0:Signaldiagramm menu.scope_help 0:Hilfe menu.scope_file.ptrace 0:Drucken Signaldiagramm... menu.scope_file.close 0:Schließen menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Tastkopf hinzufügen/löschen menu.scope_sim.run 0:Laufen lassen menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Epochenschritt(e) menu.scope_sim.cycle 5:Periodenschritt(e) menu.scope_sim.break 0:Haltepunkt... menu.scope_sim.script 1:Skript ausführen... menu.scope_sim.load 16:Speicherbereich laden... menu.scope_sim.dump 16:Speicherbereich ausgeben... menu.scope_help.about 0:Autor... menu.scope_help.license 0:Lizenz... menu.scope_help.doc 0:Dokumentation... mod.intf Schnittstelle port.title TkGate: Porteigenschaften port.parms Portparameter port.in Eingang port.out Ausgang port.inout Ein/Ausgang ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gatter gm.rgate Reduktion gm.msi MSI gm.alu ALU gm.mem Speicher gm.mod Module gm.comment Kommentar gm.frame Rahmen gm.io.switch Schalter gm.io.dip DIP Schalter gm.io.ground Masse gm.io.vdd Vdd gm.io.merge Zusammenführen gm.io.clock Taktgeber gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direkt) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Puffer gm.gate.inv Inverter gm.gate.tribuf Tri-Puffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Addierer gm.alu.mult Multiplizierer gm.alu.div Dividierer gm.alu.lshift Linksshift gm.alu.rshift Rechtsshift gm.alu.arshift Arith. Rechtsshift gm.alu.roll Zyklischer Shift gm.mem.reg Register gm.mem.ff Flip-Flop gm.mem.rff Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK Flip-Flop gm.mem.rjkff Rev. JK Flip-Flop gm.msi.21mux 2-1 Multiplexer gm.msi.41mux 4-1 Multiplexer gm.msi.81mux 8-1 Multiplexer gm.msi.12dec 1-2 Dekoder gm.msi.14dec 1-4 Dekoder gm.msi.18dec 1-8 Dekoder gm.msi.12demux 1-2 Demultiplexer gm.msi.14demux 1-4 Demultiplexer gm.msi.18demux 1-8 Demultiplexer gm.mod.inst Module Instanz gm.mod.in Module Eingang gm.mod.out Module Ausgang gm.mod.inout Module Ein/Ausgang tutorial.prev ZURÃœCK tutorial.next WEITER tutorial.chapter INHALTSVERZEICHNIS tutorial.reload NEU LADEN ############################################################################## # # Popup menus # pop.make Bausteine pop.tool Werkzeug pop.edit.paste Einfügen pop.edit.cut Trennen pop.edit.copy Kopieren pop.port.in Eingang pop.port.out Ausgang pop.port.inout Ein/Ausgang pop.wire.addseg Leitungssegment hinzufügen pop.wire.prop Schaltungseigenschaften... pop.wire.hidesize Bitbreite verstecken pop.wire.showsize Bitbreite anzeigen pop.wire.hidelabel Namen verstecken pop.wire.hidealllabel Alle Namen verstecken pop.wire.clearalllabel Alle Namen löschen pop.wire.showlabel Namen anzeigen pop.gate.open Öffnen pop.gate.close Schließen pop.gate.prop Instanzeigenschaften... pop.gate.addport Port hinzufügen pop.gate.addin Eingang hinzufügen... pop.gate.addout Ausgang hinzufügen... pop.gate.addinout Ein/Ausgang hinzufügen... pop.gate.anchor Verankern/Loslösen pop.gate.settech Technologie festlegen pop.gate.delete Löschen pop.gate.ioset Typ festlegen pop.module.new Neu... pop.module.del Löschen... pop.module.copy Kopieren... pop.module.rename Umbenennen... pop.module.claim Aneignen... pop.module.setroot Als Wurzel festlegen... pop.module.prop Moduleigenschaften... pop.module.int Schnittstelle editieren... pop.simulate.end Ende Simulation pop.simulate.begin BeginN Simulation pop.simulate.addprobe Tastkopf hinzufügen pop.simulate.delprobe Tastkopf löschen pop.simulate.run Laufen lassen pop.simulate.pause Pause pop.simulate.step Epochenschritt(e) pop.simulate.cycle Periodenschritt(e) pop.simulate.break Haltepunkt... pop.simulate.script Skript ausführen... pop.simulate.load Speicherbereich laden... pop.simulate.dump Speicherbereich ausgeben... pop.interface Schnittstelle pop.interface.set Als Standard setzen pop.interface.update Abgleichen mit Standard pop.interface.updateall Alles abgleichen mit Standard... pop.interface.edit Editieren... pop.interface.auto Automatisch erzeugen... pop.interface.replace Ersetzen pop.igen.type Typ pop.igen.side Seite pop.igen.size Größe pop.igen.delete Löschen pop.igen.in Eingang pop.igen.out Ausgang pop.igen.inout Ein/Ausgang pop.igen.left links pop.igen.right rechts pop.igen.top oben pop.igen.bottom unten pop.igen.other sonstige pop.library.mgr Bibliotheksmanager... pop.library.close Schließen ############################################################################## # # Symbol editor strings # #symed.bsave Speichern #symed.file Datei #symed.file.load Bitmap laden... #symed.file.save Bitmap sichern... #symed.file.updateclose Auffrischen und schließen #symed.file.discardclose Verwerfen und schließen #symed.help Hilfe #symed.help.about Zu... #symed.edit Editieren #symed.edit.cut Trennen #symed.edit.copy Kopieren #symed.edit.paste Einfügen #symed.edit.overlay Overlay einfügen #symed.edit.rclock Rechts drehen #symed.edit.rcclock Links drehen #symed.module Modul #symed.modes Modes #symed.cutpaste Ausschneiden/Einfügen #symed.rotate Port drehen #symed.zoom Zoom #symed.cancel Abbrechen #symed.update Auffrischen symed.tab.normal Nicht ausgewählt symed.tab.select Ausgewählt symed.link Ausgewähltes mit Unausgewähltem verlinken # width of symbol editor tabs ############################################################################## scope.emptymsg Doppelklick auf eine Leitung fügt ein Signal ein oder löscht es comment.empty [Text hinzufügen mit Doppelklick.] ############################################################################## # Interface strings # ifile Datei imodule Modul iblmodule Module iports Ports ibits Bits: itype Typ: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file Dateiname db.mod.type Typ db.mod.flags Flags db.mod.dataprot Editieren der Moduldefinition verhindern. db.mod.intfprot Schnittstellenveränderungen verhindern. db.mod.edprot Schnittstellenveränderungen im Editiermodus verhindern. db.mod.props Eigenschaften db.mod.inuse.0 Modul wird nicht benutzt. db.mod.inuse.1 Modul wird benutzt. db.mod.lmod.0 Modul seit dem Laden nicht verändert. db.mod.lmod.1 Modul seit dem Laden verändert. db.mod.smod.0 Modul seit dem Sichern nicht verändert. db.mod.smod.1 Modul seit dem Sichern verändert. db.mod.islib.1 Modul ist Teil der [%s] Bibliothek. db.mod.islib.0 Modul ist kein Bibliotheksmodul. db.mod.netlist Bauteilliste db.mod.hdl HDL db.mod.netexpl -begin- Moduldefinition mit einem graphischen Editor, um Leitungen zwischen Komponenten zu ziehen -end- db.mod.hdlexpl -begin- Moduldefinition mit einem Texteditor, um das Verhalten in Verilog zu beschreiben. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Fehlerliste db.err.caption Fehlerliste db.err.explain.warn -fillbegin- In der Schaltung gab es Warnhinweise, die Simulation wird aber fortgesetzt. Im Editiermodus kann man die Warnhinweise sehen. -end- db.err.explain.err -fillbegin- In der Schaltung gab es Fehler. TkGate kann die Simulation nicht fortsetzen. -end- db.err.neededit -fillbegin- Zum Navigieren zu den Warnungen muß erst in den Editiermodus geschaltet werden. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Netzeigenschaften db.net.caption Netzeigenschaften db.net.name Netzname db.net.hide Name verstecken db.net.bits Bitbreite db.net.type Netztyp db.net.port Porttyp db.net.in Eingang db.net.out Ausgang db.net.inout Ein/Ausgang db.net.inets Netze ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: Neue Schaltung db.newcirc.directory Verzeichnis: db.newcirc.cap Neue Schaltung db.newcirc.exp -fillbegin- Die aktuelle Schaltung verwerfen und eine neue Schaltung bearbeiten. -end- db.newcirc.file Dateiname db.newcirc.topname Name des obersten Moduls ############################################################################## # Gate dialog box # db.gate.title TKGate: Gattereigenschaften db.gate.signam Signalname db.gate.portnam Portname db.gate.iotype Typ db.gate.bitw Bitbreite db.gate.cyclew Taktlänge db.gate.phase Phase db.gate.duty Taktverhältnis db.gate.waveform Takt-Signalform db.gate.port Port db.gate.bitws Bits db.gate.side Seite db.gate.gtype Gattertyp db.gate.gname Gattername db.gate.hidenam Namen verstecken db.gate.anchor Verankern db.gate.cpbreak Aufteilung des kritischen Pfades db.gate.butstate Schalterzustand db.gate.dipval Schalterstellung db.gate.range Bitbereich db.gate.memfilenam Dateiname f. Speicherinhalt db.gate.modname Funktion db.gate.general Allgemein db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Verzögerung db.gate.parameters Parameter db.gate.stddelay Standardverzögerung db.gate.custdelay Einstellen der Verzögerung db.gate.catdiruse Platzieren des Ports db.gate.edit Editieren db.gate.delete Löschen db.gate.add Hinzufügen db.gate.ff.type Flip-Flop Ausrichtung db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- Datenfluß im Flip-Flop von links nach rechts. -end- db.gate.ff.reverse.hdr Umgekehrt db.gate.ff.reverse.exp -fillbegin- Datenfluß im Flip-Flop von rechts nach links. -end- db.gate.jkff.type JK Flip-Flop Ausrichtung db.gate.jkff.normal.hdr Normal db.gate.jkff.normal.exp -fillbegin- Datenfluß im JK Flip-Flop von links nach rechts. -end- db.gate.jkff.reverse.hdr Reversed db.gate.jkff.reverse.exp -fillbegin- Datenfluß im JK Flip-Flop von rechts nach links. -end- db.gate.cat.asc.hdr Aufsteigend db.gate.cat.dec.hdr Absteigend db.gate.cat.asc.exp -fillbegin- Bits werden in aufsteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.dec.exp -fillbegin- Bits werden in absteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.sigdir Signalrichtung db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Mehrfacheingang db.gate.cat.singin.hdr Einzelner Eingang db.gate.cat.tran.hdr Bidirektional db.gate.cat.auto.exp -fillbegin- Die Signalrichtung wird automatisch aus den verbundenen Teilschaltungen erschlossen. -end- db.gate.cat.multin.exp -fillbegin- Die Seite mit Mehrfachleitung wird immer als Eingang angenommen. -end- db.gate.cat.singin.exp -fillbegin- Die Seite mit der Einzelleitung wird immer als Eingang angenommen. -end- db.gate.cat.tran.exp -fillbegin- Bidirektionaler Signalfluß (transmission) ist erlaubt. Kann nicht mit Schaltern oder Registern verbunden werden. -end- # Minimum size of textbox for comment (in characters) # @db.gate.comment.width *900 @db.gate.comment.height *550 db.gate.tab.General.cap Allgemeine Eigenschaften db.gate.tab.Ports.cap Porteigenschaften db.gate.tab.Delay.cap Eigenschaften der Verzögerung db.gate.tab.Parameters.cap Modulparameter db.gate.tab.CLOCK.cap Takteigenschaften db.gate.tab.SWITCH.cap Schaltereigenschaften db.gate.tab.DIP.cap DIP Eigenschaften db.gate.tab.TAP.cap Tran Eigenschaften db.gate.tab.RAM.cap RAM Eigenschaften db.gate.tab.ROM.cap ROM Eigenschaften db.gate.tab.MODULE.cap Moduleigenschaften db.gate.tab.FRAME.cap Rahmeneigenschaften db.gate.tab.LED.cap LED Eigenschaften db.gate.tab.AND.cap AND Eigenschaften db.gate.tab.OR.cap OR Eigenschaften db.gate.tab.XOR.cap XOR Eigenschaften db.gate.tab.MUX.cap Mux Eigenschaften db.gate.tab.DEMUX.cap Demux Eigenschaften db.gate.tab.DECODER.cap Decoder Eigenschaften db.gate.tab.CONCAT.cap Concat Eigenschaften db.gate.tab.COMMENT.cap Text Eigenschaften db.gate.tab.FF.cap Flip-Flop Eigenschaften db.gate.tab.General.exp -fillbegin- Die grundlegenden Eigenschaften einer Instanz ansehen und verändern. -end- db.gate.tab.Ports.exp -fillbegin- Hinzufügen, Editieren oder Löschen von Ports einer Instanz. -end- db.gate.tab.Delay.exp -fillbegin- Die Verzögerung kann entweder durch Angabe der Technologie oder durch spezielle Werte für diese Instanz festgelegt werden. -end- db.gate.tab.Parameters.exp -fillbegin- Festlegen der Modulparameter dieser Modulinstanz, falls welche definiert sind. Modulparameter werden zur Definition von Verzögerungen und konstanten Werten in Moduln verwendet. -end- db.gate.tab.details.exp -fillbegin- Genaue Festlegung der typspezifischen Eigenschaften eines Gatters. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Definition des Textes in einem Kommentar. Es können in beschränktem Umfang HTML Tags einschließlich Links verwendet werden. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Wert db.gate.mparm.exampleA -begin- Dieses Modul hat keinerlei Parameter. Parameter können zu Verilog-Textmodulen hinzugefügt werden. Dert Wert jedes Parameters kann für jede Instanz durch diese Dialogbox konfiguriert werden. Modul- Parameter werden als geklammerte Liste deklariert, die mit einem # beginnt. Hier ist ein Beispiel einer Moduldeklaration mit einem Parameter namens "base_value", der einen Standardwert von 1'b1 besitzt. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.switch.state Initiale Schalterstellung db.gate.switch.state.on.hdr Schalter Ein db.gate.switch.state.on.exp Schalter beginnt Simulation im Ein-Zustand. db.gate.switch.state.off.hdr Schalter Aus db.gate.switch.state.off.exp Schalter beginnt Simulation im Aus-Zustand. db.gate.dip.value Initialer DIP-Schalter-Wert db.gate.dip.value.exp Initialer Wert des DIP-Schalters zu Simulationsbeginn. db.gate.dip.value.hex Hexwert: @db.gate.dip.value.exp.width 150 db.gate.tap.select Auswahl der Bitverzweigung db.gate.tap.exp.bit Wähle das Bit aus, das aus dem Multibit-Bus herausgeführt werden soll. db.gate.tap.exp.bus Wähle das niederwertigste Bit (LSB) aus dem Bitbereich und führe es aus dem Multibit-Bus heraus. db.gate.tap.lbl.bit Bit: db.gate.tap.lbl.bus LSB: @db.gate.tap.exp.width *180 db.gate.mux.dataorder Eingangsordnung db.gate.mux.ord1.hdr Links-rechts db.gate.mux.ord2.hdr Rechts-links db.gate.mux.ord1.exp -fillbegin- Ordne MUX-Eingänge von links nach rechts. -end- db.gate.mux.ord2.exp -fillbegin- Ordne MUX-Eingänge von rechts nach links. -end- db.gate.mux.select Auswahlstil db.gate.mux.sel1.hdr Selektor links db.gate.mux.sel2.hdr Selektor rechts db.gate.mux.sel1.exp -fillbegin- Setze den Datenselektor auf der linken Seite des Gatters. -end- db.gate.mux.sel2.exp -fillbegin- Setze den Datenselektor auf der rechten Seite des Gatters. -end- db.gate.demux.dataorder Ausgangsordnung db.gate.demux.ord1.hdr Links-rechts db.gate.demux.ord2.hdr Rechts-links db.gate.demux.ord1.exp -fillbegin- Ordne DEMUX-Ausgänge von links nach rechts. -end- db.gate.demux.ord2.exp -fillbegin- Ordne DEMUX-Ausgänge von rechts nach links. -end- db.gate.demux.select Wähle die Positionierung db.gate.demux.sel1.hdr Auf der Linken db.gate.demux.sel2.hdr Auf der Rechten db.gate.demux.sel1.exp -fillbegin- Plaziere den Select-Eingang auf der linken Seite des DEMUX. -end- db.gate.demux.sel2.exp -fillbegin- Plaziere den Select-Eingang auf der rechten Seite des DEMUX. -end- db.gate.decoder.dataorder Ausgangsreihenfolge db.gate.decoder.ord1.hdr Links-nach-rechts db.gate.decoder.ord2.hdr Rechts-nach-links db.gate.decoder.ord1.exp -fillbegin- Ordne die Decoderausgänge von links nach rechts. -end- db.gate.decoder.ord2.exp -fillbegin- Ordne die Decoderausgänge von rechts nach links. -end- db.gate.decoder.select Plazierung des Enable-Eingangs db.gate.decoder.sel1.hdr Links db.gate.decoder.sel2.hdr Rechts db.gate.decoder.sel1.exp -fillbegin- Plaziere den Enable-Eingang auf der linken DECODER-Seite. -end- db.gate.decoder.sel2.exp -fillbegin- Plaziere den Enable-Eingang auf der rechten DECODER-Seite. -end- db.gate.aox.extbaruse Nutzung von Erweiterungsbalken db.gate.aox.use.hdr Erweiterungsbalken db.gate.aox.nouse.hdr Keine Erweiterungsbalken db.gate.aox.use.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden diese an Erweiterungsbalken angebracht. -end- db.gate.aox.nouse.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden keine Erweiterungsbalken verwendet. -end- db.gate.led.type LED Typ db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Balkenanzeige db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direkt) db.gate.led.bit.exp -fillbegin- Einzelne LED-Anzeige für 1-Bit-Signale. -end- db.gate.led.bar.exp -fillbegin- LED Balkenanzeige mit einem Balken pro Bit. -end- db.gate.led.hex.exp -fillbegin- Hexadezimale Anzeige des Signals. -end- db.gate.led.dec.exp -fillbegin- Dezimale Anzeige des Signals. -end- db.gate.led.seg.exp -fillbegin- Die Signalbits steuern direkt die LED-Segmente a-g. -end- db.seq.back db.hdl.namechange.title HDL Modulname geändert db.hdl.textdisp.title HDL Textdisposition db.hdl.savecap Mehrfach-Module db.hdl.saveexp -fillbegin- Der Textpuffer des gerade editierten Moduls enthält mehr als eine Moduldefinition. Bitte wähle eine der drei Aktionen auf der rechten Seite aus. -end- db.hdl.autoedit Auto-Editieren db.hdl.split Aufteilen db.hdl.comment Kommentar db.hdl.cancel Abbrechen db.hdl.ignore Ignorieren db.hdl.autoeditcap Der Name paßt nicht db.hdl.autoeditexp -fillbegin- Die Textbeschreibung des Moduls paßt nicht zum erwarteten Namen. Wähle eine der Optionen rechts, um dieses Problem zu beseitigen. -end- db.dip.title TkGate: Dip-Wert cpath.cloops -fillbegin- In der kombinatorischen Schaltung wurde eine Rückkopplung entdeckt. Um für diese Schaltung eine Verzögerungsanalyse durchführen zu können, muß entweder die Rückkopplung aufgebrochen werden oder einige der Gatter im Rückkopplungszweig werden als "Kritische-Pfad-Aufteilung" markiert. Schaltungsteile, in denen eine Rückkopplung ent- deckt wurde, sind unten gelistet. -end- ############################################################################## # Print dialog box # #print.outto Ausgabe nach print.title TkGate: Drucken print.config.title TkGate: Druckerkonfiguration print.scope.title TkGate: Scopedruck print.printer Drucker: print.file Datei print.prcmd Druckbefehl: print.prname Drucker print.advanced Erweitert... print.filename Dateiname print.epssave Sichern als Encapsulated Postscript. #print.doctit Dokumenttitel #print.prmod Druck von Modulen print.epcm Epochen/cm print.estpg Ungefähre Seitenzahl print.all Alles print.cur Aktuelle print.use Benutzte print.sel Ausgewählte print.inclib Bibliotheksmodule einbeziehen. print.incunused Unbenutzte Module einfügen. print.papsz Papiergröße print.orient Orientierung print.portrait Hochformat print.landscape Querformat print.2side Duplexdruck print.opts Optionen print.scale Anpassen großer Module auf eine Seite. print.partition Aufteilen großer Module auf mehrere Seiten. print.incidx Index hinzufügen. print.incgraph Hierarchiegraph hinzufügen. print.4up Kleine Module: vier auf eine Seite drucken. print.rangeselection Wahl des Bereichs print.scaleselect Wahl der Skalierung print.fulltr Vollständiges Signaldiagramm print.parttr Ausschnitt aus dem Signaldiagramm print.start Start print.range Bereich print.linelen Zeilenlänge print.filesel Ausgabe in Datei print.printersel Ausgabe auf Drucker print.defaultprinter Standarddrucker print.pageset Seiteneinstellungen print.modulesel Modulauswahl ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Drucken print.printtrace.cap Signaldiagramm drucken print.printcirc.cap Schaltung drucken print.printcirc.out.exp -fillbegin- Wahl der Druckausgabe: direkt zum Drucker oder in eine PostScript-Datei. -end- print.printcirc.page.exp -fillbegin- Auswahl der Optionen für den Seitenaufbau und den Drucker. -end- print.printcirc.mod.exp -fillbegin- Auswahl der zu druckenden Module, Einstellung der Optionen für die Darstellung. -end- print.printtrace.trace.exp -fillbegin- Auswahl des Zeitbereichs für die Ausgabe und Einstellung der Skalierung, um die ungefähre Seitenzahl zu berechnen. -end- print.tab.output Ausgabe #print.tab.page Seite print.tab.modules Module print.tab.content Inhalt print.tab.advanced Einstellungen ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Optionen opt.treelabel Optionen opt.general Allgemein opt.interface Schnittstelle opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Drucken opt.print.output Ausgabe opt.print.content Inhalt opt.simulate Simulieren opt.simulate.basic Grundlegendes opt.simulate.tech Technologie opt.simulate.error Fehlerbehandlung opt.library Bibliotheken opt.library.path Pfad opt.library.load Autom. Laden opt.library.vpd VPD opt.analysis Analyse opt.color Farben opt.color.title TkGate: Farbauswahl opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Verfügbare Bibliotheken opt.lib.load.selected Ausgewählte Bibliotheken opt.identity Organisation opt.site Netzadresse opt.username Benutzername opt.libname Bibliotheksname: opt.inst Instanzen opt.mods Module opt.modports Modul-Ports opt.frames Rahmen opt.comment Kommentare opt.hlink Hyperlinks opt.wire Einfach-Leitungen opt.bus Mehrfachleitungen opt.tools Gatter-Werkzeuge opt.background Hintergrund opt.cpath Kritischer Pfad opt.grid Scope Raster opt.logic1 Logisch Eins opt.logic0 Logisch Null opt.float Float opt.unknown Unbekannt/Konflikt opt.offled LED aus opt.onled LED ein opt.zled Undefinierte LED opt.restdef Auf Standard zurücksetzen opt.regudate Auffrischen eines Gebiets opt.smoothscroll Glattes Scrolling opt.balloon Hilfeballone einschalten opt.tearawaymenus Einschalten von wegziehbaren Hauptmenues opt.safeSave Sicheres Abspeichern der Dateien opt.saveCells Zellen in abgespeicherte Dateien einbeziehen opt.showimage Zeige Randstreifenbilder in Dialogboxen opt.novice Novizenmodus opt.blockDropConnect Porterzeugung mit Fallenlassen von Leitungen opt.ckpoint.1 Checkpointing alle opt.ckpoint.2 Kommandos ausführen. opt.freq Intervall opt.beak Sondermodi einstellen opt.bat Bat opt.trek Star Trek opt.miles Heinrich opt.contver Automatische Integritätsprüfung opt.showsimcmd Anzeige der Simulationsgeschichte opt.estepsz Epochen Schrittweite opt.cstepsz Periodendauer Schrittweite opt.overstep Takt Ãœberschreitung opt.sorttraces Scope-Signale alphabetisch sortieren opt.vpopupdelay Pop-Up Verzögerungswert #opt.initscript Globales Initialisierungsskript opt.posedge Takt hält an allen positiven Flanken opt.setclock Takt hält an allen Flanken opt.delayfilepath Technologiedateien opt.devfilepath VPD (Virtuelles Peripheres Device) Dateipfad opt.vlibpath Verilog Bibliothekspfad opt.vlibnames Basisbibliotheken opt.display Anzeige opt.interaction Interaktion opt.input Eingabe opt.security Sicherheit opt.undolen Maximale Anzahl von Undo-Op. opt.keybind Tastaturbelegungsstil opt.useless Nutzlose Features einschalten opt.features Basis Features opt.simbase Grundlegende Simulatoroptionen opt.simclock Taktoptionen opt.cpopts Optionen für Kritische Pfade opt.maxpath Maximalzahl der Pfade: opt.cpflash Anzeige mit blinkendem Pfad opt.general.fontset Font-Klasse opt.simulator.savetraces Tastkopfpositionen zwischen Simulatorläufen sichern. opt.simulator.noglitch Glitch-Unterdrückung im Simulator einschalten. opt.simulator.err Fehlerbehandlung opt.simulator.stopany Abbrechen der Simulation bei jeder Warnung. opt.simulator.showall Warnungen immer anzeigen. opt.simulator.showiferr Warnung nur bei Fehlern. opt.simulator.ignore Alle Warnungen ignorieren. opt.tool.file Datei opt.tool.edit Editieren opt.tool.gateopt Drehen/Ausrichten opt.tool.gateprop Gatter opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Modus opt.tool.module Module opt.tool.tech Technologie opt.tool.simctl Simulatorsteuerung opt.tool.simaux Simulatorbefehle opt.tool.simmode Simulator Werkzeuge opt.tool.symmode Symboleditor Werkzeuge opt.tool.symedit Ausschneiden/Einfügen opt.tool.symport Ports opt.tool.symshift Bitverschiebung opt.tool.symopr Bitoperationen opt.editor.features Editor Features: Grundlagen opt.editor.format Automatische Einrückung einschalten opt.editor.colorize Syntax Highlighting einschalten opt.editor.comments Kommentare opt.editor.strings Strings opt.editor.reserved Schlüsselwörter opt.editor.gateword Eingebaute Gatter opt.editor.instword Modulinstanzen opt.editor.taskword Systemaufgaben opt.editor.color Farbe opt.editor.bold Fett opt.editor.italic Schräg opt.editor.indentlevel Einrückung per Stufe: opt.editor.beginindent Ausrichten von begin...end an der Einrücktiefe. opt.editor.movesel Drag-and-drop der Wahl einschalten. opt.editor.returntab Automatische Einrückung nach RETURN. opt.vercheck -begin- Periodische Nachfrage nach neuen TkGate-Versionen im Internet. Dieses Feature sollte nur bei dauerhaftem Internetzugang eingeschaltet werden. -end- opt.sec.execlevel Die $tkg$exec() Systemroutine ist opt.sec.exec komplett eingeschaltet. opt.sec.regexec nur für registrierte Funktionen eingeschaltet. opt.sec.noexec ausgeschaltet. opt.sec.simfeatures Simulator Features opt.sec.send $tkg$command() Systemroutine einschalten. opt.sec.open $fopen() Systemroutine einschalten. opt.sec.writemem $writememb() und $writememh() Systemroutinen einschalten. opt.sec.enqueue $tkg$recv() und $tkg$send() Systemroutinen einschalten. opt.sec.handle Behandlung von Sicherheitsverletzungen opt.sec.stop Beenden des Simulators bei Nutzung ausgeschalteter Features. opt.sec.warn Anzeige einer Warnung bei Nutzung ausgeschalteter Features. opt.sec.ignore Ignoriere versuchte Benutzung von ausgeschalteten Features. opt.html.linkopts Link Optionen opt.html.browser Browser Aufruf opt.html.email e-Mail Aufruf opt.debug.opt Debugging Optionen opt.color.editwin Fensterfarben editieren opt.color.scopewin Farben fürs Signaldiagramm-Fenster einstellen opt.vlibadd.title TkGate: Bibliothek hinzufügen opt.gen.basetoolbar Editorkern Toolbars opt.gen.simtoolbar Simulationsmodus Toolbars opt.gen.symedtoolbar Symboleditor Toolbars opt.bbar.restore Seitendefaults wiederherstellen opt.bbar.restoreall Alle Defaults wiederherstellen ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Typ igen.side Seite igen.size Größe igen.bits Bits igen.modname Modulname: #igen.resort Erneut Sortieren igen.add Hinzufügen igen.delete Löschen igen.edit Editieren igen.in Eingang igen.out Ausgang igen.inout Ein/Ausgang igen.left links igen.right rechts igen.top oben igen.bottom unten #igen.other andere igen.mod Verwende nur Ports, die im Modul benutzt werden. igen.int Verwende nur Ports aus existierender Schnittstelle. igen.modint Verwende sowohl Modul- als auch Schnittstellen-Ports. igen.portsel Port Auswahl igen.portpos Port Positionen igen.portpos.keep Erhalte soweit möglich die Port-Positionen. igen.portpos.renew Erzeuge alle Port-Positionierungen neu. igen.caption Erzeugen der Schnittstelle igen.description -begin- Erzeugen einer neuen Schnittstelle für ein Modul. -end- info.script.error Skript Fehler module.props.title TkGate: Moduleigenschaften module.props Moduleigenschaften ipanel.plist Portliste ipanel.props Schnittstelleneigenschaften #ipanel.itype.change Typ ändern... #ipanel.itype.edsymbol Symbol editieren... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Automatisch erzeugen... ipanel.updateall Alles auffrischen... ipanel.itype.select Schnittstellentyp #ipanel.block.description Standardschnittstelle #ipanel.symbol.description Benutzerdefinierte Symbolschnittstelle ipanel.ppos.label Blockgröße verändern (mit Ortsveränderung der Ports): ipanel.ppos.fix Feste Positionen ipanel.ppos.scale Skalierte Positionen #ipanel.ppos.grid Raster ipanel.warn.toblock -begin- Der Schnittstellentyp dieses Moduls soll nach "Block" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Ist das wirklich so gewollt? -end- ipanel.warn.tosymbol -begin- Der Schnittstellentyp dieses Moduls soll nach "Symbol" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Zusätzlich muß ein neues Bitmapbild für das neue Symbol erzeugt werden. Ist das wirklich so gewollt? -end- ############################################################################## # # Block list dialog boxes # blklst.delete.title TKGate: Modul löschen blklst.copy.title TKGate: Modul kopieren blklst.rename.title TKGate: Modul umbenennen blklst.claim.title TKGate: Modul aneignen blklst.setroot.title TKGate: Wurzel-Modul festlegen blklst.new.title TKGate: Neues Modul blklst.claim Modul aneignen blklst.to Nach blklst.from Von blklst.name Name blklst.new.cap Neues Modul erzeugen blklst.del.cap Modul löschen blklst.copy.cap Modul kopieren blklst.rename.cap Modul umbenennen blklst.claim.cap Modul aneignen blklst.setroot.cap Wurzel-Modul festlegen blklst.new.exp -fillbegin- Mit dieser Dialogbox wird eine neue Moduldefinition erzeugt. Das Modul kann als Netzliste oder HDL Modul erzeugt werden. Einmal erzeugt, kann der Typ aber nicht geändert werden; es muß gelöscht und neu erzeugt werden. -end- blklst.del.exp -fillbegin- Löschen der Definition und Schnittstellendaten des angegebenen Moduls. Existierende Instanzen des gelöschten Moduls beleiben erhalten, werden aber als undefiniert markiert. -end- blklst.copy.exp -fillbegin- Erzeugen einer Kopie der angegebenen Moduldefinition. Damit kann eine Variante eines existierenden Moduls erschaffen werden. -end- blklst.rename.exp -fillbegin- Umbenennen einer Moduldefinition. Diese Operation betrifft nur die Definition, alle existierenden Instanzen dieses Moduls verweisen weiterhin auf den alten Modulnamen. -end- blklst.claim.exp -fillbegin- Umwandeln eines Bibliotheksmoduls in ein Benutzermodul. Damit kann das Modul editiert und zusammen mit der eigenen Schaltung gesichert werden. -end- blklst.setroot.exp -fillbegin- Mache das angegebene Modul zum obersten (Top-Level). -end- find.title TkGate: Objekte finden find.label Objekte finden find.exp -fillbegin- Suche den Mustertext entweder in Gatternamen, Leitungsnamen oder in Kommentaren. Ein Doppelklick auf das Resultat führt zum gesuchten Objekt. -end- find.ignorecase Groß/Kleinschreibung ignorieren find.result.module Modul find.result.type Typ find.result.name Objektname # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Suchoptionen find.results Suchresultate # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Enthält... find.qual.begins Fängt an mit... find.qual.ends Endet mit... find.qual.matches Paßt auf... find.dom.label Nach Objekten suchen in: find.dom.gates Gatter find.dom.nets Schaltungen find.dom.text Kommentartext find.search Suchen: find.target Ziel # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Schaltungseigenschaften circ.label Schaltungseigenschaften circ.ident Identifikation circ.filev Dateiversion circ.file Dateiname circ.title Schaltungsüberschrift circ.encoding Dateicodierung circ.lang Datei: Sprache circ.discchg Keine Warnungen bei Verwerfen von Änderungen. circ.flags Optionen circ.extbar Erweiterungsleisten benutzen. circ.autostart Automatischen Simulationsstart einschalten. circ.iniscript Initialisierungsskripte #circ.noscript Keine Skriptdateien ausgewählt. #circ.really Soll '%s' wirklich aus der Liste der Inititalisierungsskripte gelöscht werden? circ.reallyupdate -fillbegin- Sollen wirklich alle '%s' Instanzen der Schnittstelle geändert werden? -end- circ.reallyoverwrite -fillbegin- Soll die bereits existierende Datei '%s' wirklich überschrieben werden? -end- @circ.library.width *500 @circ.library.height *350 circ.general Allgemein circ.library Bibliotheken circ.script Skript circ.simulator Simulation circ.timescale Standard Simulations-Zeitskala circ.timescale.unit Einheit: circ.timescale.prec Genauigkeit: circ.exp.general -fillbegin- Betrachten und Modifizieren schaltungsspezifischer Eigenschaften. Diese Eigenschaften werden beim Speichern der Schaltung mitgesichert. -end- circ.exp.library -fillbegin- Auswählen der von dieser Schaltung benutzten Bibliotheken. Die Bibliotheksangaben werden mit der Schaltung gesichert, sie werden beim nächsten Laden der Schaltung automatisch eingelesen. -end- circ.exp.simulator -fillbegin- Anzeige und Modifikation der Simulationseinstellungen dieser Schaltung. -end- ############################################################################## # # Bibliotheksverwaltung # libmgr.cap Bibliotheksverwaltung libmgr.library Bibliothek libmgr.description Beschreibung libmgr.status Status libmgr.status.load Geladen libmgr.status.unload Nicht geladen libmgr.status.loadp [Geladen] libmgr.status.unloadp [Nicht geladen] libmgr.exp -fillbegin- Wähle zu ladende oder zu entfernende Bibliotheken aus. -end- libmgr.load Laden libmgr.unload Entfernen libmgr.unloadall Alle entfernen libmgr.notedit -fillbegin- Die Bibliotheksverwaltung kann nur im Editiermodus der Schaltung geöffnet werden. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Haltepunkte break.id ID break.state S break.condition Bedingung break.value Wert ############################################################################## # Simulator # #sim.breakpt Haltepunkt sim.recursive -fillbegin- Rekursive Moduldefinition in '%s' gefunden. Simulator kann nicht gestartet werden. Keine kritische Pfadanalyse möglich. -end- sim.hyperlinkstop -fillbegin- Der Simulator läuft gerade. Soll die Simulation beendet und dem Link gefolgt werden? -end- ############################################################################## # # Critical path messages # cp.delay Pfadverzögerung: cp.pathl Pfadliste: cp.numpath Anzahl der Pfade: cp.recompute Neuberechnung ############################################################################## # Error messages # err.rootinterface Kann die Schnittstelle des obersten Moduls nicht definieren. err.nopin Ausgewählter Pin kann nicht verändert werden. err.badhex Illegaler Hexwert '%s', ignoriert. err.gatanchor Gatter ist (sind) verankert und können nicht bewegt werden. err.protdata Kann den Inhalt eines geschützen (Bibliotheks-)Moduls nicht ändern. err.badfind Kann Suchziel '%s' nicht finden. err.badopendel Kann geöffnetes Modul nicht löschen. err.nosrcmod Quelle zu Modul '%s' nicht gefunden. err.noerr Fehler nicht bestimmbar. err.misserr Fehler nur teilweise bestimmbar (Absturz des Simulators?) err.nofunc Ungeeigneter oder fehlender Funktionsname für die Modulschnittstelle. err.badinadd Kann keine Eingänge mehr zur angewählten Schaltung hinzufügen. err.badoutadd Kann keine Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badinoutadd Kann keine Ein/Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badpinchg Kann Pintyp des angewählten Gatters nicht ändern. err.badnetname Illegale Zeichen im Bezeichner gelöscht. err.netbcrename Bezeichner umbenannt in '%s' wegen illegaler Zeichen. err.netconfnet Bezeichner umbenannt in '%s' wegen Konflikten. err.netconfgat Bezeichner umbenannt in '%s' um Konflikt mit Grundgatternamen zu vermeiden. err.netconfkw Bezeichner umbenannt in '%s' um Konflikt mit Schlüsselwort zu vermeiden. err.badconsame Keine Verbindung, weil Leitungen Teil desselben Netzes sind. err.badconptsp Keine Verbindung, weil beide Leitungen Modulports oder Versorgungsleitungen sind. err.badconbitw Keine Verbindung, weil die Bitbreiten nicht zusammenpassen. err.badrange Nichtpositiver Bereich für Signaldiagramm nicht erlaubt. err.badlprcmd Druckkommando '%s' kann nicht ausgeführt werden. err.badpsopen Die Datei '%s' kann nicht für die Postscript-Ausgabe geöffnet werden. err.badid Ungültiger Bezeichner '%s' err.noinvgate Inverters sind auf Gattern dieses Typs nicht erlaubt. err.protintf Kann die geschützte Schnittstelle von Modul '%s' nicht ändern. err.bkpt.badexp Syntaxfehler in Haltepunkt-Ausdruck. Mögliche Werte: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Ungültiger Netzname '%s'. Namen beginnen mit Buchstaben und enthalten nur Buchstaben, Ziffern und '.' err.bkpt.badval Syntaxfehler in Wert '%s'. Nur dezimale oder Verilog-Konstante erlaubt. err.bkpt.toomany Zu viele Haltepunkte. Maximum ist %d. err.sim.badtmp Zwischendatei '%s' für Simulator konnte nicht gesichert werden (Platte voll?) err.sim.syntx Syntaxfehler in '%s' Kommando. err.sim.noincl Include-Datei '%s' nicht gefunden. err.sim.badedge Illegaler Flanken-Indikator '%c' in Takt-Kommando. err.sim.nobkpt Kein derartiger Haltepunkt '%s'. err.sim.nonet Kann Netz '%s' nicht finden. err.sim.nogate Kann Gatter '%s' nicht finden. err.sim.badbin Illegales Zeichen in binärer Konstante '%s'. err.sim.notswitch Schaltung '%s' ist kein Schalter, DIP-Schalter oder Register. err.sim.badcmd Kommando '%s' im Simulations-Skript unbekannt. err.sim.isrun Simulator läuft bereits (Beenden mit 'Ctrl-s e'). err.sim.run Laufzeitfehler err.sim.cmd Interner Fehler (Befehl) err.noteditpchg Eigenschaften können nur im Edit-Modus geändert werden. err.badeditop Illegale Operation im Schnittstellen-Editiermodus. err.badopen Datei '%s' kann nicht geöffnet werden. err.badlibopen Bibliotheksdatei '%s' kann nicht geöffnet werden. err.nomark Vor dem Anwählen eines Schaltungstyps eine Markierung setzen (linke Maustaste). err.badgate Unbekannter Schaltungstyp. err.badportadd Zu diesem Gattertyp ist Hinzufügen von Ports nicht möglich. err.modmissing HDL Modultext fehlt für Modul "%s". err.modtoomany Ãœberzählige Moduldefinitionen in Modul "%s". err.modmismatch Namens-mismatch zwischen Textdefinition und Modulname in "%s". err.manypages -begin- Dieses Dokument hat entsetzlich viele Seiten! Soll es tatsächlich gedruckt werden? -end- err.nojump -begin- Die Funktion 'Springe-zum-Modul' kann bei der Simulation und bei der Analyse Kritischer Pfade nicht genutzt werden. Stattdessen sollte von Hand zum Zielblock navigiert werden, indem Module selektiert und mit der Taste '>' geöffnet werden. Das Modul kann mit der Taste '<' wieder verlassen werden. -end- err.nomod Modul '%s' nicht definiert. err.modlock Logikblock ist gesperrt! err.closeroot Toplevel Modul kann nicht geschlossen werden. Quit benutzen. err.editonly Kommando im Simulationsmodus nicht möglich. err.simonly Kommando nur im Simulationsmodus möglich. err.deltop Toplevel Modul '%s' kann nicht gelöscht werden. err.delprot Geschütztes Modul '%s' kann nicht gelöscht werden. err.nodel Keine löschbare Auswahl. err.modnotdef Modul '%s' ist nicht definiert. err.moddef Der Block '%s' existiert bereits. err.primredef Built-in element name '%s' can not be redefined. err.noprop Das ausgewählte Gatter hat keine editierbaren Eigenschaften. err.openscript Datei mit Simulationsskript '%s' kann nicht geöffnet werden. err.oldversion Geladene Datei hat veraltete Versionsnummer '%s' (die aktuelle Version ist '%s'). err.futureversion Geladene Datei mit künftiger TkGate-Version '%s' gesichert (die aktuelle Version ist '%s'). err.badversion Unbekannte Versionsnummer. Benutzung auf eigene Gefahr. err.nodrive Netz '%s' hat keinen Treiber in Modul '%s'. err.noconn Leitung %s{%d} ist unverbunden -- gelöscht. err.oldportact Port hinzufügen/ändern durch Rechtsklick auf Port oder Modulkante err.nomodule Kein ausgewähltes Modul. err.nomodop Keine geeigneten Module zum Betrieb verhanden. err.protexec Versuchte Ausführung des geschützten Befehls '%s' in $tkg$exec(). err.notwritable Datei '%s' ist nicht beschreibbar. err.backupfail Erzeugen einer Backupdatei '%s' gescheitert. err.yy.badprop Unbekannte Schaltungseigenschaft '%s' wird ignoriert. err.yy.baddata Falscher Datentyp für Schaltungeigenschaft '%s' gewählt. err.yy.nosym Kein aktuelles Modulsymbol definiert. err.yy.badicon Falscher Icontyp '%s'. err.yy.toomuchdata Zu viele Icon-Daten. err.yy.nosyminst Fehlerhaftes Symbol %d in Instanz %s von %s. err.yy.badmodprop Unbekannte Moduleigenschaft '%s' wird ignoriert. err.yy.badmoddata Fehlerhafter Datentyp für Moduleigenschaft '%s' festgelegt. err.yy.badprim Unbekanntes Schlüsselwort '%s'. err.yy.nonet Undeklariertes Netz '%s'. err.yy.bogussave Gesicherte Schrottdaten entdeckt. Schaltung kann beschädigt sein. err.yy.pinformat Illegales Pin Namensformat '%s'. err.yy.pinname Pinname '%s' ist für Gattertyp '%s' nicht definiert. err.yy.nonetpos Kein Netz für Position %d in Gatter %s. err.yy.baddirective Illegale oder fehlerhafte Direktive '%s'. err.yy.badlocale Unbekannte locale '%s' in der Datei. Benutze die engl. locale. err.corruptnewsave -fillbegin- TkGate konnte die Datei in '%s' sichern, sie scheint aber korrupt zu sein. Sind Aufsetzpunkte definiert: Lade eine der Checkpoint Dateien. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.corruptsave -fillbegin- TkGate hat ein Problem bei der Sicherung der Datei '%s' entdeckt. Die existierende Datei wurde nicht modifiziert, die beschädigte Datei wurde nach '%s' geschrieben. Ist die Verwendung von Aufsetzpunkten eingeschaltet, kann versuchsweise eine der Checkpoint-Dateien geladen werden. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.badsave -fillbegin- Beim Öffnen oder Schreiben in Datei '%s' gab es ein Problem. Bitte Datei/Verzeichnisrechte und/oder verfügbaren Plattenplatz überprüfen. -end- err.nosafesave -fillbegin- Beim Versuch der Sicherung von Datei '%s' ist ein Problem aufgetreten. Es ist möglich, einen erneuten Versuch ohne Sicherungsvalidierung zu starten. Bei Antwort "nein" bleibt die Originaldatei unverändert. Bei Antwort "ja" wird die Originaldatei überschrieben, wird aber ggf. beim Auftreten eines Fehlers zerstört. Soll eine unvalidierte Sicherung versucht werden? -end- err.noback -fillbegin- Die Datei wurde von TkGate, Version %s, erzeugt und ist nach Sichern mit der aktuellen Version %s möglicherweise von früheren Versionen nicht mehr lesbar. -end- err.viewfile Datei '%s' kann nicht geöffnet werden. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod Interner Fehler: Kann Module '%s' nicht finden. ############################################################################## # Informational messages # msg.selwire Ausgewählt: Die Leitung hat den Namen '%s'. msg.selgate Ausgewählt: %s hat den Namen '%s'. msg.selblock Ausgewählt: %s Block hat den Namen '%s'. msg.iselwire Der ausgewählte Port '%s' ist in Block '%s'. msg.iselgate Das ausgewählte %s, genannt '%s' (huch? Diese Meldung sollte nicht möglich sein). msg.iselblock Ausgewählte Modulschnittstelle ist '%s'. msg.modoverwt Zielmodul '%s' existiert bereits. Ãœberschreiben? msg.foundgate Gatter mit Namen '%s' gefunden. msg.foundwire Leitung mit Namen '%s' gefunden. msg.searchagn Suchstring '%s' nicht gefunden. Mit 'find' Suche erneut starten. msg.sim.chgtoroot Simulationsmodus braucht das root-Modul oben auf dem Editierstack. msg.sim.nogatemod Der Simulationsmodus braucht einen konkreten Modulstack. msg.setinterface Setzen der Modulschnittstelle für '%s'. msg.needsel Bitte eine Modulinstanz auswählen. msg.wroteckpt Kontrollpunkt auf %s gesetzt... msg.save Schaltung als '%s' gesichert. msg.reallynew Die Schaltung wurde verändert. Soll sie wirklich gelöscht und eine neue erzeugt werden? msg.reallyquit Die Schaltung wurde verändert. Soll das Progamm wirklich beendet werden? msg.notlib Modul '%s' ist kein Bibliotheksmodul. ############################################################################## # Heinrich messages (Activated when Heinrich Hacker uses tkgate) # miles.msg1 Nur ein Trottel würde %s%s hierhin plazieren, Heinrich. miles.msg2 Eine richtig doofe Stelle, um %s%s abzulegen, Heinrich. miles.msg3 Ein schrecklich ungeeigneter Platz für %s%s, Heinrich. miles.msg4 Heinrich, Du bist ein Trottel %s%s hierhin zu setzen. miles.msg5 Heinrich, Du allein schaffst es, %s%s hierhin zu plazieren. miles.msg6 %s%s hierhin zu setzen beweist, daß Du ein totaler Trottel bist, Heinrich. miles.msg7 Warum gibst Du nicht auf, Heinrich, das ist eine hirnrissige Schaltung. miles.msg8a Es hat keinen Sinn weiterzumachen, Heinrich. miles.msg8b Heinrich, Du hast keine Ahnung wie man eine Schaltung baut. miles.msg8c Heinrich, mir graut vor Dir. ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Portgrößen-Mismatch bei Eingangsport '%s'. verga.err.OUTPORT Portgrößen-Mismatch bei Ausgangsport '%s'. verga.err.FLOATNET Netz '%s' hat keinen Treiber (floating net). verga.err.DIRECTCONN Direct connect Operator '=>' wird nicht unterstützt. Wird als '*>' behandelt. verga.err.MEMADDR Versuch, in Speicher %s mit unbekannter Adresse zu schreiben. verga.err.MEMBITS Versuch, in Speicher %s mit unbekanntem Bitbereich zu schreiben. verga.err.BADARRAYUSG Array '%s' wird im Ausdruck ohne Index verwendet. verga.err.BADARRAYLHS Array '%s' wird auf der linken Seite ohne Index verwendet. verga.err.BADCLOSE Versuch, einen nicht geöffneten Deskriptor in Task '%s' zu schließen. verga.err.BADAUTORNG Auto range [*] ist nur gültig in Leitungs-Deklarationen 'wire'. verga.err.BADGATERNG Fehlerhafter Bereichausdruck für eine Gatter-Instanz. verga.err.BADARGVALUE Fehlerhafter Wert für Argument '%s' in Task '%s'. verga.err.DIVZERO Teilung durch Null. verga.err.NODIV Divide/module wird auf dieser Maschine nicht unterstützt - sizeof(short) muß 2 sein. verga.err.BADEDGEEVENT Ereignis im Multi-Bit Netz '%s' kann kein posedge/negedge haben. verga.err.NEEDEDGE Positive oder negative Flanke muß für Event %s spezifiziert werden. verga.err.ASGNEVENT Warten auf ein Event ist bei Zuweisung illegal. verga.err.PROTTASK Ausführung der geschützen System Task '%s' wird blockiert. verga.err.NEEDIDENT Für Argument %s von Task '%s' wird ein Bezeichner erwartet. verga.err.BADOP Operatorfehler-Ausdruck in '%s'. verga.err.NOREAD Laden von Quelldatei '%s' fehlgeschlagen. verga.err.MEMFILE Öffnen von Speicher-Datei '%s' fehlgeschlagen. verga.err.WRONGMOD Modul '%s' wurde gefunden statt '%s'. verga.err.NOTPARM Bezeichner '%s' im konstanten Ausdruck ist kein Parameter. verga.err.BADADDR Illegaler Adressbereich für Port '%s'. verga.err.BADADDRSPEC Illegale Adressbereichsspezifikation '%s'. verga.err.BADCHAR Illegales Zeichen (%s) '%s'. verga.err.BADEVENT Illegaler Ausdruck zur Ereignissteuerung. verga.err.BADCONSTOP Illegaler Operator in konstantem Ausdruck. verga.err.BADXOP Illegaler Operator in Ausdruck. verga.err.NETREDEF Illegale Redefinition des Netzes '%s'. verga.err.BADINOUT Ein/Ausgabe-Verbindungen müssen bei Port '%s' von Netz zu Netz sein. verga.err.MODUNDEF Instanz eines undefinierten Moduls '%s'. verga.err.BADASGNLHS Ãœngültige linke Seite in 'assign'. verga.err.LHSNOTREG Illegale Benutzung von '%s' auf der linken Seite einer Zuweisung. verga.err.BADLHS Ungültige linke Seite in Zuweisung. verga.err.BADOUT Ãœngültige Ausgangs-Zuweisung. verga.err.NOTREG Speicher müssen als Register deklariert werden. verga.err.PORTMIX Vermischte benannte und unbenannte Ports bei Schnittstelle '%s' von '%s'. verga.err.REPCASE Mehr als ein default: in case-Anweisung. verga.err.NOMEM In der gelesenen Speicherdatei gibt es keinen aktuellen Speicher. verga.err.BADCMD Es gibt keinen Befehl '%s'. verga.err.CMDNOTNET Es gibt kein Netz '%s' im '%s' Befehl. verga.err.MEMNONBLK Nicht-blockierende Zuweisungen zu Speicherbereichen sind nicht implementiert. verga.err.NOTPPORT Parameter '%s' ist nicht als Port deklariert. verga.err.REDEFP Parameter redefiniert Bezeichner '%s'. verga.err.PORTNOTDEF Port '%s' in Schnittstelle '%s' ist in Modul '%s' nicht definiert. verga.err.NOCONN Port '%s' hat keine Verbindungen mit Schnittstelle '%s' von '%s'. verga.err.MULTCONN Port '%s' hat Mehrfachverbindungen mit Schnittstelle '%s' von '%s'. verga.err.PORTCOUNT Portanzahl paßt nicht zur Definition der Schnittstelle '%s' von '%s'. verga.err.BADPRTRANGE Der Bereich von Port '%s' isr nicht numerisch. verga.err.BADARRAYRNG Bereichsspezifikation ist für eine Speicherreferenz von '%s' nicht erlaubt. verga.err.CMDMODREDEF Redefinition des dynamischen Moduls '%s'. verga.err.REDEF Redefinition des Beziechners %s. verga.err.PROTTASKSTOP Simulation beendet nach versuchter Ausführung der geschützten System-Task '%s'. verga.err.NOTMEM Das spezifizierte Netz '%s' ist kein Speicher. verga.err.CMDNOTMEM Das spezifizierte Netz '%s' ist kein Speicher in Befehl '%s'. verga.err.SYNTAX Syntaxfehler. verga.err.TOOFEWPP Zu wenig Parameter Ports bei Instanz %s. verga.err.OPENTOOMANY Zu viele geöffnete Dateien in Task '%s'. verga.err.TOOMANYPP Zu viele Parameter Ports bei Instanz %s. verga.err.NOTOP Oberstes Modul '%s' nicht definiert. verga.err.BADOPEN Ausgabedatei '%s' in Task '%s' kann nicht geöffnet werden. verga.err.CMDNOMOD Undefiniertes dynamisches Modul '%s' in Befehl '%s'. verga.err.BADEVENTNET Undefiniertes Netz '%s' in Ereignissteuerungs-Ausdruck. verga.err.NOTASK Undefinierte Task '%s'. verga.err.NOTDEF Undefinierte Variable '%s'. verga.err.BADRANGE Nicht unterstützter Bitbereich [%s] in Netz %s (muss von der Form [n:0] sein). verga.err.GATEUNIMP Unimplementierter primitiver Gatter-Instanz-Typ. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Schreiben auf einen bereits geschlossenen Deskriptor. verga.err.PRIMPTCOUNT Falsche Anzahl von Ports bei der primitiven Gatter-Intsanz '%s'. verga.err.CMDARGS Falsche Zahl von Argumenten im '%s' Befehl. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' mit der falschen Anzahl von Argumenten aufgerufen. verga.err.BADSTART Illegaler Anfangswert in Task '%s'. verga.err.BADSTOP Illegaler Stopwert in $readmemb. verga.err.SPECTASKUSG Task '%s' muss in einem Specify-Block benutzt werden. verga.err.BADSPECTASK Task '%s' kann nicht in einem Specify-Block benutzt werden. verga.err.TIMING Fehler im Zeitablauf bei %s in %s[%s] %s. verga.err.NOIFDEF Kein passendes `ifdef/`ifndef für die %s Deklaration. verga.err.BADSPECLVAL Bitbereiche sind bei Pfadverzögerungs-Spezifikatoren nicht unterstützt. verga.err.PATHDITEM Nicht unterstütztes Konstrukt in Modul mit Pfadverzögerungs-Spezifikation. verga.err.PATHDINOUT Benutzung von 'inout' in Modul mit Pfadverzögerungs-Spezifikation wird nicht unterstützt. verga.err.PATHDLOOP Schleifen in Modulen mit Pfadverzögerungs-Spezifikation werden nicht unterstützt. verga.err.PATHDCOND Setzen von DelaMust durch # Ausdruck und Blockspezifikation. verga.err.TASKREDEF Redefinition eines Task oder einer Funktion '%s' in Modul '%s'. verga.err.TASKASFUNC Task '%s' wird als Funktion benutzt. verga.err.FUNCASTASK Funktion '%s' wird als Task benutzt. verga.err.TASKBADTYPE Nicht-Register-Typ in Task oder Funktion benutzt. verga.err.TASKBADPORT In Funktionen sind nur Eingabeports erlaubt. verga.err.TIMESCALEU Ungültige Einheit '%s' in `timescale Deklaration. verga.err.TIMESCALEN Ungültige Skala '%s' in `timescale Deklaration (muss 1, 10 oder 100 sein). verga.err.TIMESCALES Ungültige Syntax in `timescale Deklaration. verga.err.TIMESCALEX Einheiten müssen größer sein als die Genauigkeit der `timescale Deklaration. verga.err.TIMESCALEAN Der Entwurf enthält Module mit und ohne `timescale verga.err.BADPORTTYPE Ungültige Typdeklaration, benutzt bei '%s' verga.err.BADVALUE Ungültiger Zahlenwert '%s'. verga.err.NONEXPCTL Ereignissteuerung @(*) auf einen Nicht-Ausdruck angewendet. verga.err.NONSTATCTL Eriegnissteuerung @(*) auf eine Nicht-Anweisung angewendet. verga.err.MODREDEF Modul-Redefinition '%s'. verga.err.IE_TASK Task Definition '%s' außerhalb von Modul gefunden - interner Fehler. verga.err.IE_NONET Netz '%s' nicht gefunden - interner Fehler. verga.err.IE_NOOP Operatorbeschreibung nicht zu finden - interner Fehler. verga.err.IE_BADEXP Unerwarteter Ausdruckstyp %s - interner Fehler. verga.err.IE_BADVAR Undefinierte Variable oder unbekanntes Netz - interner Fehler. verga.err.IE_BADSTATE Unerwarteter interner Zustand bei %s - interner Fehler. verga.err.IE_RETURN BCReturn bytecode ausgeführt bei leerem Returnstack - interner Fehler. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Alle Items in die selektierte Liste. ho.setsel.alll Alle Items in die nicht selektierte Liste. ho.setsel.ltor Highlight-Items in die selektierte Liste. ho.setsel.rtol Highlight-Items in die nicht selektierte Liste. ho.net.in Single-Bit Eingang ho.net.out Single-Bit Ausgang ho.net.inout Single-Bit Ein/Ausgang ho.net.in2 Multi-Bit Eingang ho.net.out2 Multi-Bit Ausgang ho.net.inout2 Multi-Bit Ein/Ausgang ho.net.wire Single-Bit Leitung (Name sichtbar) ho.net.wire2 Multi-Bit Leitung (Name sichtbar) ho.net.hwire Single-Bit Leitung (Name versteckt) ho.net.hwire2 Multi-Bit Leitung (Name versteckt) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Sichern und Laden von Schaltungsdateien ho.opt.tool.edit Ausschneide-, Einfüge- und Suchoperationen ho.opt.tool.gateopt Gatterdrehungen und Ausrichtungsoperationen ho.opt.tool.gateprop Grundlegendes Editieren von Gattern ho.opt.tool.undo Undo und Redo Operationen ho.opt.tool.zoom Zoom in und Zoom out ho.opt.tool.mode Auswahl des Editierwerkzeugs ho.opt.tool.module Erzeugen, Löschen, Umbenennen etc. von Moduldefinitionen ho.opt.tool.tech Auswahl der Standardtechnologie für Gatter ho.opt.tool.simctl Start, Stop und Pause beim Simulator ho.opt.tool.simaux Weitere Simulatorbefehle (Lesen und Schreiben von Speicherdateien etc.) ho.opt.tool.simmode Im Simulator zwischen dem Auswahl- und dem Scroll-Werkzeug wählen. ho.opt.tool.symmode Auswahl eines Editierwerkzeugs im Symboleditor ho.opt.tool.symedit Ausschneide- und Einfügeoperationen für den Symboleditor ho.opt.tool.symport Port-Drehoperationen für den Symboleditor ho.opt.tool.symshift Verschieben der Bitmap oder von Teilen der Bitmap ho.opt.tool.symopr Verschiedene Symboleditor-Operationen ho.opt.editor.movesel -begin- Ein ausgewählter Textblock kann mit dem Mauszeiger angefaßt und in eine neue Position verschoben werden, wenn die Option angewählt ist. -end- ho.opt.editor.format -begin- Verilog Quellcode wird automatisch eingerückt, wenn die TAB-Taste gedrückt wird. -end- ho.opt.editor.indent -begin- Anzahl der Leerzeichen pro Einrückungsstufe. -end- ho.opt.editor.rtab -begin- Automatisches Einrücken der aktuellen Zeile und Tabulation zur entsprechenden Einrückung wenn RETURN gedrückt wird. -end- ho.opt.editor.beginindent -begin- Führt zur selben Einrückungstiefe eines begin..end-Blocks wie beim Vater-Block. -end- ho.opt.editor.colorize -begin- Einschalten der kontextabhängigen Einfärbung von Quellcode nach den untenstehenden Optionen. -end- ho.hdl.splitexp -begin- Mehrfachmodule im HDL-Text werden in verschiedene Module augespalten, die nach Bedarf neue Module definieren. Alle Namenskonflikte werden durch leichte Veränderung der Modulnamen aufgelöst. -end- ho.hdl.commentexp -begin- Module, die nicht auf den erwarteten Namen passen oder das oberste Modul sind, werden zu HDL-Kommentaren konvertiert. -end- ho.hdl.autoeditexp -begin- Automatisches Editieren der HDL Beschreibung zur Änderung des Modulnamens. -end- ho.hdl.cancelexp -begin- Keine Aktion ausführen und das Editieren des aktuellen Moduls fortsetzen. -end- ho.hdl.ignoreexp -begin- Ignorieren der Inkonsistenz und Fortsetzung der ausgewählten Aktion. -end- ho.new -begin- Aufgeben der aktuellen Schaltung und Editieren einer neuen. -end- ho.open Einlesen einer Schaltung aus einer Datei. ho.save Sichern der Schaltung in die aktuelle Datei. ho.saveas Sichern der Schaltung in eine neue Datei. ho.print Drucken der aktuellen Schaltung. ho.library Laden einer Bibliotheksdatei. ho.symed.tab.normal -begin- Editieren der nicht ausgewählten Symbol-Bitmap -end- ho.symed.tab.select -begin- Editieren der ausgewählten Symbol-Bitmap -end- ho.simmove -begin- Wähle Leitungen und Module aus, bediene die Schalter und gib DIP Werte ein. Klicken und festhalten einer Leitung zeigt ihren aktuellen Wert. -end- ho.move -begin- Bewegen/Verbinden - Klicken und Ziehen - setzt die Position für ein neues Gatter, - bewegt Gatter und Leitungen, - verbindet Leitungen Ein Doppelklick editiert - Gatter-, Leitungs- und Port-Eigenschaften, - Kommentartext. -end- ho.delgat -begin- Gatter entfernen - Werkzeug zum Löschen von Gattern. -end- ho.cutw -begin- Leitung trennen - Werkzeug zum Durchschneiden von Leitungen. -end- ho.scroll -begin- Scrollen - zum Einfangen und Ziehen des Editier-Canvas. -end- ho.inv -begin- Invertieren - Werkzeug zum Hinzufügen oder Löschen von Invertern an Ein- und Ausgängen von Gattern. -end- ho.bitw -begin- Bitbreite - Werkzeug zum Ändern der Breite eines Leitungsbündels. Eingabe der Anzahl der Leitungen in der Eingabebox rechts unten neben dem Logo. -end- ho.ipanel.select -begin- "Standard"-Module werden für normale rechteckige Schnittstellen benutzt, "symbolische" Module für hausgemachte Bitmap-Symbole. -end- ho.ipanel.addport -begin- Einen Port zu einem Modul hinzu- fügen. Doppelklicken nach dem letzten Item bewirkt dasselbe. -end- ho.ipanel.deleteport -begin- Löschen des ausgewählten Ports. -end- ho.ipanel.editport -begin- Editieren des ausgewählten Ports. Ein Feld in einem Port wird mit Doppelklick editiert. -end- ho.ipanel.generate -begin- Erzeugen einer neuen Schnittstelle für ein Modul, basierend auf Ports in der Port-Liste und in der Modul- definition benutzen Portelementen. -end- ho.ipanel.updateall -begin- Ersetze in allen Instanzen dieses Moduls die Schnittstelle durch die hier gezeigte kanonische Schnittstelle. -end- ho.ipanel.prot -begin- Verbiete die Änderung der Definition eines Moduls. -end- ho.ipanel.protint -begin- Verbiete die Änderung der Schnittstelle eines Moduls. -end- ho.ipanel.proted -begin- Verbiete die Änderung der Schnittstelle eines Moduls außer mit Hilfe des Schnittstelleneditors. Das dient der Verhinderung unabsichtlicher Änderungen der Schnittstelle im Haupteditorfenster -end- ho.ipanel.scale -begin- Wird ein Modul in der Größe verändert, so skaliere die Abstände zwischen den Ports mit. -end- ho.ipanel.fix -begin- Wird ein Modul in der Größe verändert, so behalte trotzdem die Abstände zwischen den Ports bei. -end- ho.mod.open Ausgewähltes Modul öffnen. ho.mod.close Aktuelles Modul schließen. ho.mod.new Einen neuen Modultyp erzeugen. ho.mod.del Modul löschen. ho.mod.copy Modul kopieren. ho.mod.rename Modul umbenennen. ho.mod.claim -begin- Konvertieren eines Bibliotheksmoduls in ein reguläres Modul. -end- ho.mod.setroot -begin- Auszeichnen eines Moduls als oberstes (Wurzel-)Modul. -end- ho.mod.type.allparts Bibliothekssammlung ho.mod.type.partlib Bibliothek ho.mod.type.part Bibliotheksmodul ho.mod.type.unknown Unbekannter Modultyp ho.mod.type.unused Sammlung unbenutzer Module ho.mod.type.conflict Modulrekursion ho.mod.type.root Oberstes (Toplevel-) Modul ho.mod.type.netlist Netzlisten Modul ho.mod.type.Lnetlist Netzlisten Modul (locked) ho.mod.type.hdl HDL Modul ho.mod.type.Lhdl HDL Modul (locked) ho.undo Undo früherer Aktion(en) ho.redo Redo von Undo-Aktion(en) ho.tab.edit -begin- Primärer Editiermodus. -end- ho.tab.interface -begin- Editieren der Modulschnittstellen. Ein Doppelklick im Schnittstellenmodus auf ein Modul der Modulliste führt zum Editieren seiner Schnittstelle. Im obersten Modul werden alle Schnittstellen anzeigt. -end- ho.tab.simulate -begin- Start des Simulators, Öffnen des Logikanalysators und Ausführen aller festgelegten Initialisierungsskripte. -end- ho.tab.cpath -begin- Suche die kritischen Pfade einer Schaltung. -end- ho.log -begin- Log von TkGate Meldungen: Fehlermeldungen, informelle Meldungen und Simulator-Konsolenausgabe. -end- ho.simgo -begin- Ist eine Simulation aktiv: kontinuierlich laufen lassen. Ist keine Simulation aktiv: Starten der Simulation und Ausführen aller Initialisierungsskripte. -end- ho.simpause -begin- Pause bei einer kontinuierlich laufenden Simulation. -end- ho.simstep -begin- Start des Ablaufs eines festen Zeitintervalls im Einzelschrittmodus. Im Fenster Simulation->Optionen kann die Schrittweite gesetzt werden. -end- ho.simclock -begin- Ablauf einer festen Anzahl von Taktzyklen. Dazu im Fenster Simulation->Optionen die Schrittweite setzen. -end- ho.simstop -begin- Beenden der aktuellen Simulation, Rückkehr in den Editiermodus. -end- ho.simbreak -begin- Editieren der aktuellen Haltepunkte. Die Simulation hält, wenn eine Haltepunktbedingung wahr wird. -end- ho.simexec -begin- Verwalten der Sammlung aktiver Skripte. -end- ho.simoptions -begin- Setzen verschiedener Optionen, die die Simulation steuern. -end- ho.simload -begin- Laden des Speichers mit dem Inhalt einer .mem-Datei. -end- ho.simdump -begin- Speicherinhalt in eine .mem-Datei schreiben. -end- ho.modlist -begin- Listen aller aktuell geladener Moduln in alphabetischer Ordnung. Ziehe die Moduln ins Editierfenster, um neue Instanzen zu erzeugen. -end- ho.modtree -begin- Hierarchiebaum aller aktuellen Module. Zum erzeugen neuer Modulinstanzen ziehe die Module ins Editierfenster. -end- ho.netlist -begin- Liste der Netze im aktuellen Modul. Das Symbol links vom Namen zeigt an, ob das Netz einbittig (grün) oder mehrbittig (rot) ist. Ein "A" im Symbol zeigt, ob der Netzname als sichtbar markiert ist. -end- ho.ports -begin- Liste der Ports des aktuellen Moduls. Das Symbol vor dem Port zeigt seine Richtung an. -end- ho.status.logo -begin- Anzeige des Simulations-Status. Wird das Eisentor-Logo angezeigt, ist TkGate im Editiermodus. Wird das vierbeinige UND- Gatter gezeigt, ist TkGate im Simulations- modus. Steht dieses UND-Gatter, so ist die Simulation angehalten; läuft es, so läuft auch die Simulation. -end- ho.status.msg Anzeigefeld für Meldungen von TkGate. ho.status.block Modulstack, der gerade editiert wird. ho.status.file -begin- Aktuelle Datei, die gerade editiert wird. Ein '*' hinter dem Dateinamen zeigt an, daß der Puffer seit der letzten Sicherung verändert worden ist. -end- ho.print.selall Ausdrucken aller zur Zeit von TKGate geladenen Module. ho.print.selcur Ausdruck des aktuellen Moduls aus dem Editierfenster. ho.print.seluse -begin- Drucke alle Moduln, die gerade "in Gebrauch" sind. Das sind solche, die Abkömmlinge des root-Moduls sind. -end- ho.print.fulltrace Drucken des ganzen Signaldiagramms. ho.print.parttrace -begin- Drucken eines Teils des Trace. Start- und Stopzeiten werden im Eingabefenster unten eingetragen. Man kann auch mit der rechten Maustaste den Bereich auf dem Scope-Fenster auswählen (mit Shift-Rechts werden große Bereich ausgewählt). -end- ho.print.parttracestart Startzeit der Trace-Ausgabe. ho.print.parttraceend Endezeit der Trace-Ausgabe. ho.print.selsel -begin- Drucke nur die unten angewählten Module. Benutze die Strg-Taste zur Auswahl mehrerer Module. -end- ho.print.modlist Wähle die zu druckenden Module aus. ho.print.timegraph -begin- Hier wird das zum Drucken ausgewählte Gebiet gezeigt. Der grüne Bereich ist der Gesamtbereich der verfügbaren Signaldaten, grau wird die zu druckende Fläche angezeigt. Verwende die Selektoren auf der Linken um ein Gebiet auszuwählen oder wähle das Gebiet im Scopefenster aus, bevor diese Dialogbox geöffnet wird. -end- ho.circuit.discchg -begin- TkGate zeigt keine Warnung an, wenn Änderungen ohne Sicherung verworfen werden. -end- ho.circuit.extbar -begin- Grundgatter (AND, OR, XOR) benutzen für Mehrfacheingänge Erweiterungsleisten. -end- ho.circuit.autostart -begin- Die Simulation beginnt, sobald das Simulationsfenster angewählt ist, wenn diese Option eingeschaltet ist. -end- ho.circuit.file -begin- Der Name der Datei, von der die aktuelle Schaltung geladen wurde. -end- ho.circuit.ver -begin- Die TkGate-Version, mit der die aktuelle Datei erzeugt wurde. -end- ho.circuit.encoding -begin- Benutze diese Codierung für die Dateisicherung. -end- ho.circuit.language -begin- Nutze Fonts mit dieser Codierung zur Anzeige von Schaltungsdaten. -end- ho.circuit.title -begin- Beschreibung der Schaltung. Dieser Titel erscheint in der Druckausgabe. -end- ho.cmd.bitw -begin- Vorgegebene Bitbreite für mit dem Bitbreite-Werkzeug selektierte Leitungen. -end- ho.edgat.signam -begin- Der Name des ausgewählten Signals am ausgewählten Gatter. Der Name des Signals kann hier durch Editieren geändert werden. -end- ho.edgat.port -begin- Der Name des Ports für dieses Signal am Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.iolab -begin- Die Richtung des ausgewählten Signals am ausgewählten Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.bitlab -begin- Die Bitbreite des ausgewählten Signals des ausgewählten Gatters. Die Bitbreite kann hier durch Editieren geändert werden. -end- ho.edgat.cycle Die Gesamtzahl der Epochen in einem Taktzyklus. ho.edgat.phase Der Startpunkt des Zyklus (in Prozent). ho.edgat.duty Der Prozentsatz des Zyklus, in dem der Takt 'low' ist. ho.edgat.hide -begin- Setze dieses Flag, um die Anzeige des Gatternamens zu verhindern. -end- ho.edgat.gtype Typ des Gatters. ho.edgat.gname Name dieser Gatterinstanz. ho.edgat.ganchor Setze dieses Flag, um die Position des Gatters zu verankern. ho.edgat.gx X Koordinate des Gatters. ho.edgat.gy Y Koordinate des Gatters. ho.edgat.swstate -begin- Der zu benutzende Anfangszustand des Schalters beim Start der Simulation. -end- ho.edgat.dipstate -begin- Der zu benutzende Anfangszustand des DIP-Schalters beim Start der Simulation. -end- ho.edgat.range Der Bitbereich, der aus einem Bus herausgeführt wird. ho.edgat.memfile -begin- Die Datei mit dem Anfangszustand für diesen Speicher. Die Datei wird gelesen, wenn der Simulator gestartet wird. -end- ho.edgat.func Der Funktionstyp dieses Moduls. ho.edgat.frame Die Markierung des Rahmens. ho.traceprint -begin- Drucke den Bereich des Logik-Signaldiagramms, der mit der rechten Maustaste ausgewählt ist. Shift-Rechts-Klick kann benutzt werden, um das augewählte Gebiet zu vergrößern. Der in der Scope-Ansicht sichtbare Bereich wird genutzt, falls keine Auswahl erfolgt ist. -end- ho.showxhair -begin- Wird dieser Knopf gedrückt, erscheint eine senkrechte Maßlinie im Scope-Fenster. -end- ho.opt.general.fontset -begin- Legt die Fontgröße des Basisfonts in der TkGate- Benutzerschnittstelle fest. Diese Option wird erst aktiv, wenn TkGate neu gestartet ist. -end- ho.opt.sec.send -begin- Aktivieren der $tkg$command() System Task erlaubt es Anwendungsschaltungen, dem TkGate GUI beliebige Simulator-Steuerkommandos zu senden. Dazu gehört auch die Fähigkeit zum Ausführen beliebiger Shellbefehle. Wird der Simulator zum Ausführen von Schaltungen unklarer Herkunft benutzt, sollte diese Task lieber ausgeschaltet bleiben. Aktivierung führt zu einem hohen Sicherheitsrisiko! -end- ho.opt.sec.open -begin- Aktivieren der $fopen() System Task erlaubt Anwendungsschaltungen in beliebige Dateien des Benutzers zu öffnen. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.writemem -begin- Aktivieren der $writememb() und $writememh() System Tasks erlaubt es Anwendungsschaltungen in beliebige Dateien des Benutzers zu schreiben. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.enqueue -begin- Aktivieren der $tkg$recv() und $tkg$send() System Tasks erlaubt virtuellen peripheren Geräten Botschaften an TkGate Schaltungen zu senden. Das ist ein relativ geringes Sicherheitsrisiko. -end- ho.opt.ssave -begin- Führe Konsistenzüberprüfungen von Schaltungsdateien durch, bevor eine existierende Sicherungsdatei überschrieben wird. Damit wird überprüft, ob es keine Probleme mit der Sicherungsdatei gibt. -end- ho.opt.sec.exec -begin- Die volle Aktivierung der $tkg$exec() System Task erlaubt es dem Benutzer, beliebige tcl/tk-Befehle einschließlich der Ausführung beliebiger Shellbefehle abzusetzen. Die Aktivierung dieser Option stellt also ein sehr hohes Sicherheitsrisiko dar. -end- ho.opt.sec.regexec -begin- Die Aktivierung der $tkg$exec() System Task für registrierte Funktionen erlaubt es Anwendungsschaltungen, nur tcl/tk Kommandos auszuführen, die als sicher registriert sind. Solange alle virtuellen peripheren Geräte vertrauenswürdig sind, hält die Aktivierung von $tkg$exec() auf dieser Stufe gefährliche Befehle von der Ausführung ab. Das Einschalten dieser Option hat ein mittleres Sicherheitsrisiko zur Folge. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- Ist diese Einstellung aktiviert, wird die Simulation beendet, sobald von der Anwendungsschaltung versucht wird, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.warn -begin- Ist diese Einstellung aktiviert, wird die Simulation nach einer Warnmeldung weitergehen, wenn die Anwendungsschaltung versucht, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.ignore -begin- Ist diese Einstellung aktiv, wird die Benutzung aller ausgeschalteten Features ignoriert; es werden keine Fehlermeldungen angezeigt. -end- ho.opt.html.browser -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zu einer HTML-Datei klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.html.email -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zum Senden einer e-mail klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.fsave -begin- Sichere die TkGate-internen Zellen mit den Schaltungsdaten. Dies erhöht die Dateigröße um ca. 20%, führt aber zu Sicherungsdateien, die zur Verwendung mit Drittanbietertools exportiert werden können. -end- ho.opt.sorttraces -begin- Ist diese Option eingeschaltet, werden die Signale im Scope-Fenster in sortierter Form angezeigt. Ist sie ausgeschaltet, werden die Signale im Scopefenster in der Reihenfolge der Probe-Setzungen angezeigt. -end- ho.opt.sim.noglitch -begin- Ist diese Option aktiv, so bewirken sich schnell verändernde Signale am Eingang eines Gatters am Ausgang desselben im wesentlichen das zeitverschobene Eingangssignal. Dies kann flüchtige Ereignisse und Schwingungen in sequentiellen Schaltungen auf Gatterebene verhindern helfen. -end- ho.opt.sim.savetraces -begin- Tastköpfe, die während eines Simulationslaufes plaziert wurden, werden abgespeichert und beim Neustart der Simulation wieder richtig gesetzt. -end- ho.opt.sim.tech -begin- Dateienliste zum Laden als potentielle "Technologie"-Dateien. Technologie-Dateien legen Verzögerungen und Flächengrößen für eingebaute Gatter fest. -end- ho.opt.sim.err -begin- Wähle, wie Warnungen vom Simulator behandelt werden sollen. -end- ho.opt.sim.err.stopany -begin- Gibt es irgendwelche Warnungen zu der Schaltung, wird sie nicht simuliert, auch nicht, falls es gar keine wirklichen Fehler gibt. -end- ho.opt.sim.err.showall -begin- Ziege immer Warnunge zu der Schaltung, auch wenn es keine Fehler gibt. Falls nur Warnungen existieren, wird der Simulator gestartet und die Warnungen in einem gesonderten Fenster angezeigt. -end- ho.opt.sim.err.showiferr -begin- Zeige Warnungen nur, wenn es auch Fehler in der Schaltung gibt. Enthält eine Schaltung nur Warnungen, so werden sie ignoriert und der Simulator wird geräuschlos gestartet. -end- ho.opt.sim.err.ignore -begin- Zeige nie Warnmeldungen, auch nicht, falls es Fehler in der Schaltung gibt. -end- ho.opt.lib.vpath -begin- Liste von Verzeichnissen, in denen nach TkGate Bibliotheksdateien gesucht wird. Bibliotheken sollten eine .v Dateierweiterung besitzen und Module enthalten, die für den Gebrauch in Anwendungsschaltungen nützlich sind. -end- ho.opt.lib.vlib -begin- Die Bibliotheksliste, die automatisch geladen wird, wenn TkGate startet. -end- ho.opt.lib.vpd -begin- Liste von Verzeichnissen, in denen nach virtuellen peripheren Geräten (VPDs) gesucht wird. Virtuelle periphere Geräte haben eine .tcl Dateierweiterung und implementieren typischerweise ein GUI, das das periphere Gerät repräsentiert und das von einer benutzerschaltung gesteuert wird. -end- ho.opt.undolen -begin- Maximale Zahl der aufzuhebenden Undo-Aktionen. -end- ho.opt.name -begin- Benutzername, der auf allen von TkGate produzierten Reports, z.B. Schaltungs- ausdrucken, aufgeführt wird. -end- ho.opt.site -begin- Der Netzname der Organisation, in der TKGate installiert ist. Dieser Name wird auf jedem Ausdruck (oder in der Postscript-Datei) ausgegeben. -end- ho.opt.smooth -begin- Falls diese Option eingestellt ist, wird Scrollen mittels Bitmap-Kopien realisiert statt das Bild immer neu zu zeichnen. Dies kann ausgeschaltet werden, falls Probleme mit dem X-Server auftreten. -end- ho.opt.clip -begin- Ist diese Option eingeschaltet, wird Clipping benutzt, um den dargestellten Teil des Fensters beim Neuaufbau zu zeichnen. Sonst wird das ganze Display für alle Teile neu gezeichnet. -end- ho.opt.showimage -begin- Durch Zurücksetzen dieser Option kann die Anzeige des Bildes un der erläuternde Text am Rand der Dialogboxen unterdrückt werden. -end- ho.opt.outmove -begin- Ist diese Option eingeschaltet, wird nur der Umriß der bewegten Modulinstanzen beim Verschieben angezeigt. Diese Einstellung ist nur auf Maschinen mit langsamen Displays nötig. -end- ho.opt.bhelp -begin- Bei Aktivierung dieser Option werden Hilfehinweise angezeigt. Sie zeigen Tips an, wenn die Maus sich gerade über einem Baustein befindet. -end- ho.opt.tearawaymenus -begin- Die Hauptmenues können von der Schnitstelle entfernt werden. Diese Option wird erst nach einem Neustart von TkGate wirksam. -end- ho.opt.novice -begin- Falls auf der Kommandozeile keine andere Schaltung angegeben ist, wird ein TkGate- Tutorial als erste Schaltung beim Start angezeigt. -end- ho.opt.blockDropConnect -begin- Dies Option erlaubt die Erzeugung von Ports bei Modulschnittstellen, indem freie Leitungen neben einer Kante fallengelassen werden. -end- ho.opt.debug -begin- Einschalten mehrerer Debugging Features. Nur interessant für TKGate-Entwickler. -end- ho.opt.ckpt Einschalten des Checkpointing nicht gespeicherter Schaltungen. ho.opt.ckptfreq Anzahl der Checkpoints pro Sekunde. ho.opt.beak -begin- Freischalten dieser total nutzlosen Features. Falls dies ausgeschaltet wird, erscheinen diese Modi (und diese Checkbox) nicht mehr im Optionsfenster. Der einzige Weg, sie wiederzubekommen, geht über das Editieren der .tkgate-properties Datei. -end- ho.opt.miles -begin- Ist dieser Modus eingeschaltet, wird TkGate periodisch die Intelligenz des Benutzers anzweifeln. -end- ho.opt.bat -begin- Falls dieser Modus eingeschaltet ist, wird TkGate eine Entwicklungsumgebung für einen Bat-Computer einrichten. -end- ho.opt.trek Beam me up Scotty! ho.opt.simstep -begin- Die Anzahl der Epochen, die bei einem Schritt-Kommando vorangeschritten wird. -end- ho.opt.ckstep -begin- Die Anzahl der Taktzyklen, die vorangeschritten wird, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.ckover -begin- Die Anzahl der Epochen nach der Anstiegsflanke des Taktes, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.vpopupdelay -begin- Die Verzögerung in Millisekunden zwischen Drücken und Halten der Maustaste und der Anzeige eines Signalwerts. Auf einigen Systemen interferieren kurze Verzögerungs- zeiten mit der Fähigkeit, einen Doppelklick zu erkennen. Liegt dieser Fall vor, so ist der Wert zu erhöhen. Es sind Werte zwischen 1 und 10000 erlaubt. -end- ho.opt.init -begin- Eine Simulationsskript-Datei, die automatisch ausgeführt wird, wenn die Simulation gestartet wird. -end- ho.opt.ckall -begin- Falls diese Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation bei der positiven Flanke jeder Taktquelle in der Schaltung an. -end- ho.opt.ckspec -begin- Falls dieser Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation nur an der positiven Flanke der spezifizierten Taktquelle an. -end- ho.opt.keybind -begin- Legt den Stil für Tastenbindungen fest. Wird diese Option geändert, werden die Bindungen sofort aufge- frischt. Allerdings muß TkGate neu gestartet werden, damit irgendwelche benutzerdefinierten Tastaturbindungen zu sehen sind. -end- ho.deftech -begin- Standard-Technologie für neue Gatter. Beeinflußt die Verzögerungszeit der Gatter. Um die Technologie eines bestimmten Gatters zu ändern, öffnet mann die Eigenschafts-Box mit Doppelklick und wählt "Delay" an. -end- ho.techbut -begin- Benutze Verzögerungszeiten aus der Datei zur Definition der Standard Technologie. Um eigene Technologien zu entwickeln, füge man sie zu der Liste im "Datei -> Optionen -> Simulation"-Menu hinzu. -end- ho.custbut -begin- Setze eigene Verzögerungszeitwerte für dieses Gatter. -end- ho.contver -begin- Verifiziere die Integrität der internen Datenstrukturen nach jeder Operation. -end- ho.simwatch -begin- Zeige Kommandos an, die zwischen GUI und Simulator gesendet werden. -end- ho.symed.point -begin- Pixel-Editiermodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.line -begin- Geraden-Modus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.rect -begin- Rechteckmodus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.fillrect -begin- Ausgefüllter Rechteckmodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.select -begin- Bitmap Auswahlmodus. Die linke Maustaste wählt Bereiche der Bitmap aus. Auf der Auswahl können dann Cut und Paste Operationen vorgenommen werden. -end- ho.symed.port -begin- Portauswahlmodus. Wähle Ports aus, bewege sie oder rotiere sie. -end- ho.symed.rshift Ausgewählte Pixel rechtsverschieben. ho.symed.lshift Ausgewählte Pixel linksverschieben. ho.symed.ushift Ausgewählte Pixel nach oben verschieben. ho.symed.dshift Ausgewählte Pixel nach unten verschieben. ho.symed.cwrotate Ausgewählte Pixel rechts drehen. ho.symed.ccwrotate Ausgewählte Pixel links drehen. ho.symed.autobold Das ausgewählte Bild fett machen. ho.symed.resize Den Bildeditor in der Größe ändern. ho.symed.import Bild aus einer Datei importieren. ho.symed.export Bild in eine Datei exportieren. ho.tool.currot -begin- Zeigt aktuelle Vorgabe des Rotationswinkels an. Ändern durch Klick auf diese Taste. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotieren der ausgewählten Gatter gegen den Uhrzeigersinn. ho.tool.brotate Rotieren der ausgewählten Gatter mit dem Uhrzeigersinn. ho.tool.valgn Ausgewählte Gatter vertikal ausrichten. ho.tool.halgn Ausgewählte Gatter horizontal ausrichten. ho.tool.cut Ausschneiden des ausgewählten Teils. ho.tool.copy Kopieren des ausgewählten Teils.. ho.tool.paste Einfügen aus dem Cut-Puffer. ho.tool.find Gatter, Leitungen oder Text suchen (und finden). ho.tool.addport Zum ausgewählten Gatter einen Port hinzufügen. ho.tool.anchor Die ausgewählten Gatter verankern. ho.tool.unanchor Die ausgewählten Gatter loslassen. ho.tool.replicate Replizieren eines Gatters. ho.tool.delete Löschen der Auswahl. tkgate-2.0-b10/locale/de/messages.iso8859000644 001751 001751 00000261207 11132534147 020527 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by bartke So 11. Jan 17:29:58 CET 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## ############################################################################## # # basic strings # b.new Neu... b.dismiss Beenden b.close Schließen b.ok OK b.clear Clear b.cancel Abbrechen #b.open Öffnen... #b.bitw Bitbreite b.in Eingang b.out Ausgang b.inout Bidirektional b.browse Durchsuchen... b.label Marke b.find Suchen b.edit Editieren... b.add Hinzufügen... b.delete Löschen #b.deleteb Löschen... b.remove Entfernen b.apply Anwenden b.anchor Anker b.tech Technologie #b.enable Freischalten #b.disable Sperren #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editieren tab.editintr Schnittstelle tab.simulate Simulieren tab.cpath Kritischer Pfad ############################################################################ # # Module tabs # module.tree Tree module.list List ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Hinzufügen... mm.delete Löschen mm.edit Editieren... mm.enable Freischalten mm.disable Sperren ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:Datei menu.edit 0:Editieren menu.tool 0:Werkzeug menu.symbol 0:Symbol menu.simulate 0:Simulieren menu.module 4:Modul menu.interface 0:Schnittstelle menu.gate 0:Gatter menu.make 0:Bausteine menu.help 0:Hilfe menu.file.new 0:Neu... menu.file.open 1:Öffnen... menu.file.openlib 3:Bibliotheksmanager... menu.file.save 0:Sichern menu.file.saveas 8:Sichern unter... menu.file.print 0:Drucken... menu.file.options 0:Optionen... menu.file.quit 0:Quit menu.file.cprop 10:Schaltungseigenschaften... menu.file.import 0:Bild Import... menu.file.export 0:Bild Export... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Ausschneiden menu.edit.copy 0:Kopieren menu.edit.paste 0:Einfügen menu.edit.overlay 1:Overlay einfügen menu.edit.selall 1:Alles auswählen menu.edit.find 0:Suchen... menu.edit.algnv 11:Ausrichten Ver. menu.edit.algnh 11:Ausrichten Hor. menu.edit.rotate 2:Drehen menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 16:Bitverschiebung Rechts menu.edit.lshift 16:Bitverschiebung Links menu.edit.ushift 16:Bitverschiebung Auf menu.edit.dshift 17:Bitverschiebung Ab menu.edit.cwrotate 11:Bitrotieren rechts menu.edit.ccwrotate 15:Bitrotieren links menu.edit.pcwrotate 12:Portrotieren rechts menu.edit.pccwrotate 16:Portrotieren links menu.edit.autobold Bits fett anzeigen menu.edit.resize Bitmapgröße anpassen menu.tool.move 0:Bewegen/Verbinden menu.tool.delg 0:Gatter löschen menu.tool.cutw 0:Leitung trennen menu.tool.inv 0:Invertieren menu.tool.bitw 0:Bitbreite menu.tool.debug 0:Debug menu.tool.point 0:Punkt menu.tool.line 0:Gerade menu.tool.rect 0:Rechteck menu.tool.fillrect 0:Rechteck füllen menu.tool.port 0:Port menu.tool.select 0:Gebiet auswählen menu.tool.rot0 4:Rot 0 menu.tool.rot90 4:Rot 90 menu.tool.rot180 4:Rot 180 menu.tool.rot270 4:Rot 270 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin 0:Beginn Simulation menu.simulate.end 0:Ende Simulation menu.simulate.addprobe 0:Tastkopf hinzufügen/löschen menu.simulate.run 0:Laufen lassen menu.simulate.pause 0:Pause menu.simulate.step 0:Epochenschritt(e) menu.simulate.cycle 5:Periodenschritt(e) menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Skript ausführen... menu.simulate.load 16:Speicherbereich laden... menu.simulate.dump 16:Speicherbereich ausgeben... menu.module.open 0:Öffnen menu.module.close 0:Schließen menu.module.new 0:Neu... menu.module.del 0:Löschen... menu.module.copy 0:Kopieren... menu.module.rename 0:Umbenennen... menu.module.claim 1:Aneignen... menu.module.setroot 1:Zur Wurzel machen... menu.module.prop 0:Eigenschaften... menu.module.interface 0:Schnittstelle menu.module.interface.set 0:Definieren menu.module.interface.update 1:Sync. to Default menu.module.interface.updateall 6:Sync. All to Default... menu.module.interface.edit 0:Editieren... menu.module.interface.auto 5:Automatisch erzeugen... menu.gate.addport 0:Port hinzufügen menu.gate.ioset 0:IO-Typ definieren menu.gate.anchor 0:Verankern menu.gate.unanchor 0:Freigeben menu.gate.prop 0:Eigenschaften dieser Instanz... menu.gate.rep 0:Vervielfachen menu.gate.del 0:Löschen menu.gate.settech 0:Technologie festlegen menu.help.about 0:Autor... menu.help.license 0:Lizenz... menu.help.doc 0:Dokumentation... menu.help.tut 1:Tutorien menu.help.home 1:Startseite menu.help.example 1:Beispiele ############################################################################# # Scope Menu # menu.scope_file 0:Datei menu.scope_sim 0:Simulieren menu.scope_trace 0:Signaldiagramm menu.scope_help 0:Hilfe menu.scope_file.ptrace 0:Drucken Signaldiagramm... menu.scope_file.close 0:Schließen menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Tastkopf hinzufügen/löschen menu.scope_sim.run 0:Laufen lassen menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Epochenschritt(e) menu.scope_sim.cycle 5:Periodenschritt(e) menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Skript ausführen... menu.scope_sim.load 16:Speicherbereich laden... menu.scope_sim.dump 16:Speicherbereich ausgeben... menu.scope_help.about 0:Autor... menu.scope_help.license 0:Lizenz... menu.scope_help.doc 0:Dokumentation... mod.intf Schnittstelle port.title TkGate: Porteigenschaften port.parms Portparameter port.in Eingang port.out Ausgang port.inout Ein/Ausgang ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gatter gm.rgate Reduktion gm.msi MSI gm.alu ALU gm.mem Speicher gm.mod Module gm.comment Kommentar gm.frame Rahmen gm.io.switch Schalter gm.io.dip DIP Schalter gm.io.ground Masse gm.io.vdd Vdd gm.io.merge Zusammenführen gm.io.clock Taktgeber gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direkt) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Puffer gm.gate.inv Inverter gm.gate.tribuf Tri-Puffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Addierer gm.alu.mult Multiplizierer gm.alu.div Dividierer gm.alu.lshift Linksshift gm.alu.rshift Rechtsshift gm.alu.arshift Arith. Rechtsshift gm.alu.roll Zyklischer Shift gm.mem.reg Register gm.mem.ff Flip-Flop gm.mem.rff Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexer gm.msi.41mux 4-1 Multiplexer gm.msi.81mux 8-1 Multiplexer gm.msi.12dec 1-2 Dekoder gm.msi.14dec 1-4 Dekoder gm.msi.18dec 1-8 Dekoder gm.mod.inst Module Instanz gm.mod.in Module Eingang gm.mod.out Module Ausgang gm.mod.inout Module Ein/Ausgang tutorial.prev ZURÃœCK tutorial.next WEITER tutorial.chapter INHALTSVERZEICHNIS tutorial.reload NEU LADEN ############################################################################## # # Popup menus # pop.make Bausteine pop.tool Werkzeug pop.edit.paste Einfügen pop.edit.cut Ausschneiden pop.edit.copy Kopieren pop.port.in Eingang pop.port.out Ausgang pop.port.inout Ein/Ausgang pop.wire.addseg Leitungssegment hinzufügen pop.wire.prop Schaltungseigenschaften... pop.wire.hidesize Bitbreite verstecken pop.wire.showsize Bitbreite anzeigen pop.wire.hidelabel Namen verstecken pop.wire.hidealllabel Alle Namen verstecken pop.wire.clearalllabel Alle Namen löschen pop.wire.showlabel Namen anzeigen pop.gate.open Öffnen pop.gate.close Schließen pop.gate.prop Instanzeigenschaften... pop.gate.addport Port hinzufügen pop.gate.addin Eingang hinzufügen... pop.gate.addout Ausgang hinzufügen... pop.gate.addinout Ein/Ausgang hinzufügen... pop.gate.anchor Verankern/Loslösen pop.gate.settech Technologie festlegen pop.gate.delete Löschen pop.gate.ioset Typ festlegen pop.module.new Neu... pop.module.del Löschen... pop.module.copy Kopieren... pop.module.rename Umbenennen... pop.module.claim Aneignen... pop.module.setroot Als Wurzel festlegen... pop.module.prop Moduleigenschaften... pop.module.int Schnittstelle editieren... pop.simulate.end Ende Simulation pop.simulate.begin BeginN Simulation pop.simulate.addprobe Tastkopf hinzufügen pop.simulate.delprobe Tastkopf löschen pop.simulate.run Laufen lassen pop.simulate.pause Pause pop.simulate.step Epochenschritt(e) pop.simulate.cycle Periodenschritt(e) pop.simulate.break Breakpoint... pop.simulate.script Skript ausführen... pop.simulate.load Speicherbereich laden... pop.simulate.dump Speicherbereich ausgeben... pop.interface Schnittstelle pop.interface.set Als Standard setzen pop.interface.update Abgleichen mit Standard pop.interface.updateall Alles abgleichen mit Standard... pop.interface.edit Editieren... pop.interface.auto Automatisch erzeugen... pop.interface.replace Ersetzen pop.igen.type Typ pop.igen.side Seite pop.igen.size Größe pop.igen.delete Löschen pop.igen.in Eingang pop.igen.out Ausgang pop.igen.inout Ein/Ausgang pop.igen.left links pop.igen.right rechts pop.igen.top oben pop.igen.bottom unten pop.igen.other sonstige ############################################################################## # # Symbol editor strings # #symed.bsave Speichern #symed.file Datei #symed.file.load Bitmap laden... #symed.file.save Bitmap sichern... #symed.file.updateclose Auffrischen und schließen #symed.file.discardclose Verwerfen und schließen #symed.help Hilfe #symed.help.about Zu... #symed.edit Editieren #symed.edit.cut Ausschneiden #symed.edit.copy Kopieren #symed.edit.paste Einfügen #symed.edit.overlay Overlay einfügen #symed.edit.rclock Rechts drehen #symed.edit.rcclock Links drehen #symed.module Modul #symed.modes Modes #symed.cutpaste Ausschneiden/Einfügen #symed.rotate Port drehen #symed.zoom Zoom #symed.cancel Abbrechen #symed.update Auffrischen symed.tab.normal Nicht ausgewählt symed.tab.select Ausgewählt symed.link Ausgewähltes mit Unausgewähltem verlinken # width of symbol editor tabs ############################################################################## scope.emptymsg Doppelklick auf eine Leitung fügt ein Signal ein oder löscht es comment.empty [Text hinzufügen mit Doppelklick.] ############################################################################## # Interface strings # ifile Datei imodule Modul iblmodule Module iports Ports ibits Bits: itype Typ: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file Dateiname db.mod.type Typ db.mod.flags Flags db.mod.dataprot Editieren der Moduldefinition verhindern. db.mod.intfprot Schnittstellenveränderungen verhindern. db.mod.edprot Schnittstellenveränderungen im Editiermodus verhindern. db.mod.props Eigenschaften db.mod.inuse.0 Modul wird nicht benutzt. db.mod.inuse.1 Modul wird benutzt. db.mod.lmod.0 Modul seit dem Laden nicht verändert. db.mod.lmod.1 Modul seit dem Laden verändert. db.mod.smod.0 Modul seit dem Sichern nicht verändert. db.mod.smod.1 Modul seit dem Sichern verändert. db.mod.islib.1 Modul ist Teil der [%s] Bibliothek. db.mod.islib.0 Modul ist kein Bibliotheksmodul. db.mod.netlist Bauteilliste db.mod.hdl HDL db.mod.netexpl -begin- Moduldefinition mit einem graphischen Editor, um Leitungen zwischen Komponenten zu ziehen -end- db.mod.hdlexpl -begin- Moduldefinition mit einem Texteditor, um das Verhalten in Verilog zu beschreiben. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Fehlerliste db.err.caption Fehlerliste db.err.explain -fillbegin- Wegen Schaltungsfehler(n) kann der Simulationsmodus nicht aufgerufen werden. Die fehlerhafte Stelle ist nach Anwahl der entspr. Fehlermeldung zu sehen. -end- db.err.neededit -fillbegin- Zum Navigieren zu den Warnungen muß erst in den Edit Modus geschaltet werden. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Netzeigenschaften db.net.caption Netzeigenschaften db.net.name Netzname db.net.hide Name verstecken db.net.bits Bitbreite db.net.type Netztyp db.net.port Porttyp db.net.in Eingang db.net.out Ausgang db.net.inout Ein/Ausgang db.net.inets Netze ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: Neue Schaltung db.newcirc.directory Verzeichnis: db.newcirc.cap Neue Schaltung db.newcirc.exp -fillbegin- Die aktuelle Schaltung verwerfen und eine neue Schaltung bearbeiten. -end- db.newcirc.file Dateiname db.newcirc.topname Name des obersten Moduls ############################################################################## # Gate dialog box # db.gate.title TKGate: Gattereigenschaften db.gate.signam Signalname db.gate.portnam Portname db.gate.iotype Typ db.gate.bitw Bitbreite db.gate.cyclew Taktlänge db.gate.phase Phase db.gate.duty Taktverhältnis db.gate.port Port db.gate.bitws Bits db.gate.side Seite db.gate.gtype Gattertyp db.gate.gname Gattername db.gate.hidenam Namen verstecken db.gate.anchor Verankern db.gate.cpbreak Aufteilung des kritischen Pfades db.gate.butstate Schalterzustand db.gate.dipval Schalterstellung db.gate.range Bitbereich db.gate.memfilenam Dateiname f. Speicherinhalt db.gate.modname Funktion db.gate.general Allgemein db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Verzögerung db.gate.parameters Parameter db.gate.stddelay Standardverzögerung db.gate.custdelay Einstellen der Verzögerung db.gate.catdiruse Platzieren des Ports db.gate.edit Editieren db.gate.delete Löschen db.gate.add Hinzufügen db.gate.ff.type Flip-Flop Ausrichtung db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- Der Datenfluß im Flip-Flop ist von links nach rechts. -end- db.gate.ff.reverse.hdr Umgekehrt db.gate.ff.reverse.exp -fillbegin- Der Datenfluß im Flip-Flop ist von rechts nach links. -end- db.gate.cat.asc.hdr Aufsteigend db.gate.cat.dec.hdr Absteigend db.gate.cat.asc.exp -fillbegin- Bits werden in aufsteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.dec.exp -fillbegin- Bits werden in absteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.sigdir Signalrichtung db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Mehrfacheingang db.gate.cat.singin.hdr Einzelner Eingang db.gate.cat.tran.hdr Bidirektional db.gate.cat.auto.exp -fillbegin- Die Signalrichtung wird automatisch aus den verbundenen Teilschaltungen erschlossen. -end- db.gate.cat.multin.exp -fillbegin- Die Seite mit Mehrfachleitung wird immer als Eingang angenommen. -end- db.gate.cat.singin.exp -fillbegin- Die Seite mit der Einzelleitung wird immer als Eingang angenommen. -end- db.gate.cat.tran.exp -fillbegin- Bidirektionaler Signalfluß (transmission) ist erlaubt. Kann nicht mit Schaltern oder Registern verbunden werden. -end- # Minimum size of textbox for comment (in characters) # @db.gate.comment.width 80 @db.gate.comment.height 30 db.gate.tab.General.cap Allgemeine Eigenschaften db.gate.tab.Ports.cap Porteigenschaften db.gate.tab.Delay.cap Eigenschaften der Verzögerung db.gate.tab.Parameters.cap Modulparameter db.gate.tab.CLOCK.cap Takteigenschaften db.gate.tab.SWITCH.cap Schaltereigenschaften db.gate.tab.DIP.cap DIP Eigenschaften db.gate.tab.TAP.cap Tran Eigenschaften db.gate.tab.RAM.cap RAM Eigenschaften db.gate.tab.ROM.cap ROM Eigenschaften db.gate.tab.MODULE.cap Moduleigenschaften db.gate.tab.FRAME.cap Rahmeneigenschaften db.gate.tab.LED.cap LED Eigenschaften db.gate.tab.AND.cap AND Eigenschaften db.gate.tab.OR.cap OR Eigenschaften db.gate.tab.XOR.cap XOR Eigenschaften db.gate.tab.MUX.cap Mux Eigenschaften db.gate.tab.DEMUX.cap Demux Eigenschaften db.gate.tab.CONCAT.cap Concat Eigenschaften db.gate.tab.COMMENT.cap Text Eigenschaften db.gate.tab.FF.cap Flip-Flop Eigenschaften db.gate.tab.General.exp -fillbegin- Die grundlegenden Eigenschaften einer Instanz ansehen und verändern. -end- db.gate.tab.Ports.exp -fillbegin- Hinzufügen, Editieren oder Löschen von Ports einer Instanz. -end- db.gate.tab.Delay.exp -fillbegin- Die Verzögerung kann entweder durch Angabe der Technologie oder durch spezielle Werte für diese Instanz festgelegt werden. -end- db.gate.tab.Parameters.exp -fillbegin- Festlegen der Modulparameter dieser Modulinstanz, falls welche definiert sind. Modulparameter werden zur Definition von Verzögerungen und konstanten Werten in Moduln verwendet. -end- db.gate.tab.details.exp -fillbegin- Genaue Festlegung der typspezifischen Eigenschaften eines Gatters. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Definition des Textes in einem Kommentar. Es können in beschränktem Umfang HTML Tags einschließlich Links verwendet werden. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Wert db.gate.mparm.exampleA -begin- Dieses Modul hat keinerlei Parameter. Parameter können zu Verilog-Textmodulen hinzugefügt werden. Dert Wert jedes Parameters kann für jede Instanz durch diese Dialogbox konfiguriert werden. Modul- Parameter werden als geklammerte Liste deklariert, die mit einem # beginnt. Hier ist ein Beispiel einer Moduldeklaration mit einem Parameter namens "base_value", der einen Standardwert von 1'b1 besitzt. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder Eingangsordnung db.gate.mux.ord1.hdr Links-rechts db.gate.mux.ord2.hdr Rechts-links db.gate.mux.ord1.exp -fillbegin- Ordne MUX-Eingänge von links nach rechts. -end- db.gate.mux.ord2.exp -fillbegin- Ordne MUX-Eingänge von rechts nach links. -end- db.gate.demux.dataorder Ausgangsordnung db.gate.demux.ord1.hdr Links-rechts db.gate.demux.ord2.hdr Rechts-links db.gate.demux.ord1.exp -fillbegin- Ordne DEMUX-Ausgänge von links nach rechts. -end- db.gate.demux.ord2.exp -fillbegin- Ordne DEMUX-Ausgänge von rechts nach links. -end- db.gate.mux.select Auswahlstil db.gate.mux.sel1.hdr Selektor links db.gate.mux.sel2.hdr Selektor rechts db.gate.mux.sel1.exp -fillbegin- Setze den Datenselektor auf der linken Seite des Gatters. -end- db.gate.mux.sel2.exp -fillbegin- Setze den Datenselektor auf der rechten Seite des Gatters. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse Nutzung von Erweiterungsbalken db.gate.aox.use.hdr Erweiterungsbalken db.gate.aox.nouse.hdr Keine Erweiterungsbalken db.gate.aox.use.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden diese an Erweiterungsbalken angebracht. -end- db.gate.aox.nouse.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden keine Erweiterungsbalken verwendet. -end- db.gate.led.type LED Typ db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Balkenanzeige db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direkt) db.gate.led.bit.exp -fillbegin- Einzelne LED-Anzeige für 1-Bit-Signale. -end- db.gate.led.bar.exp -fillbegin- LED Balkenanzeige mit einem Balken pro Bit. -end- db.gate.led.hex.exp -fillbegin- Hexadezimale Anzeige des Signals. -end- db.gate.led.dec.exp -fillbegin- Dezimale Anzeige des Signals. -end- db.gate.led.seg.exp -fillbegin- Die Signalbits steuern direkt die LED-Segmente a-g. -end- db.seq.back db.hdl.namechange.title HDL Modulname geändert db.hdl.textdisp.title HDL Textdisposition db.hdl.savecap Mehrfach-Module db.hdl.saveexp -fillbegin- Der Textpuffer des gerade editierten Moduls enthält mehr als eine Moduldefinition. Bitte wähle eine der drei Aktionen auf der rechten Seite aus. -end- db.hdl.autoedit Auto-Editieren db.hdl.split Aufteilen db.hdl.comment Kommentar db.hdl.cancel Abbrechen db.hdl.ignore Ignorieren db.hdl.autoeditcap Der Name paßt nicht db.hdl.autoeditexp -fillbegin- Die Textbeschreibung des Moduls paßt nicht zum erwarteten Namen. Wähle eine der Optionen rechts, um dieses Problem zu beseitigen. -end- db.dip.title TkGate: Dip-Wert cpath.cloops -fillbegin- In der kombinatorischen Schaltung wurde eine Rückkopplung entdeckt. Um für diese Schaltung eine Verzögerungsanalyse durchführen zu können, muß entweder die Rückkopplung aufgebrochen werden oder einige der Gatter im Rückkopplungszweig werden als "Kritische-Pfad-Aufteilung" markiert. Schaltungsteile, in denen eine Rückkopplung ent- deckt wurde, sind unten gelistet. -end- ############################################################################## # Print dialog box # #print.outto Ausgabe nach print.title TkGate: Drucken print.config.title TkGate: Druckerkonfiguration print.scope.title TkGate: Scopedruck print.printer Drucker: print.file Datei print.prcmd Druckbefehl: print.prname Drucker print.advanced Erweitert... print.filename Dateiname print.epssave Sichern als Encapsulated Postscript. #print.doctit Dokumenttitel #print.prmod Druck von Modulen print.epcm Epochen/cm print.estpg Ungefähre Seitenzahl print.all Alles print.cur Aktuelle print.use Benutzte print.sel Ausgewählte print.inclib Bibliotheksmodule einbeziehen. print.incunused Unbenutzte Module einfügen. print.papsz Papiergröße print.orient Orientierung print.portrait Hochformat print.landscape Querformat print.2side Duplexdruck print.opts Optionen print.scale Anpassen großer Module auf eine Seite. print.partition Aufteilen großer Module auf mehrere Seiten. print.incidx Index hinzufügen. print.incgraph Hierarchiegraph hinzufügen. print.4up Kleine Module: vier auf eine Seite drucken. print.rangeselection Wahl des Bereichs print.scaleselect Wahl der Skalierung print.fulltr Vollständiges Signaldiagramm print.parttr Ausschnitt aus dem Signaldiagramm print.start Start print.range Bereich print.linelen Zeilenlänge print.filesel Ausgabe in Datei print.printersel Ausgabe auf Drucker print.defaultprinter Standarddrucker print.pageset Seiteneinstellungen print.modulesel Modulauswahl ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Drucken print.printtrace.cap Signaldiagramm drucken print.printcirc.cap Schaltung drucken print.printcirc.out.exp -fillbegin- Wahl der Druckausgabe: direkt zum Drucker oder in eine PostScript-Datei. -end- print.printcirc.page.exp -fillbegin- Auswahl der Optionen für den Seitenaufbau und den Drucker. -end- print.printcirc.mod.exp -fillbegin- Auswahl der zu druckenden Module, Einstellung der Optionen für die Darstellung. -end- print.printtrace.trace.exp -fillbegin- Auswahl des Zeitbereichs für die Ausgabe und Einstellung der Skalierung, um die ungefähre Seitenzahl zu berechnen. -end- print.tab.output Ausgabe #print.tab.page Seite print.tab.modules Module print.tab.content Inhalt print.tab.advanced Einstellungen ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Optionen opt.treelabel Optionen opt.general Allgemein opt.interface Schnittstelle opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Drucken opt.print.output Ausgabe opt.print.content Inhalt opt.simulate Simulieren opt.simulate.basic Grundlegendes opt.simulate.tech Technologie opt.simulate.error Fehlerbehandlung opt.library Bibliotheken opt.library.path Pfad opt.library.load Autom. Laden opt.library.vpd VPD opt.analysis Analyse opt.color Farben opt.color.title TkGate: Farbauswahl opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Verfügbare Bibliotheken opt.lib.load.selected Ausgewählte Bibliotheken opt.identity Organisation opt.site Netzadresse opt.username Benutzername opt.libname Bibliotheksname: opt.inst Instanzen opt.mods Module opt.modports Modul-Ports opt.frames Rahmen opt.comment Kommentare opt.hlink Hyperlinks opt.wire Einfach-Leitungen opt.bus Mehrfachleitungen opt.tools Gatter-Werkzeuge opt.background Hintergrund opt.cpath Kritischer Pfad opt.grid Scope Raster opt.logic1 Logisch Eins opt.logic0 Logisch Null opt.float Float opt.unknown Unbekannt/Konflikt opt.offled LED aus opt.onled LED ein opt.zled Undefinierte LED opt.restdef Auf Standard zurücksetzen opt.regudate Auffrischen eines Gebiets opt.smoothscroll Glattes Scrolling opt.balloon Hilfeballone einschalten opt.safeSave Sicheres Abspeichern der Dateien opt.saveCells Zellen in abgespeicherte Dateien einbeziehen opt.showimage Zeige Randstreifenbilder in Dialogboxen opt.novice Novizenmodus opt.blockDropConnect Porterzeugung mit Fallenlassen von Leitungen opt.ckpoint.1 Checkpointing alle opt.ckpoint.2 Kommandos ausführen. opt.freq Intervall opt.beak Sondermodi einstellen opt.bat Bat opt.trek Star Trek opt.miles Heinrich opt.contver Automatische Integritätsprüfung opt.showsimcmd Anzeige der Simulationsgeschichte opt.estepsz Epochen Schrittweite opt.cstepsz Periodendauer Schrittweite opt.overstep Takt Ãœberschreitung opt.sorttraces Scope-Signale alphabetisch sortieren opt.vpopupdelay Pop-Up Verzögerungswert #opt.initscript Globales Initialisierungsskript opt.posedge Takt hält an allen positiven Flanken opt.setclock Takt hält an allen Flanken opt.delayfilepath Technologiedateien opt.devfilepath VPD (Virtuelles Peripheres Device) Dateipfad opt.vlibpath Verilog Bibliothekspfad opt.vlibnames Basisbibliotheken opt.display Anzeige opt.interaction Interaktion opt.input Eingabe opt.security Sicherheit opt.undolen Maximale Anzahl von Undo-Op. opt.keybind Tastaturbelegungsstil opt.useless Nutzlose Features einschalten opt.features Basis Features opt.simbase Grundlegende Simulatoroptionen opt.simclock Taktoptionen opt.cpopts Optionen für Kritische Pfade opt.maxpath Maximalzahl der Pfade: opt.cpflash Anzeige mit blinkendem Pfad opt.general.fontset Font-Klasse opt.simulator.savetraces Tastkopfpositionen zwischen Simulatorläufen sichern. opt.simulator.noglitch Glitch-Unterdrückung im Simulator einschalten. opt.simulator.err Fehlerbehandlung opt.simulator.stopany Abbrechen der Simulation bei jeder Warnung. opt.simulator.showall Warnungen immer anzeigen. opt.simulator.showiferr Warnung nur bei Fehlern. opt.simulator.ignore Alle Warnungen ignorieren. opt.tool.file Datei opt.tool.edit Editieren opt.tool.gateopt Drehen/Ausrichten opt.tool.gateprop Gatter opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Modus opt.tool.module Module opt.tool.tech Technologie opt.tool.simctl Simulatorsteuerung opt.tool.simaux Simulatorbefehle opt.tool.simmode Simulator Werkzeuge opt.tool.symmode Symboleditor Werkzeuge opt.tool.symedit Ausschneiden/Einfügen opt.tool.symport Ports opt.tool.symshift Bitverschiebung opt.tool.symopr Bitoperationen opt.editor.features Editor Features: Grundlagen opt.editor.format Automatische Einrückung einschalten opt.editor.colorize Syntax Highlighting einschalten opt.editor.comments Kommentare opt.editor.strings Strings opt.editor.reserved Schlüsselwörter opt.editor.gateword Eingebaute Gatter opt.editor.instword Modulinstanzen opt.editor.taskword Systemaufgaben opt.editor.color Farbe opt.editor.bold Fett opt.editor.italic Schräg opt.editor.indentlevel Einrückung per Stufe: opt.editor.beginindent Ausrichten von begin...end an der Einrücktiefe. opt.editor.movesel Drag-and-drop der Wahl einschalten. opt.editor.returntab Automatische Einrückung nach RETURN. opt.vercheck -begin- Periodische Nachfrage nach neuen TkGate-Versionen im Internet. Dieses Feature sollte nur bei dauerhaftem Internetzugang eingeschaltet werden. -end- opt.general.cap Allgemeine Optionen opt.editor.cap HDL Text Editor opt.interface.cap Schnittstellenoptionen opt.toolbars.cap Toolbaroptionen opt.print.cap Druckoptionen opt.analysis.cap -begin- Kritische Pfad-Optionen -end- opt.simulator.cap Simulatoroptionen opt.security.cap Sicherheitsoptionen opt.color.cap Farboptionen opt.html.cap HTML/HTTP Optionen opt.debug.cap Debug-Optionen opt.library.cap Bibliotheksoptionen opt.sec.execlevel Die $tkg$exec() Systemroutine ist opt.sec.exec komplett eingeschaltet. opt.sec.regexec nur für registrierte Funktionen eingeschaltet. opt.sec.noexec ausgeschaltet. opt.sec.simfeatures Simulator Features opt.sec.send $tkg$command() Systemroutine einschalten. opt.sec.open $fopen() Systemroutine einschalten. opt.sec.writemem $writememb() und $writememh() Systemroutinen einschalten. opt.sec.enqueue $tkg$recv() und $tkg$send() Systemroutinen einschalten. opt.sec.handle Behandlung von Sicherheitsverletzungen opt.sec.stop Beenden des Simulators bei Nutzung ausgeschalteter Features. opt.sec.warn Anzeige einer Warnung bei Nutzung ausgeschalteter Features. opt.sec.ignore Ignoriere versuchte Benutzung von ausgeschalteten Features. opt.html.linkopts Link Optionen opt.html.browser Browser Aufruf opt.html.email e-Mail Aufruf opt.debug.opt Debugging Optionen opt.color.editwin Fensterfarben editieren opt.color.scopewin Farben fürs Signaldiagramm-Fenster einstellen opt.vlibadd.title TkGate: Bibliothek hinzufügen opt.vlibadd.cap Bibliothek hinzufügen opt.vlibadd.exp -fillbegin- Gib den Dateinamen einer TkGate Verilog Bibliothek an. Bibliotheken aus der Autoload Liste werden automatisch beim Start geladen. -end- opt.editor.exp -fillbegin- Setzen der Optionen für den HDL Texteditor. -end- opt.general.exp -fillbegin- Persönliche Einstellungen und grundlegende TkGate-Optionen werden auf dieser Seite eingestellt. Die persönlichen Einstellungen werden bei der Druckausgabe benutzt. -end- opt.interface.exp -fillbegin- Einstellung der Optionen zur eigenen Gestaltung der Schnittstelle. -end- opt.toolbars.exp -fillbegin- Angabe der Toolbars, die angezeigt werden sollen. -end- opt.print.exp -fillbegin- Einstellung der Standard Druckeroptionen auf dieser Seite. -end- opt.analysis.exp -fillbegin- Diese Optionen steuern die Funktionen der kritischen Pfadanalyse. -end- opt.simulator.exp -fillbegin- Optionen, die das Arbeiten mit dem Simulator steuern. -end- opt.library.exp -fillbegin- Setzen der Suchpfade für Benutzer-Devices und Verilog-Bibliotheksdateien. -end- opt.security.exp -fillbegin- Einstellen der Simulator-Sicherheitsoptionen - Aus- bzw. Einschalten von Features kann ein Sicherheitsrisiko bei Simulation von Schaltungen aus nicht vertrauenswürdigen Quellen sein. -end- opt.color.exp -fillbegin- Optionen, die das in TkGate verwendete Farbschema steuern. -end- opt.html.exp -fillbegin- Setzen der Optionen für HTML Steueranweisungen in TkGate Schaltungskommentaren. -end- opt.debug.exp -fillbegin- Hier können Debuggingoptionen gesetzt werden. -end- opt.gen.basetoolbar Toolbars für den Editor-Kern opt.gen.simtoolbar Toolbars für den Simulationsmodus opt.gen.symedtoolbar Toolbars für den Symboleditor opt.bbar.restore Vorgaben dieser Seite wiederherstellen opt.bbar.restoreall Alle Vorgaben wiederherstellen ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Typ igen.side Seite igen.size Größe igen.bits Bits igen.modname Modulname: #igen.resort Erneut Sortieren igen.add Hinzufügen igen.delete Löschen igen.edit Editieren igen.in Eingang igen.out Ausgang igen.inout Ein/Ausgang igen.left links igen.right rechts igen.top oben igen.bottom unten #igen.other andere igen.mod Verwende nur Ports, die im Modul benutzt werden. igen.int Verwende nur Ports aus existierender Schnittstelle. igen.modint Verwende sowohl Modul- als auch Schnittstellen-Ports. igen.portsel Port Auswahl igen.portpos Port Positionen igen.portpos.keep Erhalte soweit möglich die Port-Positionen. igen.portpos.renew Erzeuge alle Port-Positionierungen neu. igen.caption Erzeugen der Schnittstelle igen.description -begin- Erzeugen einer neuen Schnittstelle für ein Modul. -end- info.script.error Skript Fehler module.props.title TkGate: Moduleigenschaften module.props Moduleigenschaften ipanel.plist Portliste ipanel.props Schnittstelleneigenschaften #ipanel.itype.change Typ ändern... #ipanel.itype.edsymbol Symbol editieren... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Automatisch erzeugen... ipanel.updateall Alles auffrischen... ipanel.itype.select Schnittstellentyp #ipanel.block.description Standardschnittstelle #ipanel.symbol.description Benutzerdefinierte Symbolschnittstelle ipanel.ppos.label Blockgröße verändern (mit Ortsveränderung der Ports): ipanel.ppos.fix Feste Positionen ipanel.ppos.scale Skalierte Positionen #ipanel.ppos.grid Raster ipanel.warn.toblock -begin- Der Schnittstellentyp dieses Moduls soll nach "Block" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Ist das wirklich so gewollt? -end- ipanel.warn.tosymbol -begin- Der Schnittstellentyp dieses Moduls soll nach "Symbol" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Zusätzlich muß ein neues Bitmapbild für das neue Symbol erzeugt werden. Ist das wirklich so gewollt? -end- ############################################################################## # # Block list dialog boxes blklst.delete.title TKGate: Modul löschen blklst.copy.title TKGate: Modul kopieren blklst.rename.title TKGate: Modul umbenennen blklst.claim.title TKGate: Modul aneignen blklst.setroot.title TKGate: Wurzel-Modul festlegen blklst.new.title TKGate: Neues Modul blklst.claim Modul aneignen blklst.to Nach blklst.from Von blklst.name Name blklst.new.cap Neues Modul erzeugen blklst.del.cap Modul löschen blklst.copy.cap Modul kopieren blklst.rename.cap Modul umbenennen blklst.claim.cap Modul aneignen blklst.setroot.cap Wurzel-Modul festlegen blklst.new.exp -fillbegin- Mit dieser Dialogbox wird eine neue Moduldefinition erzeugt. Das Modul kann als Netzliste oder HDL Modul erzeugt werden. Einmal erzeugt, kann der Typ aber nicht geändert werden; es muß gelöscht und neu erzeugt werden. -end- blklst.del.exp -fillbegin- Löschen der Definition und Schnittstellendaten des angegebenen Moduls. Existierende Instanzen des gelöschten Moduls beleiben erhalten, werden aber als undefiniert markiert. -end- blklst.copy.exp -fillbegin- Erzeugen einer Kopie der angegebenen Moduldefinition. Damit kann eine Variante eines existierenden Moduls erschaffen werden. -end- blklst.rename.exp -fillbegin- Umbenennen einer Moduldefinition. Diese Operation betrifft nur die Definition, alle existierenden Instanzen dieses Moduls verweisen weiterhin auf den alten Modulnamen. -end- blklst.claim.exp -fillbegin- Umwandeln eines Bibliotheksmoduls in ein Benutzermodul. Damit kann das Modul editiert und zusammen mit der eigenen Schaltung gesichert werden. -end- blklst.setroot.exp -fillbegin- Mache das angegebene Modul zum obersten (Top-Level). -end- find.title TkGate: Objekte finden find.label Objekte finden find.exp -fillbegin- Suche den Mustertext entweder in Gatternamen, Leitungsnamen oder in Kommentaren. Ein Doppelklick auf das Resultat führt zum gesuchten Objekt. -end- find.ignorecase Groß/Kleinschreibung ignorieren find.result.module Modul find.result.type Typ find.result.name Objektname # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Suchoptionen find.results Suchresultate # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Enthält... find.qual.begins Fängt an mit... find.qual.ends Endet mit... find.qual.matches Paßt auf... find.dom.label Nach Objekten suchen in: find.dom.gates Gatter find.dom.nets Schaltungen find.dom.text Kommentartext find.search Suchen: find.target Ziel # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Schaltungseigenschaften circ.label Schaltungseigenschaften circ.ident Identifikation circ.filev Dateiversion circ.file Dateiname circ.title Schaltungsüberschrift circ.discchg Keine Warnungen bei Verwerfen von Änderungen. circ.extbar Erweiterungsleisten benutzen. circ.autostart Automatischen Simulationsstart einschalten. circ.iniscript Initialisierungsskripte #circ.noscript Keine Skriptdateien ausgewählt. #circ.really Soll '%s' wirklich aus der Liste der Inititalisierungsskripte gelöscht werden? circ.reallyupdate -fillbegin- Sollen wirklich alle '%s' Instanzen der Schnittstelle geändert werden? -end- @circ.library.width *500 @circ.library.height *350 circ.general Allgemein circ.library Bibliotheken circ.script Skript circ.simulator Simulation circ.timescale Standard Simulations-Zeitskala circ.timescale.unit Einheit: circ.timescale.prec Genauigkeit: circ.exp -fillbegin- Schaltungsspezifische Eigenschaften betrachten und verändern. Diese Eigenschaften werden mit der Schaltung beim Sichern abgespeichert. -end- circ.exp.general -fillbegin- Betrachten und Modifizieren schaltungsspezifischer Eigenschaften. Diese Eigenschaften werden beim Speichern der Schaltung mitgesichert. -end- circ.exp.library -fillbegin- Auswählen der von dieser Schaltung benutzten Bibliotheken. Die Bibliotheksangaben werden mit der Schaltung gesichert, sie werden beim nächsten Laden der Schaltung automatisch eingelesen. -end- circ.exp.simulator -fillbegin- Anzeige und Modifikation der Simulationseinstellungen dieser Schaltung. -end- ############################################################################## # # Bibliotheksverwaltung # libmgr.cap Bibliotheksverwaltung libmgr.library Bibliothek libmgr.description Beschreibung libmgr.status Status libmgr.status.load Geladen libmgr.status.unload Nicht geladen libmgr.status.loadp [Geladen] libmgr.status.unloadp [Nicht geladen] libmgr.exp -fillbegin- Wähle zu ladende oder zu entfernende Bibliotheken aus. -end- libmgr.load Laden libmgr.unload Entfernen libmgr.unloadall Alle entfernen libmgr.notedit -fillbegin- Die Bibliotheksverwaltung kann nur im Editiermodus der Schaltung geöffnet werden. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- Rekursive Moduldefinition in '%s' gefunden. Simulator kann nicht gestartet werden. Keine kritische Pfadanalyse möglich. -end- sim.hyperlinkstop -fillbegin- Der Simulator läuft gerade. Soll die Simulation beendet und dem Link gefolgt werden? -end- ############################################################################## # # Critical path messages # cp.delay Pfadverzögerung: cp.pathl Pfadliste: cp.numpath Anzahl der Pfade: cp.recompute Neuberechnung ############################################################################## # Error messages # err.rootinterface Kann die Schnittstelle des obersten Moduls nicht definieren. err.nopin Ausgewählter Pin kann nicht verändert werden. err.badhex Illegaler Hexwert '%s', ignoriert. err.gatanchor Gatter ist (sind) verankert und können nicht bewegt werden. err.protdata Kann den Inhalt eines geschützen (Bibliotheks-)Moduls nicht ändern. err.badfind Kann Suchziel '%s' nicht finden. err.badopendel Kann geöffnetes Modul nicht löschen. err.nosrcmod Quelle zu Modul '%s' nicht gefunden. err.noerr Fehler nicht bestimmbar. err.misserr Fehler nur teilweise bestimmbar (Absturz des Simulators?) err.badinadd Kann keine Eingänge mehr zur angewählten Schaltung hinzufügen. err.badoutadd Kann keine Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badinoutadd Kann keine Ein/Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badpinchg Kann Pintyp des angewählten Gatters nicht ändern. err.badnetname Illegale Zeichen im Bezeichner gelöscht. err.netbcrename Bezeichner umbenannt in '%s' wegen illegaler Zeichen. err.netconfnet Bezeichner umbenannt in '%s' wegen Konflikten. err.netconfgat Bezeichner umbenannt in '%s' um Konflikt mit Grundgatternamen zu vermeiden. err.netconfkw Bezeichner umbenannt in '%s' um Konflikt mit Schlüsselwort zu vermeiden. err.badconsame Keine Verbindung, weil Leitungen Teil desselben Netzes sind. err.badconptsp Keine Verbindung, weil beide Leitungen Modulports oder Versorgungsleitungen sind. err.badconbitw Keine Verbindung, weil die Bitbreiten nicht zusammenpassen. err.badrange Nichtpositiver Bereich für Signaldiagramm nicht erlaubt. err.badlprcmd Druckkommando '%s' kann nicht ausgeführt werden. err.badpsopen Die Datei '%s' kann nicht für die Postscript-Ausgabe geöffnet werden. err.badid Ungültiger Bezeichner '%s' err.noinvgate Inverters sind auf Gattern dieses Typs nicht erlaubt. err.protintf Kann die geschützte Schnittstelle von Modul '%s' nicht ändern. err.bkpt.badexp Syntaxfehler in Breakpoint-Ausdruck. Mögliche Werte: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Ungültiger Netzname '%s'. Namen beginnen mit Buchstaben und enthalten nur Buchstaben, Ziffern und '.' err.bkpt.badval Syntaxfehler in Wert '%s'. Nur dezimale oder Verilog-Konstante erlaubt. err.bkpt.toomany Zu viele Breakpoints. Maximum ist %d. err.sim.badtmp Zwischendatei '%s' für Simulator konnte nicht gesichert werden (Platte voll?) err.sim.syntx Syntaxfehler in '%s' Kommando. err.sim.noincl Include-Datei '%s' nicht gefunden. err.sim.badedge Illegaler Flanken-Indikator '%c' in Takt-Kommando. err.sim.nobkpt Kein derartiger Breakpoint '%s'. err.sim.nonet Kann Netz '%s' nicht finden. err.sim.nogate Kann Gatter '%s' nicht finden. err.sim.badbin Illegales Zeichen in binärer Konstante '%s'. err.sim.notswitch Schaltung '%s' ist kein Schalter, DIP-Schalter oder Register. err.sim.badcmd Kommando '%s' im Simulations-Skript unbekannt. err.sim.isrun Simulator läuft bereits (Beenden mit 'Ctrl-s e'). err.sim.run Laufzeitfehler err.sim.cmd Interner Fehler (Befehl) err.noteditpchg Eigenschaften können nur im Edit-Modus geändert werden. err.badeditop Illegale Operation im Schnittstellen-Editiermodus. err.badopen Datei '%s' kann nicht geöffnet werden. err.badlibopen Bibliotheksdatei '%s' kann nicht geöffnet werden. err.nomark Vor dem Anwählen eines Schaltungstyps eine Markierung setzen (linke Maustaste). err.badgate Unbekannter Schaltungstyp. err.badportadd Zu diesem Gattertyp ist Hinzufügen von Ports nicht möglich. err.modmissing HDL Modultext fehlt für Modul "%s". err.modtoomany Ãœberzählige Moduldefinitionen in Modul "%s". err.modmismatch Namens-mismatch zwischen Textdefinition und Modulname in "%s". err.manypages -begin- Dieses Dokument hat entsetzlich viele Seiten! Soll es tatsächlich gedruckt werden? -end- err.nojump -begin- Die Funktion 'Springe-zum-Modul' kann bei der Simulation und bei der Analyse Kritischer Pfade nicht genutzt werden. Stattdessen sollte von Hand zum Zielblock navigiert werden, indem Module selektiert und mit der Taste '>' geöffnet werden. Das Modul kann mit der Taste '<' wieder verlassen werden. -end- err.nomod Modul '%s' nicht definiert. err.modlock Logikblock ist gesperrt! err.closeroot Toplevel Modul kann nicht geschlossen werden. Quit benutzen. err.editonly Kommando im Simulationsmodus nicht möglich. err.simonly Kommando nur im Simulationsmodus möglich. err.deltop Toplevel Modul '%s' kann nicht gelöscht werden. err.delprot Geschütztes Modul '%s' kann nicht gelöscht werden. err.nodel Keine löschbare Auswahl. err.modnotdef Modul '%s' ist nicht definiert. err.moddef Der Block '%s' existiert bereits. err.primredef Built-in element name '%s' can not be redefined. err.noprop Das ausgewählte Gatter hat keine editierbaren Eigenschaften. err.openscript Datei mit Simulationsskript '%s' kann nicht geöffnet werden. err.oldversion Geladene Datei hat veraltete Versionsnummer '%s' (die aktuelle Version ist '%s'). err.futureversion Geladene Datei mit künftiger TkGate-Version '%s' gesichert (die aktuelle Version ist '%s'). err.badversion Unbekannte Versionsnummer. Benutzung auf eigene Gefahr. err.nodrive Netz '%s' hat keinen Treiber in Modul '%s'. err.noconn Leitung %s{%d} ist unverbunden -- gelöscht. err.oldportact Port hinzufügen/ändern durch Rechtsklick auf Port oder Modulkante err.nomodule Kein ausgewähltes Modul. err.nomodop Keine geeigneten Module zum Betrieb verhanden. err.protexec Versuchte Ausführung des geschützten Befehls '%s' in $tkg$exec(). err.notwritable Datei '%s' ist nicht beschreibbar. err.backupfail Erzeugen einer Backupdatei '%s' gescheitert. err.yy.badprop Unbekannte Schaltungseigenschaft '%s' wird ignoriert. err.yy.baddata Falscher Datentyp für Schaltungeigenschaft '%s' gewählt. err.yy.nosym Kein aktuelles Modulsymbol definiert. err.yy.badicon Falscher Icontyp '%s'. err.yy.toomuchdata Zu viele Icon-Daten. err.yy.nosyminst Fehlerhaftes Symbol %d in Instanz %s von %s. err.yy.badmodprop Unbekannte Moduleigenschaft '%s' wird ignoriert. err.yy.badmoddata Fehlerhafter Datentyp für Moduleigenschaft '%s' festgelegt. err.yy.badprim Unbekanntes Schlüsselwort '%s'. err.yy.nonet Undeklariertes Netz '%s'. err.yy.bogussave Gesicherte Schrottdaten entdeckt. Schaltung kann beschädigt sein. err.yy.pinformat Illegales Pin Namensformat '%s'. err.yy.pinname Pinname '%s' ist für Gattertyp '%s' nicht definiert. err.yy.nonetpos Kein Netz für Position %d in Gatter %s. err.yy.baddirective Illegale oder fehlerhafte Direktive '%s'. err.corruptnewsave -fillbegin- TkGate konnte die Datei in '%s' sichern, sie scheint aber korrupt zu sein. Sind Aufsetzpunkte definiert: Lade eine der Checkpoint Dateien. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.corruptsave -fillbegin- TkGate hat ein Problem bei der Sicherung der Datei '%s' entdeckt. Die existierende Datei wurde nicht modifiziert, die beschädigte Datei wurde nach '%s' geschrieben. Ist die Verwendung von Aufsetzpunkten eingeschaltet, kann versuchsweise eine der Checkpoint-Dateien geladen werden. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.badsave -fillbegin- Beim Öffnen oder Schreiben in Datei '%s' gab es ein Problem. Bitte Datei/Verzeichnisrechte und/oder verfügbaren Plattenplatz überprüfen. -end- err.nosafesave -fillbegin- Beim Versuch der Sicherung von Datei '%s' ist ein Problem aufgetreten. Es ist möglich, einen erneuten Versuch ohne Sicherungsvalidierung zu starten. Bei Antwort "nein" bleibt die Originaldatei unverändert. Bei Antwort "ja" wird die Originaldatei überschrieben, wird aber ggf. beim Auftreten eines Fehlers zerstört. Soll eine unvalidierte Sicherung versucht werden? -end- err.noback -fillbegin- Die Datei wurde von TkGate, Version %s, erzeugt und ist nach Sichern mit der aktuellen Version %s möglicherweise von früheren Versionen nicht mehr lesbar. -end- err.viewfile Datei '%s' kann nicht geöffnet werden. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod Interner Fehler: Kann Module '%s' nicht finden. ############################################################################## # Informational messages # msg.selwire Ausgewählt: Die Leitung hat den Namen '%s'. msg.selgate Ausgewählt: %s hat den Namen '%s'. msg.selblock Ausgewählt: %s Block hat den Namen '%s'. msg.iselwire Der ausgewählte Port '%s' ist in Block '%s'. msg.iselgate Das ausgewählte %s, genannt '%s' (huch? Diese Meldung sollte nicht möglich sein). msg.iselblock Ausgewählte Modulschnittstelle ist '%s'. msg.modoverwt Zielmodul '%s' existiert bereits. Ãœberschreiben? msg.foundgate Gatter mit Namen '%s' gefunden. msg.foundwire Leitung mit Namen '%s' gefunden. msg.searchagn Suchstring '%s' nicht gefunden. Mit 'find' Suche erneut starten. msg.sim.chgtoroot Simulationsmodus braucht das root-Modul oben auf dem Editierstack. msg.sim.nogatemod Der Simulationsmodus braucht einen konkreten Modulstack. msg.setinterface Setzen der Modulschnittstelle für '%s'. msg.needsel Bitte eine Modulinstanz auswählen. msg.wroteckpt Kontrollpunkt auf %s gesetzt... msg.save Schaltung als '%s' gesichert. msg.reallynew Die Schaltung wurde verändert. Soll sie wirklich gelöscht und eine neue erzeugt werden? msg.reallyquit Die Schaltung wurde verändert. Soll das Progamm wirklich beendet werden? msg.notlib Modul '%s' ist kein Bibliotheksmodul. ############################################################################## # Heinrich messages (Activated when Heinrich Hacker uses tkgate) # miles.msg1 Nur ein Trottel würde %s%s hierhin plazieren, Heinrich. miles.msg2 Eine richtig doofe Stelle, um %s%s abzulegen, Heinrich. miles.msg3 Ein schrecklich ungeeigneter Platz für %s%s, Heinrich. miles.msg4 Heinrich, Du bist ein Trottel %s%s hierhin zu setzen. miles.msg5 Heinrich, Du allein schaffst es, %s%s hierhin zu plazieren. miles.msg6 %s%s hierhin zu setzen beweist, daß Du ein totaler Trottel bist, Heinrich. miles.msg7 Warum gibst Du nicht auf, Heinrich, das ist eine hirnrissige Schaltung. miles.msg8a Es hat keinen Sinn weiterzumachen, Heinrich. miles.msg8b Heinrich, Du hast keine Ahnung wie man eine Schaltung baut. miles.msg8c Heinrich, mir graut vor Dir. ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Portgrößen-mismatch bei Eingangsport '%s'. verga.err.OUTPORT Portgrößen-mismatch bei Ausgangsport '%s'. verga.err.FLOATNET Netz '%s' hat keinen Treiber (floating net). verga.err.DIRECTCONN Direct connect Operator '=>' wird nicht unterstützt. Wird als '*>' behandelt. verga.err.MEMADDR Versuch, in Speicher %s mit unbekannter Adresse zu schreiben. verga.err.MEMBITS Versuch, in Speicher %s mit unbekanntem Bitbereich zu schreiben. verga.err.BADARRAYUSG Array '%s' wird im Ausdruck ohne Index verwendet. verga.err.BADARRAYLHS Array '%s' wird auf der linken Seite ohne Index verwendet. verga.err.BADCLOSE Versuch, einen nicht geöffneten Deskriptor in Task '%s' zu schließen. verga.err.BADAUTORNG Auto range [*] ist nur gültig in Leitungs-Deklarationen 'wire'. verga.err.BADGATERNG Fehlerhafter Bereichausdruck für eine Gatter-Instanz. verga.err.BADARGVALUE Fehlerhafter Wert für Argument '%s' in Task '%s'. verga.err.DIVZERO Teilung durch Null. verga.err.NODIV Divide/module wird auf dieser Maschine nicht unterstützt - sizeof(short) muß 2 sein. verga.err.BADEDGEEVENT Ereignis im Multi-Bit Netz '%s' kann kein posedge/negedge haben. verga.err.NEEDEDGE Positive oder negative Flanke muß für Event %s spezifiziert werden. verga.err.ASGNEVENT Warten auf ein Event ist bei Zuweisung illegal. verga.err.PROTTASK Ausführung der geschützen System Task '%s' wird blockiert. verga.err.NEEDIDENT Für Argument %s von Task '%s' wird ein Bezeichner erwartet. verga.err.BADOP Operatorfehler-Ausdruck in '%s'. verga.err.NOREAD Laden von Quelldatei '%s' fehlgeschlagen. verga.err.MEMFILE Öffnen von Speicher-Datei '%s' fehlgeschlagen. verga.err.WRONGMOD Modul '%s' wurde gefunden statt '%s'. verga.err.NOTPARM Bezeichner '%s' im konstanten Ausdruck ist kein Parameter. verga.err.BADADDR Illegaler Adressbereich für Port '%s'. verga.err.BADADDRSPEC Illegale Adressbereichsspezifikation '%s'. verga.err.BADCHAR Illegales Zeichen (%s) '%s'. verga.err.BADEVENT Illegaler Ausdruck zur Ereignissteuerung. verga.err.BADCONSTOP Illegaler Operator in konstantem Ausdruck. verga.err.BADXOP Illegaler Operator in Ausdruck. verga.err.NETREDEF Illegale Redefinition des Netzes '%s'. verga.err.BADINOUT Ein/Ausgabe-Verbindungen müssen bei Port '%s' von Netz zu Netz sein. verga.err.MODUNDEF Instanz eines undefinierten Moduls '%s'. verga.err.BADASGNLHS Ãœngültige linke Seite in 'assign'. verga.err.LHSNOTREG Illegale Benutzung von '%s' auf der linken Seite einer Zuweisung. verga.err.BADLHS Ungültige linke Seite in Zuweisung. verga.err.BADOUT Ãœngültige Ausgangs-Zuweisung. verga.err.NOTREG Speicher müssen als Register deklariert werden. verga.err.PORTMIX Vermischte benannte und unbenannte Ports bei Schnittstelle '%s' von '%s'. verga.err.REPCASE Mehr als ein default: in case-Anweisung. verga.err.NOMEM In der gelesenen Speicherdatei gibt es keinen aktuellen Speicher. verga.err.BADCMD Es gibt keinen Befehl '%s'. verga.err.CMDNOTNET Es gibt kein Netz '%s' im '%s' Befehl. verga.err.MEMNONBLK Nicht-blockierende Zuweisungen zu Speicherbereichen sind nicht implementiert. verga.err.NOTPPORT Parameter '%s' ist nicht als Port deklariert. verga.err.REDEFP Parameter redefiniert Bezeichner '%s'. verga.err.PORTNOTDEF Port '%s' in Schnittstelle '%s' ist in Modul '%s' nicht definiert. verga.err.NOCONN Port '%s' hat keine Verbindungen mit Schnittstelle '%s' von '%s'. verga.err.MULTCONN Port '%s' hat Mehrfachverbindungen mit Schnittstelle '%s' von '%s'. verga.err.PORTCOUNT Portanzahl paßt nicht zur Definition der Schnittstelle '%s' von '%s'. verga.err.BADPRTRANGE Der Bereich von Port '%s' isr nicht numerisch. verga.err.BADARRAYRNG Bereichsspezifikation ist für eine Speicherreferenz von '%s' nicht erlaubt. verga.err.CMDMODREDEF Redefinition des dynamischen Moduls '%s'. verga.err.REDEF Redefinition des Beziechners %s. verga.err.PROTTASKSTOP Simulation beendet nach versuchter Ausführung der geschützten System-Task '%s'. verga.err.NOTMEM Das spezifizierte Netz '%s' ist kein Speicher. verga.err.CMDNOTMEM Das spezifizierte Netz '%s' ist kein Speicher in Befehl '%s'. verga.err.SYNTAX Syntaxfehler. verga.err.TOOFEWPP Zu wenig Parameter Ports bei Instanz %s. verga.err.OPENTOOMANY Zu viele geöffnete Dateien in Task '%s'. verga.err.TOOMANYPP Zu viele Parameter Ports bei Instanz %s. verga.err.NOTOP Oberstes Modul '%s' nicht definiert. verga.err.BADOPEN Ausgabedatei '%s' in Task '%s' kann nicht geöffnet werden. verga.err.CMDNOMOD Undefiniertes dynamisches Modul '%s' in Befehl '%s'. verga.err.BADEVENTNET Undefiniertes Netz '%s' in Ereignissteuerungs-Ausdruck. verga.err.NOTASK Undefinierte Task '%s'. verga.err.NOTDEF Undefinierte Variable '%s'. verga.err.BADRANGE Nicht unterstützter Bitbereich [%s] in Netz %s (muss von der Form [n:0] sein). verga.err.GATEUNIMP Unimplementierter primitiver Gatter-Instanz-Typ. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Schreiben auf einen bereits geschlossenen Deskriptor. verga.err.PRIMPTCOUNT Falsche Anzahl von Ports bei der primitiven Gatter-Intsanz '%s'. verga.err.CMDARGS Falsche Zahl von Argumenten im '%s' Befehl. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' mit der falschen Anzahl von Argumenten aufgerufen. verga.err.BADSTART Illegaler Anfangswert in Task '%s'. verga.err.BADSTOP Illegaler Stopwert in $readmemb. verga.err.SPECTASKUSG Task '%s' muss in einem Specify-Block benutzt werden. verga.err.BADSPECTASK Task '%s' kann nicht in einem Specify-Block benutzt werden. verga.err.TIMING Fehler im Zeitablauf bei %s in %s[%s] %s. verga.err.NOIFDEF Kein passendes `ifdef/`ifndef für die %s Deklaration. verga.err.BADSPECLVAL Bitbereiche sind bei Pfadverzögerungs-Spezifikatoren nicht unterstützt. verga.err.PATHDITEM Nicht unterstütztes Konstrukt in Modul mit Pfadverzögerungs-Spezifikation. verga.err.PATHDINOUT Benutzung von 'inout' in Modul mit Pfadverzögerungs-Spezifikation wird nicht unterstützt. verga.err.PATHDLOOP Schleifen in Modulen mit Pfadverzögerungs-Spezifikation werden nicht unterstützt. verga.err.PATHDCOND Setzen von DelaMust durch # Ausdruck und Blockspezifikation. verga.err.TASKREDEF Redefinition eines Task oder einer Funktion '%s' in Modul '%s'. verga.err.TASKASFUNC Task '%s' wird als Funktion benutzt. verga.err.FUNCASTASK Funktion '%s' wird als Task benutzt. verga.err.TASKBADTYPE Nicht-Register-Typ in Task oder Funktion benutzt. verga.err.TASKBADPORT In Funktionen sind nur Eingabeports erlaubt. verga.err.TIMESCALEU Ungültige Einheit '%s' in `timescale Deklaration. verga.err.TIMESCALEN Ungültige Skala '%s' in `timescale Deklaration (muss 1, 10 oder 100 sein). verga.err.TIMESCALES Ungültige Syntax in `timescale Deklaration. verga.err.TIMESCALEX Einheiten müssen größer sein als die Genauigkeit der `timescale Deklaration. verga.err.TIMESCALEAN Der Entwurf enthält Module mit und ohne `timescale verga.err.BADPORTTYPE Ungültige Typdeklaration, benutzt bei '%s' verga.err.BADVALUE Ungültiger Zahlenwert '%s'. verga.err.NONEXPCTL Ereignissteuerung @(*) auf einen Nicht-Ausdruck angewendet. verga.err.NONSTATCTL Eriegnissteuerung @(*) auf eine Nicht-Anweisung angewendet. verga.err.IE_TASK Task Definition '%s' außerhalb von Modul gefunden - interner Fehler. verga.err.IE_NONET Netz '%s' nicht gefunden - interner Fehler. verga.err.IE_NOOP Operatorbeschreibung nicht zu finden - interner Fehler. verga.err.IE_BADEXP Unerwarteter Ausdruckstyp %s - interner Fehler. verga.err.IE_BADVAR Undefinierte Variable oder unbekanntes Netz - interner Fehler. verga.err.IE_BADSTATE Unerwarteter interner Zustand bei %s - interner Fehler. verga.err.IE_RETURN BCReturn bytecode ausgeführt bei leerem Returnstack - interner Fehler. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Alle Items in die selektierte Liste. ho.setsel.alll Alle Items in die nicht selektierte Liste. ho.setsel.ltor Highlight-Items in die selektierte Liste. ho.setsel.rtol Highlight-Items in die nicht selektierte Liste. ho.net.in Single-Bit Eingang ho.net.out Single-Bit Ausgang ho.net.inout Single-Bit Ein/Ausgang ho.net.in2 Multi-Bit Eingang ho.net.out2 Multi-Bit Ausgang ho.net.inout2 Multi-Bit Ein/Ausgang ho.net.wire Single-Bit Leitung (Name sichtbar) ho.net.wire2 Multi-Bit Leitung (Name sichtbar) ho.net.hwire Single-Bit Leitung (Name versteckt) ho.net.hwire2 Multi-Bit Leitung (Name versteckt) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Sichern und Laden von Schaltungsdateien ho.opt.tool.edit Ausschneide-, Einfüge- und Suchoperationen ho.opt.tool.gateopt Gatterdrehungen und Ausrichtungsoperationen ho.opt.tool.gateprop Grundlegendes Editieren von Gattern ho.opt.tool.undo Undo und Redo Operationen ho.opt.tool.zoom Zoom in und Zoom out ho.opt.tool.mode Auswahl des Editierwerkzeugs ho.opt.tool.module Erzeugen, Löschen, Umbenennen etc. von Moduldefinitionen ho.opt.tool.tech Auswahl der Standardtechnologie für Gatter ho.opt.tool.simctl Start, Stop und Pause beim Simulator ho.opt.tool.simaux Weitere Simulatorbefehle (Lesen und Schreiben von Speicherdateien etc.) ho.opt.tool.simmode Im Simulator zwischen dem Auswahl- und dem Scroll-Werkzeug wählen. ho.opt.tool.symmode Auswahl eines Editierwerkzeugs im Symboleditor ho.opt.tool.symedit Ausschneide- und Einfügeoperationen für den Symboleditor ho.opt.tool.symport Port-Drehoperationen für den Symboleditor ho.opt.tool.symshift Verschieben der Bitmap oder von Teilen der Bitmap ho.opt.tool.symopr Verschiedene Symboleditor-Operationen ho.opt.editor.movesel -begin- Ein ausgewählter Textblock kann mit dem Mauszeiger angefaßt und in eine neue Position verschoben werden, wenn die Option angewählt ist. -end- ho.opt.editor.format -begin- Verilog Quellcode wird automatisch eingerückt, wenn die TAB-Taste gedrückt wird. -end- ho.opt.editor.indent -begin- Anzahl der Leerzeichen pro Einrückungsstufe. -end- ho.opt.editor.rtab -begin- Automatisches Einrücken der aktuellen Zeile und Tabulation zur entsprechenden Einrückung wenn RETURN gedrückt wird. -end- ho.opt.editor.beginindent -begin- Führt zur selben Einrückungstiefe eines begin..end-Blocks wie beim Vater-Block. -end- ho.opt.editor.colorize -begin- Einschalten der kontextabhängigen Einfärbung von Quellcode nach den untenstehenden Optionen. -end- ho.hdl.splitexp -begin- Mehrfachmodule im HDL-Text werden in verschiedene Module augespalten, die nach Bedarf neue Module definieren. Alle Namenskonflikte werden durch leichte Veränderung der Modulnamen aufgelöst. -end- ho.hdl.commentexp -begin- Module, die nicht auf den erwarteten Namen passen oder das oberste Modul sind, werden zu HDL-Kommentaren konvertiert. -end- ho.hdl.autoeditexp -begin- Automatisches Editieren der HDL Beschreibung zur Änderung des Modulnamens. -end- ho.hdl.cancelexp -begin- Keine Aktion ausführen und das Editieren des aktuellen Moduls fortsetzen. -end- ho.hdl.ignoreexp -begin- Ignorieren der Inkonsistenz und Fortsetzung der ausgewählten Aktion. -end- ho.new -begin- Aufgeben der aktuellen Schaltung und Editieren einer neuen. -end- ho.open Einlesen einer Schaltung aus einer Datei. ho.save Sichern der Schaltung in die aktuelle Datei. ho.saveas Sichern der Schaltung in eine neue Datei. ho.print Drucken der aktuellen Schaltung. ho.library Laden einer Bibliotheksdatei. ho.symed.tab.normal -begin- Editieren der nicht ausgewählten Symbol-Bitmap -end- ho.symed.tab.select -begin- Editieren der ausgewählten Symbol-Bitmap -end- ho.simmove -begin- Wähle Leitungen und Module aus, bediene die Schalter und gib DIP Werte ein. Klicken und festhalten einer Leitung zeigt ihren aktuellen Wert. -end- ho.move -begin- Bewegen/Verbinden - Klicken und Ziehen - setzt die Position für ein neues Gatter, - bewegt Gatter und Leitungen, - verbindet Leitungen Ein Doppelklick editiert - Gatter-, Leitungs- und Port-Eigenschaften, - Kommentartext. -end- ho.delgat -begin- Gatter entfernen - Werkzeug zum Löschen von Gattern. -end- ho.cutw -begin- Leitung trennen - Werkzeug zum Durchschneiden von Leitungen. -end- ho.scroll -begin- Scrollen - zum Einfangen und Ziehen des Editier-Canvas. -end- ho.inv -begin- Invertieren - Werkzeug zum Hinzufügen oder Löschen von Invertern an Ein- und Ausgängen von Gattern. -end- ho.bitw -begin- Bitbreite - Werkzeug zum Ändern der Breite eines Leitungsbündels. Eingabe der Anzahl der Leitungen in der Eingabebox rechts unten neben dem Logo. -end- ho.ipanel.select -begin- "Standard"-Module werden für normale rechteckige Schnittstellen benutzt, "symbolische" Module für hausgemachte Bitmap-Symbole. -end- ho.ipanel.addport -begin- Einen Port zu einem Modul hinzu- fügen. Doppelklicken nach dem letzten Item bewirkt dasselbe. -end- ho.ipanel.deleteport -begin- Löschen des ausgewählten Ports. -end- ho.ipanel.editport -begin- Editieren des ausgewählten Ports. Ein Feld in einem Port wird mit Doppelklick editiert. -end- ho.ipanel.generate -begin- Erzeugen einer neuen Schnittstelle für ein Modul, basierend auf Ports in der Port-Liste und in der Modul- definition benutzen Portelementen. -end- ho.ipanel.updateall -begin- Ersetze in allen Instanzen dieses Moduls die Schnittstelle durch die hier gezeigte kanonische Schnittstelle. -end- ho.ipanel.prot -begin- Verbiete die Änderung der Definition eines Moduls. -end- ho.ipanel.protint -begin- Verbiete die Änderung der Schnittstelle eines Moduls. -end- ho.ipanel.proted -begin- Verbiete die Änderung der Schnittstelle eines Moduls außer mit Hilfe des Schnittstelleneditors. Das dient der Verhinderung unabsichtlicher Änderungen der Schnittstelle im Haupteditorfenster -end- ho.ipanel.scale -begin- Wird ein Modul in der Größe verändert, so skaliere die Abstände zwischen den Ports mit. -end- ho.ipanel.fix -begin- Wird ein Modul in der Größe verändert, so behalte trotzdem die Abstände zwischen den Ports bei. -end- ho.mod.open Ausgewähltes Modul öffnen. ho.mod.close Aktuelles Modul schließen. ho.mod.new Einen neuen Modultyp erzeugen. ho.mod.del Modul löschen. ho.mod.copy Modul kopieren. ho.mod.rename Modul umbenennen. ho.mod.claim -begin- Konvertieren eines Bibliotheksmoduls in ein reguläres Modul. -end- ho.mod.setroot -begin- Auszeichnen eines Moduls als oberstes (Wurzel-)Modul. -end- ho.mod.type.allparts Bibliothekssammlung ho.mod.type.partlib Bibliothek ho.mod.type.part Bibliotheksmodul ho.mod.type.unknown Unbekannter Modultyp ho.mod.type.unused Sammlung unbenutzer Module ho.mod.type.conflict Modulrekursion ho.mod.type.root Oberstes (Toplevel-) Modul ho.mod.type.netlist Netzlisten Modul ho.mod.type.Lnetlist Netzlisten Modul (locked) ho.mod.type.hdl HDL Modul ho.mod.type.Lhdl HDL Modul (locked) ho.undo Undo früherer Aktion(en) ho.redo Redo von Undo-Aktion(en) ho.tab.edit -begin- Primärer Editiermodus. -end- ho.tab.interface -begin- Editieren der Modulschnittstellen. Ein Doppelklick im Schnittstellenmodus auf ein Modul der Modulliste führt zum Editieren seiner Schnittstelle. Im obersten Modul werden alle Schnittstellen anzeigt. -end- ho.tab.simulate -begin- Start des Simulators, Öffnen des Logikanalysators und Ausführen aller festgelegten Initialisierungsskripte. -end- ho.tab.cpath -begin- Suche die kritischen Pfade einer Schaltung. -end- ho.log -begin- Log von TkGate Meldungen: Fehlermeldungen, informelle Meldungen und Simulator-Konsolenausgabe. -end- ho.simgo -begin- Ist eine Simulation aktiv: kontinuierlich laufen lassen. Ist keine Simulation aktiv: Starten der Simulation und Ausführen aller Initialisierungsskripte. -end- ho.simpause -begin- Pause bei einer kontinuierlich laufenden Simulation. -end- ho.simstep -begin- Start des Ablaufs eines festen Zeitintervalls im Einzelschrittmodus. Im Fenster Simulation->Optionen kann die Schrittweite gesetzt werden. -end- ho.simclock -begin- Ablauf einer festen Anzahl von Taktzyklen. Dazu im Fenster Simulation->Optionen die Schrittweite setzen. -end- ho.simstop -begin- Beenden der aktuellen Simulation, Rückkehr in den Editiermodus. -end- ho.simbreak -begin- Editieren der aktuellen Breakpoints. Die Simulation hält, wenn eine Breakpoint-Bedingung wahr wird. -end- ho.simexec -begin- Verwalten der Sammlung aktiver Skripte. -end- ho.simoptions -begin- Setzen verschiedener Optionen, die die Simulation steuern. -end- ho.simload -begin- Laden des Speichers mit dem Inhalt einer .mem-Datei. -end- ho.simdump -begin- Speicherinhalt in eine .mem-Datei schreiben. -end- ho.modlist -begin- Listen aller aktuell geladener Moduln in alphabetischer Ordnung. Ziehe die Moduln ins Editierfenster, um neue Instanzen zu erzeugen. -end- ho.modtree -begin- List of all modules currently in a hierarchical list. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- Liste der Netze im aktuellen Modul. Das Symbol links vom Namen zeigt an, ob das Netz einbittig (grün) oder mehrbittig (rot) ist. Ein "A" im Symbol zeigt, ob der Netzname als sichtbar markiert ist. -end- ho.ports -begin- Liste der Ports des aktuellen Moduls. Das Symbol vor dem Port zeigt seine Richtung an. -end- ho.status.logo -begin- Anzeige des Simulations-Status. Wird das Eisentor-Logo angezeigt, ist TkGate im Editiermodus. Wird das vierbeinige UND- Gatter gezeigt, ist TkGate im Simulations- modus. Steht dieses UND-Gatter, so ist die Simulation angehalten; läuft es, so läuft auch die Simulation. -end- ho.status.msg Anzeigefeld für Meldungen von TkGate. ho.status.block Modulstack, der gerade editiert wird. ho.status.file -begin- Aktuelle Datei, die gerade editiert wird. Ein '*' hinter dem Dateinamen zeigt an, daß der Puffer seit der letzten Sicherung verändert worden ist. -end- ho.print.selall Ausdrucken aller zur Zeit von TKGate geladenen Module. ho.print.selcur Ausdruck des aktuellen Moduls aus dem Editierfenster. ho.print.seluse -begin- Drucke alle Moduln, die gerade "in Gebrauch" sind. Das sind solche, die Abkömmlinge des root-Moduls sind. -end- ho.print.fulltrace Drucken des ganzen Signaldiagramms. ho.print.parttrace -begin- Drucken eines Teils des Trace. Start- und Stopzeiten werden im Eingabefenster unten eingetragen. Man kann auch mit der rechten Maustaste den Bereich auf dem Scope-Fenster auswählen (mit Shift-Rechts werden große Bereich ausgewählt). -end- ho.print.parttracestart Startzeit der Trace-Ausgabe. ho.print.parttraceend Endezeit der Trace-Ausgabe. ho.print.selsel -begin- Drucke nur die unten angewählten Module. Benutze die Strg-Taste zur Auswahl mehrerer Module. -end- ho.print.modlist Wähle die zu druckenden Module aus. ho.print.timegraph -begin- Hier wird das zum Drucken ausgewählte Gebiet gezeigt. Der grüne Bereich ist der Gesamtbereich der verfügbaren Signaldaten, grau wird die zu druckende Fläche angezeigt. Verwende die Selektoren auf der Linken um ein Gebiet auszuwählen oder wähle das Gebiet im Scopefenster aus, bevor diese Dialogbox geöffnet wird. -end- ho.circuit.discchg -begin- TkGate zeigt keine Warnung an, wenn Änderungen ohne Sicherung verworfen werden. -end- ho.circuit.extbar -begin- Grundgatter (AND, OR, XOR) benutzen für Mehrfacheingänge Erweiterungsleisten. -end- ho.circuit.autostart -begin- Die Simulation beginnt, sobald das Simulationsfenster angewählt ist, wenn diese Option eingeschaltet ist. -end- ho.cmd.bitw -begin- Vorgegebene Bitbreite für mit dem Bitbreite-Werkzeug selektierte Leitungen. -end- ho.edgat.signam -begin- Der Name des ausgewählten Signals am ausgewählten Gatter. Der Name des Signals kann hier durch Editieren geändert werden. -end- ho.edgat.port -begin- Der Name des Ports für dieses Signal am Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.iolab -begin- Die Richtung des ausgewählten Signals am ausgewählten Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.bitlab -begin- Die Bitbreite des ausgewählten Signals des ausgewählten Gatters. Die Bitbreite kann hier durch Editieren geändert werden. -end- ho.edgat.cycle Die Gesamtzahl der Epochen in einem Taktzyklus. ho.edgat.phase Der Startpunkt des Zyklus (in Prozent). ho.edgat.duty Der Prozentsatz des Zyklus, in dem der Takt 'low' ist. ho.edgat.hide -begin- Setze dieses Flag, um die Anzeige des Gatternamens zu verhindern. -end- ho.edgat.gtype Typ des Gatters. ho.edgat.gname Name dieser Gatterinstanz. ho.edgat.ganchor Setze dieses Flag, um die Position des Gatters zu verankern. ho.edgat.gx X Koordinate des Gatters. ho.edgat.gy Y Koordinate des Gatters. ho.edgat.swstate -begin- Der zu benutzende Anfangszustand des Schalters beim Start der Simulation. -end- ho.edgat.dipstate -begin- Der zu benutzende Anfangszustand des DIP-Schalters beim Start der Simulation. -end- ho.edgat.range Der Bitbereich, der aus einem Bus herausgeführt wird. ho.edgat.memfile -begin- Die Datei mit dem Anfangszustand für diesen Speicher. Die Datei wird gelesen, wenn der Simulator gestartet wird. -end- ho.edgat.func Der Funktionstyp dieses Moduls. ho.edgat.frame Die Markierung des Rahmens. ho.traceprint -begin- Drucke den Bereich des Logik-Signaldiagramms, der mit der rechten Maustaste ausgewählt ist. Shift-Rechts-Klick kann benutzt werden, um das augewählte Gebiet zu vergrößern. Der in der Scope-Ansicht sichtbare Bereich wird genutzt, falls keine Auswahl erfolgt ist. -end- ho.showxhair -begin- Wird dieser Knopf gedrückt, erscheint eine senkrechte Maßlinie im Scope-Fenster. -end- ho.opt.general.fontset -begin- Legt die Fontgröße des Basisfonts in der TkGate- Benutzerschnittstelle fest. Diese Option wird erst aktiv, wenn TkGate neu gestartet ist. -end- ho.opt.sec.send -begin- Aktivieren der $tkg$command() System Task erlaubt es Anwendungsschaltungen, dem TkGate GUI beliebige Simulator-Steuerkommandos zu senden. Dazu gehört auch die Fähigkeit zum Ausführen beliebiger Shellbefehle. Wird der Simulator zum Ausführen von Schaltungen unklarer Herkunft benutzt, sollte diese Task lieber ausgeschaltet bleiben. Aktivierung führt zu einem hohen Sicherheitsrisiko! -end- ho.opt.sec.open -begin- Aktivieren der $fopen() System Task erlaubt Anwendungsschaltungen in beliebige Dateien des Benutzers zu öffnen. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.writemem -begin- Aktivieren der $writememb() und $writememh() System Tasks erlaubt es Anwendungsschaltungen in beliebige Dateien des Benutzers zu schreiben. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.enqueue -begin- Aktivieren der $tkg$recv() und $tkg$send() System Tasks erlaubt virtuellen peripheren Geräten Botschaften an TkGate Schaltungen zu senden. Das ist ein relativ geringes Sicherheitsrisiko. -end- ho.opt.ssave -begin- Führe Konsistenzüberprüfungen von Schaltungsdateien durch, bevor eine existierende Sicherungsdatei überschrieben wird. Damit wird überprüft, ob es keine Probleme mit der Sicherungsdatei gibt. -end- ho.opt.sec.exec -begin- Die volle Aktivierung der $tkg$exec() System Task erlaubt es dem Benutzer, beliebige tcl/tk-Befehle einschließlich der Ausführung beliebiger Shellbefehle abzusetzen. Die Aktivierung dieser Option stellt also ein sehr hohes Sicherheitsrisiko dar. -end- ho.opt.sec.regexec -begin- Die Aktivierung der $tkg$exec() System Task für registrierte Funktionen erlaubt es Anwendungsschaltungen, nur tcl/tk Kommandos auszuführen, die als sicher registriert sind. Solange alle virtuellen peripheren Geräte vertrauenswürdig sind, hält die Aktivierung von $tkg$exec() auf dieser Stufe gefährliche Befehle von der Ausführung ab. Das Einschalten dieser Option hat ein mittleres Sicherheitsrisiko zur Folge. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- Ist diese Einstellung aktiviert, wird die Simulation beendet, sobald von der Anwendungsschaltung versucht wird, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.warn -begin- Ist diese Einstellung aktiviert, wird die Simulation nach einer Warnmeldung weitergehen, wenn die Anwendungsschaltung versucht, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.ignore -begin- Ist diese Einstellung aktiv, wird die Benutzung aller ausgeschalteten Features ignoriert; es werden keine Fehlermeldungen angezeigt. -end- ho.opt.html.browser -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zu einer HTML-Datei klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.html.email -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zum Senden einer e-mail klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.fsave -begin- Sichere die TkGate-internen Zellen mit den Schaltungsdaten. Dies erhöht die Dateigröße um ca. 20%, führt aber zu Sicherungsdateien, die zur Verwendung mit Drittanbietertools exportiert werden können. -end- ho.opt.sorttraces -begin- Ist diese Option eingeschaltet, werden die Signale im Scope-Fenster in sortierter Form angezeigt. Ist sie ausgeschaltet, werden die Signale im Scopefenster in der Reihenfolge der Probe-Setzungen angezeigt. -end- ho.opt.sim.noglitch -begin- Ist diese Option aktiv, so bewirken sich schnell verändernde Signale am Eingang eines Gatters am Ausgang desselben im wesentlichen das zeitverschobene Eingangssignal. Dies kann flüchtige Ereignisse und Schwingungen in sequentiellen Schaltungen auf Gatterebene verhindern helfen. -end- ho.opt.sim.savetraces -begin- Tastköpfe, die während eines Simulationslaufes plaziert wurden, werden abgespeichert und beim Neustart der Simulation wieder richtig gesetzt. -end- ho.opt.sim.tech -begin- Dateienliste zum Laden als potentielle "Technologie"-Dateien. Technologie-Dateien legen Verzögerungen und Flächengrößen für eingebaute Gatter fest. -end- ho.opt.sim.err -begin- Wähle, wie Warnungen vom Simulator behandelt werden sollen. -end- ho.opt.sim.err.stopany -begin- Gibt es irgendwelche Warnungen zu der Schaltung, wird sie nicht simuliert, auch nicht, falls es gar keine wirklichen Fehler gibt. -end- ho.opt.sim.err.showall -begin- Ziege immer Warnunge zu der Schaltung, auch wenn es keine Fehler gibt. Falls nur Warnungen existieren, wird der Simulator gestartet und die Warnungen in einem gesonderten Fenster angezeigt. -end- ho.opt.sim.err.showiferr -begin- Zeige Warnungen nur, wenn es auch Fehler in der Schaltung gibt. Enthält eine Schaltung nur Warnungen, so werden sie ignoriert und der Simulator wird geräuschlos gestartet. -end- ho.opt.sim.err.ignore -begin- Zeige nie Warnmeldungen, auch nicht, falls es Fehler in der Schaltung gibt. -end- ho.opt.lib.vpath -begin- Liste von Verzeichnissen, in denen nach TkGate Bibliotheksdateien gesucht wird. Bibliotheken sollten eine .v Dateierweiterung besitzen und Module enthalten, die für den Gebrauch in Anwendungsschaltungen nützlich sind. -end- ho.opt.lib.vlib -begin- Die Bibliotheksliste, die automatisch geladen wird, wenn TkGate startet. -end- ho.opt.lib.vpd -begin- Liste von Verzeichnissen, in denen nach virtuellen peripheren Geräten (VPDs) gesucht wird. Virtuelle periphere Geräte haben eine .tcl Dateierweiterung und implementieren typischerweise ein GUI, das das periphere Gerät repräsentiert und das von einer benutzerschaltung gesteuert wird. -end- ho.opt.undolen -begin- Maximale Zahl der aufzuhebenden Undo-Aktionen. -end- ho.opt.name -begin- Benutzername, der auf allen von TkGate produzierten Reports, z.B. Schaltungs- ausdrucken, aufgeführt wird. -end- ho.opt.site -begin- Der Netzname der Organisation, in der TKGate installiert ist. Dieser Name wird auf jedem Ausdruck (oder in der Postscript-Datei) ausgegeben. -end- ho.opt.smooth -begin- Falls diese Option eingestellt ist, wird Scrollen mittels Bitmap-Kopien realisiert statt das Bild immer neu zu zeichnen. Dies kann ausgeschaltet werden, falls Probleme mit dem X-Server auftreten. -end- ho.opt.clip -begin- Ist diese Option eingeschaltet, wird Clipping benutzt, um den dargestellten Teil des Fensters beim Neuaufbau zu zeichnen. Sonst wird das ganze Display für alle Teile neu gezeichnet. -end- ho.opt.showimage -begin- Durch Zurücksetzen dieser Option kann die Anzeige des Bildes un der erläuternde Text am Rand der Dialogboxen unterdrückt werden. -end- ho.opt.outmove -begin- Ist diese Option eingeschaltet, wird nur der Umriß der bewegten Modulinstanzen beim Verschieben angezeigt. Diese Einstellung ist nur auf Maschinen mit langsamen Displays nötig. -end- ho.opt.bhelp -begin- Bei Aktivierung dieser Option werden Hilfehinweise angezeigt. Sie zeigen Tips an, wenn die Maus sich gerade über einem Baustein befindet. -end- ho.opt.novice -begin- Falls auf der Kommandozeile keine andere Schaltung angegeben ist, wird ein TkGate- Tutorial als erste Schaltung beim Start angezeigt. -end- ho.opt.blockDropConnect -begin- Dies Option erlaubt die Erzeugung von Ports bei Modulschnittstellen, indem freie Leitungen neben einer Kante fallengelassen werden. -end- ho.opt.debug -begin- Einschalten mehrerer Debugging Features. Nur interessant für TKGate-Entwickler. -end- ho.opt.ckpt Einschalten des Checkpointing nicht gespeicherter Schaltungen. ho.opt.ckptfreq Anzahl der Checkpoints pro Sekunde. ho.opt.beak -begin- Freischalten dieser total nutzlosen Features. Falls dies ausgeschaltet wird, erscheinen diese Modi (und diese Checkbox) nicht mehr im Optionsfenster. Der einzige Weg, sie wiederzubekommen, geht über das Editieren der .tkgate-properties Datei. -end- ho.opt.miles -begin- Ist dieser Modus eingeschaltet, wird TkGate periodisch die Intelligenz des Benutzers anzweifeln. -end- ho.opt.bat -begin- Falls dieser Modus eingeschaltet ist, wird TkGate eine Entwicklungsumgebung für einen Bat-Computer einrichten. -end- ho.opt.trek Beam me up Scotty! ho.opt.simstep -begin- Die Anzahl der Epochen, die bei einem Schritt-Kommando vorangeschritten wird. -end- ho.opt.ckstep -begin- Die Anzahl der Taktzyklen, die vorangeschritten wird, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.ckover -begin- Die Anzahl der Epochen nach der Anstiegsflanke des Taktes, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.vpopupdelay -begin- Die Verzögerung in Millisekunden zwischen Drücken und Halten der Maustaste und der Anzeige eines Signalwerts. Auf einigen Systemen interferieren kurze Verzögerungs- zeiten mit der Fähigkeit, einen Doppelklick zu erkennen. Liegt dieser Fall vor, so ist der Wert zu erhöhen. Es sind Werte zwischen 1 und 10000 erlaubt. -end- ho.opt.init -begin- Eine Simulationsskript-Datei, die automatisch ausgeführt wird, wenn die Simulation gestartet wird. -end- ho.opt.ckall -begin- Falls diese Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation bei der positiven Flanke jeder Taktquelle in der Schaltung an. -end- ho.opt.ckspec -begin- Falls dieser Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation nur an der positiven Flanke der spezifizierten Taktquelle an. -end- ho.opt.keybind -begin- Legt den Stil für Tastenbindungen fest. Wird diese Option geändert, werden die Bindungen sofort aufge- frischt. Allerdings muß TkGate neu gestartet werden, damit irgendwelche benutzerdefinierten Tastaturbindungen zu sehen sind. -end- ho.deftech -begin- Standard-Technologie für neue Gatter. Beeinflußt die Verzögerungszeit der Gatter. Um die Technologie eines bestimmten Gatters zu ändern, öffnet mann die Eigenschafts-Box mit Doppelklick und wählt "Delay" an. -end- ho.techbut -begin- Benutze Verzögerungszeiten aus der Datei zur Definition der Standard Technologie. Um eigene Technologien zu entwickeln, füge man sie zu der Liste im "Datei -> Optionen -> Simulation"-Menu hinzu. -end- ho.custbut -begin- Setze eigene Verzögerungszeitwerte für dieses Gatter. -end- ho.contver -begin- Verifiziere die Integrität der internen Datenstrukturen nach jeder Operation. -end- ho.simwatch -begin- Zeige Kommandos an, die zwischen GUI und Simulator gesendet werden. -end- ho.symed.point -begin- Pixel-Editiermodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.line -begin- Geraden-Modus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.rect -begin- Rechteckmodus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.fillrect -begin- Ausgefüllter Rechteckmodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.select -begin- Bitmap Auswahlmodus. Die linke Maustaste wählt Bereiche der Bitmap aus. Auf der Auswahl können dann Cut und Paste Operationen vorgenommen werden. -end- ho.symed.port -begin- Portauswahlmodus. Wähle Ports aus, bewege sie oder rotiere sie. -end- ho.symed.rshift Ausgewählte Pixel rechtsverschieben. ho.symed.lshift Ausgewählte Pixel linksverschieben. ho.symed.ushift Ausgewählte Pixel nach oben verschieben. ho.symed.dshift Ausgewählte Pixel nach unten verschieben. ho.symed.cwrotate Ausgewählte Pixel rechts drehen. ho.symed.ccwrotate Ausgewählte Pixel links drehen. ho.symed.autobold Das ausgewählte Bild fett machen. ho.symed.resize Den Bildeditor in der Größe ändern. ho.symed.import Bild aus einer Datei importieren. ho.symed.export Bild in eine Datei exportieren. ho.tool.currot -begin- Zeigt aktuelle Vorgabe des Rotationswinkels an. Ändern durch Klick auf diese Taste. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotieren der ausgewählten Gatter gegen den Uhrzeigersinn. ho.tool.brotate Rotieren der ausgewählten Gatter mit dem Uhrzeigersinn. ho.tool.valgn Ausgewählte Gatter vertikal ausrichten. ho.tool.halgn Ausgewählte Gatter horizontal ausrichten. ho.tool.cut Ausschneiden des ausgewählten Teils. ho.tool.copy Kopieren des ausgewählten Teils.. ho.tool.paste Einfügen aus dem Cut-Puffer. ho.tool.find Gatter, Leitungen oder Text suchen (und finden). ho.tool.addport Zum ausgewählten Gatter einen Port hinzufügen. ho.tool.anchor Die ausgewählten Gatter verankern. ho.tool.unanchor Die ausgewählten Gatter loslassen. ho.tool.replicate Replizierung eines Gatters. ho.tool.delete Löschen der Auswahl. tkgate-2.0-b10/locale/de/messages.bak000644 001751 001751 00000261505 11134010127 020122 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by bartke So 11. Jan 17:29:58 CET 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## \font-encoding iso8859-1 \messages-encoding utf-8 \verilog-encoding iso8859-1 \display-encoding iso8859-1 \postscript-encoding iso8859-1 \language German ############################################################################## # # basic strings # b.new Neu... b.dismiss Beenden b.close Schließen b.ok OK b.clear Clear b.cancel Abbrechen #b.open Öffnen... #b.bitw Bitbreite b.in Eingang b.out Ausgang b.inout Bidirektional b.browse Durchsuchen... b.label Marke b.find Suchen b.edit Editieren... b.add Hinzufügen... b.delete Löschen #b.deleteb Löschen... b.remove Entfernen b.apply Anwenden b.anchor Anker b.tech Technologie #b.enable Freischalten #b.disable Sperren #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editieren tab.editintr Schnittstelle tab.simulate Simulieren tab.cpath Kritischer Pfad ############################################################################ # # Module tabs # module.tree Tree module.list List ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Hinzufügen... mm.delete Löschen mm.edit Editieren... mm.enable Freischalten mm.disable Sperren ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:Datei menu.edit 0:Editieren menu.tool 0:Werkzeug menu.symbol 0:Symbol menu.simulate 0:Simulieren menu.module 4:Modul menu.interface 0:Schnittstelle menu.format 0:Gatter menu.make 0:Bausteine menu.help 0:Hilfe menu.file.new 0:Neu... menu.file.open 1:Öffnen... menu.file.openlib 3:Bibliotheksmanager... menu.file.save 0:Sichern menu.file.saveas 8:Sichern unter... menu.file.print 0:Drucken... menu.file.options 0:Optionen... menu.file.quit 0:Quit menu.file.cprop 10:Schaltungseigenschaften... menu.file.import 0:Bild Import... menu.file.export 0:Bild Export... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Ausschneiden menu.edit.copy 0:Kopieren menu.edit.paste 0:Einfügen menu.edit.overlay 1:Overlay einfügen menu.edit.selall 1:Alles auswählen menu.edit.find 0:Suchen... menu.edit.algnv 11:Ausrichten Ver. menu.edit.algnh 11:Ausrichten Hor. menu.format.rot.rotate 2:Drehen menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 16:Bitverschiebung Rechts menu.edit.lshift 16:Bitverschiebung Links menu.edit.ushift 16:Bitverschiebung Auf menu.edit.dshift 17:Bitverschiebung Ab menu.edit.cwrotate 11:Bitrotieren rechts menu.edit.ccwrotate 15:Bitrotieren links menu.edit.pcwrotate 12:Portrotieren rechts menu.edit.pccwrotate 16:Portrotieren links menu.edit.autobold Bits fett anzeigen menu.edit.resize Bitmapgröße anpassen menu.tool.move 0:Bewegen/Verbinden menu.tool.delg 0:Gatter löschen menu.tool.cutw 0:Leitung trennen menu.tool.inv 0:Invertieren menu.tool.bitw 0:Bitbreite menu.tool.debug 0:Debug menu.tool.point 0:Punkt menu.tool.line 0:Gerade menu.tool.rect 0:Rechteck menu.tool.fillrect 0:Rechteck füllen menu.tool.port 0:Port menu.tool.select 0:Gebiet auswählen menu.format.rot.0 4:Rot 0 menu.format.rot.90 4:Rot 90 menu.format.rot.180 4:Rot 180 menu.format.rot.270 4:Rot 270 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin 0:Beginn Simulation menu.simulate.end 0:Ende Simulation menu.simulate.addprobe 0:Tastkopf hinzufügen/löschen menu.simulate.run 0:Laufen lassen menu.simulate.pause 0:Pause menu.simulate.step 0:Epochenschritt(e) menu.simulate.cycle 5:Periodenschritt(e) menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Skript ausführen... menu.simulate.load 16:Speicherbereich laden... menu.simulate.dump 16:Speicherbereich ausgeben... menu.module.open 0:Öffnen menu.module.close 0:Schließen menu.module.new 0:Neu... menu.module.del 0:Löschen... menu.module.copy 0:Kopieren... menu.module.rename 0:Umbenennen... menu.module.claim 1:Aneignen... menu.module.setroot 1:Zur Wurzel machen... menu.module.prop 0:Eigenschaften... menu.module.interface 0:Schnittstelle menu.module.interface.set 0:Definieren menu.module.interface.update 1:Sync. to Default menu.module.interface.updateall 6:Sync. All to Default... menu.module.interface.edit 0:Editieren... menu.module.interface.auto 5:Automatisch erzeugen... menu.format.addport 0:Port hinzufügen menu.format.ioset 0:IO-Typ definieren menu.format.anchor 0:Verankern menu.format.unanchor 0:Freigeben menu.format.prop 0:Eigenschaften dieser Instanz... menu.tool.rep 0:Vervielfachen menu.format.del 0:Löschen menu.format.settech 0:Technologie festlegen menu.help.about 0:Autor... menu.help.license 0:Lizenz... menu.help.doc 0:Dokumentation... menu.help.tut 1:Tutorien menu.help.home 1:Startseite menu.help.example 1:Beispiele ############################################################################# # Scope Menu # menu.scope_file 0:Datei menu.scope_sim 0:Simulieren menu.scope_trace 0:Signaldiagramm menu.scope_help 0:Hilfe menu.scope_file.ptrace 0:Drucken Signaldiagramm... menu.scope_file.close 0:Schließen menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Tastkopf hinzufügen/löschen menu.scope_sim.run 0:Laufen lassen menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Epochenschritt(e) menu.scope_sim.cycle 5:Periodenschritt(e) menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Skript ausführen... menu.scope_sim.load 16:Speicherbereich laden... menu.scope_sim.dump 16:Speicherbereich ausgeben... menu.scope_help.about 0:Autor... menu.scope_help.license 0:Lizenz... menu.scope_help.doc 0:Dokumentation... mod.intf Schnittstelle port.title TkGate: Porteigenschaften port.parms Portparameter port.in Eingang port.out Ausgang port.inout Ein/Ausgang ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gatter gm.rgate Reduktion gm.msi MSI gm.alu ALU gm.mem Speicher gm.mod Module gm.comment Kommentar gm.frame Rahmen gm.io.switch Schalter gm.io.dip DIP Schalter gm.io.ground Masse gm.io.vdd Vdd gm.io.merge Zusammenführen gm.io.clock Taktgeber gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direkt) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Puffer gm.gate.inv Inverter gm.gate.tribuf Tri-Puffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Addierer gm.alu.mult Multiplizierer gm.alu.div Dividierer gm.alu.lshift Linksshift gm.alu.rshift Rechtsshift gm.alu.arshift Arith. Rechtsshift gm.alu.roll Zyklischer Shift gm.mem.reg Register gm.mem.ff Flip-Flop gm.mem.rff Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexer gm.msi.41mux 4-1 Multiplexer gm.msi.81mux 8-1 Multiplexer gm.msi.12dec 1-2 Dekoder gm.msi.14dec 1-4 Dekoder gm.msi.18dec 1-8 Dekoder gm.mod.inst Module Instanz gm.mod.in Module Eingang gm.mod.out Module Ausgang gm.mod.inout Module Ein/Ausgang tutorial.prev ZURÃœCK tutorial.next WEITER tutorial.chapter INHALTSVERZEICHNIS tutorial.reload NEU LADEN ############################################################################## # # Popup menus # pop.make Bausteine pop.tool Werkzeug pop.edit.paste Einfügen pop.edit.cut Ausschneiden pop.edit.copy Kopieren pop.port.in Eingang pop.port.out Ausgang pop.port.inout Ein/Ausgang pop.wire.addseg Leitungssegment hinzufügen pop.wire.prop Schaltungseigenschaften... pop.wire.hidesize Bitbreite verstecken pop.wire.showsize Bitbreite anzeigen pop.wire.hidelabel Namen verstecken pop.wire.hidealllabel Alle Namen verstecken pop.wire.clearalllabel Alle Namen löschen pop.wire.showlabel Namen anzeigen pop.gate.open Öffnen pop.gate.close Schließen pop.gate.prop Instanzeigenschaften... pop.gate.addport Port hinzufügen pop.gate.addin Eingang hinzufügen... pop.gate.addout Ausgang hinzufügen... pop.gate.addinout Ein/Ausgang hinzufügen... pop.gate.anchor Verankern/Loslösen pop.gate.settech Technologie festlegen pop.gate.delete Löschen pop.gate.ioset Typ festlegen pop.module.new Neu... pop.module.del Löschen... pop.module.copy Kopieren... pop.module.rename Umbenennen... pop.module.claim Aneignen... pop.module.setroot Als Wurzel festlegen... pop.module.prop Moduleigenschaften... pop.module.int Schnittstelle editieren... pop.simulate.end Ende Simulation pop.simulate.begin BeginN Simulation pop.simulate.addprobe Tastkopf hinzufügen pop.simulate.delprobe Tastkopf löschen pop.simulate.run Laufen lassen pop.simulate.pause Pause pop.simulate.step Epochenschritt(e) pop.simulate.cycle Periodenschritt(e) pop.simulate.break Breakpoint... pop.simulate.script Skript ausführen... pop.simulate.load Speicherbereich laden... pop.simulate.dump Speicherbereich ausgeben... pop.interface Schnittstelle pop.interface.set Als Standard setzen pop.interface.update Abgleichen mit Standard pop.interface.updateall Alles abgleichen mit Standard... pop.interface.edit Editieren... pop.interface.auto Automatisch erzeugen... pop.interface.replace Ersetzen pop.igen.type Typ pop.igen.side Seite pop.igen.size Größe pop.igen.delete Löschen pop.igen.in Eingang pop.igen.out Ausgang pop.igen.inout Ein/Ausgang pop.igen.left links pop.igen.right rechts pop.igen.top oben pop.igen.bottom unten pop.igen.other sonstige ############################################################################## # # Symbol editor strings # #symed.bsave Speichern #symed.file Datei #symed.file.load Bitmap laden... #symed.file.save Bitmap sichern... #symed.file.updateclose Auffrischen und schließen #symed.file.discardclose Verwerfen und schließen #symed.help Hilfe #symed.help.about Zu... #symed.edit Editieren #symed.edit.cut Ausschneiden #symed.edit.copy Kopieren #symed.edit.paste Einfügen #symed.edit.overlay Overlay einfügen #symed.edit.rclock Rechts drehen #symed.edit.rcclock Links drehen #symed.module Modul #symed.modes Modes #symed.cutpaste Ausschneiden/Einfügen #symed.rotate Port drehen #symed.zoom Zoom #symed.cancel Abbrechen #symed.update Auffrischen symed.tab.normal Nicht ausgewählt symed.tab.select Ausgewählt symed.link Ausgewähltes mit Unausgewähltem verlinken # width of symbol editor tabs ############################################################################## scope.emptymsg Doppelklick auf eine Leitung fügt ein Signal ein oder löscht es comment.empty [Text hinzufügen mit Doppelklick.] ############################################################################## # Interface strings # ifile Datei imodule Modul iblmodule Module iports Ports ibits Bits: itype Typ: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file Dateiname db.mod.type Typ db.mod.flags Flags db.mod.dataprot Editieren der Moduldefinition verhindern. db.mod.intfprot Schnittstellenveränderungen verhindern. db.mod.edprot Schnittstellenveränderungen im Editiermodus verhindern. db.mod.props Eigenschaften db.mod.inuse.0 Modul wird nicht benutzt. db.mod.inuse.1 Modul wird benutzt. db.mod.lmod.0 Modul seit dem Laden nicht verändert. db.mod.lmod.1 Modul seit dem Laden verändert. db.mod.smod.0 Modul seit dem Sichern nicht verändert. db.mod.smod.1 Modul seit dem Sichern verändert. db.mod.islib.1 Modul ist Teil der [%s] Bibliothek. db.mod.islib.0 Modul ist kein Bibliotheksmodul. db.mod.netlist Bauteilliste db.mod.hdl HDL db.mod.netexpl -begin- Moduldefinition mit einem graphischen Editor, um Leitungen zwischen Komponenten zu ziehen -end- db.mod.hdlexpl -begin- Moduldefinition mit einem Texteditor, um das Verhalten in Verilog zu beschreiben. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Fehlerliste db.err.caption Fehlerliste db.err.explain -fillbegin- Wegen Schaltungsfehler(n) kann der Simulationsmodus nicht aufgerufen werden. Die fehlerhafte Stelle ist nach Anwahl der entspr. Fehlermeldung zu sehen. -end- db.err.neededit -fillbegin- Zum Navigieren zu den Warnungen muß erst in den Edit Modus geschaltet werden. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Netzeigenschaften db.net.caption Netzeigenschaften db.net.name Netzname db.net.hide Name verstecken db.net.bits Bitbreite db.net.type Netztyp db.net.port Porttyp db.net.in Eingang db.net.out Ausgang db.net.inout Ein/Ausgang db.net.inets Netze ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: Neue Schaltung db.newcirc.directory Verzeichnis: db.newcirc.cap Neue Schaltung db.newcirc.exp -fillbegin- Die aktuelle Schaltung verwerfen und eine neue Schaltung bearbeiten. -end- db.newcirc.file Dateiname db.newcirc.topname Name des obersten Moduls ############################################################################## # Gate dialog box # db.gate.title TKGate: Gattereigenschaften db.gate.signam Signalname db.gate.portnam Portname db.gate.iotype Typ db.gate.bitw Bitbreite db.gate.cyclew Taktlänge db.gate.phase Phase db.gate.duty Taktverhältnis db.gate.port Port db.gate.bitws Bits db.gate.side Seite db.gate.gtype Gattertyp db.gate.gname Gattername db.gate.hidenam Namen verstecken db.gate.anchor Verankern db.gate.cpbreak Aufteilung des kritischen Pfades db.gate.butstate Schalterzustand db.gate.dipval Schalterstellung db.gate.range Bitbereich db.gate.memfilenam Dateiname f. Speicherinhalt db.gate.modname Funktion db.gate.general Allgemein db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Verzögerung db.gate.parameters Parameter db.gate.stddelay Standardverzögerung db.gate.custdelay Einstellen der Verzögerung db.gate.catdiruse Platzieren des Ports db.gate.edit Editieren db.gate.delete Löschen db.gate.add Hinzufügen db.gate.ff.type Flip-Flop Ausrichtung db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- Der Datenfluß im Flip-Flop ist von links nach rechts. -end- db.gate.ff.reverse.hdr Umgekehrt db.gate.ff.reverse.exp -fillbegin- Der Datenfluß im Flip-Flop ist von rechts nach links. -end- db.gate.cat.asc.hdr Aufsteigend db.gate.cat.dec.hdr Absteigend db.gate.cat.asc.exp -fillbegin- Bits werden in aufsteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.dec.exp -fillbegin- Bits werden in absteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.sigdir Signalrichtung db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Mehrfacheingang db.gate.cat.singin.hdr Einzelner Eingang db.gate.cat.tran.hdr Bidirektional db.gate.cat.auto.exp -fillbegin- Die Signalrichtung wird automatisch aus den verbundenen Teilschaltungen erschlossen. -end- db.gate.cat.multin.exp -fillbegin- Die Seite mit Mehrfachleitung wird immer als Eingang angenommen. -end- db.gate.cat.singin.exp -fillbegin- Die Seite mit der Einzelleitung wird immer als Eingang angenommen. -end- db.gate.cat.tran.exp -fillbegin- Bidirektionaler Signalfluß (transmission) ist erlaubt. Kann nicht mit Schaltern oder Registern verbunden werden. -end- # Minimum size of textbox for comment (in characters) # @db.gate.comment.width 80 @db.gate.comment.height 30 db.gate.tab.General.cap Allgemeine Eigenschaften db.gate.tab.Ports.cap Porteigenschaften db.gate.tab.Delay.cap Eigenschaften der Verzögerung db.gate.tab.Parameters.cap Modulparameter db.gate.tab.CLOCK.cap Takteigenschaften db.gate.tab.SWITCH.cap Schaltereigenschaften db.gate.tab.DIP.cap DIP Eigenschaften db.gate.tab.TAP.cap Tran Eigenschaften db.gate.tab.RAM.cap RAM Eigenschaften db.gate.tab.ROM.cap ROM Eigenschaften db.gate.tab.MODULE.cap Moduleigenschaften db.gate.tab.FRAME.cap Rahmeneigenschaften db.gate.tab.LED.cap LED Eigenschaften db.gate.tab.AND.cap AND Eigenschaften db.gate.tab.OR.cap OR Eigenschaften db.gate.tab.XOR.cap XOR Eigenschaften db.gate.tab.MUX.cap Mux Eigenschaften db.gate.tab.DEMUX.cap Demux Eigenschaften db.gate.tab.CONCAT.cap Concat Eigenschaften db.gate.tab.COMMENT.cap Text Eigenschaften db.gate.tab.FF.cap Flip-Flop Eigenschaften db.gate.tab.General.exp -fillbegin- Die grundlegenden Eigenschaften einer Instanz ansehen und verändern. -end- db.gate.tab.Ports.exp -fillbegin- Hinzufügen, Editieren oder Löschen von Ports einer Instanz. -end- db.gate.tab.Delay.exp -fillbegin- Die Verzögerung kann entweder durch Angabe der Technologie oder durch spezielle Werte für diese Instanz festgelegt werden. -end- db.gate.tab.Parameters.exp -fillbegin- Festlegen der Modulparameter dieser Modulinstanz, falls welche definiert sind. Modulparameter werden zur Definition von Verzögerungen und konstanten Werten in Moduln verwendet. -end- db.gate.tab.details.exp -fillbegin- Genaue Festlegung der typspezifischen Eigenschaften eines Gatters. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Definition des Textes in einem Kommentar. Es können in beschränktem Umfang HTML Tags einschließlich Links verwendet werden. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Wert db.gate.mparm.exampleA -begin- Dieses Modul hat keinerlei Parameter. Parameter können zu Verilog-Textmodulen hinzugefügt werden. Dert Wert jedes Parameters kann für jede Instanz durch diese Dialogbox konfiguriert werden. Modul- Parameter werden als geklammerte Liste deklariert, die mit einem # beginnt. Hier ist ein Beispiel einer Moduldeklaration mit einem Parameter namens "base_value", der einen Standardwert von 1'b1 besitzt. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder Eingangsordnung db.gate.mux.ord1.hdr Links-rechts db.gate.mux.ord2.hdr Rechts-links db.gate.mux.ord1.exp -fillbegin- Ordne MUX-Eingänge von links nach rechts. -end- db.gate.mux.ord2.exp -fillbegin- Ordne MUX-Eingänge von rechts nach links. -end- db.gate.demux.dataorder Ausgangsordnung db.gate.demux.ord1.hdr Links-rechts db.gate.demux.ord2.hdr Rechts-links db.gate.demux.ord1.exp -fillbegin- Ordne DEMUX-Ausgänge von links nach rechts. -end- db.gate.demux.ord2.exp -fillbegin- Ordne DEMUX-Ausgänge von rechts nach links. -end- db.gate.mux.select Auswahlstil db.gate.mux.sel1.hdr Selektor links db.gate.mux.sel2.hdr Selektor rechts db.gate.mux.sel1.exp -fillbegin- Setze den Datenselektor auf der linken Seite des Gatters. -end- db.gate.mux.sel2.exp -fillbegin- Setze den Datenselektor auf der rechten Seite des Gatters. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse Nutzung von Erweiterungsbalken db.gate.aox.use.hdr Erweiterungsbalken db.gate.aox.nouse.hdr Keine Erweiterungsbalken db.gate.aox.use.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden diese an Erweiterungsbalken angebracht. -end- db.gate.aox.nouse.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden keine Erweiterungsbalken verwendet. -end- db.gate.led.type LED Typ db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Balkenanzeige db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direkt) db.gate.led.bit.exp -fillbegin- Einzelne LED-Anzeige für 1-Bit-Signale. -end- db.gate.led.bar.exp -fillbegin- LED Balkenanzeige mit einem Balken pro Bit. -end- db.gate.led.hex.exp -fillbegin- Hexadezimale Anzeige des Signals. -end- db.gate.led.dec.exp -fillbegin- Dezimale Anzeige des Signals. -end- db.gate.led.seg.exp -fillbegin- Die Signalbits steuern direkt die LED-Segmente a-g. -end- db.seq.back db.hdl.namechange.title HDL Modulname geändert db.hdl.textdisp.title HDL Textdisposition db.hdl.savecap Mehrfach-Module db.hdl.saveexp -fillbegin- Der Textpuffer des gerade editierten Moduls enthält mehr als eine Moduldefinition. Bitte wähle eine der drei Aktionen auf der rechten Seite aus. -end- db.hdl.autoedit Auto-Editieren db.hdl.split Aufteilen db.hdl.comment Kommentar db.hdl.cancel Abbrechen db.hdl.ignore Ignorieren db.hdl.autoeditcap Der Name paßt nicht db.hdl.autoeditexp -fillbegin- Die Textbeschreibung des Moduls paßt nicht zum erwarteten Namen. Wähle eine der Optionen rechts, um dieses Problem zu beseitigen. -end- db.dip.title TkGate: Dip-Wert cpath.cloops -fillbegin- In der kombinatorischen Schaltung wurde eine Rückkopplung entdeckt. Um für diese Schaltung eine Verzögerungsanalyse durchführen zu können, muß entweder die Rückkopplung aufgebrochen werden oder einige der Gatter im Rückkopplungszweig werden als "Kritische-Pfad-Aufteilung" markiert. Schaltungsteile, in denen eine Rückkopplung ent- deckt wurde, sind unten gelistet. -end- ############################################################################## # Print dialog box # #print.outto Ausgabe nach print.title TkGate: Drucken print.config.title TkGate: Druckerkonfiguration print.scope.title TkGate: Scopedruck print.printer Drucker: print.file Datei print.prcmd Druckbefehl: print.prname Drucker print.advanced Erweitert... print.filename Dateiname print.epssave Sichern als Encapsulated Postscript. #print.doctit Dokumenttitel #print.prmod Druck von Modulen print.epcm Epochen/cm print.estpg Ungefähre Seitenzahl print.all Alles print.cur Aktuelle print.use Benutzte print.sel Ausgewählte print.inclib Bibliotheksmodule einbeziehen. print.incunused Unbenutzte Module einfügen. print.papsz Papiergröße print.orient Orientierung print.portrait Hochformat print.landscape Querformat print.2side Duplexdruck print.opts Optionen print.scale Anpassen großer Module auf eine Seite. print.partition Aufteilen großer Module auf mehrere Seiten. print.incidx Index hinzufügen. print.incgraph Hierarchiegraph hinzufügen. print.4up Kleine Module: vier auf eine Seite drucken. print.rangeselection Wahl des Bereichs print.scaleselect Wahl der Skalierung print.fulltr Vollständiges Signaldiagramm print.parttr Ausschnitt aus dem Signaldiagramm print.start Start print.range Bereich print.linelen Zeilenlänge print.filesel Ausgabe in Datei print.printersel Ausgabe auf Drucker print.defaultprinter Standarddrucker print.pageset Seiteneinstellungen print.modulesel Modulauswahl ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Drucken print.printtrace.cap Signaldiagramm drucken print.printcirc.cap Schaltung drucken print.printcirc.out.exp -fillbegin- Wahl der Druckausgabe: direkt zum Drucker oder in eine PostScript-Datei. -end- print.printcirc.page.exp -fillbegin- Auswahl der Optionen für den Seitenaufbau und den Drucker. -end- print.printcirc.mod.exp -fillbegin- Auswahl der zu druckenden Module, Einstellung der Optionen für die Darstellung. -end- print.printtrace.trace.exp -fillbegin- Auswahl des Zeitbereichs für die Ausgabe und Einstellung der Skalierung, um die ungefähre Seitenzahl zu berechnen. -end- print.tab.output Ausgabe #print.tab.page Seite print.tab.modules Module print.tab.content Inhalt print.tab.advanced Einstellungen ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Optionen opt.treelabel Optionen opt.general Allgemein opt.interface Schnittstelle opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Drucken opt.print.output Ausgabe opt.print.content Inhalt opt.simulate Simulieren opt.simulate.basic Grundlegendes opt.simulate.tech Technologie opt.simulate.error Fehlerbehandlung opt.library Bibliotheken opt.library.path Pfad opt.library.load Autom. Laden opt.library.vpd VPD opt.analysis Analyse opt.color Farben opt.color.title TkGate: Farbauswahl opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Verfügbare Bibliotheken opt.lib.load.selected Ausgewählte Bibliotheken opt.identity Organisation opt.site Netzadresse opt.username Benutzername opt.libname Bibliotheksname: opt.inst Instanzen opt.mods Module opt.modports Modul-Ports opt.frames Rahmen opt.comment Kommentare opt.hlink Hyperlinks opt.wire Einfach-Leitungen opt.bus Mehrfachleitungen opt.tools Gatter-Werkzeuge opt.background Hintergrund opt.cpath Kritischer Pfad opt.grid Scope Raster opt.logic1 Logisch Eins opt.logic0 Logisch Null opt.float Float opt.unknown Unbekannt/Konflikt opt.offled LED aus opt.onled LED ein opt.zled Undefinierte LED opt.restdef Auf Standard zurücksetzen opt.regudate Auffrischen eines Gebiets opt.smoothscroll Glattes Scrolling opt.balloon Hilfeballone einschalten opt.safeSave Sicheres Abspeichern der Dateien opt.saveCells Zellen in abgespeicherte Dateien einbeziehen opt.showimage Zeige Randstreifenbilder in Dialogboxen opt.novice Novizenmodus opt.blockDropConnect Porterzeugung mit Fallenlassen von Leitungen opt.ckpoint.1 Checkpointing alle opt.ckpoint.2 Kommandos ausführen. opt.freq Intervall opt.beak Sondermodi einstellen opt.bat Bat opt.trek Star Trek opt.miles Heinrich opt.contver Automatische Integritätsprüfung opt.showsimcmd Anzeige der Simulationsgeschichte opt.estepsz Epochen Schrittweite opt.cstepsz Periodendauer Schrittweite opt.overstep Takt Ãœberschreitung opt.sorttraces Scope-Signale alphabetisch sortieren opt.vpopupdelay Pop-Up Verzögerungswert #opt.initscript Globales Initialisierungsskript opt.posedge Takt hält an allen positiven Flanken opt.setclock Takt hält an allen Flanken opt.delayfilepath Technologiedateien opt.devfilepath VPD (Virtuelles Peripheres Device) Dateipfad opt.vlibpath Verilog Bibliothekspfad opt.vlibnames Basisbibliotheken opt.display Anzeige opt.interaction Interaktion opt.input Eingabe opt.security Sicherheit opt.undolen Maximale Anzahl von Undo-Op. opt.keybind Tastaturbelegungsstil opt.useless Nutzlose Features einschalten opt.features Basis Features opt.simbase Grundlegende Simulatoroptionen opt.simclock Taktoptionen opt.cpopts Optionen für Kritische Pfade opt.maxpath Maximalzahl der Pfade: opt.cpflash Anzeige mit blinkendem Pfad opt.general.fontset Font-Klasse opt.simulator.savetraces Tastkopfpositionen zwischen Simulatorläufen sichern. opt.simulator.noglitch Glitch-Unterdrückung im Simulator einschalten. opt.simulator.err Fehlerbehandlung opt.simulator.stopany Abbrechen der Simulation bei jeder Warnung. opt.simulator.showall Warnungen immer anzeigen. opt.simulator.showiferr Warnung nur bei Fehlern. opt.simulator.ignore Alle Warnungen ignorieren. opt.tool.file Datei opt.tool.edit Editieren opt.tool.gateopt Drehen/Ausrichten opt.tool.gateprop Gatter opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Modus opt.tool.module Module opt.tool.tech Technologie opt.tool.simctl Simulatorsteuerung opt.tool.simaux Simulatorbefehle opt.tool.simmode Simulator Werkzeuge opt.tool.symmode Symboleditor Werkzeuge opt.tool.symedit Ausschneiden/Einfügen opt.tool.symport Ports opt.tool.symshift Bitverschiebung opt.tool.symopr Bitoperationen opt.editor.features Editor Features: Grundlagen opt.editor.format Automatische Einrückung einschalten opt.editor.colorize Syntax Highlighting einschalten opt.editor.comments Kommentare opt.editor.strings Strings opt.editor.reserved Schlüsselwörter opt.editor.gateword Eingebaute Gatter opt.editor.instword Modulinstanzen opt.editor.taskword Systemaufgaben opt.editor.color Farbe opt.editor.bold Fett opt.editor.italic Schräg opt.editor.indentlevel Einrückung per Stufe: opt.editor.beginindent Ausrichten von begin...end an der Einrücktiefe. opt.editor.movesel Drag-and-drop der Wahl einschalten. opt.editor.returntab Automatische Einrückung nach RETURN. opt.vercheck -begin- Periodische Nachfrage nach neuen TkGate-Versionen im Internet. Dieses Feature sollte nur bei dauerhaftem Internetzugang eingeschaltet werden. -end- opt.general.cap Allgemeine Optionen opt.editor.cap HDL Text Editor opt.interface.cap Schnittstellenoptionen opt.toolbars.cap Toolbaroptionen opt.print.cap Druckoptionen opt.analysis.cap -begin- Kritische Pfad-Optionen -end- opt.simulator.cap Simulatoroptionen opt.security.cap Sicherheitsoptionen opt.color.cap Farboptionen opt.html.cap HTML/HTTP Optionen opt.debug.cap Debug-Optionen opt.library.cap Bibliotheksoptionen opt.sec.execlevel Die $tkg$exec() Systemroutine ist opt.sec.exec komplett eingeschaltet. opt.sec.regexec nur für registrierte Funktionen eingeschaltet. opt.sec.noexec ausgeschaltet. opt.sec.simfeatures Simulator Features opt.sec.send $tkg$command() Systemroutine einschalten. opt.sec.open $fopen() Systemroutine einschalten. opt.sec.writemem $writememb() und $writememh() Systemroutinen einschalten. opt.sec.enqueue $tkg$recv() und $tkg$send() Systemroutinen einschalten. opt.sec.handle Behandlung von Sicherheitsverletzungen opt.sec.stop Beenden des Simulators bei Nutzung ausgeschalteter Features. opt.sec.warn Anzeige einer Warnung bei Nutzung ausgeschalteter Features. opt.sec.ignore Ignoriere versuchte Benutzung von ausgeschalteten Features. opt.html.linkopts Link Optionen opt.html.browser Browser Aufruf opt.html.email e-Mail Aufruf opt.debug.opt Debugging Optionen opt.color.editwin Fensterfarben editieren opt.color.scopewin Farben fürs Signaldiagramm-Fenster einstellen opt.vlibadd.title TkGate: Bibliothek hinzufügen opt.vlibadd.cap Bibliothek hinzufügen opt.vlibadd.exp -fillbegin- Gib den Dateinamen einer TkGate Verilog Bibliothek an. Bibliotheken aus der Autoload Liste werden automatisch beim Start geladen. -end- opt.editor.exp -fillbegin- Setzen der Optionen für den HDL Texteditor. -end- opt.general.exp -fillbegin- Persönliche Einstellungen und grundlegende TkGate-Optionen werden auf dieser Seite eingestellt. Die persönlichen Einstellungen werden bei der Druckausgabe benutzt. -end- opt.interface.exp -fillbegin- Einstellung der Optionen zur eigenen Gestaltung der Schnittstelle. -end- opt.toolbars.exp -fillbegin- Angabe der Toolbars, die angezeigt werden sollen. -end- opt.print.exp -fillbegin- Einstellung der Standard Druckeroptionen auf dieser Seite. -end- opt.analysis.exp -fillbegin- Diese Optionen steuern die Funktionen der kritischen Pfadanalyse. -end- opt.simulator.exp -fillbegin- Optionen, die das Arbeiten mit dem Simulator steuern. -end- opt.library.exp -fillbegin- Setzen der Suchpfade für Benutzer-Devices und Verilog-Bibliotheksdateien. -end- opt.security.exp -fillbegin- Einstellen der Simulator-Sicherheitsoptionen - Aus- bzw. Einschalten von Features kann ein Sicherheitsrisiko bei Simulation von Schaltungen aus nicht vertrauenswürdigen Quellen sein. -end- opt.color.exp -fillbegin- Optionen, die das in TkGate verwendete Farbschema steuern. -end- opt.html.exp -fillbegin- Setzen der Optionen für HTML Steueranweisungen in TkGate Schaltungskommentaren. -end- opt.debug.exp -fillbegin- Hier können Debuggingoptionen gesetzt werden. -end- opt.gen.basetoolbar Toolbars für den Editor-Kern opt.gen.simtoolbar Toolbars für den Simulationsmodus opt.gen.symedtoolbar Toolbars für den Symboleditor opt.bbar.restore Vorgaben dieser Seite wiederherstellen opt.bbar.restoreall Alle Vorgaben wiederherstellen ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Typ igen.side Seite igen.size Größe igen.bits Bits igen.modname Modulname: #igen.resort Erneut Sortieren igen.add Hinzufügen igen.delete Löschen igen.edit Editieren igen.in Eingang igen.out Ausgang igen.inout Ein/Ausgang igen.left links igen.right rechts igen.top oben igen.bottom unten #igen.other andere igen.mod Verwende nur Ports, die im Modul benutzt werden. igen.int Verwende nur Ports aus existierender Schnittstelle. igen.modint Verwende sowohl Modul- als auch Schnittstellen-Ports. igen.portsel Port Auswahl igen.portpos Port Positionen igen.portpos.keep Erhalte soweit möglich die Port-Positionen. igen.portpos.renew Erzeuge alle Port-Positionierungen neu. igen.caption Erzeugen der Schnittstelle igen.description -begin- Erzeugen einer neuen Schnittstelle für ein Modul. -end- info.script.error Skript Fehler module.props.title TkGate: Moduleigenschaften module.props Moduleigenschaften ipanel.plist Portliste ipanel.props Schnittstelleneigenschaften #ipanel.itype.change Typ ändern... #ipanel.itype.edsymbol Symbol editieren... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Automatisch erzeugen... ipanel.updateall Alles auffrischen... ipanel.itype.select Schnittstellentyp #ipanel.block.description Standardschnittstelle #ipanel.symbol.description Benutzerdefinierte Symbolschnittstelle ipanel.ppos.label Blockgröße verändern (mit Ortsveränderung der Ports): ipanel.ppos.fix Feste Positionen ipanel.ppos.scale Skalierte Positionen #ipanel.ppos.grid Raster ipanel.warn.toblock -begin- Der Schnittstellentyp dieses Moduls soll nach "Block" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Ist das wirklich so gewollt? -end- ipanel.warn.tosymbol -begin- Der Schnittstellentyp dieses Moduls soll nach "Symbol" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Zusätzlich muß ein neues Bitmapbild für das neue Symbol erzeugt werden. Ist das wirklich so gewollt? -end- ############################################################################## # # Block list dialog boxes blklst.delete.title TKGate: Modul löschen blklst.copy.title TKGate: Modul kopieren blklst.rename.title TKGate: Modul umbenennen blklst.claim.title TKGate: Modul aneignen blklst.setroot.title TKGate: Wurzel-Modul festlegen blklst.new.title TKGate: Neues Modul blklst.claim Modul aneignen blklst.to Nach blklst.from Von blklst.name Name blklst.new.cap Neues Modul erzeugen blklst.del.cap Modul löschen blklst.copy.cap Modul kopieren blklst.rename.cap Modul umbenennen blklst.claim.cap Modul aneignen blklst.setroot.cap Wurzel-Modul festlegen blklst.new.exp -fillbegin- Mit dieser Dialogbox wird eine neue Moduldefinition erzeugt. Das Modul kann als Netzliste oder HDL Modul erzeugt werden. Einmal erzeugt, kann der Typ aber nicht geändert werden; es muß gelöscht und neu erzeugt werden. -end- blklst.del.exp -fillbegin- Löschen der Definition und Schnittstellendaten des angegebenen Moduls. Existierende Instanzen des gelöschten Moduls beleiben erhalten, werden aber als undefiniert markiert. -end- blklst.copy.exp -fillbegin- Erzeugen einer Kopie der angegebenen Moduldefinition. Damit kann eine Variante eines existierenden Moduls erschaffen werden. -end- blklst.rename.exp -fillbegin- Umbenennen einer Moduldefinition. Diese Operation betrifft nur die Definition, alle existierenden Instanzen dieses Moduls verweisen weiterhin auf den alten Modulnamen. -end- blklst.claim.exp -fillbegin- Umwandeln eines Bibliotheksmoduls in ein Benutzermodul. Damit kann das Modul editiert und zusammen mit der eigenen Schaltung gesichert werden. -end- blklst.setroot.exp -fillbegin- Mache das angegebene Modul zum obersten (Top-Level). -end- find.title TkGate: Objekte finden find.label Objekte finden find.exp -fillbegin- Suche den Mustertext entweder in Gatternamen, Leitungsnamen oder in Kommentaren. Ein Doppelklick auf das Resultat führt zum gesuchten Objekt. -end- find.ignorecase Groß/Kleinschreibung ignorieren find.result.module Modul find.result.type Typ find.result.name Objektname # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Suchoptionen find.results Suchresultate # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Enthält... find.qual.begins Fängt an mit... find.qual.ends Endet mit... find.qual.matches Paßt auf... find.dom.label Nach Objekten suchen in: find.dom.gates Gatter find.dom.nets Schaltungen find.dom.text Kommentartext find.search Suchen: find.target Ziel # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Schaltungseigenschaften circ.label Schaltungseigenschaften circ.ident Identifikation circ.filev Dateiversion circ.file Dateiname circ.title Schaltungsüberschrift circ.discchg Keine Warnungen bei Verwerfen von Änderungen. circ.extbar Erweiterungsleisten benutzen. circ.autostart Automatischen Simulationsstart einschalten. circ.iniscript Initialisierungsskripte #circ.noscript Keine Skriptdateien ausgewählt. #circ.really Soll '%s' wirklich aus der Liste der Inititalisierungsskripte gelöscht werden? circ.reallyupdate -fillbegin- Sollen wirklich alle '%s' Instanzen der Schnittstelle geändert werden? -end- @circ.library.width *500 @circ.library.height *350 circ.general Allgemein circ.library Bibliotheken circ.script Skript circ.simulator Simulation circ.timescale Standard Simulations-Zeitskala circ.timescale.unit Einheit: circ.timescale.prec Genauigkeit: circ.exp -fillbegin- Schaltungsspezifische Eigenschaften betrachten und verändern. Diese Eigenschaften werden mit der Schaltung beim Sichern abgespeichert. -end- circ.exp.general -fillbegin- Betrachten und Modifizieren schaltungsspezifischer Eigenschaften. Diese Eigenschaften werden beim Speichern der Schaltung mitgesichert. -end- circ.exp.library -fillbegin- Auswählen der von dieser Schaltung benutzten Bibliotheken. Die Bibliotheksangaben werden mit der Schaltung gesichert, sie werden beim nächsten Laden der Schaltung automatisch eingelesen. -end- circ.exp.simulator -fillbegin- Anzeige und Modifikation der Simulationseinstellungen dieser Schaltung. -end- ############################################################################## # # Bibliotheksverwaltung # libmgr.cap Bibliotheksverwaltung libmgr.library Bibliothek libmgr.description Beschreibung libmgr.status Status libmgr.status.load Geladen libmgr.status.unload Nicht geladen libmgr.status.loadp [Geladen] libmgr.status.unloadp [Nicht geladen] libmgr.exp -fillbegin- Wähle zu ladende oder zu entfernende Bibliotheken aus. -end- libmgr.load Laden libmgr.unload Entfernen libmgr.unloadall Alle entfernen libmgr.notedit -fillbegin- Die Bibliotheksverwaltung kann nur im Editiermodus der Schaltung geöffnet werden. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- Rekursive Moduldefinition in '%s' gefunden. Simulator kann nicht gestartet werden. Keine kritische Pfadanalyse möglich. -end- sim.hyperlinkstop -fillbegin- Der Simulator läuft gerade. Soll die Simulation beendet und dem Link gefolgt werden? -end- ############################################################################## # # Critical path messages # cp.delay Pfadverzögerung: cp.pathl Pfadliste: cp.numpath Anzahl der Pfade: cp.recompute Neuberechnung ############################################################################## # Error messages # err.rootinterface Kann die Schnittstelle des obersten Moduls nicht definieren. err.nopin Ausgewählter Pin kann nicht verändert werden. err.badhex Illegaler Hexwert '%s', ignoriert. err.gatanchor Gatter ist (sind) verankert und können nicht bewegt werden. err.protdata Kann den Inhalt eines geschützen (Bibliotheks-)Moduls nicht ändern. err.badfind Kann Suchziel '%s' nicht finden. err.badopendel Kann geöffnetes Modul nicht löschen. err.nosrcmod Quelle zu Modul '%s' nicht gefunden. err.noerr Fehler nicht bestimmbar. err.misserr Fehler nur teilweise bestimmbar (Absturz des Simulators?) err.badinadd Kann keine Eingänge mehr zur angewählten Schaltung hinzufügen. err.badoutadd Kann keine Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badinoutadd Kann keine Ein/Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badpinchg Kann Pintyp des angewählten Gatters nicht ändern. err.badnetname Illegale Zeichen im Bezeichner gelöscht. err.netbcrename Bezeichner umbenannt in '%s' wegen illegaler Zeichen. err.netconfnet Bezeichner umbenannt in '%s' wegen Konflikten. err.netconfgat Bezeichner umbenannt in '%s' um Konflikt mit Grundgatternamen zu vermeiden. err.netconfkw Bezeichner umbenannt in '%s' um Konflikt mit Schlüsselwort zu vermeiden. err.badconsame Keine Verbindung, weil Leitungen Teil desselben Netzes sind. err.badconptsp Keine Verbindung, weil beide Leitungen Modulports oder Versorgungsleitungen sind. err.badconbitw Keine Verbindung, weil die Bitbreiten nicht zusammenpassen. err.badrange Nichtpositiver Bereich für Signaldiagramm nicht erlaubt. err.badlprcmd Druckkommando '%s' kann nicht ausgeführt werden. err.badpsopen Die Datei '%s' kann nicht für die Postscript-Ausgabe geöffnet werden. err.badid Ungültiger Bezeichner '%s' err.noinvgate Inverters sind auf Gattern dieses Typs nicht erlaubt. err.protintf Kann die geschützte Schnittstelle von Modul '%s' nicht ändern. err.bkpt.badexp Syntaxfehler in Breakpoint-Ausdruck. Mögliche Werte: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Ungültiger Netzname '%s'. Namen beginnen mit Buchstaben und enthalten nur Buchstaben, Ziffern und '.' err.bkpt.badval Syntaxfehler in Wert '%s'. Nur dezimale oder Verilog-Konstante erlaubt. err.bkpt.toomany Zu viele Breakpoints. Maximum ist %d. err.sim.badtmp Zwischendatei '%s' für Simulator konnte nicht gesichert werden (Platte voll?) err.sim.syntx Syntaxfehler in '%s' Kommando. err.sim.noincl Include-Datei '%s' nicht gefunden. err.sim.badedge Illegaler Flanken-Indikator '%c' in Takt-Kommando. err.sim.nobkpt Kein derartiger Breakpoint '%s'. err.sim.nonet Kann Netz '%s' nicht finden. err.sim.nogate Kann Gatter '%s' nicht finden. err.sim.badbin Illegales Zeichen in binärer Konstante '%s'. err.sim.notswitch Schaltung '%s' ist kein Schalter, DIP-Schalter oder Register. err.sim.badcmd Kommando '%s' im Simulations-Skript unbekannt. err.sim.isrun Simulator läuft bereits (Beenden mit 'Ctrl-s e'). err.sim.run Laufzeitfehler err.sim.cmd Interner Fehler (Befehl) err.noteditpchg Eigenschaften können nur im Edit-Modus geändert werden. err.badeditop Illegale Operation im Schnittstellen-Editiermodus. err.badopen Datei '%s' kann nicht geöffnet werden. err.badlibopen Bibliotheksdatei '%s' kann nicht geöffnet werden. err.nomark Vor dem Anwählen eines Schaltungstyps eine Markierung setzen (linke Maustaste). err.badgate Unbekannter Schaltungstyp. err.badportadd Zu diesem Gattertyp ist Hinzufügen von Ports nicht möglich. err.modmissing HDL Modultext fehlt für Modul "%s". err.modtoomany Ãœberzählige Moduldefinitionen in Modul "%s". err.modmismatch Namens-mismatch zwischen Textdefinition und Modulname in "%s". err.manypages -begin- Dieses Dokument hat entsetzlich viele Seiten! Soll es tatsächlich gedruckt werden? -end- err.nojump -begin- Die Funktion 'Springe-zum-Modul' kann bei der Simulation und bei der Analyse Kritischer Pfade nicht genutzt werden. Stattdessen sollte von Hand zum Zielblock navigiert werden, indem Module selektiert und mit der Taste '>' geöffnet werden. Das Modul kann mit der Taste '<' wieder verlassen werden. -end- err.nomod Modul '%s' nicht definiert. err.modlock Logikblock ist gesperrt! err.closeroot Toplevel Modul kann nicht geschlossen werden. Quit benutzen. err.editonly Kommando im Simulationsmodus nicht möglich. err.simonly Kommando nur im Simulationsmodus möglich. err.deltop Toplevel Modul '%s' kann nicht gelöscht werden. err.delprot Geschütztes Modul '%s' kann nicht gelöscht werden. err.nodel Keine löschbare Auswahl. err.modnotdef Modul '%s' ist nicht definiert. err.moddef Der Block '%s' existiert bereits. err.primredef Built-in element name '%s' can not be redefined. err.noprop Das ausgewählte Gatter hat keine editierbaren Eigenschaften. err.openscript Datei mit Simulationsskript '%s' kann nicht geöffnet werden. err.oldversion Geladene Datei hat veraltete Versionsnummer '%s' (die aktuelle Version ist '%s'). err.futureversion Geladene Datei mit künftiger TkGate-Version '%s' gesichert (die aktuelle Version ist '%s'). err.badversion Unbekannte Versionsnummer. Benutzung auf eigene Gefahr. err.nodrive Netz '%s' hat keinen Treiber in Modul '%s'. err.noconn Leitung %s{%d} ist unverbunden -- gelöscht. err.oldportact Port hinzufügen/ändern durch Rechtsklick auf Port oder Modulkante err.nomodule Kein ausgewähltes Modul. err.nomodop Keine geeigneten Module zum Betrieb verhanden. err.protexec Versuchte Ausführung des geschützten Befehls '%s' in $tkg$exec(). err.notwritable Datei '%s' ist nicht beschreibbar. err.backupfail Erzeugen einer Backupdatei '%s' gescheitert. err.yy.badprop Unbekannte Schaltungseigenschaft '%s' wird ignoriert. err.yy.baddata Falscher Datentyp für Schaltungeigenschaft '%s' gewählt. err.yy.nosym Kein aktuelles Modulsymbol definiert. err.yy.badicon Falscher Icontyp '%s'. err.yy.toomuchdata Zu viele Icon-Daten. err.yy.nosyminst Fehlerhaftes Symbol %d in Instanz %s von %s. err.yy.badmodprop Unbekannte Moduleigenschaft '%s' wird ignoriert. err.yy.badmoddata Fehlerhafter Datentyp für Moduleigenschaft '%s' festgelegt. err.yy.badprim Unbekanntes Schlüsselwort '%s'. err.yy.nonet Undeklariertes Netz '%s'. err.yy.bogussave Gesicherte Schrottdaten entdeckt. Schaltung kann beschädigt sein. err.yy.pinformat Illegales Pin Namensformat '%s'. err.yy.pinname Pinname '%s' ist für Gattertyp '%s' nicht definiert. err.yy.nonetpos Kein Netz für Position %d in Gatter %s. err.yy.baddirective Illegale oder fehlerhafte Direktive '%s'. err.corruptnewsave -fillbegin- TkGate konnte die Datei in '%s' sichern, sie scheint aber korrupt zu sein. Sind Aufsetzpunkte definiert: Lade eine der Checkpoint Dateien. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.corruptsave -fillbegin- TkGate hat ein Problem bei der Sicherung der Datei '%s' entdeckt. Die existierende Datei wurde nicht modifiziert, die beschädigte Datei wurde nach '%s' geschrieben. Ist die Verwendung von Aufsetzpunkten eingeschaltet, kann versuchsweise eine der Checkpoint-Dateien geladen werden. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.badsave -fillbegin- Beim Öffnen oder Schreiben in Datei '%s' gab es ein Problem. Bitte Datei/Verzeichnisrechte und/oder verfügbaren Plattenplatz überprüfen. -end- err.nosafesave -fillbegin- Beim Versuch der Sicherung von Datei '%s' ist ein Problem aufgetreten. Es ist möglich, einen erneuten Versuch ohne Sicherungsvalidierung zu starten. Bei Antwort "nein" bleibt die Originaldatei unverändert. Bei Antwort "ja" wird die Originaldatei überschrieben, wird aber ggf. beim Auftreten eines Fehlers zerstört. Soll eine unvalidierte Sicherung versucht werden? -end- err.noback -fillbegin- Die Datei wurde von TkGate, Version %s, erzeugt und ist nach Sichern mit der aktuellen Version %s möglicherweise von früheren Versionen nicht mehr lesbar. -end- err.viewfile Datei '%s' kann nicht geöffnet werden. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod Interner Fehler: Kann Module '%s' nicht finden. ############################################################################## # Informational messages # msg.selwire Ausgewählt: Die Leitung hat den Namen '%s'. msg.selgate Ausgewählt: %s hat den Namen '%s'. msg.selblock Ausgewählt: %s Block hat den Namen '%s'. msg.iselwire Der ausgewählte Port '%s' ist in Block '%s'. msg.iselgate Das ausgewählte %s, genannt '%s' (huch? Diese Meldung sollte nicht möglich sein). msg.iselblock Ausgewählte Modulschnittstelle ist '%s'. msg.modoverwt Zielmodul '%s' existiert bereits. Ãœberschreiben? msg.foundgate Gatter mit Namen '%s' gefunden. msg.foundwire Leitung mit Namen '%s' gefunden. msg.searchagn Suchstring '%s' nicht gefunden. Mit 'find' Suche erneut starten. msg.sim.chgtoroot Simulationsmodus braucht das root-Modul oben auf dem Editierstack. msg.sim.nogatemod Der Simulationsmodus braucht einen konkreten Modulstack. msg.setinterface Setzen der Modulschnittstelle für '%s'. msg.needsel Bitte eine Modulinstanz auswählen. msg.wroteckpt Kontrollpunkt auf %s gesetzt... msg.save Schaltung als '%s' gesichert. msg.reallynew Die Schaltung wurde verändert. Soll sie wirklich gelöscht und eine neue erzeugt werden? msg.reallyquit Die Schaltung wurde verändert. Soll das Progamm wirklich beendet werden? msg.notlib Modul '%s' ist kein Bibliotheksmodul. ############################################################################## # Heinrich messages (Activated when Heinrich Hacker uses tkgate) # miles.msg1 Nur ein Trottel würde %s%s hierhin plazieren, Heinrich. miles.msg2 Eine richtig doofe Stelle, um %s%s abzulegen, Heinrich. miles.msg3 Ein schrecklich ungeeigneter Platz für %s%s, Heinrich. miles.msg4 Heinrich, Du bist ein Trottel %s%s hierhin zu setzen. miles.msg5 Heinrich, Du allein schaffst es, %s%s hierhin zu plazieren. miles.msg6 %s%s hierhin zu setzen beweist, daß Du ein totaler Trottel bist, Heinrich. miles.msg7 Warum gibst Du nicht auf, Heinrich, das ist eine hirnrissige Schaltung. miles.msg8a Es hat keinen Sinn weiterzumachen, Heinrich. miles.msg8b Heinrich, Du hast keine Ahnung wie man eine Schaltung baut. miles.msg8c Heinrich, mir graut vor Dir. ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Portgrößen-mismatch bei Eingangsport '%s'. verga.err.OUTPORT Portgrößen-mismatch bei Ausgangsport '%s'. verga.err.FLOATNET Netz '%s' hat keinen Treiber (floating net). verga.err.DIRECTCONN Direct connect Operator '=>' wird nicht unterstützt. Wird als '*>' behandelt. verga.err.MEMADDR Versuch, in Speicher %s mit unbekannter Adresse zu schreiben. verga.err.MEMBITS Versuch, in Speicher %s mit unbekanntem Bitbereich zu schreiben. verga.err.BADARRAYUSG Array '%s' wird im Ausdruck ohne Index verwendet. verga.err.BADARRAYLHS Array '%s' wird auf der linken Seite ohne Index verwendet. verga.err.BADCLOSE Versuch, einen nicht geöffneten Deskriptor in Task '%s' zu schließen. verga.err.BADAUTORNG Auto range [*] ist nur gültig in Leitungs-Deklarationen 'wire'. verga.err.BADGATERNG Fehlerhafter Bereichausdruck für eine Gatter-Instanz. verga.err.BADARGVALUE Fehlerhafter Wert für Argument '%s' in Task '%s'. verga.err.DIVZERO Teilung durch Null. verga.err.NODIV Divide/module wird auf dieser Maschine nicht unterstützt - sizeof(short) muß 2 sein. verga.err.BADEDGEEVENT Ereignis im Multi-Bit Netz '%s' kann kein posedge/negedge haben. verga.err.NEEDEDGE Positive oder negative Flanke muß für Event %s spezifiziert werden. verga.err.ASGNEVENT Warten auf ein Event ist bei Zuweisung illegal. verga.err.PROTTASK Ausführung der geschützen System Task '%s' wird blockiert. verga.err.NEEDIDENT Für Argument %s von Task '%s' wird ein Bezeichner erwartet. verga.err.BADOP Operatorfehler-Ausdruck in '%s'. verga.err.NOREAD Laden von Quelldatei '%s' fehlgeschlagen. verga.err.MEMFILE Öffnen von Speicher-Datei '%s' fehlgeschlagen. verga.err.WRONGMOD Modul '%s' wurde gefunden statt '%s'. verga.err.NOTPARM Bezeichner '%s' im konstanten Ausdruck ist kein Parameter. verga.err.BADADDR Illegaler Adressbereich für Port '%s'. verga.err.BADADDRSPEC Illegale Adressbereichsspezifikation '%s'. verga.err.BADCHAR Illegales Zeichen (%s) '%s'. verga.err.BADEVENT Illegaler Ausdruck zur Ereignissteuerung. verga.err.BADCONSTOP Illegaler Operator in konstantem Ausdruck. verga.err.BADXOP Illegaler Operator in Ausdruck. verga.err.NETREDEF Illegale Redefinition des Netzes '%s'. verga.err.BADINOUT Ein/Ausgabe-Verbindungen müssen bei Port '%s' von Netz zu Netz sein. verga.err.MODUNDEF Instanz eines undefinierten Moduls '%s'. verga.err.BADASGNLHS Ãœngültige linke Seite in 'assign'. verga.err.LHSNOTREG Illegale Benutzung von '%s' auf der linken Seite einer Zuweisung. verga.err.BADLHS Ungültige linke Seite in Zuweisung. verga.err.BADOUT Ãœngültige Ausgangs-Zuweisung. verga.err.NOTREG Speicher müssen als Register deklariert werden. verga.err.PORTMIX Vermischte benannte und unbenannte Ports bei Schnittstelle '%s' von '%s'. verga.err.REPCASE Mehr als ein default: in case-Anweisung. verga.err.NOMEM In der gelesenen Speicherdatei gibt es keinen aktuellen Speicher. verga.err.BADCMD Es gibt keinen Befehl '%s'. verga.err.CMDNOTNET Es gibt kein Netz '%s' im '%s' Befehl. verga.err.MEMNONBLK Nicht-blockierende Zuweisungen zu Speicherbereichen sind nicht implementiert. verga.err.NOTPPORT Parameter '%s' ist nicht als Port deklariert. verga.err.REDEFP Parameter redefiniert Bezeichner '%s'. verga.err.PORTNOTDEF Port '%s' in Schnittstelle '%s' ist in Modul '%s' nicht definiert. verga.err.NOCONN Port '%s' hat keine Verbindungen mit Schnittstelle '%s' von '%s'. verga.err.MULTCONN Port '%s' hat Mehrfachverbindungen mit Schnittstelle '%s' von '%s'. verga.err.PORTCOUNT Portanzahl paßt nicht zur Definition der Schnittstelle '%s' von '%s'. verga.err.BADPRTRANGE Der Bereich von Port '%s' isr nicht numerisch. verga.err.BADARRAYRNG Bereichsspezifikation ist für eine Speicherreferenz von '%s' nicht erlaubt. verga.err.CMDMODREDEF Redefinition des dynamischen Moduls '%s'. verga.err.REDEF Redefinition des Beziechners %s. verga.err.PROTTASKSTOP Simulation beendet nach versuchter Ausführung der geschützten System-Task '%s'. verga.err.NOTMEM Das spezifizierte Netz '%s' ist kein Speicher. verga.err.CMDNOTMEM Das spezifizierte Netz '%s' ist kein Speicher in Befehl '%s'. verga.err.SYNTAX Syntaxfehler. verga.err.TOOFEWPP Zu wenig Parameter Ports bei Instanz %s. verga.err.OPENTOOMANY Zu viele geöffnete Dateien in Task '%s'. verga.err.TOOMANYPP Zu viele Parameter Ports bei Instanz %s. verga.err.NOTOP Oberstes Modul '%s' nicht definiert. verga.err.BADOPEN Ausgabedatei '%s' in Task '%s' kann nicht geöffnet werden. verga.err.CMDNOMOD Undefiniertes dynamisches Modul '%s' in Befehl '%s'. verga.err.BADEVENTNET Undefiniertes Netz '%s' in Ereignissteuerungs-Ausdruck. verga.err.NOTASK Undefinierte Task '%s'. verga.err.NOTDEF Undefinierte Variable '%s'. verga.err.BADRANGE Nicht unterstützter Bitbereich [%s] in Netz %s (muss von der Form [n:0] sein). verga.err.GATEUNIMP Unimplementierter primitiver Gatter-Instanz-Typ. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Schreiben auf einen bereits geschlossenen Deskriptor. verga.err.PRIMPTCOUNT Falsche Anzahl von Ports bei der primitiven Gatter-Intsanz '%s'. verga.err.CMDARGS Falsche Zahl von Argumenten im '%s' Befehl. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' mit der falschen Anzahl von Argumenten aufgerufen. verga.err.BADSTART Illegaler Anfangswert in Task '%s'. verga.err.BADSTOP Illegaler Stopwert in $readmemb. verga.err.SPECTASKUSG Task '%s' muss in einem Specify-Block benutzt werden. verga.err.BADSPECTASK Task '%s' kann nicht in einem Specify-Block benutzt werden. verga.err.TIMING Fehler im Zeitablauf bei %s in %s[%s] %s. verga.err.NOIFDEF Kein passendes `ifdef/`ifndef für die %s Deklaration. verga.err.BADSPECLVAL Bitbereiche sind bei Pfadverzögerungs-Spezifikatoren nicht unterstützt. verga.err.PATHDITEM Nicht unterstütztes Konstrukt in Modul mit Pfadverzögerungs-Spezifikation. verga.err.PATHDINOUT Benutzung von 'inout' in Modul mit Pfadverzögerungs-Spezifikation wird nicht unterstützt. verga.err.PATHDLOOP Schleifen in Modulen mit Pfadverzögerungs-Spezifikation werden nicht unterstützt. verga.err.PATHDCOND Setzen von DelaMust durch # Ausdruck und Blockspezifikation. verga.err.TASKREDEF Redefinition eines Task oder einer Funktion '%s' in Modul '%s'. verga.err.TASKASFUNC Task '%s' wird als Funktion benutzt. verga.err.FUNCASTASK Funktion '%s' wird als Task benutzt. verga.err.TASKBADTYPE Nicht-Register-Typ in Task oder Funktion benutzt. verga.err.TASKBADPORT In Funktionen sind nur Eingabeports erlaubt. verga.err.TIMESCALEU Ungültige Einheit '%s' in `timescale Deklaration. verga.err.TIMESCALEN Ungültige Skala '%s' in `timescale Deklaration (muss 1, 10 oder 100 sein). verga.err.TIMESCALES Ungültige Syntax in `timescale Deklaration. verga.err.TIMESCALEX Einheiten müssen größer sein als die Genauigkeit der `timescale Deklaration. verga.err.TIMESCALEAN Der Entwurf enthält Module mit und ohne `timescale verga.err.BADPORTTYPE Ungültige Typdeklaration, benutzt bei '%s' verga.err.BADVALUE Ungültiger Zahlenwert '%s'. verga.err.NONEXPCTL Ereignissteuerung @(*) auf einen Nicht-Ausdruck angewendet. verga.err.NONSTATCTL Eriegnissteuerung @(*) auf eine Nicht-Anweisung angewendet. verga.err.IE_TASK Task Definition '%s' außerhalb von Modul gefunden - interner Fehler. verga.err.IE_NONET Netz '%s' nicht gefunden - interner Fehler. verga.err.IE_NOOP Operatorbeschreibung nicht zu finden - interner Fehler. verga.err.IE_BADEXP Unerwarteter Ausdruckstyp %s - interner Fehler. verga.err.IE_BADVAR Undefinierte Variable oder unbekanntes Netz - interner Fehler. verga.err.IE_BADSTATE Unerwarteter interner Zustand bei %s - interner Fehler. verga.err.IE_RETURN BCReturn bytecode ausgeführt bei leerem Returnstack - interner Fehler. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Alle Items in die selektierte Liste. ho.setsel.alll Alle Items in die nicht selektierte Liste. ho.setsel.ltor Highlight-Items in die selektierte Liste. ho.setsel.rtol Highlight-Items in die nicht selektierte Liste. ho.net.in Single-Bit Eingang ho.net.out Single-Bit Ausgang ho.net.inout Single-Bit Ein/Ausgang ho.net.in2 Multi-Bit Eingang ho.net.out2 Multi-Bit Ausgang ho.net.inout2 Multi-Bit Ein/Ausgang ho.net.wire Single-Bit Leitung (Name sichtbar) ho.net.wire2 Multi-Bit Leitung (Name sichtbar) ho.net.hwire Single-Bit Leitung (Name versteckt) ho.net.hwire2 Multi-Bit Leitung (Name versteckt) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Sichern und Laden von Schaltungsdateien ho.opt.tool.edit Ausschneide-, Einfüge- und Suchoperationen ho.opt.tool.gateopt Gatterdrehungen und Ausrichtungsoperationen ho.opt.tool.gateprop Grundlegendes Editieren von Gattern ho.opt.tool.undo Undo und Redo Operationen ho.opt.tool.zoom Zoom in und Zoom out ho.opt.tool.mode Auswahl des Editierwerkzeugs ho.opt.tool.module Erzeugen, Löschen, Umbenennen etc. von Moduldefinitionen ho.opt.tool.tech Auswahl der Standardtechnologie für Gatter ho.opt.tool.simctl Start, Stop und Pause beim Simulator ho.opt.tool.simaux Weitere Simulatorbefehle (Lesen und Schreiben von Speicherdateien etc.) ho.opt.tool.simmode Im Simulator zwischen dem Auswahl- und dem Scroll-Werkzeug wählen. ho.opt.tool.symmode Auswahl eines Editierwerkzeugs im Symboleditor ho.opt.tool.symedit Ausschneide- und Einfügeoperationen für den Symboleditor ho.opt.tool.symport Port-Drehoperationen für den Symboleditor ho.opt.tool.symshift Verschieben der Bitmap oder von Teilen der Bitmap ho.opt.tool.symopr Verschiedene Symboleditor-Operationen ho.opt.editor.movesel -begin- Ein ausgewählter Textblock kann mit dem Mauszeiger angefaßt und in eine neue Position verschoben werden, wenn die Option angewählt ist. -end- ho.opt.editor.format -begin- Verilog Quellcode wird automatisch eingerückt, wenn die TAB-Taste gedrückt wird. -end- ho.opt.editor.indent -begin- Anzahl der Leerzeichen pro Einrückungsstufe. -end- ho.opt.editor.rtab -begin- Automatisches Einrücken der aktuellen Zeile und Tabulation zur entsprechenden Einrückung wenn RETURN gedrückt wird. -end- ho.opt.editor.beginindent -begin- Führt zur selben Einrückungstiefe eines begin..end-Blocks wie beim Vater-Block. -end- ho.opt.editor.colorize -begin- Einschalten der kontextabhängigen Einfärbung von Quellcode nach den untenstehenden Optionen. -end- ho.hdl.splitexp -begin- Mehrfachmodule im HDL-Text werden in verschiedene Module augespalten, die nach Bedarf neue Module definieren. Alle Namenskonflikte werden durch leichte Veränderung der Modulnamen aufgelöst. -end- ho.hdl.commentexp -begin- Module, die nicht auf den erwarteten Namen passen oder das oberste Modul sind, werden zu HDL-Kommentaren konvertiert. -end- ho.hdl.autoeditexp -begin- Automatisches Editieren der HDL Beschreibung zur Änderung des Modulnamens. -end- ho.hdl.cancelexp -begin- Keine Aktion ausführen und das Editieren des aktuellen Moduls fortsetzen. -end- ho.hdl.ignoreexp -begin- Ignorieren der Inkonsistenz und Fortsetzung der ausgewählten Aktion. -end- ho.new -begin- Aufgeben der aktuellen Schaltung und Editieren einer neuen. -end- ho.open Einlesen einer Schaltung aus einer Datei. ho.save Sichern der Schaltung in die aktuelle Datei. ho.saveas Sichern der Schaltung in eine neue Datei. ho.print Drucken der aktuellen Schaltung. ho.library Laden einer Bibliotheksdatei. ho.symed.tab.normal -begin- Editieren der nicht ausgewählten Symbol-Bitmap -end- ho.symed.tab.select -begin- Editieren der ausgewählten Symbol-Bitmap -end- ho.simmove -begin- Wähle Leitungen und Module aus, bediene die Schalter und gib DIP Werte ein. Klicken und festhalten einer Leitung zeigt ihren aktuellen Wert. -end- ho.move -begin- Bewegen/Verbinden - Klicken und Ziehen - setzt die Position für ein neues Gatter, - bewegt Gatter und Leitungen, - verbindet Leitungen Ein Doppelklick editiert - Gatter-, Leitungs- und Port-Eigenschaften, - Kommentartext. -end- ho.delgat -begin- Gatter entfernen - Werkzeug zum Löschen von Gattern. -end- ho.cutw -begin- Leitung trennen - Werkzeug zum Durchschneiden von Leitungen. -end- ho.scroll -begin- Scrollen - zum Einfangen und Ziehen des Editier-Canvas. -end- ho.inv -begin- Invertieren - Werkzeug zum Hinzufügen oder Löschen von Invertern an Ein- und Ausgängen von Gattern. -end- ho.bitw -begin- Bitbreite - Werkzeug zum Ändern der Breite eines Leitungsbündels. Eingabe der Anzahl der Leitungen in der Eingabebox rechts unten neben dem Logo. -end- ho.ipanel.select -begin- "Standard"-Module werden für normale rechteckige Schnittstellen benutzt, "symbolische" Module für hausgemachte Bitmap-Symbole. -end- ho.ipanel.addport -begin- Einen Port zu einem Modul hinzu- fügen. Doppelklicken nach dem letzten Item bewirkt dasselbe. -end- ho.ipanel.deleteport -begin- Löschen des ausgewählten Ports. -end- ho.ipanel.editport -begin- Editieren des ausgewählten Ports. Ein Feld in einem Port wird mit Doppelklick editiert. -end- ho.ipanel.generate -begin- Erzeugen einer neuen Schnittstelle für ein Modul, basierend auf Ports in der Port-Liste und in der Modul- definition benutzen Portelementen. -end- ho.ipanel.updateall -begin- Ersetze in allen Instanzen dieses Moduls die Schnittstelle durch die hier gezeigte kanonische Schnittstelle. -end- ho.ipanel.prot -begin- Verbiete die Änderung der Definition eines Moduls. -end- ho.ipanel.protint -begin- Verbiete die Änderung der Schnittstelle eines Moduls. -end- ho.ipanel.proted -begin- Verbiete die Änderung der Schnittstelle eines Moduls außer mit Hilfe des Schnittstelleneditors. Das dient der Verhinderung unabsichtlicher Änderungen der Schnittstelle im Haupteditorfenster -end- ho.ipanel.scale -begin- Wird ein Modul in der Größe verändert, so skaliere die Abstände zwischen den Ports mit. -end- ho.ipanel.fix -begin- Wird ein Modul in der Größe verändert, so behalte trotzdem die Abstände zwischen den Ports bei. -end- ho.mod.open Ausgewähltes Modul öffnen. ho.mod.close Aktuelles Modul schließen. ho.mod.new Einen neuen Modultyp erzeugen. ho.mod.del Modul löschen. ho.mod.copy Modul kopieren. ho.mod.rename Modul umbenennen. ho.mod.claim -begin- Konvertieren eines Bibliotheksmoduls in ein reguläres Modul. -end- ho.mod.setroot -begin- Auszeichnen eines Moduls als oberstes (Wurzel-)Modul. -end- ho.mod.type.allparts Bibliothekssammlung ho.mod.type.partlib Bibliothek ho.mod.type.part Bibliotheksmodul ho.mod.type.unknown Unbekannter Modultyp ho.mod.type.unused Sammlung unbenutzer Module ho.mod.type.conflict Modulrekursion ho.mod.type.root Oberstes (Toplevel-) Modul ho.mod.type.netlist Netzlisten Modul ho.mod.type.Lnetlist Netzlisten Modul (locked) ho.mod.type.hdl HDL Modul ho.mod.type.Lhdl HDL Modul (locked) ho.undo Undo früherer Aktion(en) ho.redo Redo von Undo-Aktion(en) ho.tab.edit -begin- Primärer Editiermodus. -end- ho.tab.interface -begin- Editieren der Modulschnittstellen. Ein Doppelklick im Schnittstellenmodus auf ein Modul der Modulliste führt zum Editieren seiner Schnittstelle. Im obersten Modul werden alle Schnittstellen anzeigt. -end- ho.tab.simulate -begin- Start des Simulators, Öffnen des Logikanalysators und Ausführen aller festgelegten Initialisierungsskripte. -end- ho.tab.cpath -begin- Suche die kritischen Pfade einer Schaltung. -end- ho.log -begin- Log von TkGate Meldungen: Fehlermeldungen, informelle Meldungen und Simulator-Konsolenausgabe. -end- ho.simgo -begin- Ist eine Simulation aktiv: kontinuierlich laufen lassen. Ist keine Simulation aktiv: Starten der Simulation und Ausführen aller Initialisierungsskripte. -end- ho.simpause -begin- Pause bei einer kontinuierlich laufenden Simulation. -end- ho.simstep -begin- Start des Ablaufs eines festen Zeitintervalls im Einzelschrittmodus. Im Fenster Simulation->Optionen kann die Schrittweite gesetzt werden. -end- ho.simclock -begin- Ablauf einer festen Anzahl von Taktzyklen. Dazu im Fenster Simulation->Optionen die Schrittweite setzen. -end- ho.simstop -begin- Beenden der aktuellen Simulation, Rückkehr in den Editiermodus. -end- ho.simbreak -begin- Editieren der aktuellen Breakpoints. Die Simulation hält, wenn eine Breakpoint-Bedingung wahr wird. -end- ho.simexec -begin- Verwalten der Sammlung aktiver Skripte. -end- ho.simoptions -begin- Setzen verschiedener Optionen, die die Simulation steuern. -end- ho.simload -begin- Laden des Speichers mit dem Inhalt einer .mem-Datei. -end- ho.simdump -begin- Speicherinhalt in eine .mem-Datei schreiben. -end- ho.modlist -begin- Listen aller aktuell geladener Moduln in alphabetischer Ordnung. Ziehe die Moduln ins Editierfenster, um neue Instanzen zu erzeugen. -end- ho.modtree -begin- List of all modules currently in a hierarchical list. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- Liste der Netze im aktuellen Modul. Das Symbol links vom Namen zeigt an, ob das Netz einbittig (grün) oder mehrbittig (rot) ist. Ein "A" im Symbol zeigt, ob der Netzname als sichtbar markiert ist. -end- ho.ports -begin- Liste der Ports des aktuellen Moduls. Das Symbol vor dem Port zeigt seine Richtung an. -end- ho.status.logo -begin- Anzeige des Simulations-Status. Wird das Eisentor-Logo angezeigt, ist TkGate im Editiermodus. Wird das vierbeinige UND- Gatter gezeigt, ist TkGate im Simulations- modus. Steht dieses UND-Gatter, so ist die Simulation angehalten; läuft es, so läuft auch die Simulation. -end- ho.status.msg Anzeigefeld für Meldungen von TkGate. ho.status.block Modulstack, der gerade editiert wird. ho.status.file -begin- Aktuelle Datei, die gerade editiert wird. Ein '*' hinter dem Dateinamen zeigt an, daß der Puffer seit der letzten Sicherung verändert worden ist. -end- ho.print.selall Ausdrucken aller zur Zeit von TKGate geladenen Module. ho.print.selcur Ausdruck des aktuellen Moduls aus dem Editierfenster. ho.print.seluse -begin- Drucke alle Moduln, die gerade "in Gebrauch" sind. Das sind solche, die Abkömmlinge des root-Moduls sind. -end- ho.print.fulltrace Drucken des ganzen Signaldiagramms. ho.print.parttrace -begin- Drucken eines Teils des Trace. Start- und Stopzeiten werden im Eingabefenster unten eingetragen. Man kann auch mit der rechten Maustaste den Bereich auf dem Scope-Fenster auswählen (mit Shift-Rechts werden große Bereich ausgewählt). -end- ho.print.parttracestart Startzeit der Trace-Ausgabe. ho.print.parttraceend Endezeit der Trace-Ausgabe. ho.print.selsel -begin- Drucke nur die unten angewählten Module. Benutze die Strg-Taste zur Auswahl mehrerer Module. -end- ho.print.modlist Wähle die zu druckenden Module aus. ho.print.timegraph -begin- Hier wird das zum Drucken ausgewählte Gebiet gezeigt. Der grüne Bereich ist der Gesamtbereich der verfügbaren Signaldaten, grau wird die zu druckende Fläche angezeigt. Verwende die Selektoren auf der Linken um ein Gebiet auszuwählen oder wähle das Gebiet im Scopefenster aus, bevor diese Dialogbox geöffnet wird. -end- ho.circuit.discchg -begin- TkGate zeigt keine Warnung an, wenn Änderungen ohne Sicherung verworfen werden. -end- ho.circuit.extbar -begin- Grundgatter (AND, OR, XOR) benutzen für Mehrfacheingänge Erweiterungsleisten. -end- ho.circuit.autostart -begin- Die Simulation beginnt, sobald das Simulationsfenster angewählt ist, wenn diese Option eingeschaltet ist. -end- ho.cmd.bitw -begin- Vorgegebene Bitbreite für mit dem Bitbreite-Werkzeug selektierte Leitungen. -end- ho.edgat.signam -begin- Der Name des ausgewählten Signals am ausgewählten Gatter. Der Name des Signals kann hier durch Editieren geändert werden. -end- ho.edgat.port -begin- Der Name des Ports für dieses Signal am Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.iolab -begin- Die Richtung des ausgewählten Signals am ausgewählten Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.bitlab -begin- Die Bitbreite des ausgewählten Signals des ausgewählten Gatters. Die Bitbreite kann hier durch Editieren geändert werden. -end- ho.edgat.cycle Die Gesamtzahl der Epochen in einem Taktzyklus. ho.edgat.phase Der Startpunkt des Zyklus (in Prozent). ho.edgat.duty Der Prozentsatz des Zyklus, in dem der Takt 'low' ist. ho.edgat.hide -begin- Setze dieses Flag, um die Anzeige des Gatternamens zu verhindern. -end- ho.edgat.gtype Typ des Gatters. ho.edgat.gname Name dieser Gatterinstanz. ho.edgat.ganchor Setze dieses Flag, um die Position des Gatters zu verankern. ho.edgat.gx X Koordinate des Gatters. ho.edgat.gy Y Koordinate des Gatters. ho.edgat.swstate -begin- Der zu benutzende Anfangszustand des Schalters beim Start der Simulation. -end- ho.edgat.dipstate -begin- Der zu benutzende Anfangszustand des DIP-Schalters beim Start der Simulation. -end- ho.edgat.range Der Bitbereich, der aus einem Bus herausgeführt wird. ho.edgat.memfile -begin- Die Datei mit dem Anfangszustand für diesen Speicher. Die Datei wird gelesen, wenn der Simulator gestartet wird. -end- ho.edgat.func Der Funktionstyp dieses Moduls. ho.edgat.frame Die Markierung des Rahmens. ho.traceprint -begin- Drucke den Bereich des Logik-Signaldiagramms, der mit der rechten Maustaste ausgewählt ist. Shift-Rechts-Klick kann benutzt werden, um das augewählte Gebiet zu vergrößern. Der in der Scope-Ansicht sichtbare Bereich wird genutzt, falls keine Auswahl erfolgt ist. -end- ho.showxhair -begin- Wird dieser Knopf gedrückt, erscheint eine senkrechte Maßlinie im Scope-Fenster. -end- ho.opt.general.fontset -begin- Legt die Fontgröße des Basisfonts in der TkGate- Benutzerschnittstelle fest. Diese Option wird erst aktiv, wenn TkGate neu gestartet ist. -end- ho.opt.sec.send -begin- Aktivieren der $tkg$command() System Task erlaubt es Anwendungsschaltungen, dem TkGate GUI beliebige Simulator-Steuerkommandos zu senden. Dazu gehört auch die Fähigkeit zum Ausführen beliebiger Shellbefehle. Wird der Simulator zum Ausführen von Schaltungen unklarer Herkunft benutzt, sollte diese Task lieber ausgeschaltet bleiben. Aktivierung führt zu einem hohen Sicherheitsrisiko! -end- ho.opt.sec.open -begin- Aktivieren der $fopen() System Task erlaubt Anwendungsschaltungen in beliebige Dateien des Benutzers zu öffnen. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.writemem -begin- Aktivieren der $writememb() und $writememh() System Tasks erlaubt es Anwendungsschaltungen in beliebige Dateien des Benutzers zu schreiben. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.enqueue -begin- Aktivieren der $tkg$recv() und $tkg$send() System Tasks erlaubt virtuellen peripheren Geräten Botschaften an TkGate Schaltungen zu senden. Das ist ein relativ geringes Sicherheitsrisiko. -end- ho.opt.ssave -begin- Führe Konsistenzüberprüfungen von Schaltungsdateien durch, bevor eine existierende Sicherungsdatei überschrieben wird. Damit wird überprüft, ob es keine Probleme mit der Sicherungsdatei gibt. -end- ho.opt.sec.exec -begin- Die volle Aktivierung der $tkg$exec() System Task erlaubt es dem Benutzer, beliebige tcl/tk-Befehle einschließlich der Ausführung beliebiger Shellbefehle abzusetzen. Die Aktivierung dieser Option stellt also ein sehr hohes Sicherheitsrisiko dar. -end- ho.opt.sec.regexec -begin- Die Aktivierung der $tkg$exec() System Task für registrierte Funktionen erlaubt es Anwendungsschaltungen, nur tcl/tk Kommandos auszuführen, die als sicher registriert sind. Solange alle virtuellen peripheren Geräte vertrauenswürdig sind, hält die Aktivierung von $tkg$exec() auf dieser Stufe gefährliche Befehle von der Ausführung ab. Das Einschalten dieser Option hat ein mittleres Sicherheitsrisiko zur Folge. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- Ist diese Einstellung aktiviert, wird die Simulation beendet, sobald von der Anwendungsschaltung versucht wird, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.warn -begin- Ist diese Einstellung aktiviert, wird die Simulation nach einer Warnmeldung weitergehen, wenn die Anwendungsschaltung versucht, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.ignore -begin- Ist diese Einstellung aktiv, wird die Benutzung aller ausgeschalteten Features ignoriert; es werden keine Fehlermeldungen angezeigt. -end- ho.opt.html.browser -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zu einer HTML-Datei klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.html.email -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zum Senden einer e-mail klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.fsave -begin- Sichere die TkGate-internen Zellen mit den Schaltungsdaten. Dies erhöht die Dateigröße um ca. 20%, führt aber zu Sicherungsdateien, die zur Verwendung mit Drittanbietertools exportiert werden können. -end- ho.opt.sorttraces -begin- Ist diese Option eingeschaltet, werden die Signale im Scope-Fenster in sortierter Form angezeigt. Ist sie ausgeschaltet, werden die Signale im Scopefenster in der Reihenfolge der Probe-Setzungen angezeigt. -end- ho.opt.sim.noglitch -begin- Ist diese Option aktiv, so bewirken sich schnell verändernde Signale am Eingang eines Gatters am Ausgang desselben im wesentlichen das zeitverschobene Eingangssignal. Dies kann flüchtige Ereignisse und Schwingungen in sequentiellen Schaltungen auf Gatterebene verhindern helfen. -end- ho.opt.sim.savetraces -begin- Tastköpfe, die während eines Simulationslaufes plaziert wurden, werden abgespeichert und beim Neustart der Simulation wieder richtig gesetzt. -end- ho.opt.sim.tech -begin- Dateienliste zum Laden als potentielle "Technologie"-Dateien. Technologie-Dateien legen Verzögerungen und Flächengrößen für eingebaute Gatter fest. -end- ho.opt.sim.err -begin- Wähle, wie Warnungen vom Simulator behandelt werden sollen. -end- ho.opt.sim.err.stopany -begin- Gibt es irgendwelche Warnungen zu der Schaltung, wird sie nicht simuliert, auch nicht, falls es gar keine wirklichen Fehler gibt. -end- ho.opt.sim.err.showall -begin- Ziege immer Warnunge zu der Schaltung, auch wenn es keine Fehler gibt. Falls nur Warnungen existieren, wird der Simulator gestartet und die Warnungen in einem gesonderten Fenster angezeigt. -end- ho.opt.sim.err.showiferr -begin- Zeige Warnungen nur, wenn es auch Fehler in der Schaltung gibt. Enthält eine Schaltung nur Warnungen, so werden sie ignoriert und der Simulator wird geräuschlos gestartet. -end- ho.opt.sim.err.ignore -begin- Zeige nie Warnmeldungen, auch nicht, falls es Fehler in der Schaltung gibt. -end- ho.opt.lib.vpath -begin- Liste von Verzeichnissen, in denen nach TkGate Bibliotheksdateien gesucht wird. Bibliotheken sollten eine .v Dateierweiterung besitzen und Module enthalten, die für den Gebrauch in Anwendungsschaltungen nützlich sind. -end- ho.opt.lib.vlib -begin- Die Bibliotheksliste, die automatisch geladen wird, wenn TkGate startet. -end- ho.opt.lib.vpd -begin- Liste von Verzeichnissen, in denen nach virtuellen peripheren Geräten (VPDs) gesucht wird. Virtuelle periphere Geräte haben eine .tcl Dateierweiterung und implementieren typischerweise ein GUI, das das periphere Gerät repräsentiert und das von einer benutzerschaltung gesteuert wird. -end- ho.opt.undolen -begin- Maximale Zahl der aufzuhebenden Undo-Aktionen. -end- ho.opt.name -begin- Benutzername, der auf allen von TkGate produzierten Reports, z.B. Schaltungs- ausdrucken, aufgeführt wird. -end- ho.opt.site -begin- Der Netzname der Organisation, in der TKGate installiert ist. Dieser Name wird auf jedem Ausdruck (oder in der Postscript-Datei) ausgegeben. -end- ho.opt.smooth -begin- Falls diese Option eingestellt ist, wird Scrollen mittels Bitmap-Kopien realisiert statt das Bild immer neu zu zeichnen. Dies kann ausgeschaltet werden, falls Probleme mit dem X-Server auftreten. -end- ho.opt.clip -begin- Ist diese Option eingeschaltet, wird Clipping benutzt, um den dargestellten Teil des Fensters beim Neuaufbau zu zeichnen. Sonst wird das ganze Display für alle Teile neu gezeichnet. -end- ho.opt.showimage -begin- Durch Zurücksetzen dieser Option kann die Anzeige des Bildes un der erläuternde Text am Rand der Dialogboxen unterdrückt werden. -end- ho.opt.outmove -begin- Ist diese Option eingeschaltet, wird nur der Umriß der bewegten Modulinstanzen beim Verschieben angezeigt. Diese Einstellung ist nur auf Maschinen mit langsamen Displays nötig. -end- ho.opt.bhelp -begin- Bei Aktivierung dieser Option werden Hilfehinweise angezeigt. Sie zeigen Tips an, wenn die Maus sich gerade über einem Baustein befindet. -end- ho.opt.novice -begin- Falls auf der Kommandozeile keine andere Schaltung angegeben ist, wird ein TkGate- Tutorial als erste Schaltung beim Start angezeigt. -end- ho.opt.blockDropConnect -begin- Dies Option erlaubt die Erzeugung von Ports bei Modulschnittstellen, indem freie Leitungen neben einer Kante fallengelassen werden. -end- ho.opt.debug -begin- Einschalten mehrerer Debugging Features. Nur interessant für TKGate-Entwickler. -end- ho.opt.ckpt Einschalten des Checkpointing nicht gespeicherter Schaltungen. ho.opt.ckptfreq Anzahl der Checkpoints pro Sekunde. ho.opt.beak -begin- Freischalten dieser total nutzlosen Features. Falls dies ausgeschaltet wird, erscheinen diese Modi (und diese Checkbox) nicht mehr im Optionsfenster. Der einzige Weg, sie wiederzubekommen, geht über das Editieren der .tkgate-properties Datei. -end- ho.opt.miles -begin- Ist dieser Modus eingeschaltet, wird TkGate periodisch die Intelligenz des Benutzers anzweifeln. -end- ho.opt.bat -begin- Falls dieser Modus eingeschaltet ist, wird TkGate eine Entwicklungsumgebung für einen Bat-Computer einrichten. -end- ho.opt.trek Beam me up Scotty! ho.opt.simstep -begin- Die Anzahl der Epochen, die bei einem Schritt-Kommando vorangeschritten wird. -end- ho.opt.ckstep -begin- Die Anzahl der Taktzyklen, die vorangeschritten wird, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.ckover -begin- Die Anzahl der Epochen nach der Anstiegsflanke des Taktes, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.vpopupdelay -begin- Die Verzögerung in Millisekunden zwischen Drücken und Halten der Maustaste und der Anzeige eines Signalwerts. Auf einigen Systemen interferieren kurze Verzögerungs- zeiten mit der Fähigkeit, einen Doppelklick zu erkennen. Liegt dieser Fall vor, so ist der Wert zu erhöhen. Es sind Werte zwischen 1 und 10000 erlaubt. -end- ho.opt.init -begin- Eine Simulationsskript-Datei, die automatisch ausgeführt wird, wenn die Simulation gestartet wird. -end- ho.opt.ckall -begin- Falls diese Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation bei der positiven Flanke jeder Taktquelle in der Schaltung an. -end- ho.opt.ckspec -begin- Falls dieser Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation nur an der positiven Flanke der spezifizierten Taktquelle an. -end- ho.opt.keybind -begin- Legt den Stil für Tastenbindungen fest. Wird diese Option geändert, werden die Bindungen sofort aufge- frischt. Allerdings muß TkGate neu gestartet werden, damit irgendwelche benutzerdefinierten Tastaturbindungen zu sehen sind. -end- ho.deftech -begin- Standard-Technologie für neue Gatter. Beeinflußt die Verzögerungszeit der Gatter. Um die Technologie eines bestimmten Gatters zu ändern, öffnet mann die Eigenschafts-Box mit Doppelklick und wählt "Delay" an. -end- ho.techbut -begin- Benutze Verzögerungszeiten aus der Datei zur Definition der Standard Technologie. Um eigene Technologien zu entwickeln, füge man sie zu der Liste im "Datei -> Optionen -> Simulation"-Menu hinzu. -end- ho.custbut -begin- Setze eigene Verzögerungszeitwerte für dieses Gatter. -end- ho.contver -begin- Verifiziere die Integrität der internen Datenstrukturen nach jeder Operation. -end- ho.simwatch -begin- Zeige Kommandos an, die zwischen GUI und Simulator gesendet werden. -end- ho.symed.point -begin- Pixel-Editiermodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.line -begin- Geraden-Modus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.rect -begin- Rechteckmodus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.fillrect -begin- Ausgefüllter Rechteckmodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.select -begin- Bitmap Auswahlmodus. Die linke Maustaste wählt Bereiche der Bitmap aus. Auf der Auswahl können dann Cut und Paste Operationen vorgenommen werden. -end- ho.symed.port -begin- Portauswahlmodus. Wähle Ports aus, bewege sie oder rotiere sie. -end- ho.symed.rshift Ausgewählte Pixel rechtsverschieben. ho.symed.lshift Ausgewählte Pixel linksverschieben. ho.symed.ushift Ausgewählte Pixel nach oben verschieben. ho.symed.dshift Ausgewählte Pixel nach unten verschieben. ho.symed.cwrotate Ausgewählte Pixel rechts drehen. ho.symed.ccwrotate Ausgewählte Pixel links drehen. ho.symed.autobold Das ausgewählte Bild fett machen. ho.symed.resize Den Bildeditor in der Größe ändern. ho.symed.import Bild aus einer Datei importieren. ho.symed.export Bild in eine Datei exportieren. ho.tool.currot -begin- Zeigt aktuelle Vorgabe des Rotationswinkels an. Ändern durch Klick auf diese Taste. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotieren der ausgewählten Gatter gegen den Uhrzeigersinn. ho.tool.brotate Rotieren der ausgewählten Gatter mit dem Uhrzeigersinn. ho.tool.valgn Ausgewählte Gatter vertikal ausrichten. ho.tool.halgn Ausgewählte Gatter horizontal ausrichten. ho.tool.cut Ausschneiden des ausgewählten Teils. ho.tool.copy Kopieren des ausgewählten Teils.. ho.tool.paste Einfügen aus dem Cut-Puffer. ho.tool.find Gatter, Leitungen oder Text suchen (und finden). ho.tool.addport Zum ausgewählten Gatter einen Port hinzufügen. ho.tool.anchor Die ausgewählten Gatter verankern. ho.tool.unanchor Die ausgewählten Gatter loslassen. ho.tool.replicate Replizierung eines Gatters. ho.tool.delete Löschen der Auswahl. tkgate-2.0-b10/locale/de/messages000644 001751 001751 00000272471 11150625613 017404 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by bartke Tue Feb 24 00:04:27 CET 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## \font-encoding iso8859-1 \messages-encoding utf-8 \verilog-encoding iso8859-1 \postscript-encoding iso8859-1 \display-encoding iso8859-1 \language German ############################################################################## # # basic strings # b.new Neu... b.dismiss Beenden b.close Schließen b.ok OK b.clear Clear b.cancel Abbrechen #b.open Öffnen... #b.bitw Bitbreite b.in Eingang b.out Ausgang b.inout Bidirektional b.browse Durchsuchen... b.label Marke b.find Suchen b.edit Editieren... b.add Hinzufügen... b.delete Löschen #b.deleteb Löschen... b.remove Entfernen b.apply Anwenden b.anchor Anker b.tech Technologie #b.enable Freischalten #b.disable Sperren #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Editieren tab.editintr Schnittstelle tab.simulate Simulieren tab.cpath Kritischer Pfad ############################################################################ # # Module tabs # module.tree Baum module.list Liste module.box.libraries Bibliotheken ############################################################################ # # Tabs for Nets/Ports # sidetab.nets Netze sidetab.ports Ports ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Hinzufügen... mm.delete Löschen mm.edit Editieren... mm.enable Freischalten mm.disable Sperren ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:Datei menu.edit 0:Editieren menu.tool 0:Werkzeug menu.symbol 0:Symbol menu.simulate 0:Simulieren menu.module 0:Modul menu.interface 0:Schnittstelle menu.format 0:Gatter menu.make 0:Bausteine menu.help 0:Hilfe menu.file.new 0:Neu... menu.file.open 1:Öffnen... menu.file.openlib 3:Bibliotheksmanager... menu.file.save 0:Sichern menu.file.saveas 8:Sichern unter... menu.file.print 0:Drucken... menu.file.quit 0:Quit menu.file.cprop 10:Schaltungseigenschaften... menu.file.import 0:Bild Import... menu.file.export 0:Bild Export... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Trennen menu.edit.copy 0:Kopieren menu.edit.paste 0:Einfügen menu.edit.overlay 1:Overlay einfügen menu.edit.selall 1:Alles auswählen menu.edit.find 0:Suchen... menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 16:Bitverschiebung Rechts menu.edit.lshift 16:Bitverschiebung Links menu.edit.ushift 16:Bitverschiebung Auf menu.edit.dshift 17:Bitverschiebung Ab menu.edit.cwrotate 11:Bitrotieren rechts menu.edit.ccwrotate 15:Bitrotieren links menu.edit.pcwrotate 12:Portrotieren rechts menu.edit.pccwrotate 16:Portrotieren links menu.edit.autobold Bits fett anzeigen menu.edit.resize Bitmapgröße anpassen menu.tool.move 0:Bewegen/Verbinden menu.tool.delg 0:Gatter löschen menu.tool.cutw 0:Leitung trennen menu.tool.inv 0:Invertieren menu.tool.bitw 0:Bitbreite menu.tool.debug 0:Debug menu.tool.point 0:Punkt menu.tool.line 0:Gerade menu.tool.rect 0:Rechteck menu.tool.fillrect 0:Rechteck füllen menu.tool.port 0:Port menu.tool.select 0:Gebiet auswählen menu.tool.options 0:Optionen... menu.format.addport 4:Port hinzufügen menu.format.ioset 0:Typ setzen menu.format.anchor 0:Verankern (ausgewählt) menu.format.unanchor 0:Anker los (ausgewählt) menu.format.prop 0:Instanzeigenschaften... menu.format.del 0:Löschen menu.format.settech 0:Technologie festlegen menu.format.rot 0:Rotation menu.format.rot.0 15:Default Drehen 0 menu.format.rot.90 15:Default Drehen 90 menu.format.rot.180 15:Default Drehen 180 menu.format.rot.270 15:Default Drehen 270 menu.format.rot.rotate 0:Uhrzeigersinn drehen menu.format.rot.brotate 0:Gegenuhrzeigersinn drehen menu.format.algnv 11:Ausrichten Ver. menu.format.algnh 11:Ausrichten Hor. menu.tool.tclshell 0:Tcl Shell menu.tool.rep 0:Replizieren menu.simulate.begin 0:Beginn Simulation menu.simulate.end 0:Ende Simulation menu.simulate.addprobe 0:Tastkopf hinzufügen/löschen menu.simulate.run 0:Laufen lassen menu.simulate.pause 0:Pause menu.simulate.step 0:Epochenschritt(e) menu.simulate.cycle 5:Periodenschritt(e) menu.simulate.break 0:Haltepunkt... menu.simulate.script 1:Skript ausführen... menu.simulate.load 16:Speicherbereich laden... menu.simulate.dump 16:Speicherbereich ausgeben... menu.simulate.view 0:Ansehen Speicherauszug... menu.module.open 0:Öffnen menu.module.close 0:Schließen menu.module.new 0:Neu... menu.module.del 0:Löschen... menu.module.copy 0:Kopieren... menu.module.rename 0:Umbenennen... menu.module.claim 1:Aneignen... menu.module.setroot 1:Zur Wurzel machen... menu.module.prop 0:Eigenschaften... menu.module.interface 0:Schnittstelle menu.module.interface.set 0:Definieren menu.module.interface.update 0:Mit Standard synchr. menu.module.interface.updateall 0:Alles mit Std. synchr... menu.module.interface.edit 0:Editieren... menu.module.interface.auto 1:Automatisch erzeugen... menu.help.about 0:Autor... menu.help.license 0:Lizenz... menu.help.doc 0:Dokumentation... menu.help.tut 0:Tutorien menu.help.home 0:Startseite menu.help.example 0:Beispiele ############################################################################# # Scope Menu # menu.scope_file 0:Datei menu.scope_sim 0:Simulieren menu.scope_trace 0:Signaldiagramm menu.scope_help 0:Hilfe menu.scope_file.ptrace 0:Drucken Signaldiagramm... menu.scope_file.close 0:Schließen menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Tastkopf hinzufügen/löschen menu.scope_sim.run 0:Laufen lassen menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Epochenschritt(e) menu.scope_sim.cycle 5:Periodenschritt(e) menu.scope_sim.break 0:Haltepunkt... menu.scope_sim.script 1:Skript ausführen... menu.scope_sim.load 16:Speicherbereich laden... menu.scope_sim.dump 16:Speicherbereich ausgeben... menu.scope_help.about 0:Autor... menu.scope_help.license 0:Lizenz... menu.scope_help.doc 0:Dokumentation... mod.intf Schnittstelle port.title TkGate: Porteigenschaften port.parms Portparameter port.in Eingang port.out Ausgang port.inout Ein/Ausgang ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gatter gm.rgate Reduktion gm.msi MSI gm.alu ALU gm.mem Speicher gm.mod Module gm.comment Kommentar gm.script Verilogskript gm.frame Rahmen gm.io.switch Schalter gm.io.dip DIP Schalter gm.io.ground Masse gm.io.vdd Vdd gm.io.merge Zusammenführen gm.io.clock Taktgeber gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direkt) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Puffer gm.gate.inv Inverter gm.gate.tribuf Tri-Puffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Addierer gm.alu.mult Multiplizierer gm.alu.div Dividierer gm.alu.lshift Linksshift gm.alu.rshift Rechtsshift gm.alu.arshift Arith. Rechtsshift gm.alu.roll Zyklischer Shift gm.mem.reg Register gm.mem.ff D-Flipflop gm.mem.rff Rev. D-Flipflop gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK Flipflop gm.mem.rjkff Rev. JK Flipflop gm.msi.21mux 2-1 Multiplexer gm.msi.41mux 4-1 Multiplexer gm.msi.81mux 8-1 Multiplexer gm.msi.12dec 1-2 Dekoder gm.msi.14dec 1-4 Dekoder gm.msi.18dec 1-8 Dekoder gm.msi.12demux 1-2 Demultiplexer gm.msi.14demux 1-4 Demultiplexer gm.msi.18demux 1-8 Demultiplexer gm.mod.inst Module Instanz gm.mod.in Module Eingang gm.mod.out Module Ausgang gm.mod.inout Module Ein/Ausgang tutorial.prev ZURÃœCK tutorial.next WEITER tutorial.chapter INHALTSVERZEICHNIS tutorial.reload NEU LADEN ############################################################################## # # Popup menus # pop.make Bausteine pop.tool Werkzeug pop.edit.paste Einfügen pop.edit.cut Trennen pop.edit.copy Kopieren pop.port.in Eingang pop.port.out Ausgang pop.port.inout Ein/Ausgang pop.wire.addseg Leitungssegment hinzufügen pop.wire.prop Schaltungseigenschaften... pop.wire.hidesize Bitbreite verstecken pop.wire.showsize Bitbreite anzeigen pop.wire.hidelabel Namen verstecken pop.wire.hidealllabel Alle Namen verstecken pop.wire.clearalllabel Alle Namen löschen pop.wire.showlabel Namen anzeigen pop.gate.open Öffnen pop.gate.close Schließen pop.gate.prop Instanzeigenschaften... pop.gate.addport Port hinzufügen pop.gate.addin Eingang hinzufügen... pop.gate.addout Ausgang hinzufügen... pop.gate.addinout Ein/Ausgang hinzufügen... pop.gate.anchor Verankern/Loslösen pop.gate.settech Technologie festlegen pop.gate.delete Löschen pop.gate.ioset Typ festlegen pop.module.new Neu... pop.module.del Löschen... pop.module.copy Kopieren... pop.module.rename Umbenennen... pop.module.claim Aneignen... pop.module.setroot Als Wurzel festlegen... pop.module.prop Moduleigenschaften... pop.module.int Schnittstelle editieren... pop.simulate.end Ende Simulation pop.simulate.begin BeginN Simulation pop.simulate.addprobe Tastkopf hinzufügen pop.simulate.delprobe Tastkopf löschen pop.simulate.run Laufen lassen pop.simulate.pause Pause pop.simulate.step Epochenschritt(e) pop.simulate.cycle Periodenschritt(e) pop.simulate.break Haltepunkt... pop.simulate.script Skript ausführen... pop.simulate.load Speicherbereich laden... pop.simulate.dump Speicherbereich ausgeben... pop.simulate.view Ansehen Speicherauszug... pop.interface Schnittstelle pop.interface.set Als Standard setzen pop.interface.update Abgleichen mit Standard pop.interface.updateall Alles abgleichen mit Standard... pop.interface.edit Editieren... pop.interface.auto Automatisch erzeugen... pop.interface.replace Ersetzen pop.igen.type Typ pop.igen.side Seite pop.igen.size Größe pop.igen.delete Löschen pop.igen.in Eingang pop.igen.out Ausgang pop.igen.inout Ein/Ausgang pop.igen.left links pop.igen.right rechts pop.igen.top oben pop.igen.bottom unten pop.igen.other sonstige pop.library.mgr Bibliotheksmanager... pop.library.close Schließen ############################################################################## # # Symbol editor strings # #symed.bsave Speichern #symed.file Datei #symed.file.load Bitmap laden... #symed.file.save Bitmap sichern... #symed.file.updateclose Auffrischen und schließen #symed.file.discardclose Verwerfen und schließen #symed.help Hilfe #symed.help.about Zu... #symed.edit Editieren #symed.edit.cut Trennen #symed.edit.copy Kopieren #symed.edit.paste Einfügen #symed.edit.overlay Overlay einfügen #symed.edit.rclock Rechts drehen #symed.edit.rcclock Links drehen #symed.module Modul #symed.modes Modes #symed.cutpaste Ausschneiden/Einfügen #symed.rotate Port drehen #symed.zoom Zoom #symed.cancel Abbrechen #symed.update Auffrischen symed.tab.normal Nicht ausgewählt symed.tab.select Ausgewählt symed.link Ausgewähltes mit Unausgewähltem verlinken # width of symbol editor tabs scope.title TkGate: Scope ############################################################################## ### memory viewer # memview.title Speicherauszug memview.exp -fillbegin- Ansehen und Modifizieren des Speicherinhalts von RAM oder ROM. Zum Ändern des Speicherinhalts wähle die Speicherseite aus und gib dann neue Hex-Werte ein. -end- ############################################################################## scope.emptymsg Doppelklick auf eine Leitung fügt ein Signal ein oder löscht es comment.empty [Text hinzufügen mit Doppelklick.] ############################################################################## # Interface strings # ifile Datei imodule Modul iblmodule Module iports Ports ibits Bits: itype Typ: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file Dateiname db.mod.type Typ db.mod.flags Flags db.mod.dataprot Editieren der Moduldefinition verhindern. db.mod.intfprot Schnittstellenveränderungen verhindern. db.mod.edprot Schnittstellenveränderungen im Editiermodus verhindern. db.mod.props Eigenschaften db.mod.inuse.0 Modul wird nicht benutzt. db.mod.inuse.1 Modul wird benutzt. db.mod.lmod.0 Modul seit dem Laden nicht verändert. db.mod.lmod.1 Modul seit dem Laden verändert. db.mod.smod.0 Modul seit dem Sichern nicht verändert. db.mod.smod.1 Modul seit dem Sichern verändert. db.mod.islib.1 Modul ist Teil der [%s] Bibliothek. db.mod.islib.0 Modul ist kein Bibliotheksmodul. db.mod.netlist Bauteilliste db.mod.hdl HDL db.mod.netexpl -begin- Moduldefinition mit einem graphischen Editor, um Leitungen zwischen Komponenten zu ziehen -end- db.mod.hdlexpl -begin- Moduldefinition mit einem Texteditor, um das Verhalten in Verilog zu beschreiben. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Fehlerliste db.err.caption Fehlerliste db.err.explain.warn -fillbegin- In der Schaltung gab es Warnhinweise, die Simulation wird aber fortgesetzt. Im Editiermodus kann man die Warnhinweise sehen. -end- db.err.explain.err -fillbegin- In der Schaltung gab es Fehler. TkGate kann die Simulation nicht fortsetzen. -end- db.err.neededit -fillbegin- Zum Navigieren zu den Warnungen muß erst in den Editiermodus geschaltet werden. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Netzeigenschaften db.net.caption Netzeigenschaften db.net.name Netzname db.net.hide Name verstecken db.net.bits Bitbreite db.net.type Netztyp db.net.port Porttyp db.net.in Eingang db.net.out Ausgang db.net.inout Ein/Ausgang db.net.inets Netze ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: Neue Schaltung db.newcirc.directory Verzeichnis: db.newcirc.cap Neue Schaltung db.newcirc.exp -fillbegin- Die aktuelle Schaltung verwerfen und eine neue Schaltung bearbeiten. -end- db.newcirc.file Dateiname db.newcirc.topname Name des obersten Moduls ############################################################################## # Gate dialog box # db.gate.title TKGate: Gattereigenschaften db.gate.signam Signalname db.gate.portnam Portname db.gate.iotype Typ db.gate.bitw Bitbreite db.gate.cyclew Taktlänge db.gate.phase Phase db.gate.duty Taktverhältnis db.gate.waveform Takt-Signalform db.gate.port Port db.gate.bitws Bits db.gate.side Seite db.gate.gtype Gattertyp db.gate.gname Gattername db.gate.hidenam Namen verstecken db.gate.anchor Verankern db.gate.cpbreak Aufteilung des kritischen Pfades db.gate.butstate Schalterzustand db.gate.dipval Schalterstellung db.gate.range Bitbereich db.gate.memfilenam Dateiname f. Speicherinhalt db.gate.modname TyP db.gate.general Allgemein db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Verzögerung db.gate.parameters Parameter db.gate.stddelay Standardverzögerung db.gate.custdelay Einstellen der Verzögerung db.gate.catdiruse Platzieren des Ports db.gate.edit Editieren db.gate.delete Löschen db.gate.add Hinzufügen db.gate.ff.type D-Flipflop Ausrichtung db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- Datenfluß im D-Flipflop von links nach rechts. -end- db.gate.ff.reverse.hdr Umgekehrt db.gate.ff.reverse.exp -fillbegin- Datenfluß im D-Flipflop von rechts nach links. -end- db.gate.jkff.type JK Flipflop Ausrichtung db.gate.jkff.normal.hdr Normal db.gate.jkff.normal.exp -fillbegin- Datenfluß im JK-Flipflop von links nach rechts. -end- db.gate.jkff.reverse.hdr Reversed db.gate.jkff.reverse.exp -fillbegin- Datenfluß im JK-Flipflop von rechts nach links. -end- db.gate.cat.asc.hdr Aufsteigend db.gate.cat.dec.hdr Absteigend db.gate.cat.asc.exp -fillbegin- Bits werden in aufsteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.dec.exp -fillbegin- Bits werden in absteigender Ordnung von oben nach unten zusammengeführt. -end- db.gate.cat.sigdir Signalrichtung db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Mehrfacheingang db.gate.cat.singin.hdr Einzelner Eingang db.gate.cat.tran.hdr Bidirektional db.gate.cat.auto.exp -fillbegin- Die Signalrichtung wird automatisch aus den verbundenen Teilschaltungen erschlossen. -end- db.gate.cat.multin.exp -fillbegin- Die Seite mit Mehrfachleitung wird immer als Eingang angenommen. -end- db.gate.cat.singin.exp -fillbegin- Die Seite mit der Einzelleitung wird immer als Eingang angenommen. -end- db.gate.cat.tran.exp -fillbegin- Bidirektionaler Signalfluß (transmission) ist erlaubt. Kann nicht mit Schaltern oder Registern verbunden werden. -end- # Minimum size of textbox for comment (in characters) # @db.gate.comment.width *500 @db.gate.comment.height *450 db.gate.tab.General.cap Allgemeine Eigenschaften db.gate.tab.Ports.cap Porteigenschaften db.gate.tab.Delay.cap Eigenschaften der Verzögerung db.gate.tab.Parameters.cap Modulparameter db.gate.tab.CLOCK.cap Takteigenschaften db.gate.tab.SWITCH.cap Schaltereigenschaften db.gate.tab.DIP.cap DIP Eigenschaften db.gate.tab.TAP.cap Tran Eigenschaften db.gate.tab.RAM.cap RAM Eigenschaften db.gate.tab.ROM.cap ROM Eigenschaften db.gate.tab.MODULE.cap Moduleigenschaften db.gate.tab.FRAME.cap Rahmeneigenschaften db.gate.tab.LED.cap LED Eigenschaften db.gate.tab.AND.cap AND Eigenschaften db.gate.tab.OR.cap OR Eigenschaften db.gate.tab.XOR.cap XOR Eigenschaften db.gate.tab.MUX.cap Mux Eigenschaften db.gate.tab.DEMUX.cap Demux Eigenschaften db.gate.tab.DECODER.cap Decoder Eigenschaften db.gate.tab.CONCAT.cap Concat Eigenschaften db.gate.tab.COMMENT.cap Text Eigenschaften db.gate.tab.FF.cap D-Flipflop Eigenschaften db.gate.tab.JKFF.cap JK-Flipflop Eigenschaften db.gate.tab.SCRIPT.cap Verilogskript db.gate.tab.General.exp -fillbegin- Die grundlegenden Eigenschaften einer Instanz ansehen und verändern. -end- db.gate.tab.Ports.exp -fillbegin- Hinzufügen, Editieren oder Löschen von Ports einer Instanz. -end- db.gate.tab.Delay.exp -fillbegin- Die Verzögerung kann entweder durch Angabe der Technologie oder durch spezielle Werte für diese Instanz festgelegt werden. -end- db.gate.tab.Parameters.exp -fillbegin- Festlegen der Modulparameter dieser Modulinstanz, falls welche definiert sind. Modulparameter werden zur Definition von Verzögerungen und konstanten Werten in Moduln verwendet. -end- db.gate.tab.details.exp -fillbegin- Genaue Festlegung der typspezifischen Eigenschaften eines Gatters. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.JKFF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Festlegung des Textes für einen Kommentar. In beschränktem Umfang können HTML Tags einschließlich Links verwendet werden. -end- db.gate.tab.SCRIPT.exp -fillbegin- Hier kann zum Modul ein Stück beliebig formatierter Verilog-Quellcode hinzugefügt werden. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Wert db.gate.mparm.exampleA -begin- Dieses Modul hat keinerlei Parameter. Parameter können zu Verilog-Textmodulen hinzugefügt werden. Der Wert jedes Parameters kann für jede Instanz durch diese Dialogbox konfiguriert werden. Modul- Parameter werden als geklammerte Liste deklariert, die mit einem # beginnt. Hier ist ein Beispiel einer Moduldeklaration mit einem Parameter namens "base_value", der einen Standardwert von 1'b1 besitzt. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.switch.state Initiale Schalterstellung db.gate.switch.state.on.hdr Schalter Ein db.gate.switch.state.on.exp Schalter beginnt Simulation im Ein-Zustand. db.gate.switch.state.off.hdr Schalter Aus db.gate.switch.state.off.exp Schalter beginnt Simulation im Aus-Zustand. db.gate.switch.shownet Zeige den Netznamen an db.gate.switch.shownet.on.hdr Zeigen db.gate.switch.shownet.on.exp Zeige den Netznamen direkt neben dem Schalter an. db.gate.switch.shownet.off.hdr Verstecken db.gate.switch.shownet.off.exp Zeige keinen Netznamen neben dem Schalter an. db.gate.dip.value Initialer DIP-Schalter-Wert db.gate.dip.value.exp Initialer Wert des DIP-Schalters zu Simulationsbeginn. db.gate.dip.value.hex Hexwert: @db.gate.dip.value.exp.width 150 db.gate.dip.shownet Zeige den Netznamen db.gate.dip.shownet.on.hdr Zeigen db.gate.dip.shownet.on.exp Zeige den Namen des Netzes neben dem DIP-Schalter an. db.gate.dip.shownet.off.hdr Verstecken db.gate.dip.shownet.off.exp Zeige keinen Netznamen neben dem DIP-Schalter an. db.gate.tap.select Auswahl der Bitverzweigung db.gate.tap.exp.bit Wähle das Bit aus, das aus dem Multibit-Bus herausgeführt werden soll. db.gate.tap.exp.bus Wähle das niederwertigste Bit (LSB) aus dem Bitbereich und führe es aus dem Multibit-Bus heraus. db.gate.tap.lbl.bit Bit: db.gate.tap.lbl.bus LSB: @db.gate.tap.exp.width *180 db.gate.mux.dataorder Eingangsordnung db.gate.mux.ord1.hdr Links-rechts db.gate.mux.ord2.hdr Rechts-links db.gate.mux.ord1.exp -fillbegin- Ordne MUX-Eingänge von links nach rechts. -end- db.gate.mux.ord2.exp -fillbegin- Ordne MUX-Eingänge von rechts nach links. -end- db.gate.mux.select Auswahlstil db.gate.mux.sel1.hdr Selektor links db.gate.mux.sel2.hdr Selektor rechts db.gate.mux.sel1.exp -fillbegin- Setze den Datenselektor auf der linken Seite des Gatters. -end- db.gate.mux.sel2.exp -fillbegin- Setze den Datenselektor auf der rechten Seite des Gatters. -end- db.gate.demux.dataorder Ausgangsordnung db.gate.demux.ord1.hdr Links-rechts db.gate.demux.ord2.hdr Rechts-links db.gate.demux.ord1.exp -fillbegin- Ordne DEMUX-Ausgänge von links nach rechts. -end- db.gate.demux.ord2.exp -fillbegin- Ordne DEMUX-Ausgänge von rechts nach links. -end- db.gate.demux.select Wähle die Positionierung db.gate.demux.sel1.hdr Auf der Linken db.gate.demux.sel2.hdr Auf der Rechten db.gate.demux.sel1.exp -fillbegin- Plaziere den Select-Eingang auf der linken Seite des DEMUX. -end- db.gate.demux.sel2.exp -fillbegin- Plaziere den Select-Eingang auf der rechten Seite des DEMUX. -end- db.gate.decoder.dataorder Ausgangsreihenfolge db.gate.decoder.ord1.hdr Links-nach-rechts db.gate.decoder.ord2.hdr Rechts-nach-links db.gate.decoder.ord1.exp -fillbegin- Ordne die Decoderausgänge von links nach rechts. -end- db.gate.decoder.ord2.exp -fillbegin- Ordne die Decoderausgänge von rechts nach links. -end- db.gate.decoder.select Plazierung des Enable-Eingangs db.gate.decoder.sel1.hdr Links db.gate.decoder.sel2.hdr Rechts db.gate.decoder.sel1.exp -fillbegin- Plaziere den Enable-Eingang auf der linken DECODER-Seite. -end- db.gate.decoder.sel2.exp -fillbegin- Plaziere den Enable-Eingang auf der rechten DECODER-Seite. -end- db.gate.aox.extbaruse Nutzung von Erweiterungsbalken db.gate.aox.use.hdr Erweiterungsbalken db.gate.aox.nouse.hdr Keine Erweiterungsbalken db.gate.aox.use.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden diese an Erweiterungsbalken angebracht. -end- db.gate.aox.nouse.exp -fillbegin- Beim Hinzufügen von Eingängen an Grundgattern (AND, OR, etc.) werden keine Erweiterungsbalken verwendet. -end- db.gate.led.type LED Typ db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Balkenanzeige db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direkt) db.gate.led.bit.exp -fillbegin- Einzelne LED-Anzeige für 1-Bit-Signale. -end- db.gate.led.bar.exp -fillbegin- LED Balkenanzeige mit einem Balken pro Bit. -end- db.gate.led.hex.exp -fillbegin- Hexadezimale Anzeige des Signals. -end- db.gate.led.dec.exp -fillbegin- Dezimale Anzeige des Signals. -end- db.gate.led.seg.exp -fillbegin- Die Signalbits steuern direkt die LED-Segmente a-g. -end- db.seq.back db.hdl.namechange.title HDL Modulname geändert db.hdl.textdisp.title HDL Textdisposition db.hdl.savecap Mehrfach-Module db.hdl.saveexp -fillbegin- Der Textpuffer des gerade editierten Moduls enthält mehr als eine Moduldefinition. Bitte wähle eine der drei Aktionen auf der rechten Seite aus. -end- db.hdl.autoedit Auto-Editieren db.hdl.split Aufteilen db.hdl.comment Kommentar db.hdl.cancel Abbrechen db.hdl.ignore Ignorieren db.hdl.autoeditcap Der Name paßt nicht db.hdl.autoeditexp -fillbegin- Die Textbeschreibung des Moduls paßt nicht zum erwarteten Namen. Wähle eine der Optionen rechts, um dieses Problem zu beseitigen. -end- db.dip.title TkGate: Dip-Wert cpath.cloops -fillbegin- In der kombinatorischen Schaltung wurde eine Rückkopplung entdeckt. Um für diese Schaltung eine Verzögerungsanalyse durchführen zu können, muß entweder die Rückkopplung aufgebrochen werden oder einige der Gatter im Rückkopplungszweig werden als "Kritische-Pfad-Aufteilung" markiert. Schaltungsteile, in denen eine Rückkopplung ent- deckt wurde, sind unten gelistet. -end- ############################################################################## # Print dialog box # #print.outto Ausgabe nach print.title TkGate: Drucken print.config.title TkGate: Druckerkonfiguration print.scope.title TkGate: Scopedruck print.printer Drucker: print.file Datei print.prcmd Druckbefehl: print.prname Drucker print.advanced Erweitert... print.filename Dateiname print.epssave Sichern als Encapsulated Postscript. #print.doctit Dokumenttitel #print.prmod Druck von Modulen print.epcm Epochen/cm print.estpg Ungefähre Seitenzahl print.all Alles print.cur Aktuelle print.use Benutzte print.sel Ausgewählte print.inclib Bibliotheksmodule einbeziehen. print.incunused Unbenutzte Module einfügen. print.papsz Papiergröße print.orient Orientierung print.portrait Hochformat print.landscape Querformat print.2side Duplexdruck print.opts Optionen print.scale Anpassen großer Module auf eine Seite. print.partition Aufteilen großer Module auf mehrere Seiten. print.incidx Index hinzufügen. print.incgraph Hierarchiegraph hinzufügen. print.4up Kleine Module: vier auf eine Seite drucken. print.rangeselection Wahl des Bereichs print.scaleselect Wahl der Skalierung print.fulltr Vollständiges Signaldiagramm print.parttr Ausschnitt aus dem Signaldiagramm print.start Start print.range Bereich print.linelen Zeilenlänge print.filesel Ausgabe in Datei print.printersel Ausgabe auf Drucker print.defaultprinter Standarddrucker print.pageset Seiteneinstellungen print.modulesel Modulauswahl ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Drucken print.printtrace.cap Signaldiagramm drucken print.printcirc.cap Schaltung drucken print.printcirc.out.exp -fillbegin- Wahl der Druckausgabe: direkt zum Drucker oder in eine PostScript-Datei. -end- print.printcirc.page.exp -fillbegin- Auswahl der Optionen für den Seitenaufbau und den Drucker. -end- print.printcirc.mod.exp -fillbegin- Auswahl der zu druckenden Module, Einstellung der Optionen für die Darstellung. -end- print.printtrace.trace.exp -fillbegin- Auswahl des Zeitbereichs für die Ausgabe und Einstellung der Skalierung, um die ungefähre Seitenzahl zu berechnen. -end- print.tab.output Ausgabe #print.tab.page Seite print.tab.modules Module print.tab.content Inhalt print.tab.advanced Einstellungen ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *250 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Optionen opt.treelabel Optionen opt.general Allgemein opt.interface Schnittstelle opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Drucken opt.print.output Ausgabe opt.print.content Inhalt opt.simulate Simulieren opt.simulate.basic Grundlegendes opt.simulate.tech Technologie opt.simulate.error Fehlerbehandlung opt.library Bibliotheken opt.library.path Pfad opt.library.load Autom. Laden opt.library.vpd VPD opt.analysis Analyse opt.color Farben opt.color.title TkGate: Farbauswahl opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Verfügbare Bibliotheken opt.lib.load.selected Ausgewählte Bibliotheken opt.identity Organisation opt.site Netzadresse opt.username Benutzername opt.libname Bibliotheksname: opt.inst Instanzen opt.mods Module opt.modports Modul-Ports opt.frames Rahmen opt.comment Kommentare opt.hlink Hyperlinks opt.wire Einfach-Leitungen opt.bus Mehrfachleitungen opt.tools Gatter-Werkzeuge opt.background Hintergrund opt.cpath Kritischer Pfad opt.grid Scope Raster opt.logic1 Logisch Eins opt.logic0 Logisch Null opt.float Float opt.unknown Unbekannt/Konflikt opt.offled LED aus opt.onled LED ein opt.zled Undefinierte LED opt.restdef Auf Standard zurücksetzen opt.regudate Auffrischen eines Gebiets opt.smoothscroll Glattes Scrolling opt.balloon Hilfeballone einschalten opt.tearawaymenus Einschalten von wegziehbaren Hauptmenues opt.safeSave Sicheres Abspeichern der Dateien opt.saveCells Zellen in abgespeicherte Dateien einbeziehen opt.showimage Zeige Randstreifenbilder in Dialogboxen opt.novice Novizenmodus opt.blockDropConnect Porterzeugung mit Fallenlassen von Leitungen opt.ckpoint.1 Checkpointing alle opt.ckpoint.2 Kommandos ausführen. opt.freq Intervall opt.beak Sondermodi einstellen opt.bat Bat opt.trek Star Trek opt.miles Heinrich opt.contver Automatische Integritätsprüfung opt.showsimcmd Anzeige der Simulationsgeschichte opt.estepsz Epochen Schrittweite opt.cstepsz Periodendauer Schrittweite opt.overstep Takt Ãœberschreitung opt.sorttraces Scope-Signale alphabetisch sortieren opt.vpopupdelay Pop-Up Verzögerungswert #opt.initscript Globales Initialisierungsskript opt.posedge Takt hält an allen positiven Flanken opt.setclock Takt hält an allen Flanken opt.delayfilepath Technologiedateien opt.devfilepath VPD (Virtuelles Peripheres Device) Dateipfad opt.vlibpath Verilog Bibliothekspfad opt.vlibnames Basisbibliotheken opt.display Anzeige opt.interaction Interaktion opt.input Eingabe opt.security Sicherheit opt.undolen Maximale Anzahl von Undo-Op. opt.keybind Tastaturbelegungsstil opt.useless Nutzlose Features einschalten opt.features Basis Features opt.simbase Grundlegende Simulatoroptionen opt.simclock Taktoptionen opt.cpopts Optionen für Kritische Pfade opt.maxpath Maximalzahl der Pfade: opt.cpflash Anzeige mit blinkendem Pfad opt.general.fontset Font-Klasse opt.simulator.savetraces Tastkopfpositionen zwischen Simulatorläufen sichern. opt.simulator.noglitch Glitch-Unterdrückung im Simulator einschalten. opt.simulator.err Fehlerbehandlung opt.simulator.stopany Abbrechen der Simulation bei jeder Warnung. opt.simulator.showall Warnungen immer anzeigen. opt.simulator.showiferr Warnung nur bei Fehlern. opt.simulator.ignore Alle Warnungen ignorieren. opt.tool.file Datei opt.tool.edit Editieren opt.tool.gateopt Drehen/Ausrichten opt.tool.gateprop Gatter opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Modus opt.tool.module Module opt.tool.tech Technologie opt.tool.simctl Simulatorsteuerung opt.tool.simaux Simulatorbefehle opt.tool.simmode Simulator Werkzeuge opt.tool.symmode Symboleditor Werkzeuge opt.tool.symedit Ausschneiden/Einfügen opt.tool.symport Ports opt.tool.symshift Bitverschiebung opt.tool.symopr Bitoperationen opt.editor.features Editor Features: Grundlagen opt.editor.format Automatische Einrückung einschalten opt.editor.colorize Syntax Highlighting einschalten opt.editor.comments Kommentare opt.editor.strings Strings opt.editor.reserved Schlüsselwörter opt.editor.gateword Eingebaute Gatter opt.editor.instword Modulinstanzen opt.editor.taskword Systemaufgaben opt.editor.color Farbe opt.editor.bold Fett opt.editor.italic Schräg opt.editor.indentlevel Einrückung per Stufe: opt.editor.beginindent Ausrichten von begin...end an der Einrücktiefe. opt.editor.movesel Drag-and-drop der Wahl einschalten. opt.editor.returntab Automatische Einrückung nach RETURN. opt.vercheck -begin- Periodische Nachfrage nach neuen TkGate-Versionen im Internet. Dieses Feature sollte nur bei dauerhaftem Internetzugang eingeschaltet werden. -end- opt.sec.execlevel Die $tkg$exec() Systemroutine ist opt.sec.exec komplett eingeschaltet. opt.sec.regexec nur für registrierte Funktionen eingeschaltet. opt.sec.noexec ausgeschaltet. opt.sec.simfeatures Simulator Features opt.sec.send $tkg$command() Systemroutine einschalten. opt.sec.open $fopen() Systemroutine einschalten. opt.sec.writemem $writememb() und $writememh() Systemroutinen einschalten. opt.sec.enqueue $tkg$recv() und $tkg$send() Systemroutinen einschalten. opt.sec.handle Behandlung von Sicherheitsverletzungen opt.sec.stop Beenden des Simulators bei Nutzung ausgeschalteter Features. opt.sec.warn Anzeige einer Warnung bei Nutzung ausgeschalteter Features. opt.sec.ignore Ignoriere versuchte Benutzung von ausgeschalteten Features. opt.html.linkopts Link Optionen opt.html.browser Browser Aufruf opt.html.email e-Mail Aufruf opt.debug.opt Debugging Optionen opt.color.editwin Fensterfarben editieren opt.color.scopewin Farben fürs Signaldiagramm-Fenster einstellen opt.vlibadd.title TkGate: Bibliothek hinzufügen opt.gen.basetoolbar Editorkern Toolbars opt.gen.simtoolbar Simulationsmodus Toolbars opt.gen.symedtoolbar Symboleditor Toolbars opt.bbar.restore Seitendefaults wiederherstellen opt.bbar.restoreall Alle Defaults wiederherstellen ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Typ igen.side Seite igen.size Größe igen.bits Bits igen.modname Modulname: #igen.resort Erneut Sortieren igen.add Hinzufügen igen.delete Löschen igen.edit Editieren igen.in Eingang igen.out Ausgang igen.inout Ein/Ausgang igen.left links igen.right rechts igen.top oben igen.bottom unten #igen.other andere igen.mod Verwende nur Ports, die im Modul benutzt werden. igen.int Verwende nur Ports aus existierender Schnittstelle. igen.modint Verwende sowohl Modul- als auch Schnittstellen-Ports. igen.portsel Port Auswahl igen.portpos Port Positionen igen.portpos.keep Erhalte soweit möglich die Port-Positionen. igen.portpos.renew Erzeuge alle Port-Positionierungen neu. igen.caption Erzeugen der Schnittstelle igen.description -begin- Erzeugen einer neuen Schnittstelle für ein Modul. -end- info.script.error Skript Fehler module.props.title TkGate: Moduleigenschaften module.props Moduleigenschaften ipanel.plist Portliste ipanel.props Schnittstelleneigenschaften #ipanel.itype.change Typ ändern... #ipanel.itype.edsymbol Symbol editieren... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Automatisch erzeugen... ipanel.updateall Alles auffrischen... ipanel.itype.select Schnittstellentyp #ipanel.block.description Standardschnittstelle #ipanel.symbol.description Benutzerdefinierte Symbolschnittstelle ipanel.ppos.label Blockgröße verändern (mit Ortsveränderung der Ports): ipanel.ppos.fix Feste Positionen ipanel.ppos.scale Skalierte Positionen #ipanel.ppos.grid Raster ipanel.warn.toblock -begin- Der Schnittstellentyp dieses Moduls soll nach "Block" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Ist das wirklich so gewollt? -end- ipanel.warn.tosymbol -begin- Der Schnittstellentyp dieses Moduls soll nach "Symbol" verändert werden. Damit werden die aktuellen Schnittstellen- Daten zerstört. Zusätzlich muß ein neues Bitmapbild für das neue Symbol erzeugt werden. Ist das wirklich so gewollt? -end- ############################################################################## # # Block list dialog boxes # blklst.delete.title TKGate: Modul löschen blklst.copy.title TKGate: Modul kopieren blklst.rename.title TKGate: Modul umbenennen blklst.claim.title TKGate: Modul aneignen blklst.setroot.title TKGate: Wurzel-Modul festlegen blklst.new.title TKGate: Neues Modul blklst.claim Modul aneignen blklst.to Nach blklst.from Von blklst.name Name blklst.new.cap Neues Modul erzeugen blklst.del.cap Modul löschen blklst.copy.cap Modul kopieren blklst.rename.cap Modul umbenennen blklst.claim.cap Modul aneignen blklst.setroot.cap Wurzel-Modul festlegen blklst.new.exp -fillbegin- Mit dieser Dialogbox wird eine neue Moduldefinition erzeugt. Das Modul kann als Netzliste oder HDL Modul erzeugt werden. Einmal erzeugt, kann der Typ aber nicht geändert werden; es muß gelöscht und neu erzeugt werden. -end- blklst.del.exp -fillbegin- Löschen der Definition und Schnittstellendaten des angegebenen Moduls. Existierende Instanzen des gelöschten Moduls beleiben erhalten, werden aber als undefiniert markiert. -end- blklst.copy.exp -fillbegin- Erzeugen einer Kopie der angegebenen Moduldefinition. Damit kann eine Variante eines existierenden Moduls erschaffen werden. -end- blklst.rename.exp -fillbegin- Umbenennen einer Moduldefinition. Diese Operation betrifft nur die Definition, alle existierenden Instanzen dieses Moduls verweisen weiterhin auf den alten Modulnamen. -end- blklst.claim.exp -fillbegin- Umwandeln eines Bibliotheksmoduls in ein Benutzermodul. Damit kann das Modul editiert und zusammen mit der eigenen Schaltung gesichert werden. -end- blklst.setroot.exp -fillbegin- Mache das angegebene Modul zum obersten (Top-Level). -end- find.title TkGate: Objekte finden find.label Objekte finden find.exp -fillbegin- Suche den Mustertext entweder in Gatternamen, Leitungsnamen oder in Kommentaren. Ein Doppelklick auf das Resultat führt zum gesuchten Objekt. -end- find.ignorecase Groß/Kleinschreibung ignorieren find.result.module Modul find.result.type Typ find.result.name Objektname # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Suchoptionen find.results Suchresultate # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Enthält... find.qual.begins Fängt an mit... find.qual.ends Endet mit... find.qual.matches Paßt auf... find.dom.label Nach Objekten suchen in: find.dom.gates Gatter find.dom.nets Schaltungen find.dom.text Kommentartext find.search Suchen: find.target Ziel # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Schaltungseigenschaften circ.label Schaltungseigenschaften circ.ident Identifikation circ.filev Dateiversion circ.file Dateiname circ.title Schaltungsüberschrift circ.encoding Dateicodierung circ.lang Datei: Sprache circ.discchg Keine Warnungen bei Verwerfen von Änderungen. circ.flags Optionen circ.defaults Standardeinstellungen für Komponenten circ.extbar Erweiterungsleisten für AND, OR und XOR benutzen. circ.shownet Zeige bei Schaltern und DIP-Schaltern den Netznamen. circ.autostart Automatischen Simulationsstart einschalten. circ.iniscript Initialisierungsskripte #circ.noscript Keine Skriptdateien ausgewählt. #circ.really Soll '%s' wirklich aus der Liste der Inititalisierungsskripte gelöscht werden? circ.reallyupdate -fillbegin- Sollen wirklich alle '%s' Instanzen der Schnittstelle geändert werden? -end- circ.reallyoverwrite -fillbegin- Soll die bereits existierende Datei '%s' wirklich überschrieben werden? -end- @circ.library.width *500 @circ.library.height *350 circ.general Allgemein circ.library Bibliotheken circ.script Skripte circ.simulator Simulation circ.timescale Standard Simulations-Zeitskala circ.timescale.unit Einheit: circ.timescale.prec Genauigkeit: circ.sim.features Features # # Strings for timing violation reporting styles. The "after" case # is broken into the string before the time period box and after the # time period box. You can use the string "-empty-" to make a string # empty if it is not needed in a particular language. # circ.sim.tv.title Verletzung von Zeitbedingungen: Behandlung circ.sim.tv.all Ãœber alle Verletzungen von Zeitbedingungen informieren circ.sim.tv.after.1 Ãœber Verletzungen von Zeitbedingungen nachher informieren circ.sim.tv.after.2 -empty- circ.sim.tv.never Keine Benachrichtigung über Verletzungen von Zeitbedingungen. circ.exp.general -fillbegin- Betrachten und Modifizieren schaltungsspezifischer Eigenschaften. Diese Eigenschaften werden beim Speichern der Schaltung mitgesichert. -end- circ.exp.library -fillbegin- Auswählen der von dieser Schaltung benutzten Bibliotheken. Die Bibliotheksangaben werden mit der Schaltung gesichert, sie werden beim nächsten Laden der Schaltung automatisch eingelesen. -end- circ.exp.script -fillbegin- Hinzufügen von Simulationsskripten, die vor Beginn der Simulation automatisch gelesen und ausgeführt werden sollen. -end- circ.exp.simulator -fillbegin- Anzeige und Modifikation der Simulationseinstellungen dieser Schaltung. -end- ############################################################################## # # Bibliotheksverwaltung # libmgr.cap Bibliotheksverwaltung libmgr.library Bibliothek libmgr.description Beschreibung libmgr.status Status libmgr.status.load Geladen libmgr.status.unload Nicht geladen libmgr.status.loadp [Geladen] libmgr.status.unloadp [Nicht geladen] libmgr.exp -fillbegin- Wähle zu ladende oder zu entfernende Bibliotheken aus. -end- libmgr.load Laden libmgr.unload Entfernen libmgr.unloadall Alle entfernen libmgr.notedit -fillbegin- Die Bibliotheksverwaltung kann nur im Editiermodus der Schaltung geöffnet werden. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Haltepunkte break.id ID break.state S break.condition Bedingung break.value Wert ############################################################################## # Simulator # #sim.breakpt Haltepunkt sim.recursive -fillbegin- Rekursive Moduldefinition in '%s' gefunden. Simulator kann nicht gestartet werden. Keine kritische Pfadanalyse möglich. -end- sim.hyperlinkstop -fillbegin- Der Simulator läuft gerade. Soll die Simulation beendet und dem Link gefolgt werden? -end- ############################################################################## # # Critical path messages # cp.delay Pfadverzögerung: cp.pathl Pfadliste: cp.numpath Anzahl der Pfade: cp.recompute Neuberechnung ############################################################################## # Error messages # err.notinsim Nicht erlaubt, solange der Simulator aktiv ist. err.nomemselect Der Speicher ist nicht ausgewählt. err.rootinterface Kann die Schnittstelle des obersten Moduls nicht definieren. err.nopin Ausgewählter Pin kann nicht verändert werden. err.badhex Illegaler Hexwert '%s', ignoriert. err.gatanchor Gatter ist (sind) verankert und können nicht bewegt werden. err.protdata Kann den Inhalt eines geschützen (Bibliotheks-)Moduls nicht ändern. err.badfind Kann Suchziel '%s' nicht finden. err.badopendel Kann geöffnetes Modul nicht löschen. err.nosrcmod Quelle zu Modul '%s' nicht gefunden. err.noerr Fehler nicht bestimmbar. err.misserr Fehler nur teilweise bestimmbar (Absturz des Simulators?) err.nofunc Ungeeigneter oder fehlender Funktionsname für die Modulschnittstelle. err.wirerot Wegen dranhängender Leitungen kann der ausgewählte Teil nicht rotiert werden. err.badinadd Kann keine Eingänge mehr zur angewählten Schaltung hinzufügen. err.badoutadd Kann keine Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badinoutadd Kann keine Ein/Ausgänge mehr zur angewählten Schaltung hinzufügen. err.badpinchg Kann Pintyp des angewählten Gatters nicht ändern. err.badnetname Illegale Zeichen im Bezeichner gelöscht. err.netbcrename Bezeichner umbenannt in '%s' wegen illegaler Zeichen. err.netconfnet Bezeichner umbenannt in '%s' wegen Konflikten. err.netconfgat Bezeichner umbenannt in '%s' um Konflikt mit Grundgatternamen zu vermeiden. err.netconfkw Bezeichner umbenannt in '%s' um Konflikt mit Schlüsselwort zu vermeiden. err.badconsame Keine Verbindung, weil Leitungen Teil desselben Netzes sind. err.badconptsp Keine Verbindung, weil beide Leitungen Modulports oder Versorgungsleitungen sind. err.badconbitw Keine Verbindung, weil die Bitbreiten nicht zusammenpassen. err.badrange Nichtpositiver Bereich für Signaldiagramm nicht erlaubt. err.badlprcmd Druckkommando '%s' kann nicht ausgeführt werden. err.badpsopen Die Datei '%s' kann nicht für die Postscript-Ausgabe geöffnet werden. err.badid Ungültiger Bezeichner '%s' err.noinvgate Inverters sind auf Gattern dieses Typs nicht erlaubt. err.protintf Kann die geschützte Schnittstelle von Modul '%s' nicht ändern. err.bkpt.badexp Syntaxfehler in Haltepunkt-Ausdruck. Mögliche Werte: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Ungültiger Netzname '%s'. Namen beginnen mit Buchstaben und enthalten nur Buchstaben, Ziffern und '.' err.bkpt.badval Syntaxfehler in Wert '%s'. Nur dezimale oder Verilog-Konstante erlaubt. err.bkpt.toomany Zu viele Haltepunkte. Maximum ist %d. err.sim.badtmp Zwischendatei '%s' für Simulator konnte nicht gesichert werden (Platte voll?) err.sim.syntx Syntaxfehler in '%s' Kommando. err.sim.noincl Include-Datei '%s' nicht gefunden. err.sim.badedge Illegaler Flanken-Indikator '%c' in Takt-Kommando. err.sim.nobkpt Kein derartiger Haltepunkt '%s'. err.sim.nonet Kann Netz '%s' nicht finden. err.sim.nogate Kann Gatter '%s' nicht finden. err.sim.badbin Illegales Zeichen in binärer Konstante '%s'. err.sim.notswitch Schaltung '%s' ist kein Schalter, DIP-Schalter oder Register. err.sim.badcmd Kommando '%s' im Simulations-Skript unbekannt. err.sim.isrun Simulator läuft bereits (Beenden mit 'Ctrl-s e'). err.sim.run Laufzeitfehler Zeitpunkt %s. err.sim.cmd Interner Fehler (Befehl) err.noteditpchg Eigenschaften können nur im Edit-Modus geändert werden. err.badeditop Illegale Operation im Schnittstellen-Editiermodus. err.badopen Datei '%s' kann nicht geöffnet werden. err.badlibopen Bibliotheksdatei '%s' kann nicht geöffnet werden. err.nomark Vor dem Anwählen eines Schaltungstyps eine Markierung setzen (linke Maustaste). err.badgate Unbekannter Schaltungstyp. err.badportadd Zu diesem Gattertyp ist Hinzufügen von Ports nicht möglich. err.modmissing HDL Modultext fehlt für Modul "%s". err.modtoomany Ãœberzählige Moduldefinitionen in Modul "%s". err.modmismatch Namens-mismatch zwischen Textdefinition und Modulname in "%s". err.manypages -begin- Dieses Dokument hat entsetzlich viele Seiten! Soll es tatsächlich gedruckt werden? -end- err.nojump -begin- Die Funktion 'Springe-zum-Modul' kann bei der Simulation und bei der Analyse Kritischer Pfade nicht genutzt werden. Stattdessen sollte von Hand zum Zielblock navigiert werden, indem Module selektiert und mit der Taste '>' geöffnet werden. Das Modul kann mit der Taste '<' wieder verlassen werden. -end- err.nomod Modul '%s' nicht definiert. err.modlock Logikblock ist gesperrt! err.closeroot Toplevel Modul kann nicht geschlossen werden. Quit benutzen. err.editonly Kommando im Simulationsmodus nicht möglich. err.simonly Kommando nur im Simulationsmodus möglich. err.deltop Toplevel Modul '%s' kann nicht gelöscht werden. err.delprot Geschütztes Modul '%s' kann nicht gelöscht werden. err.nodel Keine löschbare Auswahl. err.modnotdef Modul '%s' ist nicht definiert. err.moddef Der Block '%s' existiert bereits. err.primredef Eingebauter Elementname '%s' kann nicht umdefiniert werden. err.primprefix Illegaler Modulname '%s' beginnt mit eingebautem Präfix '%s'. err.iskeyword Verilog Schlüsselwort '%s' kann nicht als Bezeichner verwendet werden. err.noprop Das ausgewählte Gatter hat keine editierbaren Eigenschaften. err.openscript Datei mit Simulationsskript '%s' kann nicht geöffnet werden. err.oldversion Geladene Datei hat veraltete Versionsnummer '%s' (die aktuelle Version ist '%s'). err.futureversion Geladene Datei mit künftiger TkGate-Version '%s' gesichert (die aktuelle Version ist '%s'). err.badversion Unbekannte Versionsnummer. Benutzung auf eigene Gefahr. err.nodrive Netz '%s' hat keinen Treiber in Modul '%s'. err.noconn Leitung %s{%d} ist unverbunden -- gelöscht. err.oldportact Port hinzufügen/ändern durch Rechtsklick auf Port oder Modulkante err.nomodule Kein ausgewähltes Modul. err.nomodop Keine geeigneten Module zum Betrieb verhanden. err.protexec Versuchte Ausführung des geschützten Befehls '%s' in $tkg$exec(). err.notwritable Datei '%s' ist nicht beschreibbar. err.backupfail Erzeugen einer Backupdatei '%s' gescheitert. err.yy.badprop Unbekannte Schaltungseigenschaft '%s' wird ignoriert. err.yy.badpropval Falscher Wert '%s' für Schaltungseigenschaft '%s'. err.yy.baddata Falscher Datentyp für Schaltungeigenschaft '%s' gewählt. err.yy.nosym Kein aktuelles Modulsymbol definiert. err.yy.badicon Falscher Icontyp '%s'. err.yy.toomuchdata Zu viele Icon-Daten. err.yy.nosyminst Fehlerhaftes Symbol %d in Instanz %s von %s. err.yy.badmodprop Unbekannte Moduleigenschaft '%s' wird ignoriert. err.yy.badmoddata Fehlerhafter Datentyp für Moduleigenschaft '%s' festgelegt. err.yy.badprim Unbekanntes Schlüsselwort '%s'. err.yy.nonet Undeklariertes Netz '%s'. err.yy.bogussave Gesicherte Schrottdaten entdeckt. Schaltung kann beschädigt sein. err.yy.pinformat Illegales Pin Namensformat '%s'. err.yy.pinname Pinname '%s' ist für Gattertyp '%s' nicht definiert. err.yy.nonetpos Kein Netz für Position %d in Gatter %s. err.yy.baddirective Illegale oder fehlerhafte Direktive '%s'. err.yy.badlocale Unbekannte locale '%s' in der Datei. Benutze die engl. locale. err.corruptnewsave -fillbegin- TkGate konnte die Datei in '%s' sichern, sie scheint aber korrupt zu sein. Sind Aufsetzpunkte definiert: Lade eine der Checkpoint Dateien. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.corruptsave -fillbegin- TkGate hat ein Problem bei der Sicherung der Datei '%s' entdeckt. Die existierende Datei wurde nicht modifiziert, die beschädigte Datei wurde nach '%s' geschrieben. Ist die Verwendung von Aufsetzpunkten eingeschaltet, kann versuchsweise eine der Checkpoint-Dateien geladen werden. 'tkgate -V' prüft die Integrität einer abgespeicherten Datei. -end- err.badsave -fillbegin- Beim Öffnen oder Schreiben in Datei '%s' gab es ein Problem. Bitte Datei/Verzeichnisrechte und/oder verfügbaren Plattenplatz überprüfen. -end- err.nosafesave -fillbegin- Beim Versuch der Sicherung von Datei '%s' ist ein Problem aufgetreten. Es ist möglich, einen erneuten Versuch ohne Sicherungsvalidierung zu starten. Bei Antwort "nein" bleibt die Originaldatei unverändert. Bei Antwort "ja" wird die Originaldatei überschrieben, wird aber ggf. beim Auftreten eines Fehlers zerstört. Soll eine unvalidierte Sicherung versucht werden? -end- err.noback -fillbegin- Die Datei wurde von TkGate, Version %s, erzeugt und ist nach Sichern mit der aktuellen Version %s möglicherweise von früheren Versionen nicht mehr lesbar. -end- err.viewfile Datei '%s' kann nicht geöffnet werden. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod Interner Fehler: Kann Module '%s' nicht finden. ############################################################################## # Informational messages # msg.selwire Ausgewählt: Die Leitung hat den Namen '%s'. msg.selgate Ausgewählt: %s hat den Namen '%s'. msg.selblock Ausgewählt: %s Block hat den Namen '%s'. msg.iselwire Der ausgewählte Port '%s' ist in Block '%s'. msg.iselgate Das ausgewählte %s, genannt '%s' (huch? Diese Meldung sollte nicht möglich sein). msg.iselblock Ausgewählte Modulschnittstelle ist '%s'. msg.modoverwt Zielmodul '%s' existiert bereits. Ãœberschreiben? msg.foundgate Gatter mit Namen '%s' gefunden. msg.foundwire Leitung mit Namen '%s' gefunden. msg.searchagn Suchstring '%s' nicht gefunden. Mit 'find' Suche erneut starten. msg.sim.chgtoroot Simulationsmodus braucht das root-Modul oben auf dem Editierstack. msg.sim.nogatemod Der Simulationsmodus braucht einen konkreten Modulstack. msg.setinterface Setzen der Modulschnittstelle für '%s'. msg.needsel Bitte eine Modulinstanz auswählen. msg.wroteckpt Kontrollpunkt auf %s gesetzt... msg.save Schaltung als '%s' gesichert. msg.reallynew Die Schaltung wurde verändert. Soll sie wirklich gelöscht und eine neue erzeugt werden? msg.reallyquit Die Schaltung wurde verändert. Soll das Progamm wirklich beendet werden? msg.notlib Modul '%s' ist kein Bibliotheksmodul. ############################################################################## # Heinrich messages (Activated when Heinrich Hacker uses tkgate) # miles.msg1 Nur ein Trottel würde %s%s hierhin plazieren, Heinrich. miles.msg2 Eine richtig doofe Stelle, um %s%s abzulegen, Heinrich. miles.msg3 Ein schrecklich ungeeigneter Platz für %s%s, Heinrich. miles.msg4 Heinrich, Du bist ein Trottel %s%s hierhin zu setzen. miles.msg5 Heinrich, Du allein schaffst es, %s%s hierhin zu plazieren. miles.msg6 %s%s hierhin zu setzen beweist, daß Du ein totaler Trottel bist, Heinrich. miles.msg7 Warum gibst Du nicht auf, Heinrich, das ist eine hirnrissige Schaltung. miles.msg8a Es hat keinen Sinn weiterzumachen, Heinrich. miles.msg8b Heinrich, Du hast keine Ahnung wie man eine Schaltung baut. miles.msg8c Heinrich, mir graut vor Dir. ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Portgrößen-Mismatch bei Eingangsport '%s'. verga.err.OUTPORT Portgrößen-Mismatch bei Ausgangsport '%s'. verga.err.FLOATNET Netz '%s' hat keinen Treiber (floating net). verga.err.DIRECTCONN Direct connect Operator '=>' wird nicht unterstützt. Wird als '*>' behandelt. verga.err.MEMADDR Versuch, in Speicher %s mit unbekannter Adresse zu schreiben. verga.err.MEMBITS Versuch, in Speicher %s mit unbekanntem Bitbereich zu schreiben. verga.err.BADARRAYUSG Array '%s' wird im Ausdruck ohne Index verwendet. verga.err.BADARRAYLHS Array '%s' wird auf der linken Seite ohne Index verwendet. verga.err.BADCLOSE Versuch, einen nicht geöffneten Deskriptor in Task '%s' zu schließen. verga.err.BADAUTORNG Auto range [*] ist nur gültig in Leitungs-Deklarationen 'wire'. verga.err.BADGATERNG Fehlerhafter Bereichausdruck für eine Gatter-Instanz. verga.err.BADARGVALUE Fehlerhafter Wert für Argument '%s' in Task '%s'. verga.err.DIVZERO Teilung durch Null. verga.err.NODIV Divide/module wird auf dieser Maschine nicht unterstützt - sizeof(short) muß 2 sein. verga.err.BADEDGEEVENT Ereignis im Multi-Bit Netz '%s' kann kein posedge/negedge haben. verga.err.NEEDEDGE Positive oder negative Flanke muß für Event %s spezifiziert werden. verga.err.ASGNEVENT Warten auf ein Event ist bei Zuweisung illegal. verga.err.PROTTASK Ausführung der geschützen System Task '%s' wird blockiert. verga.err.NEEDIDENT Für Argument %s von Task '%s' wird ein Bezeichner erwartet. verga.err.BADOP Operatorfehler-Ausdruck in '%s'. verga.err.NOREAD Laden von Quelldatei '%s' fehlgeschlagen. verga.err.MEMFILE Öffnen von Speicher-Datei '%s' fehlgeschlagen. verga.err.WRONGMOD Modul '%s' wurde gefunden statt '%s'. verga.err.NOTPARM Bezeichner '%s' im konstanten Ausdruck ist kein Parameter. verga.err.BADADDR Illegaler Adressbereich für Port '%s'. verga.err.BADADDRSPEC Illegale Adressbereichsspezifikation '%s'. verga.err.BADCHAR Illegales Zeichen (%s) '%s'. verga.err.BADEVENT Illegaler Ausdruck zur Ereignissteuerung. verga.err.BADCONSTOP Illegaler Operator in konstantem Ausdruck. verga.err.BADXOP Illegaler Operator in Ausdruck. verga.err.NETREDEF Illegale Redefinition des Netzes '%s'. verga.err.BADINOUT Ein/Ausgabe-Verbindungen müssen bei Port '%s' von Netz zu Netz sein. verga.err.MODUNDEF Instanz eines undefinierten Moduls '%s'. verga.err.BADASGNLHS Ãœngültige linke Seite in 'assign'. verga.err.LHSNOTREG Illegale Benutzung von '%s' auf der linken Seite einer Zuweisung. verga.err.BADLHS Ungültige linke Seite in Zuweisung. verga.err.BADOUT Ãœngültige Ausgangs-Zuweisung. verga.err.NOTREG Speicher müssen als Register deklariert werden. verga.err.PORTMIX Vermischte benannte und unbenannte Ports bei Schnittstelle '%s' von '%s'. verga.err.REPCASE Mehr als ein default: in case-Anweisung. verga.err.NOMEM In der gelesenen Speicherdatei gibt es keinen aktuellen Speicher. verga.err.BADCMD Es gibt keinen Befehl '%s'. verga.err.CMDNOTNET Es gibt kein Netz '%s' im '%s' Befehl. verga.err.MEMNONBLK Nicht-blockierende Zuweisungen zu Speicherbereichen sind nicht implementiert. verga.err.NOTPPORT Parameter '%s' ist nicht als Port deklariert. verga.err.REDEFP Parameter redefiniert Bezeichner '%s'. verga.err.PORTNOTDEF Port '%s' in Schnittstelle '%s' ist in Modul '%s' nicht definiert. verga.err.NOCONN Port '%s' hat keine Verbindungen mit Schnittstelle '%s' von '%s'. verga.err.MULTCONN Port '%s' hat Mehrfachverbindungen mit Schnittstelle '%s' von '%s'. verga.err.PORTCOUNT Portanzahl paßt nicht zur Definition der Schnittstelle '%s' von '%s'. verga.err.BADPRTRANGE Der Bereich von Port '%s' isr nicht numerisch. verga.err.BADARRAYRNG Bereichsspezifikation ist für eine Speicherreferenz von '%s' nicht erlaubt. verga.err.CMDMODREDEF Redefinition des dynamischen Moduls '%s'. verga.err.REDEF Redefinition des Beziechners %s. verga.err.PROTTASKSTOP Simulation beendet nach versuchter Ausführung der geschützten System-Task '%s'. verga.err.NOTMEM Das spezifizierte Netz '%s' ist kein Speicher. verga.err.CMDNOTMEM Das spezifizierte Netz '%s' ist kein Speicher in Befehl '%s'. verga.err.SYNTAX Syntaxfehler. verga.err.TOOFEWPP Zu wenig Parameter Ports bei Instanz %s. verga.err.OPENTOOMANY Zu viele geöffnete Dateien in Task '%s'. verga.err.TOOMANYPP Zu viele Parameter Ports bei Instanz %s. verga.err.NOTOP Oberstes Modul '%s' nicht definiert. verga.err.BADOPEN Ausgabedatei '%s' in Task '%s' kann nicht geöffnet werden. verga.err.CMDNOMOD Undefiniertes dynamisches Modul '%s' in Befehl '%s'. verga.err.BADEVENTNET Undefiniertes Netz '%s' in Ereignissteuerungs-Ausdruck. verga.err.NOTASK Undefinierte Task '%s'. verga.err.NOTDEF Undefinierte Variable '%s'. verga.err.BADRANGE Nicht unterstützter Bitbereich [%s] in Netz %s (muss von der Form [n:0] sein). verga.err.GATEUNIMP Unimplementierter primitiver Gatter-Instanz-Typ. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Schreiben auf einen bereits geschlossenen Deskriptor. verga.err.PRIMPTCOUNT Falsche Anzahl von Ports bei der primitiven Gatter-Intsanz '%s'. verga.err.CMDARGS Falsche Zahl von Argumenten im '%s' Befehl. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' mit der falschen Anzahl von Argumenten aufgerufen. verga.err.BADSTART Illegaler Anfangswert in Task '%s'. verga.err.BADSTOP Illegaler Stopwert in $readmemb. verga.err.SPECTASKUSG Task '%s' muss in einem Specify-Block benutzt werden. verga.err.BADSPECTASK Task '%s' kann nicht in einem Specify-Block benutzt werden. verga.err.TIMING Fehler im Zeitablauf in %s[%s] %s. verga.err.RAMDCHG Datenleitung geändert bei gesetztem Schreibzugriff auf %s. verga.err.RAMACHG Adressleitung geändert bei gesetztem Schreibzugriff auf %s. verga.err.NOIFDEF Kein passendes `ifdef/`ifndef für die %s Deklaration. verga.err.BADSPECLVAL Bitbereiche sind bei Pfadverzögerungs-Spezifikatoren nicht unterstützt. verga.err.PATHDITEM Nicht unterstütztes Konstrukt in Modul mit Pfadverzögerungs-Spezifikation. verga.err.PATHDINOUT Benutzung von 'inout' in Modul mit Pfadverzögerungs-Spezifikation wird nicht unterstützt. verga.err.PATHDLOOP Schleifen in Modulen mit Pfadverzögerungs-Spezifikation werden nicht unterstützt. verga.err.PATHDCOND Setzen von DelaMust durch # Ausdruck und Blockspezifikation. verga.err.TASKREDEF Redefinition eines Task oder einer Funktion '%s' in Modul '%s'. verga.err.TASKASFUNC Task '%s' wird als Funktion benutzt. verga.err.FUNCASTASK Funktion '%s' wird als Task benutzt. verga.err.TASKBADTYPE Nicht-Register-Typ in Task oder Funktion benutzt. verga.err.TASKBADPORT In Funktionen sind nur Eingabeports erlaubt. verga.err.TIMESCALEU Ungültige Einheit '%s' in `timescale Deklaration. verga.err.TIMESCALEN Ungültige Skala '%s' in `timescale Deklaration (muss 1, 10 oder 100 sein). verga.err.TIMESCALES Ungültige Syntax in `timescale Deklaration. verga.err.TIMESCALEX Einheiten müssen größer sein als die Genauigkeit der `timescale Deklaration. verga.err.TIMESCALEAN Der Entwurf enthält Module mit und ohne `timescale verga.err.BADPORTTYPE Ungültige Typdeklaration, benutzt bei '%s' verga.err.BADVALUE Ungültiger Zahlenwert '%s'. verga.err.NONEXPCTL Ereignissteuerung @(*) auf einen Nicht-Ausdruck angewendet. verga.err.NONSTATCTL Eriegnissteuerung @(*) auf eine Nicht-Anweisung angewendet. verga.err.MODREDEF Modul-Redefinition '%s'. verga.err.IE_TASK Task Definition '%s' außerhalb von Modul gefunden - interner Fehler. verga.err.IE_NONET Netz '%s' nicht gefunden - interner Fehler. verga.err.IE_NOOP Operatorbeschreibung nicht zu finden - interner Fehler. verga.err.IE_BADEXP Unerwarteter Ausdruckstyp %s - interner Fehler. verga.err.IE_BADVAR Undefinierte Variable oder unbekanntes Netz - interner Fehler. verga.err.IE_BADSTATE Unerwarteter interner Zustand bei %s - interner Fehler. verga.err.IE_RETURN BCReturn bytecode ausgeführt bei leerem Returnstack - interner Fehler. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Alle Items in die selektierte Liste. ho.setsel.alll Alle Items in die nicht selektierte Liste. ho.setsel.ltor Highlight-Items in die selektierte Liste. ho.setsel.rtol Highlight-Items in die nicht selektierte Liste. ho.net.in Single-Bit Eingang ho.net.out Single-Bit Ausgang ho.net.inout Single-Bit Ein/Ausgang ho.net.in2 Multi-Bit Eingang ho.net.out2 Multi-Bit Ausgang ho.net.inout2 Multi-Bit Ein/Ausgang ho.net.wire Single-Bit Leitung (Name sichtbar) ho.net.wire2 Multi-Bit Leitung (Name sichtbar) ho.net.hwire Single-Bit Leitung (Name versteckt) ho.net.hwire2 Multi-Bit Leitung (Name versteckt) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Sichern und Laden von Schaltungsdateien ho.opt.tool.edit Ausschneide-, Einfüge- und Suchoperationen ho.opt.tool.gateopt Gatterdrehungen und Ausrichtungsoperationen ho.opt.tool.gateprop Grundlegendes Editieren von Gattern ho.opt.tool.undo Undo und Redo Operationen ho.opt.tool.zoom Zoom in und Zoom out ho.opt.tool.mode Auswahl des Editierwerkzeugs ho.opt.tool.module Erzeugen, Löschen, Umbenennen etc. von Moduldefinitionen ho.opt.tool.tech Auswahl der Standardtechnologie für Gatter ho.opt.tool.simctl Start, Stop und Pause beim Simulator ho.opt.tool.simaux Weitere Simulatorbefehle (Lesen und Schreiben von Speicherdateien etc.) ho.opt.tool.simmode Im Simulator zwischen dem Auswahl- und dem Scroll-Werkzeug wählen. ho.opt.tool.symmode Auswahl eines Editierwerkzeugs im Symboleditor ho.opt.tool.symedit Ausschneide- und Einfügeoperationen für den Symboleditor ho.opt.tool.symport Port-Drehoperationen für den Symboleditor ho.opt.tool.symshift Verschieben der Bitmap oder von Teilen der Bitmap ho.opt.tool.symopr Verschiedene Symboleditor-Operationen ho.opt.editor.movesel -begin- Ein ausgewählter Textblock kann mit dem Mauszeiger angefaßt und in eine neue Position verschoben werden, wenn die Option angewählt ist. -end- ho.opt.editor.format -begin- Verilog Quellcode wird automatisch eingerückt, wenn die TAB-Taste gedrückt wird. -end- ho.opt.editor.indent -begin- Anzahl der Leerzeichen pro Einrückungsstufe. -end- ho.opt.editor.rtab -begin- Automatisches Einrücken der aktuellen Zeile und Tabulation zur entsprechenden Einrückung wenn RETURN gedrückt wird. -end- ho.opt.editor.beginindent -begin- Führt zur selben Einrückungstiefe eines begin..end-Blocks wie beim Vater-Block. -end- ho.opt.editor.colorize -begin- Einschalten der kontextabhängigen Einfärbung von Quellcode nach den untenstehenden Optionen. -end- ho.hdl.splitexp -begin- Mehrfachmodule im HDL-Text werden in verschiedene Module augespalten, die nach Bedarf neue Module definieren. Alle Namenskonflikte werden durch leichte Veränderung der Modulnamen aufgelöst. -end- ho.hdl.commentexp -begin- Module, die nicht auf den erwarteten Namen passen oder das oberste Modul sind, werden zu HDL-Kommentaren konvertiert. -end- ho.hdl.autoeditexp -begin- Automatisches Editieren der HDL Beschreibung zur Änderung des Modulnamens. -end- ho.hdl.cancelexp -begin- Keine Aktion ausführen und das Editieren des aktuellen Moduls fortsetzen. -end- ho.hdl.ignoreexp -begin- Ignorieren der Inkonsistenz und Fortsetzung der ausgewählten Aktion. -end- ho.new -begin- Aufgeben der aktuellen Schaltung und Editieren einer neuen. -end- ho.open Einlesen einer Schaltung aus einer Datei. ho.save Sichern der Schaltung in die aktuelle Datei. ho.saveas Sichern der Schaltung in eine neue Datei. ho.print Drucken der aktuellen Schaltung. ho.library Laden einer Bibliotheksdatei. ho.symed.tab.normal -begin- Editieren der nicht ausgewählten Symbol-Bitmap -end- ho.symed.tab.select -begin- Editieren der ausgewählten Symbol-Bitmap -end- ho.simmove -begin- Wähle Leitungen und Module aus, bediene die Schalter und gib DIP Werte ein. Klicken und festhalten einer Leitung zeigt ihren aktuellen Wert. -end- ho.move -begin- Bewegen/Verbinden - Klicken und Ziehen - setzt die Position für ein neues Gatter, - bewegt Gatter und Leitungen, - verbindet Leitungen Ein Doppelklick editiert - Gatter-, Leitungs- und Port-Eigenschaften, - Kommentartext. -end- ho.delgat -begin- Gatter entfernen - Werkzeug zum Löschen von Gattern. -end- ho.cutw -begin- Leitung trennen - Werkzeug zum Durchschneiden von Leitungen. -end- ho.scroll -begin- Scrollen - zum Einfangen und Ziehen des Editier-Canvas. -end- ho.inv -begin- Invertieren - Werkzeug zum Hinzufügen oder Löschen von Invertern an Ein- und Ausgängen von Gattern. -end- ho.bitw -begin- Bitbreite - Werkzeug zum Ändern der Breite eines Leitungsbündels. Eingabe der Anzahl der Leitungen in der Eingabebox rechts unten neben dem Logo. -end- ho.ipanel.select -begin- "Standard"-Module werden für normale rechteckige Schnittstellen benutzt, "symbolische" Module für hausgemachte Bitmap-Symbole. -end- ho.ipanel.addport -begin- Einen Port zu einem Modul hinzu- fügen. Doppelklicken nach dem letzten Item bewirkt dasselbe. -end- ho.ipanel.deleteport -begin- Löschen des ausgewählten Ports. -end- ho.ipanel.editport -begin- Editieren des ausgewählten Ports. Ein Feld in einem Port wird mit Doppelklick editiert. -end- ho.ipanel.generate -begin- Erzeugen einer neuen Schnittstelle für ein Modul, basierend auf Ports in der Port-Liste und in der Modul- definition benutzen Portelementen. -end- ho.ipanel.updateall -begin- Ersetze in allen Instanzen dieses Moduls die Schnittstelle durch die hier gezeigte kanonische Schnittstelle. -end- ho.ipanel.prot -begin- Verbiete die Änderung der Definition eines Moduls. -end- ho.ipanel.protint -begin- Verbiete die Änderung der Schnittstelle eines Moduls. -end- ho.ipanel.proted -begin- Verbiete die Änderung der Schnittstelle eines Moduls außer mit Hilfe des Schnittstelleneditors. Das dient der Verhinderung unabsichtlicher Änderungen der Schnittstelle im Haupteditorfenster -end- ho.ipanel.scale -begin- Wird ein Modul in der Größe verändert, so skaliere die Abstände zwischen den Ports mit. -end- ho.ipanel.fix -begin- Wird ein Modul in der Größe verändert, so behalte trotzdem die Abstände zwischen den Ports bei. -end- ho.mod.open Ausgewähltes Modul öffnen. ho.mod.close Aktuelles Modul schließen. ho.mod.new Einen neuen Modultyp erzeugen. ho.mod.del Modul löschen. ho.mod.copy Modul kopieren. ho.mod.rename Modul umbenennen. ho.mod.claim -begin- Konvertieren eines Bibliotheksmoduls in ein reguläres Modul. -end- ho.mod.setroot -begin- Auszeichnen eines Moduls als oberstes (Wurzel-)Modul. -end- ho.mod.type.allparts Bibliothekssammlung ho.mod.type.partlib Bibliothek ho.mod.type.part Bibliotheksmodul ho.mod.type.unknown Unbekannter Modultyp ho.mod.type.unused Sammlung unbenutzer Module ho.mod.type.conflict Modulrekursion ho.mod.type.root Oberstes (Toplevel-) Modul ho.mod.type.netlist Netzlisten Modul ho.mod.type.Lnetlist Netzlisten Modul (locked) ho.mod.type.hdl HDL Modul ho.mod.type.Lhdl HDL Modul (locked) ho.undo Undo früherer Aktion(en) ho.redo Redo von Undo-Aktion(en) ho.tab.edit -begin- Primärer Editiermodus. -end- ho.tab.interface -begin- Editieren der Modulschnittstellen. Ein Doppelklick im Schnittstellenmodus auf ein Modul der Modulliste führt zum Editieren seiner Schnittstelle. Im obersten Modul werden alle Schnittstellen anzeigt. -end- ho.tab.simulate -begin- Start des Simulators, Öffnen des Logikanalysators und Ausführen aller festgelegten Initialisierungsskripte. -end- ho.tab.cpath -begin- Suche die kritischen Pfade einer Schaltung. -end- ho.log -begin- Log von TkGate Meldungen: Fehlermeldungen, informelle Meldungen und Simulator-Konsolenausgabe. -end- ho.simgo -begin- Ist eine Simulation aktiv: kontinuierlich laufen lassen. Ist keine Simulation aktiv: Starten der Simulation und Ausführen aller Initialisierungsskripte. -end- ho.simpause -begin- Pause bei einer kontinuierlich laufenden Simulation. -end- ho.simstep -begin- Start des Ablaufs eines festen Zeitintervalls im Einzelschrittmodus. Im Fenster Simulation->Optionen kann die Schrittweite gesetzt werden. -end- ho.simclock -begin- Ablauf einer festen Anzahl von Taktzyklen. Dazu im Fenster Simulation->Optionen die Schrittweite setzen. -end- ho.simstop -begin- Beenden der aktuellen Simulation, Rückkehr in den Editiermodus. -end- ho.simbreak -begin- Editieren der aktuellen Haltepunkte. Die Simulation hält, wenn eine Haltepunktbedingung wahr wird. -end- ho.simexec -begin- Verwalten der Sammlung aktiver Skripte. -end- ho.simoptions -begin- Setzen verschiedener Optionen, die die Simulation steuern. -end- ho.simload -begin- Laden des Speichers mit dem Inhalt einer .mem-Datei. -end- ho.simdump -begin- Speicherinhalt in eine .mem-Datei schreiben. -end- ho.simview -begin- Betrachten/Modifizieren von RAM- oder ROM-Speicherinhalten. -end- ho.modlist -begin- Listen aller aktuell geladener Moduln in alphabetischer Ordnung. Ziehe die Moduln ins Editierfenster, um neue Instanzen zu erzeugen. -end- ho.modtree -begin- Hierarchiebaum aller aktuellen Module. Zum erzeugen neuer Modulinstanzen ziehe die Module ins Editierfenster. -end- ho.netlist -begin- Liste der Netze im aktuellen Modul. Das Symbol links vom Namen zeigt an, ob das Netz einbittig (grün) oder mehrbittig (rot) ist. Ein "A" im Symbol zeigt, ob der Netzname als sichtbar markiert ist. -end- ho.ports -begin- Liste der Ports des aktuellen Moduls. Das Symbol vor dem Port zeigt seine Richtung an. -end- ho.status.logo -begin- Anzeige des Simulations-Status. Wird das Eisentor-Logo angezeigt, ist TkGate im Editiermodus. Wird das vierbeinige UND- Gatter gezeigt, ist TkGate im Simulations- modus. Steht dieses UND-Gatter, so ist die Simulation angehalten; läuft es, so läuft auch die Simulation. -end- ho.status.msg Anzeigefeld für Meldungen von TkGate. ho.status.block Modulstack, der gerade editiert wird. ho.status.file -begin- Aktuelle Datei, die gerade editiert wird. Ein '*' hinter dem Dateinamen zeigt an, daß der Puffer seit der letzten Sicherung verändert worden ist. -end- ho.print.selall Ausdrucken aller zur Zeit von TKGate geladenen Module. ho.print.selcur Ausdruck des aktuellen Moduls aus dem Editierfenster. ho.print.seluse -begin- Drucke alle Moduln, die gerade "in Gebrauch" sind. Das sind solche, die Abkömmlinge des root-Moduls sind. -end- ho.print.fulltrace Drucken des ganzen Signaldiagramms. ho.print.parttrace -begin- Drucken eines Teils des Trace. Start- und Stopzeiten werden im Eingabefenster unten eingetragen. Man kann auch mit der rechten Maustaste den Bereich auf dem Scope-Fenster auswählen (mit Shift-Rechts werden große Bereich ausgewählt). -end- ho.print.parttracestart Startzeit der Trace-Ausgabe. ho.print.parttraceend Endezeit der Trace-Ausgabe. ho.print.selsel -begin- Drucke nur die unten angewählten Module. Benutze die Strg-Taste zur Auswahl mehrerer Module. -end- ho.print.modlist Wähle die zu druckenden Module aus. ho.print.timegraph -begin- Hier wird das zum Drucken ausgewählte Gebiet gezeigt. Der grüne Bereich ist der Gesamtbereich der verfügbaren Signaldaten, grau wird die zu druckende Fläche angezeigt. Verwende die Selektoren auf der Linken um ein Gebiet auszuwählen oder wähle das Gebiet im Scopefenster aus, bevor diese Dialogbox geöffnet wird. -end- ho.circuit.discchg -begin- TkGate zeigt keine Warnung an, wenn Änderungen ohne Sicherung verworfen werden. -end- ho.circuit.extbar -begin- Neu erzeugte Grundgatter (AND, OR, XOR) benutzen für Mehrfacheingänge Erweiterungsleisten. -end- ho.circuit.shownet -begin- Anfänglich zeigen neu erzeugte Schalter und DIP-Schalter neben sich den Netznamen an. -end- ho.circuit.autostart -begin- Die Simulation beginnt, sobald das Simulationsfenster angewählt ist, wenn diese Option eingeschaltet ist. -end- ho.circuit.file -begin- Der Name der Datei, von der die aktuelle Schaltung geladen wurde. -end- ho.circuit.ver -begin- Die TkGate-Version, mit der die aktuelle Datei erzeugt wurde. -end- ho.circuit.encoding -begin- Benutze diese Codierung für die Dateisicherung. -end- ho.circuit.language -begin- Nutze Fonts mit dieser Codierung zur Anzeige von Schaltungsdaten. -end- ho.circuit.title -begin- Beschreibung der Schaltung. Dieser Titel erscheint in der Druckausgabe. -end- ho.cmd.bitw -begin- Vorgegebene Bitbreite für mit dem Bitbreite-Werkzeug selektierte Leitungen. -end- ho.edgat.signam -begin- Der Name des ausgewählten Signals am ausgewählten Gatter. Der Name des Signals kann hier durch Editieren geändert werden. -end- ho.edgat.port -begin- Der Name des Ports für dieses Signal am Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.iolab -begin- Die Richtung des ausgewählten Signals am ausgewählten Gatter. Dieses Feld kann nur bei Modulinstanzen editiert werden. -end- ho.edgat.bitlab -begin- Die Bitbreite des ausgewählten Signals des ausgewählten Gatters. Die Bitbreite kann hier durch Editieren geändert werden. -end- ho.edgat.cycle Die Gesamtzahl der Epochen in einem Taktzyklus. ho.edgat.phase Der Startpunkt des Zyklus (in Prozent). ho.edgat.duty Der Prozentsatz des Zyklus, in dem der Takt 'low' ist. ho.edgat.hide -begin- Setze dieses Flag, um die Anzeige des Gatternamens zu verhindern. -end- ho.edgat.gtype Typ des Gatters. ho.edgat.gname Name dieser Gatterinstanz. ho.edgat.ganchor Setze dieses Flag, um die Position des Gatters zu verankern. ho.edgat.gx X Koordinate des Gatters. ho.edgat.gy Y Koordinate des Gatters. ho.edgat.swstate -begin- Der zu benutzende Anfangszustand des Schalters beim Start der Simulation. -end- ho.edgat.dipstate -begin- Der zu benutzende Anfangszustand des DIP-Schalters beim Start der Simulation. -end- ho.edgat.range Der Bitbereich, der aus einem Bus herausgeführt wird. ho.edgat.memfile -begin- Die Datei mit dem Anfangszustand für diesen Speicher. Die Datei wird gelesen, wenn der Simulator gestartet wird. -end- ho.edgat.func Der Funktionstyp dieses Moduls. ho.edgat.frame Die Markierung des Rahmens. ho.traceprint -begin- Drucke den Bereich des Logik-Signaldiagramms, der mit der rechten Maustaste ausgewählt ist. Shift-Rechts-Klick kann benutzt werden, um das augewählte Gebiet zu vergrößern. Der in der Scope-Ansicht sichtbare Bereich wird genutzt, falls keine Auswahl erfolgt ist. -end- ho.showxhair -begin- Wird dieser Knopf gedrückt, erscheint eine senkrechte Maßlinie im Scope-Fenster. -end- ho.opt.general.fontset -begin- Legt die Fontgröße des Basisfonts in der TkGate- Benutzerschnittstelle fest. Diese Option wird erst aktiv, wenn TkGate neu gestartet ist. -end- ho.opt.sec.send -begin- Aktivieren der $tkg$command() System Task erlaubt es Anwendungsschaltungen, dem TkGate GUI beliebige Simulator-Steuerkommandos zu senden. Dazu gehört auch die Fähigkeit zum Ausführen beliebiger Shellbefehle. Wird der Simulator zum Ausführen von Schaltungen unklarer Herkunft benutzt, sollte diese Task lieber ausgeschaltet bleiben. Aktivierung führt zu einem hohen Sicherheitsrisiko! -end- ho.opt.sec.open -begin- Aktivieren der $fopen() System Task erlaubt Anwendungsschaltungen in beliebige Dateien des Benutzers zu öffnen. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.writemem -begin- Aktivieren der $writememb() und $writememh() System Tasks erlaubt es Anwendungsschaltungen in beliebige Dateien des Benutzers zu schreiben. Deswegen gibt es ein hohes Sicherheitsrisiko mit dieser Option. -end- ho.opt.sec.enqueue -begin- Aktivieren der $tkg$recv() und $tkg$send() System Tasks erlaubt virtuellen peripheren Geräten Botschaften an TkGate Schaltungen zu senden. Das ist ein relativ geringes Sicherheitsrisiko. -end- ho.opt.ssave -begin- Führe Konsistenzüberprüfungen von Schaltungsdateien durch, bevor eine existierende Sicherungsdatei überschrieben wird. Damit wird überprüft, ob es keine Probleme mit der Sicherungsdatei gibt. -end- ho.opt.sec.exec -begin- Die volle Aktivierung der $tkg$exec() System Task erlaubt es dem Benutzer, beliebige tcl/tk-Befehle einschließlich der Ausführung beliebiger Shellbefehle abzusetzen. Die Aktivierung dieser Option stellt also ein sehr hohes Sicherheitsrisiko dar. -end- ho.opt.sec.regexec -begin- Die Aktivierung der $tkg$exec() System Task für registrierte Funktionen erlaubt es Anwendungsschaltungen, nur tcl/tk Kommandos auszuführen, die als sicher registriert sind. Solange alle virtuellen peripheren Geräte vertrauenswürdig sind, hält die Aktivierung von $tkg$exec() auf dieser Stufe gefährliche Befehle von der Ausführung ab. Das Einschalten dieser Option hat ein mittleres Sicherheitsrisiko zur Folge. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- Ist diese Einstellung aktiviert, wird die Simulation beendet, sobald von der Anwendungsschaltung versucht wird, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.warn -begin- Ist diese Einstellung aktiviert, wird die Simulation nach einer Warnmeldung weitergehen, wenn die Anwendungsschaltung versucht, ein ausgeschaltetes Feature zu benutzen. -end- ho.opt.sec.ignore -begin- Ist diese Einstellung aktiv, wird die Benutzung aller ausgeschalteten Features ignoriert; es werden keine Fehlermeldungen angezeigt. -end- ho.opt.html.browser -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zu einer HTML-Datei klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.html.email -begin- Der Befehl, der zur Ausführung kommt, wenn der Benutzer auf einen Link zum Senden einer e-mail klickt. Ein "%s" in dem Befehl wird durch die Link URL ersetzt. -end- ho.opt.fsave -begin- Sichere die TkGate-internen Zellen mit den Schaltungsdaten. Dies erhöht die Dateigröße um ca. 20%, führt aber zu Sicherungsdateien, die zur Verwendung mit Drittanbietertools exportiert werden können. -end- ho.opt.sorttraces -begin- Ist diese Option eingeschaltet, werden die Signale im Scope-Fenster in sortierter Form angezeigt. Ist sie ausgeschaltet, werden die Signale im Scopefenster in der Reihenfolge der Probe-Setzungen angezeigt. -end- ho.opt.sim.noglitch -begin- Ist diese Option aktiv, so bewirken sich schnell verändernde Signale am Eingang eines Gatters am Ausgang desselben im wesentlichen das zeitverschobene Eingangssignal. Dies kann flüchtige Ereignisse und Schwingungen in sequentiellen Schaltungen auf Gatterebene verhindern helfen. -end- ho.opt.sim.savetraces -begin- Tastköpfe, die während eines Simulationslaufes plaziert wurden, werden abgespeichert und beim Neustart der Simulation wieder richtig gesetzt. -end- ho.opt.sim.tech -begin- Dateienliste zum Laden als potentielle "Technologie"-Dateien. Technologie-Dateien legen Verzögerungen und Flächengrößen für eingebaute Gatter fest. -end- ho.opt.sim.err -begin- Wähle, wie Warnungen vom Simulator behandelt werden sollen. -end- ho.opt.sim.err.stopany -begin- Gibt es irgendwelche Warnungen zu der Schaltung, wird sie nicht simuliert, auch nicht, falls es gar keine wirklichen Fehler gibt. -end- ho.opt.sim.err.showall -begin- Ziege immer Warnunge zu der Schaltung, auch wenn es keine Fehler gibt. Falls nur Warnungen existieren, wird der Simulator gestartet und die Warnungen in einem gesonderten Fenster angezeigt. -end- ho.opt.sim.err.showiferr -begin- Zeige Warnungen nur, wenn es auch Fehler in der Schaltung gibt. Enthält eine Schaltung nur Warnungen, so werden sie ignoriert und der Simulator wird geräuschlos gestartet. -end- ho.opt.sim.err.ignore -begin- Zeige nie Warnmeldungen, auch nicht, falls es Fehler in der Schaltung gibt. -end- ho.opt.lib.vpath -begin- Liste von Verzeichnissen, in denen nach TkGate Bibliotheksdateien gesucht wird. Bibliotheken sollten eine .v Dateierweiterung besitzen und Module enthalten, die für den Gebrauch in Anwendungsschaltungen nützlich sind. -end- ho.opt.lib.vlib -begin- Die Bibliotheksliste, die automatisch geladen wird, wenn TkGate startet. -end- ho.opt.lib.vpd -begin- Liste von Verzeichnissen, in denen nach virtuellen peripheren Geräten (VPDs) gesucht wird. Virtuelle periphere Geräte haben eine .tcl Dateierweiterung und implementieren typischerweise ein GUI, das das periphere Gerät repräsentiert und das von einer benutzerschaltung gesteuert wird. -end- ho.opt.undolen -begin- Maximale Zahl der aufzuhebenden Undo-Aktionen. -end- ho.opt.name -begin- Benutzername, der auf allen von TkGate produzierten Reports, z.B. Schaltungs- ausdrucken, aufgeführt wird. -end- ho.opt.site -begin- Der Netzname der Organisation, in der TKGate installiert ist. Dieser Name wird auf jedem Ausdruck (oder in der Postscript-Datei) ausgegeben. -end- ho.opt.smooth -begin- Falls diese Option eingestellt ist, wird Scrollen mittels Bitmap-Kopien realisiert statt das Bild immer neu zu zeichnen. Dies kann ausgeschaltet werden, falls Probleme mit dem X-Server auftreten. -end- ho.opt.clip -begin- Ist diese Option eingeschaltet, wird Clipping benutzt, um den dargestellten Teil des Fensters beim Neuaufbau zu zeichnen. Sonst wird das ganze Display für alle Teile neu gezeichnet. -end- ho.opt.showimage -begin- Durch Zurücksetzen dieser Option kann die Anzeige des Bildes un der erläuternde Text am Rand der Dialogboxen unterdrückt werden. -end- ho.opt.outmove -begin- Ist diese Option eingeschaltet, wird nur der Umriß der bewegten Modulinstanzen beim Verschieben angezeigt. Diese Einstellung ist nur auf Maschinen mit langsamen Displays nötig. -end- ho.opt.bhelp -begin- Bei Aktivierung dieser Option werden Hilfehinweise angezeigt. Sie zeigen Tips an, wenn die Maus sich gerade über einem Baustein befindet. -end- ho.opt.tearawaymenus -begin- Die Hauptmenues können von der Schnitstelle entfernt werden. Diese Option wird erst nach einem Neustart von TkGate wirksam. -end- ho.opt.novice -begin- Falls auf der Kommandozeile keine andere Schaltung angegeben ist, wird ein TkGate- Tutorial als erste Schaltung beim Start angezeigt. -end- ho.opt.blockDropConnect -begin- Dies Option erlaubt die Erzeugung von Ports bei Modulschnittstellen, indem freie Leitungen neben einer Kante fallengelassen werden. -end- ho.opt.debug -begin- Einschalten mehrerer Debugging Features. Nur interessant für TKGate-Entwickler. -end- ho.opt.ckpt Einschalten des Checkpointing nicht gespeicherter Schaltungen. ho.opt.ckptfreq Anzahl der Checkpoints pro Sekunde. ho.opt.beak -begin- Freischalten dieser total nutzlosen Features. Falls dies ausgeschaltet wird, erscheinen diese Modi (und diese Checkbox) nicht mehr im Optionsfenster. Der einzige Weg, sie wiederzubekommen, geht über das Editieren der .tkgate-properties Datei. -end- ho.opt.miles -begin- Ist dieser Modus eingeschaltet, wird TkGate periodisch die Intelligenz des Benutzers anzweifeln. -end- ho.opt.bat -begin- Falls dieser Modus eingeschaltet ist, wird TkGate eine Entwicklungsumgebung für einen Bat-Computer einrichten. -end- ho.opt.trek Beam me up Scotty! ho.opt.simstep -begin- Die Anzahl der Epochen, die bei einem Schritt-Kommando vorangeschritten wird. -end- ho.opt.ckstep -begin- Die Anzahl der Taktzyklen, die vorangeschritten wird, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.ckover -begin- Die Anzahl der Epochen nach der Anstiegsflanke des Taktes, wenn das Taktschritt-Kommando gegeben wird. -end- ho.opt.vpopupdelay -begin- Die Verzögerung in Millisekunden zwischen Drücken und Halten der Maustaste und der Anzeige eines Signalwerts. Auf einigen Systemen interferieren kurze Verzögerungs- zeiten mit der Fähigkeit, einen Doppelklick zu erkennen. Liegt dieser Fall vor, so ist der Wert zu erhöhen. Es sind Werte zwischen 1 und 10000 erlaubt. -end- ho.opt.init -begin- Eine Simulationsskript-Datei, die automatisch ausgeführt wird, wenn die Simulation gestartet wird. -end- ho.opt.ckall -begin- Falls diese Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation bei der positiven Flanke jeder Taktquelle in der Schaltung an. -end- ho.opt.ckspec -begin- Falls dieser Modus eingeschaltet ist, hält das Taktschritt-Kommando die Simulation nur an der positiven Flanke der spezifizierten Taktquelle an. -end- ho.opt.keybind -begin- Legt den Stil für Tastenbindungen fest. Wird diese Option geändert, werden die Bindungen sofort aufge- frischt. Allerdings muß TkGate neu gestartet werden, damit irgendwelche benutzerdefinierten Tastaturbindungen zu sehen sind. -end- ho.deftech -begin- Standard-Technologie für neue Gatter. Beeinflußt die Verzögerungszeit der Gatter. Um die Technologie eines bestimmten Gatters zu ändern, öffnet mann die Eigenschafts-Box mit Doppelklick und wählt "Delay" an. -end- ho.techbut -begin- Benutze Verzögerungszeiten aus der Datei zur Definition der Standard Technologie. Um eigene Technologien zu entwickeln, füge man sie zu der Liste im "Datei -> Optionen -> Simulation"-Menu hinzu. -end- ho.custbut -begin- Setze eigene Verzögerungszeitwerte für dieses Gatter. -end- ho.contver -begin- Verifiziere die Integrität der internen Datenstrukturen nach jeder Operation. -end- ho.simwatch -begin- Zeige Kommandos an, die zwischen GUI und Simulator gesendet werden. -end- ho.symed.point -begin- Pixel-Editiermodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.line -begin- Geraden-Modus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.rect -begin- Rechteckmodus. Die linke Maus- taste setzt Pixel, die rechte löscht sie. -end- ho.symed.fillrect -begin- Ausgefüllter Rechteckmodus. Die linke Maustaste setzt Pixel, die rechte löscht sie. -end- ho.symed.select -begin- Bitmap Auswahlmodus. Die linke Maustaste wählt Bereiche der Bitmap aus. Auf der Auswahl können dann Cut und Paste Operationen vorgenommen werden. -end- ho.symed.port -begin- Portauswahlmodus. Wähle Ports aus, bewege sie oder rotiere sie. -end- ho.symed.rshift Ausgewählte Pixel rechtsverschieben. ho.symed.lshift Ausgewählte Pixel linksverschieben. ho.symed.ushift Ausgewählte Pixel nach oben verschieben. ho.symed.dshift Ausgewählte Pixel nach unten verschieben. ho.symed.cwrotate Ausgewählte Pixel rechts drehen. ho.symed.ccwrotate Ausgewählte Pixel links drehen. ho.symed.autobold Das ausgewählte Bild fett machen. ho.symed.resize Den Bildeditor in der Größe ändern. ho.symed.import Bild aus einer Datei importieren. ho.symed.export Bild in eine Datei exportieren. ho.tool.currot -begin- Zeigt aktuelle Vorgabe des Rotationswinkels an. Ändern durch Klick auf diese Taste. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotieren der ausgewählten Gatter gegen den Uhrzeigersinn. ho.tool.brotate Rotieren der ausgewählten Gatter mit dem Uhrzeigersinn. ho.tool.valgn Ausgewählte Gatter vertikal ausrichten. ho.tool.halgn Ausgewählte Gatter horizontal ausrichten. ho.tool.cut Ausschneiden des ausgewählten Teils. ho.tool.copy Kopieren des ausgewählten Teils.. ho.tool.paste Einfügen aus dem Cut-Puffer. ho.tool.find Gatter, Leitungen oder Text suchen (und finden). ho.tool.addport Zum ausgewählten Gatter einen Port hinzufügen. ho.tool.anchor Die ausgewählten Gatter verankern. ho.tool.unanchor Die ausgewählten Gatter loslassen. ho.tool.replicate Replizieren eines Gatters. ho.tool.delete Löschen der Auswahl. tkgate-2.0-b10/locale/de/examples.18/ex1000777 001751 001751 00000000000 11145151105 020316 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18/ex2000777 001751 001751 00000000000 11145151105 020317 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18/ex3000777 001751 001751 00000000000 11145151105 020320 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18/ex4000777 001751 001751 00000000000 11145151105 020321 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18/ex5000777 001751 001751 00000000000 11145151105 020322 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples.18/index.v000644 001751 001751 00000004351 10521363116 021201 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "index.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g4 @(553,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Coke Machine

" //: /line:"This example uses TkGate's Viritual" //: /line:"Peripheral Device (VPD) mechanism to" //: /line:"create an interactive \"Coke Machine\"" //: /line:"that can be controlled by a user circuit." //: /line:"Only the coke machine device itself is" //: /line:"included. Can you build a controller" //: /line:"for it?" //: /line:"" //: /end //: comment g3 @(32,317) /sn:0 /anc:1 //: /line:"" //: /line:"

Transistor-Level FF

" //: /line:"A flop-flop implemented using" //: /line:"nmos and pmos devices." //: /line:"" //: /end //: comment g2 @(551,30) /sn:0 /anc:1 //: /line:"" //: /line:"

8-Bit Counter

" //: /line:"A counter implemented using the" //: /line:"register and adder devices." //: /end //: comment g1 @(299,30) /sn:0 /anc:1 //: /line:"" //: /line:"

3-Bit Counter

" //: /line:"A 3-bitcounter implemented using" //: /line:"three single-bit D-flip-flops." //: /end //: comment g6 @(20,552) /sn:0 //: /line:"Go back to the TkGate main page" //: /end //: comment g5 @(301,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Menagerie CPU

" //: /line:"A simple microcode-based CPU that" //: /line:"will play the \"Animals\" game on a" //: /line:"TTY device when simulated." //: /end //: comment g0 @(32,30) /sn:0 /anc:1 //: /line:"

" //: /line:"Combinational Logic

" //: /line:"A simple 3-bit adder that you" //: /line:"simulate. Push the play button" //: /line:"then click on the switches and" //: /line:"watch how the LEDs change." //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/de/examples.18/ex5/menagerie.v000644 001751 001751 00000210407 10013160063 022520 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 //: script "menagerie.gss" module MEMORY(DATA, _wrt, _ldpc, spc, _ldmdr, _rd, _rdmdr, _ldhmdr, _CLR, _rdpc, _incmar, _ldmar, CK, _incpc); //: interface /sz:(125, 353) /bd:[ Ti0>_CLR(83/125) Ti1>CK(33/125) Bi0>DATA[15:0](60/125) Ri0>_incmar(186/353) Ri1>_rdpc(171/353) Ri2>_ldhmdr(155/353) Ri3>spc(136/353) Ri4>_rd(120/353) Ri5>_wrt(104/353) Ri6>_rdmdr(88/353) Ri7>_incpc(73/353) Ri8>_ldmdr(57/353) Ri9>_ldmar(42/353) Ri10>_ldpc(25/353) ] supply0 [5:0] w16; //: /sn:0 {0}(545,861)(545,840){1} input _rd; //: /sn:0 {0}(671,557)(671,614){1} //: {2}(673,616)(708,616)(708,273)(740,273){3} //: {4}(669,616)(512,616){5} //: {6}(510,614)(510,579){7} //: {8}(508,616)(482,616){9} input _rdpc; //: /sn:0 {0}(259,285)(270,285)(270,306){1} input CK; //: /sn:0 /dp:1 {0}(753,813)(742,813)(742,833)(618,833)(618,815){1} //: {2}(620,813)(631,813){3} //: {4}(616,813)(524,813)(524,438){5} //: {6}(526,436)(641,436)(641,334)(726,334){7} //: {8}(522,436)(130,436){9} //: {10}(128,434)(128,335){11} //: {12}(130,333)(321,333)(321,307)(326,307){13} //: {14}(128,331)(128,253)(151,253){15} //: {16}(126,436)(62,436){17} input _CLR; //: /sn:0 {0}(512,218)(512,201){1} //: {2}(514,199)(844,199)(844,327){3} //: {4}(842,329)(802,329){5} //: {6}(844,331)(844,770){7} //: {8}(842,772)(716,772)(716,808)(707,808){9} //: {10}(844,774)(844,808)(829,808){11} //: {12}(510,199)(409,199){13} //: {14}(405,199)(263,199)(263,248)(227,248){15} //: {16}(407,201)(407,302)(402,302){17} supply0 [7:0] w3; //: /sn:0 {0}(683,269)(683,251)(662,251){1} input _ldmar; //: /sn:0 {0}(458,247)(458,314)(438,314){1} input _wrt; //: /sn:0 {0}(691,706)(424,706){1} //: {2}(422,704)(422,510){3} //: {4}(424,508)(454,508){5} //: {6}(420,508)(399,508){7} //: {8}(422,708)(422,758)(692,758){9} input _ldhmdr; //: /sn:0 {0}(673,103)(709,103){1} //: {2}(713,103)(871,103)(871,269){3} //: {4}(711,105)(711,137){5} supply0 [15:0] w21; //: /sn:0 {0}(220,59)(220,42)(194,42)(194,69){1} inout [15:0] DATA; //: /sn:0 /dp:13 {0}(278,311)(297,311)(297,213)(371,213){1} //: {2}(373,211)(373,167){3} //: {4}(375,165)(508,165){5} //: {6}(512,165)(547,165){7} //: {8}(551,165)(568,165){9} //: {10}(549,167)(549,246)(616,246){11} //: {12}(510,163)(510,134){13} //: {14}(371,165)(198,165)(198,188){15} //: {16}(373,215)(373,248){17} input _ldpc; //: /sn:0 {0}(233,131)(217,131)(217,152)(148,152){1} //: {2}(144,152)(131,152){3} //: {4}(146,154)(146,204)(165,204){5} supply0 w23; //: /sn:0 {0}(829,818)(844,818)(844,836){1} supply1 w20; //: /sn:0 {0}(241,70)(241,83)(202,83){1} supply0 [7:0] w24; //: /sn:0 {0}(595,538)(595,523){1} supply0 [7:0] w1; //: /sn:0 {0}(800,724)(800,677)(825,677)(825,687){1} input _rdmdr; //: /sn:0 {0}(624,284)(624,251){1} input _incpc; //: /sn:0 {0}(233,126)(133,126){1} supply0 w17; //: /sn:0 {0}(496,579)(496,592){1} input spc; //: /sn:0 {0}(251,380)(207,380){1} input _ldmdr; //: /sn:0 /dp:1 {0}(876,269)(876,80)(673,80){1} input _incmar; //: /sn:0 {0}(438,309)(448,309)(448,281)(327,281){1} //: {2}(325,279)(325,266){3} //: {4}(327,264)(340,264){5} //: {6}(325,262)(325,243){7} //: {8}(325,283)(325,293)(313,293)(313,326)(223,326)(223,411)(96,411)(96,383){9} wire [15:0] w6; //: /sn:0 {0}(162,69)(162,47)(70,47)(70,360)(83,360){1} wire [7:0] mdrin; //: /sn:0 {0}(520,552)(557,552){1} //: {2}(561,552)(663,552){3} //: {4}(559,550)(559,523){5} wire w46; //: /sn:0 {0}(402,312)(417,312){1} wire w14; //: /sn:0 {0}(254,129)(272,129)(272,258)(227,258){1} wire [15:0] w4; //: /sn:0 {0}(584,165)(614,165){1} wire [15:0] w19; //: /sn:0 {0}(188,217)(188,243){1} wire w15; //: /sn:0 {0}(691,711)(645,711){1} //: {2}(643,709)(643,672){3} //: {4}(641,711)(436,711){5} //: {6}(434,709)(434,512)(454,512){7} //: {8}(432,711)(365,711){9} wire w; //: /sn:0 {0}(802,339)(874,339)(874,290){1} wire [15:0] PC; //: /sn:0 {0}(188,264)(188,309){1} //: {2}(190,311)(262,311){3} //: {4}(188,313)(188,348){5} //: {6}(190,350)(264,350)(264,364){7} //: {8}(186,350)(112,350){9} wire [15:0] w38; //: /sn:0 {0}(210,713)(300,713){1} wire w37; //: /sn:0 {0}(713,761)(722,761)(722,818)(707,818){1} wire DTR; //: /sn:0 {0}(451,982)(565,982)(565,840){1} wire [7:0] w34; //: /sn:0 {0}(555,834)(555,668)(571,668)(571,523){1} wire [15:0] w43; //: /sn:0 {0}(363,297)(363,277){1} wire RTS; //: /sn:0 {0}(451,958)(555,958)(555,840){1} wire w31; //: /sn:0 {0}(366,763)(446,763){1} //: {2}(450,763)(631,763){3} //: {4}(635,763)(692,763){5} //: {6}(633,761)(633,672){7} //: {8}(448,761)(448,515)(454,515){9} wire [15:0] w28; //: /sn:0 {0}(344,711)(321,711){1} wire [7:0] w36; //: /sn:0 {0}(790,753)(790,803){1} wire DSR; //: /sn:0 {0}(451,974)(800,974)(800,858){1} wire CTS; //: /sn:0 {0}(451,966)(790,966)(790,858){1} wire [7:0] w25; //: /sn:0 {0}(763,286)(763,324){1} wire [15:0] w18; //: /sn:0 {0}(274,393)(274,550){1} //: {2}(276,552)(485,552){3} //: {4}(274,554)(274,706){5} //: {6}(276,708)(300,708){7} //: {8}(274,710)(274,760)(301,760){9} wire [7:0] w8; //: /sn:0 {0}(620,170)(695,170){1} wire [5:0] w35; //: /sn:0 {0}(780,858)(780,881)(760,881){1} wire [15:0] w40; //: /sn:0 {0}(212,765)(301,765){1} wire [15:0] w30; //: /sn:0 {0}(345,763)(322,763){1} wire w22; //: /sn:0 {0}(154,83)(144,83){1} wire w11; //: /sn:0 {0}(503,529)(503,512)(475,512){1} wire [15:0] w2; //: /sn:0 {0}(656,246)(632,246){1} wire [7:0] mdr; //: /sn:0 {0}(780,724)(780,676)(724,676){1} //: {2}(722,674)(722,552)(699,552){3} //: {4}(697,550)(697,379){5} //: {6}(699,377)(763,377)(763,345){7} //: {8}(697,375)(697,241)(662,241){9} //: {10}(695,552)(679,552){11} //: {12}(720,676)(668,676)(668,803){13} wire [7:0] RD; //: /sn:0 {0}(668,824)(668,949)(451,949){1} wire [15:0] mar; //: /sn:0 {0}(363,318)(363,349){1} //: {2}(361,351)(284,351)(284,364){3} //: {4}(363,353)(363,400)(136,400)(136,370)(112,370){5} wire [7:0] w13; //: /sn:0 {0}(753,257)(753,198)(577,198)(577,494){1} wire [1:0] w27; //: /sn:0 {0}(600,507)(638,507)(638,666){1} wire [7:0] w5; //: /sn:0 {0}(620,160)(661,160)(661,150)(695,150){1} wire [7:0] w33; //: /sn:0 {0}(790,852)(790,824){1} wire [7:0] w42; //: /sn:0 {0}(773,257)(773,160)(724,160){1} wire [15:0] w9; //: /sn:0 {0}(178,188)(178,114){1} //: {2}(178,110)(178,98){3} //: {4}(180,112)(353,112)(353,248){5} wire [7:0] TD; //: /sn:0 {0}(451,941)(583,941)(583,523){1} wire w26; //: /sn:0 {0}(712,709)(745,709)(745,740)(767,740){1} //: enddecls //: joint g61 (w31) @(448, 763) /w:[ 2 8 1 -1 ] //: inout g8 (DATA) @(510,128) /sn:0 /R:3 /w:[ 13 ] //: joint g4 (_rd) @(510, 616) /w:[ 5 6 8 -1 ] //: joint g3 (_CLR) @(512, 199) /w:[ 2 -1 12 1 ] //: joint g55 (CK) @(524, 436) /w:[ 6 -1 8 5 ] //: joint g86 (_wrt) @(422, 508) /w:[ 4 -1 6 3 ] //: input g13 (_wrt) @(397,508) /sn:0 /w:[ 7 ] //: input g34 (_ldpc) @(129,152) /sn:0 /w:[ 3 ] //: input g37 (spc) @(205,380) /sn:0 /w:[ 1 ] register g51 (.Q(RD), .D(mdr), .EN(w37), .CLR(_CLR), .CK(CK)); //: @(668,813) /sn:0 /w:[ 0 13 1 9 3 ] //: joint g58 (_CLR) @(844, 772) /w:[ -1 7 8 10 ] //: comment g89 /dolink:0 /link:"" @(37,543) /sn:0 //: /line:"This is the memory address line." //: /line:"The address can be selected from" //: /line:"the MAR (Memory Address Register)" //: /line:"or from the PC (Program Counter)." //: /end //: input g77 (_ldmdr) @(671,80) /sn:0 /w:[ 1 ] //: joint g76 (w9) @(178, 112) /w:[ 2 1 4 -1 ] //: joint g65 (mdr) @(722, 676) /w:[ 1 2 12 -1 ] //: input g2 (_rd) @(480,616) /sn:0 /w:[ 9 ] nand g59 (.I0(!_wrt), .I1(w31), .Z(w37)); //: @(703,761) /sn:0 /w:[ 9 5 0 ] //: supply0 g1 (w17) @(496,598) /sn:0 /w:[ 1 ] register PC (.Q(PC), .D(w19), .EN(w14), .CLR(_CLR), .CK(CK)); //: @(188,253) /w:[ 0 1 1 15 15 ] bufif0 g72 (.Z(DATA), .I(PC), .E(_rdpc)); //: @(268,311) /sn:0 /w:[ 0 3 1 ] //: joint g64 (_wrt) @(422, 706) /w:[ 1 2 -1 8 ] mux g11 (.I0(mdrin), .I1(w34), .I2(TD), .I3(w24), .S(w27), .Z(w13)); //: @(577,507) /sn:0 /R:2 /w:[ 5 1 1 1 0 1 ] //: frame g16 @(110,659) /sn:0 /wi:762 /ht:347 /tx:"TTY Control" //: joint g10 (CK) @(128, 333) /w:[ 12 14 -1 11 ] //: comment g87 /dolink:0 /link:"" @(210,776) //: /line:"These dip switches specify the" //: /line:"addresses for the tty status" //: /line:"and data registers." //: /end //: joint g78 (PC) @(188, 350) /w:[ 6 5 8 -1 ] add g28 (.A(w6), .B(w21), .S(w9), .CI(w20), .CO(w22)); //: @(178,85) /sn:0 /w:[ 0 1 3 1 0 ] concat g50 (.I0(DSR), .I1(CTS), .I2(w35), .Z(w33)); //: @(790,853) /sn:0 /R:1 /w:[ 1 1 0 0 ] /dr:0 mux g32 (.I0(w9), .I1(DATA), .S(_incmar), .Z(w43)); //: @(363,264) /sn:0 /w:[ 5 17 5 1 ] //: joint g19 (mdr) @(697, 552) /w:[ 3 4 10 -1 ] //: joint g27 (DATA) @(373, 165) /w:[ 4 -1 14 3 ] //: input g6 (_rdmdr) @(624,286) /sn:0 /R:1 /w:[ 0 ] //: input g69 (_ldhmdr) @(671,103) /sn:0 /w:[ 0 ] //: joint g38 (DATA) @(549, 165) /w:[ 8 -1 7 10 ] ram m1 (.A(w18), .D(mdrin), .WE(w11), .OE(_rd), .CS(w17)); //: @(503,553) /w:[ 3 0 0 7 0 ] //: joint g75 (DATA) @(373, 213) /w:[ -1 2 1 16 ] bufif1 g7 (.Z(mdrin), .I(mdr), .E(_rd)); //: @(673,552) /sn:0 /R:2 /w:[ 3 11 0 ] mux g9 (.I0(w13), .I1(w42), .S(_rd), .Z(w25)); //: @(763,273) /sn:0 /w:[ 0 0 3 0 ] register g53 (.Q(w33), .D(w36), .EN(w23), .CLR(_CLR), .CK(CK)); //: @(790,813) /sn:0 /w:[ 1 1 0 11 0 ] //: joint g57 (_CLR) @(844, 329) /w:[ -1 3 4 6 ] mux g31 (.I0(PC), .I1(mar), .S(!_incmar), .Z(w6)); //: @(96,360) /sn:0 /R:3 /w:[ 9 5 9 1 ] //: joint g71 (_ldhmdr) @(711, 103) /w:[ 2 -1 1 4 ] concat g15 (.I0(w5), .I1(w8), .Z(w4)); //: @(615,165) /sn:0 /R:2 /w:[ 0 0 1 ] /dr:0 //: supply0 g20 (w3) @(683,275) /sn:0 /w:[ 0 ] mux g68 (.I0(w5), .I1(w8), .S(!_ldhmdr), .Z(w42)); //: @(711,160) /sn:0 /R:1 /w:[ 1 1 5 1 ] //: supply0 g67 (w23) @(844,842) /sn:0 /w:[ 1 ] xor g39 (.I0(w18), .I1(w38), .Z(w28)); //: @(311,711) /sn:0 /w:[ 7 1 1 ] //: joint g43 (w18) @(274, 552) /w:[ 2 1 -1 4 ] //: supply0 g48 (w16) @(545,867) /sn:0 /w:[ 0 ] //: input g88 (_CLR) @(512,220) /sn:0 /R:1 /w:[ 0 ] //: joint g17 (DATA) @(510, 165) /w:[ 6 12 5 -1 ] mux g25 (.I0(PC), .I1(mar), .S(!spc), .Z(w18)); //: @(274,380) /sn:0 /w:[ 7 3 0 0 ] //: supply1 g29 (w20) @(252,70) /sn:0 /w:[ 0 ] nand g62 (.I0(!_wrt), .I1(w15), .Z(w26)); //: @(702,709) /sn:0 /w:[ 0 0 0 ] //: input g73 (_rdpc) @(257,285) /sn:0 /w:[ 0 ] //: joint g52 (mdr) @(697, 377) /w:[ 6 8 -1 5 ] nor g42 (.I0(w30), .Z(w31)); //: @(356,763) /sn:0 /w:[ 0 0 ] //: joint g63 (w15) @(643, 711) /w:[ 1 2 4 -1 ] nor g83 (.I0(!_incmar), .I1(!_ldmar), .Z(w46)); //: @(427,312) /sn:0 /R:2 /w:[ 0 1 1 ] //: joint g74 (PC) @(188, 311) /w:[ 2 1 -1 4 ] //: joint g5 (_CLR) @(407, 199) /w:[ 13 -1 14 16 ] //: frame g14 @(536,27) /sn:0 /wi:372 /ht:394 /tx:"MDR Control" //: joint g56 (CK) @(618, 813) /w:[ 2 -1 4 1 ] //: input g80 (_incmar) @(325,241) /sn:0 /R:3 /w:[ 7 ] //: joint g79 (mar) @(363, 351) /w:[ -1 1 2 4 ] //: joint g44 (w18) @(274, 708) /w:[ 6 5 -1 8 ] concat g47 (.I0(DTR), .I1(RTS), .I2(w16), .Z(w34)); //: @(555,835) /sn:0 /R:1 /w:[ 1 1 1 0 ] /dr:0 //: joint g24 (CK) @(128, 436) /w:[ 9 10 16 -1 ] //: joint g85 (w15) @(434, 711) /w:[ 5 6 8 -1 ] or g84 (.I0(_wrt), .I1(w15), .I2(w31), .Z(w11)); //: @(465,512) /sn:0 /w:[ 5 7 9 1 ] register mdr (.Q(mdr), .D(w25), .EN(w), .CLR(_CLR), .CK(CK)); //: @(763,334) /w:[ 7 1 0 5 7 ] bufif0 g21 (.Z(DATA), .I(w2), .E(_rdmdr)); //: @(626,246) /sn:0 /R:2 /w:[ 11 1 1 ] //: joint g36 (_ldpc) @(146, 152) /w:[ 1 -1 2 4 ] //: input g23 (_ldmar) @(458,245) /sn:0 /R:3 /w:[ 0 ] nor g41 (.I0(w28), .Z(w15)); //: @(355,711) /sn:0 /w:[ 0 9 ] //: dip TTYSTATUS (w38) @(172,713) /R:1 /w:[ 0 ] /st:16 //: frame g93 @(354,466) /sn:0 /wi:421 /ht:164 /tx:"Main Memory" //: joint g81 (_incmar) @(325, 264) /w:[ 4 6 -1 3 ] mux g54 (.I0(mdr), .I1(w1), .S(w26), .Z(w36)); //: @(790,740) /sn:0 /w:[ 0 0 1 0 ] xor g40 (.I0(w18), .I1(w40), .Z(w30)); //: @(312,763) /sn:0 /w:[ 9 1 1 ] //: joint g60 (w31) @(633, 763) /w:[ 4 6 3 -1 ] //: comment g90 /dolink:0 /link:"" @(211,844) /sn:0 //: /line:"This is the tty. When simulation mode" //: /line:"starts, a tty window will be popped up" //: /line:"corresponding to this device. The device" //: /line:"may be accessed through the simulated CPU" //: /line:"by reading or writing the addresses indicated" //: /line:"by the dip switches TTYSTATUS and TTYDATA." //: /end nor g70 (.I0(!_ldhmdr), .I1(!_ldmdr), .Z(w)); //: @(874,280) /sn:0 /R:3 /w:[ 3 0 1 ] buf g22 (.I(DATA), .Z(w4)); //: @(574,165) /sn:0 /w:[ 9 0 ] register mar (.Q(mar), .D(w43), .EN(w46), .CLR(_CLR), .CK(CK)); //: @(363,307) /w:[ 0 0 0 17 13 ] //: input g0 (CK) @(60,436) /sn:0 /w:[ 17 ] mux g26 (.I0(w9), .I1(DATA), .S(!_ldpc), .Z(w19)); //: @(188,204) /sn:0 /w:[ 0 15 5 0 ] nor g35 (.I0(!_incpc), .I1(!_ldpc), .Z(w14)); //: @(244,129) /sn:0 /w:[ 0 0 0 ] //: joint g45 (mdrin) @(559, 552) /w:[ 2 4 1 -1 ] concat g46 (.I0(w15), .I1(w31), .Z(w27)); //: @(638,667) /sn:0 /R:1 /w:[ 3 7 1 ] /dr:0 //: joint g82 (_incmar) @(325, 281) /w:[ 1 2 -1 8 ] //: supply0 g66 (w1) @(825,693) /sn:0 /w:[ 1 ] tty tty0 (.TD(TD), .RD(RD), .RTS(RTS), .CTS(CTS), .DSR(DSR), .DTR(DTR)); //: @(414,963) /w:[ 0 1 0 0 0 0 ] //: dip TTYDATA (w40) @(174,765) /R:1 /w:[ 0 ] /st:17 concat g18 (.I0(mdr), .I1(w3), .Z(w2)); //: @(657,246) /sn:0 /R:2 /w:[ 9 1 0 ] /dr:0 //: joint g12 (_rd) @(671, 616) /w:[ 2 1 4 -1 ] //: frame g91 @(45,27) /sn:0 /wi:441 /ht:397 /tx:"Address Resolution" //: supply0 g30 (w21) @(220,65) /sn:0 /w:[ 0 ] //: input g33 (_incpc) @(131,126) /sn:0 /w:[ 1 ] //: supply0 g49 (w24) @(595,544) /sn:0 /w:[ 0 ] endmodule module REG4(SB, _ENA, B, CK, DIN, _ENB, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0A[15:0](31/107) Ti1>B[15:0](79/107) Li0>FUNC[4:0](18/127) Li1>CIN(95/127) Bo0DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0_CLR(86/132) Ti1>CK(37/132) Li0>_incmar(187/353) Bi0>IR[15:0](62/132) Ri0>COUT(314/353) Ri1>_Z(296/353) Ri2>_GT(276/353) Ri3>_LT(258/353) Lo0<_rd(121/353) Lo10 Ti1>0 Bo0<1 Ro0<1 Ro1<0 Ro2<1 Ro3<0 Ro4<1 Ro5<1 ] //: joint g6 (_CLR) @(525, 74) /w:[ 2 4 6 1 ] //: input g69 (_CLR) @(525,61) /sn:0 /R:3 /w:[ 5 ] rom m1 (.A(mp_nxtaddr), .D(w26), .OE(w5)); //: @(368,710) /w:[ 5 1 1 ] //: joint g7 (CK) @(102, 120) /w:[ 16 18 -1 15 ] //: output g53 (_ldmdr) @(701,1017) /sn:0 /w:[ 0 ] //: output g57 (SB) @(766,890) /sn:0 /w:[ 0 ] //: supply0 g9 (w5) @(368,751) /sn:0 /w:[ 0 ] //: output g75 (_LDQH) @(701,1127) /sn:0 /w:[ 1 ] //: input g31 (IR) @(57,70) /sn:0 /w:[ 0 ] mux g20 (.I0(IDATA), .I1(w27), .S(w35), .Z(w12)); //: @(393,390) /sn:0 /R:3 /w:[ 0 0 1 0 ] //: supply0 g15 (w15) @(205,723) /sn:0 /w:[ 1 ] mux g71 (.I0(w45), .I1(w46), .S(w47), .Z(SB)); //: @(725,890) /sn:0 /R:1 /w:[ 0 0 0 1 ] //: joint g67 (w6) @(151, 65) /w:[ 2 -1 1 4 ] //: supply1 g39 (w19) @(421,649) /sn:0 /w:[ 1 ] mux g68 (.I0(w41), .I1(w39), .S(w43), .Z(SA)); //: @(725,818) /sn:0 /R:1 /w:[ 0 1 0 0 ] //: joint g48 (IDATA) @(540, 654) /w:[ 2 1 4 -1 ] //: supply0 g43 (w20) @(455,1042) /sn:0 /w:[ 1 ] //: comment g62 /dolink:0 /link:"" @(370,940) //: /line:"This is the high half" //: /line:"of the microinstruction" //: /line:"memory." //: /end //: supply0 g17 (w23) @(360,367) /sn:0 /w:[ 0 ] nor g25 (.I0(!w55), .I1(!w32), .Z(_SA0)); //: @(890,384) /sn:0 /R:2 /w:[ 13 0 0 ] mux g73 (.I0(w7), .I1(w49), .S(w42), .Z(FUNC)); //: @(725,956) /sn:0 /R:1 /w:[ 1 1 0 1 ] //: joint g29 (ww) @(945, 358) /w:[ 2 4 1 -1 ] //: frame g88 @(176,317) /sn:0 /wi:311 /ht:239 /tx:"Microcode Next Address Generation" //: output g52 (_ldmar) @(701,1007) /sn:0 /w:[ 1 ] //: supply0 g42 (w30) @(455,678) /sn:0 /w:[ 1 ] //: joint g63 (CK) @(264, 771) /w:[ 2 4 -1 1 ] //: output g83 (_incmar) @(701,1177) /sn:0 /w:[ 0 ] //: output g74 (_LDQL) @(701,1117) /sn:0 /w:[ 1 ] //: supply1 g14 (w21) @(186,641) /sn:0 /w:[ 0 ] //: joint g5 (mp_nxtaddr) @(331, 709) /w:[ 4 6 -1 3 ] //: output g56 (SA) @(766,818) /sn:0 /w:[ 1 ] //: output g44 (_incpc) @(701,997) /sn:0 /w:[ 1 ] //: output g47 (IDATA) @(690,654) /sn:0 /w:[ 3 ] concat g79 (.I0(w32), .I1(ww), .I2(w55), .I3(w4), .Z(w3)); //: @(1030,353) /sn:0 /w:[ 3 3 0 1 1 ] /dr:0 //: joint g80 (CK) @(102, 276) /w:[ 12 14 -1 11 ] //: comment g84 /dolink:0 /link:"" @(694,22) //: /line:"This is a trival example of an" //: /line:"instruction unit. The mpc register" //: /line:"contains the micro-instruction" //: /line:"program counter, and the two" //: /line:"registers on the data out of ROMs" //: /line:"m1 and m2 are the current micro-" //: /line:"instructions. Note that since these" //: /line:"are two separate registers the a" //: /line:"single cycle jump delay." //: /end //: input g24 (_LT) @(1168,345) /sn:0 /R:2 /w:[ 0 ] //: input g21 (COUT) @(1163,375) /sn:0 /R:2 /w:[ 1 ] //: output g36 (_LDDATA) @(690,734) /sn:0 /w:[ 0 ] //: comment g85 /dolink:0 /link:"" @(16,131) /sn:0 //: /line:"This block" //: /line:"decodes" //: /line:"insructions" //: /line:"producing" //: /line:"a map index," //: /line:"register" //: /line:"numbers," //: /line:"a function" //: /line:"code and a" //: /line:"condition" //: /line:"code." //: /end //: output g41 (spc) @(701,1067) /sn:0 /w:[ 1 ] //: input g23 (_Z) @(1164,361) /sn:0 /R:2 /w:[ 0 ] //: output g81 (_ldhmdr) @(701,1157) /sn:0 /w:[ 0 ] //: output g60 (_wrt) @(701,1057) /sn:0 /w:[ 1 ] //: output g54 (_ldpc) @(701,1027) /sn:0 /w:[ 1 ] //: supply1 g40 (w24) @(421,1016) /sn:0 /w:[ 1 ] //: joint g70 (_CLR) @(385, 74) /w:[ 7 -1 8 10 ] //: output g46 (BOP) @(690,694) /sn:0 /w:[ 1 ] //: output g45 (AOP) @(690,684) /sn:0 /w:[ 1 ] register g35 (.Q(w8), .D(w10), .EN(w20), .CLR(w24), .CK(CK)); //: @(436,1087) /sn:0 /R:1 /w:[ 1 0 0 0 0 ] //: input g26 (_GT) @(1165,323) /sn:0 /R:2 /w:[ 0 ] concat g0 (.I0(w14), .I1(IDATA), .I2(w18), .I3(_ldir), .I4(AOP), .I5(BOP), .I6(CIN), .I7(_CLQ), .I8(_LDQ), .I9(_LDDATA), .I10(_ldopr), .I11(_WA), .I12(w39), .I13(w46), .Z(mp_wrd0)); //: @(483,709) /sn:0 /R:2 /w:[ 0 5 0 0 0 0 1 1 1 1 0 1 0 1 1 ] /dr:0 //: joint g22 (w55) @(879, 300) /w:[ 3 4 6 -1 ] concat g66 (.I0(w6), .I1(w25), .Z(IR)); //: @(85,70) /sn:0 /R:2 /w:[ 0 1 1 ] /dr:0 //: output g82 (_rdpc) @(701,1167) /sn:0 /w:[ 1 ] mux g18 (.I0(!w55), .I1(!w4), .I2(w55), .I3(ww), .I4(w32), .I5(_SA), .I6(_SA0), .I7(w28), .S(w44), .Z(w35)); //: @(797,311) /sn:0 /R:3 /w:[ 5 0 7 5 5 1 1 1 0 0 ] add g12 (.A(mp_nxtaddr), .B(w15), .S(w27), .CI(w21), .CO(w22)); //: @(221,657) /sn:0 /R:2 /w:[ 9 0 5 1 0 ] //: joint g33 (w55) @(911, 353) /w:[ -1 9 10 12 ] //: joint g30 (CK) @(102, 511) /w:[ 9 10 20 -1 ] //: output g49 (CIN) @(690,704) /sn:0 /w:[ 0 ] endmodule module OPRDEC(SB, SA, FUNC, OPR, OM2, MAP, OM1, COND, IR); //: interface /sz:(192, 126) /bd:[ Ti0>OPR[7:0](148/192) Ti1>IR[7:0](19/192) Bo0DIN[15:0](53/108) Li0>CK(118/138) Li1>SA[3:0](17/138) Li2>SB[3:0](33/138) Li3>_CLR(51/138) Li4>_ENA(66/138) Li5>_ENB(82/138) Li6>_WA(101/138) Bo013 Li0>13 Li1>13 Li2>1 Li3>1 Li4>13 Li5>13 Li6>13 Bo0<13 Bo1<13 ] demux g19 (.I(w15), .E(!_ENB), .Z0(!w17), .Z1(!w10), .Z2(!w25), .Z3(!w46)); //: @(222,585) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] //: joint g27 (CK) @(512, 403) /w:[ 4 10 3 -1 ] //: input g32 (_ENA) @(33,453) /sn:0 /w:[ 1 ] //: joint g6 (w50) @(690, 520) /w:[ 6 8 5 -1 ] //: joint g38 (B) @(880, 435) /w:[ 5 6 8 -1 ] //: input g9 (SA) @(31,525) /sn:0 /w:[ 1 ] //: joint g7 (w49) @(142, 623) /w:[ 2 12 1 -1 ] //: joint g15 (_CLR) @(465, 359) /w:[ 4 10 3 -1 ] //: joint g31 (DIN) @(853, 156) /w:[ 6 -1 5 8 ] //: joint g39 (B) @(1133, 435) /w:[ 1 2 4 -1 ] demux g17 (.I(w37), .E(!_ENA), .Z0(!w16), .Z1(!w9), .Z2(!w26), .Z3(!w47)); //: @(222,485) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] //: joint g25 (_WA) @(769, 379) /w:[ 6 8 5 -1 ] //: joint g29 (DIN) @(360, 156) /w:[ 2 -1 1 12 ] REG4 RF3 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w47), ._ENB(w46), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(1053, 197) /sz:(109, 138) /p:[ Ti0>7 Li0>7 Li1>7 Li2>7 Li3>1 Li4>1 Li5>7 Li6>7 Bo0<3 Bo1<3 ] concat g5 (.I0(w49), .I1(w15), .Z(SB)); //: @(79,628) /sn:0 /R:2 /w:[ 0 1 0 ] /dr:0 //: joint g14 (_CLR) @(163, 359) /w:[ 2 12 1 -1 ] //: joint g24 (_WA) @(500, 379) /w:[ 4 10 3 -1 ] //: joint g36 (A) @(1085, 467) /w:[ 1 2 4 -1 ] //: joint g23 (_WA) @(279, 379) /w:[ 2 12 1 -1 ] //: output g41 (A) @(1207,467) /sn:0 /w:[ 0 ] REG4 RF1 (.DIN(DIN), .CK(CK), ._WA(_WA), ._ENB(w10), ._ENA(w9), ._CLR(_CLR), .SB(w49), .SA(w50), .B(B), .A(A)); //: @(567, 198) /sz:(106, 138) /p:[ Ti0>11 Li0>11 Li1>11 Li2>1 Li3>1 Li4>11 Li5>11 Li6>11 Bo0<11 Bo1<11 ] //: output g40 (B) @(1205,435) /sn:0 /w:[ 0 ] //: input g22 (CK) @(40,403) /sn:0 /w:[ 0 ] //: joint g26 (CK) @(294, 403) /w:[ 2 12 1 -1 ] //: joint g35 (A) @(832, 467) /w:[ 5 6 8 -1 ] //: input g12 (_CLR) @(41,359) /sn:0 /w:[ 0 ] //: input g18 (_WA) @(40,379) /sn:0 /w:[ 0 ] //: joint g30 (DIN) @(619, 156) /w:[ 4 -1 3 10 ] //: input g33 (_ENB) @(33,555) /sn:0 /w:[ 1 ] REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(801, 198) /sz:(107, 138) /p:[ Ti0>9 Li0>9 Li1>9 Li2>9 Li3>1 Li4>1 Li5>9 Li6>9 Bo0<7 Bo1<7 ] endmodule module main; //: root_module wire w32; //: /sn:0 {0}(589,382)(659,382){1} wire [3:0] w45; //: /sn:0 {0}(589,142)(659,142){1} wire [3:0] w46; //: /sn:0 {0}(589,157)(659,157){1} wire w56; //: /sn:0 {0}(589,324)(659,324){1} wire w38; //: /sn:0 {0}(455,197)(394,197){1} wire [7:0] w51; //: /sn:0 {0}(589,237)(659,237){1} wire w0; //: /sn:0 {0}(455,310)(394,310){1} wire w37; //: /sn:0 {0}(455,212)(394,212){1} wire w34; //: /sn:0 {0}(589,420)(659,420){1} wire w43; //: /sn:0 {0}(455,260)(394,260){1} wire w54; //: /sn:0 {0}(589,289)(659,289){1} wire w58; //: /sn:0 {0}(589,363)(659,363){1} wire [15:0] DATA; //: /dp:5 {0}(727,478)(727,525)(519,525){1} //: {2}(517,523)(517,478){3} //: {4}(515,525)(328,525)(328,478){5} wire w36; //: /sn:0 {0}(455,228)(394,228){1} wire w41; //: /sn:0 {0}(455,149)(394,149){1} wire w35; //: /sn:0 {0}(589,438)(659,438){1} wire w40; //: /sn:0 {0}(455,166)(394,166){1} wire w53; //: /sn:0 {0}(589,275)(659,275){1} wire w59; //: /sn:0 {0}(455,295)(394,295){1} wire w44; //: /sn:0 {0}(455,244)(394,244){1} wire [1:0] w49; //: /sn:0 {0}(589,205)(659,205){1} wire w57; //: /sn:0 {0}(589,344)(659,344){1} wire clk; //: /dp:4 {0}(694,123)(694,66)(494,66){1} //: {2}(490,66)(303,66){3} //: {4}(299,66)(148,66){5} //: {6}(301,68)(301,123){7} //: {8}(492,68)(492,123){9} wire w33; //: /sn:0 {0}(589,400)(659,400){1} wire [1:0] w48; //: /sn:0 {0}(589,189)(659,189){1} wire w52; //: /sn:0 {0}(589,257)(659,257){1} wire w47; //: /sn:0 {0}(589,174)(659,174){1} wire _reset; //: /dp:4 {0}(749,123)(749,31)(543,31){1} //: {2}(539,31)(353,31){3} //: {4}(349,31)(154,31){5} //: {6}(351,33)(351,123){7} //: {8}(541,33)(541,123){9} wire w42; //: /sn:0 {0}(455,279)(394,279){1} wire [4:0] w50; //: /sn:0 {0}(589,219)(659,219){1} wire w39; //: /sn:0 {0}(455,181)(394,181){1} wire w55; //: /sn:0 {0}(589,306)(659,306){1} //: enddecls //: comment g8 /dolink:1 /link:"@C/menagerie.gm" @(17,366) /sn:0 //: /line:"* Mikrocode/Makrocode Definitionen" //: /end //: joint g4 (DATA) @(517, 525) /w:[ 1 2 4 -1 ] //: comment g13 /dolink:0 /link:"" @(17,448) /sn:0 //: /line:"Schaltungs-\"Highlights\":" //: /end //: joint g3 (_reset) @(541, 31) /w:[ 1 -1 2 8 ] //: joint g2 (clk) @(492, 66) /w:[ 1 -1 2 8 ] //: comment g1 /dolink:0 /link:"" @(17,104) //: /line:"Diese Schaltung realisiert einen" //: /line:"einfachen Mikroprozessor. Ein" //: /line:"Simulationsskript startet es mit" //: /line:"dem \"Animals\"-Spiel sobald die" //: /line:"\"Simulation\"-Taste gedrückt wird." //: /line:"Klicke auf die verschiedenen" //: /line:"Logikblöcke. Die Subschaltungen" //: /line:"kann man mit der '>'-Taste ansehen." //: /line:"Zum Eltern-Modul kehrt man mit" //: /line:"der '<'-Taste zurück. Klicke im" //: /line:"Simulationsmodus auf eine Leitung," //: /line:"um den aktuellen Logikwert zu sehen." //: /line:"Oder erzeuge mit einem Doppelklick" //: /line:"einen neuen Signalverlauf." //: /line:"" //: /line:"Zu dieser Schaltung gehören einige" //: /line:"weitere Dateien im `examples/ex4'" //: /line:"Unterverzeichnis des TkGate" //: /line:"Bibliotheksverzeichnisses. Klicke" //: /line:"auf die Links unten um ihren Inhalt" //: /line:"anzusehen." //: /end //: comment g11 /dolink:1 /link:"@C/menagerie.gss" @(17,406) /sn:0 //: /line:"* Simulatorskript" //: /end //: comment g16 /dolink:1 /link:"#eunit.alu" @(17,510) /sn:0 //: /line:"* ALU" //: /end //: comment g10 /dolink:1 /link:"@C/menagerie.mem" @(17,386) /sn:0 //: /line:"* Datei Hauptspeicherinitialisierung" //: /end IUNIT iunit (._CLR(_reset), .CK(clk), .IR(DATA), .COUT(w35), ._Z(w34), ._GT(w33), ._LT(w32), ._rdpc(w59), ._incmar(w0), ._rd(w44), .spc(w43), ._ldhmdr(w42), ._ldpc(w41), ._ldmar(w40), ._ldmdr(w39), ._incpc(w38), ._rdmdr(w37), ._wrt(w36), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), .SA(w45)); //: @(456, 124) /sz:(132, 353) /p:[ Ti0>9 Ti1>9 Bi0>3 Ri0>0 Ri1>0 Ri2>0 Ri3>0 Lo0<0 Lo1<0 Lo2<0 Lo3<0 Lo4<0 Lo5<0 Lo6<0 Lo7<0 Lo8<0 Lo9<0 Lo10<0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 ] //: joint g6 (_reset) @(351, 31) /w:[ 3 -1 4 6 ] //: comment g7 /dolink:0 /link:"" @(20,17) /sn:0 //: /line:"Dies ist der" //: /line:"Resetschalter." //: /end //: comment g9 /dolink:0 /link:"" @(23,54) //: /line:"Dies ist der" //: /line:"Systemtakt." //: /line:" " //: /end //: comment g15 /dolink:1 /link:"#iunit.mpc" @(17,487) /sn:0 //: /line:"* Mikroprogrammzähler" //: /end MEMORY memory (._CLR(_reset), .CK(clk), ._incmar(w0), ._rdpc(w59), ._ldhmdr(w42), .spc(w43), ._rd(w44), ._wrt(w36), ._rdmdr(w37), ._incpc(w38), ._ldmdr(w39), ._ldmar(w40), ._ldpc(w41), .DATA(DATA)); //: @(268, 124) /sz:(125, 353) /p:[ Ti0>7 Ti1>7 Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Ri5>1 Ri6>1 Ri7>1 Ri8>1 Ri9>1 Ri10>1 Bt0=5 ] //: comment g17 /dolink:1 /link:"#memory.m1" @(17,531) /sn:0 //: /line:"* Hauptspeicher" //: /end EUNIT eunit (._CLR(_reset), .CK(clk), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .SA(w45), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), ._LT(w32), ._GT(w33), ._Z(w34), .COUT(w35), .DATA(DATA)); //: @(660, 124) /sz:(128, 353) /p:[ Ti0>0 Ti1>0 Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Li6>1 Li7>1 Li8>1 Li9>1 Li10>1 Li11>1 Li12>1 Li13>1 Lo0<1 Lo1<1 Lo2<1 Lo3<1 Bt0=0 ] //: comment g14 /dolink:1 /link:"#memory.tty0" @(17,468) /sn:0 //: /line:"* TTY Gerät" //: /end //: joint g5 (clk) @(301, 66) /w:[ 3 -1 4 6 ] clock g0 (.Z(clk)); //: @(135,66) /sn:0 /w:[ 5 ] /omega:300 /phi:0 /duty:50 //: comment g12 /dolink:1 /link:"@C/menagerie.map" @(17,426) /sn:0 //: /line:"* Symbol Map" //: /end //: switch reset (_reset) @(137,31) /sn:0 /w:[ 5 ] /st:1 //: comment g18 /dolink:1 /link:"#memory.PC" @(17,551) /sn:0 //: /line:"* Programmzähler" //: /end endmodule module EUNIT(_CLR, _LDDATA, SB, SA, BOP, AOP, _LDQ, _GT, _Z, _WA, _CLQ, CK, DATA, _LT, FUNC, _LDQH, _LDQL, CIN, IDATA, COUT, _DOUT); //: interface /sz:(128, 353) /bd:[ Ti0>_CLR(89/128) Ti1>CK(34/128) Li0>_DOUT(239/353) Li1>_LDQL(220/353) Li2>_LDQH(200/353) Li3>_LDDATA(182/353) Li4>SA[3:0](18/353) Li5>CIN(165/353) Li6>_LDQ(150/353) Li7>_CLQ(133/353) Li8>IDATA[7:0](113/353) Li9>FUNC[4:0](95/353) Li10>BOP[1:0](81/353) Li11>AOP[1:0](65/353) Li12>_WA(50/353) Li13>SB[3:0](33/353) Lo0<_LT(258/353) Lo1<_GT(276/353) Lo2<_Z(296/353) Lo31 Li0>0 Li1>1 Li2>1 Li3>3 Li4>0 Li5>3 Li6>0 Bo0<1 Bo1<1 ] tran g39(.Z(w12), .I(w1[15:8])); //: @(678,679) /sn:0 /R:3 /w:[ 0 7 8 ] /ss:0 //: joint g48 (w1) @(844, 676) /w:[ 1 2 4 -1 ] register QL (.Q(QL), .D(w8), .EN(w9), .CLR(w10), .CK(CK)); //: @(620,829) /w:[ 1 0 0 0 7 ] nor g43 (.I0(!_LDQL), .I1(!_LDQ), .Z(w9)); //: @(706,783) /sn:0 /R:3 /w:[ 0 7 1 ] ALU alu (.B(w31), .A(w38), .CIN(CIN), .FUNC(FUNC), .OUT(w1), .COUT(COUT), ._LT(_LT), ._GT(_GT), ._Z(_Z)); //: @(500, 523) /sz:(107, 127) /sn:0 /p:[ Ti0>1 Ti1>1 Li0>1 Li1>1 Bo0<9 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] //: output g29 (_LT) @(642,575) /sn:0 /w:[ 0 ] //: input g25 (FUNC) @(475,541) /sn:0 /w:[ 0 ] bufif0 g17 (.Z(DATA), .I(w1), .E(_DOUT)); //: @(906,676) /sn:0 /cpc:1 /w:[ 13 0 0 ] register QH (.Q(QH), .D(w2), .EN(w7), .CLR(w10), .CK(CK)); //: @(761,855) /w:[ 1 1 1 3 9 ] //: joint g42 (CK) @(537, 829) /w:[ 6 -1 5 8 ] //: supply0 g14 (w30) @(299,394) /sn:0 /w:[ 0 ] //: joint g5 (w0) @(463, 316) /w:[ 2 1 -1 4 ] //: joint g47 (DATA) @(959, 676) /w:[ 1 2 12 -1 ] //: joint g44 (_LDQ) @(708, 739) /w:[ 2 -1 1 4 ] //: joint g21 (w35) @(486, 418) /w:[ 2 -1 4 1 ] //: input g24 (_LDQH) @(808,771) /sn:0 /w:[ 1 ] //: joint g36 (w8) @(771, 710) /w:[ -1 2 1 4 ] //: input g23 (_LDQL) @(677,764) /sn:0 /w:[ 1 ] //: joint g41 (CK) @(195, 409) /w:[ -1 1 2 4 ] //: joint g40 (w10) @(669, 809) /w:[ 2 -1 4 1 ] //: input g26 (CIN) @(473,618) /sn:0 /w:[ 0 ] mux g35 (.I0(w12), .I1(w8), .S(_LDQ), .Z(w2)); //: @(761,739) /sn:0 /w:[ 1 5 3 0 ] nor g45 (.I0(!_LDQH), .I1(!_LDQ), .Z(w7)); //: @(840,809) /sn:0 /R:3 /w:[ 0 9 0 ] //: joint g46 (_LDQ) @(708, 757) /w:[ 6 5 8 -1 ] //: joint g0 (DATA) @(864, 437) /w:[ 3 4 6 -1 ] //: joint g22 (DATA) @(608, 437) /w:[ 7 -1 8 10 ] mux g18 (.I0(w21), .I1(DATA), .I2(w35), .I3(w28), .S(BOP), .Z(w31)); //: @(614,481) /sn:0 /w:[ 3 11 3 0 1 0 ] //: input g12 (IDATA) @(296,423) /sn:0 /w:[ 1 ] //: output g30 (COUT) @(642,592) /sn:0 /w:[ 0 ] //: input g49 (_DOUT) @(908,642) /sn:0 /R:3 /w:[ 1 ] endmodule tkgate-2.0-b10/locale/de/examples.18/ex5/menagerie.gss000644 001751 001751 00000001423 07311226664 023064 0ustar00hansenhansen000000 000000 # # This is the simulator script for the menagerie cpu example. It # is registered to run automatically when the example is simulated. # # # Initialize the memories with the data in the menagerie.mem file. # The menagerie.mem file was compiled using gmac from the menagerie.gm # file. # load "menagerie.mem" # # Set the zoom factor for the scope. This command will zoom out # three steps to show a larger time range. # zoom 3 # # Command such as these can be uncommented to set probes or # breakpoints. # #probe clk #break iunit.extra==8'h15 # # Set the reset (active low) line to '0', step two clocks and # then set the reset line back to '1'. This sequence resets # the cpu. # set reset 1'b0 clock +2 set reset 1'b1 # # Start simulating the circuit in continous mode. # run tkgate-2.0-b10/locale/de/examples.18/ex5/menagerie.gm000644 001751 001751 00000132563 07311226664 022705 0ustar00hansenhansen000000 000000 // // Copyright (C) 1987-2000 by Jeffery P. Hansen // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. // // Last edit by hansen on Fri Dec 1 14:34:44 2000 // // Microcode memory bank declarations microcode bank[31:0] iunit.m1; microcode bank[63:32] iunit.m2; map bank[7:0] iunit.map; macrocode bank[7:0] memory.m1; // Microcode field declarations // // Microcode branching. mpcop specifies the basic operation. // field mpcop[1:0]={ next=0, // Increment mpc reinit=1, // Restart CPU jmap=2, // Jump from map value jump=3 // Jump from condition }; // // Specifies the condition on which to jump if mpcop is "jump". // field mpccond[12:10]={ jne=0, // Jump if not equal jcarry=1, // Jump on carry jeq=2, // Jump if equal jlt=3, // Jump if less than jgt=4, // Jump if greater than jle=5, // Jump if less than or equal jge=6, // Jump if greater than or equal jmp=7 // Jump always }; // // Address to jump to if mpcop is "jump" and condition specified // by mpccond is true. This field can not be used at the same // time as the idata field. // field mpcaddr[9:2]; // // Specifies 8 bits of data to be used by the EUNIT. This field // can not be used on jump microinstructions. // field idata[9:2]; // // Specifies the A and B operands of the ALU. // // qreg Use Q register // din Use data in // idata Use idata field from microinstruction // reg Use register file // field aop[15:14]={qreg=0, din=1, idata=2, reg=3}; field bop[17:16]={qreg=0, din=1, idata=2, reg=3}; field ~ldir[13]; // Load instruction register field cin[18]; // Carry in field ~clq[19]; // Clear Q register field ~ldq[20]; // 16-bit load of Q register field ~lddata[21]; // Load EUNIT data from external bus field ~ldopr[22]; // Load operand register field ~wa[23]; // Write register file on SA field sa[27:24]; // Register address A field sb[31:28]; // Register address B // // These fields specify the ALU function. // field ALU_FUNC[36:32]; field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3}; field ALU_BCOMP[32]; field ALU_AZERO[33]; field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7}; field ~incpc[37]; // Increment PC field ~ldmar[38]; // Load MAR field ~ldmdr[39]; // Load MDR field ~ldpc[40]; // Load PC field ~rd[41]; // Read main memory field ~rdmdr[42]; // Read MDR onto external data bus field ~wrt[43]; // Write main memory field spc[44]; // Address main memory from PC field ~isa[45]; // Use sa address from macro instruction field ~isb[46]; // Use sb address from macro instruction field ~ifunc[47]; // Use function code from macro instruction field ~icond[48]; // Use branch condition from macro instruction field ~ldql[49]; // 8-bit load of lower half of Q register field ~ldqh[50]; // 8-bit load of upper half of Q register field ~dout[51]; // Output EUNIT data to external bus field ~ldcc[52]; // Load condition code register field ~ldhmdr[53]; // Load mdr from high byte of data bus field ~rdpc[54]; // Read PC onto external bus field ~incmar[55]; // Increment mar (can't use with incpc) field extra[63:56]; // Extra bits ////////////////////////////////////////////////////////////////////// // // +-+-+-+-+-+-+-+-+ // |7|6|5|4|3|2|1|0| // +-+-+-+-+-+-+-+-+ // // Basic instruction types are encoded by the high two bits of the // first byte of the instruction. For certain types (e.g., ALU // types) some bits are masked when forming the map address. Bits // contributing to the map vector are marked with a *. // // Move Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 1 1 s|a a|b b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // s = size (1 = byte, 0 = word) // aa = operand mode 1 // bb = operand mode 2 // // Single operand instruction (push, pop, call, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0| op |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // // Branch instruction (jmp, jne, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|cond |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * // // // ALU Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1| func |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * // // func = ALU function // a = operand mode // // Other instructions // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0| op |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15; operands basic { %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands runiop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; #1 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands wuniop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; // // Operands for move instructions // operands movoprs { %1,%2 = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; %1,(%2) = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; %1,#3(%2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; %1,(#2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),%2 = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#2 = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),(%2) = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#3(%2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; (%1),(#2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; #1(%2),%3 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#3 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; #1(%2),(%3) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; }; #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),%2 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#2 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; (#1),(%2) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),(#2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|1 1 1 1 1|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op nop { map nop : 0x3e; +0=0x3e; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op halt { map halt : 0x0; +0=0; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 1|0| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op cmp { map cmp_rr : 0x2; map cmp_ri : 0x3; +0[7:1]=0x1; operands basic; }; // Generic branch operation // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|x x x|b b| |0 0 0 0| reg1 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // br #7, loop // // Jump always to loop. 7 is a code indicating the condition always. // op jp { map br_r : 0xa0; map br_i : 0xa1; map br_d : 0xa2; map br_x : 0xa3; +0[7:5] = 0x5; operands { #1,%2 = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#2 = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; }; }; }; op jne { +0[7:5] = 0x5; +0[4:2] = 0x0; operands runiop; }; op jcarry { +0[7:5] = 0x5; +0[4:2] = 0x1; operands runiop; }; op jeq { +0[7:5] = 0x5; +0[4:2] = 0x2; operands runiop; }; op jlt { +0[7:5] = 0x5; +0[4:2] = 0x3; operands runiop; }; op jgt { +0[7:5] = 0x5; +0[4:2] = 0x4; operands runiop; }; op jle { +0[7:5] = 0x5; +0[4:2] = 0x5; operands runiop; }; op jge { +0[7:5] = 0x5; +0[4:2] = 0x6; operands runiop; }; op jmp { +0[7:5] = 0x5; +0[4:2] = 0x7; operands runiop; }; // Generic ALU operation // // Note this is not a real instruction but is here for illustrative // purposes only. Map entries must be made for each function code // to use this instruction for real. // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|x x x x x|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // alu #0x14, R1, R2 // // Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1. // //op alu { // map alu_rr : 0x40; // map alu_ri : 0x41; // +0[7:6] = 0x1; // operands { // #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; }; // #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; // }; //}; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op add { map alu_rr : 0x68; map alu_ri : 0x69; +0[7:0]=0x68; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 1|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op sub { map alu_rr : 0x6a; map alu_ri : 0x6b; +0[7:0]=0x6a; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mul { map xalu_rr : 0x60; map xalu_ri : 0x61; +0[7:0]=0x60; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op div { map xalu_rr : 0x78; map xalu_ri : 0x79; +0[7:0]=0x78; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mod { map xalu_rr : 0x70; map xalu_ri : 0x71; +0[7:0]=0x70; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|0 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op and { map alu_rr : 0x50; map alu_ri : 0x51; +0[7:0]=0x50; operands basic; }; // Call subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 0|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // call foo, #8 // // This will perform the following actions: // sp = sp - 2 // [sp] = pc // sp = sp - 2 // [sp] = fp // fp = sp // sp = sp+8 // pc = foo // op call { map call_ri : 0x80; map call_ii : 0x81; map call_di : 0x82; map call_xi : 0x83; +0[7:4] = 0x8; operands { #1,%2 = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1 = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; }; }; }; // Return from subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 1 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // ret // // This will perform the following actions: // sp = fp // fp = [sp] // sp = sp + 2 // pc = [sp] // sp = sp + 2 // // op ret { map ret : 0x4; +0=4; operands { - = { +1=0; }; }; }; // Push a word on the stack // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 1|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // pushw R1 // op pushw { map pushw_r : 0x84; map pushw_i : 0x85; map pushw_d : 0x86; map pushw_x : 0x87; +0[7:2]=0x21; operands runiop; }; op movb { map movb_rr : 0xf0; map movb_ri : 0xf1; map movb_rd : 0xf2; map movb_rx : 0xf3; map movb_dr : 0xf8; map movb_di : 0xf9; map movb_dd : 0xfa; map movb_dx : 0xfb; map movb_xr : 0xfc; map movb_xi : 0xfd; map movb_xd : 0xfe; map movb_xx : 0xff; +0[7:4]=0xf; operands movoprs; }; op movw { map movw_rr : 0xe0; map movw_ri : 0xe1; map movw_rd : 0xe2; map movw_rx : 0xe3; map movw_dr : 0xe8; map movw_di : 0xe9; map movw_dd : 0xea; map movw_dx : 0xeb; map movw_xr : 0xec; map movw_xi : 0xed; map movw_xd : 0xee; map movw_xx : 0xef; +0[7:4]=0xe; operands movoprs; }; ///////////////////////////////////////////////////////////////////////////// // // The microcode for the Menagerie CPU begins here. // // The CPU begins executing microinstuctions at address 0. The instructions // in the start block are executed only once. The next block consists of // the instuction fetch sequnce. The multiple labels account for partial // fetches that are done by some of the macrocode routines. // // For macro instructions which have no operands or have only only one operand, // there is usually a plain label for that instruction. For example the // microinstruction labeled 'ret' implements the 'ret' macroinstruction. This // mapping is defined by the 'map ret : 0x4;' line in the operand declaration // for the ret macroinstruction. // // For macro instructions with multiple addressing modes, labels are generally // of the form 'op_??' where each character after the '_' denotes an addressing // mode for an operand. By convension, the characters: // // r register direct // i immediate // d register indirect // x indexed // // are used. // begin microcode @ 0 start: clq; // Q <- 0 idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh; // Q.H <- 1 ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to 'fetch' mpcop=next; fetch: incpc spc rd ldmdr; // mdr <- [PC]; PC++; fetch1: incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; fetch2: mpcop=jmap rdmdr ldopr; // opr <- mdr; jump to opcode mpcop=next; halt: mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; // // Standard ALU operations (add, sub, and, or, etc.) // alu_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; alu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; // // 2-cycle ALU operations (mul, div, mod). These are the same as the alu_?? // ops except the ALU inputs and function code are held for 2 clock cycles // due to the longer delay in computing these functions. // xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg; // Ra (op) Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; xalu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=next ifunc isa isb aop=reg bop=qreg; // Ra (op) Q; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; cmp_rr: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22 isa isb aop=reg bop=reg ldcc; // Ra - Rb; CC; jump to fetch mpcop=next; cmp_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP aop=reg bop=qreg isa ldcc; // Ra - Q; CC; jump to fetch mpcop=next; br_i: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; btest: mpcop=jump mpcaddr=bdojmp icond; // jump to bdojmp if cond mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to fetch mpcop=next; bdojmp: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q, jump to fetch mpcop=next; br_r: mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10 isa aop=reg sb=0 bop=reg ALU_OP=add ldq; // Q <- Ra; jump to btest mpcop=next; br_d: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; br_x: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; call_ii: // Push the PC aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa extra=0x11; // SP-2 -> mar; SP = SP - 2; rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq; // Q = PC+4 ALU_AZERO ALU_OP=add bop=qreg dout ldmdr; // Q.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr; // Q.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; mpcop=next; // Push the FP aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa; // SP-2 -> mar; SP = SP - 2; ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr; // FP.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldhmdr; // SP.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; aop=reg sa=0xe bop=reg sb=0xf ALU_AZERO ALU_OP=add wa; // FP <- SP // Dec SP incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=qreg ALU_OP=add wa; // SP = SP + Q // PC = branch address incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q mpcop=next; call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_di: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; ret: ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12; // SP <- FP; mar <- FP; aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr; // SP <- SP+4; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr; // FP <- Q; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch1 ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q; jump fetch1 incpc spc rd ldmdr; // mdr <- [PC]; PC++; pushw_d: mpcop=next; pushw_x: mpcop=next; pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Rb.L; wrt; // [mar] <- mdr; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; pushw_i: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Q.L; wrt; // [mar] <- mdr; aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add isa isb wa aop=reg bop=reg ldcc extra=1 incpc spc rd ldmdr; // Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql; // Q.L <- Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata ALU_OP=add ldqh incpc spc rd ldmdr; // Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++; ALU_AZERO ALU_OP=add bop=qreg isa wa incpc spc rd ldmdr rdmdr ldir; // Ra <- Q; mdr <- [PC]; PC++; ir <- mdr; movw_ri: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_ri:incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0; // Q.H = 0; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mbrd: rd ldmdr; // mdr <- [mar] mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa; // Ra <- mdr ALU_OP=add idata=0 bop=idata aop=reg isa ldcc; // CC movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mwrd: rd ldmdr incmar; // mdr <- [mar++] rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql; // Q.L <- mdr; mdr <- [mar++] lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add isa wa ldcc; // Ra <- Q; CC mpcop=next; movb_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mbrd isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q; movw_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mbdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mwdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb.L wrt; // [mar] <- mdr; isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mbdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mwdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xx: mpcop=next extra=7; movb_xx: mpcop=next extra=7; movw_xd: mpcop=next extra=7; movb_xd: mpcop=next extra=7; movw_dd: mpcop=next extra=7; movb_dd: mpcop=next extra=7; movw_dx: mpcop=next extra=7; movb_dx: mpcop=next extra=7; mpcop=next extra=7; movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar; // mar <- Ra _mwdi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L wrt; // [mar] <- mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra _mbdi: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q movb_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q nop: mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15; mpcop=next; end ///////////////////////////////////////////////////////////////////////////// // // General notes on assembler // Registers are not saved accross function calls unless explicitly saved. // Functions return values in R1. // The register R0 is a special "always 0" register. Writing to R0 will have no // effect other than to set condition codes. // // begin macrocode @ 0x100 ttydata: .symbol 0x11 // tty data in/out register ttystatus: .symbol 0x10 // tty status register // // Nodes have the format (note that pointers are two bytes): // // struct node { // struct node *yes_b; // struct node *no_b; // char text[100]; // }; // nsize: .symbol 104 // Size of a tree node. That is "sizeof(struct node)". yes_b: .symbol 0 // Pointer to yes side no_b: .symbol 2 // Pointer to no side text: .symbol 4 // Text of node (animal name or question) // // Execution starts here. // start: movw SP, 0 // Initialize stack pointer movw FP, 0 // Initialize frame pointer call main // Call main program sdone: jmp sdone // Infinite loop when main ends //////////////////// // main() // .proc main movw R13, mend // Use R13 as a sort of heap pointer pushw welcome // Push the "Welcome to" message call printf // Print the message add SP,2 // Restore stack pointer movw (root),top_node // Initialize root node movw (known),1 // Know one animal loop: pushw think // Push the "Think of an animal..." message call printf // Print the message add SP,2 // Restore stack pointer movw R1, (known) // Put number of known animals in R1 pushw R1 // Push that number on the stack pushw numk // Push the "I know %d animals" message call printf // Call printf to print message add SP,4 // Restore stack movw R1,(root) // Put the root pointer in R1 pushw R1 // Push the pointer on the stack call find_animal // Ask questions to find animal add SP,2 // Restore the stack movw (root),R1 // Save new root jmp loop // Go back and guess another animal ret // Return to call (actually we should never get here) .end //////////////////// // find_animal(p) Find the animal. p is the root node in question tree // .proc find_animal tree: .symbol -2 // Local variable for tree pointer sub SP,2 // Allocate space for local variables movw R1, 4(FP) // Get the pointer to top node movw tree(FP),R1 // Store it in "tree" movw R2,yes_b(R1) // Get pointer in "yes" branch of tree cmp R2,0 // Compare against 0 jne get_response // If not 0, then treat as question node pushw R1 // Push pointer to top node call get_final // As the final question, and insert new node if necessary add SP,2 // Restore stack movw tree(FP),R1 // Save new root node in "tree" jmp done // All done, go to final cleanup get_response: movw R1,tree(FP) // Put current node pointer in R1 movw R4,R1 // R4 = R1 add R4,text // Add offset to make R4 pointer to question pushw R4 // Push text of question call print // Print question in tree node add SP,2 // Restore stack pushw qprompt // Push "?" prompt call print // Print the "? " add SP,2 // Restore stack pushw buf // Push address of buffer in which to get response call gets // Read response from user add SP,2 // Restore stack pushw buf // Push users response on stack pushw yes // Push "yes" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_yes // If so, user answered "yes", goto say_yes pushw buf // Push users response on stack pushw no // Push "no" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_no // If so, user answered "no", goto say_no pushw yesno // Push the "yes or no" error message call print // Print error message add SP,2 // Restore stack jmp get_response // Go back and ask again say_yes: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,yes_b(R1) // Put "yes" branch pointer in R2 pushw R2 // Push the yes branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw yes_b(R2),R1 // Update the "yes" branch jmp done // Finish up and prepare to return to caller say_no: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,no_b(R1) // Put "no" branch pointer in R2 pushw R2 // Push the no branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw no_b(R2),R1 // Update the "no" branch jmp done // Finish up and prepare to return to caller done: movw R1,tree(FP) // Put new root node in R1 ret // Return to caller .end //////////////////// // get_final(p) Ask final question (at node p), and update tree if necessary. // .proc get_final tree: .symbol -2 // Local variable for tree pointer animal_node: .symbol -4 // Local variable for new animal node pointer discrim_node: .symbol -6 // Local variable for new question node pointer sub SP,6 // Allocate space for local variables get_response: movw R1, 4(FP) // Get pointer to current node movw tree(FP),R1 // Save it in the 'tree' variable movw R1, 4(FP) // Put pointer to tree in R1 add R1,text // Advance R1 to animal name text pushw R1 // Push pointer to animal name on stack pushw isita // Push the "is it a..." string pointer call printf // Print the final question add SP,4 // Restore stack pushw buf // Push buffer for response call gets // Get the response add SP,2 // Restore the stack pushw buf // Push response on stack pushw yes // Push "yes" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq win // If so, we guessed the animal pushw buf // Push response on stack pushw no // Push "no" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq loose // If so, we did not guess the animal pushw yesno // Push the "yes or no" error message call print // Print it add SP,2 // Restore stack jmp get_response // Go back and ask again win: pushw winmsg // Push the (computer) win message call printf // Print it add SP,2 // Restore stack jmp done // All done, go finish up and return loose: pushw loosemsg // Push the (computer) loose message call printf // Print it add SP,2 // Restore stack pushw nsize // Push number of bytes in a node call malloc // Allocate memory for new animal node add SP,2 // Restore stack movw animal_node(FP),R1 // Put address of new node in animal_node movw yes_b(R1),0 // Intialize yes branches movw no_b(R1),0 // Intialize no branches add R1,text // Move R1 to point to text area pushw R1 // Push text buffer call gets // Get animal name add SP,2 // Restore stack movw R1,tree(FP) // Put pointer to exiting node in R1 add R1,text // Advance to the text field pushw R1 // Push pointer to old animal name movw R1,animal_node(FP) // Put pointer to new node in R1 add R1,text // Advance to the text field pushw R1 // Push new animal name on stack pushw dscrim // Push "what is difference" question call printf // Print the question add SP,6 // Restore pointer pushw nsize // Allocate memory for discrimination node call malloc // Allocate memory for new discrimination node add SP,2 // Restore stack movw discrim_node(FP),R1 // Put address of new node in discrim_node add R1,text // Advance pointer to text field of discrimination node pushw R1 // Push pointer to text buffer to input question call gets // Input the question add SP,2 // Restore pointer movw R1, (known) // Put number of known animals in R1 add R1,1 // Increment R1 movw (known),R1 // Store number of known animals back in "known" L1: movw R1,animal_node(FP) // Put pointer to new animal node in R1 add R1,text // Advance R1 to the text field pushw R1 // Push new animal name on stack pushw which // Push the "..correct answer for..." message. call printf // Print the message add SP,4 // Restore stack pushw buf // Push text buffer on stack call gets // Input a "yes" or "no" add SP,2 // Restore stack pushw buf // Push user response pushw yes // Push string "yes" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L2 // If so, goto L2. New animal is on "yes" branch pushw buf // Push user response pushw no // Push string "no" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L3 // If so, goto L3. New animal is on "no" branch pushw yesno // Push the "yes or no" error message call printf // Print it add SP,2 // Restore stack jmp L1 // Go back and ask again // // Insert new animal on yes branch of new question // L2: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R3 // Set yes branch to new node movw no_b(R1),R2 // Set no branch to old node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return // // Insert new animal on no branch of new question // L3: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R2 // Set yes branch to old node movw no_b(R1),R3 // Set no branch to new node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return done: movw R1,tree(FP) // Put tree pointer into return register R1 ret // Return to caller .end //////////////////// // malloc(n) -> p Allocate n bytes and return address in R1. Allocated memory // can not be freed. // .proc malloc movw R2, 4(FP) // Get number of bytes movw R1,R13 // Pointer to block of memory add R13,R2 // Update heap pointer ret .end //////////////////// // print(s) Print the string s // .proc print movw R1, 4(FP) // Get parameter (string address) loop: movb R2, (R1) // Put character R1 is pointing to in R2 jeq done // If it was a 0, this is the end of the string movb (ttydata),R2 // Move char to the tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Move pointer to next char jmp loop // Go back and print more done: ret .end //////////////////// // printf(s,...) Print the format string // .proc printf ptr: .symbol -2 // Local var for string pointer arg: .symbol -4 // Local var for argument pointer sub SP,4 // Allocate 4 bytes for local variables movw R3,FP // Assign R3 and add an offset so that it points add R3,6 // to the argument after the control string movw R1, 4(FP) // Put the control string pointer in R1 loop: movb R2, (R1) // Get the next char from control string jeq done // If it was a 0, this is the end of the string cmp R2, '%' // See if it is the '%' character jne cout // If not goto cout, and simply print it add R1,1 // Advance the string pointer movb R2,(R1) // Get the next char add R1,1 // Advance the string pointer again //switch (R2) L1: cmp R2,'s' // See if this is a "%s" conversion jne L2 // If not, goto L2 // case 's' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get address of string (from arguments) to print pushw R2 // Push it on the stack call print // Print the string add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more L2: cmp R2,'d' // See if this is a "%d" conversion jne loop // If not, ignore unknown conversion // case 'd' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get number (from arguments) to print pushw R2 // Push it on the stack call nprint // Go print the decimal number add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more cout: movb (ttydata),R2 // Put character in tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Advance to next char in control string jmp loop // Go back and print more done: ret // All done, return to caller .end //////////////////// // nprint(d) Print the number d in decimal // .proc nprint movw R1, 4(FP) // Move argument value to R1 jeq zprint // If it was zero, goto zprint pushw R1 // Push value to print on stack call nprint_aux // Call aux function to print number add SP,2 // Restore stack pointer ret // All done, return to caller zprint: movb (ttydata), '0' // Put the ascii value of '0' in tty data register movb (ttystatus), #1 // Signal tty controller to print character ret // All done, return to caller .end //////////////////// // nprint_aux(d) Print the number d in decimal (but prints nothing if d is zero) // .proc nprint_aux digit: .symbol -2 // Digit to print sub SP, 2 // Allocate space for local variables movw R1, 4(FP) // Get argument jeq done // If zero, return // To print the number n we compute // R2 = n / 10, and // R3 = n % 10 // We can then recursively call nprint_aux to print all // but the lowest digit, then print the lowest digit ourselves // movw R2, R1 // R2 = R1 div R2, 10 // R2 = R2 / 10 movw R3, R1 // R3 = R1 mod R3, 10 // R3 = R3 % 10 movw digit(FP),R3 // save lowest digit value pushw R2 // Push the higher digits call nprint_aux // Recursively call ourselves to print them add SP,2 // Restore stack pointer movw R3,digit(FP) // Restore digit value add R3, '0' // Add ascii for '0' to get ascii for digit movb (ttydata),R3 // Put char in tty data register movb (ttystatus),#1 // Signal tty controller to print character done: ret // All done, resturn to caller .end //////////////////// // strcmp(a,b) Compare strings a and b // .proc strcmp movw R2,4(FP) // Get pointer to first string movw R3,6(FP) // Get pointer to second string loop: movb R1,(R2) // Get next char from R2 jeq eos // If end of string, goto eos movb R4,(R3) // Get next char from R3 jeq eos // If end of string, goto eos sub R1,R4 // Compute difference in R1 jne done // If difference was not 0, we are done add R2,1 // Advance to next char in R2 add R3,1 // Advance to next char in R3 jmp loop // Go compare more eos: movb R4,(R3) // Get next char from R3 again (in case R1 was eos) sub R1,R4 // Compute difference in R1 done: ret // Return to caller, result is in R1 .end //////////////////// // gets(b) Reads chars from tty into b. // .proc gets movw R1, 4(FP) // Get pointer to buffer movw R4,R1 // Save starting pointer in R4 // // Poll for a characcter // cwait: movb R2,(ttystatus) // Get ready status and R2, #2 // Test if a char is ready jeq cwait // If not, go back and wait some more movb R3,(ttydata) // Get char from tty data register movb (ttystatus),#2 // Signal char received cmp R3,'\r' // Compare against return char jeq done // Exit if return received cmp R3,'\b' // Compare against backspace char jeq del_char // Delete char if backspace cmp R3,0x7f // Compare against delete char jeq del_char // Delete char if delete character movb (ttydata),R3 // Put char to echo in tty data register movb (ttystatus),#1 // Signal tty controller to print character movb (R1),R3 // Save in buffer add R1,1 // increment pointer jmp cwait // Go back and get another char del_char: cmp R1,R4 // Compare current pointer against start of line jle bell // If already at start of line, ring bell movb R3, 0x7f // Make sure delete char is in R3 sub R1,1 // Decrement pointer movb (ttydata),R3 // Echo backspace movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char bell: movb R3, 7 // Put bell char in R3 movb (ttydata),R3 // Echo bell movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char done: movb (ttydata),'\n' // Output newline movb (ttystatus),#1 // Signal tty controller to print character movb (R1),0 // Put eos in the string we just read ret // Return to caller .end buf: .bss 128 // Buffer for input known: .bss 2 // Number of animals known root: .bss 2 // root of animals tree top_node: .short 0 // Pointer to "yes" node .short 0 // Pointer to "no" node .byte "aardvark",0 // Animal name or question text welcome: .byte "\nWelcome to Animals.\n", 0 think: .byte "\nThink of an animal and I will try to guess what it is.\n", 0 numk: .byte "I currently know %d animals.\n\n", 0 isita: .byte "Is the animal you are thinking of a %s? ",0 yes: .byte "yes",0 no: .byte "no",0 yesno: .byte "Please type 'yes' or 'no'.\n",0 winmsg: .byte "I guessed your animal!!!\n\n",0 loosemsg: .byte "I could not guess your animal. What was your animal? ",0 dscrim: .byte "Enter a question that would distinguish a %s from a %s.\n> ",0 which: .byte "The correct answer for a %s is? ",0 nl: .byte "\n",0 qprompt: .byte "? ",0 mend: end tkgate-2.0-b10/locale/de/examples.18/ex5/menagerie.mem000644 001751 001751 00000020560 07311226664 023051 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 40/ f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 48/ f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 50/ f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 58/ f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 60/ f82000 f82000 d92000 d92000 f7ae008 fa2000 f82000 fa2000 68/ f82000 f83c17 f82000 7bfc1f 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0 a9 0 570/ 66 5 f3 30 11 0 fd 0 578/ 10 0 2 0 3 30 d 0 580/ a9 0 d6 5 3 30 8 0 588/ a9 0 a8 5 3 30 7f 0 590/ a9 0 a8 5 fc 3 11 0 598/ fd 0 10 0 1 0 f8 13 5a0/ 69 10 1 0 bd 0 66 5 5a8/ 2 14 b5 0 c4 5 f1 30 5b0/ 7f 0 6b 10 1 0 fc 3 5b8/ 11 0 fd 0 10 0 1 0 5c0/ bd 0 66 5 f1 30 7 0 5c8/ fc 3 11 0 fd 0 10 0 5d0/ 1 0 bd 0 66 5 fd 0 5d8/ 11 0 a 0 fd 0 10 0 5e0/ 1 0 f9 10 0 0 4 0 66c/ 0 0 0 0 61 61 72 64 674/ 76 61 72 6b 0 a 57 65 67c/ 6c 63 6f 6d 65 20 74 6f 684/ 20 41 6e 69 6d 61 6c 73 68c/ 2e a 0 a 54 68 69 6e 694/ 6b 20 6f 66 20 61 6e 20 69c/ 61 6e 69 6d 61 6c 20 61 6a4/ 6e 64 20 49 20 77 69 6c 6ac/ 6c 20 74 72 79 20 74 6f 6b4/ 20 67 75 65 73 73 20 77 6bc/ 68 61 74 20 69 74 20 69 6c4/ 73 2e a 0 49 20 63 75 6cc/ 72 72 65 6e 74 6c 79 20 6d4/ 6b 6e 6f 77 20 25 64 20 6dc/ 61 6e 69 6d 61 6c 73 2e 6e4/ a a 0 49 73 20 74 68 6ec/ 65 20 61 6e 69 6d 61 6c 6f4/ 20 79 6f 75 20 61 72 65 6fc/ 20 74 68 69 6e 6b 69 6e 704/ 67 20 6f 66 20 61 20 25 70c/ 73 3f 20 0 79 65 73 0 714/ 6e 6f 0 50 6c 65 61 73 71c/ 65 20 74 79 70 65 20 27 724/ 79 65 73 27 20 6f 72 20 72c/ 27 6e 6f 27 2e a 0 49 734/ 20 67 75 65 73 73 65 64 73c/ 20 79 6f 75 72 20 61 6e 744/ 69 6d 61 6c 21 21 21 a 74c/ a 0 49 20 63 6f 75 6c 754/ 64 20 6e 6f 74 20 67 75 75c/ 65 73 73 20 79 6f 75 72 764/ 20 61 6e 69 6d 61 6c 2e 76c/ 20 20 57 68 61 74 20 77 774/ 61 73 20 79 6f 75 72 20 77c/ 61 6e 69 6d 61 6c 3f 20 784/ 0 45 6e 74 65 72 20 61 78c/ 20 71 75 65 73 74 69 6f 794/ 6e 20 74 68 61 74 20 77 79c/ 6f 75 6c 64 20 64 69 73 7a4/ 74 69 6e 67 75 69 73 68 7ac/ 20 61 20 25 73 20 66 72 7b4/ 6f 6d 20 61 20 25 73 2e 7bc/ a 3e 20 0 54 68 65 20 7c4/ 63 6f 72 72 65 63 74 20 7cc/ 61 6e 73 77 65 72 20 66 7d4/ 6f 72 20 61 20 25 73 20 7dc/ 69 73 3f 20 0 a 0 3f 7e4/ 20 0 tkgate-2.0-b10/locale/de/examples.18/ex5/menagerie.map000644 001751 001751 00000012527 07311226664 023054 0ustar00hansenhansen000000 000000 Microcode Symbols (total=57): --------------------------------------- _mbdi 000000b3 _mbdr 0000008d _mbrd 0000007b _mwdi 000000a9 _mwdr 00000091 _mwrd 0000007f alu_ri 0000000d alu_rr 0000000b bdojmp 00000029 br_d 0000002d br_i 00000022 br_r 0000002b br_x 0000002f btest 00000025 call_di 0000004b call_ii 00000031 call_ri 00000049 call_xi 0000004d cmp_ri 0000001d cmp_rr 0000001b fetch 00000005 fetch1 00000006 fetch2 00000007 halt 00000009 movb_dd 000000a4 movb_di 000000b2 movb_dr 0000008c movb_dx 000000a6 movb_rd 0000007a movb_ri 00000075 movb_rr 0000006d movb_rx 00000084 movb_xd 000000a2 movb_xi 000000bc movb_xr 00000097 movb_xx 000000a0 movw_dd 000000a3 movw_di 000000a8 movw_dr 00000090 movw_dx 000000a5 movw_rd 0000007e movw_ri 00000070 movw_rr 0000006b movw_rx 00000088 movw_xd 000000a1 movw_xi 000000b8 movw_xr 0000009b movw_xx 0000009f nop 000000c0 pushw_d 00000058 pushw_i 00000061 pushw_r 0000005a pushw_x 00000059 ret 0000004f start 00000000 xalu_ri 00000015 xalu_rr 00000012 Macrocode Symbols (total=69): Global Local --------------------------------------- buf 000005f8 dscrim 00000795 find_animal 0000017a done 0000025e get_response 000001a6 say_no 0000023e say_yes 0000021e tree fffffffe get_final 00000264 L1 0000037c L2 000003e8 L3 00000404 animal_node fffffffc discrim_node fffffffa done 00000420 get_response 00000268 loose 000002f0 tree fffffffe win 000002de gets 00000570 bell 000005d4 cwait 00000576 del_char 000005b8 done 000005e6 isita 000006f7 known 00000678 loosemsg 0000075e main 00000112 loop 0000013e malloc 00000426 mend 000007f6 nl 000007f1 no 00000724 no_b 00000002 nprint 000004e8 zprint 000004fe nprint_aux 0000050c done 00000546 nsize 00000064 numk 000006d8 print 00000430 done 0000044c loop 00000434 printf 0000044e L1 00000474 L2 000004a2 arg fffffffc cout 000004d4 done 000004e6 loop 0000045c ptr fffffffe qprompt 000007f3 root 0000067a sdone 0000010e start 00000100 strcmp 00000548 done 0000056e loop 00000550 text 00000004 think 0000069f top_node 0000067c ttydata 00000011 ttystatus 00000010 welcome 00000689 which 000007d0 winmsg 00000743 yes 00000720 yes_b 00000000 yesno 00000727 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4c 4 fc 2 11 0 fd 0 440/ 10 0 1 0 69 10 1 0 448/ bd 0 34 4 4 0 6b f0 450/ 4 0 e0 3e 69 30 6 0 458/ e3 1e 4 0 f2 21 a9 0 460/ e6 4 3 20 25 0 a1 0 468/ d4 4 69 10 1 0 f2 21 470/ 69 10 1 0 3 20 73 0 478/ a1 0 a2 4 ec e1 fe ff 480/ ec e3 fc ff e2 23 84 20 488/ 81 0 0 0 30 4 69 f0 490/ 2 0 e3 1e fe ff e3 3e 498/ fc ff 69 30 2 0 bd 0 4a0/ 5c 4 3 20 64 0 a1 0 4a8/ 5c 4 ec e1 fe ff ec e3 4b0/ fc ff e2 23 84 20 81 0 4b8/ 0 0 e8 4 69 f0 2 0 4c0/ e3 1e fe ff e3 3e fc ff 4c8/ 69 30 2 0 bd 0 5c 4 4d0/ bd 0 5c 4 fc 2 11 0 4d8/ fd 0 10 0 1 0 69 10 4e0/ 1 0 bd 0 5c 4 4 0 4e8/ e3 1e 4 0 a9 0 fe 4 4f0/ 84 10 81 0 0 0 c 5 4f8/ 69 f0 2 0 4 0 fd 0 500/ 11 0 30 0 fd 0 10 0 508/ 1 0 4 0 6b f0 2 0 510/ e3 1e 4 0 a9 0 46 5 518/ e0 21 79 20 a 0 e0 31 520/ 71 30 a 0 ec e3 fe ff 528/ 84 20 81 0 0 0 c 5 530/ 69 f0 2 0 e3 3e fe ff 538/ 69 30 30 0 fc 3 11 0 540/ fd 0 10 0 1 0 4 0 548/ e3 2e 4 0 e3 3e 6 0 550/ f2 12 f2 43 6a 14 a1 0 558/ 6e 5 3 40 0 0 a9 0 560/ 6e 5 69 20 1 0 69 30 568/ 1 0 bd 0 50 5 4 0 570/ e3 1e 4 0 e0 41 f3 20 578/ 10 0 51 20 2 0 a9 0 580/ 76 5 f3 30 11 0 fd 0 588/ 10 0 2 0 3 30 d 0 590/ a9 0 e6 5 3 30 8 0 598/ a9 0 b8 5 3 30 7f 0 5a0/ a9 0 b8 5 fc 3 11 0 5a8/ fd 0 10 0 1 0 f8 13 5b0/ 69 10 1 0 bd 0 76 5 5b8/ 2 14 b5 0 d4 5 f1 30 5c0/ 7f 0 6b 10 1 0 fc 3 5c8/ 11 0 fd 0 10 0 1 0 5d0/ bd 0 76 5 f1 30 7 0 5d8/ fc 3 11 0 fd 0 10 0 5e0/ 1 0 bd 0 76 5 fd 0 5e8/ 11 0 a 0 fd 0 10 0 5f0/ 1 0 f9 10 0 0 4 0 67c/ 0 0 0 0 61 61 72 64 684/ 76 61 72 6b 0 a 57 65 68c/ 6c 63 6f 6d 65 20 74 6f 694/ 20 41 6e 69 6d 61 6c 73 69c/ 2e a 0 a 54 68 69 6e 6a4/ 6b 20 6f 66 20 61 6e 20 6ac/ 61 6e 69 6d 61 6c 20 61 6b4/ 6e 64 20 49 20 77 69 6c 6bc/ 6c 20 74 72 79 20 74 6f 6c4/ 20 67 75 65 73 73 20 77 6cc/ 68 61 74 20 69 74 20 69 6d4/ 73 2e a 0 49 20 63 75 6dc/ 72 72 65 6e 74 6c 79 20 6e4/ 6b 6e 6f 77 20 25 64 20 6ec/ 61 6e 69 6d 61 6c 73 2e 6f4/ a a 0 49 73 20 74 68 6fc/ 65 20 61 6e 69 6d 61 6c 704/ 20 79 6f 75 20 61 72 65 70c/ 20 74 68 69 6e 6b 69 6e 714/ 67 20 6f 66 20 61 20 25 71c/ 73 3f 20 0 79 65 73 0 724/ 6e 6f 0 50 6c 65 61 73 72c/ 65 20 74 79 70 65 20 27 734/ 79 65 73 27 20 6f 72 20 73c/ 27 6e 6f 27 2e a 0 49 744/ 20 67 75 65 73 73 65 64 74c/ 20 79 6f 75 72 20 61 6e 754/ 69 6d 61 6c 21 21 21 a 75c/ a 0 49 20 63 6f 75 6c 764/ 64 20 6e 6f 74 20 67 75 76c/ 65 73 73 20 79 6f 75 72 774/ 20 61 6e 69 6d 61 6c 2e 77c/ 20 20 57 68 61 74 20 77 784/ 61 73 20 79 6f 75 72 20 78c/ 61 6e 69 6d 61 6c 3f 20 794/ 0 45 6e 74 65 72 20 61 79c/ 20 71 75 65 73 74 69 6f 7a4/ 6e 20 74 68 61 74 20 77 7ac/ 6f 75 6c 64 20 64 69 73 7b4/ 74 69 6e 67 75 69 73 68 7bc/ 20 61 20 25 73 20 66 72 7c4/ 6f 6d 20 61 20 25 73 2e 7cc/ a 3e 20 0 54 68 65 20 7d4/ 63 6f 72 72 65 63 74 20 7dc/ 61 6e 73 77 65 72 20 66 7e4/ 6f 72 20 61 20 25 73 20 7ec/ 69 73 3f 20 0 a 0 3f 7f4/ 20 0 tkgate-2.0-b10/locale/de/examples.18/ex4/trff.v000644 001751 001751 00000012511 10013155324 021524 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w14; //: /sn:0 {0}(654,415)(654,436)(603,436){1} //: {2}(599,436)(566,436)(566,415){3} //: {4}(601,438)(601,455){5} supply1 w17; //: /sn:0 {0}(620,315)(620,292){1} supply1 w12; //: /sn:0 {0}(625,86)(625,63){1} supply0 w13; //: /sn:0 {0}(650,191)(650,213)(608,213){1} //: {2}(604,213)(571,213)(571,191){3} //: {4}(606,215)(606,231){5} wire w6; //: /sn:0 {0}(625,119)(625,103){1} wire w16; //: /sn:0 {0}(620,345)(620,332){1} wire Q; //: {0}(765,383)(656,383){1} //: {2}(654,381)(654,273)(532,273)(532,184){3} //: {4}(534,182)(557,182){5} //: {6}(532,180)(532,127)(611,127){7} //: {8}(652,383)(622,383){9} //: {10}(620,381)(620,362){11} //: {12}(618,383)(566,383)(566,398){13} //: {14}(654,385)(654,398){15} wire _Q; //: /dp:1 {0}(759,159)(694,159){1} //: {2}(690,159)(652,159){3} //: {4}(648,159)(627,159){5} //: {6}(625,157)(625,136){7} //: {8}(623,159)(571,159)(571,174){9} //: {10}(650,161)(650,174){11} //: {12}(692,161)(692,252)(584,252)(584,321){13} //: {14}(586,323)(606,323){15} //: {16}(584,325)(584,406)(640,406){17} wire R; //: /dp:7 {0}(606,353)(535,353){1} //: {2}(531,353)(503,353){3} //: {4}(501,351)(501,336){5} //: {6}(499,353)(442,353){7} //: {8}(533,355)(533,406)(552,406){9} wire S; //: /dp:7 {0}(611,94)(591,94){1} //: {2}(587,94)(505,94){3} //: {4}(503,92)(503,81){5} //: {6}(501,94)(436,94){7} //: {8}(589,96)(589,182)(636,182){9} //: enddecls //: joint g8 (w13) @(606, 213) /anc:1 /w:[ 1 -1 2 4 ] //: supply1 g4 (w12) @(636,63) /sn:0 /anc:1 /w:[ 1 ] nmos g13 (.Z(w14), .S0(Q), .G0(_Q)); //: @(648,406) /sn:0 /anc:1 /w:[ 0 15 17 ] pmos g3 (.Z(w12), .S0(w6), .G0(S)); //: @(619,94) /sn:0 /anc:1 /w:[ 0 1 0 ] //: joint g34 (S) @(503, 94) /w:[ 3 4 6 -1 ] pmos g2 (.Z(w6), .S0(_Q), .G0(Q)); //: @(619,127) /sn:0 /anc:1 /w:[ 0 7 7 ] nmos g1 (.Z(w13), .S0(_Q), .G0(S)); //: @(644,182) /sn:0 /anc:1 /w:[ 0 11 9 ] //: supply1 g16 (w17) @(631,292) /sn:0 /anc:1 /w:[ 1 ] //: joint g11 (S) @(589, 94) /anc:1 /w:[ 1 -1 2 8 ] //: joint g10 (Q) @(654, 383) /anc:1 /w:[ 1 2 8 14 ] //: comment g28 /dolink:0 /link:"" @(26,299) /anc:1 //: /line:"3) Stelle den \"S\"-Schalter in die \"off\"-Position" //: /line:"zurück und drücke die Leertaste 10 bis 20 mal. Die" //: /line:"\"Q\" und \"_Q\" Signale bleiben konstant." //: /end //: comment g27 /dolink:0 /link:"" @(25,193) /anc:1 //: /line:"2) Für den Simulationsfortschritt drücke die" //: /line:"Leertaste 10 bis 20 mal. Beide Signale" //: /line:"\"Q\" and \"_Q\" sind nun im \"unknown\" Zustand." //: /line:"Schalte nun mit einem Klick auf \"S\" den Schalter" //: /line:"an und drücke die Leertaste noch einmal 10 bis 20" //: /line:"mal. Das \"Q\"-Signal geht auf \"high\" und das" //: /line:"\"_Q\"-Signal geht auf \"low\"." //: /line:"" //: /end //: switch g19 (R) @(425,353) /sn:0 /anc:1 /w:[ 7 ] /st:0 led g32 (.I(Q)); //: @(772,383) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g6 (S) @(419,94) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: joint g7 (Q) @(620, 383) /anc:1 /w:[ 9 10 12 -1 ] //: joint g9 (_Q) @(692, 159) /anc:1 /w:[ 1 -1 2 12 ] //: joint g20 (w14) @(601, 436) /anc:1 /w:[ 1 -1 2 4 ] pmos g15 (.Z(w17), .S0(w16), .G0(_Q)); //: @(614,323) /sn:0 /anc:1 /w:[ 0 1 15 ] led g31 (.I(_Q)); //: @(766,159) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g25 /dolink:0 /link:"" @(35,22) /anc:1 //: /line:"Diese Schaltung realisiert ein einfaches Flipflop," //: /line:"das aus zwei CMOS NOR-Gattern besteht, die auf" //: /line:"Transistorebene implementiert sind." //: /end //: supply0 g17 (w14) @(601,461) /sn:0 /anc:1 /w:[ 5 ] //: comment g29 /dolink:0 /link:"" @(26,355) /anc:1 //: /line:"4) Stelle nun den \"R\" Schalter (draufklicken)" //: /line:"auf \"off\" und drücke die Leertaste 10 bis 20 mal." //: /line:"Das \"_Q\"-Signal geht auf \"high\" und das" //: /line:"\"Q\"-Signal geht auf \"low\"." //: /end pmos g14 (.Z(w16), .S0(Q), .G0(R)); //: @(614,353) /sn:0 /anc:1 /w:[ 0 11 0 ] //: supply0 g5 (w13) @(606,237) /sn:0 /anc:1 /w:[ 5 ] //: joint g21 (Q) @(532, 182) /anc:1 /w:[ 4 6 -1 3 ] //: joint g24 (_Q) @(625, 159) /anc:1 /w:[ 5 6 8 -1 ] //: joint g36 (R) @(501, 353) /w:[ 3 4 6 -1 ] //: joint g23 (_Q) @(650, 159) /anc:1 /w:[ 3 -1 4 10 ] //: comment g26 /dolink:0 /link:"" @(26,101) /anc:1 //: /line:"1) Starte die Simulation durch Klick auf die" //: /line:"\"Abspiel\"-Taste oder durch Auswahl von \"Anfang" //: /line:"Simulation\" aus dem \"Simulation\"-Menu." //: /line:"Setze Tastköpfe auf die Signale \"S\", \"R\", \"Q\"" //: /line:"und \"_Q\" (Doppelklick). Das \"_Q\"-Signal" //: /line:"ist das negierte \"Q\"-Signal (Querstrich)." //: /end //: joint g22 (R) @(533, 353) /anc:1 /w:[ 1 -1 2 8 ] nmos g0 (.Z(w13), .S0(_Q), .G0(Q)); //: @(565,182) /sn:0 /anc:1 /w:[ 3 9 5 ] led g35 (.I(R)); //: @(501,329) /sn:0 /w:[ 5 ] /type:0 //: joint g18 (_Q) @(584, 323) /anc:1 /w:[ 14 13 -1 16 ] nmos g12 (.Z(w14), .S0(Q), .G0(R)); //: @(560,406) /sn:0 /anc:1 /w:[ 3 13 9 ] //: comment g30 /dolink:0 /link:"" @(23,420) /anc:1 //: /line:"5) Stelle den \"R\"-Schalter in die \"off\" Position" //: /line:"zurück und drücke die Leertaste 10 bis 20 mal. Die" //: /line:"Signale \"Q\" und \"_Q\" bleiben konstant." //: /end led g33 (.I(S)); //: @(503,74) /sn:0 /w:[ 5 ] /type:0 endmodule tkgate-2.0-b10/locale/de/examples.18/ex3/counter.v000644 001751 001751 00000005365 10013155043 022250 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w11; //: /sn:0 {0}(269,197)(269,181)(248,181){1} wire [7:0] w4; //: /sn:0 {0}(208,114)(208,167){1} wire w8; //: /sn:0 {0}(263,269)(325,269)(325,283){1} wire w12; //: /sn:0 {0}(200,181)(190,181){1} wire ck; //: /dp:1 {0}(187,264)(56,264){1} wire [7:0] w5; //: /sn:0 {0}(224,196)(224,254){1} wire [7:0] reg_out; //: {0}(224,275)(224,332)(297,332)(297,173){1} //: {2}(299,171)(379,171){3} //: {4}(297,169)(297,125)(240,125)(240,167){5} wire w9; //: /sn:0 {0}(263,259)(324,259)(324,245){1} //: enddecls //: comment g8 /dolink:0 /link:"" @(41,205) //: /line:"2) Setze einen Tastkopf" //: /line:"auf die Taktleitung" //: /line:"durch einen Doppelklick." //: /end clock g4 (.Z(ck)); //: @(43,264) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g13 /dolink:0 /link:"" @(23,412) //: /line:"7) Drücke nun die \"TAB\"-Taste, um eine Taktperiode" //: /line:"voranzuschreiten. Da die CLR-Leitung aktiv low ist," //: /line:"wird das Register gelöscht. Setze dann die CLR-Leitung" //: /line:"auf \"on\" und drücke weiterhin die \"TAB\"-Taste." //: /line:"Beobachte den Wert des Registers, der mit jedem Takt" //: /line:"hochzählt." //: /end //: dip g3 (w4) @(208,104) /sn:0 /w:[ 0 ] /st:1 add g2 (.A(w4), .B(reg_out), .S(w5), .CI(w11), .CO(w12)); //: @(224,183) /sn:0 /w:[ 1 5 0 1 0 ] //: switch g1 (w8) @(325,297) /sn:0 /R:1 /w:[ 1 ] /st:0 //: comment g11 /dolink:0 /link:"" @(348,218) //: /line:"5) Die \"CLR\"-Leitung muß" //: /line:"ausgeschaltet sein, um das" //: /line:"Register zurückzusetzen." //: /end //: comment g10 /dolink:0 /link:"" @(270,64) //: /line:"4) Setze den Dip-Schalter mit einem" //: /line:"Klick auf 1, gib eine \"1\" in die" //: /line:"erscheinende Dialogbox ein und" //: /line:"drücke die \"Anwenden\"-Taste." //: /end //: supply0 g6 (w11) @(269,203) /sn:0 /w:[ 0 ] //: comment g9 /dolink:0 /link:"" @(198,354) //: /line:"3) Setze mit einem Doppelklick" //: /line:"einen Tastkopf auf den" //: /line:"Registerausgang." //: /end //: switch g7 (w9) @(324,232) /sn:0 /R:3 /w:[ 1 ] /st:0 led g17 (.I(reg_out)); //: @(386,171) /sn:0 /R:3 /w:[ 3 ] /type:2 //: joint g14 (reg_out) @(297, 171) /w:[ 2 4 -1 1 ] //: comment g5 /dolink:0 /link:"" @(15,11) //: /line:"Beispiel: 8-Bit Zähler" //: /line:"" //: /line:"1) Starte die Simulation durch Eingabe von \"Strg-S b\"." //: /line:"" //: /end register g0 (.Q(reg_out), .D(w5), .EN(w8), .CLR(w9), .CK(ck)); //: @(224,264) /sn:0 /w:[ 0 1 0 0 0 ] //: comment g12 /dolink:0 /link:"" @(309,316) //: /line:"6) Stelle sicher, daß die" //: /line:"Enable-Leitung EN ausgeschaltet ist." //: /end endmodule tkgate-2.0-b10/locale/de/examples.18/ex2/flipflop.v000644 001751 001751 00000005632 07416325602 022415 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 module main; //: root_module supply0 w4; //: /sn:0 {0}(661,215)(661,212)(640,212)(640,229){1} supply0 w0; //: /sn:0 {0}(346,226)(346,200)(362,200)(362,210){1} supply0 w3; //: /sn:0 {0}(499,211)(499,207)(483,207)(483,226){1} wire w6; //: /sn:0 /dp:1 {0}(336,226)(336,171){1} //: {2}(338,169)(471,169){3} //: {4}(475,169)(630,169)(630,229){5} //: {6}(473,171)(473,226){7} //: {8}(334,169)(178,169){9} wire w7; //: /sn:0 {0}(494,247)(504,247){1} wire w16; //: /sn:0 {0}(435,235)(446,235)(446,242)(462,242){1} wire w15; //: /sn:0 {0}(458,122)(458,139)(380,139)(380,235){1} //: {2}(382,237)(414,237){3} //: {4}(378,237)(357,237){5} //: {6}(380,239)(380,272)(534,272){7} wire w19; //: /sn:0 {0}(555,270)(564,270)(564,247)(574,247){1} wire w1; //: /sn:0 {0}(357,247)(367,247)(367,277)(312,277)(312,242)(325,242){1} wire [2:0] w17; //: /sn:0 {0}(448,116)(448,91){1} wire w2; //: /sn:0 {0}(175,344)(339,344){1} //: {2}(343,344)(476,344){3} //: {4}(480,344)(635,344)(635,261){5} //: {6}(478,342)(478,258){7} //: {8}(341,342)(341,258){9} wire w11; //: /sn:0 {0}(438,122)(438,152)(677,152)(677,188){1} //: {2}(675,190)(564,190)(564,242)(574,242){3} //: {4}(677,192)(677,240)(651,240){5} wire w12; //: /sn:0 {0}(595,245)(619,245){1} wire w13; //: /sn:0 {0}(651,250)(661,250){1} wire w5; //: /sn:0 {0}(494,237)(518,237){1} //: {2}(520,235)(520,194){3} //: {4}(520,190)(520,133)(448,133)(448,122){5} //: {6}(518,192)(404,192)(404,232)(414,232){7} //: {8}(520,239)(520,267)(534,267){9} //: enddecls clock g4 (.Z(w2)); //: @(162,344) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: supply0 g8 (w3) @(499,217) /sn:0 /w:[ 0 ] led g13 (.I(w17)); //: @(448,84) /sn:0 /w:[ 1 ] /type:1 //: supply0 g3 (w0) @(362,216) /sn:0 /w:[ 1 ] ff g2 (.Q(w11), ._Q(w13), .D(w12), .EN(w4), .CLR(w6), .CK(w2)); //: @(635,245) /sn:0 /w:[ 5 0 1 1 5 5 ] ff g1 (.Q(w5), ._Q(w7), .D(w16), .EN(w3), .CLR(w6), .CK(w2)); //: @(478,242) /sn:0 /w:[ 0 0 1 1 7 7 ] //: joint g11 (w2) @(341, 344) /w:[ 2 8 1 -1 ] //: joint g16 (w5) @(520, 192) /w:[ -1 4 6 3 ] and g19 (.I0(w5), .I1(w15), .Z(w19)); //: @(545,270) /sn:0 /w:[ 9 7 0 ] //: joint g6 (w6) @(336, 169) /w:[ 2 -1 8 1 ] //: joint g7 (w6) @(473, 169) /w:[ 4 -1 3 6 ] //: supply0 g9 (w4) @(661,221) /sn:0 /w:[ 0 ] xor g15 (.I0(w5), .I1(w15), .Z(w16)); //: @(425,235) /sn:0 /w:[ 7 3 0 ] //: joint g20 (w5) @(520, 237) /w:[ -1 2 1 8 ] //: joint g17 (w15) @(380, 237) /w:[ 2 1 4 6 ] //: switch g5 (w6) @(161,169) /sn:0 /w:[ 9 ] /st:1 concat g14 (.I0(w15), .I1(w5), .I2(w11), .Z(w17)); //: @(448,117) /sn:0 /R:1 /w:[ 0 5 0 0 ] /dr:0 //: joint g21 (w11) @(677, 190) /w:[ -1 1 2 4 ] ff g0 (.Q(w15), ._Q(w1), .D(w1), .EN(w0), .CLR(w6), .CK(w2)); //: @(341,242) /sn:0 /w:[ 5 0 1 0 0 9 ] //: joint g12 (w2) @(478, 344) /w:[ 4 6 3 -1 ] xor g18 (.I0(w11), .I1(w19), .Z(w12)); //: @(585,245) /sn:0 /w:[ 3 1 0 ] endmodule tkgate-2.0-b10/locale/de/examples.18/ex1/combinational.v000644 001751 001751 00000011777 10013154345 023416 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire A0; //: /dp:3 {0}(173,94)(163,94){1} //: {2}(159,94)(95,94){3} //: {4}(161,96)(161,154)(173,154){5} wire w6; //: /sn:0 {0}(215,171)(215,138){1} wire S1; //: {0}(303,253)(257,253){1} wire w14; //: /sn:0 {0}(211,329)(211,296){1} wire w4; //: /sn:0 {0}(239,97)(214,97){1} //: {2}(210,97)(194,97){3} //: {4}(212,99)(212,117){5} wire w19; //: /sn:0 {0}(231,413)(211,413){1} //: {2}(209,411)(209,350){3} //: {4}(209,415)(209,438){5} wire w0; //: /sn:0 {0}(239,92)(219,92){1} //: {2}(217,90)(217,50){3} //: {4}(217,94)(217,117){5} wire w3; //: /sn:0 {0}(210,171)(210,157)(194,157){1} wire C3; //: {0}(303,533)(205,533)(205,513){1} wire w21; //: /sn:0 {0}(202,492)(202,478)(186,478){1} wire A2; //: /dp:3 {0}(165,415)(155,415){1} //: {2}(151,415)(96,415){3} //: {4}(153,417)(153,475)(165,475){5} wire B2; //: {0}(100,480)(142,480){1} //: {2}(146,480)(165,480){3} //: {4}(144,478)(144,420)(165,420){5} wire B1; //: {0}(98,317)(142,317){1} //: {2}(146,317)(169,317){3} //: {4}(144,315)(144,257)(169,257){5} wire S0; //: {0}(303,95)(260,95){1} wire w18; //: /sn:0 {0}(231,418)(206,418){1} //: {2}(202,418)(186,418){3} //: {4}(204,420)(204,438){5} wire w22; //: /sn:0 {0}(207,492)(207,459){1} wire w11; //: /sn:0 {0}(236,250)(215,250){1} //: {2}(213,248)(213,192){3} //: {4}(213,252)(213,275){5} wire A1; //: /dp:3 {0}(169,252)(159,252){1} //: {2}(155,252)(96,252){3} //: {4}(157,254)(157,312)(169,312){5} wire w10; //: /sn:0 {0}(236,255)(210,255){1} //: {2}(206,255)(190,255){3} //: {4}(208,257)(208,275){5} wire w13; //: /sn:0 {0}(206,329)(206,315)(190,315){1} wire B0; //: {0}(93,159)(144,159){1} //: {2}(148,159)(173,159){3} //: {4}(146,157)(146,99)(173,99){5} wire S2; //: {0}(303,416)(252,416){1} //: enddecls //: switch g4 (B0) @(76,159) /sn:0 /w:[ 0 ] /st:1 nand g8 (.I0(w4), .I1(w0), .Z(w6)); //: @(215,128) /sn:0 /R:3 /w:[ 5 5 1 ] //: switch g3 (w0) @(217,37) /sn:0 /R:3 /w:[ 3 ] /st:0 xor g13 (.I0(A1), .I1(B1), .Z(w10)); //: @(180,255) /sn:0 /w:[ 0 5 3 ] //: comment g34 /dolink:0 /link:"" @(351,22) //: /line:"Diese Schaltung realisiert einen einfachen Drei-Bit-Addierer." //: /line:"" //: /line:"Starte den Simulator durch Drücken der \"Logikanalysator\"-" //: /line:"Taste aus der Tastenleiste." //: /line:"Setze dann Tastköpfe durch Doppelklick auf die" //: /line:"Leitungen S0, S1, S2 und C3 (und beliebige andere" //: /line:"zusätzliche Leitungen). Drücke die \"Abspiel\"-Taste" //: /line:"um den kontinuierlichen Simulationsmodus zu starten." //: /line:"In diesem Modus zeigt der Simulator bei einem geänderten" //: /line:"Schalterwert (einfacher Mausklickauf den Schalter)" //: /line:"die Simulation bis alle Werte sich stabilisiert haben." //: /line:"Die Simulation wird durch Drücken der \"Stop\"-Taste" //: /line:"in der Tastenleiste beendet." //: /end led g37 (.I(S2)); //: @(310,416) /sn:0 /R:3 /w:[ 0 ] /type:0 xor g2 (.I0(w0), .I1(w4), .Z(S0)); //: @(250,95) /sn:0 /w:[ 0 0 1 ] xor g1 (.I0(A0), .I1(B0), .Z(w4)); //: @(184,97) /sn:0 /w:[ 0 5 3 ] nand g11 (.I0(w3), .I1(w6), .Z(w11)); //: @(213,182) /sn:0 /R:3 /w:[ 0 0 3 ] nand g16 (.I0(A1), .I1(B1), .Z(w13)); //: @(180,315) /sn:0 /w:[ 5 3 1 ] //: joint g10 (w4) @(212, 97) /w:[ 1 -1 2 4 ] //: joint g28 (A2) @(153, 415) /w:[ 1 -1 2 4 ] nand g19 (.I0(w10), .I1(w11), .Z(w14)); //: @(211,286) /sn:0 /R:3 /w:[ 5 5 1 ] nand g27 (.I0(A2), .I1(B2), .Z(w21)); //: @(176,478) /sn:0 /w:[ 5 3 1 ] //: joint g32 (w18) @(204, 418) /w:[ 1 -1 2 4 ] //: joint g6 (A0) @(161, 94) /w:[ 1 -1 2 4 ] led g38 (.I(C3)); //: @(310,533) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g7 (B0) @(146, 159) /w:[ 2 4 1 -1 ] //: joint g9 (w0) @(217, 92) /w:[ 1 2 -1 4 ] //: switch g15 (B1) @(81,317) /sn:0 /w:[ 0 ] /st:0 //: joint g20 (w11) @(213, 250) /w:[ 1 2 -1 4 ] //: joint g31 (w19) @(209, 413) /w:[ 1 2 -1 4 ] //: joint g17 (A1) @(157, 252) /w:[ 1 -1 2 4 ] xor g25 (.I0(w19), .I1(w18), .Z(S2)); //: @(242,416) /sn:0 /w:[ 0 0 1 ] //: joint g29 (B2) @(144, 480) /w:[ 2 4 1 -1 ] nand g5 (.I0(A0), .I1(B0), .Z(w3)); //: @(184,157) /sn:0 /w:[ 5 3 1 ] xor g14 (.I0(w11), .I1(w10), .Z(S1)); //: @(247,253) /sn:0 /w:[ 0 0 1 ] //: joint g21 (w10) @(208, 255) /w:[ 1 -1 2 4 ] xor g24 (.I0(A2), .I1(B2), .Z(w18)); //: @(176,418) /sn:0 /w:[ 0 5 3 ] led g36 (.I(S1)); //: @(310,253) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g23 (A2) @(79,415) /sn:0 /w:[ 3 ] /st:0 //: switch g0 (A0) @(78,94) /sn:0 /w:[ 3 ] /st:0 nand g22 (.I0(w13), .I1(w14), .Z(w19)); //: @(209,340) /sn:0 /R:3 /w:[ 0 0 3 ] //: switch g26 (B2) @(83,480) /sn:0 /w:[ 0 ] /st:0 led g35 (.I(S0)); //: @(310,95) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g12 (A1) @(79,252) /sn:0 /w:[ 3 ] /st:1 //: joint g18 (B1) @(144, 317) /w:[ 2 4 1 -1 ] nand g30 (.I0(w18), .I1(w19), .Z(w22)); //: @(207,449) /sn:0 /R:3 /w:[ 5 5 1 ] nand g33 (.I0(w21), .I1(w22), .Z(C3)); //: @(205,503) /sn:0 /R:3 /w:[ 0 0 1 ] endmodule tkgate-2.0-b10/locale/de/examples/ex5000777 001751 001751 00000000000 11145151105 020073 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/ex1000777 001751 001751 00000000000 11145151105 020067 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/ex2000777 001751 001751 00000000000 11145151105 020070 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/ex3000777 001751 001751 00000000000 11145151105 020071 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/ex6000777 001751 001751 00000000000 11145151105 020074 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/ex4000777 001751 001751 00000000000 11145151105 020072 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/de/examples/index.v000644 001751 001751 00000004601 11137713346 020760 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "index.v" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module //: enddecls //: comment g4 @(553,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Cola-Automat

" //: /line:"Dieses Beispiel nutzt TkGate's Virtual" //: /line:"Peripheral Devices (VPD) um einen inter-" //: /line:"aktiven \"Cola-Automaten\" zu erzeugen, der" //: /line:"durch eine Benutzerschaltung gesteuert werden" //: /line:"kann. Nur das Gerät selbst ist enthalten." //: /line:"Kannst Du eine Steuerung dafür entwerfen?" //: /line:"" //: /end //: comment g3 @(32,317) /sn:0 /anc:1 //: /line:"" //: /line:"

Transistor-Level Flipflop

" //: /line:"Ein Flipflop, implementiert mit" //: /line:"NMOS and PMOS Transistoren." //: /line:"" //: /end //: comment g2 @(551,30) /sn:0 /anc:1 //: /line:"" //: /line:"

8-Bit Zähler

" //: /line:"Ein Zähler, der mit Register- und" //: /line:"Addierer-Bausteinen entworfen ist." //: /end //: comment g1 @(299,30) /sn:0 /anc:1 //: /line:"" //: /line:"

3-Bit Zähler

" //: /line:"Ein 3-Bit-Zähler, der mit drei" //: /line:"einzelnen D-Flipflops implementert ist." //: /end //: comment g6 @(20,552) /sn:0 //: /line:"Zurück zur TkGate Hauptseite" //: /end //: comment g5 @(301,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Menagerie CPU

" //: /line:"Eine einfache, Microcode-basierte CPU" //: /line:"die das \"Animals\" Spiel auf einem" //: /line:"TTY Baustein bei der Simulation ausführt." //: /end //: comment g0 @(32,30) /sn:0 /anc:1 //: /line:"

" //: /line:"Schaltnetz

" //: /line:"Ein einfacher 3-Bit Addierer." //: /line:"Drücke den Abspielknopf und" //: /line:"Klicke auf die Schalter und" //: /line:"beobachte, wie sich die LEDs ändern." //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/de/examples/ex4/trff.v000644 001751 001751 00000013673 11137714167 021325 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "trff.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module supply0 w14; //: /sn:0 {0}(654,415)(654,436)(603,436){1} //: {2}(599,436)(566,436)(566,415){3} //: {4}(601,438)(601,455){5} reg R; //: {0}(606,353)(535,353){1} //: {2}(531,353)(503,353){3} //: {4}(501,351)(501,336){5} //: {6}(59:499,353)(442,353){7} //: {8}(533,355)(533,406)(552,406){9} supply1 w17; //: /sn:0 {0}(620,315)(620,292){1} supply1 w12; //: /sn:0 {0}(625,86)(625,63){1} supply0 w13; //: /sn:0 {0}(650,191)(650,213)(608,213){1} //: {2}(604,213)(571,213)(571,191){3} //: {4}(606,215)(606,231){5} reg S; //: {0}(611,94)(591,94){1} //: {2}(587,94)(505,94){3} //: {4}(503,92)(503,81){5} //: {6}(56:501,94)(436,94){7} //: {8}(589,96)(589,182)(636,182){9} wire w6; //: /sn:0 {0}(625,119)(625,103){1} wire w16; //: /sn:0 {0}(620,345)(620,332){1} wire Q; //: {0}(50:765,383)(656,383){1} //: {2}(654,381)(654,273)(532,273)(532,184){3} //: {4}(534,182)(557,182){5} //: {6}(532,180)(532,127)(611,127){7} //: {8}(652,383)(622,383){9} //: {10}(620,381)(620,362){11} //: {12}(618,383)(566,383)(566,398){13} //: {14}(654,385)(654,398){15} wire _Q; //: {0}(50:759,159)(694,159){1} //: {2}(690,159)(652,159){3} //: {4}(648,159)(627,159){5} //: {6}(625,157)(625,136){7} //: {8}(623,159)(571,159)(571,174){9} //: {10}(650,161)(650,174){11} //: {12}(692,161)(692,252)(584,252)(584,321){13} //: {14}(586,323)(606,323){15} //: {16}(584,325)(584,406)(640,406){17} //: enddecls //: joint g8 (w13) @(606, 213) /anc:1 /w:[ 1 -1 2 4 ] //: VDD g4 (w12) @(636,63) /sn:0 /anc:1 /w:[ 1 ] _GGNMOS #(2, 1) g13 (.Z(Q), .S(w14), .G(_Q)); //: @(648,406) /sn:0 /anc:1 /w:[ 15 0 17 ] _GGPMOS #(2, 1) g3 (.Z(w6), .S(w12), .G(S)); //: @(619,94) /sn:0 /anc:1 /w:[ 1 0 0 ] //: joint g34 (S) @(503, 94) /w:[ 3 4 6 -1 ] _GGPMOS #(2, 1) g2 (.Z(_Q), .S(w6), .G(Q)); //: @(619,127) /sn:0 /anc:1 /w:[ 7 0 7 ] _GGNMOS #(2, 1) g1 (.Z(_Q), .S(w13), .G(S)); //: @(644,182) /sn:0 /anc:1 /w:[ 11 0 9 ] //: VDD g16 (w17) @(631,292) /sn:0 /anc:1 /w:[ 1 ] //: joint g11 (S) @(589, 94) /anc:1 /w:[ 1 -1 2 8 ] //: joint g10 (Q) @(654, 383) /anc:1 /w:[ 1 2 8 14 ] //: comment g28 @(26,299) /anc:1 //: /line:"3) Stelle den Schalter \"S\" wieder auf die \"off\" Position" //: /line:"und drücke die Leertaste 10 bis 20 mal. Die Signale" //: /line:"\"Q\" und \"_Q\" bleiben bestehen." //: /end //: comment g27 @(25,193) /anc:1 //: /line:"2) Drücke die Leertaste 10 bis 20 mal um den Simulator" //: /line:"vorzurücken. Beachte, daß beide Signale, " //: /line:"\"Q\" und \"_Q\", im unbekannten Zustand sind." //: /line:"Schalte jetzt \"S\" ein (durch Draufklicken)" //: /line:"und drücke die Leertaste weitere 10 bis 20 Male" //: /line:"Das \"Q\" Signal wird auf high gehen und das" //: /line:"\"_Q\" Signal auf low." //: /line:"" //: /end //: SWITCH g19 (R) @(425,353) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: LED g32 (Q) @(772,383) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g6 (S) @(419,94) /sn:0 /anc:1 /w:[ 7 ] /st:1 //: joint g7 (Q) @(620, 383) /anc:1 /w:[ 9 10 12 -1 ] //: joint g9 (_Q) @(692, 159) /anc:1 /w:[ 1 -1 2 12 ] //: joint g20 (w14) @(601, 436) /anc:1 /w:[ 1 -1 2 4 ] _GGPMOS #(2, 1) g15 (.Z(w16), .S(w17), .G(_Q)); //: @(614,323) /sn:0 /anc:1 /w:[ 1 0 15 ] //: LED g31 (_Q) @(766,159) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g39 @(20,12) /sn:0 //: /line:"[ZURÜCK]" //: /end //: comment g25 @(26,42) //: /line:"Diese Schaltung ist ein einfaches Flipflop, das aus" //: /line:"zwei CMOS NOR Gattern auf Transistorebene konstruiert ist." //: /line:"" //: /end //: GROUND g17 (w14) @(601,461) /sn:0 /anc:1 /w:[ 5 ] //: comment g29 @(26,355) /anc:1 //: /line:"4) Schalter durch Klicken den \"R\" Schalter aus" //: /line:"und drücke die Leertaste 10 bis 20 mal." //: /line:"Das \"_Q\" Signal wird high und das \"Q\"" //: /line:"Signal geht auf low." //: /end _GGPMOS #(2, 1) g14 (.Z(Q), .S(w16), .G(R)); //: @(614,353) /sn:0 /anc:1 /w:[ 11 0 0 ] //: GROUND g5 (w13) @(606,237) /sn:0 /anc:1 /w:[ 5 ] //: joint g21 (Q) @(532, 182) /anc:1 /w:[ 4 6 -1 3 ] //: joint g24 (_Q) @(625, 159) /anc:1 /w:[ 5 6 8 -1 ] //: joint g36 (R) @(501, 353) /w:[ 3 4 6 -1 ] //: joint g23 (_Q) @(650, 159) /anc:1 /w:[ 3 -1 4 10 ] //: comment g26 @(26,101) /anc:1 //: /line:"1) Starte die Simulation durch Klicken auf den" //: /line:"\"Abspielen\" Knopf oder durch Auswahl von \"Beginn" //: /line:"Simulation\" aus dem \"Simulieren\" Menu." //: /line:"Setze Tastköpfe auf die \"S\", \"R\", \"Q\" und \"_Q\"" //: /line:"Signale (durch Doppelklick auf sie). Das \"_Q\"" //: /line:"Signal ist das negierte \"Q\" mit einem Überstrich." //: /end //: joint g22 (R) @(533, 353) /anc:1 /w:[ 1 -1 2 8 ] _GGNMOS #(2, 1) g0 (.Z(_Q), .S(w13), .G(Q)); //: @(565,182) /sn:0 /anc:1 /w:[ 9 3 5 ] //: LED g35 (R) @(501,329) /sn:0 /w:[ 5 ] /type:0 //: joint g18 (_Q) @(584, 323) /anc:1 /w:[ 14 13 -1 16 ] _GGNMOS #(2, 1) g12 (.Z(Q), .S(w14), .G(R)); //: @(560,406) /sn:0 /anc:1 /w:[ 13 3 9 ] //: comment g30 @(23,420) /anc:1 //: /line:"5) Lege den \"R\" Schalter in die off Position" //: /line:"und drücke die Leertaste 10 bis 20 mal. Die" //: /line:"\"Q\" und \"_Q\" Signale werden gleich bleiben." //: /end //: LED g33 (S) @(503,74) /sn:0 /w:[ 5 ] /type:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/de/examples/ex6/coke.v000644 001751 001751 00000012543 11137716743 021304 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "Willkommen zu TkGate" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg [5:0] w6; //: /sn:0 {0}(#:95,107)(114,107)(114,117)(143,117){1} reg BILLT; //: /sn:0 {0}(143,213)(49,213){1} reg [7:0] w0; //: /sn:0 {0}(#:88,321)(127,321)(127,293)(143,293){1} reg RETINS; //: /sn:0 {0}(143,261)(88,261){1} reg CHGD; //: /sn:0 {0}(143,149)(49,149){1} reg [5:0] w20; //: /sn:0 {0}(#:95,68)(124,68)(124,101)(143,101){1} reg INSACK; //: /sn:0 {0}(143,277)(49,277){1} reg w1; //: /sn:0 {0}(236,375)(236,358){1} reg BILLIN; //: /sn:0 {0}(143,197)(88,197){1} reg BILLOUT; //: /sn:0 {0}(143,229)(88,229){1} reg CHGQ; //: /sn:0 {0}(143,133)(88,133){1} reg NOCHG; //: /sn:0 {0}(143,181)(49,181){1} reg CHGCOM; //: /sn:0 {0}(143,245)(49,245){1} reg CHGN; //: /sn:0 {0}(143,165)(88,165){1} wire w38; //: /sn:0 {0}(326,325)(358,325){1} wire w37; //: /sn:0 {0}(326,309)(358,309){1} wire w34; //: /sn:0 {0}(326,261)(358,261){1} wire [2:0] w21; //: /sn:0 {0}(#:358,197)(326,197){1} wire w31; //: /sn:0 {0}(326,245)(358,245){1} wire w36; //: /sn:0 {0}(326,293)(358,293){1} wire w24; //: /sn:0 {0}(326,149)(358,149){1} wire w23; //: /sn:0 {0}(326,133)(358,133){1} wire [5:0] w18; //: /sn:0 {0}(#:326,117)(354,117){1} wire w30; //: /sn:0 {0}(326,229)(358,229){1} wire INSN; //: /sn:0 {0}(358,165)(326,165){1} wire [5:0] w17; //: /sn:0 {0}(#:326,101)(354,101){1} wire [2:0] w29; //: /sn:0 {0}(#:326,213)(358,213){1} wire [2:0] w26; //: /sn:0 {0}(#:326,181)(358,181){1} wire BILLACK; //: /sn:0 {0}(358,277)(326,277){1} //: enddecls //: SWITCH g8 (BILLOUT) @(71,229) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g4 (CHGN) @(71,165) /sn:0 /w:[ 1 ] /st:0 //: LED g13 (INSN) @(365,165) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g3 (CHGD) @(32,149) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g2 (CHGQ) @(71,133) /sn:0 /w:[ 1 ] /st:0 //: DIP g1 (w20) @(57,68) /sn:0 /R:1 /w:[ 0 ] /st:0 //: DIP g11 (w6) @(57,107) /sn:0 /R:1 /w:[ 0 ] /st:0 //: LED g16 (w21) @(365,197) /sn:0 /R:3 /w:[ 0 ] /type:1 //: LED g28 (w37) @(365,309) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g10 (w23) @(365,133) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g27 (INSACK) @(32,277) /sn:0 /w:[ 1 ] /st:0 //: LED g19 (w31) @(365,245) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g6 (BILLIN) @(71,197) /sn:0 /w:[ 1 ] /st:0 //: LED g9 (w17) @(361,101) /sn:0 /R:3 /w:[ 1 ] /type:1 //: SWITCH g7 (BILLT) @(32,213) /sn:0 /w:[ 1 ] /st:0 //: comment g31 @(20,16) /sn:0 //: /line:"

Cola-Automat: Aufgabe

" //: /end //: LED g20 (w34) @(365,261) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g15 (w18) @(361,117) /sn:0 /R:3 /w:[ 1 ] /type:1 //: comment g39 @(18,426) /sn:0 //: /line:"[ZURÃœCK]" //: /end //: LED g29 (w38) @(365,325) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g25 (BILLACK) @(365,277) /sn:0 /R:3 /w:[ 0 ] /type:0 //: LED g17 (w29) @(365,213) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g14 (w26) @(365,181) /sn:0 /R:3 /w:[ 1 ] /type:1 //: SWITCH g5 (NOCHG) @(32,181) /sn:0 /w:[ 1 ] /st:0 cokemachine g21 (.COST(w0), .INSACK(INSACK), .RETINS(RETINS), .CHGCOM(CHGCOM), .BILLOUT(BILLOUT), .BILLLT(BILLT), .BILLIN(BILLIN), .NOCHG(NOCHG), .CHGN(CHGN), .CHGD(CHGD), .CHGQ(CHGQ), .ELIGHT(w6), .DISP(w20), ._RESET(w1), .BILLNG(w38), .DISPACK(w37), .CHGACK(w36), .BILLACK(BILLACK), .CNRET(w34), .BILLOK(w31), .BILLSNS(w30), .NUMN(w29), .NUMD(w21), .NUMQ(w26), .INSN(INSN), .INSD(w24), .INSQ(w23), .EMPTY(w18), .PRESS(w17)); //: @(144, 85) /sz:(181, 272) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>0 Li4>0 Li5>0 Li6>0 Li7>0 Li8>0 Li9>0 Li10>0 Li11>1 Li12>1 Bi0>1 Ro0<0 Ro1<0 Ro2<0 Ro3<1 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<1 Ro9<0 Ro10<1 Ro11<0 Ro12<0 Ro13<0 Ro14<0 ] //: LED g24 (w36) @(365,293) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g23 (RETINS) @(71,261) /sn:0 /w:[ 1 ] /st:0 //: DIP g26 (w0) @(50,321) /sn:0 /R:1 /w:[ 0 ] /st:15 //: comment g0 @(421,39) /sn:0 //: /line:"Das Modul links ist die Schnittstelle zu einem \"Cola\"-Automaten." //: /line:"Wenn Du in den Simulationsmodus umschaltest und den \"Abspielen\"" //: /line:"Knopf drückst, wird ein Fenster angezeigt, das eine externe und" //: /line:"eine interne Sicht des Cola-Automaten aufzeigt. Du kannst dann" //: /line:"Münzen einwerfen und Banknoten in den Schlitz ziehen, drücke" //: /line:"die Getränkeknöpfe oder die Geldrückgabe. Diese Aktionen" //: /line:"erzeugen Signale, die an Deine Schaltung gesendet werden." //: /line:"Eingänge der Steuerung können zur Beleuchtung und/oder für " //: /line:"den Getränkespender oder das Wechselgeld benutzt werden." //: /line:"" //: /line:"Aufgaben:" //: /line:"" //: /line:"1) Entwirf eine Steuerung für den obigen Cola-Automaten" //: /line:"mit der gegebenen Schnittstelle." //: /line:"" //: /line:"2) Ändere den Entwurf so, daß nur einer der beiden \"Cola\"" //: /line:"knöpfe jeweils benutzt werden kann, falls mindestens eine Cola im" //: /line:"Automaten ist." //: /line:"" //: /end //: SWITCH g22 (CHGCOM) @(32,245) /sn:0 /w:[ 1 ] /st:0 //: LED g18 (w30) @(365,229) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g12 (w24) @(365,149) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g30 (w1) @(236,389) /sn:0 /R:1 /w:[ 0 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/de/examples/ex3/counter.v000644 001751 001751 00000010024 11137714074 022022 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "counter.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg [7:0] w4; //: /sn:0 {0}(#:208,114)(208,167){1} reg w8; //: /sn:0 {0}(263,269)(325,269)(325,283){1} supply0 w11; //: /sn:0 {0}(269,197)(269,181)(248,181){1} reg w9; //: /sn:0 {0}(263,259)(324,259)(324,245){1} wire w12; //: /sn:0 {0}(200,181)(190,181){1} wire ck; //: {0}(50:187,264)(56,264){1} wire [7:0] w5; //: /sn:0 {0}(#:224,196)(224,254){1} wire [7:0] reg_out; //: {0}(#:50:224,275)(224,332)(297,332)(297,173){1} //: {2}(299,171)(379,171){3} //: {4}(297,169)(297,125)(240,125)(240,167){5} //: enddecls //: comment g8 @(41,205) //: /line:"2) Setze per Doppelklick einen " //: /line:"Tastkopf auf die Taktleitung." //: /end _GGCLOCK_P100_0_50 g4 (.Z(ck)); //: @(43,264) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g13 @(23,412) //: /line:"7) Drücke die Tab-Taste, um einen Takt vorzurücken." //: /line:"Die Clear-Leitung ist nun gesetzt, das Register" //: /line:"wird zurückgesetzt. Setze nun die Clear" //: /line:"Leitung auf \"on\" und fahre fort, die \"Tab\"-Taste" //: /line:"zu drücken. Beobachte, wie der Registerwert mit jeder" //: /line:"Taktperiode hochzählt." //: /end //: DIP g3 (w4) @(208,104) /sn:0 /w:[ 0 ] /st:1 _GGADD8 #(68, 70, 62, 64) g2 (.A(w4), .B(reg_out), .S(w5), .CI(w11), .CO(w12)); //: @(224,183) /sn:0 /w:[ 1 5 0 1 0 ] //: SWITCH g1 (w8) @(325,297) /sn:0 /R:1 /w:[ 1 ] /st:0 //: comment g11 @(348,218) //: /line:"5) Stelle sicher, daß die Clear" //: /line:"Leitung CLR \"off\" ist, um das" //: /line:"Register zurückzusetzen." //: /end //: comment g10 @(270,64) //: /line:"4) Setze den DIP Schalter auf 1" //: /line:"(draufklicken, Eingeben einer" //: /line:"\"1\" in die Dialogbox die sich" //: /line:"öffnet) und drücke \"Anwenden\"." //: /end //: GROUND g6 (w11) @(269,203) /sn:0 /w:[ 0 ] //: comment g9 @(198,354) //: /line:"3) Setze einen Tastkopf auf den" //: /line:"Registerausgang durch" //: /line:"Doppelklick." //: /end //: SWITCH g7 (w9) @(324,232) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g39 @(20,12) /sn:0 //: /line:"[ZURÃœCK]" //: /end //: LED g17 (reg_out) @(386,171) /sn:0 /R:3 /w:[ 3 ] /type:2 //: joint g14 (reg_out) @(297, 171) /w:[ 2 4 -1 1 ] //: comment g5 @(14,33) //: /line:"8-Bit Zähler" //: /line:"" //: /line:"1) Starte die Simulation durch Eingabe von" //: /line:"\"Ctl-S b\" auf der Tastatur" //: /line:"" //: /end _GGREG8 #(10, 10, 20) g0 (.Q(reg_out), .D(w5), .EN(w8), .CLR(w9), .CK(ck)); //: @(224,264) /sn:0 /w:[ 0 1 0 0 0 ] //: comment g12 @(309,316) //: /line:"6) Stelle sicher, daß die Enable-Leitung" //: /line:"EN auf \"off\" steht." //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/de/examples/ex2/flipflop.v000644 001751 001751 00000010502 11137713517 022157 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "flipflop.v" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg w6; //: /sn:0 {0}(336,226)(336,171){1} //: {2}(338,169)(471,169){3} //: {4}(475,169)(630,169)(630,229){5} //: {6}(473,171)(473,226){7} //: {8}(334,169)(178,169){9} supply0 w4; //: /sn:0 {0}(661,215)(661,212)(640,212)(640,229){1} supply0 w3; //: /sn:0 {0}(499,211)(499,207)(483,207)(483,226){1} supply0 w0; //: /sn:0 {0}(346,226)(346,200)(362,200)(362,210){1} wire w7; //: /sn:0 {0}(494,247)(504,247){1} wire w16; //: /sn:0 {0}(435,235)(446,235)(446,242)(462,242){1} wire w19; //: /sn:0 {0}(555,270)(564,270)(564,247)(574,247){1} wire w15; //: /sn:0 {0}(458,122)(458,139)(380,139)(380,235){1} //: {2}(382,237)(414,237){3} //: {4}(378,237)(357,237){5} //: {6}(380,239)(380,272)(534,272){7} wire w1; //: /sn:0 {0}(357,247)(367,247)(367,277)(312,277)(312,242)(325,242){1} wire [2:0] w17; //: /sn:0 {0}(#:448,116)(448,91){1} wire w12; //: /sn:0 {0}(595,245)(619,245){1} wire w11; //: /sn:0 {0}(438,122)(438,152)(677,152)(677,188){1} //: {2}(675,190)(564,190)(564,242)(574,242){3} //: {4}(677,192)(677,240)(651,240){5} wire w2; //: /sn:0 {0}(175,344)(339,344){1} //: {2}(343,344)(476,344){3} //: {4}(480,344)(635,344)(635,261){5} //: {6}(478,342)(478,258){7} //: {8}(341,342)(341,258){9} wire w13; //: /sn:0 {0}(651,250)(661,250){1} wire w5; //: /sn:0 {0}(494,237)(518,237){1} //: {2}(520,235)(520,194){3} //: {4}(520,190)(520,133)(448,133)(448,122){5} //: {6}(518,192)(404,192)(404,232)(414,232){7} //: {8}(520,239)(520,267)(534,267){9} //: enddecls //: GROUND g8 (w3) @(499,217) /sn:0 /w:[ 0 ] _GGCLOCK_P100_0_50 g4 (.Z(w2)); //: @(162,344) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g3 (w0) @(362,216) /sn:0 /w:[ 1 ] //: LED g13 (w17) @(448,84) /sn:0 /w:[ 1 ] /type:1 _GGFF #(10, 10, 20) g2 (.Q(w11), ._Q(w13), .D(w12), .EN(w4), .CLR(w6), .CK(w2)); //: @(635,245) /sn:0 /w:[ 5 0 1 1 5 5 ] /mi:0 _GGFF #(10, 10, 20) g1 (.Q(w5), ._Q(w7), .D(w16), .EN(w3), .CLR(w6), .CK(w2)); //: @(478,242) /sn:0 /w:[ 0 0 1 1 7 7 ] /mi:0 //: joint g16 (w5) @(520, 192) /w:[ -1 4 6 3 ] //: joint g11 (w2) @(341, 344) /w:[ 2 8 1 -1 ] _GGAND2 #(6) g19 (.I0(w5), .I1(w15), .Z(w19)); //: @(545,270) /sn:0 /w:[ 9 7 0 ] /eb:0 //: joint g6 (w6) @(336, 169) /w:[ 2 -1 8 1 ] //: GROUND g9 (w4) @(661,221) /sn:0 /w:[ 0 ] //: joint g7 (w6) @(473, 169) /w:[ 4 -1 3 6 ] //: joint g20 (w5) @(520, 237) /w:[ -1 2 1 8 ] _GGXOR2 #(8) g15 (.I0(w5), .I1(w15), .Z(w16)); //: @(425,235) /sn:0 /w:[ 7 3 0 ] /eb:0 //: comment g39 @(20,12) /sn:0 //: /line:"[ZURÃœCK]" //: /end //: joint g17 (w15) @(380, 237) /w:[ 2 1 4 6 ] assign w17 = {w11, w5, w15}; //: CONCAT g14 @(448,117) /sn:0 /R:1 /w:[ 0 0 5 0 ] /dr:0 /tp:0 /drp:1 //: SWITCH g5 (w6) @(161,169) /sn:0 /w:[ 9 ] /st:1 //: joint g21 (w11) @(677, 190) /w:[ -1 1 2 4 ] _GGFF #(10, 10, 20) g0 (.Q(w15), ._Q(w1), .D(w1), .EN(w0), .CLR(w6), .CK(w2)); //: @(341,242) /sn:0 /w:[ 5 0 1 0 0 9 ] /mi:0 _GGXOR2 #(8) g18 (.I0(w11), .I1(w19), .Z(w12)); //: @(585,245) /sn:0 /w:[ 3 1 0 ] /eb:0 //: joint g12 (w2) @(478, 344) /w:[ 4 6 3 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGFF #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, _Q, D, EN, CLR, CK); input CK,EN,CLR; input D; output Q,_Q; reg Qreg; specify $setup(D,posedge CK, Dsetup); $hold(posedge CK,D, Dhold); endspecify assign #Dck_q Q = Qreg; assign #Dck_q _Q = ~Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 1'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/de/examples/ex1/combinational.v000644 001751 001751 00000013443 11137713464 023172 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "combinational.v" //: property discardChanges = 1 //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg A0; //: {0}(173,94)(163,94){1} //: {2}(67:159,94)(95,94){3} //: {4}(161,96)(161,154)(173,154){5} reg w0; //: /sn:0 {0}(239,92)(219,92){1} //: {2}(217,90)(217,50){3} //: {4}(217,94)(217,117){5} reg A2; //: {0}(165,415)(155,415){1} //: {2}(60:151,415)(96,415){3} //: {4}(153,417)(153,475)(165,475){5} reg B2; //: {0}(30:100,480)(142,480){1} //: {2}(146,480)(165,480){3} //: {4}(144,478)(144,420)(165,420){5} reg B1; //: {0}(50:98,317)(142,317){1} //: {2}(146,317)(169,317){3} //: {4}(144,315)(144,257)(169,257){5} reg A1; //: {0}(169,252)(159,252){1} //: {2}(61:155,252)(96,252){3} //: {4}(157,254)(157,312)(169,312){5} reg B0; //: {0}(50:93,159)(144,159){1} //: {2}(148,159)(173,159){3} //: {4}(146,157)(146,99)(173,99){5} wire w6; //: /sn:0 {0}(215,171)(215,138){1} wire S1; //: {0}(50:303,253)(257,253){1} wire w14; //: /sn:0 {0}(211,329)(211,296){1} wire w19; //: /sn:0 {0}(231,413)(211,413){1} //: {2}(209,411)(209,350){3} //: {4}(209,415)(209,438){5} wire w4; //: /sn:0 {0}(239,97)(214,97){1} //: {2}(210,97)(194,97){3} //: {4}(212,99)(212,117){5} wire w3; //: /sn:0 {0}(210,171)(210,157)(194,157){1} wire C3; //: {0}(23:303,533)(205,533)(205,513){1} wire w21; //: /sn:0 {0}(202,492)(202,478)(186,478){1} wire S0; //: {0}(50:303,95)(260,95){1} wire w18; //: /sn:0 {0}(231,418)(206,418){1} //: {2}(202,418)(186,418){3} //: {4}(204,420)(204,438){5} wire w22; //: /sn:0 {0}(207,492)(207,459){1} wire w11; //: /sn:0 {0}(236,250)(215,250){1} //: {2}(213,248)(213,192){3} //: {4}(213,252)(213,275){5} wire w10; //: /sn:0 {0}(236,255)(210,255){1} //: {2}(206,255)(190,255){3} //: {4}(208,257)(208,275){5} wire w13; //: /sn:0 {0}(206,329)(206,315)(190,315){1} wire S2; //: {0}(50:303,416)(252,416){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w4), .I1(w0), .Z(w6)); //: @(215,128) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: SWITCH g4 (B0) @(76,159) /sn:0 /w:[ 0 ] /st:1 //: LED g37 (S2) @(310,416) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g34 @(351,22) //: /line:"Ein einfacher 3-Bit-Addierer." //: /line:"" //: /line:"Starte den Simulator durch Drücken des \"Abspielen\"" //: /line:"Knopfes aus der Knopfleiste. Setze dann Tastköpfe" //: /line:"durch Doppelklick auf die Leitungen S0, S1, S2 and C3" //: /line:"(und beliebige zusätzliche Leitungen, die getastet" //: /line:"werden sollen). Drücke wieder den \"Abspielen\" Knopf" //: /line:"um in den kontinuierlichen Simulationsmodus einzutreten." //: /line:"Immer, wenn sich ein Schalterwert ändert (durch Klicken)" //: /line:"simuliert der Simulator so lange, bis sich alle Werte" //: /line:"stabilisiert haben." //: /line:"Beende die Simulation durch Drücken des \"stop\"" //: /line:"Knopfes auf der Knopfleiste." //: /end _GGXOR2 #(8) g13 (.I0(A1), .I1(B1), .Z(w10)); //: @(180,255) /sn:0 /w:[ 0 5 3 ] /eb:0 //: SWITCH g3 (w0) @(217,37) /sn:0 /R:3 /w:[ 3 ] /st:0 _GGXOR2 #(8) g2 (.I0(w0), .I1(w4), .Z(S0)); //: @(250,95) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGXOR2 #(8) g1 (.I0(A0), .I1(B0), .Z(w4)); //: @(184,97) /sn:0 /w:[ 0 5 3 ] /eb:0 _GGNAND2 #(4) g16 (.I0(A1), .I1(B1), .Z(w13)); //: @(180,315) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g11 (.I0(w3), .I1(w6), .Z(w11)); //: @(213,182) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: joint g28 (A2) @(153, 415) /w:[ 1 -1 2 4 ] //: joint g10 (w4) @(212, 97) /w:[ 1 -1 2 4 ] //: joint g32 (w18) @(204, 418) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g27 (.I0(A2), .I1(B2), .Z(w21)); //: @(176,478) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g19 (.I0(w10), .I1(w11), .Z(w14)); //: @(211,286) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g38 (C3) @(310,533) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g6 (A0) @(161, 94) /w:[ 1 -1 2 4 ] //: joint g9 (w0) @(217, 92) /w:[ 1 2 -1 4 ] //: joint g7 (B0) @(146, 159) /w:[ 2 4 1 -1 ] //: joint g31 (w19) @(209, 413) /w:[ 1 2 -1 4 ] //: joint g20 (w11) @(213, 250) /w:[ 1 2 -1 4 ] //: SWITCH g15 (B1) @(81,317) /sn:0 /w:[ 0 ] /st:0 //: comment g39 @(20,12) /sn:0 //: /line:"[ZURÃœCK]" //: /end //: joint g29 (B2) @(144, 480) /w:[ 2 4 1 -1 ] _GGXOR2 #(8) g25 (.I0(w19), .I1(w18), .Z(S2)); //: @(242,416) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g17 (A1) @(157, 252) /w:[ 1 -1 2 4 ] _GGXOR2 #(8) g14 (.I0(w11), .I1(w10), .Z(S1)); //: @(247,253) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g5 (.I0(A0), .I1(B0), .Z(w3)); //: @(184,157) /sn:0 /w:[ 5 3 1 ] /eb:0 //: LED g36 (S1) @(310,253) /sn:0 /R:3 /w:[ 0 ] /type:0 _GGXOR2 #(8) g24 (.I0(A2), .I1(B2), .Z(w18)); //: @(176,418) /sn:0 /w:[ 0 5 3 ] /eb:0 //: joint g21 (w10) @(208, 255) /w:[ 1 -1 2 4 ] //: SWITCH g23 (A2) @(79,415) /sn:0 /w:[ 3 ] /st:0 //: LED g35 (S0) @(310,95) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g26 (B2) @(83,480) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g22 (.I0(w13), .I1(w14), .Z(w19)); //: @(209,340) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: SWITCH g0 (A0) @(78,94) /sn:0 /w:[ 3 ] /st:0 //: joint g18 (B1) @(144, 317) /w:[ 2 4 1 -1 ] //: SWITCH g12 (A1) @(79,252) /sn:0 /w:[ 3 ] /st:1 _GGNAND2 #(4) g33 (.I0(w21), .I1(w22), .Z(C3)); //: @(205,503) /sn:0 /R:3 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g30 (.I0(w18), .I1(w19), .Z(w22)); //: @(207,449) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/de/examples/ex5/menagerie.mem.bak000644 001751 001751 00000020560 07311226664 023356 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 40/ f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 48/ f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 50/ f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 58/ f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 60/ f82000 f82000 d92000 d92000 f7ae008 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_mbdr 0000008d _mbrd 0000007b _mwdi 000000a9 _mwdr 00000091 _mwrd 0000007f alu_ri 0000000d alu_rr 0000000b bdojmp 00000029 br_d 0000002d br_i 00000022 br_r 0000002b br_x 0000002f btest 00000025 call_di 0000004b call_ii 00000031 call_ri 00000049 call_xi 0000004d cmp_ri 0000001d cmp_rr 0000001b fetch 00000005 fetch1 00000006 fetch2 00000007 halt 00000009 movb_dd 000000a4 movb_di 000000b2 movb_dr 0000008c movb_dx 000000a6 movb_rd 0000007a movb_ri 00000075 movb_rr 0000006d movb_rx 00000084 movb_xd 000000a2 movb_xi 000000bc movb_xr 00000097 movb_xx 000000a0 movw_dd 000000a3 movw_di 000000a8 movw_dr 00000090 movw_dx 000000a5 movw_rd 0000007e movw_ri 00000070 movw_rr 0000006b movw_rx 00000088 movw_xd 000000a1 movw_xi 000000b8 movw_xr 0000009b movw_xx 0000009f nop 000000c0 pushw_d 00000058 pushw_i 00000061 pushw_r 0000005a pushw_x 00000059 ret 0000004f start 00000000 xalu_ri 00000015 xalu_rr 00000012 Macrocode Symbole (total=69): Global Lokal --------------------------------------- buf 000005f8 dscrim 00000795 find_animal 0000017a done 0000025e get_response 000001a6 say_no 0000023e say_yes 0000021e tree fffffffe get_final 00000264 L1 0000037c L2 000003e8 L3 00000404 animal_node fffffffc discrim_node fffffffa done 00000420 get_response 00000268 loose 000002f0 tree fffffffe win 000002de gets 00000570 bell 000005d4 cwait 00000576 del_char 000005b8 done 000005e6 isita 000006f7 known 00000678 loosemsg 0000075e main 00000112 loop 0000013e malloc 00000426 mend 000007f6 nl 000007f1 no 00000724 no_b 00000002 nprint 000004e8 zprint 000004fe nprint_aux 0000050c done 00000546 nsize 00000064 numk 000006d8 print 00000430 done 0000044c loop 00000434 printf 0000044e L1 00000474 L2 000004a2 arg fffffffc cout 000004d4 done 000004e6 loop 0000045c ptr fffffffe qprompt 000007f3 root 0000067a sdone 0000010e start 00000100 strcmp 00000548 done 0000056e loop 00000550 text 00000004 think 0000069f top_node 0000067c ttydata 00000011 ttystatus 00000010 welcome 00000689 which 000007d0 winmsg 00000743 yes 00000720 yes_b 00000000 yesno 00000727 tkgate-2.0-b10/locale/de/examples/ex5/menagerie.mem000644 001751 001751 00000016360 11131770415 022616 0ustar00hansenhansen000000 000000 @memory iunit.m1 @0 f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 f82000 f82000 d92000 d92000 f7ae008 fa2000 f82000 fa2000 f82000 f83c17 f82000 7bfc1f f80000 fbe000 fabc1f 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@memory iunit.map @3e c0 @0 9 @2 1b 1d @a0 2b 22 2d 2f @68 b d b d @60 12 15 @78 12 15 @70 12 15 @50 b d @80 49 31 4b 4d @4 4f @84 5a 61 58 59 @f0 6d 75 7a 84 @f8 8c b2 a4 a6 97 bc a2 a0 @e0 6b 70 7e 88 @e8 90 a8 a3 a5 9b b8 a1 9f @memory memory.m1 @100 e1 f0 0 0 e1 e0 0 0 81 0 0 0 12 1 bd 0 e 1 e1 d0 e6 7 85 0 79 6 81 0 0 0 3e 4 69 f0 2 0 ed 0 6a 6 6c 6 ed 0 68 6 1 0 85 0 8f 6 81 0 0 0 3e 4 69 f0 2 0 e3 10 68 6 84 10 85 0 c8 6 81 0 0 0 3e 4 69 f0 4 0 e3 10 6a 6 84 10 81 0 0 0 6c 1 69 f0 2 0 ec 1 6a 6 bd 0 30 1 4 0 6b f0 2 0 e3 1e 4 0 ec e1 fe ff e3 21 0 0 3 20 0 0 a1 0 98 1 84 10 81 0 0 0 56 2 69 f0 2 0 ec e1 fe ff bd 0 50 2 e3 1e fe ff e0 41 69 40 4 0 84 40 81 0 0 0 20 4 69 f0 2 0 85 0 e3 7 81 0 0 0 20 4 69 f0 2 0 85 0 e8 5 81 0 0 0 60 5 69 f0 2 0 85 0 e8 5 85 0 10 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 10 2 85 0 e8 5 85 0 14 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 30 2 85 0 @200 17 7 81 0 0 0 20 4 69 f0 2 0 bd 0 98 1 e3 1e fe ff e3 21 0 0 84 20 81 0 0 0 6c 1 69 f0 2 0 e3 2e fe ff ec 21 0 0 bd 0 50 2 e3 1e fe ff e3 21 2 0 84 20 81 0 0 0 6c 1 69 f0 2 0 e3 2e fe ff ec 21 2 0 bd 0 50 2 e3 1e fe ff 4 0 6b f0 6 0 e3 1e 4 0 ec e1 fe ff e3 1e 4 0 69 10 4 0 84 10 85 0 e7 6 81 0 0 0 3e 4 69 f0 4 0 85 0 e8 5 81 0 0 0 60 5 69 f0 2 0 85 0 e8 5 85 0 10 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 ce 2 85 0 e8 5 85 0 14 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 e0 2 85 0 17 7 81 0 0 0 20 4 69 f0 2 0 bd 0 5a 2 85 0 33 7 81 0 0 0 3e 4 69 f0 2 0 bd 0 10 4 85 0 4e 7 81 0 0 0 3e 4 69 f0 2 0 85 0 68 0 81 0 0 0 16 4 69 f0 2 0 ec e1 fc ff @300 ed 10 0 0 0 0 ed 10 2 0 0 0 69 10 4 0 84 10 81 0 0 0 60 5 69 f0 2 0 e3 1e fe ff 69 10 4 0 84 10 e3 1e fc ff 69 10 4 0 84 10 85 0 85 7 81 0 0 0 3e 4 69 f0 6 0 85 0 68 0 81 0 0 0 16 4 69 f0 2 0 ec e1 fa ff 69 10 4 0 84 10 81 0 0 0 60 5 69 f0 2 0 e3 10 68 6 69 10 1 0 ec 1 68 6 e3 1e fc ff 69 10 4 0 84 10 85 0 c0 7 81 0 0 0 3e 4 69 f0 4 0 85 0 e8 5 81 0 0 0 60 5 69 f0 2 0 85 0 e8 5 85 0 10 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 d8 3 85 0 e8 5 85 0 14 7 81 0 0 0 34 5 69 f0 4 0 3 10 0 0 a9 0 f4 3 85 0 17 7 81 0 0 0 3e 4 69 f0 2 0 bd 0 6c 3 e3 1e fa ff e3 2e fe ff e3 3e fc ff ec 13 0 0 ec 12 2 0 ec e1 fe ff bd 0 10 4 e3 1e fa ff e3 2e fe ff e3 3e fc ff @400 ec 12 0 0 ec 13 2 0 ec e1 fe ff bd 0 10 4 e3 1e fe ff 4 0 e3 2e 4 0 e0 1d 68 d2 4 0 e3 1e 4 0 f2 21 a9 0 3c 4 fc 2 11 0 fd 0 10 0 1 0 69 10 1 0 bd 0 24 4 4 0 6b f0 4 0 e0 3e 69 30 6 0 e3 1e 4 0 f2 21 a9 0 d2 4 3 20 25 0 a1 0 c0 4 69 10 1 0 f2 21 69 10 1 0 3 20 73 0 a1 0 92 4 ec e1 fe ff ec e3 fc ff e2 23 84 20 81 0 0 0 20 4 69 f0 2 0 e3 1e fe ff e3 3e fc ff 69 30 2 0 bd 0 4c 4 3 20 64 0 a1 0 4c 4 ec e1 fe ff ec e3 fc ff e2 23 84 20 81 0 0 0 d4 4 69 f0 2 0 e3 1e fe ff e3 3e fc ff 69 30 2 0 bd 0 4c 4 fc 2 11 0 fd 0 10 0 1 0 69 10 1 0 bd 0 4c 4 4 0 e3 1e 4 0 a9 0 ea 4 84 10 81 0 0 0 f8 4 69 f0 2 0 4 0 fd 0 11 0 30 0 fd 0 10 0 1 0 4 0 6b f0 2 0 e3 1e 4 0 @500 a9 0 32 5 e0 21 79 20 a 0 e0 31 71 30 a 0 ec e3 fe ff 84 20 81 0 0 0 f8 4 69 f0 2 0 e3 3e fe ff 69 30 30 0 fc 3 11 0 fd 0 10 0 1 0 4 0 e3 2e 4 0 e3 3e 6 0 f2 12 a9 0 5a 5 f2 43 a9 0 5a 5 6a 14 a1 0 5e 5 69 20 1 0 69 30 1 0 bd 0 3c 5 f2 43 6a 14 4 0 e3 1e 4 0 e0 41 f3 20 10 0 51 20 2 0 a9 0 66 5 f3 30 11 0 fd 0 10 0 2 0 3 30 d 0 a9 0 d6 5 3 30 8 0 a9 0 a8 5 3 30 7f 0 a9 0 a8 5 fc 3 11 0 fd 0 10 0 1 0 f8 13 69 10 1 0 bd 0 66 5 2 14 b5 0 c4 5 f1 30 7f 0 6b 10 1 0 fc 3 11 0 fd 0 10 0 1 0 bd 0 66 5 f1 30 7 0 fc 3 11 0 fd 0 10 0 1 0 bd 0 66 5 fd 0 11 0 a 0 fd 0 10 0 1 0 f9 10 0 0 4 0 @66c 0 0 0 0 61 61 72 64 76 61 72 6b 0 a 57 65 6c 63 6f 6d 65 20 74 6f 20 41 6e 69 6d 61 6c 73 2e a 0 a 54 68 69 6e 6b 20 6f 66 20 61 6e 20 61 6e 69 6d 61 6c 20 61 6e 64 20 49 20 77 69 6c 6c 20 74 72 79 20 74 6f 20 67 75 65 73 73 20 77 68 61 74 20 69 74 20 69 73 2e a 0 49 20 63 75 72 72 65 6e 74 6c 79 20 6b 6e 6f 77 20 25 64 20 61 6e 69 6d 61 6c 73 2e a a 0 49 73 20 74 68 65 20 61 6e 69 6d 61 6c 20 79 6f 75 20 61 72 65 20 74 68 69 @700 6e 6b 69 6e 67 20 6f 66 20 61 20 25 73 3f 20 0 79 65 73 0 6e 6f 0 50 6c 65 61 73 65 20 74 79 70 65 20 27 79 65 73 27 20 6f 72 20 27 6e 6f 27 2e a 0 49 20 67 75 65 73 73 65 64 20 79 6f 75 72 20 61 6e 69 6d 61 6c 21 21 21 a a 0 49 20 63 6f 75 6c 64 20 6e 6f 74 20 67 75 65 73 73 20 79 6f 75 72 20 61 6e 69 6d 61 6c 2e 20 20 57 68 61 74 20 77 61 73 20 79 6f 75 72 20 61 6e 69 6d 61 6c 3f 20 0 45 6e 74 65 72 20 61 20 71 75 65 73 74 69 6f 6e 20 74 68 61 74 20 77 6f 75 6c 64 20 64 69 73 74 69 6e 67 75 69 73 68 20 61 20 25 73 20 66 72 6f 6d 20 61 20 25 73 2e a 3e 20 0 54 68 65 20 63 6f 72 72 65 63 74 20 61 6e 73 77 65 72 20 66 6f 72 20 61 20 25 73 20 69 73 3f 20 0 a 0 3f 20 0 tkgate-2.0-b10/locale/de/examples/ex5/menagerie.gm000644 001751 001751 00000132563 07311226664 022456 0ustar00hansenhansen000000 000000 // // Copyright (C) 1987-2000 by Jeffery P. Hansen // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. // // Last edit by hansen on Fri Dec 1 14:34:44 2000 // // Microcode memory bank declarations microcode bank[31:0] iunit.m1; microcode bank[63:32] iunit.m2; map bank[7:0] iunit.map; macrocode bank[7:0] memory.m1; // Microcode field declarations // // Microcode branching. mpcop specifies the basic operation. // field mpcop[1:0]={ next=0, // Increment mpc reinit=1, // Restart CPU jmap=2, // Jump from map value jump=3 // Jump from condition }; // // Specifies the condition on which to jump if mpcop is "jump". // field mpccond[12:10]={ jne=0, // Jump if not equal jcarry=1, // Jump on carry jeq=2, // Jump if equal jlt=3, // Jump if less than jgt=4, // Jump if greater than jle=5, // Jump if less than or equal jge=6, // Jump if greater than or equal jmp=7 // Jump always }; // // Address to jump to if mpcop is "jump" and condition specified // by mpccond is true. This field can not be used at the same // time as the idata field. // field mpcaddr[9:2]; // // Specifies 8 bits of data to be used by the EUNIT. This field // can not be used on jump microinstructions. // field idata[9:2]; // // Specifies the A and B operands of the ALU. // // qreg Use Q register // din Use data in // idata Use idata field from microinstruction // reg Use register file // field aop[15:14]={qreg=0, din=1, idata=2, reg=3}; field bop[17:16]={qreg=0, din=1, idata=2, reg=3}; field ~ldir[13]; // Load instruction register field cin[18]; // Carry in field ~clq[19]; // Clear Q register field ~ldq[20]; // 16-bit load of Q register field ~lddata[21]; // Load EUNIT data from external bus field ~ldopr[22]; // Load operand register field ~wa[23]; // Write register file on SA field sa[27:24]; // Register address A field sb[31:28]; // Register address B // // These fields specify the ALU function. // field ALU_FUNC[36:32]; field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3}; field ALU_BCOMP[32]; field ALU_AZERO[33]; field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7}; field ~incpc[37]; // Increment PC field ~ldmar[38]; // Load MAR field ~ldmdr[39]; // Load MDR field ~ldpc[40]; // Load PC field ~rd[41]; // Read main memory field ~rdmdr[42]; // Read MDR onto external data bus field ~wrt[43]; // Write main memory field spc[44]; // Address main memory from PC field ~isa[45]; // Use sa address from macro instruction field ~isb[46]; // Use sb address from macro instruction field ~ifunc[47]; // Use function code from macro instruction field ~icond[48]; // Use branch condition from macro instruction field ~ldql[49]; // 8-bit load of lower half of Q register field ~ldqh[50]; // 8-bit load of upper half of Q register field ~dout[51]; // Output EUNIT data to external bus field ~ldcc[52]; // Load condition code register field ~ldhmdr[53]; // Load mdr from high byte of data bus field ~rdpc[54]; // Read PC onto external bus field ~incmar[55]; // Increment mar (can't use with incpc) field extra[63:56]; // Extra bits ////////////////////////////////////////////////////////////////////// // // +-+-+-+-+-+-+-+-+ // |7|6|5|4|3|2|1|0| // +-+-+-+-+-+-+-+-+ // // Basic instruction types are encoded by the high two bits of the // first byte of the instruction. For certain types (e.g., ALU // types) some bits are masked when forming the map address. Bits // contributing to the map vector are marked with a *. // // Move Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 1 1 s|a a|b b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // s = size (1 = byte, 0 = word) // aa = operand mode 1 // bb = operand mode 2 // // Single operand instruction (push, pop, call, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0| op |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // // Branch instruction (jmp, jne, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|cond |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * // // // ALU Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1| func |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * // // func = ALU function // a = operand mode // // Other instructions // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0| op |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15; operands basic { %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands runiop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; #1 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands wuniop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; // // Operands for move instructions // operands movoprs { %1,%2 = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; %1,(%2) = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; %1,#3(%2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; %1,(#2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),%2 = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#2 = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),(%2) = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#3(%2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; (%1),(#2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; #1(%2),%3 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#3 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; #1(%2),(%3) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; }; #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),%2 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#2 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; (#1),(%2) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),(#2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|1 1 1 1 1|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op nop { map nop : 0x3e; +0=0x3e; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op halt { map halt : 0x0; +0=0; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 1|0| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op cmp { map cmp_rr : 0x2; map cmp_ri : 0x3; +0[7:1]=0x1; operands basic; }; // Generic branch operation // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|x x x|b b| |0 0 0 0| reg1 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // br #7, loop // // Jump always to loop. 7 is a code indicating the condition always. // op jp { map br_r : 0xa0; map br_i : 0xa1; map br_d : 0xa2; map br_x : 0xa3; +0[7:5] = 0x5; operands { #1,%2 = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#2 = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; }; }; }; op jne { +0[7:5] = 0x5; +0[4:2] = 0x0; operands runiop; }; op jcarry { +0[7:5] = 0x5; +0[4:2] = 0x1; operands runiop; }; op jeq { +0[7:5] = 0x5; +0[4:2] = 0x2; operands runiop; }; op jlt { +0[7:5] = 0x5; +0[4:2] = 0x3; operands runiop; }; op jgt { +0[7:5] = 0x5; +0[4:2] = 0x4; operands runiop; }; op jle { +0[7:5] = 0x5; +0[4:2] = 0x5; operands runiop; }; op jge { +0[7:5] = 0x5; +0[4:2] = 0x6; operands runiop; }; op jmp { +0[7:5] = 0x5; +0[4:2] = 0x7; operands runiop; }; // Generic ALU operation // // Note this is not a real instruction but is here for illustrative // purposes only. Map entries must be made for each function code // to use this instruction for real. // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|x x x x x|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // alu #0x14, R1, R2 // // Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1. // //op alu { // map alu_rr : 0x40; // map alu_ri : 0x41; // +0[7:6] = 0x1; // operands { // #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; }; // #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; // }; //}; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op add { map alu_rr : 0x68; map alu_ri : 0x69; +0[7:0]=0x68; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 1|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op sub { map alu_rr : 0x6a; map alu_ri : 0x6b; +0[7:0]=0x6a; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mul { map xalu_rr : 0x60; map xalu_ri : 0x61; +0[7:0]=0x60; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op div { map xalu_rr : 0x78; map xalu_ri : 0x79; +0[7:0]=0x78; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mod { map xalu_rr : 0x70; map xalu_ri : 0x71; +0[7:0]=0x70; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|0 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op and { map alu_rr : 0x50; map alu_ri : 0x51; +0[7:0]=0x50; operands basic; }; // Call subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 0|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // call foo, #8 // // This will perform the following actions: // sp = sp - 2 // [sp] = pc // sp = sp - 2 // [sp] = fp // fp = sp // sp = sp+8 // pc = foo // op call { map call_ri : 0x80; map call_ii : 0x81; map call_di : 0x82; map call_xi : 0x83; +0[7:4] = 0x8; operands { #1,%2 = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1 = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; }; }; }; // Return from subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 1 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // ret // // This will perform the following actions: // sp = fp // fp = [sp] // sp = sp + 2 // pc = [sp] // sp = sp + 2 // // op ret { map ret : 0x4; +0=4; operands { - = { +1=0; }; }; }; // Push a word on the stack // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 1|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // pushw R1 // op pushw { map pushw_r : 0x84; map pushw_i : 0x85; map pushw_d : 0x86; map pushw_x : 0x87; +0[7:2]=0x21; operands runiop; }; op movb { map movb_rr : 0xf0; map movb_ri : 0xf1; map movb_rd : 0xf2; map movb_rx : 0xf3; map movb_dr : 0xf8; map movb_di : 0xf9; map movb_dd : 0xfa; map movb_dx : 0xfb; map movb_xr : 0xfc; map movb_xi : 0xfd; map movb_xd : 0xfe; map movb_xx : 0xff; +0[7:4]=0xf; operands movoprs; }; op movw { map movw_rr : 0xe0; map movw_ri : 0xe1; map movw_rd : 0xe2; map movw_rx : 0xe3; map movw_dr : 0xe8; map movw_di : 0xe9; map movw_dd : 0xea; map movw_dx : 0xeb; map movw_xr : 0xec; map movw_xi : 0xed; map movw_xd : 0xee; map movw_xx : 0xef; +0[7:4]=0xe; operands movoprs; }; ///////////////////////////////////////////////////////////////////////////// // // The microcode for the Menagerie CPU begins here. // // The CPU begins executing microinstuctions at address 0. The instructions // in the start block are executed only once. The next block consists of // the instuction fetch sequnce. The multiple labels account for partial // fetches that are done by some of the macrocode routines. // // For macro instructions which have no operands or have only only one operand, // there is usually a plain label for that instruction. For example the // microinstruction labeled 'ret' implements the 'ret' macroinstruction. This // mapping is defined by the 'map ret : 0x4;' line in the operand declaration // for the ret macroinstruction. // // For macro instructions with multiple addressing modes, labels are generally // of the form 'op_??' where each character after the '_' denotes an addressing // mode for an operand. By convension, the characters: // // r register direct // i immediate // d register indirect // x indexed // // are used. // begin microcode @ 0 start: clq; // Q <- 0 idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh; // Q.H <- 1 ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to 'fetch' mpcop=next; fetch: incpc spc rd ldmdr; // mdr <- [PC]; PC++; fetch1: incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; fetch2: mpcop=jmap rdmdr ldopr; // opr <- mdr; jump to opcode mpcop=next; halt: mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; // // Standard ALU operations (add, sub, and, or, etc.) // alu_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; alu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; // // 2-cycle ALU operations (mul, div, mod). These are the same as the alu_?? // ops except the ALU inputs and function code are held for 2 clock cycles // due to the longer delay in computing these functions. // xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg; // Ra (op) Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; xalu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=next ifunc isa isb aop=reg bop=qreg; // Ra (op) Q; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; cmp_rr: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22 isa isb aop=reg bop=reg ldcc; // Ra - Rb; CC; jump to fetch mpcop=next; cmp_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP aop=reg bop=qreg isa ldcc; // Ra - Q; CC; jump to fetch mpcop=next; br_i: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; btest: mpcop=jump mpcaddr=bdojmp icond; // jump to bdojmp if cond mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to fetch mpcop=next; bdojmp: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q, jump to fetch mpcop=next; br_r: mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10 isa aop=reg sb=0 bop=reg ALU_OP=add ldq; // Q <- Ra; jump to btest mpcop=next; br_d: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; br_x: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; call_ii: // Push the PC aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa extra=0x11; // SP-2 -> mar; SP = SP - 2; rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq; // Q = PC+4 ALU_AZERO ALU_OP=add bop=qreg dout ldmdr; // Q.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr; // Q.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; mpcop=next; // Push the FP aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa; // SP-2 -> mar; SP = SP - 2; ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr; // FP.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldhmdr; // SP.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; aop=reg sa=0xe bop=reg sb=0xf ALU_AZERO ALU_OP=add wa; // FP <- SP // Dec SP incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=qreg ALU_OP=add wa; // SP = SP + Q // PC = branch address incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q mpcop=next; call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_di: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; ret: ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12; // SP <- FP; mar <- FP; aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr; // SP <- SP+4; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr; // FP <- Q; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch1 ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q; jump fetch1 incpc spc rd ldmdr; // mdr <- [PC]; PC++; pushw_d: mpcop=next; pushw_x: mpcop=next; pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Rb.L; wrt; // [mar] <- mdr; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; pushw_i: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Q.L; wrt; // [mar] <- mdr; aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add isa isb wa aop=reg bop=reg ldcc extra=1 incpc spc rd ldmdr; // Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql; // Q.L <- Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata ALU_OP=add ldqh incpc spc rd ldmdr; // Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++; ALU_AZERO ALU_OP=add bop=qreg isa wa incpc spc rd ldmdr rdmdr ldir; // Ra <- Q; mdr <- [PC]; PC++; ir <- mdr; movw_ri: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_ri:incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0; // Q.H = 0; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mbrd: rd ldmdr; // mdr <- [mar] mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa; // Ra <- mdr ALU_OP=add idata=0 bop=idata aop=reg isa ldcc; // CC movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mwrd: rd ldmdr incmar; // mdr <- [mar++] rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql; // Q.L <- mdr; mdr <- [mar++] lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add isa wa ldcc; // Ra <- Q; CC mpcop=next; movb_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mbrd isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q; movw_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mbdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mwdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb.L wrt; // [mar] <- mdr; isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mbdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mwdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xx: mpcop=next extra=7; movb_xx: mpcop=next extra=7; movw_xd: mpcop=next extra=7; movb_xd: mpcop=next extra=7; movw_dd: mpcop=next extra=7; movb_dd: mpcop=next extra=7; movw_dx: mpcop=next extra=7; movb_dx: mpcop=next extra=7; mpcop=next extra=7; movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar; // mar <- Ra _mwdi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L wrt; // [mar] <- mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra _mbdi: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q movb_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q nop: mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15; mpcop=next; end ///////////////////////////////////////////////////////////////////////////// // // General notes on assembler // Registers are not saved accross function calls unless explicitly saved. // Functions return values in R1. // The register R0 is a special "always 0" register. Writing to R0 will have no // effect other than to set condition codes. // // begin macrocode @ 0x100 ttydata: .symbol 0x11 // tty data in/out register ttystatus: .symbol 0x10 // tty status register // // Nodes have the format (note that pointers are two bytes): // // struct node { // struct node *yes_b; // struct node *no_b; // char text[100]; // }; // nsize: .symbol 104 // Size of a tree node. That is "sizeof(struct node)". yes_b: .symbol 0 // Pointer to yes side no_b: .symbol 2 // Pointer to no side text: .symbol 4 // Text of node (animal name or question) // // Execution starts here. // start: movw SP, 0 // Initialize stack pointer movw FP, 0 // Initialize frame pointer call main // Call main program sdone: jmp sdone // Infinite loop when main ends //////////////////// // main() // .proc main movw R13, mend // Use R13 as a sort of heap pointer pushw welcome // Push the "Welcome to" message call printf // Print the message add SP,2 // Restore stack pointer movw (root),top_node // Initialize root node movw (known),1 // Know one animal loop: pushw think // Push the "Think of an animal..." message call printf // Print the message add SP,2 // Restore stack pointer movw R1, (known) // Put number of known animals in R1 pushw R1 // Push that number on the stack pushw numk // Push the "I know %d animals" message call printf // Call printf to print message add SP,4 // Restore stack movw R1,(root) // Put the root pointer in R1 pushw R1 // Push the pointer on the stack call find_animal // Ask questions to find animal add SP,2 // Restore the stack movw (root),R1 // Save new root jmp loop // Go back and guess another animal ret // Return to call (actually we should never get here) .end //////////////////// // find_animal(p) Find the animal. p is the root node in question tree // .proc find_animal tree: .symbol -2 // Local variable for tree pointer sub SP,2 // Allocate space for local variables movw R1, 4(FP) // Get the pointer to top node movw tree(FP),R1 // Store it in "tree" movw R2,yes_b(R1) // Get pointer in "yes" branch of tree cmp R2,0 // Compare against 0 jne get_response // If not 0, then treat as question node pushw R1 // Push pointer to top node call get_final // As the final question, and insert new node if necessary add SP,2 // Restore stack movw tree(FP),R1 // Save new root node in "tree" jmp done // All done, go to final cleanup get_response: movw R1,tree(FP) // Put current node pointer in R1 movw R4,R1 // R4 = R1 add R4,text // Add offset to make R4 pointer to question pushw R4 // Push text of question call print // Print question in tree node add SP,2 // Restore stack pushw qprompt // Push "?" prompt call print // Print the "? " add SP,2 // Restore stack pushw buf // Push address of buffer in which to get response call gets // Read response from user add SP,2 // Restore stack pushw buf // Push users response on stack pushw yes // Push "yes" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_yes // If so, user answered "yes", goto say_yes pushw buf // Push users response on stack pushw no // Push "no" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_no // If so, user answered "no", goto say_no pushw yesno // Push the "yes or no" error message call print // Print error message add SP,2 // Restore stack jmp get_response // Go back and ask again say_yes: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,yes_b(R1) // Put "yes" branch pointer in R2 pushw R2 // Push the yes branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw yes_b(R2),R1 // Update the "yes" branch jmp done // Finish up and prepare to return to caller say_no: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,no_b(R1) // Put "no" branch pointer in R2 pushw R2 // Push the no branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw no_b(R2),R1 // Update the "no" branch jmp done // Finish up and prepare to return to caller done: movw R1,tree(FP) // Put new root node in R1 ret // Return to caller .end //////////////////// // get_final(p) Ask final question (at node p), and update tree if necessary. // .proc get_final tree: .symbol -2 // Local variable for tree pointer animal_node: .symbol -4 // Local variable for new animal node pointer discrim_node: .symbol -6 // Local variable for new question node pointer sub SP,6 // Allocate space for local variables get_response: movw R1, 4(FP) // Get pointer to current node movw tree(FP),R1 // Save it in the 'tree' variable movw R1, 4(FP) // Put pointer to tree in R1 add R1,text // Advance R1 to animal name text pushw R1 // Push pointer to animal name on stack pushw isita // Push the "is it a..." string pointer call printf // Print the final question add SP,4 // Restore stack pushw buf // Push buffer for response call gets // Get the response add SP,2 // Restore the stack pushw buf // Push response on stack pushw yes // Push "yes" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq win // If so, we guessed the animal pushw buf // Push response on stack pushw no // Push "no" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq loose // If so, we did not guess the animal pushw yesno // Push the "yes or no" error message call print // Print it add SP,2 // Restore stack jmp get_response // Go back and ask again win: pushw winmsg // Push the (computer) win message call printf // Print it add SP,2 // Restore stack jmp done // All done, go finish up and return loose: pushw loosemsg // Push the (computer) loose message call printf // Print it add SP,2 // Restore stack pushw nsize // Push number of bytes in a node call malloc // Allocate memory for new animal node add SP,2 // Restore stack movw animal_node(FP),R1 // Put address of new node in animal_node movw yes_b(R1),0 // Intialize yes branches movw no_b(R1),0 // Intialize no branches add R1,text // Move R1 to point to text area pushw R1 // Push text buffer call gets // Get animal name add SP,2 // Restore stack movw R1,tree(FP) // Put pointer to exiting node in R1 add R1,text // Advance to the text field pushw R1 // Push pointer to old animal name movw R1,animal_node(FP) // Put pointer to new node in R1 add R1,text // Advance to the text field pushw R1 // Push new animal name on stack pushw dscrim // Push "what is difference" question call printf // Print the question add SP,6 // Restore pointer pushw nsize // Allocate memory for discrimination node call malloc // Allocate memory for new discrimination node add SP,2 // Restore stack movw discrim_node(FP),R1 // Put address of new node in discrim_node add R1,text // Advance pointer to text field of discrimination node pushw R1 // Push pointer to text buffer to input question call gets // Input the question add SP,2 // Restore pointer movw R1, (known) // Put number of known animals in R1 add R1,1 // Increment R1 movw (known),R1 // Store number of known animals back in "known" L1: movw R1,animal_node(FP) // Put pointer to new animal node in R1 add R1,text // Advance R1 to the text field pushw R1 // Push new animal name on stack pushw which // Push the "..correct answer for..." message. call printf // Print the message add SP,4 // Restore stack pushw buf // Push text buffer on stack call gets // Input a "yes" or "no" add SP,2 // Restore stack pushw buf // Push user response pushw yes // Push string "yes" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L2 // If so, goto L2. New animal is on "yes" branch pushw buf // Push user response pushw no // Push string "no" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L3 // If so, goto L3. New animal is on "no" branch pushw yesno // Push the "yes or no" error message call printf // Print it add SP,2 // Restore stack jmp L1 // Go back and ask again // // Insert new animal on yes branch of new question // L2: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R3 // Set yes branch to new node movw no_b(R1),R2 // Set no branch to old node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return // // Insert new animal on no branch of new question // L3: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R2 // Set yes branch to old node movw no_b(R1),R3 // Set no branch to new node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return done: movw R1,tree(FP) // Put tree pointer into return register R1 ret // Return to caller .end //////////////////// // malloc(n) -> p Allocate n bytes and return address in R1. Allocated memory // can not be freed. // .proc malloc movw R2, 4(FP) // Get number of bytes movw R1,R13 // Pointer to block of memory add R13,R2 // Update heap pointer ret .end //////////////////// // print(s) Print the string s // .proc print movw R1, 4(FP) // Get parameter (string address) loop: movb R2, (R1) // Put character R1 is pointing to in R2 jeq done // If it was a 0, this is the end of the string movb (ttydata),R2 // Move char to the tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Move pointer to next char jmp loop // Go back and print more done: ret .end //////////////////// // printf(s,...) Print the format string // .proc printf ptr: .symbol -2 // Local var for string pointer arg: .symbol -4 // Local var for argument pointer sub SP,4 // Allocate 4 bytes for local variables movw R3,FP // Assign R3 and add an offset so that it points add R3,6 // to the argument after the control string movw R1, 4(FP) // Put the control string pointer in R1 loop: movb R2, (R1) // Get the next char from control string jeq done // If it was a 0, this is the end of the string cmp R2, '%' // See if it is the '%' character jne cout // If not goto cout, and simply print it add R1,1 // Advance the string pointer movb R2,(R1) // Get the next char add R1,1 // Advance the string pointer again //switch (R2) L1: cmp R2,'s' // See if this is a "%s" conversion jne L2 // If not, goto L2 // case 's' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get address of string (from arguments) to print pushw R2 // Push it on the stack call print // Print the string add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more L2: cmp R2,'d' // See if this is a "%d" conversion jne loop // If not, ignore unknown conversion // case 'd' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get number (from arguments) to print pushw R2 // Push it on the stack call nprint // Go print the decimal number add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more cout: movb (ttydata),R2 // Put character in tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Advance to next char in control string jmp loop // Go back and print more done: ret // All done, return to caller .end //////////////////// // nprint(d) Print the number d in decimal // .proc nprint movw R1, 4(FP) // Move argument value to R1 jeq zprint // If it was zero, goto zprint pushw R1 // Push value to print on stack call nprint_aux // Call aux function to print number add SP,2 // Restore stack pointer ret // All done, return to caller zprint: movb (ttydata), '0' // Put the ascii value of '0' in tty data register movb (ttystatus), #1 // Signal tty controller to print character ret // All done, return to caller .end //////////////////// // nprint_aux(d) Print the number d in decimal (but prints nothing if d is zero) // .proc nprint_aux digit: .symbol -2 // Digit to print sub SP, 2 // Allocate space for local variables movw R1, 4(FP) // Get argument jeq done // If zero, return // To print the number n we compute // R2 = n / 10, and // R3 = n % 10 // We can then recursively call nprint_aux to print all // but the lowest digit, then print the lowest digit ourselves // movw R2, R1 // R2 = R1 div R2, 10 // R2 = R2 / 10 movw R3, R1 // R3 = R1 mod R3, 10 // R3 = R3 % 10 movw digit(FP),R3 // save lowest digit value pushw R2 // Push the higher digits call nprint_aux // Recursively call ourselves to print them add SP,2 // Restore stack pointer movw R3,digit(FP) // Restore digit value add R3, '0' // Add ascii for '0' to get ascii for digit movb (ttydata),R3 // Put char in tty data register movb (ttystatus),#1 // Signal tty controller to print character done: ret // All done, resturn to caller .end //////////////////// // strcmp(a,b) Compare strings a and b // .proc strcmp movw R2,4(FP) // Get pointer to first string movw R3,6(FP) // Get pointer to second string loop: movb R1,(R2) // Get next char from R2 jeq eos // If end of string, goto eos movb R4,(R3) // Get next char from R3 jeq eos // If end of string, goto eos sub R1,R4 // Compute difference in R1 jne done // If difference was not 0, we are done add R2,1 // Advance to next char in R2 add R3,1 // Advance to next char in R3 jmp loop // Go compare more eos: movb R4,(R3) // Get next char from R3 again (in case R1 was eos) sub R1,R4 // Compute difference in R1 done: ret // Return to caller, result is in R1 .end //////////////////// // gets(b) Reads chars from tty into b. // .proc gets movw R1, 4(FP) // Get pointer to buffer movw R4,R1 // Save starting pointer in R4 // // Poll for a characcter // cwait: movb R2,(ttystatus) // Get ready status and R2, #2 // Test if a char is ready jeq cwait // If not, go back and wait some more movb R3,(ttydata) // Get char from tty data register movb (ttystatus),#2 // Signal char received cmp R3,'\r' // Compare against return char jeq done // Exit if return received cmp R3,'\b' // Compare against backspace char jeq del_char // Delete char if backspace cmp R3,0x7f // Compare against delete char jeq del_char // Delete char if delete character movb (ttydata),R3 // Put char to echo in tty data register movb (ttystatus),#1 // Signal tty controller to print character movb (R1),R3 // Save in buffer add R1,1 // increment pointer jmp cwait // Go back and get another char del_char: cmp R1,R4 // Compare current pointer against start of line jle bell // If already at start of line, ring bell movb R3, 0x7f // Make sure delete char is in R3 sub R1,1 // Decrement pointer movb (ttydata),R3 // Echo backspace movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char bell: movb R3, 7 // Put bell char in R3 movb (ttydata),R3 // Echo bell movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char done: movb (ttydata),'\n' // Output newline movb (ttystatus),#1 // Signal tty controller to print character movb (R1),0 // Put eos in the string we just read ret // Return to caller .end buf: .bss 128 // Buffer for input known: .bss 2 // Number of animals known root: .bss 2 // root of animals tree top_node: .short 0 // Pointer to "yes" node .short 0 // Pointer to "no" node .byte "aardvark",0 // Animal name or question text welcome: .byte "\nWelcome to Animals.\n", 0 think: .byte "\nThink of an animal and I will try to guess what it is.\n", 0 numk: .byte "I currently know %d animals.\n\n", 0 isita: .byte "Is the animal you are thinking of a %s? ",0 yes: .byte "yes",0 no: .byte "no",0 yesno: .byte "Please type 'yes' or 'no'.\n",0 winmsg: .byte "I guessed your animal!!!\n\n",0 loosemsg: .byte "I could not guess your animal. What was your animal? ",0 dscrim: .byte "Enter a question that would distinguish a %s from a %s.\n> ",0 which: .byte "The correct answer for a %s is? ",0 nl: .byte "\n",0 qprompt: .byte "? ",0 mend: end tkgate-2.0-b10/locale/de/examples/ex5/menagerie.v000644 001751 001751 00000275616 11142374103 022314 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "menagerie.v" //: property simAutoStart = 1 //: property discardChanges = 1 //: script "menagerie.vs" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /symbolBegin: 688806032 //: /iconBegin normal 3404 0 0 //: /data "#define bitmap_width 73" //: /data "#define bitmap_height 53" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xe8, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48," //: /data " 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48, 0x80, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x3f, 0x88, 0x48, 0x80, 0x01, 0x00, 0x50," //: /data " 0x00, 0x00, 0x00, 0x50, 0x88, 0x48, 0x80, 0x01, 0x00, 0x28, 0x00, 0x00," //: /data " 0x00, 0x88, 0x88, 0x38, 0x80, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xc4," //: /data " 0x08, 0x00, 0x80, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xa2, 0x08, 0x00," //: /data " 0x80, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x91, 0xe8, 0x38, 0x80, 0x00," //: /data " 0x80, 0x02, 0x00, 0x00, 0x80, 0x88, 0x28, 0x49, 0x80, 0x01, 0x40, 0x01," //: /data " 0x00, 0x00, 0x40, 0x84, 0x28, 0x49, 0x80, 0x01, 0xa0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0x82, 0xe8, 0x48, 0x80, 0x01, 0x60, 0x00, 0x00, 0x00, 0x40, 0x81," //: /data " 0x28, 0x49, 0x80, 0x01, 0x20, 0xff, 0xff, 0xff, 0x8f, 0x80, 0x28, 0x39," //: /data " 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x7c," //: /data " 0xef, 0x03, 0xa0, 0x80, 0xe8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x2f, 0x11, 0x81, 0x00, 0xa0, 0xdc, 0x0f, 0x00, 0xa0, 0x80," //: /data " 0x28, 0x11, 0x87, 0x01, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0xef, 0x10," //: /data " 0x88, 0x01, 0xa0, 0x7c, 0xbf, 0x01, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11, 0x86, 0x00, 0xa0, 0x04," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x0f, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0xc8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11," //: /data " 0x81, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x28, 0x10, 0x8f, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x10, 0x88, 0x01, 0xa0, 0x00," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0xc8, 0x10, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0x08, 0x00, 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00," //: /data " 0x80, 0x00, 0x20, 0xfe, 0xff, 0xff, 0x8f, 0x80, 0xe8, 0x30, 0x87, 0x00," //: /data " 0x60, 0x00, 0x00, 0x00, 0xc0, 0x80, 0x28, 0x09, 0x89, 0x00, 0xa0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0x80, 0x28, 0x79, 0x89, 0x01, 0x10, 0x00, 0x00, 0x00," //: /data " 0x40, 0x80, 0x28, 0x41, 0x87, 0x01, 0xd0, 0xff, 0xff, 0xff, 0x4f, 0x80," //: /data " 0x28, 0x49, 0x89, 0x01, 0xc8, 0xaa, 0xaa, 0xaa, 0x2a, 0x40, 0xe8, 0x30," //: /data " 0x89, 0x00, 0xa8, 0xff, 0xff, 0xff, 0x27, 0x20, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa4, 0xaa, 0xaa, 0xaa, 0x16, 0x10, 0x08, 0x00, 0x80, 0x00, 0xf4, 0xff," //: /data " 0xff, 0xff, 0x13, 0x08, 0xe8, 0x7c, 0x87, 0x00, 0x92, 0xaa, 0xaa, 0xaa," //: /data " 0x0a, 0x04, 0x28, 0x11, 0x89, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x0b, 0x02," //: /data " 0x28, 0x11, 0x89, 0x01, 0x01, 0x00, 0x00, 0x00, 0x04, 0x01, 0x28, 0x11," //: /data " 0x87, 0x01, 0xff, 0xff, 0xff, 0xff, 0x87, 0x00, 0x28, 0x11, 0x89, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x44, 0x00, 0xe8, 0x10, 0x89, 0x00, 0x01, 0x00," //: /data " 0x00, 0x00, 0x24, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00," //: /data " 0x14, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /iconBegin select 3389 0 0 //: /data "#define x_width 73" //: /data "#define x_height 53" //: /data "static unsigned char x_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xf8, 0x7b, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0xd9," //: /data " 0xc0, 0x01, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 0x98, 0xd9, 0xc0, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x70," //: /data " 0x00, 0x00, 0x00, 0xf8, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x38, 0x00, 0x00," //: /data " 0x00, 0xcc, 0x98, 0x79, 0xc0, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0xe6," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0xf3, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x00, 0x07, 0x00, 0x00, 0x80, 0xd9, 0xf8, 0x79, 0xc0, 0x00," //: /data " 0x80, 0x03, 0x00, 0x00, 0xc0, 0xcc, 0x78, 0xdb, 0xc0, 0x01, 0xc0, 0xff," //: /data " 0xff, 0xff, 0x7f, 0xc6, 0x78, 0xdb, 0xc0, 0x01, 0xe0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0xc3, 0xf8, 0xd9, 0xc0, 0x01, 0x60, 0x00, 0x00, 0x00, 0xc0, 0xc1," //: /data " 0x78, 0xdb, 0xc0, 0x01, 0x60, 0xff, 0xff, 0xff, 0x8f, 0xc1, 0x78, 0x7b," //: /data " 0xc0, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x9f, 0xc1, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x7c," //: /data " 0xef, 0x03, 0xb0, 0xc1, 0xf8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x7f, 0x33, 0xc3, 0x00, 0xe0, 0xdc, 0x0f, 0x00, 0xb0, 0xc1," //: /data " 0x78, 0x33, 0xcf, 0x01, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0xff, 0x30," //: /data " 0xd8, 0x01, 0xe0, 0x7c, 0xbf, 0x01, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33, 0xce, 0x00, 0xe0, 0x04," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x1f, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0xd8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33," //: /data " 0xc3, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x30, 0xdf, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x30, 0xd8, 0x01, 0xe0, 0x00," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0xd8, 0x31, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x60, 0x01, 0x00, 0x00, 0x98, 0xc1, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x60, 0xfe, 0xff, 0xff, 0x8f, 0xc1, 0xf8, 0x70, 0xc7, 0x00," //: /data " 0xe0, 0xff, 0xff, 0xff, 0xff, 0xc1, 0x78, 0x1b, 0xdb, 0x00, 0xe0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0xc1, 0x78, 0xfb, 0xdb, 0x01, 0x30, 0x00, 0x00, 0x00," //: /data " 0xe0, 0xc0, 0x78, 0xc3, 0xcf, 0x01, 0xf0, 0xff, 0xff, 0xff, 0x6f, 0xc0," //: /data " 0x78, 0xdb, 0xdb, 0x01, 0xd8, 0xaa, 0xaa, 0xaa, 0x3a, 0x60, 0xf8, 0x70," //: /data " 0xdb, 0x00, 0xb8, 0xff, 0xff, 0xff, 0x37, 0x30, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xac, 0xaa, 0xaa, 0xaa, 0x1e, 0x18, 0x18, 0x00, 0xc0, 0x00, 0xfc, 0xff," //: /data " 0xff, 0xff, 0x1b, 0x0c, 0xf8, 0x7c, 0xc7, 0x00, 0x96, 0xaa, 0xaa, 0xaa," //: /data " 0x0e, 0x06, 0x78, 0x33, 0xdb, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x0f, 0x03," //: /data " 0x78, 0x33, 0xdb, 0x01, 0x03, 0x00, 0x00, 0x00, 0x86, 0x01, 0x78, 0x33," //: /data " 0xc7, 0x01, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x00, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0x67, 0x00, 0xf8, 0x30, 0xdb, 0x00, 0x03, 0x00," //: /data " 0x00, 0x00, 0x36, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x03, 0x00, 0x00, 0x00," //: /data " 0x1e, 0x00, 0xf8, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /port output TD[7:0] @(73, 5) /r:0 //: /port input DSR @(73, 38) /r:0 //: /port output RTS @(73, 22) /r:0 //: /port input RD[7:0] @(73, 13) /r:0 //: /port input CTS @(73, 30) /r:0 //: /port output DTR @(73, 46) /r:0 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg _reset; //: {0}(50:749,83)(749,31)(543,31){1} //: {2}(539,31)(353,31){3} //: {4}(349,31)(154,31){5} //: {6}(351,33)(351,83){7} //: {8}(541,33)(541,83){9} wire w32; //: /sn:0 {0}(589,342)(659,342){1} wire [3:0] w45; //: /sn:0 {0}(#:589,102)(659,102){1} wire [3:0] w46; //: /sn:0 {0}(#:589,117)(659,117){1} wire w56; //: /sn:0 {0}(589,284)(659,284){1} wire w38; //: /sn:0 {0}(455,157)(394,157){1} wire [7:0] w51; //: /sn:0 {0}(#:589,197)(659,197){1} wire w0; //: /sn:0 {0}(455,270)(394,270){1} wire w37; //: /sn:0 {0}(455,172)(394,172){1} wire w34; //: /sn:0 {0}(589,380)(659,380){1} wire w43; //: /sn:0 {0}(455,220)(394,220){1} wire w54; //: /sn:0 {0}(589,249)(659,249){1} wire w58; //: /sn:0 {0}(589,323)(659,323){1} wire [15:0] DATA; //: {0}(#:50:727,438)(727,473)(519,473){1} //: {2}(517,471)(517,438){3} //: {4}(515,473)(328,473)(328,438){5} wire w41; //: /sn:0 {0}(455,109)(394,109){1} wire w36; //: /sn:0 {0}(455,188)(394,188){1} wire w40; //: /sn:0 {0}(455,126)(394,126){1} wire w35; //: /sn:0 {0}(589,398)(659,398){1} wire w59; //: /sn:0 {0}(455,255)(394,255){1} wire w53; //: /sn:0 {0}(589,235)(659,235){1} wire clk; //: {0}(50:694,83)(694,66)(494,66){1} //: {2}(490,66)(303,66){3} //: {4}(299,66)(146,66){5} //: {6}(301,68)(301,83){7} //: {8}(492,68)(492,83){9} wire w57; //: /sn:0 {0}(589,304)(659,304){1} wire [1:0] w49; //: /sn:0 {0}(#:589,165)(659,165){1} wire w44; //: /sn:0 {0}(455,204)(394,204){1} wire w52; //: /sn:0 {0}(589,217)(659,217){1} wire [1:0] w48; //: /sn:0 {0}(#:589,149)(659,149){1} wire w33; //: /sn:0 {0}(589,360)(659,360){1} wire w47; //: /sn:0 {0}(589,134)(659,134){1} wire [4:0] w50; //: /sn:0 {0}(#:589,179)(659,179){1} wire w42; //: /sn:0 {0}(455,239)(394,239){1} wire w55; //: /sn:0 {0}(589,266)(659,266){1} wire w39; //: /sn:0 {0}(455,141)(394,141){1} //: enddecls //: joint g4 (DATA) @(517, 473) /w:[ 1 2 4 -1 ] //: joint g3 (_reset) @(541, 31) /w:[ 1 -1 2 8 ] //: comment g13 @(17,390) /sn:0 //: /line:"Highlights der Schaltung:" //: /line:"* TTY Baustein" //: /line:"* Microprogrammzähler" //: /line:"* ALU" //: /line:"* Hauptspeicher" //: /line:"* Programmzähler" //: /line:"" //: /end //: joint g2 (clk) @(492, 66) /w:[ 1 -1 2 8 ] //: comment g1 @(13,90) //: /line:"Die Schaltung implementiert einen einfachen" //: /line:"Mikroprozessor. Ein Simulationsskript startet" //: /line:"sofort das Spiel \"Animals\", wenn man in den" //: /line:"Simulationsmodus geht. Klicke auf die unter-" //: /line:"schiedlichen Logikblöcke und drücke die '>'-" //: /line:"Taste um die Innenschaltungen zu sehen." //: /line:"Zum Elternmodul kommt man durch Drücken " //: /line:"der '<' Taste zurück. Während des Simu-" //: /line:"lationsmodus kann man auf Leitungen klicken," //: /line:"um die aktuellen Werte zu sehen oder man" //: /line:"setzt sie mit einem Doppelklick." //: /line:"" //: /line:"Klicke auf die Links unten, um die Inhalte" //: /line:"der unterstützenden Dateien für diese " //: /line:"Schaltung zu sehen:" //: /line:"" //: /line:"* Mikrocode/Makrocode Definitionen" //: /line:"* Initialisierungsdatei für den Hauptspeicher" //: /line:"* Simulatorskript" //: /line:"* Symboltabelle" //: /line:"" //: /end IUNIT iunit (._CLR(_reset), .CK(clk), .IR(DATA), .COUT(w35), ._Z(w34), ._GT(w33), ._LT(w32), ._rdpc(w59), ._incmar(w0), ._rd(w44), .spc(w43), ._ldhmdr(w42), ._ldpc(w41), ._ldmar(w40), ._ldmdr(w39), ._incpc(w38), ._rdmdr(w37), ._wrt(w36), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), .SA(w45)); //: @(456, 84) /sz:(132, 353) /p:[ Ti0>9 Ti1>9 Bi0>3 Ri0>0 Ri1>0 Ri2>0 Ri3>0 Lo0<0 Lo1<0 Lo2<0 Lo3<0 Lo4<0 Lo5<0 Lo6<0 Lo7<0 Lo8<0 Lo9<0 Lo10<0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 ] //: joint g6 (_reset) @(351, 31) /w:[ 3 -1 4 6 ] //: comment g7 @(43,7) /sn:0 //: /line:"Dies ist der" //: /line:"Resetschalter." //: /end //: comment g9 @(43,50) //: /line:"Dies ist der" //: /line:"Systemtakt." //: /line:" " //: /end MEMORY memory (._CLR(_reset), .CK(clk), ._incmar(w0), ._rdpc(w59), ._ldhmdr(w42), .spc(w43), ._rd(w44), ._wrt(w36), ._rdmdr(w37), ._incpc(w38), ._ldmdr(w39), ._ldmar(w40), ._ldpc(w41), .DATA(DATA)); //: @(268, 84) /sz:(125, 353) /p:[ Ti0>7 Ti1>7 Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Ri5>1 Ri6>1 Ri7>1 Ri8>1 Ri9>1 Ri10>1 Bt0=5 ] //: comment g39 @(12,517) /sn:0 //: /line:"[ZURÃœCK]" //: /end EUNIT eunit (._CLR(_reset), .CK(clk), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .SA(w45), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), ._LT(w32), ._GT(w33), ._Z(w34), .COUT(w35), .DATA(DATA)); //: @(660, 84) /sz:(128, 353) /p:[ Ti0>0 Ti1>0 Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Li6>1 Li7>1 Li8>1 Li9>1 Li10>1 Li11>1 Li12>1 Li13>1 Lo0<1 Lo1<1 Lo2<1 Lo3<1 Bt0=0 ] //: joint g5 (clk) @(301, 66) /w:[ 3 -1 4 6 ] _GGCLOCK_P3000_0_50 g0 (.Z(clk)); //: @(133,66) /sn:0 /w:[ 5 ] /omega:3000 /phi:0 /duty:50 //: SWITCH reset (_reset) @(137,31) /sn:0 /w:[ 5 ] /st:1 endmodule //: /netlistEnd //: /netlistBegin ALUshift module ALUshift(A, B, OUT, FUNC); //: interface /sz:(170, 116) /bd:[ Ti0>A[15:0](34/170) Ti1>B[15:0](82/170) Ti2>FUNC[4:0](121/170) Bo0CK(33/125) Ti1>_CLR(83/125) Ri0>_ldpc(25/353) Ri1>_ldmar(42/353) Ri2>_ldmdr(57/353) Ri3>_incpc(73/353) Ri4>_rdmdr(88/353) Ri5>_wrt(104/353) Ri6>_rd(120/353) Ri7>spc(136/353) Ri8>_ldhmdr(155/353) Ri9>_rdpc(171/353) Ri10>_incmar(186/353) Bt0=DATA[15:0](60/125) ] input _rdpc; //: /sn:0 {0}(259,285)(270,285)(270,306){1} input _rd; //: /sn:0 {0}(671,557)(671,614){1} //: {2}(673,616)(708,616)(708,273)(740,273){3} //: {4}(669,616)(512,616){5} //: {6}(510,614)(510,579){7} //: {8}(508,616)(482,616){9} supply0 [5:0] w16; //: /sn:0 {0}(#:545,861)(545,840){1} reg [15:0] w38; //: /sn:0 {0}(#:210,713)(300,713){1} input CK; //: /sn:0 {0}(753,813)(742,813)(742,833)(618,833)(618,815){1} //: {2}(620,813)(631,813){3} //: {4}(616,813)(524,813)(524,438){5} //: {6}(526,436)(641,436)(641,334)(726,334){7} //: {8}(522,436)(130,436){9} //: {10}(128,434)(128,335){11} //: {12}(130,333)(321,333)(321,307)(326,307){13} //: {14}(128,331)(128,253)(151,253){15} //: {16}(126,436)(62,436){17} supply0 [7:0] w3; //: /sn:0 {0}(#:683,269)(683,251)(662,251){1} input _CLR; //: /sn:0 {0}(512,218)(512,201){1} //: {2}(514,199)(844,199)(844,327){3} //: {4}(842,329)(802,329){5} //: {6}(844,331)(844,770){7} //: {8}(842,772)(716,772)(716,808)(707,808){9} //: {10}(844,774)(844,808)(829,808){11} //: {12}(510,199)(409,199){13} //: {14}(405,199)(263,199)(263,248)(227,248){15} //: {16}(407,201)(407,302)(402,302){17} input _ldhmdr; //: /sn:0 {0}(673,103)(709,103){1} //: {2}(713,103)(871,103)(871,269){3} //: {4}(711,105)(711,137){5} input _wrt; //: /sn:0 {0}(691,706)(424,706){1} //: {2}(422,704)(422,510){3} //: {4}(424,508)(454,508){5} //: {6}(420,508)(399,508){7} //: {8}(422,708)(422,758)(692,758){9} input _ldmar; //: /sn:0 {0}(458,247)(458,314)(438,314){1} supply0 [15:0] w21; //: /sn:0 {0}(#:220,59)(220,42)(194,42)(194,69){1} input _ldpc; //: /sn:0 {0}(233,131)(217,131)(217,152)(148,152){1} //: {2}(144,152)(131,152){3} //: {4}(146,154)(146,204)(165,204){5} inout [15:0] DATA; //: /sn:0 {0}(#:278,311)(297,311)(297,213)(371,213){1} //: {2}(373,211)(373,167){3} //: {4}(375,165)(508,165){5} //: {6}(512,165)(547,165){7} //: {8}(551,165)(568,165){9} //: {10}(549,167)(549,246)(616,246){11} //: {12}(510,163)(510,134){13} //: {14}(371,165)(198,165)(198,188){15} //: {16}(373,215)(373,248){17} supply0 [7:0] w24; //: /sn:0 {0}(#:595,538)(595,523){1} supply1 w20; //: /sn:0 {0}(241,70)(241,83)(202,83){1} supply0 w23; //: /sn:0 {0}(829,818)(844,818)(844,836){1} supply0 [7:0] w1; //: /sn:0 {0}(#:800,724)(800,677)(825,677)(825,687){1} input _rdmdr; //: /sn:0 {0}(624,284)(624,251){1} reg [15:0] w40; //: /sn:0 {0}(#:212,765)(301,765){1} input _incpc; //: /sn:0 {0}(233,126)(133,126){1} input spc; //: /sn:0 {0}(251,380)(207,380){1} supply0 w17; //: /sn:0 {0}(496,579)(496,592){1} input _ldmdr; //: /sn:0 {0}(876,269)(876,80)(673,80){1} input _incmar; //: /sn:0 {0}(438,309)(448,309)(448,281)(327,281){1} //: {2}(325,279)(325,266){3} //: {4}(327,264)(340,264){5} //: {6}(325,262)(325,243){7} //: {8}(325,283)(325,293)(313,293)(313,326)(223,326)(223,411)(96,411)(96,383){9} wire [15:0] w6; //: /sn:0 {0}(#:162,69)(162,47)(70,47)(70,360)(83,360){1} wire [7:0] mdrin; //: /sn:0 {0}(#:520,552)(557,552){1} //: {2}(561,552)(663,552){3} //: {4}(559,550)(559,523){5} wire w46; //: /sn:0 {0}(402,312)(417,312){1} wire w14; //: /sn:0 {0}(254,129)(272,129)(272,258)(227,258){1} wire w15; //: /sn:0 {0}(691,711)(645,711){1} //: {2}(643,709)(643,672){3} //: {4}(641,711)(436,711){5} //: {6}(434,709)(434,512)(454,512){7} //: {8}(432,711)(365,711){9} wire [15:0] w19; //: /sn:0 {0}(#:188,217)(188,243){1} wire [15:0] w4; //: /sn:0 {0}(#:584,165)(614,165){1} wire [15:0] PC; //: /sn:0 {0}(#:188,264)(188,309){1} //: {2}(190,311)(262,311){3} //: {4}(188,313)(188,348){5} //: {6}(190,350)(264,350)(264,364){7} //: {8}(186,350)(112,350){9} wire w; //: /sn:0 {0}(802,339)(874,339)(874,290){1} wire DTR; //: /sn:0 {0}(433,982)(565,982)(565,840){1} wire w37; //: /sn:0 {0}(713,761)(722,761)(722,818)(707,818){1} wire [7:0] w34; //: /sn:0 {0}(#:555,834)(555,668)(571,668)(571,523){1} wire [15:0] w43; //: /sn:0 {0}(#:363,297)(363,277){1} wire RTS; //: /sn:0 {0}(433,958)(555,958)(555,840){1} wire w31; //: /sn:0 {0}(366,763)(446,763){1} //: {2}(450,763)(631,763){3} //: {4}(635,763)(692,763){5} //: {6}(633,761)(633,672){7} //: {8}(448,761)(448,515)(454,515){9} wire [15:0] w28; //: /sn:0 {0}(#:344,711)(321,711){1} wire DSR; //: /sn:0 {0}(433,974)(800,974)(800,858){1} wire [7:0] w36; //: /sn:0 {0}(#:790,753)(790,803){1} wire CTS; //: /sn:0 {0}(790,858)(790,966)(433,966){1} wire [7:0] w25; //: /sn:0 {0}(#:763,286)(763,324){1} wire [5:0] w35; //: /sn:0 {0}(#:780,858)(780,881)(760,881){1} wire [7:0] w8; //: /sn:0 {0}(#:620,170)(695,170){1} wire [15:0] w18; //: /sn:0 {0}(#:274,393)(274,550){1} //: {2}(276,552)(485,552){3} //: {4}(274,554)(274,706){5} //: {6}(276,708)(300,708){7} //: {8}(274,710)(274,760)(301,760){9} wire [15:0] w30; //: /sn:0 {0}(#:345,763)(322,763){1} wire w22; //: /sn:0 {0}(154,83)(144,83){1} wire [7:0] RD; //: /sn:0 {0}(#:433,949)(668,949)(668,824){1} wire [7:0] mdr; //: /sn:0 {0}(#:780,724)(780,676)(724,676){1} //: {2}(722,674)(722,552)(699,552){3} //: {4}(697,550)(697,379){5} //: {6}(699,377)(763,377)(763,345){7} //: {8}(697,375)(697,241)(662,241){9} //: {10}(695,552)(679,552){11} //: {12}(720,676)(668,676)(668,803){13} wire [15:0] w2; //: /sn:0 {0}(#:656,246)(632,246){1} wire w11; //: /sn:0 {0}(503,529)(503,512)(475,512){1} wire [1:0] w27; //: /sn:0 {0}(#:600,507)(638,507)(638,666){1} wire [7:0] w13; //: /sn:0 {0}(#:753,257)(753,222)(577,222)(577,494){1} wire [15:0] mar; //: /sn:0 {0}(#:363,318)(363,349){1} //: {2}(361,351)(284,351)(284,364){3} //: {4}(363,353)(363,400)(136,400)(136,370)(112,370){5} wire [7:0] w33; //: /sn:0 {0}(#:790,852)(790,824){1} wire [7:0] w5; //: /sn:0 {0}(#:620,160)(661,160)(661,150)(695,150){1} wire [7:0] TD; //: /sn:0 {0}(#:433,941)(583,941)(583,523){1} wire [15:0] w9; //: /sn:0 {0}(#:178,188)(178,114){1} //: {2}(178,110)(178,98){3} //: {4}(180,112)(353,112)(353,248){5} wire [7:0] w42; //: /sn:0 {0}(#:773,257)(773,160)(724,160){1} wire w26; //: /sn:0 {0}(712,709)(745,709)(745,740)(767,740){1} //: enddecls //: joint g4 (_rd) @(510, 616) /w:[ 5 6 8 -1 ] //: INOUT g8 (DATA) @(510,128) /sn:0 /R:3 /w:[ 13 ] //: joint g61 (w31) @(448, 763) /w:[ 2 8 1 -1 ] //: joint g58 (_CLR) @(844, 772) /w:[ -1 7 8 10 ] _GGREG8 #(10, 10, 20) g51 (.Q(RD), .D(mdr), .EN(w37), .CLR(_CLR), .CK(CK)); //: @(668,813) /sn:0 /w:[ 1 13 1 9 3 ] //: IN g37 (spc) @(205,380) /sn:0 /w:[ 1 ] //: IN g34 (_ldpc) @(129,152) /sn:0 /w:[ 3 ] //: IN g13 (_wrt) @(397,508) /sn:0 /w:[ 7 ] //: joint g86 (_wrt) @(422, 508) /w:[ 4 -1 6 3 ] //: joint g55 (CK) @(524, 436) /w:[ 6 -1 8 5 ] //: joint g3 (_CLR) @(512, 199) /w:[ 2 -1 12 1 ] //: comment g89 @(37,543) /sn:0 //: /line:"Eine Adressleitung zum Hauptspeicher." //: /line:"Die Adresse kann im MAR (Memory Address" //: /line:"Register) oder im PC (Program Counter)" //: /line:"ausgewählt werden." //: /end //: IN g2 (_rd) @(480,616) /sn:0 /w:[ 9 ] //: joint g65 (mdr) @(722, 676) /w:[ 1 2 12 -1 ] //: joint g76 (w9) @(178, 112) /w:[ 2 1 4 -1 ] //: IN g77 (_ldmdr) @(671,80) /sn:0 /w:[ 1 ] _GGNAND2 #(6) g59 (.I0(!_wrt), .I1(w31), .Z(w37)); //: @(703,761) /sn:0 /w:[ 9 5 0 ] /eb:0 _GGBUFIF16 #(4, 6) g72 (.Z(DATA), .I(PC), .E(~_rdpc)); //: @(268,311) /sn:0 /w:[ 0 3 1 ] _GGREG16 #(10, 10, 20) PC (.Q(PC), .D(w19), .EN(w14), .CLR(_CLR), .CK(CK)); //: @(188,253) /w:[ 0 1 1 15 15 ] //: GROUND g1 (w17) @(496,598) /sn:0 /w:[ 1 ] //: joint g64 (_wrt) @(422, 706) /w:[ 1 2 -1 8 ] //: frame g16 @(110,659) /sn:0 /wi:762 /ht:347 /tx:"TTY Steuerung" _GGMUX4x8 #(12, 12) g11 (.I0(mdrin), .I1(w34), .I2(TD), .I3(w24), .S(w27), .Z(w13)); //: @(577,507) /sn:0 /R:2 /w:[ 5 1 1 1 0 1 ] /ss:0 /do:1 assign {w35, CTS, DSR} = w33; //: CONCAT g50 @(790,853) /sn:0 /R:1 /w:[ 0 0 1 0 ] /dr:0 /tp:0 /drp:0 _GGADD16 #(132, 134, 126, 128) g28 (.A(w6), .B(w21), .S(w9), .CI(w20), .CO(w22)); //: @(178,85) /sn:0 /w:[ 0 1 3 1 0 ] //: joint g78 (PC) @(188, 350) /w:[ 6 5 8 -1 ] //: comment g87 @(210,776) //: /line:"Diese DIP Schalter legen die" //: /line:"Adressen für den TTY Status" //: /line:"und die Datenregister fest." //: /end //: joint g10 (CK) @(128, 333) /w:[ 12 14 -1 11 ] //: joint g27 (DATA) @(373, 165) /w:[ 4 -1 14 3 ] //: joint g19 (mdr) @(697, 552) /w:[ 3 4 10 -1 ] _GGMUX2x16 #(8, 8) g32 (.I0(w9), .I1(DATA), .S(_incmar), .Z(w43)); //: @(363,264) /sn:0 /w:[ 5 17 5 1 ] /ss:0 /do:0 _GGRAM16x8 #(10, 60, 70, 10, 10, 10) m1 (.A(w18), .D(mdrin), .WE(w11), .OE(_rd), .CS(w17)); //: @(503,553) /w:[ 3 0 0 7 0 ] //: joint g38 (DATA) @(549, 165) /w:[ 8 -1 7 10 ] //: IN g69 (_ldhmdr) @(671,103) /sn:0 /w:[ 0 ] //: IN g6 (_rdmdr) @(624,286) /sn:0 /R:1 /w:[ 0 ] //: joint g57 (_CLR) @(844, 329) /w:[ -1 3 4 6 ] _GGREG8 #(10, 10, 20) g53 (.Q(w33), .D(w36), .EN(w23), .CLR(_CLR), .CK(CK)); //: @(790,813) /sn:0 /w:[ 1 1 0 11 0 ] _GGMUX2x8 #(8, 8) g9 (.I0(w13), .I1(w42), .S(_rd), .Z(w25)); //: @(763,273) /sn:0 /w:[ 0 0 3 0 ] /ss:0 /do:0 _GGBUFIF8 #(4, 6) g7 (.Z(mdrin), .I(mdr), .E(_rd)); //: @(673,552) /sn:0 /R:2 /w:[ 3 11 0 ] //: joint g75 (DATA) @(373, 213) /w:[ -1 2 1 16 ] //: GROUND g20 (w3) @(683,275) /sn:0 /w:[ 0 ] assign {w8, w5} = w4; //: CONCAT g15 @(615,165) /sn:0 /R:2 /w:[ 0 0 1 ] /dr:0 /tp:0 /drp:0 //: joint g71 (_ldhmdr) @(711, 103) /w:[ 2 -1 1 4 ] _GGMUX2x16 #(8, 8) g31 (.I0(PC), .I1(mar), .S(~_incmar), .Z(w6)); //: @(96,360) /sn:0 /R:3 /w:[ 9 5 9 1 ] /ss:1 /do:0 _GGXOR2x16 #(8) g39 (.I0(w18), .I1(w38), .Z(w28)); //: @(311,711) /sn:0 /w:[ 7 1 1 ] /eb:0 //: GROUND g67 (w23) @(844,842) /sn:0 /w:[ 1 ] _GGMUX2x8 #(8, 8) g68 (.I0(w5), .I1(w8), .S(~_ldhmdr), .Z(w42)); //: @(711,160) /sn:0 /R:1 /w:[ 1 1 5 1 ] /ss:1 /do:1 //: GROUND g48 (w16) @(545,867) /sn:0 /w:[ 0 ] //: joint g43 (w18) @(274, 552) /w:[ 2 1 -1 4 ] //: IN g73 (_rdpc) @(257,285) /sn:0 /w:[ 0 ] _GGNAND2 #(6) g62 (.I0(!_wrt), .I1(w15), .Z(w26)); //: @(702,709) /sn:0 /w:[ 0 0 0 ] /eb:0 //: VDD g29 (w20) @(252,70) /sn:0 /w:[ 0 ] _GGMUX2x16 #(8, 8) g25 (.I0(PC), .I1(mar), .S(~spc), .Z(w18)); //: @(274,380) /sn:0 /w:[ 7 3 0 0 ] /ss:0 /do:0 //: joint g17 (DATA) @(510, 165) /w:[ 6 12 5 -1 ] //: IN g88 (_CLR) @(512,220) /sn:0 /R:1 /w:[ 0 ] //: joint g63 (w15) @(643, 711) /w:[ 1 2 4 -1 ] _GGNOR1x16 #(1) g42 (.I0(w30), .Z(w31)); //: @(356,763) /sn:0 /w:[ 0 0 ] /eb:0 //: joint g52 (mdr) @(697, 377) /w:[ 6 8 -1 5 ] _GGNOR2 #(6) g83 (.I0(!_incmar), .I1(!_ldmar), .Z(w46)); //: @(427,312) /sn:0 /R:2 /w:[ 0 1 1 ] /eb:0 //: joint g74 (PC) @(188, 311) /w:[ 2 1 -1 4 ] //: joint g56 (CK) @(618, 813) /w:[ 2 -1 4 1 ] //: frame g14 @(536,27) /sn:0 /wi:372 /ht:394 /tx:"MDR Steuerung" //: joint g5 (_CLR) @(407, 199) /w:[ 13 -1 14 16 ] assign w34 = {w16, RTS, DTR}; //: CONCAT g47 @(555,835) /sn:0 /R:1 /w:[ 0 1 1 1 ] /dr:0 /tp:0 /drp:1 //: joint g44 (w18) @(274, 708) /w:[ 6 5 -1 8 ] //: joint g79 (mar) @(363, 351) /w:[ -1 1 2 4 ] //: IN g80 (_incmar) @(325,241) /sn:0 /R:3 /w:[ 7 ] //: joint g36 (_ldpc) @(146, 152) /w:[ 1 -1 2 4 ] _GGBUFIF16 #(4, 6) g21 (.Z(DATA), .I(w2), .E(~_rdmdr)); //: @(626,246) /sn:0 /R:2 /w:[ 11 1 1 ] _GGREG8 #(10, 10, 20) mdr (.Q(mdr), .D(w25), .EN(w), .CLR(_CLR), .CK(CK)); //: @(763,334) /w:[ 7 1 0 5 7 ] _GGOR3 #(8) g84 (.I0(_wrt), .I1(w15), .I2(w31), .Z(w11)); //: @(465,512) /sn:0 /w:[ 5 7 9 1 ] /eb:0 //: joint g85 (w15) @(434, 711) /w:[ 5 6 8 -1 ] //: joint g24 (CK) @(128, 436) /w:[ 9 10 16 -1 ] //: DIP TTYSTATUS (w38) @(172,713) /R:1 /w:[ 0 ] /st:16 _GGNOR1x16 #(1) g41 (.I0(w28), .Z(w15)); //: @(355,711) /sn:0 /w:[ 0 9 ] /eb:0 //: IN g23 (_ldmar) @(458,245) /sn:0 /R:3 /w:[ 0 ] //: joint g60 (w31) @(633, 763) /w:[ 4 6 3 -1 ] _GGXOR2x16 #(8) g40 (.I0(w18), .I1(w40), .Z(w30)); //: @(312,763) /sn:0 /w:[ 9 1 1 ] /eb:0 _GGMUX2x8 #(8, 8) g54 (.I0(mdr), .I1(w1), .S(w26), .Z(w36)); //: @(790,740) /sn:0 /w:[ 0 0 1 0 ] /ss:0 /do:0 //: joint g81 (_incmar) @(325, 264) /w:[ 4 6 -1 3 ] //: frame g93 @(354,466) /sn:0 /wi:421 /ht:164 /tx:"Hauptspeicher" assign w27 = {w31, w15}; //: CONCAT g46 @(638,667) /sn:0 /R:1 /w:[ 1 7 3 ] /dr:0 /tp:0 /drp:1 //: joint g45 (mdrin) @(559, 552) /w:[ 2 4 1 -1 ] _GGNOR2 #(6) g35 (.I0(!_incpc), .I1(!_ldpc), .Z(w14)); //: @(244,129) /sn:0 /w:[ 0 0 0 ] /eb:0 _GGMUX2x16 #(8, 8) g26 (.I0(w9), .I1(DATA), .S(~_ldpc), .Z(w19)); //: @(188,204) /sn:0 /w:[ 0 15 5 0 ] /ss:0 /do:0 //: IN g0 (CK) @(60,436) /sn:0 /w:[ 17 ] _GGREG16 #(10, 10, 20) mar (.Q(mar), .D(w43), .EN(w46), .CLR(_CLR), .CK(CK)); //: @(363,307) /w:[ 0 0 0 17 13 ] _GGBUF16 #(4) g22 (.I(DATA), .Z(w4)); //: @(574,165) /sn:0 /w:[ 9 0 ] _GGNOR2 #(6) g70 (.I0(!_ldhmdr), .I1(!_ldmdr), .Z(w)); //: @(874,280) /sn:0 /R:3 /w:[ 3 0 1 ] /eb:0 //: comment g90 @(211,844) /sn:0 //: /line:"Dies ist das TTY-Gerät. Im Simulationsmodus" //: /line:"geht ein tty-Fenster auf, das diesem" //: /line:"Gerät entspricht. Auf das Gerät kann durch" //: /line:"die simulierte CPU zugegriffen werden, indem" //: /line:"an Adressen gelesen oder geschrieben wird, " //: /line:"die durch die DIP-Schalter TTYSTATUS und" //: /line:"TTYDATA eingestellt sind." //: /end //: DIP TTYDATA (w40) @(174,765) /R:1 /w:[ 0 ] /st:17 //: GROUND g66 (w1) @(825,693) /sn:0 /w:[ 1 ] //: joint g82 (_incmar) @(325, 281) /w:[ 1 2 -1 8 ] TTY tty0 (.TD(TD), .DSR(DSR), .RTS(RTS), .RD(RD), .CTS(CTS), .DTR(DTR)); //: @(396, 962) /symbol:688806032 /w:[ 0 0 0 0 1 0 ] //: joint g12 (_rd) @(671, 616) /w:[ 2 1 4 -1 ] assign w2 = {w3, mdr}; //: CONCAT g18 @(657,246) /sn:0 /R:2 /w:[ 0 1 9 ] /dr:0 /tp:0 /drp:1 //: IN g33 (_incpc) @(131,126) /sn:0 /w:[ 1 ] //: GROUND g30 (w21) @(220,65) /sn:0 /w:[ 0 ] //: frame g91 @(45,27) /sn:0 /wi:441 /ht:397 /tx:"Addressauflösung" //: GROUND g49 (w24) @(595,544) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin REG4 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>SA[1:0](17/138) Li1>SB[1:0](33/138) Li2>_CLR(51/138) Li3>_ENA(70/138) Li4>_ENB(88/138) Li5>_WA(106/138) Li6>CK(123/138) Bo0B[15:0](79/107) Ti1>A[15:0](31/107) Li0>CIN(95/127) Li1>FUNC[4:0](18/127) Bo07 Ti1>5 Ti2>5 Bo0<0 ] //: OUT g39 (_GT) @(554,503) /sn:0 /w:[ 1 ] _GGOR1x16 #(1) g43 (.I0(OUT), .Z(_Z)); //: @(468,431) /sn:0 /w:[ 3 0 ] /eb:0 //: joint g48 (_Z) @(490, 431) /w:[ 2 -1 1 4 ] //: OUT g42 (_Z) @(553,431) /sn:0 /w:[ 3 ] _GGOR1x3 #(1) g5 (.I0(w0), .Z(w2)); //: @(317,402) /sn:0 /w:[ 0 1 ] /eb:0 _GGNAND2 #(4) g47 (.I0(_LT), .I1(_Z), .Z(_GT)); //: @(522,503) /sn:0 /w:[ 5 5 0 ] /eb:0 //: OUT g41 (OUT) @(406,507) /sn:0 /R:3 /w:[ 7 ] ALUbasic g54 (.FUNC(FUNC), .B(B), .A(A), .CIN(CIN), .OUT(w1), .COUT(COUT)); //: @(468, 172) /sz:(165, 122) /sn:0 /p:[ Ti0>5 Ti1>3 Ti2>3 Li0>1 Bo0<1 Ro0<0 ] //: OUT g40 (_LT) @(554,467) /sn:0 /w:[ 0 ] _GGNBUF #(2) g45 (.I(w3), .Z(_LT)); //: @(465,467) /sn:0 /w:[ 1 3 ] assign w3 = OUT[15]; //: TAP g46 @(404,467) /sn:0 /R:2 /w:[ 0 6 5 ] /ss:1 //: joint g0 (A) @(223, 67) /w:[ 2 -1 1 4 ] //: joint g49 (_LT) @(502, 467) /w:[ 1 -1 2 4 ] endmodule //: /netlistEnd //: /netlistBegin IUNIT module IUNIT(CK, _LDQ, _WA, _rd, _DOUT, _rdmdr, _CLQ, FUNC, _CLR, _LDQH, SB, _ldmdr, IR, _ldmar, _incmar, _LDQL, SA, IDATA, _incpc, _LDDATA, COUT, _LT, _Z, spc, _ldpc, _wrt, _ldhmdr, _GT, AOP, BOP, _rdpc, CIN); //: interface /sz:(132, 353) /bd:[ Ti0>CK(37/132) Ti1>_CLR(86/132) Li0>_incmar(187/353) Bi0>IR[15:0](62/132) Ri0>_LT(258/353) Ri1>_GT(276/353) Ri2>_Z(296/353) Ri3>COUT(314/353) Lo0<_wrt(105/353) Lo1<_rdmdr(89/353) Lo2<_incpc(74/353) Lo3<_ldmdr(58/353) Lo4<_ldmar(43/353) Lo5<_ldpc(26/353) Lo6<_ldhmdr(156/353) Lo70 Ti1>0 Bo0<1 Ro0<1 Ro1<0 Ro2<1 Ro3<0 Ro4<1 Ro5<1 ] //: OUT g75 (_LDQH) @(701,1127) /sn:0 /w:[ 1 ] //: GROUND g9 (w5) @(368,751) /sn:0 /w:[ 0 ] //: OUT g57 (SB) @(766,890) /sn:0 /w:[ 0 ] //: OUT g53 (_ldmdr) @(701,1017) /sn:0 /w:[ 0 ] //: joint g7 (CK) @(102, 120) /w:[ 16 18 -1 15 ] _GGMUX2x4 #(8, 8) g71 (.I0(w45), .I1(w46), .S(w47), .Z(SB)); //: @(725,890) /sn:0 /R:1 /w:[ 0 0 0 1 ] /ss:1 /do:1 //: GROUND g15 (w15) @(205,723) /sn:0 /w:[ 1 ] _GGMUX2x8 #(8, 8) g20 (.I0(IDATA), .I1(w27), .S(w35), .Z(w12)); //: @(393,390) /sn:0 /R:3 /w:[ 0 0 1 0 ] /ss:1 /do:0 //: IN g31 (IR) @(57,70) /sn:0 /w:[ 0 ] _GGMUX2x4 #(8, 8) g68 (.I0(w41), .I1(w39), .S(w43), .Z(SA)); //: @(725,818) /sn:0 /R:1 /w:[ 0 1 0 0 ] /ss:1 /do:1 //: VDD g39 (w19) @(421,649) /sn:0 /w:[ 1 ] //: joint g67 (w6) @(151, 65) /w:[ 2 -1 1 4 ] //: GROUND g43 (w20) @(455,1042) /sn:0 /w:[ 1 ] //: joint g48 (IDATA) @(540, 654) /w:[ 2 1 4 -1 ] //: frame g88 @(176,317) /sn:0 /wi:311 /ht:239 /tx:"Mikrocode Erzeugung der nächsten Adresse" //: joint g29 (ww) @(945, 358) /w:[ 2 4 1 -1 ] _GGMUX2x5 #(8, 8) g73 (.I0(w7), .I1(w49), .S(w42), .Z(FUNC)); //: @(725,956) /sn:0 /R:1 /w:[ 1 1 0 1 ] /ss:1 /do:1 _GGNOR2 #(6) g25 (.I0(!w55), .I1(!w32), .Z(_SA0)); //: @(890,384) /sn:0 /R:2 /w:[ 13 0 0 ] /eb:0 //: GROUND g17 (w23) @(360,367) /sn:0 /w:[ 0 ] //: comment g62 @(370,940) //: /line:"Dies ist die obere Hälfte" //: /line:"des Mikrobefehlspeichers." //: /end //: joint g63 (CK) @(264, 771) /w:[ 2 4 -1 1 ] //: GROUND g42 (w30) @(455,678) /sn:0 /w:[ 1 ] //: OUT g52 (_ldmar) @(701,1007) /sn:0 /w:[ 1 ] //: OUT g83 (_incmar) @(701,1177) /sn:0 /w:[ 0 ] //: OUT g74 (_LDQL) @(701,1117) /sn:0 /w:[ 1 ] //: OUT g56 (SA) @(766,818) /sn:0 /w:[ 1 ] //: joint g5 (mp_nxtaddr) @(331, 709) /w:[ 4 6 -1 3 ] //: VDD g14 (w21) @(186,641) /sn:0 /w:[ 0 ] //: joint g80 (CK) @(102, 276) /w:[ 12 14 -1 11 ] assign {w4, w55, ww, w32} = w3; //: CONCAT g79 @(1030,353) /sn:0 /w:[ 1 0 3 3 1 ] /dr:0 /tp:0 /drp:0 //: OUT g47 (IDATA) @(690,654) /sn:0 /w:[ 3 ] //: OUT g44 (_incpc) @(701,997) /sn:0 /w:[ 1 ] //: comment g85 @(16,131) /sn:0 //: /line:"Dieser Block" //: /line:"decodiert" //: /line:"Befehle," //: /line:"erstellt" //: /line:"einen Index," //: /line:"Register" //: /line:"Zahlen," //: /line:"Funktions-" //: /line:"code und" //: /line:"Condition" //: /line:"Code." //: /end //: OUT g36 (_LDDATA) @(690,734) /sn:0 /w:[ 0 ] //: IN g21 (COUT) @(1163,375) /sn:0 /R:2 /w:[ 1 ] //: IN g24 (_LT) @(1168,345) /sn:0 /R:2 /w:[ 0 ] //: comment g84 @(694,22) //: /line:"Hier ist ein einfaches Beispiel einer" //: /line:"Befehlseinheit. Das mpc Register" //: /line:"enthält den Mikrobefehlszähler" //: /line:"und die beiden Register ans den" //: /line:"Datenausgängen der ROM m1 und m2" //: /line:"sind die aktuellen Mikrobefehle" //: /line:"Da dies zwei getrennte Register" //: /line:"sind, gibt es eine Sprungverzögerung" //: /line:"von einem Taktzyklus." //: /end //: IN g23 (_Z) @(1164,361) /sn:0 /R:2 /w:[ 0 ] //: OUT g41 (spc) @(701,1067) /sn:0 /w:[ 1 ] //: VDD g40 (w24) @(421,1016) /sn:0 /w:[ 1 ] //: OUT g54 (_ldpc) @(701,1027) /sn:0 /w:[ 1 ] //: OUT g60 (_wrt) @(701,1057) /sn:0 /w:[ 1 ] //: OUT g81 (_ldhmdr) @(701,1157) /sn:0 /w:[ 0 ] //: joint g22 (w55) @(879, 300) /w:[ 3 4 6 -1 ] assign {w46, w39, _WA, _ldopr, _LDDATA, _LDQ, _CLQ, CIN, BOP, AOP, _ldir, w18, IDATA, w14} = mp_wrd0; //: CONCAT g0 @(483,709) /sn:0 /R:2 /w:[ 1 0 1 0 1 1 1 1 0 0 0 0 5 0 1 ] /dr:0 /tp:0 /drp:0 //: IN g26 (_GT) @(1165,323) /sn:0 /R:2 /w:[ 0 ] _GGREG32 #(10, 10, 20) g35 (.Q(w8), .D(w10), .EN(w20), .CLR(w24), .CK(CK)); //: @(436,1087) /sn:0 /R:1 /w:[ 1 0 0 0 0 ] //: OUT g45 (AOP) @(690,684) /sn:0 /w:[ 1 ] //: OUT g46 (BOP) @(690,694) /sn:0 /w:[ 1 ] //: joint g70 (_CLR) @(385, 74) /w:[ 7 -1 8 10 ] //: OUT g82 (_rdpc) @(701,1167) /sn:0 /w:[ 1 ] assign {w25, w6} = IR; //: CONCAT g66 @(85,70) /sn:0 /R:2 /w:[ 1 0 1 ] /dr:0 /tp:0 /drp:0 _GGADD8 #(68, 70, 62, 64) g12 (.A(mp_nxtaddr), .B(w15), .S(w27), .CI(w21), .CO(w22)); //: @(221,657) /sn:0 /R:2 /w:[ 9 0 5 1 0 ] _GGMUX8 #(20, 22) g18 (.I0(~w55), .I1(~w4), .I2(w55), .I3(ww), .I4(w32), .I5(_SA), .I6(_SA0), .I7(w28), .S(w44), .Z(w35)); //: @(797,311) /sn:0 /R:3 /w:[ 5 0 7 5 5 1 1 1 0 0 ] /ss:1 /do:0 //: joint g30 (CK) @(102, 511) /w:[ 9 10 20 -1 ] //: joint g33 (w55) @(911, 353) /w:[ -1 9 10 12 ] //: OUT g49 (CIN) @(690,704) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin ZREG4 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>SA[1:0](17/138) Li1>SB[1:0](33/138) Li2>_CLR(51/138) Li3>_ENA(70/138) Li4>_ENB(88/138) Li5>_WA(106/138) Li6>CK(123/138) Bo0IR[7:0](19/192) Ti1>OPR[7:0](148/192) Bo0DIN[15:0](53/108) Li0>_WA(101/138) Li1>_ENB(82/138) Li2>_ENA(66/138) Li3>_CLR(51/138) Li4>SB[3:0](33/138) Li5>SA[3:0](17/138) Li6>CK(118/138) Bo013 Li0>13 Li1>13 Li2>1 Li3>1 Li4>13 Li5>13 Li6>13 Bo0<13 Bo1<13 ] //: joint g38 (B) @(880, 435) /w:[ 5 6 8 -1 ] //: joint g6 (w50) @(690, 520) /w:[ 6 8 5 -1 ] //: joint g7 (w49) @(142, 623) /w:[ 2 12 1 -1 ] //: IN g9 (SA) @(31,525) /sn:0 /w:[ 1 ] //: joint g31 (DIN) @(853, 156) /w:[ 6 -1 5 8 ] //: joint g15 (_CLR) @(465, 359) /w:[ 4 10 3 -1 ] //: joint g39 (B) @(1133, 435) /w:[ 1 2 4 -1 ] //: joint g29 (DIN) @(360, 156) /w:[ 2 -1 1 12 ] //: joint g25 (_WA) @(769, 379) /w:[ 6 8 5 -1 ] _GGNDECODER4 #(4, 4) g17 (.I(w37), .E(~_ENA), .Z0(w16), .Z1(w9), .Z2(w26), .Z3(w47)); //: @(222,485) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] /ss:1 /do:1 //: joint g14 (_CLR) @(163, 359) /w:[ 2 12 1 -1 ] assign {w15, w49} = SB; //: CONCAT g5 @(79,628) /sn:0 /R:2 /w:[ 1 0 0 ] /dr:0 /tp:0 /drp:0 REG4 RF3 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w47), ._ENB(w46), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(1053, 197) /sz:(109, 138) /p:[ Ti0>7 Li0>7 Li1>7 Li2>7 Li3>1 Li4>1 Li5>7 Li6>7 Bo0<3 Bo1<3 ] //: joint g36 (A) @(1085, 467) /w:[ 1 2 4 -1 ] //: joint g24 (_WA) @(500, 379) /w:[ 4 10 3 -1 ] //: OUT g41 (A) @(1207,467) /sn:0 /w:[ 0 ] //: joint g23 (_WA) @(279, 379) /w:[ 2 12 1 -1 ] //: OUT g40 (B) @(1205,435) /sn:0 /w:[ 0 ] REG4 RF1 (.DIN(DIN), .CK(CK), ._WA(_WA), ._ENB(w10), ._ENA(w9), ._CLR(_CLR), .SB(w49), .SA(w50), .B(B), .A(A)); //: @(567, 198) /sz:(106, 138) /p:[ Ti0>11 Li0>11 Li1>11 Li2>1 Li3>1 Li4>11 Li5>11 Li6>11 Bo0<11 Bo1<11 ] //: joint g35 (A) @(832, 467) /w:[ 5 6 8 -1 ] //: joint g26 (CK) @(294, 403) /w:[ 2 12 1 -1 ] //: IN g22 (CK) @(40,403) /sn:0 /w:[ 0 ] //: IN g18 (_WA) @(40,379) /sn:0 /w:[ 0 ] //: IN g12 (_CLR) @(41,359) /sn:0 /w:[ 0 ] //: IN g33 (_ENB) @(33,555) /sn:0 /w:[ 1 ] //: joint g30 (DIN) @(619, 156) /w:[ 4 -1 3 10 ] REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(801, 198) /sz:(107, 138) /p:[ Ti0>9 Li0>9 Li1>9 Li2>9 Li3>1 Li4>1 Li5>9 Li6>9 Bo0<7 Bo1<7 ] endmodule //: /netlistEnd //: /netlistBegin ALUbasic module ALUbasic(B, A, OUT, COUT, CIN, FUNC); //: interface /sz:(165, 122) /bd:[ Ti0>A[15:0](38/165) Ti1>B[15:0](84/165) Ti2>FUNC[4:0](125/165) Li0>CIN(54/122) Bo0CK(34/128) Ti1>_CLR(89/128) Li0>SB[3:0](33/353) Li1>_WA(50/353) Li2>AOP[1:0](65/353) Li3>BOP[1:0](81/353) Li4>FUNC[4:0](95/353) Li5>IDATA[7:0](113/353) Li6>_CLQ(133/353) Li7>_LDQ(150/353) Li8>CIN(165/353) Li9>SA[3:0](18/353) Li10>_LDDATA(182/353) Li11>_LDQH(200/353) Li12>_LDQL(220/353) Li13>_DOUT(239/353) Lo01 Li0>0 Li1>1 Li2>1 Li3>3 Li4>0 Li5>3 Li6>0 Bo0<1 Bo1<1 ] assign w12 = w1[15:8]; //: TAP g39 @(678,679) /sn:0 /R:3 /w:[ 0 7 8 ] /ss:0 ALU alu (.B(w31), .A(w38), .CIN(CIN), .FUNC(FUNC), .OUT(w1), .COUT(COUT), ._LT(_LT), ._GT(_GT), ._Z(_Z)); //: @(500, 523) /sz:(107, 127) /sn:0 /p:[ Ti0>1 Ti1>1 Li0>1 Li1>1 Bo0<9 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] _GGNOR2 #(6) g43 (.I0(!_LDQL), .I1(!_LDQ), .Z(w9)); //: @(706,783) /sn:0 /R:3 /w:[ 0 7 1 ] /eb:0 _GGREG8 #(10, 10, 20) QL (.Q(QL), .D(w8), .EN(w9), .CLR(w10), .CK(CK)); //: @(620,829) /w:[ 1 0 0 0 7 ] //: joint g48 (w1) @(844, 676) /w:[ 1 2 4 -1 ] _GGREG8 #(10, 10, 20) QH (.Q(QH), .D(w2), .EN(w7), .CLR(w10), .CK(CK)); //: @(761,855) /w:[ 1 1 1 3 9 ] _GGBUFIF16 #(4, 6) g17 (.Z(DATA), .I(w1), .E(~_DOUT)); //: @(906,676) /sn:0 /cpc:1 /w:[ 13 0 0 ] //: IN g25 (FUNC) @(475,541) /sn:0 /w:[ 0 ] //: OUT g29 (_LT) @(642,575) /sn:0 /w:[ 0 ] //: joint g42 (CK) @(537, 829) /w:[ 6 -1 5 8 ] //: joint g5 (w0) @(463, 316) /w:[ 2 1 -1 4 ] //: GROUND g14 (w30) @(299,394) /sn:0 /w:[ 0 ] //: joint g44 (_LDQ) @(708, 739) /w:[ 2 -1 1 4 ] //: joint g47 (DATA) @(959, 676) /w:[ 1 2 12 -1 ] //: joint g36 (w8) @(771, 710) /w:[ -1 2 1 4 ] //: IN g24 (_LDQH) @(808,771) /sn:0 /w:[ 1 ] //: joint g21 (w35) @(486, 418) /w:[ 2 -1 4 1 ] //: joint g41 (CK) @(195, 409) /w:[ -1 1 2 4 ] //: IN g23 (_LDQL) @(677,764) /sn:0 /w:[ 1 ] //: joint g40 (w10) @(669, 809) /w:[ 2 -1 4 1 ] //: joint g22 (DATA) @(608, 437) /w:[ 7 -1 8 10 ] //: joint g0 (DATA) @(864, 437) /w:[ 3 4 6 -1 ] //: joint g46 (_LDQ) @(708, 757) /w:[ 6 5 8 -1 ] _GGNOR2 #(6) g45 (.I0(!_LDQH), .I1(!_LDQ), .Z(w7)); //: @(840,809) /sn:0 /R:3 /w:[ 0 9 0 ] /eb:0 _GGMUX2x8 #(8, 8) g35 (.I0(w12), .I1(w8), .S(_LDQ), .Z(w2)); //: @(761,739) /sn:0 /w:[ 1 5 3 0 ] /ss:0 /do:0 //: IN g26 (CIN) @(473,618) /sn:0 /w:[ 0 ] //: IN g12 (IDATA) @(296,423) /sn:0 /w:[ 1 ] _GGMUX4x16 #(12, 12) g18 (.I0(w21), .I1(DATA), .I2(w35), .I3(w28), .S(BOP), .Z(w31)); //: @(614,481) /sn:0 /w:[ 3 11 3 0 1 0 ] /ss:0 /do:0 //: OUT g30 (COUT) @(642,592) /sn:0 /w:[ 0 ] //: IN g49 (_DOUT) @(908,642) /sn:0 /R:3 /w:[ 1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; reg Z; assign #Diz Z = ~( I0 & I1 & I2 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2x2 #(.Diz(1)) (I0, I1, Z); output [1:0] Z; input [1:0] I0, I1; reg [1:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX2x5 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [4:0] I0, I1; input S; output [4:0] Z; reg [4:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 5'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX2x4 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [3:0] I0, I1; input S; output [3:0] Z; reg [3:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 4'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGNOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ~( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGXOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGARSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >>> S); endmodule // arshift //: /builtinEnd //: /builtinBegin module _GGMUX2x3 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [2:0] I0, I1; input S; output [2:0] Z; reg [2:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 3'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; reg [15:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGREG4 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [3:0] D; output [3:0] Q; reg [3:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 4'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x3 #(.Diz(1)) (I0, I1, Z); output [2:0] Z; input [2:0] I0, I1; reg [2:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF3 #(.Diz(1)) (I, Z); input [2:0] I; output [2:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGROM8x32 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [31:0] D; reg [31:0] m[0:255]; wire [31:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 32'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGNOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = ~ | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGLSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I << S); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGROM8x8 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [7:0] D; reg [7:0] m[0:255]; wire [7:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 8'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output Z; reg Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 1'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGOR3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; assign #Diz Z = ( I0 | I1 | I2 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGAND1x4 #(.Diz(1)) (I0, Z); output Z; input [3:0] I0; assign #Diz Z = & I0; endmodule // rand //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR1x3 #(.Diz(1)) (I0, Z); output Z; input [2:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGBUFIF16 #(.Dez(1), .Diz(1)) (Z, I, E); input [15:0] I; input E; output [15:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 16'bz; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGREG32 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [31:0] D; output [31:0] Q; reg [31:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 32'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD16 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [15:0] A,B; output [15:0] S; wire [15:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGRAM16x8 #(.Dout(1), // Output time .Dread(1), // Read time .Dwrite(1), // Write time .Daddr_setup(1), // Address setup time .Daddr_hold(1), // Address hold time .Ddata_hold(1)) // Data hold time (A, D, WE, OE, CS); input OE, WE, CS; input [15:0] A; inout [7:0] D; reg [7:0] m[0:65535]; wire [7:0] X; wire doRead, doWrite; specify $setup(A, posedge doWrite, Daddr_setup); $hold(negedge doWrite, A, Daddr_hold); $hold(negedge doWrite, D, Ddata_hold); $width(posedge doWrite, Dwrite); endspecify assign doRead = (!CS && !OE); assign doWrite = (!CS && !WE); // // Value read from addressed memory // assign #Dread X = m[A]; // // If chip-select and output-enable are asserted, output value from memory // assign #Dout D = doRead ? X : 8'bz; // // Look for conditions on which to write to memory // always @(doWrite or D or A) if (doWrite) m[A] <= #Dwrite D; always @(D) if (doWrite) $error("`RAMDCHG %m[%M]"); always @(A) if (doWrite) $error("`RAMACHG %m[%M]"); endmodule // ram //: /builtinEnd //: /builtinBegin module _GGREG16 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [15:0] D; output [15:0] Q; reg [15:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 16'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGROLL16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ((I << (S % 16)) | (I >> ((16 - S) % 16))); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGMUX2x16 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [15:0] I0, I1; input S; output [15:0] Z; reg [15:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGCLOCK_P3000_0_50 (Z); output Z; reg Z = 1'b0; initial #1500 forever begin Z = 1'b1; #1500; Z = 1'b0; #1500; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGRSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >> S); endmodule // rshift //: /builtinEnd //: /builtinBegin module _GGDIV16 #(.Dab_q(1), .Dab_r(1)) (A, B, Q, R); input [15:0] A,B; output [15:0] Q,R; assign #Dab_q Q = (A / B); assign #Dab_r R = (A % B); endmodule // div //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUL16 #(.Dab_p(1)) (A, B, P); input [15:0] A,B; output [15:0] P; assign #Dab_p P = (A * B); endmodule //: /builtinEnd //: /builtinBegin module _GGBUF5 #(.Diz(1)) (I, Z); input [4:0] I; output [4:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGMUX8x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input [15:0] I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGBUF16 #(.Diz(1)) (I, Z); input [15:0] I; output [15:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGBUFIF8 #(.Dez(1), .Diz(1)) (Z, I, E); input [7:0] I; input E; output [7:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 8'bz; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGMUX4x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [15:0] I0, I1, I2, I3; input [1:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd tkgate-2.0-b10/locale/de/examples/ex5/x-menagerie.mem000644 001751 001751 00000020634 07311226664 023071 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 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f82000 d92000 d93ecf f8e000 c0/ f83c17 f82000 memory iunit.m2 0/ ffefe0 fbeff6 f7eef6 ffefe0 ffefe0 fffd40 fff940 ffebe0 8/ ffefe0 1ffefe0 1ffefe0 ef1d40 fff940 fffd40 fdf956 fbebf6 10/ ef4fe0 ffefe0 ff0fe0 ef1d40 fff940 fffd40 fdf956 fbebf6 18/ ff0fe0 ef4fe0 ffefe0 22ef8ff5 ffefe0 fffd40 fdf956 fbebf6 20/ efcff5 ffefe0 fffd40 fdf956 fbebf6 feefe0 ffefe0 ffefe0 28/ ffefe0 f7eef6 ffefe0 10ffcff4 ffefe0 ffefe0 ffefe0 ffefe0 30/ ffefe0 11f7efb5 bfeff4 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 38/ ffefe0 f7efb5 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 ffeff6 40/ fffd40 fdf956 fbebf6 ffeff4 fffd40 fdf956 fbebf6 f7eef6 48/ ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 12f7efb6 50/ 7fed74 7de976 fbebf6 7fed76 7de976 fbebf6 f7eef6 fffd40 58/ ffefe0 ffefe0 13f7efb5 f7cf74 ffe7e0 57cff4 ffefe0 ffe7e0 60/ ffefe0 2fffd40 fdf956 fbebf6 13f7efb5 f7ef74 ffe7e0 57eff4 68/ ffefe0 ffe7e0 ffefe0 1ef9d56 fff940 1edaff6 fbfd54 ffd956 70/ 2fffd40 fdf956 fbebf6 efcff6 ffefe0 2fffd40 fdf956 fbebf6 78/ efcff6 ffefe0 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61 6c 20 61 6b4/ 6e 64 20 49 20 77 69 6c 6bc/ 6c 20 74 72 79 20 74 6f 6c4/ 20 67 75 65 73 73 20 77 6cc/ 68 61 74 20 69 74 20 69 6d4/ 73 2e a 0 49 20 63 75 6dc/ 72 72 65 6e 74 6c 79 20 6e4/ 6b 6e 6f 77 20 25 64 20 6ec/ 61 6e 69 6d 61 6c 73 2e 6f4/ a a 0 49 73 20 74 68 6fc/ 65 20 61 6e 69 6d 61 6c 704/ 20 79 6f 75 20 61 72 65 70c/ 20 74 68 69 6e 6b 69 6e 714/ 67 20 6f 66 20 61 20 25 71c/ 73 3f 20 0 79 65 73 0 724/ 6e 6f 0 50 6c 65 61 73 72c/ 65 20 74 79 70 65 20 27 734/ 79 65 73 27 20 6f 72 20 73c/ 27 6e 6f 27 2e a 0 49 744/ 20 67 75 65 73 73 65 64 74c/ 20 79 6f 75 72 20 61 6e 754/ 69 6d 61 6c 21 21 21 a 75c/ a 0 49 20 63 6f 75 6c 764/ 64 20 6e 6f 74 20 67 75 76c/ 65 73 73 20 79 6f 75 72 774/ 20 61 6e 69 6d 61 6c 2e 77c/ 20 20 57 68 61 74 20 77 784/ 61 73 20 79 6f 75 72 20 78c/ 61 6e 69 6d 61 6c 3f 20 794/ 0 45 6e 74 65 72 20 61 79c/ 20 71 75 65 73 74 69 6f 7a4/ 6e 20 74 68 61 74 20 77 7ac/ 6f 75 6c 64 20 64 69 73 7b4/ 74 69 6e 67 75 69 73 68 7bc/ 20 61 20 25 73 20 66 72 7c4/ 6f 6d 20 61 20 25 73 2e 7cc/ a 3e 20 0 54 68 65 20 7d4/ 63 6f 72 72 65 63 74 20 7dc/ 61 6e 73 77 65 72 20 66 7e4/ 6f 72 20 61 20 25 73 20 7ec/ 69 73 3f 20 0 a 0 3f 7f4/ 20 0 tkgate-2.0-b10/locale/de/examples/ex5/menagerie.vs000644 001751 001751 00000000547 11137706734 022501 0ustar00hansenhansen000000 000000 // // Menagerie Initialisierungsskript // initial begin $readmemh("menagerie.mem"); // Lade den Speicherauszug aus Datei. _reset = 1'b0; // Setze Resetleitung repeat (3) // Rücke drei Taktzyklen vor @ (posedge clk); # 10; // Rücke 10 Schritte nach der pos. Taktflanke vor _reset = 1'b1; // Setze Resetleitung zurück end tkgate-2.0-b10/locale/de/examples/ex5/menagerie.gss000644 001751 001751 00000001531 11137710075 022630 0ustar00hansenhansen000000 000000 # # Das Simulationsskript für das Menagerie CPU Beispiel. Es läuft # automatisch, wenn das Beispiel simuliert wird. # # # Initialisiere die Speicher mit den Daten in der menagerie.mem Datei. # Die menagerie.mem Datei wurde mit gmac aus der Datei menagerie.gm # kompiliert. # load "menagerie.mem" # # Setze den Zoomfaktor für das Scope. Das Koomando zoomt drei Stufen # aus um einen größeren Zeitbereich zu zeigen. # zoom 3 # # Diese Kommandos können einkommentiert werden, um Tastköpfe oder # Haltepunkte zu setzen. # #probe clk #break iunit.extra==8'h15 # # Setze die Resetleitung (aktiv low) auf '0', mache zwei Taktschritte # und setze die Resetleitng zurück auf '1'. Diese Folge setzt die CPU # in den Initialzustand. # set reset 1'b0 clock +2 set reset 1'b1 # # Starte die Simulation der Schaltung im kontinuierlichen Modus. # run tkgate-2.0-b10/locale/de/tutorials.18/edit1_tut.v000644 001751 001751 00000016361 07703341036 022215 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w7; //: /sn:0 {0}(713,355)(728,355)(728,367){1} wire s0; //: {0}(781,302)(811,302){1} wire w4; //: /sn:0 {0}(733,337)(733,367){1} wire c0; //: {0}(650,264)(735,264)(735,302){1} //: {2}(737,304)(760,304){3} //: {4}(735,306)(735,316){5} wire c1; //: {0}(731,388)(731,425){1} //: {2}(733,427)(756,427){3} //: {4}(731,429)(731,439){5} wire s1; //: /dp:1 {0}(777,425)(812,425){1} wire a1; //: {0}(645,420)(646,420)(646,419)(669,419){1} //: {2}(673,419)(681,419){3} //: {4}(671,421)(671,475)(688,475){5} wire b1; //: {0}(647,454)(667,454){1} //: {2}(665,452)(665,424)(681,424){3} //: {4}(665,456)(665,480)(688,480){5} wire w8; //: /sn:0 {0}(709,478)(724,478)(724,490){1} wire a0; //: /dp:1 {0}(650,296)(673,296){1} //: {2}(677,296)(685,296){3} //: {4}(675,298)(675,352)(692,352){5} wire b0; //: /dp:1 {0}(648,331)(667,331){1} //: {2}(669,329)(669,301)(685,301){3} //: {4}(669,333)(669,357)(692,357){5} wire c2; //: {0}(814,522)(727,522)(727,511){1} wire w10; //: /sn:0 {0}(756,422)(728,422){1} //: {2}(724,422)(702,422){3} //: {4}(726,424)(726,439){5} wire w5; //: /sn:0 {0}(729,460)(729,490){1} wire w9; //: /sn:0 {0}(760,299)(732,299){1} //: {2}(728,299)(706,299){3} //: {4}(730,301)(730,316){5} //: enddecls //: joint g8 (c1) @(731, 427) /w:[ 2 1 -1 4 ] nand g4 (.I0(w8), .I1(w5), .Z(c2)); //: @(727,501) /sn:0 /R:3 /w:[ 1 1 1 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end led g37 (.I(s0)); //: @(818,302) /sn:0 /R:3 /w:[ 1 ] /type:0 xor g34 (.I0(w10), .I1(c1), .Z(s1)); //: @(767,425) /sn:0 /w:[ 0 3 0 ] //: comment g13 /dolink:0 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end //: comment g3 /dolink:0 /link:"" @(29,277) /anc:1 //: /line:"5) Öffne das \"Werkzeug\"-Menu und wähle \"Bitbreite\" aus, um das Bandkabel-" //: /line:"Werkzeug zu bekommen. Gleichzeitig wird rechts unten neben dem Logo ein Fenster" //: /line:"geöffnet, das mit \"Bits:\" gekennzeichnet ist. Trage in das Feld eine Zahl von" //: /line:"1 bis 32 ein. Dann klicke auf eine Leitung, um sie auf die angegebene Bitbreite" //: /line:"zu bringen." //: /line:"" //: /line:"6) Ein Doppelklick auf eine Leitung öffnet das Eigenschaften-Fenster. Ändere" //: /line:"den Signalnamen, mache den Signalnamen sichtbar oder setze die Bitbreite der" //: /line:"Leitung. Die Eigenschaftsbox kann auch mit der rechten Maustaste im Klappauf-" //: /line:"Menu geöffnet werden." //: /line:"" //: /line:"7) Öffne das \"Werkzeug\"-Menu und wähle \"Bewegen/Verbinden\" aus, um zum Basis-" //: /line:"Editierwerkzeug zurückzukehren. Klicke doppelt (oder mit Rechtsklick und " //: /line:"\"Eigenschaften\" ...) auf ein XOR-Gatter. Dies öffnet das Eigenschaften-Fenster" //: /line:"für das Gatter. Dort kann man den Namen ändern, den Namen sichtbar machen " //: /line:"(Rückgängigmachen der \"Verstecken\"-Option) und Ports hinzufügen oder löschen." //: /line:"" //: /line:"8) Schalte mit einem Rechtsklick auf einem Gatter das \"Anker\"-Flag ein. " //: /line:"Versuche nun, das Gatter zu bewegen (das sollte nicht gehen). Das kann man" //: /line:"benutzen, die Teile der Schaltung festzuzurren, die man möglichst nicht" //: /line:"verschoben haben möchte." //: /end //: comment g2 /dolink:0 /link:"" @(29,38) /anc:1 //: /line:"1) Mit der linken Maustaste auf das Gatter klicken. Dann ziehe man das Gatter" //: /line:"in eine neue Position und beobachte, wie die Leitungen sich mit dem Gatter " //: /line:"bewegen." //: /line:"" //: /line:"2) \"Werkzeugmenu\" Öffnen und \"Leitung trennen\" auswählen. Damit wird eine" //: /line:"Kneifzange bereitgestellt. Klickt man mit der Kneifzange irgendwo auf einen " //: /line:"Draht, so wird er aufgetrennt. Lose Segmente oder Segmente zu einem " //: /line:"Verbindungspunkt werden automatisch gelöscht. Den Modus kann man wieder wechseln," //: /line:"indem man mit der rechten Maustaste in einen leeren Bereich klickt und aus dem" //: /line:"Klappauf-Menu einen geeigneten Modus auswählt." //: /line:"" //: /line:"3) Öffne das \"Werkzeug\"-Menu und wähle \"Invertieren\" aus, das Invertierer-" //: /line:"Werkzeug zeigt sich. Klicke mit der \"Inverter-Blase\" in der Nähe eines Eingangs" //: /line:"oder des Ausgangs, so wird eine Invertierung hinzugefügt oder entfernt." //: /line:"" //: /line:"4) Öffne das \"Werkzeug\"-Menu und wähle \"Gatter löschen\" aus; dies stellt ein" //: /line:"IC-Entfernungs-Werkzeug bereit. Klicke probeweise damit auf ein Gatter: es wird" //: /line:"entfernt. Alternative: Wähle das Gatter aus und drücke die \"Entf\"-Taste oder" //: /line:"wähle mit der rechten Maustaste aus dem Klappaufmenu \"Löschen\"." //: /end nand g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(731,378) /sn:0 /R:3 /w:[ 1 1 0 ] //: switch g11 (a1) @(628,420) /sn:0 /w:[ 0 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: joint g10 (a1) @(671, 419) /w:[ 2 -1 1 4 ] nand g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(703,355) /sn:0 /w:[ 5 5 0 ] led g19 (.I(s1)); //: @(819,425) /sn:0 /R:3 /w:[ 1 ] /type:0 //: switch g27 (c0) @(633,264) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(730, 299) /w:[ 1 -1 2 4 ] //: joint g38 (b1) @(665, 454) /w:[ 1 2 -1 4 ] nand g6 (.I0(a1), .I1(b1), .Z(w8)); //: @(699,478) /sn:0 /w:[ 5 5 0 ] nand g9 (.I0(w10), .I1(c1), .Z(w5)); //: @(729,450) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g7 (w10) @(726, 422) /w:[ 1 -1 2 4 ] //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end nand g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(733,327) /sn:0 /R:3 /w:[ 5 5 0 ] led g39 (.I(c2)); //: @(821,522) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: switch g25 (a0) @(633,296) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(675, 296) /w:[ 2 -1 1 4 ] //: comment g5 /dolink:0 /link:"" @(268,523) /sn:0 //: /line:"" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: switch g36 (b1) @(630,454) /sn:0 /w:[ 0 ] /st:0 //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end xor g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(771,302) /sn:0 /w:[ 0 3 0 ] xor g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(696,299) /sn:0 /w:[ 3 3 3 ] xor g35 (.I0(a1), .I1(b1), .Z(w10)); //: @(692,422) /sn:0 /w:[ 3 3 3 ] //: comment g22 /dolink:0 /link:"" @(605,70) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(8,10) /anc:1 //: /line:"Dieser Abschnitt führt in die grundlegenden Editiervorgänge von TkGate ein." //: /end //: switch g26 (b0) @(631,331) /sn:0 /w:[ 0 ] /st:0 //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end //: joint g30 (b0) @(669, 331) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(735, 304) /w:[ 2 1 -1 4 ] endmodule tkgate-2.0-b10/locale/de/tutorials.18/edit2_tut.v000644 001751 001751 00000007541 07703341036 022216 0ustar00hansenhansen000000 000000 //: version "1.7" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w3; //: /sn:0 {0}(756,264)(679,264){1} wire w1; //: /sn:0 {0}(756,259)(712,259)(712,224)(679,224){1} wire w2; //: /sn:0 {0}(679,302)(689,302){1} wire w5; //: /sn:0 {0}(777,262)(787,262){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end and g4 (.I0(w1), .I1(w3), .Z(w5)); //: @(767,262) /sn:0 /w:[ 0 0 0 ] //: switch g3 (w2) @(662,302) /sn:0 /w:[ 0 ] /st:0 //: switch g2 (w3) @(662,264) /sn:0 /w:[ 1 ] /st:0 //: switch g1 (w1) @(662,224) /sn:0 /w:[ 1 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: frame g11 @(434,355) /sn:0 /anc:1 /wi:373 /ht:230 /tx:"Gatter hier hin kopieren" //: frame g10 @(21,357) /sn:0 /anc:1 /wi:394 /ht:227 /tx:"Gatter hier hin ziehen" //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: comment g5 /dolink:0 /link:"" @(26,34) /anc:1 //: /line:"1) Klicke mit der linken Maustaste links oberhalb der drei Schalter. Drücke" //: /line:"und halte die linke Maustaste und ziehe sie nach rechts unten. Nach ein paar" //: /line:"mm Ziehen erscheint ein Auswahlfenster. Bewege die Maus soweit, bis die " //: /line:"ganze Schaltung im Kasten eingeschlossen ist. Die Schalter und das Gatter sind" //: /line:"hervorgehoben, um die Selektion anzudeuten." //: /line:"" //: /line:"2) Drücke und halte die Maus auf einem der ausgewählten Gatter. Ziehe die" //: /line:"ganze Gattergruppe in das Fenster \"Gatter hier hin ziehen\". Klicke irgendwo" //: /line:"auf die Canvas-Fläche, wo kein Gatter und kein Draht ist, um die Selektion " //: /line:"aufzuheben." //: /line:"" //: /line:"3) Wähle das AND-Gatter in der Gattergruppe aus. Gehe ins \"Gatter\"-Menu und " //: /line:"wähle \"Eingang hinzufügen\" aus. Damit entsteht ein neuer Eingang des AND-" //: /line:"Gatters, der nun mit dem noch unbeschalteten Schalter verbunden werden kann." //: /line:"" //: /line:"4) Nach den Anweisungen in 1) werden wieder die drei Schalter und das AND-Gatter" //: /line:"ausgewählt. Gehe nun ins \"Editieren\"-Menu und wähle \"Kopieren\" aus, um die " //: /line:"Gruppe der Gatter in den Ausschnittpuffer zu kopieren. Klicke nun mit der" //: /line:"linken Maustaste in die Mitte des Kastens \"Gatter hier hin kopieren\" und wähle " //: /line:"\"einfügen\" aus dem \"Editieren\"-Menu. Das erzeugt eine Kopie des selektierten" //: /line:"Gatters. Man kann auch die \"Entf\"-Taste auf einer Gruppe selektierter Gatter" //: /line:"drücken, um sie zu entfernen." //: /line:"" //: /line:"5) Eine Gruppenauswahl gelingt auch, wenn man auf ein Gatter klickt und die" //: /line:"\"Strg\"-Taste gedrückt hält. Das fügt ein Gatter nach dem anderen zu einer " //: /line:"Auswahl hinzu." //: /end //: comment g21 /dolink:0 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end //: comment g22 /dolink:0 /link:"" @(605,85) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(26,17) /anc:1 //: /line:"Dieser Abschnitt führt in die Gruppen-Editiervorgänge ein." //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end //: comment g12 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end endmodule tkgate-2.0-b10/locale/de/tutorials.18/edwire_tut.v000644 001751 001751 00000024255 07703341036 022467 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(484,155)(524,155)(524,138)(549,138)(549,150)(574,150)(574,200)(500,200)(500,170){1} wire w7; //: /sn:0 {0}(476,435)(486,435){1} wire w46; //: /sn:0 /dp:1 {0}(737,572)(694,572)(694,563){1} //: {2}(696,561)(710,561)(710,523)(735,523){3} //: {4}(692,561)(659,561){5} wire w16; //: /sn:0 {0}(553,109)(563,109){1} wire w14; //: /sn:0 /dp:1 {0}(532,106)(522,106)(522,87)(541,87)(541,54)(488,54){1} wire w19; //: /sn:0 {0}(610,437)(620,437){1} wire w15; //: /sn:0 {0}(522,111)(532,111){1} wire w4; //: /sn:0 {0}(453,157)(463,157){1} wire w38; //: /sn:0 {0}(755,394)(765,394){1} wire w0; //: /sn:0 {0}(453,152)(463,152){1} wire w3; //: /sn:0 {0}(489,288)(530,288){1} //: {2}(534,288)(587,288){3} //: {4}(532,286)(532,242)(562,242){5} wire w37; //: /sn:0 {0}(729,394)(739,394){1} wire w34; //: /sn:0 {0}(752,363)(762,363){1} wire w43; //: /sn:0 {0}(628,558)(638,558){1} wire w21; //: /sn:0 {0}(610,475)(620,475){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(640,365)(650,365){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,393)(554,393){1} wire w24; //: /sn:0 {0}(554,365)(531,365){1} //: {2}(529,363)(529,334)(555,334){3} //: {4}(527,365)(489,365){5} wire w20; //: /sn:0 {0}(594,475)(582,475)(582,437)(594,437){1} wire w1; //: /sn:0 {0}(458,285)(468,285){1} wire w25; //: /sn:0 {0}(571,334)(581,334){1} wire w35; //: /sn:0 {0}(640,360)(650,360){1} wire w8; //: /sn:0 {0}(583,240)(593,240){1} wire w18; //: /sn:0 {0}(529,481)(539,481){1} wire w40; //: /sn:0 {0}(560,479)(570,479){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,367)(468,367){1} wire w17; //: /sn:0 {0}(539,476)(523,476)(523,438)(507,438){1} wire w44; //: /sn:0 {0}(628,563)(638,563){1} wire w12; //: /sn:0 {0}(457,56)(467,56){1} wire w11; //: /sn:0 {0}(457,51)(467,51){1} wire w2; //: /sn:0 {0}(458,290)(468,290){1} wire w10; //: /sn:0 {0}(458,362)(468,362){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,393)(580,393){1} wire w48; //: /sn:0 {0}(751,523)(761,523){1} wire w33; //: /sn:0 {0}(736,363)(713,363){1} //: {2}(711,361)(711,331)(737,331){3} //: {4}(709,363)(671,363){5} wire w5; //: /sn:0 {0}(552,237)(562,237){1} wire w47; //: /sn:0 {0}(753,572)(763,572){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(476,440)(486,440){1} wire w39; //: /sn:0 {0}(753,331)(763,331){1} wire w26; //: /sn:0 {0}(570,365)(580,365){1} //: enddecls //: comment g61 /dolink:0 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end xor g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(474,155) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g4 /dolink:0 /link:"" @(543,256) /sn:0 //: /line:"<---" //: /end //: frame g51 @(450,507) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Bild 6a" //: joint g37 (w33) @(711, 363) /w:[ 1 2 4 -1 ] //: frame g34 @(449,321) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Bild 4a" //: joint g3 (w3) @(532, 288) /w:[ 2 4 1 -1 ] or g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(550,479) /sn:0 /w:[ 0 1 0 ] and g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(573,240) /sn:0 /w:[ 1 5 0 ] //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end and g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(543,109) /sn:0 /anc:1 /w:[ 0 1 0 ] //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: joint g50 (w46) @(694, 561) /w:[ 2 -1 4 1 ] buf g28 (.I(w24), .Z(w26)); //: @(560,365) /sn:0 /w:[ 0 0 ] and g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(478,54) /sn:0 /anc:1 /w:[ 1 1 1 ] and g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 365) /w:[ 1 2 4 -1 ] buf g19 (.I(w20), .Z(w19)); //: @(600,437) /sn:0 /anc:1 /w:[ 1 0 ] and g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(661,363) /sn:0 /w:[ 1 1 5 ] //: comment g6 /dolink:0 /link:"" @(22,11) /sn:0 /anc:1 //: /line:"Dieses Tutorium führt in spezielle Editiervorgänge auf Leitungen ein." //: /end //: comment g53 /dolink:0 /link:"" @(726,534) /sn:0 //: /line:"<---" //: /end //: comment g7 /dolink:0 /link:"" @(508,162) /sn:0 /anc:1 //: /line:"<---" //: /end //: comment g9 /dolink:0 /link:"" @(26,30) /anc:1 //: /line:"1) In TkGate ist ein besonderes \"Schwerkraftfeld\" " //: /line:"eingebaut. Kurze Leitungssegmente werden automatisch" //: /line:"bereinigt. Klicke auf den Draht am durch den Pfeil " //: /line:"gekennzeichneten Punkt in Bild 1 und bewege ihn, bis" //: /line:"er zu dem anderen vertikalen Leitungsabschnitt fast" //: /line:"ausgerichtet ist. Beim Auslässen der Maustaste rasten" //: /line:"die beiden Segmente perfekt ausgerichtet ein." //: /line:"" //: /line:"2) Tkgate löscht automatisch Leitungsabschnitte, die " //: /line:"Schleifen bilden. Zur Demonstration wähle das Ende der" //: /line:"Ausgangsleitung des XOR-Gatters in Bild 2 mit der linken" //: /line:"Maustaste aus. Ziehe das Ende nach oben direkt zum " //: /line:"Ausgang des Gatters und löse die Maustaste aus. Diese" //: /line:"Automatik kann ausgeschaltet werden: Drücke beim " //: /line:"Bewegen von Drähten die \"ALT\"-Taste." //: /line:"" //: /line:"3) TkGate ist auch in der Lage, unbenutzte " //: /line:"Verbindungspunkte automatisch zu löschen. Wähle die" //: /line:"Kneifzange aus und schneide den Draht an der in Bild" //: /line:"3a angegebenen Stelle auf. Beachte, dass der Lötpunkt" //: /line:"automatisch entfernt wird. Ein Schnitt auf das freie" //: /line:"Ende in Bild 3b beseitigt dieses rückstandsfrei." //: /line:"" //: /line:"4) Schalte zurück auf Bewegen/Verbinden und wähle den " //: /line:"Eingang des untersten Puffers in Bild 4a aus, so daß" //: /line:"der Lötkolben erscheint. Bewege den Endpunkt in die" //: /line:"Nähe der Lötstelle und löse die Maustaste aus. Der" //: /line:"Draht wird mit der Lötstelle verbunden. Wiederhole die" //: /line:"Aktion in Bild 4b und löse die Maustaste zwischen dem " //: /line:"AND-Gatter und der Lötstelle aus. Diesesmal wird eine" //: /line:"neue Lötstelle erzeugt." //: /line:"" //: /line:"5) Füge zum Ausgang des AND-Gatters in Bild 5 ein neues" //: /line:"Segment hinzu, um es mit dem gemeinsamen Eingang der" //: /line:"beiden Puffer zu verbinden. Klicke dazu mit der rechten" //: /line:"Maustaste auf das durch den Pfeil gekennzeichnete " //: /line:"Leitungssegment. Wähle dann \"Leitungssegment hinzufügen\"" //: /line:"aus dem eingeblendeten Menu. Jetzt kann das Ende des" //: /line:"erzeugten Segments irgendwo mit dem Draht am Eingang" //: /line:"der beiden Puffer verbunden werden." //: /line:"" //: /line:"6) Wähle die Leitung an den in den Bildern 6a und 6b" //: /line:"gekennzeichneten Punkten aus und ziehe sie nach links" //: /line:"hinter den Ausgangs-Punkt des AND-Gatters bzw. hinter" //: /line:"die Position des Verbindungspunktes. Im Fall des " //: /line:"AND-Gatters werden Segmente hinzugefügt, damit der" //: /line:"die Leitung den Ausgang mit Sicherheit nach rechts " //: /line:"verläßt. Im Fall des Lötpunktes wird die" //: /line:"Position des Drahtes rund um diesen Verbindungspunkt" //: /line:"neu justiert. " //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" and g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /anc:1 /w:[ 1 1 0 ] buf g48 (.I(w46), .Z(w47)); //: @(743,572) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,224) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Bild 3b" buf g29 (.I(w23), .Z(w27)); //: @(560,393) /sn:0 /w:[ 1 0 ] and g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,365) /sn:0 /w:[ 1 1 5 ] //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: frame g52 @(612,509) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Bild 6b" //: frame g42 @(448,226) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Bild 3a" and g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(497,438) /sn:0 /w:[ 1 1 1 ] //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end and g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(649,561) /sn:0 /w:[ 1 1 5 ] buf g44 (.I(w37), .Z(w38)); //: @(745,394) /sn:0 /w:[ 1 0 ] buf g36 (.I(w33), .Z(w34)); //: @(742,363) /sn:0 /w:[ 0 0 ] //: comment g24 /dolink:0 /link:"" @(491,449) /sn:0 //: /line:"--->" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end //: frame g41 @(447,128) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Bild 2" buf g23 (.I(w20), .Z(w21)); //: @(600,475) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g54 /dolink:0 /link:"" @(556,521) /sn:0 /anc:1 //: /line:"<---" //: /end //: frame g40 @(442,34) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Bild 1" //: frame g46 @(449,419) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Bild 5" buf g45 (.I(w33), .Z(w39)); //: @(743,331) /sn:0 /w:[ 3 0 ] //: frame g35 @(627,319) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Bild 4b" buf g26 (.I(w24), .Z(w25)); //: @(561,334) /sn:0 /w:[ 3 0 ] //: comment g22 /dolink:0 /link:"" @(605,100) /sn:0 /anc:1 //: /line:"->" //: /end and g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(479,288) /sn:0 /w:[ 1 1 0 ] //: comment g12 /dolink:0 /link:"" @(552,63) /sn:0 /anc:1 //: /line:"<---" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end and g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 /dolink:0 /link:"" @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end buf g49 (.I(w46), .Z(w48)); //: @(741,523) /sn:0 /anc:1 /w:[ 3 0 ] endmodule tkgate-2.0-b10/locale/de/tutorials.18/module_tut.v000644 001751 001751 00000017072 07703341036 022474 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module foo(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 //: /line:"Leitungen editieren" //: /end //: comment g3 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 //: /line:"Grundlegende Editier-Modi" //: /end //: frame g1 @(409,199) /sn:0 /wi:404 /ht:316 /tx:"Hier Ports des Moduls erzeugen" //: comment g16 /dolink:0 /link:"@T/module_tut.v" @(630,115) /sn:0 //: /line:"Module benutzen" //: /end //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 //: /line:"Erzeugen einer Schaltung" //: /end //: frame g15 @(600,25) /sn:0 /wi:213 /ht:149 /tx:"Tutorien" //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 //: /line:"Schaltnetzsimulation" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 //: /line:"Schaltwerkssimulation" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 //: /line:"Editieren von Gruppen" //: /end //: comment g0 /dolink:0 /link:"" @(26,29) /anc:1 //: /line:"10) Dies ist die Definition des \"foo\"" //: /line:"Moduls. Die \"Ports\" Liste in der linken" //: /line:"unteren Ecke des Hauptfensters zeigt die" //: /line:"Ports an, die wir in der Standard Modulinstanz" //: /line:"definiert haben. Um eine interne Referenz auf" //: /line:"einen Port zu erzeugen, klicke mit der Maus" //: /line:"(Setzen einer Markierung) und wähle \"Modul Eingang\"," //: /line:"\"Modul Ausgang\" oder \"Modul InOut\" aus dem" //: /line:"\"Modul\" Untermenu des \"Make\"-Menus. Es" //: /line:"erscheint ein Dialogfenster, in dem man den" //: /line:"Namen des Ports setzen kann. Gib einen Namen ein" //: /line:"und drücke \"RETURN\"." //: /line:"" //: /line:"11) Man kann auch eine neue Moduldefinition" //: /line:"erzeugen, ohne eine Instanz zu erzeugen, indem" //: /line:"man \"Neu...\" aus dem \"Module\"-Menu auswählt." //: /line:"Dadurch erhält man ein Dialogfenster, in dem" //: /line:"nach einem Modulnamen gefragt wird. Gib" //: /line:"\"bar\" ein und drücke RETURN." //: /line:"" //: /line:"12) Man kann Module umbenennen, kopieren und" //: /line:"löschen, indem man die anderen Kommandos im \"Modul\"-" //: /line:"Menu benutzt." //: /line:"" //: /line:"13) Falls dieser Block durch Doppelklick" //: /line:"auf \"foo\" in der Modulliste geöffnet wurde," //: /line:"kann man zum Hauptmodul zurückkehren, indem man auf" //: /line:"\"main\" doppelklickt. Falls dieser Block mit dem" //: /line:"\"Öffnen\" Kommando aus dem \"Modul\"-Menu geöffnet" //: /line:"wurde, kann man zur nächsthöheren Ebene gelangen," //: /line:"indem \"Schließen\" im \"Modul\"-Menu ausgewählt wird" //: /line:"oder ein Doppelklick auf \"main\" erfolgt." //: /end //: comment g22 /dolink:0 /link:"" @(605,115) /sn:0 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 //: /line:"TkGate Einführung" //: /end endmodule module main; //: root_module //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end //: comment g3 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end //: frame g2 @(477,189) /sn:0 /wi:330 /ht:350 /tx:"Freies Feld für Modulinstanzen" //: comment g1 /dolink:0 /link:"" @(11,34) /anc:1 //: /line:"1) Klicke mit der linken Maustaste in der Mitte der leeren Fläche." //: /line:"Wähle nun \"Modul-Instanz\" aus dem \"Module\"-Untermenu des \"Make\"-Menus. Damit" //: /line:"wird eine Modul-Instanz erzeugt, eine Dialogbox erscheint, in der der" //: /line:"\"Funktion\"-Eintrag aktiviert ist. Trage dort \"foo\" in Kleinbuchstaben ein und" //: /line:"drücke RETURN. Damit wird der Instanzen-Typ auf \"foo\" gesetzt." //: /line:" " //: /line:"2) Drücke die linke Maustaste in der Nähe der unteren rechten Ecke der" //: /line:"Modulinstanz und ziehe sie nach unten und nach rechts, um den Kasten zu" //: /line:"vergrößern." //: /end //: comment g16 /dolink:0 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: comment g6 /dolink:0 /link:"" @(10,148) /anc:1 //: /line:"3) Klicke mit der rechten Maustaste auf den Block nahe der linken" //: /line:"Kante und wähle \"Eingang hinzufügen\" aus dem hochkommenden Menu. Es " //: /line:"öffnet sich eine Dialogbox, in der der Eintrag für \"Port Name\" " //: /line:"aktiviert ist. Tippe ein \"A\" und RETURN. Wiederhole den Vorgang" //: /line:"und füge die Eingänge \"B\" und \"C\" auf der gleichen Seite hinzu." //: /line:"Wiederhole den gleichen Vorgang auf der rechten Seite und füge" //: /line:"diesmal Ausgänge hinzu: erzeuge \"X\", \"Y\" und \"Z\" auf der rechten" //: /line:"Seite des Blocks." //: /line:"" //: /line:"4) Klicke auf einen der neu hinzugefügten Ports nahe der Modul-" //: /line:"Kante. Er kann dann entlang der Kante, an der er hinzugefügt " //: /line:"wurde, verschoben werden." //: /line:"" //: /line:"5) Klicke mit der rechten Maustaste auf den Block in der Nähe" //: /line:"eines der Ports und wähle \"Typ ändern\" aus dem hochkommenden Menu." //: /line:"Das ändert die Richtung des selektierten Ports. Wiederhole" //: /line:"diese Aktion und ändere in einen der drei Port-Typen \"Eingang\"," //: /line:"\"Ausgang\" oder \"InOut\"." //: /line:"" //: /line:"6) Wähle \"Leitung trennen\" aus dem \"Werkzeug\"-Menu und klicke " //: /line:"auf den \"Z\"-Draht nahe an der Kante der Modulinstanz. Damit" //: /line:"wird der Port gelöscht. " //: /line:"" //: /line:"7) Wähle \"Bewegen/Verbinden\" aus dem \"Werkzeug\"-Menu, um in den" //: /line:"Standard-Editiermodus zu gelangen. Wähle nun eine neue Position " //: /line:"mit der Maus und erzeuge eine neue Modulinstanz vom Typ \"foo\"." //: /line:"Beachte, daß die Instanzgröße und die Leitungspositionen nicht " //: /line:"kopiert werden." //: /line:"" //: /line:"8) Selektiere wieder die Instanz, zu der Eingänge und " //: /line:"Ausgänge hinzugefügt wurden, und wähle \"Schnittstelle belegen\"" //: /line:"aus dem \"Modul\"-Menu. Erzeuge nun wieder eine neue Modul-Instanz" //: /line:"des \"foo\"-Moduls. Jetzt wird bei jeder neu erzeugten \"foo\"-Instanz" //: /line:"auch die Schnittstelle mit kopiert." //: /line:"" //: /line:"9) Öffne nun das \"foo\"-Modul. Das geht entweder durch Auswahl " //: /line:"einer der Modul-Instanzen und nachfolgender Auswahl von \"Öffnen\"" //: /line:"aus dem \"Modul\"-Menu oder durch Doppelklick auf den Eintrag \"foo\"" //: /line:"in der Modulliste auf der linken Seite im Hauptfenster." //: /end //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end //: comment g0 /dolink:0 /link:"" @(22,9) /anc:1 //: /line:"Dieses Tutorium zeigt die Verwendung von Modulen in TkGate." //: /end //: comment g22 /dolink:0 /link:"" @(605,115) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end endmodule tkgate-2.0-b10/locale/de/tutorials.18/seqsim_tut.v000644 001751 001751 00000013324 10013112121 022457 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w3; //: /sn:0 {0}(705,275)(705,265)(692,265){1} supply0 w0; //: /sn:0 /dp:1 {0}(707,320)(730,320)(730,335){1} wire [7:0] w7; //: /sn:0 {0}(652,225)(652,251){1} wire w4; //: /sn:0 /dp:1 {0}(707,310)(718,310)(718,298)(728,298){1} wire [7:0] w2; //: /sn:0 /dp:1 {0}(668,305)(668,280){1} wire ck; //: /dp:1 {0}(631,315)(566,315){1} wire [7:0] reg_out; //: {0}(668,326)(668,368)(724,368){1} //: {2}(728,368)(784,368)(784,241)(684,241)(684,251){3} //: {4}(726,370)(726,400){5} wire w9; //: /sn:0 {0}(644,265)(634,265){1} //: enddecls //: joint g8 (reg_out) @(726, 368) /w:[ 2 -1 1 4 ] //: supply0 g4 (w0) @(730,341) /sn:0 /w:[ 1 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end //: switch g3 (w4) @(746,298) /sn:0 /R:2 /w:[ 1 ] /st:1 //: comment g13 /dolink:0 /link:"" @(24,45) /anc:1 //: /line:"1) Drücke den \"Simulationsknopf\" in der Knopfleiste oben oder wähle" //: /line:"\"Anfang Simulation\" aus dem \"Simulieren\"-Menu. Das Simulationsfenster" //: /line:"sollte erscheinen." //: /line:"" //: /line:"2) Bringe je einen Tastkopf auf der mit \"ck\" markierten Leitung" //: /line:"und auf den mit \"reg_out\" markierten Ausgangsleitungen des Registers" //: /line:"mit einem Doppelklick an. Für jedes Signal sollte ein Signaldiagramm" //: /line:"im Fenster erscheinen." //: /line:"" //: /line:"3) Die Simulation schreitet fort, wenn man mehrfach nacheinander" //: /line:"die Leertaste drückt. Eine Epoche ist die kleinste vom Simulator " //: /line:"modellierte Zeiteinheit. Die Einzelheiten zum Setzen der Schrittweite " //: /line:"stehen im Tutorium für Schaltnetze." //: /line:"" //: /line:"4) Simulationsfortschritt um einen Taktzyklus wird durch Drücken" //: /line:"der \"TAB\"-Taste oder durch \"Periodenschritt\" im \"Simulieren\"-Menu" //: /line:"erreicht. Die Simulation schreitet bis zur nächsten positiven Flanke " //: /line:"in jedem Taktgenerator der Schaltung fort und zusätzlich noch einige" //: /line:"Epochenschritte, um den Registern Zeit zu geben, die neuen Werte vor" //: /line:"dem Pausieren der Simulation einzuspeichern. Man kan diesen Überschuß" //: /line:"ebenso wie die Anzahl der fortzuschreitenden Taktzyklen ändern oder" //: /line:"Einzeltakt wählen über die Simulationsoptionen in der Optionen-" //: /line:"Dialogbox." //: /line:"" //: /line:"5) Setze in diesem Beispiel den Schalter CLR auf \"off\" und simuliere" //: /line:"einen Takt, um das Register zu löschen. Schalte dann den Schalter auf" //: /line:"\"on\" und treibe die Simulation ein paar Takte voran, um den Zähler zu" //: /line:"erhöhen." //: /line:"" //: /line:"6) Klicke auf den DIP-Schalter. Es öffnet sich ein Fenster, in dem man" //: /line:"den DIP-Schalter-wert ändern kann. Gib eine Zahl (in HEX) ein und drücke" //: /line:"\"Anwenden\", um die Dauer des Intervallschritts zu ändern." //: /line:"" //: /line:"7) Genau wie im Schaltnetzbeispiel kann man hier auch auf Leitungen klicken," //: /line:"um den (logischen) Wert auf dem Draht zu sehen." //: /line:"" //: /line:"8) Drücke den \"Simulationsknopf\" in der Knopfleiste erneut oder wähle " //: /line:"\"Run\" aus dem \"Simulieren\"-Menu. Dann geht der Simulator in den" //: /line:"kontinuierlichen Simulationsmodus, bis der \"Pause\"-Knopf gedrückt wird." //: /line:"Man kann weiterhin die Werte von Schaltern etc. ändern, während" //: /line:"die Simulation läuft." //: /line:"" //: /end register g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(668,315) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: comment g10 /dolink:0 /link:"" @(531,478) /sn:0 /R:2 //: /line:"9) Man kann das Oszilloskopbild entweder" //: /line:"mit dem Rollbalken verschieben oder in" //: /line:"das Diagrammfenster klicken und die Spuren" //: /line:"nach links oder rechts verschieben. Zoom" //: /line:"In und Out ist auch möglich: Klicke mit" //: /line:"gedrückter Strg- oder Shift-Taste." //: /line:"Das Ziehen des Rollbalkens ganz nach rechts" //: /line:"führt dazu, dass die aktuellen Werte erneut" //: /line:"kontinuierlich aufgefrischt werden." //: /end //: dip g6 (w7) @(652,215) /sn:0 /w:[ 0 ] /st:1 //: supply0 g9 (w3) @(705,281) /sn:0 /w:[ 0 ] led g7 (.I(reg_out)); //: @(726,407) /sn:0 /R:2 /w:[ 5 ] /type:2 //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Schaltung erzeugen" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end add g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(668,267) /sn:0 /w:[ 1 3 1 1 0 ] //: comment g14 /dolink:0 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editiiern von Gruppen" //: /end clock g0 (.Z(ck)); //: @(553,315) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g22 /dolink:0 /link:"" @(605,145) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"Dieses Tutorium führt in die Grundlagen der Simulation von Schaltwerken ein." //: /line:"" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end endmodule tkgate-2.0-b10/locale/de/tutorials.18/sim_tut.v000644 001751 001751 00000013670 10013112445 021763 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(750,326)(678,326){1} wire w4; //: /sn:0 {0}(652,260)(620,260){1} //: {2}(618,258)(618,240)(588,240){3} //: {4}(586,238)(586,227){5} //: {6}(584,240)(571,240){7} //: {8}(618,262)(618,323)(657,323){9} wire w0; //: /sn:0 {0}(750,321)(707,321)(707,305){1} wire w3; //: /sn:0 {0}(687,225)(707,225){1} //: {2}(709,223)(709,214){3} //: {4}(709,227)(709,256){5} //: {6}(711,258)(749,258){7} //: {8}(709,260)(709,284){9} wire w1; //: /sn:0 {0}(749,263)(706,263){1} //: {2}(702,263)(673,263){3} //: {4}(704,265)(704,284){5} wire C; //: /dp:1 {0}(798,312)(798,324)(771,324){1} wire w5; //: /sn:0 {0}(571,288)(585,288){1} //: {2}(589,288)(607,288){3} //: {4}(609,286)(609,265)(652,265){5} //: {6}(609,290)(609,328)(657,328){7} //: {8}(587,286)(587,276){9} wire S; //: {0}(770,261)(795,261)(795,251){1} //: enddecls nand g8 (.I0(w0), .I1(w6), .Z(C)); //: @(761,324) /sn:0 /w:[ 0 0 1 ] xor g4 (.I0(w4), .I1(w5), .Z(w1)); //: @(663,263) /sn:0 /w:[ 0 5 3 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editieren" //: /end //: switch g3 (w3) @(670,225) /sn:0 /w:[ 0 ] /st:1 //: comment g13 /dolink:0 /link:"" @(25,45) /anc:1 //: /line:"1) Drücke die \"Simulations\"-Taste aus der Knopfleiste oben oder " //: /line:"wähle \"Anfang Simulation\" aus dem \"Simulieren\"-Menu. Jetzt" //: /line:"sollte das Simulationsfenster erscheinen." //: /line:"" //: /line:"2) Setze einen Tastkopf auf die zwei Leitungen mit dem Marken " //: /line:"\"S\" und \"C\" und auf jede Leitung, die von den Schaltern abgeht." //: /line:"(Mit einem Doppelklick!). Im Oszilloskop-Fenster erscheint für" //: /line:"jedes der Signale eine Zeitachse. " //: /line:"" //: /line:"3) Drücke einigemale die Leertaste, um die Simulation " //: /line:"voranzubringen. Jeder Leertastendruck bringt die Simulationszeit" //: /line:"um eine Einheit, die sog. Epoche,voran. Das ist die kleinste" //: /line:"Zeiteinheit, die der Simulator auflösen kann." //: /line:"" //: /line:"4) Wähle \"Optionen...\" aus dem \"Datei\"-Menu. Klicke auf die " //: /line:"Simulator-Taste im Optionen-Kasten und gib \"5\" als Eintrag" //: /line:"für die \"Epochen-Schrittweite\" ein, danach \"OK\". Wenn jetzt" //: /line:"die Leertaste gedrückt wird, schreitet der Simulator in " //: /line:"5-Epochen-Schritten voran." //: /line:"" //: /line:"5) Klicke auf einen der Schalter, um den Wert zu ändern und" //: /line:"bewege den Simulator mit der Leertaste voran. Die richtigen" //: /line:"Simulationswerte sollten im Fenster erscheinen." //: /line:"" //: /line:"6) Drücke und halte die linke Maustaste auf irgendeiner der " //: /line:"internen Verbindungen, um den aktuellen Wert anzusehen. Der " //: /line:"Wert wird im \"Verilog\"-Format angezeigt. Die erste Zahl gibt" //: /line:"die Bitbreite an, der Buchstabe die Basis und die Zahl am Schluß" //: /line:"den Wert. Zum Beispiel bedeutet \"1b0\", dass es ein 1-Bit-Wert" //: /line:"in Binärdarstellung mit Wert \"0\" ist." //: /line:"" //: /line:"7) Drücke wieder die \"Simulations\"-Taste aus der Knopfleiste oder" //: /line:"wähle \"Run\" aus dem \"Simulieren\"-Menu. Das führt in den " //: /line:"kontinuierlichen Simulationsmodus. Versuche die " //: /line:"Schalterstellungen während der Simulation zu ändern. Nach jedem " //: /line:"Schalter-Stellungswechsel setzt sich die Simulation fort, bis die" //: /line:"Ausgänge stabil sind. Der \"Pause\"-Knopf läßt den Simulator in den" //: /line:"Einzelschrittmodus zurückkehren." //: /line:"" //: /line:"8) Zur Beendigung der Simulation drückt man den \"Stop\"-Knopf auf der" //: /line:"Knopfleiste oder wählt \"Ende der Simulation\" aus dem \"Simulieren\"-" //: /line:"Menu aus." //: /end nand g2 (.I0(w4), .I1(w5), .Z(w6)); //: @(668,326) /sn:0 /w:[ 9 7 1 ] //: switch g1 (w5) @(554,288) /sn:0 /w:[ 0 ] /st:0 //: joint g11 (w1) @(704, 263) /w:[ 1 -1 2 4 ] //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end led g28 (.I(w4)); //: @(586,220) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (w3) @(709, 258) /w:[ 6 5 -1 8 ] //: joint g27 (w3) @(709, 225) /w:[ -1 2 1 4 ] //: joint g6 (w5) @(609, 288) /w:[ -1 4 3 6 ] nand g9 (.I0(w1), .I1(w3), .Z(w0)); //: @(707,295) /sn:0 /R:3 /w:[ 5 9 1 ] xor g7 (.I0(w3), .I1(w1), .Z(S)); //: @(760,261) /sn:0 /w:[ 7 0 0 ] //: joint g31 (w4) @(586, 240) /w:[ 3 4 6 -1 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" led g29 (.I(w5)); //: @(587,269) /sn:0 /w:[ 9 ] /type:0 led g25 (.I(C)); //: @(798,305) /sn:0 /w:[ 0 ] /type:0 //: comment g17 /dolink:0 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: joint g5 (w4) @(618, 260) /w:[ 1 2 -1 8 ] //: comment g14 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end //: comment g21 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: comment g24 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end //: comment g23 /dolink:0 /link:"" @(605,130) /sn:0 /anc:1 //: /line:"->" //: /end led g26 (.I(w3)); //: @(709,207) /sn:0 /w:[ 3 ] /type:0 //: switch g0 (w4) @(554,240) /sn:0 /w:[ 7 ] /st:1 //: comment g22 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end led g18 (.I(S)); //: @(795,244) /sn:0 /w:[ 1 ] /type:0 //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"Dieses Tutorium führt in die Grundlagen der Simulation von Schaltnetzen ein." //: /end //: joint g30 (w5) @(587, 288) /w:[ 2 8 1 -1 ] endmodule tkgate-2.0-b10/locale/de/tutorials.18/create_tut.v000644 001751 001751 00000011067 07703341036 022450 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(232,502)(177,502){1} //: {2}(175,500)(175,466)(187,466){3} //: {4}(173,502)(141,502){5} wire w7; //: /sn:0 {0}(253,500)(263,500){1} wire w2; //: /sn:0 {0}(187,461)(141,461){1} wire w5; //: /sn:0 {0}(232,497)(218,497)(218,464)(208,464){1} //: enddecls or g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(243,500) /sn:0 /anc:1 /w:[ 0 0 0 ] //: comment g8 /dolink:0 /link:"" @(250,481) /anc:1 //: /line:"OR-Gatter" //: /end //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(630,100) /sn:0 /anc:1 //: /line:"Leitungen editeren" //: /end //: frame g13 @(410,406) /sn:0 /wi:381 /ht:177 /tx:"Erzeuge die Schaltung hier" and g3 (.I0(w2), .I1(w6), .Z(w5)); //: @(198,464) /sn:0 /anc:1 /w:[ 0 3 1 ] //: switch g2 (w6) @(124,502) /sn:0 /anc:1 /w:[ 5 ] /st:0 //: switch g1 (w2) @(124,461) /sn:0 /anc:1 /w:[ 1 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(630,115) /sn:0 /anc:1 //: /line:"Module benutzen" //: /end //: comment g10 /dolink:0 /link:"" @(12,236) /anc:1 //: /line:"5) Erzeuge zwei Schalter auf gleichem Wege wie die AND und OR-Gatter durch" //: /line:"Setzen einer Position und Auswahl von \"Schalter\" aus dem \"I/O\"-Submenu des" //: /line:"\"Make\"-Menu oder mit dem Tastaturkürzel \"s\"." //: /line:"" //: /line:"4) wiederhole Schritt 4, um den Ausgang des oberen Schalters mit dem oberen" //: /line:"Eingang des AND-Gatters zu verbinden." //: /line:"" //: /line:"7) Wiederhole Schritt 4, um den Ausgang des unteren Schalters mit dem unteren" //: /line:"Eingang des OR-Gatters zu verbinden." //: /line:"" //: /line:"8) Klicke und halte den unteren Eingang des AND-Gatters, um den Lötkolben" //: /line:"anzuwärmen. Ziehe ihn hinunter auf die Mitte des Drahtes, der den unteren " //: /line:"Schalter mit dem OR-Gatter verbindet und lasse die Maustaste los. Es wird" //: /line:"automatisch ein Klecks Lötzinn erzeugt." //: /end //: comment g6 /dolink:0 /link:"" @(101,427) /anc:1 //: /line:"Schalter" //: /end //: comment g7 /dolink:0 /link:"" @(193,441) /anc:1 //: /line:"AND-Gatter" //: /end //: comment g9 /dolink:0 /link:"" @(11,4) //: /line:"1) In diesem Beispiel wird die unten gezeigte Schaltung konstruiert." //: /line:"Baue die Schaltung im umrahmten Feld rechts unten auf. Beginne mit dem Setzen" //: /line:"der Position eines \"AND\"-Gatters durch Klicken mit der rechten Maustaste. Es" //: /line:"erscheint ein \"X\" Symbol zur Markierung der Position." //: /line:"" //: /line:"2) Wähle \"AND\" aus dem \"Gatter\"-Submenu nach dem Aufklappen" //: /line:"des \"Make\"-Menus mit der rechten Maustaste (oder über die" //: /line:"Menuleiste). Damit wird ein AND-Gatter an der ausgewählten Stelle erzeugt." //: /line:"Alternativ (und schneller) geht es mit dem Tastenkürzel \"a\"." //: /line:"" //: /line:"3) Wiederhole diese Aktion, diesmal mit Auswahl eines OR-Gatters. Setze es " //: /line:"rechts unterhalb der Position des AND-Gatters. Erzeuge das OR-Gatter durch" //: /line:"Anwahl von \"OR\" aus dem \"Gatter\"-Submenu des \"Make\"-Menus oder durch Tippen" //: /line:"von \"o\"." //: /line:"" //: /line:"4) Verbinde die obere Eingangsleitung des \"OR\"-Gatters mit dem Ausgang" //: /line:"des AND-Gatters durch Klicken und Halten des freien Endes des AND-Gatters mit" //: /line:"der linken Maustaste. Das ändert den Mauszeiger in einen Lötkolben." //: /line:"Nun ziehe den Draht in die Nähe der oberen Eingangsleitung des OR-Gatters und" //: /line:"löse die Maustaste. Die Leitungen verbinden sich selbsttätig." //: /end //: comment g20 /dolink:0 /link:"@T/create_tut.v" @(630,55) /sn:0 /anc:1 //: /line:"Erzeugen einer Schaltung" //: /end //: frame g15 @(600,25) /sn:0 /anc:1 /wi:213 /ht:149 /tx:"Tutorien" //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: joint g5 (w6) @(175, 502) /anc:1 /w:[ 1 2 4 -1 ] //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end //: comment g0 /dolink:1 /link:"@T/edit1_tut.v" @(630,70) /sn:0 /anc:1 //: /line:"Grundlegende Editier-Modi" //: /end //: comment g22 /dolink:0 /link:"" @(605,55) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end endmodule tkgate-2.0-b10/locale/de/tutorials.18/welcome_tut.v000644 001751 001751 00000036066 10015430352 022634 0ustar00hansenhansen000000 000000 //: version "1.6i" //: property discardChanges = 1 module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>B[7:0](67/89) Ti1>A[7:0](20/89) Li0>F[1:0](28/65) Bo0AIN[7:0](46/94) Li0>ck(56/80) Li1>SB[1:0](34/80) Li2>SA[1:0](14/80) Bo00 Ti1>0 Li0>1 Bo0<1 ] REGS regs (.AIN(w17), .ck(ck), .SB(w23), .SA(w21), .BOUT(w15), .AOUT(w6)); //: @(679, 457) /sz:(94, 80) /p:[ Ti0>0 Li0>1 Li1>0 Li2>1 Bo0<3 Bo1<3 ] //: supply0 g43 (w11) @(500,428) /sn:0 /w:[ 0 ] //: dip func (w26) @(599,356) /R:1 /w:[ 0 ] /st:0 led g48 (.I(reg_out)); //: @(472,576) /sn:0 /R:2 /w:[ 5 ] /type:1 led g62 (.I(w6)); //: @(773,245) /sn:0 /w:[ 5 ] /type:2 //: joint g29 (a) @(101, 490) /w:[ 2 -1 1 4 ] //: switch g25 (a) @(40,490) /sn:0 /w:[ 0 ] /st:0 //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(630,130) /sn:0 /anc:1 //: /line:"Schaltnetzsimulation" //: /end //: dip g42 (w14) @(444,349) /sn:0 /w:[ 1 ] /st:248 led g52 (.I(s)); //: @(225,520) /sn:0 /R:2 /w:[ 1 ] /type:0 //: dip data_in (w25) @(620,233) /R:1 /w:[ 0 ] /st:11 //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(630,145) /sn:0 /anc:1 //: /line:"Schaltwerkssimulation" //: /end led g56 (.I(w13)); //: @(290,408) /sn:0 /w:[ 5 ] /type:0 pmos g5 (.Z(w5), .S0(w13), .G0(w1)); //: @(245,401) /sn:0 /w:[ 1 9 3 ] //: comment g47 /dolink:0 /link:"" @(300,308) /sn:0 /anc:1 //: /line:"klicken." //: /end //: switch g44 (w19) @(348,457) /sn:0 /w:[ 1 ] /st:1 add g36 (.A(w14), .B(reg_out), .S(w16), .CI(w11), .CO(w18)); //: @(460,402) /sn:0 /w:[ 0 3 1 1 0 ] xor g24 (.I0(w8), .I1(ci), .Z(s)); //: @(197,496) /sn:0 /w:[ 0 3 0 ] /eb:0 //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(630,85) /sn:0 /anc:1 //: /line:"Editieren von Gruppen" //: /end //: supply0 g41 (w9) @(391,428) /sn:0 /w:[ 0 ] xor g23 (.I0(a), .I1(b), .Z(w8)); //: @(122,493) /sn:0 /w:[ 3 3 3 ] /eb:0 //: joint g60 (w15) @(773, 335) /w:[ 2 4 1 -1 ] led g54 (.I(w1)); //: @(189,385) /sn:0 /w:[ 5 ] /type:0 mux g40 (.I0(w9), .I1(w16), .S(w19), .Z(w20)); //: @(425,457) /sn:0 /w:[ 1 0 0 0 ] //: comment g46 /dolink:1 /link:"@T/create_tut.v" @(110,308) /sn:0 /anc:1 //: /line:"\"Erzeugen einer Schaltung\"" //: /end //: comment g45 /dolink:0 /link:"" @(17,308) /sn:0 /anc:1 //: /line:"Zum Start auf " //: /end register g35 (.Q(reg_out), .D(w20), .EN(w12), .CLR(w10), .CK(clk)); //: @(425,503) /sn:0 /w:[ 0 1 1 0 1 ] //: switch g26 (b) @(40,525) /sn:0 /w:[ 0 ] /st:1 //: comment g0 /dolink:0 /link:"" @(19,4) //: /line:"Willkommen in TkGate V1.8.3!" //: /line:"" //: /line:"Copyright (C) 1987-2004 by Jeffery P. Hansen" //: /line:"TkGate kommt OHNE JEGLICHE GARANTIE-Zusage; Details zur Lizenz und zum" //: /line:"Garantieausschluß findet man unter 'Help...License'. Probleme bitte an" //: /line:"hansen@cmu.edu weiterleiten." //: /line:"" //: /line:" * Dieses Tutorial erscheint automatisch beim ersten Start von TkGate." //: /line:" Man kann es ausblenden: Unter dem Menupunkt \"Optionen...\" des " //: /line:" \"Datei\"-Menus den Anfängermodus ausschalten." //: /line:"" //: /line:" * Eine von Grund auf neue Schaltung kann man mit \"Neu\" (\"Datei\"-Menu)" //: /line:" erzeugen. Oder man lädt eine vorhandene Schaltung aus einer Datei " //: /line:" mit \"Öffnen\" aus dem \"Datei\"-Menu." //: /line:" * Die vollständige Dokumentation zu TKGate findet man unter" //: /line:" http://www.tkgate.org" //: /line:"" //: /line:"Es folgt ein kurzes Tutorium zur Benutzung von TkGate. Zur schnellen " //: /line:"Navigation durch die Abschnitte gibt es Links in der rechten oberen Ecke." //: /line:"Alternativ dazu kann man sie auch im \"Hilfe\"-Menu auswählen." //: /line:"" //: /line:"In jedem Abschnitt sollte man die Schritte in der numerierten Reihenfolge" //: /line:"nachvollziehen. Nach Beendigung aller Tutorienteile kann man noch eine" //: /line:"Reihe von Beispielschaltungen aus dem \"Hilfe\"-Menu bearbeiten." //: /end //: comment g22 /dolink:0 /link:"" @(605,40) /sn:0 /anc:1 //: /line:"->" //: /end //: switch data_select (w28) @(620,293) /w:[ 0 ] /st:0 //: switch g12 (w1) @(134,401) /sn:0 /w:[ 0 ] /st:0 //: comment g18 /dolink:0 /link:"@T/welcome_tut.v" @(630,40) /sn:0 /anc:1 //: /line:"TkGate Einführung" //: /end //: joint g33 (ci) @(161, 498) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(95, 525) /w:[ -1 2 1 4 ] //: joint g49 (reg_out) @(472, 550) /w:[ 2 -1 1 4 ] endmodule tkgate-2.0-b10/locale/de/tutorials/sequential5.v000644 001751 001751 00000010003 11137635335 022312 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:199,201)(199,227){1} supply0 w3; //: /sn:0 {0}(252,251)(252,241)(239,241){1} supply0 w0; //: /sn:0 {0}(254,296)(274,296)(274,307){1} reg clr; //: {0}(32:254,286)(285,286){1} wire [7:0] w2; //: /sn:0 {0}(#:215,281)(215,256){1} wire ck; //: {0}(50:178,291)(113,291){1} wire [7:0] reg_out; //: {0}(#:215,302)(215,328)(273,328){1} //: {2}(277,328)(333,328)(52:333,215)(231,215)(231,227){3} //: {4}(275,330)(275,338){5} wire w9; //: /sn:0 {0}(191,241)(181,241){1} //: enddecls //: joint g8 (reg_out) @(275, 328) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(274,313) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) //: /line:"

Simulation von Schaltwerken

(Skripte)" //: /line:"" //: /line:"Neben interaktiver Simulatorsteuerung können auch Simulatorskripte geschrieben werden." //: /line:"Simulator-Skriptdateien haben die Endung \".vs\" und werden in Verilog-Syntax geschrieben." //: /line:"Drücke bei aktivem Simulator , um die Skriptdatei in den Simulator zu laden." //: /line:"Man kann eine Skriptdatei benutzen, um Tastköpfe zu setzen und zu löschen, die Simulationszeit vorrücken zu lassen," //: /line:"Signalwerte zu setzen und Meldungen im TkGate log () Fenster anzuzeigen. Details" //: /line:"zum Schreiben von Simulatorskipten sehe man in der TkGate 2.0 Dokumentation nach." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(clr), .CK(ck)); //: @(215,291) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(495,118) /sn:0 /R:14 /anc:1 //: /line:"Simulator Skript Beispiel:" //: /line:"" //: /line:"initial" //: /line:" begin" //: /line:" $display(\"%t: Start des Skripts\",$time);" //: /line:" $tkg$probe(ck, reg_out, clr);" //: /line:" $display(\"%t: Tastkoepfe setzen\",$time);" //: /line:" clr = 1'b0;" //: /line:" #200;" //: /line:" clr = 1'b1;" //: /line:" $display(\"%t: Ende mit Reset\",$time);" //: /line:" #500;" //: /line:" $stop();" //: /line:" end" //: /line:"" //: /end //: DIP g6 (w7) @(199,191) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(252,257) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(275,345) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(215,243) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(100,291) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (clr) @(303,286) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/modules.v000644 001751 001751 00000050331 11137600625 021525 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "module_tut.v" //: property discardChanges = 1 //: property encoding= "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g3 @(259,83) /anc:1 //: /line:"Ein Modul ist ein gekapselte Stück Schaltungslogik, das in einer" //: /line:"größeren Schaltung eine bestimmte Aufgabe erfüllt, ganz ähnlich" //: /line:"wie ein Modul oder eine Klasse in einem Programm." //: /line:"Jedes Modul in TkGate hat eine \"Schnittstelle\" und" //: /line:"eine \"Definition\":" //: /line:"" //: /line:" * Die Schnittstelle beschreibt die äußere Erscheinung" //: /line:" eines Moduls einschließlich der Größe der Box und der" //: /line:" Positionen der Ports auf ihr. TkGate unterstützt \"block\"" //: /line:" Schnittstellen und \"symbolische\" Schnittstellen." //: /line:" " //: /line:" * Die Definition beschreibt die interne, durch das Modul" //: /line:" implementierte Logik. TkGate unterstützt \"Netzlisten\"" //: /line:" und \"HDL\" Module." //: /line:"" //: /end //: comment g2 @(10,65) /sn:0 /anc:1 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

" //: /line:"" //: /line:"In diesem Abschnitt wird gezeigt, wie man Module erzeugt, editiert und verwaltet." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(258,177)(273,177){1} wire w0; //: /sn:0 {0}(200,161)(185,161){1} wire w3; //: /sn:0 {0}(258,161)(273,161){1} wire w1; //: /sn:0 {0}(200,177)(185,177){1} wire w2; //: /sn:0 {0}(200,192)(185,192){1} wire w5; //: /sn:0 {0}(258,193)(273,193){1} //: enddecls bar g4 (.C(w2), .B(w1), .A(w0), .Z(w5), .Y(w4), .X(w3)); //: @(201, 145) /sz:(56, 72) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Ro0<0 Ro1<0 Ro2<0 ] //: comment g3 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Editieren von Moduldefinitionen)" //: /line:"" //: /line:"Ein Doppelklick auf den Namen eines selbsterzeugten Moduls in der Modulbaum- oder Modullistenansicht" //: /line:"ermöglicht das Editieren der Moduldefinition. Alternativ dazu kann man auch auf eine Modulinstanz rechtsklicken" //: /line:"und Öffnen aus dem Popup Menu wählen." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g4 @(576,89) /sn:0 /anc:1 //: /line:"Hinweis: Die Seiten dieses Tutoriums" //: /line:"sind in Wirklichkeit Module mit den" //: /line:"Namen PAGE1, PAGE2, etc." //: /end //: comment g3 @(23,72) /sn:0 /anc:1 //: /line:" Oberstes oder Wurzelmodul." //: /line:"" //: /line:" Netzlistenmodul." //: /line:"" //: /line:" Verilog HDL Modul." //: /line:"" //: /line:" Verriegeltes Netzlistenmodul." //: /line:"" //: /line:" Verriegeltes Verilog HDL Modul." //: /line:"" //: /line:" Behälter für unbenutzte Module." //: /line:"" //: /end //: comment g2 @(257,69) /anc:1 //: /line:" Bibliotheksmodul." //: /line:"" //: /line:" Behälter für alle Bibliotheken." //: /line:"" //: /line:" Behälter für eine einzige Bibliothek." //: /line:"" //: /line:" Benutzung eines undefinierten Moduls." //: /line:"" //: /line:" Rekursive Einbindung eines Moduls." //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Modullistensymbole)" //: /line:"" //: /line:"Folgende Symbole werden in der Baum- oder Listenansicht der Module verwendet:" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(40, 40) /bd:[ ] input [7:0] B; //: /sn:0 {0}(#:342,147)(342,184){1} //: {2}(344,186)(367,186){3} //: {4}(371,186)(425,186)(425,258){5} //: {6}(369,188)(369,261){7} //: {8}(342,188)(342,258){9} input [1:0] F; //: /sn:0 {0}(#:343,353)(214,353){1} input [7:0] A; //: /sn:0 {0}(#:265,147)(265,215){1} //: {2}(267,217)(345,217){3} //: {4}(349,217)(372,217){5} //: {6}(376,217)(457,217)(457,258){7} //: {8}(374,219)(374,261){9} //: {10}(347,219)(347,258){11} //: {12}(265,219)(265,322)(348,322)(348,337){13} supply0 w0; //: /sn:0 {0}(491,295)(491,272)(465,272){1} output [7:0] Z; //: /sn:0 {0}(#:366,404)(366,366){1} wire [7:0] w14; //: /sn:0 {0}(#:345,279)(345,310)(360,310)(360,337){1} wire w4; //: /sn:0 {0}(417,272)(407,272){1} wire [7:0] w11; //: /sn:0 {0}(#:372,282)(372,337){1} wire [7:0] w10; //: /sn:0 {0}(#:384,337)(384,307)(441,307)(441,287){1} //: enddecls //: joint g8 (A) @(347, 217) /w:[ 4 -1 3 10 ] _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4)); //: @(441,274) /sn:0 /w:[ 5 7 1 1 0 ] //: GROUND g13 (w0) @(491,301) /sn:0 /w:[ 0 ] //: IN g3 (F) @(212,353) /sn:0 /w:[ 1 ] //: IN g2 (A) @(265,145) /sn:0 /R:3 /w:[ 0 ] //: IN g1 (B) @(342,145) /sn:0 /R:3 /w:[ 0 ] //: joint g11 (B) @(369, 186) /w:[ 4 -1 3 6 ] //: joint g10 (A) @(374, 217) /w:[ 6 -1 5 8 ] _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11)); //: @(372,272) /sn:0 /R:3 /w:[ 7 9 0 ] /eb:0 //: joint g9 (A) @(265, 217) /w:[ 2 1 -1 12 ] _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14)); //: @(345,269) /sn:0 /R:3 /w:[ 9 11 0 ] /eb:0 //: OUT g5 (Z) @(366,401) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z)); //: @(366,353) /sn:0 /w:[ 13 1 1 0 0 1 ] /ss:0 /do:0 //: joint g12 (B) @(342, 186) /w:[ 2 1 -1 8 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(Z2, I3, Z1, I1, I2, Z3); //: interface /sz:(41, 40) /bd:[ ] input I2; //: /sn:0 {0}(245,200)(275,200){1} //: {2}(277,198)(277,153)(292,153){3} //: {4}(277,202)(277,248)(348,248){5} output Z3; //: /sn:0 {0}(369,251)(448,251){1} input I1; //: /sn:0 {0}(292,148)(278,148)(278,128)(246,128){1} output Z2; //: /sn:0 {0}(392,156)(380,156)(380,184){1} //: {2}(382,186)(448,186){3} //: {4}(378,186)(369,186){5} output Z1; //: /sn:0 {0}(448,154)(413,154){1} input I3; //: /sn:0 {0}(348,188)(296,188)(296,251){1} //: {2}(298,253)(348,253){3} //: {4}(294,253)(245,253){5} wire w0; //: /sn:0 {0}(348,183)(338,183)(338,153){1} //: {2}(340,151)(392,151){3} //: {4}(336,151)(313,151){5} //: enddecls //: OUT g4 (Z2) @(445,186) /sn:0 /w:[ 3 ] _GGAND2 #(6) g8 (.I0(I2), .I1(I3), .Z(Z3)); //: @(359,251) /sn:0 /w:[ 5 3 0 ] /eb:0 //: joint g13 (w0) @(338, 151) /w:[ 2 -1 4 1 ] //: IN g2 (I3) @(243,253) /sn:0 /w:[ 5 ] //: OUT g1 (Z1) @(445,154) /sn:0 /w:[ 0 ] _GGAND2 #(6) g11 (.I0(w0), .I1(Z2), .Z(Z1)); //: @(403,154) /sn:0 /w:[ 3 0 1 ] /eb:0 //: comment g16 @(585,127) /sn:0 //: /line:"Hinweis: Wurde das Modul durch Auswahl" //: /line:"von Öffnen aus dem Menu oder der" //: /line:"Toolbar geöffnet, kann es durch Rechtsklick" //: /line:"in die Planfläche mit Auswahl von" //: /line:"Schließen wieder geschlossen werden." //: /end //: joint g10 (I2) @(277, 200) /w:[ -1 2 1 4 ] //: IN g19 (I1) @(244,128) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g6 (.I0(I1), .I1(I2), .Z(w0)); //: @(303,151) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(I3), .Z(Z2)); //: @(359,186) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (I3) @(296, 253) /w:[ 2 1 4 -1 ] //: comment g15 @(22,25) //: /line:"Dies ist die Definition des Moduls \"foo\"." //: /end //: IN g5 (I2) @(243,200) /sn:0 /w:[ 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨Zurück zum Tutorium⟩" //: /end //: joint g23 (Z2) @(380, 186) /w:[ 2 1 4 -1 ] //: OUT g12 (Z3) @(445,251) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(500,160) /sn:0 /anc:1 //: /line:"Hinweis: Falls die Änderung einer Modulschnittstelle" //: /line:"nicht gelingt, klicke rechts auf sie und" //: /line:"wähle Moduleigenschaften... und setze" //: /line:"dann die Schutzeigenschaften der Schnittstelle" //: /line:"in der aufkommenden Dialogbox." //: /end foo g2 (); //: @(208, 163) /sz:(40, 40) /sn:0 /p:[ ] //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Schnittstellenerzeugung von Hand)" //: /line:"" //: /line:"Die Schnittstelle eines Moduls kann auch von Hand erzeugt und editiert werden:" //: /line:" * Mit Linksklick auf eine Kante oder Ecke und Ziehen wird die Größe der Schnittstelle verändert." //: /line:" * Mit einem Rechtsklick auf eine Kante kann der zu erzeugende Porttyp aus dem Popup Menu gewählt werden." //: /line:" * Um einen Port wieder zu löschen, wählt man das Werkzeug und schneidet die Leitung am Modul ab." //: /line:" * Mit einem Doppelklick auf einem Port mit dem Werkzeug können die Porteigenschaften editiert werden." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire [7:0] w3; //: /sn:0 {0}(#:329,194)(314,194){1} wire [1:0] w0; //: /sn:0 {0}(#:257,226)(272,226){1} wire [7:0] w1; //: /sn:0 {0}(#:257,210)(272,210){1} wire [7:0] w2; //: /sn:0 {0}(#:257,194)(272,194){1} //: enddecls ALU g3 (.A(w2), .B(w1), .F(w0), .Z(w3)); //: @(273, 178) /sz:(40, 64) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Ro0<1 ] //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Standardschnittstellen aktualisieren)" //: /line:"" //: /line:"Modulschnittstellen, die im Edit Modus erzeugt wurden, gehören nur zur speziellen Instanz, aus der sie geschaffen wurden." //: /line:"Um eine Schnittstelle zur Standardschnittstelle für neu erzeugte Modulinstanzen dieses Typs zu machen, klickt man mit rechts" //: /line:"auf eine Schnittstelle und wählt Schnittstelle → Setzen. Versuche die Schnittstellen von jeder der beiden Instanzen" //: /line:"der ALU Module unten zu setzen. Versuche dann, neue ALU Module durch Ziehen aus der Modulliste zu erzeugen." //: /end ALU g0 (); //: @(130, 184) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Automatische Schnittstellenerzeugung)" //: /line:"" //: /line:"Die Schnittstelle eines Moduls enthält Größe und Form der Box und Ort und Namen der Ports:" //: /line:"Am einfachsten ist es, die Schnittstelle automatisch generieren zu lassen. Automatische" //: /line:"Erzeugung nutzt die in der Definition festgelegten Ports zur Generierung der Schnittstelle." //: /line:"Klicke auf den Modullisten-Tab , um automatisch eine Schnittstelle für das \"bar\" Modul" //: /line:"zu erzeugen. Klicke mit rechts auf \"bar\" und wähle Schnittstelle→ Automatisch erzeugen...." //: /line:"Dann ziehe mit einem Linksklick das \"bar\" Modul auf die Planfläche, um die neue Schnittstelle" //: /line:"zu sehen." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Moduldefinitionen erzeugen)" //: /line:"" //: /line:"Zum Erzeugen eines neuen Moduls drückt man den Knopf. Gib den Namen für das neue Modul ein" //: /line:"und wähle, ob es ein graphisches Netzlistenmodul oder ein textuelles HDL Modul werden soll." //: /line:"Versuche, ein neues Modul namens \"CPU\" zu erzeugen." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(545,102) /sn:0 /anc:1 //: /line:"Hinweis: Man kann auch eine Modulinstanz" //: /line:"aus der Baumansicht ziehen und plazieren," //: /line:"es ist aber leichter mit der Listenansicht," //: /line:"weil es da eine alphabetische Sicht" //: /line:"auf alle Module gibt." //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Modulinstanzen erzeugen)" //: /line:"" //: /line:"Am leichtesten läßt sich eine Modulinstanz erzeugen, wenn man den Modulnamen in der Modulliste findet" //: /line:"und ihn in die aktuelle Schaltung hineinzieht. Versuche, durch Umschalten mit auf die Listenansicht" //: /line:"einzustellen und ziehe mehere Instanzen des \"bar\" Moduls ins aktuelle Editierfenster." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(620,6) /sn:0 /anc:1 //: /line:"" //: /end //: comment g2 @(620,346) /sn:0 /anc:1 //: /line:"Beispiel einer Modulbaumansicht" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Module benutzen

(Modulliste)" //: /line:"" //: /line:"Die Menge der zur aktuellen Schaltung gehörenden Module wird auf der linken Seite der " //: /line:"Schnittstelle gezeigt. Man kann zwischen einer Baumansicht (siehe Beispiel) und einer" //: /line:"Listenansicht entscheiden. Die Baumansicht zeigt die Modulhierarchie, beginnend mit" //: /line:"einem obersten Wurzelmodul, das durch symbolisiert wird. Module, die noch zur Schaltung" //: /line:"gehören, aber nirgends mehr in der Hierarchie benutzt werden, sind im \" Unbenutzten\"" //: /line:"Zweig gelistet. Klicke auf , um einen Zweig im Baum zu öffnen." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(11,22) /anc:1 //: /line:"

Module benutzen

(Schnittstelleneditor)" //: /line:"" //: /line:"Die Modulschnittstelle kann direkt mit TkGate's Schnittstellenmodus editiert werden. Klicke auf das Schnittstellen Tab" //: /line:"über dem dem Haupteditierfeld, um in diesen Modus zu gelangen. Details zu Benutzung dieses Modus stehen in der" //: /line:"TkGate Dokumentation. Klicke auf den Edit Tab, um zum normalen Editiermodus zurückzukehren." //: /end endmodule //: /netlistEnd //: /netlistBegin bar module bar(Y, X, C, B, Z, A); //: interface /sz:(56, 72) /bd:[ Li0>C(48/72) Li1>B(32/72) Li2>A(16/72) Ro0Hinweis: Falls dieses Modul durch Anwahl von" //: /line:"Öffnen aus Menu oder" //: /line:"Toolbar geöffnet wurde, kann es durch einen Rechtsklick" //: /line:"in das Editierfeld und die Anwahl von" //: /line:"Schließen geschlossen werden." //: /end _GGAND2 #(6) g11 (.I0(w0), .I1(Y), .Z(X)); //: @(244,161) /sn:0 /w:[ 3 0 5 ] /eb:0 //: joint g10 (B) @(118, 207) /w:[ -1 2 1 4 ] //: joint g19 (C) @(162, 260) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g6 (.I0(A), .I1(B), .Z(w0)); //: @(144,158) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(C), .Z(Y)); //: @(200,193) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (C) @(137, 260) /w:[ 2 1 8 -1 ] //: comment g15 @(22,25) //: /line:"Dies ist die Definiton für das Modul \"bar\". Ports A, B und C sind Eingänge und Ports X, Y und Z sind" //: /line:"Ausgänge. Versuche, einen zusätzlichen Ausgangsport \"W\" aus dem Ausgang des XOR Gatters unten zu erzeugen." //: /line:"Durch Rechtsklick an der Position, wo der Port erzeugt werden soll, und Anwahl von Bausteine → Module → Modulausgang" //: /line:"aus dem Popup Menu. Gib als Netznamen \"W\" in die Dialog box ein." //: /line:"" //: /line:"" //: /end _GGXOR2 #(8) g17 (.I0(C), .I1(X), .Z(w3)); //: @(293,129) /sn:0 /w:[ 7 3 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: OUT g5 (Z) @(343,258) /sn:0 /w:[ 1 ] //: IN g0 (A) @(84,135) /sn:0 /w:[ 1 ] //: joint g12 (Y) @(221, 193) /w:[ 2 1 4 -1 ] //: joint g18 (X) @(266, 161) /w:[ 1 2 4 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always @(*) begin case (S) 2'h0: Z <= #Dsz I0; 2'h1: Z <= #Dsz I1; 2'h2: Z <= #Dsz I2; 2'h3: Z <= #Dsz I3; default: Z <= #Dsz 2'h0; endcase end endmodule //: /builtinEnd //: /builtinBegin module _GGOR2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/verilog.v000644 001751 001751 00000006542 11137644110 021526 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "texver_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textuelle Beschreibung mit Verilog

" //: /line:"" //: /line:"Der TkGate Simulator basiert auf der Hardwarebeschreibungssprache Verilog. Jedes Modul, das" //: /line:"mit dem graphischen Editor entworfen wird, wird vor der Simulation in Verilog-Programmtext übersetzt." //: /line:"Man kann Module auch direkt in Verilog schreiben. Allerdings kann dieser Abschnitt nicht dazu dienen," //: /line:"die Sprache Verilog zu lehren. Vielmehr soll erläutert werden, wie man Verilog-Module in TkGate einbindet." //: /end //: comment g0 @(145,107) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(55, 80) /bd:[ Li0>d(64/80) Li1>c(48/80) Li2>b(32/80) Li3>a(16/80) Ro0 und setze den Typ auf HDL." //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textbasiertes Verilog

" //: /line:"" //: /line:"1) Klicke rechts auf das Modul unten und wähle Öffnen." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g5 (w4) @(246,131) /sn:0 /w:[ 1 ] /type:0 foo g0 (.a(w5), .b(w6), .c(w7), .d(w8), .z(w4)); //: @(164, 113) /sz:(55, 80) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>1 Ro0<0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/group.v000644 001751 001751 00000025734 11137600514 021217 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(140,67) /sn:0 /anc:1 //: /line:"" //: /end //: comment g5 @(10,10) /anc:1 //: /line:"

Editieren von Bausteingruppen

" //: /line:"" //: /line:"In diesem Abschnitt lernen wir, wie Gruppen von Gattern gemeinsam editiert werden können." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:183,147)(289,147)(289,189){1} //: {2}(291,191)(314,191){3} //: {4}(289,193)(289,210){5} reg a0; //: {0}(40:183,183)(227,183){1} //: {2}(231,183)(239,183){3} //: {4}(229,185)(229,239)(246,239){5} reg b0; //: {0}(50:183,218)(221,218){1} //: {2}(223,216)(223,188)(239,188){3} //: {4}(223,220)(223,244)(246,244){5} wire w7; //: /sn:0 {0}(267,242)(282,242)(282,254){1} wire s0; //: {0}(36:335,189)(365,189){1} wire w4; //: /sn:0 {0}(287,231)(287,254){1} wire c1; //: {0}(99:285,275)(285,294){1} wire w9; //: /sn:0 {0}(314,186)(286,186){1} //: {2}(282,186)(260,186){3} //: {4}(284,188)(284,210){5} //: enddecls //: LED g37 (s0) @(372,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(285,265) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(257,242) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(284, 186) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(166,147) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(287,221) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(229, 183) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(166,183) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Editieren von Bausteingruppen

(inkrementelle Auswahl)" //: /line:"" //: /line:"Es ist möglich, zur aktuellen Auswahl Gatter hinzuzufügen oder zu entfernen. Dazu hält man die Strg Taste gedrückt, während" //: /line:"auf das Gatter geklickt wird. Wähle mit der Auswahlbox die Gatter unten aus und klicke dann auf einige, während die Strg Taste" //: /line:"gedrückt bleibt. Gib die Strg Taste frei und versuche dann, die Auswahl mit nur einigen ausgewählten Gattern zu bewegen." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(325,189) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(250,186) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(166,218) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(289, 191) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(223, 218) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:167,153)(273,153)(273,195){1} //: {2}(275,197)(298,197){3} //: {4}(273,199)(273,216){5} reg a0; //: {0}(40:167,189)(189,189)(189,189)(211,189){1} //: {2}(215,189)(223,189){3} //: {4}(213,191)(213,245)(230,245){5} reg b0; //: {0}(50:167,224)(186,224)(186,224)(205,224){1} //: {2}(207,222)(207,194)(223,194){3} //: {4}(207,226)(207,250)(230,250){5} wire w7; //: /sn:0 {0}(251,248)(266,248)(266,260){1} wire s0; //: {0}(36:319,195)(349,195){1} wire w4; //: /sn:0 {0}(271,237)(271,260){1} wire c1; //: {0}(99:269,281)(269,300){1} wire w9; //: /sn:0 {0}(298,192)(270,192){1} //: {2}(266,192)(244,192){3} //: {4}(268,194)(268,216){5} //: enddecls //: LED g37 (s0) @(356,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(570,113) /sn:0 /anc:1 //: /line:"Hinweis: Enthält eine Auswahl" //: /line:"irgendwelche verankerten Gatter, so" //: /line:"verhält sich die gesamte Auswahl," //: /line:"als wäre sie verankert." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(269,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(241,248) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(268, 192) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(150,153) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(271,227) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(213, 189) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(150,189) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Editieren von Bausteingruppen

(Drehen und Verankern)" //: /line:"" //: /line:"Eine Bausteingruppe kann (mit und ) gedreht und (mit und ) verankert werden, und das genauso, wie es im Abschnitt" //: /line:"Gatter editieren für einzelne Gatter geschah. Versuche es mit der Schaltung unten." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(309,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(234,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(150,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(273, 197) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(207, 224) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:182,149)(288,149)(288,191){1} //: {2}(290,193)(313,193){3} //: {4}(288,195)(288,212){5} reg a0; //: {0}(40:182,185)(226,185){1} //: {2}(230,185)(238,185){3} //: {4}(228,187)(228,241)(245,241){5} reg b0; //: {0}(50:182,220)(220,220){1} //: {2}(222,218)(222,190)(238,190){3} //: {4}(222,222)(222,246)(245,246){5} wire w7; //: /sn:0 {0}(266,244)(281,244)(281,256){1} wire s0; //: {0}(36:334,191)(364,191){1} wire w4; //: /sn:0 {0}(286,233)(286,256){1} wire c1; //: {0}(99:284,277)(284,296){1} wire w9; //: /sn:0 {0}(313,188)(285,188){1} //: {2}(281,188)(259,188){3} //: {4}(283,190)(283,212){5} //: enddecls //: LED g37 (s0) @(371,191) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(609,113) /sn:0 /anc:1 //: /line:"Hinweis: Klicke in eine Freifläche," //: /line:"wenn eine Gruppe wieder" //: /line:"deselektiert werden soll." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(284,267) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(256,244) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(283, 188) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(165,149) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(286,223) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(228, 185) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(165,185) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Editieren von Bausteingruppen

(Auswahl und Bewegung)" //: /line:"" //: /line:"Eine Gruppe von Gattern wird ausgewählt, indem die linke Maustaste links oberhalb der Gatter gedrückt und festgehalten wird und" //: /line:"dann der Mauszeiger diagonal nach rechts unten gezogen wird, um die Auswahlbox zu öffnen. Man gibt die Maus frei, wenn alle" //: /line:"gewünschten Gatter sich innerhalb der Box befinden. Jetzt kann die Gruppe an einem beliebigen Gatter angefaßt und bewegt werden." //: /line:"Versuche das bei der Schaltung unten." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(324,191) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(249,188) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(165,220) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(288, 193) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(222, 220) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:174,160)(280,160)(280,202){1} //: {2}(282,204)(305,204){3} //: {4}(280,206)(280,223){5} reg a0; //: {0}(40:174,196)(196,196)(196,196)(218,196){1} //: {2}(222,196)(230,196){3} //: {4}(220,198)(220,252)(237,252){5} reg b0; //: {0}(50:174,231)(193,231)(193,231)(212,231){1} //: {2}(214,229)(214,201)(230,201){3} //: {4}(214,233)(214,257)(237,257){5} wire w7; //: /sn:0 {0}(258,255)(273,255)(273,267){1} wire s0; //: {0}(36:326,202)(356,202){1} wire w4; //: /sn:0 {0}(278,244)(278,267){1} wire c1; //: {0}(99:276,288)(276,307){1} wire w9; //: /sn:0 {0}(305,199)(277,199){1} //: {2}(273,199)(251,199){3} //: {4}(275,201)(275,223){5} //: enddecls //: LED g37 (s0) @(363,202) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(548,117) /sn:0 /anc:1 //: /line:"Hinweis: Durch Drücken der Entf Taste" //: /line:"können alle ausgewählten Gatter gelöscht" //: /line:"werden, ohne sie in die Zwischenablage" //: /line:"zu kopieren." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(276,278) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(248,255) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(275, 199) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(157,160) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(278,234) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(220, 196) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(157,196) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Editieren von Bausteingruppen

(Zwischenablagefunktionen)" //: /line:"" //: /line:"Die Zwischenablage kann für das Ausschneiden oder Kopieren einer Gattergruppe genutzt werden, um sie nachher" //: /line:" woanders wieder einzufügen. Wähle eine Gruppe von Gattern aus klicke dann auf die oder Knöpfe, um sie " //: /line:"in die Zwischenablage auszuschneiden oder zu kopieren. Zum Einfügen des Inhalts der Zwischenablage setzt man" //: /line:"erst mit einem Linksklick ein , dann drückt man den Knopf und der Inhalt der Zwischenablage erscheint an dieser Stelle." //: /line:"" //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(316,202) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(241,199) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(157,231) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(280, 204) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(214, 231) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/sequential3.v000644 001751 001751 00000012135 11137635335 022320 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /symbolBegin: 680294000 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:232,193)(232,219){1} reg w4; //: /sn:0 {0}(287,278)(298,278)(298,266)(308,266){1} supply0 w3; //: /sn:0 {0}(285,243)(285,233)(272,233){1} supply0 w0; //: /sn:0 {0}(287,288)(310,288)(310,303){1} wire [7:0] w2; //: /sn:0 {0}(#:248,273)(248,248){1} wire ck; //: {0}(-39:130,283)(211,283){1} wire [7:0] reg_out; //: {0}(#:248,294)(248,327)(304,327){1} //: {2}(308,327)(364,327)(58:364,206)(264,206)(264,219){3} //: {4}(306,329)(306,342){5} wire w9; //: /sn:0 {0}(224,233)(214,233){1} //: enddecls //: joint g8 (reg_out) @(306, 327) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(310,309) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Simulation von Schaltwerken

(Kontinuierliche Simulation)" //: /line:"" //: /line:"Genau wie beim Schaltnetz kann auch hier der Knopf gedrückt werden, um aus der" //: /line:"Pause zurückzukehren und kontinuierlich zu simulieren. Versuche das mit der untenstehenden" //: /line:"Schaltung. Sie enthält einen \"Realzeit\"-Oszillator, der eine Periode pro Sekunde ausführt. Wie im" //: /line:"vorigen Beispiel ist das kurzzeitige Ausschalten des \"reset\" Schalters erforderlich." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(248,283) /sn:0 /w:[ 0 0 0 0 1 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end OSCILLATOR g10 (.Z(ck)); //: @(116, 283) /symbol:680294000 /sn:0 /w:[ 0 ] //: DIP g6 (w7) @(232,183) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(285,249) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(306,349) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(248,235) /sn:0 /w:[ 1 3 1 1 0 ] //: SWITCH reset (w4) @(326,266) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/combinational2.v000644 001751 001751 00000007161 11137616233 022763 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:153,316)(167,316){1} //: {2}(171,316)(189,316){3} //: {4}(193,316)(241,316){5} //: {6}(191,314)(191,253)(236,253){7} //: {8}(169,314)(169,304){9} reg A; //: {0}(236,248)(204,248){1} //: {2}(202,246)(-86:202,228)(172,228){3} //: {4}(170,226)(170,215){5} //: {6}(168,228)(155,228){7} //: {8}(202,250)(202,311)(241,311){9} reg Cin; //: {0}(271,213)(291,213){1} //: {2}(293,211)(293,202){3} //: {4}(41:293,215)(293,244){5} //: {6}(295,246)(333,246){7} //: {8}(293,248)(293,272){9} wire w6; //: /sn:0 {0}(334,314)(262,314){1} wire w0; //: /sn:0 {0}(334,309)(291,309)(291,293){1} wire w1; //: /sn:0 {0}(333,251)(290,251){1} //: {2}(286,251)(257,251){3} //: {4}(288,253)(288,272){5} wire C; //: {0}(-21:403,221)(403,312)(355,312){1} wire S; //: {0}(354,249)(-39:373,249)(373,221){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(345,312) /sn:0 /w:[ 0 0 1 ] _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(247,251) /sn:0 /w:[ 0 7 3 ] //: comment g13 @(10,10) /anc:1 //: /line:"

Simulation von Schaltnetzen

(Starten des Simulators)" //: /line:"" //: /line:"Drücke die \" Simulieren\" Taste oberhalb der Hauptarbeitsfläche, um in die Simulation zu gelangen. Beim ersten Eintritt in den" //: /line:"Simulationsmodus ist der Simulator im Pause-Zustand. Das wird durch den gedrückten Knopf in der Simulations-Toolbar angezeigt." //: /line:"Drücke den Knopf zum Start der Simulation. Versuche nun, durch Klicken auf die Schalter die Schalterzustände zu ändern und" //: /line:"beobachte, wie die LEDs sich ändern. Der Simulator wird durch Druck auf den Knopf gestoppt, wenn Du fertig bist." //: /line:"Gehe dann zur nächsten Seite." //: /end //: SWITCH g3 (Cin) @(254,213) /sn:0 /w:[ 0 ] /st:1 _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(252,314) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(136,316) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(288, 251) /w:[ 1 -1 2 4 ] //: LED g28 (A) @(170,208) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (Cin) @(293, 246) /w:[ 6 5 -1 8 ] //: joint g27 (Cin) @(293, 213) /w:[ -1 2 1 4 ] //: joint g6 (B) @(191, 316) /w:[ 4 6 3 -1 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(291,283) /sn:0 /R:3 /w:[ 5 9 1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(344,249) /sn:0 /w:[ 7 0 0 ] //: joint g31 (A) @(170, 228) /w:[ 3 4 6 -1 ] //: LED g29 (B) @(169,297) /sn:0 /w:[ 9 ] /type:0 //: LED g25 (C) @(403,214) /sn:0 /w:[ 0 ] /type:0 //: joint g5 (A) @(202, 248) /w:[ 1 2 -1 8 ] //: LED g26 (Cin) @(293,195) /sn:0 /w:[ 3 ] /type:0 //: SWITCH g0 (A) @(138,228) /sn:0 /w:[ 7 ] /st:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g18 (S) @(373,214) /sn:0 /w:[ 1 ] /type:0 //: joint g30 (B) @(169, 316) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/combinational3.v000644 001751 001751 00000010223 11137616233 022755 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:140,305)(154,305){1} //: {2}(158,305)(176,305){3} //: {4}(180,305)(228,305){5} //: {6}(178,303)(178,242)(223,242){7} //: {8}(156,303)(156,293){9} reg A; //: {0}(223,237)(191,237){1} //: {2}(189,235)(-86:189,217)(159,217){3} //: {4}(157,215)(157,204){5} //: {6}(155,217)(142,217){7} //: {8}(189,239)(189,300)(228,300){9} reg Cin; //: {0}(258,202)(278,202){1} //: {2}(280,200)(280,191){3} //: {4}(48:280,204)(280,233){5} //: {6}(282,235)(320,235){7} //: {8}(280,237)(280,261){9} wire w6; //: /sn:0 {0}(321,303)(249,303){1} wire w0; //: /sn:0 {0}(321,298)(278,298)(278,282){1} wire w1; //: /sn:0 {0}(320,240)(277,240){1} //: {2}(273,240)(244,240){3} //: {4}(275,242)(275,261){5} wire C; //: {0}(-21:390,210)(390,301)(342,301){1} wire S; //: {0}(341,238)(-39:360,238)(360,210){1} //: enddecls _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(234,240) /sn:0 /w:[ 0 7 3 ] _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(332,301) /sn:0 /w:[ 0 0 1 ] //: SWITCH g3 (Cin) @(241,202) /sn:0 /w:[ 0 ] /st:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Simulation von Schaltnetzen

(Setzen von Tastköpfen)" //: /line:"" //: /line:"Drücke erneut die \" Simulieren\" Taste zum Eintritt in den Simulationsmodus. Klicke diesmal auf eine Leitung, (z.B. die" //: /line:"mit \"S\" bezeichnete) und wähle \"Tastkopf hinzufügen/löschen\" aus dem Popup Menu. Damit wird ein Tastkopf" //: /line:"auf diese Leitung gesetzt und ein Logikanalysatorfenster öffnet sich. Setze auf einige andere Leitung ebenfalls Tastköpfe und löse den " //: /line:"Simulator durch Druck auf den Knopf aus dem Pause-Zustand. Klicke auf die Schalter, um ihre Zustände zu ändern und" //: /line:"beobachte, wie sich die Ausgabe im Logikanalysator ändert." //: /end _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(239,303) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(123,305) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(275, 240) /w:[ 1 -1 2 4 ] //: joint g10 (Cin) @(280, 235) /w:[ 6 5 -1 8 ] //: LED g28 (A) @(157,197) /sn:0 /w:[ 5 ] /type:0 //: joint g27 (Cin) @(280, 202) /w:[ -1 2 1 4 ] //: joint g6 (B) @(178, 305) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(331,238) /sn:0 /w:[ 7 0 0 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(278,272) /sn:0 /R:3 /w:[ 5 9 1 ] //: comment g15 @(545,254) /sn:0 /anc:1 //: /line:"Hinweis: Normalerweise simuliert TkGate" //: /line:"Schaltnetze, bis alle Signale einen stabilen" //: /line:"Zustand erreicht haben. Der Simulator" //: /line:"schreitet um eine Zeiteinheit fort, wenn die " //: /line:"Leertaste gedrückt wird." //: /end //: joint g31 (A) @(157, 217) /w:[ 3 4 6 -1 ] //: LED g25 (C) @(390,203) /sn:0 /w:[ 0 ] /type:0 //: LED g29 (B) @(156,286) /sn:0 /w:[ 9 ] /type:0 //: joint g5 (A) @(189, 237) /w:[ 1 2 -1 8 ] //: comment g14 @(545,172) /sn:0 /anc:1 //: /line:"Hinweis: Zusätzlich kann man" //: /line:"den aktuellen Wert einer Leitung" //: /line:"sehen wenn man klickt und die" //: /line:"Maustaste einige Sekunden gedrückt hält." //: /end //: SWITCH g0 (A) @(125,217) /sn:0 /w:[ 7 ] /st:0 //: LED g26 (Cin) @(280,184) /sn:0 /w:[ 3 ] /type:0 //: LED g18 (S) @(360,203) /sn:0 /w:[ 1 ] /type:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (B) @(156, 305) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/interface.txt000644 001751 001751 00000002275 10472227451 022376 0ustar00hansenhansen000000 000000 Creating and Editing Module Interfaces 1) Select the "Interface" tab in the main window to start the interface editor. 2) Double-click on module "bar" in module list to edit its interface. 3) Double-click on a port name or port property to change it, any changes will be immediately reflected in the interface example. 4) Double-click on the blank line below the last port in the port list to add a new port. 5) You can also add a new port by right-clicking on the edge of the interface example and then selecting one of the "Add..." options. 6) Change the size of the interface by selecting and dragging the edge or corner of the box. 7) Move the position of a port by selecting and dragging it. Autogeneration of Interfaces 1) Double-clock on the module "foo" in the module list to bring it up in the inteface editor. It should have a blank interface with no ports. 2) To automatically generate an interface, click on the "Auto Generate" button, then select "OK". The generate ports on the interface will be determined from the ports used in the module definition. Return to Edit Mode Click on the "Edit" tab in the main window to switch to the definition for the inteface you have been editing. tkgate-2.0-b10/locale/de/tutorials/combinational4.v000644 001751 001751 00000014561 11137616233 022767 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g13 @(10,10) /anc:1 //: /line:"

Simulation von Schaltnetzen

(DIP Schalter)" //: /line:"" //: /line:"Um während der Simulation einer Schaltung den Wert eines DIP Schalters zu ändern, klickt man zuerst auf ihn, um die Werte-Dialogbox" //: /line:"zu öffnen. Dann gibt man den neuen Wert hexadezimal an und klickt Anwenden. Starte den Simulator und versuche dann," //: /line:"die Eingangswerte für den 4-Bit-Addierer unten zu ändern und beobachte die Ausgabe." //: /end //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(540,127) /sn:0 /anc:1 //: /line:"Hinweis zu Erinnerung: zum Start des" //: /line:"Simulators und der Rückkehr aus der Pause" //: /line:"drücke die \" Simulieren\" Taste," //: /line:"gefolgt vom Knopf." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>A(12/50) Li1>B(34/50) Bo0Simulation von Schaltwerken (Haltepunkte)" //: /line:"" //: /line:"Haltepunkte können verwendet werden, um eine Schaltung so lange zu simulieren, bis eine Bedingung erfüllt ist." //: /line:"Um einen Haltepunkt zu setzen klicke auf die Taste auf der Informationsbox" //: /line:"unterhalb der Arbeitsfläche und drücke den Hinzufügen... Knopf. Gib den Haltepunkt" //: /line:"als Verilog-Ausdruck an. Starte den Simulator und versuche es mit dem Ausdruck \"reg_out == 8'h42\" wie" //: /line:"im Beispiel auf der rechten Seite. Das führt zum Halt des Simulators, wenn das reg_out Signal den hexadezimalen Wert 42 hat." //: /line:"Vergiß nicht, nach der Eingabe des Haltepunkts zu drücken." //: /end //: SWITCH g3 (w4) @(307,295) /sn:0 /R:2 /w:[ 1 ] /st:1 _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(229,312) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(515,140) /sn:0 /anc:1 //: /line:"" //: /line:"" //: /line:"

Beispiel zur Haltepunkteingabe.

" //: /end //: DIP g6 (w7) @(213,212) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(289,366) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(266,278) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(229,264) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(114,312) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/advanced.v000644 001751 001751 00000064720 11137600376 021634 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Fortgeschrittene Editiertechniken

" //: /line:"" //: /line:"In diesem Abschnitt lernen wir weitere Techniken, um noch effizienter Schaltungen in TkGate editieren zu können." //: /end //: comment g0 @(150,93) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Leitungen editieren

(Erzeugen von Lötstellen)" //: /line:"" //: /line:"Nun noch einmal das gleiche, diesmal aber lasse das Invertereingangssegment näher am AND-Ausgang los," //: /line:"weg von der Lötstelle. Diesmal wird eine neue Lötstelle automatischerzeugt." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(162,164)(202,164)(202,147)(227,147)(227,159)(252,159)(252,209)(178,209)(178,179){1} wire w4; //: /sn:0 {0}(131,166)(141,166){1} wire w0; //: /sn:0 {0}(131,161)(141,161){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(152,164) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Automatische Schleifenerkennung)" //: /line:"" //: /line:"Fasse das Ende der XOR-Ausgangsleitung in der Schaltung unten an und ziehe es hoch, bis es das horizontale" //: /line:"Segment dicht am Gatter kreuzt und lasse los. TkGate wird die Leitungsschleife automatisch beseitigen." //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w46; //: /sn:0 {0}(421,254)(374,254)(374,196){1} //: {2}(376,194)(397,194)(397,127)(422,127){3} //: {4}(372,194)(339,194){5} wire w0; //: /sn:0 {0}(67,208)(82,208){1} wire w43; //: /sn:0 {0}(308,191)(318,191){1} wire w1; //: /sn:0 {0}(67,213)(82,213){1} wire w44; //: /sn:0 {0}(308,196)(318,196){1} wire w2; //: /sn:0 {0}(103,211)(130,211)(130,135){1} wire w48; //: /sn:0 {0}(438,127)(448,127){1} wire w47; //: /sn:0 {0}(437,254)(447,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(93,211) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) hari (.I0(w43), .I1(w44), .Z(w46)); //: @(329,194) /sn:0 /anc:1 /w:[ 1 1 5 ] /eb:0 //: joint g50 (w46) @(374, 194) /anc:1 /w:[ 2 -1 4 1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Neuverbinden)" //: /line:"" //: /line:"TkGate verbindet automatisch Leitungen neu, die ein Gatter oder eine Lötstelle nicht in die richtige Richtung" //: /line:"verlassen. Versuche in den beiden Beispielen unten, die Leitung an der Pfeilstelle anzufassen und nach links zu ziehen." //: /line:"Im XOR-Beispiel werden zwei neue Leitungssegmente hinzugefügt. Im Lötstellenbeispiel wird ein Segment" //: /line:"hinzugefügt und die Verbindungsstelle angepaßt." //: /line:"" //: /end _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(427,254) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g0 @(405,147) /sn:0 //: /line:"⇐" //: /end //: comment g12 @(141,164) /sn:0 //: /line:"⇐" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(428,127) /sn:0 /anc:1 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(85,173)(100,173){1} wire w32; //: /sn:0 {0}(316,199)(316,214){1} wire w7; //: /sn:0 {0}(85,178)(100,178){1} wire w14; //: /sn:0 {0}(107,216)(122,216){1} wire w16; //: /sn:0 {0}(80,237)(95,237){1} wire w4; //: /sn:0 {0}(99,157)(114,157){1} wire w15; //: /sn:0 {0}(80,232)(95,232){1} wire w19; //: /sn:0 {0}(85,256)(100,256){1} wire w38; //: /sn:0 {0}(335,190)(335,205){1} wire w0; //: /sn:0 {0}(91,132)(106,132){1} wire w3; //: /sn:0 {0}(99,152)(114,152){1} wire w37; //: /sn:0 {0}(333,154)(333,169){1} wire w34; //: /sn:0 {0}(295,168)(295,183){1} wire w21; //: /sn:0 {0}(359,164)(359,179){1} wire w31; //: /sn:0 {0}(314,163)(314,178){1} wire w28; //: /sn:0 {0}(394,182)(394,197){1} wire w20; //: /sn:0 {0}(121,254)(136,254){1} wire w23; //: /sn:0 {0}(356,200)(356,215){1} wire w24; //: /sn:0 {0}(378,168)(378,183){1} wire w36; //: /sn:0 {0}(338,154)(338,169){1} wire w41; //: /sn:0 {0}(416,210)(416,225){1} wire w1; //: /sn:0 {0}(91,137)(106,137){1} wire w25; //: /sn:0 {0}(373,168)(373,183){1} wire w8; //: /sn:0 {0}(121,176)(136,176){1} wire w18; //: /sn:0 {0}(85,251)(100,251){1} wire w35; //: /sn:0 {0}(297,204)(297,219){1} wire w40; //: /sn:0 {0}(414,174)(414,189){1} wire w30; //: /sn:0 {0}(319,163)(319,178){1} wire w17; //: /sn:0 {0}(116,235)(131,235){1} wire w22; //: /sn:0 {0}(354,164)(354,179){1} wire w2; //: /sn:0 {0}(127,135)(142,135){1} wire w11; //: /sn:0 {0}(117,195)(132,195){1} wire w12; //: /sn:0 {0}(71,213)(86,213){1} wire w10; //: /sn:0 {0}(81,197)(96,197){1} wire w13; //: /sn:0 {0}(71,218)(86,218){1} wire w27; //: /sn:0 {0}(399,182)(399,197){1} wire w5; //: /sn:0 {0}(135,155)(150,155){1} wire w33; //: /sn:0 {0}(300,168)(300,183){1} wire w29; //: /sn:0 {0}(396,218)(396,233){1} wire w9; //: /sn:0 {0}(81,192)(96,192){1} wire w26; //: /sn:0 {0}(375,204)(375,219){1} wire w39; //: /sn:0 {0}(419,174)(419,189){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g8 (.I0(w21), .I1(w22), .Z(w23)); //: @(356,190) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w9), .I1(w10), .Z(w11)); //: @(107,195) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g13 (.I0(w33), .I1(w34), .Z(w35)); //: @(297,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g2 (.I0(w6), .I1(w7), .Z(w8)); //: @(111,176) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g1 (.I0(w3), .I1(w4), .Z(w5)); //: @(125,155) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g11 (.I0(w27), .I1(w28), .Z(w29)); //: @(396,208) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g10 (.I0(w24), .I1(w25), .Z(w26)); //: @(375,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g6 (.I0(w15), .I1(w16), .Z(w17)); //: @(106,235) /sn:0 /w:[ 1 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Gatter ausrichten)" //: /line:"" //: /line:"Eine Gruppe von Gattern kann man durch Auswählen und Drücken von vertikal ausrichten" //: /line:"und mit horizontal. Versuche das mit der Gruppe von Gattern unten." //: /end _GGAND2 #(6) g7 (.I0(w18), .I1(w19), .Z(w20)); //: @(111,254) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g15 (.I0(w39), .I1(w40), .Z(w41)); //: @(416,200) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g5 (.I0(w12), .I1(w13), .Z(w14)); //: @(97,216) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g14 (.I0(w36), .I1(w37), .Z(w38)); //: @(335,180) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(117,135) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g12 (.I0(w30), .I1(w31), .Z(w32)); //: @(316,189) /sn:0 /R:3 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(85,137)(95,137){1} wire w19; //: /sn:0 {0}(322,140)(332,140){1} wire w21; //: /sn:0 {0}(321,242)(331,242){1} wire w20; //: /sn:0 {0}(305,242)(288,242)(288,140)(306,140){1} wire w18; //: /sn:0 {0}(162,245)(172,245){1} wire w40; //: /sn:0 {0}(193,243)(203,243){1} wire w17; //: /sn:0 {0}(172,240)(153,240)(153,140)(116,140){1} wire w9; //: /sn:0 {0}(85,142)(95,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(183,243) /sn:0 /anc:1 /w:[ 0 1 0 ] /eb:0 //: comment g1 @(120,178) /sn:0 /anc:1 //: /line:"⇒" //: /end _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(312,140) /sn:0 /anc:1 /w:[ 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Leitungssegmente)" //: /line:"" //: /line:"Manchmal gibt es keine freien Enden von zwei Leitungen, die verbunden werden sollen. Klicke mit rechts auf den" //: /line:"mit dem AND-Gatter verbundenen Ausgang an der durch den Pfeil angezeigten Stelle. Wähle die" //: /line:"Leitungssegment hinzufügen Option aus dem Popup Menu. Jetzt kann" //: /line:"die neu erzeugte Leitung zu den Puffereingängen hinzugefügt werden." //: /line:"" //: /end _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(106,140) /sn:0 /anc:1 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(311,242) /sn:0 /anc:1 /w:[ 0 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Leitungen editieren

(Erzeugen von Lötstellen)" //: /line:"" //: /line:"Wähle das Werkzeug und ziehe den Eingang des Inverters in der Schaltung unten" //: /line:"nahe an die Lötstelle in der Mitte des AND-Gatterausgangssegments und lasse los. Die Leitung sollte sich" //: /line:"von selbst mit der Lötstelle verbinden." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(325,245)(373,245){1} //: {2}(377,245)(468,245){3} //: {4}(375,243)(375,163)(436,163){5} wire w7; //: /sn:0 {0}(421,158)(436,158){1} wire w4; //: /sn:0 {0}(289,247)(304,247){1} wire w3; //: /sn:0 {0}(61,247)(108,247){1} //: {2}(112,247)(199,247){3} //: {4}(110,245)(110,161)(169,161){5} wire w0; //: /sn:0 {0}(289,242)(304,242){1} wire w1; //: /sn:0 {0}(30,244)(40,244){1} wire w8; //: /sn:0 {0}(190,159)(200,159){1} wire w2; //: /sn:0 {0}(30,249)(40,249){1} wire w10; //: /sn:0 {0}(457,161)(472,161){1} wire w5; //: /sn:0 {0}(159,156)(169,156){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g3 (w3) @(110, 247) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(180,159) /sn:0 /anc:1 /w:[ 1 5 0 ] /eb:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w4), .Z(w6)); //: @(315,245) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g11 @(363,264) /sn:0 /anc:1 //: /line:"OR-Gatterschaltung" //: /end //: comment g10 @(70,271) /sn:0 /anc:1 //: /line:"AND-Gatterschaltung" //: /end //: joint g6 (w6) @(375, 245) /w:[ 2 4 1 -1 ] //: comment g7 @(413,213) /sn:0 /anc:1 //: /line:"⇓" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Automatisches Aufräumen von Leitungen)" //: /line:"" //: /line:"Wähle das Werkzeug und schneide die Leitung in der AND-Schaltung an der durch den Pfeil bezeichneten Stelle durch." //: /line:"TkGate wird automatisch die Leitungsverbindung lösen. Schneide dann auch in der OR-Schaltung" //: /line:"an der durch den Pfeil bezeichneten Stelle die Leitung ab. Das freie Leitungsende wird automatisch gelöscht." //: /line:"" //: /end _GGOR2 #(6) g5 (.I0(w7), .I1(w6), .Z(w10)); //: @(447,161) /sn:0 /anc:1 /w:[ 1 5 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(51,247) /sn:0 /anc:1 /w:[ 1 1 0 ] /eb:0 //: comment g12 @(123,184) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] wire w14; //: /sn:0 {0}(292,263)(226,263)(226,200)(245,200)(245,140)(178,140){1} wire w16; //: /sn:0 {0}(313,266)(323,266){1} wire w15; //: /sn:0 {0}(282,268)(292,268){1} wire w11; //: /sn:0 {0}(147,137)(157,137){1} wire w12; //: /sn:0 {0}(147,142)(157,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(303,266) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(168,140) /sn:0 /w:[ 1 1 1 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Anziehungskraft)" //: /line:"" //: /line:"Klicke in der Schaltung unten auf die Leitung an der Stelle mit dem Pfeil und ziehe sie solange nach links" //: /line:"bis sie mit dem anderen vertikalen Element nahezu auf Linie ist. Wird die Leitung losgelassen, führt \"Anziehungskraft\" dazu," //: /line:"daß die beiden vertikalen Segmente zu einem einzigen Segment einrasten." //: /line:"" //: /end //: comment g0 @(562,122) /sn:0 /anc:1 //: /line:"Hinweis: Die automatische Bereinigung" //: /line:"beim Editieren von Leitungen kann durch" //: /line:"Halten der Alt Taste während der Bewegung" //: /line:"verhindert werden." //: /end //: comment g12 @(252,158) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] reg crete; //: {0}(7:215,136)(359,136)(359,189){1} //: {2}(361,191)(416,191){3} //: {4}(359,193)(359,203){5} reg ithaca; //: {0}(18:215,183)(259,183){1} //: {2}(263,183)(271,183){3} //: {4}(261,185)(261,238)(278,238){5} reg toledo; //: {0}(-21:213,243)(254,243){1} //: {2}(258,243)(278,243){3} //: {4}(256,241)(256,188)(271,188){5} wire styx; //: {0}(99:355,275)(355,295){1} wire athens; //: {0}(416,186)(356,186){1} //: {2}(71:352,186)(292,186){3} //: {4}(354,188)(354,203){5} wire pheneos; //: {0}(76:357,224)(357,254){1} wire olympos; //: {0}(-15:437,189)(506,189){1} wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: LED g37 (olympos) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGXOR2 #(8) Athena (.I0(ithaca), .I1(toledo), .Z(athens)); //: @(282,186) /w:[ 3 5 3 ] /eb:0 _GGNAND2 #(4) Hermes (.I0(athens), .I1(crete), .Z(pheneos)); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0 _GGNAND2 #(4) Hades (.I0(delphi), .I1(pheneos), .Z(styx)); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0 _GGXOR2 #(8) Zeus (.I0(athens), .I1(crete), .Z(olympos)); //: @(427,189) /w:[ 0 3 0 ] /eb:0 //: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Leitungen editieren

(Suchen)" //: /line:"" //: /line:"In der ganzen Schaltung kann mit einem Namen nach einer bestimmten Leitung oder einem bestimmten Gatter mit dem Suchwerkzeug" //: /line:"gesucht werden. Klicke zum Öffnen auf das Werkzeug. Die Liste der Treffer wird dynamisch angepaßt, während der Suchstring" //: /line:"getippt wird. Mit einem Doppelklick auf einen Eintrag in den Suchergebnissen gelangt man zu diesem Objekt." //: /line:"Probiere das Suchwerkzeug für einige der Leitungen und Gatter in der untenstehenden Schaltung aus." //: /line:"" //: /end //: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ] //: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 //: SWITCH Theseus (crete) @(198,136) /w:[ 0 ] /st:0 _GGNAND2 #(4) Apollo (.I0(ithaca), .I1(toledo), .Z(delphi)); //: @(289,241) /w:[ 5 3 0 ] /eb:0 //: SWITCH Odysseus (ithaca) @(198,183) /w:[ 0 ] /st:0 //: comment g0 @(588,148) /sn:0 //: /line:"Hinweis: Das Suchwerkzeug schaut" //: /line:"in allen Modulen der Schaltung" //: /line:"nach dem Suchstring. Suche nach" //: /line:"einem Gatter namens \"hari\"." //: /end //: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ] //: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ] endmodule //: /netlistEnd //: /netlistBegin OLD module OLD(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(624,293)(634,293){1} wire w6; //: /sn:0 {0}(476,150)(516,150)(516,133)(541,133)(541,145)(566,145)(566,195)(492,195)(492,165){1} wire w7; //: /sn:0 {0}(470,428)(480,428){1} wire w46; //: /sn:0 {0}(724,568)(681,568)(681,559){1} //: {2}(683,557)(697,557)(697,519)(722,519){3} //: {4}(679,557)(646,557){5} wire w16; //: /sn:0 {0}(543,101)(553,101){1} wire w14; //: /sn:0 {0}(522,98)(512,98)(512,79)(531,79)(531,46)(478,46){1} wire w19; //: /sn:0 {0}(604,430)(614,430){1} wire w15; //: /sn:0 {0}(512,103)(522,103){1} wire w4; //: /sn:0 {0}(445,152)(455,152){1} wire w38; //: /sn:0 {0}(747,392)(757,392){1} wire w3; //: /sn:0 {0}(475,285)(516,285){1} //: {2}(520,285)(573,285){3} //: {4}(518,283)(518,239)(548,239){5} wire w0; //: /sn:0 {0}(445,147)(455,147){1} wire w37; //: /sn:0 {0}(721,392)(731,392){1} wire w34; //: /sn:0 {0}(744,361)(754,361){1} wire w21; //: /sn:0 {0}(604,468)(614,468){1} wire w43; //: /sn:0 {0}(615,554)(625,554){1} wire w31; //: /sn:0 {0}(624,288)(634,288){1} wire w28; //: /sn:0 {0}(655,291)(696,291){1} //: {2}(700,291)(753,291){3} //: {4}(698,289)(698,245)(728,245){5} wire w23; //: /sn:0 {0}(537,388)(547,388){1} wire w41; //: /sn:0 {0}(492,556)(502,556){1} wire w36; //: /sn:0 {0}(632,363)(642,363){1} wire w20; //: /sn:0 {0}(588,468)(576,468)(576,430)(588,430){1} wire w24; //: /sn:0 {0}(547,360)(524,360){1} //: {2}(522,358)(522,329)(548,329){3} //: {4}(520,360)(482,360){5} wire w1; //: /sn:0 {0}(444,282)(454,282){1} wire w25; //: /sn:0 {0}(564,329)(574,329){1} wire w35; //: /sn:0 {0}(632,358)(642,358){1} wire w8; //: /sn:0 {0}(569,237)(579,237){1} wire w40; //: /sn:0 {0}(554,475)(564,475){1} wire w18; //: /sn:0 {0}(523,477)(533,477){1} wire w30; //: /sn:0 {0}(749,243)(759,243){1} wire w22; //: /sn:0 {0}(451,362)(461,362){1} wire w17; //: /sn:0 {0}(533,472)(517,472)(517,431)(501,431){1} wire w2; //: /sn:0 {0}(444,287)(454,287){1} wire w44; //: /sn:0 {0}(615,559)(625,559){1} wire w12; //: /sn:0 {0}(447,48)(457,48){1} wire w11; //: /sn:0 {0}(447,43)(457,43){1} wire w10; //: /sn:0 {0}(451,357)(461,357){1} wire w27; //: /sn:0 {0}(563,388)(573,388){1} wire w13; //: /sn:0 {0}(492,551)(502,551){1} wire w48; //: /sn:0 {0}(738,519)(748,519){1} wire w5; //: /sn:0 {0}(538,234)(548,234){1} wire w33; //: /sn:0 {0}(728,361)(705,361){1} //: {2}(703,359)(703,330)(729,330){3} //: {4}(701,361)(663,361){5} wire w47; //: /sn:0 {0}(740,568)(750,568){1} wire w29; //: /sn:0 {0}(718,240)(728,240){1} wire w9; //: /sn:0 {0}(470,433)(480,433){1} wire w42; //: /sn:0 {0}(523,554)(541,554)(541,518){1} wire w39; //: /sn:0 {0}(745,330)(755,330){1} wire w26; //: /sn:0 {0}(563,360)(573,360){1} //: enddecls //: comment g4 @(10,552) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(466,150) /sn:0 /w:[ 1 1 0 ] /eb:0 //: frame g51 @(442,505) /sn:0 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(703, 361) /w:[ 1 2 4 -1 ] //: frame g34 @(437,317) /sn:0 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(518, 285) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(544,475) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(559,237) /sn:0 /w:[ 1 5 0 ] /eb:0 //: comment g1 @(542,55) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(533,101) /sn:0 /w:[ 0 1 0 ] /eb:0 //: joint g50 (w46) @(681, 557) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(553,360) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(468,46) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(739,243) /sn:0 /w:[ 1 5 0 ] /eb:0 //: joint g27 (w24) @(522, 360) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(594,430) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(653,361) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(698, 291) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(513,554) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(730,568) /sn:0 /w:[ 0 0 ] //: frame g43 @(617,222) /sn:0 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(553,388) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(472,360) /sn:0 /w:[ 1 1 5 ] /eb:0 //: frame g52 @(597,507) /sn:0 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(437,221) /sn:0 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(491,431) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(636,557) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(737,392) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(734,361) /sn:0 /w:[ 0 0 ] //: comment g24 @(485,442) /sn:0 //: /line:"--->" //: /end //: frame g41 @(436,127) /sn:0 /wi:141 /ht:77 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(594,468) /sn:0 /w:[ 0 0 ] //: frame g40 @(434,30) /sn:0 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(440,416) /sn:0 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(735,330) /sn:0 /w:[ 3 0 ] //: frame g35 @(618,318) /sn:0 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(554,329) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(465,285) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(645,291) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g30 @(723,257) /sn:0 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(728,519) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/wires.v000644 001751 001751 00000024513 11137600577 021217 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Leitungen editieren

" //: /line:"" //: /line:"Dieser Abschnitt führt in die grundlegenden Möglichkeiten ein, Leitungen zu editieren." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(185,114) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Leitungen editieren

(I/O Inverter)" //: /line:"" //: /line:"Wähle das Werkzeug, um einen Inverter an einen Gatterein- oder ausgang zu setzen oder dort zu löschen." //: /line:"Klicke auf einen Port, an dem ein Inverter gesetzt oder gelöscht werden soll und versuche mit dem" //: /line:"Inverterwerkzeug in der Schaltung unten Negationen zu setzen oder zu löschen." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:155,153)(261,153)(261,195){1} //: {2}(263,197)(286,197){3} //: {4}(261,199)(261,209){5} reg a0; //: {0}(40:155,189)(199,189){1} //: {2}(203,189)(211,189){3} //: {4}(201,191)(201,245)(218,245){5} reg b0; //: {0}(50:155,224)(193,224){1} //: {2}(195,222)(195,194)(211,194){3} //: {4}(195,226)(195,250)(218,250){5} wire w7; //: /sn:0 {0}(239,248)(254,248)(254,260){1} wire s0; //: {0}(36:307,195)(337,195){1} wire w4; //: /sn:0 {0}(259,230)(259,260){1} wire c1; //: {0}(99:257,281)(257,300){1} wire w9; //: /sn:0 {0}(286,192)(258,192){1} //: {2}(254,192)(232,192){3} //: {4}(256,194)(256,209){5} //: enddecls //: LED g37 (s0) @(344,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Leitungen editieren

(Leitungsmarkierungen)" //: /line:"" //: /line:"Mit dem Werkzeug kann man Bezeichnungen an Leitungen anbringen. Aktiviere dieses Werkzeug, falls es noch nicht aktuell" //: /line:"ausgewählt ist. Bereits existierende Namen können durch Linksklick mit Ziehen neu positioniert werden. Allerdings" //: /line:"kann der Name nur in der Nähe der assoziiierten Leitung verschoben werden. Wird die Markierung zu weit wegbewegt, kann sie" //: /line:"verlorengehen. Um einen neuen Namen zu vergeben, wählt man nach Rechtsklick auf die Leitung die Namen anzeigen Option." //; /line:"Man kann einzelne oder alle Markierungen für eine Leitung verstecken (Namen verstecken, Alle Namen verstecken)." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(257,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(229,248) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(138,153) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(256, 192) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(259,220) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(138,189) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(201, 189) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(297,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(222,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(138,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g30 (b0) @(195, 224) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(261, 197) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Leitungen editieren

(Trennen)" //: /line:"" //: /line:"Zum Durchtrennen von Leitungen wähle das Werkzeug und klicke auf eine Leitung an der Trennstelle." //: /line:"Probiere das Trennwerkzeug an einigen Leitungen in der untenstehenden Schaltung aus." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] supply1 w7; //: /sn:0 {0}(320,176)(335,176)(335,158){1} reg [7:0] w3; //: /sn:0 {0}(#:184,170)(184,208)(212,208)(212,224){1} supply0 w8; //: /sn:0 {0}(271,250)(271,238)(252,238){1} supply0 w5; //: /sn:0 {0}(339,207)(339,186)(320,186){1} wire [7:0] w6; //: /sn:0 {0}(281,171)(281,146)(371,146)(371,268)(#:228,268)(#:228,253){1} wire w4; //: /sn:0 {0}(204,238)(189,238){1} wire [7:0] w1; //: /sn:0 {0}(244,224)(244,211)(#:281,211)(#:281,192){1} wire w2; //: /sn:0 {0}(85,181)(244,181){1} //: enddecls //: DIP g8 (w3) @(184,160) /sn:0 /w:[ 0 ] /st:66 //: GROUND g4 (w5) @(339,213) /sn:0 /w:[ 0 ] //: comment g2 @(9,10) /anc:1 //: /line:"

Leitungen editieren

(Bitbreiten)" //: /line:"" //: /line:"Um die Bitbreite einer oder mehrerer Leitungen zu ändern, muß zuerst die gewünschte Bitbreite in der" //: /line:"Bitbreiten-Auswahl eingegeben werden. Dann wähle das Werkzeug und klicke" //: /line:"auf jede Leitung, deren Breite geändert werden soll. Versuche in der Schaltung unten die 8-Bit-Leitungen" //: /line:"in 16 Bit Breite zu ändern." //: /line:"" //: /end _GGREG8 #(10, 10, 20) g1 (.Q(w1), .D(w6), .EN(w5), .CLR(w7), .CK(w2)); //: @(281,181) /sn:0 /w:[ 1 0 1 0 1 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGCLOCK_P100_0_50 g6 (.Z(w2)); //: @(72,181) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g7 (w8) @(271,256) /sn:0 /w:[ 0 ] //: VDD g5 (w7) @(346,158) /sn:0 /w:[ 1 ] _GGADD8 #(68, 70, 62, 64) g0 (.A(w3), .B(w1), .S(w6), .CI(w8), .CO(w4)); //: @(228,240) /sn:0 /w:[ 1 0 1 1 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/combinational5.v000644 001751 001751 00000015452 11137616233 022770 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g13 @(10,10) /anc:1 //: /line:"

Simulation von Schaltnetzen

(Instanzhierarchie)" //: /line:"" //: /line:"Während der Simulator aktiv ist, zeigt die hierarchische Modulliste die Hierarchie der Instanzen" //: /line:"anstelle der Module an. Denn der Zustand (die Netzeigenschaften) jeder Instanz eines Moduls in der" //: /line:"Hierarchie können verschieden sein. Rufe die simulation der untenstehenden Schaltung auf und entlasse" //: /line:"sie aus der Pause. Untersuche dann die Netze in verschiedenen Instanzen des ADD1-Moduls. Klicke jedesmal" //: /line:"doppelt auf \"g0<ADD1>\",\"g1<ADD1>\", etc. in der Hierarchielisten-Box, um zu jeder Instanz zu gelangen." //: /line:"" //: /end //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(540,147) /sn:0 /anc:1 //: /line:"Hinweis, zur Erinnerung: Start und Rückkehr" //: /line:"aus der Pause geht durch Drücken der" //: /line:"\" Simulieren\" Taste," //: /line:"gefolgt vom Knopf." //: /end //: comment g7 @(540,227) /sn:0 /anc:1 //: /line:"Hinweis: Um zu den Modulen zu gelangen" //: /line:"kann man auch Rechtsklicken und Öffnen" //: /line:"aus dem Popup Menu aufrufen." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>A(12/50) Li1>B(34/50) Bo0Simulation von Schaltnetzen" //: /line:"" //: /line:"TkGate benutzt einen Verilog-basierten diskret-ereignisgesteuerten Simulator zur" //: /line:"Simulation der Schaltungsbeschreibung. In diesem Abschnitt werden die Grundlagen" //: /line:"beschrieben, die zur Simulation von Schaltnetzen benötigt werden." //: /end //: comment g0 @(191,165) /sn:0 /anc:1 //: /line:"" //: /end //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/de/tutorials/notes.v000644 001751 001751 00000002474 10012327623 021205 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "notes.v" module main; //: root_module //: enddecls //: comment g1 /dolink:1 /link:"@T/welcome_tut.v" @(611,27) /sn:0 //: /line:"Return to welcome." //: /end //: comment g0 /dolink:0 /link:"" @(42,57) /sn:0 //: /line:"* Make sure interface in library matches interfaces used in circuit." //: /line:"* Add HDL module type." //: /line:"* HTML tags in comments instead of all-or-nothing hyperlink." //: /line:"* How about a simulator selection dialog box with options for switches to include, etc." //: /line:"* Bitmap symbol editor for libraries" //: /line:"* HDL modules" //: /line:"* Current module's interface shown in lower left box." //: /line:"" //: /line:"BUGS:" //: /line:"* Landscape printing with A4 paper." //: /line:"* Lack of editing on edit interfaces screen." //: /line:"* Mysterious double modules on interface screen in welcome_tut.v" //: /line:"* Ctl-D duplicate a gate, then double click. prop box doesn't open." //: /line:"" //: /line:"TO DO:" //: /line:"" //: /line:"* Finish module interface generator" //: /line:"* Convert port box to use SpreadSheet" //: /line:"* Verilog Modules" //: /line:"* Custom Module Symbols" //: /line:"* Dialog box images" //: /line:"* Japanese messages.ja" //: /line:"" //: /end endmodule tkgate-2.0-b10/locale/de/tutorials/gates.v000644 001751 001751 00000037022 11137600554 021163 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

" //: /line:"" //: /line:"Dieser Abschnitt führt in einige grundlegende Editierfunktionen von TkGate für Gatter ein." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(144,69) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(256,171)(271,171){1} wire w0; //: /sn:0 {0}(102,172)(117,172){1} wire w3; //: /sn:0 {0}(256,166)(271,166){1} wire w1; //: /sn:0 {0}(102,177)(117,177){1} wire w2; //: /sn:0 {0}(138,175)(153,175){1} wire w5; //: /sn:0 {0}(292,169)(307,169){1} //: enddecls //: comment g4 @(247,195) /sn:0 /anc:1 //: /line:"Verankertes Gatter" //: /end _GGOR2 #(6) g3 (.I0(w3), .I1(w4), .Z(w5)); //: @(282,169) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

(Verankerung)" //: /line:"" //: /line:"Um zu verhindern, daß ein Gatter aus Versehen bewegt wird, kann man es auswählen und den" //: /line:" Knopf drücken, um einen Anker zu setzen. Er kann mit dem Knopf wieder entfernt werden." //: /line:"Festgezurrte Gatter, wie das OR Gatter unten, können nicht bewegt werden, solange" //: /line:"der Anker nicht entfernt ist. Versuche die Gatter unten zu bewegen." //: /line:"" //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(128,175) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(587,112) /sn:0 /anc:1 //: /line:"Hinweis: ein alternativer Weg, einen" //: /line:"Anker eines Gatters zu setzen oder" //: /line:"zu löschen ist ein Rechtsklick" //: /line:"und ein Wechsel des Anker-" //: /line:"Flags im Popup Menu." //: /end //: comment g5 @(81,195) /sn:0 /anc:1 //: /line:"Nicht verankertes Gatter" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) /anc:1 //: /line:"

Editieren von Gattern

(Verschieben)" //: /line:"" //: /line:"um ein Gatter zu bewegen, wähle es mit aus und ziehe es an den neuen Ort. " //: /line:"Versuche es mit der Beispielschaltung unten." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(39,221)(54,221){1} wire w7; //: /sn:0 {0}(41,265)(56,265){1} wire w16; //: /sn:0 {0}(154,267)(169,267){1} wire w14; //: /sn:0 {0}(169,222)(154,222){1} wire w19; //: /sn:0 {0}(169,277)(154,277){1} wire w15; //: /sn:0 {0}(154,262)(169,262){1} wire w4; //: /sn:0 {0}(39,218)(54,218){1} wire w0; //: /sn:0 {0}(37,166)(52,166){1} wire w3; //: /sn:0 {0}(39,214)(54,214){1} wire w21; //: /sn:0 {0}(152,167)(167,167){1} wire w20; //: /sn:0 {0}(41,274)(56,274){1} wire w23; //: /sn:0 {0}(188,169)(203,169){1} wire w1; //: /sn:0 {0}(37,171)(52,171){1} wire w18; //: /sn:0 {0}(190,269)(205,269){1} wire w8; //: /sn:0 {0}(41,268)(56,268){1} wire w17; //: /sn:0 {0}(169,272)(154,272){1} wire w22; //: /sn:0 {0}(152,172)(167,172){1} wire w12; //: /sn:0 {0}(154,217)(169,217){1} wire w11; //: /sn:0 {0}(154,212)(169,212){1} wire w2; //: /sn:0 {0}(73,169)(88,169){1} wire w10; //: /sn:0 {0}(41,271)(56,271){1} wire w13; //: /sn:0 {0}(190,217)(205,217){1} wire w5; //: /sn:0 {0}(75,218)(90,218){1} wire w9; //: /sn:0 {0}(77,270)(92,270){1} //: enddecls _GGAND4 #(10) g4 (.I0(w7), .I1(w8), .I2(w10), .I3(w20), .Z(w9)); //: @(67,270) /sn:0 /w:[ 1 1 1 1 0 ] //: comment g8 @(149,126) /sn:0 /anc:1 //: /line:"Gatter mit" //: /line:"Erweiterungsbalken" //: /end _GGAND3 #(8) g3 (.I0(w3), .I1(w4), .I2(w6), .Z(w5)); //: @(65,218) /sn:0 /w:[ 1 1 1 0 ] //: comment g2 @(11,13) /anc:1 //: /line:"

Editieren von Gattern

(Eingänge hinzufügen)" //: /line:"" //: /line:"Einige Gatter (AND Gatter z.B.) können eine variable Anzahl von Eingängen oder Ausgängen haben. Um diesen Gattern" //: /line:"Eingänge oder AusgÄnge hinzuzufügen, wählt man das Gatter aus und drückt den Knopf. Einige Gatter können auch" //: /line:"verschiedene Methoden zum Hinzufügen von Ports bieten, die dann in der Eigenschaftsbox" //: /line:"des Gatters angeboten werden. Versuche, zu den Gattern unten Eingänge hinzuzufügen" //: /line:"oder erzeuge ein neues Gatter und versieh es mit zusätzlichen Eingängen." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(63,169) /sn:0 /w:[ 1 1 0 ] _GGAND4 #(10) g6 (.I0(w15), .I1(w16), .I2(w17), .I3(w19), .Z(w18)); //: @(180,269) /sn:0 /w:[ 1 1 0 0 0 ] /eb:1 //: comment g7 @(26,127) /sn:0 /anc:1 //: /line:"Gatter ohne" //: /line:"Erweiterungsbalken" //: /end _GGAND2 #(6) g9 (.I0(w21), .I1(w22), .Z(w23)); //: @(178,169) /sn:0 /w:[ 1 1 0 ] /eb:1 _GGAND3 #(8) g5 (.I0(w11), .I1(w12), .I2(w14), .Z(w13)); //: @(180,217) /sn:0 /w:[ 1 1 0 0 ] /eb:1 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: frame g3 @(298,213) /sn:0 /wi:167 /ht:69 /tx:"This is a frame" //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

(Kommentare und Rahmen)" //: /line:"" //: /line:"Es gibt zwei spezielle \"Gatter\", die man zur Beschriftung der Schaltung nutzen kann: Kommentare und Rahmen." //: /line:"Keines dieser \"Gatter\" hat irgendeinen Effekt auf die Simulationsergebnisse." //: /line:"" //: /line:"Kommentare sind Textblöcke wie die, mit denen dieser Lehrgang erzeugt ist. Kommentare werden durch Rechtsklick" //: /line:"und Auswahl von Bausteine → Kommentar aus dem Popup Menu erzeugt. Wird ein Kommentar erzeugt, so erscheint" //: /line:"die Eigenschaftsbox sofort und erlaubt, den Text des Kommentars einzugeben. Kommentare können eine begrenzte" //: /line:"Zahl von HTML-Tags einschließlich Links zu anderen Schaltungsdateien enthalten, oder Kurzschlußzugänge zu" //: /line:"bestimmten Gattern der aktuellen Schaltung." //: /line:"" //: /line:"Rahmen sind benannte Boxen, mit denen Gruppen zusammengehöriger Schaltungselemente zusammengefaßt werden" //: /line:"können, wenn sich die Erzeugung eines eigenen Moduls dafür nicht lohnt. Öffne die Eigenschaftsbox durch Doppelklick" //: /line:"auf eine Kante und gib die Zeichenkette zur Beschreibung ein. Verändere die Größe durch Klicken und Ziehen an einer Ecke." //: /line:"" //: /end //: comment g1 @(72,233) /sn:0 //: /line:"Dies ist ein Kommentar" //: /line:"mit fettem Text." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(118,149)(133,149){1} wire w1; //: /sn:0 {0}(118,154)(133,154){1} wire w2; //: /sn:0 {0}(154,152)(169,152){1} //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

(Drehungen)" //: /line:"" //: /line:"Die Ausrichtung eines Gatters kann geändert werden, indem man das Gatter auswählt und den Knopf" //: /line:"(oder die Tab Taste) drückt, um es gegen den Uhrzeigersinn zu drehen. Den Knopf (oder die Shift-Tab" //: /line:"Tastenkombination) nimmt man, um im Uhrzeigersinn zu drehen. Versuche das mit dem AND Gatter unten." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(144,152) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(567,92) /sn:0 /anc:1 //: /line:"Hinweis: Genauso gut kann man den " //: /line:"Knopf drücken, um die Standard-" //: /line:"orientierung für neue erzeugte Gatter" //: /line:"festzulegen." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

(Eigenschaften)" //: /line:"" //: /line:"Die Eigenschaftsbox eines Gatters öffnet man durch Doppelklick darauf. Versuche das" //: /line:"bei einigen Gattern der untenstehenden Schaltung. In der Eigensschaftsbox kann" //: /line:"die Bezeichnng eines Gatters geändert werden. Sie kann auch durch die" //: /line:"\"Namen verbergen\"-Eigenschaft sichtbar oder unsichtbar gemacht werden." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: comment g6 @(548,104) /sn:0 /anc:1 //: /line:"Hinweis: Viele Eigenschaften sind gatter-" //: /line:"spezifisch. Öffne die Eigenschaftsboxen" //: /line:"unterschiedlicher Gattertypen, um zu sehen," //: /line:"welche Eigenschaften geändert werden" //: /line:"können." //: /end _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editieren von Gattern

(Löschen)" //: /line:"" //: /line:"Um ein Gatter zu löschen, wird es mit dem Werkzeug ausgewählt und die Entf Taste gedrückt." //: /line:"Versuche das bei der Beispielschaltung unten." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGAND4 #(.Diz(1)) (I0, I1, I2, I3, Z); output Z; input I0; input I1; input I2; input I3; assign #Diz Z = I0 & I1 & I2 & I3; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0; input I1; input I2; assign #Diz Z = I0 & I1 & I2; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/welcome.v000644 001751 001751 00000061664 11150625122 021515 0ustar00hansenhansen000000 000000 //: version "2.0-b7" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "Willkommen bei TkGate" //: property discardChanges = 1 //: property timingViolationMode = 2 //: property initTime = "0 ns" `timescale 1ns/1ns //: /symbolBegin: 688896144 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg b; //: {0}(41:73,134)(107,134){1} //: {2}(109,132)(109,84)(127,84){3} //: {4}(109,136)(109,160)(139,160){5} supply1 w7; //: /sn:0 {0}(456,31)(456,18){1} reg [7:0] w19; //: /sn:0 {0}(#:703,66)(703,39){1} reg w0; //: /sn:0 {0}(357,39)(429,39){1} //: {2}(433,39)(442,39){3} //: {4}(431,37)(431,29){5} //: {6}(431,41)(431,141)(481,141){7} reg [1:0] sa; //: /sn:0 {0}(#:136,463)(103,463)(103,428)(90,428){1} reg w28; //: /sn:0 {0}(69,268)(118,268){1} reg w20; //: /sn:0 {0}(661,137)(624,137){1} reg w1; //: /sn:0 {0}(357,87)(392,87){1} //: {2}(396,87)(442,87){3} //: {4}(394,85)(394,78){5} //: {6}(394,89)(394,140)(409,140){7} reg [1:0] sb; //: /sn:0 {0}(#:136,478)(90,478){1} reg [7:0] w25; //: /sn:0 {0}(#:90,208)(131,208)(131,252){1} supply0 w18; //: /sn:0 {0}(741,206)(741,188)(723,188){1} reg ci; //: {0}(12:74,33)(177,33)(177,85){1} //: {2}(179,87)(202,87){3} //: {4}(177,89)(177,116){5} supply0 w11; //: /sn:0 {0}(759,102)(759,80)(743,80){1} supply0 w2; //: /sn:0 {0}(495,150)(495,166)(458,166){1} //: {2}(454,166)(423,166)(423,149){3} //: {4}(456,168)(456,177){5} supply1 w10; //: /sn:0 {0}(723,178)(737,178)(737,160){1} reg a; //: {0}(30:73,79)(115,79){1} //: {2}(119,79)(127,79){3} //: {4}(117,81)(117,155)(139,155){5} supply0 [7:0] w9; //: /sn:0 {0}(#:650,102)(650,92)(674,92)(674,121){1} reg [1:0] w26; //: /sn:0 {0}(#:90,331)(111,331)(111,368)(120,368){1} wire [7:0] w14; //: /sn:0 {0}(#:153,508)(153,545)(248,545)(248,237)(215,237){1} //: {2}(213,235)(213,218){3} //: {4}(211,237)(151,237)(151,252){5} wire w4; //: /sn:0 {0}(205,158)(160,158){1} wire w3; //: /sn:0 {0}(205,153)(175,153)(175,137){1} wire w24; //: /sn:0 {0}(695,80)(685,80){1} wire co; //: {0}(245,146)(-68:245,156)(226,156){1} wire w8; //: /sn:0 {0}(202,82)(174,82){1} //: {2}(170,82)(148,82){3} //: {4}(172,84)(172,116){5} wire [7:0] w30; //: /sn:0 {0}(#:180,508)(180,520)(228,520)(228,310)(215,310){1} //: {2}(213,308)(213,295){3} //: {4}(211,310)(188,310)(188,339){5} wire [7:0] w22; //: /sn:0 {0}(#:694,121)(694,107)(719,107)(719,95){1} wire clk; //: {0}(20:593,183)(647,183){1} wire [7:0] w12; //: /sn:0 {0}(#:165,449)(165,406){1} wire [7:0] w27; //: /sn:0 {0}(#:684,150)(684,173){1} wire s; //: {0}(246,97)(39:246,85)(223,85){1} wire w13; //: /sn:0 {0}(423,132)(423,113)(454,113){1} //: {2}(458,113)(493,113){3} //: {4}(495,111)(495,101){5} //: {6}(495,115)(495,133){7} //: {8}(456,111)(456,96){9} wire w5; //: /sn:0 {0}(456,48)(456,79){1} wire w33; //: /sn:0 {0}(136,493)(86,493)(86,529)(59,529){1} wire [7:0] reg_out; //: {0}(#:684,194)(50:684,230)(729,230){1} //: {2}(-24:733,230)(783,230)(783,55)(735,55)(735,66){3} //: {4}(731,232)(731,249){5} wire [7:0] w29; //: /sn:0 {0}(#:141,339)(141,281){1} //: enddecls //: joint g61 (reg_out) @(731, 230) /w:[ 2 -1 1 4 ] //: VDD g8 (w7) @(467,18) /sn:0 /w:[ 1 ] _GGNMOS #(2, 1) g4 (.Z(w13), .S(w2), .G(w0)); //: @(489,141) /sn:0 /w:[ 7 0 7 ] //: LED g55 (w0) @(431,22) /sn:0 /w:[ 5 ] /type:0 _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co)); //: @(216,156) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g13 (w1) @(394, 87) /w:[ 2 4 1 6 ] //: SWITCH g3 (w0) @(340,39) /sn:0 /w:[ 0 ] /st:0 /dn:1 _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(46,529) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 REGS g2 (.SA(sa), .AIN(w12), .AOUT(w14), .SB(sb), .BOUT(w30), .ck(w33)); //: @(165, 479) /symbol:688896144 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(213,288) /sn:0 /w:[ 3 ] /type:2 _GGCLOCK_P120_0_50 g1 (.Z(clk)); //: @(580,183) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 //: joint g11 (w2) @(456, 166) /w:[ 1 -1 2 4 ] //: joint g16 (w30) @(213, 310) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4)); //: @(150,158) /sn:0 /w:[ 5 5 1 ] /eb:0 //: GROUND g10 (w2) @(456,183) /sn:0 /w:[ 5 ] //: joint g32 (w8) @(172, 82) /w:[ 1 -1 2 4 ] //: SWITCH g27 (ci) @(57,33) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g19 (w0) @(431, 39) /w:[ 2 4 1 6 ] _GGNMOS #(2, 1) g6 (.Z(w13), .S(w2), .G(w1)); //: @(417,140) /sn:0 /w:[ 0 3 7 ] //: DIP sa (sa) @(52,428) /sn:0 /R:1 /w:[ 1 ] /st:0 /dn:1 //: joint g57 (w13) @(495, 113) /w:[ -1 4 3 6 ] //: joint g9 (w13) @(456, 113) /w:[ 2 8 1 -1 ] _GGPMOS #(2, 1) g7 (.Z(w5), .S(w7), .G(w0)); //: @(450,39) /sn:0 /w:[ 0 0 3 ] _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(141,268) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(175,127) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g15 (s) @(246,104) /sn:0 /R:2 /w:[ 0 ] /type:0 //: DIP sb (sb) @(52,478) /sn:0 /R:1 /w:[ 1 ] /st:1 /dn:1 //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(121, 340) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: DIP func (w26) @(52,331) /sn:0 /R:1 /w:[ 0 ] /st:0 /dn:1 //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: joint g29 (a) @(117, 79) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a) @(56,79) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 /dn:1 //: DIP data_in (w25) @(52,208) /sn:0 /R:1 /w:[ 0 ] /st:11 /dn:1 //: LED g56 (w13) @(495,94) /sn:0 /w:[ 5 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,87) /sn:0 /w:[ 9 1 3 ] //: LED g14 (co) @(245,139) /sn:0 /w:[ 0 ] /type:0 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 /dn:1 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,85) /sn:0 /w:[ 0 3 1 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,82) /sn:0 /w:[ 3 3 3 ] /eb:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: LED g54 (w1) @(394,71) /sn:0 /w:[ 5 ] /type:0 //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: SWITCH g26 (b) @(56,134) /sn:0 /w:[ 0 ] /st:1 /dn:1 //: comment g0 @(280,236) /anc:1 //: /line:"

Willkommen bei TkGate

" //: /line:"[Betaversion]" //: /line:"" //: /line:"" //: /line:" TKGate kommt mit KEINERLEI GARANTIE; siehe dazu auch im Menu 'Hilfe...Lizenz'" //: /line:" die Lizenz- und Garantiedetails. Fehlerberichte bitte an senden" //: /line:" [freigegeben ]" //: /line:"" //: /line:"Zum Ausprobieren von TkGate auf einen der Links unten klicken!" //: /line:"" //: /line:" * Zum Tutorial" //: /line:"" //: /line:" * Zu den Beispielschaltungen" //: /line:"" //: /line:" * Editieren einer neuen Schaltung" //: /line:"" //: /line:" * Öffnen der Dokumentation " //: /end //: SWITCH data_select (w28) @(52,268) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: SWITCH g12 (w1) @(340,87) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g33 (ci) @(177, 87) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(109, 134) /w:[ -1 2 1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](21/89) Ti1>B[7:0](67/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z = 1'b0; initial #100 if (0 == 0) forever begin Z = 1'b1; #100; Z = 1'b0; #100; end else forever begin Z = 1'b0; #100; Z = 1'b1; #100; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/moddef_tut.v000644 001751 001751 00000001376 11137720063 022213 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "module_tut.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g0 @(23,20) /sn:0 //: /line:"

Erzeugen einer Moduldefinition

" //: /line:"" //: /line:"1) Drücke auf der Toolbar." //: /line:"" //: /line:"2) Gib den Namen des neuen Moduls ein." //: /line:"" //: /line:"3) Wähle den Modultyp (Netzliste oder HDL)" //: /line:"" //: /line:"4) Klicke \"OK\" und erzeuge das Modul." //: /line:"" //: /line:"5) Editiere esdurch Doppelklick in der Modulliste." //: /line:"" //: /line:"Hier klicken, um ins Hauptmenu zurückzukehren." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/de/tutorials/sequential1.v000644 001751 001751 00000001517 11137635335 022320 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(14,12) /anc:1 //: /line:"

Simulation von Schaltwerken

" //: /line:"" //: /line:"Dieser Abschnitt baut auf dem vorigen über die Simulation von Schaltnetzen auf." //: /line:"Er führt Simulatorelemente ein, die für die Simulation von Schaltwerken nützlich sind." //: /end //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(208,188) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/de/tutorials/create.v000644 001751 001751 00000017520 11137600417 021322 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg w3; //: /sn:0 {0}(219,137)(154,137){1} reg w9; //: /sn:0 {0}(314,237)(213,237){1} //: {2}(211,235)(211,142)(219,142){3} //: {4}(209,237)(154,237){5} wire w8; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} wire w10; //: /sn:0 {0}(335,235)(345,235){1} //: enddecls //: comment g8 @(313,208) //: /line:"OR Gatter" //: /end //: joint g13 (w9) @(211, 237) /w:[ 1 2 4 -1 ] //: comment g1 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w3), .I1(w9), .Z(w8)); //: @(230,140) /sn:0 /w:[ 0 3 1 ] //: comment g6 @(115,104) //: /line:"Schalter" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"In diesem Abschnitt zeigen wir schrittweise, wie die einfache Schaltung unten erzeugt wird." //: /end //: comment g7 @(208,112) //: /line:"AND Gatter" //: /end //: SWITCH g14 (w3) @(137,137) /sn:0 /w:[ 1 ] /st:0 _GGOR2 #(6) g0 (.I0(w8), .I1(w9), .Z(w10)); //: @(325,235) /sn:0 /w:[ 0 0 0 ] //: SWITCH g12 (w9) @(137,237) /sn:0 /w:[ 5 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(182,237)(182,237)(314,237){1} reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1} wire w7; //: /sn:0 {0}(335,235)(345,235){1} wire w0; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} //: enddecls _GGOR2 #(6) g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(325,235) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g3 (.I0(w2), .I1(w0), .Z(w5)); //: @(230,140) /sn:0 /w:[ 0 1 1 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /w:[ 0 ] /st:0 //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(537,46) /sn:0 /anc:1 //: /line:"" //: /end //: comment g7 @(537,126) /sn:0 /anc:1 //: /line:"Hinweis: Verbindungen werden" //: /line:"immer dann erzeugt, wenn der Lötkolben" //: /line:"aktiv ist und die Leitung in der Mitte" //: /line:"einer anderen Leitung fallengelassen" //: /line:"wird." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"Erzeuge nun die letzte Verbindung. Fasse den unteren Eingang des AND Gatters" //: /line:"und ziehe ihn in die Nähe des Drahtes zwischen dem unteren Schalter und dem OR Gatter." //: /line:"Lasse den Draht los, dann entsteht eine Lötverbindung." //: /line:"" //: /end //: SWITCH g5 (w2) @(137,137) /sn:0 /w:[ 1 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w2; //: /sn:0 {0}(240,140)(255,140){1} //: enddecls _GGAND2 #(6) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(230,140) /sn:0 /w:[ 1 1 0 ] //: frame g1 @(283,202) /sn:0 /wi:78 /ht:46 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"Erzeuge nun ein OR Gatter. Klicke mit der rechten Maustaste in die strichlierte Box" //: /line:"und wähle Bausteine → Gatter → OR aus dem Popup Menu." //: /end //: comment g0 @(532,85) /sn:0 /anc:1 //: /line:"Hinweis: Genauso gut ist ein Tastendruck." //: /line:"Wähle die Position mit Linksklick und tippe" //: /line:"\"o\", um ein OR Gatter zu erzeugen." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(169,237){1} reg w2; //: /sn:0 {0}(154,137)(169,137){1} wire w7; //: /sn:0 {0}(240,140)(255,140){1} wire w4; //: /sn:0 {0}(204,137)(219,137){1} wire w0; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(335,235)(350,235){1} wire w1; //: /sn:0 {0}(299,237)(314,237){1} wire w5; //: /sn:0 {0}(204,142)(219,142){1} //: enddecls //: SWITCH g4 (w2) @(137,137) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGAND2 #(6) g3 (.I0(w4), .I1(w5), .Z(w7)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w1), .Z(w3)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(578,122) /sn:0 /anc:1 //: /line:"Hinweis: Der Lötkolben-Cursor zeigt" //: /line:"an, wenn ein verbindbares Drahtende" //: /line:"ausgewählt ist." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"Verbinde schließlich die Leitungen. Fasse ein Schalter-Drahtende mit der linken Maustaste" //: /line:"und ziehe es zum oberen Eingang des AND Gatters." //: /end //: comment g0 @(579,61) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(335,235)(350,235){1} wire w4; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(240,140)(255,140){1} wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(299,237)(314,237){1} //: enddecls //: frame g8 @(109,215) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" _GGOR2 #(6) g4 (.I0(w4), .I1(w5), .Z(w7)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w0), .I1(w1), .Z(w3)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g1 @(109,121) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"Erzuge als nächstes zwei Schalter. Klicke rechts in jede der strichlierten Boxen" //: /line:"und wähle Bausteine → I/O → Schalter aus dem Popup Menu." //: /end //: comment g0 @(532,86) /sn:0 /anc:1 //: /line:"Hinweis: Genauso gut ist ein Tastendruck." //: /line:"Wähle die Position mit Linksklick und tippe" //: /line:"\"s\", um einen Schalter zu erzeugen." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(531,86) /sn:0 /anc:1 //: /line:"Hinweis: Genauso gut ist ein Tastendruck." //: /line:"Wähle die Position mit Linksklick und tippe" //: /line:"\"a\", um ein AND Gatter zu erzeugen." //: /end //: frame g1 @(208,124) /sn:0 /wi:76 /ht:43 /tx:"" //: comment g9 @(10,10) /anc:1 //: /line:"

Erzeugen einer einfachen Schaltung

" //: /line:"" //: /line:"Beginne mit der Erzeugung eines AND Gatters. Klicke mit rechts in die strichlierte Box und wähle" //: /line:"Bausteine → Gatter → AND aus dem Popup Menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/options.v000644 001751 001751 00000005035 11137644115 021553 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "options.v" //: property discardChanges = 1 //: require "tty" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(219,134) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Anpassen von TkGate

" //: /line:"" //: /line:"Dieser Abschnitt führt einige der Optionen ein, mit denen TkGate angepaßt werden kann." //: /line:"Die Definitionen der Optionen werden in einer Datei namens \".tkgate2-preferences\" im" //: /line:"Heimatverzeichnis gespeichert." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(134,181) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Anpassen von TkGate

(Setzen der Tastaturbindungen)" //: /line:"" //: /line:"Man kann die Tastaturbindungen für die Benutzung der Schnittstelle Taste der Optionen-Dialogbox" //: /line:"anpassen. Zur Zeit kann man zwischen \"emacs\"-style und \"Windows\"-Stil wählen. Das paßt" //: /line:"die Tastaturbelegungen für Operationen wie Ausschneiden/Einfügen an die Gepflogenheiten von emacs oder Windows an." //: /line:"Die Tastenbelegungen für die Erzeugung von Gattern bleiben allerdings erhalten." //: /end //: comment g0 @(10,310) /sn:0 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(116,149) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Anpassen von TkGate

(Angabe der persönlichen Daten)" //: /line:"" //: /line:"Zum Festlegen der TkGate Optionen öffnet man die Optionen Dialogbox durch Auswahl von Datei → Optionen aus dem" //: /line:"Hauptmenu. Gib den Namen der Institution und den Benutzernamen in der \"Organisation\" Dialogbox ein. Die eingegebenen Werte" //: /line:"werden in jeder Druckausgabe von TkGate-Schaltungen benutzt." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/de/tutorials/index.v000644 001751 001751 00000004137 11137615625 021175 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: property encoding = "utf-8" //: property locale = "de" //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(433,291) /sn:0 /R:14 //: /line:"Zurück zur Hauptseite von TkGate." //: /end //: comment g0 @(434,49) /sn:0 /anc:1 //: /line:"" //: /end //: comment g18 @(10,10) /sn:0 /anc:1 //: /line:"

Lernabschnitte:

" //: /line:"" //: /line:"

1. Erzeugen einer Schaltung

" //:/line:" - Anfangen mit der Entwicklung einer einfachen Schaltung." //: /line:"" //: /line:"

2. Gatter editieren

- Grundlagen zum Konfigurieren von Gattern." //: /line:"" //: /line:"

3. Leitungen editieren

- Grundlagen zum Konfigurieren von Leitungen." //: /line:"" //: /line:"

4. Editieren von Gattergruppen

" //: /line:" - Bearbeiten von Gruppen benachbarter Gatter." //: /line:"" //: /line:"

5. Benutzung von Modulen

" //: /line:" - Verwenden von Modulkapselung in der Schaltung." //: /line:"" //: /line:"

6. Fortgeschrittene Editiertechniken

" //: /line:" - Einige weniger gebräuchliche Editiertricks." //: /line:"" //: /line:"

7. Simulation von Schaltnetzen

" //: /line:" - Simulieren eines Schaltnetzes." //: /line:"" //: /line:"

8. Simulation von Schaltwerken

- Simulation sequentieller Schaltungen." //: /line:"" //: /line:"

9. Schaltungen mit Verilog-Text

- Erzeugen von Modulen, die textuelle Verilog-Beschreibungen enthalten." //: /line:"" //: /line:"

10. Anpassen von TkGate

- Konfigurieren nach eigenem Geschmack." //: /line:"" //: /line:"" //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/de/tutorials/sequential2.v000644 001751 001751 00000007661 11137635335 022327 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:190,196)(190,222){1} reg w4; //: /sn:0 {0}(245,281)(256,281)(256,269)(266,269){1} supply0 w3; //: /sn:0 {0}(243,246)(243,236)(230,236){1} supply0 w0; //: /sn:0 {0}(245,291)(268,291)(268,306){1} wire [7:0] w2; //: /sn:0 {0}(#:206,276)(206,251){1} wire ck; //: {0}(50:169,286)(104,286){1} wire [7:0] reg_out; //: {0}(#:206,297)(206,327)(263,327){1} //: {2}(267,327)(323,327)(-70:323,200)(222,200)(222,222){3} //: {4}(265,329)(265,342){5} wire w9; //: /sn:0 {0}(182,236)(172,236){1} //: enddecls //: joint g8 (reg_out) @(265, 327) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(268,312) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Simulation von Schaltwerken

(Schrittweise Simulation)" //: /line:"" //: /line:"Starte den Simulator duch Drücken der \" Simulieren\" Taste, genauso wie bei einem Schaltnetz. Setze dann Tastköpfe" //: /line:"auf die \"ck\" und \"reg_out\" Signale durch Rechtsklicken und Auswahl von Hinzufügen/Löschen Tastkopf. Schreite nun im" //: /line:"Simulator durch mehrere \"Taktschritte\" fort, indem Du den Knopf oder die Tab Taste drückst. Beachte, daß" //: /line:"das \"reg_out\" Signal einen unbekannten \"x\"-Wert zeigt. Um es zurückzusetzen und den Zähler neu zu starten, muß erst" //: /line:"der \"reset\" Schalter auf \"off\" gesetzt werden. Rücke den Simulator um einen Taktschritt vor und stelle dann" //: /line:"den \"reset\" Schalter auf die \"on\" Position zurück." //: /end //: comment g3 @(500,149) /sn:0 /anc:1 //: /line:"Hinweis: Zusätzlich zum Scrollbar im" //: /line:"Logikanalysator kann man auch im Hauptfenster" //: /line:"durch Klicken und Ziehen die Position der Signale" //: /line:"feinabstimmen." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(206,286) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: DIP g6 (w7) @(190,186) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(243,252) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(265,349) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(206,238) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(91,286) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (w4) @(284,269) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/wire2.v000644 001751 001751 00000020645 10472740235 021115 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "edwire_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g4 @(16,548) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(549,50) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g9 @(23,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/de/tutorials/glossary.v000644 001751 001751 00000002645 10207530263 021722 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module //: enddecls //: frame g15 @(600,25) /sn:0 /wi:213 /ht:149 /tx:"Tutorials" //: comment g14 @(629,42) /sn:0 //: /line:"TkGate Introduction
" //: /line:"Creating a Circuit
" //: /line:"Basic Editing Modes
" //: /line:"Group Editing Features
" //: /line:"Editing Wires
" //: /line:"Using Modules
" //: /line:"Combinational Simulation
" //: /line:"Sequential Simulation" //: /end //: comment g0 @(21,26) /sn:0 //: /line:"

Glossary

" //: /line:"" //: /line:"epoch: The smallest unit of time understood by the simulator." //: /line:"" //: /line:"Verilog format constant: The first number indicates the bit width, the" //: /line:"letter indicates the radix, and the last number the value. For example, the \"1\"" //: /line:"in \"1'b0\" indicates that this is a 1-bit value, the \"b\" indicates the value is" //: /line:"given in binary, and the \"0\" indicates the value of the signal." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/de/tutorials/welcome.v~000644 001751 001751 00000061020 11137753743 021715 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "utf-8" //: property locale = "de" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /symbolBegin: 688686768 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg b; //: {0}(41:73,97)(109,97){1} //: {2}(111,95)(111,67)(127,67){3} //: {4}(111,99)(111,143)(139,143){5} supply1 w7; //: /sn:0 {0}(456,31)(456,18){1} reg [7:0] w19; //: /sn:0 {0}(#:703,66)(703,39){1} reg w0; //: /sn:0 {0}(357,39)(429,39){1} //: {2}(433,39)(442,39){3} //: {4}(431,37)(431,29){5} //: {6}(431,41)(431,127)(481,127){7} reg [1:0] w21; //: /sn:0 {0}(#:136,463)(96,463)(96,428)(90,428){1} reg w28; //: /sn:0 {0}(69,268)(89,268)(89,268)(118,268){1} reg w20; //: /sn:0 {0}(661,137)(624,137){1} reg [1:0] w23; //: /sn:0 {0}(#:136,478)(90,478){1} reg w1; //: /sn:0 {0}(357,73)(392,73){1} //: {2}(396,73)(442,73){3} //: {4}(394,71)(394,64){5} //: {6}(394,75)(394,126)(409,126){7} reg [7:0] w25; //: /sn:0 {0}(#:90,208)(131,208)(131,252){1} supply0 w18; //: /sn:0 {0}(741,206)(741,188)(723,188){1} reg ci; //: {0}(12:73,26)(177,26)(177,68){1} //: {2}(179,70)(202,70){3} //: {4}(177,72)(177,99){5} supply0 w11; //: /sn:0 {0}(759,102)(759,80)(743,80){1} supply0 w2; //: /sn:0 {0}(495,136)(495,152)(458,152){1} //: {2}(454,152)(423,152)(423,135){3} //: {4}(456,154)(456,163){5} supply1 w10; //: /sn:0 {0}(723,178)(737,178)(737,160){1} reg a; //: {0}(30:73,62)(115,62){1} //: {2}(119,62)(127,62){3} //: {4}(117,64)(117,138)(139,138){5} supply0 [7:0] w9; //: /sn:0 {0}(#:650,102)(650,92)(674,92)(674,121){1} reg [1:0] w26; //: /sn:0 {0}(#:90,331)(111,331)(111,368)(120,368){1} wire [7:0] w14; //: /sn:0 {0}(#:153,508)(153,545)(248,545)(248,237)(215,237){1} //: {2}(213,235)(213,218){3} //: {4}(211,237)(151,237)(151,252){5} wire w4; //: /sn:0 {0}(205,141)(160,141){1} wire w3; //: /sn:0 {0}(205,136)(175,136)(175,120){1} wire w24; //: /sn:0 {0}(695,80)(685,80){1} wire co; //: {0}(245,129)(-68:245,139)(226,139){1} wire w8; //: /sn:0 {0}(202,65)(174,65){1} //: {2}(170,65)(148,65){3} //: {4}(172,67)(172,99){5} wire [7:0] w30; //: /sn:0 {0}(#:180,508)(180,520)(228,520)(228,310)(215,310){1} //: {2}(213,308)(213,295){3} //: {4}(211,310)(188,310)(188,339){5} wire [7:0] w22; //: /sn:0 {0}(#:694,121)(694,107)(719,107)(719,95){1} wire clk; //: {0}(20:593,183)(647,183){1} wire [7:0] w12; //: /sn:0 {0}(#:165,449)(165,406){1} wire [7:0] w27; //: /sn:0 {0}(#:684,150)(684,173){1} wire s; //: {0}(246,80)(39:246,68)(223,68){1} wire w13; //: /sn:0 {0}(423,118)(423,99)(454,99){1} //: {2}(458,99)(493,99){3} //: {4}(495,97)(495,87){5} //: {6}(495,101)(495,119){7} //: {8}(456,97)(456,82){9} wire w5; //: /sn:0 {0}(456,48)(456,65){1} wire w33; //: /sn:0 {0}(136,493)(86,493)(86,529)(59,529){1} wire [7:0] reg_out; //: {0}(#:684,194)(50:684,230)(729,230){1} //: {2}(-24:733,230)(783,230)(783,55)(735,55)(735,66){3} //: {4}(731,232)(731,249){5} wire [7:0] w29; //: /sn:0 {0}(#:141,339)(141,281){1} //: enddecls //: joint g61 (reg_out) @(731, 230) /w:[ 2 -1 1 4 ] //: VDD g8 (w7) @(467,18) /sn:0 /w:[ 1 ] _GGNMOS #(2, 1) g4 (.Z(w13), .S(w2), .G(w0)); //: @(489,127) /sn:0 /w:[ 7 0 7 ] //: LED g55 (w0) @(431,22) /sn:0 /w:[ 5 ] /type:0 _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co)); //: @(216,139) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g13 (w1) @(394, 73) /w:[ 2 4 1 6 ] //: SWITCH g3 (w0) @(340,39) /sn:0 /w:[ 0 ] /st:0 _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(46,529) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 REGS g2 (.SA(w21), .AIN(w12), .AOUT(w14), .SB(w23), .BOUT(w30), .ck(w33)); //: @(165, 479) /symbol:688686768 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(213,288) /sn:0 /w:[ 3 ] /type:2 _GGCLOCK_P120_0_50 g1 (.Z(clk)); //: @(580,183) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 //: joint g11 (w2) @(456, 152) /w:[ 1 -1 2 4 ] //: joint g16 (w30) @(213, 310) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4)); //: @(150,141) /sn:0 /w:[ 5 5 1 ] /eb:0 //: GROUND g10 (w2) @(456,169) /sn:0 /w:[ 5 ] //: joint g32 (w8) @(172, 65) /w:[ 1 -1 2 4 ] //: SWITCH g27 (ci) @(56,26) /sn:0 /w:[ 0 ] /st:0 //: joint g19 (w0) @(431, 39) /w:[ 2 4 1 6 ] _GGNMOS #(2, 1) g6 (.Z(w13), .S(w2), .G(w1)); //: @(417,126) /sn:0 /w:[ 0 3 7 ] //: DIP sa (w21) @(52,428) /R:1 /w:[ 1 ] /st:0 //: joint g57 (w13) @(495, 99) /w:[ -1 4 3 6 ] //: joint g9 (w13) @(456, 99) /w:[ 2 8 1 -1 ] _GGPMOS #(2, 1) g7 (.Z(w5), .S(w7), .G(w0)); //: @(450,39) /sn:0 /w:[ 0 0 3 ] _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(141,268) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(175,110) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g15 (s) @(246,87) /sn:0 /R:2 /w:[ 0 ] /type:0 //: DIP sb (w23) @(52,478) /R:1 /w:[ 1 ] /st:1 //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(121, 340) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: DIP func (w26) @(52,331) /R:1 /w:[ 0 ] /st:0 //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: joint g29 (a) @(117, 62) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a) @(56,62) /sn:0 /w:[ 0 ] /st:0 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 //: DIP data_in (w25) @(52,208) /R:1 /w:[ 0 ] /st:11 //: LED g56 (w13) @(495,80) /sn:0 /w:[ 5 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,73) /sn:0 /w:[ 9 1 3 ] //: LED g14 (co) @(245,122) /sn:0 /w:[ 0 ] /type:0 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,68) /sn:0 /w:[ 0 3 1 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,65) /sn:0 /w:[ 3 3 3 ] /eb:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: LED g54 (w1) @(394,57) /sn:0 /w:[ 5 ] /type:0 //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: SWITCH g26 (b) @(56,97) /sn:0 /w:[ 0 ] /st:1 //: comment g0 @(280,236) /anc:1 //: /line:"

Willkommen bei TkGate

" //: /line:"[Betaversion]" //: /line:"" //: /line:"" //: /line:" TKGate kommt mit KEINERLEI GARANTIE; siehe auch im Menu 'Hilfe...Lizenz'" //: /line:" die Lizenz- und Garantiedetails. Fehlerberichte bitte an senden" //: /line:" [freigegeben ]" //: /line:"" //: /line:"Zum Ausprobieren von TkGate auf einen der Links unten klicken!" //: /line:"" //: /line:" * Zum Tutorial" //: /line:"" //: /line:" * Zu den Beispielschaltungen" //: /line:"" //: /line:" * Editieren einer neuen Schaltung" //: /line:"" //: /line:" * Öffnen der Dokumentation " //: /end //: SWITCH data_select (w28) @(52,268) /w:[ 0 ] /st:0 //: SWITCH g12 (w1) @(340,73) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (ci) @(177, 70) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(111, 97) /w:[ -1 2 1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](21/89) Ti1>B[7:0](67/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z = 1'b0; initial #100 forever begin Z = 1'b1; #100; Z = 1'b0; #100; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials000777 001751 001751 00000000000 11145151105 017604 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/ja/obsolete-tutorials000777 001751 001751 00000000000 11145151105 021416 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/ja/messages.xxx000644 001751 001751 00000252522 10625203115 020222 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed May 23 23:28:09 2007 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages ############################################################################## # # basic strings # b.new æ–°è¦... b.dismiss é–‰ã˜ã‚‹ b.close é–‰ã˜ã‚‹ b.ok ＯＫ b.clear クリア b.cancel キャンセル b.open é–‹ã b.bitw ビット幅 b.in å…¥ b.out 出 b.inout 入出 b.browse é¸æŠž... b.label åå‰ b.find 探索 b.edit 編集... b.add 追加... b.delete 削除 b.deleteb 削除... b.remove 消㙠b.apply セット b.anchor 移動ä¸å¯ b.tech テクノロジー b.enable å¯èƒ½ã«ã™ã‚‹ b.disable 無能ã«ã™ã‚‹ b.flush クリア ############################################################################## # # Main tab strings # tab.edit 編集 tab.editintr インタフェース tab.simulate シミュレート tab.cpath é…å»¶è§£æž # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add 追加... mm.delete 削除 mm.edit 編集... mm.enable 有効ã«ã™ã‚‹ mm.disable 無効ã«ã™ã‚‹ ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ファイル menu.edit 編集 menu.tool ツール menu.simulate シミュレート menu.module モジュール menu.interface インタフェース menu.gate ゲート menu.make ä½œæˆ menu.help ヘルプ menu.file.new æ–°è¦ä½œæˆ menu.file.open é–‹ã... menu.file.openlib ライブラリを開ã... menu.file.save ä¿å­˜ menu.file.saveas åå‰ã‚’付ã‘ã¦ä¿å­˜... menu.file.print å°åˆ·... menu.file.options 設定... menu.file.quit 終了 menu.file.cprop 回路ã®ç‰¹å¾´... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut カット menu.edit.copy コピー menu.edit.paste ペースト menu.edit.overlay Overlay張り付㑠menu.edit.selall å…¨ã¦ã‚’é¸æŠž menu.edit.find 回路を探索... menu.edit.algnv 縦ã®ä¸€åˆ— menu.edit.algnh 横ã®ãƒ¼åˆ— menu.edit.rotate 回転 menu.edit.zoomin ズーム・イン menu.edit.zoomout ズーム・アウト menu.edit.rshift å³ã‚·ãƒ•ãƒˆ menu.edit.lshift 左シフト menu.edit.ushift 上シフト menu.edit.dshift 下シフト menu.edit.cwrotate 時計周り回転 menu.edit.ccwrotate 時計å対周り回転 menu.edit.pcwrotate ãƒãƒ¼ãƒˆã®æ™‚計周り回転 menu.edit.pccwrotate ãƒãƒ¼ãƒˆã®éžæ™‚計周り回転 #menu.edit.autobold 太字化 menu.edit.resize å†ã‚µã‚¤ã‚ºåŒ– menu.tool.move 移動ï¼æŽ¥ç¶š menu.tool.delg ゲートã®å‰Šé™¤ menu.tool.cutw ワイヤã®åˆ‡æ–­ menu.tool.inv å¦å®š menu.tool.bitw ビット幅 menu.tool.debug デãƒãƒƒã‚° menu.tool.point ãƒã‚¤ãƒ³ãƒˆ menu.tool.line ライン menu.tool.rect 長方形 menu.tool.fillrect 色ã¥ã‘長方形 menu.tool.port ãƒãƒ¼ãƒˆ menu.tool.select å…責é¸æŠž menu.tool.rot0 0度回転 menu.tool.rot90 90度回転 menu.tool.rot180 180度回転 menu.tool.rot270 270度回転 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin シミュレーションを開始 menu.simulate.end シミュレーションを終了 menu.simulate.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.simulate.run ラン menu.simulate.pause 一時ストップ menu.simulate.step ステップ(エãƒãƒƒã‚¯) menu.simulate.cycle ステップ(サイクル) menu.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆã®è¨­å®š... menu.simulate.script スクリプトを実行... menu.simulate.load メモリã®èª­ã¿è¾¼ã¿... menu.simulate.dump メモリã®æ›¸ã出ã—... menu.module.open é–‹ã menu.module.close é–‰ã˜ã‚‹ menu.module.new æ–°è¦ä½œæˆ... menu.module.del 削除... menu.module.copy コピー... menu.module.rename åå‰ã®ç·¨é›†... menu.module.claim å–å¾—... menu.module.setroot ルートã«ã™ã‚‹... menu.module.prop モジュールã®è¨­å®š... menu.module.interface インタフェース menu.module.interface.set セット menu.module.interface.edit 編集 menu.gate.addport ãƒãƒ¼ãƒˆè¿½åŠ  menu.gate.ioset タイプ指定 menu.gate.anchor é¸æŠžã‚’移動ä¸å¯ã«ã™ã‚‹ menu.gate.unanchor é¸æŠžã‚’移動å¯ã«ã™ã‚‹ menu.gate.prop ゲートã®è¨­å®š... menu.gate.rep 複製 menu.gate.del 削除 menu.gate.settech テクノロジーã®è¨­å®š menu.help.about tkgateã«ã¤ã„ã¦... menu.help.license ライセンス... menu.help.doc ドキュメンテーション... menu.help.tut ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ« menu.help.home ホーム・ページ menu.help.example 回路ã®ä¾‹ ############################################################################# # Scope Menu # menu.scope_file ファイル menu.scope_sim シミュレート menu.scope_trace トレース menu.scope_help ヘルプ menu.scope_file.ptrace トレースå°åˆ·... menu.scope_file.close é–‰ã˜ã‚‹ menu.scope_trace.zoomin ズーム・イン menu.scope_trace.zoomout ズーム・アウト menu.scope_sim.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.scope_sim.run 時効 menu.scope_sim.pause 一時åœæ­¢ menu.scope_sim.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— menu.scope_sim.cycle サイクル・ステップ menu.scope_sim.break ブレークãƒã‚¤ãƒ³ãƒˆ... menu.scope_sim.script スクリプトã®æ™‚効... menu.scope_sim.load メモリã®èª­ã¿è¾¼ã¿... menu.scope_sim.dump メモリã®æ›¸ãè¾¼ã¿... menu.scope_help.about tkgateã«ä»˜ã„ã¦... menu.scope_help.license ライセンス... menu.scope_help.doc ドキュメンテーション... mod.intf インタフェース port.parms ãƒãƒ¼ãƒˆã®ãƒ‘ラメタ port.in å…¥ port.out 出 port.inout 入出 ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ゲート gm.rgate å˜é …縮約ゲート gm.msi MSI gm.alu ALU gm.mem メモリー gm.mod モジュール gm.comment コメント gm.frame フレーム gm.io.switch スイッムgm.io.dip DIPスイッムgm.io.ground アース gm.io.vdd Vdd gm.io.merge ワイヤã®ãƒžãƒ¼ã‚¸ gm.io.clock クロック gm.io.led LEDビット gm.io.ledbar LED棒グラフ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ãƒãƒƒãƒ•ã‚¡ gm.gate.inv å¦å®šãƒãƒƒãƒ•ã‚¡ gm.gate.tribuf トライ・ãƒãƒƒãƒ•ã‚¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and å˜é …縮約AND gm.rgate.nand å˜é …縮約NAND gm.rgate.or å˜é …縮約OR gm.rgate.nor å˜é …縮約NOR gm.rgate.xor å˜é …縮約XOR gm.rgate.xnor å˜é …縮約XNOR gm.alu.add 加算器 gm.alu.mult 乗算器 gm.alu.div 除算器 gm.alu.lshift 左シフト gm.alu.rshift å³ã‚·ãƒ•ãƒˆ gm.alu.arshift ç®—æ•°çš„å³ã‚·ãƒ•ãƒˆ gm.alu.roll ロール gm.mem.reg レジスタ gm.mem.ff フリップ・フロップ gm.mem.rff é¡åƒãƒ•ãƒªãƒƒãƒ—・フロップ gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 セレクター gm.msi.41mux 4-1 セレクター gm.msi.81mux 8-1 セレクター gm.msi.12dec 1-2 デコーダ gm.msi.14dec 1-4 デコーダ gm.msi.18dec 1-8 デコーダ gm.mod.inst モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ gm.mod.in モジュールã®å…¥åŠ› gm.mod.out モジュールã®å‡ºåŠ› gm.mod.inout モジュールã®å…¥å‡ºåŠ› tutorial.prev å‰ã¸ tutorial.next 次㸠tutorial.chapter ç« ã®ä¸€è¦§è¡¨ tutorial.reload å†èª­ã¿è¾¼ã¿ ############################################################################## # # Popup menus # pop.make ä½œæˆ pop.tool ツール pop.edit.paste ペースト pop.edit.cut カット pop.edit.copy コピー pop.port.in å…¥ pop.port.out 出 pop.port.inout 入出 pop.wire.addseg ワイヤã®è¿½åŠ  pop.wire.prop ãƒãƒƒãƒˆã®ç‰¹å¾´... pop.wire.hidesize ビット幅を隠㙠pop.wire.showsize ビット幅を示㙠pop.wire.hidelabel レーベルを隠㙠pop.wire.hidealllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’éš ã™ pop.wire.clearalllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’クリア pop.wire.showlabel レーベルを示㙠pop.gate.open é–‹ã pop.gate.close é–‰ã˜ã‚‹ pop.gate.prop インスタンスã®ç‰¹å¾´... pop.gate.addport ãƒãƒ¼ãƒˆã®è¿½åŠ  pop.gate.addin 入力ã®è¿½åŠ ... pop.gate.addout 出力ã®è¿½åŠ ... pop.gate.addinout 入出力ã®è¿½åŠ ... pop.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ pop.gate.settech テクノロジ指定 pop.gate.delete 削除 pop.gate.ioset タイプã®æŒ‡å®š pop.module.new æ–°è¦... pop.module.del 削除... pop.module.copy コピー... pop.module.rename åå‰ã®å¤‰æ›´... pop.module.claim モジュールã®å–å¾— pop.module.setroot ルート指定... pop.module.prop モジュールã®ç‰¹å¾´... pop.module.int インタフェースã®ç·¨é›†... pop.simulate.end シミュレーションを終了 pop.simulate.begin シミュレーションを開始 pop.simulate.addprobe プローブを追加ï¼å‰Šé™¤ pop.simulate.run 時効 pop.simulate.pause 一時åœæ­¢ pop.simulate.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— pop.simulate.cycle サイクル・ステップ pop.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆ... pop.simulate.script スクリプトã®æ™‚効... pop.simulate.load メモリã®èª­ã¿è¾¼ã¿... pop.simulate.dump メモリã®æ›¸ãè¾¼ã¿... pop.interface インタフェース pop.interface.set 指定 pop.interface.edit 編集... pop.interface.auto 自動作æˆ... pop.interface.replace å–ã‚Šæ›ãˆ pop.igen.type タイプ pop.igen.side サイド pop.igen.size サイズ pop.igen.delete 削除 pop.igen.in å…¥ pop.igen.out 出 pop.igen.inout 入出 pop.igen.left å·¦ pop.igen.right å³ pop.igen.top 上 pop.igen.bottom 下 pop.igen.other ä»– ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit 編集 #symed.edit.cut カット #symed.edit.copy コピー #symed.edit.paste ペースト #symed.edit.overlay Overlayペースト #symed.edit.rclock 時計周り回転 #symed.edit.rcclock éžæ™‚計周り回転 #symed.module モジュール #symed.modes モード #symed.cutpaste カットï¼ãƒšãƒ¼ã‚¹ãƒˆ #symed.rotate ãƒãƒ¼ãƒˆã®å›žè»¢ #symed.zoom ズーム #symed.update Update symed.cancel キャンセル symed.tab.normal éžã‚»ãƒ¬ã‚¯ãƒˆ symed.tab.select セレクト symed.link セレクトã¨éžã‚»ãƒ¬ã‚¯ãƒˆã‚’åŒæ™‚ã«ç·¨é›†ã™ã‚‹ã€‚ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg ワイヤã«ãƒ€ãƒ–ル・クリックã—ã¦ã€ãƒ—ローブã«ä»˜ã‘ã£ã¦ãã ã•ã„。 comment.empty [ダブル・クリックã—ã¦ã€ãƒ†ã‚­ã‚¹ãƒˆã‚’編集ã—ã¦ãã ã•ã„。] ############################################################################## # Interface strings # ifile ファイル imodule モジュール iblmodule モジュール: iports ãƒãƒ¼ãƒˆ: ibits ビット幅: itype タイプ: ############################################################################# # Module Dialog Box # db.mod.name モジュールå db.mod.file ファイルå db.mod.type タイプ db.mod.flags フラグ db.mod.dataprot モジュールã®å®šç¾©ã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.intfprot インタフェースã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.edprot インタフェースã®ç·¨é›†ã‚’専用エディタã«é™ã‚‹ã€‚ db.mod.props 特徴 db.mod.netlist ãƒãƒƒãƒˆãƒªã‚¹ãƒˆ db.mod.hdl HDL # # These are probably not used anymore. # db.mod.inuse.0 TODO: Module is not in use. db.mod.inuse.1 TODO: Module is in use. db.mod.lmod.0 TODO: Module has not been modified since loading. db.mod.lmod.1 TODO: Module has been modified since loading. db.mod.smod.0 TODO: Module has not been modified since saving. db.mod.smod.1 TODO: Module has been modified since saving. db.mod.islib.1 TODO: Module is part of [%s] library. db.mod.islib.0 TODO: Module is not a library module. db.mod.netexpl -begin- グラフィカルã®ã‚¨ãƒ‡ã‚£ã‚¿ã‚’ 利用ã—ã¦ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®æ“作を 定義ã™ã‚‹ã€‚ -end- db.mod.hdlexpl -begin- Verilogã®ãƒ†ã‚­ã‚¹ãƒˆã‚’利用ã—ã¦ã€ モジュールã®æ“作を定義ã™ã‚‹ã€‚ -end- ############################################################################# # Error List Dialog box # db.err.caption エラーã®ä¸€è¦§è¡¨ db.err.explain -begin- 回路ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºè¦‹ã•ã‚ŒãŸã®ã§ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã‚’開始 出æ¥ãªã‹ã£ãŸã€‚以下ã®ãƒªã‚¹ãƒˆã®ä¸­ã‹ã‚‰ã€ã‚¨ãƒ©ãƒ¼ã‚’é¸æŠž ã—ã¦ã€ã‚¨ãƒ©ãƒ¼ã®å ´æ‰€ã«ç§»å‹•ã—ã¦ãã ã•ã„。 -end- ############################################################################# # Net Dialog Box # db.net.name ãƒãƒƒãƒˆå db.net.hide ãƒãƒƒãƒˆåã‚’éš ã™ db.net.bits ビット幅 db.net.type ãƒãƒƒãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.port ãƒãƒ¼ãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.in å…¥ db.net.out 出 db.net.inout 入出 db.net.inets ãƒãƒƒãƒˆ ############################################################################## # # New circuit dialog box # db.newcirc.directory ディレクトリ db.newcirc.cap æ–°è¦å›žè·¯ db.newcirc.exp -begin- ç¾åœ¨ã®å›žè·¯ã®ç·¨é›†ã‚’ 辞ã‚ã¦ã€æ–°ã—ã„回路を 編集ã—始ã‚る。 -end- db.newcirc.file ファイルå db.newcirc.topname トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å ############################################################################## # Gate dialog box # @db.gate.tabwidth *80 db.gate.signam ãƒãƒƒãƒˆå db.gate.portnam ãƒãƒ¼ãƒˆå db.gate.iotype タイプ db.gate.bitw ビット幅 db.gate.cyclew サイクル幅 db.gate.phase フェーズ db.gate.duty デューティー db.gate.port ãƒãƒ¼ãƒˆ db.gate.bitws ビット db.gate.side サイド db.gate.gtype ゲート・タイプ db.gate.gname ゲートå db.gate.hidenam åå‰ã‚’éš ã™ db.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ db.gate.cpbreak クリティカル・パス分割点 db.gate.butstate スイッãƒçŠ¶æ…‹ db.gate.dipval DIP状態 db.gate.range ビット範囲 db.gate.memfilenam メモリ・ファイルå db.gate.modname 機能å db.gate.general 一般 db.gate.details 詳細 db.gate.text テキスト db.gate.ports ãƒãƒ¼ãƒˆ db.gate.delay é…延 db.gate.parameters パラメタ db.gate.stddelay 標準ã®é…延 db.gate.custdelay カスタムã®é…延 db.gate.catdiruse ãƒãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ db.gate.edit 編集 db.gate.delete 削除 db.gate.add 追加 db.gate.ff.type フリップフロップã®æ–¹ä½æ±ºå®š db.gate.ff.normal.hdr 普通 db.gate.ff.normal.exp -begin- データãŒå·¦ã‹ã‚‰å³ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.ff.reverse.hdr åå°„ db.gate.ff.reverse.exp -fillbegin- データãŒå³ã‹ã‚‰å·¦ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.cat.asc.hdr TODO: Ascending db.gate.cat.dec.hdr TODO: Decending db.gate.cat.asc.exp -fillbegin- TODO: Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- TODO: Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir ä¿¡å·æ–¹å‘ db.gate.cat.auto.hdr 自動 db.gate.cat.multin.hdr 多入力 db.gate.cat.singin.hdr 多出力 db.gate.cat.tran.hdr TODO: Bidirectional db.gate.cat.auto.exp -fillbegin- ä¿¡å·ã®æ–¹å‘を自動的 ã«åˆ¤æ–­ã™ã‚‹ã€‚ -end- db.gate.cat.multin.exp -fillbegin- TODO: Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- TODO: Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- TODO: Allow bidirectional (tran) signal flow. Cannot be connected to switches or registers. -end- db.gate.tab.General.cap 一般特徴 db.gate.tab.Ports.cap ãƒãƒ¼ãƒˆç‰¹å¾´ db.gate.tab.Delay.cap é…延特徴 db.gate.tab.Parameters.cap モジュール特徴 db.gate.tab.CLOCK.cap クロック特徴 db.gate.tab.SWITCH.cap スイッãƒç‰¹å¾´ db.gate.tab.DIP.cap DIP特徴 db.gate.tab.TAP.cap Tran特徴 db.gate.tab.RAM.cap RAM特徴 db.gate.tab.ROM.cap ROM特徴 db.gate.tab.MODULE.cap モジュール特徴 db.gate.tab.FRAME.cap フレーム特徴 db.gate.tab.LED.cap LED特徴 db.gate.tab.AND.cap AND特徴 db.gate.tab.OR.cap OR特徴 db.gate.tab.XOR.cap XOR特徴 db.gate.tab.MUX.cap Mux特徴 db.gate.tab.DEMUX.cap Demux特徴 db.gate.tab.CONCAT.cap Concat特徴 db.gate.tab.COMMENT.cap テキスト特徴 db.gate.tab.FF.cap フリップフロップ特徴 db.gate.tab.General.exp -fillbegin- TODO: View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- TODO: Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- TODO: Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- TODO: Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- TODO: Set detailed type-specific properties of a gate here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- TODO: Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter パラメタ db.gate.mparm.value 値 db.gate.mparm.exampleA -begin- ã“ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¯ãƒ‘ラメタを利用ã—ã¦ã„ãªã„。 パラメタã¯Verilogテキストã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã« 利用出æ¥ã‚‹ã€‚ã“ã®ãƒ€ã‚¤ã‚¢ãƒ­ã‚°ã§ã€ãã‚Œãžã‚Œã® パラメタã®å€¤ãŒè¨­å®šå‡ºæ¥ã‚‹ã€‚モジュール㮠パラメタを利用ã™ã‚‹ãŸã‚ã€ãƒ†ã‚­ã‚¹ãƒˆã®å®šç¾©ã« 「#ã€ã‹ã‚‰å§‹ã¾ã‚‹ãƒ‘ラメタã®ãƒªã‚¹ãƒˆã‚’書ã„㦠ãã ã•ã„。以下ã®ä¾‹é¡Œã§ã€ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®å€¤ãŒ 「1'b1ã€ã®ã€Œbase_valueã€ã¨ã„ã†ãƒ‘ラメタを æŒã¤ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãŒç¤ºã—ã¦ã‚る。 -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder 入力ã®é †åº db.gate.mux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.mux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.mux.ord1.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.ord2.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.dataorder 出力ã®é †åº db.gate.demux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.demux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.demux.ord1.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.ord2.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.select TODO: Selector Style db.gate.mux.sel1.hdr TODO: Selector on Left db.gate.mux.sel2.hdr TODO: Selector on Right db.gate.mux.sel1.exp -fillbegin- TODO: Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- TODO: Place the data selector on the right side of the gate. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse æ‹¡å¼µãƒãƒ¼ã‚’利用 db.gate.aox.use.hdr æ‹¡å¼µãƒãƒ¼ db.gate.aox.nouse.hdr æ‹¡å¼µãƒãƒ¼ã‚’利用ã—ãªã„ db.gate.aox.use.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LEDã®ã‚¿ã‚¤ãƒ— db.gate.led.bit.hdr ビット db.gate.led.bar.hdr 棒グラフ db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- TODO: Single-lamp LED display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- TODO: LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- TODO: Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- TODO: Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- TODO: Signal bits directly control LED segments. -end- db.seq.back <å‰ã¸ db.seq.next 次ã¸> db.hdl.savecap 複数ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« db.hdl.saveexp -fillbegin- TODO: The text buffer for the module you have just edited contains more than one module definition. Please select one of the three actions described on the right. -end- db.hdl.autoedit 自動変数 db.hdl.split 分離 db.hdl.comment コメント db.hdl.cancel キャンセル db.hdl.ignore 無視ã™ã‚‹ db.hdl.autoeditcap åå‰ãŒä¸€ç­‰ã—ãªã„ db.hdl.autoeditexp -fillbegin- TODO: The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- 回路ã«çµ„åˆã›ã®ãƒ«ãƒ¼ãƒ—ãŒç™ºè¦‹ã•ã‚ŒãŸã€‚クリティカル ・パスã®è§£æžã‚’è¡Œãªã„ãŸã‘ã‚Œã°ã€ãƒ«ãƒ¼ãƒ—上ã®ãƒãƒƒãƒˆ を切ã£ãŸã‚Šã€ãƒ«ãƒ¼ãƒ—上ã®ã‚²ãƒ¼ãƒˆã‚’「クリティカル・ パス分割点ã€ã«ã—ãŸã‚Šã™ã‚‹å¿…è¦ãŒã‚る。 -end- ############################################################################## # Print dialog box # print.outto 出力先 print.printer プリンター print.file ファイル print.prcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ print.prname プリンタ print.advanced オプション... print.filename ファイルå print.epssave Encapsulated Postscriptã¨ã—ã¦ã‚»ãƒ¼ãƒ–ã™ã‚‹. print.doctit ドキュメントã®é¡Œå print.epcm エãƒãƒƒã‚¯/cm print.estpg ページ数ã®è¦‹ç©ã‚‚ã‚Š print.all 全㦠print.cur ç¾åœ¨ print.use 使用中 print.sel 指定 print.inclib ライブラリ・ファイルもå°åˆ· print.papsz ページ・サイズ print.orient オリエンテーション print.portrait 縦 print.landscape 横 print.2side 両é¢å°åˆ· print.opts オプション print.scale 大ãã„モジュールをスケールã—ã¦ä¸€ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.partition 大ãã„モジュールを複数ã®ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.incidx インデックスをå«ã‚€ print.incgraph 階層グラフをå«ã‚€ print.4up å°ã•ã„モジュールを一é ã«å››ã¤ãšã¤å°åˆ·ã™ã‚‹ print.range レンジ print.scaleselect é¸æŠžç¯„囲をスケールã™ã‚‹ print.fulltr 全部 print.parttr 部分 print.start スタート print.end ストップ print.filesel ファイルã«å°åˆ· print.printersel プリンタã«å°åˆ· print.defaultprinter デフォルトã®ãƒ—リンタ print.pageset ページ・setup print.modulesel モジュールã®é¸æŠž ############################################################################## # # TkGate 2.0 print dialog strings # print.ok å°åˆ· print.printtrace.cap トレースã®å°åˆ· print.printcirc.cap 回路図ã®å°åˆ· print.printcirc.out.exp -begin- 回路図ã®å°åˆ·å…ˆãŒ プリンタã‹ãƒ•ã‚¡ã‚¤ãƒ« ã‹é¸æŠžã™ã‚‹ã€‚ -end- #probably not used print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã‚„å°åˆ·ã®æ§˜å­ã‚’é¸æŠž る。 -end- print.printtrace.trace.exp -fillbegin- 時間ã®ç¯„囲をé¸æŠžã™ã‚‹ã€‚ åˆã€ã‚¹ã‚±ãƒ¼ãƒ«ã«ã‚ˆã£ã¦ã€ å¿…è¦ã®ãƒšãƒ¼ã‚¸æ•°ã‚’表㋠評価ã™ã‚‹ã€‚ -end- print.tab.output å°åˆ·å…ˆ print.tab.page å°åˆ· print.tab.content 内容 ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 600 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 115 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 opt.general 一般 opt.interface インタフェース opt.toolbars ツール・ãƒãƒ¼ opt.editor HDL opt.print å°åˆ· opt.simulate シミュレート opt.library ライブラリ opt.analysis è§£æž opt.color 色 opt.html HTML opt.debug デãƒãƒƒã‚° opt.security セキュリティ opt.identity 正体 opt.site サイトå opt.username ユーザå opt.libname ライブラリå opt.inst インスタンス opt.mods モジュール opt.modports ãƒãƒ¼ãƒˆ opt.frames フレーム opt.comment コメント opt.hlink リンク opt.wire 1ビットã®ãƒ¯ã‚¤ãƒ¤ opt.bus 多ビットã®ãƒ¯ã‚¤ãƒ¤ opt.tools ツール opt.background ãƒãƒƒã‚¯ã‚°ãƒ©ã‚¦ãƒ³ãƒ‰ opt.cpath クリティカル・パス opt.grid スコープã®ã‚°ãƒªãƒƒãƒ‰ opt.logic1 è«–ç†ï¼‘ opt.logic0 è«–ç†ï¼ opt.float フロート opt.unknown ä¸æ˜Ž opt.offled オフã®LED opt.onled オンã®LED opt.zled フロートã®LED opt.restdef デフォールト opt.regudate リージョン・アップデート opt.smoothscroll スムーズ・スクロール opt.balloon ãƒãƒ«ãƒ¼ãƒ³ãƒ»ãƒ˜ãƒ«ãƒ—を利用 opt.safeSave 安全書ã込㿠opt.saveCells セーブファイルã«ã‚»ãƒ«ã‚’å«ã‚€ã€‚ opt.showimage TODO: Show side-bar images in dialog boxes opt.novice åˆå¿ƒè€…モード opt.blockDropConnect TODO: Wire drop port creation opt.ckpoint ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ opt.freq 期間 opt.beak 特別モードをå¯èƒ½ã«ã™ã‚‹ opt.bat ãƒãƒƒãƒˆãƒžãƒ³ opt.trek スター・トレック opt.miles マイルス opt.contver 内部構造ã®è‡ªå‹•ç¢ºèª opt.showsimcmd シミュレートã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ opt.estepsz エãƒãƒƒã‚¯ã®ã‚¹ãƒ†ãƒƒãƒ—æ•° opt.cstepsz クロックã®ã‚µã‚¤ã‚¯ãƒ«æ•° opt.overstep クロックã®ã‚ªãƒãƒ¼ã‚¹ãƒ†ãƒƒãƒ— opt.sorttraces TODO: Sort traces alphabetically on scope opt.vpopupdelay ä¿¡å·å€¤ã‚¦ã‚£ãƒ³ãƒ‰ã®è¡¨ç¤ºé…延 opt.initscript åˆæœŸåŒ–スクリプト opt.posedge å…¨ã¦ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.setclock 指定ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.delayfilepath é…延ファイル opt.devfilepath VPD(Virtual Periperal Device)ファイルã®ãƒ‘ス opt.vlibpath Verilogã®ãƒ©ã‚¤ãƒ–ラリã®ãƒ‘ス opt.vlibnames ベースã®ãƒ©ã‚¤ãƒ–ラリ opt.display ç”»é¢ opt.input 入力 opt.undolen 最大Undo opt.keybind キー・ãƒã‚¤ãƒ³ãƒ‡ã‚£ãƒ³ã‚°ã®ã‚¹ã‚¿ã‚¤ãƒ« opt.useless å½¹ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ opt.features 基本ã®æ©Ÿèƒ½ opt.simbase 基本ã®ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã®ã‚ªãƒ—ション opt.simclock クロックã®ã‚ªãƒ—ション opt.cpopts クリティカル・パス設定: opt.maxpath 最大パス数: opt.cpflash パスã®ç‚¹æ»…表示 opt.general.fontset フォント・サイズ opt.simulator.noglitch TODO: Enable simulator glitch suppression. opt.simulator.err TODO: Error Handling opt.simulator.stopany TODO: Cancel simulation on any warnings. opt.simulator.showall TODO: Always display warnings. opt.simulator.showiferr TODO: Display warnings only with errors. opt.simulator.ignore TODO: Ignore all warnings. opt.tool.file ファイル opt.tool.edit 編集 opt.tool.gateopt 回転ï¼æ•´åˆ—化 opt.tool.gateprop ゲート特徴 opt.tool.undo Undo/Redo opt.tool.zoom ズーム opt.tool.mode モード opt.tool.module モジュール opt.tool.tech テクノロジー opt.tool.simctl TODO: Simulator Control opt.tool.simaux TODO: Simulator Commands opt.tool.symmode モード opt.tool.symedit カットï¼ãƒšãƒ¼ã‚¹ãƒˆ opt.tool.symport ãƒãƒ¼ãƒˆ opt.tool.symshift ビット・マップã®ã‚·ãƒ•ãƒˆ opt.tool.symopr ビット・マップã®æ¼”ç®— opt.editor.features 基礎的ãªã‚¨ãƒ‡ã‚£ã‚¿ãƒ¼ã®æ©Ÿèƒ½ opt.editor.format 自動インデントを有効ã«ã™ã‚‹ opt.editor.colorize 自動色付ã‘を有効ã«ã™ã‚‹ opt.editor.comments コメント opt.editor.strings 文字列 opt.editor.reserved キーワード opt.editor.gateword ゲートå opt.editor.instword モジュールå opt.editor.taskword システム・タスク opt.editor.color 色 opt.editor.bold 太字 opt.editor.italic イタリック opt.editor.indentlevel TODO: Indentation per level: opt.editor.beginindent TODO: Make begin..end flush with enclosing level. opt.editor.movesel TODO: Enable drag-and-drop of selection. opt.editor.returntab TODO: Auto indent after return. opt.vercheck -begin- 定期的㫠tkgate ã®æ–°ã—ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã‚’インターãƒãƒƒãƒˆã§ ãƒã‚§ãƒƒã‚¯ã™ã‚‹ã€‚常時接続ã§ãªã‘ã‚Œã°æœ‰åŠ¹ã«ã—ãªã„ã“ã¨ã€‚ -end- opt.general.cap 一般オプション opt.editor.cap HDLテキスト・エディタ opt.interface.cap インタフェス・オプション opt.toolbars.cap ツールãƒãƒ¼ãƒ»ã‚ªãƒ—ション opt.print.cap å°åˆ·ã‚ªãƒ—ション opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap シミュレータ・オプション opt.security.cap セキュリティ・オプション opt.color.cap 色ã¥ã‘・オプション opt.html.cap HTML/HTTPオプション opt.debug.cap デãƒãƒƒã‚°ãƒ»ã‚ªãƒ—ション opt.library.cap ライブラリ・オプション opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.color.editwin 編集ウィンドウã®è‰²ã¥ã‘ opt.color.scopewin スコープ・ウィンドウã®è‰²ã¥ã‘ opt.vlibadd.cap ライブラリ追加 opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- TODO: Set personal identification and basic TkGate options here. The personal identification info. will be used on printed output. -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore ページã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ opt.bbar.restoreall å…¨ã¦ã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ ############################################################################## # # Interface generator # igen.port ãƒãƒ¼ãƒˆ igen.type タイプ igen.side サイド igen.size ビット幅 igen.bits ビット igen.modname モジュールå: igen.resort å†ã‚½ãƒ¼ãƒˆ igen.add 追加 igen.delete 削除 igen.edit 編集 igen.in å…¥ igen.out 出 igen.inout 入出 igen.left å·¦ igen.right å³ igen.top 上 igen.bottom 下 igen.other ä»– igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error スクリプトã®ã‚¨ãƒ©ãƒ¼ module.props モジュールã®ç‰¹å¾´ ipanel.plist ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ ipanel.props インタフェースã®ç‰¹å¾´ ipanel.itype.change タイプã®å¤‰æ›´... ipanel.itype.edsymbol シンプルã®ç·¨é›†... ipanel.block ブロック ipanel.symbol シンボル ipanel.autogen 自動作æˆ... ipanel.itype.select インタフェス・タイプ ipanel.itype.selectexp -begin- 長方形型ã®ã€Œãƒ–ロッ クã€ã‹ã€ãƒ“ットマッ プã®ã€Œã‚·ãƒ³ãƒœãƒ«ã€ã€ ã„ãšã‚Œã‹é¸æŠžã—㦠ãã ã•ã„。 -end- ipanel.block.description TODO: Block Interface ipanel.symbol.description TODO: Custom Symbol Interface ipanel.ppos.label ブロックã®ã‚µã‚¤ã‚ºã‚’変更ã™ã‚‹æ™‚ã®ãƒãƒ¼ãƒˆã®å–り扱ㄠipanel.ppos.fix 指定 ipanel.ppos.scale スケール ipanel.ppos.grid グリッド ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim å–å¾—ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.to æ–°è¦ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.from ç¾åœ¨ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.name モジュールå blklst.new.cap モジュールã®æ–°è¦ä½œæˆ blklst.del.cap 削除ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.copy.cap コピー・モジュール blklst.rename.cap モジュールã®æ”¹å blklst.claim.cap モジュールã®å–å¾— blklst.setroot.cap トップ・モジュールã®é¸æŠž blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label 探索 find.exp -fillbegin- ゲートåã€ãƒãƒƒãƒˆå〠コメントãªã©ã®ä¸­ã« 指定ストリングを 探索ã™ã‚‹ã€‚ -end- find.ignorecase ケースを無視ã™ã‚‹ã€‚ find.result.module モジュールå find.result.type タイプ find.result.name オブジェクトå # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options 探索ã®ã‚ªãƒ—ション find.results 探索ã®çµæžœ # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ã‚’å«ã‚€ find.qual.begins ã‹ã‚‰å§‹ã¾ã‚‹ find.qual.ends ã§çµ‚ã‚‹ find.qual.matches åŒç­‰ã™ã‚‹ find.dom.label 以下ã®å ´æ‰€ã‚’探索ã™ã‚‹ã€‚ find.dom.gates ゲート find.dom.nets ãƒãƒƒãƒˆ find.dom.text コメントã®ãƒ†ã‚­ã‚¹ãƒˆ find.search 探索: find.target 探索ã®ç¯„囲 # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label 回路ã®ç‰¹å¾´ circ.ident TODO: Identification circ.filev ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ circ.file ファイルå circ.title 回路å circ.discchg 変更を無視ã™ã‚‹ circ.extbar æ‹¡å¼µãƒãƒ¼ã‚’利用ã™ã‚‹ã€‚ circ.autostart シミュレーションã®è‡ªå‹•é–‹å§‹ã‚’有効ã«ã™ã‚‹ã€‚ circ.iniscript åˆæœŸåŒ–スクリプト circ.noscript スクリプト・ファイルã¯æŒ‡å®šã•ã‚Œã¦ã„ãªã„。 circ.really TODO: Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general 一般 circ.library ライブラリ circ.script スクリプト circ.simulator シミュレーション circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # # Library Manager # libmgr.cap ライブラリ・マãƒã‚¸ãƒ£ãƒ¼ libmgr.library ライブラリ libmgr.description TODO: Description libmgr.status TODO: Status libmgr.status.load TODO: Loaded libmgr.status.unload TODO: Not Loaded libmgr.status.loadp TODO: [Loaded] libmgr.status.unloadp TODO: [Not Loaded] libmgr.exp -fillbegin- TODO: Select libraries to be loaded or unloaded. -end- libmgr.load TODO: Load libmgr.unload TODO: Unload libmgr.unloadall TODO: Unload All libmgr.notedit -fillbegin- TODO: Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab ブレークãƒã‚¤ãƒ³ãƒˆ break.id ç•ªå· break.state 状 break.condition æ¡ä»¶ break.value 値 ############################################################################## # Simulator # sim.breakpt ブレークãƒã‚¤ãƒ³ãƒˆ sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay パスé…延: cp.pathl パスã®ä¸€è¦§: cp.numpath パス数: cp.recompute å†è¨ˆç®— ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin é¸æŠžã•ã‚ŒãŸãƒ”ンã®ã‚¿ã‚¤ãƒ—を変更出æ¥ãªã„。 err.badhex ä¸æ­£ã®16進数ã®å€¤ã¯ç„¡è¦–ã•ã‚ŒãŸã€‚ err.gatanchor ゲートãŒç§»å‹•ä¸å¯ã«ãƒžãƒ¼ã‚¯ã•ã‚Œã¦ã„る為ã€ç§»å‹•å‡ºæ¥ãªã„。 err.protdata TODO: Can not modify contents of protected or library module. err.badfind 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badopendel 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’削除出æ¥ãªã„。 err.nosrcmod ソース・モジュール'%s'ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.noerr エラー・メッセージãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.misserr エラー情報ãŒä¸å®Œå…¨ã§ã‚る。(シミュレータãŒè½ã¡ãŸï¼Ÿ) err.badinadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥åŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badinoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badpinchg é¸æŠžã®ã‚²ãƒ¼ãƒˆã®ãƒ”ンã®ã‚¿ã‚¤ãƒ—ãŒå¤‰æ›´å‡ºæ¥ãªã„。 err.badnetname åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為削除ã•ã‚ŒãŸã€‚ err.netbcrename 指定ã®åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為ã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfnet 指定ã®åå‰ãŒåˆ¥ã®åå‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfgat 指定ã®åå‰ãŒåŸºç¤Žã®ã‚²ãƒ¼ãƒˆåã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfkw 指定ã®åå‰ãŒã‚­ãƒ¼ãƒ¯ãƒ¼ãƒ‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.badconsame ãƒãƒƒãƒˆãŒåŒã˜ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconptsp ãƒãƒƒãƒˆã®ä¸¡æ–¹ãŒãƒãƒ¼ãƒˆåˆã¯é›»åŠ›ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconbitw ãƒãƒƒãƒˆã®ãƒ“ット幅ãŒç•°ãªã‚‹ã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badrange 指定ã•ã‚ŒãŸæ™‚é–“ã®ãƒ¬ãƒ³ã‚¸ãŒä¸æ­£ã§ã‚る。 err.badlprcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒå®Ÿè¡Œå‡ºæ¥ãªã„。 err.badpsopen ãƒã‚¹ãƒˆãƒ»ã‚¹ã‚¯ãƒªãƒ—トを「%sã€ã«æ›¸ãè¾¼ã‚ãªã„。 err.badid 「%sã€ã¯ä¸æ­£ã®åå‰ã§ã‚る。 err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp ä¸æ­£ãªãƒ–レークãƒã‚¤ãƒ³ãƒˆã®æ¡ä»¶ã§ã‚る。「netã€, 「!netã€, 「net==valueã€, 「net!=valueã€ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.bkpt.badnet ä¸æ­£ã®ãƒãƒƒãƒˆåã§ã‚る。 err.bkpt.badval ä¸æ­£ã®å€¤ã§ã‚る。10進数ã‚ã‚‹ã„ã¯ã€verilogå½¢å¼ã®å€¤ã—ã‹èªè­˜ã•ã‚Œã¦ã„ãªã„。 err.bkpt.toomany ブレークãƒã‚¤ãƒ³ãƒˆãŒå¤šéŽãŽã‚‹ã€‚制é™ã¯%dã§ã‚る。 err.sim.badtmp /tmpã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ›¸ãè¾¼ã‚ãªã‹ã£ãŸï¼ˆãƒ‡ã‚£ã‚¹ã‚¯ãŒã„ã£ã±ã„ã‹ï¼‰ã€‚ err.sim.syntx ä¸æ­£ã®ã€Œ%sã€ã‚³ãƒžãƒ³ãƒ‰ err.sim.noincl インクルード・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ err.sim.badedge clockコマンドã®ã‚¨ãƒƒã‚¸'%c'ãŒä¸æ­£ã§ã‚る。 err.sim.nobkpt ブレーク・ãƒã‚¤ãƒ³ãƒˆã€Œ%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.sim.nonet ãƒãƒƒãƒˆã€Œ%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.nogate ゲート「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.badbin 2進数ã®å€¤ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る。 err.sim.notswitch ゲート'%s'ã¯ã‚¹ã‚¤ãƒƒãƒã€DIPã€ãƒ¬ã‚¸ã‚¹ã‚¿ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.sim.badcmd シミュレーション・スクリプトã«ä¸æ­£ã®ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒã‚る。 err.sim.isrun シミュレータã¯æ—¢ã«å®Ÿè¡Œã—ã¦ã„る。 ('Ctrl-s e'ã§çµ‚了ã™ã‚‹). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg 設定ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ä»¥å¤–ã€å¤‰æ›´ä¸å¯ã€‚ err.badeditop 編集コマンドã«ä¸æ­£ãŒã‚る。 err.badopen 回路ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badlibopen ライブラリ・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.nomark ゲート種をé¸ã¶å‰ã«ã€ãƒžã‚¦ã‚¹ã§ä½ç½®ã‚’設定ã—ã¦ãã ã•ã„。 err.badgate ゲート種ãŒæœªå®šç¾©ã§ã‚る。 err.badportadd é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã¯è¿½åŠ ä¸å¯ã€‚ err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- ページ数ãŒæ¥µã‚ã¦å¤§ãã„。 本当ã«å°åˆ·ã—ã¾ã™ã‹? -end- err.nojump -fillbegin- ç¾åœ¨ã€'jump-to-module'機能ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ç”¨å‡ºæ¥ãªã„。 トップ・モジュールよりã€ã€Œ>ã€ã‚„「<ã€ã®ã‚³ãƒžãƒ³ãƒ‰ã§ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã‘ã¦ãã ã•ã„。 -end- err.nomod モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.modlock モジュールãŒãƒ­ãƒƒã‚¯ã—ã¦ã„る。 err.closeroot トップ・モジュールãŒé–‰ã˜ã‚Œãªã„。 err.editonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ãˆãªã„。 err.simonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ã—ã‹ä½¿ãˆãªã„。 err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel ゲートをé¸æŠžã—ã¦ã„ãªã„。 err.modnotdef モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.moddef モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã—ã¦ã„る。 err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã¯ç·¨é›†å‡ºæ¥ã‚‹è¨­å®šãŒãªã„。 err.openscript シミュレーション・スクリプト「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.oldversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³(%s)ãŒå¤ã„。(ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s). err.futureversion 未æ¥ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ï¼ˆ%s）ã®tkgateファイルã§ã‚る。（ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s） err.badversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒèªè­˜å‡ºæ¥ãªã„。注æ„ã—ã¦åˆ©ç”¨ä¸‹ã•ã„。 err.nodrive ãƒãƒƒãƒˆ%sã¯ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«%sã«ä¿¡å·ã®ã‚½ãƒ¼ã‚¹ãŒãªã„。 err.noconn ワイヤ%s{%d}ã¯æŽ¥ç¶šãŒãªã„（削除ã—ãŸï¼‰ã€‚ err.oldportact ãƒãƒ¼ãƒˆã‚„モジュールã®ç«¯ã«å³ã‚¯ãƒªãƒƒã‚¯ã—ã¦ä¸‹ã•ã„。 err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail ãƒãƒƒã‚¯ã‚¢ãƒƒãƒ—・ファイル'%s'ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã€‚ err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TkGateã¯'%s'ã«ã‚»ãƒ¼ãƒ–出æ¥ãŸãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ··ä¹±ã•ã‚Œã¦ã„ã‚‹ã¿ãŸã„。もã—ãƒã‚§ãƒƒ ク・ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’使ã£ã¦ã¿ã¦ã ã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.corruptsave -fillbegin- '%s'をセーブã—よã†ã¨ã—ã¦ã„る時ã€TkGateã«å†…部å•é¡ŒãŒç™ºè¦‹ã—ãŸã€‚元々ã®ãƒ•ã‚¡ã‚¤ ルã¯ãã®ã¾ã¾æ®‹ã—ã¦ã‚る。混乱ã•ã‚Œã¦ã„ã‚‹å¯èƒ½æ€§ã®ã‚るファイルã¯'%s'ã«ã‚»ãƒ¼ãƒ– ã—ãŸã€‚ã‚‚ã—ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ ルを使ã£ã¦ã¿ã¦ãã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.badsave -fillbegin- '%s'をセーブ出æ¥ãªã‹ã£ãŸã€‚ファイルã®ãƒ—ロテクションや空ãディスクé‡ã‚’ç¢ºèª ã—ã¦ãã ã•ã„。 -end- err.nosafesave -fillbegin- '%s'ã®å®‰å…¨ã‚»ãƒ¼ãƒ–ã‚’è¡Œã†ãŸã‚ã®ä¸€æ™‚ã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã‹ã‚‰ã€ç›´æŽ¥ã‚»ãƒ¼ ブã—ãªãã¦ã¯ãªã‚‰ãªã„。「NOã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€å…ƒã€…ã®ãƒ•ã‚¡ã‚¤ãƒ«ã¯ãã®ã¾ã¾æ®‹ ã™ã€‚「YESã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€ã‚»ãƒ¼ãƒ–ã™ã‚‹ãŒã€ã‚»ãƒ¼ãƒ–途中ã«å•é¡ŒãŒèµ·ã“ã£ãŸã‚‰ã€ 回路データãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚る。直接セーブã—ã¦ã¿ã¾ã—ょã†ã‹ã€‚ -end- err.noback -fillbegin- tkgateãƒãƒ¼ã‚¸ãƒ§ãƒ³%sã§ä½œã‚‰ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ã§ã‚る。ä¿å­˜ã™ã‚‹ã¨ã€ tkgateã®å¤ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã«èª­ã¿è¾¼ã‚ãªã„ã“ã¨ãŒã‚る（ç¾åœ¨ã® ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%sã§ã‚る）。 -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selgate %2$sã¨ã„ã†%1$sゲートãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selblock %2$sã¨ã„ã†%1$sモジュールãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã•ã‚Œã¦ã„る。定義ã—ãªãŠã—ã¾ã™ã‹? msg.foundgate %sã¨ã„ã†ã‚²ãƒ¼ãƒˆãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.foundwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.searchagn 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ã‚‚ã†ä¸€åº¦ã€ŒæŽ¢ç´¢ã€ã‚’押ã™ã¨ã€æŽ¢ç´¢ã—ãªãŠã™ã€‚ msg.sim.chgtoroot シミュレーション・モードã§ã¯ã€ãƒˆãƒƒãƒ—・モジュールãŒãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ã®ãƒˆãƒƒãƒ—ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 msg.sim.nogatemod シミュレーション・モードã§ã€å…·ä½“çš„ãªãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ãŒå¿…è¦ã§ã‚る。 msg.setinterface モジュール「%sã€ã®ã‚¤ãƒ³ã‚¿ãƒ•ã‚§ãƒ¼ã‚¹ã‚’セットã—ãŸã€‚ msg.needsel モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ã‚’é¸ã‚“ã§ãã ã•ã„。 msg.wroteckpt 「%sã€ã«ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆã‚’書ã込んã ... msg.save 「%sã€ã«ä¿å­˜ã—ãŸã€‚ msg.reallynew 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€æ–°ã—ã„回路を開ãã¾ã™ã‹? msg.reallyquit 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€çµ‚了ã—ã¾ã™ã‹? msg.notlib モジュール「%sã€ã¯ãƒ©ã‚¤ãƒ–ラリ・モジュールã§ã¯ãªã„。 ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€ãŠå‰ã¿ãŸã„ãªå¤§é¦¬é¹¿ã—ã‹ã„ãªã„よ。 miles.msg2 é¦¬é¹¿ï¼ miles.msg3 æ„šã‹ã‚‚ã®ï¼ miles.msg4 マイルスã€ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€é¦¬é¹¿ã ã‚ˆã€‚ miles.msg5 馬鹿ãªã‚²ãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ã‚’ã‚„ã‚ã¦ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg6 ゲートをãã®ä½ç½®ã«ãŠã„ãŸã®ã¯ã€ãŠå‰ã®æ„šã‹ã•ã®è¨¼æ˜Žã ã‚ˆã€‚ miles.msg7 ã“ã®ãƒ­ã‚¯ã§ãªã—回路ã®è¨­è¨ˆã‚’諦ã‚よã€ãƒžã‚¤ã‚¹ãƒ«ã€‚ miles.msg8a 続ã‘ã¦ã‚‚ã€ç„¡é§„ã ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg8b ãŠå‰ãŒå›žè·¯ã‚’設計出æ¥ãªã„ã¨ã„ã†ã®ã¯ã€èª°ã§ã‚‚分ã‹ã‚‹ã‚ˆã€‚ ############################################################################# # # Error messages generated by verga # verga.err.OK 心é…ã—ãªã„ã§ã€ç¬‘ã£ã¦ãã ã•ã„。 verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # Balloon Help # ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ç¾åœ¨ã®å›žè·¯ã‚’消ã—ã¦ã€æ–°ã—ㄠ回路を作æˆã™ã‚‹ã€‚ -end- ho.open 回路ファイルを開ã ho.save 回路ファイルをä¿å­˜ã™ã‚‹ ho.saveas TODO: Save circuit to specified file. ho.print 回路ファイルをå°åˆ·ã™ã‚‹ ho.library TODO: Open the library manager. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- 移動ï¼æŽ¥ç¶š - ã“ã®ãƒ„ールã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ æ–°ã—ã„ゲートã®ä½ç½®ã‚’設定ã™ã‚‹ ゲートを移動ã™ã‚‹ ワイヤを移動ã™ã‚‹ ワイヤを接続ã™ã‚‹ ダブル・クリックã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ ゲートã®å±žæ€§ã‚’編集ã™ã‚‹ ワイヤã®å±žæ€§ã‚’編集ã™ã‚‹ ãƒãƒ¼ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ コメントã®ãƒ†ã‚­ã‚¹ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ -end- ho.delgat -begin- ã“ã®ãƒ„ールã§ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ -end- ho.cutw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã‚’切断ã™ã‚‹ -end- ho.inv -begin- ã“ã®ãƒ„ールã§ã€ã‚²ãƒ¼ãƒˆã®å…¥å‡ºåŠ›ã« å¦å®šã‚’付ã‘ãŸã‚Šã€æ¶ˆã—ãŸã‚Šã™ã‚‹ã€‚ -end- ho.bitw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã®ãƒ“ット幅を 変更ã™ã‚‹ã€‚ビット幅をå³ä¸‹ã®å…¥åŠ› ボックスã«å…¥åŠ›ã—ã¦ãã ã•ã„。 -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open é¸æŠžã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã ho.mod.close ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‰ã˜ã‚‹ ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo 最近行ã£ãŸå¤‰åŒ–を元通りã«ã™ã‚‹ã€‚ ho.redo undoã—ãŸå¤‰åŒ–ã‚’ã‚„ã‚Šç›´ã™ã€‚ ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- シミュレータを開始ã—ã€è«–ç†ã‚¢ãƒŠãƒ©ã‚¤ã‚¶ã®ã‚¦ã‚£ãƒ³ãƒ‰ã‚’ é–‹ãã€ãã—ã¦åˆæœŸåŒ–スクリプトãŒå®šç¾©ã—ã¦ã„ã‚‹å ´åˆã€ ãã®ã‚¹ã‚¯ãƒªãƒ—トを実行ã™ã‚‹ã€‚ -end- ho.tab.cpath -begin- 回路ã®ã‚¯ãƒªãƒ†ã‚£ã‚«ãƒ«ãƒ»ãƒ‘スを探索ã™ã‚‹ã€‚ -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- シミュレータを動ã‹ã™ã€‚組åˆã›å›žè·¯ã®å ´åˆã€ ä¿¡å·ãŒå¤‰ã‚らãªããªã‚‹æ™‚ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ ãŒä¸€æ™‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.simpause -begin- シミュレータã®ä¸€æ™‚åœæ­¢ -end- ho.simstep -begin- シミュレータを一定数ã®ã‚¨ãƒãƒƒã‚¯ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simclock -begin- シミュレータを一定数ã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚µã‚¤ã‚¯ãƒ« ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simstop -begin- シミュレータをåœæ­¢ã—ã¦ã€ 編集モードã«æˆ»ã‚‹ã€‚ -end- ho.simbreak -begin- シミュレータã®ãƒ–レークãƒã‚¤ãƒ³ãƒˆ を編集ã™ã‚‹ã€‚ -end- ho.simexec -begin- スクリプトを実行ã™ã‚‹ã€‚ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- メモリ・ファイルを読ã¿è¾¼ã‚€ -end- ho.simdump -begin- メモリ・ファイルã«æ›¸ã出㙠-end- ho.f.modlist -begin- 読ã¿è¾¼ã‚“ã§ã‚るモジュールã®ä¸€è¦§è¡¨ã€‚ トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®åå‰ã«ã€Œ+ã€ãŒ 付ã„ã¦ã„る。ライブラリã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã¯æ‹¬å¼§ã«å›²ã¾ã‚Œã¦ã„る。 -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ä¸€è¦§è¡¨ã€‚åå‰ã‚’éš ã—㦠ã„ã‚‹ãƒãƒƒãƒˆã®åå‰ã«ã€Œ@ã€ãŒä»˜ã„ã¦ã„る。 マルãƒãƒ»ãƒ“ットã®ãƒãƒƒãƒˆã®åå‰ã®å¾Œã« ビットã®ãƒ¬ãƒ³ã‚¸ã‚’表示ã—ã¦ã„る。 -end- ho.ports -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ã€‚ 入力ã«ã€Œ>ã€ã€å‡ºåŠ›ã«ã€Œ<ã€ã€å…¥å‡ºåŠ›ã« 「=ã€ãŒä»˜ã„ã¦ã„る。 -end- ho.status.logo -begin- ç¾åœ¨ã®ãƒ¢ãƒ¼ãƒ‰ãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。鉄ã®ã‚²ãƒ¼ãƒˆ ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ã‚’表ã™ã€‚ANDゲートã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ ション・モードを表ã™ã€‚ANDゲートãŒèµ°ã£ã¦ ã„る時ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ãŒå‹•ã„ã¦ã„る。 -end- ho.status.msg tkgateよりã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ãŒã“ã“ã«è¡¨ç¤ºã•ã‚Œã‚‹ã€‚ ho.status.block ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒ‘ス ho.status.file -begin- ç¾åœ¨ç·¨é›†ä¸­ã®ãƒ•ã‚¡ã‚¤ãƒ«åãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。「*〠ã¨ã„ã†è¨˜å·ãŒã¤ã„ã¦ã„る時ã€ä¿å­˜ã—ã¦ã„ãªã„変更 ãŒã‚る。 -end- ho.print.selall å…¨ã¦ã®èª­ã¿è¾¼ã‚“ã§ã„るモジュールをå°åˆ·ã™ã‚‹ã€‚ ho.print.selcur ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ ho.print.seluse -begin- 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿å°åˆ·ã™ã‚‹ã€‚ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- 以下ã«ãƒžãƒ¼ã‚¯ã—ã¦ã„るモジュールã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ コントロール・キーã§è¤‡æ•°ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠž 出æ¥ã‚‹ã€‚ -end- ho.print.modlist å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠžã™ã‚‹ã€‚ ho.circuit.discchg -begin- 有効ã«ã™ã‚‹ã¨ã€å¤‰æ›´ã‚ã‚Šã®å›žè·¯ã‚’ ä¿å­˜ã—ãªã„ã§é–‰ã˜ã‚‹ã¨ã警告ã—ãªã„。 -end- ho.circuit.extbar -begin- 基本ゲート(AND, OR, XOR)ã®å…¥åŠ›æ•°ãŒ 3本以上ã®æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã™ã‚‹ã€‚ -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- カーソルã§é¸æŠžã•ã‚ŒãŸãƒ¯ã‚¤ãƒ¤ã¯è¡¨ç¤º ã•ã‚Œã¦ã„るビット幅ã«è¨­å®šã•ã‚Œã‚‹ã€‚ -end- ho.edgat.signam -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã§ã‚る。åå‰ãŒå¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.port -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆåã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.iolab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆæ–¹å‘ã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.bitlab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒ“ット幅ã§ã‚る。変更出æ¥ã‚‹ã€‚ -end- ho.edgat.cycle 一サイクルã®ã‚¨ãƒãƒƒã‚¯æ•° ho.edgat.phase クロックã®ãƒ•ã‚§ãƒ¼ã‚ºï¼ˆãƒ‘ーセントã§è¨­å®šã™ã‚‹ï¼‰ ho.edgat.duty クロック・サイクルã®ä½•ãƒ‘ーセントãŒè«–ç†0ã§ã‚ã‚‹ã‹ ho.edgat.hide -begin- 有効ã«ã™ã‚‹ã¨ã‚²ãƒ¼ãƒˆåãŒè¡¨ç¤ºã•ã‚Œãªã„。 -end- ho.edgat.gtype ゲートã®ç¨®é¡ž ho.edgat.gname ゲートã®åå‰ ho.edgat.ganchor 有効ã«ã™ã‚‹ã¨ã€ã‚²ãƒ¼ãƒˆãŒç§»å‹•ä¸å¯ã«ãªã‚‹ã€‚ ho.edgat.gx ゲートã®Xä½ç½® ho.edgat.gy ゲートã®Yä½ç½® ho.edgat.swstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.dipstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.range マルãƒãƒ“ットã®ä¿¡å·ã®ã‚µãƒ–・レンジã§ã‚る。 ho.edgat.memfile -begin- メモリã®åˆæœŸã®å€¤ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’指定ã™ã‚‹ã€‚ シミュレーションを始ã‚る時ã€ã“ã®ãƒ•ã‚¡ã‚¤ãƒ« ãŒèª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.edgat.func モジュールã®æ©Ÿèƒ½ ho.edgat.frame フレームã®ãƒ©ãƒ™ãƒ« ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undoã®ãƒªã‚¹ãƒˆã®é•·ã• -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- 回路ãªã©ã‚’å°åˆ·ã™ã‚‹æ™‚ã€ã“ã®ã‚µã‚¤ãƒˆåãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.smooth -begin- ã“ã®è¨­å®šã‚’有効ã«ã™ã‚‹ã¨ã€å›žè·¯ã‚’スクロールã™ã‚‹æ™‚〠ビットマップã®ã‚³ãƒ”ーを利用ã—ã¦ã€åŠ¹çŽ‡ã‚ˆã スクロールã§ãる。Xサーãƒã®å•é¡ŒãŒã‚ã‚Œã°ã€ã“㮠設定を無効ã«ã™ã‚Œã°è‰¯ã„。 -end- ho.opt.clip -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¦ã‚¤ãƒ³ãƒ‰ã‚¦ã®éƒ¨åˆ†é ˜åŸŸã® å†æ画を行ãªã†ã€‚ãã†ã§ãªã‘ã‚Œã°å¸¸ã« 全領域をå†æç”»ã™ã‚‹ã€‚ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’移動ã™ã‚‹æ™‚〠ワイヤãªã©ã¯ãƒžã‚¦ã‚¹ã®ãƒœã‚¿ãƒ³ã‚’離ã™ã¾ã§ 移動ã—ãªã„。画é¢ã®è¡¨ç¤ºãŒé…ã„時ã«ä¾¿åˆ©ã§ã‚る。 -end- ho.opt.bhelp -begin- 有効ã«ã™ã‚‹ã¨ã€ã“ã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ã®æ§˜ãªã€Œãƒ˜ãƒ«ãƒ—・ ãƒãƒ«ãƒ¼ãƒ³ã€ãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.novice -begin- 有効ã«ã™ã‚‹ã¨ã€åˆå¿ƒè€…モードã«ãªã‚‹ã€‚ åˆå¿ƒè€…モードã§ã¯ã€tkgateãŒç«‹ã¡ä¸ŠãŒã‚‹æ™‚〠ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ«ãŒè‡ªå‹•çš„ã«èª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ‡ãƒã‚°æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ 開発者以外ã«ã€ã‚ã¾ã‚Šå½¹ã«ç«‹ãŸãªã„。 -end- ho.opt.ckpt 有効ã«ã™ã‚‹ã¨ã€tkgateã¯ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’作る。 ho.opt.ckptfreq ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã‚’何クリック毎ã«è¡Œãªã†ã‹ ho.opt.beak -begin- 全然役ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ã€‚ã“ã®æ©Ÿèƒ½ã‚’ 無効ã«ã™ã‚‹ã¨ã€ã“ã®ã‚¹ã‚¤ãƒƒãƒã¯ãƒ€ã‚¤ã‚¢ãƒ­ã‚° ボックスã‹ã‚‰æ¶ˆãˆã€.tkgate-propertiesを編集ã—ãªã„é™ã‚Š 戻らãªã„。 -end- ho.opt.miles -begin- 有効ã«ã™ã‚‹ã¨ã€tkgateã¯æ™‚々ユーザを 馬鹿ã«ã—ãŸã‚Šã€æ‚ªå£ã‚’言ã£ãŸã‚Šã™ã‚‹ã€‚ -end- ho.opt.bat -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒãƒƒãƒˆãƒžãƒ³ã®ã‚³ãƒ³ãƒ”ュータを 設計ã™ã‚‹ç‚ºã«ã€Œå½¹ã«ãŸã¤ã€æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ -end- ho.opt.trek 転é€ã—ã‚ã€ã‚¹ã‚³ãƒƒãƒ†ã‚£ï¼ ho.opt.simstep -begin- シミュレータã®ã‚¹ãƒ†ãƒƒãƒ—・コマンド㧠何エãƒãƒƒã‚¯é€²ã‚€ã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckstep -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ã‚¹ãƒ†ãƒƒãƒ—・ コマンド㧠何サイクル進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckover -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ クロックã®ã‚¨ãƒƒã‚¸ã‚ˆã‚Šæ›´ã«ä½•ã‚¨ãƒãƒƒã‚¯ 進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.vpopupdelay -begin- マウスボタンを押ã—ã¦ã‹ã‚‰ã€ä½•ãƒŸãƒªç§’経ã£ã¦ ã‹ã‚‰ä¿¡å·ã®å€¤ãŒè¡¨ç¤ºã•ã‚Œã‚‹é…延ã§ã‚る。 ã“ã® é…延ãŒçŸ­éŽãŽã‚‹æ™‚ã€ãƒ€ãƒ–ルクリック㌠èªçŸ¥ ã§ããªããªã‚‹å•é¡ŒãŒã‚るシステム㯠ã‚る。 ã“ã®å•é¡ŒãŒèµ·ã“らãªã‘ã‚Œã°ã€é…延 をより 短ãã—ã¦ã‚‚良ã„。 -end- ho.opt.init -begin- シミュレータを立ã¡ä¸Šã’る時㫠自動的ã«å®Ÿè¡Œã™ã‚‹ã‚¹ã‚¯ãƒªãƒ—ト・ ファイルを指定ã™ã‚‹ã€‚ -end- ho.opt.ckall -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ ã©ã®ã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã§ã‚‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.ckspec -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ 指定ã—ãŸã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã®ã¿ã«åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- æ–°ã—ã„ゲートã®ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ã€‚ ゲートã®é…延ã«å½±éŸ¿ã™ã‚‹ã€‚ä»»æ„ã®ã‚²ãƒ¼ãƒˆ 㮠テクノロジーを変更ã™ã‚‹ã«ã¯ã€ã‚²ãƒ¼ãƒˆã®è¨­å®š ボックスを開ã„ã¦ã€ã€Œé…延ã€ã®ã‚¿ãƒ– ã‚’é¸æŠž ã—ã¦ä¸‹ã•ã„。 -end- ho.techbut -begin- 指定ã—ãŸãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ãƒ»ãƒ•ã‚¡ã‚¤ãƒ«ã‹ã‚‰ã® é…延値を 利用ã™ã‚‹ã€‚æ–°ã—ã„テクノロジーを 追加ã™ã‚‹ç‚ºã€ã€Œãƒ•ã‚¡ã‚¤ãƒ«ã€â†’「設定...ã€â†’ 「シミュレート〠ã®ãƒ¡ãƒ‹ãƒ¥ãƒ¼ã‚’é–‹ã„ã¦ã€ ファイルã®ãƒªã‚¹ãƒˆã«è¿½åŠ  ã—ã¦ä¸‹ã•ã„。 -end- ho.custbut -begin- ã“ã®ã‚²ãƒ¼ãƒˆå°‚用ã®é…延値を指定ã™ã‚‹ã€‚ -end- ho.contver -begin- マウスæ“作を行ãªã†æ™‚ã€å†…部構造を自動的㫠確èªã—ã¦ã€ä¸æ­£ã®æ‰€ã‚’知らã™ã€‚ -end- ho.simwatch -begin- シミュレータã¨GUIã®é–“ã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ã€‚ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin ズーム・イン ho.tool.zoomout ズーム・アウト ho.tool.rotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’éžæ™‚計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.brotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’時計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.valgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’縦ã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.halgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ç¿Œã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.cut é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚«ãƒƒãƒˆã™ã‚‹ã€‚ ho.tool.copy é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚³ãƒ”ーã™ã‚‹ã€‚ ho.tool.paste カットãƒãƒƒãƒ•ã‚¡ã®ã‚²ãƒ¼ãƒˆã‚’張り付ã‘る。 ho.tool.find ゲートã€ãƒ¯ã‚¤ãƒ¤ã€ãƒ†ã‚­ã‚¹ãƒˆãªã©ã‚’探索ã™ã‚‹ã€‚ ho.tool.addport é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã‚’追加ã™ã‚‹ã€‚ ho.tool.anchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動ä¸å¯ã«ã™ã‚‹ã€‚ ho.tool.unanchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動å¯èƒ½ã«ã™ã‚‹ã€‚ ho.tool.replicate ゲートを複製ã™ã‚‹ã€‚ ho.tool.delete é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ã€‚ tkgate-2.0-b10/locale/ja/oldmessages.euc000644 001751 001751 00000070753 10624732615 020665 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Tue May 22 23:31:25 2007 ############################################################################## # # Japanese messages file (should be EUC encoded) # # NOTE: The messages file should not be edited directly. Please edit # the message.euc and/or messages.utf8 files. The messages file # will be overwritten by the either the .euc or .utf8 file when doing # a configure. # # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages # ############################################################################## ############################################################################## # # basic strings # b.dismiss ÊĤ¸¤ë b.close ÊĤ¸¤ë b.clear ¥¯¥ê¥¢ b.ok £Ï£Ë b.cancel ¥­¥ã¥ó¥»¥ë b.open ³«¤¯ b.bitw ¥Ó¥Ã¥ÈÉý b.in Æþ b.out ½Ð b.inout Æþ½Ð b.browse ÁªÂò... b.label ̾Á° b.find õº÷ b.edit ÊÔ½¸... b.add ÄɲÃ... b.delete ºï½ü b.deleteb ºï½ü... b.apply ¥»¥Ã¥È b.anchor °ÜÆ°ÉÔ²Ä b.tech ¥Æ¥¯¥Î¥í¥¸¡¼ ############################################################################## # # Main tab strings # tab.edit ÊÔ½¸ tab.editintr ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ tab.simulate ¥·¥ß¥å¥ì¡¼¥È tab.cpath ÃÙ±ä²òÀÏ ############################################################################## # Menu strings # menu.file ¥Õ¥¡¥¤¥ë menu.edit ÊÔ½¸ menu.tool ¥Ä¡¼¥ë menu.simulate ¥·¥ß¥å¥ì¡¼¥È menu.module ¥â¥¸¥å¡¼¥ë menu.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.gate ¥²¡¼¥È menu.make ºîÀ® menu.circ ²óÏ© menu.help ¥Ø¥ë¥× menu.file.new ¿·µ¬ºîÀ® menu.file.open ³«¤¯... menu.file.openlib ¥é¥¤¥Ö¥é¥ê¤ò³«¤¯... menu.file.save Êݸ menu.file.saveas ̾Á°¤òÉÕ¤±¤ÆÊݸ... menu.file.print °õºþ... menu.file.options ÀßÄê... menu.file.quit ½ªÎ» menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut ÀÚ¤ê¼è¤ê menu.edit.copy ¥³¥Ô¡¼ menu.edit.paste Ä¥¤êÉÕ¤± menu.edit.selall Á´¤Æ¤òÁªÂò menu.edit.find ²óÏ©¤òõº÷... menu.edit.algnv ½Ä¤Î°ìÎó menu.edit.algnh ²£¤Î¡¼Îó menu.edit.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.edit.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.tool.move °ÜÆ°¡¿Àܳ menu.tool.delg ¥²¡¼¥È¤Îºï½ü menu.tool.cutw ¥ï¥¤¥ä¤ÎÀÚÃÇ menu.tool.inv ÈÝÄê menu.tool.bitw ¥Ó¥Ã¥ÈÉý menu.tool.debug ¥Ç¥Ð¥Ã¥° menu.tool.rot0 0ÅÙ²óž menu.tool.rot90 90ÅÙ²óž menu.tool.rot180 180ÅÙ²óž menu.tool.rot270 270ÅÙ²óž menu.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï menu.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» menu.simulate.run ¥é¥ó menu.simulate.pause °ì»þ¥¹¥È¥Ã¥× menu.simulate.step ¥¹¥Æ¥Ã¥×(¥¨¥Ý¥Ã¥¯) menu.simulate.cycle ¥¹¥Æ¥Ã¥×(¥µ¥¤¥¯¥ë) menu.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤ÎÀßÄê... menu.simulate.script ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô... menu.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.simulate.dump ¥á¥â¥ê¤Î½ñ¤­½Ð¤·... menu.simulate.adprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.module.open ³«¤¯ menu.module.close ÊĤ¸¤ë menu.module.seti ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÀßÄê menu.module.editi ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸... menu.module.new ¿·µ¬ºîÀ®... menu.module.del ºï½ü... menu.module.copy ¥³¥Ô¡¼... menu.module.rename ̾Á°¤ÎÊÔ½¸... menu.module.claim ¼èÆÀ... menu.module.setroot ¥ë¡¼¥È¤Ë¤¹¤ë... menu.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÀßÄê... menu.circ.prop ²óÏ©¤ÎÀßÄê... menu.circ.cpath ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹... menu.gate.addin ÆþÎϤòÄɲà menu.gate.addout ½ÐÎϤòÄɲà menu.gate.addinout Æþ½ÐÎϤòÄɲà menu.gate.iochg ¥Ô¥ó¡¦¥¿¥¤¥×¤ÎÊѹ¹ menu.gate.anchor ÁªÂò¤ò°ÜÆ°ÉԲĤˤ¹¤ë menu.gate.unanchor ÁªÂò¤ò°ÜÆ°²Ä¤Ë¤¹¤ë menu.gate.prop ¥²¡¼¥È¤ÎÀßÄê... menu.gate.rep Ê£À½ menu.gate.del ºï½ü menu.gate.settech ¥Æ¥¯¥Î¥í¥¸¡¼¤ÎÀßÄê menu.help.about tkgate¤Ë¤Ä¤¤¤Æ... menu.help.license ¥é¥¤¥»¥ó¥¹... menu.help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... menu.help.tut ¥Á¥å¡¼¥È¥ê¥¢¥ë menu.help.example ²óÏ©¤ÎÎã menu.help.example.comb Áȹ礻²óÏ© menu.help.example.3bit 3¥Ó¥Ã¥È¤Î¥«¥¦¥ó¥¿¡¼ menu.help.example.8bit 8¥Ó¥Ã¥È¤Î¥«¥¦¥ó¥¿¡¼ menu.help.example.trff ¥È¥é¥ó¥¸¥¹¥¿¡¦¥ì¥Ù¥ë¤ÎFF menu.help.example.cpu Menagerie CPU menu.help.tut.welcome tkgate¤Î¾Ò²ð menu.help.tut.create ´ðËܤλȤ¤Êý menu.help.tut.edit1 ²óÏ©¤ÎÊÔ½¸(1) menu.help.tut.edit2 ²óÏ©¤ÎÊÔ½¸(2) menu.help.tut.mods ¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý menu.help.tut.sim ¥·¥ß¥å¥ì¡¼¥¿¤Î»È¤¤Êý pop.wire.addseg ¥ï¥¤¥ä¤ÎÄɲà gm.io I/O gm.gate ¥²¡¼¥È gm.rgate ñ¹à½ÌÌ󥲡¼¥È gm.msi MSI gm.alu ALU gm.mem ¥á¥â¥ê¡¼ gm.mod ¥â¥¸¥å¡¼¥ë gm.comment ¥³¥á¥ó¥È gm.frame ¥Õ¥ì¡¼¥à gm.io.switch ¥¹¥¤¥Ã¥Á gm.io.dip DIP¥¹¥¤¥Ã¥Á gm.io.ground ¥¢¡¼¥¹ gm.io.vdd Vdd gm.io.merge ¥ï¥¤¥ä¤Î¥Þ¡¼¥¸ gm.io.clock ¥¯¥í¥Ã¥¯ gm.io.led LED¥Ó¥Ã¥È gm.io.ledbar LEDËÀ¥°¥é¥Õ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ¥Ð¥Ã¥Õ¥¡ gm.gate.inv ÈÝÄê¥Ð¥Ã¥Õ¥¡ gm.gate.tribuf ¥È¥é¥¤¡¦¥Ð¥Ã¥Õ¥¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and ñ¹à½ÌÌóAND gm.rgate.nand ñ¹à½ÌÌóNAND gm.rgate.or ñ¹à½ÌÌóOR gm.rgate.nor ñ¹à½ÌÌóNOR gm.rgate.xor ñ¹à½ÌÌóXOR gm.rgate.xnor ñ¹à½ÌÌóXNOR gm.alu.add ²Ã»»´ï gm.alu.mult ¾è»»´ï gm.alu.div ½ü»»´ï gm.alu.lshift º¸¥·¥Õ¥È gm.alu.rshift ±¦¥·¥Õ¥È gm.alu.arshift »»¿ôŪ±¦¥·¥Õ¥È gm.alu.roll ¥í¡¼¥ë gm.mem.reg ¥ì¥¸¥¹¥¿ gm.mem.ff ¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.41mux 4-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.81mux 8-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.12dec 1-2 ¥Ç¥³¡¼¥À gm.msi.14dec 1-4 ¥Ç¥³¡¼¥À gm.msi.18dec 1-8 ¥Ç¥³¡¼¥À gm.mod.inst ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹ gm.mod.in ¥â¥¸¥å¡¼¥ë¤ÎÆþÎÏ gm.mod.out ¥â¥¸¥å¡¼¥ë¤Î½ÐÎÏ gm.mod.inout ¥â¥¸¥å¡¼¥ë¤ÎÆþ½ÐÎÏ # Scope Menu menu.sc.prtrace ¥È¥ì¡¼¥¹°õºþ... menu.sc.close ÊĤ¸¤ë menu.sc.trace ¥È¥ì¡¼¥¹ menu.sc.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.sc.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È ############################################################################## # Interface strings # ifile ¥Õ¥¡¥¤¥ë imodule ¥â¥¸¥å¡¼¥ë iblmodule ¥â¥¸¥å¡¼¥ë: iports ¥Ý¡¼¥È: ibits ¥Ó¥Ã¥ÈÉý: ############################################################################# # Net Dialog Box # db.net.name ¥Í¥Ã¥È̾ db.net.hide ¥Í¥Ã¥È̾¤ò±£¤¹ db.net.bits ¥Ó¥Ã¥ÈÉý db.net.port ¥Ý¡¼¥È¡¦¥¿¥¤¥× db.net.in Æþ db.net.out ½Ð db.net.inout Æþ½Ð db.net.inets ¥Í¥Ã¥È db.gate.extbar ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ¹¤ë¡£ ############################################################################## # Gate dialog box # db.gate.signam ¥Í¥Ã¥È̾ db.gate.portnam ¥Ý¡¼¥È̾ db.gate.iotype ¥¿¥¤¥× db.gate.bitw ¥Ó¥Ã¥ÈÉý db.gate.cyclew ¥µ¥¤¥¯¥ëÉý db.gate.phase ¥Õ¥§¡¼¥º db.gate.duty ¥Ç¥å¡¼¥Æ¥£¡¼ db.gate.port ¥Ý¡¼¥È db.gate.bitws ¥Ó¥Ã¥È db.gate.gtype ¥²¡¼¥È¡¦¥¿¥¤¥× db.gate.gname ¥²¡¼¥È̾ db.gate.hidenam ̾Á°¤ò±£¤¹ db.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë db.gate.cpbreak ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹Ê¬³äÅÀ db.gate.butstate ¥¹¥¤¥Ã¥Á¾õÂÖ db.gate.dipval DIP¾õÂÖ db.gate.memfilenam ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë̾ db.gate.modname µ¡Ç½Ì¾ db.gate.islink ¥ê¥ó¥¯¤Ë¤¹¤ë db.gate.link ¥ê¥ó¥¯Àè db.gate.findw ¥ï¥¤¥ä¤Î¤ß¤Îõº÷ db.gate.findg ¥²¡¼¥È¤Î¤ß¤Îõº÷ db.gate.findwg ¥ï¥¤¥ä¤È¥²¡¼¥È¤Îõº÷ db.gate.general °ìÈÌ db.gate.details ¾ÜºÙ db.gate.ports ¥Ý¡¼¥È db.gate.delay ÃÙ±ä db.gate.stddelay ɸ½à¤ÎÃÙ±ä db.gate.custdelay ¥«¥¹¥¿¥à¤ÎÃÙ±ä db.led.type LED¤Î¥¿¥¤¥× db.led.bit ¥Ó¥Ã¥È db.led.bar ËÀ¥°¥é¥Õ db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Direct) cpath.cloops -begin- ²óÏ©¤ËÁȹ礻¤Î¥ë¡¼¥×¤¬È¯¸«¤µ¤ì¤¿¡£¥¯¥ê¥Æ¥£¥«¥ë ¡¦¥Ñ¥¹¤Î²òÀϤò¹Ô¤Ê¤¤¤¿¤±¤ì¤Ð¡¢¥ë¡¼¥×¾å¤Î¥Í¥Ã¥È ¤òÀڤ俤ꡢ¥ë¡¼¥×¾å¤Î¥²¡¼¥È¤ò¡Ö¥¯¥ê¥Æ¥£¥«¥ë¡¦ ¥Ñ¥¹Ê¬³äÅÀ¡×¤Ë¤·¤¿¤ê¤¹¤ëɬÍפ¬¤¢¤ë¡£ -end- ############################################################################## # Print dialog box # print.outto ½ÐÎÏÀè print.printer ¥×¥ê¥ó¥¿¡¼ print.file ¥Õ¥¡¥¤¥ë print.prcmd °õºþ¥³¥Þ¥ó¥É print.filename ¥Õ¥¡¥¤¥ë̾ print.browse ÁªÂò... print.epssave Encapsulated Postscript¤È¤·¤Æ¥»¡¼¥Ö¤¹¤ë. print.doctit ¥É¥­¥å¥á¥ó¥È¤ÎÂê̾ print.prmod °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë print.epcm ¥¨¥Ý¥Ã¥¯/cm print.estpg ¥Ú¡¼¥¸¿ô¤Î¸«ÀѤâ¤ê print.all Á´¤Æ print.cur ¸½ºß print.use »ÈÍÑÃæ print.sel »ØÄê print.inclib ¥é¥¤¥Ö¥é¥ê¡¦¥Õ¥¡¥¤¥ë¤â°õºþ print.papsz ¥Ú¡¼¥¸¡¦¥µ¥¤¥º print.orient ¥ª¥ê¥¨¥ó¥Æ¡¼¥·¥ç¥ó print.portrait ½Ä print.landscape ²£ print.2side ξÌÌ°õºþ print.opts ¥ª¥×¥·¥ç¥ó print.scale Â礭¤¤¥â¥¸¥å¡¼¥ë¤ò¥¹¥±¡¼¥ë¤·¤Æ°ì¥Ú¡¼¥¸¤Ç°õºþ¤¹¤ë print.partition Â礭¤¤¥â¥¸¥å¡¼¥ë¤òÊ£¿ô¤Î¥Ú¡¼¥¸¤Ç°õºþ¤¹¤ë print.incidx ¥¤¥ó¥Ç¥Ã¥¯¥¹¤ò´Þ¤à print.incgraph ³¬ÁØ¥°¥é¥Õ¤ò´Þ¤à print.4up ¾®¤µ¤¤¥â¥¸¥å¡¼¥ë¤ò°ìÊǤ˻ͤĤº¤Ä°õºþ¤¹¤ë print.range ¥ì¥ó¥¸ print.fulltr Á´Éô print.parttr Éôʬ print.start ¥¹¥¿¡¼¥È print.end ¥¹¥È¥Ã¥× ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 @opt.width 775 @opt.height 450 @opt.tabwidth 95 opt.editor.features ´ðÁÃŪ¤Ê¥¨¥Ç¥£¥¿¡¼¤Îµ¡Ç½ opt.editor.format ¼«Æ°¥¤¥ó¥Ç¥ó¥È¤òÍ­¸ú¤Ë¤¹¤ë opt.editor.colorize ¼«Æ°¿§ÉÕ¤±¤òÍ­¸ú¤Ë¤¹¤ë opt.editor.comments ¥³¥á¥ó¥È opt.editor.strings ʸ»úÎó opt.editor.reserved ¥­¡¼¥ï¡¼¥É opt.editor.gateword ¥²¡¼¥È̾ opt.editor.instword ¥â¥¸¥å¡¼¥ë̾ opt.editor.taskword ¥·¥¹¥Æ¥à¡¦¥¿¥¹¥¯ opt.editor.color ¿§ opt.editor.bold ÂÀ»ú opt.editor.italic ¥¤¥¿¥ê¥Ã¥¯ opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin..end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.site ¥µ¥¤¥È̾ opt.inst ¥¤¥ó¥¹¥¿¥ó¥¹ opt.mods ¥â¥¸¥å¡¼¥ë opt.modports ¥Ý¡¼¥È opt.frames ¥Õ¥ì¡¼¥à opt.comment ¥³¥á¥ó¥È opt.hlink ¥ê¥ó¥¯ opt.wire 1¥Ó¥Ã¥È¤Î¥ï¥¤¥ä opt.bus ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä opt.tools ¥Ä¡¼¥ë opt.cpath ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹ opt.grid ¥¹¥³¡¼¥×¤Î¥°¥ê¥Ã¥É opt.logic1 ÏÀÍý£± opt.logic0 ÏÀÍý£° opt.float ¥Õ¥í¡¼¥È opt.unknown ÉÔÌÀ opt.offled ¥ª¥Õ¤ÎLED opt.onled ¥ª¥ó¤ÎLED opt.zled ¥Õ¥í¡¼¥È¤ÎLED opt.restdef ¥Ç¥Õ¥©¡¼¥ë¥È opt.regudate ¥ê¡¼¥¸¥ç¥ó¡¦¥¢¥Ã¥×¥Ç¡¼¥È opt.smoothscroll ¥¹¥à¡¼¥º¡¦¥¹¥¯¥í¡¼¥ë opt.outmove ¥â¥¸¥å¡¼¥ë¤Î¥¢¥¦¥È¥é¥¤¥ó°ÜÆ° opt.balloon ¥Ð¥ë¡¼¥ó¡¦¥Ø¥ë¥×¤òÍøÍÑ opt.debug ¥Ç¥Ð¥Ã¥° opt.novice ½é¿´¼Ô¥â¡¼¥É opt.ckpoint ¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ opt.freq ´ü´Ö opt.beak ÆÃÊ̥⡼¥É¤ò²Äǽ¤Ë¤¹¤ë opt.mode ¥â¡¼¥É opt.normal ÉáÄÌ opt.bat ¥Ð¥Ã¥È¥Þ¥ó opt.trek ¥¹¥¿¡¼¡¦¥È¥ì¥Ã¥¯ opt.miles ¥Þ¥¤¥ë¥¹ opt.contver ÆâÉô¹½Â¤¤Î¼«Æ°³Îǧ opt.showsimcmd ¥·¥ß¥å¥ì¡¼¥È¤Î¥³¥Þ¥ó¥É¤òɽ¼¨¤¹¤ë opt.logfile ¥·¥ß¥å¥ì¡¼¥¿¤Î¥í¥°¡¦¥Õ¥¡¥¤¥ë opt.estepsz ¥¨¥Ý¥Ã¥¯¤Î¥¹¥Æ¥Ã¥×¿ô opt.cstepsz ¥¯¥í¥Ã¥¯¤Î¥µ¥¤¥¯¥ë¿ô opt.overstep ¥¯¥í¥Ã¥¯¤Î¥ª¥Ð¡¼¥¹¥Æ¥Ã¥× opt.initscript ½é´ü²½¥¹¥¯¥ê¥×¥È opt.posedge Á´¤Æ¤Î¥¯¥í¥Ã¥¯¤ÇÄä»ß¤¹¤ë opt.setclock »ØÄê¤Î¥¯¥í¥Ã¥¯¤ÇÄä»ß¤¹¤ë opt.delayfilepath ÃÙ±ä¥Õ¥¡¥¤¥ë opt.general °ìÈÌ opt.print °õºþ opt.simulate ¥·¥ß¥å¥ì¡¼¥È opt.analysis ²òÀÏ opt.color ¿§ opt.undolen ºÇÂçUndo opt.cpopts ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹ÀßÄê: opt.maxpath ºÇÂç¥Ñ¥¹¿ô: opt.cpflash ¥Ñ¥¹¤ÎÅÀÌÇɽ¼¨ opt.vpopupdelay ¿®¹æÃÍ¥¦¥£¥ó¥É¤Îɽ¼¨ÃÙ±ä opt.vercheck -begin- Äê´üŪ¤Ë tkgate ¤Î¿·¤·¤¤¥Ð¡¼¥¸¥ç¥ó¤ò¥¤¥ó¥¿¡¼¥Í¥Ã¥È¤Ç ¥Á¥§¥Ã¥¯¤¹¤ë¡£¾ï»þÀܳ¤Ç¤Ê¤±¤ì¤ÐÍ­¸ú¤Ë¤·¤Ê¤¤¤³¤È¡£ -end- ############################################################################## # # Block list dialog boxes blklst.newmod ¿·¥â¥¸¥å¡¼¥ë̾ blklst.delmod ºï½ü¤¹¤ë¥â¥¸¥å¡¼¥ë̾ blklst.frommod ¸µ¤Î¥â¥¸¥å¡¼¥ë̾ blklst.tomod ¥³¥Ô¡¼Àè¤Î¥â¥¸¥å¡¼¥ë̾ blklst.oldname ¸µ¤Î¥â¥¸¥å¡¼¥ë̾ blklst.newname ¿·¥â¥¸¥å¡¼¥ë̾ blklst.claim ¼èÆÀ¤¹¤ë¥â¥¸¥å¡¼¥ë̾ find.label õº÷ find.exp -begin- ¥²¡¼¥È̾¡¢¥Í¥Ã¥È̾¡¢ ¥³¥á¥ó¥È¤Ê¤É¤ÎÃæ¤Ë »ØÄꥹ¥È¥ê¥ó¥°¤ò õº÷¤¹¤ë¡£ -end- # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ¤ò´Þ¤à find.qual.begins ¤«¤é»Ï¤Þ¤ë find.qual.ends ¤Ç½ª¤ë ############################################################################## # # Circuit Dialog box # circ.topmod ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë circ.discchg Êѹ¹¤ò̵»ë¤¹¤ë circ.iniscript ½é´ü²½¥¹¥¯¥ê¥×¥È circ.noscript ¥¹¥¯¥ê¥×¥È¡¦¥Õ¥¡¥¤¥ë¤Ï»ØÄꤵ¤ì¤Æ¤¤¤Ê¤¤¡£ circ.really1 ËÜÅö¤Ë circ.really2 ¤ò¥¹¥¯¥ê¥×¥È¡¦¥Õ¥¡¥¤¥ë¤Î¥ê¥¹¥È¤«¤éºï½ü¤·¤Þ¤¹¤« circ.extbar ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ¹¤ë¡£ ############################################################################# # # Breakpoint Management # break.tab ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È break.id ÈÖ¹æ break.state ¾õ break.condition ¾ò·ï break.value ÃÍ ############################################################################## # Simulator # sim.breakpt ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È ############################################################################## # # Command box # cmd.file ¥Õ¥¡¥¤¥ë̾ cmd.topname ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë̾ ############################################################################## # # Critical path messages # cp.delay ¥Ñ¥¹ÃÙ±ä: cp.pathl ¥Ñ¥¹¤Î°ìÍ÷: cp.numpath ¥Ñ¥¹¿ô: cp.recompute ºÆ·×»» ############################################################################## # Error messages # err.verilog ¥Õ¥¡¥¤¥ë¤Î¥¨¥é¡¼¡§ err.nopin ÁªÂò¤µ¤ì¤¿¥Ô¥ó¤Î¥¿¥¤¥×¤òÊѹ¹½ÐÍè¤Ê¤¤¡£ err.badhex ÉÔÀµ¤Î16¿Ê¿ô¤ÎÃͤÏ̵»ë¤µ¤ì¤¿¡£ err.gatanchor ¥²¡¼¥È¤¬°ÜÆ°ÉԲĤ˥ޡ¼¥¯¤µ¤ì¤Æ¤¤¤ë°Ù¡¢°ÜÆ°½ÐÍè¤Ê¤¤¡£ err.libmode ¥é¥¤¥Ö¥é¥ê¡¦¥â¥¸¥å¡¼¥ë¤Ë¤ÏÉÔÀµ¤ÎÁàºî¤Ç¤¢¤ë¡£ err.badfind õº÷¥¹¥È¥ê¥ó¥°¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.badopendel »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤òºï½ü½ÐÍè¤Ê¤¤¡£ err.nosrcmod ¥½¡¼¥¹¡¦¥â¥¸¥å¡¼¥ë'%s'¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.noerr ¥¨¥é¡¼¡¦¥á¥Ã¥»¡¼¥¸¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.misserr ¥¨¥é¡¼¾ðÊó¤¬ÉÔ´°Á´¤Ç¤¢¤ë¡£(¥·¥ß¥å¥ì¡¼¥¿¤¬Íî¤Á¤¿¡©) err.pounimpl ¥¤¥ó¥×¥ê¥á¥ó¥È¤·¤Æ¤¤¤Ê¤¤(in ParseOption) err.badinadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦ÆþÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badoutadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦½ÐÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badinoutadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦Æþ½ÐÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badpinchg 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¥·¥ß¥å¥ì¡¼¥¿¤Î¥³¥Þ¥ó¥É¤ò¥Õ¥¡¥¤¥ë¤Ë ½ñ¤­¹þ¤à¡£¥·¥ß¥å¥ì¡¼¥¿¤ò¥Ç¥Ð¥Ã¥¬¤Ç ¼Â¹Ô¤¹¤ë»þ¡¢¤³¤Î¥Õ¥¡¥¤¥ë¤Ï¥·¥ß¥å¥ì¡¼¥¿ ¤ÎÆþÎϤȤ·¤ÆÍøÍѤǤ­¤ë¡£ -end- ho.cpathanal -begin- ²óÏ©¤Î¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹¤òõº÷¤¹¤ë¡£ -end- ho.circuit.extbar -begin- ´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬ 3Ëܰʾå¤Î»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.edgat.extbar -begin- ´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬ 3Ëܰʾå¤Î»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.opt.undolen -begin- undo¤Î¥ê¥¹¥È¤ÎŤµ -end- ho.opt.vpopupdelay -begin- ¥Þ¥¦¥¹¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤«¤é¡¢²¿¥ß¥êÉÃ·Ð¤Ã¤Æ ¤«¤é¿®¹æ¤ÎÃͤ¬É½¼¨¤µ¤ì¤ëÃÙ±ä¤Ç¤¢¤ë¡£ ¤³¤ÎÃٱ䤬û²á¤®¤ë»þ¡¢¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤¬ ǧÃΤǤ­¤Ê¤¯¤Ê¤ëÌäÂ꤬¤¢¤ë¥·¥¹¥Æ¥à¤Ï ¤¢¤ë¡£¤³¤ÎÌäÂ꤬µ¯¤³¤é¤Ê¤±¤ì¤Ð¡¢ÃÙ±ä ¤ò¤è¤êû¤¯¤·¤Æ¤âÎɤ¤¡£ -end- tkgate-2.0-b10/locale/ja/messages.orig000644 001751 001751 00000107367 10244636674 020362 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Tue May 24 10:44:10 2005 ############################################################################## # # Japanese messages file (should be EUC encoded) # # NOTE: The messages.ja file should not be edited directly. Please edit # the message.ja.euc and/or messages.ha.utf8 files. The messages.ja file # will be overwritten by the either the .euc or .utf8 file when doing # a configure. # # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages # ############################################################################## ############################################################################## # # basic strings # b.dismiss é–‰ã˜ã‚‹ b.close é–‰ã˜ã‚‹ b.clear クリア b.ok ＯＫ b.cancel キャンセル b.open é–‹ã b.bitw ビット幅 b.in å…¥ b.out 出 b.inout 入出 b.browse é¸æŠž... b.label åå‰ b.find 探索 b.edit 編集... b.add 追加... b.delete 削除 b.deleteb 削除... b.apply セット b.anchor 移動ä¸å¯ b.tech テクノロジー ############################################################################## # # Main tab strings # tab.edit 編集 tab.editintr インタフェース tab.simulate シミュレート tab.cpath é…å»¶è§£æž ############################################################################## # Menu strings # menu.file ファイル menu.edit 編集 menu.tool ツール menu.simulate シミュレート menu.module モジュール menu.interface インタフェース menu.gate ゲート menu.make ä½œæˆ menu.circ 回路 menu.help ヘルプ menu.file.new æ–°è¦ä½œæˆ menu.file.open é–‹ã... menu.file.openlib ライブラリを開ã... menu.file.save ä¿å­˜ menu.file.saveas åå‰ã‚’付ã‘ã¦ä¿å­˜... menu.file.print å°åˆ·... menu.file.options 設定... menu.file.quit 終了 menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut 切りå–ã‚Š menu.edit.copy コピー menu.edit.paste 張り付㑠menu.edit.selall å…¨ã¦ã‚’é¸æŠž menu.edit.find 回路を探索... menu.edit.algnv 縦ã®ä¸€åˆ— menu.edit.algnh 横ã®ãƒ¼åˆ— menu.edit.zoomin ズーム・イン menu.edit.zoomout ズーム・アウト menu.tool.move 移動ï¼æŽ¥ç¶š menu.tool.delg ゲートã®å‰Šé™¤ menu.tool.cutw ワイヤã®åˆ‡æ–­ menu.tool.inv å¦å®š menu.tool.bitw ビット幅 menu.tool.debug デãƒãƒƒã‚° menu.tool.rot0 0度回転 menu.tool.rot90 90度回転 menu.tool.rot180 180度回転 menu.tool.rot270 270度回転 menu.simulate.begin シミュレーションを開始 menu.simulate.end シミュレーションを終了 menu.simulate.run ラン menu.simulate.pause 一時ストップ menu.simulate.step ステップ(エãƒãƒƒã‚¯) menu.simulate.cycle ステップ(サイクル) menu.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆã®è¨­å®š... menu.simulate.script スクリプトを実行... menu.simulate.load メモリã®èª­ã¿è¾¼ã¿... menu.simulate.dump メモリã®æ›¸ã出ã—... menu.simulate.adprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.module.open é–‹ã menu.module.close é–‰ã˜ã‚‹ menu.module.seti インタフェースã®è¨­å®š menu.module.editi インタフェースã®ç·¨é›†... menu.module.new æ–°è¦ä½œæˆ... menu.module.del 削除... menu.module.copy コピー... menu.module.rename åå‰ã®ç·¨é›†... menu.module.claim å–å¾—... menu.module.setroot ルートã«ã™ã‚‹... menu.module.prop モジュールã®è¨­å®š... menu.circ.prop 回路ã®è¨­å®š... menu.circ.cpath クリティカル・パス... menu.gate.addin 入力を追加 menu.gate.addout 出力を追加 menu.gate.addinout 入出力を追加 menu.gate.iochg ピン・タイプã®å¤‰æ›´ menu.gate.anchor é¸æŠžã‚’移動ä¸å¯ã«ã™ã‚‹ menu.gate.unanchor é¸æŠžã‚’移動å¯ã«ã™ã‚‹ menu.gate.prop ゲートã®è¨­å®š... menu.gate.rep 複製 menu.gate.del 削除 menu.gate.settech テクノロジーã®è¨­å®š menu.help.about tkgateã«ã¤ã„ã¦... menu.help.license ライセンス... menu.help.doc ドキュメンテーション... menu.help.tut ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ« menu.help.example 回路ã®ä¾‹ menu.help.example.comb 組åˆã›å›žè·¯ menu.help.example.3bit 3ビットã®ã‚«ã‚¦ãƒ³ã‚¿ãƒ¼ menu.help.example.8bit 8ビットã®ã‚«ã‚¦ãƒ³ã‚¿ãƒ¼ menu.help.example.trff トランジスタ・レベルã®FF menu.help.example.cpu Menagerie CPU menu.help.tut.welcome tkgateã®ç´¹ä»‹ menu.help.tut.create 基本ã®ä½¿ã„æ–¹ menu.help.tut.edit1 回路ã®ç·¨é›†(1) menu.help.tut.edit2 回路ã®ç·¨é›†(2) menu.help.tut.mods モジュールã®ä½¿ã„æ–¹ menu.help.tut.sim シミュレータã®ä½¿ã„æ–¹ pop.wire.addseg ワイヤã®è¿½åŠ  gm.io I/O gm.gate ゲート gm.rgate å˜é …縮約ゲート gm.msi MSI gm.alu ALU gm.mem メモリー gm.mod モジュール gm.comment コメント gm.frame フレーム gm.io.switch スイッムgm.io.dip DIPスイッムgm.io.ground アース gm.io.vdd Vdd gm.io.merge ワイヤã®ãƒžãƒ¼ã‚¸ gm.io.clock クロック gm.io.led LEDビット gm.io.ledbar LED棒グラフ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ãƒãƒƒãƒ•ã‚¡ gm.gate.inv å¦å®šãƒãƒƒãƒ•ã‚¡ gm.gate.tribuf トライ・ãƒãƒƒãƒ•ã‚¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and å˜é …縮約AND gm.rgate.nand å˜é …縮約NAND gm.rgate.or å˜é …縮約OR gm.rgate.nor å˜é …縮約NOR gm.rgate.xor å˜é …縮約XOR gm.rgate.xnor å˜é …縮約XNOR gm.alu.add 加算器 gm.alu.mult 乗算器 gm.alu.div 除算器 gm.alu.lshift 左シフト gm.alu.rshift å³ã‚·ãƒ•ãƒˆ gm.alu.arshift ç®—æ•°çš„å³ã‚·ãƒ•ãƒˆ gm.alu.roll ロール gm.mem.reg レジスタ gm.mem.ff フリップ・フロップ gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 セレクター gm.msi.41mux 4-1 セレクター gm.msi.81mux 8-1 セレクター gm.msi.12dec 1-2 デコーダ gm.msi.14dec 1-4 デコーダ gm.msi.18dec 1-8 デコーダ gm.mod.inst モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ gm.mod.in モジュールã®å…¥åŠ› gm.mod.out モジュールã®å‡ºåŠ› gm.mod.inout モジュールã®å…¥å‡ºåŠ› # Scope Menu menu.sc.prtrace トレースå°åˆ·... menu.sc.close é–‰ã˜ã‚‹ menu.sc.trace トレース menu.sc.zoomin ズーム・イン menu.sc.zoomout ズーム・アウト ############################################################################## # Interface strings # ifile ファイル imodule モジュール iblmodule モジュール: iports ãƒãƒ¼ãƒˆ: ibits ビット幅: ############################################################################# # Net Dialog Box # db.net.name ãƒãƒƒãƒˆå db.net.hide ãƒãƒƒãƒˆåã‚’éš ã™ db.net.bits ビット幅 db.net.port ãƒãƒ¼ãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.in å…¥ db.net.out 出 db.net.inout 入出 db.net.inets ãƒãƒƒãƒˆ db.gate.extbar æ‹¡å¼µãƒãƒ¼ã‚’利用ã™ã‚‹ã€‚ ############################################################################## # Gate dialog box # db.gate.signam ãƒãƒƒãƒˆå db.gate.portnam ãƒãƒ¼ãƒˆå db.gate.iotype タイプ db.gate.bitw ビット幅 db.gate.cyclew サイクル幅 db.gate.phase フェーズ db.gate.duty デューティー db.gate.port ãƒãƒ¼ãƒˆ db.gate.bitws ビット db.gate.gtype ゲート・タイプ db.gate.gname ゲートå db.gate.hidenam åå‰ã‚’éš ã™ db.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ db.gate.cpbreak クリティカル・パス分割点 db.gate.butstate スイッãƒçŠ¶æ…‹ db.gate.dipval DIP状態 db.gate.memfilenam メモリ・ファイルå db.gate.modname 機能å db.gate.islink リンクã«ã™ã‚‹ db.gate.link リンク先 db.gate.findw ワイヤã®ã¿ã®æŽ¢ç´¢ db.gate.findg ゲートã®ã¿ã®æŽ¢ç´¢ db.gate.findwg ワイヤã¨ã‚²ãƒ¼ãƒˆã®æŽ¢ç´¢ db.gate.general 一般 db.gate.details 詳細 db.gate.ports ãƒãƒ¼ãƒˆ db.gate.delay é…延 db.gate.stddelay 標準ã®é…延 db.gate.custdelay カスタムã®é…延 db.led.type LEDã®ã‚¿ã‚¤ãƒ— db.led.bit ビット db.led.bar 棒グラフ db.led.hex 7-Segment (HEX) db.led.dec 7-Segment (DEC) db.led.seg 7-Segment (Direct) cpath.cloops -begin- 回路ã«çµ„åˆã›ã®ãƒ«ãƒ¼ãƒ—ãŒç™ºè¦‹ã•ã‚ŒãŸã€‚クリティカル ・パスã®è§£æžã‚’è¡Œãªã„ãŸã‘ã‚Œã°ã€ãƒ«ãƒ¼ãƒ—上ã®ãƒãƒƒãƒˆ を切ã£ãŸã‚Šã€ãƒ«ãƒ¼ãƒ—上ã®ã‚²ãƒ¼ãƒˆã‚’「クリティカル・ パス分割点ã€ã«ã—ãŸã‚Šã™ã‚‹å¿…è¦ãŒã‚る。 -end- ############################################################################## # Print dialog box # print.outto 出力先 print.printer プリンター print.file ファイル print.prcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ print.filename ファイルå print.browse é¸æŠž... print.epssave Encapsulated Postscriptã¨ã—ã¦ã‚»ãƒ¼ãƒ–ã™ã‚‹. print.doctit ドキュメントã®é¡Œå print.prmod å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« print.epcm エãƒãƒƒã‚¯/cm print.estpg ページ数ã®è¦‹ç©ã‚‚ã‚Š print.all 全㦠print.cur ç¾åœ¨ print.use 使用中 print.sel 指定 print.inclib ライブラリ・ファイルもå°åˆ· print.papsz ページ・サイズ print.orient オリエンテーション print.portrait 縦 print.landscape 横 print.2side 両é¢å°åˆ· print.opts オプション print.scale 大ãã„モジュールをスケールã—ã¦ä¸€ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.partition 大ãã„モジュールを複数ã®ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.incidx インデックスをå«ã‚€ print.incgraph 階層グラフをå«ã‚€ print.4up å°ã•ã„モジュールを一é ã«å››ã¤ãšã¤å°åˆ·ã™ã‚‹ print.range レンジ print.fulltr 全部 print.parttr 部分 print.start スタート print.end ストップ ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 @opt.width 775 @opt.height 450 @opt.tabwidth 95 opt.editor.features 基礎的ãªã‚¨ãƒ‡ã‚£ã‚¿ãƒ¼ã®æ©Ÿèƒ½ opt.editor.format 自動インデントを有効ã«ã™ã‚‹ opt.editor.colorize 自動色付ã‘を有効ã«ã™ã‚‹ opt.editor.comments コメント opt.editor.strings 文字列 opt.editor.reserved キーワード opt.editor.gateword ゲートå opt.editor.instword モジュールå opt.editor.taskword システム・タスク opt.editor.color 色 opt.editor.bold 太字 opt.editor.italic イタリック opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin..end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.site サイトå opt.inst インスタンス opt.mods モジュール opt.modports ãƒãƒ¼ãƒˆ opt.frames フレーム opt.comment コメント opt.hlink リンク opt.wire 1ビットã®ãƒ¯ã‚¤ãƒ¤ opt.bus 多ビットã®ãƒ¯ã‚¤ãƒ¤ opt.tools ツール opt.cpath クリティカル・パス opt.grid スコープã®ã‚°ãƒªãƒƒãƒ‰ opt.logic1 è«–ç†ï¼‘ opt.logic0 è«–ç†ï¼ opt.float フロート opt.unknown ä¸æ˜Ž opt.offled オフã®LED opt.onled オンã®LED opt.zled フロートã®LED opt.restdef デフォールト opt.regudate リージョン・アップデート opt.smoothscroll スムーズ・スクロール opt.outmove モジュールã®ã‚¢ã‚¦ãƒˆãƒ©ã‚¤ãƒ³ç§»å‹• opt.balloon ãƒãƒ«ãƒ¼ãƒ³ãƒ»ãƒ˜ãƒ«ãƒ—を利用 opt.debug デãƒãƒƒã‚° opt.novice åˆå¿ƒè€…モード opt.ckpoint ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ opt.freq 期間 opt.beak 特別モードをå¯èƒ½ã«ã™ã‚‹ opt.mode モード opt.normal 普通 opt.bat ãƒãƒƒãƒˆãƒžãƒ³ opt.trek スター・トレック opt.miles マイルス opt.contver 内部構造ã®è‡ªå‹•ç¢ºèª opt.showsimcmd シミュレートã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ opt.logfile シミュレータã®ãƒ­ã‚°ãƒ»ãƒ•ã‚¡ã‚¤ãƒ« opt.estepsz エãƒãƒƒã‚¯ã®ã‚¹ãƒ†ãƒƒãƒ—æ•° opt.cstepsz クロックã®ã‚µã‚¤ã‚¯ãƒ«æ•° opt.overstep クロックã®ã‚ªãƒãƒ¼ã‚¹ãƒ†ãƒƒãƒ— opt.initscript åˆæœŸåŒ–スクリプト opt.posedge å…¨ã¦ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.setclock 指定ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.delayfilepath é…延ファイル opt.general 一般 opt.print å°åˆ· opt.simulate シミュレート opt.analysis è§£æž opt.color 色 opt.undolen 最大Undo opt.cpopts クリティカル・パス設定: opt.maxpath 最大パス数: opt.cpflash パスã®ç‚¹æ»…表示 opt.vpopupdelay ä¿¡å·å€¤ã‚¦ã‚£ãƒ³ãƒ‰ã®è¡¨ç¤ºé…延 opt.vercheck -begin- 定期的㫠tkgate ã®æ–°ã—ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã‚’インターãƒãƒƒãƒˆã§ ãƒã‚§ãƒƒã‚¯ã™ã‚‹ã€‚常時接続ã§ãªã‘ã‚Œã°æœ‰åŠ¹ã«ã—ãªã„ã“ã¨ã€‚ -end- ############################################################################## # # Block list dialog boxes blklst.newmod 新モジュールå blklst.delmod 削除ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.frommod å…ƒã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.tomod コピー先ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.oldname å…ƒã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.newname 新モジュールå blklst.claim å–å¾—ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å find.label 探索 find.exp -begin- ゲートåã€ãƒãƒƒãƒˆå〠コメントãªã©ã®ä¸­ã« 指定ストリングを 探索ã™ã‚‹ã€‚ -end- # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ã‚’å«ã‚€ find.qual.begins ã‹ã‚‰å§‹ã¾ã‚‹ find.qual.ends ã§çµ‚ã‚‹ ############################################################################## # # Circuit Dialog box # circ.topmod トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« circ.discchg 変更を無視ã™ã‚‹ circ.iniscript åˆæœŸåŒ–スクリプト circ.noscript スクリプト・ファイルã¯æŒ‡å®šã•ã‚Œã¦ã„ãªã„。 circ.really1 本当㫠circ.really2 をスクリプト・ファイルã®ãƒªã‚¹ãƒˆã‹ã‚‰å‰Šé™¤ã—ã¾ã™ã‹ circ.extbar æ‹¡å¼µãƒãƒ¼ã‚’利用ã™ã‚‹ã€‚ ############################################################################# # # Dynamic Verilog Module Manager # break.tab ブレークãƒã‚¤ãƒ³ãƒˆ break.id ç•ªå· break.state 状 break.condition æ¡ä»¶ break.value 値 ############################################################################## # Simulator # sim.breakpt ブレークãƒã‚¤ãƒ³ãƒˆ ############################################################################## # # Command box # cmd.file ファイルå cmd.topname トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å ############################################################################## # # Critical path messages # cp.delay パスé…延: cp.pathl パスã®ä¸€è¦§: cp.numpath パス数: cp.recompute å†è¨ˆç®— ############################################################################## # Error messages # err.verilog ファイルã®ã‚¨ãƒ©ãƒ¼ï¼š err.nopin é¸æŠžã•ã‚ŒãŸãƒ”ンã®ã‚¿ã‚¤ãƒ—を変更出æ¥ãªã„。 err.badhex ä¸æ­£ã®16進数ã®å€¤ã¯ç„¡è¦–ã•ã‚ŒãŸã€‚ err.gatanchor ゲートãŒç§»å‹•ä¸å¯ã«ãƒžãƒ¼ã‚¯ã•ã‚Œã¦ã„る為ã€ç§»å‹•å‡ºæ¥ãªã„。 err.libmode ライブラリ・モジュールã«ã¯ä¸æ­£ã®æ“作ã§ã‚る。 err.badfind 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badopendel 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’削除出æ¥ãªã„。 err.nosrcmod ソース・モジュール'%s'ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.noerr エラー・メッセージãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.misserr エラー情報ãŒä¸å®Œå…¨ã§ã‚る。(シミュレータãŒè½ã¡ãŸï¼Ÿ) err.pounimpl インプリメントã—ã¦ã„ãªã„(in ParseOption) err.badinadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥åŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badinoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badpinchg é¸æŠžã®ã‚²ãƒ¼ãƒˆã®ãƒ”ンã®ã‚¿ã‚¤ãƒ—ãŒå¤‰æ›´å‡ºæ¥ãªã„。 err.badnetname åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為削除ã•ã‚ŒãŸã€‚ err.netbcrename 指定ã®åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為ã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfnet 指定ã®åå‰ãŒåˆ¥ã®åå‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfgat 指定ã®åå‰ãŒåŸºç¤Žã®ã‚²ãƒ¼ãƒˆåã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfkw 指定ã®åå‰ãŒã‚­ãƒ¼ãƒ¯ãƒ¼ãƒ‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.badconsame ãƒãƒƒãƒˆãŒåŒã˜ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconptsp ãƒãƒƒãƒˆã®ä¸¡æ–¹ãŒãƒãƒ¼ãƒˆåˆã¯é›»åŠ›ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconbitw ãƒãƒƒãƒˆã®ãƒ“ット幅ãŒç•°ãªã‚‹ã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badrange 指定ã•ã‚ŒãŸæ™‚é–“ã®ãƒ¬ãƒ³ã‚¸ãŒä¸æ­£ã§ã‚る。 err.badlprcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒå®Ÿè¡Œå‡ºæ¥ãªã„。 err.badpsopen ãƒã‚¹ãƒˆãƒ»ã‚¹ã‚¯ãƒªãƒ—トを「%sã€ã«æ›¸ãè¾¼ã‚ãªã„。 err.badid 「%sã€ã¯ä¸æ­£ã®åå‰ã§ã‚る。 err.bkpt.badexp ä¸æ­£ãªãƒ–レークãƒã‚¤ãƒ³ãƒˆã®æ¡ä»¶ã§ã‚る。「netã€, 「!netã€, 「net==valueã€, 「net!=valueã€ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.bkpt.badnet ä¸æ­£ã®ãƒãƒƒãƒˆåã§ã‚る。 err.bkpt.badval ä¸æ­£ã®å€¤ã§ã‚る。10進数ã‚ã‚‹ã„ã¯ã€verilogå½¢å¼ã®å€¤ã—ã‹èªè­˜ã•ã‚Œã¦ã„ãªã„。 err.bkpt.toomany ブレークãƒã‚¤ãƒ³ãƒˆãŒå¤šéŽãŽã‚‹ã€‚制é™ã¯%dã§ã‚る。 err.sim.badtmp /tmpã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ›¸ãè¾¼ã‚ãªã‹ã£ãŸï¼ˆãƒ‡ã‚£ã‚¹ã‚¯ãŒã„ã£ã±ã„ã‹ï¼‰ã€‚ err.sim.syntx ä¸æ­£ã®ã€Œ%sã€ã‚³ãƒžãƒ³ãƒ‰ err.sim.noincl インクルード・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ err.sim.clockbadedge clockコマンドã®ã‚¨ãƒƒã‚¸'%c'ãŒä¸æ­£ã§ã‚る。 err.sim.nobkpt ブレーク・ãƒã‚¤ãƒ³ãƒˆã€Œ%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.sim.nonet ãƒãƒƒãƒˆã€Œ%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.nogate ゲート「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.badbin 2進数ã®å€¤ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る。 err.sim.notswitch ゲート'%s'ã¯ã‚¹ã‚¤ãƒƒãƒã€DIPã€ãƒ¬ã‚¸ã‚¹ã‚¿ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.sim.badcmd シミュレーション・スクリプトã«ä¸æ­£ã®ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒã‚る。 err.noteditpchg 設定ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ä»¥å¤–ã€å¤‰æ›´ä¸å¯ã€‚ err.badeditop 編集コマンドã«ä¸æ­£ãŒã‚る。 err.badopen 回路ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badlibopen ライブラリ・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.nomark ゲート種をé¸ã¶å‰ã«ã€ãƒžã‚¦ã‚¹ã§ä½ç½®ã‚’設定ã—ã¦ãã ã•ã„。 err.badgate ゲート種ãŒæœªå®šç¾©ã§ã‚る。 err.badmake ゲートãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã€‚ err.nojump -begin- ç¾åœ¨ã€'jump-to-module'機能ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ç”¨å‡ºæ¥ãªã„。 トップ・モジュールよりã€ã€Œ>ã€ã‚„「<ã€ã®ã‚³ãƒžãƒ³ãƒ‰ã§ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã‘ã¦ãã ã•ã„。 -end- err.nomod モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.modlock モジュールãŒãƒ­ãƒƒã‚¯ã—ã¦ã„る。 err.closeroot トップ・モジュールãŒé–‰ã˜ã‚Œãªã„。 err.sim.isrun シミュレータã¯æ—¢ã«å®Ÿè¡Œã—ã¦ã„る。 ('Ctrl-s e'ã§çµ‚了ã™ã‚‹). err.sim.isnotrun シミュレータã¯å®Ÿè¡Œã—ã¦ã„ãªã„。 ('Ctrl-s b'ã§å®Ÿè¡Œã™ã‚‹). err.editonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ãˆãªã„。 err.simonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ã—ã‹ä½¿ãˆãªã„。 err.nodel ゲートをé¸æŠžã—ã¦ã„ãªã„。 err.modnotdef モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.moddef モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã—ã¦ã„る。 err.noprop é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã¯ç·¨é›†å‡ºæ¥ã‚‹è¨­å®šãŒãªã„。 err.openscript シミュレーション・スクリプト「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.oldversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³(%s)ãŒå¤ã„。(ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s). err.futureversion 未æ¥ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ï¼ˆ%s）ã®tkgateファイルã§ã‚る。（ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s） err.badversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒèªè­˜å‡ºæ¥ãªã„。注æ„ã—ã¦åˆ©ç”¨ä¸‹ã•ã„。 err.nodrive ãƒãƒƒãƒˆ%sã¯ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«%sã«ä¿¡å·ã®ã‚½ãƒ¼ã‚¹ãŒãªã„。 err.noconn ワイヤ%s{%d}ã¯æŽ¥ç¶šãŒãªã„（削除ã—ãŸï¼‰ã€‚ err.oldportact ãƒãƒ¼ãƒˆã‚„モジュールã®ç«¯ã«å³ã‚¯ãƒªãƒƒã‚¯ã—ã¦ä¸‹ã•ã„。 err.badportadd é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã¯è¿½åŠ ä¸å¯ã€‚ err.badportdel é¸æŠžã•ã‚ŒãŸãƒãƒ¼ãƒˆã¯å‰Šé™¤å‡ºæ¥ãªã„。 err.badportedit é¸æŠžã•ã‚ŒãŸãƒãƒ¼ãƒˆã¯ç·¨é›†å‡ºæ¥ãªã„。 err.noport ãƒãƒ¼ãƒˆã¯é¸æŠžã—ã¦ã„ãªã„。 err.noback -begin- tkgateãƒãƒ¼ã‚¸ãƒ§ãƒ³%sã§ä½œã‚‰ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ã§ã‚る。ä¿å­˜ã™ã‚‹ã¨ã€ tkgateã®å¤ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã«èª­ã¿è¾¼ã‚ãªã„ã“ã¨ãŒã‚る（ç¾åœ¨ã® ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%sã§ã‚る）。 -end- err.manypages -begin- ページ数ãŒæ¥µã‚ã¦å¤§ãã„。 本当ã«å°åˆ·ã—ã¾ã™ã‹? -end- err.backupfail ãƒãƒƒã‚¯ã‚¢ãƒƒãƒ—・ファイル'%s'ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã€‚ err.corruptnewsave -begin- TkGateã¯'%s'ã«ã‚»ãƒ¼ãƒ–出æ¥ãŸãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ··ä¹±ã•ã‚Œã¦ã„ã‚‹ã¿ãŸã„。もã—ãƒã‚§ãƒƒ ク・ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’使ã£ã¦ã¿ã¦ã ã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.corruptsave -begin- '%s'をセーブã—よã†ã¨ã—ã¦ã„る時ã€TkGateã«å†…部å•é¡ŒãŒç™ºè¦‹ã—ãŸã€‚元々ã®ãƒ•ã‚¡ã‚¤ ルã¯ãã®ã¾ã¾æ®‹ã—ã¦ã‚る。混乱ã•ã‚Œã¦ã„ã‚‹å¯èƒ½æ€§ã®ã‚るファイルã¯'%s'ã«ã‚»ãƒ¼ãƒ– ã—ãŸã€‚ã‚‚ã—ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ ルを使ã£ã¦ã¿ã¦ãã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.badsave -begin- '%s'をセーブ出æ¥ãªã‹ã£ãŸã€‚ファイルã®ãƒ—ロテクションや空ãディスクé‡ã‚’ç¢ºèª ã—ã¦ãã ã•ã„。 -end- err.nosafesave -begin- '%s'ã®å®‰å…¨ã‚»ãƒ¼ãƒ–ã‚’è¡Œã†ãŸã‚ã®ä¸€æ™‚ã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã‹ã‚‰ã€ç›´æŽ¥ã‚»ãƒ¼ ブã—ãªãã¦ã¯ãªã‚‰ãªã„。「NOã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€å…ƒã€…ã®ãƒ•ã‚¡ã‚¤ãƒ«ã¯ãã®ã¾ã¾æ®‹ ã™ã€‚「YESã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€ã‚»ãƒ¼ãƒ–ã™ã‚‹ãŒã€ã‚»ãƒ¼ãƒ–途中ã«å•é¡ŒãŒèµ·ã“ã£ãŸã‚‰ã€ 回路データãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚る。直接セーブã—ã¦ã¿ã¾ã—ょã†ã‹ã€‚ -end- ############################################################################## # Informational messages # msg.selwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selgate %2$sã¨ã„ã†%1$sゲートãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selblock %2$sã¨ã„ã†%1$sモジュールãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.modoverwt モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã•ã‚Œã¦ã„る。定義ã—ãªãŠã—ã¾ã™ã‹? msg.foundgate %sã¨ã„ã†ã‚²ãƒ¼ãƒˆãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.foundwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.searchagn 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ã‚‚ã†ä¸€åº¦ã€ŒæŽ¢ç´¢ã€ã‚’押ã™ã¨ã€æŽ¢ç´¢ã—ãªãŠã™ã€‚ msg.sim.chgtoroot シミュレーション・モードã§ã¯ã€ãƒˆãƒƒãƒ—・モジュールãŒãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ã®ãƒˆãƒƒãƒ—ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 msg.sim.nogatemod シミュレーション・モードã§ã€å…·ä½“çš„ãªãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ãŒå¿…è¦ã§ã‚る。 msg.setinterface モジュール「%sã€ã®ã‚¤ãƒ³ã‚¿ãƒ•ã‚§ãƒ¼ã‚¹ã‚’セットã—ãŸã€‚ msg.needsel モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ã‚’é¸ã‚“ã§ãã ã•ã„。 msg.wroteckpt 「%sã€ã«ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆã‚’書ã込んã ... msg.save 「%sã€ã«ä¿å­˜ã—ãŸã€‚ msg.badsave 「%sã€ã«ä¿å­˜å‡ºæ¥ãªã‹ã£ãŸã€‚ msg.reallynew 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€æ–°ã—ã„回路を開ãã¾ã™ã‹? msg.reallyquit 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€çµ‚了ã—ã¾ã™ã‹? msg.notlib モジュール「%sã€ã¯ãƒ©ã‚¤ãƒ–ラリ・モジュールã§ã¯ãªã„。 ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€ãŠå‰ã¿ãŸã„ãªå¤§é¦¬é¹¿ã—ã‹ã„ãªã„よ。 miles.msg2 é¦¬é¹¿ï¼ miles.msg3 æ„šã‹ã‚‚ã®ï¼ miles.msg4 マイルスã€ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€é¦¬é¹¿ã ã‚ˆã€‚ miles.msg5 馬鹿ãªã‚²ãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ã‚’ã‚„ã‚ã¦ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg6 ゲートをãã®ä½ç½®ã«ãŠã„ãŸã®ã¯ã€ãŠå‰ã®æ„šã‹ã•ã®è¨¼æ˜Žã ã‚ˆã€‚ miles.msg7 ã“ã®ãƒ­ã‚¯ã§ãªã—回路ã®è¨­è¨ˆã‚’諦ã‚よã€ãƒžã‚¤ã‚¹ãƒ«ã€‚ miles.msg8a 続ã‘ã¦ã‚‚ã€ç„¡é§„ã ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg8b ãŠå‰ãŒå›žè·¯ã‚’設計出æ¥ãªã„ã¨ã„ã†ã®ã¯ã€èª°ã§ã‚‚分ã‹ã‚‹ã‚ˆã€‚ ############################################################################## # Balloon Help # ho.new -begin- ç¾åœ¨ã®å›žè·¯ã‚’消ã—ã¦ã€æ–°ã—ㄠ回路を作æˆã™ã‚‹ã€‚ -end- ho.open 回路ファイルを開ã ho.save 回路ファイルをä¿å­˜ã™ã‚‹ ho.print 回路ファイルをå°åˆ·ã™ã‚‹ ho.move -begin- 移動ï¼æŽ¥ç¶š - ã“ã®ãƒ„ールã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ æ–°ã—ã„ゲートã®ä½ç½®ã‚’設定ã™ã‚‹ ゲートを移動ã™ã‚‹ ワイヤを移動ã™ã‚‹ ワイヤを接続ã™ã‚‹ ダブル・クリックã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ ゲートã®å±žæ€§ã‚’編集ã™ã‚‹ ワイヤã®å±žæ€§ã‚’編集ã™ã‚‹ ãƒãƒ¼ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ コメントã®ãƒ†ã‚­ã‚¹ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ -end- ho.delgat ã“ã®ãƒ„ールã§ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ ho.cutw ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã‚’切断ã™ã‚‹ ho.inv -begin- ã“ã®ãƒ„ールã§ã€ã‚²ãƒ¼ãƒˆã®å…¥å‡ºåŠ›ã« å¦å®šã‚’付ã‘ãŸã‚Šã€æ¶ˆã—ãŸã‚Šã™ã‚‹ã€‚ -end- ho.bitw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã®ãƒ“ット幅を 変更ã™ã‚‹ã€‚ビット幅をå³ä¸‹ã®å…¥åŠ› ボックスã«å…¥åŠ›ã—ã¦ãã ã•ã„。 -end- ho.modopen é¸æŠžã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã ho.modclose ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‰ã˜ã‚‹ ho.undo 最近行ã£ãŸå¤‰åŒ–を元通りã«ã™ã‚‹ã€‚ ho.redo undoã—ãŸå¤‰åŒ–ã‚’ã‚„ã‚Šç›´ã™ã€‚ ho.simstart -begin- シミュレータを開始ã—ã€è«–ç†ã‚¢ãƒŠãƒ©ã‚¤ã‚¶ã®ã‚¦ã‚£ãƒ³ãƒ‰ã‚’ é–‹ãã€ãã—ã¦åˆæœŸåŒ–スクリプトãŒå®šç¾©ã—ã¦ã„ã‚‹å ´åˆã€ ãã®ã‚¹ã‚¯ãƒªãƒ—トを実行ã™ã‚‹ã€‚ -end- ho.simgo -begin- シミュレータを動ã‹ã™ã€‚組åˆã›å›žè·¯ã®å ´åˆã€ ä¿¡å·ãŒå¤‰ã‚らãªããªã‚‹æ™‚ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ ãŒä¸€æ™‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.simpause シミュレータã®ä¸€æ™‚åœæ­¢ ho.simstep -begin- シミュレータを一定数ã®ã‚¨ãƒãƒƒã‚¯ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simclock -begin- シミュレータを一定数ã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚µã‚¤ã‚¯ãƒ« ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simstop -begin- シミュレータをåœæ­¢ã—ã¦ã€ 編集モードã«æˆ»ã‚‹ã€‚ -end- ho.simbreak -begin- シミュレータã®ãƒ–レークãƒã‚¤ãƒ³ãƒˆ を編集ã™ã‚‹ã€‚ -end- ho.simexec スクリプトを実行ã™ã‚‹ã€‚ ho.simload -begin- メモリ・ファイルを読ã¿è¾¼ã‚€ -end- ho.simdump -begin- メモリ・ファイルã«æ›¸ã出㙠-end- ho.sim.break -begin- ブレークãƒã‚¤ãƒ³ãƒˆã‚’入力ã—ã¦ãã ã•ã„。ブレークãƒã‚¤ãƒ³ãƒˆ æ¡ä»¶ãŒæˆç«‹ã™ã‚‹æ™‚ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ãŒä¸€æ™‚åœæ­¢ã®ãƒ¢ãƒ¼ãƒ‰ã«å…¥ã‚‹ã€‚ ç¾åœ¨ã€ã€Œw1 == 0ã€ã€ã€Œw7 != 8ã€ã€ã€Œw8ã€ã€ã€Œ!w2ã€ãªã©ã® ブレークãƒã‚¤ãƒ³ãƒˆæ¡ä»¶ã—ã‹åˆ©ç”¨å‡ºæ¥ãªã„。 -end- ho.f.modlist -begin- 読ã¿è¾¼ã‚“ã§ã‚るモジュールã®ä¸€è¦§è¡¨ã€‚ トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®åå‰ã«ã€Œ+ã€ãŒ 付ã„ã¦ã„る。ライブラリã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã¯æ‹¬å¼§ã«å›²ã¾ã‚Œã¦ã„る。 -end- ho.netlist -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ä¸€è¦§è¡¨ã€‚åå‰ã‚’éš ã—㦠ã„ã‚‹ãƒãƒƒãƒˆã®åå‰ã«ã€Œ@ã€ãŒä»˜ã„ã¦ã„る。 マルãƒãƒ»ãƒ“ットã®ãƒãƒƒãƒˆã®åå‰ã®å¾Œã« ビットã®ãƒ¬ãƒ³ã‚¸ã‚’表示ã—ã¦ã„る。 -end- ho.ports -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ã€‚ 入力ã«ã€Œ>ã€ã€å‡ºåŠ›ã«ã€Œ<ã€ã€å…¥å‡ºåŠ›ã« 「=ã€ãŒä»˜ã„ã¦ã„る。 -end- ho.status.logo -begin- ç¾åœ¨ã®ãƒ¢ãƒ¼ãƒ‰ãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。鉄ã®ã‚²ãƒ¼ãƒˆ ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ã‚’表ã™ã€‚ANDゲートã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ ション・モードを表ã™ã€‚ANDゲートãŒèµ°ã£ã¦ ã„る時ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ãŒå‹•ã„ã¦ã„る。 -end- ho.status.msg tkgateよりã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ãŒã“ã“ã«è¡¨ç¤ºã•ã‚Œã‚‹ã€‚ ho.status.block ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒ‘ス ho.status.file -begin- ç¾åœ¨ç·¨é›†ä¸­ã®ãƒ•ã‚¡ã‚¤ãƒ«åãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。「*〠ã¨ã„ã†è¨˜å·ãŒã¤ã„ã¦ã„る時ã€ä¿å­˜ã—ã¦ã„ãªã„変更 ãŒã‚る。 -end- ho.print.selall å…¨ã¦ã®èª­ã¿è¾¼ã‚“ã§ã„るモジュールをå°åˆ·ã™ã‚‹ã€‚ ho.print.selcur ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ ho.print.seluse 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿å°åˆ·ã™ã‚‹ã€‚ ho.print.selsel -begin- 以下ã«ãƒžãƒ¼ã‚¯ã—ã¦ã„るモジュールã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ コントロール・キーã§è¤‡æ•°ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠž 出æ¥ã‚‹ã€‚ -end- ho.print.modlist å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠžã™ã‚‹ã€‚ ho.circuit.discchg -begin- 有効ã«ã™ã‚‹ã¨ã€å¤‰æ›´ã‚ã‚Šã®å›žè·¯ã‚’ ä¿å­˜ã—ãªã„ã§é–‰ã˜ã‚‹ã¨ã警告ã—ãªã„。 -end- ho.cmd.bitw -begin- カーソルã§é¸æŠžã•ã‚ŒãŸãƒ¯ã‚¤ãƒ¤ã¯è¡¨ç¤º ã•ã‚Œã¦ã„るビット幅ã«è¨­å®šã•ã‚Œã‚‹ã€‚ -end- ho.edgat.signam -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã§ã‚る。åå‰ãŒå¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.port -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆåã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.iolab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆæ–¹å‘ã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.bitlab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒ“ット幅ã§ã‚る。変更出æ¥ã‚‹ã€‚ -end- ho.edgat.cycle 一サイクルã®ã‚¨ãƒãƒƒã‚¯æ•° ho.edgat.phase クロックã®ãƒ•ã‚§ãƒ¼ã‚ºï¼ˆãƒ‘ーセントã§è¨­å®šã™ã‚‹ï¼‰ ho.edgat.duty クロック・サイクルã®ä½•ãƒ‘ーセントãŒè«–ç†0ã§ã‚ã‚‹ã‹ ho.edgat.cname 接続ã•ã‚Œã¦ã„ã‚‹ãƒãƒƒãƒˆå ho.edgat.cport 接続ã•ã‚Œã¦ã„ã‚‹ãƒãƒ¼ãƒˆå ho.edgat.ctype 接続ã®ç¨®é¡ž ho.edgat.cbitw 接続ã•ã‚Œã¦ã„ã‚‹ãƒãƒƒãƒˆã®ãƒ“ット幅 ho.edgat.cedit é¸æŠžã®ãƒãƒ¼ãƒˆã‚’編集ã™ã‚‹ã€‚ ho.edgat.cadd ゲートã«ãƒãƒ¼ãƒˆã‚’追加ã™ã‚‹ã€‚ ho.edgat.cdel ゲートã®ãƒãƒ¼ãƒˆã‚’削除ã™ã‚‹ã€‚ ho.edgat.hide -begin- 有効ã«ã™ã‚‹ã¨ã‚²ãƒ¼ãƒˆåãŒè¡¨ç¤ºã•ã‚Œãªã„。 -end- ho.edgat.gtype ゲートã®ç¨®é¡ž ho.edgat.gname ゲートã®åå‰ ho.edgat.ganchor 有効ã«ã™ã‚‹ã¨ã€ã‚²ãƒ¼ãƒˆãŒç§»å‹•ä¸å¯ã«ãªã‚‹ã€‚ ho.edgat.gx ゲートã®Xä½ç½® ho.edgat.gy ゲートã®Yä½ç½® ho.edgat.swstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.dipstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.range マルãƒãƒ“ットã®ä¿¡å·ã®ã‚µãƒ–・レンジã§ã‚る。 ho.edgat.memfile -begin- メモリã®åˆæœŸã®å€¤ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’指定ã™ã‚‹ã€‚ シミュレーションを始ã‚る時ã€ã“ã®ãƒ•ã‚¡ã‚¤ãƒ« ãŒèª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.edgat.func モジュールã®æ©Ÿèƒ½ ho.edgat.frame フレームã®ãƒ©ãƒ™ãƒ« ho.opt.site -begin- 回路ãªã©ã‚’å°åˆ·ã™ã‚‹æ™‚ã€ã“ã®ã‚µã‚¤ãƒˆåãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.smooth -begin- ã“ã®è¨­å®šã‚’有効ã«ã™ã‚‹ã¨ã€å›žè·¯ã‚’スクロールã™ã‚‹æ™‚〠ビットマップã®ã‚³ãƒ”ーを利用ã—ã¦ã€åŠ¹çŽ‡ã‚ˆã スクロールã§ãる。Xサーãƒã®å•é¡ŒãŒã‚ã‚Œã°ã€ã“㮠設定を無効ã«ã™ã‚Œã°è‰¯ã„。 -end- ho.opt.clip -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¦ã‚¤ãƒ³ãƒ‰ã‚¦ã®éƒ¨åˆ†é ˜åŸŸã® å†æ画を行ãªã†ã€‚ãã†ã§ãªã‘ã‚Œã°å¸¸ã« 全領域をå†æç”»ã™ã‚‹ã€‚ -end- ho.opt.outmove -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’移動ã™ã‚‹æ™‚〠ワイヤãªã©ã¯ãƒžã‚¦ã‚¹ã®ãƒœã‚¿ãƒ³ã‚’離ã™ã¾ã§ 移動ã—ãªã„。画é¢ã®è¡¨ç¤ºãŒé…ã„時ã«ä¾¿åˆ©ã§ã‚る。 -end- ho.opt.bhelp -begin- 有効ã«ã™ã‚‹ã¨ã€ã“ã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ã®æ§˜ãªã€Œãƒ˜ãƒ«ãƒ—・ ãƒãƒ«ãƒ¼ãƒ³ã€ãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.novice -begin- 有効ã«ã™ã‚‹ã¨ã€åˆå¿ƒè€…モードã«ãªã‚‹ã€‚ åˆå¿ƒè€…モードã§ã¯ã€tkgateãŒç«‹ã¡ä¸ŠãŒã‚‹æ™‚〠ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ«ãŒè‡ªå‹•çš„ã«èª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.opt.debug -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ‡ãƒã‚°æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ 開発者以外ã«ã€ã‚ã¾ã‚Šå½¹ã«ç«‹ãŸãªã„。 -end- ho.opt.ckpt 有効ã«ã™ã‚‹ã¨ã€tkgateã¯ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’作る。 ho.opt.ckptfreq ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã‚’何クリック毎ã«è¡Œãªã†ã‹ ho.opt.beak -begin- 全然役ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ã€‚ã“ã®æ©Ÿèƒ½ã‚’ 無効ã«ã™ã‚‹ã¨ã€ã“ã®ã‚¹ã‚¤ãƒƒãƒã¯ãƒ€ã‚¤ã‚¢ãƒ­ã‚° ボックスã‹ã‚‰æ¶ˆãˆã€.tkgate-propertiesを編集ã—ãªã„é™ã‚Š 戻らãªã„。 -end- ho.opt.miles -begin- 有効ã«ã™ã‚‹ã¨ã€tkgateã¯æ™‚々ユーザを 馬鹿ã«ã—ãŸã‚Šã€æ‚ªå£ã‚’言ã£ãŸã‚Šã™ã‚‹ã€‚ -end- ho.opt.bat -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒãƒƒãƒˆãƒžãƒ³ã®ã‚³ãƒ³ãƒ”ュータを 設計ã™ã‚‹ç‚ºã«ã€Œå½¹ã«ãŸã¤ã€æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ -end- ho.opt.trek 転é€ã—ã‚ã€ã‚¹ã‚³ãƒƒãƒ†ã‚£ï¼ ho.opt.normal ã¤ã¾ã‚‰ãªã„モードã«æˆ»ã‚‹ã€‚ ho.opt.simstep -begin- シミュレータã®ã‚¹ãƒ†ãƒƒãƒ—・コマンド㧠何エãƒãƒƒã‚¯é€²ã‚€ã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckstep -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ã‚¹ãƒ†ãƒƒãƒ—・コマンド㧠何サイクル進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckover -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ クロックã®ã‚¨ãƒƒã‚¸ã‚ˆã‚Šæ›´ã«ä½•ã‚¨ãƒãƒƒã‚¯ 進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.init -begin- シミュレータを立ã¡ä¸Šã’る時㫠自動的ã«å®Ÿè¡Œã™ã‚‹ã‚¹ã‚¯ãƒªãƒ—ト・ ファイルを指定ã™ã‚‹ã€‚ -end- ho.opt.ckall -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ ã©ã®ã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã§ã‚‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.ckspec -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ 指定ã—ãŸã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã®ã¿ã«åœæ­¢ã™ã‚‹ã€‚ -end- ho.deftech -begin- æ–°ã—ã„ゲートã®ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ã€‚ ゲートã®é…延ã«å½±éŸ¿ã™ã‚‹ã€‚ä»»æ„ã®ã‚²ãƒ¼ãƒˆ ã®ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ã‚’変更ã™ã‚‹ã«ã¯ã€ã‚²ãƒ¼ãƒˆã® 設定ボックスを開ã„ã¦ã€ã€Œé…延ã€ã®ã‚¿ãƒ– ã‚’é¸æŠžã—ã¦ä¸‹ã•ã„。 -end- ho.techbut -begin- 指定ã—ãŸãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ãƒ»ãƒ•ã‚¡ã‚¤ãƒ«ã‹ã‚‰ã®é…延値を 利用ã™ã‚‹ã€‚æ–°ã—ã„テクノロジーを追加ã™ã‚‹ç‚ºã€ 「ファイルã€â†’「設定...ã€â†’「シミュレート〠ã®ãƒ¡ãƒ‹ãƒ¥ãƒ¼ã‚’é–‹ã„ã¦ã€ãƒ•ã‚¡ã‚¤ãƒ«ã®ãƒªã‚¹ãƒˆã«è¿½åŠ  ã—ã¦ä¸‹ã•ã„。 -end- ho.custbut -begin- ã“ã®ã‚²ãƒ¼ãƒˆå°‚用ã®é…延値を指定ã™ã‚‹ã€‚ -end- ho.contver -begin- マウスæ“作を行ãªã†æ™‚ã€å†…部構造を自動的㫠確èªã—ã¦ã€ä¸æ­£ã®æ‰€ã‚’知らã™ã€‚ -end- ho.simwatch -begin- シミュレータã¨GUIã®é–“ã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ã€‚ -end- ho.simlog -begin- シミュレータã®ã‚³ãƒžãƒ³ãƒ‰ã‚’ファイル㫠書ã込む。シミュレータをデãƒãƒƒã‚¬ã§ 実行ã™ã‚‹æ™‚ã€ã“ã®ãƒ•ã‚¡ã‚¤ãƒ«ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ ã®å…¥åŠ›ã¨ã—ã¦åˆ©ç”¨ã§ãる。 -end- ho.cpathanal -begin- 回路ã®ã‚¯ãƒªãƒ†ã‚£ã‚«ãƒ«ãƒ»ãƒ‘スを探索ã™ã‚‹ã€‚ -end- ho.circuit.extbar -begin- 基本ゲート(AND, OR, XOR)ã®å…¥åŠ›æ•°ãŒ 3本以上ã®æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã™ã‚‹ã€‚ -end- ho.edgat.extbar -begin- 基本ゲート(AND, OR, XOR)ã®å…¥åŠ›æ•°ãŒ 3本以上ã®æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã™ã‚‹ã€‚ -end- ho.opt.undolen -begin- undoã®ãƒªã‚¹ãƒˆã®é•·ã• -end- ho.opt.vpopupdelay -begin- マウスボタンを押ã—ã¦ã‹ã‚‰ã€ä½•ãƒŸãƒªç§’経ã£ã¦ ã‹ã‚‰ä¿¡å·ã®å€¤ãŒè¡¨ç¤ºã•ã‚Œã‚‹é…延ã§ã‚る。 ã“ã®é…延ãŒçŸ­éŽãŽã‚‹æ™‚ã€ãƒ€ãƒ–ルクリック㌠èªçŸ¥ã§ããªããªã‚‹å•é¡ŒãŒã‚るシステム㯠ã‚る。ã“ã®å•é¡ŒãŒèµ·ã“らãªã‘ã‚Œã°ã€é…延 をより短ãã—ã¦ã‚‚良ã„。 -end- tkgate-2.0-b10/locale/ja/messages.backup000644 001751 001751 00000252533 11120112707 020637 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed May 23 23:32:30 2007 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages ############################################################################## # # basic strings # b.new æ–°è¦... b.dismiss é–‰ã˜ã‚‹ b.close é–‰ã˜ã‚‹ b.ok ＯＫ b.clear クリア b.cancel キャンセル b.open é–‹ã b.bitw ビット幅 b.in å…¥ b.out 出 b.inout 入出 b.browse é¸æŠž... b.label åå‰ b.find 探索 b.edit 編集... b.add 追加... b.delete 削除 b.deleteb 削除... b.remove 消㙠b.apply セット b.anchor 移動ä¸å¯ b.tech テクノロジー b.enable å¯èƒ½ã«ã™ã‚‹ b.disable 無能ã«ã™ã‚‹ b.flush クリア ############################################################################## # # Main tab strings # tab.edit 編集 tab.editintr インタフェース tab.simulate シミュレート tab.cpath é…å»¶è§£æž # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add 追加... mm.delete 削除 mm.edit 編集... mm.enable 有効ã«ã™ã‚‹ mm.disable 無効ã«ã™ã‚‹ ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ファイル menu.edit 編集 menu.tool ツール menu.simulate シミュレート menu.module モジュール menu.interface インタフェース menu.gate ゲート menu.make ä½œæˆ menu.help ヘルプ menu.file.new æ–°è¦ä½œæˆ menu.file.open é–‹ã... menu.file.openlib ライブラリを開ã... menu.file.save ä¿å­˜ menu.file.saveas åå‰ã‚’付ã‘ã¦ä¿å­˜... menu.file.print å°åˆ·... menu.file.options 設定... menu.file.quit 終了 menu.file.cprop 回路ã®ç‰¹å¾´... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut カット menu.edit.copy コピー menu.edit.paste ペースト menu.edit.overlay Overlay張り付㑠menu.edit.selall å…¨ã¦ã‚’é¸æŠž menu.edit.find 回路を探索... menu.edit.algnv 縦ã®ä¸€åˆ— menu.edit.algnh 横ã®ãƒ¼åˆ— menu.edit.rotate 回転 menu.edit.zoomin ズーム・イン menu.edit.zoomout ズーム・アウト menu.edit.rshift å³ã‚·ãƒ•ãƒˆ menu.edit.lshift 左シフト menu.edit.ushift 上シフト menu.edit.dshift 下シフト menu.edit.cwrotate 時計周り回転 menu.edit.ccwrotate 時計å対周り回転 menu.edit.pcwrotate ãƒãƒ¼ãƒˆã®æ™‚計周り回転 menu.edit.pccwrotate ãƒãƒ¼ãƒˆã®éžæ™‚計周り回転 #menu.edit.autobold 太字化 menu.edit.resize å†ã‚µã‚¤ã‚ºåŒ– menu.tool.move 移動ï¼æŽ¥ç¶š menu.tool.delg ゲートã®å‰Šé™¤ menu.tool.cutw ワイヤã®åˆ‡æ–­ menu.tool.inv å¦å®š menu.tool.bitw ビット幅 menu.tool.debug デãƒãƒƒã‚° menu.tool.point ãƒã‚¤ãƒ³ãƒˆ menu.tool.line ライン menu.tool.rect 長方形 menu.tool.fillrect 色ã¥ã‘長方形 menu.tool.port ãƒãƒ¼ãƒˆ menu.tool.select å…責é¸æŠž menu.tool.rot0 0度回転 menu.tool.rot90 90度回転 menu.tool.rot180 180度回転 menu.tool.rot270 270度回転 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin シミュレーションを開始 menu.simulate.end シミュレーションを終了 menu.simulate.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.simulate.run ラン menu.simulate.pause 一時ストップ menu.simulate.step ステップ(エãƒãƒƒã‚¯) menu.simulate.cycle ステップ(サイクル) menu.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆã®è¨­å®š... menu.simulate.script スクリプトを実行... menu.simulate.load メモリã®èª­ã¿è¾¼ã¿... menu.simulate.dump メモリã®æ›¸ã出ã—... menu.module.open é–‹ã menu.module.close é–‰ã˜ã‚‹ menu.module.new æ–°è¦ä½œæˆ... menu.module.del 削除... menu.module.copy コピー... menu.module.rename åå‰ã®ç·¨é›†... menu.module.claim å–å¾—... menu.module.setroot ルートã«ã™ã‚‹... menu.module.prop モジュールã®è¨­å®š... menu.module.interface インタフェース menu.module.interface.set セット menu.module.interface.edit 編集 menu.gate.addport ãƒãƒ¼ãƒˆè¿½åŠ  menu.gate.ioset タイプ指定 menu.gate.anchor é¸æŠžã‚’移動ä¸å¯ã«ã™ã‚‹ menu.gate.unanchor é¸æŠžã‚’移動å¯ã«ã™ã‚‹ menu.gate.prop ゲートã®è¨­å®š... menu.gate.rep 複製 menu.gate.del 削除 menu.gate.settech テクノロジーã®è¨­å®š menu.help.about tkgateã«ã¤ã„ã¦... menu.help.license ライセンス... menu.help.doc ドキュメンテーション... menu.help.tut ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ« menu.help.home ホーム・ページ menu.help.example 回路ã®ä¾‹ ############################################################################# # Scope Menu # menu.scope_file ファイル menu.scope_sim シミュレート menu.scope_trace トレース menu.scope_help ヘルプ menu.scope_file.ptrace トレースå°åˆ·... menu.scope_file.close é–‰ã˜ã‚‹ menu.scope_trace.zoomin ズーム・イン menu.scope_trace.zoomout ズーム・アウト menu.scope_sim.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.scope_sim.run 時効 menu.scope_sim.pause 一時åœæ­¢ menu.scope_sim.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— menu.scope_sim.cycle サイクル・ステップ menu.scope_sim.break ブレークãƒã‚¤ãƒ³ãƒˆ... menu.scope_sim.script スクリプトã®æ™‚効... menu.scope_sim.load メモリã®èª­ã¿è¾¼ã¿... menu.scope_sim.dump メモリã®æ›¸ãè¾¼ã¿... menu.scope_help.about tkgateã«ä»˜ã„ã¦... menu.scope_help.license ライセンス... menu.scope_help.doc ドキュメンテーション... mod.intf インタフェース port.parms ãƒãƒ¼ãƒˆã®ãƒ‘ラメタ port.in å…¥ port.out 出 port.inout 入出 ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ゲート gm.rgate å˜é …縮約ゲート gm.msi MSI gm.alu ALU gm.mem メモリー gm.mod モジュール gm.comment コメント gm.frame フレーム gm.io.switch スイッムgm.io.dip DIPスイッムgm.io.ground アース gm.io.vdd Vdd gm.io.merge ワイヤã®ãƒžãƒ¼ã‚¸ gm.io.clock クロック gm.io.led LEDビット gm.io.ledbar LED棒グラフ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ãƒãƒƒãƒ•ã‚¡ gm.gate.inv å¦å®šãƒãƒƒãƒ•ã‚¡ gm.gate.tribuf トライ・ãƒãƒƒãƒ•ã‚¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and å˜é …縮約AND gm.rgate.nand å˜é …縮約NAND gm.rgate.or å˜é …縮約OR gm.rgate.nor å˜é …縮約NOR gm.rgate.xor å˜é …縮約XOR gm.rgate.xnor å˜é …縮約XNOR gm.alu.add 加算器 gm.alu.mult 乗算器 gm.alu.div 除算器 gm.alu.lshift 左シフト gm.alu.rshift å³ã‚·ãƒ•ãƒˆ gm.alu.arshift ç®—æ•°çš„å³ã‚·ãƒ•ãƒˆ gm.alu.roll ロール gm.mem.reg レジスタ gm.mem.ff フリップ・フロップ gm.mem.rff é¡åƒãƒ•ãƒªãƒƒãƒ—・フロップ gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 セレクター gm.msi.41mux 4-1 セレクター gm.msi.81mux 8-1 セレクター gm.msi.12dec 1-2 デコーダ gm.msi.14dec 1-4 デコーダ gm.msi.18dec 1-8 デコーダ gm.mod.inst モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ gm.mod.in モジュールã®å…¥åŠ› gm.mod.out モジュールã®å‡ºåŠ› gm.mod.inout モジュールã®å…¥å‡ºåŠ› tutorial.prev å‰ã¸ tutorial.next 次㸠tutorial.chapter ç« ã®ä¸€è¦§è¡¨ tutorial.reload å†èª­ã¿è¾¼ã¿ ############################################################################## # # Popup menus # pop.make ä½œæˆ pop.tool ツール pop.edit.paste ペースト pop.edit.cut カット pop.edit.copy コピー pop.port.in å…¥ pop.port.out 出 pop.port.inout 入出 pop.wire.addseg ワイヤã®è¿½åŠ  pop.wire.prop ãƒãƒƒãƒˆã®ç‰¹å¾´... pop.wire.hidesize ビット幅を隠㙠pop.wire.showsize ビット幅を示㙠pop.wire.hidelabel レーベルを隠㙠pop.wire.hidealllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’éš ã™ pop.wire.clearalllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’クリア pop.wire.showlabel レーベルを示㙠pop.gate.open é–‹ã pop.gate.close é–‰ã˜ã‚‹ pop.gate.prop インスタンスã®ç‰¹å¾´... pop.gate.addport ãƒãƒ¼ãƒˆã®è¿½åŠ  pop.gate.addin 入力ã®è¿½åŠ ... pop.gate.addout 出力ã®è¿½åŠ ... pop.gate.addinout 入出力ã®è¿½åŠ ... pop.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ pop.gate.settech テクノロジ指定 pop.gate.delete 削除 pop.gate.ioset タイプã®æŒ‡å®š pop.module.new æ–°è¦... pop.module.del 削除... pop.module.copy コピー... pop.module.rename åå‰ã®å¤‰æ›´... pop.module.claim モジュールã®å–å¾— pop.module.setroot ルート指定... pop.module.prop モジュールã®ç‰¹å¾´... pop.module.int インタフェースã®ç·¨é›†... pop.simulate.end シミュレーションを終了 pop.simulate.begin シミュレーションを開始 pop.simulate.addprobe プローブを追加ï¼å‰Šé™¤ pop.simulate.run 時効 pop.simulate.pause 一時åœæ­¢ pop.simulate.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— pop.simulate.cycle サイクル・ステップ pop.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆ... pop.simulate.script スクリプトã®æ™‚効... pop.simulate.load メモリã®èª­ã¿è¾¼ã¿... pop.simulate.dump メモリã®æ›¸ãè¾¼ã¿... pop.interface インタフェース pop.interface.set 指定 pop.interface.edit 編集... pop.interface.auto 自動作æˆ... pop.interface.replace å–ã‚Šæ›ãˆ pop.igen.type タイプ pop.igen.side サイド pop.igen.size サイズ pop.igen.delete 削除 pop.igen.in å…¥ pop.igen.out 出 pop.igen.inout 入出 pop.igen.left å·¦ pop.igen.right å³ pop.igen.top 上 pop.igen.bottom 下 pop.igen.other ä»– ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit 編集 #symed.edit.cut カット #symed.edit.copy コピー #symed.edit.paste ペースト #symed.edit.overlay Overlayペースト #symed.edit.rclock 時計周り回転 #symed.edit.rcclock éžæ™‚計周り回転 #symed.module モジュール #symed.modes モード #symed.cutpaste カットï¼ãƒšãƒ¼ã‚¹ãƒˆ #symed.rotate ãƒãƒ¼ãƒˆã®å›žè»¢ #symed.zoom ズーム #symed.update Update symed.cancel キャンセル symed.tab.normal éžã‚»ãƒ¬ã‚¯ãƒˆ symed.tab.select セレクト symed.link セレクトã¨éžã‚»ãƒ¬ã‚¯ãƒˆã‚’åŒæ™‚ã«ç·¨é›†ã™ã‚‹ã€‚ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg ワイヤã«ãƒ€ãƒ–ル・クリックã—ã¦ã€ãƒ—ローブã«ä»˜ã‘ã£ã¦ãã ã•ã„。 comment.empty [ダブル・クリックã—ã¦ã€ãƒ†ã‚­ã‚¹ãƒˆã‚’編集ã—ã¦ãã ã•ã„。] ############################################################################## # Interface strings # ifile ファイル imodule モジュール iblmodule モジュール: iports ãƒãƒ¼ãƒˆ: ibits ビット幅: itype タイプ: ############################################################################# # Module Dialog Box # db.mod.name モジュールå db.mod.file ファイルå db.mod.type タイプ db.mod.flags フラグ db.mod.dataprot モジュールã®å®šç¾©ã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.intfprot インタフェースã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.edprot インタフェースã®ç·¨é›†ã‚’専用エディタã«é™ã‚‹ã€‚ db.mod.props 特徴 db.mod.netlist ãƒãƒƒãƒˆãƒªã‚¹ãƒˆ db.mod.hdl HDL # # These are probably not used anymore. # db.mod.inuse.0 TODO: Module is not in use. db.mod.inuse.1 TODO: Module is in use. db.mod.lmod.0 TODO: Module has not been modified since loading. db.mod.lmod.1 TODO: Module has been modified since loading. db.mod.smod.0 TODO: Module has not been modified since saving. db.mod.smod.1 TODO: Module has been modified since saving. db.mod.islib.1 TODO: Module is part of [%s] library. db.mod.islib.0 TODO: Module is not a library module. db.mod.netexpl -begin- グラフィカルã®ã‚¨ãƒ‡ã‚£ã‚¿ã‚’ 利用ã—ã¦ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®æ“作を 定義ã™ã‚‹ã€‚ -end- db.mod.hdlexpl -begin- Verilogã®ãƒ†ã‚­ã‚¹ãƒˆã‚’利用ã—ã¦ã€ モジュールã®æ“作を定義ã™ã‚‹ã€‚ -end- ############################################################################# # Error List Dialog box # db.err.caption エラーã®ä¸€è¦§è¡¨ db.err.explain -begin- 回路ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºè¦‹ã•ã‚ŒãŸã®ã§ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã‚’開始 出æ¥ãªã‹ã£ãŸã€‚以下ã®ãƒªã‚¹ãƒˆã®ä¸­ã‹ã‚‰ã€ã‚¨ãƒ©ãƒ¼ã‚’é¸æŠž ã—ã¦ã€ã‚¨ãƒ©ãƒ¼ã®å ´æ‰€ã«ç§»å‹•ã—ã¦ãã ã•ã„。 -end- ############################################################################# # Net Dialog Box # db.net.name ãƒãƒƒãƒˆå db.net.hide ãƒãƒƒãƒˆåã‚’éš ã™ db.net.bits ビット幅 db.net.type ãƒãƒƒãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.port ãƒãƒ¼ãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.in å…¥ db.net.out 出 db.net.inout 入出 db.net.inets ãƒãƒƒãƒˆ ############################################################################## # # New circuit dialog box # db.newcirc.directory ディレクトリ db.newcirc.cap æ–°è¦å›žè·¯ db.newcirc.exp -begin- ç¾åœ¨ã®å›žè·¯ã®ç·¨é›†ã‚’ 辞ã‚ã¦ã€æ–°ã—ã„回路を 編集ã—始ã‚る。 -end- db.newcirc.file ファイルå db.newcirc.topname トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å ############################################################################## # Gate dialog box # @db.gate.tabwidth *80 db.gate.signam ãƒãƒƒãƒˆå db.gate.portnam ãƒãƒ¼ãƒˆå db.gate.iotype タイプ db.gate.bitw ビット幅 db.gate.cyclew サイクル幅 db.gate.phase フェーズ db.gate.duty デューティー db.gate.port ãƒãƒ¼ãƒˆ db.gate.bitws ビット db.gate.side サイド db.gate.gtype ゲート・タイプ db.gate.gname ゲートå db.gate.hidenam åå‰ã‚’éš ã™ db.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ db.gate.cpbreak クリティカル・パス分割点 db.gate.butstate スイッãƒçŠ¶æ…‹ db.gate.dipval DIP状態 db.gate.range ビット範囲 db.gate.memfilenam メモリ・ファイルå db.gate.modname 機能å db.gate.general 一般 db.gate.details 詳細 db.gate.text テキスト db.gate.ports ãƒãƒ¼ãƒˆ db.gate.delay é…延 db.gate.parameters パラメタ db.gate.stddelay 標準ã®é…延 db.gate.custdelay カスタムã®é…延 db.gate.catdiruse ãƒãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ db.gate.edit 編集 db.gate.delete 削除 db.gate.add 追加 db.gate.ff.type フリップフロップã®æ–¹ä½æ±ºå®š db.gate.ff.normal.hdr 普通 db.gate.ff.normal.exp -begin- データãŒå·¦ã‹ã‚‰å³ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.ff.reverse.hdr åå°„ db.gate.ff.reverse.exp -fillbegin- データãŒå³ã‹ã‚‰å·¦ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.cat.asc.hdr TODO: Ascending db.gate.cat.dec.hdr TODO: Decending db.gate.cat.asc.exp -fillbegin- TODO: Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- TODO: Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir ä¿¡å·æ–¹å‘ db.gate.cat.auto.hdr 自動 db.gate.cat.multin.hdr 多入力 db.gate.cat.singin.hdr 多出力 db.gate.cat.tran.hdr TODO: Bidirectional db.gate.cat.auto.exp -fillbegin- ä¿¡å·ã®æ–¹å‘を自動的 ã«åˆ¤æ–­ã™ã‚‹ã€‚ -end- db.gate.cat.multin.exp -fillbegin- TODO: Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- TODO: Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- TODO: Allow bidirectional (tran) signal flow. Cannot be connected to switches or registers. -end- db.gate.tab.General.cap 一般特徴 db.gate.tab.Ports.cap ãƒãƒ¼ãƒˆç‰¹å¾´ db.gate.tab.Delay.cap é…延特徴 db.gate.tab.Parameters.cap モジュール特徴 db.gate.tab.CLOCK.cap クロック特徴 db.gate.tab.SWITCH.cap スイッãƒç‰¹å¾´ db.gate.tab.DIP.cap DIP特徴 db.gate.tab.TAP.cap Tran特徴 db.gate.tab.RAM.cap RAM特徴 db.gate.tab.ROM.cap ROM特徴 db.gate.tab.MODULE.cap モジュール特徴 db.gate.tab.FRAME.cap フレーム特徴 db.gate.tab.LED.cap LED特徴 db.gate.tab.AND.cap AND特徴 db.gate.tab.OR.cap OR特徴 db.gate.tab.XOR.cap XOR特徴 db.gate.tab.MUX.cap Mux特徴 db.gate.tab.DEMUX.cap Demux特徴 db.gate.tab.CONCAT.cap Concat特徴 db.gate.tab.COMMENT.cap テキスト特徴 db.gate.tab.FF.cap フリップフロップ特徴 db.gate.tab.General.exp -fillbegin- TODO: View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- TODO: Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- TODO: Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- TODO: Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- TODO: Set detailed type-specific properties of a gate here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- TODO: Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter パラメタ db.gate.mparm.value 値 db.gate.mparm.exampleA -begin- ã“ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¯ãƒ‘ラメタを利用ã—ã¦ã„ãªã„。 パラメタã¯Verilogテキストã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã« 利用出æ¥ã‚‹ã€‚ã“ã®ãƒ€ã‚¤ã‚¢ãƒ­ã‚°ã§ã€ãã‚Œãžã‚Œã® パラメタã®å€¤ãŒè¨­å®šå‡ºæ¥ã‚‹ã€‚モジュール㮠パラメタを利用ã™ã‚‹ãŸã‚ã€ãƒ†ã‚­ã‚¹ãƒˆã®å®šç¾©ã« 「#ã€ã‹ã‚‰å§‹ã¾ã‚‹ãƒ‘ラメタã®ãƒªã‚¹ãƒˆã‚’書ã„㦠ãã ã•ã„。以下ã®ä¾‹é¡Œã§ã€ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®å€¤ãŒ 「1'b1ã€ã®ã€Œbase_valueã€ã¨ã„ã†ãƒ‘ラメタを æŒã¤ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãŒç¤ºã—ã¦ã‚る。 -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder 入力ã®é †åº db.gate.mux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.mux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.mux.ord1.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.ord2.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.dataorder 出力ã®é †åº db.gate.demux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.demux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.demux.ord1.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.ord2.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.select TODO: Selector Style db.gate.mux.sel1.hdr TODO: Selector on Left db.gate.mux.sel2.hdr TODO: Selector on Right db.gate.mux.sel1.exp -fillbegin- TODO: Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- TODO: Place the data selector on the right side of the gate. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse æ‹¡å¼µãƒãƒ¼ã‚’利用 db.gate.aox.use.hdr æ‹¡å¼µãƒãƒ¼ db.gate.aox.nouse.hdr æ‹¡å¼µãƒãƒ¼ã‚’利用ã—ãªã„ db.gate.aox.use.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- TODO: Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LEDã®ã‚¿ã‚¤ãƒ— db.gate.led.bit.hdr ビット db.gate.led.bar.hdr 棒グラフ db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- TODO: Single-lamp LED display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- TODO: LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- TODO: Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- TODO: Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- TODO: Signal bits directly control LED segments. -end- db.seq.back <å‰ã¸ db.seq.next 次ã¸> db.hdl.savecap 複数ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« db.hdl.saveexp -fillbegin- TODO: The text buffer for the module you have just edited contains more than one module definition. Please select one of the three actions described on the right. -end- db.hdl.autoedit 自動変数 db.hdl.split 分離 db.hdl.comment コメント db.hdl.cancel キャンセル db.hdl.ignore 無視ã™ã‚‹ db.hdl.autoeditcap åå‰ãŒä¸€ç­‰ã—ãªã„ db.hdl.autoeditexp -fillbegin- TODO: The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- 回路ã«çµ„åˆã›ã®ãƒ«ãƒ¼ãƒ—ãŒç™ºè¦‹ã•ã‚ŒãŸã€‚クリティカル ・パスã®è§£æžã‚’è¡Œãªã„ãŸã‘ã‚Œã°ã€ãƒ«ãƒ¼ãƒ—上ã®ãƒãƒƒãƒˆ を切ã£ãŸã‚Šã€ãƒ«ãƒ¼ãƒ—上ã®ã‚²ãƒ¼ãƒˆã‚’「クリティカル・ パス分割点ã€ã«ã—ãŸã‚Šã™ã‚‹å¿…è¦ãŒã‚る。 -end- ############################################################################## # Print dialog box # print.outto 出力先 print.printer プリンター print.file ファイル print.prcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ print.prname プリンタ print.advanced オプション... print.filename ファイルå print.epssave Encapsulated Postscriptã¨ã—ã¦ã‚»ãƒ¼ãƒ–ã™ã‚‹. print.doctit ドキュメントã®é¡Œå print.epcm エãƒãƒƒã‚¯/cm print.estpg ページ数ã®è¦‹ç©ã‚‚ã‚Š print.all 全㦠print.cur ç¾åœ¨ print.use 使用中 print.sel 指定 print.inclib ライブラリ・ファイルもå°åˆ· print.papsz ページ・サイズ print.orient オリエンテーション print.portrait 縦 print.landscape 横 print.2side 両é¢å°åˆ· print.opts オプション print.scale 大ãã„モジュールをスケールã—ã¦ä¸€ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.partition 大ãã„モジュールを複数ã®ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.incidx インデックスをå«ã‚€ print.incgraph 階層グラフをå«ã‚€ print.4up å°ã•ã„モジュールを一é ã«å››ã¤ãšã¤å°åˆ·ã™ã‚‹ print.range レンジ print.scaleselect é¸æŠžç¯„囲をスケールã™ã‚‹ print.fulltr 全部 print.parttr 部分 print.start スタート print.end ストップ print.filesel ファイルã«å°åˆ· print.printersel プリンタã«å°åˆ· print.defaultprinter デフォルトã®ãƒ—リンタ print.pageset ページ・setup print.modulesel モジュールã®é¸æŠž ############################################################################## # # TkGate 2.0 print dialog strings # print.ok å°åˆ· print.printtrace.cap トレースã®å°åˆ· print.printcirc.cap 回路図ã®å°åˆ· print.printcirc.out.exp -begin- 回路図ã®å°åˆ·å…ˆãŒ プリンタã‹ãƒ•ã‚¡ã‚¤ãƒ« ã‹é¸æŠžã™ã‚‹ã€‚ -end- #probably not used print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã‚„å°åˆ·ã®æ§˜å­ã‚’é¸æŠž る。 -end- print.printtrace.trace.exp -fillbegin- 時間ã®ç¯„囲をé¸æŠžã™ã‚‹ã€‚ åˆã€ã‚¹ã‚±ãƒ¼ãƒ«ã«ã‚ˆã£ã¦ã€ å¿…è¦ã®ãƒšãƒ¼ã‚¸æ•°ã‚’表㋠評価ã™ã‚‹ã€‚ -end- print.tab.output å°åˆ·å…ˆ print.tab.page å°åˆ· print.tab.content 内容 ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 600 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 115 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 opt.general 一般 opt.interface インタフェース opt.toolbars ツール・ãƒãƒ¼ opt.editor HDL opt.print å°åˆ· opt.simulate シミュレート opt.library ライブラリ opt.analysis è§£æž opt.color 色 opt.html HTML opt.debug デãƒãƒƒã‚° opt.security セキュリティ opt.identity 正体 opt.site サイトå opt.username ユーザå opt.libname ライブラリå opt.inst インスタンス opt.mods モジュール opt.modports ãƒãƒ¼ãƒˆ opt.frames フレーム opt.comment コメント opt.hlink リンク opt.wire 1ビットã®ãƒ¯ã‚¤ãƒ¤ opt.bus 多ビットã®ãƒ¯ã‚¤ãƒ¤ opt.tools ツール opt.background ãƒãƒƒã‚¯ã‚°ãƒ©ã‚¦ãƒ³ãƒ‰ opt.cpath クリティカル・パス opt.grid スコープã®ã‚°ãƒªãƒƒãƒ‰ opt.logic1 è«–ç†ï¼‘ opt.logic0 è«–ç†ï¼ opt.float フロート opt.unknown ä¸æ˜Ž opt.offled オフã®LED opt.onled オンã®LED opt.zled フロートã®LED opt.restdef デフォールト opt.regudate リージョン・アップデート opt.smoothscroll スムーズ・スクロール opt.balloon ãƒãƒ«ãƒ¼ãƒ³ãƒ»ãƒ˜ãƒ«ãƒ—を利用 opt.safeSave 安全書ã込㿠opt.saveCells セーブファイルã«ã‚»ãƒ«ã‚’å«ã‚€ã€‚ opt.showimage TODO: Show side-bar images in dialog boxes opt.novice åˆå¿ƒè€…モード opt.blockDropConnect TODO: Wire drop port creation opt.ckpoint ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ opt.freq 期間 opt.beak 特別モードをå¯èƒ½ã«ã™ã‚‹ opt.bat ãƒãƒƒãƒˆãƒžãƒ³ opt.trek スター・トレック opt.miles マイルス opt.contver 内部構造ã®è‡ªå‹•ç¢ºèª opt.showsimcmd シミュレートã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ opt.estepsz エãƒãƒƒã‚¯ã®ã‚¹ãƒ†ãƒƒãƒ—æ•° opt.cstepsz クロックã®ã‚µã‚¤ã‚¯ãƒ«æ•° opt.overstep クロックã®ã‚ªãƒãƒ¼ã‚¹ãƒ†ãƒƒãƒ— opt.sorttraces TODO: Sort traces alphabetically on scope opt.vpopupdelay ä¿¡å·å€¤ã‚¦ã‚£ãƒ³ãƒ‰ã®è¡¨ç¤ºé…延 opt.initscript åˆæœŸåŒ–スクリプト opt.posedge å…¨ã¦ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.setclock 指定ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.delayfilepath é…延ファイル opt.devfilepath VPD(Virtual Periperal Device)ファイルã®ãƒ‘ス opt.vlibpath Verilogã®ãƒ©ã‚¤ãƒ–ラリã®ãƒ‘ス opt.vlibnames ベースã®ãƒ©ã‚¤ãƒ–ラリ opt.display ç”»é¢ opt.input 入力 opt.undolen 最大Undo opt.keybind キー・ãƒã‚¤ãƒ³ãƒ‡ã‚£ãƒ³ã‚°ã®ã‚¹ã‚¿ã‚¤ãƒ« opt.useless å½¹ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ opt.features 基本ã®æ©Ÿèƒ½ opt.simbase 基本ã®ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã®ã‚ªãƒ—ション opt.simclock クロックã®ã‚ªãƒ—ション opt.cpopts クリティカル・パス設定: opt.maxpath 最大パス数: opt.cpflash パスã®ç‚¹æ»…表示 opt.general.fontset フォント・サイズ opt.simulator.noglitch TODO: Enable simulator glitch suppression. opt.simulator.err TODO: Error Handling opt.simulator.stopany TODO: Cancel simulation on any warnings. opt.simulator.showall TODO: Always display warnings. opt.simulator.showiferr TODO: Display warnings only with errors. opt.simulator.ignore TODO: Ignore all warnings. opt.tool.file ファイル opt.tool.edit 編集 opt.tool.gateopt 回転ï¼æ•´åˆ—化 opt.tool.gateprop ゲート特徴 opt.tool.undo Undo/Redo opt.tool.zoom ズーム opt.tool.mode モード opt.tool.module モジュール opt.tool.tech テクノロジー opt.tool.simctl TODO: Simulator Control opt.tool.simaux TODO: Simulator Commands opt.tool.symmode モード opt.tool.symedit カットï¼ãƒšãƒ¼ã‚¹ãƒˆ opt.tool.symport ãƒãƒ¼ãƒˆ opt.tool.symshift ビット・マップã®ã‚·ãƒ•ãƒˆ opt.tool.symopr ビット・マップã®æ¼”ç®— opt.editor.features 基礎的ãªã‚¨ãƒ‡ã‚£ã‚¿ãƒ¼ã®æ©Ÿèƒ½ opt.editor.format 自動インデントを有効ã«ã™ã‚‹ opt.editor.colorize 自動色付ã‘を有効ã«ã™ã‚‹ opt.editor.comments コメント opt.editor.strings 文字列 opt.editor.reserved キーワード opt.editor.gateword ゲートå opt.editor.instword モジュールå opt.editor.taskword システム・タスク opt.editor.color 色 opt.editor.bold 太字 opt.editor.italic イタリック opt.editor.indentlevel TODO: Indentation per level: opt.editor.beginindent TODO: Make begin..end flush with enclosing level. opt.editor.movesel TODO: Enable drag-and-drop of selection. opt.editor.returntab TODO: Auto indent after return. opt.vercheck -begin- 定期的㫠tkgate ã®æ–°ã—ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã‚’インターãƒãƒƒãƒˆã§ ãƒã‚§ãƒƒã‚¯ã™ã‚‹ã€‚常時接続ã§ãªã‘ã‚Œã°æœ‰åŠ¹ã«ã—ãªã„ã“ã¨ã€‚ -end- opt.general.cap 一般オプション opt.editor.cap HDLテキスト・エディタ opt.interface.cap インタフェス・オプション opt.toolbars.cap ツールãƒãƒ¼ãƒ»ã‚ªãƒ—ション opt.print.cap å°åˆ·ã‚ªãƒ—ション opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap シミュレータ・オプション opt.security.cap セキュリティ・オプション opt.color.cap 色ã¥ã‘・オプション opt.html.cap HTML/HTTPオプション opt.debug.cap デãƒãƒƒã‚°ãƒ»ã‚ªãƒ—ション opt.library.cap ライブラリ・オプション opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.color.editwin 編集ウィンドウã®è‰²ã¥ã‘ opt.color.scopewin スコープ・ウィンドウã®è‰²ã¥ã‘ opt.vlibadd.cap ライブラリ追加 opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- TODO: Set personal identification and basic TkGate options here. The personal identification info. will be used on printed output. -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore ページã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ opt.bbar.restoreall å…¨ã¦ã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ ############################################################################## # # Interface generator # igen.port ãƒãƒ¼ãƒˆ igen.type タイプ igen.side サイド igen.size ビット幅 igen.bits ビット igen.modname モジュールå: igen.resort å†ã‚½ãƒ¼ãƒˆ igen.add 追加 igen.delete 削除 igen.edit 編集 igen.in å…¥ igen.out 出 igen.inout 入出 igen.left å·¦ igen.right å³ igen.top 上 igen.bottom 下 igen.other ä»– igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error スクリプトã®ã‚¨ãƒ©ãƒ¼ module.props モジュールã®ç‰¹å¾´ ipanel.plist ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ ipanel.props インタフェースã®ç‰¹å¾´ ipanel.itype.change タイプã®å¤‰æ›´... ipanel.itype.edsymbol シンプルã®ç·¨é›†... ipanel.block ブロック ipanel.symbol シンボル ipanel.autogen 自動作æˆ... ipanel.itype.select インタフェス・タイプ ipanel.itype.selectexp -begin- 長方形型ã®ã€Œãƒ–ロッ クã€ã‹ã€ãƒ“ットマッ プã®ã€Œã‚·ãƒ³ãƒœãƒ«ã€ã€ ã„ãšã‚Œã‹é¸æŠžã—㦠ãã ã•ã„。 -end- ipanel.block.description TODO: Block Interface ipanel.symbol.description TODO: Custom Symbol Interface ipanel.ppos.label ブロックã®ã‚µã‚¤ã‚ºã‚’変更ã™ã‚‹æ™‚ã®ãƒãƒ¼ãƒˆã®å–り扱ㄠipanel.ppos.fix 指定 ipanel.ppos.scale スケール ipanel.ppos.grid グリッド ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim å–å¾—ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.to æ–°è¦ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.from ç¾åœ¨ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.name モジュールå blklst.new.cap モジュールã®æ–°è¦ä½œæˆ blklst.del.cap 削除ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.copy.cap コピー・モジュール blklst.rename.cap モジュールã®æ”¹å blklst.claim.cap モジュールã®å–å¾— blklst.setroot.cap トップ・モジュールã®é¸æŠž blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label 探索 find.exp -fillbegin- ゲートåã€ãƒãƒƒãƒˆå〠コメントãªã©ã®ä¸­ã« 指定ストリングを 探索ã™ã‚‹ã€‚ -end- find.ignorecase ケースを無視ã™ã‚‹ã€‚ find.result.module モジュールå find.result.type タイプ find.result.name オブジェクトå # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options 探索ã®ã‚ªãƒ—ション find.results 探索ã®çµæžœ # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ã‚’å«ã‚€ find.qual.begins ã‹ã‚‰å§‹ã¾ã‚‹ find.qual.ends ã§çµ‚ã‚‹ find.qual.matches åŒç­‰ã™ã‚‹ find.dom.label 以下ã®å ´æ‰€ã‚’探索ã™ã‚‹ã€‚ find.dom.gates ゲート find.dom.nets ãƒãƒƒãƒˆ find.dom.text コメントã®ãƒ†ã‚­ã‚¹ãƒˆ find.search 探索: find.target 探索ã®ç¯„囲 # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label 回路ã®ç‰¹å¾´ circ.ident TODO: Identification circ.filev ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ circ.file ファイルå circ.title 回路å circ.discchg 変更を無視ã™ã‚‹ circ.extbar æ‹¡å¼µãƒãƒ¼ã‚’利用ã™ã‚‹ã€‚ circ.autostart シミュレーションã®è‡ªå‹•é–‹å§‹ã‚’有効ã«ã™ã‚‹ã€‚ circ.iniscript åˆæœŸåŒ–スクリプト circ.noscript スクリプト・ファイルã¯æŒ‡å®šã•ã‚Œã¦ã„ãªã„。 circ.really TODO: Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general 一般 circ.library ライブラリ circ.script スクリプト circ.simulator シミュレーション circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # # Library Manager # libmgr.cap ライブラリ・マãƒã‚¸ãƒ£ãƒ¼ libmgr.library ライブラリå libmgr.description 説明 libmgr.status 状態 libmgr.status.load 利用 libmgr.status.unload éžåˆ©ç”¨ libmgr.status.loadp TODO: [利用] libmgr.status.unloadp TODO: [éžåˆ©ç”¨] libmgr.exp -begin- 利用ã™ã‚‹ãƒ©ã‚¤ãƒ–ラリをé¸æŠžã™ã‚‹ã€‚ -end- libmgr.load 利用 libmgr.unload éžåˆ©ç”¨ libmgr.unloadall å…¨ã¦ã‚’éžåˆ©ç”¨ libmgr.notedit -fillbegin- 回路図ã®ã‚¨ãƒ‡ã‚£ã‚¿ãŒé–‹ã„ã¦ã„る時ã®ã¿ã€ ライブラリã®ãƒžãƒã‚¸ãƒ£ãƒ¼ãŒåˆ©ç”¨å‡ºæ¥ã‚‹ã€‚ -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab ブレークãƒã‚¤ãƒ³ãƒˆ break.id ç•ªå· break.state 状 break.condition æ¡ä»¶ break.value 値 ############################################################################## # Simulator # sim.breakpt ブレークãƒã‚¤ãƒ³ãƒˆ sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay パスé…延: cp.pathl パスã®ä¸€è¦§: cp.numpath パス数: cp.recompute å†è¨ˆç®— ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin é¸æŠžã•ã‚ŒãŸãƒ”ンã®ã‚¿ã‚¤ãƒ—を変更出æ¥ãªã„。 err.badhex ä¸æ­£ã®16進数ã®å€¤ã¯ç„¡è¦–ã•ã‚ŒãŸã€‚ err.gatanchor ゲートãŒç§»å‹•ä¸å¯ã«ãƒžãƒ¼ã‚¯ã•ã‚Œã¦ã„る為ã€ç§»å‹•å‡ºæ¥ãªã„。 err.protdata TODO: Can not modify contents of protected or library module. err.badfind 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badopendel 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’削除出æ¥ãªã„。 err.nosrcmod ソース・モジュール'%s'ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.noerr エラー・メッセージãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.misserr エラー情報ãŒä¸å®Œå…¨ã§ã‚る。(シミュレータãŒè½ã¡ãŸï¼Ÿ) err.badinadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥åŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badinoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badpinchg é¸æŠžã®ã‚²ãƒ¼ãƒˆã®ãƒ”ンã®ã‚¿ã‚¤ãƒ—ãŒå¤‰æ›´å‡ºæ¥ãªã„。 err.badnetname åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為削除ã•ã‚ŒãŸã€‚ err.netbcrename 指定ã®åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為ã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfnet 指定ã®åå‰ãŒåˆ¥ã®åå‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfgat 指定ã®åå‰ãŒåŸºç¤Žã®ã‚²ãƒ¼ãƒˆåã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfkw 指定ã®åå‰ãŒã‚­ãƒ¼ãƒ¯ãƒ¼ãƒ‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.badconsame ãƒãƒƒãƒˆãŒåŒã˜ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconptsp ãƒãƒƒãƒˆã®ä¸¡æ–¹ãŒãƒãƒ¼ãƒˆåˆã¯é›»åŠ›ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconbitw ãƒãƒƒãƒˆã®ãƒ“ット幅ãŒç•°ãªã‚‹ã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badrange 指定ã•ã‚ŒãŸæ™‚é–“ã®ãƒ¬ãƒ³ã‚¸ãŒä¸æ­£ã§ã‚る。 err.badlprcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒå®Ÿè¡Œå‡ºæ¥ãªã„。 err.badpsopen ãƒã‚¹ãƒˆãƒ»ã‚¹ã‚¯ãƒªãƒ—トを「%sã€ã«æ›¸ãè¾¼ã‚ãªã„。 err.badid 「%sã€ã¯ä¸æ­£ã®åå‰ã§ã‚る。 err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp ä¸æ­£ãªãƒ–レークãƒã‚¤ãƒ³ãƒˆã®æ¡ä»¶ã§ã‚る。「netã€, 「!netã€, 「net==valueã€, 「net!=valueã€ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.bkpt.badnet ä¸æ­£ã®ãƒãƒƒãƒˆåã§ã‚る。 err.bkpt.badval ä¸æ­£ã®å€¤ã§ã‚る。10進数ã‚ã‚‹ã„ã¯ã€verilogå½¢å¼ã®å€¤ã—ã‹èªè­˜ã•ã‚Œã¦ã„ãªã„。 err.bkpt.toomany ブレークãƒã‚¤ãƒ³ãƒˆãŒå¤šéŽãŽã‚‹ã€‚制é™ã¯%dã§ã‚る。 err.sim.badtmp /tmpã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ›¸ãè¾¼ã‚ãªã‹ã£ãŸï¼ˆãƒ‡ã‚£ã‚¹ã‚¯ãŒã„ã£ã±ã„ã‹ï¼‰ã€‚ err.sim.syntx ä¸æ­£ã®ã€Œ%sã€ã‚³ãƒžãƒ³ãƒ‰ err.sim.noincl インクルード・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ err.sim.badedge clockコマンドã®ã‚¨ãƒƒã‚¸'%c'ãŒä¸æ­£ã§ã‚る。 err.sim.nobkpt ブレーク・ãƒã‚¤ãƒ³ãƒˆã€Œ%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.sim.nonet ãƒãƒƒãƒˆã€Œ%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.nogate ゲート「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.badbin 2進数ã®å€¤ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る。 err.sim.notswitch ゲート'%s'ã¯ã‚¹ã‚¤ãƒƒãƒã€DIPã€ãƒ¬ã‚¸ã‚¹ã‚¿ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.sim.badcmd シミュレーション・スクリプトã«ä¸æ­£ã®ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒã‚る。 err.sim.isrun シミュレータã¯æ—¢ã«å®Ÿè¡Œã—ã¦ã„る。 ('Ctrl-s e'ã§çµ‚了ã™ã‚‹). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg 設定ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ä»¥å¤–ã€å¤‰æ›´ä¸å¯ã€‚ err.badeditop 編集コマンドã«ä¸æ­£ãŒã‚る。 err.badopen 回路ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badlibopen ライブラリ・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.nomark ゲート種をé¸ã¶å‰ã«ã€ãƒžã‚¦ã‚¹ã§ä½ç½®ã‚’設定ã—ã¦ãã ã•ã„。 err.badgate ゲート種ãŒæœªå®šç¾©ã§ã‚る。 err.badportadd é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã¯è¿½åŠ ä¸å¯ã€‚ err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- ページ数ãŒæ¥µã‚ã¦å¤§ãã„。 本当ã«å°åˆ·ã—ã¾ã™ã‹? -end- err.nojump -fillbegin- ç¾åœ¨ã€'jump-to-module'機能ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ç”¨å‡ºæ¥ãªã„。 トップ・モジュールよりã€ã€Œ>ã€ã‚„「<ã€ã®ã‚³ãƒžãƒ³ãƒ‰ã§ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã‘ã¦ãã ã•ã„。 -end- err.nomod モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.modlock モジュールãŒãƒ­ãƒƒã‚¯ã—ã¦ã„る。 err.closeroot トップ・モジュールãŒé–‰ã˜ã‚Œãªã„。 err.editonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ãˆãªã„。 err.simonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ã—ã‹ä½¿ãˆãªã„。 err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel ゲートをé¸æŠžã—ã¦ã„ãªã„。 err.modnotdef モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.moddef モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã—ã¦ã„る。 err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã¯ç·¨é›†å‡ºæ¥ã‚‹è¨­å®šãŒãªã„。 err.openscript シミュレーション・スクリプト「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.oldversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³(%s)ãŒå¤ã„。(ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s). err.futureversion 未æ¥ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ï¼ˆ%s）ã®tkgateファイルã§ã‚る。（ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s） err.badversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒèªè­˜å‡ºæ¥ãªã„。注æ„ã—ã¦åˆ©ç”¨ä¸‹ã•ã„。 err.nodrive ãƒãƒƒãƒˆ%sã¯ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«%sã«ä¿¡å·ã®ã‚½ãƒ¼ã‚¹ãŒãªã„。 err.noconn ワイヤ%s{%d}ã¯æŽ¥ç¶šãŒãªã„（削除ã—ãŸï¼‰ã€‚ err.oldportact ãƒãƒ¼ãƒˆã‚„モジュールã®ç«¯ã«å³ã‚¯ãƒªãƒƒã‚¯ã—ã¦ä¸‹ã•ã„。 err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail ãƒãƒƒã‚¯ã‚¢ãƒƒãƒ—・ファイル'%s'ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã€‚ err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TkGateã¯'%s'ã«ã‚»ãƒ¼ãƒ–出æ¥ãŸãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ··ä¹±ã•ã‚Œã¦ã„ã‚‹ã¿ãŸã„。もã—ãƒã‚§ãƒƒ ク・ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’使ã£ã¦ã¿ã¦ã ã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.corruptsave -fillbegin- '%s'をセーブã—よã†ã¨ã—ã¦ã„る時ã€TkGateã«å†…部å•é¡ŒãŒç™ºè¦‹ã—ãŸã€‚元々ã®ãƒ•ã‚¡ã‚¤ ルã¯ãã®ã¾ã¾æ®‹ã—ã¦ã‚る。混乱ã•ã‚Œã¦ã„ã‚‹å¯èƒ½æ€§ã®ã‚るファイルã¯'%s'ã«ã‚»ãƒ¼ãƒ– ã—ãŸã€‚ã‚‚ã—ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ ルを使ã£ã¦ã¿ã¦ãã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.badsave -fillbegin- '%s'をセーブ出æ¥ãªã‹ã£ãŸã€‚ファイルã®ãƒ—ロテクションや空ãディスクé‡ã‚’ç¢ºèª ã—ã¦ãã ã•ã„。 -end- err.nosafesave -fillbegin- '%s'ã®å®‰å…¨ã‚»ãƒ¼ãƒ–ã‚’è¡Œã†ãŸã‚ã®ä¸€æ™‚ã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã‹ã‚‰ã€ç›´æŽ¥ã‚»ãƒ¼ ブã—ãªãã¦ã¯ãªã‚‰ãªã„。「NOã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€å…ƒã€…ã®ãƒ•ã‚¡ã‚¤ãƒ«ã¯ãã®ã¾ã¾æ®‹ ã™ã€‚「YESã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€ã‚»ãƒ¼ãƒ–ã™ã‚‹ãŒã€ã‚»ãƒ¼ãƒ–途中ã«å•é¡ŒãŒèµ·ã“ã£ãŸã‚‰ã€ 回路データãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚る。直接セーブã—ã¦ã¿ã¾ã—ょã†ã‹ã€‚ -end- err.noback -fillbegin- tkgateãƒãƒ¼ã‚¸ãƒ§ãƒ³%sã§ä½œã‚‰ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ã§ã‚る。ä¿å­˜ã™ã‚‹ã¨ã€ tkgateã®å¤ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã«èª­ã¿è¾¼ã‚ãªã„ã“ã¨ãŒã‚る（ç¾åœ¨ã® ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%sã§ã‚る）。 -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selgate %2$sã¨ã„ã†%1$sゲートãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selblock %2$sã¨ã„ã†%1$sモジュールãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã•ã‚Œã¦ã„る。定義ã—ãªãŠã—ã¾ã™ã‹? msg.foundgate %sã¨ã„ã†ã‚²ãƒ¼ãƒˆãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.foundwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.searchagn 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ã‚‚ã†ä¸€åº¦ã€ŒæŽ¢ç´¢ã€ã‚’押ã™ã¨ã€æŽ¢ç´¢ã—ãªãŠã™ã€‚ msg.sim.chgtoroot シミュレーション・モードã§ã¯ã€ãƒˆãƒƒãƒ—・モジュールãŒãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ã®ãƒˆãƒƒãƒ—ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 msg.sim.nogatemod シミュレーション・モードã§ã€å…·ä½“çš„ãªãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ãŒå¿…è¦ã§ã‚る。 msg.setinterface モジュール「%sã€ã®ã‚¤ãƒ³ã‚¿ãƒ•ã‚§ãƒ¼ã‚¹ã‚’セットã—ãŸã€‚ msg.needsel モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ã‚’é¸ã‚“ã§ãã ã•ã„。 msg.wroteckpt 「%sã€ã«ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆã‚’書ã込んã ... msg.save 「%sã€ã«ä¿å­˜ã—ãŸã€‚ msg.reallynew 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€æ–°ã—ã„回路を開ãã¾ã™ã‹? msg.reallyquit 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€çµ‚了ã—ã¾ã™ã‹? msg.notlib モジュール「%sã€ã¯ãƒ©ã‚¤ãƒ–ラリ・モジュールã§ã¯ãªã„。 ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€ãŠå‰ã¿ãŸã„ãªå¤§é¦¬é¹¿ã—ã‹ã„ãªã„よ。 miles.msg2 é¦¬é¹¿ï¼ miles.msg3 æ„šã‹ã‚‚ã®ï¼ miles.msg4 マイルスã€ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€é¦¬é¹¿ã ã‚ˆã€‚ miles.msg5 馬鹿ãªã‚²ãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ã‚’ã‚„ã‚ã¦ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg6 ゲートをãã®ä½ç½®ã«ãŠã„ãŸã®ã¯ã€ãŠå‰ã®æ„šã‹ã•ã®è¨¼æ˜Žã ã‚ˆã€‚ miles.msg7 ã“ã®ãƒ­ã‚¯ã§ãªã—回路ã®è¨­è¨ˆã‚’諦ã‚よã€ãƒžã‚¤ã‚¹ãƒ«ã€‚ miles.msg8a 続ã‘ã¦ã‚‚ã€ç„¡é§„ã ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg8b ãŠå‰ãŒå›žè·¯ã‚’設計出æ¥ãªã„ã¨ã„ã†ã®ã¯ã€èª°ã§ã‚‚分ã‹ã‚‹ã‚ˆã€‚ ############################################################################# # # Error messages generated by verga # verga.err.OK 心é…ã—ãªã„ã§ã€ç¬‘ã£ã¦ãã ã•ã„。 verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # Balloon Help # ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ç¾åœ¨ã®å›žè·¯ã‚’消ã—ã¦ã€æ–°ã—ㄠ回路を作æˆã™ã‚‹ã€‚ -end- ho.open 回路ファイルを開ã ho.save 回路ファイルをä¿å­˜ã™ã‚‹ ho.saveas TODO: Save circuit to specified file. ho.print 回路ファイルをå°åˆ·ã™ã‚‹ ho.library TODO: Open the library manager. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- 移動ï¼æŽ¥ç¶š - ã“ã®ãƒ„ールã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ æ–°ã—ã„ゲートã®ä½ç½®ã‚’設定ã™ã‚‹ ゲートを移動ã™ã‚‹ ワイヤを移動ã™ã‚‹ ワイヤを接続ã™ã‚‹ ダブル・クリックã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ ゲートã®å±žæ€§ã‚’編集ã™ã‚‹ ワイヤã®å±žæ€§ã‚’編集ã™ã‚‹ ãƒãƒ¼ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ コメントã®ãƒ†ã‚­ã‚¹ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ -end- ho.delgat -begin- ã“ã®ãƒ„ールã§ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ -end- ho.cutw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã‚’切断ã™ã‚‹ -end- ho.inv -begin- ã“ã®ãƒ„ールã§ã€ã‚²ãƒ¼ãƒˆã®å…¥å‡ºåŠ›ã« å¦å®šã‚’付ã‘ãŸã‚Šã€æ¶ˆã—ãŸã‚Šã™ã‚‹ã€‚ -end- ho.bitw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã®ãƒ“ット幅を 変更ã™ã‚‹ã€‚ビット幅をå³ä¸‹ã®å…¥åŠ› ボックスã«å…¥åŠ›ã—ã¦ãã ã•ã„。 -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open é¸æŠžã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã ho.mod.close ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‰ã˜ã‚‹ ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo 最近行ã£ãŸå¤‰åŒ–を元通りã«ã™ã‚‹ã€‚ ho.redo undoã—ãŸå¤‰åŒ–ã‚’ã‚„ã‚Šç›´ã™ã€‚ ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- シミュレータを開始ã—ã€è«–ç†ã‚¢ãƒŠãƒ©ã‚¤ã‚¶ã®ã‚¦ã‚£ãƒ³ãƒ‰ã‚’ é–‹ãã€ãã—ã¦åˆæœŸåŒ–スクリプトãŒå®šç¾©ã—ã¦ã„ã‚‹å ´åˆã€ ãã®ã‚¹ã‚¯ãƒªãƒ—トを実行ã™ã‚‹ã€‚ -end- ho.tab.cpath -begin- 回路ã®ã‚¯ãƒªãƒ†ã‚£ã‚«ãƒ«ãƒ»ãƒ‘スを探索ã™ã‚‹ã€‚ -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- シミュレータを動ã‹ã™ã€‚組åˆã›å›žè·¯ã®å ´åˆã€ ä¿¡å·ãŒå¤‰ã‚らãªããªã‚‹æ™‚ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ ãŒä¸€æ™‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.simpause -begin- シミュレータã®ä¸€æ™‚åœæ­¢ -end- ho.simstep -begin- シミュレータを一定数ã®ã‚¨ãƒãƒƒã‚¯ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simclock -begin- シミュレータを一定数ã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚µã‚¤ã‚¯ãƒ« ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simstop -begin- シミュレータをåœæ­¢ã—ã¦ã€ 編集モードã«æˆ»ã‚‹ã€‚ -end- ho.simbreak -begin- シミュレータã®ãƒ–レークãƒã‚¤ãƒ³ãƒˆ を編集ã™ã‚‹ã€‚ -end- ho.simexec -begin- スクリプトを実行ã™ã‚‹ã€‚ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- メモリ・ファイルを読ã¿è¾¼ã‚€ -end- ho.simdump -begin- メモリ・ファイルã«æ›¸ã出㙠-end- ho.f.modlist -begin- 読ã¿è¾¼ã‚“ã§ã‚るモジュールã®ä¸€è¦§è¡¨ã€‚ トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®åå‰ã«ã€Œ+ã€ãŒ 付ã„ã¦ã„る。ライブラリã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã¯æ‹¬å¼§ã«å›²ã¾ã‚Œã¦ã„る。 -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ä¸€è¦§è¡¨ã€‚åå‰ã‚’éš ã—㦠ã„ã‚‹ãƒãƒƒãƒˆã®åå‰ã«ã€Œ@ã€ãŒä»˜ã„ã¦ã„る。 マルãƒãƒ»ãƒ“ットã®ãƒãƒƒãƒˆã®åå‰ã®å¾Œã« ビットã®ãƒ¬ãƒ³ã‚¸ã‚’表示ã—ã¦ã„る。 -end- ho.ports -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ã€‚ 入力ã«ã€Œ>ã€ã€å‡ºåŠ›ã«ã€Œ<ã€ã€å…¥å‡ºåŠ›ã« 「=ã€ãŒä»˜ã„ã¦ã„る。 -end- ho.status.logo -begin- ç¾åœ¨ã®ãƒ¢ãƒ¼ãƒ‰ãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。鉄ã®ã‚²ãƒ¼ãƒˆ ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ã‚’表ã™ã€‚ANDゲートã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ ション・モードを表ã™ã€‚ANDゲートãŒèµ°ã£ã¦ ã„る時ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ãŒå‹•ã„ã¦ã„る。 -end- ho.status.msg tkgateよりã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ãŒã“ã“ã«è¡¨ç¤ºã•ã‚Œã‚‹ã€‚ ho.status.block ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒ‘ス ho.status.file -begin- ç¾åœ¨ç·¨é›†ä¸­ã®ãƒ•ã‚¡ã‚¤ãƒ«åãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。「*〠ã¨ã„ã†è¨˜å·ãŒã¤ã„ã¦ã„る時ã€ä¿å­˜ã—ã¦ã„ãªã„変更 ãŒã‚る。 -end- ho.print.selall å…¨ã¦ã®èª­ã¿è¾¼ã‚“ã§ã„るモジュールをå°åˆ·ã™ã‚‹ã€‚ ho.print.selcur ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ ho.print.seluse -begin- 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿å°åˆ·ã™ã‚‹ã€‚ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- 以下ã«ãƒžãƒ¼ã‚¯ã—ã¦ã„るモジュールã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ コントロール・キーã§è¤‡æ•°ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠž 出æ¥ã‚‹ã€‚ -end- ho.print.modlist å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠžã™ã‚‹ã€‚ ho.circuit.discchg -begin- 有効ã«ã™ã‚‹ã¨ã€å¤‰æ›´ã‚ã‚Šã®å›žè·¯ã‚’ ä¿å­˜ã—ãªã„ã§é–‰ã˜ã‚‹ã¨ã警告ã—ãªã„。 -end- ho.circuit.extbar -begin- 基本ゲート(AND, OR, XOR)ã®å…¥åŠ›æ•°ãŒ 3本以上ã®æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã™ã‚‹ã€‚ -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- カーソルã§é¸æŠžã•ã‚ŒãŸãƒ¯ã‚¤ãƒ¤ã¯è¡¨ç¤º ã•ã‚Œã¦ã„るビット幅ã«è¨­å®šã•ã‚Œã‚‹ã€‚ -end- ho.edgat.signam -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã§ã‚る。åå‰ãŒå¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.port -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆåã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.iolab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆæ–¹å‘ã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.bitlab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒ“ット幅ã§ã‚る。変更出æ¥ã‚‹ã€‚ -end- ho.edgat.cycle 一サイクルã®ã‚¨ãƒãƒƒã‚¯æ•° ho.edgat.phase クロックã®ãƒ•ã‚§ãƒ¼ã‚ºï¼ˆãƒ‘ーセントã§è¨­å®šã™ã‚‹ï¼‰ ho.edgat.duty クロック・サイクルã®ä½•ãƒ‘ーセントãŒè«–ç†0ã§ã‚ã‚‹ã‹ ho.edgat.hide -begin- 有効ã«ã™ã‚‹ã¨ã‚²ãƒ¼ãƒˆåãŒè¡¨ç¤ºã•ã‚Œãªã„。 -end- ho.edgat.gtype ゲートã®ç¨®é¡ž ho.edgat.gname ゲートã®åå‰ ho.edgat.ganchor 有効ã«ã™ã‚‹ã¨ã€ã‚²ãƒ¼ãƒˆãŒç§»å‹•ä¸å¯ã«ãªã‚‹ã€‚ ho.edgat.gx ゲートã®Xä½ç½® ho.edgat.gy ゲートã®Yä½ç½® ho.edgat.swstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.dipstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.range マルãƒãƒ“ットã®ä¿¡å·ã®ã‚µãƒ–・レンジã§ã‚る。 ho.edgat.memfile -begin- メモリã®åˆæœŸã®å€¤ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’指定ã™ã‚‹ã€‚ シミュレーションを始ã‚る時ã€ã“ã®ãƒ•ã‚¡ã‚¤ãƒ« ãŒèª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.edgat.func モジュールã®æ©Ÿèƒ½ ho.edgat.frame フレームã®ãƒ©ãƒ™ãƒ« ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undoã®ãƒªã‚¹ãƒˆã®é•·ã• -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- 回路ãªã©ã‚’å°åˆ·ã™ã‚‹æ™‚ã€ã“ã®ã‚µã‚¤ãƒˆåãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.smooth -begin- ã“ã®è¨­å®šã‚’有効ã«ã™ã‚‹ã¨ã€å›žè·¯ã‚’スクロールã™ã‚‹æ™‚〠ビットマップã®ã‚³ãƒ”ーを利用ã—ã¦ã€åŠ¹çŽ‡ã‚ˆã スクロールã§ãる。Xサーãƒã®å•é¡ŒãŒã‚ã‚Œã°ã€ã“㮠設定を無効ã«ã™ã‚Œã°è‰¯ã„。 -end- ho.opt.clip -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¦ã‚¤ãƒ³ãƒ‰ã‚¦ã®éƒ¨åˆ†é ˜åŸŸã® å†æ画を行ãªã†ã€‚ãã†ã§ãªã‘ã‚Œã°å¸¸ã« 全領域をå†æç”»ã™ã‚‹ã€‚ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’移動ã™ã‚‹æ™‚〠ワイヤãªã©ã¯ãƒžã‚¦ã‚¹ã®ãƒœã‚¿ãƒ³ã‚’離ã™ã¾ã§ 移動ã—ãªã„。画é¢ã®è¡¨ç¤ºãŒé…ã„時ã«ä¾¿åˆ©ã§ã‚る。 -end- ho.opt.bhelp -begin- 有効ã«ã™ã‚‹ã¨ã€ã“ã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ã®æ§˜ãªã€Œãƒ˜ãƒ«ãƒ—・ ãƒãƒ«ãƒ¼ãƒ³ã€ãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.novice -begin- 有効ã«ã™ã‚‹ã¨ã€åˆå¿ƒè€…モードã«ãªã‚‹ã€‚ åˆå¿ƒè€…モードã§ã¯ã€tkgateãŒç«‹ã¡ä¸ŠãŒã‚‹æ™‚〠ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ«ãŒè‡ªå‹•çš„ã«èª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ‡ãƒã‚°æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ 開発者以外ã«ã€ã‚ã¾ã‚Šå½¹ã«ç«‹ãŸãªã„。 -end- ho.opt.ckpt 有効ã«ã™ã‚‹ã¨ã€tkgateã¯ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’作る。 ho.opt.ckptfreq ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã‚’何クリック毎ã«è¡Œãªã†ã‹ ho.opt.beak -begin- 全然役ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ã€‚ã“ã®æ©Ÿèƒ½ã‚’ 無効ã«ã™ã‚‹ã¨ã€ã“ã®ã‚¹ã‚¤ãƒƒãƒã¯ãƒ€ã‚¤ã‚¢ãƒ­ã‚° ボックスã‹ã‚‰æ¶ˆãˆã€.tkgate-propertiesを編集ã—ãªã„é™ã‚Š 戻らãªã„。 -end- ho.opt.miles -begin- 有効ã«ã™ã‚‹ã¨ã€tkgateã¯æ™‚々ユーザを 馬鹿ã«ã—ãŸã‚Šã€æ‚ªå£ã‚’言ã£ãŸã‚Šã™ã‚‹ã€‚ -end- ho.opt.bat -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒãƒƒãƒˆãƒžãƒ³ã®ã‚³ãƒ³ãƒ”ュータを 設計ã™ã‚‹ç‚ºã«ã€Œå½¹ã«ãŸã¤ã€æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ -end- ho.opt.trek 転é€ã—ã‚ã€ã‚¹ã‚³ãƒƒãƒ†ã‚£ï¼ ho.opt.simstep -begin- シミュレータã®ã‚¹ãƒ†ãƒƒãƒ—・コマンド㧠何エãƒãƒƒã‚¯é€²ã‚€ã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckstep -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ã‚¹ãƒ†ãƒƒãƒ—・ コマンド㧠何サイクル進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckover -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ クロックã®ã‚¨ãƒƒã‚¸ã‚ˆã‚Šæ›´ã«ä½•ã‚¨ãƒãƒƒã‚¯ 進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.vpopupdelay -begin- マウスボタンを押ã—ã¦ã‹ã‚‰ã€ä½•ãƒŸãƒªç§’経ã£ã¦ ã‹ã‚‰ä¿¡å·ã®å€¤ãŒè¡¨ç¤ºã•ã‚Œã‚‹é…延ã§ã‚る。 ã“ã® é…延ãŒçŸ­éŽãŽã‚‹æ™‚ã€ãƒ€ãƒ–ルクリック㌠èªçŸ¥ ã§ããªããªã‚‹å•é¡ŒãŒã‚るシステム㯠ã‚る。 ã“ã®å•é¡ŒãŒèµ·ã“らãªã‘ã‚Œã°ã€é…延 をより 短ãã—ã¦ã‚‚良ã„。 -end- ho.opt.init -begin- シミュレータを立ã¡ä¸Šã’る時㫠自動的ã«å®Ÿè¡Œã™ã‚‹ã‚¹ã‚¯ãƒªãƒ—ト・ ファイルを指定ã™ã‚‹ã€‚ -end- ho.opt.ckall -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ ã©ã®ã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã§ã‚‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.ckspec -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ 指定ã—ãŸã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã®ã¿ã«åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- æ–°ã—ã„ゲートã®ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ã€‚ ゲートã®é…延ã«å½±éŸ¿ã™ã‚‹ã€‚ä»»æ„ã®ã‚²ãƒ¼ãƒˆ 㮠テクノロジーを変更ã™ã‚‹ã«ã¯ã€ã‚²ãƒ¼ãƒˆã®è¨­å®š ボックスを開ã„ã¦ã€ã€Œé…延ã€ã®ã‚¿ãƒ– ã‚’é¸æŠž ã—ã¦ä¸‹ã•ã„。 -end- ho.techbut -begin- 指定ã—ãŸãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ãƒ»ãƒ•ã‚¡ã‚¤ãƒ«ã‹ã‚‰ã® é…延値を 利用ã™ã‚‹ã€‚æ–°ã—ã„テクノロジーを 追加ã™ã‚‹ç‚ºã€ã€Œãƒ•ã‚¡ã‚¤ãƒ«ã€â†’「設定...ã€â†’ 「シミュレート〠ã®ãƒ¡ãƒ‹ãƒ¥ãƒ¼ã‚’é–‹ã„ã¦ã€ ファイルã®ãƒªã‚¹ãƒˆã«è¿½åŠ  ã—ã¦ä¸‹ã•ã„。 -end- ho.custbut -begin- ã“ã®ã‚²ãƒ¼ãƒˆå°‚用ã®é…延値を指定ã™ã‚‹ã€‚ -end- ho.contver -begin- マウスæ“作を行ãªã†æ™‚ã€å†…部構造を自動的㫠確èªã—ã¦ã€ä¸æ­£ã®æ‰€ã‚’知らã™ã€‚ -end- ho.simwatch -begin- シミュレータã¨GUIã®é–“ã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ã€‚ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin ズーム・イン ho.tool.zoomout ズーム・アウト ho.tool.rotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’éžæ™‚計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.brotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’時計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.valgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’縦ã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.halgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ç¿Œã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.cut é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚«ãƒƒãƒˆã™ã‚‹ã€‚ ho.tool.copy é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚³ãƒ”ーã™ã‚‹ã€‚ ho.tool.paste カットãƒãƒƒãƒ•ã‚¡ã®ã‚²ãƒ¼ãƒˆã‚’張り付ã‘る。 ho.tool.find ゲートã€ãƒ¯ã‚¤ãƒ¤ã€ãƒ†ã‚­ã‚¹ãƒˆãªã©ã‚’探索ã™ã‚‹ã€‚ ho.tool.addport é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã‚’追加ã™ã‚‹ã€‚ ho.tool.anchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動ä¸å¯ã«ã™ã‚‹ã€‚ ho.tool.unanchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動å¯èƒ½ã«ã™ã‚‹ã€‚ ho.tool.replicate ゲートを複製ã™ã‚‹ã€‚ ho.tool.delete é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ã€‚ tkgate-2.0-b10/locale/ja/messages~000644 001751 001751 00000246733 11145621531 017605 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Feb 14 15:02:33 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # \font-encoding iso8859-1 \messages-encoding euc-jp \verilog-encoding euc-jp \display-encoding euc-jp \language Japanese ############################################################################## # # basic strings # b.new ¿·µ¬... b.dismiss ÊĤ¸¤ë b.close ÊĤ¸¤ë b.ok £Ï£Ë b.clear ¥¯¥ê¥¢ b.cancel ¥­¥ã¥ó¥»¥ë b.open ³«¤¯ b.bitw ¥Ó¥Ã¥ÈÉý b.in Æþ b.out ½Ð b.inout Æþ½Ð b.browse ÁªÂò... b.label ̾Á° b.find õº÷ b.edit ÊÔ½¸... b.add ÄɲÃ... b.delete ºï½ü b.deleteb ºï½ü... b.remove ¾Ã¤¹ b.apply ¥»¥Ã¥È b.anchor °ÜÆ°ÉÔ²Ä b.tech ¥Æ¥¯¥Î¥í¥¸¡¼ b.enable ²Äǽ¤Ë¤¹¤ë b.disable ̵ǽ¤Ë¤¹¤ë b.flush ¥¯¥ê¥¢ ############################################################################## # # Main tab strings # tab.edit ÊÔ½¸ tab.editintr ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ tab.simulate ¥·¥ß¥å¥ì¡¼¥È tab.cpath ÃÙ±ä²òÀÏ # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add ÄɲÃ... mm.delete ºï½ü mm.edit ÊÔ½¸... mm.enable Í­¸ú¤Ë¤¹¤ë mm.disable ̵¸ú¤Ë¤¹¤ë ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ¥Õ¥¡¥¤¥ë menu.edit ÊÔ½¸ menu.tool ¥Ä¡¼¥ë menu.simulate ¥·¥ß¥å¥ì¡¼¥È menu.module ¥â¥¸¥å¡¼¥ë menu.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.format ¥Õ¥©¡¼¥Þ¥Ã¥È menu.make ¥³¥ó¥Ý¡¼¥Í¥ó¥È menu.help ¥Ø¥ë¥× menu.file.new ¿·µ¬ºîÀ® menu.file.open ³«¤¯... menu.file.openlib ¥é¥¤¥Ö¥é¥ê´ÉÍý... menu.file.save Êݸ menu.file.saveas ̾Á°¤òÉÕ¤±¤ÆÊݸ... menu.file.print °õºþ... menu.tool.options ÀßÄê... menu.file.quit ½ªÎ» menu.file.cprop ²óÏ©¤ÎÆÃħ... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut ¥«¥Ã¥È menu.edit.copy ¥³¥Ô¡¼ menu.edit.paste ¥Ú¡¼¥¹¥È menu.edit.overlay OverlayÄ¥¤êÉÕ¤± menu.edit.selall Á´¤Æ¤òÁªÂò menu.edit.find ²óÏ©¤òõº÷... menu.edit.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.edit.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.edit.rshift ±¦¥·¥Õ¥È menu.edit.lshift º¸¥·¥Õ¥È menu.edit.ushift ¾å¥·¥Õ¥È menu.edit.dshift ²¼¥·¥Õ¥È menu.edit.cwrotate »þ·×¼þ¤ê²óž menu.edit.ccwrotate »þ·×È¿Âмþ¤ê²óž menu.edit.pcwrotate ¥Ý¡¼¥È¤Î»þ·×¼þ¤ê²óž menu.edit.pccwrotate ¥Ý¡¼¥È¤ÎÈó»þ·×¼þ¤ê²óž #menu.edit.autobold ÂÀ»ú²½ menu.edit.resize ºÆ¥µ¥¤¥º²½ menu.tool.move °ÜÆ°¡¿Àܳ menu.tool.delg ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Îºï½ü menu.tool.cutw ¥ï¥¤¥ä¤ÎÀÚÃÇ menu.tool.inv ÈÝÄê menu.tool.bitw ¥Ó¥Ã¥ÈÉý menu.tool.debug ¥Ç¥Ð¥Ã¥° menu.tool.point ¥Ý¥¤¥ó¥È menu.tool.line ¥é¥¤¥ó menu.tool.rect ĹÊý·Á menu.tool.fillrect ¿§¤Å¤±Ä¹Êý·Á menu.tool.port ¥Ý¡¼¥È menu.tool.select ÌÈÀÕÁªÂò menu.tool.tclshell 0:Tcl Shell menu.tool.rep Ê£À½ menu.format.algnv ½Ä¤Î°ìÎó menu.format.algnh ²£¤Î¡¼Îó menu.format.rot ²óž menu.format.rot.0 ¥Ç¥Õ¥©¥ë¥È²óž¤ò0Å٤ˤ¹¤ë menu.format.rot.90 ¥Ç¥Õ¥©¥ë¥È²óž¤ò90Å٤ˤ¹¤ë menu.format.rot.180 ¥Ç¥Õ¥©¥ë¥È²óž¤ò180Å٤ˤ¹¤ë menu.format.rot.270 ¥Ç¥Õ¥©¥ë¥È²óž¤ò270Å٤ˤ¹¤ë menu.format.rot.rotate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î²óž menu.format.rot.brotate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎµÕ²óž menu.format.addport ¥Ý¡¼¥ÈÄɲà menu.format.ioset ¥¿¥¤¥×»ØÄê menu.format.anchor ÁªÂò¤ò°ÜÆ°ÉԲĤˤ¹¤ë menu.format.unanchor ÁªÂò¤ò°ÜÆ°²Ä¤Ë¤¹¤ë menu.format.prop ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê... menu.format.del ºï½ü menu.format.settech ¥Æ¥¯¥Î¥í¥¸¡¼¤ÎÀßÄê menu.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï menu.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» menu.simulate.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.simulate.run ¥é¥ó menu.simulate.pause °ì»þ¥¹¥È¥Ã¥× menu.simulate.step ¥¹¥Æ¥Ã¥×(¥¨¥Ý¥Ã¥¯) menu.simulate.cycle ¥¹¥Æ¥Ã¥×(¥µ¥¤¥¯¥ë) menu.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤ÎÀßÄê... menu.simulate.script ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô... menu.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.simulate.dump ¥á¥â¥ê¤Î½ñ¤­½Ð¤·... menu.simulate.view ¥á¥â¥ê¤Îɽ¼¨... menu.module.open ³«¤¯ menu.module.close ÊĤ¸¤ë menu.module.new ¿·µ¬ºîÀ®... menu.module.del ºï½ü... menu.module.copy ¥³¥Ô¡¼... menu.module.rename ̾Á°¤ÎÊÔ½¸... menu.module.claim ¼èÆÀ... menu.module.setroot ¥ë¡¼¥È¤Ë¤¹¤ë... menu.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÀßÄê... menu.module.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.module.interface.set ¥»¥Ã¥È menu.module.interface.edit ÊÔ½¸ menu.module.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.auto ¼«Æ°ºîÀ®... menu.help.about TkGate¤Ë¤Ä¤¤¤Æ... menu.help.license ¥é¥¤¥»¥ó¥¹... menu.help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... menu.help.tut ¥Á¥å¡¼¥È¥ê¥¢¥ë menu.help.home ¥Û¡¼¥à¡¦¥Ú¡¼¥¸ menu.help.example ²óÏ©¤ÎÎã ############################################################################# # Scope Menu # menu.scope_file ¥Õ¥¡¥¤¥ë menu.scope_sim ¥·¥ß¥å¥ì¡¼¥È menu.scope_trace ¥È¥ì¡¼¥¹ menu.scope_help ¥Ø¥ë¥× menu.scope_file.ptrace ¥È¥ì¡¼¥¹°õºþ... menu.scope_file.close ÊĤ¸¤ë menu.scope_trace.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.scope_trace.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.scope_sim.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.scope_sim.run »þ¸ú menu.scope_sim.pause °ì»þÄä»ß menu.scope_sim.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... menu.scope_sim.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... menu.scope_sim.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.scope_sim.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... menu.scope_help.about TkGate¤ËÉÕ¤¤¤Æ... menu.scope_help.license ¥é¥¤¥»¥ó¥¹... menu.scope_help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... mod.intf ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ port.parms ¥Ý¡¼¥È¤Î¥Ñ¥é¥á¥¿ port.in Æþ port.out ½Ð port.inout Æþ½Ð ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ¥²¡¼¥È gm.rgate ñ¹à½ÌÌ󥲡¼¥È gm.msi MSI gm.alu ALU gm.mem ¥á¥â¥ê¡¼ gm.mod ¥â¥¸¥å¡¼¥ë gm.comment ¥³¥á¥ó¥È gm.frame ¥Õ¥ì¡¼¥à gm.script Verilog¥¹¥¯¥ê¥×¥È gm.io.switch ¥¹¥¤¥Ã¥Á gm.io.dip DIP¥¹¥¤¥Ã¥Á gm.io.ground ¥¢¡¼¥¹ gm.io.vdd Vdd gm.io.merge ¥ï¥¤¥ä¤Î¥Þ¡¼¥¸ gm.io.clock ¥¯¥í¥Ã¥¯ gm.io.led LED¥Ó¥Ã¥È gm.io.ledbar LEDËÀ¥°¥é¥Õ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ¥Ð¥Ã¥Õ¥¡ gm.gate.inv ÈÝÄê¥Ð¥Ã¥Õ¥¡ gm.gate.tribuf ¥È¥é¥¤¡¦¥Ð¥Ã¥Õ¥¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and ñ¹à½ÌÌóAND gm.rgate.nand ñ¹à½ÌÌóNAND gm.rgate.or ñ¹à½ÌÌóOR gm.rgate.nor ñ¹à½ÌÌóNOR gm.rgate.xor ñ¹à½ÌÌóXOR gm.rgate.xnor ñ¹à½ÌÌóXNOR gm.alu.add ²Ã»»´ï gm.alu.mult ¾è»»´ï gm.alu.div ½ü»»´ï gm.alu.lshift º¸¥·¥Õ¥È gm.alu.rshift ±¦¥·¥Õ¥È gm.alu.arshift »»¿ôŪ±¦¥·¥Õ¥È gm.alu.roll ¥í¡¼¥ë gm.mem.reg ¥ì¥¸¥¹¥¿ gm.mem.ff ¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rff È¿¼Í¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rjkff È¿¼ÍJK¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.msi.21mux 2-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.41mux 4-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.81mux 8-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.12dec 1-2 ¥Ç¥³¡¼¥À gm.msi.14dec 1-4 ¥Ç¥³¡¼¥À gm.msi.18dec 1-8 ¥Ç¥³¡¼¥À gm.msi.12demux 1-2 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.14demux 1-4 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.18demux 1-8 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.mod.inst ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹ gm.mod.in ¥â¥¸¥å¡¼¥ë¤ÎÆþÎÏ gm.mod.out ¥â¥¸¥å¡¼¥ë¤Î½ÐÎÏ gm.mod.inout ¥â¥¸¥å¡¼¥ë¤ÎÆþ½ÐÎÏ tutorial.prev Á°¤Ø tutorial.next ¼¡¤Ø tutorial.chapter ¾Ï¤Î°ìÍ÷ɽ tutorial.reload ºÆÆɤ߹þ¤ß ############################################################################## # # Popup menus # pop.make ¥³¥ó¥Ý¡¼¥Í¥ó¥È pop.tool ¥Ä¡¼¥ë pop.edit.paste ¥Ú¡¼¥¹¥È pop.edit.cut ¥«¥Ã¥È pop.edit.copy ¥³¥Ô¡¼ pop.port.in Æþ pop.port.out ½Ð pop.port.inout Æþ½Ð pop.wire.addseg ¥ï¥¤¥ä¤ÎÄɲà pop.wire.prop ¥Í¥Ã¥È¤ÎÆÃħ... pop.wire.hidesize ¥Ó¥Ã¥ÈÉý¤ò±£¤¹ pop.wire.showsize ¥Ó¥Ã¥ÈÉý¤ò¼¨¤¹ pop.wire.hidelabel ¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.hidealllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.clearalllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò¥¯¥ê¥¢ pop.wire.showlabel ¥ì¡¼¥Ù¥ë¤ò¼¨¤¹ pop.gate.open ³«¤¯ pop.gate.close ÊĤ¸¤ë pop.gate.prop ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÆÃħ... pop.gate.addport ¥Ý¡¼¥È¤ÎÄɲà pop.gate.addin ÆþÎϤÎÄɲÃ... pop.gate.addout ½ÐÎϤÎÄɲÃ... pop.gate.addinout Æþ½ÐÎϤÎÄɲÃ... pop.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë pop.gate.settech ¥Æ¥¯¥Î¥í¥¸»ØÄê pop.gate.delete ºï½ü pop.gate.ioset ¥¿¥¤¥×¤Î»ØÄê pop.module.new ¿·µ¬... pop.module.del ºï½ü... pop.module.copy ¥³¥Ô¡¼... pop.module.rename ̾Á°¤ÎÊѹ¹... pop.module.claim ¥â¥¸¥å¡¼¥ë¤Î¼èÆÀ pop.module.setroot ¥ë¡¼¥È»ØÄê... pop.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÆÃħ... pop.module.int ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸... pop.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» pop.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï pop.simulate.addprobe ¥×¥í¡¼¥Ö¤òÄɲῺï½ü pop.simulate.run »þ¸ú pop.simulate.pause °ì»þÄä»ß pop.simulate.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× pop.simulate.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× pop.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... pop.simulate.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... pop.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... pop.simulate.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... pop.simulate.view ¥á¥â¥ê¤Îɽ¼¨... pop.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ pop.interface.set »ØÄê pop.interface.edit ÊÔ½¸... pop.interface.replace ¼è¤ê´¹¤¨ pop.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.auto ¼«Æ°ºîÀ®... pop.igen.type ¥¿¥¤¥× pop.igen.side ¥µ¥¤¥É pop.igen.size ¥µ¥¤¥º pop.igen.delete ºï½ü pop.igen.in Æþ pop.igen.out ½Ð pop.igen.inout Æþ½Ð pop.igen.left º¸ pop.igen.right ±¦ pop.igen.top ¾å pop.igen.bottom ²¼ pop.igen.other ¾ pop.library.mgr ¥é¥¤¥Ö¥é¥ê´ÉÍý... pop.library.close ¥é¥¤¥Ö¥é¥ê¤ò¥¢¥ó¥í¡¼¥É ############################################################################## # # Symbol editor strings # symed.cancel ¥­¥ã¥ó¥»¥ë symed.tab.normal È󥻥쥯¥È symed.tab.select ¥»¥ì¥¯¥È symed.link ¥»¥ì¥¯¥È¤ÈÈ󥻥쥯¥È¤òƱ»þ¤ËÊÔ½¸¤¹¤ë¡£ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## ## memory viewer # memview.title ¥á¥â¥ê¤ÎÆâÍÆ memview.exp -fillbegin- ¥á¥â¥ê¤ÎÆâÍƤòɽ¼¨¤·¤¢¤¿¤ê¡¢Êѹ¹¤·¤¿¤ê½ÐÍè¤ë¡£ ¥á¥â¥ê¤ÎÆâÍƤòÊѹ¹¤¹¤ë°Ù¡¢Ãͤ˥¯¥ê¥Ã¥¯¤·¤Æ¡¢ ¿·¤·¤¤Ãͤò¥­¡¼¥Ü¡¼¥É¤ÇÆþÎϤ·¤Æ¤¯¤À¤À¤¤¡£ -end- ############################################################################## scope.title TkGate: ¥¹¥³¡¼¥× scope.emptymsg ¥ï¥¤¥ä¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥×¥í¡¼¥Ö¤ËÉÕ¤±¤Ã¤Æ¤¯¤À¤µ¤¤¡£ comment.empty [¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Æ¥­¥¹¥È¤òÊÔ½¸¤·¤Æ¤¯¤À¤µ¤¤¡£] ############################################################################## # Interface strings # ifile ¥Õ¥¡¥¤¥ë imodule ¥â¥¸¥å¡¼¥ë iblmodule ¥â¥¸¥å¡¼¥ë: iports ¥Ý¡¼¥È: ibits ¥Ó¥Ã¥ÈÉý: itype ¥¿¥¤¥×: ############################################################################# # Module Dialog Box # db.mod.name ¥â¥¸¥å¡¼¥ë̾ db.mod.file ¥Õ¥¡¥¤¥ë̾ db.mod.type ¥¿¥¤¥× db.mod.flags ¥Õ¥é¥° db.mod.dataprot ¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.intfprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.edprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÀìÍÑ¥¨¥Ç¥£¥¿¤Ë¸Â¤ë¡£ db.mod.props ÆÃħ db.mod.netlist ¥Í¥Ã¥È¥ê¥¹¥È db.mod.hdl HDL # # These are probably not used anymore. Lets leave them as is. # db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netexpl -begin- ¥°¥é¥Õ¥£¥«¥ë¤Î¥¨¥Ç¥£¥¿¤ò ÍøÍѤ·¤Æ¡¢¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤ò ÄêµÁ¤¹¤ë¡£ -end- db.mod.hdlexpl -begin- Verilog¤Î¥Æ¥­¥¹¥È¤òÍøÍѤ·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤òÄêµÁ¤¹¤ë¡£ -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.caption ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.explain.warn -fillbegin- ²óÏ©Ãæ¤Ë¥ï¡¼¥Ë¥ó¥°¤¬¤¢¤ê¤Þ¤¹¤¬¡¢¤½¤ì¤Ë¤«¤«¤é¤ï¤º¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤¬µ¯Æ°¤·¤Þ¤¹¡£¥ï¡¼¥Ë¥ó¥°¤Î²Õ½ê¤ò°ÜÆ°¤¹¤ë¤¿¤á¡¢ÊÔ½¸¥â¡¼¥É¤ËÀÚÂؤ¨¤Ê¤¯¤Æ¤Ï¤Ê¤ê¤Þ¤»¤ó¡£ -end- db.err.explain.err -fillbegin- ²óÏ©Ãæ¤Ë¥¨¥é¡¼¤¬Â¸ºß¤·¤Þ¤¹¡£¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°½ÐÍè¤Þ¤»¤ó¡£ -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: ¥Í¥Ã¥È¤ÎÈùºÙ db.net.name ¥Í¥Ã¥È̾ db.net.hide ¥Í¥Ã¥È̾¤ò±£¤¹ db.net.bits ¥Ó¥Ã¥ÈÉý db.net.type ¥Í¥Ã¥È¡¦¥¿¥¤¥× db.net.port ¥Ý¡¼¥È¡¦¥¿¥¤¥× db.net.in Æþ db.net.out ½Ð db.net.inout Æþ½Ð db.net.inets ¥Í¥Ã¥È ############################################################################## # # New circuit dialog box # db.newcirc.directory ¥Ç¥£¥ì¥¯¥È¥ê db.newcirc.cap ¿·µ¬²óÏ© db.newcirc.exp -begin- ¸½ºß¤Î²óÏ©¤ÎÊÔ½¸¤ò ¼­¤á¤Æ¡¢¿·¤·¤¤²óÏ©¤ò ÊÔ½¸¤·»Ï¤á¤ë¡£ -end- db.newcirc.file ¥Õ¥¡¥¤¥ë̾ db.newcirc.topname ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë̾ ############################################################################## # Gate dialog box # db.gate.title ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê db.gate.signam ¥Í¥Ã¥È̾ db.gate.portnam ¥Ý¡¼¥È̾ db.gate.iotype ¥¿¥¤¥× db.gate.bitw ¥Ó¥Ã¥ÈÉý db.gate.cyclew ¥µ¥¤¥¯¥ëÉý db.gate.phase ¥Õ¥§¡¼¥º db.gate.duty ¥Ç¥å¡¼¥Æ¥£¡¼ db.gate.port ¥Ý¡¼¥È db.gate.bitws ¥Ó¥Ã¥È db.gate.side ¥µ¥¤¥É db.gate.gtype ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¦¥¿¥¤¥× db.gate.gname ¥³¥ó¥Ý¡¼¥Í¥ó¥È̾ db.gate.hidenam ̾Á°¤ò±£¤¹ db.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë db.gate.cpbreak ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹Ê¬³äÅÀ db.gate.butstate ¥¹¥¤¥Ã¥Á¾õÂÖ db.gate.dipval DIP¾õÂÖ db.gate.range ¥Ó¥Ã¥ÈÈÏ°Ï db.gate.memfilenam ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë̾ db.gate.modname µ¡Ç½Ì¾ db.gate.general °ìÈÌ db.gate.details ¾ÜºÙ db.gate.text ¥Æ¥­¥¹¥È db.gate.ports ¥Ý¡¼¥È db.gate.delay ÃÙ±ä db.gate.parameters ¥Ñ¥é¥á¥¿ db.gate.stddelay ɸ½à¤ÎÃÙ±ä db.gate.custdelay ¥«¥¹¥¿¥à¤ÎÃÙ±ä db.gate.catdiruse ¥Ý¡¼¥È¤Î°ÌÃÖÉÕ¤± db.gate.edit ÊÔ½¸ db.gate.delete ºï½ü db.gate.add Äɲà db.gate.ff.type ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.ff.normal.hdr ÉáÄÌ db.gate.ff.normal.exp -begin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.ff.reverse.hdr È¿¼Í db.gate.ff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.jkff.type JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.jkff.normal.hdr ÉáÄÌ db.gate.jkff.normal.exp -fillbegin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø¿Ê¤à JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤Ç¤¹¡£ -end- db.gate.jkff.reverse.hdr È¿¼Í db.gate.jkff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø¿Ê¤à JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤Ç¤¹¡£ -end- db.gate.cat.asc.hdr ¾º½ç db.gate.cat.dec.hdr ¹ß½ç db.gate.cat.asc.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¾º½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.dec.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¹ß½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.sigdir ¿®¹æÊý¸þ db.gate.cat.auto.hdr ¼«Æ° db.gate.cat.multin.hdr ¿ÆþÎÏ db.gate.cat.singin.hdr ¿½ÐÎÏ db.gate.cat.tran.hdr Æþ½Ð db.gate.cat.auto.exp -fillbegin- ¿®¹æ¤ÎÊý¸þ¤ò¼«Æ°Åª ¤ËȽÃǤ¹¤ë¡£ -end- db.gate.cat.multin.exp -fillbegin- ¤¤¤Ä¤â¿¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.singin.exp -fillbegin- ¤¤¤Ä¤âñ°Ì¤Î¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.tran.exp -fillbegin- ÁÐÊý¸þ¤Î¿®¹æ¤ÎÅÁÇÅ(tran)¤òµö¤¹¡£¥¹¥¤¥Ã¥Á¤ä¥ì¥¸¥¹¥¿¤Ë¤ÎÀܳ¤ÏÉԲĤǤ¹¡£ -end- db.gate.tab.General.cap °ìÈÌÆÃħ db.gate.tab.Ports.cap ¥Ý¡¼¥ÈÆÃħ db.gate.tab.Delay.cap ÃÙ±äÆÃħ db.gate.tab.Parameters.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.CLOCK.cap ¥¯¥í¥Ã¥¯ÆÃħ db.gate.tab.SWITCH.cap ¥¹¥¤¥Ã¥ÁÆÃħ db.gate.tab.DIP.cap DIPÆÃħ db.gate.tab.TAP.cap TranÆÃħ db.gate.tab.RAM.cap RAMÆÃħ db.gate.tab.ROM.cap ROMÆÃħ db.gate.tab.MODULE.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.FRAME.cap ¥Õ¥ì¡¼¥àÆÃħ db.gate.tab.LED.cap LEDÆÃħ db.gate.tab.AND.cap ANDÆÃħ db.gate.tab.OR.cap ORÆÃħ db.gate.tab.XOR.cap XORÆÃħ db.gate.tab.MUX.cap MuxÆÃħ db.gate.tab.DEMUX.cap DemuxÆÃħ db.gate.tab.DECODER.cap DecoderÆÃħ db.gate.tab.CONCAT.cap ConcatÆÃħ db.gate.tab.COMMENT.cap ¥Æ¥­¥¹¥ÈÆÃħ db.gate.tab.FF.cap ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ db.gate.tab.JKFF.cap JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ db.gate.tab.SCRIPT.cap Verilog¥¹¥¯¥ê¥×¥È db.gate.tab.General.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î´ðËÜÆÃħ¤òɽ¼¨¡¢Ëô¤ÏÊÔ½¸¤¹¤ë¡£ -end- db.gate.tab.Ports.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î¥Ý¡¼¥È¤òÄɲá¢ÊÔ½¸¡¢Ëô¤Ïºï½ü¤¹¤ë¡£ -end- db.gate.tab.Delay.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÃÙ±ä¤Ï¥Æ¥¯¥Î¥í¥¸¤Ç¤â¡¢¸Ä¡¹¤Ç¤âÀßÄê²Äǽ¤Ç¤¢¤ë¡£ -end- db.gate.tab.Parameters.exp -fillbegin- ¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤¬ÄêµÁ¤·¤Æ¤¤¤ë¾ì¹ç¡¢¤³¤³¤Ç¤½¤ÎÃͤòÀßÄê½ÐÍè¤ë¡£¥â ¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤ÏÃÙ±äÃÍ¡¢¥³¥ó¥¹¥¿¥ó¥È¤Ê¤É¤ËÍøÍѤµ¤ì¤Æ¤¤¤ë¡£ -end- db.gate.tab.details.exp -fillbegin- ¥³¥ó¥Ý¡¼¥Í¥ó¥È¼¡Âè¤ÎÀßÄê¤ò¹Ô¤¦¡£ -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.JKFF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤òÆþÎϤ¹¤ë¡£¤¢¤ëÄøÅÙ¤Îhtml¤ä¥Ï¥¤¥Ñ¡¼¥ê¥ó¥¯¤Ê¤É¤âÍøÍѽÐÍè¤ë¡£ -end- db.gate.tab.SCRIPT.exp -fillbegin- ¤³¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ËÆþÎϤ¹¤ëVerilog¤Î¥³¡¼¥É¤Ï ¥â¥¸¥å¡¼¥ë¤Î°ìÉô¤Ë¤Ê¤ê¤Þ¤¹¡£ -end- db.gate.mparm.parameter ¥Ñ¥é¥á¥¿ db.gate.mparm.value ÃÍ db.gate.mparm.exampleA -begin- ¤³¤Î¥â¥¸¥å¡¼¥ë¤Ï¥Ñ¥é¥á¥¿¤òÍøÍѤ·¤Æ¤¤¤Ê¤¤¡£ ¥Ñ¥é¥á¥¿¤ÏVerilog¥Æ¥­¥¹¥È¤Î¥â¥¸¥å¡¼¥ë¤Ë ÍøÍѽÐÍè¤ë¡£¤³¤Î¥À¥¤¥¢¥í¥°¤Ç¡¢¤½¤ì¤¾¤ì¤Î ¥Ñ¥é¥á¥¿¤ÎÃͤ¬ÀßÄê½ÐÍè¤ë¡£¥â¥¸¥å¡¼¥ë¤Î ¥Ñ¥é¥á¥¿¤òÍøÍѤ¹¤ë¤¿¤á¡¢¥Æ¥­¥¹¥È¤ÎÄêµÁ¤Ë ¡Ö#¡×¤«¤é»Ï¤Þ¤ë¥Ñ¥é¥á¥¿¤Î¥ê¥¹¥È¤ò½ñ¤¤¤Æ ¤¯¤À¤µ¤¤¡£°Ê²¼¤ÎÎãÂê¤Ç¡¢¥Ç¥Õ¥©¥ë¥È¤ÎÃͤ¬ ¡Ö1'b1¡×¤Î¡Öbase_value¡×¤È¤¤¤¦¥Ñ¥é¥á¥¿¤ò »ý¤Ä¥â¥¸¥å¡¼¥ë¤¬¼¨¤·¤Æ¤¢¤ë¡£ -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder ÆþÎϤνç½ø db.gate.mux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.mux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.mux.ord1.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.ord2.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.select ¥»¥ì¥¯¥¿¤Î²Õ½ê db.gate.mux.sel1.hdr º¸Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel2.hdr ±¦Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel1.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤòº¸Â¦¤Ë¤ª¤¯¡£ -end- db.gate.mux.sel2.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤò±¦Â¦¤Ë¤ª¤¯¡£ -end- db.gate.decoder.dataorder ÆþÎϤνç½ø db.gate.decoder.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.decoder.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.decoder.ord1.exp -fillbegin- DECODER¤ÎÆþÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.decoder.ord2.exp -fillbegin- DECODER¤ÎÆþÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.decoder.select ¥»¥ì¥¯¥¿¤Î²Õ½ê db.gate.decoder.sel1.hdr º¸Â¦¤Î¥»¥ì¥¯¥¿ db.gate.decoder.sel2.hdr ±¦Â¦¤Î¥»¥ì¥¯¥¿ db.gate.decoder.sel1.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤòº¸Â¦¤Ë¤ª¤¯¡£ -end- db.gate.decoder.sel2.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤò±¦Â¦¤Ë¤ª¤¯¡£ -end- db.gate.demux.dataorder ½ÐÎϤνç½ø db.gate.demux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.demux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.demux.ord1.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.ord2.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse ³ÈÄ¥¥Ð¡¼¤òÍøÍÑ db.gate.aox.use.hdr ³ÈÄ¥¥Ð¡¼ db.gate.aox.nouse.hdr ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ·¤Ê¤¤ db.gate.aox.use.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.aox.nouse.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤµ¤ì¤Ê¤¤¡£ -end- db.gate.led.type LED¤Î¥¿¥¤¥× db.gate.led.bit.hdr ¥Ó¥Ã¥È db.gate.led.bar.hdr ¥Ð¡¼¡¦¥°¥é¥Õ db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- °ì¥Ó¥Ã¥È¤Î¿®¹æ¤Î°Ù¤Îñ°Ì¤ÎLED -end- db.gate.led.bar.exp -fillbegin- LED¤Î¥Ð¡¼¡¦¥°¥é¥Õ¡£°ì¥Ó¥Ã¥È¤Ë¤Ä¤­¡¢°ì¤Ä¤Î¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.led.hex.exp -fillbegin- ¿®¹æ¤ò16¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.dec.exp -fillbegin- ¿®¹æ¤ò10¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.seg.exp -fillbegin- ³Æ¥»¥°¥á¥ó¥È¤òÊÌ¡¹¤ËÀ©¸æ¤¹¤ë¡£ -end- db.gate.tap.lbl.bus LSB: db.gate.tap.exp.bus Æɤ߹þ¤à¥Ó¥Ã¥È¡¦¥ì¡¼¥ó¥¸¤ÎºÇ¤â²¼¤Î¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.gate.tap.exp.bit Æɤ߹þ¤à¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.gate.dip.value.hex 16¿Ê¿ô¤ÎÃÍ: db.gate.dip.value ½é´ü¤ÎDIP¤ÎÃÍ db.seq.back <Á°¤Ø db.seq.next ¼¡¤Ø> db.hdl.savecap Ê£¿ô¤Î¥â¥¸¥å¡¼¥ë db.hdl.saveexp -fillbegin- ¥Æ¥­¥¹¥È¤Î¥Ð¥Ã¥Õ¥¡¤ËÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬¤¢¤ë¡£±¦Â¦¤Î¥¢¥¯¥·¥ç¥ó¤Î¤¤¤º¤ì¤«¤òÁªÂò¤¹¤Æ¤¯¤À¤µ¤¤¡£ -end- db.hdl.autoedit ¼«Æ°ÊÑ¿ô db.hdl.split ʬΥ db.hdl.comment ¥³¥á¥ó¥È db.hdl.cancel ¥­¥ã¥ó¥»¥ë db.hdl.ignore ̵»ë¤¹¤ë db.hdl.autoeditcap ̾Á°¤¬°ìÅù¤·¤Ê¤¤ db.hdl.autoeditexp -fillbegin- ¥Æ¥­¥¹¥È¤Ç¤Î¥â¥¸¥å¡¼¥ë̾¤È´üÂÔ¤·¤¿Ì¾Á°¤¬°ìÅù¤·¤Ê¤¤¡£±¦Â¦¤Î¥¢¥¯¥·¥ç¥ó¤Î¤¤¤º¤ì¤«¤òÁªÂò¤¹¤Æ¤¯¤À¤µ¤¤¡£ -end- cpath.cloops -fillbegin- ²óÏ©¤ËÁȹ礻¤Î¥ë¡¼¥×¤¬È¯¸«¤µ¤ì¤¿¡£¥¯¥ê¥Æ¥£¥«¥ë ¡¦¥Ñ¥¹¤Î²òÀϤò¹Ô¤Ê¤¤¤¿¤±¤ì¤Ð¡¢¥ë¡¼¥×¾å¤Î¥Í¥Ã¥È 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ÁªÂòÈϰϤò¥¹¥±¡¼¥ë¤¹¤ë print.fulltr Á´Éô print.parttr Éôʬ print.start ¥¹¥¿¡¼¥È print.end ¥¹¥È¥Ã¥× print.filesel ¥Õ¥¡¥¤¥ë¤Ë°õºþ print.printersel ¥×¥ê¥ó¥¿¤Ë°õºþ print.defaultprinter ¥Ç¥Õ¥©¥ë¥È¤Î¥×¥ê¥ó¥¿ print.pageset ¥Ú¡¼¥¸¡¦¥»¥Ã¥È¥¢¥Ã¥× print.modulesel ¥â¥¸¥å¡¼¥ë¤ÎÁªÂò ############################################################################## # # TkGate 2.0 print dialog strings # print.ok °õºþ print.printtrace.cap ¥È¥ì¡¼¥¹¤Î°õºþ print.printcirc.cap ²óÏ©¿Þ¤Î°õºþ print.printcirc.out.exp -begin- ²óÏ©¿Þ¤Î°õºþÀ褬 ¥×¥ê¥ó¥¿¤«¥Õ¥¡¥¤¥ë ¤«ÁªÂò¤¹¤ë¡£ -end- #probably not used print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë ¤ä°õºþ¤ÎÍͻҤòÁªÂò ¤ë¡£ -end- print.printtrace.trace.exp -fillbegin- »þ´Ö¤ÎÈϰϤòÁªÂò¤¹¤ë¡£ Ëô¡¢¥¹¥±¡¼¥ë¤Ë¤è¤Ã¤Æ¡¢ ɬÍפΥڡ¼¥¸¿ô¤òɽ¤« ɾ²Á¤¹¤ë¡£ -end- print.tab.output °õºþÀè print.tab.page °õºþ print.tab.content ÆâÍÆ ############################################################################## # # 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¥»¡¼¥Ö¤Ç°ÛÊѤ¬µ¯¤³¤Ã¤Æ¤·¤Þ¤¿¡£²óÏ©¥Ç¡¼¥¿¤ËÌ·½â¤¬¤¢¤ë²ÄǽÀ­¤¬¤¢¤ë¡£ err.yy.pinformat ¡Ö%s¡×¤Ç¥Ô¥ó̾¤Î·Á¼°¤¬Ç§ÄêÉԲĤǤ¹¡£ err.yy.pinname ¥Ô¥ó̾¡Ö%s¡×¤Ï¡Ö%s¡×¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Ç̤ÄêµÁ¤Ç¤¹¡£ err.yy.nonetpos ¥Í¥Ã¥È²Õ½ê¡Ö%d¡×¤Ï¥³¥ó¥Ý¡¼¥Í¥ó¥È¡Ö%s¡×¤Ë¸«ÉÕ¤«¤é¤Ê¤¤¤Ç¤¹¡£ err.yy.baddirective ¥Ç¥£¥ì¥¯¥Æ¥£¥Ö¡Ö%s¡×¤Î·Á¼°¤¬Ç§ÄêÉԲĤǤ¹¡£ err.corruptnewsave -fillbegin- TkGate¤Ï'%s'¤Ë¥»¡¼¥Ö½ÐÍ褿¤¬¡¢¥Õ¥¡¥¤¥ë¤¬º®Í𤵤ì¤Æ¤¤¤ë¤ß¤¿¤¤¡£¤â¤·¥Á¥§¥Ã ¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯ ¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.corruptsave -fillbegin- '%s'¤ò¥»¡¼¥Ö¤·¤è¤¦¤È¤·¤Æ¤¤¤ë»þ¡¢TkGate¤ËÆâÉôÌäÂ꤬ȯ¸«¤·¤¿¡£¸µ¡¹¤Î¥Õ¥¡¥¤ ¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä¤·¤Æ¤¢¤ë¡£º®Í𤵤ì¤Æ¤¤¤ë²ÄǽÀ­¤Î¤¢¤ë¥Õ¥¡¥¤¥ë¤Ï'%s'¤Ë¥»¡¼¥Ö ¤·¤¿¡£¤â¤·¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤ ¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.badsave -fillbegin- '%s'¤ò¥»¡¼¥Ö½ÐÍè¤Ê¤«¤Ã¤¿¡£¥Õ¥¡¥¤¥ë¤Î¥×¥í¥Æ¥¯¥·¥ç¥ó¤ä¶õ¤­¥Ç¥£¥¹¥¯Î̤ò³Îǧ ¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- err.nosafesave -fillbegin- '%s'¤Î°ÂÁ´¥»¡¼¥Ö¤ò¹Ô¤¦¤¿¤á¤Î°ì»þ¤Î¥Õ¥¡¥¤¥ë¤¬ºîÀ®½ÐÍè¤Ê¤«¤Ã¤¿¤«¤é¡¢Ä¾ÀÜ¥»¡¼ ¥Ö¤·¤Ê¤¯¤Æ¤Ï¤Ê¤é¤Ê¤¤¡£¡ÖNO¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¸µ¡¹¤Î¥Õ¥¡¥¤¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä ¤¹¡£¡ÖYES¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¥»¡¼¥Ö¤¹¤ë¤¬¡¢¥»¡¼¥ÖÅÓÃæ¤ËÌäÂ꤬µ¯¤³¤Ã¤¿¤é¡¢ ²óÏ©¥Ç¡¼¥¿¤¬Ç˲õ¤µ¤ì¤ë²ÄǽÀ­¤¬¤¢¤ë¡£Ä¾ÀÜ¥»¡¼¥Ö¤·¤Æ¤ß¤Þ¤·¤ç¤¦¤«¡£ -end- err.noback -fillbegin- TkGate¥Ð¡¼¥¸¥ç¥ó%s¤Çºî¤é¤ì¤¿¥Õ¥¡¥¤¥ë¤Ç¤¢¤ë¡£Êݸ¤¹¤ë¤È¡¢ TkGate¤Î¸Å¤¤¥Ð¡¼¥¸¥ç¥ó¤ËÆɤ߹þ¤á¤Ê¤¤¤³¤È¤¬¤¢¤ë¡Ê¸½ºß¤Î ¥Ð¡¼¥¸¥ç¥ó¤Ï%s¤Ç¤¢¤ë¡Ë¡£ -end- err.viewfile ¥Õ¥¡¥¤¥ë¡Ö%s¡×¤¬³«¤±¤Þ¤»¤ó¡£ err.noinvgate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¦¥¿¥¤¥×¤ËÈÝÄê¥Ð¥Ö¥ë¤¬ÉÕ¤±¤Ê¤¤¡£ ############################################################################## # # Internal error messages (indicating a problem with TkGate) # err.internal.nomod ÆâÉô¥¨¥é¡¼¡§¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬¸«ÉÕ¤«¤ê¤Þ¤»¤ó¡£ ############################################################################## # Informational messages # msg.selwire ¥ï¥¤¥ä¡Ö%s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£ msg.selgate %2$s¤È¤¤¤¦%1$s¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.selblock %2$s¤È¤¤¤¦%1$s¥â¥¸¥å¡¼¥ë¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.iselwire ¥Ö¥í¥Ã¥¯¡Ö%2$s¡×¤Ë¥Ý¡¼¥È¡Ö%1$s¡×¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.iselgate ¡Ö%2$s¡×¤È¤¤¤¦¡Ö%1$s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£(¤¨¤Ã¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ò½Ð¤¹¤Î¤ÏÉÔ²Äǽ¤Î¤Ï¤º¤Ç¤¹¤¬¡£) msg.iselblock ¥â¥¸¥å¡¼¥ë¡¦¥¤¥ó¥¿¥Õ¥§¡¼¥¹¡Ö%s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£ msg.modoverwt ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬´û¤ËÄêµÁ¤µ¤ì¤Æ¤¤¤ë¡£ÄêµÁ¤·¤Ê¤ª¤·¤Þ¤¹¤«? msg.foundgate %s¤È¤¤¤¦¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.foundwire %s¤È¤¤¤¦¥ï¥¤¥ä¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.searchagn õº÷¥¹¥È¥ê¥ó¥°¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤«¤Ã¤¿¡£¤â¤¦°ìÅÙ¡Öõº÷¡×¤ò²¡¤¹¤È¡¢Ãµº÷¤·¤Ê¤ª¤¹¡£ msg.sim.chgtoroot ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¤Ï¡¢¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤¬¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤Î¥È¥Ã¥×¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ msg.sim.nogatemod ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¡¢¶ñÂÎŪ¤Ê¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤¬É¬ÍפǤ¢¤ë¡£ msg.setinterface ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ò¥»¥Ã¥È¤·¤¿¡£ msg.needsel ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤òÁª¤ó¤Ç¤¯¤À¤µ¤¤¡£ msg.wroteckpt ¡Ö%s¡×¤Ë¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥È¤ò½ñ¤­¹þ¤ó¤À... msg.save ¡Ö%s¡×¤ËÊݸ¤·¤¿¡£ msg.reallynew ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢¿·¤·¤¤²óÏ©¤ò³«¤­¤Þ¤¹¤«? msg.reallyquit ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢½ªÎ»¤·¤Þ¤¹¤«? msg.notlib ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ï¥é¥¤¥Ö¥é¥ê¡¦¥â¥¸¥å¡¼¥ë¤Ç¤Ï¤Ê¤¤¡£ ############################################################################## # Miles messages (Activated when Miles Bader uses TkGate) # miles.msg1 ¤½¤Î°ÌÃ֤˥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÃÖ¤¯¤Î¤Ï¡¢¤ªÁ°¤ß¤¿¤¤¤ÊÂçÇϼ¯¤·¤«¤¤¤Ê¤¤¤è¡£ miles.msg2 Çϼ¯¡ª miles.msg3 ¶ò¤«¤â¤Î¡ª miles.msg4 ¥Þ¥¤¥ë¥¹¡¢¤½¤Î°ÌÃ֤˥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÃÖ¤¯¤Î¤Ï¡¢Çϼ¯¤À¤è¡£ miles.msg5 Çϼ¯¤Ê¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°ÌÃÖÉÕ¤±¤ò¤ä¤á¤Æ¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg6 ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¤½¤Î°ÌÃ֤ˤª¤¤¤¿¤Î¤Ï¡¢¤ªÁ°¤Î¶ò¤«¤µ¤Î¾ÚÌÀ¤À¤è¡£ miles.msg7 ¤³¤Î¥í¥¯¤Ç¤Ê¤·²óÏ©¤ÎÀ߷פòÄü¤á¤è¡¢¥Þ¥¤¥¹¥ë¡£ miles.msg8a ³¤±¤Æ¤â¡¢ÌµÂ̤À¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg8b ¤ªÁ°¤¬²óÏ©¤òÀß·×½ÐÍè¤Ê¤¤¤È¤¤¤¦¤Î¤Ï¡¢Ã¯¤Ç¤âʬ¤«¤ë¤è¡£ ############################################################################# # # Error messages generated by verga # verga.err.OK ¿´ÇÛ¤·¤Ê¤¤¤Ç¡¢¾Ð¤Ã¤Æ¤¯¤À¤µ¤¤¡£ verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.RAMDCHG ½ñ¤­¹þ¤ß¿®¹æ¤¬Í­¸ú¤Ç¤¢¤ë»þ¡¢¥Ç¡¼¥¿ÆþÎϤÎÊѹ¹¤¬µ¯¤³¤ê¤Þ¤·¤¿¡£ verga.err.RAMACHG ½ñ¤­¹þ¤ß¿®¹æ¤¬Í­¸ú¤Ç¤¢¤ë»þ¡¢¥¢¥É¥ì¥¹ÆþÎϤÎÊѹ¹¤¬µ¯¤³¤ê¤Þ¤·¤¿¡£ verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.NONSTATCTL TODO: Event control @(*) applied to non-statment. verga.err.BADVALUE TODO: Bad numeric value '%s'. verga.err.BADPORTTYPE TODO: Invalid type declaration used on port '%s' verga.err.PATHDCOND TODO: DelaMust set through both # expression and specify block. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. verga.err.NONEXPCTL TODO: Event control @(*) applied to non-expression. verga.err.MODREDEF ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬ºÆÄêµÁ¤µ¤ì¤Þ¤·¤¿¡£ ############################################################################## # Balloon Help # ho.net.in °ì¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out °ì¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout °ì¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.in2 ¿¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out2 ¿¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout2 ¿¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.wire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.wire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.hwire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.hwire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.reg °ì¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.net.reg2 ¿¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.opt.tool.file ²óÏ©¥Õ¥¡¥¤¥ë¤Î¥»¡¼¥Ö¡¢¥í¡¼¥É¤Ê¤É ho.opt.tool.edit ¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¡¢Ãµº÷¤Ê¤É ho.opt.tool.gateopt ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎŸ³«¤ÈÀ°Îó ho.opt.tool.gateprop ´ðËܤΥ³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÊÔ½¸ ho.opt.tool.undo ¥¢¥ó¥É¥¥¤È¥ê¥É¥¥ ho.opt.tool.zoom ¥º¡¼¥à¡¦¥¤¥ó¤È¥º¡¼¥à¡¦¥¢¥¦¥È ho.opt.tool.mode ÊÔ½¸¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.module ¥â¥¸¥å¡¼¥ëÄêµÁ¤Î¿·µ¬ºîÀ®¡¢ºï½ü¡¢ºÆ̾Á°ÉÕ¤±¤Ê¤É ho.opt.tool.tech ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¥Æ¥¯¥Î¥í¥¸¤ÎÁªÂò ho.opt.tool.simctl ¥·¥ß¥å¥ì¡¼¥¿¤Îµ¯Æ°¡¢½ªÎ»¡¢°ì»þÄä»ß¤Ê¤É ho.opt.tool.simaux ÉÕ°¤Î¥·¥ß¥å¥ì¡¼¥¿¤Î¥³¥Þ¥ó¥É(¥á¥â¥ê¤ÎÆɤ߹þ¤ß¡¢½ñ¤­¹þ¤ß¤Ê¤É) ho.opt.tool.symmode ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.symedit ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¤Ê¤É ho.opt.tool.symport ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ý¡¼¥È¤Î²óž ho.opt.tool.symshift ¥Ó¥Ã¥È¡¦¥Þ¥Ã¥×¤ò¾å²¼º¸±¦¤Î¥·¥Õ¥È ho.opt.tool.symopr ÉÕ°¤Î¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥³¥Þ¥ó¥É ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ¸½ºß¤Î²óÏ©¤ò¾Ã¤·¤Æ¡¢¿·¤·¤¤ ²óÏ©¤òºîÀ®¤¹¤ë¡£ -end- ho.open ²óÏ©¥Õ¥¡¥¤¥ë¤ò³«¤­¤Þ¤¹¡£ ho.save ²óÏ©¥Õ¥¡¥¤¥ë¤òÊݸ¤·¤Þ¤¹¡£ ho.saveas ²óÏ©¥Õ¥¡¥¤¥ë¤ò»ØÄê¤Î¥Õ¥¡¥¤¥ë¤ËÊݸ¤·¤Þ¤¹¡£ ho.print ²óÏ©¥Õ¥¡¥¤¥ë¤ò°õºþ¤¹¤ë ho.library ¥é¥¤¥Ö¥é¥ê¡¦¥Þ¥Í¥¸¥ã¡¼¤ò³«¤­¤Þ¤¹¡£ ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- °ÜÆ°¡¿Àܳ - ¤³¤Î¥Ä¡¼¥ë¤Ç°Ê²¼¤Îµ¡Ç½¤ò¹Ô¤¤¤Þ¤¹¡£ ¿·¤·¤¤¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°ÌÃÖ¤òÀßÄꤹ¤ë¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤òÀܳ¤¹¤ë¡£ ¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤Ç°Ê²¼¤Îµ¡Ç½¤¬»È¤¨¤ë¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥ï¥¤¥ä¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥Ý¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤Î°À­¤òÊÔ½¸¤¹¤ë -end- ho.delgat -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òºï½ü¤¹¤ë -end- ho.cutw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤òÀÚÃǤ¹¤ë -end- ho.inv -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÆþ½ÐÎÏ¤Ë ÈÝÄê¤òÉÕ¤±¤¿¤ê¡¢¾Ã¤·¤¿¤ê¤¹¤ë¡£ -end- ho.bitw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤Î¥Ó¥Ã¥ÈÉý¤ò Êѹ¹¤¹¤ë¡£¥Ó¥Ã¥ÈÉý¤ò±¦²¼¤ÎÆþÎÏ ¥Ü¥Ã¥¯¥¹¤ËÆþÎϤ·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open ÁªÂò¤µ¤ì¤¿¥â¥¸¥å¡¼¥ë¤ò³«¤¯ ho.mod.close ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤òÊĤ¸¤ë ho.mod.new ¥â¥¸¥å¡¼¥ë¤Î¿·µ¬ºîÀ® ho.mod.del ¥â¥¸¥å¡¼¥ë¤Îºï½ü ho.mod.copy ¥â¥¸¥å¡¼¥ë¤ò¥³¥Ô¡¼¤·¤Þ¤¹¡£ ho.mod.rename ¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ ho.mod.claim -begin- ¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë¤ò¥æ¡¼¥¶¤Î¥â¥¸¥å¡¼¥ë¤ËÊѹ¹¤·¤Þ¤¹¡£ -end- ho.mod.setroot -begin- »ØÄê¤Î¥â¥¸¥å¡¼¥ë¤ò¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Ë¤·¤Þ¤¹¡£ -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo ºÇ¶á¹Ô¤Ã¤¿ÊѲ½¤ò¸µÄ̤ê¤Ë¤¹¤ë¡£ ho.redo ¥¢¥ó¥Ç¥©¤·¤¿ÊѲ½¤ò¤ä¤êľ¤¹¡£ ho.tab.edit -begin- ²óÏ©¥Ç¡¼¥¿¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.interface -begin- ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.simulate -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òµ¯Æ°¤·¡¢¥¹¥³¡¼¥×¤Î¥¦¥£¥ó¥É¤ò ³«¤­¡¢¤½¤·¤Æ½é´ü²½¥¹¥¯¥ê¥×¥È¤¬Â¸ºß¤¹¤ë¾ì¹ç¡¢ ¤½¤Î¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.tab.cpath -begin- ²óÏ©¤Î¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹¤òõº÷¤¹¤ë¡£ -end- ho.log -begin- TODO: Log of TkGate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÆ°¤«¤¹¡£Áȹ礻²óÏ©¤Î¾ì¹ç¡¢ ¿®¹æ¤¬ÊѤï¤é¤Ê¤¯¤Ê¤ë»þ¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö ¤¬°ì»þÄä»ß¤¹¤ë¡£ -end- ho.simpause -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î°ì»þÄä»ß -end- ho.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¨¥Ý¥Ã¥¯¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simclock -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë ¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simstop -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÄä»ß¤·¤Æ¡¢ ÊÔ½¸¥â¡¼¥É¤ËÌá¤ë¡£ -end- ho.simbreak -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È ¤òÊÔ½¸¤¹¤ë¡£ -end- ho.simexec -begin- ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤òÆɤ߹þ¤à -end- ho.simdump -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤Ë½ñ¤­½Ð¤¹ -end- ho.simview -begin- ¥á¥â¥ê(RAM¤äROM)¤ÎÆâÍƤòɽ¼¨¤·¤¿¤¤¤ê¡¢ Êѹ¹¤·¤¿¤¤¤ê¤·¤Þ¤¹¡£ -end- ho.f.modlist -begin- Æɤ߹þ¤ó¤Ç¤¢¤ë¥â¥¸¥å¡¼¥ë¤Î°ìÍ÷ɽ¡£ ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Î̾Á°¤Ë¡Ö+¡×¤¬ ÉÕ¤¤¤Æ¤¤¤ë¡£¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë ¤Ï³ç¸Ì¤Ë°Ï¤Þ¤ì¤Æ¤¤¤ë¡£ -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Í¥Ã¥È̾¤Î°ìÍ÷ɽ -end- ho.ports -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ý¡¼¥È̾¤Î°ìÍ÷ɽ -end- ho.status.logo -begin- ¸½ºß¤Î¥â¡¼¥É¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£Å´¤Î¥²¡¼¥È ¤Î¾ì¹ç¡¢ÊÔ½¸¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤Î¾ì¹ç¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤¬ Áö¤Ã¤Æ ¤¤¤ë¾ì¹ç¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö¤¬ Æ°¤¤¤Æ¤¤¤ë¡£ -end- ho.status.msg TkGate¤è¤ê¤Î¥á¥Ã¥»¡¼¥¸¤¬¤³¤³¤Ëɽ¼¨¤µ¤ì¤ë¡£ ho.status.block ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥¹ ho.status.file -begin- ¸½ºßÊÔ½¸Ãæ¤Î¥Õ¥¡¥¤¥ë̾¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£¡Ö*¡× ¤È¤¤¤¦µ­¹æ¤¬¤Ä¤¤¤Æ¤¤¤ë»þ¡¢Êݸ¤·¤Æ¤¤¤Ê¤¤Êѹ¹ ¤¬¤¢¤ë¡£ -end- ho.print.selall Á´¤Æ¤ÎÆɤ߹þ¤ó¤Ç¤¤¤ë¥â¥¸¥å¡¼¥ë¤ò°õºþ¤¹¤ë¡£ ho.print.selcur ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ho.print.seluse -begin- »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß°õºþ¤¹¤ë¡£ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- °Ê²¼¤Ë¥Þ¡¼¥¯¤·¤Æ¤¤¤ë¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ÇÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤òÁªÂò ½ÐÍè¤ë¡£ -end- ho.print.modlist °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë¤òÁªÂò¤¹¤ë¡£ ho.circuit.discchg -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢Êѹ¹¤¢¤ê¤Î²óÏ©¤ò Êݸ¤·¤Ê¤¤¤ÇÊĤ¸¤ë¤È¤­·Ù¹ð¤·¤Ê¤¤¡£ -end- ho.circuit.extbar -begin- ´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬ 3Ëܰʾå¤Î»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.circuit.autostart -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤ËÆþ¤ë¤È¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤¬¤¹¤°¼Â¹Ô¤¹¤ë¡£ -end- ho.circuit.language -begin- ²óÏ©¥Ç¡¼¥¿¤òɽ¼¨¤¹¤ë°Ù¤Î¥Õ¥©¥ó¥È¤ò ÁªÂò¤·¤Æ¤¯¤À¤À¤¤¡£ÆüËܸìn¤Î¾ì¹ç¡¢ ¡Öeuc-jp¡×¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.cmd.bitw -begin- ¥«¡¼¥½¥ë¤ÇÁªÂò¤µ¤ì¤¿¥ï¥¤¥ä¤Ïɽ¼¨ ¤µ¤ì¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤵ¤ì¤ë¡£ -end- ho.edgat.signam -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Ç¤¢¤ë¡£Ì¾Á°¤¬Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.port -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥È̾¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.iolab -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥ÈÊý¸þ¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.bitlab -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ó¥Ã¥ÈÉý¤Ç¤¢¤ë¡£Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.cycle °ì¥µ¥¤¥¯¥ë¤Î¥¨¥Ý¥Ã¥¯¿ô ho.edgat.phase ¥¯¥í¥Ã¥¯¤Î¥Õ¥§¡¼¥º¡Ê¥Ñ¡¼¥»¥ó¥È¤ÇÀßÄꤹ¤ë¡Ë ho.edgat.duty ¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë¤Î²¿¥Ñ¡¼¥»¥ó¥È¤¬ÏÀÍý0¤Ç¤¢¤ë¤« ho.edgat.hide -begin- Í­¸ú¤Ë¤¹¤ë¤È¥³¥ó¥Ý¡¼¥Í¥ó¥È̾¤¬É½¼¨¤µ¤ì¤Ê¤¤¡£ -end- ho.edgat.gtype ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¼ïÎà ho.edgat.gname ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î̾Á° ho.edgat.ganchor Í­¸ú¤Ë¤¹¤ë¤È¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬°ÜÆ°ÉԲĤˤʤ롣 ho.edgat.gx ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎX°ÌÃÖ ho.edgat.gy ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎY°ÌÃÖ ho.edgat.swstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.dipstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.range ¥Þ¥ë¥Á¥Ó¥Ã¥È¤Î¿®¹æ¤Î¥µ¥Ö¡¦¥ì¥ó¥¸¤Ç¤¢¤ë¡£ ho.edgat.memfile -begin- ¥á¥â¥ê¤Î½é´ü¤ÎÃͤΥե¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¡¢¤³¤Î¥Õ¥¡¥¤¥ë ¤¬Æɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.edgat.func ¥â¥¸¥å¡¼¥ë¤Îµ¡Ç½ ho.edgat.frame ¥Õ¥ì¡¼¥à¤Î¥é¥Ù¥ë ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the TkGate interface. This option will not take effect until restarting TkGate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the TkGate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to TkGate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save TkGate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for TkGate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when TkGate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undo¤Î¥ê¥¹¥È¤ÎŤµ -end- ho.opt.name -begin- TODO: User name to be used on TkGate generated reports such as circuit printouts. -end- ho.opt.site -begin- ²óÏ©¤Ê¤É¤ò°õºþ¤¹¤ë»þ¡¢¤³¤Î¥µ¥¤¥È̾¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.smooth -begin- ¤³¤ÎÀßÄê¤òÍ­¸ú¤Ë¤¹¤ë¤È¡¢²óÏ©¤ò¥¹¥¯¥í¡¼¥ë¤¹¤ë»þ¡¢ ¥Ó¥Ã¥È¥Þ¥Ã¥×¤Î¥³¥Ô¡¼¤òÍøÍѤ·¤Æ¡¢¸úΨ¤è¤¯ ¥¹¥¯¥í¡¼¥ë¤Ç¤­¤ë¡£X¥µ¡¼¥Ð¤ÎÌäÂ꤬¤¢¤ì¤Ð¡¢¤³¤Î ÀßÄê¤ò̵¸ú¤Ë¤¹¤ì¤ÐÎɤ¤¡£ -end- ho.opt.clip -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¦¥¤¥ó¥É¥¦¤ÎÉôʬÎΰè¤Î ºÆÉÁ²è¤ò¹Ô¤Ê¤¦¡£¤½¤¦¤Ç¤Ê¤±¤ì¤Ð¾ï¤Ë Á´Îΰè¤òºÆÉÁ²è¤¹¤ë¡£ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥â¥¸¥å¡¼¥ë¤ò°ÜÆ°¤¹¤ë»þ¡¢ ¥ï¥¤¥ä¤Ê¤É¤Ï¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤òÎ¥¤¹¤Þ¤Ç °ÜÆ°¤·¤Ê¤¤¡£²èÌ̤Îɽ¼¨¤¬ÃÙ¤¤»þ¤ËÊØÍø¤Ç¤¢¤ë¡£ -end- ho.opt.bhelp -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ÎÍͤʡ֥إë¥×¡¦ ¥Ð¥ë¡¼¥ó¡×¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.novice -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢½é¿´¼Ô¥â¡¼¥É¤Ë¤Ê¤ë¡£ ½é¿´¼Ô¥â¡¼¥É¤Ç¤Ï¡¢TkGate¤¬Î©¤Á¾å¤¬¤ë»þ¡¢ ¥Á¥å¡¼¥È¥ê¥¢¥ë¤¬¼«Æ°Åª¤ËÆɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ç¥Ð¥°µ¡Ç½¤¬»È¤¨¤ë¡£ ³«È¯¼Ô°Ê³°¤Ë¡¢¤¢¤Þ¤êÌò¤ËΩ¤¿¤Ê¤¤¡£ -end- ho.opt.ckpt Í­¸ú¤Ë¤¹¤ë¤È¡¢TkGate¤Ï¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤Î¥Õ¥¡¥¤¥ë¤òºî¤ë¡£ ho.opt.ckptfreq ¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤ò²¿¥¯¥ê¥Ã¥¯Ëè¤Ë¹Ô¤Ê¤¦¤« ho.opt.beak -begin- Á´Á³Ìò¤ËΩ¤¿¤Ê¤¤µ¡Ç½¤òÍ­¸ú¤Ë¤¹¤ë¡£¤³¤Îµ¡Ç½¤ò ̵¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥¹¥¤¥Ã¥Á¤Ï¥À¥¤¥¢¥í¥° ¥Ü¥Ã¥¯¥¹¤«¤é¾Ã¤¨¡¢.tkgate-properties¤òÊÔ½¸¤·¤Ê¤¤¸Â¤ê Ìá¤é¤Ê¤¤¡£ -end- ho.opt.miles -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢TkGate¤Ï»þ¡¹¥æ¡¼¥¶¤ò Çϼ¯¤Ë¤·¤¿¤ê¡¢°­¸ý¤ò¸À¤Ã¤¿¤ê¤¹¤ë¡£ -end- ho.opt.bat -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ð¥Ã¥È¥Þ¥ó¤Î¥³¥ó¥Ô¥å¡¼¥¿¤ò À߷פ¹¤ë°Ù¤Ë¡ÖÌò¤Ë¤¿¤Ä¡×µ¡Ç½¤¬»È¤¨¤ë¡£ -end- ho.opt.trek žÁ÷¤·¤í¡¢¥¹¥³¥Ã¥Æ¥£¡ª ho.opt.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¹¥Æ¥Ã¥×¡¦¥³¥Þ¥ó¥É¤Ç ²¿¥¨¥Ý¥Ã¥¯¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¥¹¥Æ¥Ã¥×¡¦ ¥³¥Þ¥ó¥É¤Ç ²¿¥µ¥¤¥¯¥ë¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckover -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤è¤ê¹¹¤Ë²¿¥¨¥Ý¥Ã¥¯ ¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.vpopupdelay -begin- ¥Þ¥¦¥¹¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤«¤é¡¢²¿¥ß¥êÉÃ·Ð¤Ã¤Æ ¤«¤é¿®¹æ¤ÎÃͤ¬É½¼¨¤µ¤ì¤ëÃÙ±ä¤Ç¤¢¤ë¡£ ¤³¤Î Ãٱ䤬û²á¤®¤ë»þ¡¢¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤¬ ǧÃÎ ¤Ç¤­¤Ê¤¯¤Ê¤ëÌäÂ꤬¤¢¤ë¥·¥¹¥Æ¥à¤Ï ¤¢¤ë¡£ ¤³¤ÎÌäÂ꤬µ¯¤³¤é¤Ê¤±¤ì¤Ð¡¢ÃÙ±ä ¤ò¤è¤ê û¤¯¤·¤Æ¤âÎɤ¤¡£ -end- ho.opt.init -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òΩ¤Á¾å¤²¤ë»þ¤Ë ¼«Æ°Åª¤Ë¼Â¹Ô¤¹¤ë¥¹¥¯¥ê¥×¥È¡¦ ¥Õ¥¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckall -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¤É¤Î¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Ç¤âÄä»ß¤¹¤ë¡£ -end- ho.opt.ckspec -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï »ØÄꤷ¤¿¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Î¤ß¤ËÄä»ß¤¹¤ë¡£ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart TkGate to see any user defined keybindings. -end- ho.deftech -begin- ¿·¤·¤¤¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥Æ¥¯¥Î¥í¥¸¡¼¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÃÙ±ä¤Ë±Æ¶Á¤¹¤ë¡£Ç¤°Õ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È ¤Î ¥Æ¥¯¥Î¥í¥¸¡¼¤òÊѹ¹¤¹¤ë¤Ë¤Ï¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê ¥Ü¥Ã¥¯¥¹¤ò³«¤¤¤Æ¡¢¡ÖÃÙ±ä¡×¤Î¥¿¥Ö ¤òÁªÂò ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.techbut -begin- »ØÄꤷ¤¿¥Æ¥¯¥Î¥í¥¸¡¼¡¦¥Õ¥¡¥¤¥ë¤«¤é¤Î ÃÙ±äÃͤò ÍøÍѤ¹¤ë¡£¿·¤·¤¤¥Æ¥¯¥Î¥í¥¸¡¼¤ò Äɲ乤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¢ª¡ÖÀßÄê...¡×¢ª ¡Ö¥·¥ß¥å¥ì¡¼¥È¡× ¤Î¥á¥Ë¥å¡¼¤ò³«¤¤¤Æ¡¢ ¥Õ¥¡¥¤¥ë¤Î¥ê¥¹¥È¤ËÄɲà ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.custbut -begin- ¤³¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥ÈÀìÍѤÎÃÙ±äÃͤò»ØÄꤹ¤ë¡£ -end- ho.contver -begin- ¥Þ¥¦¥¹Áàºî¤ò¹Ô¤Ê¤¦»þ¡¢ÆâÉô¹½Â¤¤ò¼«Æ°Åª¤Ë ³Îǧ¤·¤Æ¡¢ÉÔÀµ¤Î½ê¤òÃΤ餹¡£ -end- ho.simwatch -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ÈGUI¤Î´Ö¤Î¥³¥Þ¥ó¥É¤òɽ¼¨¤¹¤ë¡£ -end- ho.modtree -begin- ³¬Áإĥ꡼¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.modlist -begin- °ìÍ÷ɽ¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- ¸½ºß¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È²óž¤òɽ¼¨¤·¤Æ¤¤¤Þ¤¹¡£ ¾°¡¢¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥Ç¥Õ¥©¥ë¥È²óž¤òÊѹ¹¤·¤Þ¤¹¡£ -end- ho.tool.zoomin ¥º¡¼¥à¡¦¥¤¥ó ho.tool.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È ho.tool.rotate ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÈó»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.brotate ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.valgn ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò½Ä¤Ë°ìÎó¤Ëʤ֡£ ho.tool.halgn ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÍâ¤Ë°ìÎó¤Ëʤ֡£ ho.tool.cut ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥«¥Ã¥È¤¹¤ë¡£ ho.tool.copy ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥³¥Ô¡¼¤¹¤ë¡£ ho.tool.paste ¥«¥Ã¥È¥Ð¥Ã¥Õ¥¡¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÄ¥¤êÉÕ¤±¤ë¡£ ho.tool.find ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¢¥ï¥¤¥ä¡¢¥Æ¥­¥¹¥È¤Ê¤É¤òõº÷¤¹¤ë¡£ ho.tool.addport ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Ë¥Ý¡¼¥È¤òÄɲ乤롣 ho.tool.anchor ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°ÉԲĤˤ¹¤ë¡£ ho.tool.unanchor ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°²Äǽ¤Ë¤¹¤ë¡£ ho.tool.replicate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÊ£À½¤¹¤ë¡£ ho.tool.delete ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òºï½ü¤¹¤ë¡£ ho.opt.tearawaymenus -begin- TODO: If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.ipanel.deleteport -begin- TODO: Delete the selected port. -end- ho.ipanel.updateall -begin- TODO: Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.circuit.title -begin- TODO: Description of your circuit. This title is used on printed output. -end- ho.ipanel.generate -begin- TODO: Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.simmove -begin- TODO: Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.opt.sim.savetraces -begin- TODO: Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.ipanel.editport -begin- TODO: Edit the selected port. You can also double-click to edit a field in a port. -end- ho.symed.export TODO: Export image to file. ho.setsel.ltor TODO: Move highlighted items to selected list. ho.print.timegraph -begin- TODO: The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.setsel.allr TODO: Move all items to selected list. ho.circuit.encoding -begin- TODO: Use this encoding for save files. -end- ho.opt.tool.simmode TODO: Choose between the select and scroll tool in simulator. ho.setsel.alll TODO: Move all items to unselected list. ho.circuit.ver -begin- TODO: This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.file -begin- TODO: This is the file name from which the current circuit was loaded. -end- ho.scroll -begin- TODO: Scroll - Grab and drag the editing canvas. -end- ho.symed.import TODO: Import image from file. ho.ipanel.select -begin- TODO: Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- TODO: Add a port to the module. You can also double-click after the last item to add port. -end- ho.setsel.rtol TODO: Move highlighted items to unselected list. blklst.delete.title TkGate: ¥â¥¸¥å¡¼¥ëºï½ü print.tab.advanced ¥¢¥É¥Ð¥ó¥¹ primitive.err.nomodule ÆâÉô¥¨¥é¡¼: ¥×¥ê¥ß¥Æ¥£¥Ö¡¦¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ç¡¢¥­¡¼¥ï¡¼¥É¡Ömodule¡×¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ db.net.caption ¥Í¥Ã¥È¤ÎÆÃħ blklst.rename.title TkGate: ¥â¥¸¥å¡¼¥ë¤ÎºÆ̾ÉÕ¤± db.gate.switch.state ½é´ü¥¹¥¤¥Ã¥Á¤Î¾õÂÖ primitive.err.wrongname ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬ÆâÉô¥â¥¸¥å¡¼¥ë̾¤È°ìÅù¤·¤Þ¤»¤ó¡£ db.gate.tap.lbl.bit ¥Ó¥Ã¥È: db.hdl.textdisp.title HDL¤Î¥Æ¥­¥¹¥È¤Î½èÍý db.gate.tap.select ¥Ó¥Ã¥È¡¦¥¿¥Ã¥×¤ÎÁªÂò db.err.neededit -fillbegin- ¥¦¥¡¡¼¥ó¥¤¥ó¥°¤Ë°ÜÆ°¤¹¤ëÁ°¤Ë¡¢ÊÔ½¸¥â¡¼¥É¤ËÀÚÂؤ¨¤ëɬÍפ¬¤¢¤ê¤Þ¤¹¡£ -end- menu.edit.autobold ¼«Æ°ÂÀ»ú @db.gate.tap.exp.width *180 circ.reallyupdate -fillbegin- ËÜÅö¤ËÁ´¤Æ¤Î¡Ö%s¡×¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤ò¹¹¿·¤·¤¿¤¤¤Î¤Ç¤¹¤«¡£ -end- circ.reallyoverwrite -fillbegin- ËÜÅö¤Ë´û¤Ë¸ºß¤·¤Æ¤¤¤ë¥Õ¥¡¥¤¥ë¡Ö%s¡×¤Î¾å¤Ë½ñ¤­¹þ¤ß¤¿¤¤¤Ç¤¹¤«¡£ -end- blklst.copy.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥³¥Ô¡¼ primitive.err.missing ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬È¯¸«½ÐÍè¤Þ¤»¤ó¡£ menu.file.import ²èÁü¥Ç¡¼¥¿¤ò¥¤¥ó¥Ý¡¼¥È db.newcirc.title TkGate: ¿·µ¬²óÏ© opt.tool.simmode ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ä¡¼¥ë blklst.new.title TkGate: ¿·µ¬¥â¥¸¥å¡¼¥ë print.title TkGate: °õºþ db.gate.switch.state.on.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥ó print.config.title TkGate: °õºþ¤ÎÀßÄê db.gate.waveform ¥¯¥í¥Ã¥¯¤ÎÇÈ·Á print.incunused »ÈÍѤ·¤Ê¤¤¥â¥¸¥å¡¼¥ë¤â´Þ¤ß¤Þ¤¹¡£ db.gate.switch.state.on.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥ó¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ db.gate.switch.state.off.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥Õ opt.treelabel ¥ª¥×¥·¥ç¥ó menu.symbol ¥·¥ó¥Ü¥ë print.tab.modules ¥â¥¸¥å¡¼¥ë opt.title TkGate: ¥ª¥×¥·¥ç¥ó port.title TkGate: ¥Ý¡¼¥È¤ÎÈùºÙ primitive.err.nomodname ÆâÉô¥¨¥é¡¼:¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤ÎÄêµÁ¤Ë¥â¥¸¥å¡¼¥ë̾¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ blklst.claim.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥¯¥ì¡¼¥à igen.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤Î¼«Æ°ºîÀ® err.yy.badlocale ¥»¡¼¥Ö¡¦¥Õ¥¡¥¤¥ë¤Ë̤ÃΤÎʸ²½·÷¡Ö%s¡×¤¬¤¢¤ê¤Þ¤·¤¿¡£ÊѤï¤ê¤Ë±Ñ¸ì¤Îʸ²½·÷¤¬ÍøÍѤµ¤ì¤Þ¤¹¡£ db.dip.title TkGate: DIP¤ÎÃÍ print.scope.title TkGate: ¥¹¥³¡¼¥×¤Î°õºþ db.gate.switch.state.off.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥Õ¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ circ.wintitle TkGate: ²óÏ©¤ÎÈùºÙ find.title TkGate: õº÷ db.gate.dip.value.exp ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Îµ¯Æ°¤Î»þ¤ÎDIP¤ÎÃÍ¡£ menu.file.export ²èÁü¥Ç¡¼¥¿¤Î¥¨¥¯¥¹¥Ý¡¼¤È print.rangeselection ¥ì¡¼¥ó¥¸¤ÎÁªÂò pop.simulate.delprobe ¥Ý¥í¡¼¥Ö¤Îºï½ü print.linelen °ì¹ÔÎó¤Î»þ´Ö db.hdl.namechange.title HDL¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ opt.vlibadd.title TkGate: ¥é¥¤¥Ö¥é¥ê¡¼¤ÎÄɲà blklst.setroot.title TkGate: ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤ÎÀßÄê @db.gate.dip.value.exp.width 150 tkgate-2.0-b10/locale/ja/messages000644 001751 001751 00000250222 11150362346 017375 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Feb 22 18:51:02 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # \font-encoding iso8859-1 \messages-encoding euc-jp \verilog-encoding euc-jp \display-encoding euc-jp \language Japanese ############################################################################## # # basic strings # b.new ¿·µ¬... b.dismiss ÊĤ¸¤ë b.close ÊĤ¸¤ë b.ok £Ï£Ë b.clear ¥¯¥ê¥¢ b.cancel ¥­¥ã¥ó¥»¥ë b.open ³«¤¯ b.bitw ¥Ó¥Ã¥ÈÉý b.in Æþ b.out ½Ð b.inout Æþ½Ð b.browse ÁªÂò... b.label ̾Á° b.find õº÷ b.edit ÊÔ½¸... b.add ÄɲÃ... b.delete ºï½ü b.deleteb ºï½ü... b.remove ¾Ã¤¹ b.apply ¥»¥Ã¥È b.anchor °ÜÆ°ÉÔ²Ä b.tech ¥Æ¥¯¥Î¥í¥¸¡¼ b.enable ²Äǽ¤Ë¤¹¤ë b.disable ̵ǽ¤Ë¤¹¤ë b.flush ¥¯¥ê¥¢ ############################################################################## # # Main tab strings # tab.edit ÊÔ½¸ tab.editintr ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ tab.simulate ¥·¥ß¥å¥ì¡¼¥È tab.cpath ÃÙ±ä²òÀÏ # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add ÄɲÃ... mm.delete ºï½ü mm.edit ÊÔ½¸... mm.enable Í­¸ú¤Ë¤¹¤ë mm.disable ̵¸ú¤Ë¤¹¤ë ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ¥Õ¥¡¥¤¥ë menu.edit ÊÔ½¸ menu.tool ¥Ä¡¼¥ë menu.simulate ¥·¥ß¥å¥ì¡¼¥È menu.module ¥â¥¸¥å¡¼¥ë menu.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.format ¥Õ¥©¡¼¥Þ¥Ã¥È menu.make ¥³¥ó¥Ý¡¼¥Í¥ó¥È menu.help ¥Ø¥ë¥× menu.file.new ¿·µ¬ºîÀ® menu.file.open ³«¤¯... menu.file.openlib ¥é¥¤¥Ö¥é¥ê´ÉÍý... menu.file.save Êݸ menu.file.saveas ̾Á°¤òÉÕ¤±¤ÆÊݸ... menu.file.print °õºþ... menu.tool.options ÀßÄê... menu.file.quit ½ªÎ» menu.file.cprop ²óÏ©¤ÎÆÃħ... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut ¥«¥Ã¥È menu.edit.copy ¥³¥Ô¡¼ menu.edit.paste ¥Ú¡¼¥¹¥È menu.edit.overlay OverlayÄ¥¤êÉÕ¤± menu.edit.selall Á´¤Æ¤òÁªÂò menu.edit.find ²óÏ©¤òõº÷... menu.edit.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.edit.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.edit.rshift ±¦¥·¥Õ¥È menu.edit.lshift º¸¥·¥Õ¥È menu.edit.ushift ¾å¥·¥Õ¥È menu.edit.dshift ²¼¥·¥Õ¥È menu.edit.cwrotate »þ·×¼þ¤ê²óž menu.edit.ccwrotate »þ·×È¿Âмþ¤ê²óž menu.edit.pcwrotate ¥Ý¡¼¥È¤Î»þ·×¼þ¤ê²óž menu.edit.pccwrotate ¥Ý¡¼¥È¤ÎÈó»þ·×¼þ¤ê²óž #menu.edit.autobold ÂÀ»ú²½ menu.edit.resize ºÆ¥µ¥¤¥º²½ menu.tool.move °ÜÆ°¡¿Àܳ menu.tool.delg ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Îºï½ü menu.tool.cutw ¥ï¥¤¥ä¤ÎÀÚÃÇ menu.tool.inv ÈÝÄê menu.tool.bitw ¥Ó¥Ã¥ÈÉý menu.tool.debug ¥Ç¥Ð¥Ã¥° menu.tool.point ¥Ý¥¤¥ó¥È menu.tool.line ¥é¥¤¥ó menu.tool.rect ĹÊý·Á menu.tool.fillrect ¿§¤Å¤±Ä¹Êý·Á menu.tool.port ¥Ý¡¼¥È menu.tool.select ÌÈÀÕÁªÂò menu.tool.tclshell 0:Tcl Shell menu.tool.rep Ê£À½ menu.format.algnv ½Ä¤Î°ìÎó menu.format.algnh ²£¤Î¡¼Îó menu.format.rot ²óž menu.format.rot.0 ¥Ç¥Õ¥©¥ë¥È²óž¤ò0Å٤ˤ¹¤ë menu.format.rot.90 ¥Ç¥Õ¥©¥ë¥È²óž¤ò90Å٤ˤ¹¤ë menu.format.rot.180 ¥Ç¥Õ¥©¥ë¥È²óž¤ò180Å٤ˤ¹¤ë menu.format.rot.270 ¥Ç¥Õ¥©¥ë¥È²óž¤ò270Å٤ˤ¹¤ë menu.format.rot.rotate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î²óž menu.format.rot.brotate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎµÕ²óž menu.format.addport ¥Ý¡¼¥ÈÄɲà menu.format.ioset ¥¿¥¤¥×»ØÄê menu.format.anchor ÁªÂò¤ò°ÜÆ°ÉԲĤˤ¹¤ë menu.format.unanchor ÁªÂò¤ò°ÜÆ°²Ä¤Ë¤¹¤ë menu.format.prop ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê... menu.format.del ºï½ü menu.format.settech ¥Æ¥¯¥Î¥í¥¸¡¼¤ÎÀßÄê menu.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï menu.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» menu.simulate.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.simulate.run ¥é¥ó menu.simulate.pause °ì»þ¥¹¥È¥Ã¥× menu.simulate.step ¥¹¥Æ¥Ã¥×(¥¨¥Ý¥Ã¥¯) menu.simulate.cycle ¥¹¥Æ¥Ã¥×(¥µ¥¤¥¯¥ë) menu.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤ÎÀßÄê... menu.simulate.script ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô... menu.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.simulate.dump ¥á¥â¥ê¤Î½ñ¤­½Ð¤·... menu.simulate.view ¥á¥â¥ê¤Îɽ¼¨... menu.module.open ³«¤¯ menu.module.close ÊĤ¸¤ë menu.module.new ¿·µ¬ºîÀ®... menu.module.del ºï½ü... menu.module.copy ¥³¥Ô¡¼... menu.module.rename ̾Á°¤ÎÊÔ½¸... menu.module.claim ¼èÆÀ... menu.module.setroot ¥ë¡¼¥È¤Ë¤¹¤ë... menu.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÀßÄê... menu.module.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.module.interface.set ¥»¥Ã¥È menu.module.interface.edit ÊÔ½¸ menu.module.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.auto ¼«Æ°ºîÀ®... menu.help.about TkGate¤Ë¤Ä¤¤¤Æ... menu.help.license ¥é¥¤¥»¥ó¥¹... menu.help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... menu.help.tut ¥Á¥å¡¼¥È¥ê¥¢¥ë menu.help.home ¥Û¡¼¥à¡¦¥Ú¡¼¥¸ menu.help.example ²óÏ©¤ÎÎã ############################################################################# # Scope Menu # menu.scope_file ¥Õ¥¡¥¤¥ë menu.scope_sim ¥·¥ß¥å¥ì¡¼¥È menu.scope_trace ¥È¥ì¡¼¥¹ menu.scope_help ¥Ø¥ë¥× menu.scope_file.ptrace ¥È¥ì¡¼¥¹°õºþ... menu.scope_file.close ÊĤ¸¤ë menu.scope_trace.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.scope_trace.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.scope_sim.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.scope_sim.run »þ¸ú menu.scope_sim.pause °ì»þÄä»ß menu.scope_sim.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... menu.scope_sim.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... menu.scope_sim.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.scope_sim.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... menu.scope_help.about TkGate¤ËÉÕ¤¤¤Æ... menu.scope_help.license ¥é¥¤¥»¥ó¥¹... menu.scope_help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... mod.intf ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ port.parms ¥Ý¡¼¥È¤Î¥Ñ¥é¥á¥¿ port.in Æþ port.out ½Ð port.inout Æþ½Ð ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ¥²¡¼¥È gm.rgate ñ¹à½ÌÌ󥲡¼¥È gm.msi MSI gm.alu ALU gm.mem ¥á¥â¥ê¡¼ gm.mod ¥â¥¸¥å¡¼¥ë gm.comment ¥³¥á¥ó¥È gm.frame ¥Õ¥ì¡¼¥à gm.script Verilog¥¹¥¯¥ê¥×¥È gm.io.switch ¥¹¥¤¥Ã¥Á gm.io.dip DIP¥¹¥¤¥Ã¥Á gm.io.ground ¥¢¡¼¥¹ gm.io.vdd Vdd gm.io.merge ¥ï¥¤¥ä¤Î¥Þ¡¼¥¸ gm.io.clock ¥¯¥í¥Ã¥¯ gm.io.led LED¥Ó¥Ã¥È gm.io.ledbar LEDËÀ¥°¥é¥Õ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ¥Ð¥Ã¥Õ¥¡ gm.gate.inv ÈÝÄê¥Ð¥Ã¥Õ¥¡ gm.gate.tribuf ¥È¥é¥¤¡¦¥Ð¥Ã¥Õ¥¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and ñ¹à½ÌÌóAND gm.rgate.nand ñ¹à½ÌÌóNAND gm.rgate.or ñ¹à½ÌÌóOR gm.rgate.nor ñ¹à½ÌÌóNOR gm.rgate.xor ñ¹à½ÌÌóXOR gm.rgate.xnor ñ¹à½ÌÌóXNOR gm.alu.add ²Ã»»´ï gm.alu.mult ¾è»»´ï gm.alu.div ½ü»»´ï gm.alu.lshift º¸¥·¥Õ¥È gm.alu.rshift ±¦¥·¥Õ¥È gm.alu.arshift »»¿ôŪ±¦¥·¥Õ¥È gm.alu.roll ¥í¡¼¥ë gm.mem.reg ¥ì¥¸¥¹¥¿ gm.mem.ff ¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rff È¿¼Í¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rjkff È¿¼ÍJK¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.msi.21mux 2-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.41mux 4-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.81mux 8-1 ¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.12dec 1-2 ¥Ç¥³¡¼¥À gm.msi.14dec 1-4 ¥Ç¥³¡¼¥À gm.msi.18dec 1-8 ¥Ç¥³¡¼¥À gm.msi.12demux 1-2 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.14demux 1-4 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.msi.18demux 1-8 ¥Ç¥Þ¥ë¥Á¥×¥ì¥¯¥µ gm.mod.inst ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹ gm.mod.in ¥â¥¸¥å¡¼¥ë¤ÎÆþÎÏ gm.mod.out ¥â¥¸¥å¡¼¥ë¤Î½ÐÎÏ gm.mod.inout ¥â¥¸¥å¡¼¥ë¤ÎÆþ½ÐÎÏ tutorial.prev Á°¤Ø tutorial.next ¼¡¤Ø tutorial.chapter ¾Ï¤Î°ìÍ÷ɽ tutorial.reload ºÆÆɤ߹þ¤ß ############################################################################## # # Popup menus # pop.make ¥³¥ó¥Ý¡¼¥Í¥ó¥È pop.tool ¥Ä¡¼¥ë pop.edit.paste ¥Ú¡¼¥¹¥È pop.edit.cut ¥«¥Ã¥È pop.edit.copy ¥³¥Ô¡¼ pop.port.in Æþ pop.port.out ½Ð pop.port.inout Æþ½Ð pop.wire.addseg ¥ï¥¤¥ä¤ÎÄɲà pop.wire.prop ¥Í¥Ã¥È¤ÎÆÃħ... pop.wire.hidesize ¥Ó¥Ã¥ÈÉý¤ò±£¤¹ pop.wire.showsize ¥Ó¥Ã¥ÈÉý¤ò¼¨¤¹ pop.wire.hidelabel ¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.hidealllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.clearalllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò¥¯¥ê¥¢ pop.wire.showlabel ¥ì¡¼¥Ù¥ë¤ò¼¨¤¹ pop.gate.open ³«¤¯ pop.gate.close ÊĤ¸¤ë pop.gate.prop ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÆÃħ... pop.gate.addport ¥Ý¡¼¥È¤ÎÄɲà pop.gate.addin ÆþÎϤÎÄɲÃ... pop.gate.addout ½ÐÎϤÎÄɲÃ... pop.gate.addinout Æþ½ÐÎϤÎÄɲÃ... pop.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë pop.gate.settech ¥Æ¥¯¥Î¥í¥¸»ØÄê pop.gate.delete ºï½ü pop.gate.ioset ¥¿¥¤¥×¤Î»ØÄê pop.module.new ¿·µ¬... pop.module.del ºï½ü... pop.module.copy ¥³¥Ô¡¼... pop.module.rename ̾Á°¤ÎÊѹ¹... pop.module.claim ¥â¥¸¥å¡¼¥ë¤Î¼èÆÀ pop.module.setroot ¥ë¡¼¥È»ØÄê... pop.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÆÃħ... pop.module.int ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸... pop.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» pop.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï pop.simulate.addprobe ¥×¥í¡¼¥Ö¤òÄɲῺï½ü pop.simulate.run »þ¸ú pop.simulate.pause °ì»þÄä»ß pop.simulate.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× pop.simulate.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× pop.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... pop.simulate.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... pop.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... pop.simulate.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... pop.simulate.view ¥á¥â¥ê¤Îɽ¼¨... pop.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ pop.interface.set »ØÄê pop.interface.edit ÊÔ½¸... pop.interface.replace ¼è¤ê´¹¤¨ pop.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.auto ¼«Æ°ºîÀ®... pop.igen.type ¥¿¥¤¥× pop.igen.side ¥µ¥¤¥É pop.igen.size ¥µ¥¤¥º pop.igen.delete ºï½ü pop.igen.in Æþ pop.igen.out ½Ð pop.igen.inout Æþ½Ð pop.igen.left º¸ pop.igen.right ±¦ pop.igen.top ¾å pop.igen.bottom ²¼ pop.igen.other ¾ pop.library.mgr ¥é¥¤¥Ö¥é¥ê´ÉÍý... pop.library.close ¥é¥¤¥Ö¥é¥ê¤ò¥¢¥ó¥í¡¼¥É ############################################################################## # # Symbol editor strings # symed.cancel ¥­¥ã¥ó¥»¥ë symed.tab.normal È󥻥쥯¥È symed.tab.select ¥»¥ì¥¯¥È symed.link ¥»¥ì¥¯¥È¤ÈÈ󥻥쥯¥È¤òƱ»þ¤ËÊÔ½¸¤¹¤ë¡£ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## ## memory viewer # memview.title ¥á¥â¥ê¤ÎÆâÍÆ memview.exp -fillbegin- ¥á¥â¥ê¤ÎÆâÍƤòɽ¼¨¤·¤¢¤¿¤ê¡¢Êѹ¹¤·¤¿¤ê½ÐÍè¤ë¡£ ¥á¥â¥ê¤ÎÆâÍƤòÊѹ¹¤¹¤ë°Ù¡¢Ãͤ˥¯¥ê¥Ã¥¯¤·¤Æ¡¢ ¿·¤·¤¤Ãͤò¥­¡¼¥Ü¡¼¥É¤ÇÆþÎϤ·¤Æ¤¯¤À¤À¤¤¡£ -end- ############################################################################## scope.title TkGate: ¥¹¥³¡¼¥× scope.emptymsg ¥ï¥¤¥ä¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥×¥í¡¼¥Ö¤ËÉÕ¤±¤Ã¤Æ¤¯¤À¤µ¤¤¡£ comment.empty [¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Æ¥­¥¹¥È¤òÊÔ½¸¤·¤Æ¤¯¤À¤µ¤¤¡£] ############################################################################## # Interface strings # ifile ¥Õ¥¡¥¤¥ë imodule ¥â¥¸¥å¡¼¥ë iblmodule ¥â¥¸¥å¡¼¥ë: iports ¥Ý¡¼¥È: ibits ¥Ó¥Ã¥ÈÉý: itype ¥¿¥¤¥×: ############################################################################# # Module Dialog Box # db.mod.name ¥â¥¸¥å¡¼¥ë̾ db.mod.file ¥Õ¥¡¥¤¥ë̾ db.mod.type ¥¿¥¤¥× db.mod.flags ¥Õ¥é¥° db.mod.dataprot ¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.intfprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.edprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÀìÍÑ¥¨¥Ç¥£¥¿¤Ë¸Â¤ë¡£ db.mod.props ÆÃħ db.mod.netlist ¥Í¥Ã¥È¥ê¥¹¥È db.mod.hdl HDL # # These are probably not used anymore. Lets leave them as is. # db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netexpl -begin- ¥°¥é¥Õ¥£¥«¥ë¤Î¥¨¥Ç¥£¥¿¤ò ÍøÍѤ·¤Æ¡¢¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤ò ÄêµÁ¤¹¤ë¡£ -end- db.mod.hdlexpl -begin- Verilog¤Î¥Æ¥­¥¹¥È¤òÍøÍѤ·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤òÄêµÁ¤¹¤ë¡£ -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.caption ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.explain.warn -fillbegin- ²óÏ©Ãæ¤Ë¥ï¡¼¥Ë¥ó¥°¤¬¤¢¤ê¤Þ¤¹¤¬¡¢¤½¤ì¤Ë¤«¤«¤é¤ï¤º¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤¬µ¯Æ°¤·¤Þ¤¹¡£¥ï¡¼¥Ë¥ó¥°¤Î²Õ½ê¤ò°ÜÆ°¤¹¤ë¤¿¤á¡¢ÊÔ½¸¥â¡¼¥É¤ËÀÚÂؤ¨¤Ê¤¯¤Æ¤Ï¤Ê¤ê¤Þ¤»¤ó¡£ -end- db.err.explain.err -fillbegin- ²óÏ©Ãæ¤Ë¥¨¥é¡¼¤¬Â¸ºß¤·¤Þ¤¹¡£¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°½ÐÍè¤Þ¤»¤ó¡£ -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: ¥Í¥Ã¥È¤ÎÈùºÙ db.net.name ¥Í¥Ã¥È̾ db.net.hide ¥Í¥Ã¥È̾¤ò±£¤¹ db.net.bits ¥Ó¥Ã¥ÈÉý db.net.type ¥Í¥Ã¥È¡¦¥¿¥¤¥× db.net.port ¥Ý¡¼¥È¡¦¥¿¥¤¥× db.net.in Æþ db.net.out ½Ð db.net.inout Æþ½Ð db.net.inets ¥Í¥Ã¥È ############################################################################## # # New circuit dialog box # db.newcirc.directory ¥Ç¥£¥ì¥¯¥È¥ê db.newcirc.cap ¿·µ¬²óÏ© db.newcirc.exp -begin- ¸½ºß¤Î²óÏ©¤ÎÊÔ½¸¤ò ¼­¤á¤Æ¡¢¿·¤·¤¤²óÏ©¤ò ÊÔ½¸¤·»Ï¤á¤ë¡£ -end- db.newcirc.file ¥Õ¥¡¥¤¥ë̾ db.newcirc.topname ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë̾ ############################################################################## # Gate dialog box # db.gate.title ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê db.gate.signam ¥Í¥Ã¥È̾ db.gate.portnam ¥Ý¡¼¥È̾ db.gate.iotype ¥¿¥¤¥× db.gate.bitw ¥Ó¥Ã¥ÈÉý db.gate.cyclew ¥µ¥¤¥¯¥ëÉý db.gate.phase ¥Õ¥§¡¼¥º db.gate.duty ¥Ç¥å¡¼¥Æ¥£¡¼ db.gate.port ¥Ý¡¼¥È db.gate.bitws ¥Ó¥Ã¥È db.gate.side ¥µ¥¤¥É db.gate.gtype ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¦¥¿¥¤¥× db.gate.gname ¥³¥ó¥Ý¡¼¥Í¥ó¥È̾ db.gate.hidenam ̾Á°¤ò±£¤¹ db.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë db.gate.cpbreak ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹Ê¬³äÅÀ db.gate.butstate ¥¹¥¤¥Ã¥Á¾õÂÖ db.gate.dipval DIP¾õÂÖ db.gate.range ¥Ó¥Ã¥ÈÈÏ°Ï db.gate.memfilenam ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë̾ db.gate.modname µ¡Ç½Ì¾ db.gate.general °ìÈÌ db.gate.details ¾ÜºÙ db.gate.text ¥Æ¥­¥¹¥È db.gate.ports ¥Ý¡¼¥È db.gate.delay ÃÙ±ä db.gate.parameters ¥Ñ¥é¥á¥¿ db.gate.stddelay ɸ½à¤ÎÃÙ±ä db.gate.custdelay ¥«¥¹¥¿¥à¤ÎÃÙ±ä db.gate.catdiruse ¥Ý¡¼¥È¤Î°ÌÃÖÉÕ¤± db.gate.edit ÊÔ½¸ db.gate.delete ºï½ü db.gate.add Äɲà db.gate.ff.type ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.ff.normal.hdr ÉáÄÌ db.gate.ff.normal.exp -begin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.ff.reverse.hdr È¿¼Í db.gate.ff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.jkff.type JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.jkff.normal.hdr ÉáÄÌ db.gate.jkff.normal.exp -fillbegin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø¿Ê¤à JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤Ç¤¹¡£ -end- db.gate.jkff.reverse.hdr È¿¼Í db.gate.jkff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø¿Ê¤à JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤Ç¤¹¡£ -end- db.gate.cat.asc.hdr ¾º½ç db.gate.cat.dec.hdr ¹ß½ç db.gate.cat.asc.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¾º½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.dec.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¹ß½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.sigdir ¿®¹æÊý¸þ db.gate.cat.auto.hdr ¼«Æ° db.gate.cat.multin.hdr ¿ÆþÎÏ db.gate.cat.singin.hdr ¿½ÐÎÏ db.gate.cat.tran.hdr Æþ½Ð db.gate.cat.auto.exp -fillbegin- ¿®¹æ¤ÎÊý¸þ¤ò¼«Æ°Åª ¤ËȽÃǤ¹¤ë¡£ -end- db.gate.cat.multin.exp -fillbegin- ¤¤¤Ä¤â¿¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.singin.exp -fillbegin- ¤¤¤Ä¤âñ°Ì¤Î¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.tran.exp -fillbegin- ÁÐÊý¸þ¤Î¿®¹æ¤ÎÅÁÇÅ(tran)¤òµö¤¹¡£¥¹¥¤¥Ã¥Á¤ä¥ì¥¸¥¹¥¿¤Ë¤ÎÀܳ¤ÏÉԲĤǤ¹¡£ -end- db.gate.tab.General.cap °ìÈÌÆÃħ db.gate.tab.Ports.cap ¥Ý¡¼¥ÈÆÃħ db.gate.tab.Delay.cap ÃÙ±äÆÃħ db.gate.tab.Parameters.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.CLOCK.cap ¥¯¥í¥Ã¥¯ÆÃħ db.gate.tab.SWITCH.cap ¥¹¥¤¥Ã¥ÁÆÃħ db.gate.tab.DIP.cap DIPÆÃħ db.gate.tab.TAP.cap TranÆÃħ db.gate.tab.RAM.cap RAMÆÃħ db.gate.tab.ROM.cap ROMÆÃħ db.gate.tab.MODULE.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.FRAME.cap ¥Õ¥ì¡¼¥àÆÃħ db.gate.tab.LED.cap LEDÆÃħ db.gate.tab.AND.cap ANDÆÃħ db.gate.tab.OR.cap ORÆÃħ db.gate.tab.XOR.cap XORÆÃħ db.gate.tab.MUX.cap MuxÆÃħ db.gate.tab.DEMUX.cap DemuxÆÃħ db.gate.tab.DECODER.cap DecoderÆÃħ db.gate.tab.CONCAT.cap ConcatÆÃħ db.gate.tab.COMMENT.cap ¥Æ¥­¥¹¥ÈÆÃħ db.gate.tab.FF.cap ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ db.gate.tab.JKFF.cap JK¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ db.gate.tab.SCRIPT.cap Verilog¥¹¥¯¥ê¥×¥È db.gate.tab.General.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î´ðËÜÆÃħ¤òɽ¼¨¡¢Ëô¤ÏÊÔ½¸¤¹¤ë¡£ -end- db.gate.tab.Ports.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î¥Ý¡¼¥È¤òÄɲá¢ÊÔ½¸¡¢Ëô¤Ïºï½ü¤¹¤ë¡£ -end- db.gate.tab.Delay.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÃÙ±ä¤Ï¥Æ¥¯¥Î¥í¥¸¤Ç¤â¡¢¸Ä¡¹¤Ç¤âÀßÄê²Äǽ¤Ç¤¢¤ë¡£ -end- db.gate.tab.Parameters.exp -fillbegin- ¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤¬ÄêµÁ¤·¤Æ¤¤¤ë¾ì¹ç¡¢¤³¤³¤Ç¤½¤ÎÃͤòÀßÄê½ÐÍè¤ë¡£¥â ¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤ÏÃÙ±äÃÍ¡¢¥³¥ó¥¹¥¿¥ó¥È¤Ê¤É¤ËÍøÍѤµ¤ì¤Æ¤¤¤ë¡£ -end- db.gate.tab.details.exp -fillbegin- ¥³¥ó¥Ý¡¼¥Í¥ó¥È¼¡Âè¤ÎÀßÄê¤ò¹Ô¤¦¡£ -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.JKFF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤òÆþÎϤ¹¤ë¡£¤¢¤ëÄøÅÙ¤Îhtml¤ä¥Ï¥¤¥Ñ¡¼¥ê¥ó¥¯¤Ê¤É¤âÍøÍѽÐÍè¤ë¡£ -end- db.gate.tab.SCRIPT.exp -fillbegin- ¤³¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ËÆþÎϤ¹¤ëVerilog¤Î¥³¡¼¥É¤Ï ¥â¥¸¥å¡¼¥ë¤Î°ìÉô¤Ë¤Ê¤ê¤Þ¤¹¡£ -end- db.gate.mparm.parameter ¥Ñ¥é¥á¥¿ db.gate.mparm.value ÃÍ db.gate.mparm.exampleA -begin- ¤³¤Î¥â¥¸¥å¡¼¥ë¤Ï¥Ñ¥é¥á¥¿¤òÍøÍѤ·¤Æ¤¤¤Ê¤¤¡£ ¥Ñ¥é¥á¥¿¤ÏVerilog¥Æ¥­¥¹¥È¤Î¥â¥¸¥å¡¼¥ë¤Ë ÍøÍѽÐÍè¤ë¡£¤³¤Î¥À¥¤¥¢¥í¥°¤Ç¡¢¤½¤ì¤¾¤ì¤Î ¥Ñ¥é¥á¥¿¤ÎÃͤ¬ÀßÄê½ÐÍè¤ë¡£¥â¥¸¥å¡¼¥ë¤Î ¥Ñ¥é¥á¥¿¤òÍøÍѤ¹¤ë¤¿¤á¡¢¥Æ¥­¥¹¥È¤ÎÄêµÁ¤Ë ¡Ö#¡×¤«¤é»Ï¤Þ¤ë¥Ñ¥é¥á¥¿¤Î¥ê¥¹¥È¤ò½ñ¤¤¤Æ ¤¯¤À¤µ¤¤¡£°Ê²¼¤ÎÎãÂê¤Ç¡¢¥Ç¥Õ¥©¥ë¥È¤ÎÃͤ¬ ¡Ö1'b1¡×¤Î¡Öbase_value¡×¤È¤¤¤¦¥Ñ¥é¥á¥¿¤ò »ý¤Ä¥â¥¸¥å¡¼¥ë¤¬¼¨¤·¤Æ¤¢¤ë¡£ -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder ÆþÎϤνç½ø db.gate.mux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.mux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.mux.ord1.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.ord2.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.select ¥»¥ì¥¯¥¿¤Î²Õ½ê db.gate.mux.sel1.hdr º¸Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel2.hdr ±¦Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel1.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤòº¸Â¦¤Ë¤ª¤¯¡£ -end- db.gate.mux.sel2.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤò±¦Â¦¤Ë¤ª¤¯¡£ -end- db.gate.decoder.dataorder ÆþÎϤνç½ø db.gate.decoder.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.decoder.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.decoder.ord1.exp -fillbegin- DECODER¤ÎÆþÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.decoder.ord2.exp -fillbegin- DECODER¤ÎÆþÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.decoder.select ¥»¥ì¥¯¥¿¤Î²Õ½ê db.gate.decoder.sel1.hdr º¸Â¦¤Î¥»¥ì¥¯¥¿ db.gate.decoder.sel2.hdr ±¦Â¦¤Î¥»¥ì¥¯¥¿ db.gate.decoder.sel1.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤòº¸Â¦¤Ë¤ª¤¯¡£ -end- db.gate.decoder.sel2.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤò±¦Â¦¤Ë¤ª¤¯¡£ -end- db.gate.demux.dataorder ½ÐÎϤνç½ø db.gate.demux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.demux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.demux.ord1.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.ord2.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse ³ÈÄ¥¥Ð¡¼¤òÍøÍÑ db.gate.aox.use.hdr ³ÈÄ¥¥Ð¡¼ db.gate.aox.nouse.hdr ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ·¤Ê¤¤ db.gate.aox.use.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.aox.nouse.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤµ¤ì¤Ê¤¤¡£ -end- db.gate.led.type LED¤Î¥¿¥¤¥× db.gate.led.bit.hdr ¥Ó¥Ã¥È db.gate.led.bar.hdr ¥Ð¡¼¡¦¥°¥é¥Õ db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- °ì¥Ó¥Ã¥È¤Î¿®¹æ¤Î°Ù¤Îñ°Ì¤ÎLED -end- db.gate.led.bar.exp -fillbegin- LED¤Î¥Ð¡¼¡¦¥°¥é¥Õ¡£°ì¥Ó¥Ã¥È¤Ë¤Ä¤­¡¢°ì¤Ä¤Î¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.led.hex.exp -fillbegin- ¿®¹æ¤ò16¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.dec.exp -fillbegin- ¿®¹æ¤ò10¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.seg.exp -fillbegin- ³Æ¥»¥°¥á¥ó¥È¤òÊÌ¡¹¤ËÀ©¸æ¤¹¤ë¡£ -end- db.gate.tap.lbl.bus LSB: db.gate.tap.exp.bus Æɤ߹þ¤à¥Ó¥Ã¥È¡¦¥ì¡¼¥ó¥¸¤ÎºÇ¤â²¼¤Î¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.gate.tap.exp.bit Æɤ߹þ¤à¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.seq.back <Á°¤Ø db.seq.next ¼¡¤Ø> db.hdl.savecap Ê£¿ô¤Î¥â¥¸¥å¡¼¥ë db.hdl.saveexp -fillbegin- ¥Æ¥­¥¹¥È¤Î¥Ð¥Ã¥Õ¥¡¤ËÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬¤¢¤ë¡£±¦Â¦¤Î¥¢¥¯¥·¥ç¥ó¤Î¤¤¤º¤ì¤«¤òÁªÂò¤¹¤Æ¤¯¤À¤µ¤¤¡£ -end- db.hdl.autoedit ¼«Æ°ÊÑ¿ô db.hdl.split ʬΥ db.hdl.comment ¥³¥á¥ó¥È db.hdl.cancel ¥­¥ã¥ó¥»¥ë db.hdl.ignore ̵»ë¤¹¤ë db.hdl.autoeditcap ̾Á°¤¬°ìÅù¤·¤Ê¤¤ db.hdl.autoeditexp -fillbegin- ¥Æ¥­¥¹¥È¤Ç¤Î¥â¥¸¥å¡¼¥ë̾¤È´üÂÔ¤·¤¿Ì¾Á°¤¬°ìÅù¤·¤Ê¤¤¡£±¦Â¦¤Î¥¢¥¯¥·¥ç¥ó¤Î¤¤¤º¤ì¤«¤òÁªÂò¤¹¤Æ¤¯¤À¤µ¤¤¡£ -end- cpath.cloops -fillbegin- ²óÏ©¤ËÁȹ礻¤Î¥ë¡¼¥×¤¬È¯¸«¤µ¤ì¤¿¡£¥¯¥ê¥Æ¥£¥«¥ë ¡¦¥Ñ¥¹¤Î²òÀϤò¹Ô¤Ê¤¤¤¿¤±¤ì¤Ð¡¢¥ë¡¼¥×¾å¤Î¥Í¥Ã¥È ¤òÀڤ俤ꡢ¥ë¡¼¥×¾å¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¡Ö¥¯¥ê¥Æ¥£¥«¥ë¡¦ ¥Ñ¥¹Ê¬³äÅÀ¡×¤Ë¤·¤¿¤ê¤¹¤ëɬÍפ¬¤¢¤ë¡£ -end- ############################################################################## # Print dialog box # print.outto ½ÐÎÏÀè print.printer ¥×¥ê¥ó¥¿¡¼ print.file ¥Õ¥¡¥¤¥ë print.prcmd °õºþ¥³¥Þ¥ó¥É print.prname ¥×¥ê¥ó¥¿ print.advanced ¥ª¥×¥·¥ç¥ó... print.filename ¥Õ¥¡¥¤¥ë̾ print.epssave Encapsulated Postscript¤È¤·¤Æ¥»¡¼¥Ö¤¹¤ë. print.doctit ¥É¥­¥å¥á¥ó¥È¤ÎÂê̾ print.epcm ¥¨¥Ý¥Ã¥¯/cm print.estpg ¥Ú¡¼¥¸¿ô¤Î¸«ÀѤâ¤ê print.all Á´¤Æ print.cur ¸½ºß print.use »ÈÍÑÃæ print.sel »ØÄê print.inclib ¥é¥¤¥Ö¥é¥ê¡¦¥Õ¥¡¥¤¥ë¤â°õºþ print.papsz ¥Ú¡¼¥¸¡¦¥µ¥¤¥º print.orient ¥ª¥ê¥¨¥ó¥Æ¡¼¥·¥ç¥ó print.portrait ½Ä print.landscape ²£ print.2side ξÌÌ°õºþ print.opts ¥ª¥×¥·¥ç¥ó print.scale Â礭¤¤¥â¥¸¥å¡¼¥ë¤ò¥¹¥±¡¼¥ë¤·¤Æ°ì¥Ú¡¼¥¸¤Ç°õºþ¤¹¤ë print.partition Â礭¤¤¥â¥¸¥å¡¼¥ë¤òÊ£¿ô¤Î¥Ú¡¼¥¸¤Ç°õºþ¤¹¤ë print.incidx ¥¤¥ó¥Ç¥Ã¥¯¥¹¤ò´Þ¤à print.incgraph ³¬ÁØ¥°¥é¥Õ¤ò´Þ¤à print.4up ¾®¤µ¤¤¥â¥¸¥å¡¼¥ë¤ò°ìÊǤ˻ͤĤº¤Ä°õºþ¤¹¤ë print.range ¥ì¥ó¥¸ print.scaleselect ÁªÂòÈϰϤò¥¹¥±¡¼¥ë¤¹¤ë print.fulltr Á´Éô print.parttr Éôʬ print.start ¥¹¥¿¡¼¥È print.end ¥¹¥È¥Ã¥× print.filesel ¥Õ¥¡¥¤¥ë¤Ë°õºþ print.printersel ¥×¥ê¥ó¥¿¤Ë°õºþ print.defaultprinter ¥Ç¥Õ¥©¥ë¥È¤Î¥×¥ê¥ó¥¿ print.pageset ¥Ú¡¼¥¸¡¦¥»¥Ã¥È¥¢¥Ã¥× print.modulesel ¥â¥¸¥å¡¼¥ë¤ÎÁªÂò ############################################################################## # # TkGate 2.0 print dialog strings # print.ok °õºþ print.printtrace.cap ¥È¥ì¡¼¥¹¤Î°õºþ print.printcirc.cap ²óÏ©¿Þ¤Î°õºþ print.printcirc.out.exp -begin- ²óÏ©¿Þ¤Î°õºþÀ褬 ¥×¥ê¥ó¥¿¤«¥Õ¥¡¥¤¥ë ¤«ÁªÂò¤¹¤ë¡£ -end- #probably not used print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë ¤ä°õºþ¤ÎÍͻҤòÁªÂò ¤ë¡£ -end- print.printtrace.trace.exp -fillbegin- »þ´Ö¤ÎÈϰϤòÁªÂò¤¹¤ë¡£ Ëô¡¢¥¹¥±¡¼¥ë¤Ë¤è¤Ã¤Æ¡¢ ɬÍפΥڡ¼¥¸¿ô¤òɽ¤« ɾ²Á¤¹¤ë¡£ -end- print.tab.output °õºþÀè print.tab.page °õºþ print.tab.content ÆâÍÆ ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 600 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 115 # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 @opt.sidebar.width *200 @opt.tree.width *150 opt.general °ìÈÌ opt.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ opt.toolbars ¥Ä¡¼¥ë¡¦¥Ð¡¼ opt.toolbars.edit ÊÔ½¸ opt.toolbars.sim ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó opt.toolbars.symed ¥·¥ó¥Ü¥ëÊÔ½¸ opt.editor HDL opt.print °õºþ opt.print.output ½ÐÎÏ opt.print.content ÆâÍÆ opt.simulate ¥·¥ß¥å¥ì¡¼¥È opt.simulate.basic ´ðËÜ opt.simulate.tech ¥Æ¥¯¥Î¥í¥¸¡¼ opt.simulate.error ¥¨¥é¡¼°·¤¤ opt.library ¥é¥¤¥Ö¥é¥ê opt.library.path ¥Ñ¥¹ opt.library.load ¼«Æ°Æɤ߹þ¤ß opt.library.vpd VPD opt.analysis ²òÀÏ opt.color ¿§ opt.color.title TkGate: ¿§¤ÎÁªÂò opt.color.edit ÊÔ½¸ opt.color.scope ¥¹¥³¡¼¥× opt.color.hdl HDL¤ÎÊÔ½¸ opt.html HTML opt.debug ¥Ç¥Ð¥Ã¥° opt.security ¥»¥­¥å¥ê¥Æ¥£ opt.tearawaymenus ¥á¥Ë¥å¡¼¤ÎÀÚ¤ê¼è¤ê¤òÍ­¸ú¤Ë¤¹¤ë¡£ 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¥»¡¼¥Ö¤Ç°ÛÊѤ¬µ¯¤³¤Ã¤Æ¤·¤Þ¤¿¡£²óÏ©¥Ç¡¼¥¿¤ËÌ·½â¤¬¤¢¤ë²ÄǽÀ­¤¬¤¢¤ë¡£ err.yy.pinformat ¡Ö%s¡×¤Ç¥Ô¥ó̾¤Î·Á¼°¤¬Ç§ÄêÉԲĤǤ¹¡£ err.yy.pinname ¥Ô¥ó̾¡Ö%s¡×¤Ï¡Ö%s¡×¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Ç̤ÄêµÁ¤Ç¤¹¡£ err.yy.nonetpos ¥Í¥Ã¥È²Õ½ê¡Ö%d¡×¤Ï¥³¥ó¥Ý¡¼¥Í¥ó¥È¡Ö%s¡×¤Ë¸«ÉÕ¤«¤é¤Ê¤¤¤Ç¤¹¡£ err.yy.baddirective ¥Ç¥£¥ì¥¯¥Æ¥£¥Ö¡Ö%s¡×¤Î·Á¼°¤¬Ç§ÄêÉԲĤǤ¹¡£ err.corruptnewsave -fillbegin- TkGate¤Ï'%s'¤Ë¥»¡¼¥Ö½ÐÍ褿¤¬¡¢¥Õ¥¡¥¤¥ë¤¬º®Í𤵤ì¤Æ¤¤¤ë¤ß¤¿¤¤¡£¤â¤·¥Á¥§¥Ã ¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯ ¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.corruptsave -fillbegin- '%s'¤ò¥»¡¼¥Ö¤·¤è¤¦¤È¤·¤Æ¤¤¤ë»þ¡¢TkGate¤ËÆâÉôÌäÂ꤬ȯ¸«¤·¤¿¡£¸µ¡¹¤Î¥Õ¥¡¥¤ ¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä¤·¤Æ¤¢¤ë¡£º®Í𤵤ì¤Æ¤¤¤ë²ÄǽÀ­¤Î¤¢¤ë¥Õ¥¡¥¤¥ë¤Ï'%s'¤Ë¥»¡¼¥Ö ¤·¤¿¡£¤â¤·¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤ ¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.badsave -fillbegin- '%s'¤ò¥»¡¼¥Ö½ÐÍè¤Ê¤«¤Ã¤¿¡£¥Õ¥¡¥¤¥ë¤Î¥×¥í¥Æ¥¯¥·¥ç¥ó¤ä¶õ¤­¥Ç¥£¥¹¥¯Î̤ò³Îǧ ¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- err.nosafesave -fillbegin- '%s'¤Î°ÂÁ´¥»¡¼¥Ö¤ò¹Ô¤¦¤¿¤á¤Î°ì»þ¤Î¥Õ¥¡¥¤¥ë¤¬ºîÀ®½ÐÍè¤Ê¤«¤Ã¤¿¤«¤é¡¢Ä¾ÀÜ¥»¡¼ ¥Ö¤·¤Ê¤¯¤Æ¤Ï¤Ê¤é¤Ê¤¤¡£¡ÖNO¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¸µ¡¹¤Î¥Õ¥¡¥¤¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä ¤¹¡£¡ÖYES¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¥»¡¼¥Ö¤¹¤ë¤¬¡¢¥»¡¼¥ÖÅÓÃæ¤ËÌäÂ꤬µ¯¤³¤Ã¤¿¤é¡¢ ²óÏ©¥Ç¡¼¥¿¤¬Ç˲õ¤µ¤ì¤ë²ÄǽÀ­¤¬¤¢¤ë¡£Ä¾ÀÜ¥»¡¼¥Ö¤·¤Æ¤ß¤Þ¤·¤ç¤¦¤«¡£ -end- err.noback -fillbegin- TkGate¥Ð¡¼¥¸¥ç¥ó%s¤Çºî¤é¤ì¤¿¥Õ¥¡¥¤¥ë¤Ç¤¢¤ë¡£Êݸ¤¹¤ë¤È¡¢ TkGate¤Î¸Å¤¤¥Ð¡¼¥¸¥ç¥ó¤ËÆɤ߹þ¤á¤Ê¤¤¤³¤È¤¬¤¢¤ë¡Ê¸½ºß¤Î ¥Ð¡¼¥¸¥ç¥ó¤Ï%s¤Ç¤¢¤ë¡Ë¡£ -end- err.viewfile ¥Õ¥¡¥¤¥ë¡Ö%s¡×¤¬³«¤±¤Þ¤»¤ó¡£ err.noinvgate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¦¥¿¥¤¥×¤ËÈÝÄê¥Ð¥Ö¥ë¤¬ÉÕ¤±¤Ê¤¤¡£ ############################################################################## # # Internal error messages (indicating a problem with TkGate) # err.internal.nomod ÆâÉô¥¨¥é¡¼¡§¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬¸«ÉÕ¤«¤ê¤Þ¤»¤ó¡£ ############################################################################## # Informational messages # msg.selwire ¥ï¥¤¥ä¡Ö%s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£ msg.selgate %2$s¤È¤¤¤¦%1$s¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.selblock %2$s¤È¤¤¤¦%1$s¥â¥¸¥å¡¼¥ë¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.iselwire ¥Ö¥í¥Ã¥¯¡Ö%2$s¡×¤Ë¥Ý¡¼¥È¡Ö%1$s¡×¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.iselgate ¡Ö%2$s¡×¤È¤¤¤¦¡Ö%1$s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£(¤¨¤Ã¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ò½Ð¤¹¤Î¤ÏÉÔ²Äǽ¤Î¤Ï¤º¤Ç¤¹¤¬¡£) msg.iselblock ¥â¥¸¥å¡¼¥ë¡¦¥¤¥ó¥¿¥Õ¥§¡¼¥¹¡Ö%s¡×¤¬ÁªÂò¤µ¤ì¤Þ¤·¤¿¡£ msg.modoverwt ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬´û¤ËÄêµÁ¤µ¤ì¤Æ¤¤¤ë¡£ÄêµÁ¤·¤Ê¤ª¤·¤Þ¤¹¤«? msg.foundgate %s¤È¤¤¤¦¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.foundwire %s¤È¤¤¤¦¥ï¥¤¥ä¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.searchagn õº÷¥¹¥È¥ê¥ó¥°¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤«¤Ã¤¿¡£¤â¤¦°ìÅÙ¡Öõº÷¡×¤ò²¡¤¹¤È¡¢Ãµº÷¤·¤Ê¤ª¤¹¡£ msg.sim.chgtoroot ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¤Ï¡¢¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤¬¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤Î¥È¥Ã¥×¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ msg.sim.nogatemod ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¡¢¶ñÂÎŪ¤Ê¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤¬É¬ÍפǤ¢¤ë¡£ msg.setinterface ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ò¥»¥Ã¥È¤·¤¿¡£ msg.needsel ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤òÁª¤ó¤Ç¤¯¤À¤µ¤¤¡£ msg.wroteckpt ¡Ö%s¡×¤Ë¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥È¤ò½ñ¤­¹þ¤ó¤À... msg.save ¡Ö%s¡×¤ËÊݸ¤·¤¿¡£ msg.reallynew ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢¿·¤·¤¤²óÏ©¤ò³«¤­¤Þ¤¹¤«? msg.reallyquit ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢½ªÎ»¤·¤Þ¤¹¤«? msg.notlib ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ï¥é¥¤¥Ö¥é¥ê¡¦¥â¥¸¥å¡¼¥ë¤Ç¤Ï¤Ê¤¤¡£ ############################################################################## # Miles messages (Activated when Miles Bader uses TkGate) # miles.msg1 ¤½¤Î°ÌÃ֤˥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÃÖ¤¯¤Î¤Ï¡¢¤ªÁ°¤ß¤¿¤¤¤ÊÂçÇϼ¯¤·¤«¤¤¤Ê¤¤¤è¡£ miles.msg2 Çϼ¯¡ª miles.msg3 ¶ò¤«¤â¤Î¡ª miles.msg4 ¥Þ¥¤¥ë¥¹¡¢¤½¤Î°ÌÃ֤˥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÃÖ¤¯¤Î¤Ï¡¢Çϼ¯¤À¤è¡£ miles.msg5 Çϼ¯¤Ê¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°ÌÃÖÉÕ¤±¤ò¤ä¤á¤Æ¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg6 ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¤½¤Î°ÌÃ֤ˤª¤¤¤¿¤Î¤Ï¡¢¤ªÁ°¤Î¶ò¤«¤µ¤Î¾ÚÌÀ¤À¤è¡£ miles.msg7 ¤³¤Î¥í¥¯¤Ç¤Ê¤·²óÏ©¤ÎÀ߷פòÄü¤á¤è¡¢¥Þ¥¤¥¹¥ë¡£ miles.msg8a ³¤±¤Æ¤â¡¢ÌµÂ̤À¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg8b ¤ªÁ°¤¬²óÏ©¤òÀß·×½ÐÍè¤Ê¤¤¤È¤¤¤¦¤Î¤Ï¡¢Ã¯¤Ç¤âʬ¤«¤ë¤è¡£ ############################################################################# # # Error messages generated by verga # verga.err.OK ¿´ÇÛ¤·¤Ê¤¤¤Ç¡¢¾Ð¤Ã¤Æ¤¯¤À¤µ¤¤¡£ verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.RAMDCHG ½ñ¤­¹þ¤ß¿®¹æ¤¬Í­¸ú¤Ç¤¢¤ë»þ¡¢¥Ç¡¼¥¿ÆþÎϤÎÊѹ¹¤¬µ¯¤³¤ê¤Þ¤·¤¿¡£ verga.err.RAMACHG ½ñ¤­¹þ¤ß¿®¹æ¤¬Í­¸ú¤Ç¤¢¤ë»þ¡¢¥¢¥É¥ì¥¹ÆþÎϤÎÊѹ¹¤¬µ¯¤³¤ê¤Þ¤·¤¿¡£ verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.NONSTATCTL TODO: Event control @(*) applied to non-statment. verga.err.BADVALUE TODO: Bad numeric value '%s'. verga.err.BADPORTTYPE TODO: Invalid type declaration used on port '%s' verga.err.PATHDCOND TODO: DelaMust set through both # expression and specify block. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. verga.err.NONEXPCTL TODO: Event control @(*) applied to non-expression. verga.err.MODREDEF ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬ºÆÄêµÁ¤µ¤ì¤Þ¤·¤¿¡£ blklst.delete.title TkGate: ¥â¥¸¥å¡¼¥ëºï½ü print.tab.advanced ¥¢¥É¥Ð¥ó¥¹ primitive.err.nomodule ÆâÉô¥¨¥é¡¼: ¥×¥ê¥ß¥Æ¥£¥Ö¡¦¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ç¡¢¥­¡¼¥ï¡¼¥É¡Ömodule¡×¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ db.net.caption ¥Í¥Ã¥È¤ÎÆÃħ blklst.rename.title TkGate: ¥â¥¸¥å¡¼¥ë¤ÎºÆ̾ÉÕ¤± db.gate.switch.state ½é´ü¥¹¥¤¥Ã¥Á¤Î¾õÂÖ db.gate.switch.state.on.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥ó db.gate.switch.state.on.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥ó¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ db.gate.switch.state.off.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥Õ db.gate.switch.state.off.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥Õ¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ db.gate.switch.shownet ¥Í¥Ã¥È̾¤Îɽ¼¨ db.gate.switch.shownet.on.hdr ɽ¼¨ db.gate.switch.shownet.on.exp ¥¹¥¤¥Ã¥Á¤ÎÎ٤˥ͥåÈ̾¤òɽ¼¨¤·¤Þ¤¹¡£ db.gate.switch.shownet.off.hdr ±£¤¹ db.gate.switch.shownet.off.exp ¥¹¥¤¥Ã¥Á¤ÎÎ٤˥ͥåÈ̾¤òɽ¼¨¤·¤Þ¤»¤ó¡£ db.gate.dip.value ½é´ü¤ÎDIP¤ÎÃÍ db.gate.dip.value.hex 16¿Ê¿ô¤ÎÃÍ: db.gate.dip.value.exp ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Îµ¯Æ°¤Î»þ¤ÎDIP¤ÎÃÍ¡£ @db.gate.dip.value.exp.width 150 db.gate.dip.shownet ¥Í¥Ã¥È̾¤Îɽ¼¨ db.gate.dip.shownet.on.hdr ɽ¼¨ db.gate.dip.shownet.on.exp DIP¤ÎÎ٤˥ͥåÈ̾¤òɽ¼¨¤·¤Þ¤¹¡£ db.gate.dip.shownet.off.hdr ±£¤¹ db.gate.dip.shownet.off.exp DIP¤ÎÎ٤˥ͥåÈ̾¤òɽ¼¨¤·¤Þ¤»¤ó¡£ primitive.err.wrongname ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬ÆâÉô¥â¥¸¥å¡¼¥ë̾¤È°ìÅù¤·¤Þ¤»¤ó¡£ db.gate.tap.lbl.bit ¥Ó¥Ã¥È: db.hdl.textdisp.title HDL¤Î¥Æ¥­¥¹¥È¤Î½èÍý db.gate.tap.select ¥Ó¥Ã¥È¡¦¥¿¥Ã¥×¤ÎÁªÂò db.err.neededit -fillbegin- ¥¦¥¡¡¼¥ó¥¤¥ó¥°¤Ë°ÜÆ°¤¹¤ëÁ°¤Ë¡¢ÊÔ½¸¥â¡¼¥É¤ËÀÚÂؤ¨¤ëɬÍפ¬¤¢¤ê¤Þ¤¹¡£ -end- menu.edit.autobold ¼«Æ°ÂÀ»ú @db.gate.tap.exp.width *180 circ.reallyupdate -fillbegin- ËÜÅö¤ËÁ´¤Æ¤Î¡Ö%s¡×¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤ò¹¹¿·¤·¤¿¤¤¤Î¤Ç¤¹¤«¡£ -end- circ.reallyoverwrite -fillbegin- ËÜÅö¤Ë´û¤Ë¸ºß¤·¤Æ¤¤¤ë¥Õ¥¡¥¤¥ë¡Ö%s¡×¤Î¾å¤Ë½ñ¤­¹þ¤ß¤¿¤¤¤Ç¤¹¤«¡£ -end- blklst.copy.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥³¥Ô¡¼ primitive.err.missing ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬È¯¸«½ÐÍè¤Þ¤»¤ó¡£ menu.file.import ²èÁü¥Ç¡¼¥¿¤ò¥¤¥ó¥Ý¡¼¥È db.newcirc.title TkGate: ¿·µ¬²óÏ© opt.tool.simmode ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ä¡¼¥ë blklst.new.title TkGate: ¿·µ¬¥â¥¸¥å¡¼¥ë print.title TkGate: °õºþ print.config.title TkGate: °õºþ¤ÎÀßÄê db.gate.waveform ¥¯¥í¥Ã¥¯¤ÎÇÈ·Á print.incunused »ÈÍѤ·¤Ê¤¤¥â¥¸¥å¡¼¥ë¤â´Þ¤ß¤Þ¤¹¡£ opt.treelabel ¥ª¥×¥·¥ç¥ó menu.symbol ¥·¥ó¥Ü¥ë print.tab.modules ¥â¥¸¥å¡¼¥ë opt.title TkGate: ¥ª¥×¥·¥ç¥ó port.title TkGate: ¥Ý¡¼¥È¤ÎÈùºÙ primitive.err.nomodname ÆâÉô¥¨¥é¡¼:¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤ÎÄêµÁ¤Ë¥â¥¸¥å¡¼¥ë̾¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ blklst.claim.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥¯¥ì¡¼¥à igen.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤Î¼«Æ°ºîÀ® err.yy.badlocale ¥»¡¼¥Ö¡¦¥Õ¥¡¥¤¥ë¤Ë̤ÃΤÎʸ²½·÷¡Ö%s¡×¤¬¤¢¤ê¤Þ¤·¤¿¡£ÊѤï¤ê¤Ë±Ñ¸ì¤Îʸ²½·÷¤¬ÍøÍѤµ¤ì¤Þ¤¹¡£ db.dip.title TkGate: DIP¤ÎÃÍ print.scope.title TkGate: ¥¹¥³¡¼¥×¤Î°õºþ circ.wintitle TkGate: ²óÏ©¤ÎÈùºÙ find.title TkGate: õº÷ menu.file.export ²èÁü¥Ç¡¼¥¿¤Î¥¨¥¯¥¹¥Ý¡¼¤È print.rangeselection ¥ì¡¼¥ó¥¸¤ÎÁªÂò pop.simulate.delprobe ¥Ý¥í¡¼¥Ö¤Îºï½ü print.linelen °ì¹ÔÎó¤Î»þ´Ö db.hdl.namechange.title HDL¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ opt.vlibadd.title TkGate: ¥é¥¤¥Ö¥é¥ê¡¼¤ÎÄɲà blklst.setroot.title TkGate: ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤ÎÀßÄê ############################################################################## # Balloon Help # ho.net.in °ì¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out °ì¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout °ì¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.in2 ¿¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out2 ¿¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout2 ¿¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.wire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.wire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.hwire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.hwire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.reg °ì¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.net.reg2 ¿¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.opt.tool.file ²óÏ©¥Õ¥¡¥¤¥ë¤Î¥»¡¼¥Ö¡¢¥í¡¼¥É¤Ê¤É ho.opt.tool.edit ¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¡¢Ãµº÷¤Ê¤É ho.opt.tool.gateopt ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎŸ³«¤ÈÀ°Îó ho.opt.tool.gateprop ´ðËܤΥ³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÊÔ½¸ ho.opt.tool.undo ¥¢¥ó¥É¥¥¤È¥ê¥É¥¥ ho.opt.tool.zoom ¥º¡¼¥à¡¦¥¤¥ó¤È¥º¡¼¥à¡¦¥¢¥¦¥È ho.opt.tool.mode ÊÔ½¸¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.module ¥â¥¸¥å¡¼¥ëÄêµÁ¤Î¿·µ¬ºîÀ®¡¢ºï½ü¡¢ºÆ̾Á°ÉÕ¤±¤Ê¤É ho.opt.tool.tech ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¥Æ¥¯¥Î¥í¥¸¤ÎÁªÂò ho.opt.tool.simctl ¥·¥ß¥å¥ì¡¼¥¿¤Îµ¯Æ°¡¢½ªÎ»¡¢°ì»þÄä»ß¤Ê¤É ho.opt.tool.simaux ÉÕ°¤Î¥·¥ß¥å¥ì¡¼¥¿¤Î¥³¥Þ¥ó¥É(¥á¥â¥ê¤ÎÆɤ߹þ¤ß¡¢½ñ¤­¹þ¤ß¤Ê¤É) ho.opt.tool.symmode ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.symedit ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¤Ê¤É ho.opt.tool.symport ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ý¡¼¥È¤Î²óž ho.opt.tool.symshift ¥Ó¥Ã¥È¡¦¥Þ¥Ã¥×¤ò¾å²¼º¸±¦¤Î¥·¥Õ¥È ho.opt.tool.symopr ÉÕ°¤Î¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥³¥Þ¥ó¥É ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ¸½ºß¤Î²óÏ©¤ò¾Ã¤·¤Æ¡¢¿·¤·¤¤ ²óÏ©¤òºîÀ®¤¹¤ë¡£ -end- ho.open ²óÏ©¥Õ¥¡¥¤¥ë¤ò³«¤­¤Þ¤¹¡£ ho.save ²óÏ©¥Õ¥¡¥¤¥ë¤òÊݸ¤·¤Þ¤¹¡£ ho.saveas ²óÏ©¥Õ¥¡¥¤¥ë¤ò»ØÄê¤Î¥Õ¥¡¥¤¥ë¤ËÊݸ¤·¤Þ¤¹¡£ ho.print ²óÏ©¥Õ¥¡¥¤¥ë¤ò°õºþ¤¹¤ë ho.library ¥é¥¤¥Ö¥é¥ê¡¦¥Þ¥Í¥¸¥ã¡¼¤ò³«¤­¤Þ¤¹¡£ ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- °ÜÆ°¡¿Àܳ - ¤³¤Î¥Ä¡¼¥ë¤Ç°Ê²¼¤Îµ¡Ç½¤ò¹Ô¤¤¤Þ¤¹¡£ ¿·¤·¤¤¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°ÌÃÖ¤òÀßÄꤹ¤ë¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤òÀܳ¤¹¤ë¡£ ¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤Ç°Ê²¼¤Îµ¡Ç½¤¬»È¤¨¤ë¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥ï¥¤¥ä¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥Ý¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤Î°À­¤òÊÔ½¸¤¹¤ë -end- ho.delgat -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òºï½ü¤¹¤ë -end- ho.cutw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤òÀÚÃǤ¹¤ë -end- ho.inv -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÆþ½ÐÎÏ¤Ë ÈÝÄê¤òÉÕ¤±¤¿¤ê¡¢¾Ã¤·¤¿¤ê¤¹¤ë¡£ -end- ho.bitw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤Î¥Ó¥Ã¥ÈÉý¤ò Êѹ¹¤¹¤ë¡£¥Ó¥Ã¥ÈÉý¤ò±¦²¼¤ÎÆþÎÏ ¥Ü¥Ã¥¯¥¹¤ËÆþÎϤ·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open ÁªÂò¤µ¤ì¤¿¥â¥¸¥å¡¼¥ë¤ò³«¤¯ ho.mod.close ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤òÊĤ¸¤ë ho.mod.new ¥â¥¸¥å¡¼¥ë¤Î¿·µ¬ºîÀ® ho.mod.del ¥â¥¸¥å¡¼¥ë¤Îºï½ü ho.mod.copy ¥â¥¸¥å¡¼¥ë¤ò¥³¥Ô¡¼¤·¤Þ¤¹¡£ ho.mod.rename ¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ ho.mod.claim -begin- ¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë¤ò¥æ¡¼¥¶¤Î¥â¥¸¥å¡¼¥ë¤ËÊѹ¹¤·¤Þ¤¹¡£ -end- ho.mod.setroot -begin- »ØÄê¤Î¥â¥¸¥å¡¼¥ë¤ò¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Ë¤·¤Þ¤¹¡£ -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo ºÇ¶á¹Ô¤Ã¤¿ÊѲ½¤ò¸µÄ̤ê¤Ë¤¹¤ë¡£ ho.redo ¥¢¥ó¥Ç¥©¤·¤¿ÊѲ½¤ò¤ä¤êľ¤¹¡£ ho.tab.edit -begin- ²óÏ©¥Ç¡¼¥¿¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.interface -begin- ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.simulate -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òµ¯Æ°¤·¡¢¥¹¥³¡¼¥×¤Î¥¦¥£¥ó¥É¤ò ³«¤­¡¢¤½¤·¤Æ½é´ü²½¥¹¥¯¥ê¥×¥È¤¬Â¸ºß¤¹¤ë¾ì¹ç¡¢ ¤½¤Î¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.tab.cpath -begin- ²óÏ©¤Î¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹¤òõº÷¤¹¤ë¡£ -end- ho.log -begin- TODO: Log of TkGate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÆ°¤«¤¹¡£Áȹ礻²óÏ©¤Î¾ì¹ç¡¢ ¿®¹æ¤¬ÊѤï¤é¤Ê¤¯¤Ê¤ë»þ¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó ¤Î»þ´Ö¤¬°ì»þÄä»ß¤¹¤ë¡£ -end- ho.simpause -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î°ì»þÄä»ß -end- ho.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¨¥Ý¥Ã¥¯¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simclock -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë ¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simstop -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÄä»ß¤·¤Æ¡¢ ÊÔ½¸¥â¡¼¥É¤ËÌá¤ë¡£ -end- ho.simbreak -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È ¤òÊÔ½¸¤¹¤ë¡£ -end- ho.simexec -begin- ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤òÆɤ߹þ¤à -end- ho.simdump -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤Ë½ñ¤­½Ð¤¹ -end- ho.simview -begin- ¥á¥â¥ê(RAM¤äROM)¤ÎÆâÍƤòɽ¼¨¤·¤¿¤¤¤ê¡¢ Êѹ¹¤·¤¿¤¤¤ê¤·¤Þ¤¹¡£ -end- ho.f.modlist -begin- Æɤ߹þ¤ó¤Ç¤¢¤ë¥â¥¸¥å¡¼¥ë¤Î°ìÍ÷ɽ¡£ ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Î̾Á°¤Ë¡Ö+¡×¤¬ ÉÕ¤¤¤Æ¤¤¤ë¡£¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë ¤Ï³ç¸Ì¤Ë°Ï¤Þ¤ì¤Æ¤¤¤ë¡£ -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Í¥Ã¥È̾¤Î°ìÍ÷ɽ -end- ho.ports -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ý¡¼¥È̾¤Î°ìÍ÷ɽ -end- ho.status.logo -begin- ¸½ºß¤Î¥â¡¼¥É¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£Å´¤Î¥²¡¼¥È ¤Î¾ì¹ç¡¢ÊÔ½¸¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤Î¾ì¹ç¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤¬ Áö¤Ã¤Æ ¤¤¤ë¾ì¹ç¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö¤¬ Æ°¤¤¤Æ¤¤¤ë¡£ -end- ho.status.msg TkGate¤è¤ê¤Î¥á¥Ã¥»¡¼¥¸¤¬¤³¤³¤Ëɽ¼¨¤µ¤ì¤ë¡£ ho.status.block ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥¹ ho.status.file -begin- ¸½ºßÊÔ½¸Ãæ¤Î¥Õ¥¡¥¤¥ë̾¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£ ¡Ö*¡×¤È¤¤¤¦µ­¹æ¤¬¤Ä¤¤¤Æ¤¤¤ë»þ¡¢Êݸ¤·¤Æ ¤¤¤Ê¤¤Êѹ¹ ¤¬¤¢¤ë¡£ -end- ho.print.selall Á´¤Æ¤ÎÆɤ߹þ¤ó¤Ç¤¤¤ë¥â¥¸¥å¡¼¥ë¤ò°õºþ¤¹¤ë¡£ ho.print.selcur ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ho.print.seluse -begin- »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß°õºþ¤¹¤ë¡£ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- °Ê²¼¤Ë¥Þ¡¼¥¯¤·¤Æ¤¤¤ë¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ÇÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤òÁªÂò ½ÐÍè¤ë¡£ -end- ho.print.modlist °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë¤òÁªÂò¤¹¤ë¡£ ho.circuit.discchg -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢Êѹ¹¤¢¤ê¤Î²óÏ©¤ò Êݸ¤·¤Ê¤¤¤ÇÊĤ¸¤ë¤È¤­·Ù¹ð¤·¤Ê¤¤¡£ -end- ho.circuit.extbar -begin- ¿·¤·¤¯ºî¤Ã¤¿´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬3Ëܰʾå¤Î»þ¡¢ ³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.circuit.shownet -begin- ¿·¤·¤¯ºî¤Ã¤¿¥¹¥¤¥Ã¥Á¤äDIP¤Ë¥Í¥Ã¥È̾¤¬ ɽ¼¨¤·¤Þ¤¹¡£ -end- ho.circuit.autostart -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤ËÆþ¤ë¤È¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤¬¤¹¤°¼Â¹Ô¤¹¤ë¡£ -end- ho.circuit.language -begin- ²óÏ©¥Ç¡¼¥¿¤òɽ¼¨¤¹¤ë°Ù¤Î¥Õ¥©¥ó¥È¤ò ÁªÂò¤·¤Æ¤¯¤À¤À¤¤¡£ÆüËܸìn¤Î¾ì¹ç¡¢ ¡Öeuc-jp¡×¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.cmd.bitw -begin- ¥«¡¼¥½¥ë¤ÇÁªÂò¤µ¤ì¤¿¥ï¥¤¥ä¤Ïɽ¼¨ ¤µ¤ì¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤵ¤ì¤ë¡£ -end- ho.edgat.signam -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Ç¤¢¤ë¡£Ì¾Á°¤¬Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.port -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥È̾¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.iolab -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥ÈÊý¸þ¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.bitlab -begin- ÁªÂò¤µ¤ì¤¿¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ó¥Ã¥ÈÉý¤Ç¤¢¤ë¡£Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.cycle °ì¥µ¥¤¥¯¥ë¤Î¥¨¥Ý¥Ã¥¯¿ô ho.edgat.phase ¥¯¥í¥Ã¥¯¤Î¥Õ¥§¡¼¥º¡Ê¥Ñ¡¼¥»¥ó¥È¤ÇÀßÄꤹ¤ë¡Ë ho.edgat.duty ¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë¤Î²¿¥Ñ¡¼¥»¥ó¥È¤¬ÏÀÍý0¤Ç¤¢¤ë¤« ho.edgat.hide -begin- Í­¸ú¤Ë¤¹¤ë¤È¥³¥ó¥Ý¡¼¥Í¥ó¥È̾¤¬É½¼¨¤µ¤ì¤Ê¤¤¡£ -end- ho.edgat.gtype ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¼ïÎà ho.edgat.gname ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î̾Á° ho.edgat.ganchor Í­¸ú¤Ë¤¹¤ë¤È¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤¬°ÜÆ°ÉԲĤˤʤ롣 ho.edgat.gx ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎX°ÌÃÖ ho.edgat.gy ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎY°ÌÃÖ ho.edgat.swstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.dipstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.range ¥Þ¥ë¥Á¥Ó¥Ã¥È¤Î¿®¹æ¤Î¥µ¥Ö¡¦¥ì¥ó¥¸¤Ç¤¢¤ë¡£ ho.edgat.memfile -begin- ¥á¥â¥ê¤Î½é´ü¤ÎÃͤΥե¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¡¢¤³¤Î¥Õ¥¡¥¤¥ë ¤¬Æɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.edgat.func ¥â¥¸¥å¡¼¥ë¤Îµ¡Ç½ ho.edgat.frame ¥Õ¥ì¡¼¥à¤Î¥é¥Ù¥ë ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the TkGate interface. This option will not take effect until restarting TkGate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the TkGate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to TkGate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save TkGate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for TkGate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when TkGate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undo¤Î¥ê¥¹¥È¤ÎŤµ -end- ho.opt.name -begin- TODO: User name to be used on TkGate generated reports such as circuit printouts. -end- ho.opt.site -begin- ²óÏ©¤Ê¤É¤ò°õºþ¤¹¤ë»þ¡¢¤³¤Î¥µ¥¤¥È̾¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.smooth -begin- ¤³¤ÎÀßÄê¤òÍ­¸ú¤Ë¤¹¤ë¤È¡¢²óÏ©¤ò¥¹¥¯¥í¡¼¥ë¤¹¤ë»þ¡¢ ¥Ó¥Ã¥È¥Þ¥Ã¥×¤Î¥³¥Ô¡¼¤òÍøÍѤ·¤Æ¡¢¸úΨ¤è¤¯ ¥¹¥¯¥í¡¼¥ë¤Ç¤­¤ë¡£X¥µ¡¼¥Ð¤ÎÌäÂ꤬¤¢¤ì¤Ð¡¢¤³¤Î ÀßÄê¤ò̵¸ú¤Ë¤¹¤ì¤ÐÎɤ¤¡£ -end- ho.opt.clip -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¦¥¤¥ó¥É¥¦¤ÎÉôʬÎΰè¤Î ºÆÉÁ²è¤ò¹Ô¤Ê¤¦¡£¤½¤¦¤Ç¤Ê¤±¤ì¤Ð¾ï¤Ë Á´Îΰè¤òºÆÉÁ²è¤¹¤ë¡£ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥â¥¸¥å¡¼¥ë¤ò°ÜÆ°¤¹¤ë»þ¡¢ ¥ï¥¤¥ä¤Ê¤É¤Ï¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤òÎ¥¤¹¤Þ¤Ç °ÜÆ°¤·¤Ê¤¤¡£²èÌ̤Îɽ¼¨¤¬ÃÙ¤¤»þ¤ËÊØÍø¤Ç¤¢¤ë¡£ -end- ho.opt.bhelp -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ÎÍͤʡ֥إë¥×¡¦ ¥Ð¥ë¡¼¥ó¡×¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.novice -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢½é¿´¼Ô¥â¡¼¥É¤Ë¤Ê¤ë¡£ ½é¿´¼Ô¥â¡¼¥É¤Ç¤Ï¡¢TkGate¤¬Î©¤Á¾å¤¬¤ë»þ¡¢ ¥Á¥å¡¼¥È¥ê¥¢¥ë¤¬¼«Æ°Åª¤ËÆɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ç¥Ð¥°µ¡Ç½¤¬»È¤¨¤ë¡£ ³«È¯¼Ô°Ê³°¤Ë¡¢¤¢¤Þ¤êÌò¤ËΩ¤¿¤Ê¤¤¡£ -end- ho.opt.ckpt Í­¸ú¤Ë¤¹¤ë¤È¡¢TkGate¤Ï¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤Î¥Õ¥¡¥¤¥ë¤òºî¤ë¡£ ho.opt.ckptfreq ¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤ò²¿¥¯¥ê¥Ã¥¯Ëè¤Ë¹Ô¤Ê¤¦¤« ho.opt.beak -begin- Á´Á³Ìò¤ËΩ¤¿¤Ê¤¤µ¡Ç½¤òÍ­¸ú¤Ë¤¹¤ë¡£¤³¤Îµ¡Ç½¤ò ̵¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥¹¥¤¥Ã¥Á¤Ï¥À¥¤¥¢¥í¥° ¥Ü¥Ã¥¯¥¹¤«¤é¾Ã¤¨¡¢.tkgate-properties¤ò ÊÔ½¸¤·¤Ê¤¤¸Â¤êÌá¤é¤Ê¤¤¡£ -end- ho.opt.miles -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢TkGate¤Ï»þ¡¹¥æ¡¼¥¶¤ò Çϼ¯¤Ë¤·¤¿¤ê¡¢°­¸ý¤ò¸À¤Ã¤¿¤ê¤¹¤ë¡£ -end- ho.opt.bat -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ð¥Ã¥È¥Þ¥ó¤Î¥³¥ó¥Ô¥å¡¼¥¿¤ò À߷פ¹¤ë°Ù¤Ë¡ÖÌò¤Ë¤¿¤Ä¡×µ¡Ç½¤¬»È¤¨¤ë¡£ -end- ho.opt.trek žÁ÷¤·¤í¡¢¥¹¥³¥Ã¥Æ¥£¡ª ho.opt.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¹¥Æ¥Ã¥×¡¦¥³¥Þ¥ó¥É¤Ç ²¿¥¨¥Ý¥Ã¥¯¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¥¹¥Æ¥Ã¥×¡¦ ¥³¥Þ¥ó¥É¤Ç ²¿¥µ¥¤¥¯¥ë¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckover -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤è¤ê¹¹¤Ë²¿¥¨¥Ý¥Ã¥¯ ¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.vpopupdelay -begin- ¥Þ¥¦¥¹¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤«¤é¡¢²¿¥ß¥êÉÃ·Ð¤Ã¤Æ ¤«¤é¿®¹æ¤ÎÃͤ¬É½¼¨¤µ¤ì¤ëÃÙ±ä¤Ç¤¢¤ë¡£ ¤³¤Î Ãٱ䤬û²á¤®¤ë»þ¡¢¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤¬ ǧÃÎ ¤Ç¤­¤Ê¤¯¤Ê¤ëÌäÂ꤬¤¢¤ë¥·¥¹¥Æ¥à¤Ï ¤¢¤ë¡£ ¤³¤ÎÌäÂ꤬µ¯¤³¤é¤Ê¤±¤ì¤Ð¡¢ÃÙ±ä ¤ò¤è¤ê û¤¯¤·¤Æ¤âÎɤ¤¡£ -end- ho.opt.init -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òΩ¤Á¾å¤²¤ë»þ¤Ë ¼«Æ°Åª¤Ë¼Â¹Ô¤¹¤ë¥¹¥¯¥ê¥×¥È¡¦ ¥Õ¥¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckall -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¤É¤Î¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Ç¤âÄä»ß¤¹¤ë¡£ -end- ho.opt.ckspec -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï »ØÄꤷ¤¿¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Î¤ß¤ËÄä»ß¤¹¤ë¡£ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart TkGate to see any user defined keybindings. -end- ho.deftech -begin- ¿·¤·¤¤¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥Æ¥¯¥Î¥í¥¸¡¼¡£ ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÃÙ±ä¤Ë±Æ¶Á¤¹¤ë¡£Ç¤°Õ¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È ¤Î ¥Æ¥¯¥Î¥í¥¸¡¼¤òÊѹ¹¤¹¤ë¤Ë¤Ï¡¢¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ÎÀßÄê ¥Ü¥Ã¥¯¥¹¤ò³«¤¤¤Æ¡¢¡ÖÃÙ±ä¡×¤Î¥¿¥Ö ¤òÁªÂò ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.techbut -begin- »ØÄꤷ¤¿¥Æ¥¯¥Î¥í¥¸¡¼¡¦¥Õ¥¡¥¤¥ë¤«¤é¤Î ÃÙ±äÃͤò ÍøÍѤ¹¤ë¡£¿·¤·¤¤¥Æ¥¯¥Î¥í¥¸¡¼¤ò Äɲ乤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¢ª¡ÖÀßÄê...¡×¢ª ¡Ö¥·¥ß¥å¥ì¡¼¥È¡× ¤Î¥á¥Ë¥å¡¼¤ò³«¤¤¤Æ¡¢ ¥Õ¥¡¥¤¥ë¤Î¥ê¥¹¥È¤ËÄɲà ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.custbut -begin- ¤³¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥ÈÀìÍѤÎÃÙ±äÃͤò»ØÄꤹ¤ë¡£ -end- ho.contver -begin- ¥Þ¥¦¥¹Áàºî¤ò¹Ô¤Ê¤¦»þ¡¢ÆâÉô¹½Â¤¤ò¼«Æ°Åª¤Ë ³Îǧ¤·¤Æ¡¢ÉÔÀµ¤Î½ê¤òÃΤ餹¡£ -end- ho.simwatch -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ÈGUI¤Î´Ö¤Î¥³¥Þ¥ó¥É¤òɽ¼¨¤¹¤ë¡£ -end- ho.modtree -begin- ³¬Áإĥ꡼¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.modlist -begin- °ìÍ÷ɽ¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- ¸½ºß¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È²óž¤òɽ¼¨¤·¤Æ¤¤¤Þ¤¹¡£ ¾°¡¢¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥Ç¥Õ¥©¥ë¥È²óž¤òÊѹ¹¤·¤Þ¤¹¡£ -end- ho.tool.zoomin ¥º¡¼¥à¡¦¥¤¥ó ho.tool.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È ho.tool.rotate ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÈó»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.brotate ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.valgn ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò½Ä¤Ë°ìÎó¤Ëʤ֡£ ho.tool.halgn ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÍâ¤Ë°ìÎó¤Ëʤ֡£ ho.tool.cut ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥«¥Ã¥È¤¹¤ë¡£ ho.tool.copy ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥³¥Ô¡¼¤¹¤ë¡£ ho.tool.paste ¥«¥Ã¥È¥Ð¥Ã¥Õ¥¡¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÄ¥¤êÉÕ¤±¤ë¡£ ho.tool.find ¥³¥ó¥Ý¡¼¥Í¥ó¥È¡¢¥ï¥¤¥ä¡¢¥Æ¥­¥¹¥È¤Ê¤É¤òõº÷¤¹¤ë¡£ ho.tool.addport ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤Ë¥Ý¡¼¥È¤òÄɲ乤롣 ho.tool.anchor ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°ÉԲĤˤ¹¤ë¡£ ho.tool.unanchor ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤ò°ÜÆ°²Äǽ¤Ë¤¹¤ë¡£ ho.tool.replicate ¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òÊ£À½¤¹¤ë¡£ ho.tool.delete ÁªÂò¤Î¥³¥ó¥Ý¡¼¥Í¥ó¥È¤òºï½ü¤¹¤ë¡£ ho.opt.tearawaymenus -begin- TODO: If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.ipanel.deleteport -begin- TODO: Delete the selected port. -end- ho.ipanel.updateall -begin- TODO: Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.circuit.title -begin- TODO: Description of your circuit. This title is used on printed output. -end- ho.ipanel.generate -begin- TODO: Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.simmove -begin- TODO: Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.opt.sim.savetraces -begin- TODO: Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.ipanel.editport -begin- TODO: Edit the selected port. You can also double-click to edit a field in a port. -end- ho.symed.export TODO: Export image to file. ho.setsel.ltor TODO: Move highlighted items to selected list. ho.print.timegraph -begin- TODO: The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.setsel.allr TODO: Move all items to selected list. ho.circuit.encoding -begin- TODO: Use this encoding for save files. -end- ho.opt.tool.simmode TODO: Choose between the select and scroll tool in simulator. ho.setsel.alll TODO: Move all items to unselected list. ho.circuit.ver -begin- TODO: This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.file -begin- TODO: This is the file name from which the current circuit was loaded. -end- ho.scroll -begin- TODO: Scroll - Grab and drag the editing canvas. -end- ho.symed.import TODO: Import image from file. ho.ipanel.select -begin- TODO: Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- TODO: Add a port to the module. You can also double-click after the last item to add port. -end- ho.setsel.rtol TODO: Move highlighted items to unselected list. tkgate-2.0-b10/locale/ja/messages.bak000644 001751 001751 00000237425 11134010127 020130 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed Jan 14 22:12:00 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # \font-encoding iso8859-1 \messages-encoding euc-jp \verilog-encoding euc-jp \display-encoding euc-jp \language Japanese ############################################################################## # # basic strings # b.new ¿·µ¬... b.dismiss ÊĤ¸¤ë b.close ÊĤ¸¤ë b.ok £Ï£Ë b.clear ¥¯¥ê¥¢ b.cancel ¥­¥ã¥ó¥»¥ë b.open ³«¤¯ b.bitw ¥Ó¥Ã¥ÈÉý b.in Æþ b.out ½Ð b.inout Æþ½Ð b.browse ÁªÂò... b.label ̾Á° b.find õº÷ b.edit ÊÔ½¸... b.add ÄɲÃ... b.delete ºï½ü b.deleteb ºï½ü... b.remove ¾Ã¤¹ b.apply ¥»¥Ã¥È b.anchor °ÜÆ°ÉÔ²Ä b.tech ¥Æ¥¯¥Î¥í¥¸¡¼ b.enable ²Äǽ¤Ë¤¹¤ë b.disable ̵ǽ¤Ë¤¹¤ë b.flush ¥¯¥ê¥¢ ############################################################################## # # Main tab strings # tab.edit ÊÔ½¸ tab.editintr ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ tab.simulate ¥·¥ß¥å¥ì¡¼¥È tab.cpath ÃÙ±ä²òÀÏ # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add ÄɲÃ... mm.delete ºï½ü mm.edit ÊÔ½¸... mm.enable Í­¸ú¤Ë¤¹¤ë mm.disable ̵¸ú¤Ë¤¹¤ë ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ¥Õ¥¡¥¤¥ë menu.edit ÊÔ½¸ menu.tool ¥Ä¡¼¥ë menu.simulate ¥·¥ß¥å¥ì¡¼¥È menu.module ¥â¥¸¥å¡¼¥ë menu.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.format ¥²¡¼¥È menu.make ºîÀ® menu.help ¥Ø¥ë¥× menu.file.new ¿·µ¬ºîÀ® menu.file.open ³«¤¯... menu.file.openlib ¥é¥¤¥Ö¥é¥ê¤ò³«¤¯... menu.file.save Êݸ menu.file.saveas ̾Á°¤òÉÕ¤±¤ÆÊݸ... menu.file.print °õºþ... menu.file.options ÀßÄê... menu.file.quit ½ªÎ» menu.file.cprop ²óÏ©¤ÎÆÃħ... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut ¥«¥Ã¥È menu.edit.copy ¥³¥Ô¡¼ menu.edit.paste ¥Ú¡¼¥¹¥È menu.edit.overlay OverlayÄ¥¤êÉÕ¤± menu.edit.selall Á´¤Æ¤òÁªÂò menu.edit.find ²óÏ©¤òõº÷... menu.edit.algnv ½Ä¤Î°ìÎó menu.edit.algnh ²£¤Î¡¼Îó menu.format.rot.rotate ²óž menu.edit.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.edit.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.edit.rshift ±¦¥·¥Õ¥È menu.edit.lshift º¸¥·¥Õ¥È menu.edit.ushift ¾å¥·¥Õ¥È menu.edit.dshift ²¼¥·¥Õ¥È menu.edit.cwrotate »þ·×¼þ¤ê²óž menu.edit.ccwrotate »þ·×È¿Âмþ¤ê²óž menu.edit.pcwrotate ¥Ý¡¼¥È¤Î»þ·×¼þ¤ê²óž menu.edit.pccwrotate ¥Ý¡¼¥È¤ÎÈó»þ·×¼þ¤ê²óž #menu.edit.autobold ÂÀ»ú²½ menu.edit.resize ºÆ¥µ¥¤¥º²½ menu.tool.move °ÜÆ°¡¿Àܳ menu.tool.delg ¥²¡¼¥È¤Îºï½ü menu.tool.cutw ¥ï¥¤¥ä¤ÎÀÚÃÇ menu.tool.inv ÈÝÄê menu.tool.bitw ¥Ó¥Ã¥ÈÉý menu.tool.debug ¥Ç¥Ð¥Ã¥° menu.tool.point ¥Ý¥¤¥ó¥È menu.tool.line ¥é¥¤¥ó menu.tool.rect ĹÊý·Á menu.tool.fillrect ¿§¤Å¤±Ä¹Êý·Á menu.tool.port ¥Ý¡¼¥È menu.tool.select ÌÈÀÕÁªÂò menu.format.rot.0 0ÅÙ²óž menu.format.rot.90 90ÅÙ²óž menu.format.rot.180 180ÅÙ²óž menu.format.rot.270 270ÅÙ²óž menu.tool.tclshell 0:Tcl Shell menu.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï menu.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» menu.simulate.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.simulate.run ¥é¥ó menu.simulate.pause °ì»þ¥¹¥È¥Ã¥× menu.simulate.step ¥¹¥Æ¥Ã¥×(¥¨¥Ý¥Ã¥¯) menu.simulate.cycle ¥¹¥Æ¥Ã¥×(¥µ¥¤¥¯¥ë) menu.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤ÎÀßÄê... menu.simulate.script ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô... menu.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.simulate.dump ¥á¥â¥ê¤Î½ñ¤­½Ð¤·... menu.module.open ³«¤¯ menu.module.close ÊĤ¸¤ë menu.module.new ¿·µ¬ºîÀ®... menu.module.del ºï½ü... menu.module.copy ¥³¥Ô¡¼... menu.module.rename ̾Á°¤ÎÊÔ½¸... menu.module.claim ¼èÆÀ... menu.module.setroot ¥ë¡¼¥È¤Ë¤¹¤ë... menu.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÀßÄê... menu.module.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.module.interface.set ¥»¥Ã¥È menu.module.interface.edit ÊÔ½¸ menu.module.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë menu.module.interface.auto ¼«Æ°ºîÀ®... menu.format.addport ¥Ý¡¼¥ÈÄɲà menu.format.ioset ¥¿¥¤¥×»ØÄê menu.format.anchor ÁªÂò¤ò°ÜÆ°ÉԲĤˤ¹¤ë menu.format.unanchor ÁªÂò¤ò°ÜÆ°²Ä¤Ë¤¹¤ë menu.format.prop ¥²¡¼¥È¤ÎÀßÄê... menu.tool.rep Ê£À½ menu.format.del ºï½ü menu.format.settech ¥Æ¥¯¥Î¥í¥¸¡¼¤ÎÀßÄê menu.help.about tkgate¤Ë¤Ä¤¤¤Æ... menu.help.license ¥é¥¤¥»¥ó¥¹... menu.help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... menu.help.tut ¥Á¥å¡¼¥È¥ê¥¢¥ë menu.help.home ¥Û¡¼¥à¡¦¥Ú¡¼¥¸ menu.help.example ²óÏ©¤ÎÎã ############################################################################# # Scope Menu # menu.scope_file ¥Õ¥¡¥¤¥ë menu.scope_sim ¥·¥ß¥å¥ì¡¼¥È menu.scope_trace ¥È¥ì¡¼¥¹ menu.scope_help ¥Ø¥ë¥× menu.scope_file.ptrace ¥È¥ì¡¼¥¹°õºþ... menu.scope_file.close ÊĤ¸¤ë menu.scope_trace.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.scope_trace.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.scope_sim.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.scope_sim.run »þ¸ú menu.scope_sim.pause °ì»þÄä»ß menu.scope_sim.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... menu.scope_sim.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... menu.scope_sim.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.scope_sim.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... menu.scope_help.about tkgate¤ËÉÕ¤¤¤Æ... menu.scope_help.license ¥é¥¤¥»¥ó¥¹... menu.scope_help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... mod.intf ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ port.parms ¥Ý¡¼¥È¤Î¥Ñ¥é¥á¥¿ port.in Æþ port.out ½Ð port.inout Æþ½Ð ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ¥²¡¼¥È gm.rgate ñ¹à½ÌÌ󥲡¼¥È gm.msi MSI gm.alu ALU gm.mem ¥á¥â¥ê¡¼ gm.mod ¥â¥¸¥å¡¼¥ë gm.comment ¥³¥á¥ó¥È gm.frame ¥Õ¥ì¡¼¥à gm.io.switch ¥¹¥¤¥Ã¥Á gm.io.dip DIP¥¹¥¤¥Ã¥Á gm.io.ground ¥¢¡¼¥¹ gm.io.vdd Vdd gm.io.merge ¥ï¥¤¥ä¤Î¥Þ¡¼¥¸ gm.io.clock ¥¯¥í¥Ã¥¯ gm.io.led LED¥Ó¥Ã¥È gm.io.ledbar LEDËÀ¥°¥é¥Õ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ¥Ð¥Ã¥Õ¥¡ gm.gate.inv ÈÝÄê¥Ð¥Ã¥Õ¥¡ gm.gate.tribuf ¥È¥é¥¤¡¦¥Ð¥Ã¥Õ¥¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and ñ¹à½ÌÌóAND gm.rgate.nand ñ¹à½ÌÌóNAND gm.rgate.or ñ¹à½ÌÌóOR gm.rgate.nor ñ¹à½ÌÌóNOR gm.rgate.xor ñ¹à½ÌÌóXOR gm.rgate.xnor ñ¹à½ÌÌóXNOR gm.alu.add ²Ã»»´ï gm.alu.mult ¾è»»´ï gm.alu.div ½ü»»´ï gm.alu.lshift º¸¥·¥Õ¥È gm.alu.rshift ±¦¥·¥Õ¥È gm.alu.arshift »»¿ôŪ±¦¥·¥Õ¥È gm.alu.roll ¥í¡¼¥ë gm.mem.reg ¥ì¥¸¥¹¥¿ gm.mem.ff ¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rff ¶ÀÁü¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.41mux 4-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.81mux 8-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.12dec 1-2 ¥Ç¥³¡¼¥À gm.msi.14dec 1-4 ¥Ç¥³¡¼¥À gm.msi.18dec 1-8 ¥Ç¥³¡¼¥À gm.mod.inst ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹ gm.mod.in ¥â¥¸¥å¡¼¥ë¤ÎÆþÎÏ gm.mod.out ¥â¥¸¥å¡¼¥ë¤Î½ÐÎÏ gm.mod.inout ¥â¥¸¥å¡¼¥ë¤ÎÆþ½ÐÎÏ tutorial.prev Á°¤Ø tutorial.next ¼¡¤Ø tutorial.chapter ¾Ï¤Î°ìÍ÷ɽ tutorial.reload ºÆÆɤ߹þ¤ß ############################################################################## # # Popup menus # pop.make ºîÀ® pop.tool ¥Ä¡¼¥ë pop.edit.paste ¥Ú¡¼¥¹¥È pop.edit.cut ¥«¥Ã¥È pop.edit.copy ¥³¥Ô¡¼ pop.port.in Æþ pop.port.out ½Ð pop.port.inout Æþ½Ð pop.wire.addseg ¥ï¥¤¥ä¤ÎÄɲà pop.wire.prop ¥Í¥Ã¥È¤ÎÆÃħ... pop.wire.hidesize ¥Ó¥Ã¥ÈÉý¤ò±£¤¹ pop.wire.showsize ¥Ó¥Ã¥ÈÉý¤ò¼¨¤¹ pop.wire.hidelabel ¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.hidealllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.clearalllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò¥¯¥ê¥¢ pop.wire.showlabel ¥ì¡¼¥Ù¥ë¤ò¼¨¤¹ pop.gate.open ³«¤¯ pop.gate.close ÊĤ¸¤ë pop.gate.prop ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÆÃħ... pop.gate.addport ¥Ý¡¼¥È¤ÎÄɲà pop.gate.addin ÆþÎϤÎÄɲÃ... pop.gate.addout ½ÐÎϤÎÄɲÃ... pop.gate.addinout Æþ½ÐÎϤÎÄɲÃ... pop.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë pop.gate.settech ¥Æ¥¯¥Î¥í¥¸»ØÄê pop.gate.delete ºï½ü pop.gate.ioset ¥¿¥¤¥×¤Î»ØÄê pop.module.new ¿·µ¬... pop.module.del ºï½ü... pop.module.copy ¥³¥Ô¡¼... pop.module.rename ̾Á°¤ÎÊѹ¹... pop.module.claim ¥â¥¸¥å¡¼¥ë¤Î¼èÆÀ pop.module.setroot ¥ë¡¼¥È»ØÄê... pop.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÆÃħ... pop.module.int ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸... pop.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» pop.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï pop.simulate.addprobe ¥×¥í¡¼¥Ö¤òÄɲῺï½ü pop.simulate.run »þ¸ú pop.simulate.pause °ì»þÄä»ß pop.simulate.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× pop.simulate.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× pop.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... pop.simulate.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... pop.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... pop.simulate.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... pop.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ pop.interface.set »ØÄê pop.interface.edit ÊÔ½¸... pop.interface.replace ¼è¤ê´¹¤¨ pop.interface.update ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.updateall Á´¤Æ¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë pop.interface.auto ¼«Æ°ºîÀ®... pop.igen.type ¥¿¥¤¥× pop.igen.side ¥µ¥¤¥É pop.igen.size ¥µ¥¤¥º pop.igen.delete ºï½ü pop.igen.in Æþ pop.igen.out ½Ð pop.igen.inout Æþ½Ð pop.igen.left º¸ pop.igen.right ±¦ pop.igen.top ¾å pop.igen.bottom ²¼ pop.igen.other ¾ ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit ÊÔ½¸ #symed.edit.cut ¥«¥Ã¥È #symed.edit.copy ¥³¥Ô¡¼ #symed.edit.paste ¥Ú¡¼¥¹¥È #symed.edit.overlay Overlay¥Ú¡¼¥¹¥È #symed.edit.rclock »þ·×¼þ¤ê²óž #symed.edit.rcclock Èó»þ·×¼þ¤ê²óž #symed.module ¥â¥¸¥å¡¼¥ë #symed.modes ¥â¡¼¥É #symed.cutpaste ¥«¥Ã¥È¡¿¥Ú¡¼¥¹¥È #symed.rotate ¥Ý¡¼¥È¤Î²óž #symed.zoom ¥º¡¼¥à #symed.update Update symed.cancel ¥­¥ã¥ó¥»¥ë symed.tab.normal È󥻥쥯¥È symed.tab.select ¥»¥ì¥¯¥È symed.link ¥»¥ì¥¯¥È¤ÈÈ󥻥쥯¥È¤òƱ»þ¤ËÊÔ½¸¤¹¤ë¡£ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg ¥ï¥¤¥ä¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥×¥í¡¼¥Ö¤ËÉÕ¤±¤Ã¤Æ¤¯¤À¤µ¤¤¡£ comment.empty [¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Æ¥­¥¹¥È¤òÊÔ½¸¤·¤Æ¤¯¤À¤µ¤¤¡£] ############################################################################## # Interface strings # ifile ¥Õ¥¡¥¤¥ë imodule ¥â¥¸¥å¡¼¥ë iblmodule ¥â¥¸¥å¡¼¥ë: iports ¥Ý¡¼¥È: ibits ¥Ó¥Ã¥ÈÉý: itype ¥¿¥¤¥×: ############################################################################# # Module Dialog Box # db.mod.name ¥â¥¸¥å¡¼¥ë̾ db.mod.file ¥Õ¥¡¥¤¥ë̾ db.mod.type ¥¿¥¤¥× db.mod.flags ¥Õ¥é¥° db.mod.dataprot ¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.intfprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.edprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÀìÍÑ¥¨¥Ç¥£¥¿¤Ë¸Â¤ë¡£ db.mod.props ÆÃħ db.mod.netlist ¥Í¥Ã¥È¥ê¥¹¥È db.mod.hdl HDL # # These are probably not used anymore. Lets leave them as is. # db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netexpl -begin- ¥°¥é¥Õ¥£¥«¥ë¤Î¥¨¥Ç¥£¥¿¤ò ÍøÍѤ·¤Æ¡¢¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤ò ÄêµÁ¤¹¤ë¡£ -end- db.mod.hdlexpl -begin- Verilog¤Î¥Æ¥­¥¹¥È¤òÍøÍѤ·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤òÄêµÁ¤¹¤ë¡£ -end- ############################################################################# # Error List Dialog box # db.err.caption ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.explain -begin- ²óÏ©¤Ë¥¨¥é¡¼¤¬È¯¸«¤µ¤ì¤¿¤Î¤Ç¡¢¥·¥ß¥å¥ì¡¼¥¿¤ò³«»Ï ½ÐÍè¤Ê¤«¤Ã¤¿¡£°Ê²¼¤Î¥ê¥¹¥È¤ÎÃ椫¤é¡¢¥¨¥é¡¼¤òÁªÂò ¤·¤Æ¡¢¥¨¥é¡¼¤Î¾ì½ê¤Ë°ÜÆ°¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: ¥Í¥Ã¥È¤ÎÈùºÙ db.net.name ¥Í¥Ã¥È̾ db.net.hide ¥Í¥Ã¥È̾¤ò±£¤¹ db.net.bits ¥Ó¥Ã¥ÈÉý db.net.type ¥Í¥Ã¥È¡¦¥¿¥¤¥× db.net.port ¥Ý¡¼¥È¡¦¥¿¥¤¥× db.net.in Æþ db.net.out ½Ð db.net.inout Æþ½Ð db.net.inets ¥Í¥Ã¥È ############################################################################## # # New circuit dialog box # db.newcirc.directory ¥Ç¥£¥ì¥¯¥È¥ê db.newcirc.cap ¿·µ¬²óÏ© db.newcirc.exp -begin- ¸½ºß¤Î²óÏ©¤ÎÊÔ½¸¤ò ¼­¤á¤Æ¡¢¿·¤·¤¤²óÏ©¤ò ÊÔ½¸¤·»Ï¤á¤ë¡£ -end- db.newcirc.file ¥Õ¥¡¥¤¥ë̾ db.newcirc.topname ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë̾ ############################################################################## # Gate dialog box # db.gate.title ¥²¡¼¥È¤ÎÀßÄê db.gate.signam ¥Í¥Ã¥È̾ db.gate.portnam ¥Ý¡¼¥È̾ db.gate.iotype ¥¿¥¤¥× db.gate.bitw ¥Ó¥Ã¥ÈÉý db.gate.cyclew ¥µ¥¤¥¯¥ëÉý db.gate.phase ¥Õ¥§¡¼¥º db.gate.duty ¥Ç¥å¡¼¥Æ¥£¡¼ db.gate.port ¥Ý¡¼¥È db.gate.bitws ¥Ó¥Ã¥È db.gate.side ¥µ¥¤¥É db.gate.gtype ¥²¡¼¥È¡¦¥¿¥¤¥× db.gate.gname ¥²¡¼¥È̾ db.gate.hidenam ̾Á°¤ò±£¤¹ db.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë db.gate.cpbreak ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹Ê¬³äÅÀ db.gate.butstate ¥¹¥¤¥Ã¥Á¾õÂÖ db.gate.dipval DIP¾õÂÖ db.gate.range ¥Ó¥Ã¥ÈÈÏ°Ï db.gate.memfilenam ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë̾ db.gate.modname µ¡Ç½Ì¾ db.gate.general °ìÈÌ db.gate.details ¾ÜºÙ db.gate.text ¥Æ¥­¥¹¥È db.gate.ports ¥Ý¡¼¥È db.gate.delay ÃÙ±ä db.gate.parameters ¥Ñ¥é¥á¥¿ db.gate.stddelay ɸ½à¤ÎÃÙ±ä db.gate.custdelay ¥«¥¹¥¿¥à¤ÎÃÙ±ä db.gate.catdiruse ¥Ý¡¼¥È¤Î°ÌÃÖÉÕ¤± db.gate.edit ÊÔ½¸ db.gate.delete ºï½ü db.gate.add Äɲà db.gate.ff.type ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.ff.normal.hdr ÉáÄÌ db.gate.ff.normal.exp -begin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.ff.reverse.hdr È¿¼Í db.gate.ff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.cat.asc.hdr ¾º½ç db.gate.cat.dec.hdr ¹ß½ç db.gate.cat.asc.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¾º½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.dec.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¹ß½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.sigdir ¿®¹æÊý¸þ db.gate.cat.auto.hdr ¼«Æ° db.gate.cat.multin.hdr ¿ÆþÎÏ db.gate.cat.singin.hdr ¿½ÐÎÏ db.gate.cat.tran.hdr Æþ½Ð db.gate.cat.auto.exp -fillbegin- ¿®¹æ¤ÎÊý¸þ¤ò¼«Æ°Åª ¤ËȽÃǤ¹¤ë¡£ -end- db.gate.cat.multin.exp -fillbegin- ¤¤¤Ä¤â¿¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.singin.exp -fillbegin- ¤¤¤Ä¤âñ°Ì¤Î¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.tran.exp -fillbegin- ÁÐÊý¸þ¤Î¿®¹æ¤ÎÅÁÇÅ(tran)¤òµö¤¹¡£¥¹¥¤¥Ã¥Á¤ä¥ì¥¸¥¹¥¿¤Ë¤ÎÀܳ¤ÏÉԲĤǤ¹¡£ -end- db.gate.tab.General.cap °ìÈÌÆÃħ db.gate.tab.Ports.cap ¥Ý¡¼¥ÈÆÃħ db.gate.tab.Delay.cap ÃÙ±äÆÃħ db.gate.tab.Parameters.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.CLOCK.cap ¥¯¥í¥Ã¥¯ÆÃħ db.gate.tab.SWITCH.cap ¥¹¥¤¥Ã¥ÁÆÃħ db.gate.tab.DIP.cap DIPÆÃħ db.gate.tab.TAP.cap TranÆÃħ db.gate.tab.RAM.cap RAMÆÃħ db.gate.tab.ROM.cap ROMÆÃħ db.gate.tab.MODULE.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.FRAME.cap ¥Õ¥ì¡¼¥àÆÃħ db.gate.tab.LED.cap LEDÆÃħ db.gate.tab.AND.cap ANDÆÃħ db.gate.tab.OR.cap ORÆÃħ db.gate.tab.XOR.cap XORÆÃħ db.gate.tab.MUX.cap MuxÆÃħ db.gate.tab.DEMUX.cap DemuxÆÃħ db.gate.tab.CONCAT.cap ConcatÆÃħ db.gate.tab.COMMENT.cap ¥Æ¥­¥¹¥ÈÆÃħ db.gate.tab.FF.cap ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ db.gate.tab.General.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î´ðËÜÆÃħ¤òɽ¼¨¡¢Ëô¤ÏÊÔ½¸¤¹¤ë¡£ -end- db.gate.tab.Ports.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤Î¥Ý¡¼¥È¤òÄɲá¢ÊÔ½¸¡¢Ëô¤Ïºï½ü¤¹¤ë¡£ -end- db.gate.tab.Delay.exp -fillbegin- ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÃÙ±ä¤Ï¥Æ¥¯¥Î¥í¥¸¤Ç¤â¡¢¸Ä¡¹¤Ç¤âÀßÄê²Äǽ¤Ç¤¢¤ë¡£ -end- db.gate.tab.Parameters.exp -fillbegin- ¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤¬ÄêµÁ¤·¤Æ¤¤¤ë¾ì¹ç¡¢¤³¤³¤Ç¤½¤ÎÃͤòÀßÄê½ÐÍè¤ë¡£¥â ¥¸¥å¡¼¥ë¤Î¥Ñ¥é¥á¥¿¡¼¤ÏÃÙ±äÃÍ¡¢¥³¥ó¥¹¥¿¥ó¥È¤Ê¤É¤ËÍøÍѤµ¤ì¤Æ¤¤¤ë¡£ -end- db.gate.tab.details.exp -fillbegin- ¥²¡¼¥È¼¡Âè¤ÎÀßÄê¤ò¹Ô¤¦¡£ -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤òÆþÎϤ¹¤ë¡£¤¢¤ëÄøÅÙ¤Îhtml¤ä¥Ï¥¤¥Ñ¡¼¥ê¥ó¥¯¤Ê¤É¤âÍøÍѽÐÍè¤ë¡£ -end- db.gate.mparm.parameter ¥Ñ¥é¥á¥¿ db.gate.mparm.value ÃÍ db.gate.mparm.exampleA -begin- ¤³¤Î¥â¥¸¥å¡¼¥ë¤Ï¥Ñ¥é¥á¥¿¤òÍøÍѤ·¤Æ¤¤¤Ê¤¤¡£ ¥Ñ¥é¥á¥¿¤ÏVerilog¥Æ¥­¥¹¥È¤Î¥â¥¸¥å¡¼¥ë¤Ë ÍøÍѽÐÍè¤ë¡£¤³¤Î¥À¥¤¥¢¥í¥°¤Ç¡¢¤½¤ì¤¾¤ì¤Î ¥Ñ¥é¥á¥¿¤ÎÃͤ¬ÀßÄê½ÐÍè¤ë¡£¥â¥¸¥å¡¼¥ë¤Î ¥Ñ¥é¥á¥¿¤òÍøÍѤ¹¤ë¤¿¤á¡¢¥Æ¥­¥¹¥È¤ÎÄêµÁ¤Ë ¡Ö#¡×¤«¤é»Ï¤Þ¤ë¥Ñ¥é¥á¥¿¤Î¥ê¥¹¥È¤ò½ñ¤¤¤Æ ¤¯¤À¤µ¤¤¡£°Ê²¼¤ÎÎãÂê¤Ç¡¢¥Ç¥Õ¥©¥ë¥È¤ÎÃͤ¬ ¡Ö1'b1¡×¤Î¡Öbase_value¡×¤È¤¤¤¦¥Ñ¥é¥á¥¿¤ò »ý¤Ä¥â¥¸¥å¡¼¥ë¤¬¼¨¤·¤Æ¤¢¤ë¡£ -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder ÆþÎϤνç½ø db.gate.mux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.mux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.mux.ord1.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.ord2.exp -fillbegin- MUX¤ÎÆþÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.dataorder ½ÐÎϤνç½ø db.gate.demux.ord1.hdr º¸¤«¤é±¦¤Ø db.gate.demux.ord2.hdr ±¦¤«¤éº¸¤Ø db.gate.demux.ord1.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤òº¸¤«¤é±¦¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.demux.ord2.exp -begin- DEMUX¤Î½ÐÎϤνç½ø¤ò±¦¤«¤éº¸¤Ø¤Ë¤¹¤ë¡£ -end- db.gate.mux.select ¥»¥ì¥¯¥¿¤Î²Õ½ê db.gate.mux.sel1.hdr º¸Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel2.hdr ±¦Â¦¤Î¥»¥ì¥¯¥¿ db.gate.mux.sel1.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤòº¸Â¦¤Ë¤ª¤¯¡£ -end- db.gate.mux.sel2.exp -fillbegin- ¥»¥ì¥¯¥¿¤ÎÆþÎϤò±¦Â¦¤Ë¤ª¤¯¡£ -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse ³ÈÄ¥¥Ð¡¼¤òÍøÍÑ db.gate.aox.use.hdr ³ÈÄ¥¥Ð¡¼ db.gate.aox.nouse.hdr ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ·¤Ê¤¤ db.gate.aox.use.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.aox.nouse.exp -fillbegin- ´ðËÜ¥²¡¼¥È(AND, OR, ¤Ê¤É)¤ËÆþÎϤòÄɲ乤ë»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤµ¤ì¤Ê¤¤¡£ -end- db.gate.led.type LED¤Î¥¿¥¤¥× db.gate.led.bit.hdr ¥Ó¥Ã¥È db.gate.led.bar.hdr ¥Ð¡¼¡¦¥°¥é¥Õ db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- °ì¥Ó¥Ã¥È¤Î¿®¹æ¤Î°Ù¤Îñ°Ì¤ÎLED -end- db.gate.led.bar.exp -fillbegin- LED¤Î¥Ð¡¼¡¦¥°¥é¥Õ¡£°ì¥Ó¥Ã¥È¤Ë¤Ä¤­¡¢°ì¤Ä¤Î¥Ð¡¼¤¬ÍøÍѤµ¤ì¤ë¡£ -end- db.gate.led.hex.exp -fillbegin- ¿®¹æ¤ò16¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.dec.exp -fillbegin- ¿®¹æ¤ò10¿Ê¿ô¤Çɽ¼¨¤¹¤ë¡£ -end- db.gate.led.seg.exp -fillbegin- ³Æ¥»¥°¥á¥ó¥È¤òÊÌ¡¹¤ËÀ©¸æ¤¹¤ë¡£ -end- db.gate.tap.lbl.bus LSB: db.gate.tap.exp.bus Æɤ߹þ¤à¥Ó¥Ã¥È¡¦¥ì¡¼¥ó¥¸¤ÎºÇ¤â²¼¤Î¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.gate.tap.exp.bit Æɤ߹þ¤à¥Ó¥Ã¥È¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£ db.gate.dip.value.hex 16¿Ê¿ô¤ÎÃÍ: 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¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¤Ï¡¢¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤¬¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤Î¥È¥Ã¥×¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ msg.sim.nogatemod ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¡¢¶ñÂÎŪ¤Ê¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤¬É¬ÍפǤ¢¤ë¡£ msg.setinterface ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ò¥»¥Ã¥È¤·¤¿¡£ msg.needsel ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤òÁª¤ó¤Ç¤¯¤À¤µ¤¤¡£ msg.wroteckpt ¡Ö%s¡×¤Ë¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥È¤ò½ñ¤­¹þ¤ó¤À... msg.save ¡Ö%s¡×¤ËÊݸ¤·¤¿¡£ msg.reallynew ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢¿·¤·¤¤²óÏ©¤ò³«¤­¤Þ¤¹¤«? msg.reallyquit ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢½ªÎ»¤·¤Þ¤¹¤«? msg.notlib ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ï¥é¥¤¥Ö¥é¥ê¡¦¥â¥¸¥å¡¼¥ë¤Ç¤Ï¤Ê¤¤¡£ ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ¤½¤Î°ÌÃ֤˥²¡¼¥È¤òÃÖ¤¯¤Î¤Ï¡¢¤ªÁ°¤ß¤¿¤¤¤ÊÂçÇϼ¯¤·¤«¤¤¤Ê¤¤¤è¡£ miles.msg2 Çϼ¯¡ª miles.msg3 ¶ò¤«¤â¤Î¡ª miles.msg4 ¥Þ¥¤¥ë¥¹¡¢¤½¤Î°ÌÃ֤˥²¡¼¥È¤òÃÖ¤¯¤Î¤Ï¡¢Çϼ¯¤À¤è¡£ miles.msg5 Çϼ¯¤Ê¥²¡¼¥È¤Î°ÌÃÖÉÕ¤±¤ò¤ä¤á¤Æ¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg6 ¥²¡¼¥È¤ò¤½¤Î°ÌÃ֤ˤª¤¤¤¿¤Î¤Ï¡¢¤ªÁ°¤Î¶ò¤«¤µ¤Î¾ÚÌÀ¤À¤è¡£ miles.msg7 ¤³¤Î¥í¥¯¤Ç¤Ê¤·²óÏ©¤ÎÀ߷פòÄü¤á¤è¡¢¥Þ¥¤¥¹¥ë¡£ miles.msg8a ³¤±¤Æ¤â¡¢ÌµÂ̤À¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg8b ¤ªÁ°¤¬²óÏ©¤òÀß·×½ÐÍè¤Ê¤¤¤È¤¤¤¦¤Î¤Ï¡¢Ã¯¤Ç¤âʬ¤«¤ë¤è¡£ ############################################################################# # # Error messages generated by verga # verga.err.OK ¿´ÇÛ¤·¤Ê¤¤¤Ç¡¢¾Ð¤Ã¤Æ¤¯¤À¤µ¤¤¡£ verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.NONSTATCTL TODO: Event control @(*) applied to non-statment. verga.err.BADVALUE TODO: Bad numeric value '%s'. verga.err.BADPORTTYPE TODO: Invalid type declaration used on port '%s' verga.err.PATHDCOND TODO: DelaMust set through both # expression and specify block. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. verga.err.NONEXPCTL TODO: Event control @(*) applied to non-expression. ############################################################################## # Balloon Help # ho.net.in °ì¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out °ì¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout °ì¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.in2 ¿¥Ó¥Ã¥È¤ÎÆþÎÏ ho.net.out2 ¿¥Ó¥Ã¥È¤Î½ÐÎÏ ho.net.inout2 ¿¥Ó¥Ã¥È¤ÎÆþ½ÐÎÏ ho.net.wire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.wire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬É½¼¨¤·¤Æ¤¤¤ë) ho.net.hwire °ì¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.hwire2 ¿¥Ó¥Ã¥È¤Î¥ï¥¤¥ä(̾Á°¤¬±£¤·¤Æ¤¤¤ë) ho.net.reg °ì¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.net.reg2 ¿¥Ó¥Ã¥È¤Î¥ì¥¸¥¹¥¿ ho.opt.tool.file ²óÏ©¥Õ¥¡¥¤¥ë¤Î¥»¡¼¥Ö¡¢¥í¡¼¥É¤Ê¤É ho.opt.tool.edit ¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¡¢Ãµº÷¤Ê¤É ho.opt.tool.gateopt ¥²¡¼¥È¤ÎŸ³«¤ÈÀ°Îó ho.opt.tool.gateprop ´ðËܤΥ²¡¼¥È¤ÎÊÔ½¸ ho.opt.tool.undo ¥¢¥ó¥É¥¥¤È¥ê¥É¥¥ ho.opt.tool.zoom ¥º¡¼¥à¡¦¥¤¥ó¤È¥º¡¼¥à¡¦¥¢¥¦¥È ho.opt.tool.mode ÊÔ½¸¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.module ¥â¥¸¥å¡¼¥ëÄêµÁ¤Î¿·µ¬ºîÀ®¡¢ºï½ü¡¢ºÆ̾Á°ÉÕ¤±¤Ê¤É ho.opt.tool.tech ¥²¡¼¥È¤Î¥Æ¥¯¥Î¥í¥¸¤ÎÁªÂò ho.opt.tool.simctl ¥·¥ß¥å¥ì¡¼¥¿¤Îµ¯Æ°¡¢½ªÎ»¡¢°ì»þÄä»ß¤Ê¤É ho.opt.tool.simaux ÉÕ°¤Î¥·¥ß¥å¥ì¡¼¥¿¤Î¥³¥Þ¥ó¥É(¥á¥â¥ê¤ÎÆɤ߹þ¤ß¡¢½ñ¤­¹þ¤ß¤Ê¤É) ho.opt.tool.symmode ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ä¡¼¥ë¤ÎÁªÂò ho.opt.tool.symedit ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥«¥Ã¥È¡¢¥Ú¡¼¥¹¥È¤Ê¤É ho.opt.tool.symport ¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥Ý¡¼¥È¤Î²óž ho.opt.tool.symshift ¥Ó¥Ã¥È¡¦¥Þ¥Ã¥×¤ò¾å²¼º¸±¦¤Î¥·¥Õ¥È ho.opt.tool.symopr ÉÕ°¤Î¥·¥ó¥Ü¥ëÊÔ½¸¤Î¥³¥Þ¥ó¥É ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ¸½ºß¤Î²óÏ©¤ò¾Ã¤·¤Æ¡¢¿·¤·¤¤ ²óÏ©¤òºîÀ®¤¹¤ë¡£ -end- ho.open ²óÏ©¥Õ¥¡¥¤¥ë¤ò³«¤­¤Þ¤¹¡£ ho.save ²óÏ©¥Õ¥¡¥¤¥ë¤òÊݸ¤·¤Þ¤¹¡£ ho.saveas ²óÏ©¥Õ¥¡¥¤¥ë¤ò»ØÄê¤Î¥Õ¥¡¥¤¥ë¤ËÊݸ¤·¤Þ¤¹¡£ ho.print ²óÏ©¥Õ¥¡¥¤¥ë¤ò°õºþ¤¹¤ë ho.library ¥é¥¤¥Ö¥é¥ê¡¦¥Þ¥Í¥¸¥ã¡¼¤ò³«¤­¤Þ¤¹¡£ ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- °ÜÆ°¡¿Àܳ - ¤³¤Î¥Ä¡¼¥ë¤Ç°Ê²¼¤Îµ¡Ç½¤ò¹Ô¤¤¤Þ¤¹¡£ ¿·¤·¤¤¥²¡¼¥È¤Î°ÌÃÖ¤òÀßÄꤹ¤ë¡£ ¥²¡¼¥È¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤ò°ÜÆ°¤¹¤ë¡£ ¥ï¥¤¥ä¤òÀܳ¤¹¤ë¡£ ¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤Ç°Ê²¼¤Îµ¡Ç½¤¬»È¤¨¤ë¡£ ¥²¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥ï¥¤¥ä¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥Ý¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë¡£ ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤Î°À­¤òÊÔ½¸¤¹¤ë -end- ho.delgat -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥²¡¼¥È¤òºï½ü¤¹¤ë -end- ho.cutw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤òÀÚÃǤ¹¤ë -end- ho.inv -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¡¢¥²¡¼¥È¤ÎÆþ½ÐÎÏ¤Ë ÈÝÄê¤òÉÕ¤±¤¿¤ê¡¢¾Ã¤·¤¿¤ê¤¹¤ë¡£ -end- ho.bitw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤Î¥Ó¥Ã¥ÈÉý¤ò Êѹ¹¤¹¤ë¡£¥Ó¥Ã¥ÈÉý¤ò±¦²¼¤ÎÆþÎÏ ¥Ü¥Ã¥¯¥¹¤ËÆþÎϤ·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open ÁªÂò¤µ¤ì¤¿¥â¥¸¥å¡¼¥ë¤ò³«¤¯ ho.mod.close ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤òÊĤ¸¤ë ho.mod.new ¥â¥¸¥å¡¼¥ë¤Î¿·µ¬ºîÀ® ho.mod.del ¥â¥¸¥å¡¼¥ë¤Îºï½ü ho.mod.copy ¥â¥¸¥å¡¼¥ë¤ò¥³¥Ô¡¼¤·¤Þ¤¹¡£ ho.mod.rename ¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ ho.mod.claim -begin- ¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë¤ò¥æ¡¼¥¶¤Î¥â¥¸¥å¡¼¥ë¤ËÊѹ¹¤·¤Þ¤¹¡£ -end- ho.mod.setroot -begin- »ØÄê¤Î¥â¥¸¥å¡¼¥ë¤ò¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Ë¤·¤Þ¤¹¡£ -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo ºÇ¶á¹Ô¤Ã¤¿ÊѲ½¤ò¸µÄ̤ê¤Ë¤¹¤ë¡£ ho.redo ¥¢¥ó¥Ç¥©¤·¤¿ÊѲ½¤ò¤ä¤êľ¤¹¡£ ho.tab.edit -begin- ²óÏ©¥Ç¡¼¥¿¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.interface -begin- ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤òÊÔ½¸¤·¤Þ¤¹¡£ -end- ho.tab.simulate -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òµ¯Æ°¤·¡¢¥¹¥³¡¼¥×¤Î¥¦¥£¥ó¥É¤ò ³«¤­¡¢¤½¤·¤Æ½é´ü²½¥¹¥¯¥ê¥×¥È¤¬ÄêµÁ¤·¤Æ¤¤¤ë¾ì¹ç¡¢ ¤½¤Î¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.tab.cpath -begin- ²óÏ©¤Î¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹¤òõº÷¤¹¤ë¡£ -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÆ°¤«¤¹¡£Áȹ礻²óÏ©¤Î¾ì¹ç¡¢ ¿®¹æ¤¬ÊѤï¤é¤Ê¤¯¤Ê¤ë»þ¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö ¤¬°ì»þÄä»ß¤¹¤ë¡£ -end- ho.simpause -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î°ì»þÄä»ß -end- ho.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¨¥Ý¥Ã¥¯¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simclock -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë ¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simstop -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÄä»ß¤·¤Æ¡¢ ÊÔ½¸¥â¡¼¥É¤ËÌá¤ë¡£ -end- ho.simbreak -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È ¤òÊÔ½¸¤¹¤ë¡£ -end- ho.simexec -begin- ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤òÆɤ߹þ¤à -end- ho.simdump -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤Ë½ñ¤­½Ð¤¹ -end- ho.f.modlist -begin- Æɤ߹þ¤ó¤Ç¤¢¤ë¥â¥¸¥å¡¼¥ë¤Î°ìÍ÷ɽ¡£ ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Î̾Á°¤Ë¡Ö+¡×¤¬ ÉÕ¤¤¤Æ¤¤¤ë¡£¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë ¤Ï³ç¸Ì¤Ë°Ï¤Þ¤ì¤Æ¤¤¤ë¡£ -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Í¥Ã¥È̾¤Î°ìÍ÷ɽ -end- ho.ports -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ý¡¼¥È̾¤Î°ìÍ÷ɽ -end- ho.status.logo -begin- ¸½ºß¤Î¥â¡¼¥É¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£Å´¤Î¥²¡¼¥È ¤Î¾ì¹ç¡¢ÊÔ½¸¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤Î¾ì¹ç¡¢ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤¬ Áö¤Ã¤Æ ¤¤¤ë¾ì¹ç¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö¤¬ Æ°¤¤¤Æ¤¤¤ë¡£ -end- ho.status.msg tkgate¤è¤ê¤Î¥á¥Ã¥»¡¼¥¸¤¬¤³¤³¤Ëɽ¼¨¤µ¤ì¤ë¡£ ho.status.block ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥¹ ho.status.file -begin- ¸½ºßÊÔ½¸Ãæ¤Î¥Õ¥¡¥¤¥ë̾¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£¡Ö*¡× ¤È¤¤¤¦µ­¹æ¤¬¤Ä¤¤¤Æ¤¤¤ë»þ¡¢Êݸ¤·¤Æ¤¤¤Ê¤¤Êѹ¹ ¤¬¤¢¤ë¡£ -end- ho.print.selall Á´¤Æ¤ÎÆɤ߹þ¤ó¤Ç¤¤¤ë¥â¥¸¥å¡¼¥ë¤ò°õºþ¤¹¤ë¡£ ho.print.selcur ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ho.print.seluse -begin- »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß°õºþ¤¹¤ë¡£ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- °Ê²¼¤Ë¥Þ¡¼¥¯¤·¤Æ¤¤¤ë¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ÇÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤òÁªÂò ½ÐÍè¤ë¡£ -end- ho.print.modlist °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë¤òÁªÂò¤¹¤ë¡£ ho.circuit.discchg -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢Êѹ¹¤¢¤ê¤Î²óÏ©¤ò Êݸ¤·¤Ê¤¤¤ÇÊĤ¸¤ë¤È¤­·Ù¹ð¤·¤Ê¤¤¡£ -end- ho.circuit.extbar -begin- ´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬ 3Ëܰʾå¤Î»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.circuit.autostart -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤ËÆþ¤ë¤È¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤¬¤¹¤°¼Â¹Ô¤¹¤ë¡£ -end- ho.circuit.language -begin- ²óÏ©¥Ç¡¼¥¿¤òɽ¼¨¤¹¤ë°Ù¤Î¥Õ¥©¥ó¥È¤ò ÁªÂò¤·¤Æ¤¯¤À¤À¤¤¡£ÆüËܸìn¤Î¾ì¹ç¡¢ ¡Öeuc-jp¡×¤Ë¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.cmd.bitw -begin- ¥«¡¼¥½¥ë¤ÇÁªÂò¤µ¤ì¤¿¥ï¥¤¥ä¤Ïɽ¼¨ ¤µ¤ì¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤵ¤ì¤ë¡£ -end- ho.edgat.signam -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Ç¤¢¤ë¡£Ì¾Á°¤¬Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.port -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥È̾¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥²¡¼¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.iolab -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥ÈÊý¸þ¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥²¡¼¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.bitlab -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ó¥Ã¥ÈÉý¤Ç¤¢¤ë¡£Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.cycle °ì¥µ¥¤¥¯¥ë¤Î¥¨¥Ý¥Ã¥¯¿ô ho.edgat.phase ¥¯¥í¥Ã¥¯¤Î¥Õ¥§¡¼¥º¡Ê¥Ñ¡¼¥»¥ó¥È¤ÇÀßÄꤹ¤ë¡Ë ho.edgat.duty ¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë¤Î²¿¥Ñ¡¼¥»¥ó¥È¤¬ÏÀÍý0¤Ç¤¢¤ë¤« ho.edgat.hide -begin- Í­¸ú¤Ë¤¹¤ë¤È¥²¡¼¥È̾¤¬É½¼¨¤µ¤ì¤Ê¤¤¡£ -end- ho.edgat.gtype ¥²¡¼¥È¤Î¼ïÎà ho.edgat.gname ¥²¡¼¥È¤Î̾Á° ho.edgat.ganchor Í­¸ú¤Ë¤¹¤ë¤È¡¢¥²¡¼¥È¤¬°ÜÆ°ÉԲĤˤʤ롣 ho.edgat.gx ¥²¡¼¥È¤ÎX°ÌÃÖ ho.edgat.gy ¥²¡¼¥È¤ÎY°ÌÃÖ ho.edgat.swstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.dipstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.range ¥Þ¥ë¥Á¥Ó¥Ã¥È¤Î¿®¹æ¤Î¥µ¥Ö¡¦¥ì¥ó¥¸¤Ç¤¢¤ë¡£ ho.edgat.memfile -begin- ¥á¥â¥ê¤Î½é´ü¤ÎÃͤΥե¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¡¢¤³¤Î¥Õ¥¡¥¤¥ë ¤¬Æɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.edgat.func ¥â¥¸¥å¡¼¥ë¤Îµ¡Ç½ ho.edgat.frame ¥Õ¥ì¡¼¥à¤Î¥é¥Ù¥ë ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undo¤Î¥ê¥¹¥È¤ÎŤµ -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- ²óÏ©¤Ê¤É¤ò°õºþ¤¹¤ë»þ¡¢¤³¤Î¥µ¥¤¥È̾¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.smooth -begin- ¤³¤ÎÀßÄê¤òÍ­¸ú¤Ë¤¹¤ë¤È¡¢²óÏ©¤ò¥¹¥¯¥í¡¼¥ë¤¹¤ë»þ¡¢ ¥Ó¥Ã¥È¥Þ¥Ã¥×¤Î¥³¥Ô¡¼¤òÍøÍѤ·¤Æ¡¢¸úΨ¤è¤¯ ¥¹¥¯¥í¡¼¥ë¤Ç¤­¤ë¡£X¥µ¡¼¥Ð¤ÎÌäÂ꤬¤¢¤ì¤Ð¡¢¤³¤Î ÀßÄê¤ò̵¸ú¤Ë¤¹¤ì¤ÐÎɤ¤¡£ -end- ho.opt.clip -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¦¥¤¥ó¥É¥¦¤ÎÉôʬÎΰè¤Î ºÆÉÁ²è¤ò¹Ô¤Ê¤¦¡£¤½¤¦¤Ç¤Ê¤±¤ì¤Ð¾ï¤Ë Á´Îΰè¤òºÆÉÁ²è¤¹¤ë¡£ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥â¥¸¥å¡¼¥ë¤ò°ÜÆ°¤¹¤ë»þ¡¢ ¥ï¥¤¥ä¤Ê¤É¤Ï¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤òÎ¥¤¹¤Þ¤Ç °ÜÆ°¤·¤Ê¤¤¡£²èÌ̤Îɽ¼¨¤¬ÃÙ¤¤»þ¤ËÊØÍø¤Ç¤¢¤ë¡£ -end- ho.opt.bhelp -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ÎÍͤʡ֥إë¥×¡¦ ¥Ð¥ë¡¼¥ó¡×¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.novice -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢½é¿´¼Ô¥â¡¼¥É¤Ë¤Ê¤ë¡£ ½é¿´¼Ô¥â¡¼¥É¤Ç¤Ï¡¢tkgate¤¬Î©¤Á¾å¤¬¤ë»þ¡¢ ¥Á¥å¡¼¥È¥ê¥¢¥ë¤¬¼«Æ°Åª¤ËÆɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ç¥Ð¥°µ¡Ç½¤¬»È¤¨¤ë¡£ ³«È¯¼Ô°Ê³°¤Ë¡¢¤¢¤Þ¤êÌò¤ËΩ¤¿¤Ê¤¤¡£ -end- ho.opt.ckpt Í­¸ú¤Ë¤¹¤ë¤È¡¢tkgate¤Ï¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤Î¥Õ¥¡¥¤¥ë¤òºî¤ë¡£ ho.opt.ckptfreq ¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤ò²¿¥¯¥ê¥Ã¥¯Ëè¤Ë¹Ô¤Ê¤¦¤« ho.opt.beak -begin- Á´Á³Ìò¤ËΩ¤¿¤Ê¤¤µ¡Ç½¤òÍ­¸ú¤Ë¤¹¤ë¡£¤³¤Îµ¡Ç½¤ò ̵¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥¹¥¤¥Ã¥Á¤Ï¥À¥¤¥¢¥í¥° ¥Ü¥Ã¥¯¥¹¤«¤é¾Ã¤¨¡¢.tkgate-properties¤òÊÔ½¸¤·¤Ê¤¤¸Â¤ê Ìá¤é¤Ê¤¤¡£ -end- ho.opt.miles -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢tkgate¤Ï»þ¡¹¥æ¡¼¥¶¤ò Çϼ¯¤Ë¤·¤¿¤ê¡¢°­¸ý¤ò¸À¤Ã¤¿¤ê¤¹¤ë¡£ -end- ho.opt.bat -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ð¥Ã¥È¥Þ¥ó¤Î¥³¥ó¥Ô¥å¡¼¥¿¤ò À߷פ¹¤ë°Ù¤Ë¡ÖÌò¤Ë¤¿¤Ä¡×µ¡Ç½¤¬»È¤¨¤ë¡£ -end- ho.opt.trek žÁ÷¤·¤í¡¢¥¹¥³¥Ã¥Æ¥£¡ª ho.opt.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¹¥Æ¥Ã¥×¡¦¥³¥Þ¥ó¥É¤Ç ²¿¥¨¥Ý¥Ã¥¯¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¥¹¥Æ¥Ã¥×¡¦ ¥³¥Þ¥ó¥É¤Ç ²¿¥µ¥¤¥¯¥ë¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckover -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤è¤ê¹¹¤Ë²¿¥¨¥Ý¥Ã¥¯ ¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.vpopupdelay -begin- ¥Þ¥¦¥¹¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤«¤é¡¢²¿¥ß¥êÉÃ·Ð¤Ã¤Æ ¤«¤é¿®¹æ¤ÎÃͤ¬É½¼¨¤µ¤ì¤ëÃÙ±ä¤Ç¤¢¤ë¡£ ¤³¤Î Ãٱ䤬û²á¤®¤ë»þ¡¢¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤¬ ǧÃÎ ¤Ç¤­¤Ê¤¯¤Ê¤ëÌäÂ꤬¤¢¤ë¥·¥¹¥Æ¥à¤Ï ¤¢¤ë¡£ ¤³¤ÎÌäÂ꤬µ¯¤³¤é¤Ê¤±¤ì¤Ð¡¢ÃÙ±ä ¤ò¤è¤ê û¤¯¤·¤Æ¤âÎɤ¤¡£ -end- ho.opt.init -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òΩ¤Á¾å¤²¤ë»þ¤Ë ¼«Æ°Åª¤Ë¼Â¹Ô¤¹¤ë¥¹¥¯¥ê¥×¥È¡¦ ¥Õ¥¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckall -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¤É¤Î¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Ç¤âÄä»ß¤¹¤ë¡£ -end- ho.opt.ckspec -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï »ØÄꤷ¤¿¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Î¤ß¤ËÄä»ß¤¹¤ë¡£ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- ¿·¤·¤¤¥²¡¼¥È¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥Æ¥¯¥Î¥í¥¸¡¼¡£ ¥²¡¼¥È¤ÎÃÙ±ä¤Ë±Æ¶Á¤¹¤ë¡£Ç¤°Õ¤Î¥²¡¼¥È ¤Î ¥Æ¥¯¥Î¥í¥¸¡¼¤òÊѹ¹¤¹¤ë¤Ë¤Ï¡¢¥²¡¼¥È¤ÎÀßÄê ¥Ü¥Ã¥¯¥¹¤ò³«¤¤¤Æ¡¢¡ÖÃÙ±ä¡×¤Î¥¿¥Ö ¤òÁªÂò ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.techbut -begin- »ØÄꤷ¤¿¥Æ¥¯¥Î¥í¥¸¡¼¡¦¥Õ¥¡¥¤¥ë¤«¤é¤Î ÃÙ±äÃͤò ÍøÍѤ¹¤ë¡£¿·¤·¤¤¥Æ¥¯¥Î¥í¥¸¡¼¤ò Äɲ乤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¢ª¡ÖÀßÄê...¡×¢ª ¡Ö¥·¥ß¥å¥ì¡¼¥È¡× ¤Î¥á¥Ë¥å¡¼¤ò³«¤¤¤Æ¡¢ ¥Õ¥¡¥¤¥ë¤Î¥ê¥¹¥È¤ËÄɲà ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.custbut -begin- ¤³¤Î¥²¡¼¥ÈÀìÍѤÎÃÙ±äÃͤò»ØÄꤹ¤ë¡£ -end- ho.contver -begin- ¥Þ¥¦¥¹Áàºî¤ò¹Ô¤Ê¤¦»þ¡¢ÆâÉô¹½Â¤¤ò¼«Æ°Åª¤Ë ³Îǧ¤·¤Æ¡¢ÉÔÀµ¤Î½ê¤òÃΤ餹¡£ -end- ho.simwatch -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ÈGUI¤Î´Ö¤Î¥³¥Þ¥ó¥É¤òɽ¼¨¤¹¤ë¡£ -end- ho.modtree -begin- ³¬Áإĥ꡼¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.modlist -begin- °ìÍ÷ɽ¤Ç²óÏ©¤ÎÃæ¤Î¥â¥¸¥å¡¼¥ë̾ ¤òɽ¼¨¤·¤Þ¤¹¡£¥â¥¸¥å¡¼¥ë̾¤ò ÊÔ½¸¥¦¥£¥ó¥É¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤òºîÀ®½ÐÍè¤Þ¤¹¡£ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- ¸½ºß¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥²¡¼¥È²óž¤òɽ¼¨¤·¤Æ¤¤¤Þ¤¹¡£ ¾°¡¢¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥Ç¥Õ¥©¥ë¥È²óž¤òÊѹ¹¤·¤Þ¤¹¡£ -end- ho.tool.zoomin ¥º¡¼¥à¡¦¥¤¥ó ho.tool.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È ho.tool.rotate ÁªÂò¤Î¥²¡¼¥È¤òÈó»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.brotate ÁªÂò¤Î¥²¡¼¥È¤ò»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.valgn ÁªÂò¤Î¥²¡¼¥È¤ò½Ä¤Ë°ìÎó¤Ëʤ֡£ ho.tool.halgn ÁªÂò¤Î¥²¡¼¥È¤òÍâ¤Ë°ìÎó¤Ëʤ֡£ ho.tool.cut ÁªÂò¤Î¥²¡¼¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥«¥Ã¥È¤¹¤ë¡£ ho.tool.copy ÁªÂò¤Î¥²¡¼¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥³¥Ô¡¼¤¹¤ë¡£ ho.tool.paste ¥«¥Ã¥È¥Ð¥Ã¥Õ¥¡¤Î¥²¡¼¥È¤òÄ¥¤êÉÕ¤±¤ë¡£ ho.tool.find ¥²¡¼¥È¡¢¥ï¥¤¥ä¡¢¥Æ¥­¥¹¥È¤Ê¤É¤òõº÷¤¹¤ë¡£ ho.tool.addport ÁªÂò¤Î¥²¡¼¥È¤Ë¥Ý¡¼¥È¤òÄɲ乤롣 ho.tool.anchor ÁªÂò¤Î¥²¡¼¥È¤ò°ÜÆ°ÉԲĤˤ¹¤ë¡£ ho.tool.unanchor ÁªÂò¤Î¥²¡¼¥È¤ò°ÜÆ°²Äǽ¤Ë¤¹¤ë¡£ ho.tool.replicate ¥²¡¼¥È¤òÊ£À½¤¹¤ë¡£ ho.tool.delete ÁªÂò¤Î¥²¡¼¥È¤òºï½ü¤¹¤ë¡£ ho.opt.tearawaymenus -begin- TODO: If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.ipanel.deleteport -begin- TODO: Delete the selected port. -end- ho.ipanel.updateall -begin- TODO: Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.circuit.title -begin- TODO: Description of your circuit. This title is used on printed output. -end- ho.ipanel.generate -begin- TODO: Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.simmove -begin- TODO: Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.opt.sim.savetraces -begin- TODO: Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.ipanel.editport -begin- TODO: Edit the selected port. You can also double-click to edit a field in a port. -end- ho.symed.export TODO: Export image to file. ho.setsel.ltor TODO: Move highlighted items to selected list. ho.print.timegraph -begin- TODO: The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.setsel.allr TODO: Move all items to selected list. ho.circuit.encoding -begin- TODO: Use this encoding for save files. -end- ho.opt.tool.simmode TODO: Choose between the select and scroll tool in simulator. ho.setsel.alll TODO: Move all items to unselected list. ho.circuit.ver -begin- TODO: This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.file -begin- TODO: This is the file name from which the current circuit was loaded. -end- ho.scroll -begin- TODO: Scroll - Grab and drag the editing canvas. -end- ho.symed.import TODO: Import image from file. ho.ipanel.select -begin- TODO: Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- TODO: Add a port to the module. You can also double-click after the last item to add port. -end- ho.setsel.rtol TODO: Move highlighted items to unselected list. blklst.delete.title TkGate: ¥â¥¸¥å¡¼¥ëºï½ü print.tab.advanced ¥¢¥É¥Ð¥ó¥¹ primitive.err.nomodule ÆâÉô¥¨¥é¡¼: ¥×¥ê¥ß¥Æ¥£¥Ö¡¦¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ç¡¢¥­¡¼¥ï¡¼¥É¡Ömodule¡×¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ db.net.caption ¥Í¥Ã¥È¤ÎÆÃħ blklst.rename.title TKGate: ¥â¥¸¥å¡¼¥ë¤ÎºÆ̾ÉÕ¤± db.gate.switch.state ½é´ü¥¹¥¤¥Ã¥Á¤Î¾õÂÖ primitive.err.wrongname ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬ÆâÉô¥â¥¸¥å¡¼¥ë̾¤È°ìÅù¤·¤Þ¤»¤ó¡£ db.gate.tap.lbl.bit ¥Ó¥Ã¥È: db.hdl.textdisp.title HDL¤Î¥Æ¥­¥¹¥È¤Î½èÍý db.gate.tap.select ¥Ó¥Ã¥È¡¦¥¿¥Ã¥×¤ÎÁªÂò db.err.neededit -fillbegin- ¥¦¥¡¡¼¥ó¥¤¥ó¥°¤Ë°ÜÆ°¤¹¤ëÁ°¤Ë¡¢ÊÔ½¸¥â¡¼¥É¤ËÀÚÂؤ¨¤ëɬÍפ¬¤¢¤ê¤Þ¤¹¡£ -end- menu.edit.autobold ¼«Æ°ÂÀ»ú @db.gate.tap.exp.width *180 circ.reallyupdate -fillbegin- ËÜÅö¤ËÁ´¤Æ¤Î¡Ö%s¡×¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤ò¹¹¿·¤·¤¿¤¤¤Î¤Ç¤¹¤«¡£ -end- blklst.copy.title TKGate: ¥â¥¸¥å¡¼¥ë¤Î¥³¥Ô¡¼ primitive.err.missing ÆâÉô¥¨¥é¡¼: ¡Ö%s¡×¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤¬È¯¸«½ÐÍè¤Þ¤»¤ó¡£ menu.file.import ²èÁü¥Ç¡¼¥¿¤ò¥¤¥ó¥Ý¡¼¥È db.newcirc.title TkGate: ¿·µ¬²óÏ© opt.tool.simmode ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ä¡¼¥ë blklst.new.title TKGate: ¿·µ¬¥â¥¸¥å¡¼¥ë print.title TkGate: °õºþ db.gate.switch.state.on.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥ó print.config.title TkGate: °õºþ¤ÎÀßÄê db.gate.waveform ¥¯¥í¥Ã¥¯¤ÎÇÈ·Á print.incunused »ÈÍѤ·¤Ê¤¤¥â¥¸¥å¡¼¥ë¤â´Þ¤ß¤Þ¤¹¡£ db.gate.switch.state.on.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥ó¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ db.gate.switch.state.off.hdr ¥¹¥¤¥Ã¥Á¡¦¥ª¥Õ opt.treelabel ¥ª¥×¥·¥ç¥ó menu.symbol ¥·¥ó¥Ü¥ë print.tab.modules ¥â¥¸¥å¡¼¥ë opt.title TkGate: ¥ª¥×¥·¥ç¥ó port.title TkGate: ¥Ý¡¼¥È¤ÎÈùºÙ primitive.err.nomodname ÆâÉô¥¨¥é¡¼:¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤ÎÄêµÁ¤Ë¥â¥¸¥å¡¼¥ë̾¤¬·ç¤±¤Æ¤¤¤Þ¤¹¡£ blklst.claim.title TKGate: ¥â¥¸¥å¡¼¥ë¤Î¥¯¥ì¡¼¥à igen.title TkGate: ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤Î¼«Æ°ºîÀ® err.yy.badlocale ¥»¡¼¥Ö¡¦¥Õ¥¡¥¤¥ë¤Ë̤ÃΤÎʸ²½·÷¡Ö%s¡×¤¬¤¢¤ê¤Þ¤·¤¿¡£ÊѤï¤ê¤Ë±Ñ¸ì¤Îʸ²½·÷¤¬ÍøÍѤµ¤ì¤Þ¤¹¡£ db.dip.title TkGate: DIP¤ÎÃÍ print.scope.title TkGate: ¥¹¥³¡¼¥×¤Î°õºþ db.gate.switch.state.off.exp ¥¹¥¤¥Ã¥Á¤Ï¡Ö¥ª¥Õ¡×¤Î¾õÂ֤ǥ·¥ß¥å¥ì¡¼¥·¥ç¥ó¤òµ¯Æ°¤·¤Þ¤¹¡£ circ.wintitle TkGate: ²óÏ©¤ÎÈùºÙ find.title TkGate: õº÷ db.gate.dip.value.exp ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Îµ¯Æ°¤Î»þ¤ÎDIP¤ÎÃÍ¡£ db.err.title TkGate: ¥¨¥é¡¼¤Î°ìÍ÷ɽ menu.file.export ²èÁü¥Ç¡¼¥¿¤Î¥¨¥¯¥¹¥Ý¡¼¤È print.rangeselection ¥ì¡¼¥ó¥¸¤ÎÁªÂò pop.simulate.delprobe ¥Ý¥í¡¼¥Ö¤Îºï½ü print.linelen °ì¹ÔÎó¤Î»þ´Ö db.hdl.namechange.title HDL¥â¥¸¥å¡¼¥ë¤Î̾Á°¤ÎÉÕ¤±ÊѤ¨ opt.vlibadd.title TkGate: ¥é¥¤¥Ö¥é¥ê¡¼¤ÎÄɲà blklst.setroot.title TKGate: ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤ÎÀßÄê @db.gate.dip.value.exp.width 150 tkgate-2.0-b10/locale/ja/messages.euc000644 001751 001751 00000227263 11132500535 020153 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Jan 11 18:31:41 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages ############################################################################## # # Set the necessary encodings for Japanese # \messages-encoding euc-ja \verilog-encoding euc-ja \font-encoding euc-ja ############################################################################## # # basic strings # b.new ¿·µ¬... b.dismiss ÊĤ¸¤ë b.close ÊĤ¸¤ë b.ok £Ï£Ë b.clear ¥¯¥ê¥¢ b.cancel ¥­¥ã¥ó¥»¥ë b.open ³«¤¯ b.bitw ¥Ó¥Ã¥ÈÉý b.in Æþ b.out ½Ð b.inout Æþ½Ð b.browse ÁªÂò... b.label ̾Á° b.find õº÷ b.edit ÊÔ½¸... b.add ÄɲÃ... b.delete ºï½ü b.deleteb ºï½ü... b.remove ¾Ã¤¹ b.apply ¥»¥Ã¥È b.anchor °ÜÆ°ÉÔ²Ä b.tech ¥Æ¥¯¥Î¥í¥¸¡¼ b.enable ²Äǽ¤Ë¤¹¤ë b.disable ̵ǽ¤Ë¤¹¤ë b.flush ¥¯¥ê¥¢ ############################################################################## # # Main tab strings # tab.edit ÊÔ½¸ tab.editintr ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ tab.simulate ¥·¥ß¥å¥ì¡¼¥È tab.cpath ÃÙ±ä²òÀÏ # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add ÄɲÃ... mm.delete ºï½ü mm.edit ÊÔ½¸... mm.enable Í­¸ú¤Ë¤¹¤ë mm.disable ̵¸ú¤Ë¤¹¤ë ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ¥Õ¥¡¥¤¥ë menu.edit ÊÔ½¸ menu.tool ¥Ä¡¼¥ë menu.simulate ¥·¥ß¥å¥ì¡¼¥È menu.module ¥â¥¸¥å¡¼¥ë menu.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.gate ¥²¡¼¥È menu.make ºîÀ® menu.help ¥Ø¥ë¥× menu.file.new ¿·µ¬ºîÀ® menu.file.open ³«¤¯... menu.file.openlib ¥é¥¤¥Ö¥é¥ê¤ò³«¤¯... menu.file.save Êݸ menu.file.saveas ̾Á°¤òÉÕ¤±¤ÆÊݸ... menu.file.print °õºþ... menu.file.options ÀßÄê... menu.file.quit ½ªÎ» menu.file.cprop ²óÏ©¤ÎÆÃħ... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut ¥«¥Ã¥È menu.edit.copy ¥³¥Ô¡¼ menu.edit.paste ¥Ú¡¼¥¹¥È menu.edit.overlay OverlayÄ¥¤êÉÕ¤± menu.edit.selall Á´¤Æ¤òÁªÂò menu.edit.find ²óÏ©¤òõº÷... menu.edit.algnv ½Ä¤Î°ìÎó menu.edit.algnh ²£¤Î¡¼Îó menu.edit.rotate ²óž menu.edit.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.edit.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.edit.rshift ±¦¥·¥Õ¥È menu.edit.lshift º¸¥·¥Õ¥È menu.edit.ushift ¾å¥·¥Õ¥È menu.edit.dshift ²¼¥·¥Õ¥È menu.edit.cwrotate »þ·×¼þ¤ê²óž menu.edit.ccwrotate »þ·×È¿Âмþ¤ê²óž menu.edit.pcwrotate ¥Ý¡¼¥È¤Î»þ·×¼þ¤ê²óž menu.edit.pccwrotate ¥Ý¡¼¥È¤ÎÈó»þ·×¼þ¤ê²óž #menu.edit.autobold ÂÀ»ú²½ menu.edit.resize ºÆ¥µ¥¤¥º²½ menu.tool.move °ÜÆ°¡¿Àܳ menu.tool.delg ¥²¡¼¥È¤Îºï½ü menu.tool.cutw ¥ï¥¤¥ä¤ÎÀÚÃÇ menu.tool.inv ÈÝÄê menu.tool.bitw ¥Ó¥Ã¥ÈÉý menu.tool.debug ¥Ç¥Ð¥Ã¥° menu.tool.point ¥Ý¥¤¥ó¥È menu.tool.line ¥é¥¤¥ó menu.tool.rect ĹÊý·Á menu.tool.fillrect ¿§¤Å¤±Ä¹Êý·Á menu.tool.port ¥Ý¡¼¥È menu.tool.select ÌÈÀÕÁªÂò menu.tool.rot0 0ÅÙ²óž menu.tool.rot90 90ÅÙ²óž menu.tool.rot180 180ÅÙ²óž menu.tool.rot270 270ÅÙ²óž menu.tool.tclshell 0:Tcl Shell menu.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï menu.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» menu.simulate.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.simulate.run ¥é¥ó menu.simulate.pause °ì»þ¥¹¥È¥Ã¥× menu.simulate.step ¥¹¥Æ¥Ã¥×(¥¨¥Ý¥Ã¥¯) menu.simulate.cycle ¥¹¥Æ¥Ã¥×(¥µ¥¤¥¯¥ë) menu.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤ÎÀßÄê... menu.simulate.script ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô... menu.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.simulate.dump ¥á¥â¥ê¤Î½ñ¤­½Ð¤·... menu.module.open ³«¤¯ menu.module.close ÊĤ¸¤ë menu.module.new ¿·µ¬ºîÀ®... menu.module.del ºï½ü... menu.module.copy ¥³¥Ô¡¼... menu.module.rename ̾Á°¤ÎÊÔ½¸... menu.module.claim ¼èÆÀ... menu.module.setroot ¥ë¡¼¥È¤Ë¤¹¤ë... menu.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÀßÄê... menu.module.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ menu.module.interface.set ¥»¥Ã¥È menu.module.interface.edit ÊÔ½¸ menu.gate.addport ¥Ý¡¼¥ÈÄɲà menu.gate.ioset ¥¿¥¤¥×»ØÄê menu.gate.anchor ÁªÂò¤ò°ÜÆ°ÉԲĤˤ¹¤ë menu.gate.unanchor ÁªÂò¤ò°ÜÆ°²Ä¤Ë¤¹¤ë menu.gate.prop ¥²¡¼¥È¤ÎÀßÄê... menu.gate.rep Ê£À½ menu.gate.del ºï½ü menu.gate.settech ¥Æ¥¯¥Î¥í¥¸¡¼¤ÎÀßÄê menu.help.about tkgate¤Ë¤Ä¤¤¤Æ... menu.help.license ¥é¥¤¥»¥ó¥¹... menu.help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... menu.help.tut ¥Á¥å¡¼¥È¥ê¥¢¥ë menu.help.home ¥Û¡¼¥à¡¦¥Ú¡¼¥¸ menu.help.example ²óÏ©¤ÎÎã ############################################################################# # Scope Menu # menu.scope_file ¥Õ¥¡¥¤¥ë menu.scope_sim ¥·¥ß¥å¥ì¡¼¥È menu.scope_trace ¥È¥ì¡¼¥¹ menu.scope_help ¥Ø¥ë¥× menu.scope_file.ptrace ¥È¥ì¡¼¥¹°õºþ... menu.scope_file.close ÊĤ¸¤ë menu.scope_trace.zoomin ¥º¡¼¥à¡¦¥¤¥ó menu.scope_trace.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È menu.scope_sim.addprobe ¥×¥í¡¼¥Ö¤ÎÄɲῺï½ü menu.scope_sim.run »þ¸ú menu.scope_sim.pause °ì»þÄä»ß menu.scope_sim.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× menu.scope_sim.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... menu.scope_sim.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... menu.scope_sim.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... menu.scope_sim.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... menu.scope_help.about tkgate¤ËÉÕ¤¤¤Æ... menu.scope_help.license ¥é¥¤¥»¥ó¥¹... menu.scope_help.doc ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó... mod.intf ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ port.parms ¥Ý¡¼¥È¤Î¥Ñ¥é¥á¥¿ port.in Æþ port.out ½Ð port.inout Æþ½Ð ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ¥²¡¼¥È gm.rgate ñ¹à½ÌÌ󥲡¼¥È gm.msi MSI gm.alu ALU gm.mem ¥á¥â¥ê¡¼ gm.mod ¥â¥¸¥å¡¼¥ë gm.comment ¥³¥á¥ó¥È gm.frame ¥Õ¥ì¡¼¥à gm.io.switch ¥¹¥¤¥Ã¥Á gm.io.dip DIP¥¹¥¤¥Ã¥Á gm.io.ground ¥¢¡¼¥¹ gm.io.vdd Vdd gm.io.merge ¥ï¥¤¥ä¤Î¥Þ¡¼¥¸ gm.io.clock ¥¯¥í¥Ã¥¯ gm.io.led LED¥Ó¥Ã¥È gm.io.ledbar LEDËÀ¥°¥é¥Õ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ¥Ð¥Ã¥Õ¥¡ gm.gate.inv ÈÝÄê¥Ð¥Ã¥Õ¥¡ gm.gate.tribuf ¥È¥é¥¤¡¦¥Ð¥Ã¥Õ¥¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and ñ¹à½ÌÌóAND gm.rgate.nand ñ¹à½ÌÌóNAND gm.rgate.or ñ¹à½ÌÌóOR gm.rgate.nor ñ¹à½ÌÌóNOR gm.rgate.xor ñ¹à½ÌÌóXOR gm.rgate.xnor ñ¹à½ÌÌóXNOR gm.alu.add ²Ã»»´ï gm.alu.mult ¾è»»´ï gm.alu.div ½ü»»´ï gm.alu.lshift º¸¥·¥Õ¥È gm.alu.rshift ±¦¥·¥Õ¥È gm.alu.arshift »»¿ôŪ±¦¥·¥Õ¥È gm.alu.roll ¥í¡¼¥ë gm.mem.reg ¥ì¥¸¥¹¥¿ gm.mem.ff ¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.rff ¶ÀÁü¥Õ¥ê¥Ã¥×¡¦¥Õ¥í¥Ã¥× gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.41mux 4-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.81mux 8-1 ¥»¥ì¥¯¥¿¡¼ gm.msi.12dec 1-2 ¥Ç¥³¡¼¥À gm.msi.14dec 1-4 ¥Ç¥³¡¼¥À gm.msi.18dec 1-8 ¥Ç¥³¡¼¥À gm.mod.inst ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹ gm.mod.in ¥â¥¸¥å¡¼¥ë¤ÎÆþÎÏ gm.mod.out ¥â¥¸¥å¡¼¥ë¤Î½ÐÎÏ gm.mod.inout ¥â¥¸¥å¡¼¥ë¤ÎÆþ½ÐÎÏ tutorial.prev Á°¤Ø tutorial.next ¼¡¤Ø tutorial.chapter ¾Ï¤Î°ìÍ÷ɽ tutorial.reload ºÆÆɤ߹þ¤ß ############################################################################## # # Popup menus # pop.make ºîÀ® pop.tool ¥Ä¡¼¥ë pop.edit.paste ¥Ú¡¼¥¹¥È pop.edit.cut ¥«¥Ã¥È pop.edit.copy ¥³¥Ô¡¼ pop.port.in Æþ pop.port.out ½Ð pop.port.inout Æþ½Ð pop.wire.addseg ¥ï¥¤¥ä¤ÎÄɲà pop.wire.prop ¥Í¥Ã¥È¤ÎÆÃħ... pop.wire.hidesize ¥Ó¥Ã¥ÈÉý¤ò±£¤¹ pop.wire.showsize ¥Ó¥Ã¥ÈÉý¤ò¼¨¤¹ pop.wire.hidelabel ¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.hidealllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò±£¤¹ pop.wire.clearalllabel Á´¤Æ¤Î¥ì¡¼¥Ù¥ë¤ò¥¯¥ê¥¢ pop.wire.showlabel ¥ì¡¼¥Ù¥ë¤ò¼¨¤¹ pop.gate.open ³«¤¯ pop.gate.close ÊĤ¸¤ë pop.gate.prop ¥¤¥ó¥¹¥¿¥ó¥¹¤ÎÆÃħ... pop.gate.addport ¥Ý¡¼¥È¤ÎÄɲà pop.gate.addin ÆþÎϤÎÄɲÃ... pop.gate.addout ½ÐÎϤÎÄɲÃ... pop.gate.addinout Æþ½ÐÎϤÎÄɲÃ... pop.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë pop.gate.settech ¥Æ¥¯¥Î¥í¥¸»ØÄê pop.gate.delete ºï½ü pop.gate.ioset ¥¿¥¤¥×¤Î»ØÄê pop.module.new ¿·µ¬... pop.module.del ºï½ü... pop.module.copy ¥³¥Ô¡¼... pop.module.rename ̾Á°¤ÎÊѹ¹... pop.module.claim ¥â¥¸¥å¡¼¥ë¤Î¼èÆÀ pop.module.setroot ¥ë¡¼¥È»ØÄê... pop.module.prop ¥â¥¸¥å¡¼¥ë¤ÎÆÃħ... pop.module.int ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸... pop.simulate.end ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò½ªÎ» pop.simulate.begin ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò³«»Ï pop.simulate.addprobe ¥×¥í¡¼¥Ö¤òÄɲῺï½ü pop.simulate.run »þ¸ú pop.simulate.pause °ì»þÄä»ß pop.simulate.step ¥¨¥Ý¥Ã¥¯¡¦¥¹¥Æ¥Ã¥× pop.simulate.cycle ¥µ¥¤¥¯¥ë¡¦¥¹¥Æ¥Ã¥× pop.simulate.break ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È... pop.simulate.script ¥¹¥¯¥ê¥×¥È¤Î»þ¸ú... pop.simulate.load ¥á¥â¥ê¤ÎÆɤ߹þ¤ß... pop.simulate.dump ¥á¥â¥ê¤Î½ñ¤­¹þ¤ß... pop.interface ¥¤¥ó¥¿¥Õ¥§¡¼¥¹ pop.interface.set »ØÄê pop.interface.edit ÊÔ½¸... pop.interface.auto ¼«Æ°ºîÀ®... pop.interface.replace ¼è¤ê´¹¤¨ pop.igen.type ¥¿¥¤¥× pop.igen.side ¥µ¥¤¥É pop.igen.size ¥µ¥¤¥º pop.igen.delete ºï½ü pop.igen.in Æþ pop.igen.out ½Ð pop.igen.inout Æþ½Ð pop.igen.left º¸ pop.igen.right ±¦ pop.igen.top ¾å pop.igen.bottom ²¼ pop.igen.other ¾ ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit ÊÔ½¸ #symed.edit.cut ¥«¥Ã¥È #symed.edit.copy ¥³¥Ô¡¼ #symed.edit.paste ¥Ú¡¼¥¹¥È #symed.edit.overlay Overlay¥Ú¡¼¥¹¥È #symed.edit.rclock »þ·×¼þ¤ê²óž #symed.edit.rcclock Èó»þ·×¼þ¤ê²óž #symed.module ¥â¥¸¥å¡¼¥ë #symed.modes ¥â¡¼¥É #symed.cutpaste ¥«¥Ã¥È¡¿¥Ú¡¼¥¹¥È #symed.rotate ¥Ý¡¼¥È¤Î²óž #symed.zoom ¥º¡¼¥à #symed.update Update symed.cancel ¥­¥ã¥ó¥»¥ë symed.tab.normal È󥻥쥯¥È symed.tab.select ¥»¥ì¥¯¥È symed.link ¥»¥ì¥¯¥È¤ÈÈ󥻥쥯¥È¤òƱ»þ¤ËÊÔ½¸¤¹¤ë¡£ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg ¥ï¥¤¥ä¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥×¥í¡¼¥Ö¤ËÉÕ¤±¤Ã¤Æ¤¯¤À¤µ¤¤¡£ comment.empty [¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Æ¥­¥¹¥È¤òÊÔ½¸¤·¤Æ¤¯¤À¤µ¤¤¡£] ############################################################################## # Interface strings # ifile ¥Õ¥¡¥¤¥ë imodule ¥â¥¸¥å¡¼¥ë iblmodule ¥â¥¸¥å¡¼¥ë: iports ¥Ý¡¼¥È: ibits ¥Ó¥Ã¥ÈÉý: itype ¥¿¥¤¥×: ############################################################################# # Module Dialog Box # db.mod.name ¥â¥¸¥å¡¼¥ë̾ db.mod.file ¥Õ¥¡¥¤¥ë̾ db.mod.type ¥¿¥¤¥× db.mod.flags ¥Õ¥é¥° db.mod.dataprot ¥â¥¸¥å¡¼¥ë¤ÎÄêµÁ¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.intfprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÉÔ²Äǽ¤Ë¤¹¤ë¡£ db.mod.edprot ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÊÔ½¸¤òÀìÍÑ¥¨¥Ç¥£¥¿¤Ë¸Â¤ë¡£ db.mod.props ÆÃħ db.mod.netlist ¥Í¥Ã¥È¥ê¥¹¥È db.mod.hdl HDL # # These are probably not used anymore. Lets leave them as is. # db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netexpl -begin- ¥°¥é¥Õ¥£¥«¥ë¤Î¥¨¥Ç¥£¥¿¤ò ÍøÍѤ·¤Æ¡¢¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤ò ÄêµÁ¤¹¤ë¡£ -end- db.mod.hdlexpl -begin- Verilog¤Î¥Æ¥­¥¹¥È¤òÍøÍѤ·¤Æ¡¢ ¥â¥¸¥å¡¼¥ë¤ÎÁàºî¤òÄêµÁ¤¹¤ë¡£ -end- ############################################################################# # Error List Dialog box # db.err.caption ¥¨¥é¡¼¤Î°ìÍ÷ɽ db.err.explain -begin- ²óÏ©¤Ë¥¨¥é¡¼¤¬È¯¸«¤µ¤ì¤¿¤Î¤Ç¡¢¥·¥ß¥å¥ì¡¼¥¿¤ò³«»Ï ½ÐÍè¤Ê¤«¤Ã¤¿¡£°Ê²¼¤Î¥ê¥¹¥È¤ÎÃ椫¤é¡¢¥¨¥é¡¼¤òÁªÂò ¤·¤Æ¡¢¥¨¥é¡¼¤Î¾ì½ê¤Ë°ÜÆ°¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- ############################################################################# # Net Dialog Box # db.net.name ¥Í¥Ã¥È̾ db.net.hide ¥Í¥Ã¥È̾¤ò±£¤¹ db.net.bits ¥Ó¥Ã¥ÈÉý db.net.type ¥Í¥Ã¥È¡¦¥¿¥¤¥× db.net.port ¥Ý¡¼¥È¡¦¥¿¥¤¥× db.net.in Æþ db.net.out ½Ð db.net.inout Æþ½Ð db.net.inets ¥Í¥Ã¥È ############################################################################## # # New circuit dialog box # db.newcirc.directory ¥Ç¥£¥ì¥¯¥È¥ê db.newcirc.cap ¿·µ¬²óÏ© db.newcirc.exp -begin- ¸½ºß¤Î²óÏ©¤ÎÊÔ½¸¤ò ¼­¤á¤Æ¡¢¿·¤·¤¤²óÏ©¤ò ÊÔ½¸¤·»Ï¤á¤ë¡£ -end- db.newcirc.file ¥Õ¥¡¥¤¥ë̾ db.newcirc.topname ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë̾ ############################################################################## # Gate dialog box # db.gate.title ¥²¡¼¥È¤ÎÀßÄê db.gate.signam ¥Í¥Ã¥È̾ db.gate.portnam ¥Ý¡¼¥È̾ db.gate.iotype ¥¿¥¤¥× db.gate.bitw ¥Ó¥Ã¥ÈÉý db.gate.cyclew ¥µ¥¤¥¯¥ëÉý db.gate.phase ¥Õ¥§¡¼¥º db.gate.duty ¥Ç¥å¡¼¥Æ¥£¡¼ db.gate.port ¥Ý¡¼¥È db.gate.bitws ¥Ó¥Ã¥È db.gate.side ¥µ¥¤¥É db.gate.gtype ¥²¡¼¥È¡¦¥¿¥¤¥× db.gate.gname ¥²¡¼¥È̾ db.gate.hidenam ̾Á°¤ò±£¤¹ db.gate.anchor °ÜÆ°ÉԲĤˤ¹¤ë db.gate.cpbreak ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹Ê¬³äÅÀ db.gate.butstate ¥¹¥¤¥Ã¥Á¾õÂÖ db.gate.dipval DIP¾õÂÖ db.gate.range ¥Ó¥Ã¥ÈÈÏ°Ï db.gate.memfilenam ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë̾ db.gate.modname µ¡Ç½Ì¾ db.gate.general °ìÈÌ db.gate.details ¾ÜºÙ db.gate.text ¥Æ¥­¥¹¥È db.gate.ports ¥Ý¡¼¥È db.gate.delay ÃÙ±ä db.gate.parameters ¥Ñ¥é¥á¥¿ db.gate.stddelay ɸ½à¤ÎÃÙ±ä db.gate.custdelay ¥«¥¹¥¿¥à¤ÎÃÙ±ä db.gate.catdiruse ¥Ý¡¼¥È¤Î°ÌÃÖÉÕ¤± db.gate.edit ÊÔ½¸ db.gate.delete ºï½ü db.gate.add Äɲà db.gate.ff.type ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¤ÎÊý°Ì·èÄê db.gate.ff.normal.hdr ÉáÄÌ db.gate.ff.normal.exp -begin- ¥Ç¡¼¥¿¤¬º¸¤«¤é±¦¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.ff.reverse.hdr È¿¼Í db.gate.ff.reverse.exp -fillbegin- ¥Ç¡¼¥¿¤¬±¦¤«¤éº¸¤Ø ή¤¹¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×¡£ -end- db.gate.cat.asc.hdr ¾º½ç db.gate.cat.dec.hdr ¹ß½ç db.gate.cat.asc.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¾º½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.dec.exp -fillbegin- ¥Ó¥Ã¥È¤Ï¾å²¼¤Ë¹ß½ç¤ÇÏ¢·ë¤¹¤ë¡£ -end- db.gate.cat.sigdir ¿®¹æÊý¸þ db.gate.cat.auto.hdr ¼«Æ° db.gate.cat.multin.hdr ¿ÆþÎÏ db.gate.cat.singin.hdr ¿½ÐÎÏ db.gate.cat.tran.hdr Æþ½Ð db.gate.cat.auto.exp -fillbegin- ¿®¹æ¤ÎÊý¸þ¤ò¼«Æ°Åª ¤ËȽÃǤ¹¤ë¡£ -end- db.gate.cat.multin.exp -fillbegin- ¤¤¤Ä¤â¿¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.singin.exp -fillbegin- ¤¤¤Ä¤âñ°Ì¤Î¥Ý¡¼¥È¦¤¬ÆþÎϤȤ·¤Æ°·¤¦¡£ -end- db.gate.cat.tran.exp -fillbegin- ÁÐÊý¸þ¤Î¿®¹æ¤ÎÅÁÇÅ(tran)¤òµö¤¹¡£¥¹¥¤¥Ã¥Á¤ä¥ì¥¸¥¹¥¿¤Ë¤ÎÀܳ¤ÏÉԲĤǤ¹¡£ -end- db.gate.tab.General.cap °ìÈÌÆÃħ db.gate.tab.Ports.cap ¥Ý¡¼¥ÈÆÃħ db.gate.tab.Delay.cap ÃÙ±äÆÃħ db.gate.tab.Parameters.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.CLOCK.cap ¥¯¥í¥Ã¥¯ÆÃħ db.gate.tab.SWITCH.cap ¥¹¥¤¥Ã¥ÁÆÃħ db.gate.tab.DIP.cap DIPÆÃħ db.gate.tab.TAP.cap TranÆÃħ db.gate.tab.RAM.cap RAMÆÃħ db.gate.tab.ROM.cap ROMÆÃħ db.gate.tab.MODULE.cap ¥â¥¸¥å¡¼¥ëÆÃħ db.gate.tab.FRAME.cap ¥Õ¥ì¡¼¥àÆÃħ db.gate.tab.LED.cap LEDÆÃħ db.gate.tab.AND.cap ANDÆÃħ db.gate.tab.OR.cap ORÆÃħ db.gate.tab.XOR.cap XORÆÃħ db.gate.tab.MUX.cap MuxÆÃħ db.gate.tab.DEMUX.cap DemuxÆÃħ db.gate.tab.CONCAT.cap ConcatÆÃħ db.gate.tab.COMMENT.cap ¥Æ¥­¥¹¥ÈÆÃħ db.gate.tab.FF.cap ¥Õ¥ê¥Ã¥×¥Õ¥í¥Ã¥×ÆÃħ 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¥¨¥Ý¥Ã¥¯¤Î¥¹¥Æ¥Ã¥×¿ô opt.cstepsz ¥¯¥í¥Ã¥¯¤Î¥µ¥¤¥¯¥ë¿ô opt.overstep ¥¯¥í¥Ã¥¯¤Î¥ª¥Ð¡¼¥¹¥Æ¥Ã¥× opt.sorttraces ¥¹¥³¡¼¥×¤Ç¿®¹æ¤òABC½ç¤Çɽ¼¨¤¹¤ë¡£ opt.vpopupdelay ¿®¹æÃÍ¥¦¥£¥ó¥É¤Îɽ¼¨ÃÙ±ä opt.initscript ½é´ü²½¥¹¥¯¥ê¥×¥È opt.posedge Á´¤Æ¤Î¥¯¥í¥Ã¥¯¤ÇÄä»ß¤¹¤ë opt.setclock »ØÄê¤Î¥¯¥í¥Ã¥¯¤ÇÄä»ß¤¹¤ë opt.delayfilepath ÃÙ±ä¥Õ¥¡¥¤¥ë opt.devfilepath VPD(Virtual Periperal Device)¥Õ¥¡¥¤¥ë¤Î¥Ñ¥¹ opt.vlibpath Verilog¤Î¥é¥¤¥Ö¥é¥ê¤Î¥Ñ¥¹ opt.vlibnames ¥Ù¡¼¥¹¤Î¥é¥¤¥Ö¥é¥ê opt.display ²èÌÌ opt.input ÆþÎÏ opt.undolen ºÇÂçUndo opt.keybind ¥­¡¼¡¦¥Ð¥¤¥ó¥Ç¥£¥ó¥°¤Î¥¹¥¿¥¤¥ë opt.useless Ìò¤ËΩ¤¿¤Ê¤¤µ¡Ç½¤òÍ­¸ú¤Ë¤¹¤ë opt.features ´ðËܤε¡Ç½ opt.simbase ´ðËܤΥ·¥ß¥å¥ì¡¼¥¿¤Î¥ª¥×¥·¥ç¥ó opt.simclock ¥¯¥í¥Ã¥¯¤Î¥ª¥×¥·¥ç¥ó opt.cpopts ¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹ÀßÄê: opt.maxpath ºÇÂç¥Ñ¥¹¿ô: opt.cpflash ¥Ñ¥¹¤ÎÅÀÌÇɽ¼¨ opt.general.fontset ¥Õ¥©¥ó¥È¡¦¥µ¥¤¥º opt.simulator.noglitch ¥·¥ß¥å¥ì¡¼¥¿¤Î¥°¥ê¥Ã¥Á¤ÎÍÞÀ© opt.simulator.err ¥¨¥é¡¼°·¤¤ opt.simulator.stopany ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ÎÃé¹ð¤ò¥¨¥é¡¼¤È¤·¤Æ°·¤¨¤ë¡£ opt.simulator.showall ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ÎÃé¹ð¤òɽ¼¨¤¹¤ë¡£ opt.simulator.showiferr ¥¨¥é¡¼¤Î¤¢¤ë»þ¤Î¤ß¡¢Ãé¹ð¤òɽ¼¨¤¹¤ë¡£ opt.simulator.ignore ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ÎÃé¹ð¤ò̵»ë¤¹¤ë¡£ opt.tool.file ¥Õ¥¡¥¤¥ë opt.tool.edit ÊÔ½¸ opt.tool.gateopt ²óž¡¿À°Îó²½ opt.tool.gateprop ¥²¡¼¥ÈÆÃħ opt.tool.undo Undo/Redo opt.tool.zoom ¥º¡¼¥à opt.tool.mode ¥â¡¼¥É opt.tool.module ¥â¥¸¥å¡¼¥ë opt.tool.tech ¥Æ¥¯¥Î¥í¥¸¡¼ opt.tool.simctl ¥·¥ß¥å¥ì¡¼¥¿¤ÎÀ©¸æ opt.tool.simaux ¥·¥ß¥å¥ì¡¼¥¿¤Î¥³¥Þ¥ó¥É opt.tool.symmode ¥â¡¼¥É opt.tool.symedit ¥«¥Ã¥È¡¿¥Ú¡¼¥¹¥È opt.tool.symport ¥Ý¡¼¥È opt.tool.symshift ¥Ó¥Ã¥È¡¦¥Þ¥Ã¥×¤Î¥·¥Õ¥È opt.tool.symopr ¥Ó¥Ã¥È¡¦¥Þ¥Ã¥×¤Î±é»» opt.editor.features ´ðÁÃŪ¤Ê¥¨¥Ç¥£¥¿¡¼¤Îµ¡Ç½ opt.editor.format ¼«Æ°¥¤¥ó¥Ç¥ó¥È¤òÍ­¸ú¤Ë¤¹¤ë opt.editor.colorize ¼«Æ°¿§ÉÕ¤±¤òÍ­¸ú¤Ë¤¹¤ë opt.editor.comments ¥³¥á¥ó¥È opt.editor.strings ʸ»úÎó opt.editor.reserved ¥­¡¼¥ï¡¼¥É opt.editor.gateword ¥²¡¼¥È̾ opt.editor.instword ¥â¥¸¥å¡¼¥ë̾ opt.editor.taskword ¥·¥¹¥Æ¥à¡¦¥¿¥¹¥¯ opt.editor.color ¿§ opt.editor.bold ÂÀ»ú opt.editor.italic ¥¤¥¿¥ê¥Ã¥¯ opt.editor.indentlevel ¥ì¥Ö¥ëËè¤Î¥¤¥ó¥Ç¥ó¥È¤Î¥¹¥Ú¡¼¥¹¿ô opt.editor.beginindent ¡Öbegin..end¡×¤Î¥¤¥ó¥Ç¥ó¥È¤ò°Ï¤Þ¤ì¤ë¤ì¤Ù¤ë¤È²ñ¤ï¤»¤ë¡£ opt.editor.movesel ÁªÂò¤Î¥É¥é¥Ã¥°¡¦¥¢¥ó¥É¡¦¥É¥í¥Ã¥×¤òÍ­¸ú¤Ë¤¹¤ë¡£ opt.editor.returntab ¥ê¥¿¡¼¥ó¤ò²¡¤¹»þ¡¢¼«Æ°¥¤¥ó¥Ç¥ó¥È¤òÍ­¸ú¤Ë¤¹¤ë¡£ opt.vercheck -begin- Äê´üŪ¤Ë tkgate ¤Î¿·¤·¤¤¥Ð¡¼¥¸¥ç¥ó¤ò¥¤¥ó¥¿¡¼¥Í¥Ã¥È¤Ç ¥Á¥§¥Ã¥¯¤¹¤ë¡£¾ï»þÀܳ¤Ç¤Ê¤±¤ì¤ÐÍ­¸ú¤Ë¤·¤Ê¤¤¤³¤È¡£ -end- opt.general.cap °ìÈÌ¥ª¥×¥·¥ç¥ó opt.editor.cap HDL¥Æ¥­¥¹¥È¡¦¥¨¥Ç¥£¥¿ opt.interface.cap ¥¤¥ó¥¿¥Õ¥§¥¹¡¦¥ª¥×¥·¥ç¥ó opt.toolbars.cap ¥Ä¡¼¥ë¥Ð¡¼¡¦¥ª¥×¥·¥ç¥ó opt.print.cap °õºþ¥ª¥×¥·¥ç¥ó opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap ¥·¥ß¥å¥ì¡¼¥¿¡¦¥ª¥×¥·¥ç¥ó opt.security.cap ¥»¥­¥å¥ê¥Æ¥£¡¦¥ª¥×¥·¥ç¥ó opt.color.cap ¿§¤Å¤±¡¦¥ª¥×¥·¥ç¥ó opt.html.cap HTML/HTTP¥ª¥×¥·¥ç¥ó opt.debug.cap ¥Ç¥Ð¥Ã¥°¡¦¥ª¥×¥·¥ç¥ó opt.library.cap ¥é¥¤¥Ö¥é¥ê¡¦¥ª¥×¥·¥ç¥ó opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.color.editwin ÊÔ½¸¥¦¥£¥ó¥É¥¦¤Î¿§¤Å¤± opt.color.scopewin ¥¹¥³¡¼¥×¡¦¥¦¥£¥ó¥É¥¦¤Î¿§¤Å¤± opt.vlibadd.cap ¥é¥¤¥Ö¥é¥êÄɲà opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- ¥¢¥¤¥Ç¥ó¥Æ¥£¥Æ¥£¡¼¡¢´ðËÜÀßÄê¤ò¤¹¤ë¡£¥¢¥¤¥Ç¥ó¥Æ¥£¥Æ¥£¡¼¤Ï°õºþ¤¹¤ë»þ¤Ê¤ÉÍѤ¤¤é¤ì¤ë¡£ -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore ¥Ú¡¼¥¸¤ÎÀßÄê¤ò¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë opt.bbar.restoreall Á´¤Æ¤ÎÀßÄê¤ò¥Ç¥Õ¥©¥ë¥È¤Ë¤¹¤ë ############################################################################## # # Interface generator # igen.port ¥Ý¡¼¥È igen.type ¥¿¥¤¥× igen.side ¥µ¥¤¥É igen.size ¥Ó¥Ã¥ÈÉý igen.bits ¥Ó¥Ã¥È igen.modname ¥â¥¸¥å¡¼¥ë̾: igen.resort ºÆ¥½¡¼¥È igen.add Äɲà igen.delete ºï½ü igen.edit ÊÔ½¸ igen.in Æþ igen.out ½Ð igen.inout Æþ½Ð igen.left º¸ igen.right ±¦ igen.top ¾å igen.bottom ²¼ igen.other ¾ igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error ¥¹¥¯¥ê¥×¥È¤Î¥¨¥é¡¼ module.props ¥â¥¸¥å¡¼¥ë¤ÎÆÃħ ipanel.plist ¥Ý¡¼¥È¤Î°ìÍ÷ɽ ipanel.props ¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ÎÆÃħ ipanel.itype.change ¥¿¥¤¥×¤ÎÊѹ¹... ipanel.itype.edsymbol ¥·¥ó¥×¥ë¤ÎÊÔ½¸... ipanel.block ¥Ö¥í¥Ã¥¯ ipanel.symbol ¥·¥ó¥Ü¥ë ipanel.autogen ¼«Æ°ºîÀ®... ipanel.itype.select ¥¤¥ó¥¿¥Õ¥§¥¹¡¦¥¿¥¤¥× ipanel.itype.selectexp -begin- ĹÊý·Á·¿¤Î¡Ö¥Ö¥í¥Ã ¥¯¡×¤«¡¢¥Ó¥Ã¥È¥Þ¥Ã ¥×¤Î¡Ö¥·¥ó¥Ü¥ë¡×¡¢ ¤¤¤º¤ì¤«ÁªÂò¤·¤Æ ¤¯¤À¤µ¤¤¡£ -end- ipanel.block.description TODO: Block Interface ipanel.symbol.description TODO: Custom Symbol Interface ipanel.ppos.label ¥Ö¥í¥Ã¥¯¤Î¥µ¥¤¥º¤òÊѹ¹¤¹¤ë»þ¤Î¥Ý¡¼¥È¤Î¼è¤ê°·¤¤ ipanel.ppos.fix »ØÄê ipanel.ppos.scale ¥¹¥±¡¼¥ë ipanel.ppos.grid ¥°¥ê¥Ã¥É ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim ¼èÆÀ¤¹¤ë¥â¥¸¥å¡¼¥ë̾ blklst.to ¿·µ¬¥â¥¸¥å¡¼¥ë̾ blklst.from ¸½ºß¥â¥¸¥å¡¼¥ë̾ blklst.name ¥â¥¸¥å¡¼¥ë̾ blklst.new.cap ¥â¥¸¥å¡¼¥ë¤Î¿·µ¬ºîÀ® blklst.del.cap ºï½ü¤¹¤ë¥â¥¸¥å¡¼¥ë̾ blklst.copy.cap ¥³¥Ô¡¼¡¦¥â¥¸¥å¡¼¥ë blklst.rename.cap ¥â¥¸¥å¡¼¥ë¤Î²þ̾ blklst.claim.cap ¥â¥¸¥å¡¼¥ë¤Î¼èÆÀ blklst.setroot.cap ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤ÎÁªÂò blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label õº÷ find.exp -fillbegin- ¥²¡¼¥È̾¡¢¥Í¥Ã¥È̾¡¢ ¥³¥á¥ó¥È¤Ê¤É¤ÎÃæ¤Ë »ØÄꥹ¥È¥ê¥ó¥°¤ò õº÷¤¹¤ë¡£ -end- find.ignorecase ¥±¡¼¥¹¤ò̵»ë¤¹¤ë¡£ find.result.module ¥â¥¸¥å¡¼¥ë̾ find.result.type ¥¿¥¤¥× find.result.name ¥ª¥Ö¥¸¥§¥¯¥È̾ # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options õº÷¤Î¥ª¥×¥·¥ç¥ó find.results õº÷¤Î·ë²Ì # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ¤ò´Þ¤à find.qual.begins ¤«¤é»Ï¤Þ¤ë find.qual.ends ¤Ç½ª¤ë find.qual.matches ƱÅù¤¹¤ë find.dom.label °Ê²¼¤Î¾ì½ê¤òõº÷¤¹¤ë¡£ find.dom.gates ¥²¡¼¥È find.dom.nets ¥Í¥Ã¥È find.dom.text ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È find.search õº÷: find.target õº÷¤ÎÈÏ°Ï # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label ²óÏ©¤ÎÆÃħ circ.ident TODO: Identification circ.filev ¥Õ¥¡¥¤¥ë¤Î¥Ð¡¼¥¸¥ç¥ó circ.file ¥Õ¥¡¥¤¥ë̾ circ.title ²óϩ̾ circ.discchg Êѹ¹¤ò̵»ë¤¹¤ë circ.extbar ³ÈÄ¥¥Ð¡¼¤òÍøÍѤ¹¤ë¡£ circ.autostart ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î¼«Æ°³«»Ï¤òÍ­¸ú¤Ë¤¹¤ë¡£ circ.iniscript ½é´ü²½¥¹¥¯¥ê¥×¥È circ.noscript ¥¹¥¯¥ê¥×¥È¡¦¥Õ¥¡¥¤¥ë¤Ï»ØÄꤵ¤ì¤Æ¤¤¤Ê¤¤¡£ circ.really TODO: Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general °ìÈÌ circ.library ¥é¥¤¥Ö¥é¥ê circ.script ¥¹¥¯¥ê¥×¥È circ.simulator ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # # Library Manager # libmgr.cap ¥é¥¤¥Ö¥é¥ê¡¦¥Þ¥Í¥¸¥ã¡¼ libmgr.library ¥é¥¤¥Ö¥é¥ê̾ libmgr.description ÀâÌÀ libmgr.status ¾õÂÖ libmgr.status.load ÍøÍÑ libmgr.status.unload ÈóÍøÍÑ libmgr.status.loadp TODO: [ÍøÍÑ] libmgr.status.unloadp TODO: [ÈóÍøÍÑ] libmgr.exp -begin- ÍøÍѤ¹¤ë¥é¥¤¥Ö¥é¥ê¤òÁªÂò¤¹¤ë¡£ -end- libmgr.load ÍøÍÑ libmgr.unload ÈóÍøÍÑ libmgr.unloadall Á´¤Æ¤òÈóÍøÍÑ libmgr.notedit -fillbegin- ²óÏ©¿Þ¤Î¥¨¥Ç¥£¥¿¤¬³«¤¤¤Æ¤¤¤ë»þ¤Î¤ß¡¢ ¥é¥¤¥Ö¥é¥ê¤Î¥Þ¥Í¥¸¥ã¡¼¤¬ÍøÍѽÐÍè¤ë¡£ -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È break.id ÈÖ¹æ break.state ¾õ break.condition ¾ò·ï break.value ÃÍ ############################################################################## # Simulator # sim.breakpt ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay ¥Ñ¥¹ÃÙ±ä: cp.pathl ¥Ñ¥¹¤Î°ìÍ÷: cp.numpath ¥Ñ¥¹¿ô: cp.recompute ºÆ·×»» ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin ÁªÂò¤µ¤ì¤¿¥Ô¥ó¤Î¥¿¥¤¥×¤òÊѹ¹½ÐÍè¤Ê¤¤¡£ err.badhex ÉÔÀµ¤Î16¿Ê¿ô¤ÎÃͤÏ̵»ë¤µ¤ì¤¿¡£ err.gatanchor ¥²¡¼¥È¤¬°ÜÆ°ÉԲĤ˥ޡ¼¥¯¤µ¤ì¤Æ¤¤¤ë°Ù¡¢°ÜÆ°½ÐÍè¤Ê¤¤¡£ err.protdata TODO: Can not modify contents of protected or library module. err.badfind õº÷¥¹¥È¥ê¥ó¥°¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.badopendel »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤òºï½ü½ÐÍè¤Ê¤¤¡£ err.nosrcmod ¥½¡¼¥¹¡¦¥â¥¸¥å¡¼¥ë'%s'¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.noerr ¥¨¥é¡¼¡¦¥á¥Ã¥»¡¼¥¸¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.misserr ¥¨¥é¡¼¾ðÊó¤¬ÉÔ´°Á´¤Ç¤¢¤ë¡£(¥·¥ß¥å¥ì¡¼¥¿¤¬Íî¤Á¤¿¡©) err.badinadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦ÆþÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badoutadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦½ÐÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badinoutadd ÁªÂò¤Î¥²¡¼¥È¤Ë¤â¤¦Æþ½ÐÎÏÄɲ䬽ÐÍè¤Ê¤¤¡£ err.badpinchg ÁªÂò¤Î¥²¡¼¥È¤Î¥Ô¥ó¤Î¥¿¥¤¥×¤¬Êѹ¹½ÐÍè¤Ê¤¤¡£ err.badnetname ̾Á°¤ËÉÔÀµ¤Îʸ»ú¤¬¤¢¤ë°Ùºï½ü¤µ¤ì¤¿¡£ err.netbcrename »ØÄê¤Î̾Á°¤ËÉÔÀµ¤Îʸ»ú¤¬¤¢¤ë°Ù¡¢¡Ö%s¡×¤ËÊѹ¹¤µ¤ì¤¿¡£ err.netconfnet »ØÄê¤Î̾Á°¤¬Ê̤Î̾Á°¤È¾×Æͤ¹¤ë°Ù¡¢¡Ö%s¡×¤ËÊѹ¹¤µ¤ì¤¿¡£ err.netconfgat »ØÄê¤Î̾Á°¤¬´ðÁäΥ²¡¼¥È̾¤È¾×Æͤ¹¤ë°Ù¡¢¡Ö%s¡×¤ËÊѹ¹¤µ¤ì¤¿¡£ err.netconfkw »ØÄê¤Î̾Á°¤¬¥­¡¼¥ï¡¼¥É¤È¾×Æͤ¹¤ë°Ù¡¢¡Ö%s¡×¤ËÊѹ¹¤µ¤ì¤¿¡£ err.badconsame ¥Í¥Ã¥È¤¬Æ±¤¸¤Ê¤Î¤Ç¡¢Àܳ½ÐÍè¤Ê¤¤¡£ err.badconptsp ¥Í¥Ã¥È¤ÎξÊý¤¬¥Ý¡¼¥ÈËô¤ÏÅÅÎϤʤΤǡ¢Àܳ½ÐÍè¤Ê¤¤¡£ err.badconbitw ¥Í¥Ã¥È¤Î¥Ó¥Ã¥ÈÉý¤¬°Û¤Ê¤ë¤Î¤Ç¡¢Àܳ½ÐÍè¤Ê¤¤¡£ err.badrange »ØÄꤵ¤ì¤¿»þ´Ö¤Î¥ì¥ó¥¸¤¬ÉÔÀµ¤Ç¤¢¤ë¡£ err.badlprcmd °õºþ¥³¥Þ¥ó¥É¡Ö%s¡×¤¬¼Â¹Ô½ÐÍè¤Ê¤¤¡£ err.badpsopen ¥Ý¥¹¥È¡¦¥¹¥¯¥ê¥×¥È¤ò¡Ö%s¡×¤Ë½ñ¤­¹þ¤á¤Ê¤¤¡£ err.badid ¡Ö%s¡×¤ÏÉÔÀµ¤Î̾Á°¤Ç¤¢¤ë¡£ err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp ÉÔÀµ¤Ê¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤Î¾ò·ï¤Ç¤¢¤ë¡£¡Önet¡×, ¡Ö!net¡×, ¡Önet==value¡×, ¡Önet!=value¡×¤Î¤É¤ì¤«¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ err.bkpt.badnet ÉÔÀµ¤Î¥Í¥Ã¥È̾¤Ç¤¢¤ë¡£ err.bkpt.badval ÉÔÀµ¤ÎÃͤǤ¢¤ë¡£10¿Ê¿ô¤¢¤ë¤¤¤Ï¡¢verilog·Á¼°¤ÎÃͤ·¤«Ç§¼±¤µ¤ì¤Æ¤¤¤Ê¤¤¡£ err.bkpt.toomany ¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È¤¬Â¿²á¤®¤ë¡£À©¸Â¤Ï%d¤Ç¤¢¤ë¡£ err.sim.badtmp /tmp¤Î¥Õ¥¡¥¤¥ë¤¬½ñ¤­¹þ¤á¤Ê¤«¤Ã¤¿¡Ê¥Ç¥£¥¹¥¯¤¬¤¤¤Ã¤Ñ¤¤¤«¡Ë¡£ err.sim.syntx ÉÔÀµ¤Î¡Ö%s¡×¥³¥Þ¥ó¥É err.sim.noincl ¥¤¥ó¥¯¥ë¡¼¥É¡¦¥Õ¥¡¥¤¥ë¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤«¤Ã¤¿¡£ err.sim.badedge clock¥³¥Þ¥ó¥É¤Î¥¨¥Ã¥¸'%c'¤¬ÉÔÀµ¤Ç¤¢¤ë¡£ err.sim.nobkpt ¥Ö¥ì¡¼¥¯¡¦¥Ý¥¤¥ó¥È¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.sim.nonet ¥Í¥Ã¥È¡Ö%s¡×¤ÏÄêµÁ¤·¤Æ¤¤¤Ê¤¤¡£ err.sim.nogate ¥²¡¼¥È¡Ö%s¡×¤ÏÄêµÁ¤·¤Æ¤¤¤Ê¤¤¡£ err.sim.badbin 2¿Ê¿ô¤ÎÃͤËÉÔÀµ¤Îʸ»ú¤¬¤¢¤ë¡£ err.sim.notswitch ¥²¡¼¥È'%s'¤Ï¥¹¥¤¥Ã¥Á¡¢DIP¡¢¥ì¥¸¥¹¥¿¤Î¤É¤ì¤«¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ err.sim.badcmd ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥¹¥¯¥ê¥×¥È¤ËÉÔÀµ¤Î¥³¥Þ¥ó¥É¡Ö%s¡×¤¬¤¢¤ë¡£ err.sim.isrun ¥·¥ß¥å¥ì¡¼¥¿¤Ï´û¤Ë¼Â¹Ô¤·¤Æ¤¤¤ë¡£ ('Ctrl-s e'¤Ç½ªÎ»¤¹¤ë). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg ÀßÄê¤ÏÊÔ½¸¥â¡¼¥É°Ê³°¡¢Êѹ¹ÉԲġ£ err.badeditop ÊÔ½¸¥³¥Þ¥ó¥É¤ËÉÔÀµ¤¬¤¢¤ë¡£ err.badopen ²óÏ©¥Õ¥¡¥¤¥ë¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.badlibopen ¥é¥¤¥Ö¥é¥ê¡¦¥Õ¥¡¥¤¥ë¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.nomark ¥²¡¼¥È¼ï¤òÁª¤ÖÁ°¤Ë¡¢¥Þ¥¦¥¹¤Ç°ÌÃÖ¤òÀßÄꤷ¤Æ¤¯¤À¤µ¤¤¡£ err.badgate ¥²¡¼¥È¼ï¤¬Ì¤ÄêµÁ¤Ç¤¢¤ë¡£ err.badportadd ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤Ë¥Ý¡¼¥È¤ÏÄɲÃÉԲġ£ err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- ¥Ú¡¼¥¸¿ô¤¬¶Ë¤á¤ÆÂ礭¤¤¡£ ËÜÅö¤Ë°õºþ¤·¤Þ¤¹¤«? -end- err.nojump -fillbegin- ¸½ºß¡¢'jump-to-module'µ¡Ç½¤Ï¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç»ÈÍѽÐÍè¤Ê¤¤¡£ ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤è¤ê¡¢¡Ö>¡×¤ä¡Ö<¡×¤Î¥³¥Þ¥ó¥É¤Ç¥â¥¸¥å¡¼¥ë¤ò³«¤±¤Æ¤¯¤À¤µ¤¤¡£ -end- err.nomod ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤ÏÄêµÁ¤·¤Æ¤¤¤Ê¤¤¡£ err.modlock ¥â¥¸¥å¡¼¥ë¤¬¥í¥Ã¥¯¤·¤Æ¤¤¤ë¡£ err.closeroot ¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤¬ÊĤ¸¤ì¤Ê¤¤¡£ err.editonly ¥³¥Þ¥ó¥É¤Ï¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç»È¤¨¤Ê¤¤¡£ err.simonly ¥³¥Þ¥ó¥É¤Ï¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¤·¤«»È¤¨¤Ê¤¤¡£ err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel ¥²¡¼¥È¤òÁªÂò¤·¤Æ¤¤¤Ê¤¤¡£ err.modnotdef ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤ÏÄêµÁ¤·¤Æ¤¤¤Ê¤¤¡£ err.moddef ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬´û¤ËÄêµÁ¤·¤Æ¤¤¤ë¡£ err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÏÊÔ½¸½ÐÍè¤ëÀßÄ꤬¤Ê¤¤¡£ err.openscript ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥¹¥¯¥ê¥×¥È¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤¤¡£ err.oldversion ²óÏ©¥Õ¥¡¥¤¥ë¤Î¥Ð¡¼¥¸¥ç¥ó(%s)¤¬¸Å¤¤¡£(¸½ºß¤Î¥Ð¡¼¥¸¥ç¥ó¤Ï%s). err.futureversion ̤Íè¤Î¥Ð¡¼¥¸¥ç¥ó¡Ê%s¡Ë¤Îtkgate¥Õ¥¡¥¤¥ë¤Ç¤¢¤ë¡£¡Ê¸½ºß¤Î¥Ð¡¼¥¸¥ç¥ó¤Ï%s¡Ë err.badversion ²óÏ©¥Õ¥¡¥¤¥ë¤Î¥Ð¡¼¥¸¥ç¥ó¤¬Ç§¼±½ÐÍè¤Ê¤¤¡£Ãí°Õ¤·¤ÆÍøÍѲ¼¤µ¤¤¡£ err.nodrive ¥Í¥Ã¥È%s¤Ï¥â¥¸¥å¡¼¥ë%s¤Ë¿®¹æ¤Î¥½¡¼¥¹¤¬¤Ê¤¤¡£ err.noconn ¥ï¥¤¥ä%s{%d}¤ÏÀܳ¤¬¤Ê¤¤¡Êºï½ü¤·¤¿¡Ë¡£ err.oldportact ¥Ý¡¼¥È¤ä¥â¥¸¥å¡¼¥ë¤Îü¤Ë±¦¥¯¥ê¥Ã¥¯¤·¤Æ²¼¤µ¤¤¡£ err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail ¥Ð¥Ã¥¯¥¢¥Ã¥×¡¦¥Õ¥¡¥¤¥ë'%s'¤¬ºîÀ®½ÐÍè¤Ê¤«¤Ã¤¿¡£ err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TkGate¤Ï'%s'¤Ë¥»¡¼¥Ö½ÐÍ褿¤¬¡¢¥Õ¥¡¥¤¥ë¤¬º®Í𤵤ì¤Æ¤¤¤ë¤ß¤¿¤¤¡£¤â¤·¥Á¥§¥Ã ¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯ ¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.corruptsave -fillbegin- '%s'¤ò¥»¡¼¥Ö¤·¤è¤¦¤È¤·¤Æ¤¤¤ë»þ¡¢TkGate¤ËÆâÉôÌäÂ꤬ȯ¸«¤·¤¿¡£¸µ¡¹¤Î¥Õ¥¡¥¤ ¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä¤·¤Æ¤¢¤ë¡£º®Í𤵤ì¤Æ¤¤¤ë²ÄǽÀ­¤Î¤¢¤ë¥Õ¥¡¥¤¥ë¤Ï'%s'¤Ë¥»¡¼¥Ö ¤·¤¿¡£¤â¤·¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤òÍøÍѤ·¤Æ¤¤¤ì¤Ð¡¢¥Á¥§¥Ã¥¯¡¦¥Ý¥¤¥ó¥È¤Î¥Õ¥¡¥¤ ¥ë¤ò»È¤Ã¤Æ¤ß¤Æ¤¯¤À¤µ¤¤¡£'tkgate -V'¤Ç¥Õ¥¡¥¤¥ë¤ò¥Á¥§¥Ã¥¯½ÐÍè¤ë¡£ -end- err.badsave -fillbegin- '%s'¤ò¥»¡¼¥Ö½ÐÍè¤Ê¤«¤Ã¤¿¡£¥Õ¥¡¥¤¥ë¤Î¥×¥í¥Æ¥¯¥·¥ç¥ó¤ä¶õ¤­¥Ç¥£¥¹¥¯Î̤ò³Îǧ ¤·¤Æ¤¯¤À¤µ¤¤¡£ -end- err.nosafesave -fillbegin- '%s'¤Î°ÂÁ´¥»¡¼¥Ö¤ò¹Ô¤¦¤¿¤á¤Î°ì»þ¤Î¥Õ¥¡¥¤¥ë¤¬ºîÀ®½ÐÍè¤Ê¤«¤Ã¤¿¤«¤é¡¢Ä¾ÀÜ¥»¡¼ ¥Ö¤·¤Ê¤¯¤Æ¤Ï¤Ê¤é¤Ê¤¤¡£¡ÖNO¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¸µ¡¹¤Î¥Õ¥¡¥¤¥ë¤Ï¤½¤Î¤Þ¤Þ»Ä ¤¹¡£¡ÖYES¡×¤Ë¥¯¥ê¥Ã¥¯¤¹¤ì¤Ð¡¢¥»¡¼¥Ö¤¹¤ë¤¬¡¢¥»¡¼¥ÖÅÓÃæ¤ËÌäÂ꤬µ¯¤³¤Ã¤¿¤é¡¢ ²óÏ©¥Ç¡¼¥¿¤¬Ç˲õ¤µ¤ì¤ë²ÄǽÀ­¤¬¤¢¤ë¡£Ä¾ÀÜ¥»¡¼¥Ö¤·¤Æ¤ß¤Þ¤·¤ç¤¦¤«¡£ -end- err.noback -fillbegin- tkgate¥Ð¡¼¥¸¥ç¥ó%s¤Çºî¤é¤ì¤¿¥Õ¥¡¥¤¥ë¤Ç¤¢¤ë¡£Êݸ¤¹¤ë¤È¡¢ tkgate¤Î¸Å¤¤¥Ð¡¼¥¸¥ç¥ó¤ËÆɤ߹þ¤á¤Ê¤¤¤³¤È¤¬¤¢¤ë¡Ê¸½ºß¤Î ¥Ð¡¼¥¸¥ç¥ó¤Ï%s¤Ç¤¢¤ë¡Ë¡£ -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire %s¤È¤¤¤¦¥ï¥¤¥ä¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.selgate %2$s¤È¤¤¤¦%1$s¥²¡¼¥È¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.selblock %2$s¤È¤¤¤¦%1$s¥â¥¸¥å¡¼¥ë¤¬ÁªÂò¤µ¤ì¤¿¡£ msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤¬´û¤ËÄêµÁ¤µ¤ì¤Æ¤¤¤ë¡£ÄêµÁ¤·¤Ê¤ª¤·¤Þ¤¹¤«? msg.foundgate %s¤È¤¤¤¦¥²¡¼¥È¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.foundwire %s¤È¤¤¤¦¥ï¥¤¥ä¤¬¸«¤Ä¤«¤Ã¤¿¡£ msg.searchagn õº÷¥¹¥È¥ê¥ó¥°¡Ö%s¡×¤¬¸«¤Ä¤«¤é¤Ê¤«¤Ã¤¿¡£¤â¤¦°ìÅÙ¡Öõº÷¡×¤ò²¡¤¹¤È¡¢Ãµº÷¤·¤Ê¤ª¤¹¡£ msg.sim.chgtoroot ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¤Ï¡¢¥È¥Ã¥×¡¦¥â¥¸¥å¡¼¥ë¤¬¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤Î¥È¥Ã¥×¤Ç¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤¡£ msg.sim.nogatemod ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¡¦¥â¡¼¥É¤Ç¡¢¶ñÂÎŪ¤Ê¥â¥¸¥å¡¼¥ë¡¦¥¹¥¿¥Ã¥¯¤¬É¬ÍפǤ¢¤ë¡£ msg.setinterface ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Î¥¤¥ó¥¿¥Õ¥§¡¼¥¹¤ò¥»¥Ã¥È¤·¤¿¡£ msg.needsel ¥â¥¸¥å¡¼¥ë¤Î¥¤¥ó¥¹¥¿¥ó¥¹¤òÁª¤ó¤Ç¤¯¤À¤µ¤¤¡£ msg.wroteckpt ¡Ö%s¡×¤Ë¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥È¤ò½ñ¤­¹þ¤ó¤À... msg.save ¡Ö%s¡×¤ËÊݸ¤·¤¿¡£ msg.reallynew ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢¿·¤·¤¤²óÏ©¤ò³«¤­¤Þ¤¹¤«? msg.reallyquit ²óÏ©¤ËÊѹ¹¤¬¤¢¤ë¡£ËÜÅö¤ËÊݸ¤·¤Ê¤¤¤Ç¡¢½ªÎ»¤·¤Þ¤¹¤«? msg.notlib ¥â¥¸¥å¡¼¥ë¡Ö%s¡×¤Ï¥é¥¤¥Ö¥é¥ê¡¦¥â¥¸¥å¡¼¥ë¤Ç¤Ï¤Ê¤¤¡£ ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ¤½¤Î°ÌÃ֤˥²¡¼¥È¤òÃÖ¤¯¤Î¤Ï¡¢¤ªÁ°¤ß¤¿¤¤¤ÊÂçÇϼ¯¤·¤«¤¤¤Ê¤¤¤è¡£ miles.msg2 Çϼ¯¡ª miles.msg3 ¶ò¤«¤â¤Î¡ª miles.msg4 ¥Þ¥¤¥ë¥¹¡¢¤½¤Î°ÌÃ֤˥²¡¼¥È¤òÃÖ¤¯¤Î¤Ï¡¢Çϼ¯¤À¤è¡£ miles.msg5 Çϼ¯¤Ê¥²¡¼¥È¤Î°ÌÃÖÉÕ¤±¤ò¤ä¤á¤Æ¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg6 ¥²¡¼¥È¤ò¤½¤Î°ÌÃ֤ˤª¤¤¤¿¤Î¤Ï¡¢¤ªÁ°¤Î¶ò¤«¤µ¤Î¾ÚÌÀ¤À¤è¡£ miles.msg7 ¤³¤Î¥í¥¯¤Ç¤Ê¤·²óÏ©¤ÎÀ߷פòÄü¤á¤è¡¢¥Þ¥¤¥¹¥ë¡£ miles.msg8a ³¤±¤Æ¤â¡¢ÌµÂ̤À¤è¡¢¥Þ¥¤¥ë¥¹¡£ miles.msg8b ¤ªÁ°¤¬²óÏ©¤òÀß·×½ÐÍè¤Ê¤¤¤È¤¤¤¦¤Î¤Ï¡¢Ã¯¤Ç¤âʬ¤«¤ë¤è¡£ ############################################################################# # # Error messages generated by verga # verga.err.OK ¿´ÇÛ¤·¤Ê¤¤¤Ç¡¢¾Ð¤Ã¤Æ¤¯¤À¤µ¤¤¡£ verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # Balloon Help # ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ¸½ºß¤Î²óÏ©¤ò¾Ã¤·¤Æ¡¢¿·¤·¤¤ ²óÏ©¤òºîÀ®¤¹¤ë¡£ -end- ho.open ²óÏ©¥Õ¥¡¥¤¥ë¤ò³«¤¯ ho.save ²óÏ©¥Õ¥¡¥¤¥ë¤òÊݸ¤¹¤ë ho.saveas TODO: Save circuit to specified file. ho.print ²óÏ©¥Õ¥¡¥¤¥ë¤ò°õºþ¤¹¤ë ho.library TODO: Open the library manager. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- °ÜÆ°¡¿Àܳ - ¤³¤Î¥Ä¡¼¥ë¤Ç°Ê²¼¤Îµ¡Ç½¤¬»È¤¨¤ë ¿·¤·¤¤¥²¡¼¥È¤Î°ÌÃÖ¤òÀßÄꤹ¤ë ¥²¡¼¥È¤ò°ÜÆ°¤¹¤ë ¥ï¥¤¥ä¤ò°ÜÆ°¤¹¤ë ¥ï¥¤¥ä¤òÀܳ¤¹¤ë ¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤Ç°Ê²¼¤Îµ¡Ç½¤¬»È¤¨¤ë ¥²¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë ¥ï¥¤¥ä¤Î°À­¤òÊÔ½¸¤¹¤ë ¥Ý¡¼¥È¤Î°À­¤òÊÔ½¸¤¹¤ë ¥³¥á¥ó¥È¤Î¥Æ¥­¥¹¥È¤Î°À­¤òÊÔ½¸¤¹¤ë -end- ho.delgat -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥²¡¼¥È¤òºï½ü¤¹¤ë -end- ho.cutw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤òÀÚÃǤ¹¤ë -end- ho.inv -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¡¢¥²¡¼¥È¤ÎÆþ½ÐÎÏ¤Ë ÈÝÄê¤òÉÕ¤±¤¿¤ê¡¢¾Ã¤·¤¿¤ê¤¹¤ë¡£ -end- ho.bitw -begin- ¤³¤Î¥Ä¡¼¥ë¤Ç¥ï¥¤¥ä¤Î¥Ó¥Ã¥ÈÉý¤ò Êѹ¹¤¹¤ë¡£¥Ó¥Ã¥ÈÉý¤ò±¦²¼¤ÎÆþÎÏ ¥Ü¥Ã¥¯¥¹¤ËÆþÎϤ·¤Æ¤¯¤À¤µ¤¤¡£ -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open ÁªÂò¤µ¤ì¤¿¥â¥¸¥å¡¼¥ë¤ò³«¤¯ ho.mod.close ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤òÊĤ¸¤ë ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo ºÇ¶á¹Ô¤Ã¤¿ÊѲ½¤ò¸µÄ̤ê¤Ë¤¹¤ë¡£ ho.redo undo¤·¤¿ÊѲ½¤ò¤ä¤êľ¤¹¡£ ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò³«»Ï¤·¡¢ÏÀÍý¥¢¥Ê¥é¥¤¥¶¤Î¥¦¥£¥ó¥É¤ò ³«¤­¡¢¤½¤·¤Æ½é´ü²½¥¹¥¯¥ê¥×¥È¤¬ÄêµÁ¤·¤Æ¤¤¤ë¾ì¹ç¡¢ ¤½¤Î¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.tab.cpath -begin- ²óÏ©¤Î¥¯¥ê¥Æ¥£¥«¥ë¡¦¥Ñ¥¹¤òõº÷¤¹¤ë¡£ -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÆ°¤«¤¹¡£Áȹ礻²óÏ©¤Î¾ì¹ç¡¢ ¿®¹æ¤¬ÊѤï¤é¤Ê¤¯¤Ê¤ë»þ¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö ¤¬°ì»þÄä»ß¤¹¤ë¡£ -end- ho.simpause -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î°ì»þÄä»ß -end- ho.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¨¥Ý¥Ã¥¯¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simclock -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ò°ìÄê¿ô¤Î¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë ¤À¤±Æ°¤«¤¹¡£ ¥¹¥Æ¥Ã¥×¿ô¤Ï¥·¥ß¥å¥ì¡¼¥È¤ÎÀßÄê¤Ë¤è¤ë¡£ -end- ho.simstop -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òÄä»ß¤·¤Æ¡¢ ÊÔ½¸¥â¡¼¥É¤ËÌá¤ë¡£ -end- ho.simbreak -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥Ö¥ì¡¼¥¯¥Ý¥¤¥ó¥È ¤òÊÔ½¸¤¹¤ë¡£ -end- ho.simexec -begin- ¥¹¥¯¥ê¥×¥È¤ò¼Â¹Ô¤¹¤ë¡£ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤òÆɤ߹þ¤à -end- ho.simdump -begin- ¥á¥â¥ê¡¦¥Õ¥¡¥¤¥ë¤Ë½ñ¤­½Ð¤¹ -end- ho.f.modlist -begin- Æɤ߹þ¤ó¤Ç¤¢¤ë¥â¥¸¥å¡¼¥ë¤Î°ìÍ÷ɽ¡£ ¥È¥Ã¥×¤Î¥â¥¸¥å¡¼¥ë¤Î̾Á°¤Ë¡Ö+¡×¤¬ ÉÕ¤¤¤Æ¤¤¤ë¡£¥é¥¤¥Ö¥é¥ê¤Î¥â¥¸¥å¡¼¥ë ¤Ï³ç¸Ì¤Ë°Ï¤Þ¤ì¤Æ¤¤¤ë¡£ -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î°ìÍ÷ɽ¡£Ì¾Á°¤ò±£¤·¤Æ ¤¤¤ë¥Í¥Ã¥È¤Î̾Á°¤Ë¡Ö@¡×¤¬ÉÕ¤¤¤Æ¤¤¤ë¡£ ¥Þ¥ë¥Á¡¦¥Ó¥Ã¥È¤Î¥Í¥Ã¥È¤Î̾Á°¤Î¸å¤Ë ¥Ó¥Ã¥È¤Î¥ì¥ó¥¸¤òɽ¼¨¤·¤Æ¤¤¤ë¡£ -end- ho.ports -begin- ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ý¡¼¥È¤Î°ìÍ÷ɽ¡£ ÆþÎϤˡÖ>¡×¡¢½ÐÎϤˡÖ<¡×¡¢Æþ½ÐÎÏ¤Ë ¡Ö=¡×¤¬ÉÕ¤¤¤Æ¤¤¤ë¡£ -end- ho.status.logo -begin- ¸½ºß¤Î¥â¡¼¥É¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£Å´¤Î¥²¡¼¥È ¤ÏÊÔ½¸¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤Ï¥·¥ß¥å¥ì¡¼ ¥·¥ç¥ó¡¦¥â¡¼¥É¤òɽ¤¹¡£AND¥²¡¼¥È¤¬Áö¤Ã¤Æ ¤¤¤ë»þ¡¢¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î»þ´Ö¤¬Æ°¤¤¤Æ¤¤¤ë¡£ -end- ho.status.msg tkgate¤è¤ê¤Î¥á¥Ã¥»¡¼¥¸¤¬¤³¤³¤Ëɽ¼¨¤µ¤ì¤ë¡£ ho.status.block ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¥Ñ¥¹ ho.status.file -begin- ¸½ºßÊÔ½¸Ãæ¤Î¥Õ¥¡¥¤¥ë̾¤¬É½¼¨¤µ¤ì¤Æ¤¤¤ë¡£¡Ö*¡× ¤È¤¤¤¦µ­¹æ¤¬¤Ä¤¤¤Æ¤¤¤ë»þ¡¢Êݸ¤·¤Æ¤¤¤Ê¤¤Êѹ¹ ¤¬¤¢¤ë¡£ -end- ho.print.selall Á´¤Æ¤ÎÆɤ߹þ¤ó¤Ç¤¤¤ë¥â¥¸¥å¡¼¥ë¤ò°õºþ¤¹¤ë¡£ ho.print.selcur ¸½ºß¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ho.print.seluse -begin- »ÈÍÑÃæ¤Î¥â¥¸¥å¡¼¥ë¤Î¤ß°õºþ¤¹¤ë¡£ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- °Ê²¼¤Ë¥Þ¡¼¥¯¤·¤Æ¤¤¤ë¥â¥¸¥å¡¼¥ë¤Î¤ß¤ò°õºþ¤¹¤ë¡£ ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ÇÊ£¿ô¤Î¥â¥¸¥å¡¼¥ë¤òÁªÂò ½ÐÍè¤ë¡£ -end- ho.print.modlist °õºþ¤¹¤ë¥â¥¸¥å¡¼¥ë¤òÁªÂò¤¹¤ë¡£ ho.circuit.discchg -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢Êѹ¹¤¢¤ê¤Î²óÏ©¤ò Êݸ¤·¤Ê¤¤¤ÇÊĤ¸¤ë¤È¤­·Ù¹ð¤·¤Ê¤¤¡£ -end- ho.circuit.extbar -begin- ´ðËÜ¥²¡¼¥È(AND, OR, XOR)¤ÎÆþÎÏ¿ô¤¬ 3Ëܰʾå¤Î»þ¡¢³ÈÄ¥¥Ð¡¼¤ÏÍøÍѤ¹¤ë¡£ -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- ¥«¡¼¥½¥ë¤ÇÁªÂò¤µ¤ì¤¿¥ï¥¤¥ä¤Ïɽ¼¨ ¤µ¤ì¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤵ¤ì¤ë¡£ -end- ho.edgat.signam -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Ç¤¢¤ë¡£Ì¾Á°¤¬Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.port -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥È̾¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥²¡¼¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.iolab -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ý¡¼¥ÈÊý¸þ¤Ç¤¢¤ë¡£¥â¥¸¥å¡¼¥ë ¤Î¥²¡¼¥È¤Î¾ì¹ç¤Î¤ßÊѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.bitlab -begin- ÁªÂò¤µ¤ì¤¿¥²¡¼¥È¤ÎÁªÂò¤µ¤ì¤¿ ¥Í¥Ã¥È¤Î¥Ó¥Ã¥ÈÉý¤Ç¤¢¤ë¡£Êѹ¹½ÐÍè¤ë¡£ -end- ho.edgat.cycle °ì¥µ¥¤¥¯¥ë¤Î¥¨¥Ý¥Ã¥¯¿ô ho.edgat.phase ¥¯¥í¥Ã¥¯¤Î¥Õ¥§¡¼¥º¡Ê¥Ñ¡¼¥»¥ó¥È¤ÇÀßÄꤹ¤ë¡Ë ho.edgat.duty ¥¯¥í¥Ã¥¯¡¦¥µ¥¤¥¯¥ë¤Î²¿¥Ñ¡¼¥»¥ó¥È¤¬ÏÀÍý0¤Ç¤¢¤ë¤« ho.edgat.hide -begin- Í­¸ú¤Ë¤¹¤ë¤È¥²¡¼¥È̾¤¬É½¼¨¤µ¤ì¤Ê¤¤¡£ -end- ho.edgat.gtype ¥²¡¼¥È¤Î¼ïÎà ho.edgat.gname ¥²¡¼¥È¤Î̾Á° ho.edgat.ganchor Í­¸ú¤Ë¤¹¤ë¤È¡¢¥²¡¼¥È¤¬°ÜÆ°ÉԲĤˤʤ롣 ho.edgat.gx ¥²¡¼¥È¤ÎX°ÌÃÖ ho.edgat.gy ¥²¡¼¥È¤ÎY°ÌÃÖ ho.edgat.swstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.dipstate -begin- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¤Î½é´ü¤ÎÃͤǤ¢¤ë¡£ -end- ho.edgat.range ¥Þ¥ë¥Á¥Ó¥Ã¥È¤Î¿®¹æ¤Î¥µ¥Ö¡¦¥ì¥ó¥¸¤Ç¤¢¤ë¡£ ho.edgat.memfile -begin- ¥á¥â¥ê¤Î½é´ü¤ÎÃͤΥե¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò»Ï¤á¤ë»þ¡¢¤³¤Î¥Õ¥¡¥¤¥ë ¤¬Æɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.edgat.func ¥â¥¸¥å¡¼¥ë¤Îµ¡Ç½ ho.edgat.frame ¥Õ¥ì¡¼¥à¤Î¥é¥Ù¥ë ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undo¤Î¥ê¥¹¥È¤ÎŤµ -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- ²óÏ©¤Ê¤É¤ò°õºþ¤¹¤ë»þ¡¢¤³¤Î¥µ¥¤¥È̾¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.smooth -begin- ¤³¤ÎÀßÄê¤òÍ­¸ú¤Ë¤¹¤ë¤È¡¢²óÏ©¤ò¥¹¥¯¥í¡¼¥ë¤¹¤ë»þ¡¢ ¥Ó¥Ã¥È¥Þ¥Ã¥×¤Î¥³¥Ô¡¼¤òÍøÍѤ·¤Æ¡¢¸úΨ¤è¤¯ ¥¹¥¯¥í¡¼¥ë¤Ç¤­¤ë¡£X¥µ¡¼¥Ð¤ÎÌäÂ꤬¤¢¤ì¤Ð¡¢¤³¤Î ÀßÄê¤ò̵¸ú¤Ë¤¹¤ì¤ÐÎɤ¤¡£ -end- ho.opt.clip -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¦¥¤¥ó¥É¥¦¤ÎÉôʬÎΰè¤Î ºÆÉÁ²è¤ò¹Ô¤Ê¤¦¡£¤½¤¦¤Ç¤Ê¤±¤ì¤Ð¾ï¤Ë Á´Îΰè¤òºÆÉÁ²è¤¹¤ë¡£ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥â¥¸¥å¡¼¥ë¤ò°ÜÆ°¤¹¤ë»þ¡¢ ¥ï¥¤¥ä¤Ê¤É¤Ï¥Þ¥¦¥¹¤Î¥Ü¥¿¥ó¤òÎ¥¤¹¤Þ¤Ç °ÜÆ°¤·¤Ê¤¤¡£²èÌ̤Îɽ¼¨¤¬ÃÙ¤¤»þ¤ËÊØÍø¤Ç¤¢¤ë¡£ -end- ho.opt.bhelp -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥á¥Ã¥»¡¼¥¸¤ÎÍͤʡ֥إë¥×¡¦ ¥Ð¥ë¡¼¥ó¡×¤¬É½¼¨¤µ¤ì¤ë¡£ -end- ho.opt.novice -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢½é¿´¼Ô¥â¡¼¥É¤Ë¤Ê¤ë¡£ ½é¿´¼Ô¥â¡¼¥É¤Ç¤Ï¡¢tkgate¤¬Î©¤Á¾å¤¬¤ë»þ¡¢ ¥Á¥å¡¼¥È¥ê¥¢¥ë¤¬¼«Æ°Åª¤ËÆɤ߹þ¤Þ¤ì¤ë¡£ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ç¥Ð¥°µ¡Ç½¤¬»È¤¨¤ë¡£ ³«È¯¼Ô°Ê³°¤Ë¡¢¤¢¤Þ¤êÌò¤ËΩ¤¿¤Ê¤¤¡£ -end- ho.opt.ckpt Í­¸ú¤Ë¤¹¤ë¤È¡¢tkgate¤Ï¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤Î¥Õ¥¡¥¤¥ë¤òºî¤ë¡£ ho.opt.ckptfreq ¥Á¥§¥Ã¥¯¥Ý¥¤¥ó¥ÈÊݸ¤ò²¿¥¯¥ê¥Ã¥¯Ëè¤Ë¹Ô¤Ê¤¦¤« ho.opt.beak -begin- Á´Á³Ìò¤ËΩ¤¿¤Ê¤¤µ¡Ç½¤òÍ­¸ú¤Ë¤¹¤ë¡£¤³¤Îµ¡Ç½¤ò ̵¸ú¤Ë¤¹¤ë¤È¡¢¤³¤Î¥¹¥¤¥Ã¥Á¤Ï¥À¥¤¥¢¥í¥° ¥Ü¥Ã¥¯¥¹¤«¤é¾Ã¤¨¡¢.tkgate-properties¤òÊÔ½¸¤·¤Ê¤¤¸Â¤ê Ìá¤é¤Ê¤¤¡£ -end- ho.opt.miles -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢tkgate¤Ï»þ¡¹¥æ¡¼¥¶¤ò Çϼ¯¤Ë¤·¤¿¤ê¡¢°­¸ý¤ò¸À¤Ã¤¿¤ê¤¹¤ë¡£ -end- ho.opt.bat -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥Ð¥Ã¥È¥Þ¥ó¤Î¥³¥ó¥Ô¥å¡¼¥¿¤ò À߷פ¹¤ë°Ù¤Ë¡ÖÌò¤Ë¤¿¤Ä¡×µ¡Ç½¤¬»È¤¨¤ë¡£ -end- ho.opt.trek žÁ÷¤·¤í¡¢¥¹¥³¥Ã¥Æ¥£¡ª ho.opt.simstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¹¥Æ¥Ã¥×¡¦¥³¥Þ¥ó¥É¤Ç ²¿¥¨¥Ý¥Ã¥¯¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckstep -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¥¹¥Æ¥Ã¥×¡¦ ¥³¥Þ¥ó¥É¤Ç ²¿¥µ¥¤¥¯¥ë¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckover -begin- ¥·¥ß¥å¥ì¡¼¥¿¤Î¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤è¤ê¹¹¤Ë²¿¥¨¥Ý¥Ã¥¯ ¿Ê¤à¤«¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.vpopupdelay -begin- ¥Þ¥¦¥¹¥Ü¥¿¥ó¤ò²¡¤·¤Æ¤«¤é¡¢²¿¥ß¥êÉÃ·Ð¤Ã¤Æ ¤«¤é¿®¹æ¤ÎÃͤ¬É½¼¨¤µ¤ì¤ëÃÙ±ä¤Ç¤¢¤ë¡£ ¤³¤Î Ãٱ䤬û²á¤®¤ë»þ¡¢¥À¥Ö¥ë¥¯¥ê¥Ã¥¯¤¬ ǧÃÎ ¤Ç¤­¤Ê¤¯¤Ê¤ëÌäÂ꤬¤¢¤ë¥·¥¹¥Æ¥à¤Ï ¤¢¤ë¡£ ¤³¤ÎÌäÂ꤬µ¯¤³¤é¤Ê¤±¤ì¤Ð¡¢ÃÙ±ä ¤ò¤è¤ê û¤¯¤·¤Æ¤âÎɤ¤¡£ -end- ho.opt.init -begin- ¥·¥ß¥å¥ì¡¼¥¿¤òΩ¤Á¾å¤²¤ë»þ¤Ë ¼«Æ°Åª¤Ë¼Â¹Ô¤¹¤ë¥¹¥¯¥ê¥×¥È¡¦ ¥Õ¥¡¥¤¥ë¤ò»ØÄꤹ¤ë¡£ -end- ho.opt.ckall -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï ¤É¤Î¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Ç¤âÄä»ß¤¹¤ë¡£ -end- ho.opt.ckspec -begin- Í­¸ú¤Ë¤¹¤ë¤È¡¢¥¯¥í¥Ã¥¯¡¦¥³¥Þ¥ó¥É¤Ï »ØÄꤷ¤¿¥¯¥í¥Ã¥¯¤Î¥¨¥Ã¥¸¤Î¤ß¤ËÄä»ß¤¹¤ë¡£ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- ¿·¤·¤¤¥²¡¼¥È¤Î¥Ç¥Õ¥©¥ë¥È¤Î¥Æ¥¯¥Î¥í¥¸¡¼¡£ ¥²¡¼¥È¤ÎÃÙ±ä¤Ë±Æ¶Á¤¹¤ë¡£Ç¤°Õ¤Î¥²¡¼¥È ¤Î ¥Æ¥¯¥Î¥í¥¸¡¼¤òÊѹ¹¤¹¤ë¤Ë¤Ï¡¢¥²¡¼¥È¤ÎÀßÄê ¥Ü¥Ã¥¯¥¹¤ò³«¤¤¤Æ¡¢¡ÖÃÙ±ä¡×¤Î¥¿¥Ö ¤òÁªÂò ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.techbut -begin- »ØÄꤷ¤¿¥Æ¥¯¥Î¥í¥¸¡¼¡¦¥Õ¥¡¥¤¥ë¤«¤é¤Î ÃÙ±äÃͤò ÍøÍѤ¹¤ë¡£¿·¤·¤¤¥Æ¥¯¥Î¥í¥¸¡¼¤ò Äɲ乤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¢ª¡ÖÀßÄê...¡×¢ª ¡Ö¥·¥ß¥å¥ì¡¼¥È¡× ¤Î¥á¥Ë¥å¡¼¤ò³«¤¤¤Æ¡¢ ¥Õ¥¡¥¤¥ë¤Î¥ê¥¹¥È¤ËÄɲà ¤·¤Æ²¼¤µ¤¤¡£ -end- ho.custbut -begin- ¤³¤Î¥²¡¼¥ÈÀìÍѤÎÃÙ±äÃͤò»ØÄꤹ¤ë¡£ -end- ho.contver -begin- ¥Þ¥¦¥¹Áàºî¤ò¹Ô¤Ê¤¦»þ¡¢ÆâÉô¹½Â¤¤ò¼«Æ°Åª¤Ë ³Îǧ¤·¤Æ¡¢ÉÔÀµ¤Î½ê¤òÃΤ餹¡£ -end- ho.simwatch -begin- ¥·¥ß¥å¥ì¡¼¥¿¤ÈGUI¤Î´Ö¤Î¥³¥Þ¥ó¥É¤òɽ¼¨¤¹¤ë¡£ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin ¥º¡¼¥à¡¦¥¤¥ó ho.tool.zoomout ¥º¡¼¥à¡¦¥¢¥¦¥È ho.tool.rotate ÁªÂò¤Î¥²¡¼¥È¤òÈó»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.brotate ÁªÂò¤Î¥²¡¼¥È¤ò»þ·×¼þ¤ê¤Ë²óž¤¹¤ë¡£ ho.tool.valgn ÁªÂò¤Î¥²¡¼¥È¤ò½Ä¤Ë°ìÎó¤Ëʤ֡£ ho.tool.halgn ÁªÂò¤Î¥²¡¼¥È¤òÍâ¤Ë°ìÎó¤Ëʤ֡£ ho.tool.cut ÁªÂò¤Î¥²¡¼¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥«¥Ã¥È¤¹¤ë¡£ ho.tool.copy ÁªÂò¤Î¥²¡¼¥È¤ò¥Ð¥Ã¥Õ¥¡¤Ë¥³¥Ô¡¼¤¹¤ë¡£ ho.tool.paste ¥«¥Ã¥È¥Ð¥Ã¥Õ¥¡¤Î¥²¡¼¥È¤òÄ¥¤êÉÕ¤±¤ë¡£ ho.tool.find ¥²¡¼¥È¡¢¥ï¥¤¥ä¡¢¥Æ¥­¥¹¥È¤Ê¤É¤òõº÷¤¹¤ë¡£ ho.tool.addport ÁªÂò¤Î¥²¡¼¥È¤Ë¥Ý¡¼¥È¤òÄɲ乤롣 ho.tool.anchor ÁªÂò¤Î¥²¡¼¥È¤ò°ÜÆ°ÉԲĤˤ¹¤ë¡£ ho.tool.unanchor ÁªÂò¤Î¥²¡¼¥È¤ò°ÜÆ°²Äǽ¤Ë¤¹¤ë¡£ ho.tool.replicate ¥²¡¼¥È¤òÊ£À½¤¹¤ë¡£ ho.tool.delete ÁªÂò¤Î¥²¡¼¥È¤òºï½ü¤¹¤ë¡£ tkgate-2.0-b10/locale/ja/messages.utf8000644 001751 001751 00000253164 11131565067 020276 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Jan 9 01:09:13 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## # On FreeBSD (and possibly Linux), the euc file can be converted to # unicode using the command: # # iconv -f euc-jp -t utf-8 messages.euc > messages ############################################################################## # # basic strings # b.new æ–°è¦... b.dismiss é–‰ã˜ã‚‹ b.close é–‰ã˜ã‚‹ b.ok ＯＫ b.clear クリア b.cancel キャンセル b.open é–‹ã b.bitw ビット幅 b.in å…¥ b.out 出 b.inout 入出 b.browse é¸æŠž... b.label åå‰ b.find 探索 b.edit 編集... b.add 追加... b.delete 削除 b.deleteb 削除... b.remove 消㙠b.apply セット b.anchor 移動ä¸å¯ b.tech テクノロジー b.enable å¯èƒ½ã«ã™ã‚‹ b.disable 無能ã«ã™ã‚‹ b.flush クリア ############################################################################## # # Main tab strings # tab.edit 編集 tab.editintr インタフェース tab.simulate シミュレート tab.cpath é…å»¶è§£æž # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 8 mm.add 追加... mm.delete 削除 mm.edit 編集... mm.enable 有効ã«ã™ã‚‹ mm.disable 無効ã«ã™ã‚‹ ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file ファイル menu.edit 編集 menu.tool ツール menu.simulate シミュレート menu.module モジュール menu.interface インタフェース menu.gate ゲート menu.make ä½œæˆ menu.help ヘルプ menu.file.new æ–°è¦ä½œæˆ menu.file.open é–‹ã... menu.file.openlib ライブラリを開ã... menu.file.save ä¿å­˜ menu.file.saveas åå‰ã‚’付ã‘ã¦ä¿å­˜... menu.file.print å°åˆ·... menu.file.options 設定... menu.file.quit 終了 menu.file.cprop 回路ã®ç‰¹å¾´... menu.edit.undo Undo menu.edit.redo Redo menu.edit.cut カット menu.edit.copy コピー menu.edit.paste ペースト menu.edit.overlay Overlay張り付㑠menu.edit.selall å…¨ã¦ã‚’é¸æŠž menu.edit.find 回路を探索... menu.edit.algnv 縦ã®ä¸€åˆ— menu.edit.algnh 横ã®ãƒ¼åˆ— menu.edit.rotate 回転 menu.edit.zoomin ズーム・イン menu.edit.zoomout ズーム・アウト menu.edit.rshift å³ã‚·ãƒ•ãƒˆ menu.edit.lshift 左シフト menu.edit.ushift 上シフト menu.edit.dshift 下シフト menu.edit.cwrotate 時計周り回転 menu.edit.ccwrotate 時計å対周り回転 menu.edit.pcwrotate ãƒãƒ¼ãƒˆã®æ™‚計周り回転 menu.edit.pccwrotate ãƒãƒ¼ãƒˆã®éžæ™‚計周り回転 #menu.edit.autobold 太字化 menu.edit.resize å†ã‚µã‚¤ã‚ºåŒ– menu.tool.move 移動ï¼æŽ¥ç¶š menu.tool.delg ゲートã®å‰Šé™¤ menu.tool.cutw ワイヤã®åˆ‡æ–­ menu.tool.inv å¦å®š menu.tool.bitw ビット幅 menu.tool.debug デãƒãƒƒã‚° menu.tool.point ãƒã‚¤ãƒ³ãƒˆ menu.tool.line ライン menu.tool.rect 長方形 menu.tool.fillrect 色ã¥ã‘長方形 menu.tool.port ãƒãƒ¼ãƒˆ menu.tool.select å…責é¸æŠž menu.tool.rot0 0度回転 menu.tool.rot90 90度回転 menu.tool.rot180 180度回転 menu.tool.rot270 270度回転 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin シミュレーションを開始 menu.simulate.end シミュレーションを終了 menu.simulate.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.simulate.run ラン menu.simulate.pause 一時ストップ menu.simulate.step ステップ(エãƒãƒƒã‚¯) menu.simulate.cycle ステップ(サイクル) menu.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆã®è¨­å®š... menu.simulate.script スクリプトを実行... menu.simulate.load メモリã®èª­ã¿è¾¼ã¿... menu.simulate.dump メモリã®æ›¸ã出ã—... menu.module.open é–‹ã menu.module.close é–‰ã˜ã‚‹ menu.module.new æ–°è¦ä½œæˆ... menu.module.del 削除... menu.module.copy コピー... menu.module.rename åå‰ã®ç·¨é›†... menu.module.claim å–å¾—... menu.module.setroot ルートã«ã™ã‚‹... menu.module.prop モジュールã®è¨­å®š... menu.module.interface インタフェース menu.module.interface.set セット menu.module.interface.edit 編集 menu.gate.addport ãƒãƒ¼ãƒˆè¿½åŠ  menu.gate.ioset タイプ指定 menu.gate.anchor é¸æŠžã‚’移動ä¸å¯ã«ã™ã‚‹ menu.gate.unanchor é¸æŠžã‚’移動å¯ã«ã™ã‚‹ menu.gate.prop ゲートã®è¨­å®š... menu.gate.rep 複製 menu.gate.del 削除 menu.gate.settech テクノロジーã®è¨­å®š menu.help.about tkgateã«ã¤ã„ã¦... menu.help.license ライセンス... menu.help.doc ドキュメンテーション... menu.help.tut ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ« menu.help.home ホーム・ページ menu.help.example 回路ã®ä¾‹ ############################################################################# # Scope Menu # menu.scope_file ファイル menu.scope_sim シミュレート menu.scope_trace トレース menu.scope_help ヘルプ menu.scope_file.ptrace トレースå°åˆ·... menu.scope_file.close é–‰ã˜ã‚‹ menu.scope_trace.zoomin ズーム・イン menu.scope_trace.zoomout ズーム・アウト menu.scope_sim.addprobe プローブã®è¿½åŠ ï¼å‰Šé™¤ menu.scope_sim.run 時効 menu.scope_sim.pause 一時åœæ­¢ menu.scope_sim.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— menu.scope_sim.cycle サイクル・ステップ menu.scope_sim.break ブレークãƒã‚¤ãƒ³ãƒˆ... menu.scope_sim.script スクリプトã®æ™‚効... menu.scope_sim.load メモリã®èª­ã¿è¾¼ã¿... menu.scope_sim.dump メモリã®æ›¸ãè¾¼ã¿... menu.scope_help.about tkgateã«ä»˜ã„ã¦... menu.scope_help.license ライセンス... menu.scope_help.doc ドキュメンテーション... mod.intf インタフェース port.parms ãƒãƒ¼ãƒˆã®ãƒ‘ラメタ port.in å…¥ port.out 出 port.inout 入出 ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate ゲート gm.rgate å˜é …縮約ゲート gm.msi MSI gm.alu ALU gm.mem メモリー gm.mod モジュール gm.comment コメント gm.frame フレーム gm.io.switch スイッムgm.io.dip DIPスイッムgm.io.ground アース gm.io.vdd Vdd gm.io.merge ワイヤã®ãƒžãƒ¼ã‚¸ gm.io.clock クロック gm.io.led LEDビット gm.io.ledbar LED棒グラフ gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf ãƒãƒƒãƒ•ã‚¡ gm.gate.inv å¦å®šãƒãƒƒãƒ•ã‚¡ gm.gate.tribuf トライ・ãƒãƒƒãƒ•ã‚¡ gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and å˜é …縮約AND gm.rgate.nand å˜é …縮約NAND gm.rgate.or å˜é …縮約OR gm.rgate.nor å˜é …縮約NOR gm.rgate.xor å˜é …縮約XOR gm.rgate.xnor å˜é …縮約XNOR gm.alu.add 加算器 gm.alu.mult 乗算器 gm.alu.div 除算器 gm.alu.lshift 左シフト gm.alu.rshift å³ã‚·ãƒ•ãƒˆ gm.alu.arshift ç®—æ•°çš„å³ã‚·ãƒ•ãƒˆ gm.alu.roll ロール gm.mem.reg レジスタ gm.mem.ff フリップ・フロップ gm.mem.rff é¡åƒãƒ•ãƒªãƒƒãƒ—・フロップ gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 セレクター gm.msi.41mux 4-1 セレクター gm.msi.81mux 8-1 セレクター gm.msi.12dec 1-2 デコーダ gm.msi.14dec 1-4 デコーダ gm.msi.18dec 1-8 デコーダ gm.mod.inst モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ gm.mod.in モジュールã®å…¥åŠ› gm.mod.out モジュールã®å‡ºåŠ› gm.mod.inout モジュールã®å…¥å‡ºåŠ› tutorial.prev å‰ã¸ tutorial.next 次㸠tutorial.chapter ç« ã®ä¸€è¦§è¡¨ tutorial.reload å†èª­ã¿è¾¼ã¿ ############################################################################## # # Popup menus # pop.make ä½œæˆ pop.tool ツール pop.edit.paste ペースト pop.edit.cut カット pop.edit.copy コピー pop.port.in å…¥ pop.port.out 出 pop.port.inout 入出 pop.wire.addseg ワイヤã®è¿½åŠ  pop.wire.prop ãƒãƒƒãƒˆã®ç‰¹å¾´... pop.wire.hidesize ビット幅を隠㙠pop.wire.showsize ビット幅を示㙠pop.wire.hidelabel レーベルを隠㙠pop.wire.hidealllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’éš ã™ pop.wire.clearalllabel å…¨ã¦ã®ãƒ¬ãƒ¼ãƒ™ãƒ«ã‚’クリア pop.wire.showlabel レーベルを示㙠pop.gate.open é–‹ã pop.gate.close é–‰ã˜ã‚‹ pop.gate.prop インスタンスã®ç‰¹å¾´... pop.gate.addport ãƒãƒ¼ãƒˆã®è¿½åŠ  pop.gate.addin 入力ã®è¿½åŠ ... pop.gate.addout 出力ã®è¿½åŠ ... pop.gate.addinout 入出力ã®è¿½åŠ ... pop.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ pop.gate.settech テクノロジ指定 pop.gate.delete 削除 pop.gate.ioset タイプã®æŒ‡å®š pop.module.new æ–°è¦... pop.module.del 削除... pop.module.copy コピー... pop.module.rename åå‰ã®å¤‰æ›´... pop.module.claim モジュールã®å–å¾— pop.module.setroot ルート指定... pop.module.prop モジュールã®ç‰¹å¾´... pop.module.int インタフェースã®ç·¨é›†... pop.simulate.end シミュレーションを終了 pop.simulate.begin シミュレーションを開始 pop.simulate.addprobe プローブを追加ï¼å‰Šé™¤ pop.simulate.run 時効 pop.simulate.pause 一時åœæ­¢ pop.simulate.step エãƒãƒƒã‚¯ãƒ»ã‚¹ãƒ†ãƒƒãƒ— pop.simulate.cycle サイクル・ステップ pop.simulate.break ブレークãƒã‚¤ãƒ³ãƒˆ... pop.simulate.script スクリプトã®æ™‚効... pop.simulate.load メモリã®èª­ã¿è¾¼ã¿... pop.simulate.dump メモリã®æ›¸ãè¾¼ã¿... pop.interface インタフェース pop.interface.set 指定 pop.interface.edit 編集... pop.interface.auto 自動作æˆ... pop.interface.replace å–ã‚Šæ›ãˆ pop.igen.type タイプ pop.igen.side サイド pop.igen.size サイズ pop.igen.delete 削除 pop.igen.in å…¥ pop.igen.out 出 pop.igen.inout 入出 pop.igen.left å·¦ pop.igen.right å³ pop.igen.top 上 pop.igen.bottom 下 pop.igen.other ä»– ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit 編集 #symed.edit.cut カット #symed.edit.copy コピー #symed.edit.paste ペースト #symed.edit.overlay Overlayペースト #symed.edit.rclock 時計周り回転 #symed.edit.rcclock éžæ™‚計周り回転 #symed.module モジュール #symed.modes モード #symed.cutpaste カットï¼ãƒšãƒ¼ã‚¹ãƒˆ #symed.rotate ãƒãƒ¼ãƒˆã®å›žè»¢ #symed.zoom ズーム #symed.update Update symed.cancel キャンセル symed.tab.normal éžã‚»ãƒ¬ã‚¯ãƒˆ symed.tab.select セレクト symed.link セレクトã¨éžã‚»ãƒ¬ã‚¯ãƒˆã‚’åŒæ™‚ã«ç·¨é›†ã™ã‚‹ã€‚ # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg ワイヤã«ãƒ€ãƒ–ル・クリックã—ã¦ã€ãƒ—ローブã«ä»˜ã‘ã£ã¦ãã ã•ã„。 comment.empty [ダブル・クリックã—ã¦ã€ãƒ†ã‚­ã‚¹ãƒˆã‚’編集ã—ã¦ãã ã•ã„。] ############################################################################## # Interface strings # ifile ファイル imodule モジュール iblmodule モジュール: iports ãƒãƒ¼ãƒˆ: ibits ビット幅: itype タイプ: ############################################################################# # Module Dialog Box # db.mod.name モジュールå db.mod.file ファイルå db.mod.type タイプ db.mod.flags フラグ db.mod.dataprot モジュールã®å®šç¾©ã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.intfprot インタフェースã®ç·¨é›†ã‚’ä¸å¯èƒ½ã«ã™ã‚‹ã€‚ db.mod.edprot インタフェースã®ç·¨é›†ã‚’専用エディタã«é™ã‚‹ã€‚ db.mod.props 特徴 db.mod.netlist ãƒãƒƒãƒˆãƒªã‚¹ãƒˆ db.mod.hdl HDL # # These are probably not used anymore. Lets leave them as is. # db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netexpl -begin- グラフィカルã®ã‚¨ãƒ‡ã‚£ã‚¿ã‚’ 利用ã—ã¦ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®æ“作を 定義ã™ã‚‹ã€‚ -end- db.mod.hdlexpl -begin- Verilogã®ãƒ†ã‚­ã‚¹ãƒˆã‚’利用ã—ã¦ã€ モジュールã®æ“作を定義ã™ã‚‹ã€‚ -end- ############################################################################# # Error List Dialog box # db.err.caption エラーã®ä¸€è¦§è¡¨ db.err.explain -begin- 回路ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºè¦‹ã•ã‚ŒãŸã®ã§ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã‚’開始 出æ¥ãªã‹ã£ãŸã€‚以下ã®ãƒªã‚¹ãƒˆã®ä¸­ã‹ã‚‰ã€ã‚¨ãƒ©ãƒ¼ã‚’é¸æŠž ã—ã¦ã€ã‚¨ãƒ©ãƒ¼ã®å ´æ‰€ã«ç§»å‹•ã—ã¦ãã ã•ã„。 -end- ############################################################################# # Net Dialog Box # db.net.name ãƒãƒƒãƒˆå db.net.hide ãƒãƒƒãƒˆåã‚’éš ã™ db.net.bits ビット幅 db.net.type ãƒãƒƒãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.port ãƒãƒ¼ãƒˆãƒ»ã‚¿ã‚¤ãƒ— db.net.in å…¥ db.net.out 出 db.net.inout 入出 db.net.inets ãƒãƒƒãƒˆ ############################################################################## # # New circuit dialog box # db.newcirc.directory ディレクトリ db.newcirc.cap æ–°è¦å›žè·¯ db.newcirc.exp -begin- ç¾åœ¨ã®å›žè·¯ã®ç·¨é›†ã‚’ 辞ã‚ã¦ã€æ–°ã—ã„回路を 編集ã—始ã‚る。 -end- db.newcirc.file ファイルå db.newcirc.topname トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å ############################################################################## # Gate dialog box # db.gate.title ゲートã®è¨­å®š db.gate.signam ãƒãƒƒãƒˆå db.gate.portnam ãƒãƒ¼ãƒˆå db.gate.iotype タイプ db.gate.bitw ビット幅 db.gate.cyclew サイクル幅 db.gate.phase フェーズ db.gate.duty デューティー db.gate.port ãƒãƒ¼ãƒˆ db.gate.bitws ビット db.gate.side サイド db.gate.gtype ゲート・タイプ db.gate.gname ゲートå db.gate.hidenam åå‰ã‚’éš ã™ db.gate.anchor 移動ä¸å¯ã«ã™ã‚‹ db.gate.cpbreak クリティカル・パス分割点 db.gate.butstate スイッãƒçŠ¶æ…‹ db.gate.dipval DIP状態 db.gate.range ビット範囲 db.gate.memfilenam メモリ・ファイルå db.gate.modname 機能å db.gate.general 一般 db.gate.details 詳細 db.gate.text テキスト db.gate.ports ãƒãƒ¼ãƒˆ db.gate.delay é…延 db.gate.parameters パラメタ db.gate.stddelay 標準ã®é…延 db.gate.custdelay カスタムã®é…延 db.gate.catdiruse ãƒãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ db.gate.edit 編集 db.gate.delete 削除 db.gate.add 追加 db.gate.ff.type フリップフロップã®æ–¹ä½æ±ºå®š db.gate.ff.normal.hdr 普通 db.gate.ff.normal.exp -begin- データãŒå·¦ã‹ã‚‰å³ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.ff.reverse.hdr åå°„ db.gate.ff.reverse.exp -fillbegin- データãŒå³ã‹ã‚‰å·¦ã¸ æµã™ãƒ•ãƒªãƒƒãƒ—フロップ。 -end- db.gate.cat.asc.hdr 昇順 db.gate.cat.dec.hdr é™é † db.gate.cat.asc.exp -fillbegin- ビットã¯ä¸Šä¸‹ã«æ˜‡é †ã§é€£çµã™ã‚‹ã€‚ -end- db.gate.cat.dec.exp -fillbegin- ビットã¯ä¸Šä¸‹ã«é™é †ã§é€£çµã™ã‚‹ã€‚ -end- db.gate.cat.sigdir ä¿¡å·æ–¹å‘ db.gate.cat.auto.hdr 自動 db.gate.cat.multin.hdr 多入力 db.gate.cat.singin.hdr 多出力 db.gate.cat.tran.hdr 入出 db.gate.cat.auto.exp -fillbegin- ä¿¡å·ã®æ–¹å‘を自動的 ã«åˆ¤æ–­ã™ã‚‹ã€‚ -end- db.gate.cat.multin.exp -fillbegin- ã„ã¤ã‚‚多ãƒãƒ¼ãƒˆå´ãŒå…¥åŠ›ã¨ã—ã¦æ‰±ã†ã€‚ -end- db.gate.cat.singin.exp -fillbegin- ã„ã¤ã‚‚å˜ä½ã®ãƒãƒ¼ãƒˆå´ãŒå…¥åŠ›ã¨ã—ã¦æ‰±ã†ã€‚ -end- db.gate.cat.tran.exp -fillbegin- åŒæ–¹å‘ã®ä¿¡å·ã®ä¼æ’­(tran)を許ã™ã€‚スイッãƒã‚„レジスタã«ã®æŽ¥ç¶šã¯ä¸å¯ã§ã™ã€‚ -end- db.gate.tab.General.cap 一般特徴 db.gate.tab.Ports.cap ãƒãƒ¼ãƒˆç‰¹å¾´ db.gate.tab.Delay.cap é…延特徴 db.gate.tab.Parameters.cap モジュール特徴 db.gate.tab.CLOCK.cap クロック特徴 db.gate.tab.SWITCH.cap スイッãƒç‰¹å¾´ db.gate.tab.DIP.cap DIP特徴 db.gate.tab.TAP.cap Tran特徴 db.gate.tab.RAM.cap RAM特徴 db.gate.tab.ROM.cap ROM特徴 db.gate.tab.MODULE.cap モジュール特徴 db.gate.tab.FRAME.cap フレーム特徴 db.gate.tab.LED.cap LED特徴 db.gate.tab.AND.cap AND特徴 db.gate.tab.OR.cap OR特徴 db.gate.tab.XOR.cap XOR特徴 db.gate.tab.MUX.cap Mux特徴 db.gate.tab.DEMUX.cap Demux特徴 db.gate.tab.CONCAT.cap Concat特徴 db.gate.tab.COMMENT.cap テキスト特徴 db.gate.tab.FF.cap フリップフロップ特徴 db.gate.tab.General.exp -fillbegin- インスタンスã®åŸºæœ¬ç‰¹å¾´ã‚’表示ã€åˆã¯ç·¨é›†ã™ã‚‹ã€‚ -end- db.gate.tab.Ports.exp -fillbegin- インスタンスã®ãƒãƒ¼ãƒˆã‚’追加ã€ç·¨é›†ã€åˆã¯å‰Šé™¤ã™ã‚‹ã€‚ -end- db.gate.tab.Delay.exp -fillbegin- インスタンスã®é…延ã¯ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ã§ã‚‚ã€å€‹ã€…ã§ã‚‚設定å¯èƒ½ã§ã‚る。 -end- db.gate.tab.Parameters.exp -fillbegin- モジュールã®ãƒ‘ラメターãŒå®šç¾©ã—ã¦ã„ã‚‹å ´åˆã€ã“ã“ã§ãã®å€¤ã‚’設定出æ¥ã‚‹ã€‚モ ジュールã®ãƒ‘ラメターã¯é…延値ã€ã‚³ãƒ³ã‚¹ã‚¿ãƒ³ãƒˆãªã©ã«åˆ©ç”¨ã•ã‚Œã¦ã„る。 -end- db.gate.tab.details.exp -fillbegin- ゲート次第ã®è¨­å®šã‚’è¡Œã†ã€‚ -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- コメントã®ãƒ†ã‚­ã‚¹ãƒˆã‚’入力ã™ã‚‹ã€‚ã‚る程度ã®htmlã‚„ãƒã‚¤ãƒ‘ーリンクãªã©ã‚‚利用出æ¥ã‚‹ã€‚ -end- db.gate.mparm.parameter パラメタ db.gate.mparm.value 値 db.gate.mparm.exampleA -begin- ã“ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¯ãƒ‘ラメタを利用ã—ã¦ã„ãªã„。 パラメタã¯Verilogテキストã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã« 利用出æ¥ã‚‹ã€‚ã“ã®ãƒ€ã‚¤ã‚¢ãƒ­ã‚°ã§ã€ãã‚Œãžã‚Œã® パラメタã®å€¤ãŒè¨­å®šå‡ºæ¥ã‚‹ã€‚モジュール㮠パラメタを利用ã™ã‚‹ãŸã‚ã€ãƒ†ã‚­ã‚¹ãƒˆã®å®šç¾©ã« 「#ã€ã‹ã‚‰å§‹ã¾ã‚‹ãƒ‘ラメタã®ãƒªã‚¹ãƒˆã‚’書ã„㦠ãã ã•ã„。以下ã®ä¾‹é¡Œã§ã€ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®å€¤ãŒ 「1'b1ã€ã®ã€Œbase_valueã€ã¨ã„ã†ãƒ‘ラメタを æŒã¤ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãŒç¤ºã—ã¦ã‚る。 -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder 入力ã®é †åº db.gate.mux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.mux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.mux.ord1.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.ord2.exp -fillbegin- MUXã®å…¥åŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.dataorder 出力ã®é †åº db.gate.demux.ord1.hdr å·¦ã‹ã‚‰å³ã¸ db.gate.demux.ord2.hdr å³ã‹ã‚‰å·¦ã¸ db.gate.demux.ord1.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å·¦ã‹ã‚‰å³ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.demux.ord2.exp -begin- DEMUXã®å‡ºåŠ›ã®é †åºã‚’å³ã‹ã‚‰å·¦ã¸ã«ã™ã‚‹ã€‚ -end- db.gate.mux.select セレクタã®ç®‡æ‰€ db.gate.mux.sel1.hdr å·¦å´ã®ã‚»ãƒ¬ã‚¯ã‚¿ db.gate.mux.sel2.hdr å³å´ã®ã‚»ãƒ¬ã‚¯ã‚¿ db.gate.mux.sel1.exp -fillbegin- セレクタã®å…¥åŠ›ã‚’å·¦å´ã«ãŠã。 -end- db.gate.mux.sel2.exp -fillbegin- セレクタã®å…¥åŠ›ã‚’å³å´ã«ãŠã。 -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse æ‹¡å¼µãƒãƒ¼ã‚’利用 db.gate.aox.use.hdr æ‹¡å¼µãƒãƒ¼ db.gate.aox.nouse.hdr æ‹¡å¼µãƒãƒ¼ã‚’利用ã—ãªã„ db.gate.aox.use.exp -fillbegin- 基本ゲート(AND, OR, ãªã©)ã«å…¥åŠ›ã‚’追加ã™ã‚‹æ™‚ã€æ‹¡å¼µãƒãƒ¼ãŒåˆ©ç”¨ã•ã‚Œã‚‹ã€‚ -end- db.gate.aox.nouse.exp -fillbegin- 基本ゲート(AND, OR, ãªã©)ã«å…¥åŠ›ã‚’追加ã™ã‚‹æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã•ã‚Œãªã„。 -end- db.gate.led.type LEDã®ã‚¿ã‚¤ãƒ— db.gate.led.bit.hdr ビット db.gate.led.bar.hdr ãƒãƒ¼ãƒ»ã‚°ãƒ©ãƒ• db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- 一ビットã®ä¿¡å·ã®ç‚ºã®å˜ä½ã®LED -end- db.gate.led.bar.exp -fillbegin- LEDã®ãƒãƒ¼ãƒ»ã‚°ãƒ©ãƒ•ã€‚一ビットã«ã¤ãã€ä¸€ã¤ã®ãƒãƒ¼ãŒåˆ©ç”¨ã•ã‚Œã‚‹ã€‚ -end- db.gate.led.hex.exp -fillbegin- ä¿¡å·ã‚’16進数ã§è¡¨ç¤ºã™ã‚‹ã€‚ -end- db.gate.led.dec.exp -fillbegin- ä¿¡å·ã‚’10進数ã§è¡¨ç¤ºã™ã‚‹ã€‚ -end- db.gate.led.seg.exp -fillbegin- å„セグメントを別々ã«åˆ¶å¾¡ã™ã‚‹ã€‚ -end- db.seq.back <å‰ã¸ db.seq.next 次ã¸> db.hdl.savecap 複数ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« db.hdl.saveexp -fillbegin- テキストã®ãƒãƒƒãƒ•ã‚¡ã«è¤‡æ•°ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®å®šç¾©ãŒã‚る。å³å´ã®ã‚¢ã‚¯ã‚·ãƒ§ãƒ³ã®ã„ãšã‚Œã‹ã‚’é¸æŠžã™ã¦ãã ã•ã„。 -end- db.hdl.autoedit 自動変数 db.hdl.split 分離 db.hdl.comment コメント db.hdl.cancel キャンセル db.hdl.ignore 無視ã™ã‚‹ db.hdl.autoeditcap åå‰ãŒä¸€ç­‰ã—ãªã„ db.hdl.autoeditexp -fillbegin- テキストã§ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«åã¨æœŸå¾…ã—ãŸåå‰ãŒä¸€ç­‰ã—ãªã„。å³å´ã®ã‚¢ã‚¯ã‚·ãƒ§ãƒ³ã®ã„ãšã‚Œã‹ã‚’é¸æŠžã™ã¦ãã ã•ã„。 -end- cpath.cloops -fillbegin- 回路ã«çµ„åˆã›ã®ãƒ«ãƒ¼ãƒ—ãŒç™ºè¦‹ã•ã‚ŒãŸã€‚クリティカル ・パスã®è§£æžã‚’è¡Œãªã„ãŸã‘ã‚Œã°ã€ãƒ«ãƒ¼ãƒ—上ã®ãƒãƒƒãƒˆ を切ã£ãŸã‚Šã€ãƒ«ãƒ¼ãƒ—上ã®ã‚²ãƒ¼ãƒˆã‚’「クリティカル・ パス分割点ã€ã«ã—ãŸã‚Šã™ã‚‹å¿…è¦ãŒã‚る。 -end- ############################################################################## # Print dialog box # print.outto 出力先 print.printer プリンター print.file ファイル print.prcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ print.prname プリンタ print.advanced オプション... print.filename ファイルå print.epssave Encapsulated Postscriptã¨ã—ã¦ã‚»ãƒ¼ãƒ–ã™ã‚‹. print.doctit ドキュメントã®é¡Œå print.epcm エãƒãƒƒã‚¯/cm print.estpg ページ数ã®è¦‹ç©ã‚‚ã‚Š print.all 全㦠print.cur ç¾åœ¨ print.use 使用中 print.sel 指定 print.inclib ライブラリ・ファイルもå°åˆ· print.papsz ページ・サイズ print.orient オリエンテーション print.portrait 縦 print.landscape 横 print.2side 両é¢å°åˆ· print.opts オプション print.scale 大ãã„モジュールをスケールã—ã¦ä¸€ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.partition 大ãã„モジュールを複数ã®ãƒšãƒ¼ã‚¸ã§å°åˆ·ã™ã‚‹ print.incidx インデックスをå«ã‚€ print.incgraph 階層グラフをå«ã‚€ print.4up å°ã•ã„モジュールを一é ã«å››ã¤ãšã¤å°åˆ·ã™ã‚‹ print.range レンジ print.scaleselect é¸æŠžç¯„囲をスケールã™ã‚‹ print.fulltr 全部 print.parttr 部分 print.start スタート print.end ストップ print.filesel ファイルã«å°åˆ· print.printersel プリンタã«å°åˆ· print.defaultprinter デフォルトã®ãƒ—リンタ print.pageset ページ・setup print.modulesel モジュールã®é¸æŠž ############################################################################## # # TkGate 2.0 print dialog strings # print.ok å°åˆ· print.printtrace.cap トレースã®å°åˆ· print.printcirc.cap 回路図ã®å°åˆ· print.printcirc.out.exp -begin- 回路図ã®å°åˆ·å…ˆãŒ プリンタã‹ãƒ•ã‚¡ã‚¤ãƒ« ã‹é¸æŠžã™ã‚‹ã€‚ -end- #probably not used print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã‚„å°åˆ·ã®æ§˜å­ã‚’é¸æŠž る。 -end- print.printtrace.trace.exp -fillbegin- 時間ã®ç¯„囲をé¸æŠžã™ã‚‹ã€‚ åˆã€ã‚¹ã‚±ãƒ¼ãƒ«ã«ã‚ˆã£ã¦ã€ å¿…è¦ã®ãƒšãƒ¼ã‚¸æ•°ã‚’表㋠評価ã™ã‚‹ã€‚ -end- print.tab.output å°åˆ·å…ˆ print.tab.page å°åˆ· print.tab.content 内容 ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 600 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 115 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 opt.general 一般 opt.interface インタフェース opt.toolbars ツール・ãƒãƒ¼ opt.editor HDL opt.print å°åˆ· opt.simulate シミュレート opt.library ライブラリ opt.analysis è§£æž opt.color 色 opt.html HTML opt.debug デãƒãƒƒã‚° opt.security セキュリティ opt.identity アイデンティティー opt.site サイトå opt.username ユーザå opt.libname ライブラリå opt.inst インスタンス opt.mods モジュール opt.modports ãƒãƒ¼ãƒˆ opt.frames フレーム opt.comment コメント opt.hlink リンク opt.wire 1ビットã®ãƒ¯ã‚¤ãƒ¤ opt.bus 多ビットã®ãƒ¯ã‚¤ãƒ¤ opt.tools ツール opt.background ãƒãƒƒã‚¯ã‚°ãƒ©ã‚¦ãƒ³ãƒ‰ opt.cpath クリティカル・パス opt.grid スコープã®ã‚°ãƒªãƒƒãƒ‰ opt.logic1 è«–ç†ï¼‘ opt.logic0 è«–ç†ï¼ opt.float フロート opt.unknown ä¸æ˜Ž opt.offled オフã®LED opt.onled オンã®LED opt.zled フロートã®LED opt.restdef デフォールト opt.regudate リージョン・アップデート opt.smoothscroll スムーズ・スクロール opt.balloon ãƒãƒ«ãƒ¼ãƒ³ãƒ»ãƒ˜ãƒ«ãƒ—を利用 opt.safeSave 安全書ã込㿠opt.saveCells セーブファイルã«ã‚»ãƒ«ã‚’å«ã‚€ã€‚ opt.showimage ダイアログボックスã®èª¬æ˜Žæ¬„を表示ã™ã‚‹ã€‚ opt.novice åˆå¿ƒè€…モード opt.blockDropConnect ワイヤ・ドロップã§ã®ãƒãƒ¼ãƒˆã®ä½œæˆã€‚ opt.ckpoint ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ opt.freq 期間 opt.beak 特別モードをå¯èƒ½ã«ã™ã‚‹ opt.bat ãƒãƒƒãƒˆãƒžãƒ³ opt.trek スター・トレック opt.miles マイルス opt.contver 内部構造ã®è‡ªå‹•ç¢ºèª opt.showsimcmd シミュレートã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ opt.estepsz エãƒãƒƒã‚¯ã®ã‚¹ãƒ†ãƒƒãƒ—æ•° opt.cstepsz クロックã®ã‚µã‚¤ã‚¯ãƒ«æ•° opt.overstep クロックã®ã‚ªãƒãƒ¼ã‚¹ãƒ†ãƒƒãƒ— opt.sorttraces スコープã§ä¿¡å·ã‚’ABCé †ã§è¡¨ç¤ºã™ã‚‹ã€‚ opt.vpopupdelay ä¿¡å·å€¤ã‚¦ã‚£ãƒ³ãƒ‰ã®è¡¨ç¤ºé…延 opt.initscript åˆæœŸåŒ–スクリプト opt.posedge å…¨ã¦ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.setclock 指定ã®ã‚¯ãƒ­ãƒƒã‚¯ã§åœæ­¢ã™ã‚‹ opt.delayfilepath é…延ファイル opt.devfilepath VPD(Virtual Periperal Device)ファイルã®ãƒ‘ス opt.vlibpath Verilogã®ãƒ©ã‚¤ãƒ–ラリã®ãƒ‘ス opt.vlibnames ベースã®ãƒ©ã‚¤ãƒ–ラリ opt.display ç”»é¢ opt.input 入力 opt.undolen 最大Undo opt.keybind キー・ãƒã‚¤ãƒ³ãƒ‡ã‚£ãƒ³ã‚°ã®ã‚¹ã‚¿ã‚¤ãƒ« opt.useless å½¹ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ opt.features 基本ã®æ©Ÿèƒ½ opt.simbase 基本ã®ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚¿ã®ã‚ªãƒ—ション opt.simclock クロックã®ã‚ªãƒ—ション opt.cpopts クリティカル・パス設定: opt.maxpath 最大パス数: opt.cpflash パスã®ç‚¹æ»…表示 opt.general.fontset フォント・サイズ opt.simulator.noglitch シミュレータã®ã‚°ãƒªãƒƒãƒã®æŠ‘制 opt.simulator.err エラー扱ㄠopt.simulator.stopany シミュレーションã®å¿ å‘Šã‚’エラーã¨ã—ã¦æ‰±ãˆã‚‹ã€‚ opt.simulator.showall シミュレーションã®å¿ å‘Šã‚’表示ã™ã‚‹ã€‚ opt.simulator.showiferr エラーã®ã‚る時ã®ã¿ã€å¿ å‘Šã‚’表示ã™ã‚‹ã€‚ opt.simulator.ignore シミュレーションã®å¿ å‘Šã‚’無視ã™ã‚‹ã€‚ opt.tool.file ファイル opt.tool.edit 編集 opt.tool.gateopt 回転ï¼æ•´åˆ—化 opt.tool.gateprop ゲート特徴 opt.tool.undo Undo/Redo opt.tool.zoom ズーム opt.tool.mode モード opt.tool.module モジュール opt.tool.tech テクノロジー opt.tool.simctl シミュレータã®åˆ¶å¾¡ opt.tool.simaux シミュレータã®ã‚³ãƒžãƒ³ãƒ‰ opt.tool.symmode モード opt.tool.symedit カットï¼ãƒšãƒ¼ã‚¹ãƒˆ opt.tool.symport ãƒãƒ¼ãƒˆ opt.tool.symshift ビット・マップã®ã‚·ãƒ•ãƒˆ opt.tool.symopr ビット・マップã®æ¼”ç®— opt.editor.features 基礎的ãªã‚¨ãƒ‡ã‚£ã‚¿ãƒ¼ã®æ©Ÿèƒ½ opt.editor.format 自動インデントを有効ã«ã™ã‚‹ opt.editor.colorize 自動色付ã‘を有効ã«ã™ã‚‹ opt.editor.comments コメント opt.editor.strings 文字列 opt.editor.reserved キーワード opt.editor.gateword ゲートå opt.editor.instword モジュールå opt.editor.taskword システム・タスク opt.editor.color 色 opt.editor.bold 太字 opt.editor.italic イタリック opt.editor.indentlevel レブル毎ã®ã‚¤ãƒ³ãƒ‡ãƒ³ãƒˆã®ã‚¹ãƒšãƒ¼ã‚¹æ•° opt.editor.beginindent 「begin..endã€ã®ã‚¤ãƒ³ãƒ‡ãƒ³ãƒˆã‚’囲ã¾ã‚Œã‚‹ã‚Œã¹ã‚‹ã¨ä¼šã‚ã›ã‚‹ã€‚ opt.editor.movesel é¸æŠžã®ãƒ‰ãƒ©ãƒƒã‚°ãƒ»ã‚¢ãƒ³ãƒ‰ãƒ»ãƒ‰ãƒ­ãƒƒãƒ—を有効ã«ã™ã‚‹ã€‚ opt.editor.returntab リターンを押ã™æ™‚ã€è‡ªå‹•ã‚¤ãƒ³ãƒ‡ãƒ³ãƒˆã‚’有効ã«ã™ã‚‹ã€‚ opt.vercheck -begin- 定期的㫠tkgate ã®æ–°ã—ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã‚’インターãƒãƒƒãƒˆã§ ãƒã‚§ãƒƒã‚¯ã™ã‚‹ã€‚常時接続ã§ãªã‘ã‚Œã°æœ‰åŠ¹ã«ã—ãªã„ã“ã¨ã€‚ -end- opt.general.cap 一般オプション opt.editor.cap HDLテキスト・エディタ opt.interface.cap インタフェス・オプション opt.toolbars.cap ツールãƒãƒ¼ãƒ»ã‚ªãƒ—ション opt.print.cap å°åˆ·ã‚ªãƒ—ション opt.analysis.cap -begin- TODO: Critical Path Options -end- opt.simulator.cap シミュレータ・オプション opt.security.cap セキュリティ・オプション opt.color.cap 色ã¥ã‘・オプション opt.html.cap HTML/HTTPオプション opt.debug.cap デãƒãƒƒã‚°ãƒ»ã‚ªãƒ—ション opt.library.cap ライブラリ・オプション opt.sec.execlevel TODO: The $tkg$exec() system task is opt.sec.exec TODO: fully enabled. opt.sec.regexec TODO: enabled only for registered functions. opt.sec.noexec TODO: disabled. opt.sec.simfeatures TODO: Simulator Features opt.sec.send TODO: Enable the $tkg$command() system task. opt.sec.open TODO: Enable the $fopen() system task. opt.sec.writemem TODO: Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue TODO: Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle TODO: Security Violation Handling opt.sec.stop TODO: Stop simulator when disabled feature is used. opt.sec.warn TODO: Display warning message when disabled feature is used. opt.sec.ignore TODO: Ignore attempted usage of disabled features. opt.html.linkopts TODO: Link Options opt.html.browser TODO: Browser Command opt.html.email TODO: e-Mail Command opt.color.editwin 編集ウィンドウã®è‰²ã¥ã‘ opt.color.scopewin スコープ・ウィンドウã®è‰²ã¥ã‘ opt.vlibadd.cap ライブラリ追加 opt.vlibadd.exp -fillbegin- TODO: Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- TODO: Set options for the HDL text editor. -end- opt.general.exp -fillbegin- アイデンティティーã€åŸºæœ¬è¨­å®šã‚’ã™ã‚‹ã€‚アイデンティティーã¯å°åˆ·ã™ã‚‹æ™‚ãªã©ç”¨ã„られる。 -end- opt.interface.exp -fillbegin- TODO: Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- TODO: Specify which toolbars to display. -end- opt.print.exp -fillbegin- TODO: Set default printer options on this page. -end- opt.analysis.exp -fillbegin- TODO: These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- TODO: These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- TODO: Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- TODO: Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- TODO: Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- TODO: Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- TODO: Debugging options can be set here. -end- opt.gen.basetoolbar TODO: Core Editor Toolbars opt.gen.simtoolbar TODO: Simulation Mode Toolbars opt.gen.symedtoolbar TODO: Symbol Editor Toolbars opt.bbar.restore ページã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ opt.bbar.restoreall å…¨ã¦ã®è¨­å®šã‚’デフォルトã«ã™ã‚‹ ############################################################################## # # Interface generator # igen.port ãƒãƒ¼ãƒˆ igen.type タイプ igen.side サイド igen.size ビット幅 igen.bits ビット igen.modname モジュールå: igen.resort å†ã‚½ãƒ¼ãƒˆ igen.add 追加 igen.delete 削除 igen.edit 編集 igen.in å…¥ igen.out 出 igen.inout 入出 igen.left å·¦ igen.right å³ igen.top 上 igen.bottom 下 igen.other ä»– igen.mod TODO: Use ports used in module only. igen.int TODO: Use ports from exisiting interface only. igen.modint TODO: Use both module and interface ports. igen.portsel TODO: Port Selection igen.portpos TODO: Port Positions igen.portpos.keep TODO: Keep exiting port positions when possible. igen.portpos.renew TODO: Regenerate all port positionings. igen.caption TODO: Generate Interface igen.description -begin- TODO: Create a new interface for a module. -end- info.script.error スクリプトã®ã‚¨ãƒ©ãƒ¼ module.props モジュールã®ç‰¹å¾´ ipanel.plist ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ ipanel.props インタフェースã®ç‰¹å¾´ ipanel.itype.change タイプã®å¤‰æ›´... ipanel.itype.edsymbol シンプルã®ç·¨é›†... ipanel.block ブロック ipanel.symbol シンボル ipanel.autogen 自動作æˆ... ipanel.itype.select インタフェス・タイプ ipanel.itype.selectexp -begin- 長方形型ã®ã€Œãƒ–ロッ クã€ã‹ã€ãƒ“ットマッ プã®ã€Œã‚·ãƒ³ãƒœãƒ«ã€ã€ ã„ãšã‚Œã‹é¸æŠžã—㦠ãã ã•ã„。 -end- ipanel.block.description TODO: Block Interface ipanel.symbol.description TODO: Custom Symbol Interface ipanel.ppos.label ブロックã®ã‚µã‚¤ã‚ºã‚’変更ã™ã‚‹æ™‚ã®ãƒãƒ¼ãƒˆã®å–り扱ㄠipanel.ppos.fix 指定 ipanel.ppos.scale スケール ipanel.ppos.grid グリッド ipanel.warn.toblock -begin- TODO: You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- TODO: You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim å–å¾—ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.to æ–°è¦ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.from ç¾åœ¨ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.name モジュールå blklst.new.cap モジュールã®æ–°è¦ä½œæˆ blklst.del.cap 削除ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å blklst.copy.cap コピー・モジュール blklst.rename.cap モジュールã®æ”¹å blklst.claim.cap モジュールã®å–å¾— blklst.setroot.cap トップ・モジュールã®é¸æŠž blklst.new.exp -fillbegin- TODO: Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- TODO: Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- TODO: Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- TODO: Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- TODO: Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- TODO: Make the specified module the top-level module. -end- find.label 探索 find.exp -fillbegin- ゲートåã€ãƒãƒƒãƒˆå〠コメントãªã©ã®ä¸­ã« 指定ストリングを 探索ã™ã‚‹ã€‚ -end- find.ignorecase ケースを無視ã™ã‚‹ã€‚ find.result.module モジュールå find.result.type タイプ find.result.name オブジェクトå # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options 探索ã®ã‚ªãƒ—ション find.results 探索ã®çµæžœ # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos after find.qual.contains ã‚’å«ã‚€ find.qual.begins ã‹ã‚‰å§‹ã¾ã‚‹ find.qual.ends ã§çµ‚ã‚‹ find.qual.matches åŒç­‰ã™ã‚‹ find.dom.label 以下ã®å ´æ‰€ã‚’探索ã™ã‚‹ã€‚ find.dom.gates ゲート find.dom.nets ãƒãƒƒãƒˆ find.dom.text コメントã®ãƒ†ã‚­ã‚¹ãƒˆ find.search 探索: find.target 探索ã®ç¯„囲 # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label 回路ã®ç‰¹å¾´ circ.ident TODO: Identification circ.filev ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ circ.file ファイルå circ.title 回路å circ.discchg 変更を無視ã™ã‚‹ circ.extbar æ‹¡å¼µãƒãƒ¼ã‚’利用ã™ã‚‹ã€‚ circ.autostart シミュレーションã®è‡ªå‹•é–‹å§‹ã‚’有効ã«ã™ã‚‹ã€‚ circ.iniscript åˆæœŸåŒ–スクリプト circ.noscript スクリプト・ファイルã¯æŒ‡å®šã•ã‚Œã¦ã„ãªã„。 circ.really TODO: Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap TODO: Edit Script circ.script.label TODO: Edit script name: circ.vlib.cap TODO: Edit Library circ.vlib.label TODO: Library script name: @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general 一般 circ.library ライブラリ circ.script スクリプト circ.simulator シミュレーション circ.timescale TODO: Default Simulation Time Scale circ.timescale.unit TODO: Units: circ.timescale.prec TODO: Precision: circ.exp -fillbegin- TODO: View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # # Library Manager # libmgr.cap ライブラリ・マãƒã‚¸ãƒ£ãƒ¼ libmgr.library ライブラリå libmgr.description 説明 libmgr.status 状態 libmgr.status.load 利用 libmgr.status.unload éžåˆ©ç”¨ libmgr.status.loadp TODO: [利用] libmgr.status.unloadp TODO: [éžåˆ©ç”¨] libmgr.exp -begin- 利用ã™ã‚‹ãƒ©ã‚¤ãƒ–ラリをé¸æŠžã™ã‚‹ã€‚ -end- libmgr.load 利用 libmgr.unload éžåˆ©ç”¨ libmgr.unloadall å…¨ã¦ã‚’éžåˆ©ç”¨ libmgr.notedit -fillbegin- 回路図ã®ã‚¨ãƒ‡ã‚£ã‚¿ãŒé–‹ã„ã¦ã„る時ã®ã¿ã€ ライブラリã®ãƒžãƒã‚¸ãƒ£ãƒ¼ãŒåˆ©ç”¨å‡ºæ¥ã‚‹ã€‚ -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab ブレークãƒã‚¤ãƒ³ãƒˆ break.id ç•ªå· break.state 状 break.condition æ¡ä»¶ break.value 値 ############################################################################## # Simulator # sim.breakpt ブレークãƒã‚¤ãƒ³ãƒˆ sim.recursive -fillbegin- TODO: Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- TODO: The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay パスé…延: cp.pathl パスã®ä¸€è¦§: cp.numpath パス数: cp.recompute å†è¨ˆç®— ############################################################################## # Error messages # err.rootinterface TODO: Can not set interface of root module. err.nopin é¸æŠžã•ã‚ŒãŸãƒ”ンã®ã‚¿ã‚¤ãƒ—を変更出æ¥ãªã„。 err.badhex ä¸æ­£ã®16進数ã®å€¤ã¯ç„¡è¦–ã•ã‚ŒãŸã€‚ err.gatanchor ゲートãŒç§»å‹•ä¸å¯ã«ãƒžãƒ¼ã‚¯ã•ã‚Œã¦ã„る為ã€ç§»å‹•å‡ºæ¥ãªã„。 err.protdata TODO: Can not modify contents of protected or library module. err.badfind 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badopendel 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’削除出æ¥ãªã„。 err.nosrcmod ソース・モジュール'%s'ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.noerr エラー・メッセージãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.misserr エラー情報ãŒä¸å®Œå…¨ã§ã‚る。(シミュレータãŒè½ã¡ãŸï¼Ÿ) err.badinadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥åŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badinoutadd é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ã‚‚ã†å…¥å‡ºåŠ›è¿½åŠ ãŒå‡ºæ¥ãªã„。 err.badpinchg é¸æŠžã®ã‚²ãƒ¼ãƒˆã®ãƒ”ンã®ã‚¿ã‚¤ãƒ—ãŒå¤‰æ›´å‡ºæ¥ãªã„。 err.badnetname åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為削除ã•ã‚ŒãŸã€‚ err.netbcrename 指定ã®åå‰ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る為ã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfnet 指定ã®åå‰ãŒåˆ¥ã®åå‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfgat 指定ã®åå‰ãŒåŸºç¤Žã®ã‚²ãƒ¼ãƒˆåã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.netconfkw 指定ã®åå‰ãŒã‚­ãƒ¼ãƒ¯ãƒ¼ãƒ‰ã¨è¡çªã™ã‚‹ç‚ºã€ã€Œ%sã€ã«å¤‰æ›´ã•ã‚ŒãŸã€‚ err.badconsame ãƒãƒƒãƒˆãŒåŒã˜ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconptsp ãƒãƒƒãƒˆã®ä¸¡æ–¹ãŒãƒãƒ¼ãƒˆåˆã¯é›»åŠ›ãªã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badconbitw ãƒãƒƒãƒˆã®ãƒ“ット幅ãŒç•°ãªã‚‹ã®ã§ã€æŽ¥ç¶šå‡ºæ¥ãªã„。 err.badrange 指定ã•ã‚ŒãŸæ™‚é–“ã®ãƒ¬ãƒ³ã‚¸ãŒä¸æ­£ã§ã‚る。 err.badlprcmd å°åˆ·ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒå®Ÿè¡Œå‡ºæ¥ãªã„。 err.badpsopen ãƒã‚¹ãƒˆãƒ»ã‚¹ã‚¯ãƒªãƒ—トを「%sã€ã«æ›¸ãè¾¼ã‚ãªã„。 err.badid 「%sã€ã¯ä¸æ­£ã®åå‰ã§ã‚る。 err.protintf TODO: Can't modifiy protected interface on module '%s'. err.bkpt.badexp ä¸æ­£ãªãƒ–レークãƒã‚¤ãƒ³ãƒˆã®æ¡ä»¶ã§ã‚る。「netã€, 「!netã€, 「net==valueã€, 「net!=valueã€ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.bkpt.badnet ä¸æ­£ã®ãƒãƒƒãƒˆåã§ã‚る。 err.bkpt.badval ä¸æ­£ã®å€¤ã§ã‚る。10進数ã‚ã‚‹ã„ã¯ã€verilogå½¢å¼ã®å€¤ã—ã‹èªè­˜ã•ã‚Œã¦ã„ãªã„。 err.bkpt.toomany ブレークãƒã‚¤ãƒ³ãƒˆãŒå¤šéŽãŽã‚‹ã€‚制é™ã¯%dã§ã‚る。 err.sim.badtmp /tmpã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ›¸ãè¾¼ã‚ãªã‹ã£ãŸï¼ˆãƒ‡ã‚£ã‚¹ã‚¯ãŒã„ã£ã±ã„ã‹ï¼‰ã€‚ err.sim.syntx ä¸æ­£ã®ã€Œ%sã€ã‚³ãƒžãƒ³ãƒ‰ err.sim.noincl インクルード・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ err.sim.badedge clockコマンドã®ã‚¨ãƒƒã‚¸'%c'ãŒä¸æ­£ã§ã‚る。 err.sim.nobkpt ブレーク・ãƒã‚¤ãƒ³ãƒˆã€Œ%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.sim.nonet ãƒãƒƒãƒˆã€Œ%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.nogate ゲート「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.sim.badbin 2進数ã®å€¤ã«ä¸æ­£ã®æ–‡å­—ãŒã‚る。 err.sim.notswitch ゲート'%s'ã¯ã‚¹ã‚¤ãƒƒãƒã€DIPã€ãƒ¬ã‚¸ã‚¹ã‚¿ã®ã©ã‚Œã‹ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 err.sim.badcmd シミュレーション・スクリプトã«ä¸æ­£ã®ã‚³ãƒžãƒ³ãƒ‰ã€Œ%sã€ãŒã‚る。 err.sim.isrun シミュレータã¯æ—¢ã«å®Ÿè¡Œã—ã¦ã„る。 ('Ctrl-s e'ã§çµ‚了ã™ã‚‹). err.sim.run TODO: Run-time Error err.sim.cmd TODO: Internal Command Error err.noteditpchg 設定ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ä»¥å¤–ã€å¤‰æ›´ä¸å¯ã€‚ err.badeditop 編集コマンドã«ä¸æ­£ãŒã‚る。 err.badopen 回路ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.badlibopen ライブラリ・ファイル「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.nomark ゲート種をé¸ã¶å‰ã«ã€ãƒžã‚¦ã‚¹ã§ä½ç½®ã‚’設定ã—ã¦ãã ã•ã„。 err.badgate ゲート種ãŒæœªå®šç¾©ã§ã‚る。 err.badportadd é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã¯è¿½åŠ ä¸å¯ã€‚ err.modmissing TODO: HDL module text missing for module "%s". err.modtoomany TODO: Excess module definitions in module "%s". err.modmismatch TODO: Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- ページ数ãŒæ¥µã‚ã¦å¤§ãã„。 本当ã«å°åˆ·ã—ã¾ã™ã‹? -end- err.nojump -fillbegin- ç¾åœ¨ã€'jump-to-module'機能ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ç”¨å‡ºæ¥ãªã„。 トップ・モジュールよりã€ã€Œ>ã€ã‚„「<ã€ã®ã‚³ãƒžãƒ³ãƒ‰ã§ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã‘ã¦ãã ã•ã„。 -end- err.nomod モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.modlock モジュールãŒãƒ­ãƒƒã‚¯ã—ã¦ã„る。 err.closeroot トップ・モジュールãŒé–‰ã˜ã‚Œãªã„。 err.editonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ä½¿ãˆãªã„。 err.simonly コマンドã¯ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ãƒ»ãƒ¢ãƒ¼ãƒ‰ã§ã—ã‹ä½¿ãˆãªã„。 err.deltop TODO: Can not delete top-level module '%s'. err.delprot TODO: Can not delete protected module '%s'. err.nodel ゲートをé¸æŠžã—ã¦ã„ãªã„。 err.modnotdef モジュール「%sã€ã¯å®šç¾©ã—ã¦ã„ãªã„。 err.moddef モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã—ã¦ã„る。 err.primredef TODO: Built-in element name '%s' can not be redefined. err.noprop é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã¯ç·¨é›†å‡ºæ¥ã‚‹è¨­å®šãŒãªã„。 err.openscript シミュレーション・スクリプト「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã„。 err.oldversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³(%s)ãŒå¤ã„。(ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s). err.futureversion 未æ¥ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ï¼ˆ%s）ã®tkgateファイルã§ã‚る。（ç¾åœ¨ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%s） err.badversion 回路ファイルã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒèªè­˜å‡ºæ¥ãªã„。注æ„ã—ã¦åˆ©ç”¨ä¸‹ã•ã„。 err.nodrive ãƒãƒƒãƒˆ%sã¯ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«%sã«ä¿¡å·ã®ã‚½ãƒ¼ã‚¹ãŒãªã„。 err.noconn ワイヤ%s{%d}ã¯æŽ¥ç¶šãŒãªã„（削除ã—ãŸï¼‰ã€‚ err.oldportact ãƒãƒ¼ãƒˆã‚„モジュールã®ç«¯ã«å³ã‚¯ãƒªãƒƒã‚¯ã—ã¦ä¸‹ã•ã„。 err.nomodule TODO: No selected module. err.nomodop TODO: No suitable modules for operation. err.protexec TODO: Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable TODO: File '%s' is not writable. err.backupfail ãƒãƒƒã‚¯ã‚¢ãƒƒãƒ—・ファイル'%s'ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã€‚ err.yy.badprop TODO: Ignoring unknown circuit property '%s'. err.yy.baddata TODO: Bad data type supplied for circuit property '%s'. err.yy.nosym TODO: No current module symbol. err.yy.badicon TODO: Bad icon type '%s'. err.yy.toomuchdata TODO: Too much icon data. err.yy.nosyminst TODO: Missing symbol %d on instance %s of %s. err.yy.badmodprop TODO: Ignoring unknown module property '%s'. err.yy.badmoddata TODO: Bad data type supplied for module property '%s'. err.yy.badprim TODO: Unknown primitive name '%s'. err.yy.nonet TODO: Undeclared net '%s'. err.yy.bogussave TODO: Bogus save data detected. circuit may be damaged. err.yy.pinformat TODO: Illegal pin name format '%s'. err.yy.pinname TODO: Pin name '%s' not defined for gate type '%s' err.yy.nonetpos TODO: No net for position %d on gate %s. err.yy.baddirective TODO: Illegal or badly formed directive '%s'. err.corruptnewsave -fillbegin- TkGateã¯'%s'ã«ã‚»ãƒ¼ãƒ–出æ¥ãŸãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ãŒæ··ä¹±ã•ã‚Œã¦ã„ã‚‹ã¿ãŸã„。もã—ãƒã‚§ãƒƒ ク・ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’使ã£ã¦ã¿ã¦ã ã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.corruptsave -fillbegin- '%s'をセーブã—よã†ã¨ã—ã¦ã„る時ã€TkGateã«å†…部å•é¡ŒãŒç™ºè¦‹ã—ãŸã€‚元々ã®ãƒ•ã‚¡ã‚¤ ルã¯ãã®ã¾ã¾æ®‹ã—ã¦ã‚る。混乱ã•ã‚Œã¦ã„ã‚‹å¯èƒ½æ€§ã®ã‚るファイルã¯'%s'ã«ã‚»ãƒ¼ãƒ– ã—ãŸã€‚ã‚‚ã—ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã‚’利用ã—ã¦ã„ã‚Œã°ã€ãƒã‚§ãƒƒã‚¯ãƒ»ãƒã‚¤ãƒ³ãƒˆã®ãƒ•ã‚¡ã‚¤ ルを使ã£ã¦ã¿ã¦ãã ã•ã„。'tkgate -V'ã§ãƒ•ã‚¡ã‚¤ãƒ«ã‚’ãƒã‚§ãƒƒã‚¯å‡ºæ¥ã‚‹ã€‚ -end- err.badsave -fillbegin- '%s'をセーブ出æ¥ãªã‹ã£ãŸã€‚ファイルã®ãƒ—ロテクションや空ãディスクé‡ã‚’ç¢ºèª ã—ã¦ãã ã•ã„。 -end- err.nosafesave -fillbegin- '%s'ã®å®‰å…¨ã‚»ãƒ¼ãƒ–ã‚’è¡Œã†ãŸã‚ã®ä¸€æ™‚ã®ãƒ•ã‚¡ã‚¤ãƒ«ãŒä½œæˆå‡ºæ¥ãªã‹ã£ãŸã‹ã‚‰ã€ç›´æŽ¥ã‚»ãƒ¼ ブã—ãªãã¦ã¯ãªã‚‰ãªã„。「NOã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€å…ƒã€…ã®ãƒ•ã‚¡ã‚¤ãƒ«ã¯ãã®ã¾ã¾æ®‹ ã™ã€‚「YESã€ã«ã‚¯ãƒªãƒƒã‚¯ã™ã‚Œã°ã€ã‚»ãƒ¼ãƒ–ã™ã‚‹ãŒã€ã‚»ãƒ¼ãƒ–途中ã«å•é¡ŒãŒèµ·ã“ã£ãŸã‚‰ã€ 回路データãŒç ´å£Šã•ã‚Œã‚‹å¯èƒ½æ€§ãŒã‚る。直接セーブã—ã¦ã¿ã¾ã—ょã†ã‹ã€‚ -end- err.noback -fillbegin- tkgateãƒãƒ¼ã‚¸ãƒ§ãƒ³%sã§ä½œã‚‰ã‚ŒãŸãƒ•ã‚¡ã‚¤ãƒ«ã§ã‚る。ä¿å­˜ã™ã‚‹ã¨ã€ tkgateã®å¤ã„ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã«èª­ã¿è¾¼ã‚ãªã„ã“ã¨ãŒã‚る（ç¾åœ¨ã® ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã¯%sã§ã‚る）。 -end- err.viewfile TODO: Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod TODO: internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selgate %2$sã¨ã„ã†%1$sゲートãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.selblock %2$sã¨ã„ã†%1$sモジュールãŒé¸æŠžã•ã‚ŒãŸã€‚ msg.iselwire TODO: Selected port '%s' on block '%s'. msg.iselgate TODO: Selected %s named '%s' (huh? this message should be impossible). msg.iselblock TODO: Selected module interface for '%s'. msg.modoverwt モジュール「%sã€ãŒæ—¢ã«å®šç¾©ã•ã‚Œã¦ã„る。定義ã—ãªãŠã—ã¾ã™ã‹? msg.foundgate %sã¨ã„ã†ã‚²ãƒ¼ãƒˆãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.foundwire %sã¨ã„ã†ãƒ¯ã‚¤ãƒ¤ãŒè¦‹ã¤ã‹ã£ãŸã€‚ msg.searchagn 探索ストリング「%sã€ãŒè¦‹ã¤ã‹ã‚‰ãªã‹ã£ãŸã€‚ã‚‚ã†ä¸€åº¦ã€ŒæŽ¢ç´¢ã€ã‚’押ã™ã¨ã€æŽ¢ç´¢ã—ãªãŠã™ã€‚ msg.sim.chgtoroot シミュレーション・モードã§ã¯ã€ãƒˆãƒƒãƒ—・モジュールãŒãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ã®ãƒˆãƒƒãƒ—ã§ãªã‘ã‚Œã°ãªã‚‰ãªã„。 msg.sim.nogatemod シミュレーション・モードã§ã€å…·ä½“çš„ãªãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ãƒ»ã‚¹ã‚¿ãƒƒã‚¯ãŒå¿…è¦ã§ã‚る。 msg.setinterface モジュール「%sã€ã®ã‚¤ãƒ³ã‚¿ãƒ•ã‚§ãƒ¼ã‚¹ã‚’セットã—ãŸã€‚ msg.needsel モジュールã®ã‚¤ãƒ³ã‚¹ã‚¿ãƒ³ã‚¹ã‚’é¸ã‚“ã§ãã ã•ã„。 msg.wroteckpt 「%sã€ã«ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆã‚’書ã込んã ... msg.save 「%sã€ã«ä¿å­˜ã—ãŸã€‚ msg.reallynew 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€æ–°ã—ã„回路を開ãã¾ã™ã‹? msg.reallyquit 回路ã«å¤‰æ›´ãŒã‚る。本当ã«ä¿å­˜ã—ãªã„ã§ã€çµ‚了ã—ã¾ã™ã‹? msg.notlib モジュール「%sã€ã¯ãƒ©ã‚¤ãƒ–ラリ・モジュールã§ã¯ãªã„。 ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€ãŠå‰ã¿ãŸã„ãªå¤§é¦¬é¹¿ã—ã‹ã„ãªã„よ。 miles.msg2 é¦¬é¹¿ï¼ miles.msg3 æ„šã‹ã‚‚ã®ï¼ miles.msg4 マイルスã€ãã®ä½ç½®ã«ã‚²ãƒ¼ãƒˆã‚’ç½®ãã®ã¯ã€é¦¬é¹¿ã ã‚ˆã€‚ miles.msg5 馬鹿ãªã‚²ãƒ¼ãƒˆã®ä½ç½®ä»˜ã‘ã‚’ã‚„ã‚ã¦ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg6 ゲートをãã®ä½ç½®ã«ãŠã„ãŸã®ã¯ã€ãŠå‰ã®æ„šã‹ã•ã®è¨¼æ˜Žã ã‚ˆã€‚ miles.msg7 ã“ã®ãƒ­ã‚¯ã§ãªã—回路ã®è¨­è¨ˆã‚’諦ã‚よã€ãƒžã‚¤ã‚¹ãƒ«ã€‚ miles.msg8a 続ã‘ã¦ã‚‚ã€ç„¡é§„ã ã‚ˆã€ãƒžã‚¤ãƒ«ã‚¹ã€‚ miles.msg8b ãŠå‰ãŒå›žè·¯ã‚’設計出æ¥ãªã„ã¨ã„ã†ã®ã¯ã€èª°ã§ã‚‚分ã‹ã‚‹ã‚ˆã€‚ ############################################################################# # # Error messages generated by verga # verga.err.OK 心é…ã—ãªã„ã§ã€ç¬‘ã£ã¦ãã ã•ã„。 verga.err.INPORT TODO: Port size mismatch on input port '%s'. verga.err.OUTPORT TODO: Port size mismatch on output port '%s'. verga.err.FLOATNET TODO: Net '%s' has no drivers (floating net). verga.err.DIRECTCONN TODO: Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR TODO: Attempt to write to memory %s with unknown address. verga.err.MEMBITS TODO: Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG TODO: Array '%s' used in expression without index. verga.err.BADARRAYLHS TODO: Array '%s' used without index on left-hand-side. verga.err.BADCLOSE TODO: Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG TODO: Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG TODO: Bad gate instance range expression. verga.err.BADARGVALUE TODO: Bad value for argument %s in task %s. verga.err.DIVZERO TODO: Divide by zero. verga.err.NODIV TODO: Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT TODO: Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE TODO: Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT TODO: Event wait on assign is illegal. verga.err.PROTTASK TODO: Execution of protected system task '%s' blocked. verga.err.NEEDIDENT TODO: Expecting identifier for argument %s of task '%s'. verga.err.BADOP TODO: Expression operator error in '%s'. verga.err.NOREAD TODO: Failed to load source file '%s'. verga.err.MEMFILE TODO: Failed to open memory file '%s'. verga.err.WRONGMOD TODO: Found module '%s' when expecting '%s'. verga.err.NOTPARM TODO: Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR TODO: Illegal address range on port '%s'. verga.err.BADADDRSPEC TODO: Illegal address range specification '%s'. verga.err.BADCHAR TODO: Illegal character (%s) '%s'. verga.err.BADEVENT TODO: Illegal event control expression. verga.err.BADCONSTOP TODO: Illegal operator in constant expression. verga.err.BADXOP TODO: Illegal operator in expression. verga.err.NETREDEF TODO: Illegal redefinition of net '%s'. verga.err.BADINOUT TODO: Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF TODO: Instance of undefined module '%s'. verga.err.BADASGNLHS TODO: Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG TODO: Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS TODO: Invalid left-hand-side in assignment. verga.err.BADOUT TODO: Invalid output assignment. verga.err.NOTREG TODO: Memories must be declared as register. verga.err.PORTMIX TODO: Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE TODO: More than one default: in case statement. verga.err.NOMEM TODO: No current memory in memory file read. verga.err.BADCMD TODO: No such command '%s'. verga.err.CMDNOTNET TODO: No such net '%s' in '%s' command. verga.err.MEMNONBLK TODO: Non-blocking assignments to memories not implemented. verga.err.NOTPPORT TODO: Parameter '%s' is not declared as a port. verga.err.REDEFP TODO: Parameter redefines identifier '%s'. verga.err.PORTNOTDEF TODO: Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN TODO: Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN TODO: Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT TODO: Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE TODO: Range on port '%s' is not numeric. verga.err.BADARRAYRNG TODO: Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF TODO: Redefinition of dynamic module '%s'. verga.err.REDEF TODO: Redefinition of identifier %s. verga.err.PROTTASKSTOP TODO: Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM TODO: Specified net '%s' is not a memory. verga.err.CMDNOTMEM TODO: Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX TODO: Syntax error. verga.err.TOOFEWPP TODO: Too few parameter ports on instance %s. verga.err.OPENTOOMANY TODO: Too many files open in task '%s'. verga.err.TOOMANYPP TODO: Too many parameter ports on instance %s. verga.err.NOTOP TODO: Top-module '%s' not defined. verga.err.BADOPEN TODO: Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD TODO: Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET TODO: Undefined net '%s' in event control expression. verga.err.NOTASK TODO: Undefined task '%s'. verga.err.NOTDEF TODO: Undefined variable '%s'. verga.err.BADRANGE TODO: Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP TODO: Unimplemented primitive gate instance type. verga.err.USAGE TODO: Usage: thyme [options][files...] verga.err.CLSDWRITE TODO: Write to closed descriptor. verga.err.PRIMPTCOUNT TODO: Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS TODO: Wrong number of arguments in '%s' command. verga.err.YYERROR TODO: YYError - %s. verga.err.TASKARGS TODO: Task '%s' called with wrong number of arguments. verga.err.BADSTART TODO: Illegal start value in task '%s'. verga.err.BADSTOP TODO: Illegal stop value in $readmemb. verga.err.SPECTASKUSG TODO: Task %s must be used in a specify block. verga.err.BADSPECTASK TODO: Task %s can not be used in a specify block. verga.err.TIMING TODO: Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF TODO: No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL TODO: Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM TODO: Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT TODO: Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP TODO: Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF TODO: Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC TODO: Task '%s' used as function. verga.err.FUNCASTASK TODO: Function '%s' used as task. verga.err.TASKBADTYPE TODO: Non-register type used in task or function. verga.err.TASKBADPORT TODO: Only input ports are allowed on functions. verga.err.TIMESCALEU TODO: Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN TODO: Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES TODO: Invalid syntax in `timescale declartion. verga.err.TIMESCALEX TODO: Units must be larger than precision in `timescale declartion. verga.err.TIMESCALEAN TODO: Design contains some modules with `timescale and some without. verga.err.IE_TASK TODO: Task definition '%s' found outside module - internal error. verga.err.IE_NONET TODO: Failed to find net '%s' - internal error. verga.err.IE_BADTYPE TODO: Bogus port type for port '%s' - internal error. verga.err.IE_NOOP TODO: Can not find operator description -- internal error. verga.err.IE_NONEXPCTL TODO: Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL TODO: Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP TODO: Unexpected expression type %s - internal error. verga.err.IE_BADVAR TODO: Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE TODO: Unexpected internal state at %s - internal error. verga.err.IE_RETURN TODO: Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # Balloon Help # ho.net.in TODO: Single-Bit Input ho.net.out TODO: Single-Bit Output ho.net.inout TODO: Single-Bit Inout ho.net.in2 TODO: Multi-Bit Input ho.net.out2 TODO: Multi-Bit Output ho.net.inout2 TODO: Multi-Bit Inout ho.net.wire TODO: Single-Bit Wire (Name Visible) ho.net.wire2 TODO: Multi-Bit Wire (Name Visible) ho.net.hwire TODO: Single-Bit Wire (Name Hidden) ho.net.hwire2 TODO: Multi-Bit Wire (Name Hidden) ho.net.reg TODO: Single-Bit Reg ho.net.reg2 TODO: Multi-Bit Reg ho.opt.tool.file TODO: Save, load of circuit files ho.opt.tool.edit TODO: Cut, Paste and Find operations ho.opt.tool.gateopt TODO: Gate rotation and alignment operations ho.opt.tool.gateprop TODO: Basic editing of gates ho.opt.tool.undo TODO: Undo and redo operations ho.opt.tool.zoom TODO: Zoom in and zoom out ho.opt.tool.mode TODO: Select the editing tool ho.opt.tool.module TODO: Create, delete, rename,etc. of module definitions ho.opt.tool.tech TODO: Select default technology for gates ho.opt.tool.simctl TODO: Start, stop and pause of simulator ho.opt.tool.simaux TODO: Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.symmode TODO: Selecting editing tool in symbol editor ho.opt.tool.symedit TODO: Cut and paste operations for symbol editor ho.opt.tool.symport TODO: Port rotation operations for symbol editor ho.opt.tool.symshift TODO: Shift the bit map or portion of bitmap ho.opt.tool.symopr TODO: Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- TODO: If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- TODO: If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- TODO: Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- TODO: Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- TODO: Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- TODO: Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- TODO: Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- TODO: Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- TODO: Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- TODO: Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- TODO: Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- ç¾åœ¨ã®å›žè·¯ã‚’消ã—ã¦ã€æ–°ã—ㄠ回路を作æˆã™ã‚‹ã€‚ -end- ho.open 回路ファイルを開ã ho.save 回路ファイルをä¿å­˜ã™ã‚‹ ho.saveas TODO: Save circuit to specified file. ho.print 回路ファイルをå°åˆ·ã™ã‚‹ ho.library TODO: Open the library manager. ho.symed.tab.normal -begin- TODO: Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- TODO: Edit the selected symbol bitmap. -end- ho.move -begin- 移動ï¼æŽ¥ç¶š - ã“ã®ãƒ„ールã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ æ–°ã—ã„ゲートã®ä½ç½®ã‚’設定ã™ã‚‹ ゲートを移動ã™ã‚‹ ワイヤを移動ã™ã‚‹ ワイヤを接続ã™ã‚‹ ダブル・クリックã§ä»¥ä¸‹ã®æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ ゲートã®å±žæ€§ã‚’編集ã™ã‚‹ ワイヤã®å±žæ€§ã‚’編集ã™ã‚‹ ãƒãƒ¼ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ コメントã®ãƒ†ã‚­ã‚¹ãƒˆã®å±žæ€§ã‚’編集ã™ã‚‹ -end- ho.delgat -begin- ã“ã®ãƒ„ールã§ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ -end- ho.cutw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã‚’切断ã™ã‚‹ -end- ho.inv -begin- ã“ã®ãƒ„ールã§ã€ã‚²ãƒ¼ãƒˆã®å…¥å‡ºåŠ›ã« å¦å®šã‚’付ã‘ãŸã‚Šã€æ¶ˆã—ãŸã‚Šã™ã‚‹ã€‚ -end- ho.bitw -begin- ã“ã®ãƒ„ールã§ãƒ¯ã‚¤ãƒ¤ã®ãƒ“ット幅を 変更ã™ã‚‹ã€‚ビット幅をå³ä¸‹ã®å…¥åŠ› ボックスã«å…¥åŠ›ã—ã¦ãã ã•ã„。 -end- ho.ipanel.prot -begin- TODO: Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- TODO: Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- TODO: Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- TODO: Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- TODO: Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open é¸æŠžã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‹ã ho.mod.close ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é–‰ã˜ã‚‹ ho.mod.new TODO: Create a new module type. ho.mod.del TODO: Delete a module. ho.mod.copy TODO: Copy a module. ho.mod.rename TODO: Rename a module. ho.mod.claim -begin- TODO: Convert a library module to a regular module. -end- ho.mod.setroot -begin- TODO: Designate a module to be the root module. -end- ho.mod.type.allparts TODO: Set of Libraries ho.mod.type.partlib TODO: Library ho.mod.type.part TODO: Library module ho.mod.type.unknown TODO: Unknown module type ho.mod.type.unused TODO: Set of unused modules ho.mod.type.conflict TODO: Module recursion ho.mod.type.root TODO: Top-level module ho.mod.type.netlist TODO: Netlist module ho.mod.type.Lnetlist TODO: Netlist module (locked) ho.mod.type.hdl TODO: HDL module ho.mod.type.Lhdl TODO: HDL module (locked) ho.undo 最近行ã£ãŸå¤‰åŒ–を元通りã«ã™ã‚‹ã€‚ ho.redo undoã—ãŸå¤‰åŒ–ã‚’ã‚„ã‚Šç›´ã™ã€‚ ho.tab.edit -begin- TODO: Primary editing mode. -end- ho.tab.interface -begin- TODO: Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- シミュレータを開始ã—ã€è«–ç†ã‚¢ãƒŠãƒ©ã‚¤ã‚¶ã®ã‚¦ã‚£ãƒ³ãƒ‰ã‚’ é–‹ãã€ãã—ã¦åˆæœŸåŒ–スクリプトãŒå®šç¾©ã—ã¦ã„ã‚‹å ´åˆã€ ãã®ã‚¹ã‚¯ãƒªãƒ—トを実行ã™ã‚‹ã€‚ -end- ho.tab.cpath -begin- 回路ã®ã‚¯ãƒªãƒ†ã‚£ã‚«ãƒ«ãƒ»ãƒ‘スを探索ã™ã‚‹ã€‚ -end- ho.log -begin- TODO: Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- シミュレータを動ã‹ã™ã€‚組åˆã›å›žè·¯ã®å ´åˆã€ ä¿¡å·ãŒå¤‰ã‚らãªããªã‚‹æ™‚ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ ãŒä¸€æ™‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.simpause -begin- シミュレータã®ä¸€æ™‚åœæ­¢ -end- ho.simstep -begin- シミュレータを一定数ã®ã‚¨ãƒãƒƒã‚¯ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simclock -begin- シミュレータを一定数ã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚µã‚¤ã‚¯ãƒ« ã ã‘å‹•ã‹ã™ã€‚ ステップ数ã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ãƒˆã®è¨­å®šã«ã‚ˆã‚‹ã€‚ -end- ho.simstop -begin- シミュレータをåœæ­¢ã—ã¦ã€ 編集モードã«æˆ»ã‚‹ã€‚ -end- ho.simbreak -begin- シミュレータã®ãƒ–レークãƒã‚¤ãƒ³ãƒˆ を編集ã™ã‚‹ã€‚ -end- ho.simexec -begin- スクリプトを実行ã™ã‚‹ã€‚ -end- ho.simoptions -begin- TODO: Set various options that control the simulation. -end- ho.simload -begin- メモリ・ファイルを読ã¿è¾¼ã‚€ -end- ho.simdump -begin- メモリ・ファイルã«æ›¸ã出㙠-end- ho.f.modlist -begin- 読ã¿è¾¼ã‚“ã§ã‚るモジュールã®ä¸€è¦§è¡¨ã€‚ トップã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®åå‰ã«ã€Œ+ã€ãŒ 付ã„ã¦ã„る。ライブラリã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« ã¯æ‹¬å¼§ã«å›²ã¾ã‚Œã¦ã„る。 -end- ho.f.modlisttab -begin- TODO: List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ä¸€è¦§è¡¨ã€‚åå‰ã‚’éš ã—㦠ã„ã‚‹ãƒãƒƒãƒˆã®åå‰ã«ã€Œ@ã€ãŒä»˜ã„ã¦ã„る。 マルãƒãƒ»ãƒ“ットã®ãƒãƒƒãƒˆã®åå‰ã®å¾Œã« ビットã®ãƒ¬ãƒ³ã‚¸ã‚’表示ã—ã¦ã„る。 -end- ho.ports -begin- ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒãƒ¼ãƒˆã®ä¸€è¦§è¡¨ã€‚ 入力ã«ã€Œ>ã€ã€å‡ºåŠ›ã«ã€Œ<ã€ã€å…¥å‡ºåŠ›ã« 「=ã€ãŒä»˜ã„ã¦ã„る。 -end- ho.status.logo -begin- ç¾åœ¨ã®ãƒ¢ãƒ¼ãƒ‰ãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。鉄ã®ã‚²ãƒ¼ãƒˆ ã¯ç·¨é›†ãƒ¢ãƒ¼ãƒ‰ã‚’表ã™ã€‚ANDゲートã¯ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ ション・モードを表ã™ã€‚ANDゲートãŒèµ°ã£ã¦ ã„る時ã€ã‚·ãƒŸãƒ¥ãƒ¬ãƒ¼ã‚·ãƒ§ãƒ³ã®æ™‚é–“ãŒå‹•ã„ã¦ã„る。 -end- ho.status.msg tkgateよりã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ãŒã“ã“ã«è¡¨ç¤ºã•ã‚Œã‚‹ã€‚ ho.status.block ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ãƒ‘ス ho.status.file -begin- ç¾åœ¨ç·¨é›†ä¸­ã®ãƒ•ã‚¡ã‚¤ãƒ«åãŒè¡¨ç¤ºã•ã‚Œã¦ã„る。「*〠ã¨ã„ã†è¨˜å·ãŒã¤ã„ã¦ã„る時ã€ä¿å­˜ã—ã¦ã„ãªã„変更 ãŒã‚る。 -end- ho.print.selall å…¨ã¦ã®èª­ã¿è¾¼ã‚“ã§ã„るモジュールをå°åˆ·ã™ã‚‹ã€‚ ho.print.selcur ç¾åœ¨ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ ho.print.seluse -begin- 使用中ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã®ã¿å°åˆ·ã™ã‚‹ã€‚ -end- ho.print.fulltrace TODO: Print the entire trace. ho.print.parttrace -begin- TODO: Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart TODO: Starting time of trace output. ho.print.parttraceend TODO: Ending time of trace output. ho.print.selsel -begin- 以下ã«ãƒžãƒ¼ã‚¯ã—ã¦ã„るモジュールã®ã¿ã‚’å°åˆ·ã™ã‚‹ã€‚ コントロール・キーã§è¤‡æ•°ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠž 出æ¥ã‚‹ã€‚ -end- ho.print.modlist å°åˆ·ã™ã‚‹ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’é¸æŠžã™ã‚‹ã€‚ ho.circuit.discchg -begin- 有効ã«ã™ã‚‹ã¨ã€å¤‰æ›´ã‚ã‚Šã®å›žè·¯ã‚’ ä¿å­˜ã—ãªã„ã§é–‰ã˜ã‚‹ã¨ã警告ã—ãªã„。 -end- ho.circuit.extbar -begin- 基本ゲート(AND, OR, XOR)ã®å…¥åŠ›æ•°ãŒ 3本以上ã®æ™‚ã€æ‹¡å¼µãƒãƒ¼ã¯åˆ©ç”¨ã™ã‚‹ã€‚ -end- ho.circuit.autostart -begin- TODO: If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- カーソルã§é¸æŠžã•ã‚ŒãŸãƒ¯ã‚¤ãƒ¤ã¯è¡¨ç¤º ã•ã‚Œã¦ã„るビット幅ã«è¨­å®šã•ã‚Œã‚‹ã€‚ -end- ho.edgat.signam -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã§ã‚る。åå‰ãŒå¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.port -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆåã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.iolab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒãƒ¼ãƒˆæ–¹å‘ã§ã‚る。モジュール ã®ã‚²ãƒ¼ãƒˆã®å ´åˆã®ã¿å¤‰æ›´å‡ºæ¥ã‚‹ã€‚ -end- ho.edgat.bitlab -begin- é¸æŠžã•ã‚ŒãŸã‚²ãƒ¼ãƒˆã®é¸æŠžã•ã‚ŒãŸ ãƒãƒƒãƒˆã®ãƒ“ット幅ã§ã‚る。変更出æ¥ã‚‹ã€‚ -end- ho.edgat.cycle 一サイクルã®ã‚¨ãƒãƒƒã‚¯æ•° ho.edgat.phase クロックã®ãƒ•ã‚§ãƒ¼ã‚ºï¼ˆãƒ‘ーセントã§è¨­å®šã™ã‚‹ï¼‰ ho.edgat.duty クロック・サイクルã®ä½•ãƒ‘ーセントãŒè«–ç†0ã§ã‚ã‚‹ã‹ ho.edgat.hide -begin- 有効ã«ã™ã‚‹ã¨ã‚²ãƒ¼ãƒˆåãŒè¡¨ç¤ºã•ã‚Œãªã„。 -end- ho.edgat.gtype ゲートã®ç¨®é¡ž ho.edgat.gname ゲートã®åå‰ ho.edgat.ganchor 有効ã«ã™ã‚‹ã¨ã€ã‚²ãƒ¼ãƒˆãŒç§»å‹•ä¸å¯ã«ãªã‚‹ã€‚ ho.edgat.gx ゲートã®Xä½ç½® ho.edgat.gy ゲートã®Yä½ç½® ho.edgat.swstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.dipstate -begin- シミュレーションを始ã‚る時ã®åˆæœŸã®å€¤ã§ã‚る。 -end- ho.edgat.range マルãƒãƒ“ットã®ä¿¡å·ã®ã‚µãƒ–・レンジã§ã‚る。 ho.edgat.memfile -begin- メモリã®åˆæœŸã®å€¤ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’指定ã™ã‚‹ã€‚ シミュレーションを始ã‚る時ã€ã“ã®ãƒ•ã‚¡ã‚¤ãƒ« ãŒèª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.edgat.func モジュールã®æ©Ÿèƒ½ ho.edgat.frame フレームã®ãƒ©ãƒ™ãƒ« ho.traceprint TODO: Print trace logic trace. ho.showxhair -begin- TODO: If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- TODO: Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- TODO: Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- TODO: Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- TODO: Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- TODO: Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- TODO: Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- TODO: Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- TODO: Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- TODO: Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- TODO: If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- TODO: If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- TODO: If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- TODO: Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- TODO: Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- TODO: Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- TODO: If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- TODO: If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- TODO: List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- TODO: Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- TODO: Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- TODO: Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- TODO: Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- TODO: Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- TODO: List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- TODO: List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- TODO: List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- undoã®ãƒªã‚¹ãƒˆã®é•·ã• -end- ho.opt.name -begin- TODO: User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- 回路ãªã©ã‚’å°åˆ·ã™ã‚‹æ™‚ã€ã“ã®ã‚µã‚¤ãƒˆåãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.smooth -begin- ã“ã®è¨­å®šã‚’有効ã«ã™ã‚‹ã¨ã€å›žè·¯ã‚’スクロールã™ã‚‹æ™‚〠ビットマップã®ã‚³ãƒ”ーを利用ã—ã¦ã€åŠ¹çŽ‡ã‚ˆã スクロールã§ãる。Xサーãƒã®å•é¡ŒãŒã‚ã‚Œã°ã€ã“㮠設定を無効ã«ã™ã‚Œã°è‰¯ã„。 -end- ho.opt.clip -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¦ã‚¤ãƒ³ãƒ‰ã‚¦ã®éƒ¨åˆ†é ˜åŸŸã® å†æ画を行ãªã†ã€‚ãã†ã§ãªã‘ã‚Œã°å¸¸ã« 全領域をå†æç”»ã™ã‚‹ã€‚ -end- ho.opt.showimage -begin- TODO: Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã‚’移動ã™ã‚‹æ™‚〠ワイヤãªã©ã¯ãƒžã‚¦ã‚¹ã®ãƒœã‚¿ãƒ³ã‚’離ã™ã¾ã§ 移動ã—ãªã„。画é¢ã®è¡¨ç¤ºãŒé…ã„時ã«ä¾¿åˆ©ã§ã‚る。 -end- ho.opt.bhelp -begin- 有効ã«ã™ã‚‹ã¨ã€ã“ã®ãƒ¡ãƒƒã‚»ãƒ¼ã‚¸ã®æ§˜ãªã€Œãƒ˜ãƒ«ãƒ—・ ãƒãƒ«ãƒ¼ãƒ³ã€ãŒè¡¨ç¤ºã•ã‚Œã‚‹ã€‚ -end- ho.opt.novice -begin- 有効ã«ã™ã‚‹ã¨ã€åˆå¿ƒè€…モードã«ãªã‚‹ã€‚ åˆå¿ƒè€…モードã§ã¯ã€tkgateãŒç«‹ã¡ä¸ŠãŒã‚‹æ™‚〠ãƒãƒ¥ãƒ¼ãƒˆãƒªã‚¢ãƒ«ãŒè‡ªå‹•çš„ã«èª­ã¿è¾¼ã¾ã‚Œã‚‹ã€‚ -end- ho.opt.blockDropConnect -begin- TODO: Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒ‡ãƒã‚°æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ 開発者以外ã«ã€ã‚ã¾ã‚Šå½¹ã«ç«‹ãŸãªã„。 -end- ho.opt.ckpt 有効ã«ã™ã‚‹ã¨ã€tkgateã¯ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã®ãƒ•ã‚¡ã‚¤ãƒ«ã‚’作る。 ho.opt.ckptfreq ãƒã‚§ãƒƒã‚¯ãƒã‚¤ãƒ³ãƒˆä¿å­˜ã‚’何クリック毎ã«è¡Œãªã†ã‹ ho.opt.beak -begin- 全然役ã«ç«‹ãŸãªã„機能を有効ã«ã™ã‚‹ã€‚ã“ã®æ©Ÿèƒ½ã‚’ 無効ã«ã™ã‚‹ã¨ã€ã“ã®ã‚¹ã‚¤ãƒƒãƒã¯ãƒ€ã‚¤ã‚¢ãƒ­ã‚° ボックスã‹ã‚‰æ¶ˆãˆã€.tkgate-propertiesを編集ã—ãªã„é™ã‚Š 戻らãªã„。 -end- ho.opt.miles -begin- 有効ã«ã™ã‚‹ã¨ã€tkgateã¯æ™‚々ユーザを 馬鹿ã«ã—ãŸã‚Šã€æ‚ªå£ã‚’言ã£ãŸã‚Šã™ã‚‹ã€‚ -end- ho.opt.bat -begin- 有効ã«ã™ã‚‹ã¨ã€ãƒãƒƒãƒˆãƒžãƒ³ã®ã‚³ãƒ³ãƒ”ュータを 設計ã™ã‚‹ç‚ºã«ã€Œå½¹ã«ãŸã¤ã€æ©Ÿèƒ½ãŒä½¿ãˆã‚‹ã€‚ -end- ho.opt.trek 転é€ã—ã‚ã€ã‚¹ã‚³ãƒƒãƒ†ã‚£ï¼ ho.opt.simstep -begin- シミュレータã®ã‚¹ãƒ†ãƒƒãƒ—・コマンド㧠何エãƒãƒƒã‚¯é€²ã‚€ã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckstep -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ã‚¹ãƒ†ãƒƒãƒ—・ コマンド㧠何サイクル進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.ckover -begin- シミュレータã®ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ クロックã®ã‚¨ãƒƒã‚¸ã‚ˆã‚Šæ›´ã«ä½•ã‚¨ãƒãƒƒã‚¯ 進むã‹ã‚’指定ã™ã‚‹ã€‚ -end- ho.opt.vpopupdelay -begin- マウスボタンを押ã—ã¦ã‹ã‚‰ã€ä½•ãƒŸãƒªç§’経ã£ã¦ ã‹ã‚‰ä¿¡å·ã®å€¤ãŒè¡¨ç¤ºã•ã‚Œã‚‹é…延ã§ã‚る。 ã“ã® é…延ãŒçŸ­éŽãŽã‚‹æ™‚ã€ãƒ€ãƒ–ルクリック㌠èªçŸ¥ ã§ããªããªã‚‹å•é¡ŒãŒã‚るシステム㯠ã‚る。 ã“ã®å•é¡ŒãŒèµ·ã“らãªã‘ã‚Œã°ã€é…延 をより 短ãã—ã¦ã‚‚良ã„。 -end- ho.opt.init -begin- シミュレータを立ã¡ä¸Šã’る時㫠自動的ã«å®Ÿè¡Œã™ã‚‹ã‚¹ã‚¯ãƒªãƒ—ト・ ファイルを指定ã™ã‚‹ã€‚ -end- ho.opt.ckall -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ ã©ã®ã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã§ã‚‚åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.ckspec -begin- 有効ã«ã™ã‚‹ã¨ã€ã‚¯ãƒ­ãƒƒã‚¯ãƒ»ã‚³ãƒžãƒ³ãƒ‰ã¯ 指定ã—ãŸã‚¯ãƒ­ãƒƒã‚¯ã®ã‚¨ãƒƒã‚¸ã®ã¿ã«åœæ­¢ã™ã‚‹ã€‚ -end- ho.opt.keybind -begin- TODO: Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- æ–°ã—ã„ゲートã®ãƒ‡ãƒ•ã‚©ãƒ«ãƒˆã®ãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ã€‚ ゲートã®é…延ã«å½±éŸ¿ã™ã‚‹ã€‚ä»»æ„ã®ã‚²ãƒ¼ãƒˆ 㮠テクノロジーを変更ã™ã‚‹ã«ã¯ã€ã‚²ãƒ¼ãƒˆã®è¨­å®š ボックスを開ã„ã¦ã€ã€Œé…延ã€ã®ã‚¿ãƒ– ã‚’é¸æŠž ã—ã¦ä¸‹ã•ã„。 -end- ho.techbut -begin- 指定ã—ãŸãƒ†ã‚¯ãƒŽãƒ­ã‚¸ãƒ¼ãƒ»ãƒ•ã‚¡ã‚¤ãƒ«ã‹ã‚‰ã® é…延値を 利用ã™ã‚‹ã€‚æ–°ã—ã„テクノロジーを 追加ã™ã‚‹ç‚ºã€ã€Œãƒ•ã‚¡ã‚¤ãƒ«ã€â†’「設定...ã€â†’ 「シミュレート〠ã®ãƒ¡ãƒ‹ãƒ¥ãƒ¼ã‚’é–‹ã„ã¦ã€ ファイルã®ãƒªã‚¹ãƒˆã«è¿½åŠ  ã—ã¦ä¸‹ã•ã„。 -end- ho.custbut -begin- ã“ã®ã‚²ãƒ¼ãƒˆå°‚用ã®é…延値を指定ã™ã‚‹ã€‚ -end- ho.contver -begin- マウスæ“作を行ãªã†æ™‚ã€å†…部構造を自動的㫠確èªã—ã¦ã€ä¸æ­£ã®æ‰€ã‚’知らã™ã€‚ -end- ho.simwatch -begin- シミュレータã¨GUIã®é–“ã®ã‚³ãƒžãƒ³ãƒ‰ã‚’表示ã™ã‚‹ã€‚ -end- ho.symed.point -begin- TODO: Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- TODO: Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- TODO: Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- TODO: Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- TODO: Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- TODO: Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift TODO: Shift selected pixels right. ho.symed.lshift TODO: Shift selected pixels left. ho.symed.ushift TODO: Shift selected pixels up. ho.symed.dshift TODO: Shift selected pixels down. ho.symed.cwrotate TODO: Rotate selected pixels clockwise. ho.symed.ccwrotate TODO: Rotate selected pixels counter-clockwise. ho.symed.autobold TODO: Make selected image bold. ho.symed.resize TODO: Resize the image editor. ho.tool.currot -begin- TODO: Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin ズーム・イン ho.tool.zoomout ズーム・アウト ho.tool.rotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’éžæ™‚計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.brotate é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’時計周りã«å›žè»¢ã™ã‚‹ã€‚ ho.tool.valgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’縦ã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.halgn é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ç¿Œã«ä¸€åˆ—ã«ä¸¦ã¶ã€‚ ho.tool.cut é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚«ãƒƒãƒˆã™ã‚‹ã€‚ ho.tool.copy é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’ãƒãƒƒãƒ•ã‚¡ã«ã‚³ãƒ”ーã™ã‚‹ã€‚ ho.tool.paste カットãƒãƒƒãƒ•ã‚¡ã®ã‚²ãƒ¼ãƒˆã‚’張り付ã‘る。 ho.tool.find ゲートã€ãƒ¯ã‚¤ãƒ¤ã€ãƒ†ã‚­ã‚¹ãƒˆãªã©ã‚’探索ã™ã‚‹ã€‚ ho.tool.addport é¸æŠžã®ã‚²ãƒ¼ãƒˆã«ãƒãƒ¼ãƒˆã‚’追加ã™ã‚‹ã€‚ ho.tool.anchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動ä¸å¯ã«ã™ã‚‹ã€‚ ho.tool.unanchor é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’移動å¯èƒ½ã«ã™ã‚‹ã€‚ ho.tool.replicate ゲートを複製ã™ã‚‹ã€‚ ho.tool.delete é¸æŠžã®ã‚²ãƒ¼ãƒˆã‚’削除ã™ã‚‹ã€‚ tkgate-2.0-b10/locale/ja/obsolete-tutorials/create_tut.v000644 001751 001751 00000007161 10104464431 024027 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(232,502)(177,502){1} //: {2}(175,500)(175,466)(187,466){3} //: {4}(173,502)(141,502){5} wire w7; //: /sn:0 {0}(253,500)(263,500){1} wire w2; //: /sn:0 {0}(187,461)(141,461){1} wire w5; //: /sn:0 {0}(232,497)(218,497)(218,464)(208,464){1} //: enddecls or g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(243,500) /sn:0 /anc:1 /w:[ 0 0 0 ] //: comment g8 @(248,476) /anc:1 //: /line:"OR¥²¡¼¥È" //: /end //: comment g61 @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: frame g13 @(412,372) /sn:0 /wi:381 /ht:177 /tx:"²óÏ©¤ò¤³¤ÎÃæ¤ËºîÀ®¤·¤Æ²¼¤µ¤¤" and g3 (.I0(w2), .I1(w6), .Z(w5)); //: @(198,464) /sn:0 /anc:1 /w:[ 0 3 1 ] //: switch g2 (w6) @(124,502) /sn:0 /anc:1 /w:[ 5 ] /st:0 //: switch g1 (w2) @(124,461) /sn:0 /anc:1 /w:[ 1 ] /st:0 //: comment g16 @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: comment g10 @(11,205) /anc:1 //: /line:"5) AND¥²¡¼¥È¤ÈOR¥²¡¼¥È¤ÈƱ¤¸ÍͤËÆó¤Ä¤Î¥¹¥¤¥Ã¥Á¤òºîÀ®¤·¤Æ²¼¤µ¤¤¡£¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤Î¡ÎI/O¡Ï" //: /line:"¥µ¥Ö¥á¥Ë¥å¡¼¤Î¡Î¥¹¥¤¥Ã¥Á¡Ï¤òÁª¤ó¤Ç¡¢Ëô¤Ï¡¢¥­¡¼¥Ü¡¼¥É¡¦¥·¥ç¡¼¥È¥«¥Ã¥È¤Î\"s\"¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"6) ¥¹¥Æ¥Ã¥×4¤ò·«¤êÊÖ¤·¤Æ¡¢¾å¤Î¥¹¥¤¥Ã¥Á¤Î½ÐÎϤòAND¥²¡¼¥È¤Î¾å¤Î½ÐÎϤËÀܳ¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"7) ¥¹¥Æ¥Ã¥×4¤ò·«¤êÊÖ¤·¤Æ¡¢²¼¤Î¥¹¥¤¥Ã¥Á¤Î½ÐÎϤòOR¥²¡¼¥È¤Î²¼¤Î½ÐÎϤËÀܳ¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"8) AND¥²¡¼¥È¤Î²¼¤ÎÆþÎϤò¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¤Ï¤ó¤À¤´¤Æ¤ò½Ð¤·¡¢²¼¤Î¥¹¥¤¥Ã¥Á¤ÈOR¥²¡¼¥È¤Î´Ö¤Î" //: /line:"¥ï¥¤¥ä¤Î¿¿Ãæ¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢¥Þ¥¦¥¹¥Ü¥¿¥ó¤òÎ¥¤·¤Æ²¼¤µ¤¤¡£ÀܳÅÀ¤¬ºîÀ®¤µ¤ì¤Þ¤¹¡£" //: /end //: comment g6 @(101,427) /anc:1 //: /line:"¥¹¥¤¥Ã¥Á" //: /end //: comment g7 @(192,436) /anc:1 //: /line:"AND¥²¡¼¥È" //: /end //: comment g9 @(12,9) /anc:1 //: /line:"1) ¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ç¤Ï¡¢²¼¤Ë¼¨¤·¤Æ¤¢¤ë¤Î¤ÈƱ¤¸ÍͤʲóÏ©¤òºîÀ®¤¹¤ë¡£±¦²¼¤Î" //: /line:"ÅÀ¤ÎÈ¢¤ÎÃæ¤ËºîÀ®¤·¤Æ²¼¤µ¤¤¡£¤Þ¤º¡¢¥Þ¥¦¥¹¤Î±¦¥Ü¥¿¥ó¤ÇAND¥²¡¼¥È¤Î°ÌÃÖ¤òÁª¤ó¤Ç" //: /line:"²¼¤µ¤¤¡£¥¯¥ê¥Ã¥¯¤·¤¿°ÌÃÖ¤ËX°õ¤È¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤¬¸½¤ì¤Þ¤¹¡£" //: /line:"" //: /line:"2) ¤½¤ì¤«¤é¡¢¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤Î¡Î¥²¡¼¥È¡Ï¥µ¥Ö¥á¥Ë¥å¡¼¤Î¡ÎAND¡Ï¤òÁª¤ó¤Ç²¼¤µ¤¤¡£" //: /line:"¥á¥Ë¥å¡¼¡¦¥Ð¡¼¡¢Ëô¤Ï¥­¡¼¥Ü¡¼¥É¡¦¥·¥ç¡¼¥È¥«¥Ã¥È¤Î\"a\"¤â»È¤¨¤Þ¤¹¡£" //: /line:"" //: /line:"3) ¥¹¥Æ¥Ã¥×1¡¢2¤ò·«¤êÊÖ¤·¤Æ, OR¥²¡¼¥È¤òAND¥²¡¼¥È¤Î±¦²¼¤Î°ÌÃ֤˺îÀ®¤·¤Æ²¼¤µ¤¤¡£" //: /line:"¥á¥Ë¥å¡¼¡¦¥Ð¡¼¡¢Ëô¤Ï¥­¡¼¥Ü¡¼¥É¥·¥ç¡¼¥È¡¦¥«¥Ã¥È¤Î\"o\"¤â»È¤¨¤Þ¤¹¡£" //: /line:"" //: /line:"4) AND¥²¡¼¥È¤Î½ÐÎϤΥ磻¥ä¤ÎÀèü¤ò¥Þ¥¦¥¹¤Îº¸¥Ü¥¿¥ó¤Ç¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Ü¥¿¥ó¤ò²¡¤·" //: /line:"¤¿¤Þ¤Þ¤Ë¤·¤Þ¤¹¡£¥Þ¥¦¥¹¡¦¥«¡¼¥½¥ë¤¬¤Ï¤ó¤À¤´¤Æ¤ËÊѤï¤ê¤Þ¤¹¡£¥ï¥¤¥ä¤òOR¥²¡¼¥È¤Î" //: /line:"¾å¤ÎÆþÎϤޤǥɥé¥Ã¥°¤·¤Æ¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤òÎ¥¤¹¤È¡¢¥ï¥¤¥ä¤¬Àܳ¤µ¤ì¤Þ¤¹¡£" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 @(622,55) /sn:0 /anc:1 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: comment g17 @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: joint g5 (w6) @(175, 502) /anc:1 /w:[ 1 2 4 -1 ] //: comment g14 @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g0 @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g22 @(605,55) /sn:0 //: /line:"->" //: /end //: comment g18 @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/edit1_tut.v000644 001751 001751 00000014271 10011742667 023601 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w7; //: /sn:0 {0}(682,363)(697,363)(697,375){1} wire s0; //: {0}(750,310)(780,310){1} wire w4; //: /sn:0 {0}(702,345)(702,375){1} wire c0; //: {0}(598,268)(704,268)(704,310){1} //: {2}(706,312)(729,312){3} //: {4}(704,314)(704,324){5} wire c1; //: {0}(700,396)(700,433){1} //: {2}(702,435)(725,435){3} //: {4}(700,437)(700,447){5} wire s1; //: /dp:1 {0}(746,433)(781,433){1} wire a1; //: {0}(598,427)(638,427){1} //: {2}(642,427)(650,427){3} //: {4}(640,429)(640,483)(657,483){5} wire b1; //: {0}(598,462)(632,462){1} //: {2}(634,460)(634,432)(650,432){3} //: {4}(634,464)(634,488)(657,488){5} wire w8; //: /sn:0 {0}(678,486)(693,486)(693,498){1} wire a0; //: /dp:1 {0}(598,304)(642,304){1} //: {2}(646,304)(654,304){3} //: {4}(644,306)(644,360)(661,360){5} wire b0; //: /dp:1 {0}(598,339)(636,339){1} //: {2}(638,337)(638,309)(654,309){3} //: {4}(638,341)(638,365)(661,365){5} wire c2; //: {0}(783,530)(696,530)(696,519){1} wire w10; //: /sn:0 {0}(725,430)(697,430){1} //: {2}(693,430)(671,430){3} //: {4}(695,432)(695,447){5} wire w5; //: /sn:0 {0}(698,468)(698,498){1} wire w9; //: /sn:0 {0}(729,307)(701,307){1} //: {2}(697,307)(675,307){3} //: {4}(699,309)(699,324){5} //: enddecls //: joint g8 (c1) @(700, 435) /w:[ 2 1 -1 4 ] nand g4 (.I0(w8), .I1(w5), .Z(c2)); //: @(696,509) /sn:0 /R:3 /w:[ 1 1 1 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end led g37 (.I(s0)); //: @(787,310) /sn:0 /R:3 /w:[ 1 ] /type:0 xor g34 (.I0(w10), .I1(c1), .Z(s1)); //: @(736,433) /sn:0 /w:[ 0 3 0 ] //: comment g3 /dolink:0 /link:"" @(29,249) /anc:1 //: /line:"5) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥Ó¥Ã¥ÈÉý¡×¤òÁªÂò¤·¤Æ¡¢¥ê¥Ü¥ó¥±¡¼¥Ö¥ë¤Î¥Ä¡¼¥ë¤ò½Ð¤·" //: /line:"¤Æ²¼¤µ¤¤¡£¤½¤¦¤¹¤ë¤È¡¢¥¦¥£¥ó¥É¥¦±¦²¼¤Ë¡Ö¥Ó¥Ã¥ÈÉý¡×¤ÎÆþÎϥܥ寥¹¤¬½Ð¤Þ¤¹¡£" //: /line:"¥Ü¥Ã¥¯¥¹¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¡¢1¡Á32¤Î¿ô»ú¤òÆþÎϤ·¤Æ²¼¤µ¤¤¡£¤½¤ì¤«¤é¥ï¥¤¥ä¤ò" //: /line:"¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¼¨¤·¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤷ¤Æ¤ß¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"6) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö°ÜÆ°¡¿Àܳ¡×¤òÁªÂò¤·¡¢¥ï¥¤¥ä¤ò¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤¹¤ë" //: /line:"¤È¡¢Â°À­¥Ü¥Ã¥¯¥¹¤¬³«¤­¤Þ¤¹¡£¥Í¥Ã¥È̾¡¢¥Í¥Ã¥È̾¤òɽ¼¨¤¹¤ë¤«¤É¤¦¤«¡¢¥Ó¥Ã¥ÈÉý" //: /line:"¤Ê¤É¤Î°À­¤¬ÀßÄê¤Ç¤­¤Þ¤¹¡£¥Þ¥¦¥¹¤Î±¦¥Ü¥¿¥ó¤Î¥á¥Ë¥å¡¼¤Ç¤âÀßÄê¤Ç¤­¤Þ¤¹¡£" //: /line:"" //: /line:"7) OR¥²¡¼¥È¤Ê¤É¤ò¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥²¡¼¥È¤Î°À­¥Ü¥Ã¥¯¥¹¤¬³«¤­¤Þ¤¹¡£" //: /line:"¥²¡¼¥È̾¡¢¥²¡¼¥È̾¤òɽ¼¨¤¹¤ë¤«¤É¤¦¤«¡¢¥²¡¼¥È¤¬°ÜÆ°½ÐÍè¤ë¤«¤É¤¦¤«¤Ê¤É¤Î" //: /line:"°À­¤¬ÀßÄê½ÐÍè¤Þ¤¹¡£¥Ý¡¼¥È¤ÎÄɲᢺï½ü¡¢ÊÔ½¸¤Ê¤É¤â½ÐÍè¤Þ¤¹¡£" //: /line:"" //: /line:"8) ¥²¡¼¥È¤ò¥Þ¥¦¥¹±¦¥Ü¥¿¥ó¤Ç¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¡Ö°ÜÆ°ÉԲġפΥե饰¤ò¥»¥Ã¥È¤·¤Æ" //: /line:"¤ß¤Æ²¼¤µ¤¤¡£¤³¤Î¥Õ¥é¥°¤¬¥»¥Ã¥È¤·¤Æ¤¢¤ì¤Ð¡¢¥²¡¼¥È¤Î°ÜÆ°¤Ï½ÐÍè¤Þ¤»¤ó¡£" //: /end //: comment g2 /dolink:0 /link:"" @(29,38) /anc:1 //: /line:"1) ¥Þ¥¦¥¹¤Îº¸¥Ü¥¿¥ó¤Ç¥²¡¼¥È¤ò¥¯¥ê¥Ã¥¯¤·¡¢¥Ü¥¿¥ó¤ò²¡¤·¤¿¤Þ¤ÞÊ̤ξì½ê¤Ë°ÜÆ°" //: /line:"¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤Ë·Ò¤¤¤Ç¤¤¤ë¥ï¥¤¥ä¤â°ì½ï¤Ë°ÜÆ°¤·¤Þ¤¹¡£" //: /line:"" //: /line:"2) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥ï¥¤¥ä¤ÎÀÚÃǡפòÁªÂò¤·¤Æ¡¢¥«¥Ã¥¿¡¼¤Î¥Ä¡¼¥ë¤ò" //: /line:"½Ð¤·¡¢¥ï¥¤¥ä¤Î¤É¤³¤«¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£²¿¤Ë¤â·Ò¤¤¤Ç¤¤¤Ê¤¤¥ï¥¤¥ä¤Î" //: /line:"Éôʬ¤Ï¼«Æ°Åª¤Ëºï½ü¤µ¤ì¤Þ¤¹¡£¥Þ¥¦¥¹±¦¥Ü¥¿¥ó¤Ç³«¤¯¥á¥Ë¥å¡¼¤òÍøÍѤ·¤Æ¤â" //: /line:"¥«¥Ã¥¿¡¼¤ò½Ð¤»¤Þ¤¹¡£" //: /line:"" //: /line:"3) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡ÖÈÝÄê¡×¤òÁªÂò¤·¤Æ¡¢ÈÝÄê¥Ä¡¼¥ë¤ò½Ð¤·¡¢¥²¡¼¥È¤Î" //: /line:"ÆþÎϤä½ÐÎϤò¥¯¥ê¥Ã¥¯¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£ÈÝÄê¤Î´Ý¤¬¸½¤ì¤¿¤ê¡¢¾Ã¤¨¤¿¤ê¤·¤Þ¤¹¡£" //: /line:"" //: /line:"4) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥²¡¼¥È¤Îºï½ü¡×¤òÁªÂò¤·¡¢¥²¡¼¥È¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¤ß¤Æ" //: /line:"²¼¤µ¤¤¡£¥²¡¼¥È¤¬ºï½ü¤µ¤ì¤Þ¤¹¡£¥²¡¼¥È¤òÁªÂò¤·¤Æ¡¢¥Ç¥ê¡¼¥È¡¦¥­¡¼¤ò²¡¤·¤¿¤ê¡¢" //: /line:"¥Þ¥¦¥¹±¦¥Ü¥¿¥ó¤Ç¡Öºï½ü¡×¤òÁªÂò¤·¤¿¤ê¤¹¤ë¤³¤È¤Ç¤â¥²¡¼¥È¤¬ºï½ü¤Ç¤­¤Þ¤¹¡£" //: /end nand g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(700,386) /sn:0 /R:3 /w:[ 1 1 0 ] //: switch g11 (a1) @(581,427) /sn:0 /w:[ 0 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: joint g10 (a1) @(640, 427) /w:[ 2 -1 1 4 ] nand g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(672,363) /sn:0 /w:[ 5 5 0 ] led g19 (.I(s1)); //: @(788,433) /sn:0 /R:3 /w:[ 1 ] /type:0 //: switch g27 (c0) @(581,268) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(699, 307) /w:[ 1 -1 2 4 ] //: joint g38 (b1) @(634, 462) /w:[ -1 2 1 4 ] nand g6 (.I0(a1), .I1(b1), .Z(w8)); //: @(668,486) /sn:0 /w:[ 5 5 0 ] nand g9 (.I0(w10), .I1(c1), .Z(w5)); //: @(698,458) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g7 (w10) @(695, 430) /w:[ 1 -1 2 4 ] nand g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(702,335) /sn:0 /R:3 /w:[ 5 5 0 ] //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end led g39 (.I(c2)); //: @(790,530) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g25 (a0) @(581,304) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(644, 304) /w:[ 2 -1 1 4 ] //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g5 /dolink:0 /link:"@T/edit1_tut.v" @(622,70) /sn:0 /anc:1 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: switch g36 (b1) @(581,462) /sn:0 /w:[ 0 ] /st:0 xor g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(740,310) /sn:0 /w:[ 0 3 0 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end xor g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(665,307) /sn:0 /w:[ 3 3 3 ] xor g35 (.I0(a1), .I1(b1), .Z(w10)); //: @(661,430) /sn:0 /w:[ 3 3 3 ] //: comment g0 /dolink:0 /link:"" @(8,10) /anc:1 //: /line:"¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ç¤Ï¡¢TkGate¤Î´ðËÜÊÔ½¸µ¡Ç½¤ò¾Ò²ð¤¹¤ë¡£" //: /line:"" //: /end //: switch g26 (b0) @(581,339) /sn:0 /w:[ 0 ] /st:0 //: comment g22 /dolink:0 /link:"" @(605,70) /sn:0 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end //: joint g30 (b0) @(638, 339) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(704, 312) /w:[ 2 1 -1 4 ] endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/edit2_tut.v000644 001751 001751 00000006645 10011742672 023604 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w3; //: /sn:0 {0}(756,264)(679,264){1} wire w1; //: /sn:0 {0}(756,259)(712,259)(712,224)(679,224){1} wire w2; //: /sn:0 {0}(679,302)(689,302){1} wire w5; //: /sn:0 {0}(777,262)(787,262){1} //: enddecls and g4 (.I0(w1), .I1(w3), .Z(w5)); //: @(767,262) /sn:0 /w:[ 0 0 0 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: switch g3 (w2) @(662,302) /sn:0 /w:[ 0 ] /st:0 //: switch g2 (w3) @(662,264) /sn:0 /w:[ 1 ] /st:0 //: switch g1 (w1) @(662,224) /sn:0 /w:[ 1 ] /st:0 //: frame g11 @(434,347) /sn:0 /anc:1 /wi:373 /ht:230 /tx:"¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë¥³¥Ô¡¼¤¹¤ë" //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: frame g10 @(22,347) /sn:0 /anc:1 /wi:394 /ht:227 /tx:"¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë°ÜÆ°¤¹¤ë" //: comment g6 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g9 /dolink:0 /link:"" @(607,452) /sn:0 //: /line:"" //: /end //: comment g7 /dolink:0 /link:"" @(634,193) /sn:0 //: /line:"" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g5 /dolink:0 /link:"" @(38,36) /anc:1 //: /line:"1) ¥Þ¥¦¥¹º¸¥Ü¥¿¥ó¤Ç±¦¤Ë¤¢¤ë²óÏ©¤Îº¸¾å¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¡¢È¢¤¬²óÏ©¤ò´°Á´¤Ë" //: /line:"´Þ¤à¤Þ¤Ç¥Þ¥¦¥¹¤ò±¦²¼¤Ø¥É¥é¥Ã¥°¤·¤Æ¡¢¥Ü¥¿¥ó¤òÎ¥¤·¤Æ²¼¤µ¤¤¡£" //: /line:"¥²¡¼¥È¤¬ÁªÂò¤µ¤ì¡¢ÂÀÀþ¤Çɽ¼¨¤µ¤ì¤Þ¤¹¡£ÁªÂò¤µ¤ì¤Æ¤¤¤ë¥²¡¼¥È¤Î½¸¹ç¤ò" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤È¤¤¤¤¤Þ¤¹¡£" //: /line:"" //: /line:"2) ¥²¡¼¥È¤Î¤É¤ì¤«¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¡Ö¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë°ÜÆ°¤¹¤ë¡×¤È½ñ¤¤¤Æ¤¢¤ë" //: /line:"ÅÀÀþ¤ÎÈ¢¤ÎÃæ¤Ë°ÜÆ°¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤ä¥ï¥¤¥ä¤Î¤Ê¤¤½ê¤ò¥¯¥ê¥Ã¥¯¤¹¤ë¤È" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤Ï²ò½ü¤µ¤ì¤Þ¤¹¡£" //: /line:"" //: /line:"3) AND¥²¡¼¥È¤òÁªÂò¤·¤Æ¡¢¥Þ¥¦¥¹±¦¥Ü¥¿¥ó¤ò²¡¤·¡¢¡ÖÆþÎϤòÄɲáפòÁªÂò¤·¤Æ" //: /line:"²¼¤µ¤¤¡£¤½¤ì¤«¤éAND¥²¡¼¥È¤ËÄɲ䵤줿¥ï¥¤¥ä¤ò²¼¤Î¥¹¥¤¥Ã¥Á¤ËÀܳ¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"4) ¥¹¥Æ¥Ã¥×1¤Ë½ñ¤¤¤Æ¤¢¤ëÍͤËÁ´¤Æ¤Î¥²¡¼¥È¤òÁªÂò¤·¤Æ¤ª¤¤¤Æ²¼¤µ¤¤¡£¤½¤ì¤«¤é" //: /line:"¡ÖÊÔ½¸¡×¥á¥Ë¥å¡¼¤Î¡Ö¥³¥Ô¡¼¡×¤òÁªÂò¤·¡¢¥Þ¥¦¥¹º¸¥Ü¥¿¥ó¤Ç¡Ö¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë" //: /line:"¥³¥Ô¡¼¤¹¤ë¡×¤È½ñ¤¤¤Æ¤¢¤ëÅÀÀþ¤ÎÈ¢¤Î¿¿Ãæ¤ò¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¡ÖÊÔ½¸¡×¥á¥Ë¥å¡¼¤Î" //: /line:"¡ÖÄ¥¤êÉÕ¤±¡×¤òÁªÂò¤·¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤Î¥»¥ì¥¯¥·¥ç¥ó¤¬¥³¥Ô¡¼¤µ¤ì¤Þ¤¹¡£¥»¥ì¥¯" //: /line:"¥·¥ç¥ó¤¬¤¢¤ë»þ¡¢¥Ç¥ê¡¼¥È¡¦¥­¡¼¤ò²¡¤¹¤È¡¢¥»¥ì¥¯¥·¥ç¥ó¤Î¥²¡¼¥È¤¬ºï½ü¤µ¤ì¤Þ¤¹¡£" //: /line:"" //: /line:"5) ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ò²¡¤·¤Ê¤¬¤é¡¢¥²¡¼¥È¤ò¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥²¡¼¥È¤ò°ì¤Ä¤º¤Ä" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤ËÄɲ乤뤳¤È¤¬½ÐÍè¤Þ¤¹¡£" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 /dolink:0 /link:"@T/edit2_tut.v" @(622,85) /sn:0 /anc:1 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g0 /dolink:0 /link:"" @(26,17) /anc:1 //: /line:"¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ï¥°¥ë¡¼¥×ÊÔ½¸¤Îµ¡Ç½¤ò¾Ò²ð¤¹¤ë¡£" //: /end //: comment g22 /dolink:0 /link:"" @(605,85) /sn:0 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/module_tut.v000644 001751 001751 00000015761 10104464547 024066 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "module_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module foo(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g61 @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: comment g3 @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: frame g1 @(409,199) /sn:0 /wi:404 /ht:316 /tx:"Create Module Ports Here" //: comment g16 @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: comment g20 @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g17 @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g14 @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g0 @(26,29) /anc:1 //: /line:"10) This is the definition for the \"foo\"" //: /line:"module. The \"ports\" list in the lower left" //: /line:"corner of the main window indicates the" //: /line:"the ports that we defined on the default" //: /line:"module instance. To create an internal" //: /line:"reference to a port, click the mouse to" //: /line:"set a mark and select \"Module Input\"," //: /line:"\"Module Output\" or \"Module InOut\" from the" //: /line:"\"Module\" submenu of the \"Make\" menu. A" //: /line:"dialog box will appear allowing you to set" //: /line:"the name of the port. Enter a name and press" //: /line:"return." //: /line:"" //: /line:"11) You can also create a new module" //: /line:"definition without creating an instance" //: /line:"by selecting \"New...\" from the \"Module\"" //: /line:"menu. This will bring up a dialog box" //: /line:"prompting for a module name. Try entering" //: /line:"\"bar\" and pressing return." //: /line:"" //: /line:"12) You can rename, copy and delete modules" //: /line:"using the other command in the \"Module\"" //: /line:"menu." //: /line:"" //: /line:"13) If you opened this block by double-clicking" //: /line:"on \"foo\" in the module list, you can return" //: /line:"to the main module by double-clicking on" //: /line:"\"main\". If you opened this block by using the" //: /line:"\"Open\" command from the \"Module\" menu, you" //: /line:"can return to the next level up by selecting" //: /line:"\"Close\" from the \"Module\" menu or by double-" //: /line:"clicking on main." //: /end //: comment g22 @(605,115) /sn:0 //: /line:"->" //: /end //: comment g18 @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule module main; //: root_module //: enddecls //: comment g61 @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: comment g8 @(500,0) /sn:0 /anc:1 //: /line:"¤³¤Î¥Ú¡¼¥¸¤ÎËÝÌõ¤Ï¾­Íè¤Î¥Ð¡¼¥¸¥ç¥ó¤Ë´°À®¤µ¤ì¤ë¡£" //: /end //: comment g3 @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: frame g2 @(477,189) /sn:0 /wi:330 /ht:350 /tx:"Use this space to create module instances" //: comment g1 @(11,34) /anc:1 //: /line:"1) Click the left mouse button in the center of the blank area to the right of" //: /line:"this text block to set a position. Now select \"Module Instance\" from the" //: /line:"\"Module\" submenu of the \"Make\" menu to create a module instance. A dialog box" //: /line:"will appear with the entry for \"Function\" active. Enter \"foo\" in lower case" //: /line:"and hit return to set the type of the instance to \"foo\"." //: /line:"" //: /line:"2) Press the left mouse button near the lower right corner of the module" //: /line:"instance and drag it down and to the right to increase the size of the box." //: /line:"" //: /end //: comment g16 @(622,115) /sn:0 /anc:1 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: comment g6 @(10,137) /anc:1 //: /line:"3) Right click on the block near the left edge and select \"Add" //: /line:"Input\" from the popup menu. A dialog box will appear with the" //: /line:"entry for \"Port Name\" active. Type an \"A\" and press return." //: /line:"Now repeat the process to add input \"B\" and \"C\" on the same side." //: /line:"Repeat the process again this time selecting \"Add Output\" and" //: /line:"creating outputs \"X\", \"Y\" and \"Z\" on the right side of the block." //: /line:"" //: /line:"4) Try clicking on one of the ports you added near the edge of" //: /line:"the module. You can drag them along the edge they are attached" //: /line:"to change their position." //: /line:"" //: /line:"5) Right click on the block near one of the ports and select" //: /line:"\"Change Type\" the popup menu. This will change the direction" //: /line:"of the selected port. You can repeat this action to cycle" //: /line:"through the three port types: input, output, and inout." //: /line:"" //: /line:"6) Select \"Cut Wire\" from the \"Tool\" menu and click on the \"Z\"" //: /line:"wire near the edge of the module instance. This will delete" //: /line:"the port." //: /line:"" //: /line:"7) Select \"Move/Connect\" from the \"Tool\" menu to return to the" //: /line:"default editing mode. Now select a new position with the mouse" //: /line:"and create a new module instance named \"foo\". Note that the" //: /line:"instance size and wire postions are not copied." //: /line:"" //: /line:"8) Now select the instance of \"foo\" to which you added input" //: /line:"and output ports and select \"Set Interface\" from the \"Module\"" //: /line:"menu. Create another instance of a \"foo\" module. Note that" //: /line:"the wire interface is now duplicated for each \"foo\" you create." //: /line:"" //: /line:"9) Now \"open\" the \"foo\" module. You can do this either by" //: /line:"selecting one of the \"foo\" module instances and then" //: /line:"selecting \"Open\" from the \"Module\" menu, or by double-clicking" //: /line:"on \"foo\" in the module list on the left side of the main window." //: /end //: comment g20 @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g17 @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g14 @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g22 @(605,115) /sn:0 //: /line:"->" //: /end //: comment g0 @(22,9) /anc:1 //: /line:"This tutorial describes the use of modules in TkGate." //: /end //: comment g18 @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/sim_tut.v000644 001751 001751 00000013774 10011742704 023362 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(750,326)(678,326){1} wire w4; //: /sn:0 {0}(652,260)(620,260){1} //: {2}(618,258)(618,240)(588,240){3} //: {4}(586,238)(586,227){5} //: {6}(584,240)(571,240){7} //: {8}(618,262)(618,323)(657,323){9} wire w3; //: /sn:0 {0}(687,225)(707,225){1} //: {2}(709,223)(709,214){3} //: {4}(709,227)(709,256){5} //: {6}(711,258)(749,258){7} //: {8}(709,260)(709,284){9} wire w0; //: /sn:0 {0}(750,321)(707,321)(707,305){1} wire w1; //: /sn:0 {0}(749,263)(706,263){1} //: {2}(702,263)(673,263){3} //: {4}(704,265)(704,284){5} wire C; //: /dp:1 {0}(798,312)(798,324)(771,324){1} wire w5; //: /sn:0 {0}(571,288)(585,288){1} //: {2}(589,288)(607,288){3} //: {4}(609,286)(609,265)(652,265){5} //: {6}(609,290)(609,328)(657,328){7} //: {8}(587,286)(587,276){9} wire S; //: {0}(770,261)(795,261)(795,251){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end xor g4 (.I0(w4), .I1(w5), .Z(w1)); //: @(663,263) /sn:0 /w:[ 0 5 3 ] nand g8 (.I0(w0), .I1(w6), .Z(C)); //: @(761,324) /sn:0 /w:[ 0 0 1 ] //: comment g13 /dolink:0 /link:"" @(25,45) /anc:1 //: /line:"1) Press the \"play\" button from the button bar above, or select" //: /line:"\"Begin Simulation\" from the \"Simulate\" menu. The simulation" //: /line:"scope window should appear." //: /line:"" //: /line:"2) Set a probe on the two on the two wires labeled \"S\" and \"C\"" //: /line:"and on the wire leading out of each of the switches by double-" //: /line:"clicking on them. A trace for each of the signals will appear" //: /line:"in the scope window." //: /line:"" //: /line:"3) Hit the space bar several times to advance the simulation" //: /line:"time. Each press of the space bar will advance the simulation" //: /line:"time by one epoch. An epoch is the smallest unit of time" //: /line:"understood by the simulator." //: /line:"" //: /line:"4) Select \"Options...\" from the \"File\" menu. Click on the" //: /line:"\"Simulator\" tab in the options box and enter \"5\" in the entry" //: /line:"for \"Epoch Step Size\" and hit \"OK\". Now try hitting the space" //: /line:"bar. Each press will advance the simulator by 5 epochs." //: /line:"" //: /line:"5) Click on one of the switches to change its value and hit the" //: /line:"space bar several times to advance the simulator. The results" //: /line:"of the simulation should appear in the scope window." //: /line:"" //: /line:"6) Press and hold the left mouse button on any of the internal" //: /line:"wires to view its value. The value is displayed in \"Verilog\"" //: /line:"format. The first number indicates the bit width, the letter" //: /line:"indicates the radix, and the last number the value. For" //: /line:"example, the \"1\" in \"1'b0\" indicates that this is a 1-bit value," //: /line:"the \"b\" indicates the value is given in binary, and the \"0\"" //: /line:"indicates the value of the signal." //: /line:"" //: /line:"7) Press \"play\" button from the button bar again, or select \"Run\"" //: /line:"from the \"Simulate\" menu. This will cause the simulator to enter" //: /line:"a continuous simulation mode. Try clicking on the switches in the" //: /line:"circuit. Each time you change a switch, the simulation will" //: /line:"continue until the outputs are stable. The \"Pause\" button will" //: /line:"return the simulator to single step mode." //: /line:"" //: /line:"8) To end the simulation, press the \"stop\" button on the button" //: /line:"bar, or select \"End Simulation\" from the \"Simulate\" menu." //: /end //: switch g3 (w3) @(670,225) /sn:0 /w:[ 0 ] /st:1 nand g2 (.I0(w4), .I1(w5), .Z(w6)); //: @(668,326) /sn:0 /w:[ 9 7 1 ] //: switch g1 (w5) @(554,288) /sn:0 /w:[ 0 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: joint g11 (w1) @(704, 263) /w:[ 1 -1 2 4 ] //: joint g10 (w3) @(709, 258) /w:[ 6 5 -1 8 ] led g28 (.I(w4)); //: @(586,220) /sn:0 /w:[ 5 ] /type:0 //: comment g19 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: joint g27 (w3) @(709, 225) /w:[ -1 2 1 4 ] //: joint g6 (w5) @(609, 288) /w:[ -1 4 3 6 ] xor g7 (.I0(w3), .I1(w1), .Z(S)); //: @(760,261) /sn:0 /w:[ 7 0 0 ] nand g9 (.I0(w1), .I1(w3), .Z(w0)); //: @(707,295) /sn:0 /R:3 /w:[ 5 9 1 ] //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: joint g31 (w4) @(586, 240) /w:[ 3 4 6 -1 ] //: comment g17 /dolink:0 /link:"@T/sim_tut.v" @(622,130) /sn:0 /anc:1 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end led g25 (.I(C)); //: @(798,305) /sn:0 /w:[ 0 ] /type:0 led g29 (.I(w5)); //: @(587,269) /sn:0 /w:[ 9 ] /type:0 //: comment g14 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: joint g5 (w4) @(618, 260) /w:[ 1 2 -1 8 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g24 /dolink:0 /link:"" @(500,0) /sn:0 /anc:1 //: /line:"¤³¤Î¥Ú¡¼¥¸¤ÎËÝÌõ¤Ï¾­Íè¤Î¥Ð¡¼¥¸¥ç¥ó¤Ë´°À®¤µ¤ì¤ë¡£" //: /line:"" //: /line:"" //: /line:"" //: /end //: comment g23 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end //: comment g22 /dolink:0 /link:"" @(605,130) /sn:0 //: /line:"->" //: /end //: switch g0 (w4) @(554,240) /sn:0 /w:[ 7 ] /st:1 led g26 (.I(w3)); //: @(709,207) /sn:0 /w:[ 3 ] /type:0 //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"This tutorial introduces the fundamentals of simulating combinational circuits." //: /line:"" //: /end led g18 (.I(S)); //: @(795,244) /sn:0 /w:[ 1 ] /type:0 //: joint g30 (w5) @(587, 288) /w:[ 2 8 1 -1 ] endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/welcome_tut.v000644 001751 001751 00000031364 10104464721 024223 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "welcome_tut.v" //: property useExtBars = 0 module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>B[7:0](67/89) Ti1>A[7:0](20/89) Li0>F[1:0](28/65) Bo0AIN[7:0](46/94) Li0>ck(56/80) Li1>SB[1:0](34/80) Li2>SA[1:0](14/80) Bo00 Ti1>0 Li0>1 Bo0<1 ] REGS regs (.AIN(w17), .ck(ck), .SB(w23), .SA(w21), .BOUT(w15), .AOUT(w6)); //: @(128, 449) /sz:(94, 80) /p:[ Ti0>0 Li0>1 Li1>0 Li2>1 Bo0<3 Bo1<3 ] //: dip func (w26) @(48,348) /R:1 /w:[ 0 ] /st:0 and g17 (.I0(w11), .I1(ci0), .Z(w9)); //: @(707,131) /sn:0 /R:3 /tech:unit /w:[ 5 5 1 ] led g62 (.I(w6)); //: @(222,237) /sn:0 /w:[ 5 ] /type:2 //: joint g29 (a) @(114, 66) /w:[ 2 -1 1 4 ] //: switch g25 (a) @(53,66) /sn:0 /w:[ 0 ] /st:0 led g52 (.I(s)); //: @(238,96) /sn:0 /R:2 /w:[ 1 ] /type:0 //: dip data_in (w25) @(69,225) /R:1 /w:[ 0 ] /st:11 and g14 (.I0(a0), .I1(b0), .Z(w10)); //: @(682,162) /sn:0 /w:[ 5 5 1 ] led g56 (.I(w13)); //: @(501,129) /sn:0 /w:[ 5 ] /type:0 pmos g5 (.Z(w5), .S0(w13), .G0(w1)); //: @(456,122) /sn:0 /w:[ 1 9 3 ] //: switch g36 (b0) @(588,118) /sn:0 /w:[ 0 ] /st:1 led g21 (.I(s0)); //: @(773,113) /sn:0 /R:2 /w:[ 1 ] /type:0 xor g24 (.I0(w8), .I1(ci), .Z(s)); //: @(210,72) /sn:0 /w:[ 0 3 0 ] xor g23 (.I0(a), .I1(b), .Z(w8)); //: @(135,69) /sn:0 /w:[ 3 3 3 ] //: joint g60 (w15) @(222, 327) /w:[ 2 4 1 -1 ] led g54 (.I(w1)); //: @(400,106) /sn:0 /w:[ 5 ] /type:0 xor g35 (.I0(a0), .I1(b0), .Z(w11)); //: @(670,86) /sn:0 /w:[ 3 3 3 ] xor g22 (.I0(w11), .I1(ci0), .Z(s0)); //: @(745,89) /sn:0 /w:[ 0 3 0 ] //: switch g26 (b) @(53,101) /sn:0 /w:[ 0 ] /st:1 //: comment g0 @(328,285) //: /line:"

TkGate ¤Ø¤è¤¦¤³¤½!

" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to " //: /line:"" //: /line:"°Ê²¼¤Î¥ê¥ó¥¯¤Ë¤¤¤º¤ì¤«¥¯¥ê¥Ã¥¯¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:" ¥Á¥å¡¼¥È¥ê¥¢¥ë¤ò¹Ô¤¦¡£" //: /line:"" //: /line:" ¿·¤·¤¤²óÏ©¿·¤òÊÔ½¸¤¹¤ë¡£" //: /line:"" //: /line:" ¤Ë¤¢¤ë¥É¥­¥å¥á¥ó¥È¤ò¸«¤ë¡£" //: /end //: switch data_select (w28) @(69,285) /w:[ 0 ] /st:0 //: switch g18 (a0) @(588,83) /sn:0 /w:[ 0 ] /st:0 //: switch g12 (w1) @(345,122) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (ci) @(174, 74) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(108, 101) /w:[ -1 2 1 4 ] endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/seqsim_tut.v000644 001751 001751 00000013433 10011742706 024065 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module supply0 w3; //: /sn:0 {0}(705,275)(705,265)(692,265){1} supply0 w0; //: /sn:0 /dp:1 {0}(707,320)(730,320)(730,335){1} wire [7:0] w7; //: /sn:0 {0}(652,225)(652,251){1} wire w4; //: /sn:0 /dp:1 {0}(707,310)(718,310)(718,298)(728,298){1} wire [7:0] w2; //: /sn:0 /dp:1 {0}(668,305)(668,280){1} wire ck; //: /dp:1 {0}(631,315)(566,315){1} wire [7:0] reg_out; //: {0}(668,326)(668,368)(724,368){1} //: {2}(728,368)(784,368)(784,241)(684,241)(684,251){3} //: {4}(726,370)(726,400){5} wire w9; //: /sn:0 {0}(644,265)(634,265){1} //: enddecls //: joint g8 (reg_out) @(726, 368) /w:[ 2 -1 1 4 ] //: supply0 g4 (w0) @(730,341) /sn:0 /w:[ 1 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: switch g3 (w4) @(746,298) /sn:0 /R:2 /w:[ 1 ] /st:1 //: comment g13 /dolink:0 /link:"" @(24,45) /anc:1 //: /line:"1) Press the \"play\" button from the button bar above, or select" //: /line:"\"Begin Simulation\" from the \"Simulate\" menu. The simulation" //: /line:"scope window should appear." //: /line:"" //: /line:"2) Set a probe on the two on the clock line labled \"ck\" and on" //: /line:"the register output labeled \"reg_out\" by double-clicking on them." //: /line:"A trace for each of the signals will appear in the scope window." //: /line:"" //: /line:"3) Hit the space bar several times to advance the simulation" //: /line:"time. Each press of the space bar will advance the simulation" //: /line:"time by a set number of epochs. An epoch is the smallest unit" //: /line:"of time understood by the simulator. See the combinational" //: /line:"simulation tutorial for details on setting the step size." //: /line:"" //: /line:"4) You can advance by a clock cycle by pressing the Tab key or" //: /line:"by selecting \"Step Cycle\" from the \"Simulate\" menu. The simulation" //: /line:"will advance to the next positive edge on any clock in the circuit," //: /line:"plus a number of \"overstep\" epochs. The overstep is give registers" //: /line:"enough time to latch in the new values before pausing the simulation." //: /line:"You can change the overstep amount, change the number of cycles to" //: /line:"advance, or select a single clock to step on through the simulation" //: /line:"options dialog box." //: /line:"" //: /line:"5) In this example, set switch on the CLR input to \"off\" and advance" //: /line:"the simulation by one cycle to clear the register. Then turn the" //: /line:"switch to \"on\" and step the clock a few cycles to advance the counter." //: /line:"" //: /line:"6) Click on the dip switch to open a window allowing you to change" //: /line:"the dip switch value. Enter a number in hex and press \"Apply\" to" //: /line:"change the size of the step interval." //: /line:"" //: /line:"7) Just as in the combinational logic example, you can click and hold" //: /line:"the mouse button on a wire to see the value on that wire." //: /line:"" //: /line:"8) Press \"play\" button from the button bar again, or select \"Run\"" //: /line:"from the \"Simulate\" menu. This will cause the simulator to enter" //: /line:"a continuous simulation mode. In sequential circuits, the simulator" //: /line:"will run continuously until you press the \"Pause\" button. You can" //: /line:"still change the values of switches and such while the simulation" //: /line:"is running." //: /line:"" //: /end register g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(668,315) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g11 /dolink:0 /link:"" @(500,0) /sn:0 /anc:1 //: /line:"¤³¤Î¥Ú¡¼¥¸¤ÎËÝÌõ¤Ï¾­Íè¤Î¥Ð¡¼¥¸¥ç¥ó¤Ë´°À®¤µ¤ì¤ë¡£" //: /line:"" //: /line:"" //: /line:"" //: /end //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: comment g10 /dolink:0 /link:"" @(528,451) /sn:0 /R:2 /anc:1 //: /line:"9) You can slide the scope trace either" //: /line:"by using the scroll bar, or by clicking" //: /line:"in the trace window and dragging the" //: /line:"trace left and right. Click while holding" //: /line:"the control or shift keys to zoom in or" //: /line:"out. Dragging the scroll bar all the way" //: /line:"to the right will cause current values to" //: /line:"be continuously updated again." //: /line:"" //: /end //: dip g6 (w7) @(652,215) /sn:0 /w:[ 0 ] /st:1 //: supply0 g9 (w3) @(705,281) /sn:0 /w:[ 0 ] led g7 (.I(reg_out)); //: @(726,407) /sn:0 /R:2 /w:[ 5 ] /type:2 //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end add g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(668,267) /sn:0 /w:[ 1 3 1 1 0 ] //: comment g14 /dolink:0 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 /anc:1 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end clock g0 (.Z(ck)); //: @(553,315) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g22 /dolink:0 /link:"" @(605,145) /sn:0 //: /line:"->" //: /end //: comment g12 /dolink:0 /link:"" @(16,18) /anc:1 //: /line:"This tutorial introduces the fundamentals of simulating sequential circuits." //: /line:"" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/edwire_tut.v000644 001751 001751 00000022455 10104470714 024047 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "edwire_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 /dp:1 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 /dp:1 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g61 @(622,100) /sn:0 /anc:1 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end xor g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: comment g55 @(456,4) /sn:0 //: /line:"¤³¤Î¥Ú¡¼¥¸¤ÎËÝÌõ¤Ï¾­Íè¤Î¥Ð¡¼¥¸¥ç¥ó¤Ë´°À®¤µ¤ì¤ë¡£" //: /end //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] or g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] and g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g16 @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end and g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] buf g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] and g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] and g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] buf g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] and g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g6 @(22,11) /sn:0 /anc:1 //: /line:"This tutorial introduces special wire editing features." //: /end //: comment g9 @(26,30) /anc:1 //: /line:"1) TkGate has a \"gravity\" feature that causes short" //: /line:"segements to be automatically deleted. Click on the" //: /line:"wire at the point indicated by the arrow in the circuit" //: /line:"in Fig. 1 and move it until it is nearly alligned with" //: /line:"the other vertical segment. When you release the" //: /line:"mouse button, the segments will \"snap\" together." //: /line:"" //: /line:"2) TkGate will automatically delete segments of wires" //: /line:"which form loops. To demonstrate this, select the end" //: /line:"of the output wire of the XOR gate in Fig. 2 with the" //: /line:"left mouse button. Drag the end up just above the" //: /line:"segment direcly connected to the XOR output and release" //: /line:"the mouse button. You can disable the automatic cleanup" //: /line:"feature by holding the Alt key while moveing wires." //: /line:"" //: /line:"3) TkGate also deletes uneeded joints automatically" //: /line:"Select the wire cutters tool and cut the wire at" //: /line:"the point indicated by the arrow in Fig. 3a. Notice" //: /line:"that the joint is automatically removed. Now cut at" //: /line:"the point indicated by the arrow in Fig. 3b The free" //: /line:"end is automatically deleted." //: /line:"" //: /line:"4) Switch back to Move/Connect mode and select the input" //: /line:"of the lowest buffer in Fig. 4a so that the solder cursor" //: /line:"appears. Move the endpoint near the joint and release it." //: /line:"The wire will be attached to the joint. Now repeat this" //: /line:"action in Fig. 4b, this time releasing it between the AND" //: /line:"gate output and the joint. This time a new joint will be" //: /line:"created." //: /line:"" //: /line:"5) Add a new segment to connect the output of the AND" //: /line:"gate in Fig. 5 to the input of the two buffers by right" //: /line:"clicking on the wire segment at the point indicated by" //: /line:"the arrow. Then select \"Add Wire Segment\" from the" //: /line:"popup menu. You can now solder the end of the created" //: /line:"segment somewhere on the wire connecting the buffer inputs." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point" //: /line:"indicated by the arrows and drag it to the left past" //: /line:"the output point of the AND gate and past the position" //: /line:"of the joint. In the AND gate example, segments will" //: /line:"be added to ensure the wire exits the AND gate to the" //: /line:"right. In the joint example, the position of the wire" //: /line:"arround the joint will be adjusted." //: /end //: comment g20 @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] and g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] buf g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" //: comment g17 @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end buf g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] and g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" //: comment g14 @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end and g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] and g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] buf g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] //: comment g21 @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end buf g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" buf g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: comment g22 @(605,100) /sn:0 //: /line:"->" //: /end //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" buf g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" buf g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] and g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] //: comment g18 @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end and g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end buf g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/create_tut.v.orig000644 001751 001751 00000007321 07311226664 024776 0ustar00hansenhansen000000 000000 //: version "1.6f" //: property discardChanges = 1 module main; //: root_module wire w6; //: /sn:0 {0}(232,502)(177,502){1} //: {2}(175,500)(175,466)(187,466){3} //: {4}(173,502)(141,502){5} wire w7; //: /sn:0 {0}(253,500)(263,500){1} wire w2; //: /sn:0 {0}(187,461)(141,461){1} wire w5; //: /sn:0 {0}(232,497)(218,497)(218,464)(208,464){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: comment g8 /dolink:0 /link:"" @(248,476) /anc:1 //: /line:"OR¥²¡¼¥È" //: /end or g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(243,500) /sn:0 /anc:1 /w:[ 0 0 0 ] and g3 (.I0(w2), .I1(w6), .Z(w5)); //: @(198,464) /sn:0 /anc:1 /w:[ 0 3 1 ] //: frame g13 @(412,372) /sn:0 /wi:381 /ht:177 /tx:"²óÏ©¤ò¤³¤ÎÃæ¤ËºîÀ®¤·¤Æ¤¯¤À¤µ¤¤" //: switch g2 (w6) @(124,502) /sn:0 /anc:1 /w:[ 5 ] /st:0 //: switch g1 (w2) @(124,461) /sn:0 /anc:1 /w:[ 1 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: comment g10 /dolink:0 /link:"" @(11,205) /anc:1 //: /line:"5) AND¥²¡¼¥È¤ÈOR¥²¡¼¥È¤ÈƱ¤¸ÍͤËÆó¤Ä¤Î¥¹¥¤¥Ã¥Á¤òºîÀ®¤·¤Æ²¼¤µ¤¤¡£¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤Î¡Î¥¹¥¤¥Ã¥Á¡Ï" //: /line:"¥µ¥Ö¥á¥Ë¥å¡¼¤Î¡Î¥¹¥¤¥Ã¥Á¡Ï¤òÁª¤ó¤Ç¡¢Ëô¤Ï¡¢¥­¡¼¥Ü¡¼¥É¡¦¥·¥ç¡¼¥È¥«¥Ã¥È¤Î\"s\"¤ò²¡¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"6) ¥¹¥Æ¥Ã¥×4¤ò·«¤êÊÖ¤·¤Æ¡¢¾å¤Î¥¹¥¤¥Ã¥Á¤Î½ÐÎϤòAND¥²¡¼¥È¤Î¾å¤Î½ÐÎϤËÀܳ¤·¤Æ¤¯¤À¤µ¤¤" //: /line:"" //: /line:"7) ¥¹¥Æ¥Ã¥×4¤ò·«¤êÊÖ¤·¤Æ¡¢²¼¤Î¥¹¥¤¥Ã¥Á¤Î½ÐÎϤòOR¥²¡¼¥È¤Î²¼¤Î½ÐÎϤËÀܳ¤·¤Æ¤¯¤À¤µ¤¤" //: /line:"" //: /line:"8) AND¥²¡¼¥È¤Î²¼¤ÎÆþÎϤ˥¯¥ê¥Ã¥¯¤·¤Æ¡¢¤Ï¤ó¤À¤´¤Æ¤ò½Ð¤·¤Æ¡¢²¼¤Î¥¹¥¤¥Ã¥Á¤ÈOR¥²¡¼¥È¤Î´Ö¤Î" //: /line:"¥ï¥¤¥ä¤Î¿¿Ãæ¤Ë¥É¥é¥Ã¥°¤·¤Æ¡¢¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤òÏ䷤Ƥ¯¤À¤µ¤¤¡£ÀܳÅÀ¤¬ºîÀ®¤µ¤ì¤ë¡£" //: /end //: comment g6 /dolink:0 /link:"" @(101,427) /anc:1 //: /line:"¥¹¥¤¥Ã¥Á" //: /end //: comment g9 /dolink:0 /link:"" @(12,9) /anc:1 //: /line:"1) ¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ç¤Ï¡¢°Ê²¼¤Ë¼¨¤·¤Æ¤¢¤ë¤Î¤ÈƱ¤¸ÍͤʲóÏ©¤òºîÀ®¤¹¤ë¡£±¦²¼¤Î" //: /line:"ÅÀ¤ÎÈ¢¤ÎÃæ¤ËºîÀ®¤·¤Æ²¼¤µ¤¤¡£¤Þ¤º¡¢±¦¤Î¥Þ¥¦¥¹¥Ü¥¿¥ó¤ÇAND¥²¡¼¥È¤Î²Õ½ê¤òÁª¤ó¤Ç" //: /line:"²¼¤µ¤¤¡£¥¯¥ê¥Ã¥¯¤·¤¿²Õ½ê¤ËX°õ¤È¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤¬¸½¤ì¤ë¡£" //: /line:"" //: /line:"2) ¤½¤ì¤«¤é¡¢¡ÎºîÀ®¡Ï¥á¥Ë¥å¡¼¤Î¡Î¥²¡¼¥È¡Ï¥µ¥Ö¥á¥Ë¥å¡¼¤Î¡ÎAND¡Ï¤òÁª¤ó¤Ç²¼¤µ¤¤¡£" //: /line:"¥á¥Ë¥å¡¼¡¦¥Ð¡¼¡¢Ëô¤Ï¥­¡¼¥Ü¡¼¥É¡¦¥·¥ç¡¼¥È¥«¥Ã¥È¤Î\"a\"¤Ç¤â»È¤¨¤ë¡£" //: /line:"" //: /line:"3) ¥¹¥Æ¥Ã¥×1¡¢2¤ò·«¤êÊÖ¤·¤Æ, OR¥²¡¼¥È¤òAND¥²¡¼¥È¤Î±¦²¼¤Î²Õ½ê¤ËºîÀ®¤·¤Æ²¼¤µ¤¤¡£" //: /line:"¥á¥Ë¥å¡¼¡¢Ëô¤Ï¥­¡¼¥Ü¡¼¥É¥·¥ç¡¼¥È¡¦¥«¥Ã¥È¤Î\"o\"¤Ç¤â»È¤¨¤ë¡£" //: /line:"" //: /line:"4) AND¥²¡¼¥È¤Î½ÐÎϤΥ磻¥ä¤ÎÀèü¤Ëº¸¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤Ç¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¥Ü¥¿¥ó¤ò" //: /line:"²¡¤·¤¿¤Þ¤Þ¤Ë¤¹¤ë¡£¥Þ¥¦¥¹¡¦¥«¡¼¥½¥ë¤Ï¤Ï¤ó¤À¤´¤Æ¤ËÊѤï¤ë¡£¥ï¥¤¥ä¤òOR¥²¡¼¥È¤Î" //: /line:"¾å¤ÎÆþÎϤޤǥɥé¥Ã¥°¤·¤Æ¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤òÏ乤ȡ¢¥ï¥¤¥ä¤¬Àܳ¤µ¤ì¤ë¡£" //: /end //: comment g7 /dolink:0 /link:"" @(192,436) /anc:1 //: /line:"AND¥²¡¼¥È" //: /end //: comment g20 /dolink:0 /link:"@T/create_tut.v" @(622,55) /sn:0 /anc:1 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: joint g5 (w6) @(175, 502) /anc:1 /w:[ 1 2 4 -1 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g22 /dolink:0 /link:"" @(605,55) /sn:0 //: /line:"->" //: /end //: comment g0 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/edit1_tut.v.orig000644 001751 001751 00000014113 07311226664 024536 0ustar00hansenhansen000000 000000 //: version "1.6f" //: property discardChanges = 1 module main; //: root_module wire w7; //: /sn:0 {0}(682,363)(697,363)(697,375){1} wire s0; //: {0}(750,310)(780,310){1} wire w4; //: /sn:0 {0}(702,345)(702,375){1} wire c0; //: {0}(598,268)(704,268)(704,310){1} //: {2}(706,312)(729,312){3} //: {4}(704,314)(704,324){5} wire c1; //: {0}(700,396)(700,433){1} //: {2}(702,435)(725,435){3} //: {4}(700,437)(700,447){5} wire s1; //: /dp:1 {0}(746,433)(781,433){1} wire a1; //: {0}(598,427)(638,427){1} //: {2}(642,427)(650,427){3} //: {4}(640,429)(640,483)(657,483){5} wire b1; //: {0}(598,462)(632,462){1} //: {2}(634,460)(634,432)(650,432){3} //: {4}(634,464)(634,488)(657,488){5} wire w8; //: /sn:0 {0}(678,486)(693,486)(693,498){1} wire a0; //: /dp:1 {0}(598,304)(642,304){1} //: {2}(646,304)(654,304){3} //: {4}(644,306)(644,360)(661,360){5} wire b0; //: /dp:1 {0}(598,339)(636,339){1} //: {2}(638,337)(638,309)(654,309){3} //: {4}(638,341)(638,365)(661,365){5} wire c2; //: {0}(783,530)(696,530)(696,519){1} wire w10; //: /sn:0 {0}(725,430)(697,430){1} //: {2}(693,430)(671,430){3} //: {4}(695,432)(695,447){5} wire w5; //: /sn:0 {0}(698,468)(698,498){1} wire w9; //: /sn:0 {0}(729,307)(701,307){1} //: {2}(697,307)(675,307){3} //: {4}(699,309)(699,324){5} //: enddecls //: joint g8 (c1) @(700, 435) /w:[ 2 1 -1 4 ] nand g4 (.I0(w8), .I1(w5), .Z(c2)); //: @(696,509) /sn:0 /R:3 /w:[ 1 1 1 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end led g37 (.I(s0)); //: @(787,310) /sn:0 /R:3 /w:[ 1 ] /type:0 xor g34 (.I0(w10), .I1(c1), .Z(s1)); //: @(736,433) /sn:0 /w:[ 0 3 0 ] //: comment g3 /dolink:0 /link:"" @(29,249) /anc:1 //: /line:"5) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥Ó¥Ã¥ÈÉý¡×¤òÁªÂò¤·¤Æ¡¢¥ê¥Ü¥ó¥±¡¼¥Ö¥ë¤Î¥Ä¡¼¥ë¤ò" //: /line:"½Ð¤·¤Æ²¼¤µ¤¤¡£¤½¤¦¤¹¤ë¤È¡¢¥¦¥£¥ó¥É¤Î±¦²¼¤Ë¡Ö¥Ó¥Ã¥ÈÉý¡×¤ÎÆþÎϥܥ寥¹¤âɽ¤¹¡£" //: /line:"¥Ü¥Ã¥¯¥¹¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢1¡Á32¤Î¿ô»ú¤òÆþÎϤ·¤Æ²¼¤µ¤¤¡£¤½¤ì¤«¤é¥ï¥¤¥ä¤Ë" //: /line:"¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¼¨¤·¤Æ¤¤¤ë¥Ó¥Ã¥ÈÉý¤ËÀßÄꤷ¤Æ¤ß¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"6) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö°ÜÆ°¡¿Àܳ¡×¤òÁªÂò¤·¤ª¤¤¤Æ¡¢¥ï¥¤¥ä¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯" //: /line:"¤¹¤ë¤È¡¢ÆÃħ¥Ü¥Ã¥¯¥¹¤¬³«¤¯¡£¥Í¥Ã¥È̾¡¢¥Í¥Ã¥È̾¤¬É½¼¨¤¹¤ë¤«¤É¤¦¤«¡¢¥Ó¥Ã¥ÈÉý¤Ê¤É¤Î" //: /line:"ÆÃħ¤¬ÀßÄê¤Ç¤­¤ë¡£±¦¤Î¥Þ¥¦¥¹¥Ü¥¿¥ó¤Ç¤âÍøÍѤ·¤Æ³«¤±¤ë" //: /line:"" //: /line:"7) OR¥²¡¼¥È¤Ê¤É¤Ë¥À¥Ö¥ë¡¦¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥²¡¼¥È¤ÎÆÃħ¥Ü¥Ã¥¯¥¹¤¬³«¤¯¡£" //: /line:"¥²¡¼¥È̾¡¢¥²¡¼¥È̾¤¬É½¼¨¤¹¤ë¤«¤É¤¦¤«¡¢¥²¡¼¥È¤¬°ÜÆ°½ÐÍè¤ë¤«¤É¤¦¤«¤Ê¤É¤Î" //: /line:"ÆÃħ¤¬ÀßÄê½ÐÍè¤ë¡£¥Ý¡¼¥È¤ÎÄɲᢺï½ü¡¢ÊÔ½¸¤Ê¤É¤â½ÐÍè¤ë¡£" //: /line:"" //: /line:"8) ¥²¡¼¥È¤Ë±¦¥Þ¥¦¥¹¥Ü¥¿¥ó¤Ç¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¡Ö°ÜÆ°ÉԲġפΥե饰¤ò¥»¥Ã¥È¤·¤Æ" //: /line:"¤ß¤Æ²¼¤µ¤¤¡£¤³¤Î¥Õ¥é¥°¤¬¥»¥Ã¥È¤·¤Æ¤¢¤ì¤Ð¡¢¥²¡¼¥È¤Î°ÜÆ°¤Ï½ÐÍè¤Ê¤¤¡£" //: /end //: comment g2 /dolink:0 /link:"" @(29,38) /anc:1 //: /line:"1) º¸¤Î¥Þ¥¦¥¹¥Ü¥¿¥ó¤Ç¥²¡¼¥È¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢Ê̤βսê¤Ë°ÜÆ°¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£" //: /line:"¥²¡¼¥È¤Ë·Ò¤¤¤Ç¤¤¤ë¥ï¥¤¥ä¤â¤Ä¤¤¤Æ°ÜÆ°¤µ¤ì¤ë¡£" //: /line:"" //: /line:"2) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥ï¥¤¥ä¤ÎÀÚÃǡפòÁªÂò¤·¤Æ¡¢¥«¥Ã¥¿¡¼¤Î¥Ä¡¼¥ë¤ò" //: /line:"½Ð¤·¡¢¥ï¥¤¥ä¤Î¤É¤³¤«¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£²¿¤Ë¤â·Ò¤¤¤Ç¤¤¤Ê¤¤¥ï¥¤¥ä¤Î" //: /line:"Éôʬ¤Ï¼«Æ°Åª¤Ëºï½ü¤µ¤ì¤ë¡£±¦¥Þ¥¦¥¹¥Ü¥¿¥ó¤Ç³«¤¯¥á¥Ë¥å¡¼¤âÍøÍѤ·¤Æ" //: /line:"¥«¥Ã¥¿¡¼¤ò½Ð¤»¤ë¡£" //: /line:"" //: /line:"3) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡ÖÈÝÄê¡×¤òÁªÂò¤·¤Æ¡¢ÈÝÄê¥Ä¡¼¥ë¤ò½Ð¤·¡¢¥²¡¼¥È¤Î" //: /line:"ÆþÎϤä½ÐÎϤ˥¯¥ê¥Ã¥¯¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£ÈÝÄê¤Î´Ý¤¬É½¤·¤¿¤ê¡¢¾Ã¤¨¤¿¤ê¤¹¤ë¡£" //: /line:"" //: /line:"4) ¡Ö¥Ä¡¼¥ë¡×¥á¥Ë¥å¡¼¤Î¡Ö¥²¡¼¥È¤Îºï½ü¡×¤òÁªÂò¤·¤Æ¡¢¥²¡¼¥È¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ" //: /line:"¤ß¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤¬ºï½ü¤µ¤ì¤ë¡£¥²¡¼¥È¤òÁªÂò¤·¤Æ¡¢¥Ç¥ê¡¼¥È¡¦¥­¡¼¤ò²¡¤·¤¿¤ê¡¢" //: /line:"±¦¥Þ¥¦¥¹¥Ü¥¿¥ó¤Ç¡Öºï½ü¡×¤òÁªÂò¤·¤¿¤ê¤¹¤ë¤³¤È¤Ç¤â¥²¡¼¥È¤¬ºï½ü¤Ç¤­¤ë¡£" //: /end nand g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(700,386) /sn:0 /R:3 /w:[ 1 1 0 ] //: switch g11 (a1) @(581,427) /sn:0 /w:[ 0 ] /st:0 //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: joint g10 (a1) @(640, 427) /w:[ 2 -1 1 4 ] nand g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(672,363) /sn:0 /w:[ 5 5 0 ] led g19 (.I(s1)); //: @(788,433) /sn:0 /R:3 /w:[ 1 ] /type:0 //: switch g27 (c0) @(581,268) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(699, 307) /w:[ 1 -1 2 4 ] //: joint g38 (b1) @(634, 462) /w:[ -1 2 1 4 ] nand g6 (.I0(a1), .I1(b1), .Z(w8)); //: @(668,486) /sn:0 /w:[ 5 5 0 ] nand g9 (.I0(w10), .I1(c1), .Z(w5)); //: @(698,458) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g7 (w10) @(695, 430) /w:[ 1 -1 2 4 ] nand g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(702,335) /sn:0 /R:3 /w:[ 5 5 0 ] //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end led g39 (.I(c2)); //: @(790,530) /sn:0 /R:3 /w:[ 0 ] /type:0 //: switch g25 (a0) @(581,304) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(644, 304) /w:[ 2 -1 1 4 ] //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g5 /dolink:0 /link:"@T/edit1_tut.v" @(622,70) /sn:0 /anc:1 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: switch g36 (b1) @(581,462) /sn:0 /w:[ 0 ] /st:0 xor g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(740,310) /sn:0 /w:[ 0 3 0 ] //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end xor g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(665,307) /sn:0 /w:[ 3 3 3 ] xor g35 (.I0(a1), .I1(b1), .Z(w10)); //: @(661,430) /sn:0 /w:[ 3 3 3 ] //: comment g0 /dolink:0 /link:"" @(8,10) /anc:1 //: /line:"¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ç¤Ï¡¢TkGate¤Î´ðËÜÊÔ½¸µ¡Ç½¤ò¾Ò²ð¤¹¤ë¡£" //: /line:"" //: /end //: switch g26 (b0) @(581,339) /sn:0 /w:[ 0 ] /st:0 //: comment g22 /dolink:0 /link:"" @(605,70) /sn:0 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end //: joint g30 (b0) @(638, 339) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(704, 312) /w:[ 2 1 -1 4 ] endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/edit2_tut.v.orig000644 001751 001751 00000006543 07311226664 024547 0ustar00hansenhansen000000 000000 //: version "1.6f" //: property discardChanges = 1 module main; //: root_module wire w3; //: /sn:0 {0}(756,264)(679,264){1} wire w1; //: /sn:0 {0}(756,259)(712,259)(712,224)(679,224){1} wire w2; //: /sn:0 {0}(679,302)(689,302){1} wire w5; //: /sn:0 {0}(777,262)(787,262){1} //: enddecls and g4 (.I0(w1), .I1(w3), .Z(w5)); //: @(767,262) /sn:0 /w:[ 0 0 0 ] //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end //: switch g3 (w2) @(662,302) /sn:0 /w:[ 0 ] /st:0 //: switch g2 (w3) @(662,264) /sn:0 /w:[ 1 ] /st:0 //: switch g1 (w1) @(662,224) /sn:0 /w:[ 1 ] /st:0 //: frame g11 @(434,347) /sn:0 /anc:1 /wi:373 /ht:230 /tx:"¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë¥³¥Ô¡¼¤¹¤ë" //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: frame g10 @(22,347) /sn:0 /anc:1 /wi:394 /ht:227 /tx:"¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë°ÜÆ°¤¹¤ë" //: comment g6 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g9 /dolink:0 /link:"" @(607,452) /sn:0 //: /line:"" //: /end //: comment g7 /dolink:0 /link:"" @(634,193) /sn:0 //: /line:"" //: /end //: frame g15 @(600,25) /sn:0 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 //: /line:"²óÏ©¤ÎºîÀ®" //: /end //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g5 /dolink:0 /link:"" @(38,36) /anc:1 //: /line:"1) º¸¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤ò±¦¤Ë¤¢¤ë²óÏ©¤Îº¸¾å¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢È¢¤¬²óÏ©¤ò" //: /line:"´°Á´¤Ë´Þ¤à¤Þ¤Ç¡¢¥Þ¥¦¥¹¤ò±¦²¼¤Ø¥É¥é¥Ã¥°¤·¤Æ¡¢¥Ü¥¿¥ó¤òÊü¤·¤Æ²¼¤µ¤¤¡£" //: /line:"¥²¡¼¥È¤¬ÁªÂò¤µ¤ì¡¢ÂÀÀþ¤Çɽ¼¨¤µ¤ì¤ë¡£ÁªÂò¤µ¤ì¤Æ¤¤¤ë¥²¡¼¥È¤Î½¸¹ç¤Ï" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤È¤¤¤¦¡£" //: /line:"" //: /line:"2) ¥²¡¼¥È¤Î¤É¤ì¤«¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡Ö¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë°ÜÆ°¤¹¤ë¡×¤È½ñ¤¤¤Æ¤¢¤ë" //: /line:"ÅÀÀþ¤ÎÈ¢¤ÎÃæ¤Ë°ÜÆ°¤·¤Æ¤ß¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤ä¥ï¥¤¥ä¤Î¤Ê¤¤½ê¤Ë¥¯¥ê¥Ã¥¯¤¹¤ë¤È" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤¬¤Ê¤¯¤Ê¤ë¡£" //: /line:"" //: /line:"3) AND¥²¡¼¥È¤òÁªÂò¤·¤Æ¡¢±¦¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤ò²¡¤·¤Æ¡¢¡ÖÆþÎϤòÄɲáפòÁªÂò¤·¤Æ" //: /line:"²¼¤µ¤¤¡£¤½¤ì¤«¤éAND¥²¡¼¥È¤ËÄɲ䵤줿¥ï¥¤¥ä¤ò²¼¤Î¥¹¥¤¥Ã¥Á¤òÀܳ¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:"4) ¥¹¥Æ¥Ã¥×1¤Ë½ñ¤¤¤Æ¤¢¤ëÍͤËÁ´¤Æ¤Î¥²¡¼¥È¤òÁªÂò¤·¤Æ¤ª¤¤¤Æ²¼¤µ¤¤¡£¤½¤ì¤«¤é" //: /line:"¡ÖÊÔ½¸¡×¥á¥Ë¥å¡¼¤Î¡Ö¥³¥Ô¡¼¡×¤òÁªÂò¤·¤Æ¡¢º¸¥Þ¥¦¥¹¡¦¥Ü¥¿¥ó¤ò¡Ö¥²¡¼¥È¤ò¤³¤ÎÃæ¤Ë" //: /line:"¥³¥Ô¡¼¤¹¤ë¡×¤È½ñ¤¤¤Æ¤¢¤ëÅÀÀþ¤ÎÈ¢¤Î¿¿Ãæ¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢¡ÖÊÔ½¸¡×¥á¥Ë¥å¡¼¤Î" //: /line:"¡ÖÄ¥¤êÉÕ¤±¡×¤òÁªÂò¤·¤Æ²¼¤µ¤¤¡£¥²¡¼¥È¤Î¥»¥ì¥¯¥·¥ç¥ó¤¬¥³¥Ô¡¼¤µ¤ì¤ë¡£¥»¥ì¥¯¥·¥ç¥ó¤¬" //: /line:"¤¢¤ë»þ¡¢¥Ç¥ê¡¼¥È¡¦¥­¡¼¤ò²¡¤¹¤È¡¢¥»¥ì¥¯¥·¥ç¥ó¤Î¥²¡¼¥È¤¬ºï½ü¤µ¤ì¤ë¡£" //: /line:"" //: /line:"5) ¥³¥ó¥È¥í¡¼¥ë¡¦¥­¡¼¤ò²¡¤·¤Ê¤¬¤é¡¢¥²¡¼¥È¤Ë¥¯¥ê¥Ã¥¯¤¹¤ë¤È¡¢¥²¡¼¥È¤ò°ì¤Ä¤º¤Ä" //: /line:"¥»¥ì¥¯¥·¥ç¥ó¤ËÄɲ乤뤳¤È¤¬½ÐÍè¤ë¡£" //: /end //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: comment g21 /dolink:0 /link:"@T/edit2_tut.v" @(622,85) /sn:0 /anc:1 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end //: comment g0 /dolink:0 /link:"" @(26,17) /anc:1 //: /line:"¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ï¥°¥ë¡¼¥×ÊÔ½¸¤Îµ¡Ç½¤ò¾Ò²ð¤¹¤ë¡£" //: /end //: comment g22 /dolink:0 /link:"" @(605,85) /sn:0 //: /line:"->" //: /end //: comment g18 /dolink:1 /link:"@T/welcome_tut.v" @(622,40) /sn:0 //: /line:"TkGate¤Î¾Ò²ð" //: /end endmodule tkgate-2.0-b10/locale/ja/obsolete-tutorials/welcome_tut.v.orig000644 001751 001751 00000035213 07311226664 025167 0ustar00hansenhansen000000 000000 //: version "1.6" //: property discardChanges = 1 module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](20/89) Ti1>B[7:0](67/89) Li0>F[1:0](28/65) Bo0AIN[7:0](46/94) Li0>SA[1:0](14/80) Li1>SB[1:0](34/80) Li2>ck(56/80) Bi0>BOUT[7:0](79/94) Bi1>AOUT[7:0](16/94) ] supply1 w0; //: /sn:0 /dp:1 {0}(361,358)(373,358)(373,339){1} supply1 w21; //: /sn:0 /dp:1 {0}(260,211)(181,211)(181,173){1} input [1:0] SB; //: /sn:0 {0}(507,507)(570,507){1} supply1 w1; //: /sn:0 /dp:1 {0}(506,358)(519,358)(519,339){1} output [7:0] BOUT; //: /sn:0 {0}(593,549)(593,520){1} input [1:0] SA; //: /sn:0 {0}(382,507)(92,507)(92,138){1} //: {2}(94,136)(284,136)(284,198){3} //: {4}(90,136)(47,136){5} supply1 w2; //: /sn:0 /dp:1 {0}(219,357)(231,357)(231,340){1} input [7:0] AIN; //: /sn:0 {0}(467,144)(467,285){1} //: {2}(469,287)(626,287)(626,353){3} //: {4}(465,287)(324,287){5} //: {6}(320,287)(180,287)(180,352){7} //: {8}(322,289)(322,353){9} //: {10}(467,289)(467,353){11} input ck; //: /sn:0 {0}(51,392)(124,392){1} //: {2}(128,392)(273,392){3} //: {4}(277,392)(412,392){5} //: {6}(416,392)(574,392)(574,363)(589,363){7} //: {8}(414,390)(414,363)(430,363){9} //: {10}(275,390)(275,363)(285,363){11} //: {12}(126,390)(126,362)(143,362){13} output [7:0] AOUT; //: /sn:0 /dp:1 {0}(405,520)(405,549){1} supply1 w5; //: /sn:0 /dp:1 {0}(665,358)(680,358)(680,340){1} wire w4; //: /sn:0 {0}(290,227)(290,266)(555,266)(555,368)(506,368){1} wire [7:0] R2; //: /dp:4 {0}(411,491)(411,432)(465,432){1} //: {2}(469,432)(599,432)(599,491){3} //: {4}(467,430)(467,374){5} wire w3; //: /sn:0 {0}(278,227)(278,281)(404,281)(404,368)(361,368){1} wire w20; //: /sn:0 {0}(302,227)(302,248)(712,248)(712,368)(665,368){1} wire [7:0] R3; //: /dp:3 {0}(423,491)(423,447)(609,447){1} //: {2}(613,447)(626,447)(626,374){3} //: {4}(611,449)(611,491){5} wire [7:0] R1; //: /dp:5 {0}(399,491)(399,422){1} //: {2}(401,420)(587,420)(587,491){3} //: {4}(397,420)(322,420)(322,374){5} wire w8; //: /sn:0 /dp:1 {0}(219,367)(266,367)(266,227){1} wire [7:0] R0; //: /dp:3 {0}(575,491)(575,460)(389,460){1} //: {2}(385,460)(180,460)(180,373){3} //: {4}(387,462)(387,491){5} //: enddecls register g8 (.Q(R3), .D(AIN), .EN(w20), .CLR(w5), .CK(ck)); //: @(626,363) /sn:0 /w:[ 3 3 1 0 7 ] //: input g4 (SB) @(505,507) /sn:0 /w:[ 0 ] mux g13 (.I0(R0), .I1(R1), .I2(R2), .I3(R3), .S(SB), .Z(BOUT)); //: @(593,507) /sn:0 /w:[ 0 3 3 5 1 1 ] //: input g3 (SA) @(45,136) /sn:0 /w:[ 5 ] //: output g2 (BOUT) @(593,546) /sn:0 /R:3 /w:[ 0 ] //: output g1 (AOUT) @(405,546) /sn:0 /R:3 /w:[ 1 ] //: joint g16 (R0) @(387, 460) /w:[ 1 -1 2 4 ] //: joint g11 (ck) @(275, 392) /w:[ 4 10 3 -1 ] //: supply1 g10 (w21) @(192,173) /sn:0 /w:[ 1 ] //: joint g27 (ck) @(126, 392) /w:[ 2 12 1 -1 ] //: joint g19 (R1) @(399, 420) /w:[ 2 -1 4 1 ] register g6 (.Q(R1), .D(AIN), .EN(w3), .CLR(w0), .CK(ck)); //: @(322,363) /sn:0 /w:[ 5 9 1 0 11 ] demux g9 (.I(SA), .E(w21), .Z0(!w8), .Z1(!w3), .Z2(!w4), .Z3(!w20)); //: @(284,211) /sn:0 /w:[ 3 0 1 0 0 0 ] register g7 (.Q(R2), .D(AIN), .EN(w4), .CLR(w1), .CK(ck)); //: @(467,363) /sn:0 /w:[ 5 11 1 0 9 ] register g15 (.Q(R0), .D(AIN), .EN(w8), .CLR(w2), .CK(ck)); //: @(180,362) /sn:0 /w:[ 3 7 0 0 13 ] //: joint g20 (SA) @(92, 136) /w:[ 2 -1 4 1 ] //: supply1 g25 (w2) @(242,340) /sn:0 /w:[ 1 ] //: joint g17 (R3) @(611, 447) /w:[ 2 -1 1 4 ] mux g14 (.I0(R0), .I1(R1), .I2(R2), .I3(R3), .S(SA), .Z(AOUT)); //: @(405,507) /sn:0 /w:[ 5 0 0 0 0 0 ] //: input g5 (ck) @(49,392) /sn:0 /w:[ 0 ] //: joint g24 (AIN) @(467, 287) /w:[ 2 1 4 10 ] //: supply1 g21 (w0) @(384,339) /sn:0 /w:[ 1 ] //: supply1 g23 (w5) @(691,340) /sn:0 /w:[ 1 ] //: joint g26 (AIN) @(322, 287) /w:[ 5 -1 6 8 ] //: supply1 g22 (w1) @(530,339) /sn:0 /w:[ 1 ] //: input g0 (AIN) @(467,142) /sn:0 /R:3 /w:[ 0 ] //: joint g18 (R2) @(467, 432) /w:[ 2 4 1 -1 ] //: joint g12 (ck) @(414, 392) /w:[ 6 8 5 -1 ] endmodule module main; //: root_module supply1 w7; //: /sn:0 {0}(256,325)(256,312){1} supply0 w2; //: /sn:0 {0}(295,430)(295,445)(258,445){1} //: {2}(254,445)(223,445)(223,429){3} //: {4}(256,447)(256,457){5} supply0 w12; //: /sn:0 {0}(478,499)(478,481)(460,481){1} supply0 w11; //: /sn:0 {0}(496,395)(496,373)(480,373){1} supply1 w10; //: /sn:0 /dp:1 {0}(460,471)(474,471)(474,453){1} supply0 [7:0] w9; //: /sn:0 {0}(387,395)(387,385)(411,385)(411,414){1} wire [7:0] w6; //: /sn:0 /dp:1 {0}(711,277)(711,265)(771,265){1} //: {2}(775,265)(817,265)(817,561)(695,561)(695,538){3} //: {4}(773,263)(773,252){5} wire b; //: /dp:1 {0}(62,491)(98,491){1} //: {2}(100,489)(100,461)(116,461){3} //: {4}(100,493)(100,537)(128,537){5} wire [7:0] w14; //: /sn:0 /dp:1 {0}(440,359)(440,332){1} wire [7:0] w16; //: /sn:0 {0}(431,414)(431,400)(456,400)(456,388){1} wire [7:0] w15; //: /sn:0 /dp:1 {0}(748,364)(748,335)(771,335){1} //: {2}(775,335)(798,335)(798,552)(758,552)(758,538){3} //: {4}(773,333)(773,320){5} wire w4; //: /sn:0 /dp:1 {0}(194,535)(149,535){1} wire w19; //: /sn:0 /dp:1 {0}(398,430)(361,430){1} wire w0; //: /sn:0 {0}(157,333)(229,333){1} //: {2}(233,333)(242,333){3} //: {4}(231,331)(231,323){5} //: {6}(231,335)(231,421)(281,421){7} wire w3; //: /sn:0 /dp:1 {0}(194,530)(164,530)(164,514){1} wire [1:0] w21; //: /sn:0 {0}(635,453)(652,453)(652,471)(678,471){1} wire w28; //: /sn:0 {0}(637,293)(678,293){1} wire [1:0] w23; //: /sn:0 /dp:1 {0}(678,491)(651,491)(651,503)(637,503){1} wire [7:0] w20; //: /sn:0 {0}(421,443)(421,466){1} wire w1; //: /sn:0 {0}(156,367)(192,367){1} //: {2}(196,367)(242,367){3} //: {4}(194,365)(194,358){5} //: {6}(194,369)(194,420)(209,420){7} wire co; //: /dp:1 {0}(215,533)(228,533)(228,522){1} wire [7:0] w25; //: /sn:0 {0}(658,233)(691,233)(691,277){1} wire w8; //: /sn:0 /dp:1 {0}(191,459)(163,459){1} //: {2}(159,459)(137,459){3} //: {4}(161,461)(161,493){5} wire w18; //: /sn:0 {0}(432,373)(422,373){1} wire [7:0] w17; //: /sn:0 {0}(725,456)(725,431){1} wire ci; //: {0}(62,420)(166,420)(166,462){1} //: {2}(168,464)(191,464){3} //: {4}(166,466)(166,493){5} wire clk; //: {0}(323,476)(384,476){1} wire w13; //: /sn:0 {0}(223,412)(223,393)(254,393){1} //: {2}(258,393)(293,393){3} //: {4}(295,391)(295,381){5} //: {6}(295,395)(295,413){7} //: {8}(256,391)(256,376){9} wire s; //: /dp:1 {0}(212,462)(230,462)(230,479){1} wire ck; //: /sn:0 {0}(611,559)(665,559)(665,513)(678,513){1} wire w5; //: /sn:0 /dp:1 {0}(256,342)(256,359){1} wire a; //: {0}(62,456)(104,456){1} //: {2}(108,456)(116,456){3} //: {4}(106,458)(106,532)(128,532){5} wire [7:0] w29; //: /sn:0 /dp:1 {0}(701,364)(701,306){1} wire [7:0] reg_out; //: {0}(421,487)(421,523)(466,523){1} //: {2}(470,523)(520,523)(520,348)(472,348)(472,359){3} //: {4}(468,525)(468,542){5} wire [1:0] w26; //: /sn:0 /dp:1 {0}(637,356)(658,356)(658,393)(680,393){1} //: enddecls //: comment g61 /dolink:1 /link:"@T/edwire_tut.v" @(622,100) /sn:0 /anc:1 //: /line:"¥ï¥¤¥ä¤ÎÊÔ½¸" //: /end nmos g4 (.Z(w2), .S0(w13), .G0(w0)); //: @(289,421) /sn:0 /w:[ 0 7 7 ] //: supply1 g8 (w7) @(267,312) /sn:0 /w:[ 1 ] clock g51 (.Z(ck)); //: @(598,559) /sn:0 /w:[ 0 ] /omega:200 /phi:0 /duty:50 //: switch g3 (w0) @(140,333) /sn:0 /w:[ 0 ] /st:0 //: joint g13 (w1) @(194, 367) /w:[ 2 4 1 6 ] or g34 (.I0(w3), .I1(w4), .Z(co)); //: @(205,533) /sn:0 /w:[ 0 0 0 ] clock g37 (.Z(clk)); //: @(310,476) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 led g55 (.I(w0)); //: @(231,316) /sn:0 /w:[ 5 ] /type:0 //: joint g58 (w6) @(773, 265) /w:[ 2 4 1 -1 ] //: comment g2 /dolink:0 /link:"" @(-2,217) /sn:0 /anc:1 //: /line:"" //: /end led g59 (.I(w15)); //: @(773,313) /sn:0 /w:[ 5 ] /type:2 //: comment g1 /dolink:1 /link:"@T/edit1_tut.v" @(622,70) /sn:0 /anc:1 //: /line:"´ðËܤÎÊÔ½¸¥â¡¼¥É" //: /end //: comment g16 /dolink:1 /link:"@T/module_tut.v" @(622,115) /sn:0 /anc:1 //: /line:"¥â¥¸¥å¡¼¥ë¤Î»È¤¤Êý" //: /end //: joint g11 (w2) @(256, 445) /w:[ 1 -1 2 4 ] led g50 (.I(co)); //: @(228,515) /sn:0 /w:[ 1 ] /type:0 //: supply0 g10 (w2) @(256,463) /sn:0 /w:[ 5 ] and g28 (.I0(a), .I1(b), .Z(w4)); //: @(139,535) /sn:0 /w:[ 5 5 1 ] //: joint g19 (w0) @(231, 333) /w:[ 2 4 1 6 ] //: switch g27 (ci) @(45,420) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w8) @(161, 459) /w:[ 1 -1 2 4 ] //: dip sa (w21) @(597,453) /R:1 /w:[ 0 ] /st:0 nmos g6 (.Z(w2), .S0(w13), .G0(w1)); //: @(217,420) /sn:0 /w:[ 3 0 7 ] //: supply0 g38 (w12) @(478,505) /sn:0 /w:[ 0 ] mux g53 (.I0(w25), .I1(w6), .S(w28), .Z(w29)); //: @(701,293) /sn:0 /w:[ 1 0 1 1 ] pmos g7 (.Z(w7), .S0(w5), .G0(w0)); //: @(250,333) /sn:0 /w:[ 0 0 3 ] //: joint g9 (w13) @(256, 393) /w:[ 2 8 1 -1 ] //: joint g57 (w13) @(295, 393) /w:[ -1 4 3 6 ] //: frame g15 @(600,25) /sn:0 /anc:1 /wi:224 /ht:149 /tx:"¥Á¥å¡¼¥È¥ê¥¢¥ë" //: comment g20 /dolink:1 /link:"@T/create_tut.v" @(622,55) /sn:0 /anc:1 //: /line:"²óÏ©¤ÎºîÀ®" //: /end and g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(164,504) /sn:0 /R:3 /w:[ 5 5 1 ] //: dip sb (w23) @(599,503) /R:1 /w:[ 1 ] /st:1 //: supply1 g39 (w10) @(485,453) /sn:0 /w:[ 1 ] led g48 (.I(reg_out)); //: @(468,549) /sn:0 /R:2 /w:[ 5 ] /type:1 //: dip func (w26) @(599,356) /R:1 /w:[ 0 ] /st:0 //: supply0 g43 (w11) @(496,401) /sn:0 /w:[ 0 ] REGS regs (.AIN(w17), .ck(ck), .SB(w23), .SA(w21), .AOUT(w6), .BOUT(w15)); //: @(679, 457) /sz:(94, 80) /p:[ Ti0>0 Li0>1 Li1>0 Li2>1 Bi0>3 Bi1>3 ] ALU alu (.B(w15), .A(w29), .F(w26), .Z(w17)); //: @(681, 365) /sz:(89, 65) /p:[ Ti0>0 Ti1>0 Li0>1 Bo0<1 ] //: comment g17 /dolink:1 /link:"@T/sim_tut.v" @(622,130) /sn:0 /anc:1 //: /line:"Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: switch g25 (a) @(45,456) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a) @(106, 456) /w:[ 2 -1 1 4 ] led g62 (.I(w6)); //: @(773,245) /sn:0 /w:[ 5 ] /type:2 led g52 (.I(s)); //: @(230,486) /sn:0 /R:2 /w:[ 1 ] /type:0 //: dip g42 (w14) @(440,322) /sn:0 /w:[ 1 ] /st:248 //: dip data_in (w25) @(620,233) /R:1 /w:[ 0 ] /st:11 pmos g5 (.Z(w5), .S0(w13), .G0(w1)); //: @(250,367) /sn:0 /w:[ 1 9 3 ] led g56 (.I(w13)); //: @(295,374) /sn:0 /w:[ 5 ] /type:0 //: comment g14 /dolink:1 /link:"@T/seqsim_tut.v" @(622,145) /sn:0 /anc:1 //: /line:"½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó" //: /end //: switch g44 (w19) @(344,430) /sn:0 /w:[ 1 ] /st:1 //: comment g47 /dolink:0 /link:"" @(106,285) /sn:0 //: /line:"¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢»Ï¤á¤è¤¦!" //: /end //: comment g21 /dolink:1 /link:"@T/edit2_tut.v" @(622,85) /sn:0 /anc:1 //: /line:"¥°¥ë¡¼¥×¤ÎÊÔ½¸µ¡Ç½" //: /end xor g24 (.I0(w8), .I1(ci), .Z(s)); //: @(202,462) /sn:0 /w:[ 0 3 0 ] add g36 (.A(w14), .B(reg_out), .S(w16), .CI(w11), .CO(w18)); //: @(456,375) /sn:0 /w:[ 0 3 1 1 0 ] xor g23 (.I0(a), .I1(b), .Z(w8)); //: @(127,459) /sn:0 /w:[ 3 3 3 ] //: supply0 g41 (w9) @(387,401) /sn:0 /w:[ 0 ] mux g40 (.I0(w9), .I1(w16), .S(w19), .Z(w20)); //: @(421,430) /sn:0 /w:[ 1 0 0 0 ] led g54 (.I(w1)); //: @(194,351) /sn:0 /w:[ 5 ] /type:0 //: joint g60 (w15) @(773, 335) /w:[ 2 4 1 -1 ] //: switch data_select (w28) @(620,293) /w:[ 0 ] /st:0 //: comment g22 /dolink:0 /link:"" @(605,40) /sn:0 /anc:1 //: /line:"->" //: /end //: comment g0 /dolink:0 /link:"" @(13,16) /anc:1 //: /line:"TkGate¤Ø¤è¤¦¤³¤½!" //: /line:"" //: /line:"Copyright (C) 1987-2000 by Jeffery P. Hansen" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to hansen@cmu.edu" //: /line:"" //: /line:" * TkGate¤ò¼Â¹Ô¤¹¤ë»þ¡¢¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤¬¼«Æ°Åª¤ËÆɤ߹þ¤Þ¤ì¤ë¡£¤³¤Îµ¡Ç½¤ò" //: /line:" ̵¸ú¤Ë¤¹¤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¤Î²¼¤Î¡ÖÀßÄê...¡×¤òÁªÂò¤·¤Æ¡¢¡Ö½é¿´¼Ô¥â¡¼¥É¡×¤Î" //: /line:" ¥Á¥§¥Ã¥¯¡¦¥Ü¥¿¥ó¤ò¾Ã¤·¤Æ²¼¤µ¤¤¡£" //: /line:"" //: /line:" * ¿·¤·¤¤²óÏ©¤òºîÀ®¤¹¤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¤Î²¼¤Î¡Ö¿·µ¬ºîÀ®¡×¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£" //: /line:" ¸ºß¤·¤Æ¤¤¤ë²óÏ©¤òÊÔ½¸¤¹¤ë°Ù¡¢¡Ö¥Õ¥¡¥¤¥ë¡×¤Î²¼¤Î¡Ö³«¤¯...¡×¤òÁªÂò¤·¤Æ¤¯¤À¤µ¤¤¡£" //: /line:"" //: /line:" * TkGate¤Î¥É¥­¥å¥á¥ó¥È¤Ê¤É¤Ïhttp://www.cs.cmu.edu/~hansen/tkgate¤Ë¤¢¤ë¡£" //: /line:"" //: /line:"¤³¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ç¤Ï¡¢TkGate¤Î´ðËܤλȤ¤Êý¤ò¾Ò²ð¤¹¤ë¡£±¦¾å¤Î¥Ï¥¤¥Ñ¡¼¥ê¥ó¥¯¡¢" //: /line:"Ëô¤Ï¡¢¡Ö¥Ø¥ë¥×¡×¤Î¥á¥Ë¥å¡¼¤Ç¡¢¤½¤ì¤¾¤ì¤Î¥Á¥å¡¼¥È¥ê¥¢¥ë¤ò¸«¤Æ¤¯¤À¤µ¤¤¡£" //: /line:"³Æ¥Á¥å¡¼¥È¥ê¥¢¥ë¤ÎÀâÌÀ¤Ë½¾¤Ã¤Æ¡¢TkGate¤ÎÁàºî¤òÎý½¬¤·¤Æ²¼¤µ¤¤¡£Á´¤Æ¤Î¥Á¥å¡¼¥È" //: /line:"¥ê¥¢¥ë¤ò½ª¤Ã¤¿¤é¡¢¡Ö¥Ø¥ë¥×¡×¥á¥Ë¥å¡¼¤Ç´ö¤Ä¤«¤ÎÎãÂê²óÏ©¤âÆɤ߹þ¤á¤é¤ì¤ë¡£" //: /line:"" //: /end //: switch g26 (b) @(45,491) /sn:0 /w:[ 0 ] /st:1 register g35 (.Q(reg_out), .D(w20), .EN(w12), .CLR(w10), .CK(clk)); //: @(421,476) /sn:0 /w:[ 0 1 1 0 1 ] //: comment g46 /dolink:1 /link:"@T/create_tut.v" @(11,285) /sn:0 //: /line:"¡Ö²óÏ©¤ÎºîÀ®¡×" //: /end //: comment g18 /dolink:0 /link:"@T/welcome_tut.v" @(622,40) /sn:0 /anc:1 //: /line:"TkGate¤Î¾Ò²ð" //: /end //: switch g12 (w1) @(139,367) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b) @(100, 491) /w:[ -1 2 1 4 ] //: joint g33 (ci) @(166, 464) /w:[ 2 1 -1 4 ] //: joint g49 (reg_out) @(468, 523) /w:[ 2 -1 1 4 ] endmodule tkgate-2.0-b10/locale/ja/tutorials/sequential5.v000644 001751 001751 00000007141 10624605075 022323 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:199,201)(199,227){1} supply0 w3; //: /sn:0 {0}(252,251)(252,241)(239,241){1} supply0 w0; //: /sn:0 {0}(254,296)(274,296)(274,307){1} reg clr; //: {0}(32:254,286)(285,286){1} wire [7:0] w2; //: /sn:0 {0}(#:215,281)(215,256){1} wire ck; //: {0}(50:178,291)(113,291){1} wire [7:0] reg_out; //: {0}(#:215,302)(215,328)(273,328){1} //: {2}(277,328)(333,328)(52:333,215)(231,215)(231,227){3} //: {4}(275,330)(275,338){5} wire w9; //: /sn:0 {0}(191,241)(181,241){1} //: enddecls //: joint g8 (reg_out) @(275, 328) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(274,313) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) //: /line:"

Sequential Simulation

(scripts)" //: /line:"" //: /line:"In addition to interactive simulator control, you can also write a simulator script." //: /line:"Simulator script files have the extension \".vs\" and are written using Verilog" //: /line:"syntax. While the simulator is active, press to load a simulator script file." //: /line:"You can use a script file to set and remove probes, advance the simulation time," //: /line:"set signal values and display messages in the TkGate log () window. See" //: /line:"the TkGate 2.0 documentation for details on how to write simulator scripts." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(clr), .CK(ck)); //: @(215,291) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(495,118) /sn:0 /R:14 /anc:1 //: /line:"Simulator Script Example:" //: /line:"" //: /line:"initial" //: /line:" begin" //: /line:" $display(\"%t: Start of script\",$time);" //: /line:" $tkg$probe(ck, reg_out, clr);" //: /line:" $display(\"%t: Set probes\",$time);" //: /line:" clr = 1'b0;" //: /line:" #200;" //: /line:" clr = 1'b1;" //: /line:" $display(\"%t: Done with reset\",$time);" //: /line:" #500;" //: /line:" $stop();" //: /line:" end" //: /line:"" //: /end //: DIP g6 (w7) @(199,191) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(252,257) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(275,345) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(215,243) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(100,291) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (clr) @(303,286) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/group.v000644 001751 001751 00000025175 11140741612 021217 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(140,67) /sn:0 /anc:1 //: /line:"" //: /end //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

" //: /line:"" //: /line:"In this chapter, you will learn about how to do editing operations on groups of gates." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:183,147)(289,147)(289,189){1} //: {2}(291,191)(314,191){3} //: {4}(289,193)(289,210){5} reg a0; //: {0}(40:183,183)(227,183){1} //: {2}(231,183)(239,183){3} //: {4}(229,185)(229,239)(246,239){5} reg b0; //: {0}(50:183,218)(221,218){1} //: {2}(223,216)(223,188)(239,188){3} //: {4}(223,220)(223,244)(246,244){5} wire w7; //: /sn:0 {0}(267,242)(282,242)(282,254){1} wire s0; //: {0}(36:335,189)(365,189){1} wire w4; //: /sn:0 {0}(287,231)(287,254){1} wire c1; //: {0}(99:285,275)(285,294){1} wire w9; //: /sn:0 {0}(314,186)(286,186){1} //: {2}(282,186)(260,186){3} //: {4}(284,188)(284,210){5} //: enddecls //: LED g37 (s0) @(372,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(285,265) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(257,242) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(284, 186) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(166,147) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(287,221) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(229, 183) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(166,183) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(incremental selection)" //: /line:"" //: /line:"You can add or remove gates from the current selection by holding the Control key while" //: /line:"you click on them. Use the selection box to select the gates below then click on a few" //: /line:"of the gates with the Control key held down. Release the Control key and then try moving" //: /line:"the selection with only some of the gates selected." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(325,189) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(250,186) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(166,218) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(289, 191) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(223, 218) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:167,153)(273,153)(273,195){1} //: {2}(275,197)(298,197){3} //: {4}(273,199)(273,216){5} reg a0; //: {0}(40:167,189)(189,189)(189,189)(211,189){1} //: {2}(215,189)(223,189){3} //: {4}(213,191)(213,245)(230,245){5} reg b0; //: {0}(50:167,224)(186,224)(186,224)(205,224){1} //: {2}(207,222)(207,194)(223,194){3} //: {4}(207,226)(207,250)(230,250){5} wire w7; //: /sn:0 {0}(251,248)(266,248)(266,260){1} wire s0; //: {0}(36:319,195)(349,195){1} wire w4; //: /sn:0 {0}(271,237)(271,260){1} wire c1; //: {0}(99:269,281)(269,300){1} wire w9; //: /sn:0 {0}(298,192)(270,192){1} //: {2}(266,192)(244,192){3} //: {4}(268,194)(268,216){5} //: enddecls //: LED g37 (s0) @(356,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(570,113) /sn:0 //: /line:"Hint: If a selection contains any" //: /line:"anchored gates, the entire selection" //: /line:"will act as if it were anchored." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(269,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(241,248) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(268, 192) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(150,153) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(271,227) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(213, 189) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(150,189) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(rotation and anchoring)" //: /line:"" //: /line:"You can rotate (with and ) and anchor (with and ) a group of gates in the same" //: /line:"way as you did for single gates in the Editing Gates chapter. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(309,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(234,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(150,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(273, 197) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(207, 224) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:182,149)(288,149)(288,191){1} //: {2}(290,193)(313,193){3} //: {4}(288,195)(288,212){5} reg a0; //: {0}(40:182,185)(226,185){1} //: {2}(230,185)(238,185){3} //: {4}(228,187)(228,241)(245,241){5} reg b0; //: {0}(50:182,220)(220,220){1} //: {2}(222,218)(222,190)(238,190){3} //: {4}(222,222)(222,246)(245,246){5} wire w7; //: /sn:0 {0}(266,244)(281,244)(281,256){1} wire s0; //: {0}(36:334,191)(364,191){1} wire w4; //: /sn:0 {0}(286,233)(286,256){1} wire c1; //: {0}(99:284,277)(284,296){1} wire w9; //: /sn:0 {0}(313,188)(285,188){1} //: {2}(281,188)(259,188){3} //: {4}(283,190)(283,212){5} //: enddecls //: LED g37 (s0) @(371,191) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(609,113) /sn:0 //: /line:"Hint: Click in a blank area to" //: /line:"unselect a group." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(284,267) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(256,244) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(283, 188) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(165,149) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(286,223) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(228, 185) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(165,185) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(selection and movement)" //: /line:"" //: /line:"To select a group of gates, press and hold the left mouse button above and to the left" //: /line:"of the group, then drag the cursor diagonally accross the group to open the selection box." //: /line:"Release the mouse when the selection box includes all of the gates you wish to select. Drag" //: /line:"any selected gate to move the entire group. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(324,191) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(249,188) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(165,220) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(288, 193) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(222, 220) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:174,160)(280,160)(280,202){1} //: {2}(282,204)(305,204){3} //: {4}(280,206)(280,223){5} reg a0; //: {0}(40:174,196)(196,196)(196,196)(218,196){1} //: {2}(222,196)(230,196){3} //: {4}(220,198)(220,252)(237,252){5} reg b0; //: {0}(50:174,231)(193,231)(193,231)(212,231){1} //: {2}(214,229)(214,201)(230,201){3} //: {4}(214,233)(214,257)(237,257){5} wire w7; //: /sn:0 {0}(258,255)(273,255)(273,267){1} wire s0; //: {0}(36:326,202)(356,202){1} wire w4; //: /sn:0 {0}(278,244)(278,267){1} wire c1; //: {0}(99:276,288)(276,307){1} wire w9; //: /sn:0 {0}(305,199)(277,199){1} //: {2}(273,199)(251,199){3} //: {4}(275,201)(275,223){5} //: enddecls //: LED g37 (s0) @(363,202) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(548,117) /sn:0 //: /line:"Hint: Hitting the Delete key will" //: /line:"delete all of the selected gates" //: /line:"without copying it to the clipboard." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(276,278) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(248,255) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(275, 199) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(157,160) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(278,234) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(220, 196) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(157,196) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(clipboard operations)" //: /line:"" //: /line:"You can use Cut and Paste operations to cut or copy a group of gates to the clipboard" //: /line:"and paste it somewhere else. Select a group of gates then press the or buttons to" //: /line:"cut or copy, respectively, the selected gates to the clipboard. To paste the contents of the" //: /line:"clipboard, first set a with the left mouse button, then press the button to paste the" //: /line:"clipboard contents to that location." //: /line:"" //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(316,202) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(241,199) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(157,231) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(280, 204) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(214, 231) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/wires.v000644 001751 001751 00000045640 11140741606 021216 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Wires

" //: /line:"" //: /line:"This chapter will introduce the basic wire editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(185,114) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:155,153)(261,153)(261,195){1} //: {2}(263,197)(286,197){3} //: {4}(261,199)(261,209){5} reg a0; //: {0}(40:155,189)(199,189){1} //: {2}(203,189)(211,189){3} //: {4}(201,191)(201,245)(218,245){5} reg b0; //: {0}(50:155,224)(193,224){1} //: {2}(195,222)(195,194)(211,194){3} //: {4}(195,226)(195,250)(218,250){5} wire w7; //: /sn:0 {0}(239,248)(254,248)(254,260){1} wire s0; //: {0}(36:307,195)(337,195){1} wire w4; //: /sn:0 {0}(259,230)(259,260){1} wire c1; //: {0}(99:257,281)(257,300){1} wire w9; //: /sn:0 {0}(286,192)(258,192){1} //: {2}(254,192)(232,192){3} //: {4}(256,194)(256,209){5} //: enddecls //: LED g37 (s0) @(344,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Basic Editing Modes

(wire labels)" //: /line:"" //: /line:"Wire label editing is performed with the tool. Select this tool if it is not already selected. Existing" //: /line:"wire labels can be moved by left clicking and dragging the label to a new position. Wire labels can only" //: /line:"be moved to a different locations on the wire from which it was grabbed. If you drop the label too far from" //: /line:"its wire, the label will be discarded. To display a new label right click on the wire and choose the Show" //: /line:"Label option. You can also hide a specific label (Hide Label) or hide all labels for a wire (Hide All Labels)." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(257,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(229,248) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(256, 192) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(138,153) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(259,220) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(201, 189) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(138,189) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(297,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(222,192) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(138,224) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(261, 197) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(195, 224) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin advanced module advanced(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w14; //: /sn:0 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} //: enddecls _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: comment g4 @(16,548) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(549,50) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g9 @(23,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(cutting)" //: /line:"" //: /line:"To cut a wire, select the tool and click on a wire at the point you wish to cut. Try" //: /line:"using the wire cutter tool to cut some of the wires in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] supply1 w7; //: /sn:0 {0}(320,176)(335,176)(335,158){1} reg [7:0] w3; //: /sn:0 {0}(#:184,170)(184,208)(212,208)(212,224){1} supply0 w8; //: /sn:0 {0}(271,250)(271,238)(252,238){1} supply0 w5; //: /sn:0 {0}(339,207)(339,186)(320,186){1} wire [7:0] w6; //: /sn:0 {0}(281,171)(281,146)(371,146)(371,268)(#:228,268)(#:228,253){1} wire w4; //: /sn:0 {0}(204,238)(189,238){1} wire [7:0] w1; //: /sn:0 {0}(244,224)(244,211)(#:281,211)(#:281,192){1} wire w2; //: /sn:0 {0}(85,181)(244,181){1} //: enddecls //: GROUND g4 (w5) @(339,213) /sn:0 /w:[ 0 ] //: DIP g8 (w3) @(184,160) /sn:0 /w:[ 0 ] /st:66 //: comment g2 @(9,10) /anc:1 //: /line:"

Basic Editing Modes

(bit widths)" //: /line:"" //: /line:"To change the bit size of one or more wires, first enter the desired bit size in the" //: /line:"bit size selector . Next, choose the tool, and click on each wire" //: /line:"to be changed to that size. Try changing the 8-bit wires in the circuit below to 16-bit wires." //: /line:"" //: /end _GGREG8 #(10, 10, 20) g1 (.Q(w1), .D(w6), .EN(w5), .CLR(w7), .CK(w2)); //: @(281,181) /sn:0 /w:[ 1 0 1 0 1 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGCLOCK_P100_0_50 g6 (.Z(w2)); //: @(72,181) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g7 (w8) @(271,256) /sn:0 /w:[ 0 ] //: VDD g5 (w7) @(346,158) /sn:0 /w:[ 1 ] _GGADD8 #(68, 70, 62, 64) g0 (.A(w3), .B(w1), .S(w6), .CI(w8), .CO(w4)); //: @(228,240) /sn:0 /w:[ 1 0 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Basic Editing Modes

(I/O inverters)" //: /line:"" //: /line:"To place or remove an inverter on a gate input or output, select the tool" //: /line:"and click on the port at which you want to place or remove an inveter. Try" //: /line:"using the inverter tool to place and remove inverters in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,11) //: /line:"

Basic Editing Modes

(properties)" //: /line:"" //: /line:"Wire properties" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; specify $setup(D,posedge CK, Dsetup); $hold(posedge CK,D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/sequential2.v000644 001751 001751 00000007076 10624605075 022327 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: require "timer" //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:190,196)(190,222){1} reg w4; //: /sn:0 {0}(245,281)(256,281)(256,269)(266,269){1} supply0 w0; //: /sn:0 {0}(245,291)(268,291)(268,306){1} supply0 w3; //: /sn:0 {0}(243,246)(243,236)(230,236){1} wire [7:0] w2; //: /sn:0 {0}(#:206,276)(206,251){1} wire ck; //: {0}(50:169,286)(104,286){1} wire [7:0] reg_out; //: {0}(#:206,297)(206,327)(263,327){1} //: {2}(267,327)(323,327)(-70:323,200)(222,200)(222,222){3} //: {4}(265,329)(265,342){5} wire w9; //: /sn:0 {0}(182,236)(172,236){1} //: enddecls //: GROUND g4 (w0) @(268,312) /sn:0 /w:[ 1 ] //: joint g8 (reg_out) @(265, 327) /w:[ 2 -1 1 4 ] //: comment g3 @(533,149) /sn:0 /anc:1 //: /line:"Hint: In addition to using the scroll bar" //: /line:"on the logic analyzer, you can click and" //: /line:"drag in the main window to fine tune the" //: /line:"the position of the traces." //: /end //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(stepped simulation)" //: /line:"" //: /line:"Start the simulator by pressing the \" Simulate\" tab just as with a combinational circuit. Next, set probes" //: /line:"on the \"ck\" and \"reg_out\" signals by right clicking and selecting Add/Delete probe. Now advance" //: /line:"the simulator by a several \"clock steps\" by pressing the button or by pressing the Tab key. Notice that" //: /line:"the \"reg_out\" single show an unknown value of \"x\". In order to reset it and start the counter you," //: /line:"must first set the \"reset\" switch to \"off\", advance the simulator by a clock step, then return" //: /line:"the \"reset\" switch to the \"on\" position." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(206,286) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: DIP g6 (w7) @(190,186) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(265,349) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(243,252) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(206,238) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(91,286) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (w4) @(284,269) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/verilog.v000644 001751 001751 00000006111 11140741640 021520 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "texver_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"The TkGate simulator is based on the Verilog hardware description language. As such, any" //: /line:"modules you design using the graphical editor are translated into Verilog before being simulated." //: /line:"You can also write modules directly in Verilog. Note that this chapter is not designed to teach" //: /line:"Verilog, but rather to teach how to include Verilog modules in TkGate." //: /end //: comment g0 @(145,107) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(55, 80) /bd:[ Li0>d(64/80) Li1>c(48/80) Li2>b(32/80) Li3>a(16/80) Ro0 and set the type to HDL." //: /end //: comment g9 @(8,9) //: /line:"

Textual Verilog

" //: /line:"" //: /line:"1) Right click on the module below and select Open." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g5 (w4) @(246,131) /sn:0 /w:[ 1 ] /type:0 foo g0 (.a(w5), .b(w6), .c(w7), .d(w8), .z(w4)); //: @(164, 113) /sz:(55, 80) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>1 Ro0<0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/notes.v000644 001751 001751 00000002474 10624605075 021220 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "notes.v" module main; //: root_module //: enddecls //: comment g1 /dolink:1 /link:"@T/welcome_tut.v" @(611,27) /sn:0 //: /line:"Return to welcome." //: /end //: comment g0 /dolink:0 /link:"" @(42,57) /sn:0 //: /line:"* Make sure interface in library matches interfaces used in circuit." //: /line:"* Add HDL module type." //: /line:"* HTML tags in comments instead of all-or-nothing hyperlink." //: /line:"* How about a simulator selection dialog box with options for switches to include, etc." //: /line:"* Bitmap symbol editor for libraries" //: /line:"* HDL modules" //: /line:"* Current module's interface shown in lower left box." //: /line:"" //: /line:"BUGS:" //: /line:"* Landscape printing with A4 paper." //: /line:"* Lack of editing on edit interfaces screen." //: /line:"* Mysterious double modules on interface screen in welcome_tut.v" //: /line:"* Ctl-D duplicate a gate, then double click. prop box doesn't open." //: /line:"" //: /line:"TO DO:" //: /line:"" //: /line:"* Finish module interface generator" //: /line:"* Convert port box to use SpreadSheet" //: /line:"* Verilog Modules" //: /line:"* Custom Module Symbols" //: /line:"* Dialog box images" //: /line:"* Japanese messages.ja" //: /line:"" //: /end endmodule tkgate-2.0-b10/locale/ja/tutorials/glossary.v000644 001751 001751 00000002645 10624605075 021733 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module //: enddecls //: frame g15 @(600,25) /sn:0 /wi:213 /ht:149 /tx:"Tutorials" //: comment g14 @(629,42) /sn:0 //: /line:"TkGate Introduction
" //: /line:"Creating a Circuit
" //: /line:"Basic Editing Modes
" //: /line:"Group Editing Features
" //: /line:"Editing Wires
" //: /line:"Using Modules
" //: /line:"Combinational Simulation
" //: /line:"Sequential Simulation" //: /end //: comment g0 @(21,26) /sn:0 //: /line:"

Glossary

" //: /line:"" //: /line:"epoch: The smallest unit of time understood by the simulator." //: /line:"" //: /line:"Verilog format constant: The first number indicates the bit width, the" //: /line:"letter indicates the radix, and the last number the value. For example, the \"1\"" //: /line:"in \"1'b0\" indicates that this is a 1-bit value, the \"b\" indicates the value is" //: /line:"given in binary, and the \"0\" indicates the value of the signal." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/ja/tutorials/combinational2.v000644 001751 001751 00000006443 10624605075 022771 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:153,316)(167,316){1} //: {2}(171,316)(189,316){3} //: {4}(193,316)(241,316){5} //: {6}(191,314)(191,253)(236,253){7} //: {8}(169,314)(169,304){9} reg A; //: {0}(236,248)(204,248){1} //: {2}(202,246)(-86:202,228)(172,228){3} //: {4}(170,226)(170,215){5} //: {6}(168,228)(155,228){7} //: {8}(202,250)(202,311)(241,311){9} reg Cin; //: {0}(271,213)(291,213){1} //: {2}(293,211)(293,202){3} //: {4}(41:293,215)(293,244){5} //: {6}(295,246)(333,246){7} //: {8}(293,248)(293,272){9} wire w6; //: /sn:0 {0}(334,314)(262,314){1} wire w0; //: /sn:0 {0}(334,309)(291,309)(291,293){1} wire w1; //: /sn:0 {0}(333,251)(290,251){1} //: {2}(286,251)(257,251){3} //: {4}(288,253)(288,272){5} wire C; //: {0}(-21:403,221)(403,312)(355,312){1} wire S; //: {0}(354,249)(-39:373,249)(373,221){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(345,312) /sn:0 /w:[ 0 0 1 ] _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(247,251) /sn:0 /w:[ 0 7 3 ] //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(starting the simulator)" //: /line:"" //: /line:"Press the \" Simulate\" tab above the main canvas to enter simulation mode. When you first enter simulation" //: /line:"mode, the simulator will be paused as indicated by the depressed button on the simulator tool bar. Press" //: /line:"the button to begin simulation. Now try clicking on the switches to change their state and observe how the" //: /line:"LEDs change. When you are done, stop the simulator by pressing and go on to the next page." //: /end //: SWITCH g3 (Cin) @(254,213) /sn:0 /w:[ 0 ] /st:1 _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(252,314) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(136,316) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(288, 251) /w:[ 1 -1 2 4 ] //: LED g28 (A) @(170,208) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (Cin) @(293, 246) /w:[ 6 5 -1 8 ] //: joint g27 (Cin) @(293, 213) /w:[ -1 2 1 4 ] //: joint g6 (B) @(191, 316) /w:[ 4 6 3 -1 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(291,283) /sn:0 /R:3 /w:[ 5 9 1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(344,249) /sn:0 /w:[ 7 0 0 ] //: joint g31 (A) @(170, 228) /w:[ 3 4 6 -1 ] //: LED g29 (B) @(169,297) /sn:0 /w:[ 9 ] /type:0 //: LED g25 (C) @(403,214) /sn:0 /w:[ 0 ] /type:0 //: joint g5 (A) @(202, 248) /w:[ 1 2 -1 8 ] //: LED g26 (Cin) @(293,195) /sn:0 /w:[ 3 ] /type:0 //: SWITCH g0 (A) @(138,228) /sn:0 /w:[ 7 ] /st:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g18 (S) @(373,214) /sn:0 /w:[ 1 ] /type:0 //: joint g30 (B) @(169, 316) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/definition.txt000644 001751 001751 00000000000 10624605075 022551 0ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/ja/tutorials/interface.txt000644 001751 001751 00000002275 10624605075 022401 0ustar00hansenhansen000000 000000 Creating and Editing Module Interfaces 1) Select the "Interface" tab in the main window to start the interface editor. 2) Double-click on module "bar" in module list to edit its interface. 3) Double-click on a port name or port property to change it, any changes will be immediately reflected in the interface example. 4) Double-click on the blank line below the last port in the port list to add a new port. 5) You can also add a new port by right-clicking on the edge of the interface example and then selecting one of the "Add..." options. 6) Change the size of the interface by selecting and dragging the edge or corner of the box. 7) Move the position of a port by selecting and dragging it. Autogeneration of Interfaces 1) Double-clock on the module "foo" in the module list to bring it up in the inteface editor. It should have a blank interface with no ports. 2) To automatically generate an interface, click on the "Auto Generate" button, then select "OK". The generate ports on the interface will be determined from the ports used in the module definition. Return to Edit Mode Click on the "Edit" tab in the main window to switch to the definition for the inteface you have been editing. tkgate-2.0-b10/locale/ja/tutorials/moddef_tut.v000644 001751 001751 00000001377 10624605075 022223 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "module_tut.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g0 @(23,20) /sn:0 //: /line:"

Creating a Module Definition

" //: /line:"" //: /line:"1) Press on the tool bar." //: /line:"" //: /line:"2) Enter the name of the new module." //: /line:"" //: /line:"3) Select the type of module (Netlist or HDL)" //: /line:"" //: /line:"4) Click \"OK\" to create the module." //: /line:"" //: /line:"5) Edit it by double clicking on it in the module list." //: /line:"" //: /line:"Click here to return to the main module tutorial." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/ja/tutorials/welcome.v000644 001751 001751 00000060723 11140740223 021511 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /symbolBegin: 689601296 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module supply1 w7; //: /sn:0 {0}(456,31)(456,18){1} reg b; //: {0}(41:73,97)(109,97){1} //: {2}(111,95)(111,67)(127,67){3} //: {4}(111,99)(111,143)(139,143){5} reg [7:0] w19; //: /sn:0 {0}(#:703,66)(703,39){1} reg w0; //: /sn:0 {0}(357,39)(429,39){1} //: {2}(433,39)(442,39){3} //: {4}(431,37)(431,29){5} //: {6}(431,41)(431,127)(481,127){7} reg [1:0] w21; //: /sn:0 {0}(#:136,463)(96,463)(96,428)(90,428){1} reg w28; //: /sn:0 {0}(69,268)(89,268)(89,268)(118,268){1} reg [1:0] w23; //: /sn:0 {0}(#:136,478)(90,478){1} reg w20; //: /sn:0 {0}(661,137)(624,137){1} reg w1; //: /sn:0 {0}(357,73)(392,73){1} //: {2}(396,73)(442,73){3} //: {4}(394,71)(394,64){5} //: {6}(394,75)(394,126)(409,126){7} reg [7:0] w25; //: /sn:0 {0}(#:90,208)(131,208)(131,252){1} supply0 w18; //: /sn:0 {0}(741,206)(741,188)(723,188){1} supply0 w2; //: /sn:0 {0}(495,136)(495,152)(458,152){1} //: {2}(454,152)(423,152)(423,135){3} //: {4}(456,154)(456,163){5} supply0 w11; //: /sn:0 {0}(759,102)(759,80)(743,80){1} reg ci; //: {0}(12:73,26)(177,26)(177,68){1} //: {2}(179,70)(202,70){3} //: {4}(177,72)(177,99){5} supply1 w10; //: /sn:0 {0}(723,178)(737,178)(737,160){1} reg a; //: {0}(30:73,62)(115,62){1} //: {2}(119,62)(127,62){3} //: {4}(117,64)(117,138)(139,138){5} supply0 [7:0] w9; //: /sn:0 {0}(#:650,102)(650,92)(674,92)(674,121){1} reg [1:0] w26; //: /sn:0 {0}(#:90,331)(111,331)(111,368)(120,368){1} wire [7:0] w14; //: /sn:0 {0}(#:153,508)(153,545)(248,545)(248,237)(215,237){1} //: {2}(213,235)(213,218){3} //: {4}(211,237)(151,237)(151,252){5} wire w4; //: /sn:0 {0}(205,141)(160,141){1} wire w3; //: /sn:0 {0}(205,136)(175,136)(175,120){1} wire w24; //: /sn:0 {0}(695,80)(685,80){1} wire co; //: {0}(245,129)(-68:245,139)(226,139){1} wire w8; //: /sn:0 {0}(202,65)(174,65){1} //: {2}(170,65)(148,65){3} //: {4}(172,67)(172,99){5} wire [7:0] w30; //: /sn:0 {0}(#:180,508)(180,520)(228,520)(228,310)(215,310){1} //: {2}(213,308)(213,295){3} //: {4}(211,310)(188,310)(188,339){5} wire [7:0] w22; //: /sn:0 {0}(#:694,121)(694,107)(719,107)(719,95){1} wire [7:0] w12; //: /sn:0 {0}(#:165,449)(165,406){1} wire clk; //: {0}(20:593,183)(647,183){1} wire w13; //: /sn:0 {0}(423,118)(423,99)(454,99){1} //: {2}(458,99)(493,99){3} //: {4}(495,97)(495,87){5} //: {6}(495,101)(495,119){7} //: {8}(456,97)(456,82){9} wire s; //: {0}(246,80)(39:246,68)(223,68){1} wire [7:0] w27; //: /sn:0 {0}(#:684,150)(684,173){1} wire w33; //: /sn:0 {0}(136,493)(86,493)(86,529)(59,529){1} wire w5; //: /sn:0 {0}(456,48)(456,65){1} wire [7:0] w29; //: /sn:0 {0}(#:141,339)(141,281){1} wire [7:0] reg_out; //: {0}(#:684,194)(50:684,230)(729,230){1} //: {2}(-24:733,230)(783,230)(783,55)(735,55)(735,66){3} //: {4}(731,232)(731,249){5} //: enddecls _GGNMOS #(2, 1) g4 (.Z(w13), .S(w2), .G(w0)); //: @(489,127) /sn:0 /w:[ 7 0 7 ] //: VDD g8 (w7) @(467,18) /sn:0 /w:[ 1 ] //: joint g61 (reg_out) @(731, 230) /w:[ 2 -1 1 4 ] _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(46,529) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 //: SWITCH g3 (w0) @(340,39) /sn:0 /w:[ 0 ] /st:0 //: joint g13 (w1) @(394, 73) /w:[ 2 4 1 6 ] _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co)); //: @(216,139) /sn:0 /w:[ 0 0 1 ] /eb:0 //: LED g55 (w0) @(431,22) /sn:0 /w:[ 5 ] /type:0 REGS g2 (.SA(w21), .AIN(w12), .AOUT(w14), .SB(w23), .BOUT(w30), .ck(w33)); //: @(165, 479) /symbol:689601296 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(213,288) /sn:0 /w:[ 3 ] /type:2 _GGCLOCK_P120_0_50 g1 (.Z(clk)); //: @(580,183) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 //: joint g16 (w30) @(213, 310) /w:[ 1 2 4 -1 ] //: joint g11 (w2) @(456, 152) /w:[ 1 -1 2 4 ] //: GROUND g10 (w2) @(456,169) /sn:0 /w:[ 5 ] _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4)); //: @(150,141) /sn:0 /w:[ 5 5 1 ] /eb:0 //: joint g19 (w0) @(431, 39) /w:[ 2 4 1 6 ] //: SWITCH g27 (ci) @(56,26) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w8) @(172, 65) /w:[ 1 -1 2 4 ] //: DIP sa (w21) @(52,428) /R:1 /w:[ 1 ] /st:0 _GGNMOS #(2, 1) g6 (.Z(w13), .S(w2), .G(w1)); //: @(417,126) /sn:0 /w:[ 0 3 7 ] _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(141,268) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 _GGPMOS #(2, 1) g7 (.Z(w5), .S(w7), .G(w0)); //: @(450,39) /sn:0 /w:[ 0 0 3 ] //: joint g9 (w13) @(456, 99) /w:[ 2 8 1 -1 ] //: joint g57 (w13) @(495, 99) /w:[ -1 4 3 6 ] //: LED g15 (s) @(246,87) /sn:0 /R:2 /w:[ 0 ] /type:0 _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(175,110) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: DIP sb (w23) @(52,478) /R:1 /w:[ 1 ] /st:1 //: DIP func (w26) @(52,331) /R:1 /w:[ 0 ] /st:0 ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(121, 340) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: SWITCH g25 (a) @(56,62) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a) @(117, 62) /w:[ 2 -1 1 4 ] //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 //: DIP data_in (w25) @(52,208) /R:1 /w:[ 0 ] /st:11 //: LED g14 (co) @(245,122) /sn:0 /w:[ 0 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,73) /sn:0 /w:[ 9 1 3 ] //: LED g56 (w13) @(495,80) /sn:0 /w:[ 5 ] /type:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,68) /sn:0 /w:[ 0 3 1 ] /eb:0 _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,65) /sn:0 /w:[ 3 3 3 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] //: LED g54 (w1) @(394,57) /sn:0 /w:[ 5 ] /type:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: SWITCH data_select (w28) @(52,268) /w:[ 0 ] /st:0 //: comment g0 @(280,236) /anc:1 //: /line:"

TkGate ¤Ø¤è¤¦¤³¤½

" //: /line:"[Alpha Release]" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to " //: /line:" [released ]" //: /line:"" //: /line:"°Ê²¼¤Î¥ê¥ó¥¯¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢tkgate¤ò»È¤¨»Ï¤á¤è¤¦¡£" //: /line:"" //: /line:" * ¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ø" //: /line:"" //: /line:" * ÎãÂê²óÏ©¤Ø" //: /line:"" //: /line:" * ¿·µ¬²óÏ©¤òºîÀ®" //: /line:"" //: /line:" * ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó¤òÆɤ⤦ " //: /end //: SWITCH g26 (b) @(56,97) /sn:0 /w:[ 0 ] /st:1 _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] //: SWITCH g12 (w1) @(340,73) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b) @(111, 97) /w:[ -1 2 1 4 ] //: joint g33 (ci) @(177, 70) /w:[ 2 1 -1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>B[7:0](67/89) Ti1>A[7:0](21/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z = 1'b0; initial #100 forever begin Z = 1'b1; #100; Z = 1'b0; #100; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/index.v000644 001751 001751 00000003731 11140741567 021175 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(433,291) /sn:0 /R:14 //: /line:"TkGate¤Î¥á¥¤¥ó¤Î¥Ú¡¼¥¸¤ËÌá¤ë¡£" //: /end //: comment g0 @(434,49) /sn:0 /anc:1 //: /line:"" //: /end //: comment g18 @(10,10) /sn:0 /anc:1 //: /line:"

¥Á¥å¡¼¥È¥ê¥¢¥ë¤Î¾Ï¤Î°ìÍ÷ɽ:

" //: /line:"" //: /line:"

1. ²óÏ©¤ÎºîÀ®

- Get started by creating a simple circuit." //: /line:"" //: /line:"

2. ¥²¡¼¥È¤ÎÊÔ½¸

- The basics of editing gates." //: /line:"" //: /line:"

3. ¥ï¥¤¥ä¤ÎÊÔ½¸

- The basics of editing wires." //: /line:"" //: /line:"

4. ¥°¥ë¡¼¥×ÊÔ½¸¤Îµ¡Ç½

- Operate on groups of gates." //: /line:"" //: /line:"

5. ¥æ¡¼¥¶¡¦¥â¥¸¥å¡¼¥ë

- Using modules in your circuit." //: /line:"" //: /line:"

6. Advanced Editing Techniques

- Learn advanced editing tricks." //: /line:"" //: /line:"

7. Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó

- Simulate a circuit with" //: /line:" combinational logic." //: /line:"" //: /line:"

8. ½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó

- Simulate a circuit with" //: /line:" sequential logic." //: /line:"" //: /line:"

9. ¥Æ¥­¥¹¥ÈVerilog

- Create modules with textual Verilog descriptions." //: /line:"" //: /line:"

10. TkGate¤Î¥ª¥×¥·¥ç¥ó

- Customize TkGate to suit your tastes." //: /line:"" //: /line:"" //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/ja/tutorials/create.v000644 001751 001751 00000017273 11140741573 021334 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg w3; //: /sn:0 {0}(219,137)(154,137){1} reg w9; //: /sn:0 {0}(314,237)(213,237){1} //: {2}(211,235)(211,142)(219,142){3} //: {4}(209,237)(154,237){5} wire w8; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} wire w10; //: /sn:0 {0}(335,235)(345,235){1} //: enddecls //: comment g8 @(313,208) //: /line:"OR gate" //: /end //: joint g13 (w9) @(211, 237) /w:[ 1 2 4 -1 ] //: comment g1 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w3), .I1(w9), .Z(w8)); //: @(230,140) /sn:0 /w:[ 0 3 1 ] //: comment g6 @(115,104) //: /line:"Switches" //: /end //: comment g7 @(208,112) //: /line:"AND gate" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

ñ½ã¤Î²óÏ©¤ÎºîÀ®

" //: /line:"" //: /line:"In this chapter, we will walk through the steps of creating the simple circuit shown below." //: /end //: SWITCH g14 (w3) @(137,137) /sn:0 /w:[ 1 ] /st:0 _GGOR2 #(6) g0 (.I0(w8), .I1(w9), .Z(w10)); //: @(325,235) /sn:0 /w:[ 0 0 0 ] //: SWITCH g12 (w9) @(137,237) /sn:0 /w:[ 5 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(182,237)(182,237)(314,237){1} reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1} wire w7; //: /sn:0 {0}(335,235)(345,235){1} wire w0; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} //: enddecls _GGOR2 #(6) g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(325,235) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g3 (.I0(w2), .I1(w0), .Z(w5)); //: @(230,140) /sn:0 /w:[ 0 1 1 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /w:[ 0 ] /st:0 //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(537,46) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now make the final connection. Grab the lower input terminal of the AND gate" //: /line:"and drag it down near the wire between the lower switch and the OR gate. Release" //: /line:"the wire to create a joint." //: /line:"" //: /end //: comment g7 @(537,126) /sn:0 //: /line:"Hint: Joints are formed any" //: /line:"time the soldering iron is" //: /line:"active and you release the" //: /line:"wire in the middle of another" //: /line:"wire." //: /end //: SWITCH g5 (w2) @(137,137) /sn:0 /w:[ 1 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w2; //: /sn:0 {0}(240,140)(255,140){1} //: enddecls _GGAND2 #(6) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(230,140) /sn:0 /w:[ 1 1 0 ] //: frame g1 @(283,202) /sn:0 /wi:78 /ht:46 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now create an OR gate. Right click in the dashed line box then select" //: /line:"Make → Gate → OR from the popup menu." //: /end //: comment g0 @(532,85) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"o\" to create an OR gate." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(169,237){1} reg w2; //: /sn:0 {0}(154,137)(169,137){1} wire w7; //: /sn:0 {0}(240,140)(255,140){1} wire w4; //: /sn:0 {0}(204,137)(219,137){1} wire w3; //: /sn:0 {0}(335,235)(350,235){1} wire w0; //: /sn:0 {0}(299,232)(314,232){1} wire w1; //: /sn:0 {0}(299,237)(314,237){1} wire w5; //: /sn:0 {0}(204,142)(219,142){1} //: enddecls //: SWITCH g4 (w2) @(137,137) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGAND2 #(6) g3 (.I0(w4), .I1(w5), .Z(w7)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w1), .Z(w3)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(578,122) /sn:0 /anc:1 //: /line:"Hint: The soldering iron cursor will" //: /line:"show you when you have selected" //: /line:"a connectable wire end." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Finally, connect the wires. Begin by grabbing the end of the wire leading from one of the" //: /line:"switches with the left mouse button and drag it to the upper input terminal of the AND gate." //: /end //: comment g0 @(579,61) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(531,86) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"a\" to create an AND gate." //: /end //: frame g1 @(208,124) /sn:0 /wi:76 /ht:43 /tx:"" //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Start by creating an AND gate. Right click in the dashed line box then select" //: /line:"Make → Gate → AND from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(335,235)(350,235){1} wire w4; //: /sn:0 {0}(299,232)(314,232){1} wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w3; //: /sn:0 {0}(240,140)(255,140){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(299,237)(314,237){1} //: enddecls _GGOR2 #(6) g4 (.I0(w4), .I1(w5), .Z(w7)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g8 @(109,215) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" _GGAND2 #(6) g3 (.I0(w0), .I1(w1), .Z(w3)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g1 @(109,121) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Next create two switches. Right click in each of the two dashed line box then" //: /line:"select Make → I/O → Switch from the popup menu." //: /end //: comment g0 @(532,86) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"s\" to create a switch." //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/wire2.v000644 001751 001751 00000020645 10624605075 021120 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "edwire_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g4 @(16,548) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(549,50) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g9 @(23,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/gates.v000644 001751 001751 00000035500 11140741601 021155 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

" //: /line:"" //: /line:"This chapter will introduce some of the basic circuit editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(144,69) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(256,171)(271,171){1} wire w0; //: /sn:0 {0}(102,172)(117,172){1} wire w3; //: /sn:0 {0}(256,166)(271,166){1} wire w1; //: /sn:0 {0}(102,177)(117,177){1} wire w2; //: /sn:0 {0}(138,175)(153,175){1} wire w5; //: /sn:0 {0}(292,169)(307,169){1} //: enddecls //: comment g4 @(247,195) /sn:0 /anc:1 //: /line:"Anchored Gate" //: /end _GGOR2 #(6) g3 (.I0(w3), .I1(w4), .Z(w5)); //: @(282,169) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Anchoring)" //: /line:"" //: /line:"You can prevent a gate from being accidentally moved by selecting it and pressing" //: /line:"the button to set an anchor. You can remove an anchor with the button." //: /line:"Gates which have been anchored (e.g., the OR gate below) can not be moved until" //: /line:"you remove the anchor. Try moving the gates below." //: /line:"" //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(128,175) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(587,112) /sn:0 //: /line:"Hint: An alternate way to add or" //: /line:"remove an anchor on a gate is to" //: /line:"right click and change the anchor" //: /line:"flag in the popup menu." //: /end //: comment g5 @(81,195) /sn:0 /anc:1 //: /line:"Unanchored Gate" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Editing Gates

(Repositioning)" //: /line:"" //: /line:"To move a gate, select it with the tool and drag it to a new location. Try" //: /line:"it on the sample circuit below." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(39,221)(54,221){1} wire w7; //: /sn:0 {0}(41,265)(56,265){1} wire w16; //: /sn:0 {0}(154,267)(169,267){1} wire w14; //: /sn:0 {0}(169,222)(154,222){1} wire w19; //: /sn:0 {0}(169,277)(154,277){1} wire w15; //: /sn:0 {0}(154,262)(169,262){1} wire w4; //: /sn:0 {0}(39,218)(54,218){1} wire w0; //: /sn:0 {0}(37,166)(52,166){1} wire w3; //: /sn:0 {0}(39,214)(54,214){1} wire w21; //: /sn:0 {0}(152,167)(167,167){1} wire w20; //: /sn:0 {0}(41,274)(56,274){1} wire w23; //: /sn:0 {0}(188,169)(203,169){1} wire w1; //: /sn:0 {0}(37,171)(52,171){1} wire w18; //: /sn:0 {0}(190,269)(205,269){1} wire w8; //: /sn:0 {0}(41,268)(56,268){1} wire w17; //: /sn:0 {0}(169,272)(154,272){1} wire w22; //: /sn:0 {0}(152,172)(167,172){1} wire w12; //: /sn:0 {0}(154,217)(169,217){1} wire w11; //: /sn:0 {0}(154,212)(169,212){1} wire w2; //: /sn:0 {0}(73,169)(88,169){1} wire w10; //: /sn:0 {0}(41,271)(56,271){1} wire w13; //: /sn:0 {0}(190,217)(205,217){1} wire w5; //: /sn:0 {0}(75,218)(90,218){1} wire w9; //: /sn:0 {0}(77,270)(92,270){1} //: enddecls _GGAND4 #(10) g4 (.I0(w7), .I1(w8), .I2(w10), .I3(w20), .Z(w9)); //: @(67,270) /sn:0 /w:[ 1 1 1 1 0 ] //: comment g8 @(149,126) /sn:0 //: /line:"gates with" //: /line:"extender bars" //: /end _GGAND3 #(8) g3 (.I0(w3), .I1(w4), .I2(w6), .Z(w5)); //: @(65,218) /sn:0 /w:[ 1 1 1 0 ] //: comment g2 @(11,13) //: /line:"

Editing Gates

(Adding Inputs)" //: /line:"" //: /line:"Some gates (e.g., AND gates) can have a variable number of inputs or outputs. To add inputs (or" //: /line:"outputs) to these gates, select the gate and press the button. Also, some gates may have multiple styles" //: /line:"for adding ports that can be selected through the gate properties box. Try adding inputs to the gates below," //: /line:"or create a new gate and add inputs to it." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(63,169) /sn:0 /w:[ 1 1 0 ] _GGAND4 #(10) g6 (.I0(w15), .I1(w16), .I2(w17), .I3(w19), .Z(w18)); //: @(180,269) /sn:0 /w:[ 1 1 0 0 0 ] /eb:1 //: comment g7 @(26,127) /sn:0 //: /line:"gates without" //: /line:"extender bars" //: /end _GGAND2 #(6) g9 (.I0(w21), .I1(w22), .Z(w23)); //: @(178,169) /sn:0 /w:[ 1 1 0 ] /eb:1 _GGAND3 #(8) g5 (.I0(w11), .I1(w12), .I2(w14), .Z(w13)); //: @(180,217) /sn:0 /w:[ 1 1 0 0 ] /eb:1 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: frame g3 @(298,213) /sn:0 /wi:167 /ht:69 /tx:"This is a frame" //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Comments and Frames)" //: /line:"" //: /line:"There are two special \"gates\" that you can use for annotating your circuit specification: comments and frames." //: /line:"Neither of these \"gates\" has any effect on the simulation results." //: /line:"" //: /line:"Comments are blocks of text such as those used to construct this tutorial. Comments are created by right clicking" //: /line:"and selecting Make → Comment from the popup menu. When you create a comment, the properties box will" //: /line:"appear immediately allowing you to enter the text of the comment. Comments can contain limited html tags including links" //: /line:"to other circuit files, or short cuts to specific gates in your circuit." //: /line:"" //: /line:"Frames are annotated boxes for organzing groups of related circuit elements that don't warrant creating a new module. Open" //: /line:"the properties box by double clicking on an edge to set the annotation string. Click and drag on a corner to resize." //: /line:"" //: /end //: comment g1 @(72,233) /sn:0 //: /line:"This is a comment with" //: /line:"some bold text in it." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(118,149)(133,149){1} wire w1; //: /sn:0 {0}(118,154)(133,154){1} wire w2; //: /sn:0 {0}(154,152)(169,152){1} //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Rotation)" //: /line:"" //: /line:"The orientation of a gate can be changed by selecting it and pressing the button" //: /line:"(or Tab key) to rotate it counter-clockwise and the button (or Shift-Tab key) to" //: /line:"rotate it clockwise. Try it on the AND gate below." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(144,152) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(567,92) /sn:0 /anc:1 //: /line:"Hint: You can also use the " //: /line:"button to set the default orientation" //: /line:"for newly created gates." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Properties)" //: /line:"" //: /line:"You can also open the properties box of a gate by double clicking on it. Try" //: /line:"double clicking on some of the gates in the circuit below. Through the properties" //: /line:"box you can change the label of a gate and make the label visible or invisible" //: /line:"though the \"Hide Name\" property." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: comment g6 @(548,104) /sn:0 /anc:1 //: /line:"Hint: Many properties are gate-" //: /line:"specific. Try opening the property" //: /line:"boxes of different gate types to see" //: /line:"what proprties can be modified." //: /end _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Deletion)" //: /line:"" //: /line:"To delete a gate, select it with the tool and press the Delete key. Try it on the sample circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND4 #(.Diz(1)) (I0, I1, I2, I3, Z); output Z; input I0, I1, I2, I3; reg Z; assign #Diz Z = ( I0 & I1 & I2 & I3 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; reg Z; assign #Diz Z = ( I0 & I1 & I2 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/advanced.v000644 001751 001751 00000063627 11140741621 021634 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Advanced Editing Techniques

" //: /line:"" //: /line:"In this chapter you will learn some additional techniques to be more efficient at editing circuits" //: /line:"in TkGate." //: /end //: comment g0 @(150,93) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Now try the same thing again, but this time drop the inverter input closer to the AND gate output" //: /line:"away from the joint. This time a new joint is automatically created." //: /line:"" //: /end _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(162,164)(202,164)(202,147)(227,147)(227,159)(252,159)(252,209)(178,209)(178,179){1} wire w4; //: /sn:0 {0}(131,166)(141,166){1} wire w0; //: /sn:0 {0}(131,161)(141,161){1} //: enddecls _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(152,164) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Loop Deletion)" //: /line:"" //: /line:"Grab the endpoint of the XOR output wire in the circuit below. Drag it up until it crosses the" //: /line:"horizontal segment next to the gate and release it. TkGate will automatically remove the loop." //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w46; //: /sn:0 {0}(421,254)(374,254)(374,196){1} //: {2}(376,194)(397,194)(397,127)(422,127){3} //: {4}(372,194)(339,194){5} wire w0; //: /sn:0 {0}(67,208)(82,208){1} wire w43; //: /sn:0 {0}(308,191)(318,191){1} wire w1; //: /sn:0 {0}(67,213)(82,213){1} wire w2; //: /sn:0 {0}(103,211)(130,211)(130,135){1} wire w44; //: /sn:0 {0}(308,196)(318,196){1} wire w48; //: /sn:0 {0}(438,127)(448,127){1} wire w47; //: /sn:0 {0}(437,254)(447,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(93,211) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) hari (.I0(w43), .I1(w44), .Z(w46)); //: @(329,194) /sn:0 /anc:1 /w:[ 1 1 5 ] /eb:0 //: joint g50 (w46) @(374, 194) /anc:1 /w:[ 2 -1 4 1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Rerouting)" //: /line:"" //: /line:"TkGate will automatically reroute wires that do not leave a gate or joint on the correct" //: /line:"direction. Try grabbing the wire indicated by the arrow in the two examples below and drag" //: /line:"them to the left. In the XOR gate example, two new wire segments are added. In the joint" //: /line:"example, one new segment is added, and the position on the joint is adjusted." //: /line:"" //: /end _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(427,254) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g0 @(405,147) /sn:0 //: /line:"⇐" //: /end //: comment g12 @(141,164) /sn:0 //: /line:"⇐" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(428,127) /sn:0 /anc:1 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(316,199)(316,214){1} wire w6; //: /sn:0 {0}(85,173)(100,173){1} wire w7; //: /sn:0 {0}(85,178)(100,178){1} wire w16; //: /sn:0 {0}(80,237)(95,237){1} wire w14; //: /sn:0 {0}(107,216)(122,216){1} wire w19; //: /sn:0 {0}(85,256)(100,256){1} wire w15; //: /sn:0 {0}(80,232)(95,232){1} wire w4; //: /sn:0 {0}(99,157)(114,157){1} wire w38; //: /sn:0 {0}(335,190)(335,205){1} wire w3; //: /sn:0 {0}(99,152)(114,152){1} wire w0; //: /sn:0 {0}(91,132)(106,132){1} wire w37; //: /sn:0 {0}(333,154)(333,169){1} wire w34; //: /sn:0 {0}(295,168)(295,183){1} wire w21; //: /sn:0 {0}(359,164)(359,179){1} wire w31; //: /sn:0 {0}(314,163)(314,178){1} wire w28; //: /sn:0 {0}(394,182)(394,197){1} wire w41; //: /sn:0 {0}(416,210)(416,225){1} wire w36; //: /sn:0 {0}(338,154)(338,169){1} wire w24; //: /sn:0 {0}(378,168)(378,183){1} wire w23; //: /sn:0 {0}(356,200)(356,215){1} wire w20; //: /sn:0 {0}(121,254)(136,254){1} wire w1; //: /sn:0 {0}(91,137)(106,137){1} wire w25; //: /sn:0 {0}(373,168)(373,183){1} wire w40; //: /sn:0 {0}(414,174)(414,189){1} wire w35; //: /sn:0 {0}(297,204)(297,219){1} wire w18; //: /sn:0 {0}(85,251)(100,251){1} wire w8; //: /sn:0 {0}(121,176)(136,176){1} wire w30; //: /sn:0 {0}(319,163)(319,178){1} wire w22; //: /sn:0 {0}(354,164)(354,179){1} wire w17; //: /sn:0 {0}(116,235)(131,235){1} wire w12; //: /sn:0 {0}(71,213)(86,213){1} wire w11; //: /sn:0 {0}(117,195)(132,195){1} wire w2; //: /sn:0 {0}(127,135)(142,135){1} wire w10; //: /sn:0 {0}(81,197)(96,197){1} wire w27; //: /sn:0 {0}(399,182)(399,197){1} wire w13; //: /sn:0 {0}(71,218)(86,218){1} wire w33; //: /sn:0 {0}(300,168)(300,183){1} wire w5; //: /sn:0 {0}(135,155)(150,155){1} wire w29; //: /sn:0 {0}(396,218)(396,233){1} wire w9; //: /sn:0 {0}(81,192)(96,192){1} wire w39; //: /sn:0 {0}(419,174)(419,189){1} wire w26; //: /sn:0 {0}(375,204)(375,219){1} //: enddecls _GGAND2 #(6) g8 (.I0(w21), .I1(w22), .Z(w23)); //: @(356,190) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g13 (.I0(w33), .I1(w34), .Z(w35)); //: @(297,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w9), .I1(w10), .Z(w11)); //: @(107,195) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g2 (.I0(w6), .I1(w7), .Z(w8)); //: @(111,176) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g1 (.I0(w3), .I1(w4), .Z(w5)); //: @(125,155) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g11 (.I0(w27), .I1(w28), .Z(w29)); //: @(396,208) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g10 (.I0(w24), .I1(w25), .Z(w26)); //: @(375,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g6 (.I0(w15), .I1(w16), .Z(w17)); //: @(106,235) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g7 (.I0(w18), .I1(w19), .Z(w20)); //: @(111,254) /sn:0 /w:[ 1 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gate Alignment)" //: /line:"" //: /line:"You can align a group of gates by selecting them and then pressing the to align them vertically," //: /line:"and to align them horizontally. Try it on the groups of gates below." //: /end _GGAND2 #(6) g15 (.I0(w39), .I1(w40), .Z(w41)); //: @(416,200) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g14 (.I0(w36), .I1(w37), .Z(w38)); //: @(335,180) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g5 (.I0(w12), .I1(w13), .Z(w14)); //: @(97,216) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(117,135) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g12 (.I0(w30), .I1(w31), .Z(w32)); //: @(316,189) /sn:0 /R:3 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(85,137)(95,137){1} wire w19; //: /sn:0 {0}(322,140)(332,140){1} wire w21; //: /sn:0 {0}(321,242)(331,242){1} wire w20; //: /sn:0 {0}(305,242)(288,242)(288,140)(306,140){1} wire w40; //: /sn:0 {0}(193,243)(203,243){1} wire w18; //: /sn:0 {0}(162,245)(172,245){1} wire w17; //: /sn:0 {0}(172,240)(153,240)(153,140)(116,140){1} wire w9; //: /sn:0 {0}(85,142)(95,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(183,243) /sn:0 /anc:1 /w:[ 0 1 0 ] /eb:0 //: comment g1 @(120,178) /sn:0 /anc:1 //: /line:"⇒" //: /end _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(312,140) /sn:0 /anc:1 /w:[ 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Wire Segments)" //: /line:"" //: /line:"Sometime there may not be a free end of two wires you want to connect. Right click on the" //: /line:"wire connected to the AND gate output at the position indicated by the arrow. Select the" //: /line:"Add Wire Segment option from the popup menu. You can now connect" //: /line:"the newly created wire to the buffer inputs." //: /line:"" //: /end _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(106,140) /sn:0 /anc:1 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(311,242) /sn:0 /anc:1 /w:[ 0 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Select the tool and drag the input of the inverter in the circuit below. Drag the input close" //: /line:"to the joint in the middle of the AND gate output and release it. The wire should attach itself to" //: /line:"the joint." //: /line:"" //: /end _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] wire w16; //: /sn:0 {0}(313,266)(323,266){1} wire w14; //: /sn:0 {0}(292,263)(226,263)(226,200)(245,200)(245,140)(178,140){1} wire w15; //: /sn:0 {0}(282,268)(292,268){1} wire w12; //: /sn:0 {0}(147,142)(157,142){1} wire w11; //: /sn:0 {0}(147,137)(157,137){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(303,266) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(168,140) /sn:0 /w:[ 1 1 1 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gravity)" //: /line:"" //: /line:"Click on the wire indicated by the arrow in the circuit below and drag it until it is nearly" //: /line:"alligned with the other vertical segment. When you release the wire, \"gravity\" will cause" //: /line:"the two vertical segments to snap together into a single segment." //: /line:"" //: /end //: comment g0 @(562,122) /sn:0 //: /line:"Hint: You can disable the automatic" //: /line:"cleanup features in wire editing by" //: /line:"holding the Alt key while moving wires." //: /end //: comment g12 @(252,158) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(325,245)(373,245){1} //: {2}(377,245)(468,245){3} //: {4}(375,243)(375,163)(436,163){5} wire w7; //: /sn:0 {0}(421,158)(436,158){1} wire w4; //: /sn:0 {0}(289,247)(304,247){1} wire w0; //: /sn:0 {0}(289,242)(304,242){1} wire w3; //: /sn:0 {0}(61,247)(108,247){1} //: {2}(112,247)(199,247){3} //: {4}(110,245)(110,161)(169,161){5} wire w1; //: /sn:0 {0}(30,244)(40,244){1} wire w8; //: /sn:0 {0}(190,159)(200,159){1} wire w2; //: /sn:0 {0}(30,249)(40,249){1} wire w10; //: /sn:0 {0}(457,161)(472,161){1} wire w5; //: /sn:0 {0}(159,156)(169,156){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g3 (w3) @(110, 247) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(180,159) /sn:0 /anc:1 /w:[ 1 5 0 ] /eb:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w4), .Z(w6)); //: @(315,245) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g11 @(363,264) /sn:0 //: /line:"OR Gate Circuit" //: /end //: comment g10 @(70,271) /sn:0 //: /line:"AND Gate Circuit" //: /end //: joint g6 (w6) @(375, 245) /w:[ 2 4 1 -1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Wire Cleanup)" //: /line:"" //: /line:"Select the tool and cut the wire at the position indicated by the arrow in the AND Gate" //: /line:"Circuit. TkGate will automatically remove the wire joint. Now cut the wire at the position indicated" //: /line:"by the arrow in the OR Gate Circuit. The free wire end is automatically deleted." //: /line:"" //: /end //: comment g7 @(413,213) /sn:0 /anc:1 //: /line:"⇓" //: /end _GGOR2 #(6) g5 (.I0(w7), .I1(w6), .Z(w10)); //: @(447,161) /sn:0 /anc:1 /w:[ 1 5 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(51,247) /sn:0 /anc:1 /w:[ 1 1 0 ] /eb:0 //: comment g12 @(123,184) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] reg ithaca; //: {0}(18:215,183)(259,183){1} //: {2}(263,183)(271,183){3} //: {4}(261,185)(261,238)(278,238){5} reg crete; //: {0}(7:215,136)(359,136)(359,189){1} //: {2}(361,191)(416,191){3} //: {4}(359,193)(359,203){5} reg toledo; //: {0}(-21:213,243)(254,243){1} //: {2}(258,243)(278,243){3} //: {4}(256,241)(256,188)(271,188){5} wire styx; //: {0}(99:355,275)(355,295){1} wire athens; //: {0}(416,186)(356,186){1} //: {2}(71:352,186)(292,186){3} //: {4}(354,188)(354,203){5} wire pheneos; //: {0}(76:357,224)(357,254){1} wire olympus; //: {0}(-15:437,189)(506,189){1} wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: LED g37 (olympus) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGXOR2 #(8) Athena (.I0(ithaca), .I1(toledo), .Z(athens)); //: @(282,186) /w:[ 3 5 3 ] /eb:0 _GGNAND2 #(4) Hermes (.I0(athens), .I1(crete), .Z(pheneos)); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0 _GGNAND2 #(4) Hades (.I0(delphi), .I1(pheneos), .Z(styx)); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0 _GGXOR2 #(8) Zeus (.I0(athens), .I1(crete), .Z(olympus)); //: @(427,189) /w:[ 0 3 0 ] /eb:0 //: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Search)" //: /line:"" //: /line:"You can search your circuit for a wire or gate with a specific name by using the search tool. Click" //: /line:"on the tool to open it. The list of matches will by dynamically updated as you type the target" //: /line:"string. Double click on an entry in the Search Results to go to that object. Try using the search" //: /line:"tool to search for some of the wire and gate names in the circuit below." //: /line:"" //: /end //: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ] //: SWITCH Thesus (crete) @(198,136) /w:[ 0 ] /st:0 //: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 _GGNAND2 #(4) Apollo (.I0(ithaca), .I1(toledo), .Z(delphi)); //: @(289,241) /w:[ 5 3 0 ] /eb:0 //: SWITCH Odyseus (ithaca) @(198,183) /w:[ 0 ] /st:0 //: comment g0 @(588,148) /sn:0 //: /line:"Hint: The search tool will look" //: /line:"in all modules of your circuit for" //: /line:"the target string. Try searching for" //: /line:"a gate named \"hari\"." //: /end //: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ] //: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin OLD module OLD(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(476,150)(516,150)(516,133)(541,133)(541,145)(566,145)(566,195)(492,195)(492,165){1} wire w32; //: /sn:0 {0}(624,293)(634,293){1} wire w7; //: /sn:0 {0}(470,428)(480,428){1} wire w46; //: /sn:0 {0}(724,568)(681,568)(681,559){1} //: {2}(683,557)(697,557)(697,519)(722,519){3} //: {4}(679,557)(646,557){5} wire w14; //: /sn:0 {0}(522,98)(512,98)(512,79)(531,79)(531,46)(478,46){1} wire w16; //: /sn:0 {0}(543,101)(553,101){1} wire w4; //: /sn:0 {0}(445,152)(455,152){1} wire w15; //: /sn:0 {0}(512,103)(522,103){1} wire w19; //: /sn:0 {0}(604,430)(614,430){1} wire w38; //: /sn:0 {0}(747,392)(757,392){1} wire w0; //: /sn:0 {0}(445,147)(455,147){1} wire w3; //: /sn:0 {0}(475,285)(516,285){1} //: {2}(520,285)(573,285){3} //: {4}(518,283)(518,239)(548,239){5} wire w37; //: /sn:0 {0}(721,392)(731,392){1} wire w34; //: /sn:0 {0}(744,361)(754,361){1} wire w43; //: /sn:0 {0}(615,554)(625,554){1} wire w21; //: /sn:0 {0}(604,468)(614,468){1} wire w31; //: /sn:0 {0}(624,288)(634,288){1} wire w28; //: /sn:0 {0}(655,291)(696,291){1} //: {2}(700,291)(753,291){3} //: {4}(698,289)(698,245)(728,245){5} wire w24; //: /sn:0 {0}(547,360)(524,360){1} //: {2}(522,358)(522,329)(548,329){3} //: {4}(520,360)(482,360){5} wire w20; //: /sn:0 {0}(588,468)(576,468)(576,430)(588,430){1} wire w36; //: /sn:0 {0}(632,363)(642,363){1} wire w41; //: /sn:0 {0}(492,556)(502,556){1} wire w23; //: /sn:0 {0}(537,388)(547,388){1} wire w1; //: /sn:0 {0}(444,282)(454,282){1} wire w25; //: /sn:0 {0}(564,329)(574,329){1} wire w18; //: /sn:0 {0}(523,477)(533,477){1} wire w40; //: /sn:0 {0}(554,475)(564,475){1} wire w8; //: /sn:0 {0}(569,237)(579,237){1} wire w35; //: /sn:0 {0}(632,358)(642,358){1} wire w30; //: /sn:0 {0}(749,243)(759,243){1} wire w17; //: /sn:0 {0}(533,472)(517,472)(517,431)(501,431){1} wire w22; //: /sn:0 {0}(451,362)(461,362){1} wire w11; //: /sn:0 {0}(447,43)(457,43){1} wire w12; //: /sn:0 {0}(447,48)(457,48){1} wire w44; //: /sn:0 {0}(615,559)(625,559){1} wire w2; //: /sn:0 {0}(444,287)(454,287){1} wire w10; //: /sn:0 {0}(451,357)(461,357){1} wire w13; //: /sn:0 {0}(492,551)(502,551){1} wire w27; //: /sn:0 {0}(563,388)(573,388){1} wire w33; //: /sn:0 {0}(728,361)(705,361){1} //: {2}(703,359)(703,330)(729,330){3} //: {4}(701,361)(663,361){5} wire w5; //: /sn:0 {0}(538,234)(548,234){1} wire w48; //: /sn:0 {0}(738,519)(748,519){1} wire w29; //: /sn:0 {0}(718,240)(728,240){1} wire w47; //: /sn:0 {0}(740,568)(750,568){1} wire w42; //: /sn:0 {0}(523,554)(541,554)(541,518){1} wire w9; //: /sn:0 {0}(470,433)(480,433){1} wire w26; //: /sn:0 {0}(563,360)(573,360){1} wire w39; //: /sn:0 {0}(745,330)(755,330){1} //: enddecls _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(466,150) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g4 @(10,552) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(544,475) /sn:0 /w:[ 0 1 0 ] /eb:0 //: joint g3 (w3) @(518, 285) /w:[ 2 4 1 -1 ] //: frame g34 @(437,317) /sn:0 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g37 (w33) @(703, 361) /w:[ 1 2 4 -1 ] //: frame g51 @(442,505) /sn:0 /wi:145 /ht:74 /tx:"Fig. 6a" _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(559,237) /sn:0 /w:[ 1 5 0 ] /eb:0 //: comment g1 @(542,55) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(533,101) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(468,46) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(553,360) /sn:0 /w:[ 0 0 ] //: joint g50 (w46) @(681, 557) /w:[ 2 -1 4 1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(594,430) /sn:0 /w:[ 1 0 ] //: joint g27 (w24) @(522, 360) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(739,243) /sn:0 /w:[ 1 5 0 ] /eb:0 _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(653,361) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(698, 291) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(513,554) /sn:0 /w:[ 1 1 0 ] /eb:0 //: frame g43 @(617,222) /sn:0 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(730,568) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(472,360) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(553,388) /sn:0 /w:[ 1 0 ] //: frame g42 @(437,221) /sn:0 /wi:163 /ht:83 /tx:"Fig. 3a" //: frame g52 @(597,507) /sn:0 /wi:189 /ht:73 /tx:"Fig. 6b" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(491,431) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(737,392) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(636,557) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g24 @(485,442) /sn:0 //: /line:"--->" //: /end _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(734,361) /sn:0 /w:[ 0 0 ] _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(594,468) /sn:0 /w:[ 0 0 ] //: frame g41 @(436,127) /sn:0 /wi:141 /ht:77 /tx:"Fig. 2" //: frame g40 @(434,30) /sn:0 /wi:147 /ht:86 /tx:"Fig. 1" _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(465,285) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(554,329) /sn:0 /w:[ 3 0 ] //: frame g35 @(618,318) /sn:0 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(735,330) /sn:0 /w:[ 3 0 ] //: frame g46 @(440,416) /sn:0 /wi:190 /ht:75 /tx:"Fig. 5" //: comment g30 @(723,257) /sn:0 //: /line:"|" //: /line:"v" //: /end _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(645,291) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(728,519) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/options.v000644 001751 001751 00000004712 11140741644 021555 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "options.v" //: property discardChanges = 1 //: require "tty" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(219,134) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

" //: /line:"" //: /line:"This chapter introduces some of the options that can be customized in TkGate. Your option settings" //: /line:"are stored in a file named \".tkgate2-preferences\" in your home directory." //: /line:"" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(134,181) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your key beinding style)" //: /line:"" //: /line:"You can the basic key-binding style that you would like to use on the Interface tab of the options dialog" //: /line:"box. Currently you can choose between \"emacs\"-style and \"Windows\"-style. Chosing one of these" //: /line:"options will make key bindings for operations such as cut/paste similar to either emacs or Windows," //: /line:"although key bindings for gate creation operations will remain the same." //: /end //: comment g0 @(10,310) /sn:0 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(116,149) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your personal identification)" //: /line:"" //: /line:"To set your TkGate options, open the options dilaog box by selecting File → Options from the" //: /line:"main menu. Enter your site name and user name in the \"Identity\" dialog box. The values you enter" //: /line:"here will be used on any printed output from TkGate." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/ja/tutorials/combinational1.v000644 001751 001751 00000001534 11140741630 022754 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

" //: /line:"" //: /line:"TkGate uses a Verilog-based discrete event simulator to simulate your circuit description. In this" //: /line:"chapter the basics needed to simulate a combinational circuit will be presented." //: /end //: comment g0 @(191,165) /sn:0 /anc:1 //: /line:"" //: /end //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/ja/tutorials/sequential1.v000644 001751 001751 00000001511 11140741635 022307 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "euc-jp" //: property locale = "ja" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

" //: /line:"" //: /line:"This chapter builds on the previous chapter about simulating combinational circuits and introduces" //: /line:"simulator features that are useful for simulating sequential circuits." //: /end //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(208,188) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/ja/tutorials/combinational3.v000644 001751 001751 00000007513 10624605075 022771 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:140,305)(154,305){1} //: {2}(158,305)(176,305){3} //: {4}(180,305)(228,305){5} //: {6}(178,303)(178,242)(223,242){7} //: {8}(156,303)(156,293){9} reg A; //: {0}(223,237)(191,237){1} //: {2}(189,235)(-86:189,217)(159,217){3} //: {4}(157,215)(157,204){5} //: {6}(155,217)(142,217){7} //: {8}(189,239)(189,300)(228,300){9} reg Cin; //: {0}(258,202)(278,202){1} //: {2}(280,200)(280,191){3} //: {4}(48:280,204)(280,233){5} //: {6}(282,235)(320,235){7} //: {8}(280,237)(280,261){9} wire w6; //: /sn:0 {0}(321,303)(249,303){1} wire w0; //: /sn:0 {0}(321,298)(278,298)(278,282){1} wire w1; //: /sn:0 {0}(320,240)(277,240){1} //: {2}(273,240)(244,240){3} //: {4}(275,242)(275,261){5} wire C; //: {0}(-21:390,210)(390,301)(342,301){1} wire S; //: {0}(341,238)(-39:360,238)(360,210){1} //: enddecls _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(234,240) /sn:0 /w:[ 0 7 3 ] _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(332,301) /sn:0 /w:[ 0 0 1 ] //: SWITCH g3 (Cin) @(241,202) /sn:0 /w:[ 0 ] /st:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(setting probes)" //: /line:"" //: /line:"Press the \" Simulate\" tab again, to enter simulation mode. This time right click on a wire (e.g., the" //: /line:"one labeled \"S\") and slect \"Add/Delete Probe\" from the popup menu. The will set a probe on that" //: /line:"wire and bring up the logic analyzer window. Set probes on some more wires, then unpause the" //: /line:"simulator by pressing . Click on the switches to change their state and observe how the logic" //: /line:"analyzer is updated." //: /end _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(239,303) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(123,305) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(275, 240) /w:[ 1 -1 2 4 ] //: joint g10 (Cin) @(280, 235) /w:[ 6 5 -1 8 ] //: LED g28 (A) @(157,197) /sn:0 /w:[ 5 ] /type:0 //: joint g27 (Cin) @(280, 202) /w:[ -1 2 1 4 ] //: joint g6 (B) @(178, 305) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(331,238) /sn:0 /w:[ 7 0 0 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(278,272) /sn:0 /R:3 /w:[ 5 9 1 ] //: comment g15 @(585,254) /sn:0 /anc:1 //: /line:"Hint: Normally, TkGate will simulate" //: /line:"combinational circuits until all signals" //: /line:"have reached a steady state. You can" //: /line:"hit the space bar to advance the" //: /line:"simulator by one time unit." //: /end //: joint g31 (A) @(157, 217) /w:[ 3 4 6 -1 ] //: LED g25 (C) @(390,203) /sn:0 /w:[ 0 ] /type:0 //: LED g29 (B) @(156,286) /sn:0 /w:[ 9 ] /type:0 //: joint g5 (A) @(189, 237) /w:[ 1 2 -1 8 ] //: comment g14 @(583,172) /sn:0 /anc:1 //: /line:"Hint: In addition to using probes," //: /line:"you can also see the value of a net" //: /line:"by clicking and holding the mouse" //: /line:"button down for a few seconds." //: /end //: SWITCH g0 (A) @(125,217) /sn:0 /w:[ 7 ] /st:0 //: LED g26 (Cin) @(280,184) /sn:0 /w:[ 3 ] /type:0 //: LED g18 (S) @(360,203) /sn:0 /w:[ 1 ] /type:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (B) @(156, 305) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/combinational5.v000644 001751 001751 00000015065 10624605075 022774 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(the instance hierarchy)" //: /line:"" //: /line:"While the simulator is active, the hierarchical module list displays the hierarchy by instance" //: /line:"rather than by module. This is because the state (i.e., net values) for each instance of a module" //: /line:"in the hierarcy may be different. Invoke and unpause the simulation for the circuit below, then" //: /line:"try examining the nets in different instances of the ADD1 module. Double click on \"g0<ADD1>\"," //: /line:"\"g1<ADD1>\", etc. in the the hierarchical list box to go to each instance." //: /line:"" //: /end //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(580,147) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: comment g7 @(581,227) /sn:0 /anc:1 //: /line:"Hint: You can also navigate to modules" //: /line:"by right clicking and select Open" //: /line:"from the popup menu." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>A(12/50) Li1>B(34/50) Bo0interface describes the external" //: /line:" appearance of a module including the size of the box and" //: /line:" the positions of the ports on it. TkGate supports \"block\"" //: /line:" interfaces and \"symbol\" interfaces." //: /line:" " //: /line:" * The definition describes the internal" //: /line:" logic that the module implements. TkGate supports \"netlist\"" //: /line:" and \"HDL\" modules." //: /line:"" //: /end //: comment g2 @(10,65) /sn:0 /anc:1 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

" //: /line:"" //: /line:"In this chapter, you will learn how to create, edit and manage modules." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(258,177)(273,177){1} wire w0; //: /sn:0 {0}(200,161)(185,161){1} wire w3; //: /sn:0 {0}(258,161)(273,161){1} wire w1; //: /sn:0 {0}(200,177)(185,177){1} wire w2; //: /sn:0 {0}(200,192)(185,192){1} wire w5; //: /sn:0 {0}(258,193)(273,193){1} //: enddecls bar g4 (.C(w2), .B(w1), .A(w0), .Z(w5), .Y(w4), .X(w3)); //: @(201, 145) /sz:(56, 72) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Ro0<0 Ro1<0 Ro2<0 ] //: comment g3 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(editing module definitions)" //: /line:"" //: /line:"To edit the definition of a module you have created, double click on its name in the module name" //: /line:"tree or list view. Alternatively you can right click on an instance of the module and select" //: /line:"Open from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g4 @(576,89) /sn:0 /anc:1 //: /line:"Hint: The pages in this tutorial" //: /line:"are actually modules with the" //: /line:"names PAGE1, PAGE2, etc." //: /end //: comment g3 @(23,72) /sn:0 /anc:1 //: /line:" Top-level or root module." //: /line:"" //: /line:" Netlist module." //: /line:"" //: /line:" Verilog HDL module." //: /line:"" //: /line:" Locked netlist module." //: /line:"" //: /line:" Locked Verilog HDL module." //: /line:"" //: /line:" Container for unused modules." //: /line:"" //: /end //: comment g2 @(257,69) /anc:1 //: /line:" Library module." //: /line:"" //: /line:" Container for all libraries." //: /line:"" //: /line:" Container for a single library." //: /line:"" //: /line:" Use of an undefined module." //: /line:"" //: /line:" Recursive inclusion of a module." //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(module list symbols)" //: /line:"" //: /line:"The following symbols are used in the module tree and list view:" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(40, 40) /bd:[ ] input [7:0] B; //: /sn:0 {0}(#:342,147)(342,184){1} //: {2}(344,186)(367,186){3} //: {4}(371,186)(425,186)(425,258){5} //: {6}(369,188)(369,261){7} //: {8}(342,188)(342,258){9} input [1:0] F; //: /sn:0 {0}(#:343,353)(214,353){1} input [7:0] A; //: /sn:0 {0}(#:265,147)(265,215){1} //: {2}(267,217)(345,217){3} //: {4}(349,217)(372,217){5} //: {6}(376,217)(457,217)(457,258){7} //: {8}(374,219)(374,261){9} //: {10}(347,219)(347,258){11} //: {12}(265,219)(265,322)(348,322)(348,337){13} supply0 w0; //: /sn:0 {0}(491,295)(491,272)(465,272){1} output [7:0] Z; //: /sn:0 {0}(#:366,404)(366,366){1} wire [7:0] w14; //: /sn:0 {0}(#:345,279)(345,310)(360,310)(360,337){1} wire w4; //: /sn:0 {0}(417,272)(407,272){1} wire [7:0] w11; //: /sn:0 {0}(#:372,282)(372,337){1} wire [7:0] w10; //: /sn:0 {0}(#:384,337)(384,307)(441,307)(441,287){1} //: enddecls //: joint g8 (A) @(347, 217) /w:[ 4 -1 3 10 ] _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4)); //: @(441,274) /sn:0 /w:[ 5 7 1 1 0 ] //: GROUND g13 (w0) @(491,301) /sn:0 /w:[ 0 ] //: IN g3 (F) @(212,353) /sn:0 /w:[ 1 ] //: IN g2 (A) @(265,145) /sn:0 /R:3 /w:[ 0 ] //: IN g1 (B) @(342,145) /sn:0 /R:3 /w:[ 0 ] //: joint g11 (B) @(369, 186) /w:[ 4 -1 3 6 ] //: joint g10 (A) @(374, 217) /w:[ 6 -1 5 8 ] _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11)); //: @(372,272) /sn:0 /R:3 /w:[ 7 9 0 ] /eb:0 //: joint g9 (A) @(265, 217) /w:[ 2 1 -1 12 ] _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14)); //: @(345,269) /sn:0 /R:3 /w:[ 9 11 0 ] /eb:0 //: OUT g5 (Z) @(366,401) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z)); //: @(366,353) /sn:0 /w:[ 13 1 1 0 0 1 ] /ss:0 /do:0 //: joint g12 (B) @(342, 186) /w:[ 2 1 -1 8 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(Z2, I3, Z1, I1, I2, Z3); //: interface /sz:(41, 40) /bd:[ ] input I2; //: /sn:0 {0}(245,200)(275,200){1} //: {2}(277,198)(277,153)(292,153){3} //: {4}(277,202)(277,248)(348,248){5} output Z3; //: /sn:0 {0}(369,251)(448,251){1} input I1; //: /sn:0 {0}(292,148)(278,148)(278,128)(246,128){1} output Z2; //: /sn:0 {0}(392,156)(380,156)(380,184){1} //: {2}(382,186)(448,186){3} //: {4}(378,186)(369,186){5} output Z1; //: /sn:0 {0}(448,154)(413,154){1} input I3; //: /sn:0 {0}(348,188)(296,188)(296,251){1} //: {2}(298,253)(348,253){3} //: {4}(294,253)(245,253){5} wire w0; //: /sn:0 {0}(348,183)(338,183)(338,153){1} //: {2}(340,151)(392,151){3} //: {4}(336,151)(313,151){5} //: enddecls //: OUT g4 (Z2) @(445,186) /sn:0 /w:[ 3 ] _GGAND2 #(6) g8 (.I0(I2), .I1(I3), .Z(Z3)); //: @(359,251) /sn:0 /w:[ 5 3 0 ] /eb:0 //: joint g13 (w0) @(338, 151) /w:[ 2 -1 4 1 ] //: IN g2 (I3) @(243,253) /sn:0 /w:[ 5 ] //: OUT g1 (Z1) @(445,154) /sn:0 /w:[ 0 ] _GGAND2 #(6) g11 (.I0(w0), .I1(Z2), .Z(Z1)); //: @(403,154) /sn:0 /w:[ 3 0 1 ] /eb:0 //: comment g16 @(585,127) /sn:0 //: /line:"Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end //: joint g10 (I2) @(277, 200) /w:[ -1 2 1 4 ] //: IN g19 (I1) @(244,128) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g6 (.I0(I1), .I1(I2), .Z(w0)); //: @(303,151) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(I3), .Z(Z2)); //: @(359,186) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (I3) @(296, 253) /w:[ 2 1 4 -1 ] //: comment g15 @(22,25) //: /line:"This is the definition for module \"foo\"." //: /end //: IN g5 (I2) @(243,200) /sn:0 /w:[ 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: joint g23 (Z2) @(380, 186) /w:[ 2 1 4 -1 ] //: OUT g12 (Z3) @(445,251) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(573,160) /sn:0 /anc:1 //: /line:"Hint: If you are unable to modify a" //: /line:"module interface, right click on it," //: /line:"select Module Properties..., then" //: /line:"unset the interface protection options" //: /line:"in the dialog box." //: /end foo g2 (); //: @(208, 163) /sz:(40, 40) /sn:0 /p:[ ] //: comment g1 @(9,13) //: /line:"

Using Modules

(manual interface generation)" //: /line:"" //: /line:"You can also manually create and edit the interface of a module:" //: /line:" * To change the size of the interface, left-click on an edge or corner and drag it with the mouse." //: /line:" * To add a port, right click on an edge and choose the port type to create from the popup menu." //: /line:" * To delete a port, select the tool and cut the wire off of the module." //: /line:" * To edit port properties, double click on the port with the tool." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire [7:0] w3; //: /sn:0 {0}(#:329,194)(314,194){1} wire [1:0] w0; //: /sn:0 {0}(#:257,226)(272,226){1} wire [7:0] w1; //: /sn:0 {0}(#:257,210)(272,210){1} wire [7:0] w2; //: /sn:0 {0}(#:257,194)(272,194){1} //: enddecls ALU g3 (.A(w2), .B(w1), .F(w0), .Z(w3)); //: @(273, 178) /sz:(40, 64) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Ro0<1 ] //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(updating the default interface)" //: /line:"" //: /line:"Module interfaces constructed in Edit mode, apply only to the specific instance that you created." //: /line:"To make an interface the default for newly created instance of modules of that type, right click" //: /line:"on an interface and select Interface → Set. Try setting the interface to each of the two instances of" //: /line:"ALU modules below, then try creating new ALU modules by dragging them from the module list." //: /end ALU g0 (); //: @(130, 184) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(automatic interface generation)" //: /line:"" //: /line:"The interface of a module includes the size and shape of the box as well as the location and names" //: /line:"of the ports. The easiest way to create an interface is to use automatic generation. Automatic" //: /line:"generation uses the ports referenced in the definition to create the interface. To automatically" //: /line:"create an interface for the \"bar\" module, first click on the module list tab , then right click on \"bar\"" //: /line:"and select Interface → Auto Generate... Now left click and drag the bar module onto the canvas to see" //: /line:"the new interface." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) //: /line:"

Using Modules

(creating module definitions)" //: /line:"" //: /line:"To create a new module, press the button. Enter the name for the new module" //: /line:"and select whether you wish to create it as a \"netlist\" (graphical) module or an" //: /line:"HDL (textual) module. Try creating a new module named \"CPU\"." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(545,102) /sn:0 //: /line:"Hint: You can also drag and drop" //: /line:"module instance from the tree view," //: /line:"but it is easier to use the list view" //: /line:"since that view gives you a straight" //: /line:"alphabetical list of all module." //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module instances)" //: /line:"" //: /line:"The easiest way to create a module instance is to find its name in the module list and" //: /line:"drag it into the current circuit. Try switching to the list view by pressing then" //: /line:"dragging several instances of the \"bar\" module into the current edit window." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(548,6) /sn:0 /anc:1 //: /line:"" //: /end //: comment g2 @(554,346) /sn:0 /anc:1 //: /line:"Module Tree View Example" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list)" //: /line:"" //: /line:"The set of modules in the current circuit is shown on the left-hand side of the interface. You" //: /line:"can choose between a tree view (see example) and a list view . The tree view shows" //: /line:"the module hierarchy starting at a top-level root module indicated by the symbol. Modules" //: /line:"which are still in the circuit, but are not used anywhere in the hierarchy are listed under the" //: /line:"\" Unused\" branch. Click on to open a branch on the tree." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(11,22) //: /line:"

Using Modules

(interface editor)" //: /line:"" //: /line:"You can directly edit the module interface using TkGate's interface mode. Click on the Interface" //: /line:"tab over the main canvas to enter this mode. Details on how to use this mode are given in the TkGate" //: /line:"documentation. Click on the Edit tab to return to the normal editing mode." //: /end endmodule //: /netlistEnd //: /netlistBegin bar module bar(Y, X, C, B, Z, A); //: interface /sz:(56, 72) /bd:[ Li0>C(48/72) Li1>B(32/72) Li2>A(16/72) Ro0Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end _GGAND2 #(6) g11 (.I0(w0), .I1(Y), .Z(X)); //: @(244,161) /sn:0 /w:[ 3 0 5 ] /eb:0 //: joint g10 (B) @(118, 207) /w:[ -1 2 1 4 ] //: joint g19 (C) @(162, 260) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g6 (.I0(A), .I1(B), .Z(w0)); //: @(144,158) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(C), .Z(Y)); //: @(200,193) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (C) @(137, 260) /w:[ 2 1 8 -1 ] //: comment g15 @(22,25) //: /line:"This is the definition for module \"bar\". Ports A, B and C are inputs, and ports X, Y and Z are" //: /line:"outputs. Try adding an additional output port \"W\" from the output of the XOR gate below." //: /line:"Right click at the position you want to create the port then select Make → Module → Module" //: /line:"Output from the popup menu. Enter \"W\" for the net name in the dialog box." //: /line:"" //: /line:"" //: /end _GGXOR2 #(8) g17 (.I0(C), .I1(X), .Z(w3)); //: @(293,129) /sn:0 /w:[ 7 3 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: OUT g5 (Z) @(343,258) /sn:0 /w:[ 1 ] //: IN g0 (A) @(84,135) /sn:0 /w:[ 1 ] //: joint g12 (Y) @(221, 193) /w:[ 2 1 4 -1 ] //: joint g18 (X) @(266, 161) /w:[ 1 2 4 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGOR2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/sequential3.v000644 001751 001751 00000011355 10624605075 022323 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" //: /symbolBegin: 140311312 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:232,193)(232,219){1} reg w4; //: /sn:0 {0}(287,278)(298,278)(298,266)(308,266){1} supply0 w3; //: /sn:0 {0}(285,243)(285,233)(272,233){1} supply0 w0; //: /sn:0 {0}(287,288)(310,288)(310,303){1} wire [7:0] w2; //: /sn:0 {0}(#:248,273)(248,248){1} wire ck; //: {0}(-39:130,283)(211,283){1} wire [7:0] reg_out; //: {0}(#:248,294)(248,327)(304,327){1} //: {2}(308,327)(364,327)(58:364,206)(264,206)(264,219){3} //: {4}(306,329)(306,342){5} wire w9; //: /sn:0 {0}(224,233)(214,233){1} //: enddecls //: joint g8 (reg_out) @(306, 327) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(310,309) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(continuous simulation)" //: /line:"" //: /line:"Also like with a combinational circuit, you can press the button to unpause and simulate" //: /line:"continously. Try it with the circuit below. This circuit contains a \"real-world-time\" oscilator" //: /line:"that will cycle once per second. Like in the previous example, you will need to reset it by" //: /line:"turning the \"reset\" switch off monentarily." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(248,283) /sn:0 /w:[ 0 0 0 0 1 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end OSCILLATOR g10 (.Z(ck)); //: @(116, 283) /symbol:140311312 /sn:0 /w:[ 0 ] //: DIP g6 (w7) @(232,183) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(285,249) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(306,349) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(248,235) /sn:0 /w:[ 1 3 1 1 0 ] //: SWITCH reset (w4) @(326,266) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/combinational4.v000644 001751 001751 00000014150 10624605075 022765 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(dip switches)" //: /line:"" //: /line:"To change the value of a dip while simulating a circuit, first click on it to open a value dialog" //: /line:"box. Then enter the new value in hexidecimal and click Apply. Start the simulator then try" //: /line:"changing the input values in the four-bit adder below and observe the output." //: /end //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(560,127) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>B[3:0](41/64) Li1>A[3:0](16/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>B(34/50) Li1>A(12/50) Bo0Sequential Simulation (breakpoints)" //: /line:"" //: /line:"You can use breakpoints to simulate a circuit until some condition holds. To add a" //: /line:"breakpoint click on the tab on the information box below the canvas, and press" //: /line:"the Add... button. Enter the breakpoint as a Verilog expression. Start the simulator" //: /line:"and try it with the expresion \"reg_out == 8'h42\" as shown in the example on the right." //: /line:"This will cause the simulator to stop when the reg_out signal has the value 42 hexidecimal." //: /line:"Be sure to press after entering the breakpoint." //: /end //: SWITCH g3 (w4) @(307,295) /sn:0 /R:2 /w:[ 1 ] /st:1 _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(229,312) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(565,96) /sn:0 /anc:1 //: /line:"" //: /line:"" //: /line:"

Breakpoint Entry Example.

" //: /end //: DIP g6 (w7) @(213,212) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(289,366) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(266,278) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(229,264) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(114,312) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/welcome.v~000644 001751 001751 00000057205 11140740223 021710 0ustar00hansenhansen000000 000000 //: version "2.0-a5" //: property locale = "ja" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property encoding = "euc-jp" //: property discardChanges = 1 `timescale 1ns/1ns //: /symbolBegin: 141521168 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg b; //: {0}(41:73,97)(109,97){1} //: {2}(111,95)(111,67)(127,67){3} //: {4}(111,99)(111,143)(139,143){5} supply1 w7; //: /sn:0 {0}(456,31)(456,18){1} reg [7:0] w19; //: /sn:0 {0}(#:703,66)(703,39){1} reg w0; //: /sn:0 {0}(357,39)(429,39){1} //: {2}(433,39)(442,39){3} //: {4}(431,37)(431,29){5} //: {6}(431,41)(431,127)(481,127){7} reg [1:0] w21; //: /sn:0 {0}(#:136,463)(96,463)(96,428)(90,428){1} reg w28; //: /sn:0 {0}(69,268)(89,268)(89,268)(118,268){1} reg w20; //: /sn:0 {0}(661,137)(624,137){1} reg [1:0] w23; //: /sn:0 {0}(#:136,478)(90,478){1} reg w1; //: /sn:0 {0}(357,73)(392,73){1} //: {2}(396,73)(442,73){3} //: {4}(394,71)(394,64){5} //: {6}(394,75)(394,126)(409,126){7} reg [7:0] w25; //: /sn:0 {0}(#:90,208)(131,208)(131,252){1} supply0 w18; //: /sn:0 {0}(741,206)(741,188)(723,188){1} reg ci; //: {0}(12:73,26)(177,26)(177,68){1} //: {2}(179,70)(202,70){3} //: {4}(177,72)(177,99){5} supply0 w11; //: /sn:0 {0}(759,102)(759,80)(743,80){1} supply0 w2; //: /sn:0 {0}(495,136)(495,152)(458,152){1} //: {2}(454,152)(423,152)(423,135){3} //: {4}(456,154)(456,163){5} supply1 w10; //: /sn:0 {0}(723,178)(737,178)(737,160){1} reg a; //: {0}(30:73,62)(115,62){1} //: {2}(119,62)(127,62){3} //: {4}(117,64)(117,138)(139,138){5} supply0 [7:0] w9; //: /sn:0 {0}(#:650,102)(650,92)(674,92)(674,121){1} reg [1:0] w26; //: /sn:0 {0}(#:90,331)(111,331)(111,368)(120,368){1} wire [7:0] w14; //: /sn:0 {0}(#:153,508)(153,545)(248,545)(248,237)(215,237){1} //: {2}(213,235)(213,218){3} //: {4}(211,237)(151,237)(151,252){5} wire w4; //: /sn:0 {0}(205,141)(160,141){1} wire w3; //: /sn:0 {0}(205,136)(175,136)(175,120){1} wire w24; //: /sn:0 {0}(695,80)(685,80){1} wire co; //: {0}(245,129)(-68:245,139)(226,139){1} wire w8; //: /sn:0 {0}(202,65)(174,65){1} //: {2}(170,65)(148,65){3} //: {4}(172,67)(172,99){5} wire [7:0] w30; //: /sn:0 {0}(#:180,508)(180,520)(228,520)(228,310)(215,310){1} //: {2}(213,308)(213,295){3} //: {4}(211,310)(188,310)(188,339){5} wire [7:0] w22; //: /sn:0 {0}(#:694,121)(694,107)(719,107)(719,95){1} wire clk; //: {0}(20:593,183)(647,183){1} wire [7:0] w12; //: /sn:0 {0}(#:165,449)(165,406){1} wire [7:0] w27; //: /sn:0 {0}(#:684,150)(684,173){1} wire s; //: {0}(246,80)(39:246,68)(223,68){1} wire w13; //: /sn:0 {0}(423,118)(423,99)(454,99){1} //: {2}(458,99)(493,99){3} //: {4}(495,97)(495,87){5} //: {6}(495,101)(495,119){7} //: {8}(456,97)(456,82){9} wire w5; //: /sn:0 {0}(456,48)(456,65){1} wire w33; //: /sn:0 {0}(136,493)(86,493)(86,529)(59,529){1} wire [7:0] reg_out; //: {0}(#:684,194)(50:684,230)(729,230){1} //: {2}(-24:733,230)(783,230)(783,55)(735,55)(735,66){3} //: {4}(731,232)(731,249){5} wire [7:0] w29; //: /sn:0 {0}(#:141,339)(141,281){1} //: enddecls //: joint g61 (reg_out) @(731, 230) /w:[ 2 -1 1 4 ] //: VDD g8 (w7) @(467,18) /sn:0 /w:[ 1 ] _GGNMOS #(2, 1) g4 (.Z(w13), .S(w2), .G(w0)); //: @(489,127) /sn:0 /w:[ 7 0 7 ] //: LED g55 (w0) @(431,22) /sn:0 /w:[ 5 ] /type:0 _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co)); //: @(216,139) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g13 (w1) @(394, 73) /w:[ 2 4 1 6 ] //: SWITCH g3 (w0) @(340,39) /sn:0 /w:[ 0 ] /st:0 _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(46,529) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 REGS g2 (.SA(w21), .AIN(w12), .AOUT(w14), .SB(w23), .BOUT(w30), .ck(w33)); //: @(165, 479) /symbol:141521168 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(213,288) /sn:0 /w:[ 3 ] /type:2 _GGCLOCK_P120_0_50 g1 (.Z(clk)); //: @(580,183) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 //: joint g11 (w2) @(456, 152) /w:[ 1 -1 2 4 ] //: joint g16 (w30) @(213, 310) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4)); //: @(150,141) /sn:0 /w:[ 5 5 1 ] /eb:0 //: GROUND g10 (w2) @(456,169) /sn:0 /w:[ 5 ] //: joint g32 (w8) @(172, 65) /w:[ 1 -1 2 4 ] //: SWITCH g27 (ci) @(56,26) /sn:0 /w:[ 0 ] /st:0 //: joint g19 (w0) @(431, 39) /w:[ 2 4 1 6 ] _GGNMOS #(2, 1) g6 (.Z(w13), .S(w2), .G(w1)); //: @(417,126) /sn:0 /w:[ 0 3 7 ] //: DIP sa (w21) @(52,428) /R:1 /w:[ 1 ] /st:0 //: joint g57 (w13) @(495, 99) /w:[ -1 4 3 6 ] //: joint g9 (w13) @(456, 99) /w:[ 2 8 1 -1 ] _GGPMOS #(2, 1) g7 (.Z(w5), .S(w7), .G(w0)); //: @(450,39) /sn:0 /w:[ 0 0 3 ] _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(141,268) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(175,110) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g15 (s) @(246,87) /sn:0 /R:2 /w:[ 0 ] /type:0 //: DIP sb (w23) @(52,478) /R:1 /w:[ 1 ] /st:1 //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(121, 340) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: DIP func (w26) @(52,331) /R:1 /w:[ 0 ] /st:0 //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: joint g29 (a) @(117, 62) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a) @(56,62) /sn:0 /w:[ 0 ] /st:0 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 //: DIP data_in (w25) @(52,208) /R:1 /w:[ 0 ] /st:11 //: LED g56 (w13) @(495,80) /sn:0 /w:[ 5 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,73) /sn:0 /w:[ 9 1 3 ] //: LED g14 (co) @(245,122) /sn:0 /w:[ 0 ] /type:0 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,68) /sn:0 /w:[ 0 3 1 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,65) /sn:0 /w:[ 3 3 3 ] /eb:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: LED g54 (w1) @(394,57) /sn:0 /w:[ 5 ] /type:0 //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: SWITCH g26 (b) @(56,97) /sn:0 /w:[ 0 ] /st:1 //: comment g0 @(280,236) /anc:1 //: /line:"

TkGate ¤Ø¤è¤¦¤³¤½

" //: /line:"[Alpha Release]" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to " //: /line:" [released ]" //: /line:"" //: /line:"°Ê²¼¤Î¥ê¥ó¥¯¤Ë¥¯¥ê¥Ã¥¯¤·¤Æ¡¢tkgate¤ò»È¤¨»Ï¤á¤è¤¦¡£" //: /line:"" //: /line:" * ¥Á¥å¡¼¥È¥ê¥¢¥ë¤Ø" //: /line:"" //: /line:" * ÎãÂê²óÏ©¤Ø" //: /line:"" //: /line:" * ¿·µ¬²óÏ©¤òºîÀ®" //: /line:"" //: /line:" * ¥É¥­¥å¥á¥ó¥Æ¡¼¥·¥ç¥ó¤òÆɤ⤦ " //: /end //: SWITCH data_select (w28) @(52,268) /w:[ 0 ] /st:0 //: SWITCH g12 (w1) @(340,73) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (ci) @(177, 70) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(111, 97) /w:[ -1 2 1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](21/89) Ti1>B[7:0](67/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGNDEMUX4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; assign Zcat = 4'b1 << I; assign #1 Z0 = ~(E & Zcat[0]); assign #1 Z1 = ~(E & Zcat[1]); assign #1 Z2 = ~(E & Zcat[2]); assign #1 Z3 = ~(E & Zcat[3]); endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; nmos #Dgz mos (Z,S,G); endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always @(*) begin case (S) 1'h0: Z <= #Dsz I0; 1'h1: Z <= #Dsz I1; default: Z <= #Dsz 1'h0; endcase end endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #100; Z = 1'b1; #100; end end endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; pmos #Dgz mos (Z,S,G); endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/index.v~000644 001751 001751 00000003635 11140741567 021376 0ustar00hansenhansen000000 000000 //: version "2.0-b3" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(433,291) /sn:0 /R:14 //: /line:"TkGate¤Î¥á¥¤¥ó¤Î¥Ú¡¼¥¸¤ËÌá¤ë¡£" //: /end //: comment g0 @(434,49) /sn:0 /anc:1 //: /line:"" //: /end //: comment g18 @(10,10) /sn:0 /anc:1 //: /line:"

¥Á¥å¡¼¥È¥ê¥¢¥ë¤Î¾Ï¤Î°ìÍ÷ɽ:

" //: /line:"" //: /line:"

1. ²óÏ©¤ÎºîÀ®

- Get started by creating a simple circuit." //: /line:"" //: /line:"

2. ¥²¡¼¥È¤ÎÊÔ½¸

- The basics of editing gates." //: /line:"" //: /line:"

3. ¥ï¥¤¥ä¤ÎÊÔ½¸

- The basics of editing wires." //: /line:"" //: /line:"

4. ¥°¥ë¡¼¥×ÊÔ½¸¤Îµ¡Ç½

- Operate on groups of gates." //: /line:"" //: /line:"

5. ¥æ¡¼¥¶¡¦¥â¥¸¥å¡¼¥ë

- Using modules in your circuit." //: /line:"" //: /line:"

6. Advanced Editing Techniques

- Learn advanced editing tricks." //: /line:"" //: /line:"

7. Áȹ礻²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó

- Simulate a circuit with" //: /line:" combinational logic." //: /line:"" //: /line:"

8. ½ç½ø²óÏ©¤Î¥·¥ß¥å¥ì¡¼¥·¥ç¥ó

- Simulate a circuit with" //: /line:" sequential logic." //: /line:"" //: /line:"

9. ¥Æ¥­¥¹¥ÈVerilog

- Create modules with textual Verilog descriptions." //: /line:"" //: /line:"

10. TkGate¤Î¥ª¥×¥·¥ç¥ó

- Customize TkGate to suit your tastes." //: /line:"" //: /line:"" //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/ja/tutorials/create.v~000644 001751 001751 00000017105 11140741573 021524 0ustar00hansenhansen000000 000000 //: version "2.0-a5" //: property prefix = "_GG" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg w3; //: /sn:0 {0}(219,137)(154,137){1} reg w9; //: /sn:0 {0}(314,237)(213,237){1} //: {2}(211,235)(211,142)(219,142){3} //: {4}(209,237)(154,237){5} wire w8; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} wire w10; //: /sn:0 {0}(335,235)(345,235){1} //: enddecls //: comment g8 @(313,208) //: /line:"OR gate" //: /end //: joint g13 (w9) @(211, 237) /w:[ 1 2 4 -1 ] //: comment g1 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w3), .I1(w9), .Z(w8)); //: @(230,140) /sn:0 /w:[ 0 3 1 ] //: comment g6 @(115,104) //: /line:"Switches" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

ñ½ã¤Î²óÏ©¤ÎºîÀ®

" //: /line:"" //: /line:"In this chapter, we will walk through the steps of creating the simple circuit shown below." //: /end //: comment g7 @(208,112) //: /line:"AND gate" //: /end //: SWITCH g14 (w3) @(137,137) /sn:0 /w:[ 1 ] /st:0 _GGOR2 #(6) g0 (.I0(w8), .I1(w9), .Z(w10)); //: @(325,235) /sn:0 /w:[ 0 0 0 ] //: SWITCH g12 (w9) @(137,237) /sn:0 /w:[ 5 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(182,237)(182,237)(314,237){1} reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1} wire w7; //: /sn:0 {0}(335,235)(345,235){1} wire w0; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} //: enddecls _GGOR2 #(6) g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(325,235) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g3 (.I0(w2), .I1(w0), .Z(w5)); //: @(230,140) /sn:0 /w:[ 0 1 1 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /w:[ 0 ] /st:0 //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(537,46) /sn:0 /anc:1 //: /line:"" //: /end //: comment g7 @(537,126) /sn:0 //: /line:"Hint: Joints are formed any" //: /line:"time the soldering iron is" //: /line:"active and you release the" //: /line:"wire in the middle of another" //: /line:"wire." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now make the final connection. Grab the lower input terminal of the AND gate" //: /line:"and drag it down near the wire between the lower switch and the OR gate. Release" //: /line:"the wire to create a joint." //: /line:"" //: /end //: SWITCH g5 (w2) @(137,137) /sn:0 /w:[ 1 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w2; //: /sn:0 {0}(240,140)(255,140){1} //: enddecls _GGAND2 #(6) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(230,140) /sn:0 /w:[ 1 1 0 ] //: frame g1 @(283,202) /sn:0 /wi:78 /ht:46 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now create an OR gate. Right click in the dashed line box then select" //: /line:"Make → Gate → OR from the popup menu." //: /end //: comment g0 @(532,85) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"o\" to create an OR gate." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(169,237){1} reg w2; //: /sn:0 {0}(154,137)(169,137){1} wire w7; //: /sn:0 {0}(240,140)(255,140){1} wire w4; //: /sn:0 {0}(204,137)(219,137){1} wire w0; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(335,235)(350,235){1} wire w1; //: /sn:0 {0}(299,237)(314,237){1} wire w5; //: /sn:0 {0}(204,142)(219,142){1} //: enddecls //: SWITCH g4 (w2) @(137,137) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGAND2 #(6) g3 (.I0(w4), .I1(w5), .Z(w7)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w1), .Z(w3)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(578,122) /sn:0 /anc:1 //: /line:"Hint: The soldering iron cursor will" //: /line:"show you when you have selected" //: /line:"a connectable wire end." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Finally, connect the wires. Begin by grabbing the end of the wire leading from one of the" //: /line:"switches with the left mouse button and drag it to the upper input terminal of the AND gate." //: /end //: comment g0 @(579,61) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(335,235)(350,235){1} wire w4; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(240,140)(255,140){1} wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(299,237)(314,237){1} //: enddecls //: frame g8 @(109,215) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" _GGOR2 #(6) g4 (.I0(w4), .I1(w5), .Z(w7)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w0), .I1(w1), .Z(w3)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g1 @(109,121) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Next create two switches. Right click in each of the two dashed line box then" //: /line:"select Make → I/O → Switch from the popup menu." //: /end //: comment g0 @(532,86) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"s\" to create a switch." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(531,86) /sn:0 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"a\" to create an AND gate." //: /end //: frame g1 @(208,124) /sn:0 /wi:76 /ht:43 /tx:"" //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Start by creating an AND gate. Right click in the dashed line box then select" //: /line:"Make → Gate → AND from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/gates.v~000644 001751 001751 00000035123 11140741601 021354 0ustar00hansenhansen000000 000000 //: version "2.0-a2" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

" //: /line:"" //: /line:"This chapter will introduce some of the basic circuit editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(144,69) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(256,171)(271,171){1} wire w3; //: /sn:0 {0}(256,166)(271,166){1} wire w0; //: /sn:0 {0}(102,172)(117,172){1} wire w1; //: /sn:0 {0}(102,177)(117,177){1} wire w2; //: /sn:0 {0}(138,175)(153,175){1} wire w5; //: /sn:0 {0}(292,169)(307,169){1} //: enddecls //: comment g4 @(247,195) /sn:0 /anc:1 //: /line:"Anchored Gate" //: /end _GGOR2 #(6) g3 (.I0(w3), .I1(w4), .Z(w5)); //: @(282,169) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Anchoring)" //: /line:"" //: /line:"You can prevent a gate from being accidentally moved by selecting it and pressing" //: /line:"the button to set an anchor. You can remove an anchor with the button." //: /line:"Gates which have been anchored (e.g., the OR gate below) can not be moved until" //: /line:"you remove the anchor. Try moving the gates below." //: /line:"" //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(128,175) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(587,112) /sn:0 //: /line:"Hint: An alternate way to add or" //: /line:"remove an anchor on a gate is to" //: /line:"right click and change the anchor" //: /line:"flag in the popup menu." //: /end //: comment g5 @(81,195) /sn:0 /anc:1 //: /line:"Unanchored Gate" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Editing Gates

(Repositioning)" //: /line:"" //: /line:"To move a gate, select it with the tool and drag it to a new location. Try" //: /line:"it on the sample circuit below." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(39,221)(54,221){1} wire w7; //: /sn:0 {0}(41,265)(56,265){1} wire w14; //: /sn:0 {0}(169,222)(154,222){1} wire w16; //: /sn:0 {0}(154,267)(169,267){1} wire w4; //: /sn:0 {0}(39,218)(54,218){1} wire w15; //: /sn:0 {0}(154,262)(169,262){1} wire w19; //: /sn:0 {0}(169,277)(154,277){1} wire w3; //: /sn:0 {0}(39,214)(54,214){1} wire w0; //: /sn:0 {0}(37,166)(52,166){1} wire w21; //: /sn:0 {0}(152,167)(167,167){1} wire w23; //: /sn:0 {0}(188,169)(203,169){1} wire w20; //: /sn:0 {0}(41,274)(56,274){1} wire w1; //: /sn:0 {0}(37,171)(52,171){1} wire w8; //: /sn:0 {0}(41,268)(56,268){1} wire w18; //: /sn:0 {0}(190,269)(205,269){1} wire w22; //: /sn:0 {0}(152,172)(167,172){1} wire w17; //: /sn:0 {0}(169,272)(154,272){1} wire w2; //: /sn:0 {0}(73,169)(88,169){1} wire w11; //: /sn:0 {0}(154,212)(169,212){1} wire w12; //: /sn:0 {0}(154,217)(169,217){1} wire w10; //: /sn:0 {0}(41,271)(56,271){1} wire w13; //: /sn:0 {0}(190,217)(205,217){1} wire w5; //: /sn:0 {0}(75,218)(90,218){1} wire w9; //: /sn:0 {0}(77,270)(92,270){1} //: enddecls //: comment g8 @(149,126) /sn:0 //: /line:"gates with" //: /line:"extender bars" //: /end _GGAND4 #(10) g4 (.I0(w7), .I1(w8), .I2(w10), .I3(w20), .Z(w9)); //: @(67,270) /sn:0 /w:[ 1 1 1 1 0 ] _GGAND3 #(8) g3 (.I0(w3), .I1(w4), .I2(w6), .Z(w5)); //: @(65,218) /sn:0 /w:[ 1 1 1 0 ] //: comment g2 @(11,13) //: /line:"

Editing Gates

(Adding Inputs)" //: /line:"" //: /line:"Some gates (e.g., AND gates) can have a variable number of inputs or outputs. To add inputs (or" //: /line:"outputs) to these gates, select the gate and press the button. Also, some gates may have multiple styles" //: /line:"for adding ports that can be selected through the gate properties box. Try adding inputs to the gates below," //: /line:"or create a new gate and add inputs to it." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(63,169) /sn:0 /w:[ 1 1 0 ] _GGAND4 #(10) g6 (.I0(w15), .I1(w16), .I2(w17), .I3(w19), .Z(w18)); //: @(180,269) /sn:0 /w:[ 1 1 0 0 0 ] /eb:1 _GGAND2 #(6) g9 (.I0(w21), .I1(w22), .Z(w23)); //: @(178,169) /sn:0 /w:[ 1 1 0 ] /eb:1 //: comment g7 @(26,127) /sn:0 //: /line:"gates without" //: /line:"extender bars" //: /end _GGAND3 #(8) g5 (.I0(w11), .I1(w12), .I2(w14), .Z(w13)); //: @(180,217) /sn:0 /w:[ 1 1 0 0 ] /eb:1 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: frame g3 @(298,213) /sn:0 /wi:167 /ht:69 /tx:"This is a frame" //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Comments and Frames)" //: /line:"" //: /line:"There are two special \"gates\" that you can use for annotating your circuit specification: comments and frames." //: /line:"Neither of these \"gates\" has any effect on the simulation results." //: /line:"" //: /line:"Comments are blocks of text such as those used to construct this tutorial. Comments are created by right clicking" //: /line:"and selecting Make → Comment from the popup menu. When you create a comment, the properties box will" //: /line:"appear immediately allowing you to enter the text of the comment. Comments can contain limited html tags including links" //: /line:"to other circuit files, or short cuts to specific gates in your circuit." //: /line:"" //: /line:"Frames are annotated boxes for organzing groups of related circuit elements that don't warrant creating a new module. Open" //: /line:"the properties box by double clicking on an edge to set the annotation string. Click and drag on a corner to resize." //: /line:"" //: /end //: comment g1 @(72,233) /sn:0 //: /line:"This is a comment with" //: /line:"some bold text in it." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(118,149)(133,149){1} wire w1; //: /sn:0 {0}(118,154)(133,154){1} wire w2; //: /sn:0 {0}(154,152)(169,152){1} //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Rotation)" //: /line:"" //: /line:"The orientation of a gate can be changed by selecting it and pressing the button" //: /line:"(or Tab key) to rotate it counter-clockwise and the button (or Shift-Tab key) to" //: /line:"rotate it clockwise. Try it on the AND gate below." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(144,152) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(567,92) /sn:0 /anc:1 //: /line:"Hint: You can also use the " //: /line:"button to set the default orientation" //: /line:"for newly created gates." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Deletion)" //: /line:"" //: /line:"To delete a gate, select it with the tool and press the Delete key. Try it on the sample circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Properties)" //: /line:"" //: /line:"You can also open the properties box of a gate by double clicking on it. Try" //: /line:"double clicking on some of the gates in the circuit below. Through the properties" //: /line:"box you can change the label of a gate and make the label visible or invisible" //: /line:"though the \"Hide Name\" property." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: comment g6 @(548,104) /sn:0 /anc:1 //: /line:"Hint: Many properties are gate-" //: /line:"specific. Try opening the property" //: /line:"boxes of different gate types to see" //: /line:"what proprties can be modified." //: /end _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGAND4 #(.Diz(1)) (I0, I1, I2, I3, Z); output Z; input I0; input I1; input I2; input I3; assign #Diz Z = I0 & I1 & I2 & I3; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0; input I1; input I2; assign #Diz Z = I0 & I1 & I2; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/wires.v~000644 001751 001751 00000044756 11140741606 021423 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Wires

" //: /line:"" //: /line:"This chapter will introduce the basic wire editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(185,114) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:155,153)(261,153)(261,195){1} //: {2}(263,197)(286,197){3} //: {4}(261,199)(261,209){5} reg a0; //: {0}(40:155,189)(199,189){1} //: {2}(203,189)(211,189){3} //: {4}(201,191)(201,245)(218,245){5} reg b0; //: {0}(50:155,224)(193,224){1} //: {2}(195,222)(195,194)(211,194){3} //: {4}(195,226)(195,250)(218,250){5} wire w7; //: /sn:0 {0}(239,248)(254,248)(254,260){1} wire s0; //: {0}(36:307,195)(337,195){1} wire w4; //: /sn:0 {0}(259,230)(259,260){1} wire c1; //: {0}(99:257,281)(257,300){1} wire w9; //: /sn:0 {0}(286,192)(258,192){1} //: {2}(254,192)(232,192){3} //: {4}(256,194)(256,209){5} //: enddecls //: LED g37 (s0) @(344,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Basic Editing Modes

(wire labels)" //: /line:"" //: /line:"Wire label editing is performed with the tool. Select this tool if it is not already selected. Existing" //: /line:"wire labels can be moved by left clicking and dragging the label to a new position. Wire labels can only" //: /line:"be moved to a different locations on the wire from which it was grabbed. If you drop the label too far from" //: /line:"its wire, the label will be discarded. To display a new label right click on the wire and choose the Show" //: /line:"Label option. You can also hide a specific label (Hide Label) or hide all labels for a wire (Hide All Labels)." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(257,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(229,248) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(138,153) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(256, 192) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(259,220) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(138,189) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(201, 189) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(297,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(222,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(138,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g30 (b0) @(195, 224) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(261, 197) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin advanced module advanced(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g4 @(16,548) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(549,50) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g9 @(23,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(cutting)" //: /line:"" //: /line:"To cut a wire, select the tool and click on a wire at the point you wish to cut. Try" //: /line:"using the wire cutter tool to cut some of the wires in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] supply1 w7; //: /sn:0 {0}(320,176)(335,176)(335,158){1} reg [7:0] w3; //: /sn:0 {0}(#:184,170)(184,208)(212,208)(212,224){1} supply0 w8; //: /sn:0 {0}(271,250)(271,238)(252,238){1} supply0 w5; //: /sn:0 {0}(339,207)(339,186)(320,186){1} wire [7:0] w6; //: /sn:0 {0}(281,171)(281,146)(371,146)(371,268)(#:228,268)(#:228,253){1} wire w4; //: /sn:0 {0}(204,238)(189,238){1} wire [7:0] w1; //: /sn:0 {0}(244,224)(244,211)(#:281,211)(#:281,192){1} wire w2; //: /sn:0 {0}(85,181)(244,181){1} //: enddecls //: DIP g8 (w3) @(184,160) /sn:0 /w:[ 0 ] /st:66 //: GROUND g4 (w5) @(339,213) /sn:0 /w:[ 0 ] //: comment g2 @(9,10) /anc:1 //: /line:"

Basic Editing Modes

(bit widths)" //: /line:"" //: /line:"To change the bit size of one or more wires, first enter the desired bit size in the" //: /line:"bit size selector . Next, choose the tool, and click on each wire" //: /line:"to be changed to that size. Try changing the 8-bit wires in the circuit below to 16-bit wires." //: /line:"" //: /end _GGREG8 #(10, 10, 20) g1 (.Q(w1), .D(w6), .EN(w5), .CLR(w7), .CK(w2)); //: @(281,181) /sn:0 /w:[ 1 0 1 0 1 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGCLOCK_P100_0_50 g6 (.Z(w2)); //: @(72,181) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g7 (w8) @(271,256) /sn:0 /w:[ 0 ] //: VDD g5 (w7) @(346,158) /sn:0 /w:[ 1 ] _GGADD8 #(68, 70, 62, 64) g0 (.A(w3), .B(w1), .S(w6), .CI(w8), .CO(w4)); //: @(228,240) /sn:0 /w:[ 1 0 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,11) //: /line:"

Basic Editing Modes

(properties)" //: /line:"" //: /line:"Wire properties" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Basic Editing Modes

(I/O inverters)" //: /line:"" //: /line:"To place or remove an inverter on a gate input or output, select the tool" //: /line:"and click on the port at which you want to place or remove an inveter. Try" //: /line:"using the inverter tool to place and remove inverters in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/group.v~000644 001751 001751 00000024763 11140741612 021417 0ustar00hansenhansen000000 000000 //: version "2.0-a2" //: property prefix = "_GG" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(140,67) /sn:0 /anc:1 //: /line:"" //: /end //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

" //: /line:"" //: /line:"In this chapter, you will learn about how to do editing operations on groups of gates." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:183,147)(289,147)(289,189){1} //: {2}(291,191)(314,191){3} //: {4}(289,193)(289,210){5} reg a0; //: {0}(40:183,183)(227,183){1} //: {2}(231,183)(239,183){3} //: {4}(229,185)(229,239)(246,239){5} reg b0; //: {0}(50:183,218)(221,218){1} //: {2}(223,216)(223,188)(239,188){3} //: {4}(223,220)(223,244)(246,244){5} wire w7; //: /sn:0 {0}(267,242)(282,242)(282,254){1} wire s0; //: {0}(36:335,189)(365,189){1} wire w4; //: /sn:0 {0}(287,231)(287,254){1} wire c1; //: {0}(99:285,275)(285,294){1} wire w9; //: /sn:0 {0}(314,186)(286,186){1} //: {2}(282,186)(260,186){3} //: {4}(284,188)(284,210){5} //: enddecls //: LED g37 (s0) @(372,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(285,265) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(257,242) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(166,147) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(284, 186) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(287,221) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(166,183) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(229, 183) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(incremental selection)" //: /line:"" //: /line:"You can add or remove gates from the current selection by holding the Control key while" //: /line:"you click on them. Use the selection box to select the gates below then click on a few" //: /line:"of the gates with the Control key held down. Release the Control key and then try moving" //: /line:"the selection with only some of the gates selected." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(325,189) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(250,186) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(166,218) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (b0) @(223, 218) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(289, 191) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:167,153)(273,153)(273,195){1} //: {2}(275,197)(298,197){3} //: {4}(273,199)(273,216){5} reg a0; //: {0}(40:167,189)(189,189)(189,189)(211,189){1} //: {2}(215,189)(223,189){3} //: {4}(213,191)(213,245)(230,245){5} reg b0; //: {0}(50:167,224)(186,224)(186,224)(205,224){1} //: {2}(207,222)(207,194)(223,194){3} //: {4}(207,226)(207,250)(230,250){5} wire w7; //: /sn:0 {0}(251,248)(266,248)(266,260){1} wire s0; //: {0}(36:319,195)(349,195){1} wire w4; //: /sn:0 {0}(271,237)(271,260){1} wire c1; //: {0}(99:269,281)(269,300){1} wire w9; //: /sn:0 {0}(298,192)(270,192){1} //: {2}(266,192)(244,192){3} //: {4}(268,194)(268,216){5} //: enddecls //: LED g37 (s0) @(356,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(570,113) /sn:0 //: /line:"Hint: If a selection contains any" //: /line:"anchored gates, the entire selection" //: /line:"will act as if it were anchored." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(269,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(241,248) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(150,153) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(268, 192) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(271,227) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(150,189) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(213, 189) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(rotation and anchoring)" //: /line:"" //: /line:"You can rotate (with and ) and anchor (with and ) a group of gates in the same" //: /line:"way as you did for single gates in the Editing Gates chapter. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(309,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(234,192) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(150,224) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(207, 224) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(273, 197) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:174,160)(280,160)(280,202){1} //: {2}(282,204)(305,204){3} //: {4}(280,206)(280,223){5} reg a0; //: {0}(40:174,196)(196,196)(196,196)(218,196){1} //: {2}(222,196)(230,196){3} //: {4}(220,198)(220,252)(237,252){5} reg b0; //: {0}(50:174,231)(193,231)(193,231)(212,231){1} //: {2}(214,229)(214,201)(230,201){3} //: {4}(214,233)(214,257)(237,257){5} wire w7; //: /sn:0 {0}(258,255)(273,255)(273,267){1} wire s0; //: {0}(36:326,202)(356,202){1} wire w4; //: /sn:0 {0}(278,244)(278,267){1} wire c1; //: {0}(99:276,288)(276,307){1} wire w9; //: /sn:0 {0}(305,199)(277,199){1} //: {2}(273,199)(251,199){3} //: {4}(275,201)(275,223){5} //: enddecls //: LED g37 (s0) @(363,202) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(548,117) /sn:0 //: /line:"Hint: Hitting the Delete key will" //: /line:"delete all of the selected gates" //: /line:"without copying it to the clipboard." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(276,278) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(248,255) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(157,160) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(275, 199) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(278,234) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(157,196) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(220, 196) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(clipboard operations)" //: /line:"" //: /line:"You can use Cut and Paste operations to cut or copy a group of gates to the clipboard" //: /line:"and paste it somewhere else. Select a group of gates then press the or buttons to" //: /line:"cut or copy, respectively, the selected gates to the clipboard. To paste the contents of the" //: /line:"clipboard, first set a with the left mouse button, then press the button to paste the" //: /line:"clipboard contents to that location." //: /line:"" //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(316,202) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(241,199) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(157,231) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(214, 231) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(280, 204) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:182,149)(288,149)(288,191){1} //: {2}(290,193)(313,193){3} //: {4}(288,195)(288,212){5} reg a0; //: {0}(40:182,185)(226,185){1} //: {2}(230,185)(238,185){3} //: {4}(228,187)(228,241)(245,241){5} reg b0; //: {0}(50:182,220)(220,220){1} //: {2}(222,218)(222,190)(238,190){3} //: {4}(222,222)(222,246)(245,246){5} wire w7; //: /sn:0 {0}(266,244)(281,244)(281,256){1} wire s0; //: {0}(36:334,191)(364,191){1} wire w4; //: /sn:0 {0}(286,233)(286,256){1} wire c1; //: {0}(99:284,277)(284,296){1} wire w9; //: /sn:0 {0}(313,188)(285,188){1} //: {2}(281,188)(259,188){3} //: {4}(283,190)(283,212){5} //: enddecls //: LED g37 (s0) @(371,191) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(609,113) /sn:0 //: /line:"Hint: Click in a blank area to" //: /line:"unselect a group." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(284,267) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(256,244) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(165,149) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(283, 188) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(286,223) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(165,185) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(228, 185) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(selection and movement)" //: /line:"" //: /line:"To select a group of gates, press and hold the left mouse button above and to the left" //: /line:"of the group, then drag the cursor diagonally accross the group to open the selection box." //: /line:"Release the mouse when the selection box includes all of the gates you wish to select. Drag" //: /line:"any selected gate to move the entire group. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(324,191) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(249,188) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(165,220) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(222, 220) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(288, 193) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/modules.v~000644 001751 001751 00000046307 11140741616 021735 0ustar00hansenhansen000000 000000 //: version "2.0-a2" //: property prefix = "_GG" //: property title = "module_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g3 @(259,83) /anc:1 //: /line:"A module is an encapsulated piece of logic that can be made" //: /line:"to serve a purpose in a circuit, similar to a function call" //: /line:"in a program. Each module in TkGate has an \"interface\" and" //: /line:"a \"definition\":" //: /line:"" //: /line:" * The interface describes the external" //: /line:" appearance of a module including the size of the box and" //: /line:" the positions of the ports on it. TkGate supports \"block\"" //: /line:" interfaces and \"symbol\" interfaces." //: /line:" " //: /line:" * The definition describes the internal" //: /line:" logic that the module implements. TkGate supports \"netlist\"" //: /line:" and \"HDL\" modules." //: /line:"" //: /end //: comment g2 @(10,65) /sn:0 /anc:1 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

" //: /line:"" //: /line:"In this chapter, you will learn how to create, edit and manage modules." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(258,177)(273,177){1} wire w3; //: /sn:0 {0}(258,161)(273,161){1} wire w0; //: /sn:0 {0}(200,161)(185,161){1} wire w1; //: /sn:0 {0}(200,177)(185,177){1} wire w2; //: /sn:0 {0}(200,192)(185,192){1} wire w5; //: /sn:0 {0}(258,193)(273,193){1} //: enddecls bar g4 (.C(w2), .B(w1), .A(w0), .Z(w5), .Y(w4), .X(w3)); //: @(201, 145) /sz:(56, 72) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Ro0<0 Ro1<0 Ro2<0 ] //: comment g3 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(editing module definitions)" //: /line:"" //: /line:"To edit the definition of a module you have created, double click on its name in the module name" //: /line:"tree or list view. Alternatively you can right click on an instance of the module and select" //: /line:"Open from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g4 @(576,89) /sn:0 /anc:1 //: /line:"Hint: The pages in this tutorial" //: /line:"are actually modules with the" //: /line:"names PAGE1, PAGE2, etc." //: /end //: comment g3 @(23,72) /sn:0 /anc:1 //: /line:" Top-level or root module." //: /line:"" //: /line:" Netlist module." //: /line:"" //: /line:" Verilog HDL module." //: /line:"" //: /line:" Locked netlist module." //: /line:"" //: /line:" Locked Verilog HDL module." //: /line:"" //: /line:" Container for unused modules." //: /line:"" //: /end //: comment g2 @(257,69) /anc:1 //: /line:" Library module." //: /line:"" //: /line:" Container for all libraries." //: /line:"" //: /line:" Container for a single library." //: /line:"" //: /line:" Use of an undefined module." //: /line:"" //: /line:" Recursive inclusion of a module." //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(module list symbols)" //: /line:"" //: /line:"The following symbols are used in the module tree and list view:" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin foo module foo(Z2, I3, Z1, I1, I2, Z3); //: interface /sz:(41, 40) /bd:[ ] input I2; //: /sn:0 {0}(245,200)(275,200){1} //: {2}(277,198)(277,153)(292,153){3} //: {4}(277,202)(277,248)(348,248){5} output Z3; //: /sn:0 {0}(369,251)(448,251){1} input I1; //: /sn:0 {0}(292,148)(278,148)(278,128)(246,128){1} output Z2; //: /sn:0 {0}(392,156)(380,156)(380,184){1} //: {2}(382,186)(448,186){3} //: {4}(378,186)(369,186){5} output Z1; //: /sn:0 {0}(448,154)(413,154){1} input I3; //: /sn:0 {0}(348,188)(296,188)(296,251){1} //: {2}(298,253)(348,253){3} //: {4}(294,253)(245,253){5} wire w0; //: /sn:0 {0}(348,183)(338,183)(338,153){1} //: {2}(340,151)(392,151){3} //: {4}(336,151)(313,151){5} //: enddecls _GGAND2 #(6) g8 (.I0(I2), .I1(I3), .Z(Z3)); //: @(359,251) /sn:0 /w:[ 5 3 0 ] /eb:0 //: OUT g4 (Z2) @(445,186) /sn:0 /w:[ 3 ] //: joint g13 (w0) @(338, 151) /w:[ 2 -1 4 1 ] //: IN g2 (I3) @(243,253) /sn:0 /w:[ 5 ] //: OUT g1 (Z1) @(445,154) /sn:0 /w:[ 0 ] //: comment g16 @(585,127) /sn:0 //: /line:"Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end _GGAND2 #(6) g11 (.I0(w0), .I1(Z2), .Z(Z1)); //: @(403,154) /sn:0 /w:[ 3 0 1 ] /eb:0 //: joint g10 (I2) @(277, 200) /w:[ -1 2 1 4 ] //: IN g19 (I1) @(244,128) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g6 (.I0(I1), .I1(I2), .Z(w0)); //: @(303,151) /sn:0 /w:[ 0 3 5 ] /eb:0 //: joint g9 (I3) @(296, 253) /w:[ 2 1 4 -1 ] _GGXOR2 #(8) g7 (.I0(w0), .I1(I3), .Z(Z2)); //: @(359,186) /sn:0 /w:[ 0 0 5 ] /eb:0 //: comment g15 @(22,25) //: /line:"This is the definition for module \"foo\"." //: /end //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: IN g5 (I2) @(243,200) /sn:0 /w:[ 0 ] //: joint g23 (Z2) @(380, 186) /w:[ 2 1 4 -1 ] //: OUT g12 (Z3) @(445,251) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(40, 40) /bd:[ ] input [7:0] B; //: /sn:0 {0}(#:342,147)(342,184){1} //: {2}(344,186)(367,186){3} //: {4}(371,186)(425,186)(425,258){5} //: {6}(369,188)(369,261){7} //: {8}(342,188)(342,258){9} input [1:0] F; //: /sn:0 {0}(#:343,353)(214,353){1} supply0 w0; //: /sn:0 {0}(491,295)(491,272)(465,272){1} input [7:0] A; //: /sn:0 {0}(#:265,147)(265,215){1} //: {2}(267,217)(345,217){3} //: {4}(349,217)(372,217){5} //: {6}(376,217)(457,217)(457,258){7} //: {8}(374,219)(374,261){9} //: {10}(347,219)(347,258){11} //: {12}(265,219)(265,322)(348,322)(348,337){13} output [7:0] Z; //: /sn:0 {0}(#:366,404)(366,366){1} wire [7:0] w14; //: /sn:0 {0}(#:345,279)(345,310)(360,310)(360,337){1} wire w4; //: /sn:0 {0}(417,272)(407,272){1} wire [7:0] w11; //: /sn:0 {0}(#:372,282)(372,337){1} wire [7:0] w10; //: /sn:0 {0}(#:384,337)(384,307)(441,307)(441,287){1} //: enddecls _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4)); //: @(441,274) /sn:0 /w:[ 5 7 1 1 0 ] //: joint g8 (A) @(347, 217) /w:[ 4 -1 3 10 ] //: IN g3 (F) @(212,353) /sn:0 /w:[ 1 ] //: GROUND g13 (w0) @(491,301) /sn:0 /w:[ 0 ] //: IN g2 (A) @(265,145) /sn:0 /R:3 /w:[ 0 ] //: IN g1 (B) @(342,145) /sn:0 /R:3 /w:[ 0 ] //: joint g11 (B) @(369, 186) /w:[ 4 -1 3 6 ] //: joint g10 (A) @(374, 217) /w:[ 6 -1 5 8 ] _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11)); //: @(372,272) /sn:0 /R:3 /w:[ 7 9 0 ] /eb:0 _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14)); //: @(345,269) /sn:0 /R:3 /w:[ 9 11 0 ] /eb:0 //: joint g9 (A) @(265, 217) /w:[ 2 1 -1 12 ] //: OUT g5 (Z) @(366,401) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z)); //: @(366,353) /sn:0 /w:[ 13 1 1 0 0 1 ] /ss:0 /do:0 //: joint g12 (B) @(342, 186) /w:[ 2 1 -1 8 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(573,160) /sn:0 /anc:1 //: /line:"Hint: If you are unable to modify a" //: /line:"module interface, right click on it," //: /line:"select Module Properties..., then" //: /line:"unset the interface protection options" //: /line:"in the dialog box." //: /end foo g2 (); //: @(208, 163) /sz:(40, 40) /sn:0 /p:[ ] //: comment g1 @(9,13) //: /line:"

Using Modules

(manual interface generation)" //: /line:"" //: /line:"You can also manually create and edit the interface of a module:" //: /line:" * To change the size of the interface, left-click on an edge or corner and drag it with the mouse." //: /line:" * To add a port, right click on an edge and choose the port type to create from the popup menu." //: /line:" * To delete a port, select the tool and cut the wire off of the module." //: /line:" * To edit port properties, double click on the port with the tool." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire [1:0] w0; //: /sn:0 {0}(#:257,226)(272,226){1} wire [7:0] w3; //: /sn:0 {0}(#:329,194)(314,194){1} wire [7:0] w1; //: /sn:0 {0}(#:257,210)(272,210){1} wire [7:0] w2; //: /sn:0 {0}(#:257,194)(272,194){1} //: enddecls ALU g3 (.A(w2), .B(w1), .F(w0), .Z(w3)); //: @(273, 178) /sz:(40, 64) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Ro0<1 ] //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) //: /line:"

Using Modules

(updating the default interface)" //: /line:"" //: /line:"Module interfaces constructed in Edit mode, apply only to the specific instance that you created." //: /line:"To make an interface the default for newly created instance of modules of that type, right click" //: /line:"on an interface and select Interface → Set. Try setting the interface to each of the two instances of" //: /line:"ALU modules below, then try creating new ALU modules by dragging them from the module list." //: /end ALU g0 (); //: @(130, 184) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(automatic interface generation)" //: /line:"" //: /line:"The interface of a module includes the size and shape of the box as well as the location and names" //: /line:"of the ports. The easiest way to create an interface is to use automatic generation. Automatic" //: /line:"generation uses the ports referenced in the definition to create the interface. To automatically" //: /line:"create an interface for the \"bar\" module, first click on the module list tab , then right click on \"bar\"" //: /line:"and select Interface → Auto Generate... Now left click and drag the bar module onto the canvas to see" //: /line:"the new interface." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) //: /line:"

Using Modules

(creating module definitions)" //: /line:"" //: /line:"To create a new module, press the button. Enter the name for the new module" //: /line:"and select whether you wish to create it as a \"netlist\" (graphical) module or an" //: /line:"HDL (textual) module. Try creating a new module named \"CPU\"." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(548,6) /sn:0 /anc:1 //: /line:"" //: /end //: comment g2 @(554,346) /sn:0 /anc:1 //: /line:"Module Tree View Example" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list)" //: /line:"" //: /line:"The set of modules in the current circuit is shown on the left-hand side of the interface. You" //: /line:"can choose between a tree view (see example) and a list view . The tree view shows" //: /line:"the module hierarchy starting at a top-level root module indicated by the symbol. Modules" //: /line:"which are still in the circuit, but are not used anywhere in the hierarchy are listed under the" //: /line:"\" Unused\" branch. Click on to open a branch on the tree." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(545,102) /sn:0 //: /line:"Hint: You can also drag and drop" //: /line:"module instance from the tree view," //: /line:"but it is easier to use the list view" //: /line:"since that view gives you a straight" //: /line:"alphabetical list of all module." //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module instances)" //: /line:"" //: /line:"The easiest way to create a module instance is to find its name in the module list and" //: /line:"drag it into the current circuit. Try switching to the list view by pressing then" //: /line:"dragging several instances of the \"bar\" module into the current edit window." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(11,22) //: /line:"

Using Modules

(interface editor)" //: /line:"" //: /line:"You can directly edit the module interface using TkGate's interface mode. Click on the Interface" //: /line:"tab over the main canvas to enter this mode. Details on how to use this mode are given in the TkGate" //: /line:"documentation. Click on the Edit tab to return to the normal editing mode." //: /end endmodule //: /netlistEnd //: /netlistBegin bar module bar(Y, X, C, B, Z, A); //: interface /sz:(56, 72) /bd:[ Li0>A(16/72) Li1>B(32/72) Li2>C(48/72) Ro0Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end //: joint g10 (B) @(118, 207) /w:[ -1 2 1 4 ] //: joint g19 (C) @(162, 260) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g6 (.I0(A), .I1(B), .Z(w0)); //: @(144,158) /sn:0 /w:[ 0 3 5 ] /eb:0 //: joint g9 (C) @(137, 260) /w:[ 2 1 8 -1 ] _GGXOR2 #(8) g7 (.I0(w0), .I1(C), .Z(Y)); //: @(200,193) /sn:0 /w:[ 0 0 5 ] /eb:0 //: comment g15 @(22,25) //: /line:"This is the definition for module \"bar\". Ports A, B and C are inputs, and ports X, Y and Z are" //: /line:"outputs. Try adding an additional output port \"W\" from the output of the XOR gate below." //: /line:"Right click at the position you want to create the port then select Make → Module → Module" //: /line:"Output from the popup menu. Enter \"W\" for the net name in the dialog box." //: /line:"" //: /line:"" //: /end _GGXOR2 #(8) g17 (.I0(C), .I1(X), .Z(w3)); //: @(293,129) /sn:0 /w:[ 7 3 0 ] //: OUT g5 (Z) @(343,258) /sn:0 /w:[ 1 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: IN g0 (A) @(84,135) /sn:0 /w:[ 1 ] //: joint g18 (X) @(266, 161) /w:[ 1 2 4 -1 ] //: joint g12 (Y) @(221, 193) /w:[ 2 1 4 -1 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always @(*) begin case (S) 2'h0: Z <= #Dsz I0; 2'h1: Z <= #Dsz I1; 2'h2: Z <= #Dsz I2; 2'h3: Z <= #Dsz I3; default: Z <= #Dsz 2'h0; endcase end endmodule //: /builtinEnd //: /builtinBegin module _GGOR2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/advanced.v~000644 001751 001751 00000063252 11140741621 022024 0ustar00hansenhansen000000 000000 //: version "2.0-a2" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Advanced Editing Techniques

" //: /line:"" //: /line:"In this chapter you will learn some additional techniques to be more efficient at editing circuits" //: /line:"in TkGate." //: /end //: comment g0 @(150,93) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Now try the same thing again, but this time drop the inverter input closer to the AND gate output" //: /line:"away from the joint. This time a new joint is automatically created." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(162,164)(202,164)(202,147)(227,147)(227,159)(252,159)(252,209)(178,209)(178,179){1} wire w4; //: /sn:0 {0}(131,166)(141,166){1} wire w0; //: /sn:0 {0}(131,161)(141,161){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(152,164) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Loop Deletion)" //: /line:"" //: /line:"Grab the endpoint of the XOR output wire in the circuit below. Drag it up until it crosses the" //: /line:"horizontal segment next to the gate and release it. TkGate will automatically remove the loop." //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w46; //: /sn:0 {0}(421,254)(374,254)(374,196){1} //: {2}(376,194)(397,194)(397,127)(422,127){3} //: {4}(372,194)(339,194){5} wire w0; //: /sn:0 {0}(67,208)(82,208){1} wire w43; //: /sn:0 {0}(308,191)(318,191){1} wire w1; //: /sn:0 {0}(67,213)(82,213){1} wire w44; //: /sn:0 {0}(308,196)(318,196){1} wire w2; //: /sn:0 {0}(103,211)(130,211)(130,135){1} wire w48; //: /sn:0 {0}(438,127)(448,127){1} wire w47; //: /sn:0 {0}(437,254)(447,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(93,211) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) hari (.I0(w43), .I1(w44), .Z(w46)); //: @(329,194) /sn:0 /anc:1 /w:[ 1 1 5 ] /eb:0 //: joint g50 (w46) @(374, 194) /anc:1 /w:[ 2 -1 4 1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Rerouting)" //: /line:"" //: /line:"TkGate will automatically reroute wires that do not leave a gate or joint on the correct" //: /line:"direction. Try grabbing the wire indicated by the arrow in the two examples below and drag" //: /line:"them to the left. In the XOR gate example, two new wire segments are added. In the joint" //: /line:"example, one new segment is added, and the position on the joint is adjusted." //: /line:"" //: /end _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(427,254) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g0 @(405,147) /sn:0 //: /line:"⇐" //: /end //: comment g12 @(141,164) /sn:0 //: /line:"⇐" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(428,127) /sn:0 /anc:1 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(85,173)(100,173){1} wire w32; //: /sn:0 {0}(316,199)(316,214){1} wire w7; //: /sn:0 {0}(85,178)(100,178){1} wire w14; //: /sn:0 {0}(107,216)(122,216){1} wire w16; //: /sn:0 {0}(80,237)(95,237){1} wire w4; //: /sn:0 {0}(99,157)(114,157){1} wire w15; //: /sn:0 {0}(80,232)(95,232){1} wire w19; //: /sn:0 {0}(85,256)(100,256){1} wire w38; //: /sn:0 {0}(335,190)(335,205){1} wire w0; //: /sn:0 {0}(91,132)(106,132){1} wire w3; //: /sn:0 {0}(99,152)(114,152){1} wire w37; //: /sn:0 {0}(333,154)(333,169){1} wire w34; //: /sn:0 {0}(295,168)(295,183){1} wire w21; //: /sn:0 {0}(359,164)(359,179){1} wire w31; //: /sn:0 {0}(314,163)(314,178){1} wire w28; //: /sn:0 {0}(394,182)(394,197){1} wire w20; //: /sn:0 {0}(121,254)(136,254){1} wire w23; //: /sn:0 {0}(356,200)(356,215){1} wire w24; //: /sn:0 {0}(378,168)(378,183){1} wire w36; //: /sn:0 {0}(338,154)(338,169){1} wire w41; //: /sn:0 {0}(416,210)(416,225){1} wire w1; //: /sn:0 {0}(91,137)(106,137){1} wire w25; //: /sn:0 {0}(373,168)(373,183){1} wire w8; //: /sn:0 {0}(121,176)(136,176){1} wire w18; //: /sn:0 {0}(85,251)(100,251){1} wire w35; //: /sn:0 {0}(297,204)(297,219){1} wire w40; //: /sn:0 {0}(414,174)(414,189){1} wire w30; //: /sn:0 {0}(319,163)(319,178){1} wire w17; //: /sn:0 {0}(116,235)(131,235){1} wire w22; //: /sn:0 {0}(354,164)(354,179){1} wire w2; //: /sn:0 {0}(127,135)(142,135){1} wire w11; //: /sn:0 {0}(117,195)(132,195){1} wire w12; //: /sn:0 {0}(71,213)(86,213){1} wire w10; //: /sn:0 {0}(81,197)(96,197){1} wire w13; //: /sn:0 {0}(71,218)(86,218){1} wire w27; //: /sn:0 {0}(399,182)(399,197){1} wire w5; //: /sn:0 {0}(135,155)(150,155){1} wire w33; //: /sn:0 {0}(300,168)(300,183){1} wire w29; //: /sn:0 {0}(396,218)(396,233){1} wire w9; //: /sn:0 {0}(81,192)(96,192){1} wire w26; //: /sn:0 {0}(375,204)(375,219){1} wire w39; //: /sn:0 {0}(419,174)(419,189){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g8 (.I0(w21), .I1(w22), .Z(w23)); //: @(356,190) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w9), .I1(w10), .Z(w11)); //: @(107,195) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g13 (.I0(w33), .I1(w34), .Z(w35)); //: @(297,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g2 (.I0(w6), .I1(w7), .Z(w8)); //: @(111,176) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g1 (.I0(w3), .I1(w4), .Z(w5)); //: @(125,155) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g11 (.I0(w27), .I1(w28), .Z(w29)); //: @(396,208) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g10 (.I0(w24), .I1(w25), .Z(w26)); //: @(375,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g6 (.I0(w15), .I1(w16), .Z(w17)); //: @(106,235) /sn:0 /w:[ 1 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gate Alignment)" //: /line:"" //: /line:"You can align a group of gates by selecting them and then pressing the to align them vertically," //: /line:"and to align them horizontally. Try it on the groups of gates below." //: /end _GGAND2 #(6) g7 (.I0(w18), .I1(w19), .Z(w20)); //: @(111,254) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g15 (.I0(w39), .I1(w40), .Z(w41)); //: @(416,200) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g5 (.I0(w12), .I1(w13), .Z(w14)); //: @(97,216) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g14 (.I0(w36), .I1(w37), .Z(w38)); //: @(335,180) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(117,135) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g12 (.I0(w30), .I1(w31), .Z(w32)); //: @(316,189) /sn:0 /R:3 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(85,137)(95,137){1} wire w19; //: /sn:0 {0}(322,140)(332,140){1} wire w21; //: /sn:0 {0}(321,242)(331,242){1} wire w20; //: /sn:0 {0}(305,242)(288,242)(288,140)(306,140){1} wire w18; //: /sn:0 {0}(162,245)(172,245){1} wire w40; //: /sn:0 {0}(193,243)(203,243){1} wire w17; //: /sn:0 {0}(172,240)(153,240)(153,140)(116,140){1} wire w9; //: /sn:0 {0}(85,142)(95,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(183,243) /sn:0 /anc:1 /w:[ 0 1 0 ] /eb:0 //: comment g1 @(120,178) /sn:0 /anc:1 //: /line:"⇒" //: /end _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(312,140) /sn:0 /anc:1 /w:[ 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Wire Segments)" //: /line:"" //: /line:"Sometime there may not be a free end of two wires you want to connect. Right click on the" //: /line:"wire connected to the AND gate output at the position indicated by the arrow. Select the" //: /line:"Add Wire Segment option from the popup menu. You can now connect" //: /line:"the newly created wire to the buffer inputs." //: /line:"" //: /end _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(106,140) /sn:0 /anc:1 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(311,242) /sn:0 /anc:1 /w:[ 0 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Select the tool and drag the input of the inverter in the circuit below. Drag the input close" //: /line:"to the joint in the middle of the AND gate output and release it. The wire should attach itself to" //: /line:"the joint." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(325,245)(373,245){1} //: {2}(377,245)(468,245){3} //: {4}(375,243)(375,163)(436,163){5} wire w7; //: /sn:0 {0}(421,158)(436,158){1} wire w4; //: /sn:0 {0}(289,247)(304,247){1} wire w3; //: /sn:0 {0}(61,247)(108,247){1} //: {2}(112,247)(199,247){3} //: {4}(110,245)(110,161)(169,161){5} wire w0; //: /sn:0 {0}(289,242)(304,242){1} wire w1; //: /sn:0 {0}(30,244)(40,244){1} wire w8; //: /sn:0 {0}(190,159)(200,159){1} wire w2; //: /sn:0 {0}(30,249)(40,249){1} wire w10; //: /sn:0 {0}(457,161)(472,161){1} wire w5; //: /sn:0 {0}(159,156)(169,156){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g3 (w3) @(110, 247) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(180,159) /sn:0 /anc:1 /w:[ 1 5 0 ] /eb:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w4), .Z(w6)); //: @(315,245) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g11 @(363,264) /sn:0 //: /line:"OR Gate Circuit" //: /end //: comment g10 @(70,271) /sn:0 //: /line:"AND Gate Circuit" //: /end //: joint g6 (w6) @(375, 245) /w:[ 2 4 1 -1 ] //: comment g7 @(413,213) /sn:0 /anc:1 //: /line:"⇓" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Wire Cleanup)" //: /line:"" //: /line:"Select the tool and cut the wire at the position indicated by the arrow in the AND Gate" //: /line:"Circuit. TkGate will automatically remove the wire joint. Now cut the wire at the position indicated" //: /line:"by the arrow in the OR Gate Circuit. The free wire end is automatically deleted." //: /line:"" //: /end _GGOR2 #(6) g5 (.I0(w7), .I1(w6), .Z(w10)); //: @(447,161) /sn:0 /anc:1 /w:[ 1 5 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(51,247) /sn:0 /anc:1 /w:[ 1 1 0 ] /eb:0 //: comment g12 @(123,184) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] wire w14; //: /sn:0 {0}(292,263)(226,263)(226,200)(245,200)(245,140)(178,140){1} wire w16; //: /sn:0 {0}(313,266)(323,266){1} wire w15; //: /sn:0 {0}(282,268)(292,268){1} wire w11; //: /sn:0 {0}(147,137)(157,137){1} wire w12; //: /sn:0 {0}(147,142)(157,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(303,266) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(168,140) /sn:0 /w:[ 1 1 1 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gravity)" //: /line:"" //: /line:"Click on the wire indicated by the arrow in the circuit below and drag it until it is nearly" //: /line:"alligned with the other vertical segment. When you release the wire, \"gravity\" will cause" //: /line:"the two vertical segments to snap together into a single segment." //: /line:"" //: /end //: comment g0 @(562,122) /sn:0 //: /line:"Hint: You can disable the automatic" //: /line:"cleanup features in wire editing by" //: /line:"holding the Alt key while moving wires." //: /end //: comment g12 @(252,158) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] reg crete; //: {0}(7:215,136)(359,136)(359,189){1} //: {2}(361,191)(416,191){3} //: {4}(359,193)(359,203){5} reg ithaca; //: {0}(18:215,183)(259,183){1} //: {2}(263,183)(271,183){3} //: {4}(261,185)(261,238)(278,238){5} reg toledo; //: {0}(-21:213,243)(254,243){1} //: {2}(258,243)(278,243){3} //: {4}(256,241)(256,188)(271,188){5} wire styx; //: {0}(99:355,275)(355,295){1} wire athens; //: {0}(416,186)(356,186){1} //: {2}(71:352,186)(292,186){3} //: {4}(354,188)(354,203){5} wire pheneos; //: {0}(76:357,224)(357,254){1} wire olympus; //: {0}(-15:437,189)(506,189){1} wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: LED g37 (olympus) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGXOR2 #(8) Athena (.I0(ithaca), .I1(toledo), .Z(athens)); //: @(282,186) /w:[ 3 5 3 ] /eb:0 _GGNAND2 #(4) Hermes (.I0(athens), .I1(crete), .Z(pheneos)); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0 _GGNAND2 #(4) Hades (.I0(delphi), .I1(pheneos), .Z(styx)); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0 _GGXOR2 #(8) Zeus (.I0(athens), .I1(crete), .Z(olympus)); //: @(427,189) /w:[ 0 3 0 ] /eb:0 //: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Search)" //: /line:"" //: /line:"You can search your circuit for a wire or gate with a specific name by using the search tool. Click" //: /line:"on the tool to open it. The list of matches will by dynamically updated as you type the target" //: /line:"string. Double click on an entry in the Search Results to go to that object. Try using the search" //: /line:"tool to search for some of the wire and gate names in the circuit below." //: /line:"" //: /end //: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ] //: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 //: SWITCH Thesus (crete) @(198,136) /w:[ 0 ] /st:0 _GGNAND2 #(4) Apollo (.I0(ithaca), .I1(toledo), .Z(delphi)); //: @(289,241) /w:[ 5 3 0 ] /eb:0 //: SWITCH Odyseus (ithaca) @(198,183) /w:[ 0 ] /st:0 //: comment g0 @(588,148) /sn:0 //: /line:"Hint: The search tool will look" //: /line:"in all modules of your circuit for" //: /line:"the target string. Try searching for" //: /line:"a gate named \"hari\"." //: /end //: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ] //: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ] endmodule //: /netlistEnd //: /netlistBegin OLD module OLD(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(624,293)(634,293){1} wire w6; //: /sn:0 {0}(476,150)(516,150)(516,133)(541,133)(541,145)(566,145)(566,195)(492,195)(492,165){1} wire w7; //: /sn:0 {0}(470,428)(480,428){1} wire w46; //: /sn:0 {0}(724,568)(681,568)(681,559){1} //: {2}(683,557)(697,557)(697,519)(722,519){3} //: {4}(679,557)(646,557){5} wire w16; //: /sn:0 {0}(543,101)(553,101){1} wire w14; //: /sn:0 {0}(522,98)(512,98)(512,79)(531,79)(531,46)(478,46){1} wire w19; //: /sn:0 {0}(604,430)(614,430){1} wire w15; //: /sn:0 {0}(512,103)(522,103){1} wire w4; //: /sn:0 {0}(445,152)(455,152){1} wire w38; //: /sn:0 {0}(747,392)(757,392){1} wire w3; //: /sn:0 {0}(475,285)(516,285){1} //: {2}(520,285)(573,285){3} //: {4}(518,283)(518,239)(548,239){5} wire w0; //: /sn:0 {0}(445,147)(455,147){1} wire w37; //: /sn:0 {0}(721,392)(731,392){1} wire w34; //: /sn:0 {0}(744,361)(754,361){1} wire w21; //: /sn:0 {0}(604,468)(614,468){1} wire w43; //: /sn:0 {0}(615,554)(625,554){1} wire w31; //: /sn:0 {0}(624,288)(634,288){1} wire w28; //: /sn:0 {0}(655,291)(696,291){1} //: {2}(700,291)(753,291){3} //: {4}(698,289)(698,245)(728,245){5} wire w23; //: /sn:0 {0}(537,388)(547,388){1} wire w41; //: /sn:0 {0}(492,556)(502,556){1} wire w36; //: /sn:0 {0}(632,363)(642,363){1} wire w20; //: /sn:0 {0}(588,468)(576,468)(576,430)(588,430){1} wire w24; //: /sn:0 {0}(547,360)(524,360){1} //: {2}(522,358)(522,329)(548,329){3} //: {4}(520,360)(482,360){5} wire w1; //: /sn:0 {0}(444,282)(454,282){1} wire w25; //: /sn:0 {0}(564,329)(574,329){1} wire w35; //: /sn:0 {0}(632,358)(642,358){1} wire w8; //: /sn:0 {0}(569,237)(579,237){1} wire w40; //: /sn:0 {0}(554,475)(564,475){1} wire w18; //: /sn:0 {0}(523,477)(533,477){1} wire w30; //: /sn:0 {0}(749,243)(759,243){1} wire w22; //: /sn:0 {0}(451,362)(461,362){1} wire w17; //: /sn:0 {0}(533,472)(517,472)(517,431)(501,431){1} wire w2; //: /sn:0 {0}(444,287)(454,287){1} wire w44; //: /sn:0 {0}(615,559)(625,559){1} wire w12; //: /sn:0 {0}(447,48)(457,48){1} wire w11; //: /sn:0 {0}(447,43)(457,43){1} wire w10; //: /sn:0 {0}(451,357)(461,357){1} wire w27; //: /sn:0 {0}(563,388)(573,388){1} wire w13; //: /sn:0 {0}(492,551)(502,551){1} wire w48; //: /sn:0 {0}(738,519)(748,519){1} wire w5; //: /sn:0 {0}(538,234)(548,234){1} wire w33; //: /sn:0 {0}(728,361)(705,361){1} //: {2}(703,359)(703,330)(729,330){3} //: {4}(701,361)(663,361){5} wire w47; //: /sn:0 {0}(740,568)(750,568){1} wire w29; //: /sn:0 {0}(718,240)(728,240){1} wire w9; //: /sn:0 {0}(470,433)(480,433){1} wire w42; //: /sn:0 {0}(523,554)(541,554)(541,518){1} wire w39; //: /sn:0 {0}(745,330)(755,330){1} wire w26; //: /sn:0 {0}(563,360)(573,360){1} //: enddecls //: comment g4 @(10,552) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(466,150) /sn:0 /w:[ 1 1 0 ] /eb:0 //: frame g51 @(442,505) /sn:0 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(703, 361) /w:[ 1 2 4 -1 ] //: frame g34 @(437,317) /sn:0 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(518, 285) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(544,475) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(559,237) /sn:0 /w:[ 1 5 0 ] /eb:0 //: comment g1 @(542,55) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(533,101) /sn:0 /w:[ 0 1 0 ] /eb:0 //: joint g50 (w46) @(681, 557) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(553,360) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(468,46) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(739,243) /sn:0 /w:[ 1 5 0 ] /eb:0 //: joint g27 (w24) @(522, 360) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(594,430) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(653,361) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(698, 291) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(513,554) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(730,568) /sn:0 /w:[ 0 0 ] //: frame g43 @(617,222) /sn:0 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(553,388) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(472,360) /sn:0 /w:[ 1 1 5 ] /eb:0 //: frame g52 @(597,507) /sn:0 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(437,221) /sn:0 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(491,431) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(636,557) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(737,392) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(734,361) /sn:0 /w:[ 0 0 ] //: comment g24 @(485,442) /sn:0 //: /line:"--->" //: /end //: frame g41 @(436,127) /sn:0 /wi:141 /ht:77 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(594,468) /sn:0 /w:[ 0 0 ] //: frame g40 @(434,30) /sn:0 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(440,416) /sn:0 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(735,330) /sn:0 /w:[ 3 0 ] //: frame g35 @(618,318) /sn:0 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(554,329) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(465,285) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(645,291) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g30 @(723,257) /sn:0 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(728,519) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~ I; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/combinational1.v~000644 001751 001751 00000001363 11140741630 023152 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

" //: /line:"" //: /line:"TkGate uses a Verilog-based discrete event simulator to simulate your circuit description. In this" //: /line:"chapter the basics needed to simulate a combinational circuit will be presented." //: /end //: comment g0 @(191,165) /sn:0 /anc:1 //: /line:"" //: /end //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/ja/tutorials/sequential1.v~000644 001751 001751 00000001340 11140741635 022505 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

" //: /line:"" //: /line:"This chapter builds on the previous chapter about simulating combinational circuits and introduces" //: /line:"simulator features that are useful for simulating sequential circuits." //: /end //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(208,188) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/ja/tutorials/verilog.v~000644 001751 001751 00000005762 11140741640 021731 0ustar00hansenhansen000000 000000 //: version "2.0-a2" //: property prefix = "_GG" //: property title = "texver_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"The TkGate simulator is based on the Verilog hardware description language. As such, any" //: /line:"modules you design using the graphical editor are translated into Verilog before being simulated." //: /line:"You can also write modules directly in Verilog. Note that this chapter is not designed to teach" //: /line:"Verilog, but rather to teach how to include Verilog modules in TkGate." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(145,107) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(55, 80) /bd:[ Li0>a(16/80) Li1>b(32/80) Li2>c(48/80) Li3>d(64/80) Ro0 and set the type to HDL." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(8,9) //: /line:"

Textual Verilog

" //: /line:"" //: /line:"1) Right click on the module below and select Open." //: /end //: LED g5 (w4) @(246,131) /sn:0 /w:[ 1 ] /type:0 foo g0 (.a(w5), .b(w6), .c(w7), .d(w8), .z(w4)); //: @(164, 113) /sz:(55, 80) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>1 Ro0<0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/ja/tutorials/options.v~000644 001751 001751 00000004541 11140741644 021753 0ustar00hansenhansen000000 000000 //: version "2.0-a1" //: property prefix = "_GG" //: property title = "options.v" //: property discardChanges = 1 //: require "tty" //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(219,134) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

" //: /line:"" //: /line:"This chapter introduces some of the options that can be customized in TkGate. Your option settings" //: /line:"are stored in a file named \".tkgate2-preferences\" in your home directory." //: /line:"" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(134,181) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your key beinding style)" //: /line:"" //: /line:"You can the basic key-binding style that you would like to use on the Interface tab of the options dialog" //: /line:"box. Currently you can choose between \"emacs\"-style and \"Windows\"-style. Chosing one of these" //: /line:"options will make key bindings for operations such as cut/paste similar to either emacs or Windows," //: /line:"although key bindings for gate creation operations will remain the same." //: /end //: comment g0 @(10,310) /sn:0 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(116,149) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your personal identification)" //: /line:"" //: /line:"To set your TkGate options, open the options dilaog box by selecting File → Options from the" //: /line:"main menu. Enter your site name and user name in the \"Identity\" dialog box. The values you enter" //: /line:"here will be used on any printed output from TkGate." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/examples000777 001751 001751 00000000000 11145151105 017404 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/tutorials000777 001751 001751 00000000000 11150143335 017616 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/messages.old000644 001751 001751 00000222260 10474724243 020171 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Aug 28 22:38:27 2006 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-2". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## ############################################################################## # # basic strings # b.new New... b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel b.open Open... b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete b.deleteb Delete... b.remove Remove b.apply Apply b.anchor Anchor b.tech Technology b.enable Enable b.disable Disable b.flush Clear ############################################################################## # # Main tab strings # tab.edit Edit tab.editintr Interface tab.simulate Simulate tab.cpath Critical Path # Width of mode selection tabs @tab.width 150 ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Add... mm.delete Delete mm.edit Edit... mm.enable Enable mm.disable Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:File menu.edit 0:Edit menu.tool 0:Tool menu.simulate 0:Simulate menu.module 4:Module menu.interface 0:Interface menu.gate 0:Gate menu.make 0:Make menu.help 0:Help menu.file.new 0:New menu.file.open 0:Open... menu.file.openlib 5:Library Manager... menu.file.save 0:Save menu.file.saveas 0:Save As... menu.file.print 0:Print... menu.file.options 2:Options... menu.file.quit 0:Quit menu.file.cprop 0:Circuit Properties... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Cut menu.edit.copy 3:Copy menu.edit.paste 0:Paste menu.edit.overlay 0:Overlay Paste menu.edit.selall 0:Select All menu.edit.find 0:Find... menu.edit.algnv 6:Align Ver. menu.edit.algnh 6:Align Horz. menu.edit.rotate 2:Rotate menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 10:Bit Shift Right menu.edit.lshift 10:Bit Shift Left menu.edit.ushift 10:Bit Shift Up menu.edit.dshift 10:Bit Shift Down menu.edit.cwrotate 11:Bit Rotate C-W menu.edit.ccwrotate 15:Bit Rotate C-C-W menu.edit.pcwrotate 12:Port Rotate C-C-W menu.edit.pccwrotate 16:Port Rotate C-C-W menu.edit.autobold Boldify Bits menu.edit.resize Resize Bitmap menu.tool.move 0:Move/Connect menu.tool.delg 0:Delete Gate menu.tool.cutw 0:Cut Wire menu.tool.inv 0:Invert menu.tool.bitw 0:Bit Width menu.tool.debug 0:Debug menu.tool.point 0:Point menu.tool.line 0:Line menu.tool.rect 0:Rectangle menu.tool.fillrect 0:Fill Rectangle menu.tool.port 0:Port menu.tool.select 0:Select Region menu.tool.rot0 4:Rot 0 menu.tool.rot90 4:Rot 90 menu.tool.rot180 4:Rot 180 menu.tool.rot270 4:Rot 270 menu.tool.tclshell 0:Tcl Shell menu.simulate.begin 0:Begin Simulation menu.simulate.end 0:End Simulation menu.simulate.addprobe 0:Add/Delete Probe menu.simulate.run 0:Run menu.simulate.pause 0:Pause menu.simulate.step 0:Step Epoch(s) menu.simulate.cycle 5:Step Cycle menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Exec. Script... menu.simulate.load 1:Load Memory... menu.simulate.dump 1:Dump Memory... menu.module.open 0:Open menu.module.close 0:Close menu.module.new 0:New... menu.module.del 0:Delete... menu.module.copy 0:Copy... menu.module.rename 0:Rename... menu.module.claim 1:Claim... menu.module.setroot 1:Set As Root... menu.module.prop 0:Properties... menu.module.interface 0:Interface menu.module.interface.set 0:Set menu.module.interface.edit 0:Edit... menu.gate.addport 4:Add Port menu.gate.ioset 0:Set Type menu.gate.anchor 0:Anchor Selected menu.gate.unanchor 0:Unanchor Selected menu.gate.prop 0:Gate Properties... menu.gate.rep 0:Replicate menu.gate.del 0:Delete menu.gate.settech 0:Set Technology menu.help.about 0:About... menu.help.license 0:License... menu.help.doc 0:Documentation... menu.help.tut 1:Tutorials menu.help.home 1:Home Page menu.help.example 1:Examples ############################################################################# # Scope Menu # menu.scope_file 0:File menu.scope_sim 0:Simulate menu.scope_trace 0:Trace menu.scope_help 0:Help menu.scope_file.ptrace 0:Print Trace... menu.scope_file.close 0:Close menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Add/Delete Probe menu.scope_sim.run 0:Run menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Step Epoch(s) menu.scope_sim.cycle 5:Step Cycle menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Exec. Script... menu.scope_sim.load 1:Load Memory... menu.scope_sim.dump 1:Dump Memory... menu.scope_help.about 0:About... menu.scope_help.license 0:License... menu.scope_help.doc 0:Documentation... mod.intf Interface port.parms Port Parameters port.in In port.out Out port.inout InOut ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gate gm.rgate Reduction gm.msi MSI gm.alu ALU gm.mem Memory gm.mod Module gm.comment Comment gm.frame Frame gm.io.switch Switch gm.io.dip DIP Switch gm.io.ground Ground gm.io.vdd Vdd gm.io.merge Concat gm.io.clock Clock gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Adder gm.alu.mult Multiplier gm.alu.div Divider gm.alu.lshift Left Shift gm.alu.rshift Right Shift gm.alu.arshift Arith. Right Shift gm.alu.roll Roll gm.mem.reg Register gm.mem.ff Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decoder gm.msi.14dec 1-4 Decoder gm.msi.18dec 1-8 Decoder gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut tutorial.prev PREVIOUS tutorial.next NEXT tutorial.chapter CHAPTER LIST tutorial.reload RELOAD ############################################################################## # # Popup menus # pop.make Make pop.tool Tool pop.edit.paste Paste pop.edit.cut Cut pop.edit.copy Copy pop.port.in In pop.port.out Out pop.port.inout InOut pop.wire.addseg Add Wire Segment pop.wire.prop Properties... pop.wire.hidesize Hide Bit Width pop.wire.showsize Show Bit Width pop.wire.hidelabel Hide Label pop.wire.hidealllabel Hide All Labels pop.wire.clearalllabel Clear All Labels pop.wire.showlabel Show Label pop.gate.open Open pop.gate.close Close pop.gate.prop Properties... pop.gate.addport Add Port pop.gate.addin Add Input... pop.gate.addout Add Output... pop.gate.addinout Add BiDir... pop.gate.anchor Anchor pop.gate.settech Set Technology pop.gate.delete Delete pop.gate.ioset Set Type pop.module.new New... pop.module.del Delete... pop.module.copy Copy... pop.module.rename Rename... pop.module.claim Claim... pop.module.setroot Set As Root... pop.module.prop Properties... pop.module.int Edit Interface... pop.simulate.end End Simulation pop.simulate.begin Begin Simulation pop.simulate.addprobe Add/Delete Probe pop.simulate.run Run pop.simulate.pause Pause pop.simulate.step Step Epoch(s) pop.simulate.cycle Step Cycle pop.simulate.break Breakpoint... pop.simulate.script Exec. Script... pop.simulate.load Load Memory... pop.simulate.dump Dump Memory... pop.interface Interface pop.interface.set Set pop.interface.edit Edit... pop.interface.auto Auto Generate... pop.interface.replace Replace pop.igen.type Type pop.igen.side Side pop.igen.size Size pop.igen.delete Delete pop.igen.in in pop.igen.out out pop.igen.inout inout pop.igen.left left pop.igen.right right pop.igen.top top pop.igen.bottom bottom pop.igen.other other ############################################################################## # # Symbol editor strings # symed.bsave Store symed.file File symed.file.load Load Bitmap... symed.file.save Save Bitmap... symed.file.updateclose Close and Update symed.file.discardclose Close and Discard symed.help Help symed.help.about About... symed.edit Edit symed.edit.cut Cut symed.edit.copy Copy symed.edit.paste Paste symed.edit.overlay Overlay Paste symed.edit.rclock Rotate Clockwise symed.edit.rcclock Rotate Counter-Clockwise symed.module Module symed.modes Modes symed.cutpaste Cut/Paste symed.rotate Port Rotation symed.zoom Zoom symed.update Update symed.cancel Cancel symed.tab.normal UnSelected symed.tab.select Selected symed.link Link selected to unselected # width of symbol editor tabs @symed.tab.width 115 ############################################################################## scope.emptymsg Double-click on a wire to add or delete a trace. comment.empty [Double click to add text.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: itype Type: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file File Name db.mod.type Type db.mod.flags Flags db.mod.dataprot Disallow editing of module definition. db.mod.intfprot Disallow all interface changes. db.mod.edprot Disallow edit mode interface changes. db.mod.props Properties db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netlist Netlist db.mod.hdl HDL db.mod.netexpl -begin- Define module using a graphical editor to connect wires between components. -end- db.mod.hdlexpl -begin- Define module using a textural editor to describe behavior in Verilog. -end- ############################################################################# # Error List Dialog box # db.err.caption Error List db.err.explain -fillbegin- I am unable to enter simulation mode due to errors in your circuit. Select an error message to see the error location. -end- ############################################################################# # Net Dialog Box # db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.type Net Type db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # # New circuit dialog box # db.newcirc.cap New Circuit db.newcirc.exp -fillbegin- Discard the current circuit and start editing a new circuit. -end- db.newcirc.file File Name db.newcirc.topname Top Module Name ############################################################################## # Gate dialog box # @db.gate.tabwidth *80 db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.side Side db.gate.gtype Gate Type db.gate.gname Gate Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.range Bit Range db.gate.memfilenam Memory File db.gate.modname Function db.gate.general General db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Delay db.gate.parameters Parameters db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.catdiruse Port Placement db.gate.edit Edit db.gate.delete Delete db.gate.add Add db.gate.cat.asc.hdr Ascending db.gate.cat.dec.hdr Decending db.gate.cat.asc.exp -fillbegin- Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir Signal Direction db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Multi-Input db.gate.cat.singin.hdr Single-Input db.gate.cat.tran.hdr Bidirectional db.gate.cat.auto.exp -fillbegin- Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- Allow bidirectional (tran) signal flow. Can not be connected to switches or registers. -end- db.gate.tab.General.cap General Properties db.gate.tab.Ports.cap Port Properties db.gate.tab.Delay.cap Delay Properties db.gate.tab.Parameters.cap Module Parameters db.gate.tab.CLOCK.cap Clock Properties db.gate.tab.SWITCH.cap Switch Properties db.gate.tab.DIP.cap DIP Properties db.gate.tab.TAP.cap Tran Properties db.gate.tab.RAM.cap RAM Properties db.gate.tab.ROM.cap ROM Properties db.gate.tab.MODULE.cap Module Properties db.gate.tab.FRAME.cap Frame Properties db.gate.tab.LED.cap LED Properties db.gate.tab.AND.cap AND Properties db.gate.tab.OR.cap OR Properties db.gate.tab.XOR.cap XOR Properties db.gate.tab.MUX.cap Mux Properties db.gate.tab.DEMUX.cap Demux Properties db.gate.tab.CONCAT.cap Concat Properties db.gate.tab.COMMENT.cap Text Properties db.gate.tab.General.exp -fillbegin- View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- Set detailed type specific properties of a gate here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Value db.gate.mparm.exampleA -begin- This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameters can be customized for each instance though this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.mux.dataorder Input Ordering db.gate.mux.ord1.hdr Left-to-Right db.gate.mux.ord2.hdr Right-to-Left db.gate.mux.ord1.exp -fillbegin- Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- Order MUX inputs from right to left. -end- db.gate.demux.dataorder Output Ordering db.gate.demux.ord1.hdr Left-to-Right db.gate.demux.ord2.hdr Right-to-Left db.gate.demux.ord1.exp -fillbegin- Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- Order DEMUX outputs from right to left. -end- db.gate.mux.select Selector Style db.gate.mux.sel1.hdr Selector on Left db.gate.mux.sel2.hdr Selector on Right db.gate.mux.sel1.exp -fillbegin- Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- Place the data selector on the right side of the gate. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse Extender Bar Use db.gate.aox.use.hdr Extender Bars db.gate.aox.nouse.hdr No Extender Bars db.gate.aox.use.exp -fillbegin- Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LED Type db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Bar Graph db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- Single-lamp led display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- Signal bits directly control led segments. -end- db.seq.back db.hdl.savecap Multiple Modules db.hdl.saveexp -fillbegin- The text buffer for the module you have just edited appears to contain more than one module definition. Please select one of the three actions described to the right. -end- db.hdl.autoedit Auto Edit db.hdl.split Split db.hdl.comment Comment db.hdl.cancel Cancel db.hdl.ignore Ignore db.hdl.autoeditcap Name Mismatch db.hdl.autoeditexp -fillbegin- The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- cpath.cloops -fillbegin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the gates in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # print.outto Output to print.printer Printer print.file File print.prcmd Print Command print.prname Printer print.filename File Name print.epssave Save as Encapsulated Postscript. print.doctit Document Title #print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.range Range Selection print.scaleselect Scale Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.end End print.outsel Output Selection print.filesel Output to file print.printersel Output to printer print.pageset Page Setup print.modulesel Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Print print.printtrace.cap Print Trace print.printcirc.cap Print Schematic print.printcirc.out.exp -fillbegin- Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output Output print.tab.page Page print.tab.content Content ############################################################################## # # Options dialog # # Width of options dialog box (not including image sidebar) @opt.width 555 # Height of options dialog box @opt.height 450 # Width of tabs on options dialog box @opt.tabwidth 80 # Number of columns in list of toolbars @opt.tool.columns 3 # Width of columns in list of toolbars @opt.tool.colwidth 30 opt.general General opt.interface Interface opt.toolbars Toolbars opt.editor HDL opt.print Print opt.simulate Simulate opt.library Libraries opt.analysis Analysis opt.color Color opt.html HTML opt.debug Debug opt.identity Identity opt.site Site Name opt.username User Name opt.libname Library Name: opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.background Background opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.balloon Enable Help Balloons opt.safeSave Do safe file saving opt.saveCells Include cells in save files opt.showimage Show side-bar images in dialog boxes opt.novice Novice Mode opt.ckpoint Do Checkpointing opt.freq Interval opt.beak Enable Special Modes opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.vpopupdelay Pop-Up Delay opt.initscript Global Initialization script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Technology Files opt.devfilepath VPD (Virtual Periperal Device) File Path opt.vlibpath Verilog Library Path opt.vlibnames Base Libraries opt.display Display opt.input Input opt.security Security opt.undolen Max Undo opt.keybind Key Binding Style opt.useless Enable Useless Features opt.features Basic Features opt.simbase Basic Simulator Options opt.simclock Clock Options opt.cpopts Critical Path Options opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.general.fontset Font Set opt.simulator.noglitch Enable simulator glitch suppression. opt.simulator.err Error Handling opt.simulator.stopany Cancel simulation on any warnings. opt.simulator.showall Always display warnings. opt.simulator.showiferr Display warnings only if with errors. opt.simulator.ignore Ignore all warnings. opt.tool.file File opt.tool.edit Edit opt.tool.gateopt Rotation/Alignment opt.tool.gateprop Gate opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Mode opt.tool.module Module opt.tool.tech Technology opt.tool.simctl Simulator Control opt.tool.simaux Simulator Commands opt.tool.symmode Mode opt.tool.symedit Cut/Paste opt.tool.symport Ports opt.tool.symshift Bit Shift opt.tool.symopr Bit Ops opt.editor.features Basic Editor Features opt.editor.format Enable Automatic Indenting opt.editor.colorize Enable Code Colorization opt.editor.comments Comments opt.editor.strings Strings opt.editor.reserved Reserved Words opt.editor.gateword Built-in Gates opt.editor.instword Module Instances opt.editor.taskword System Tasks opt.editor.color Color opt.editor.bold Bold opt.editor.italic Italic opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin..end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.vercheck -begin- Periodically check for new versions of tkgate over the Internet. Do not enable unless you have continuous access to the Internet. -end- opt.general.cap General Options opt.editor.cap HDL Text Editor opt.interface.cap Interface Options opt.toolbars.cap Toolbar Options opt.print.cap Print Options opt.analysis.cap -begin- Critical Path Options -end- opt.simulator.cap Simulator Options opt.security.cap Security Options opt.color.cap Color Options opt.html.cap HTML/HTTP Options opt.debug.cap Debug Options opt.library.cap Library Options opt.sec.execlevel The $tkg$exec() system task is opt.sec.exec fully enabled. opt.sec.regexec enabled only for registered functions. opt.sec.noexec disabled. opt.sec.simfeatures Simulator Features opt.sec.send Enable the $tkg$command() system task. opt.sec.open Enable the $fopen() system task. opt.sec.writemem Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle Security Violation Handling opt.sec.stop Stop simulator when disabled feature is used. opt.sec.warn Display warning message when disabled feature is used. opt.sec.ignore Ignore attempted usage of disabled features. opt.html.linkopts Link Options opt.html.browser Browser Command opt.html.email e-Mail Command opt.color.editwin Edit Window Colors opt.color.scopewin Scope Window Colors opt.vlibadd.cap Add Library opt.vlibadd.exp -fillbegin- Enter the name of a TkGate Verilog library. Libraries named in the autoload list will be automatically loaded on startup. -end- opt.editor.exp -fillbegin- Set options for the HDL text editor. -end- opt.general.exp -fillbegin- Set personal identification and basic TkGate options on this page. The personal identification will be used on printed output. -end- opt.interface.exp -fillbegin- Set options controlling the look and feel of the interface. -end- opt.toolbars.exp -fillbegin- Specify which toolbars to display. -end- opt.print.exp -fillbegin- Set default printer options on this page. -end- opt.analysis.exp -fillbegin- These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- These options control the functioning of the simulator. -end- opt.library.exp -fillbegin- Set search paths for User Device and Verilog library files. -end- opt.security.exp -fillbegin- Set the simulator security options by enabling or disabling features that may be a risk when simulating circuits from untrusted sources. -end- opt.color.exp -fillbegin- Use these options to set the color scheme to use in TkGate. -end- opt.html.exp -fillbegin- Set options pertaining to html commands in tkgate circuit comments. -end- opt.debug.exp -fillbegin- Debugging options can be set here. -end- opt.gen.basetoolbar Core Editor Toolbars opt.gen.simtoolbar Simulation Mode Toolbars opt.gen.symedtoolbar Symbol Editor Toolbars opt.bbar.restore Restore Page Defaults opt.bbar.restoreall Restore All Defaults ############################################################################## # # Interface generator # igen.type Type igen.side Side igen.size Size igen.modname Module Name: igen.resort Re-sort igen.add Add igen.delete Delete igen.edit Edit igen.in in igen.out out igen.inout inout igen.left left igen.right right igen.top top igen.bottom bottom igen.other other igen.mod Use ports used in module only. igen.int Use ports from exisiting interface only. igen.modint Use both module and interface ports. igen.portsel Port Selection igen.portpos Port Positions igen.portpos.keep Keep exiting port positions when possible. igen.portpos.renew Regenerate all port positionings. igen.caption Generate Interface igen.description -begin- Create a new interface for a module. -end- module.props Module Properties ipanel.plist Port List ipanel.props Interface Properties ipanel.itype.change Change Type... ipanel.itype.edsymbol Edit Symbol... ipanel.block Block ipanel.symbol Symbol ipanel.autogen Auto Generate... ipanel.itype.select Interface Type ipanel.itype.selectexp -begin- Use "block" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ipanel.block.description Block Interface ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label Block resize port position handling: ipanel.ppos.fix Fixed ipanel.ppos.scale Scaled ipanel.ppos.grid Grid ipanel.warn.toblock -begin- You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.claim Claim Module blklst.to To blklst.from From blklst.name Name blklst.new.cap Create New Module blklst.del.cap Delete Module blklst.copy.cap Copy Module blklst.rename.cap Rename Module blklst.claim.cap Claim Module blklst.setroot.cap Set Root Module blklst.new.exp -fillbegin- Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- Make the specified module the top-level module. -end- find.label Find Objects find.exp -fillbegin- Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase Ignore Case find.result.module Module find.result.type Type find.result.name Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Search Options find.results Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Contains... find.qual.begins Begins with... find.qual.ends Ends with... find.qual.matches Matches... find.dom.label Look for objects in: find.dom.gates Gates find.dom.nets Nets find.dom.text Comment Text find.search Find: find.target Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.label Circuit Properties circ.ident Identification circ.filev File Version circ.file File Name circ.title Circuit Title circ.discchg Do not warn about discarding changes. circ.extbar Use extender bars. circ.autostart Enable auto-start of simulation. circ.iniscript Initialization Scripts circ.noscript No script files selected. circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.script.cap Edit Script circ.script.label Edit script name: circ.vlib.cap Edit Library circ.vlib.label Library script name: @circ.tabwidth 100 @circ.width 650 @circ.height 400 circ.general General circ.library Libraries circ.script Script circ.exp -fillbegin- View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- ############################################################################## # # Library Manager # libmgr.cap Library Manager libmgr.library Library libmgr.description Description libmgr.status Status libmgr.status.load Loaded libmgr.status.unload Not Loaded libmgr.status.loadp [Loaded] libmgr.status.unloadp [Not Loaded] libmgr.exp -fillbegin- Select libraries to be loaded or unloaded. -end- libmgr.load Load libmgr.unload Unload libmgr.unloadall Unload All libmgr.notedit -fillbegin- Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # sim.breakpt Breakpoint sim.recursive -fillbegin- Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Gate(s) are anchored and can not be moved. err.protdata Can not modify contents of protected or library module. err.badfind Can't find target '%s'. err.badopendel Can't delete open module. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.badinadd Can't add any more inputs to selected gate. err.badoutadd Can't add any more outputs to selected gate. err.badinoutadd Can't add any more inout pins to selected gate. err.badpinchg Can't change pin types on selected gate. err.badnetname Illegal characters in identifier deleted. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with primitive gate name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Connection refused because wires are part of the same net. err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Connection refused because bit widths do not match. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Unable to exectute printer command '%s'. err.badpsopen Unable to open file '%s' for postscript output. err.badid Illegal identifier '%s'. err.protintf Can't modifiy protected interface on module '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Too many breakpoints. Maximum is %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.badedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Can't find net '%s'. err.sim.nogate Can't find gate '%s'. err.sim.badbin Illegal charcter in binary constant '%s'. err.sim.notswitch Gate '%s' is not a switch, dip or register. err.sim.badcmd Unrecognized command '%s' in simulation script. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.run Run-time Error err.sim.cmd Internal Command Error err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Unable to open input file '%s'. err.badlibopen Unable to open library file '%s'. err.nomark Please set a mark with the left mouse button before selecting a gate type. err.badgate Unknown gate type '%s'. err.badportadd Can't add ports to gates of this type. err.modmissing HDL module text missing for module "%s". err.modtoomany Excess module definitions in module "%s". err.modmismatch Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -fillbegin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot Can't close top-level module. Use quit. err.editonly Command not valid when in simulation mode. err.simonly Command valid only in simulation mode. err.deltop Can not delete top-level module '%s'. err.delprot Can not delete protected module '%s'. err.nodel No deletable selection. err.modnotdef Module '%s' is undefined. err.moddef The module '%s' already exists. err.primredef Built-in element name '%s' can not be redefined. err.noprop Selected gate has no editable properites. err.openscript Can't open simulation script file '%s' err.oldversion Loaded file with obsolete version number %s (current version is %s). err.futureversion Loaded file saved by future tkgate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.nomodule No selected module. err.nomodop No suitable modules for operation. err.protexec Attempted execution of protected command '%s' in $tkg$exec(). err.backupfail Unable to create backup file '%s'. err.yy.badprop Ignoring unknown circuit property '%s'. err.yy.baddata Bad data type supplied for circuit property '%s'. err.yy.nosym No current module symbol. err.yy.badicon Bad icon type '%s'. err.yy.toomuchdata Too much icon data. err.yy.nosyminst Missing symbol %d on instance %s of %s. err.yy.badmodprop Ignoring unknown module property '%s'. err.yy.badmoddata Bad data type supplied for module property '%s'. err.yy.badprim Unknown primitive name '%s'. err.yy.nonet Undeclared net '%s'. err.yy.bogussave Bogus save data detected. circuit may be damaged. err.yy.pinformat Illegal pin name format '%s'. err.yy.pinname Pin name '%s' not defined for gate type '%s' err.yy.nonetpos No net for position %d on gate %s. err.corruptnewsave -fillbegin- TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- File was created by tkgate %s, and may not be readable by versions earlier than current version (%s) if you save. -end- ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Selected %s named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.iselwire Selected port '%s' on block '%s'. msg.iselgate Selected %s named '%s' (huh? this message should be impossible). msg.iselblock Selected module interface for '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Found gate named '%s'. msg.foundwire Found wire named '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Saved circuit to '%s'. msg.reallynew Circuit has been modified. Do you really want to discard your changes and create a new circuit? msg.reallyquit Circuit has been modified. Do you really want to exit? msg.notlib Module '%s' is not a library module. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Port size mismatch on input port '%s'. verga.err.OUTPORT Port size mismatch on output port '%s'. verga.err.FLOATNET Net '%s' has no drivers (floating net). verga.err.DIRECTCONN Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR Attempt to write to memory %s with unknown address. verga.err.MEMBITS Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG Array '%s' used in expression without index. verga.err.BADARRAYLHS Array '%s' used without index on left-hand-side. verga.err.BADCLOSE Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG Bad gate instance range expression. verga.err.BADARGVALUE Bad value for argument %s in task %s. verga.err.DIVZERO Divide by zero. verga.err.NODIV Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT Event wait on assign is illegal. verga.err.PROTTASK Execution of protected system task '%s' blocked. verga.err.NEEDIDENT Expecting identifier for argument %s of task '%s'. verga.err.BADOP Expression operator error in '%s'. verga.err.NOREAD Failed to load source file '%s'. verga.err.MEMFILE Failed to open memory file '%s'. verga.err.WRONGMOD Found module '%s' when expecting '%s'. verga.err.NOTPARM Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR Illegal address range on port '%s'. verga.err.BADADDRSPEC Illegal address range specification '%s'. verga.err.BADCHAR Illegal character (%s) '%s'. verga.err.BADEVENT Illegal event control expression. verga.err.BADCONSTOP Illegal operator in constant expression. verga.err.BADXOP Illegal operator in expression. verga.err.NETREDEF Illegal redefinition of net '%s'. verga.err.BADINOUT Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF Instance of undefined module '%s'. verga.err.BADASGNLHS Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS Invalid left-hand-side in assignment. verga.err.BADOUT Invalid output assignment. verga.err.NOTREG Memories must be declared as register. verga.err.PORTMIX Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE More than one default: in case statement. verga.err.NOMEM No current memory in memory file read. verga.err.BADCMD No such command '%s'. verga.err.CMDNOTNET No such net '%s' in '%s' command. verga.err.MEMNONBLK Non-blocking assignments to memories not implemented. verga.err.NOTPPORT Parameter '%s' is not declared as a port. verga.err.REDEFP Parameter redefines identifier '%s'. verga.err.PORTNOTDEF Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE Range on port '%s' is not numeric. verga.err.BADARRAYRNG Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF Redefinition of dynamic module '%s'. verga.err.REDEF Redefinition of identifier %s. verga.err.PROTTASKSTOP Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM Specified net '%s' is not a memory. verga.err.CMDNOTMEM Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX Syntax error. verga.err.TOOFEWPP Too few parameter ports on instance %s. verga.err.OPENTOOMANY Too many files open in task '%s'. verga.err.TOOMANYPP Too many parameter ports on instance %s. verga.err.NOTOP Top-module '%s' not defined. verga.err.BADOPEN Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET Undefined net '%s' in event control expression. verga.err.NOTASK Undefined task '%s'. verga.err.NOTDEF Undefined variable '%s'. verga.err.BADRANGE Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP Unimplemented primitive gate instance type. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Write to closed descriptor. verga.err.PRIMPTCOUNT Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS Wrong number of arguments in '%s' command. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' called with wrong number of arguments. verga.err.BADSTART Illegal start value in task '%s'. verga.err.BADSTOP Illegal stop value in $readmemb. verga.err.SPECTASKUSG Task %s must be used in a specify block. verga.err.BADSPECTASK Task %s can not be used in a specify block. verga.err.TIMING Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP Loops in modules with path-delay specification are unsupported. verga.err.TASKREDEF Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC Task '%s' used as function. verga.err.FUNCASTASK Function '%s' used as task. verga.err.TASKBADTYPE Non-register type used in task or function. verga.err.TASKBADPORT Only input ports are allowed on functions. verga.err.IE_TASK Task definition '%s' found outside module - internal error. verga.err.IE_NONET Failed to find net '%s' - internal error. verga.err.IE_BADTYPE Bogus port type for port '%s' - internal error. verga.err.IE_NOOP Can not find operator description -- internal error. verga.err.IE_NONEXPCTL Event control @(*) applied to non-expression - internal error. verga.err.IE_NONSTATCTL Event control @(*) applied to non-statment - internal error. verga.err.IE_BADEXP Unexpected expression type %s - internal error. verga.err.IE_BADVAR Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE Unexpected internal state at %s - internal error. verga.err.IE_RETURN Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # Balloon Help # ho.net.in Single-Bit Input ho.net.out Single-Bit Output ho.net.inout Single-Bit Inout ho.net.in2 Multi-Bit Input ho.net.out2 Multi-Bit Output ho.net.inout2 Multi-Bit Inout ho.net.wire Single-Bit Wire (Name Visible) ho.net.wire2 Multi-Bit Wire (Name Visible) ho.net.hwire Single-Bit Wire (Name Hidden) ho.net.hwire2 Multi-Bit Wire (Name Hidden) ho.net.reg Single-Bit Reg ho.net.reg2 Multi-Bit Reg ho.opt.tool.file Save, load of circuit files ho.opt.tool.edit Cut, Paste and Find operations ho.opt.tool.gateopt Gate rotation and alignment operations ho.opt.tool.gateprop Basic editing of gates ho.opt.tool.undo Undo and redo operations ho.opt.tool.zoom Zoom in and zoom out ho.opt.tool.mode Select the editing tool ho.opt.tool.module Create, delete, rename,etc. of module definitions ho.opt.tool.tech Select default technology for gates ho.opt.tool.simctl Start, stop and pause of simulator ho.opt.tool.simaux Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.symmode Selecting editing tool in symbol editor ho.opt.tool.symedit Cut and paste operations for symbol editor ho.opt.tool.symport Port rotation operations for symbol editor ho.opt.tool.symshift Shift the bit map or portion of bitmap ho.opt.tool.symopr Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.saveas Save circuit to specified file. ho.print Print current circuit. ho.library Open the library manager. ho.symed.tab.normal -begin- Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- Edit the selected symbol bitmap. -end- ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new gate Move gates and wires Connect wires By double-clicking you can: Edit gate, wire and port properties Edit comment text -end- ho.delgat -begin- Delete Gate - Use this tool to delete gates. -end- ho.cutw -begin- Cut Wire - Use this tool to cut wires. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from gate ports. -end- ho.bitw -begin- Net Attributes - Use this tool to change the attributes of a net. The bit size and wire type of nets selected with this tool will be changed to the those shown in the drop-down boxes to the right. -end- ho.ipanel.prot -begin- Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Open the selected module. ho.mod.close Close the current module. ho.mod.new Create a new module type. ho.mod.del Delete a module. ho.mod.copy Copy a module. ho.mod.rename Rename a module. ho.mod.claim -begin- Convert a library module to a regular module. -end- ho.mod.setroot -begin- Designate a module to be the root module. -end- ho.mod.type.allparts Set of Libraries ho.mod.type.partlib Library ho.mod.type.part Library module ho.mod.type.unknown Unknown module type ho.mod.type.unused Set of unused modules ho.mod.type.conflict Module recursion ho.mod.type.root Top-level module ho.mod.type.netlist Netlist module ho.mod.type.Lnetlist Netlist module (locked) ho.mod.type.hdl HDL module ho.mod.type.Lhdl HDL module (locked) ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.tab.edit -begin- Primary editing mode. -end- ho.tab.interface -begin- Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Find critical paths in a circuit. -end- ho.log -begin- Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. Breakpoints can be edited in both simulation mode and edit mode. -end- ho.simexec -begin- Manage the set of active scripts. -end- ho.simoptions -begin- Set various options that control the simulation. -end- ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.sim.break -begin- Enter a simulator breakpoint. Breakpoints are expressions which cause the simulator to pause execution when they become true. Currently only simple expressions with a single relational operator such as "w1 == 0" or "w7 != 8" are supported. Expressions such as "w8" or "!w2" may also be used to test for non-zero and zero values respectively. -end- ho.f.modlist -begin- OBSOLETE -end- ho.f.modlisttab -begin- List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- List of nets in the current module. The symbol to the left of the name indicates whether the net is single bit (green) or multi-bit (red). An "A" shown in the symbol indicates that the net name is marked as visible. -end- ho.ports -begin- List of ports on the interface of the module displayed in the edit window. The symbol before the port indicates the direction of the port. -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, tkgate is in edit mode. If the quadrapedal AND gate is shown, tkgate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from tkgate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TKGate. ho.print.selcur Print only the current module in the TKGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.autostart -begin- If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.cmd.bitw -begin- Wires selected with the ribbon cable tool will be set to this bit width. -end- ho.edgat.signam -begin- The name of the selected signal on the selected gate. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the gate. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected gate. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected gate. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Type of the gate. ho.edgat.gname Name of this gate instance. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx X coordinate of gate. ho.edgat.gy Y coordinate of gate. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint Print trace logic trace. ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.tech -begin- List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.name -begin- User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- The name of the site where tkgate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this option, the useless features checkbox will no longer appear in this dialog box. The only way to see the useless features again will be to edit your .tkgate2-properties file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when simulation of any circuit is initiated. Do not use this for circuit specific scripts, use the circuit properties instead. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. -end- ho.opt.keybind -begin- Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- Default technology for new gates. Affects delay of gates. To change the technology of a specific gate, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this gate. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.symed.point -begin- Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift Shift selected pixels right. ho.symed.lshift Shift selected pixels left. ho.symed.ushift Shift selected pixels up. ho.symed.dshift Shift selected pixels down. ho.symed.cwrotate Rotate selected pixels clockwise. ho.symed.ccwrotate Rotate selected pixels counter-clockwise. ho.symed.autobold Make selected image bold. ho.symed.resize Resize the image editor. ho.tool.currot -begin- Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotate selected gate(s) counter-clockwise. ho.tool.brotate Rotate selected gate(s) clockwise. ho.tool.valgn Align selected gate(s) vertically. ho.tool.halgn Align selected gate(s) horizontally. ho.tool.cut Cut selection. ho.tool.copy Copy selection. ho.tool.paste Paste from cut buffer. ho.tool.find Find gate, wire or text. ho.tool.addport Add a port to the selected gate. ho.tool.anchor Anchor the selected gate(s). ho.tool.unanchor Unanchor the selected gate(s). ho.tool.replicate Replicate a gate. ho.tool.delete Delete the selection. tkgate-2.0-b10/locale/en/unused.txt000644 001751 001751 00000002246 10625170511 017715 0ustar00hansenhansen000000 000000 b.bitw b.deleteb b.disable b.enable b.flush b.open break.tab circ.library circ.noscript circ.really db.hdl.comment db.net.inets db.seq.back db.seq.next err.bkpt.badexp err.bkpt.badnet err.bkpt.badval err.bkpt.toomany err.internal.nomod err.modmissing err.openscript err.sim.badbin err.sim.badcmd err.sim.badedge err.sim.nobkpt err.sim.nogate err.sim.noincl err.sim.notswitch err.sim.syntx err.simonly find.options ho.hdl.commentexp ho.opt.debug ho.opt.init ho.opt.outmove ho.sim.break ho.symed.fillrect ho.symed.line ho.symed.point ho.symed.port ho.symed.rect ho.symed.select igen.other igen.resort ipanel.block.description ipanel.itype.change ipanel.itype.edsymbol ipanel.ppos.grid ipanel.symbol.description ipanel.warn.toblock ipanel.warn.tosymbol opt.initscript print.doctit print.outsel print.outto print.printcirc.page.exp print.tab.page sim.breakpt symed.bsave symed.cancel symed.cutpaste symed.edit symed.edit.copy symed.edit.cut symed.edit.overlay symed.edit.paste symed.edit.rcclock symed.edit.rclock symed.file symed.file.discardclose symed.file.load symed.file.save symed.file.updateclose symed.help symed.help.about symed.modes symed.module symed.rotate symed.update symed.zoom tkgate-2.0-b10/locale/en/all.txt000644 001751 001751 00000047714 10625164434 017202 0ustar00hansenhansen000000 000000 menu.scope_help.doc ho.opt.html.browser ho.cmd.bitw ho.mod.type.unused menu.edit.rotate verga.err.BADOP db.net.type b.find opt.sec.enqueue blklst.new.cap ipanel.ppos.fix err.netconfgat print.papsz verga.err.BADXOP ho.symed.dshift db.gate.cat.tran.exp @circ.tabwidth db.mod.edprot menu.edit.rshift msg.foundwire ho.ipanel.proted b.close opt.sec.noexec err.misserr err.yy.badicon ho.edgat.signam gm.comment opt.safeSave menu.scope_trace opt.unknown find.dom.label ho.print.parttrace find.dom.text db.net.in db.mod.intfprot symed.rotate menu.simulate err.netconfkw db.gate.demux.ord2.exp symed.modes pop.interface.set menu.edit.overlay opt.html.exp ho.simstep ho.net.in verga.err.IE_BADSTATE db.gate.mux.ord1.exp symed.help igen.left err.netbcrename ho.opt.sec.open ho.techbut db.gate.mux.select db.mod.islib.1 db.gate.ff.normal.exp ho.net.inout pop.wire.clearalllabel err.noprop miles.msg2 ho.print.parttraceend mm.disable gm.msi print.landscape opt.keybind ho.save gm.rgate.xor ho.opt.tool.file db.gate.demux.sel1.hdr db.gate.aox.nouse.hdr pop.module.setroot opt.editor.comments ho.symed.resize db.gate.demux.dataorder db.gate.bitws gm.gate.pmos print.range igen.delete verga.err.NOTMEM symed.help.about opt.blockDropConnect err.protexec ho.mod.type.allparts db.gate.cpbreak symed.edit.copy pop.simulate.addprobe igen.portpos.keep err.closeroot err.badgate ho.net.in2 menu.module.prop db.gate.tab.Ports.exp mm.add print.outto ho.edgat.memfile ho.circuit.extbar db.gate.tab.SWITCH.exp db.gate.mux.sel1.exp b.new port.in opt.color.scopewin libmgr.description msg.needsel ho.opt.tool.undo verga.err.BADAUTORNG ho.net.out2 db.gate.tab.Parameters.exp db.gate.port menu.edit.zoomout pop.simulate.end print.printersel err.deltop msg.iselblock libmgr.library ho.f.modlist db.gate.tab.FRAME.exp err.oldportact pop.simulate.run pop.igen.delete opt.general.cap circ.title db.gate.tab.Parameters.cap opt.sec.execlevel ho.opt.sec.ignore ho.status.msg menu.simulate.cycle err.bkpt.badnet verga.err.BADEDGEEVENT ho.opt.tool.symopr verga.err.CMDNOTMEM opt.logic0 ho.opt.sim.err.stopany menu.scope_sim.step err.sim.badbin ho.opt.ckall menu.scope_file.ptrace ho.contver ho.edgat.duty print.estpg db.gate.tab.Delay.cap db.gate.details opt.simulator.ignore ho.opt.tool.symmode db.newcirc.directory b.enable ho.symed.fillrect ho.mod.type.unknown verga.err.REPCASE opt.contver opt.editor.reserved circ.filev msg.iselwire ho.tool.replicate menu.tool.rot0 err.badopendel verga.err.MEMFILE opt.editor.strings ho.opt.html.email db.gate.tab.DIP.exp menu.file opt.tool.gateopt opt.security.cap ho.status.logo db.gate.tab.LED.cap b.deleteb miles.msg5 ho.edgat.gtype ho.print verga.err.REDEF opt.gen.basetoolbar opt.bbar.restoreall db.gate.led.hex.hdr libmgr.unloadall print.printcirc.mod.exp ho.opt.sim.noglitch db.seq.next pop.interface symed.link err.yy.nosyminst ho.circuit.autostart db.mod.smod.0 opt.toolbars opt.tool.undo opt.editor.colorize module.props ho.tab.interface menu.help.tut @portlist.in2 ho.opt.tool.tech cp.delay err.backupfail err.yy.nonet menu.tool.fillrect opt.maxpath @find.type.net db.gate.ports db.mod.lmod.0 menu.module.new opt.background gm.io.leddec print.ok err.sim.notswitch ho.opt.sim.err.showall opt.simulate blklst.claim verga.err.OUTPORT err.yy.badmodprop ho.symed.ccwrotate ho.move @opt.tool.colwidth find.label verga.err.PATHDINOUT db.gate.cat.auto.hdr b.in b.dismiss verga.err.BADCLOSE ho.symed.tab.select db.gate.demux.sel2.hdr opt.posedge circ.library circ.timescale.unit err.editonly ho.opt.ckspec db.mod.lmod.1 err.nodel miles.msg4 menu.scope_help.about gm.alu.add libmgr.unload err.badrange db.gate.led.seg.exp db.gate.cat.singin.hdr db.newcirc.topname opt.modports err.nomodop ho.tool.brotate ho.mod.setroot ho.ipanel.fix circ.extbar err.noconn ho.opt.sim.err.ignore db.hdl.autoeditcap err.yy.nonetpos ho.print.parttracestart verga.err.CLSDWRITE db.newcirc.file ho.mod.del ho.net.reg verga.err.USAGE print.prcmd db.gate.led.type pop.simulate.load mm.delete find.results opt.features db.gate.mparm.exampleA symed.file.discardclose circ.general msg.sim.chgtoroot ho.opt.sim.tech db.gate.mparm.exampleB db.gate.tab.CLOCK.exp ipanel.block.description err.badhex db.gate.demux.select db.gate.tab.MUX.exp print.prname db.gate.tab.CONCAT.cap opt.editor.color find.qual.begins msg.selgate menu.gate.addport opt.overstep blklst.copy.cap ho.opt.ckover ho.new verga.err.IE_BADVAR db.hdl.autoedit ho.opt.ssave verga.err.PRIMPTCOUNT menu.module.interface print.4up opt.editor.movesel pop.interface.edit @tab.width b.anchor gm.mod tutorial.chapter db.hdl.savecap verga.err.BADLHS ho.opt.ckptfreq verga.err.IE_NONET db.gate.iotype db.mod.dataprot symed.file.save ipanel.plist db.gate.tab.CONCAT.exp menu.edit.copy find.qual.matches @portlist.in err.bkpt.toomany ho.symed.tab.normal pop.simulate.dump blklst.to ho.ipanel.protint print.printer opt.toolbars.exp ho.opt.debug ho.edgat.bitlab verga.err.IE_NONSTATCTL verga.err.NOTPARM ho.symed.ushift ho.opt.bat ho.opt.beak ho.showxhair ho.opt.tool.gateopt opt.vlibadd.cap verga.err.ASGNEVENT ho.tool.cut pop.wire.showsize ho.opt.lib.vpath ho.opt.editor.beginindent ho.net.out pop.module.int ho.edgat.hide ho.opt.editor.movesel err.modtoomany menu.simulate.script db.net.out b.edit tutorial.prev verga.err.NOTDEF opt.editor.features ho.symed.rshift ho.edgat.gy verga.err.SPECTASKUSG pop.interface.auto opt.tool.simaux err.badconbitw print.sel db.hdl.comment db.gate.mux.ord2.exp symed.edit.overlay print.opts ho.undo ho.net.wire verga.err.BADSTART ho.tool.anchor ho.opt.lib.vpd verga.err.BADCMD db.hdl.saveexp db.gate.cyclew pop.wire.hidesize @opt.height opt.general.fontset opt.library.exp ho.simexec err.badpinchg db.gate.tab.ROM.exp opt.tool.symmode opt.color.exp ipanel.ppos.scale break.condition gm.alu.mult igen.size ho.simgo ho.opt.vpopupdelay db.gate.dipval gm.rgate.or opt.library pop.interface.replace find.target symed.zoom opt.editor.returntab libmgr.status.loadp verga.err.BADARRAYLHS ho.simpause db.gate.ff.normal.hdr pop.gate.addin b.apply print.printtrace.trace.exp opt.ckpoint opt.tool.symport opt.editor.instword blklst.setroot.exp ho.print.selcur print.pageset ho.opt.sec.writemem menu.edit.selall gm.io.ground gm.mod.inout @opt.width @portlist.inout2 circ.script.cap libmgr.load b.browse menu.scope_help pop.gate.addport ipanel.autogen ho.delgat pop.wire.addseg find.result.module libmgr.status.load menu.file.print err.badversion msg.searchagn ho.opt.editor.rtab print.doctit iblmodule pop.simulate.pause menu.help.home pop.gate.addinout igen.inout menu.tool.move menu.scope_sim.script verga.err.TASKBADPORT opt.analysis.cap db.gate.led.bar.exp db.gate.ff.reverse.exp port.parms opt.html.cap db.gate.mux.dataorder db.gate.tab.Ports.cap db.gate.hidenam print.inclib opt.bbar.restore ho.opt.sim.err db.gate.tab.FRAME.cap find.qual.ends pop.igen.left print.incidx db.gate.memfilenam gm.mod.out find.options verga.err.TIMESCALEU db.gate.demux.ord1.exp db.gate.tab.COMMENT.cap symed.file.updateclose menu.simulate.pause print.filesel ho.print.fulltrace verga.err.CMDARGS itype opt.debug igen.modname ipanel.symbol err.modmissing err.yy.pinformat verga.err.NEEDIDENT db.gate.mux.sel2.hdr db.gate.tab.TAP.cap circ.iniscript menu.simulate.run info.script.error @find.type.gate menu.gate.ioset menu.tool.delg igen.port err.modmismatch err.yy.baddata verga.err.IE_NONEXPCTL pop.igen.other ho.opt.ckpt ho.ipanel.prot ho.edgat.phase ho.tool.valgn verga.err.BADASGNLHS gm.msi.21mux tab.simulate menu.scope_file blklst.del.exp opt.freq err.sim.noincl ho.edgat.func ho.edgat.cycle ho.print.seluse db.gate.cat.asc.exp opt.restdef err.badportadd cpath.cloops db.gate.aox.extbaruse pop.edit.copy err.manypages ho.log ho.open db.gate.demux.sel1.exp db.gate.mux.ord1.hdr err.nojump opt.sec.writemem ho.opt.sec.regexec ho.opt.sec.enqueue ho.net.hwire pop.port.out err.badconptsp err.sim.nonet verga.err.BADCHAR ho.symed.point cp.recompute ho.library menu.edit.find err.viewfile verga.err.NOTPPORT db.hdl.split db.gate.tab.FF.exp ho.print.selall menu.edit.ccwrotate gm.alu.arshift opt.sec.handle verga.err.PATHDLOOP opt.cpopts menu.edit.ushift circ.ident ho.edgat.dipstate pop.simulate.break menu.edit.cwrotate gm.mem.ram err.yy.bogussave verga.err.NOTREG menu.simulate.end opt.wire opt.vlibadd.exp ho.opt.lib.vlib ho.opt.tool.simctl ifile symed.file.load menu.module.interface.set gm.gate.and opt.cpflash find.result.name db.gate.tab.LED.exp gm.frame db.gate.demux.ord2.hdr db.gate.delete pop.tool opt.offled verga.err.CMDNOMOD db.mod.inuse.0 igen.add db.gate.led.dec.exp err.noerr err.badinadd verga.err.INPORT ho.tool.halgn print.printcirc.cap err.yy.badmoddata verga.err.BADPRTRANGE opt.tool.mode opt.sec.exec ho.opt.miles db.gate.cat.multin.exp menu.scope_trace.zoomin pop.wire.showlabel opt.gen.simtoolbar err.yy.baddirective circ.really ho.simbreak db.gate.tab.MUX.cap gm.alu.lshift opt.vpopupdelay ho.sim.break ho.opt.tool.symedit db.gate.tab.Delay.exp menu.scope_sim.cycle gm.rgate.nand print.fulltr tab.edit igen.modint print.scale opt.editor.indentlevel ho.opt.tool.mode menu.module.del tab.cpath circ.vlib.cap msg.selwire ho.opt.general.fontset menu.module.close opt.simbase opt.sec.regexec b.delete opt.editor.bold msg.selblock igen.portpos break.id ho.saveas err.corruptnewsave db.gate.stddelay scope.emptymsg opt.frames err.badinoutadd verga.err.NOTOP iports gm.rgate.xnor print.2side print.printcirc.page.exp ho.inv verga.err.NODIV verga.err.NOTASK db.gate.butstate pop.igen.in opt.sec.stop libmgr.cap menu.gate.anchor menu.tool.tclshell blklst.del.cap @db.gate.tabwidth igen.resort libmgr.notedit err.protdata ho.opt.editor.indent verga.err.PORTNOTDEF print.orient opt.sec.send ho.deftech ipanel.warn.toblock msg.wroteckpt ho.opt.sec.exec ho.opt.fsave db.gate.tab.SWITCH.cap err.sim.run print.advanced menu.tool.rect menu.edit.pccwrotate opt.inst opt.editor.beginindent ho.status.file print.filename menu.scope_sim verga.err.TOOFEWPP verga.err.PROTTASKSTOP port.inout print.outsel igen.top menu.scope_sim.pause gm.gate.nmos pop.gate.close opt.tool.edit @portlist.out2 pop.igen.right menu.make gm.mem.ff circ.vlib.label b.bitw menu.scope_sim.run gm.mod.in opt.sec.ignore opt.interface opt.showimage ho.symed.cwrotate ho.tool.find ho.cutw symed.edit.paste menu.simulate.load opt.saveCells err.primredef opt.tool.simctl miles.msg1 pop.gate.open ipanel.warn.tosymbol msg.notlib db.err.caption b.disable menu.edit.algnh print.modulesel symed.tab.normal ho.symed.lshift err.badlibopen verga.err.SYNTAX db.gate.demux.sel2.exp gm.io.vdd verga.err.TASKBADTYPE opt.tool.tech ipanel.props b.open opt.comment ho.tool.zoomout opt.editor.exp ho.opt.smooth verga.err.BADRANGE verga.err.MULTCONN db.mod.file pop.igen.type opt.simulator.err opt.tool.gateprop ipanel.itype.selectexp verga.err.OK db.mod.name menu.tool.select ho.tool.delete menu.module.claim verga.err.YYERROR pop.simulate.begin ho.mod.type.root db.mod.flags pop.module.prop ho.opt.undolen pop.wire.hidelabel db.gate.portnam gm.rgate print.tab.page ho.opt.clip db.gate.led.bit.hdr err.simonly gm.io.ledbar err.nomod verga.err.BADEVENT db.gate.duty db.mod.netexpl symed.edit gm.io.switch err.netconfnet db.gate.gtype menu.edit.zoomin b.label gm.io.tty db.hdl.cancel gm.msi.81mux opt.editor.taskword pop.simulate.script @mm.width ho.tool.addport verga.err.TIMESCALEAN imodule symed.edit.rclock print.partition circ.label err.protintf verga.err.IE_RETURN opt.float err.nosrcmod print.file db.gate.tab.DEMUX.exp ho.opt.tool.gateprop opt.print @portlist.out ho.simstop db.gate.bitw menu.interface opt.delayfilepath ipanel.itype.select find.result.type ho.opt.editor.format db.gate.mux.ord2.hdr menu.help.doc menu.edit.paste igen.mod ho.hdl.cancelexp db.gate.led.seg.hdr opt.smoothscroll ho.opt.ckstep verga.err.IE_NOOP symed.cutpaste gm.io.ledseg menu.tool.inv b.clear menu.help.example igen.side verga.err.BADOUT ho.opt.tool.zoom verga.err.FLOATNET db.gate.tab.MODULE.cap symed.cancel menu.module.setroot err.sim.syntx err.sim.nogate opt.html.linkopts err.modlock igen.caption verga.err.IE_BADTYPE mm.enable opt.general menu.edit.undo pop.wire.prop opt.simulator.noglitch verga.err.NOREAD db.gate.cat.singin.exp igen.type pop.igen.top pop.gate.anchor err.sim.badtmp db.gate.tab.details.exp err.badlprcmd opt.cstepsz verga.err.MEMBITS ho.mod.copy db.gate.custdelay db.net.port gm.alu.rshift msg.setinterface db.gate.tab.OR.exp menu.edit.algnv db.gate.demux.ord1.hdr db.gate.tab.ROM.cap print.incgraph ipanel.itype.edsymbol ho.tab.edit pop.igen.size menu.edit.pcwrotate pop.module.rename err.sim.badedge ho.opt.tool.symport @symed.tab.width gm.msi.41mux err.yy.nosym blklst.rename.cap pop.make pop.edit.paste opt.simulator.exp ho.circuit.discchg ho.simoptions find.qual.contains pop.igen.side menu.gate.rep opt.identity verga.err.NEEDEDGE verga.err.BADSPECLVAL gm.io db.gate.cat.auto.exp igen.portpos.renew db.gate.aox.nouse.exp ho.symed.select db.gate.parameters pop.igen.bottom menu.gate.prop db.gate.cat.dec.exp opt.libname err.nopin verga.err.LHSNOTREG verga.err.BADOPEN menu.simulate.addprobe opt.mods ho.opt.tool.edit ho.hdl.ignoreexp opt.miles break.tab print.epssave db.mod.netlist opt.html.browser ho.opt.simstep verga.err.MEMNONBLK gm.mem.rff print.parttr opt.simulator.cap verga.err.BADGATERNG db.net.bits db.net.name menu.tool.rot90 print.tab.content verga.err.MEMADDR menu.file.open tab.editintr ipanel.ppos.grid menu.scope_trace.zoomout symed.file db.newcirc.exp opt.display opt.security igen.in ho.opt.sim.err.showiferr opt.tool.symedit msg.iselgate symed.tab.select ho.opt.sec.stop menu.gate.settech menu.module.open opt.grid opt.beak blklst.rename.exp circ.simulator db.mod.smod.1 @opt.tool.columns blklst.new.exp db.gate.tab.RAM.exp menu.help.about menu.help gm.msi.18dec circ.autostart ho.edgat.port verga.err.TASKREDEF igen.edit ho.netlist menu.scope_file.close opt.html db.gate.mux.sel2.exp opt.editor.cap ho.hdl.commentexp verga.err.BADARRAYRNG ho.mod.new miles.msg6 db.mod.type find.exp @circ.width db.gate.mparm.parameter gm.rgate.and opt.tool.zoom ho.opt.outmove menu.edit.resize pop.module.del db.gate.anchor pop.simulate.step print.printcirc.out.exp ho.symed.rect db.err.explain menu.tool ho.opt.editor.colorize db.gate.tab.XOR.cap db.mod.props opt.showsimcmd find.dom.nets sim.breakpt verga.err.PORTMIX db.gate.tab.AND.cap db.gate.modname err.bkpt.badval miles.msg8a ho.edgat.swstate db.gate.gname db.newcirc.cap print.defaultprinter verga.err.TIMESCALEX db.gate.cat.dec.hdr gm.msi.14dec ho.opt.keybind ho.mod.type.partlib db.gate.aox.use.exp db.net.inout circ.exp err.noteditpchg db.gate.tab.DIP.cap gm.rgate.nor opt.regudate verga.err.IE_BADEXP @opt.tabwidth opt.cpath circ.file err.yy.toomuchdata ho.edgat.range ho.opt.tool.simaux err.rootinterface ho.opt.site symed.module menu.edit.redo menu.gate.del gm.gate.inv pop.gate.delete symed.bsave gm.mod.inst tutorial.next opt.toolbars.cap verga.err.TASKASFUNC print.portrait opt.simulator.stopany verga.err.TOOMANYPP gm.gate opt.input msg.save verga.err.BADARRAYUSG verga.err.BADARGVALUE menu.tool.port menu.tool.point db.hdl.ignore db.gate.cat.sigdir db.mod.inuse.1 ho.f.modlisttab ho.mod.rename opt.interface.exp err.sim.isrun ho.simclock ho.hdl.splitexp opt.debug.cap circ.discchg ho.edgat.gname db.gate.led.bar.hdr menu.simulate.dump gm.mem.rom err.moddef verga.err.DIRECTCONN gm.msi.12dec b.remove menu.scope_sim.load verga.err.BADADDRSPEC ho.print.selsel circ.script verga.err.NOIFDEF gm.gate.or menu.scope_sim.addprobe err.bkpt.badexp ho.mod.open pop.edit.cut opt.color.editwin menu.file.new @portlist.inout menu.tool.rot180 libmgr.exp err.gatanchor miles.msg8b ho.opt.tool.module menu.edit print.tab.output verga.err.NOMEM ho.ipanel.scale tutorial.reload break.value opt.site opt.sec.simfeatures blklst.copy.exp circ.script.label opt.novice opt.gen.symedtoolbar @circ.height sim.hyperlinkstop ho.symed.line ibits ho.mod.claim verga.err.BADSTOP err.sim.badcmd db.gate.phase print.end find.search ho.opt.sec.warn ho.edgat.iolab ho.status.block menu.tool.line menu.edit.lshift pop.gate.prop print.printtrace.cap opt.sorttraces opt.simulator.showiferr ho.tool.copy ho.net.reg2 err.noback verga.err.CMDNOTNET print.cur sim.recursive ho.redo menu.gate.unanchor err.badpsopen cp.pathl verga.err.BADADDR b.out opt.analysis opt.editor.format db.gate.tab.CLOCK.cap cp.numpath db.gate.led.dec.hdr gm.mem opt.initscript db.gate.tab.RAM.cap symed.edit.cut b.tech gm.gate.xor opt.estepsz menu.file.options print.all db.gate.tab.FF.cap opt.library.cap ho.tool.unanchor verga.err.FUNCASTASK gm.gate.tribuf opt.sec.open libmgr.status pop.igen.out menu.scope_sim.dump opt.editor.italic verga.err.BADCONSTOP db.mod.islib.0 menu.module.copy db.gate.tab.COMMENT.exp opt.bus miles.msg3 db.gate.aox.use.hdr db.gate.cat.tran.hdr menu.file.saveas blklst.name find.ignorecase circ.noscript ho.opt.blockDropConnect pop.simulate.cycle menu.file.cprop @find.qual.pos mm.edit gm.gate.nand opt.html.email verga.err.MODUNDEF b.inout verga.err.GATEUNIMP blklst.claim.cap symed.edit.rcclock opt.tools opt.vlibpath verga.err.WRONGMOD opt.general.exp err.badid verga.err.NETREDEF verga.err.BADSPECTASK print.epcm db.gate.tab.XOR.exp menu.module.rename opt.hlink opt.devfilepath verga.err.TIMESCALES opt.username opt.simclock err.openscript verga.err.REDEFP db.gate.ff.reverse.hdr db.mod.hdlexpl libmgr.status.unload msg.sim.nogatemod ho.mod.type.part menu.module.interface.edit menu.tool.rot270 opt.bat ho.opt.init igen.bits err.badeditop gm.gate.xnor gm.alu.div err.corruptsave err.badsave ho.opt.name db.gate.tab.OR.cap pop.module.copy blklst.claim.exp ho.symed.port db.gate.general opt.onled @find.type.comment msg.foundgate verga.err.DIVZERO ho.tool.rotate db.mod.hdl opt.tool.symshift libmgr.status.unloadp ho.opt.novice ho.opt.showimage menu.edit.dshift gm.io.dip opt.vlibnames err.nosafesave ho.custbut pop.gate.addout menu.file.quit opt.zled db.gate.tab.TAP.exp opt.color ho.simdump ho.net.hwire2 verga.err.BADEVENTNET pop.igen.inout opt.security.exp db.gate.tab.DEMUX.cap symed.update opt.trek msg.modoverwt pop.port.in igen.other miles.msg7 menu.simulate.begin err.futureversion db.seq.back db.gate.delay pop.gate.settech err.delprot ho.opt.sorttraces menu.module err.badoutadd ho.bitw ho.opt.sec.noexec menu.help.license menu.file.save opt.tool.symopr blklst.from db.gate.add opt.balloon err.yy.badprop msg.reallynew ho.net.wire2 comment.empty opt.print.cap ho.mod.type.netlist pop.gate.ioset err.sim.nobkpt opt.interface.cap igen.right err.badnetname verga.err.OPENTOOMANY opt.undolen opt.tool.file igen.int db.hdl.autoeditexp menu.simulate.step pop.port.inout opt.editor.gateword verga.err.PROTTASK igen.bottom ho.tab.simulate opt.simulator.showall ho.opt.sec.send ho.opt.tool.symshift db.gate.cat.asc.hdr menu.tool.bitw menu.file.openlib opt.setclock igen.description ho.simwatch ho.mod.type.Lhdl b.flush err.modnotdef err.yy.badprim ho.edgat.frame verga.err.NOCONN db.gate.range gm.io.merge ipanel.symbol.description ho.edgat.ganchor db.net.inets menu.tool.cutw ho.tool.zoomin ho.mod.type.conflict gm.io.ledhex blklst.setroot.cap circ.timescale opt.vercheck ho.net.inout2 find.dom.gates db.gate.tab.General.exp db.gate.cat.multin.hdr opt.useless ho.print.modlist b.add mod.intf port.out opt.editor db.gate.text ho.ports ho.tab.cpath ho.mod.type.hdl db.gate.side gm.gate.nor opt.print.exp igen.out ho.mod.close err.notwritable verga.err.TIMESCALEN db.gate.tab.General.cap err.nomark err.oldversion ho.tool.currot verga.err.CMDMODREDEF gm.mem.reg ipanel.block opt.debug.exp b.cancel print.use opt.sec.warn err.internal.nomod verga.err.PATHDITEM verga.err.TIMING menu.tool.debug ho.tool.paste gm.gate.buf break.state err.badopen err.nodrive menu.gate pop.wire.hidealllabel opt.color.cap err.sim.cmd menu.edit.cut db.gate.mparm.value opt.analysis.exp ho.mod.type.Lnetlist db.gate.mux.sel1.hdr db.gate.catdiruse gm.alu.roll ho.opt.bhelp ho.hdl.autoeditexp verga.err.IE_TASK opt.logic1 ho.traceprint ho.edgat.gx db.gate.signam pop.module.new db.gate.led.bit.exp pop.module.claim print.start igen.portsel ipanel.ppos.label ipanel.itype.change err.badconsame menu.simulate.break gm.io.led print.scaleselect err.yy.pinname msg.reallyquit err.badfind err.nomodule circ.timescale.prec verga.err.BADINOUT ho.symed.autobold verga.err.TASKARGS ho.opt.trek ho.simload db.gate.tab.MODULE.exp db.gate.led.hex.exp db.net.hide b.ok menu.scope_sim.break db.gate.tab.AND.exp menu.scope_help.license gm.io.clock verga.err.PORTCOUNT gm.alu db.gate.ff.type db.gate.edit opt.tool.module tkgate-2.0-b10/locale/en/messages~000644 001751 001751 00000253504 11150362264 017610 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Feb 22 18:50:12 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file are declarations. The # declarations should normally be specified before any tags are specified. # The currently supported declarations are: # # \font-encoding code # \messages-encoding code # \verilog-encoding code # \language name # # where "code" is a font encoding. Typical encodings are: # # iso8859-1 English and many European languages # iso8859-2 Some other European languages (e.g., Bosnian, Czech, Polish) # euc-ja Japanese EUC # utf-8 Unicode # # "\font-encoding" selects the encoding to use when displaying strings from # comments and frames in the main edit window. It should be "iso8859-1" or # "iso8859-2". # # "\messages-encoding" specifies the encoding of this messages file. # # "\verilog-encoding" specifies the default encoding to use for verilog files # when editing files in this locale. # # "\language" specifies the full language name of this messages file. It should # be after the \messages-encoding delcaration so that it will be processed # using the correct encoding. # ############################################################################## \font-encoding iso8859-1 \display-encoding iso8859-1 \messages-encoding iso8859-1 \verilog-encoding iso8859-1 \postscript-encoding iso8859-1 \language English ############################################################################## # # basic strings # b.new New... b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel #b.open Open... #b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete #b.deleteb Delete... b.remove Remove b.apply Apply b.anchor Anchor b.tech Technology #b.enable Enable #b.disable Disable #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Edit tab.editintr Interface tab.simulate Simulate tab.cpath Critical Path ############################################################################# # # Module tree/list box # module.tree Tree module.list List module.box.libraries Libraries ############################################################################# # # Tabs for Nets/Ports # sidetab.nets Nets sidetab.ports Ports ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Add... mm.delete Delete mm.edit Edit... mm.enable Enable mm.disable Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:File menu.edit 0:Edit menu.tool 0:Tool menu.symbol 0:Symbol menu.simulate 0:Simulate menu.module 0:Module menu.interface 0:Interface menu.format 0:Format menu.make 0:Components menu.help 0:Help menu.file.new 0:New... menu.file.open 0:Open... menu.file.openlib 0:Library Manager... menu.file.save 0:Save menu.file.saveas 5:Save As... menu.file.print 0:Print... menu.file.quit 0:Quit menu.file.cprop 0:Circuit Properties... menu.file.import 0:Import Image... menu.file.export 0:Export Image... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Cut menu.edit.copy 3:Copy menu.edit.paste 0:Paste menu.edit.overlay 0:Overlay Paste menu.edit.selall 0:Select All menu.edit.find 0:Find... menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 10:Bit Shift Right menu.edit.lshift 10:Bit Shift Left menu.edit.ushift 10:Bit Shift Up menu.edit.dshift 10:Bit Shift Down menu.edit.cwrotate 11:Bit Rotate C-W menu.edit.ccwrotate 15:Bit Rotate C-C-W menu.edit.pcwrotate 12:Port Rotate C-C-W menu.edit.pccwrotate 16:Port Rotate C-C-W menu.edit.autobold Boldify Bits menu.edit.resize Resize Bitmap menu.tool.move 0:Move/Connect menu.tool.delg 0:Delete Component menu.tool.cutw 0:Cut Wire menu.tool.inv 0:Invert menu.tool.bitw 0:Bit Width menu.tool.debug 0:Debug menu.tool.point 0:Point menu.tool.line 0:Line menu.tool.rect 0:Rectangle menu.tool.fillrect 0:Fill Rectangle menu.tool.port 0:Port menu.tool.select 0:Select Region menu.tool.options 0:Options... menu.format.addport 4:Add Port menu.format.ioset 0:Set Type menu.format.anchor 0:Anchor Selected menu.format.unanchor 0:Unanchor Selected menu.format.prop 0:Instance Properties... menu.format.del 0:Delete menu.format.settech 0:Set Technology menu.format.rot 0:Rotation menu.format.rot.0 17:Default Rotation 0 menu.format.rot.90 17:Default Rotation 90 menu.format.rot.180 17:Default Rotation 180 menu.format.rot.270 17:Default Rotation 270 menu.format.rot.rotate 10:Clockwise Rotate menu.format.rot.brotate 0:Counter-Clockwise Rotate menu.format.algnv 6:Align Ver. menu.format.algnh 6:Align Horz. menu.tool.tclshell 0:Tcl Shell menu.tool.rep 0:Replicate menu.simulate.begin 0:Begin Simulation menu.simulate.end 0:End Simulation menu.simulate.addprobe 0:Add/Delete Probe menu.simulate.run 0:Run menu.simulate.pause 0:Pause menu.simulate.step 0:Step Epoch(s) menu.simulate.cycle 5:Step Cycle menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Exec. Script... menu.simulate.load 1:Load Memory... menu.simulate.dump 1:Dump Memory... menu.simulate.view 1:View Memory... menu.module.open 0:Open menu.module.close 0:Close menu.module.new 0:New... menu.module.del 0:Delete... menu.module.copy 1:Copy... menu.module.rename 0:Rename... menu.module.claim 1:Claim... menu.module.setroot 1:Set As Root... menu.module.prop 0:Properties... menu.module.interface 0:Interface menu.module.interface.set 0:Set As Default menu.module.interface.update 1:Sync. to Default menu.module.interface.updateall 6:Sync. All to Default... menu.module.interface.edit 0:Edit... menu.module.interface.auto 5:Auto Generate... menu.help.about 0:About... menu.help.license 0:License... menu.help.doc 0:Documentation... menu.help.tut 1:Tutorials menu.help.home 1:Home Page menu.help.example 1:Examples ############################################################################# # Scope Menu # menu.scope_file 0:File menu.scope_sim 0:Simulate menu.scope_trace 0:Trace menu.scope_help 0:Help menu.scope_file.ptrace 0:Print Trace... menu.scope_file.close 0:Close menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Add/Delete Probe menu.scope_sim.run 0:Run menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Step Epoch(s) menu.scope_sim.cycle 5:Step Cycle menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Exec. Script... menu.scope_sim.load 1:Load Memory... menu.scope_sim.dump 1:Dump Memory... menu.scope_help.about 0:About... menu.scope_help.license 0:License... menu.scope_help.doc 0:Documentation... mod.intf Interface port.title TkGate: Port Properties port.parms Port Parameters port.in In port.out Out port.inout InOut ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gate gm.rgate Reduction gm.msi MSI gm.alu ALU gm.mem Memory gm.mod Module gm.comment Comment gm.script Verilog Script gm.frame Frame gm.io.switch Switch gm.io.dip DIP Switch gm.io.ground Ground gm.io.vdd Vdd gm.io.merge Concat gm.io.clock Clock gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Adder gm.alu.mult Multiplier gm.alu.div Divider gm.alu.lshift Left Shift gm.alu.rshift Right Shift gm.alu.arshift Arith. Right Shift gm.alu.roll Roll gm.mem.reg Register gm.mem.ff D Flip-Flop gm.mem.rff Rev. D Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK Flip-Flop gm.mem.rjkff Rev. JK Flip-Flop gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decoder gm.msi.14dec 1-4 Decoder gm.msi.18dec 1-8 Decoder gm.msi.12demux 1-2 Demultiplexor gm.msi.14demux 1-4 Demultiplexor gm.msi.18demux 1-8 Demultiplexor gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut tutorial.prev PREVIOUS tutorial.next NEXT tutorial.chapter CHAPTER LIST tutorial.reload RELOAD ############################################################################## # # Popup menus # pop.make Components pop.tool Tool pop.edit.paste Paste pop.edit.cut Cut pop.edit.copy Copy pop.port.in In pop.port.out Out pop.port.inout InOut pop.wire.addseg Add Wire Segment pop.wire.prop Net Properties... pop.wire.hidesize Hide Bit Width pop.wire.showsize Show Bit Width pop.wire.hidelabel Hide Label pop.wire.hidealllabel Hide All Labels pop.wire.clearalllabel Clear All Labels pop.wire.showlabel Show Label pop.gate.open Open pop.gate.close Close pop.gate.prop Instance Properties... pop.gate.addport Add Port pop.gate.addin Add Input... pop.gate.addout Add Output... pop.gate.addinout Add InOut... pop.gate.anchor Anchor/Unanchor pop.gate.settech Set Technology pop.gate.delete Delete pop.gate.ioset Set Type pop.module.new New... pop.module.del Delete... pop.module.copy Copy... pop.module.rename Rename... pop.module.claim Claim... pop.module.setroot Set As Root... pop.module.prop Module Properties... pop.module.int Edit Interface... pop.simulate.end End Simulation pop.simulate.begin Begin Simulation pop.simulate.addprobe Add/Delete Probe pop.simulate.delprobe Delete Probe pop.simulate.run Run pop.simulate.pause Pause pop.simulate.step Step Epoch(s) pop.simulate.cycle Step Cycle pop.simulate.break Breakpoint... pop.simulate.script Exec. Script... pop.simulate.load Load Memory... pop.simulate.dump Dump Memory... pop.simulate.view View Memory... pop.interface Interface pop.interface.set Set As Default pop.interface.update Sync. to Default pop.interface.updateall Sync. All to Default... pop.interface.edit Edit... pop.interface.auto Auto Generate... pop.interface.replace Replace pop.igen.type Type pop.igen.side Side pop.igen.size Size pop.igen.delete Delete pop.igen.in in pop.igen.out out pop.igen.inout inout pop.igen.left left pop.igen.right right pop.igen.top top pop.igen.bottom bottom pop.igen.other other pop.library.mgr Library Manager... pop.library.close Unload ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit Edit #symed.edit.cut Cut #symed.edit.copy Copy #symed.edit.paste Paste #symed.edit.overlay Overlay Paste #symed.edit.rclock Rotate Clockwise #symed.edit.rcclock Rotate Counter-Clockwise #symed.module Module #symed.modes Modes #symed.cutpaste Cut/Paste #symed.rotate Port Rotation #symed.zoom Zoom #symed.cancel Cancel #symed.update Update symed.tab.normal UnSelected symed.tab.select Selected symed.link Link selected to unselected # width of symbol editor tabs ############################################################################## ## memory viewer # memview.title Memory Viewer memview.exp -fillbegin- View and modify the contents of a RAM or ROM component. Select memory page, then type new hex values to change memory content. -end- ############################################################################## scope.title TkGate: Scope scope.emptymsg Double-click on a wire to add or delete a trace. comment.empty [Double click to add text.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: itype Type: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file File Name db.mod.type Type db.mod.flags Flags db.mod.dataprot Prevent editing of module definition. db.mod.intfprot Prevent all interface changes. db.mod.edprot Prevent edit mode interface changes. db.mod.props Properties db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netlist Netlist db.mod.hdl HDL db.mod.netexpl -begin- Define module using a graphical editor to connect wires between components. -end- db.mod.hdlexpl -begin- Define module using a textual editor to describe behavior in Verilog. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Error List db.err.caption Error List db.err.explain.warn -fillbegin- There were warnings in your circuit, but simulation will continue. Return to edit mode to examine the warnings. -end- db.err.explain.err -fillbegin- There were errors in your circuit. TkGate is unable to continue the simulation. -end- db.err.neededit -fillbegin- You must first switch to Edit mode before navigating to warnings. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Net Properties db.net.caption Net Properties db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.type Net Type db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: New Circuit db.newcirc.directory Directory: db.newcirc.cap New Circuit db.newcirc.exp -fillbegin- Discard the current circuit and start editing a new circuit. -end- db.newcirc.file File Name db.newcirc.topname Top Module Name ############################################################################## # Gate dialog box # db.gate.title TKGate: Component Properties db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Period db.gate.phase Phase db.gate.duty Duty db.gate.waveform Clock Waveform db.gate.port Port db.gate.bitws Bits db.gate.side Side db.gate.gtype Type db.gate.gname Instance Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.range Bit Range db.gate.memfilenam Memory File db.gate.modname Type db.gate.general General db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Delay db.gate.parameters Parameters db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.catdiruse Port Placement db.gate.edit Edit db.gate.delete Delete db.gate.add Add db.gate.ff.type D Flip-Flop Orientation db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- D Flip-Flop with data flowing left to right. -end- db.gate.ff.reverse.hdr Reversed db.gate.ff.reverse.exp -fillbegin- D Flip-Flop with data flowing right to left. -end- db.gate.jkff.type JK Flip-Flop Orientation db.gate.jkff.normal.hdr Normal db.gate.jkff.normal.exp -fillbegin- JK Flip-Flop with data flowing left to right. -end- db.gate.jkff.reverse.hdr Reversed db.gate.jkff.reverse.exp -fillbegin- JK Flip-Flop with data flowing right to left. -end- db.gate.cat.asc.hdr Ascending db.gate.cat.dec.hdr Decending db.gate.cat.asc.exp -fillbegin- Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir Signal Direction db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Multi-Input db.gate.cat.singin.hdr Single-Input db.gate.cat.tran.hdr Bidirectional db.gate.cat.auto.exp -fillbegin- Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- Allow bidirectional (tran) signal flow. Cannot be connected to switches or registers. -end- # # Minimum size of textbox for comment # @db.gate.comment.width *900 @db.gate.comment.height *550 db.gate.tab.General.cap General Properties db.gate.tab.Ports.cap Port Properties db.gate.tab.Delay.cap Delay Properties db.gate.tab.Parameters.cap Module Parameters db.gate.tab.CLOCK.cap Clock Properties db.gate.tab.SWITCH.cap Switch Properties db.gate.tab.DIP.cap DIP Properties db.gate.tab.TAP.cap Tran Properties db.gate.tab.RAM.cap RAM Properties db.gate.tab.ROM.cap ROM Properties db.gate.tab.MODULE.cap Module Properties db.gate.tab.FRAME.cap Frame Properties db.gate.tab.LED.cap LED Properties db.gate.tab.AND.cap AND Properties db.gate.tab.OR.cap OR Properties db.gate.tab.XOR.cap XOR Properties db.gate.tab.MUX.cap Mux Properties db.gate.tab.DEMUX.cap Demux Properties db.gate.tab.DECODER.cap Decoder Properties db.gate.tab.CONCAT.cap Concat Properties db.gate.tab.COMMENT.cap Text Properties db.gate.tab.FF.cap D Flip-Flop Properties db.gate.tab.JKFF.cap JK Flip-Flop Properties db.gate.tab.SCRIPT.cap Verilog Script db.gate.tab.General.exp -fillbegin- View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- Set detailed type-specific properties of a component here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.JKFF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.tab.SCRIPT.exp -fillbegin- Enter free-form Verilog code here to be included as part of this module. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Value db.gate.mparm.exampleA -begin- This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameter can be customized for each instance through this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.switch.state Initial Switch State db.gate.switch.state.on.hdr Switch On db.gate.switch.state.on.exp Switch begins simulation in the "on" state. db.gate.switch.state.off.hdr Switch Off db.gate.switch.state.off.exp Switch begins simulation in the "off" state. db.gate.switch.shownet Show Net Name db.gate.switch.shownet.on.hdr Show db.gate.switch.shownet.on.exp Show the name of the net next to switch. db.gate.switch.shownet.off.hdr Hide db.gate.switch.shownet.off.exp Do not show the name of the net next to switch. db.gate.dip.value Initial DIP Value db.gate.dip.value.exp Initial value of DIP switch at start of simulation. db.gate.dip.value.hex Hex Value: @db.gate.dip.value.exp.width 150 db.gate.dip.shownet Show Net Name db.gate.dip.shownet.on.hdr Show db.gate.dip.shownet.on.exp Show the name of the net next to dip. db.gate.dip.shownet.off.hdr Hide db.gate.dip.shownet.off.exp Do not show the name of the net next to dip. db.gate.tap.select Bit Tap Selection db.gate.tap.exp.bit Select the bit to pull off of the multi-bit bus. db.gate.tap.exp.bus Select the least-significant bit of the bit range to pull off of the multi-bit bus. db.gate.tap.lbl.bit Bit: db.gate.tap.lbl.bus LSB: @db.gate.tap.exp.width *180 db.gate.mux.dataorder Input Ordering db.gate.mux.ord1.hdr Left-to-Right db.gate.mux.ord2.hdr Right-to-Left db.gate.mux.ord1.exp -fillbegin- Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- Order MUX inputs from right to left. -end- db.gate.mux.select Selector Placement db.gate.mux.sel1.hdr On Left db.gate.mux.sel2.hdr On Right db.gate.mux.sel1.exp -fillbegin- Place the data selector on the left side of the MUX. -end- db.gate.mux.sel2.exp -fillbegin- Place the data selector on the right side of the MUX. -end- db.gate.demux.dataorder Output Ordering db.gate.demux.ord1.hdr Left-to-Right db.gate.demux.ord2.hdr Right-to-Left db.gate.demux.ord1.exp -fillbegin- Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- Order DEMUX outputs from right to left. -end- db.gate.demux.select Select Placement db.gate.demux.sel1.hdr On Left db.gate.demux.sel2.hdr On Right db.gate.demux.sel1.exp -fillbegin- Place the select input on the left side of the DEMUX. -end- db.gate.demux.sel2.exp -fillbegin- Place the select input on the right side of the DEMUX. -end- db.gate.decoder.dataorder Output Ordering db.gate.decoder.ord1.hdr Left-to-Right db.gate.decoder.ord2.hdr Right-to-Left db.gate.decoder.ord1.exp -fillbegin- Order DECODER outputs from left to right. -end- db.gate.decoder.ord2.exp -fillbegin- Order DECODER outputs from right to left. -end- db.gate.decoder.select Enable Placement db.gate.decoder.sel1.hdr On Left db.gate.decoder.sel2.hdr On Right db.gate.decoder.sel1.exp -fillbegin- Place the enable input on the left side of the DECODER. -end- db.gate.decoder.sel2.exp -fillbegin- Place the enable input on the right side of the DECODER. -end- db.gate.aox.extbaruse Extender Bar Use db.gate.aox.use.hdr Extender Bars db.gate.aox.nouse.hdr No Extender Bars db.gate.aox.use.exp -fillbegin- Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LED Type db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Bar Graph db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- Single-lamp LED display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- Signal bits directly control LED segments. -end- db.seq.back db.hdl.namechange.title HDL Module Name Changed db.hdl.textdisp.title HDL Text Disposition db.hdl.savecap Multiple Modules db.hdl.saveexp -fillbegin- The text buffer for the module you have just edited contains more than one module definition. Please select one of the three actions described on the right. -end- db.hdl.autoedit Auto Edit db.hdl.split Split db.hdl.comment Comment db.hdl.cancel Cancel db.hdl.ignore Ignore db.hdl.autoeditcap Name Mismatch db.hdl.autoeditexp -fillbegin- The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- db.dip.title TkGate: Dip Value cpath.cloops -fillbegin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the components in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # #print.outto Output to print.title TkGate: Print print.config.title TkGate: Printer Configuration print.scope.title TkGate: Scope Print print.printer Printer: print.file File print.prcmd Print Command: print.prname Printer print.advanced Advanced... print.filename File Name print.epssave Save as Encapsulated Postscript. #print.doctit Document Title #print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.incunused Include unused modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Content Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.rangeselection Range Selection print.scaleselect Scale Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.range Range print.linelen Line Length print.filesel Output to file print.printersel Output to printer print.defaultprinter Default Printer print.pageset Page Setup print.modulesel Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Print print.printtrace.cap Print Trace print.printcirc.cap Print Schematic print.printcirc.out.exp -fillbegin- Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output Output #print.tab.page Page print.tab.modules Modules print.tab.content Content print.tab.advanced Advanced ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Options opt.treelabel Options opt.general General opt.interface Interface # opt.circuit Circuit Defaults opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Print opt.print.output Output opt.print.content Content opt.simulate Simulate opt.simulate.basic Basic opt.simulate.tech Technology opt.simulate.error Error Handling opt.library Libraries opt.library.path Path opt.library.load Auto Loading opt.library.vpd VPD opt.analysis Analysis opt.color Color opt.color.title TkGate: Color Selection opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Available Libraries opt.lib.load.selected Selected Libraries opt.identity Identity opt.site Site Name opt.username User Name opt.libname Library Name: opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.background Background opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.balloon Enable Help Balloons opt.tearawaymenus Enable tear-away main menus opt.safeSave Do safe file saving opt.saveCells Include cells in save files opt.showimage Show side-bar images in dialog boxes opt.novice Novice mode opt.blockDropConnect Wire drop port creation opt.ckpoint.1 Do checkpointing every opt.ckpoint.2 commands. opt.freq Interval opt.beak Enable Special Modes opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.vpopupdelay Pop-Up Delay #opt.initscript Global Initialization Script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Technology Files opt.devfilepath VPD (Virtual Peripheral Device) File Path opt.vlibpath Verilog Library Path opt.vlibnames Base Libraries opt.display Display opt.interaction Interaction opt.input Input opt.security Security opt.undolen Max Undo opt.keybind Key Binding Style opt.useless Enable Useless Features opt.features Save File Features opt.simbase Basic Simulator Options opt.simclock Clock Options #opt.circdefaults Circuit Defaults opt.cpopts Critical Path Options opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.general.fontset Font Set opt.simulator.savetraces Save probe locations between simlation runs. opt.simulator.noglitch Enable simulator glitch suppression. opt.simulator.err Error Handling opt.simulator.stopany Treat warnings as errors. opt.simulator.showall Always display warnings. opt.simulator.showiferr Display warnings only with errors. opt.simulator.ignore Ignore all warnings. opt.tool.file File opt.tool.edit Edit opt.tool.gateopt Rotation/Alignment opt.tool.gateprop Gate opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Editor Tools opt.tool.module Module opt.tool.tech Technology opt.tool.simctl Simulator Control opt.tool.simaux Simulator Commands opt.tool.simmode Simulator Tools opt.tool.symmode Symbol Editor Tools opt.tool.symedit Cut/Paste opt.tool.symport Ports opt.tool.symshift Bit Shift opt.tool.symopr Bit Ops opt.editor.features Basic Editor Features opt.editor.format Enable Automatic Indenting opt.editor.colorize Enable Code Colorization opt.editor.comments Comments opt.editor.strings Strings opt.editor.reserved Reserved Words opt.editor.gateword Built-in Gates opt.editor.instword Module Instances opt.editor.taskword System Tasks opt.editor.color Color opt.editor.bold Bold opt.editor.italic Italic opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin...end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.vercheck -begin- Periodically check for new versions of TkGate over the Internet. Do not enable unless you have continuous access to the Internet. -end- opt.sec.execlevel The $tkg$exec() system task is opt.sec.exec fully enabled. opt.sec.regexec enabled only for registered functions. opt.sec.noexec disabled. opt.sec.simfeatures Simulator Features opt.sec.send Enable the $tkg$command() system task. opt.sec.open Enable the $fopen() system task. opt.sec.writemem Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle Security Violation Handling opt.sec.stop Stop simulator when disabled feature is used. opt.sec.warn Display warning message when disabled feature is used. opt.sec.ignore Ignore attempted usage of disabled features. opt.html.linkopts Link Options opt.html.browser Browser Command opt.html.email e-Mail Command opt.debug.opt Debugging Options opt.color.editwin Edit Window Colors opt.color.scopewin Scope Window Colors opt.vlibadd.title TkGate: Add Library opt.gen.basetoolbar Core Editor Toolbars opt.gen.simtoolbar Simulation Mode Toolbars opt.gen.symedtoolbar Symbol Editor Toolbars opt.bbar.restore Restore Page Defaults opt.bbar.restoreall Restore All Defaults ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Type igen.side Side igen.size Size igen.bits Bits igen.modname Module Name: #igen.resort Re-sort igen.add Add... igen.delete Delete igen.edit Edit... igen.in in igen.out out igen.inout inout igen.left left igen.right right igen.top top igen.bottom bottom #igen.other other igen.mod Use ports used in module only. igen.int Use ports from exisiting interface only. igen.modint Use both module and interface ports. igen.portsel Port Selection igen.portpos Port Positions igen.portpos.keep Keep exiting port positions when possible. igen.portpos.renew Regenerate all port positionings. igen.caption Generate Interface igen.description -begin- Create a new interface for a module. -end- info.script.error Script Errors module.props.title TkGate: Module Properties module.props Module Properties ipanel.plist Port List ipanel.props Interface Properties #ipanel.itype.change Change Type... #ipanel.itype.edsymbol Edit Symbol... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Auto Generate... ipanel.updateall Synchronize All... ipanel.itype.select Interface Type #ipanel.block.description Standard Interface #ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label Block resize port position handling: ipanel.ppos.fix Fixed ipanel.ppos.scale Scaled #ipanel.ppos.grid Grid ipanel.warn.toblock -begin- You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes # blklst.delete.title TKGate: Module Delete blklst.copy.title TKGate: Module Copy blklst.rename.title TKGate: Module Rename blklst.claim.title TKGate: Claim Module blklst.setroot.title TKGate: Set Root Module blklst.new.title TKGate: Module New blklst.claim Claim Module blklst.to To blklst.from From blklst.name Name blklst.new.cap Create New Module blklst.del.cap Delete Module blklst.copy.cap Copy Module blklst.rename.cap Rename Module blklst.claim.cap Claim Module blklst.setroot.cap Set Root Module blklst.new.exp -fillbegin- Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- Make the specified module the top-level module. -end- find.title TkGate: Find Object find.label Find Objects find.exp -fillbegin- Look for text either in a component name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase Ignore Case find.result.module Module find.result.type Type find.result.name Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Search Options find.results Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Contains... find.qual.begins Begins with... find.qual.ends Ends with... find.qual.matches Matches... find.dom.label Look for objects in: find.dom.gates Components find.dom.nets Nets find.dom.text Comment Text find.search Find: find.target Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Circuit Properties circ.label Circuit Properties circ.ident Identification circ.filev File Version circ.file File Name circ.title Circuit Title circ.encoding File Encoding circ.lang File Language circ.discchg Do not warn about discarding changes. circ.flags Options circ.defaults Component Defaults circ.extbar Use extender bars on AND, OR and XOR. circ.shownet Show net name on switches and dips. circ.autostart Enable auto-start of simulation. circ.iniscript Initialization Scripts #circ.noscript No script files selected. #circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.reallyupdate -fillbegin- Do you really want to update the interface of all '%s' instances? -end- circ.reallyoverwrite -fillbegin- Do you really want to overwrite the existing file '%s'? -end- @circ.library.width *500 @circ.library.height *350 circ.general General circ.library Libraries circ.script Scripts circ.simulator Simulation circ.timescale Default Simulation Time Scale circ.timescale.unit Units: circ.timescale.prec Precision: circ.sim.features Features # # Strings for timing violation reporting styles. The "after" case # is broken into the string before the time period box and after the # time period box. You can use the string "-empty-" to make a string # empty if it is not needed in a particular language. # circ.sim.tv.title Timing Violation Handling circ.sim.tv.all Report all timing violations. circ.sim.tv.after.1 Report timing violations after circ.sim.tv.after.2 -empty- circ.sim.tv.never Never report timing violations. circ.exp.general -fillbegin- View and modify circuit specific properties. These properties will be stored with the circuit when you save. -end- circ.exp.library -fillbegin- Select libraries required by this circuit. Library requirements are saved with the circuit and will be automatically loaded the next time you load this circuit. -end- circ.exp.script -fillbegin- Add any simulation scripts that should be automatically read and excuted when this circuit is simulated. -end- circ.exp.simulator -fillbegin- View and modify simulation preferences for this circuit. -end- ############################################################################## # # Library Manager # libmgr.cap Library Manager libmgr.library Library libmgr.description Description libmgr.status Status libmgr.status.load Loaded libmgr.status.unload Not Loaded libmgr.status.loadp [Loaded] libmgr.status.unloadp [Not Loaded] libmgr.exp -fillbegin- Select libraries to be loaded or unloaded. -end- libmgr.load Load libmgr.unload Unload libmgr.unloadall Unload All libmgr.notedit -fillbegin- Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.notinsim Not allowed while simulator is active. err.nomemselect Memory is not selected. err.rootinterface Can not set interface of root module. err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Components(s) are anchored and can not be moved. err.protdata Can not modify contents of protected or library module. err.badfind Can't find target '%s'. err.badopendel Can't delete open module. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.nofunc Bad or missing function name for module interface. err.wirerot Selection can not be rotated due to attaching wires. err.badinadd Can't add any more inputs to selected component. err.badoutadd Can't add any more outputs to selected component. err.badinoutadd Can't add any more inout pins to selected component. err.badpinchg Can't change pin types on selected component. err.badnetname Illegal characters in identifier deleted. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with built-in component name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Connection refused because wires are part of the same net. err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Connection refused because bit widths do not match. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Unable to exectute printer command '%s'. err.badpsopen Unable to open file '%s' for postscript output. err.badid Illegal identifier '%s'. err.noinvgate Inverters are not allowed on components of this type. err.protintf Can't modifiy protected interface on module '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Too many breakpoints. Maximum is %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.badedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Can't find net '%s'. err.sim.nogate Can't find component '%s'. err.sim.badbin Illegal charcter in binary constant '%s'. err.sim.notswitch Component '%s' is not a switch, dip or register. err.sim.badcmd Unrecognized command '%s' in simulation script. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.run Run-time error at time %s: err.sim.cmd Internal Command Error err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Unable to open input file '%s'. err.badlibopen Unable to open library file '%s'. err.nomark Please set a mark with the left mouse button before selecting a component type. err.badgate Unknown component type '%s'. err.badportadd Can't add ports to components of this type. err.modmissing HDL module text missing for module "%s". err.modtoomany Excess module definitions in module "%s". err.modmismatch Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -fillbegin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot No higher level module opened on the module stack. err.editonly Command not valid when in simulation mode. err.simonly Command valid only in simulation mode. err.deltop Can not delete top-level module '%s'. err.delprot Can not delete protected module '%s'. err.nodel No deletable selection. err.modnotdef Module '%s' is undefined. err.moddef The module '%s' already exists. err.primredef Built-in element name '%s' can not be redefined. err.primprefix Illegal module name '%s' begins with built-in prefix '%s'. err.iskeyword Verilog keyword '%s' can not be used as an identifier. err.noprop Selected component has no editable properites. err.openscript Can't open simulation script file '%s' err.oldversion Loaded file '%s' with obsolete version number %s (current version is %s). err.futureversion Loaded file '%s' saved by future TkGate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.nomodule No selected module. err.nomodop No suitable modules for operation. err.protexec Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable File '%s' is not writable. err.backupfail Unable to create backup file '%s'. err.yy.badprop Ignoring unknown circuit property '%s'. err.yy.badpropval Bad value '%s' for circuit property '%s'. err.yy.baddata Bad data type supplied for circuit property '%s'. err.yy.nosym No current module symbol. err.yy.badicon Bad icon type '%s'. err.yy.toomuchdata Too much icon data. err.yy.nosyminst Missing symbol %d on instance %s of %s. err.yy.badmodprop Ignoring unknown module property '%s'. err.yy.badmoddata Bad data type supplied for module property '%s'. err.yy.badprim Unknown primitive name '%s'. err.yy.nonet Undeclared net '%s'. err.yy.bogussave Bogus save data detected. circuit may be damaged. err.yy.pinformat Illegal pin name format '%s'. err.yy.pinname Pin name '%s' not defined for component type '%s' err.yy.nonetpos No net for position %d on component %s. err.yy.baddirective Illegal or badly formed directive '%s'. err.yy.badlocale Unknown locale '%s' in save file. Using English locale. err.corruptnewsave -fillbegin- TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- File '%s' was created by TkGate %s, and may not be readable by versions earlier than current version (%s) if you save. -end- err.viewfile Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Selected %s named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.iselwire Selected port '%s' on block '%s'. msg.iselgate Selected %s named '%s' (huh? this message should be impossible). msg.iselblock Selected module interface for '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Found component named '%s'. msg.foundwire Found wire named '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Saved circuit to '%s'. msg.reallynew Circuit has been modified. Do you really want to discard your changes and create a new circuit? msg.reallyquit Circuit has been modified. Do you really want to exit? msg.notlib Module '%s' is not a library module. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Port size mismatch on input port '%s'. verga.err.OUTPORT Port size mismatch on output port '%s'. verga.err.FLOATNET Net '%s' has no drivers (floating net). verga.err.DIRECTCONN Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR Attempt to write to memory %s with unknown address. verga.err.MEMBITS Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG Array '%s' used in expression without index. verga.err.BADARRAYLHS Array '%s' used without index on left-hand-side. verga.err.BADCLOSE Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG Bad component instance range expression. verga.err.BADARGVALUE Bad value for argument '%s' in task '%s'. verga.err.DIVZERO Divide by zero. verga.err.NODIV Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT Event wait on assign is illegal. verga.err.PROTTASK Execution of protected system task '%s' blocked. verga.err.NEEDIDENT Expecting identifier for argument %s of task '%s'. verga.err.BADOP Expression operator error in '%s'. verga.err.NOREAD Failed to load source file '%s'. verga.err.MEMFILE Failed to open memory file '%s'. verga.err.WRONGMOD Found module '%s' when expecting '%s'. verga.err.NOTPARM Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR Illegal address range on port '%s'. verga.err.BADADDRSPEC Illegal address range specification '%s'. verga.err.BADCHAR Illegal character (%s) '%s'. verga.err.BADEVENT Illegal event control expression. verga.err.BADCONSTOP Illegal operator in constant expression. verga.err.BADXOP Illegal operator in expression. verga.err.NETREDEF Illegal redefinition of net '%s'. verga.err.BADINOUT Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF Instance of undefined module '%s'. verga.err.BADASGNLHS Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS Invalid left-hand-side in assignment. verga.err.BADOUT Invalid output assignment. verga.err.NOTREG Memories must be declared as register. verga.err.PORTMIX Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE More than one default: in case statement. verga.err.NOMEM No current memory in memory file read. verga.err.BADCMD No such command '%s'. verga.err.CMDNOTNET No such net '%s' in '%s' command. verga.err.MEMNONBLK Non-blocking assignments to memories not implemented. verga.err.NOTPPORT Parameter '%s' is not declared as a port. verga.err.REDEFP Parameter redefines identifier '%s'. verga.err.PORTNOTDEF Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE Range on port '%s' is not numeric. verga.err.BADARRAYRNG Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF Redefinition of dynamic module '%s'. verga.err.REDEF Redefinition of identifier %s. verga.err.PROTTASKSTOP Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM Specified net '%s' is not a memory. verga.err.CMDNOTMEM Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX Syntax error. verga.err.TOOFEWPP Too few parameter ports on instance %s. verga.err.OPENTOOMANY Too many files open in task '%s'. verga.err.TOOMANYPP Too many parameter ports on instance %s. verga.err.NOTOP Top-module '%s' not defined. verga.err.BADOPEN Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET Undefined net '%s' in event control expression. verga.err.NOTASK Undefined task '%s'. verga.err.NOTDEF Undefined variable '%s'. verga.err.BADRANGE Unsupported bit range [%s] on net '%s' (must be of form [n:0]). verga.err.GATEUNIMP Unimplemented primitive component type on instance '%s'. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Write to closed descriptor. verga.err.PRIMPTCOUNT Wrong number of ports on primitive component instance '%s'. verga.err.CMDARGS Wrong number of arguments in '%s' command. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' called with wrong number of arguments. verga.err.BADSTART Illegal start value in task '%s'. verga.err.BADSTOP Illegal stop value in $readmemb. verga.err.SPECTASKUSG Task '%s' must be used in a specify block. verga.err.BADSPECTASK Task '%s' can not be used in a specify block. verga.err.TIMING Timing violation in %s[%s] %s. verga.err.RAMDCHG Data line changed while write enabled on %s verga.err.RAMACHG Address line changed while write enabled on %s verga.err.NOIFDEF No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP Loops in modules with path-delay specification are unsupported. verga.err.PATHDCOND DelaMust set through both # expression and specify block. verga.err.TASKREDEF Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC Task '%s' used as function. verga.err.FUNCASTASK Function '%s' used as task. verga.err.TASKBADTYPE Non-register type used in task or function. verga.err.TASKBADPORT Only input ports are allowed on functions. verga.err.TIMESCALEU Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES Invalid syntax in `timescale declaration. verga.err.TIMESCALEX Units must be larger than precision in `timescale declaration. verga.err.TIMESCALEAN Design contains some modules with `timescale and some without. verga.err.BADPORTTYPE Invalid type declaration used on port '%s' verga.err.BADVALUE Bad numeric value '%s'. verga.err.NONEXPCTL Event control @(*) applied to non-expression. verga.err.NONSTATCTL Event control @(*) applied to non-statment. verga.err.MODREDEF Redefinition of module '%s'. verga.err.IE_TASK Task definition '%s' found outside module - internal error. verga.err.IE_NONET Failed to find net '%s' - internal error. verga.err.IE_NOOP Can not find operator description -- internal error. verga.err.IE_BADEXP Unexpected expression type %s - internal error. verga.err.IE_BADVAR Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE Unexpected internal state at %s - internal error. verga.err.IE_RETURN Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Move all items to selected list. ho.setsel.alll Move all items to unselected list. ho.setsel.ltor Move highlighted items to selected list. ho.setsel.rtol Move highlighted items to unselected list. ho.net.in Single-Bit Input ho.net.out Single-Bit Output ho.net.inout Single-Bit Inout ho.net.in2 Multi-Bit Input ho.net.out2 Multi-Bit Output ho.net.inout2 Multi-Bit Inout ho.net.wire Single-Bit Wire (Name Visible) ho.net.wire2 Multi-Bit Wire (Name Visible) ho.net.hwire Single-Bit Wire (Name Hidden) ho.net.hwire2 Multi-Bit Wire (Name Hidden) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Save, load of circuit files ho.opt.tool.edit Cut, Paste and Find operations ho.opt.tool.gateopt Component rotation and alignment operations ho.opt.tool.gateprop Basic editing of components ho.opt.tool.undo Undo and redo operations ho.opt.tool.zoom Zoom in and zoom out ho.opt.tool.mode Select the editing tool ho.opt.tool.module Create, delete, rename,etc. of module definitions ho.opt.tool.tech Select default technology for components ho.opt.tool.simctl Start, stop and pause of simulator ho.opt.tool.simaux Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.simmode Choose between the select and scroll tool in simulator. ho.opt.tool.symmode Selecting editing tool in symbol editor ho.opt.tool.symedit Cut and paste operations for symbol editor ho.opt.tool.symport Port rotation operations for symbol editor ho.opt.tool.symshift Shift the bit map or portion of bitmap ho.opt.tool.symopr Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.saveas Save circuit to specified file. ho.print Print current circuit. ho.library Open the library manager. ho.symed.tab.normal -begin- Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- Edit the selected symbol bitmap. -end- ho.simmove -begin- Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new component Move components and wires Connect wires By double-clicking you can: Edit component, wire and port properties Edit comment text -end- ho.delgat -begin- Delete Component - Use this tool to delete components. -end- ho.cutw -begin- Cut Wire - Use this tool to cut wires. -end- ho.scroll -begin- Scroll - Grab and drag the editing canvas. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from component ports. -end- ho.bitw -begin- Net Attributes - Use this tool to change the attributes of a net. The bit size and wire type of nets selected with this tool will be changed to the those shown in the drop-down boxes to the right. -end- ho.ipanel.select -begin- Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- Add a port to the module. You can also double-click after the last item to add port. -end- ho.ipanel.deleteport -begin- Delete the selected port. -end- ho.ipanel.editport -begin- Edit the selected port. You can also double-click to edit a field in a port. -end- ho.ipanel.generate -begin- Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.ipanel.updateall -begin- Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.ipanel.prot -begin- Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Open the selected module. ho.mod.close Close the current module. ho.mod.new Create a new module type. ho.mod.del Delete a module. ho.mod.copy Copy a module. ho.mod.rename Rename a module. ho.mod.claim -begin- Convert a library module to a regular module. -end- ho.mod.setroot -begin- Designate a module to be the root module. -end- ho.mod.type.allparts Set of Libraries ho.mod.type.partlib Library ho.mod.type.part Library module ho.mod.type.unknown Unknown module type ho.mod.type.unused Set of unused modules ho.mod.type.conflict Module recursion ho.mod.type.root Top-level module ho.mod.type.netlist Netlist module ho.mod.type.Lnetlist Netlist module (locked) ho.mod.type.hdl HDL module ho.mod.type.Lhdl HDL module (locked) ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.tab.edit -begin- Primary editing mode. -end- ho.tab.interface -begin- Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Find critical paths in a circuit. -end- ho.log -begin- Log of TkGate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. Breakpoints can be edited in both simulation mode and edit mode. -end- ho.simexec -begin- Manage the set of active scripts. -end- ho.simoptions -begin- Set various options that control the simulation. -end- ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.simview -begin- View/modify the contents of a memory (RAM or ROM). -end- ho.modlist -begin- List of all modules currently loaded in alphabetical order. Drag modules to the edit window to create new instances. -end- ho.modtree -begin- List of all modules currently in a hierarchical list. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- List of nets in the current module. The symbol to the left of the name indicates whether the net is single bit (green) or multi-bit (red). An "A" shown in the symbol indicates that the net name is marked as visible. -end- ho.ports -begin- List of ports on the interface of the module displayed in the edit window. The symbol before the port indicates the direction of the port. -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, TkGate is in edit mode. If the quadrapedal AND gate is shown, TkGate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from TkGate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TkGate. ho.print.selcur Print only the current module in the TkGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.print.timegraph -begin- The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Newly created basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.shownet -begin- Newly created switches and dips will initially show the net name next to them. -end- ho.circuit.autostart -begin- If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.circuit.file -begin- This is the file name from which the current circuit was loaded. -end- ho.circuit.ver -begin- This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.encoding -begin- Use this encoding for save files. -end- ho.circuit.language -begin- Use fonts for this encoding to display circuit data. -end- ho.circuit.title -begin- Description of your circuit. This title is used on printed output. -end- ho.cmd.bitw -begin- Wires selected with the ribbon cable tool will be set to this bit width. -end- ho.edgat.signam -begin- The name of the selected signal on the selected component. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the component. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected component. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected component. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.hide -begin- Set this flag to disable display of component names. -end- ho.edgat.gtype Type of the component. ho.edgat.gname Name of this component instance. ho.edgat.ganchor Set this flag to anchor the position of a component. ho.edgat.gx X coordinate of component. ho.edgat.gy Y coordinate of component. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint -begin- Print the logic trace range selected using the right mouse button. Shift-right click can be used to expand the selected region. The range visible in the scope view is used when there is no selection. -end- ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- Specifies the basic font size to use in the TkGate interface. This option will not take effect until restarting TkGate. -end- ho.opt.sec.send -begin- Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the TkGate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to TkGate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- Save TkGate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- If this option is enabled, rapidly changing inputs to a component will cause the component to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.savetraces -begin- Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.opt.sim.tech -begin- List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in components. -end- ho.opt.sim.err -begin- Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- List of directories to search for TkGate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- List of libaries that should automatically be loaded when TkGate starts. -end- ho.opt.lib.vpd -begin- List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.name -begin- User name to be used on TkGate generated reports such as circuit printouts. -end- ho.opt.site -begin- The name of the site where TkGate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. Unset only if you are having problems on your display. -end- ho.opt.showimage -begin- Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.tearawaymenus -begin- If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.blockDropConnect -begin- Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this option, the useless features checkbox will no longer appear in this dialog box. The only way to see the useless features again will be to edit your .tkgate2-properties file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when simulation of any circuit is initiated. Do not use this for circuit specific scripts, use the circuit properties instead. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. Use the name of the net to which the clock is attached. -end- ho.opt.keybind -begin- Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart TkGate to see any user defined keybindings. -end- ho.deftech -begin- Default technology for new components. Affects delay of components. To change the technology of a specific component, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this component. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.symed.point -begin- Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift Shift selected pixels right. ho.symed.lshift Shift selected pixels left. ho.symed.ushift Shift selected pixels up. ho.symed.dshift Shift selected pixels down. ho.symed.cwrotate Rotate selected pixels clockwise. ho.symed.ccwrotate Rotate selected pixels counter-clockwise. ho.symed.autobold Make selected image bold. ho.symed.resize Resize the image editor. ho.symed.import Import image from file. ho.symed.export Export image to file. ho.tool.currot -begin- Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotate selected component(s) counter-clockwise. ho.tool.brotate Rotate selected component(s) clockwise. ho.tool.valgn Align selected component(s) vertically. ho.tool.halgn Align selected component(s) horizontally. ho.tool.cut Cut selection. ho.tool.copy Copy selection. ho.tool.paste Paste from cut buffer. ho.tool.find Find component, wire or text. ho.tool.addport Add a port to the selected component. ho.tool.anchor Anchor the selected component(s). ho.tool.unanchor Unanchor the selected component(s). ho.tool.replicate Replicate a component. ho.tool.delete Delete the selection. #ho.opt.circuit.extbar TODO #ho.opt.circuit.shownet TODO #ho.circuit.shownet TODO tkgate-2.0-b10/locale/en/messages.bak000644 001751 001751 00000242656 11134010127 020142 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Jan 15 23:35:07 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file are declarations. The # declarations should normally be specified before any tags are specified. # The currently supported declarations are: # # \font-encoding code # \messages-encoding code # \verilog-encoding code # \language name # # where "code" is a font encoding. Typical encodings are: # # iso8859-1 English and many European languages # iso8859-2 Some other European languages (e.g., Bosnian, Czech, Polish) # euc-ja Japanese EUC # utf-8 Unicode # # "\font-encoding" selects the encoding to use when displaying strings from # comments and frames in the main edit window. It should be "iso8859-1" or # "iso8859-2". # # "\messages-encoding" specifies the encoding of this messages file. # # "\verilog-encoding" specifies the default encoding to use for verilog files # when editing files in this locale. # # "\language" specifies the full language name of this messages file. It should # be after the \messages-encoding delcaration so that it will be processed # using the correct encoding. # ############################################################################## \font-encoding iso8859-1 \display-encoding iso8859-1 \messages-encoding iso8859-1 \verilog-encoding iso8859-1 \postscript-encoding iso8859-1 \language English ############################################################################## # # basic strings # b.new New... b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel #b.open Open... #b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete #b.deleteb Delete... b.remove Remove b.apply Apply b.anchor Anchor b.tech Technology #b.enable Enable #b.disable Disable #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Edit tab.editintr Interface tab.simulate Simulate tab.cpath Critical Path ############################################################################# # # Module tabs # module.tree Tree module.list List ############################################################################# # # Tabs for Nets/Ports # sidetab.nets Nets sidetab.ports Ports ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Add... mm.delete Delete mm.edit Edit... mm.enable Enable mm.disable Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:File menu.edit 0:Edit menu.tool 0:Tool menu.symbol 0:Symbol menu.simulate 0:Simulate menu.module 0:Module menu.interface 0:Interface menu.format 0:Format menu.make 0:Components menu.help 0:Help menu.file.new 0:New... menu.file.open 0:Open... menu.file.openlib 0:Library Manager... menu.file.save 0:Save menu.file.saveas 5:Save As... menu.file.print 0:Print... menu.file.quit 0:Quit menu.file.cprop 0:Circuit Properties... menu.file.import 0:Import Image... menu.file.export 0:Export Image... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Cut menu.edit.copy 3:Copy menu.edit.paste 0:Paste menu.edit.overlay 0:Overlay Paste menu.edit.selall 0:Select All menu.edit.find 0:Find... menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 10:Bit Shift Right menu.edit.lshift 10:Bit Shift Left menu.edit.ushift 10:Bit Shift Up menu.edit.dshift 10:Bit Shift Down menu.edit.cwrotate 11:Bit Rotate C-W menu.edit.ccwrotate 15:Bit Rotate C-C-W menu.edit.pcwrotate 12:Port Rotate C-C-W menu.edit.pccwrotate 16:Port Rotate C-C-W menu.edit.autobold Boldify Bits menu.edit.resize Resize Bitmap menu.tool.move 0:Move/Connect menu.tool.delg 0:Delete Gate menu.tool.cutw 0:Cut Wire menu.tool.inv 0:Invert menu.tool.bitw 0:Bit Width menu.tool.debug 0:Debug menu.tool.point 0:Point menu.tool.line 0:Line menu.tool.rect 0:Rectangle menu.tool.fillrect 0:Fill Rectangle menu.tool.port 0:Port menu.tool.select 0:Select Region menu.tool.options 0:Options... menu.format.addport 4:Add Port menu.format.ioset 0:Set Type menu.format.anchor 0:Anchor Selected menu.format.unanchor 0:Unanchor Selected menu.format.prop 0:Instance Properties... menu.format.del 0:Delete menu.format.settech 0:Set Technology menu.format.rot 0:Rotation menu.format.rot.0 17:Default Rotation 0 menu.format.rot.90 17:Default Rotation 90 menu.format.rot.180 17:Default Rotation 180 menu.format.rot.270 17:Default Rotation 270 menu.format.rot.rotate 10:Clockwise Rotate menu.format.rot.brotate 0:Counter-Clockwise Rotate menu.format.algnv 6:Align Ver. menu.format.algnh 6:Align Horz. menu.tool.tclshell 0:Tcl Shell menu.tool.rep 0:Replicate menu.simulate.begin 0:Begin Simulation menu.simulate.end 0:End Simulation menu.simulate.addprobe 0:Add/Delete Probe menu.simulate.run 0:Run menu.simulate.pause 0:Pause menu.simulate.step 0:Step Epoch(s) menu.simulate.cycle 5:Step Cycle menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Exec. Script... menu.simulate.load 1:Load Memory... menu.simulate.dump 1:Dump Memory... menu.module.open 0:Open menu.module.close 0:Close menu.module.new 0:New... menu.module.del 0:Delete... menu.module.copy 1:Copy... menu.module.rename 0:Rename... menu.module.claim 1:Claim... menu.module.setroot 1:Set As Root... menu.module.prop 0:Properties... menu.module.interface 0:Interface menu.module.interface.set 0:Set As Default menu.module.interface.update 1:Sync. to Default menu.module.interface.updateall 6:Sync. All to Default... menu.module.interface.edit 0:Edit... menu.module.interface.auto 5:Auto Generate... menu.help.about 0:About... menu.help.license 0:License... menu.help.doc 0:Documentation... menu.help.tut 1:Tutorials menu.help.home 1:Home Page menu.help.example 1:Examples ############################################################################# # Scope Menu # menu.scope_file 0:File menu.scope_sim 0:Simulate menu.scope_trace 0:Trace menu.scope_help 0:Help menu.scope_file.ptrace 0:Print Trace... menu.scope_file.close 0:Close menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Add/Delete Probe menu.scope_sim.run 0:Run menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Step Epoch(s) menu.scope_sim.cycle 5:Step Cycle menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Exec. Script... menu.scope_sim.load 1:Load Memory... menu.scope_sim.dump 1:Dump Memory... menu.scope_help.about 0:About... menu.scope_help.license 0:License... menu.scope_help.doc 0:Documentation... mod.intf Interface port.title TkGate: Port Properties port.parms Port Parameters port.in In port.out Out port.inout InOut ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gate gm.rgate Reduction gm.msi MSI gm.alu ALU gm.mem Memory gm.mod Module gm.comment Comment gm.frame Frame gm.io.switch Switch gm.io.dip DIP Switch gm.io.ground Ground gm.io.vdd Vdd gm.io.merge Concat gm.io.clock Clock gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Adder gm.alu.mult Multiplier gm.alu.div Divider gm.alu.lshift Left Shift gm.alu.rshift Right Shift gm.alu.arshift Arith. Right Shift gm.alu.roll Roll gm.mem.reg Register gm.mem.ff Flip-Flop gm.mem.rff Rev. Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decoder gm.msi.14dec 1-4 Decoder gm.msi.18dec 1-8 Decoder gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut tutorial.prev PREVIOUS tutorial.next NEXT tutorial.chapter CHAPTER LIST tutorial.reload RELOAD ############################################################################## # # Popup menus # pop.make Make pop.tool Tool pop.edit.paste Paste pop.edit.cut Cut pop.edit.copy Copy pop.port.in In pop.port.out Out pop.port.inout InOut pop.wire.addseg Add Wire Segment pop.wire.prop Net Properties... pop.wire.hidesize Hide Bit Width pop.wire.showsize Show Bit Width pop.wire.hidelabel Hide Label pop.wire.hidealllabel Hide All Labels pop.wire.clearalllabel Clear All Labels pop.wire.showlabel Show Label pop.gate.open Open pop.gate.close Close pop.gate.prop Instance Properties... pop.gate.addport Add Port pop.gate.addin Add Input... pop.gate.addout Add Output... pop.gate.addinout Add InOut... pop.gate.anchor Anchor/Unanchor pop.gate.settech Set Technology pop.gate.delete Delete pop.gate.ioset Set Type pop.module.new New... pop.module.del Delete... pop.module.copy Copy... pop.module.rename Rename... pop.module.claim Claim... pop.module.setroot Set As Root... pop.module.prop Module Properties... pop.module.int Edit Interface... pop.simulate.end End Simulation pop.simulate.begin Begin Simulation pop.simulate.addprobe Add/Delete Probe pop.simulate.delprobe Delete Probe pop.simulate.run Run pop.simulate.pause Pause pop.simulate.step Step Epoch(s) pop.simulate.cycle Step Cycle pop.simulate.break Breakpoint... pop.simulate.script Exec. Script... pop.simulate.load Load Memory... pop.simulate.dump Dump Memory... pop.interface Interface pop.interface.set Set As Default pop.interface.update Sync. to Default pop.interface.updateall Sync. All to Default... pop.interface.edit Edit... pop.interface.auto Auto Generate... pop.interface.replace Replace pop.igen.type Type pop.igen.side Side pop.igen.size Size pop.igen.delete Delete pop.igen.in in pop.igen.out out pop.igen.inout inout pop.igen.left left pop.igen.right right pop.igen.top top pop.igen.bottom bottom pop.igen.other other ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit Edit #symed.edit.cut Cut #symed.edit.copy Copy #symed.edit.paste Paste #symed.edit.overlay Overlay Paste #symed.edit.rclock Rotate Clockwise #symed.edit.rcclock Rotate Counter-Clockwise #symed.module Module #symed.modes Modes #symed.cutpaste Cut/Paste #symed.rotate Port Rotation #symed.zoom Zoom #symed.cancel Cancel #symed.update Update symed.tab.normal UnSelected symed.tab.select Selected symed.link Link selected to unselected # width of symbol editor tabs ############################################################################## scope.emptymsg Double-click on a wire to add or delete a trace. comment.empty [Double click to add text.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: itype Type: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file File Name db.mod.type Type db.mod.flags Flags db.mod.dataprot Prevent editing of module definition. db.mod.intfprot Prevent all interface changes. db.mod.edprot Prevent edit mode interface changes. db.mod.props Properties db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netlist Netlist db.mod.hdl HDL db.mod.netexpl -begin- Define module using a graphical editor to connect wires between components. -end- db.mod.hdlexpl -begin- Define module using a textual editor to describe behavior in Verilog. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Error List db.err.caption Error List db.err.explain.warn -fillbegin- There were warnings in your circuit, but simulation will continue. Return to edit mode to examine the warnings. -end- db.err.explain.err -fillbegin- There were errors in your circuit. TkGate is unable to continue the simulation. -end- db.err.neededit -fillbegin- You must first switch to Edit mode before navigating to warnings. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Net Properties db.net.caption Net Properties db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.type Net Type db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: New Circuit db.newcirc.directory Directory: db.newcirc.cap New Circuit db.newcirc.exp -fillbegin- Discard the current circuit and start editing a new circuit. -end- db.newcirc.file File Name db.newcirc.topname Top Module Name ############################################################################## # Gate dialog box # db.gate.title TKGate: Gate Properties db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.waveform Clock Waveform db.gate.port Port db.gate.bitws Bits db.gate.side Side db.gate.gtype Gate Type db.gate.gname Gate Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.range Bit Range db.gate.memfilenam Memory File db.gate.modname Function db.gate.general General db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Delay db.gate.parameters Parameters db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.catdiruse Port Placement db.gate.edit Edit db.gate.delete Delete db.gate.add Add db.gate.ff.type Flip-Flop Orientation db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- Flip-Flop with data flowing left to right. -end- db.gate.ff.reverse.hdr Reversed db.gate.ff.reverse.exp -fillbegin- Flip-Flop with data flowing right to left. -end- db.gate.cat.asc.hdr Ascending db.gate.cat.dec.hdr Decending db.gate.cat.asc.exp -fillbegin- Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir Signal Direction db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Multi-Input db.gate.cat.singin.hdr Single-Input db.gate.cat.tran.hdr Bidirectional db.gate.cat.auto.exp -fillbegin- Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- Allow bidirectional (tran) signal flow. Cannot be connected to switches or registers. -end- # # Minimum size of textbox for comment # @db.gate.comment.width *900 @db.gate.comment.height *550 db.gate.tab.General.cap General Properties db.gate.tab.Ports.cap Port Properties db.gate.tab.Delay.cap Delay Properties db.gate.tab.Parameters.cap Module Parameters db.gate.tab.CLOCK.cap Clock Properties db.gate.tab.SWITCH.cap Switch Properties db.gate.tab.DIP.cap DIP Properties db.gate.tab.TAP.cap Tran Properties db.gate.tab.RAM.cap RAM Properties db.gate.tab.ROM.cap ROM Properties db.gate.tab.MODULE.cap Module Properties db.gate.tab.FRAME.cap Frame Properties db.gate.tab.LED.cap LED Properties db.gate.tab.AND.cap AND Properties db.gate.tab.OR.cap OR Properties db.gate.tab.XOR.cap XOR Properties db.gate.tab.MUX.cap Mux Properties db.gate.tab.DEMUX.cap Demux Properties db.gate.tab.CONCAT.cap Concat Properties db.gate.tab.COMMENT.cap Text Properties db.gate.tab.FF.cap Flip-Flop Properties db.gate.tab.General.exp -fillbegin- View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- Set detailed type-specific properties of a gate here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Value db.gate.mparm.exampleA -begin- This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameter can be customized for each instance through this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.switch.state Initial Switch State db.gate.switch.state.on.hdr Switch On db.gate.switch.state.on.exp Switch begins simulation in the "on" state. db.gate.switch.state.off.hdr Switch Off db.gate.switch.state.off.exp Switch begins simulation in the "off" state. db.gate.dip.value Initial DIP Value db.gate.dip.value.exp Initial value of DIP switch at start of simulation. db.gate.dip.value.hex Hex Value: @db.gate.dip.value.exp.width 150 db.gate.tap.select Bit Tap Selection db.gate.tap.exp.bit Select the bit to pull off of the multi-bit bus. db.gate.tap.exp.bus Select the least-significant bit of the bit range to pull off of the multi-bit bus. db.gate.tap.lbl.bit Bit: db.gate.tap.lbl.bus LSB: @db.gate.tap.exp.width *180 db.gate.mux.dataorder Input Ordering db.gate.mux.ord1.hdr Left-to-Right db.gate.mux.ord2.hdr Right-to-Left db.gate.mux.ord1.exp -fillbegin- Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- Order MUX inputs from right to left. -end- db.gate.demux.dataorder Output Ordering db.gate.demux.ord1.hdr Left-to-Right db.gate.demux.ord2.hdr Right-to-Left db.gate.demux.ord1.exp -fillbegin- Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- Order DEMUX outputs from right to left. -end- db.gate.mux.select Selector Style db.gate.mux.sel1.hdr Selector on Left db.gate.mux.sel2.hdr Selector on Right db.gate.mux.sel1.exp -fillbegin- Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- Place the data selector on the right side of the gate. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse Extender Bar Use db.gate.aox.use.hdr Extender Bars db.gate.aox.nouse.hdr No Extender Bars db.gate.aox.use.exp -fillbegin- Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LED Type db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Bar Graph db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- Single-lamp LED display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- Signal bits directly control LED segments. -end- db.seq.back db.hdl.namechange.title HDL Module Name Changed db.hdl.textdisp.title HDL Text Disposition db.hdl.savecap Multiple Modules db.hdl.saveexp -fillbegin- The text buffer for the module you have just edited contains more than one module definition. Please select one of the three actions described on the right. -end- db.hdl.autoedit Auto Edit db.hdl.split Split db.hdl.comment Comment db.hdl.cancel Cancel db.hdl.ignore Ignore db.hdl.autoeditcap Name Mismatch db.hdl.autoeditexp -fillbegin- The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- db.dip.title TkGate: Dip Value cpath.cloops -fillbegin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the gates in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # #print.outto Output to print.title TkGate: Print print.config.title TkGate: Printer Configuration print.scope.title TkGate: Scope Print print.printer Printer: print.file File print.prcmd Print Command: print.prname Printer print.advanced Advanced... print.filename File Name print.epssave Save as Encapsulated Postscript. #print.doctit Document Title #print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.incunused Include unused modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Content Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.rangeselection Range Selection print.scaleselect Scale Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.range Range print.linelen Line Length print.filesel Output to file print.printersel Output to printer print.defaultprinter Default Printer print.pageset Page Setup print.modulesel Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Print print.printtrace.cap Print Trace print.printcirc.cap Print Schematic print.printcirc.out.exp -fillbegin- Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output Output #print.tab.page Page print.tab.modules Modules print.tab.content Content print.tab.advanced Advanced ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Options opt.treelabel Options opt.general General opt.interface Interface opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Print opt.print.output Output opt.print.content Content opt.simulate Simulate opt.simulate.basic Basic opt.simulate.tech Technology opt.simulate.error Error Handling opt.library Libraries opt.library.path Path opt.library.load Auto Loading opt.library.vpd VPD opt.analysis Analysis opt.color Color opt.color.title TkGate: Color Selection opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Available Libraries opt.lib.load.selected Selected Libraries opt.identity Identity opt.site Site Name opt.username User Name opt.libname Library Name: opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.background Background opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.balloon Enable Help Balloons opt.tearawaymenus Enable tear-away main menus opt.safeSave Do safe file saving opt.saveCells Include cells in save files opt.showimage Show side-bar images in dialog boxes opt.novice Novice mode opt.blockDropConnect Wire drop port creation opt.ckpoint.1 Do checkpointing every opt.ckpoint.2 commands. opt.freq Interval opt.beak Enable Special Modes opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.vpopupdelay Pop-Up Delay #opt.initscript Global Initialization Script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Technology Files opt.devfilepath VPD (Virtual Peripheral Device) File Path opt.vlibpath Verilog Library Path opt.vlibnames Base Libraries opt.display Display opt.interaction Interaction opt.input Input opt.security Security opt.undolen Max Undo opt.keybind Key Binding Style opt.useless Enable Useless Features opt.features Save File Features opt.simbase Basic Simulator Options opt.simclock Clock Options opt.cpopts Critical Path Options opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.general.fontset Font Set opt.simulator.savetraces Save probe locations between simlation runs. opt.simulator.noglitch Enable simulator glitch suppression. opt.simulator.err Error Handling opt.simulator.stopany Treat warnings as errors. opt.simulator.showall Always display warnings. opt.simulator.showiferr Display warnings only with errors. opt.simulator.ignore Ignore all warnings. opt.tool.file File opt.tool.edit Edit opt.tool.gateopt Rotation/Alignment opt.tool.gateprop Gate opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Editor Tools opt.tool.module Module opt.tool.tech Technology opt.tool.simctl Simulator Control opt.tool.simaux Simulator Commands opt.tool.simmode Simulator Tools opt.tool.symmode Symbol Editor Tools opt.tool.symedit Cut/Paste opt.tool.symport Ports opt.tool.symshift Bit Shift opt.tool.symopr Bit Ops opt.editor.features Basic Editor Features opt.editor.format Enable Automatic Indenting opt.editor.colorize Enable Code Colorization opt.editor.comments Comments opt.editor.strings Strings opt.editor.reserved Reserved Words opt.editor.gateword Built-in Gates opt.editor.instword Module Instances opt.editor.taskword System Tasks opt.editor.color Color opt.editor.bold Bold opt.editor.italic Italic opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin...end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.vercheck -begin- Periodically check for new versions of tkgate over the Internet. Do not enable unless you have continuous access to the Internet. -end- opt.sec.execlevel The $tkg$exec() system task is opt.sec.exec fully enabled. opt.sec.regexec enabled only for registered functions. opt.sec.noexec disabled. opt.sec.simfeatures Simulator Features opt.sec.send Enable the $tkg$command() system task. opt.sec.open Enable the $fopen() system task. opt.sec.writemem Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle Security Violation Handling opt.sec.stop Stop simulator when disabled feature is used. opt.sec.warn Display warning message when disabled feature is used. opt.sec.ignore Ignore attempted usage of disabled features. opt.html.linkopts Link Options opt.html.browser Browser Command opt.html.email e-Mail Command opt.debug.opt Debugging Options opt.color.editwin Edit Window Colors opt.color.scopewin Scope Window Colors opt.vlibadd.title TkGate: Add Library opt.gen.basetoolbar Core Editor Toolbars opt.gen.simtoolbar Simulation Mode Toolbars opt.gen.symedtoolbar Symbol Editor Toolbars opt.bbar.restore Restore Page Defaults opt.bbar.restoreall Restore All Defaults ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Type igen.side Side igen.size Size igen.bits Bits igen.modname Module Name: #igen.resort Re-sort igen.add Add... igen.delete Delete igen.edit Edit... igen.in in igen.out out igen.inout inout igen.left left igen.right right igen.top top igen.bottom bottom #igen.other other igen.mod Use ports used in module only. igen.int Use ports from exisiting interface only. igen.modint Use both module and interface ports. igen.portsel Port Selection igen.portpos Port Positions igen.portpos.keep Keep exiting port positions when possible. igen.portpos.renew Regenerate all port positionings. igen.caption Generate Interface igen.description -begin- Create a new interface for a module. -end- info.script.error Script Errors module.props.title TkGate: Module Properties module.props Module Properties ipanel.plist Port List ipanel.props Interface Properties #ipanel.itype.change Change Type... #ipanel.itype.edsymbol Edit Symbol... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Auto Generate... ipanel.updateall Synchronize All... ipanel.itype.select Interface Type #ipanel.block.description Standard Interface #ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label Block resize port position handling: ipanel.ppos.fix Fixed ipanel.ppos.scale Scaled #ipanel.ppos.grid Grid ipanel.warn.toblock -begin- You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes # blklst.delete.title TKGate: Module Delete blklst.copy.title TKGate: Module Copy blklst.rename.title TKGate: Module Rename blklst.claim.title TKGate: Claim Module blklst.setroot.title TKGate: Set Root Module blklst.new.title TKGate: Module New blklst.claim Claim Module blklst.to To blklst.from From blklst.name Name blklst.new.cap Create New Module blklst.del.cap Delete Module blklst.copy.cap Copy Module blklst.rename.cap Rename Module blklst.claim.cap Claim Module blklst.setroot.cap Set Root Module blklst.new.exp -fillbegin- Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- Make the specified module the top-level module. -end- find.title TkGate: Find Object find.label Find Objects find.exp -fillbegin- Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase Ignore Case find.result.module Module find.result.type Type find.result.name Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Search Options find.results Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Contains... find.qual.begins Begins with... find.qual.ends Ends with... find.qual.matches Matches... find.dom.label Look for objects in: find.dom.gates Gates find.dom.nets Nets find.dom.text Comment Text find.search Find: find.target Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Circuit Properties circ.label Circuit Properties circ.ident Identification circ.filev File Version circ.file File Name circ.title Circuit Title circ.encoding File Encoding circ.lang File Language circ.discchg Do not warn about discarding changes. circ.flags Options circ.extbar Use extender bars. circ.autostart Enable auto-start of simulation. circ.iniscript Initialization Scripts #circ.noscript No script files selected. #circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.reallyupdate -fillbegin- Do you really want to update the interface of all '%s' instances? -end- circ.reallyoverwrite -fillbegin- Do you really want to overwrite the existing file '%s'? -end- @circ.library.width *500 @circ.library.height *350 circ.general General circ.library Libraries circ.script Script circ.simulator Simulation circ.timescale Default Simulation Time Scale circ.timescale.unit Units: circ.timescale.prec Precision: circ.exp.general -fillbegin- View and modifiy circuit specific properties. These properties will be stored with the circuit when you save. -end- circ.exp.library -fillbegin- Select libraries required by this circuit. Library requirements are saved with the circuit and will be automatically loaded the next time you load this circuit. -end- circ.exp.simulator -fillbegin- View and modifiy simulation preferences for this circuit. -end- ############################################################################## # # Library Manager # libmgr.cap Library Manager libmgr.library Library libmgr.description Description libmgr.status Status libmgr.status.load Loaded libmgr.status.unload Not Loaded libmgr.status.loadp [Loaded] libmgr.status.unloadp [Not Loaded] libmgr.exp -fillbegin- Select libraries to be loaded or unloaded. -end- libmgr.load Load libmgr.unload Unload libmgr.unloadall Unload All libmgr.notedit -fillbegin- Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.rootinterface Can not set interface of root module. err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Gate(s) are anchored and can not be moved. err.protdata Can not modify contents of protected or library module. err.badfind Can't find target '%s'. err.badopendel Can't delete open module. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.badinadd Can't add any more inputs to selected gate. err.badoutadd Can't add any more outputs to selected gate. err.badinoutadd Can't add any more inout pins to selected gate. err.badpinchg Can't change pin types on selected gate. err.badnetname Illegal characters in identifier deleted. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with primitive gate name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Connection refused because wires are part of the same net. err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Connection refused because bit widths do not match. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Unable to exectute printer command '%s'. err.badpsopen Unable to open file '%s' for postscript output. err.badid Illegal identifier '%s'. err.noinvgate Inverters are not allowed on gates of this type. err.protintf Can't modifiy protected interface on module '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Too many breakpoints. Maximum is %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.badedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Can't find net '%s'. err.sim.nogate Can't find gate '%s'. err.sim.badbin Illegal charcter in binary constant '%s'. err.sim.notswitch Gate '%s' is not a switch, dip or register. err.sim.badcmd Unrecognized command '%s' in simulation script. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.run Run-time Error err.sim.cmd Internal Command Error err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Unable to open input file '%s'. err.badlibopen Unable to open library file '%s'. err.nomark Please set a mark with the left mouse button before selecting a gate type. err.badgate Unknown gate type '%s'. err.badportadd Can't add ports to gates of this type. err.modmissing HDL module text missing for module "%s". err.modtoomany Excess module definitions in module "%s". err.modmismatch Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -fillbegin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot No higher level module opened on the module stack. err.editonly Command not valid when in simulation mode. err.simonly Command valid only in simulation mode. err.deltop Can not delete top-level module '%s'. err.delprot Can not delete protected module '%s'. err.nodel No deletable selection. err.modnotdef Module '%s' is undefined. err.moddef The module '%s' already exists. err.primredef Built-in element name '%s' can not be redefined. err.noprop Selected gate has no editable properites. err.openscript Can't open simulation script file '%s' err.oldversion Loaded file with obsolete version number %s (current version is %s). err.futureversion Loaded file saved by future tkgate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.nomodule No selected module. err.nomodop No suitable modules for operation. err.protexec Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable File '%s' is not writable. err.backupfail Unable to create backup file '%s'. err.yy.badprop Ignoring unknown circuit property '%s'. err.yy.baddata Bad data type supplied for circuit property '%s'. err.yy.nosym No current module symbol. err.yy.badicon Bad icon type '%s'. err.yy.toomuchdata Too much icon data. err.yy.nosyminst Missing symbol %d on instance %s of %s. err.yy.badmodprop Ignoring unknown module property '%s'. err.yy.badmoddata Bad data type supplied for module property '%s'. err.yy.badprim Unknown primitive name '%s'. err.yy.nonet Undeclared net '%s'. err.yy.bogussave Bogus save data detected. circuit may be damaged. err.yy.pinformat Illegal pin name format '%s'. err.yy.pinname Pin name '%s' not defined for gate type '%s' err.yy.nonetpos No net for position %d on gate %s. err.yy.baddirective Illegal or badly formed directive '%s'. err.yy.badlocale Unknown locale '%s' in save file. Using English locale. err.corruptnewsave -fillbegin- TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- File was created by tkgate %s, and may not be readable by versions earlier than current version (%s) if you save. -end- err.viewfile Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Selected %s named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.iselwire Selected port '%s' on block '%s'. msg.iselgate Selected %s named '%s' (huh? this message should be impossible). msg.iselblock Selected module interface for '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Found gate named '%s'. msg.foundwire Found wire named '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Saved circuit to '%s'. msg.reallynew Circuit has been modified. Do you really want to discard your changes and create a new circuit? msg.reallyquit Circuit has been modified. Do you really want to exit? msg.notlib Module '%s' is not a library module. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Port size mismatch on input port '%s'. verga.err.OUTPORT Port size mismatch on output port '%s'. verga.err.FLOATNET Net '%s' has no drivers (floating net). verga.err.DIRECTCONN Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR Attempt to write to memory %s with unknown address. verga.err.MEMBITS Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG Array '%s' used in expression without index. verga.err.BADARRAYLHS Array '%s' used without index on left-hand-side. verga.err.BADCLOSE Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG Bad gate instance range expression. verga.err.BADARGVALUE Bad value for argument '%s' in task '%s'. verga.err.DIVZERO Divide by zero. verga.err.NODIV Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT Event wait on assign is illegal. verga.err.PROTTASK Execution of protected system task '%s' blocked. verga.err.NEEDIDENT Expecting identifier for argument %s of task '%s'. verga.err.BADOP Expression operator error in '%s'. verga.err.NOREAD Failed to load source file '%s'. verga.err.MEMFILE Failed to open memory file '%s'. verga.err.WRONGMOD Found module '%s' when expecting '%s'. verga.err.NOTPARM Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR Illegal address range on port '%s'. verga.err.BADADDRSPEC Illegal address range specification '%s'. verga.err.BADCHAR Illegal character (%s) '%s'. verga.err.BADEVENT Illegal event control expression. verga.err.BADCONSTOP Illegal operator in constant expression. verga.err.BADXOP Illegal operator in expression. verga.err.NETREDEF Illegal redefinition of net '%s'. verga.err.BADINOUT Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF Instance of undefined module '%s'. verga.err.BADASGNLHS Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS Invalid left-hand-side in assignment. verga.err.BADOUT Invalid output assignment. verga.err.NOTREG Memories must be declared as register. verga.err.PORTMIX Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE More than one default: in case statement. verga.err.NOMEM No current memory in memory file read. verga.err.BADCMD No such command '%s'. verga.err.CMDNOTNET No such net '%s' in '%s' command. verga.err.MEMNONBLK Non-blocking assignments to memories not implemented. verga.err.NOTPPORT Parameter '%s' is not declared as a port. verga.err.REDEFP Parameter redefines identifier '%s'. verga.err.PORTNOTDEF Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE Range on port '%s' is not numeric. verga.err.BADARRAYRNG Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF Redefinition of dynamic module '%s'. verga.err.REDEF Redefinition of identifier %s. verga.err.PROTTASKSTOP Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM Specified net '%s' is not a memory. verga.err.CMDNOTMEM Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX Syntax error. verga.err.TOOFEWPP Too few parameter ports on instance %s. verga.err.OPENTOOMANY Too many files open in task '%s'. verga.err.TOOMANYPP Too many parameter ports on instance %s. verga.err.NOTOP Top-module '%s' not defined. verga.err.BADOPEN Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET Undefined net '%s' in event control expression. verga.err.NOTASK Undefined task '%s'. verga.err.NOTDEF Undefined variable '%s'. verga.err.BADRANGE Unsupported bit range [%s] on net %s (must be of form [n:0]). verga.err.GATEUNIMP Unimplemented primitive gate instance type. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Write to closed descriptor. verga.err.PRIMPTCOUNT Wrong number of ports on primitive gate instance '%s'. verga.err.CMDARGS Wrong number of arguments in '%s' command. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' called with wrong number of arguments. verga.err.BADSTART Illegal start value in task '%s'. verga.err.BADSTOP Illegal stop value in $readmemb. verga.err.SPECTASKUSG Task '%s' must be used in a specify block. verga.err.BADSPECTASK Task '%s' can not be used in a specify block. verga.err.TIMING Timing violation at %s in %s[%s] %s. verga.err.NOIFDEF No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP Loops in modules with path-delay specification are unsupported. verga.err.PATHDCOND DelaMust set through both # expression and specify block. verga.err.TASKREDEF Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC Task '%s' used as function. verga.err.FUNCASTASK Function '%s' used as task. verga.err.TASKBADTYPE Non-register type used in task or function. verga.err.TASKBADPORT Only input ports are allowed on functions. verga.err.TIMESCALEU Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES Invalid syntax in `timescale declaration. verga.err.TIMESCALEX Units must be larger than precision in `timescale declaration. verga.err.TIMESCALEAN Design contains some modules with `timescale and some without. verga.err.BADPORTTYPE Invalid type declaration used on port '%s' verga.err.BADVALUE Bad numeric value '%s'. verga.err.NONEXPCTL Event control @(*) applied to non-expression. verga.err.NONSTATCTL Event control @(*) applied to non-statment. verga.err.IE_TASK Task definition '%s' found outside module - internal error. verga.err.IE_NONET Failed to find net '%s' - internal error. verga.err.IE_NOOP Can not find operator description -- internal error. verga.err.IE_BADEXP Unexpected expression type %s - internal error. verga.err.IE_BADVAR Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE Unexpected internal state at %s - internal error. verga.err.IE_RETURN Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Move all items to selected list. ho.setsel.alll Move all items to unselected list. ho.setsel.ltor Move highlighted items to selected list. ho.setsel.rtol Move highlighted items to unselected list. ho.net.in Single-Bit Input ho.net.out Single-Bit Output ho.net.inout Single-Bit Inout ho.net.in2 Multi-Bit Input ho.net.out2 Multi-Bit Output ho.net.inout2 Multi-Bit Inout ho.net.wire Single-Bit Wire (Name Visible) ho.net.wire2 Multi-Bit Wire (Name Visible) ho.net.hwire Single-Bit Wire (Name Hidden) ho.net.hwire2 Multi-Bit Wire (Name Hidden) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Save, load of circuit files ho.opt.tool.edit Cut, Paste and Find operations ho.opt.tool.gateopt Gate rotation and alignment operations ho.opt.tool.gateprop Basic editing of gates ho.opt.tool.undo Undo and redo operations ho.opt.tool.zoom Zoom in and zoom out ho.opt.tool.mode Select the editing tool ho.opt.tool.module Create, delete, rename,etc. of module definitions ho.opt.tool.tech Select default technology for gates ho.opt.tool.simctl Start, stop and pause of simulator ho.opt.tool.simaux Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.simmode Choose between the select and scroll tool in simulator. ho.opt.tool.symmode Selecting editing tool in symbol editor ho.opt.tool.symedit Cut and paste operations for symbol editor ho.opt.tool.symport Port rotation operations for symbol editor ho.opt.tool.symshift Shift the bit map or portion of bitmap ho.opt.tool.symopr Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.saveas Save circuit to specified file. ho.print Print current circuit. ho.library Open the library manager. ho.symed.tab.normal -begin- Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- Edit the selected symbol bitmap. -end- ho.simmove -begin- Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new gate Move gates and wires Connect wires By double-clicking you can: Edit gate, wire and port properties Edit comment text -end- ho.delgat -begin- Delete Gate - Use this tool to delete gates. -end- ho.cutw -begin- Cut Wire - Use this tool to cut wires. -end- ho.scroll -begin- Scroll - Grab and drag the editing canvas. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from gate ports. -end- ho.bitw -begin- Net Attributes - Use this tool to change the attributes of a net. The bit size and wire type of nets selected with this tool will be changed to the those shown in the drop-down boxes to the right. -end- ho.ipanel.select -begin- Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- Add a port to the module. You can also double-click after the last item to add port. -end- ho.ipanel.deleteport -begin- Delete the selected port. -end- ho.ipanel.editport -begin- Edit the selected port. You can also double-click to edit a field in a port. -end- ho.ipanel.generate -begin- Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.ipanel.updateall -begin- Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.ipanel.prot -begin- Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Open the selected module. ho.mod.close Close the current module. ho.mod.new Create a new module type. ho.mod.del Delete a module. ho.mod.copy Copy a module. ho.mod.rename Rename a module. ho.mod.claim -begin- Convert a library module to a regular module. -end- ho.mod.setroot -begin- Designate a module to be the root module. -end- ho.mod.type.allparts Set of Libraries ho.mod.type.partlib Library ho.mod.type.part Library module ho.mod.type.unknown Unknown module type ho.mod.type.unused Set of unused modules ho.mod.type.conflict Module recursion ho.mod.type.root Top-level module ho.mod.type.netlist Netlist module ho.mod.type.Lnetlist Netlist module (locked) ho.mod.type.hdl HDL module ho.mod.type.Lhdl HDL module (locked) ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.tab.edit -begin- Primary editing mode. -end- ho.tab.interface -begin- Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Find critical paths in a circuit. -end- ho.log -begin- Log of tkgate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. Breakpoints can be edited in both simulation mode and edit mode. -end- ho.simexec -begin- Manage the set of active scripts. -end- ho.simoptions -begin- Set various options that control the simulation. -end- ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.modlist -begin- List of all modules currently loaded in alphabetical order. Drag modules to the edit window to create new instances. -end- ho.modtree -begin- List of all modules currently in a hierarchical list. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- List of nets in the current module. The symbol to the left of the name indicates whether the net is single bit (green) or multi-bit (red). An "A" shown in the symbol indicates that the net name is marked as visible. -end- ho.ports -begin- List of ports on the interface of the module displayed in the edit window. The symbol before the port indicates the direction of the port. -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, tkgate is in edit mode. If the quadrapedal AND gate is shown, tkgate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from tkgate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TKGate. ho.print.selcur Print only the current module in the TKGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.print.timegraph -begin- The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.autostart -begin- If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.circuit.file -begin- This is the file name from which the current circuit was loaded. -end- ho.circuit.ver -begin- This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.encoding -begin- Use this encoding for save files. -end- ho.circuit.language -begin- Use fonts for this encoding to display circuit data. -end- ho.circuit.title -begin- Description of your circuit. This title is used on printed output. -end- ho.cmd.bitw -begin- Wires selected with the ribbon cable tool will be set to this bit width. -end- ho.edgat.signam -begin- The name of the selected signal on the selected gate. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the gate. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected gate. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected gate. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Type of the gate. ho.edgat.gname Name of this gate instance. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx X coordinate of gate. ho.edgat.gy Y coordinate of gate. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint -begin- Print the logic trace range selected using the right mouse button. Shift-right click can be used to expand the selected region. The range visible in the scope view is used when there is no selection. -end- ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- Specifies the basic font size to use in the tkgate interface. This option will not take effect until restarting tkgate. -end- ho.opt.sec.send -begin- Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the tkgate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking tkgate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to tkgate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- Save tkgate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- If this option is enabled, rapidly changing inputs to a gate will cause the gate to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.savetraces -begin- Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.opt.sim.tech -begin- List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in gates. -end- ho.opt.sim.err -begin- Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- List of directories to search for tkgate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- List of libaries that should automatically be loaded when tkgate starts. -end- ho.opt.lib.vpd -begin- List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.name -begin- User name to be used on tkgate generated reports such as circuit printouts. -end- ho.opt.site -begin- The name of the site where tkgate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. Unset only if you are having problems on your display. -end- ho.opt.showimage -begin- Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.tearawaymenus -begin- If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.blockDropConnect -begin- Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this option, the useless features checkbox will no longer appear in this dialog box. The only way to see the useless features again will be to edit your .tkgate2-properties file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when simulation of any circuit is initiated. Do not use this for circuit specific scripts, use the circuit properties instead. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. Use the name of the net to which the clock is attached. -end- ho.opt.keybind -begin- Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- Default technology for new gates. Affects delay of gates. To change the technology of a specific gate, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this gate. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.symed.point -begin- Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift Shift selected pixels right. ho.symed.lshift Shift selected pixels left. ho.symed.ushift Shift selected pixels up. ho.symed.dshift Shift selected pixels down. ho.symed.cwrotate Rotate selected pixels clockwise. ho.symed.ccwrotate Rotate selected pixels counter-clockwise. ho.symed.autobold Make selected image bold. ho.symed.resize Resize the image editor. ho.symed.import Import image from file. ho.symed.export Export image to file. ho.tool.currot -begin- Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotate selected gate(s) counter-clockwise. ho.tool.brotate Rotate selected gate(s) clockwise. ho.tool.valgn Align selected gate(s) vertically. ho.tool.halgn Align selected gate(s) horizontally. ho.tool.cut Cut selection. ho.tool.copy Copy selection. ho.tool.paste Paste from cut buffer. ho.tool.find Find gate, wire or text. ho.tool.addport Add a port to the selected gate. ho.tool.anchor Anchor the selected gate(s). ho.tool.unanchor Unanchor the selected gate(s). ho.tool.replicate Replicate a gate. ho.tool.delete Delete the selection. tkgate-2.0-b10/locale/en/messages000644 001751 001751 00000253512 11150371405 017406 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Feb 22 19:51:17 2009 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file are declarations. The # declarations should normally be specified before any tags are specified. # The currently supported declarations are: # # \font-encoding code # \messages-encoding code # \verilog-encoding code # \language name # # where "code" is a font encoding. Typical encodings are: # # iso8859-1 English and many European languages # iso8859-2 Some other European languages (e.g., Bosnian, Czech, Polish) # euc-ja Japanese EUC # utf-8 Unicode # # "\font-encoding" selects the encoding to use when displaying strings from # comments and frames in the main edit window. It should be "iso8859-1" or # "iso8859-2". # # "\messages-encoding" specifies the encoding of this messages file. # # "\verilog-encoding" specifies the default encoding to use for verilog files # when editing files in this locale. # # "\language" specifies the full language name of this messages file. It should # be after the \messages-encoding delcaration so that it will be processed # using the correct encoding. # ############################################################################## \font-encoding iso8859-1 \display-encoding iso8859-1 \messages-encoding iso8859-1 \verilog-encoding iso8859-1 \postscript-encoding iso8859-1 \language English ############################################################################## # # basic strings # b.new New... b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel #b.open Open... #b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete #b.deleteb Delete... b.remove Remove b.apply Apply b.anchor Anchor b.tech Technology #b.enable Enable #b.disable Disable #b.flush Clear ############################################################################## # # Main tab strings # tab.edit Edit tab.editintr Interface tab.simulate Simulate tab.cpath Critical Path ############################################################################# # # Module tree/list box # module.tree Tree module.list List module.box.libraries Libraries ############################################################################# # # Tabs for Nets/Ports # sidetab.nets Nets sidetab.ports Ports ############################################################################# # # MsgMgr strings (including breakpoint and script handling) # @mm.width 7 mm.add Add... mm.delete Delete mm.edit Edit... mm.enable Enable mm.disable Disable ############################################################################## # Menu strings # # Menu strings (tags beginning with "menu.") can take an option prefix consisting # of a number and a colon. If this prefix exists, it indicates the character # position in the string that will be underlined. This enables keyboard shortcuts # using the Alt key. # menu.file 0:File menu.edit 0:Edit menu.tool 0:Tool menu.symbol 0:Symbol menu.simulate 0:Simulate menu.module 0:Module menu.interface 0:Interface menu.format 0:Format menu.make 0:Components menu.help 0:Help menu.file.new 0:New... menu.file.open 0:Open... menu.file.openlib 0:Library Manager... menu.file.save 0:Save menu.file.saveas 5:Save As... menu.file.print 0:Print... menu.file.quit 0:Quit menu.file.cprop 0:Circuit Properties... menu.file.import 0:Import Image... menu.file.export 0:Export Image... menu.edit.undo 0:Undo menu.edit.redo 0:Redo menu.edit.cut 0:Cut menu.edit.copy 3:Copy menu.edit.paste 0:Paste menu.edit.overlay 0:Overlay Paste menu.edit.selall 0:Select All menu.edit.find 0:Find... menu.edit.zoomin 5:Zoom In menu.edit.zoomout 5:Zoom Out menu.edit.rshift 10:Bit Shift Right menu.edit.lshift 10:Bit Shift Left menu.edit.ushift 10:Bit Shift Up menu.edit.dshift 10:Bit Shift Down menu.edit.cwrotate 11:Bit Rotate C-W menu.edit.ccwrotate 15:Bit Rotate C-C-W menu.edit.pcwrotate 12:Port Rotate C-C-W menu.edit.pccwrotate 16:Port Rotate C-C-W menu.edit.autobold Boldify Bits menu.edit.resize Resize Bitmap menu.tool.move 0:Move/Connect menu.tool.delg 0:Delete Component menu.tool.cutw 0:Cut Wire menu.tool.inv 0:Invert menu.tool.bitw 0:Bit Width menu.tool.debug 0:Debug menu.tool.point 0:Point menu.tool.line 0:Line menu.tool.rect 0:Rectangle menu.tool.fillrect 0:Fill Rectangle menu.tool.port 0:Port menu.tool.select 0:Select Region menu.tool.options 0:Options... menu.format.addport 4:Add Port menu.format.ioset 0:Set Type menu.format.anchor 0:Anchor Selected menu.format.unanchor 0:Unanchor Selected menu.format.prop 0:Instance Properties... menu.format.del 0:Delete menu.format.settech 0:Set Technology menu.format.rot 0:Rotation menu.format.rot.0 17:Default Rotation 0 menu.format.rot.90 17:Default Rotation 90 menu.format.rot.180 17:Default Rotation 180 menu.format.rot.270 17:Default Rotation 270 menu.format.rot.rotate 10:Clockwise Rotate menu.format.rot.brotate 0:Counter-Clockwise Rotate menu.format.algnv 6:Align Ver. menu.format.algnh 6:Align Horz. menu.tool.tclshell 0:Tcl Shell menu.tool.rep 0:Replicate menu.simulate.begin 0:Begin Simulation menu.simulate.end 0:End Simulation menu.simulate.addprobe 0:Add/Delete Probe menu.simulate.run 0:Run menu.simulate.pause 0:Pause menu.simulate.step 0:Step Epoch(s) menu.simulate.cycle 5:Step Cycle menu.simulate.break 0:Breakpoint... menu.simulate.script 1:Exec. Script... menu.simulate.load 1:Load Memory... menu.simulate.dump 1:Dump Memory... menu.simulate.view 1:View Memory... menu.module.open 0:Open menu.module.close 0:Close menu.module.new 0:New... menu.module.del 0:Delete... menu.module.copy 1:Copy... menu.module.rename 0:Rename... menu.module.claim 1:Claim... menu.module.setroot 1:Set As Root... menu.module.prop 0:Properties... menu.module.interface 0:Interface menu.module.interface.set 0:Set As Default menu.module.interface.update 1:Sync. to Default menu.module.interface.updateall 6:Sync. All to Default... menu.module.interface.edit 0:Edit... menu.module.interface.auto 5:Auto Generate... menu.help.about 0:About... menu.help.license 0:License... menu.help.doc 0:Documentation... menu.help.tut 1:Tutorials menu.help.home 1:Home Page menu.help.example 1:Examples ############################################################################# # Scope Menu # menu.scope_file 0:File menu.scope_sim 0:Simulate menu.scope_trace 0:Trace menu.scope_help 0:Help menu.scope_file.ptrace 0:Print Trace... menu.scope_file.close 0:Close menu.scope_trace.zoomin 5:Zoom In menu.scope_trace.zoomout 5:Zoom Out menu.scope_sim.addprobe 0:Add/Delete Probe menu.scope_sim.run 0:Run menu.scope_sim.pause 0:Pause menu.scope_sim.step 0:Step Epoch(s) menu.scope_sim.cycle 5:Step Cycle menu.scope_sim.break 0:Breakpoint... menu.scope_sim.script 1:Exec. Script... menu.scope_sim.load 1:Load Memory... menu.scope_sim.dump 1:Dump Memory... menu.scope_help.about 0:About... menu.scope_help.license 0:License... menu.scope_help.doc 0:Documentation... mod.intf Interface port.title TkGate: Port Properties port.parms Port Parameters port.in In port.out Out port.inout InOut ############################################################################## # # Tags for built-in gate types # gm.io I/O gm.gate Gate gm.rgate Reduction gm.msi MSI gm.alu ALU gm.mem Memory gm.mod Module gm.comment Comment gm.script Verilog Script gm.frame Frame gm.io.switch Switch gm.io.dip DIP Switch gm.io.ground Ground gm.io.vdd Vdd gm.io.merge Concat gm.io.clock Clock gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gm.gate.and AND gm.gate.nand NAND gm.gate.or OR gm.gate.nor NOR gm.gate.xor XOR gm.gate.xnor XNOR gm.gate.buf Buffer gm.gate.inv Inverter gm.gate.tribuf Tri-Buffer gm.gate.nmos NMOS gm.gate.pmos PMOS gm.rgate.and AND gm.rgate.nand NAND gm.rgate.or OR gm.rgate.nor NOR gm.rgate.xor XOR gm.rgate.xnor XNOR gm.alu.add Adder gm.alu.mult Multiplier gm.alu.div Divider gm.alu.lshift Left Shift gm.alu.rshift Right Shift gm.alu.arshift Arith. Right Shift gm.alu.roll Roll gm.mem.reg Register gm.mem.ff D Flip-Flop gm.mem.rff Rev. D Flip-Flop gm.mem.ram RAM gm.mem.rom ROM gm.mem.jkff JK Flip-Flop gm.mem.rjkff Rev. JK Flip-Flop gm.msi.21mux 2-1 Multiplexor gm.msi.41mux 4-1 Multiplexor gm.msi.81mux 8-1 Multiplexor gm.msi.12dec 1-2 Decoder gm.msi.14dec 1-4 Decoder gm.msi.18dec 1-8 Decoder gm.msi.12demux 1-2 Demultiplexor gm.msi.14demux 1-4 Demultiplexor gm.msi.18demux 1-8 Demultiplexor gm.mod.inst Module Instance gm.mod.in Module Input gm.mod.out Module Output gm.mod.inout Module InOut tutorial.prev PREVIOUS tutorial.next NEXT tutorial.chapter CHAPTER LIST tutorial.reload RELOAD ############################################################################## # # Popup menus # pop.make Components pop.tool Tool pop.edit.paste Paste pop.edit.cut Cut pop.edit.copy Copy pop.port.in In pop.port.out Out pop.port.inout InOut pop.wire.addseg Add Wire Segment pop.wire.prop Net Properties... pop.wire.hidesize Hide Bit Width pop.wire.showsize Show Bit Width pop.wire.hidelabel Hide Label pop.wire.hidealllabel Hide All Labels pop.wire.clearalllabel Clear All Labels pop.wire.showlabel Show Label pop.gate.open Open pop.gate.close Close pop.gate.prop Instance Properties... pop.gate.addport Add Port pop.gate.addin Add Input... pop.gate.addout Add Output... pop.gate.addinout Add InOut... pop.gate.anchor Anchor/Unanchor pop.gate.settech Set Technology pop.gate.delete Delete pop.gate.ioset Set Type pop.module.new New... pop.module.del Delete... pop.module.copy Copy... pop.module.rename Rename... pop.module.claim Claim... pop.module.setroot Set As Root... pop.module.prop Module Properties... pop.module.int Edit Interface... pop.simulate.end End Simulation pop.simulate.begin Begin Simulation pop.simulate.addprobe Add/Delete Probe pop.simulate.delprobe Delete Probe pop.simulate.run Run pop.simulate.pause Pause pop.simulate.step Step Epoch(s) pop.simulate.cycle Step Cycle pop.simulate.break Breakpoint... pop.simulate.script Exec. Script... pop.simulate.load Load Memory... pop.simulate.dump Dump Memory... pop.simulate.view View Memory... pop.interface Interface pop.interface.set Set As Default pop.interface.update Sync. to Default pop.interface.updateall Sync. All to Default... pop.interface.edit Edit... pop.interface.auto Auto Generate... pop.interface.replace Replace pop.igen.type Type pop.igen.side Side pop.igen.size Size pop.igen.delete Delete pop.igen.in in pop.igen.out out pop.igen.inout inout pop.igen.left left pop.igen.right right pop.igen.top top pop.igen.bottom bottom pop.igen.other other pop.library.mgr Library Manager... pop.library.close Unload ############################################################################## # # Symbol editor strings # #symed.bsave Store #symed.file File #symed.file.load Load Bitmap... #symed.file.save Save Bitmap... #symed.file.updateclose Close and Update #symed.file.discardclose Close and Discard #symed.help Help #symed.help.about About... #symed.edit Edit #symed.edit.cut Cut #symed.edit.copy Copy #symed.edit.paste Paste #symed.edit.overlay Overlay Paste #symed.edit.rclock Rotate Clockwise #symed.edit.rcclock Rotate Counter-Clockwise #symed.module Module #symed.modes Modes #symed.cutpaste Cut/Paste #symed.rotate Port Rotation #symed.zoom Zoom #symed.cancel Cancel #symed.update Update symed.tab.normal UnSelected symed.tab.select Selected symed.link Link selected to unselected # width of symbol editor tabs ############################################################################## ## memory viewer # memview.title Memory Viewer memview.exp -fillbegin- View and modify the contents of a RAM or ROM component. Select memory page, then type new hex values to change memory content. -end- ############################################################################## scope.title TkGate: Scope scope.emptymsg Double-click on a wire to add or delete a trace. comment.empty [Double click to add text.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: itype Type: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file File Name db.mod.type Type db.mod.flags Flags db.mod.dataprot Prevent editing of module definition. db.mod.intfprot Prevent all interface changes. db.mod.edprot Prevent edit mode interface changes. db.mod.props Properties db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netlist Netlist db.mod.hdl HDL db.mod.netexpl -begin- Define module using a graphical editor to connect wires between components. -end- db.mod.hdlexpl -begin- Define module using a textual editor to describe behavior in Verilog. -end- ############################################################################# # Error List Dialog box # db.err.title TkGate: Error List db.err.caption Error List db.err.explain.warn -fillbegin- There were warnings in your circuit, but simulation will continue. Return to edit mode to examine the warnings. -end- db.err.explain.err -fillbegin- There were errors in your circuit. TkGate is unable to continue the simulation. -end- db.err.neededit -fillbegin- You must first switch to Edit mode before navigating to warnings. -end- ############################################################################# # Net Dialog Box # db.net.title TkGate: Net Properties db.net.caption Net Properties db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.type Net Type db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # # New circuit dialog box # db.newcirc.title TkGate: New Circuit db.newcirc.directory Directory: db.newcirc.cap New Circuit db.newcirc.exp -fillbegin- Discard the current circuit and start editing a new circuit. -end- db.newcirc.file File Name db.newcirc.topname Top Module Name ############################################################################## # Gate dialog box # db.gate.title TKGate: Component Properties db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Period db.gate.phase Phase db.gate.duty Duty db.gate.waveform Clock Waveform db.gate.port Port db.gate.bitws Bits db.gate.side Side db.gate.gtype Type db.gate.gname Instance Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.range Bit Range db.gate.memfilenam Memory File db.gate.modname Type db.gate.general General db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Delay db.gate.parameters Parameters db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.catdiruse Port Placement db.gate.edit Edit db.gate.delete Delete db.gate.add Add db.gate.ff.type D Flip-Flop Orientation db.gate.ff.normal.hdr Normal db.gate.ff.normal.exp -fillbegin- D Flip-Flop with data flowing left to right. -end- db.gate.ff.reverse.hdr Reversed db.gate.ff.reverse.exp -fillbegin- D Flip-Flop with data flowing right to left. -end- db.gate.jkff.type JK Flip-Flop Orientation db.gate.jkff.normal.hdr Normal db.gate.jkff.normal.exp -fillbegin- JK Flip-Flop with data flowing left to right. -end- db.gate.jkff.reverse.hdr Reversed db.gate.jkff.reverse.exp -fillbegin- JK Flip-Flop with data flowing right to left. -end- db.gate.cat.asc.hdr Ascending db.gate.cat.dec.hdr Decending db.gate.cat.asc.exp -fillbegin- Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir Signal Direction db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Multi-Input db.gate.cat.singin.hdr Single-Input db.gate.cat.tran.hdr Bidirectional db.gate.cat.auto.exp -fillbegin- Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- Allow bidirectional (tran) signal flow. Cannot be connected to switches or registers. -end- # # Minimum size of textbox for comment # @db.gate.comment.width *900 @db.gate.comment.height *550 db.gate.tab.General.cap General Properties db.gate.tab.Ports.cap Port Properties db.gate.tab.Delay.cap Delay Properties db.gate.tab.Parameters.cap Module Parameters db.gate.tab.CLOCK.cap Clock Properties db.gate.tab.SWITCH.cap Switch Properties db.gate.tab.DIP.cap DIP Properties db.gate.tab.TAP.cap Tran Properties db.gate.tab.RAM.cap RAM Properties db.gate.tab.ROM.cap ROM Properties db.gate.tab.MODULE.cap Module Properties db.gate.tab.FRAME.cap Frame Properties db.gate.tab.LED.cap LED Properties db.gate.tab.AND.cap AND Properties db.gate.tab.OR.cap OR Properties db.gate.tab.XOR.cap XOR Properties db.gate.tab.MUX.cap Mux Properties db.gate.tab.DEMUX.cap Demux Properties db.gate.tab.DECODER.cap Decoder Properties db.gate.tab.CONCAT.cap Concat Properties db.gate.tab.COMMENT.cap Text Properties db.gate.tab.FF.cap D Flip-Flop Properties db.gate.tab.JKFF.cap JK Flip-Flop Properties db.gate.tab.SCRIPT.cap Verilog Script db.gate.tab.General.exp -fillbegin- View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.Parameters.exp -fillbegin- Set the module parameters for this instance of this module if any are defined. Module parameters are used to configure delays and constant values used in a module. -end- db.gate.tab.details.exp -fillbegin- Set detailed type-specific properties of a component here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.MODULE.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.DECODER.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.FF.exp `db.gate.tab.details.exp db.gate.tab.JKFF.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.tab.SCRIPT.exp -fillbegin- Enter free-form Verilog code here to be included as part of this module. -end- db.gate.mparm.parameter Parameter db.gate.mparm.value Value db.gate.mparm.exampleA -begin- This module does not have any parameters. Parameters can be added to Verilog text modules. The value of each parameter can be customized for each instance through this dialog box. Module parameters are declared in a parenthesized list starting with a '#' character. Below is an example module declaration with a parameter named "base_value" that has a default value of 1'b1. -end- db.gate.mparm.exampleB -begin- module foo #(.base_value(1'b1)) (Z,A,B); assign Z = A ^ B ^ base_value; endmodule -end- db.gate.switch.state Initial Switch State db.gate.switch.state.on.hdr Switch On db.gate.switch.state.on.exp Switch begins simulation in the "on" state. db.gate.switch.state.off.hdr Switch Off db.gate.switch.state.off.exp Switch begins simulation in the "off" state. db.gate.switch.shownet Show Net Name db.gate.switch.shownet.on.hdr Show db.gate.switch.shownet.on.exp Show the name of the net next to switch. db.gate.switch.shownet.off.hdr Hide db.gate.switch.shownet.off.exp Do not show the name of the net next to switch. db.gate.dip.value Initial DIP Value db.gate.dip.value.exp Initial value of DIP switch at start of simulation. db.gate.dip.value.hex Hex Value: @db.gate.dip.value.exp.width 150 db.gate.dip.shownet Show Net Name db.gate.dip.shownet.on.hdr Show db.gate.dip.shownet.on.exp Show the name of the net next to dip. db.gate.dip.shownet.off.hdr Hide db.gate.dip.shownet.off.exp Do not show the name of the net next to dip. db.gate.tap.select Bit Tap Selection db.gate.tap.exp.bit Select the bit to pull off of the multi-bit bus. db.gate.tap.exp.bus Select the least-significant bit of the bit range to pull off of the multi-bit bus. db.gate.tap.lbl.bit Bit: db.gate.tap.lbl.bus LSB: @db.gate.tap.exp.width *180 db.gate.mux.dataorder Input Ordering db.gate.mux.ord1.hdr Left-to-Right db.gate.mux.ord2.hdr Right-to-Left db.gate.mux.ord1.exp -fillbegin- Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- Order MUX inputs from right to left. -end- db.gate.mux.select Selector Placement db.gate.mux.sel1.hdr On Left db.gate.mux.sel2.hdr On Right db.gate.mux.sel1.exp -fillbegin- Place the data selector on the left side of the MUX. -end- db.gate.mux.sel2.exp -fillbegin- Place the data selector on the right side of the MUX. -end- db.gate.demux.dataorder Output Ordering db.gate.demux.ord1.hdr Left-to-Right db.gate.demux.ord2.hdr Right-to-Left db.gate.demux.ord1.exp -fillbegin- Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- Order DEMUX outputs from right to left. -end- db.gate.demux.select Select Placement db.gate.demux.sel1.hdr On Left db.gate.demux.sel2.hdr On Right db.gate.demux.sel1.exp -fillbegin- Place the select input on the left side of the DEMUX. -end- db.gate.demux.sel2.exp -fillbegin- Place the select input on the right side of the DEMUX. -end- db.gate.decoder.dataorder Output Ordering db.gate.decoder.ord1.hdr Left-to-Right db.gate.decoder.ord2.hdr Right-to-Left db.gate.decoder.ord1.exp -fillbegin- Order DECODER outputs from left to right. -end- db.gate.decoder.ord2.exp -fillbegin- Order DECODER outputs from right to left. -end- db.gate.decoder.select Enable Placement db.gate.decoder.sel1.hdr On Left db.gate.decoder.sel2.hdr On Right db.gate.decoder.sel1.exp -fillbegin- Place the enable input on the left side of the DECODER. -end- db.gate.decoder.sel2.exp -fillbegin- Place the enable input on the right side of the DECODER. -end- db.gate.aox.extbaruse Extender Bar Use db.gate.aox.use.hdr Extender Bars db.gate.aox.nouse.hdr No Extender Bars db.gate.aox.use.exp -fillbegin- Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LED Type db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Bar Graph db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- Single-lamp LED display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- Signal bits directly control LED segments. -end- db.seq.back db.hdl.namechange.title HDL Module Name Changed db.hdl.textdisp.title HDL Text Disposition db.hdl.savecap Multiple Modules db.hdl.saveexp -fillbegin- The text buffer for the module you have just edited contains more than one module definition. Please select one of the three actions described on the right. -end- db.hdl.autoedit Auto Edit db.hdl.split Split db.hdl.comment Comment db.hdl.cancel Cancel db.hdl.ignore Ignore db.hdl.autoeditcap Name Mismatch db.hdl.autoeditexp -fillbegin- The textual description of the module does not match the expected name. Please select an option to the right to handle the discrepancy. -end- db.dip.title TkGate: Dip Value cpath.cloops -fillbegin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the components in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # #print.outto Output to print.title TkGate: Print print.config.title TkGate: Printer Configuration print.scope.title TkGate: Scope Print print.printer Printer: print.file File print.prcmd Print Command: print.prname Printer print.advanced Advanced... print.filename File Name print.epssave Save as Encapsulated Postscript. #print.doctit Document Title #print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.incunused Include unused modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Content Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.rangeselection Range Selection print.scaleselect Scale Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.range Range print.linelen Line Length print.filesel Output to file print.printersel Output to printer print.defaultprinter Default Printer print.pageset Page Setup print.modulesel Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Print print.printtrace.cap Print Trace print.printcirc.cap Print Schematic print.printcirc.out.exp -fillbegin- Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output Output #print.tab.page Page print.tab.modules Modules print.tab.content Content print.tab.advanced Advanced ############################################################################## # # Options dialog # # Number of columns in list of toolbars @opt.tool.columns 2 # Width of columns in list of toolbars @opt.tool.colwidth 30 # Width of image sidebar @opt.sidebar.width *200 # Width of tree box with option categories @opt.tree.width *150 opt.title TkGate: Options opt.treelabel Options opt.general General opt.interface Interface # opt.circuit Circuit Defaults opt.toolbars Toolbars opt.toolbars.edit Editor opt.toolbars.sim Simulation opt.toolbars.symed Symbol Editor opt.editor HDL opt.print Print opt.print.output Output opt.print.content Content opt.simulate Simulate opt.simulate.basic Basic opt.simulate.tech Technology opt.simulate.error Error Handling opt.library Libraries opt.library.path Path opt.library.load Auto Loading opt.library.vpd VPD opt.analysis Analysis opt.color Color opt.color.title TkGate: Color Selection opt.color.edit Editor opt.color.scope Scope opt.color.hdl HDL Editor opt.html HTML opt.debug Debug opt.lib.load.available Available Libraries opt.lib.load.selected Selected Libraries opt.identity Identity opt.site Site Name opt.username User Name opt.libname Library Name: opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.background Background opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.balloon Enable Help Balloons opt.tearawaymenus Enable tear-away main menus opt.safeSave Do safe file saving opt.saveCells Include cells in save files opt.showimage Show side-bar images in dialog boxes opt.novice Novice mode opt.blockDropConnect Wire drop port creation opt.ckpoint.1 Do checkpointing every opt.ckpoint.2 commands. opt.freq Interval opt.beak Enable Special Modes opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.vpopupdelay Pop-Up Delay #opt.initscript Global Initialization Script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Technology Files opt.devfilepath VPD (Virtual Peripheral Device) File Path opt.vlibpath Verilog Library Path opt.vlibnames Base Libraries opt.display Display opt.interaction Interaction opt.input Input opt.security Security opt.undolen Max Undo opt.keybind Key Binding Style opt.useless Enable Useless Features opt.features Save File Features opt.simbase Basic Simulator Options opt.simclock Clock Options #opt.circdefaults Circuit Defaults opt.cpopts Critical Path Options opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.general.fontset Font Set opt.simulator.savetraces Save probe locations between simlation runs. opt.simulator.noglitch Enable simulator glitch suppression. opt.simulator.err Error Handling opt.simulator.stopany Treat warnings as errors. opt.simulator.showall Always display warnings. opt.simulator.showiferr Display warnings only with errors. opt.simulator.ignore Ignore all warnings. opt.tool.file File opt.tool.edit Edit opt.tool.gateopt Rotation/Alignment opt.tool.gateprop Gate opt.tool.undo Undo/Redo opt.tool.zoom Zoom opt.tool.mode Editor Tools opt.tool.module Module opt.tool.tech Technology opt.tool.simctl Simulator Control opt.tool.simaux Simulator Commands opt.tool.simmode Simulator Tools opt.tool.symmode Symbol Editor Tools opt.tool.symedit Cut/Paste opt.tool.symport Ports opt.tool.symshift Bit Shift opt.tool.symopr Bit Ops opt.editor.features Basic Editor Features opt.editor.format Enable Automatic Indenting opt.editor.colorize Enable Code Colorization opt.editor.comments Comments opt.editor.strings Strings opt.editor.reserved Reserved Words opt.editor.gateword Built-in Gates opt.editor.instword Module Instances opt.editor.taskword System Tasks opt.editor.color Color opt.editor.bold Bold opt.editor.italic Italic opt.editor.indentlevel Indentation per level: opt.editor.beginindent Make begin...end flush with enclosing level. opt.editor.movesel Enable drag-and-drop of selection. opt.editor.returntab Auto indent after return. opt.vercheck -begin- Periodically check for new versions of TkGate over the Internet. Do not enable unless you have continuous access to the Internet. -end- opt.sec.execlevel The $tkg$exec() system task is opt.sec.exec fully enabled. opt.sec.regexec enabled only for registered functions. opt.sec.noexec disabled. opt.sec.simfeatures Simulator Features opt.sec.send Enable the $tkg$command() system task. opt.sec.open Enable the $fopen() system task. opt.sec.writemem Enable the $writememb() and $writememh() system tasks. opt.sec.enqueue Enable the $tkg$recv() and $tkg$send() system tasks. opt.sec.handle Security Violation Handling opt.sec.stop Stop simulator when disabled feature is used. opt.sec.warn Display warning message when disabled feature is used. opt.sec.ignore Ignore attempted usage of disabled features. opt.html.linkopts Link Options opt.html.browser Browser Command opt.html.email e-Mail Command opt.debug.opt Debugging Options opt.color.editwin Edit Window Colors opt.color.scopewin Scope Window Colors opt.vlibadd.title TkGate: Add Library opt.gen.basetoolbar Core Editor Toolbars opt.gen.simtoolbar Simulation Mode Toolbars opt.gen.symedtoolbar Symbol Editor Toolbars opt.bbar.restore Restore Page Defaults opt.bbar.restoreall Restore All Defaults ############################################################################## # # Interface generator # igen.title TkGate: Module Interface Generation igen.port Port igen.type Type igen.side Side igen.size Size igen.bits Bits igen.modname Module Name: #igen.resort Re-sort igen.add Add... igen.delete Delete igen.edit Edit... igen.in in igen.out out igen.inout inout igen.left left igen.right right igen.top top igen.bottom bottom #igen.other other igen.mod Use ports used in module only. igen.int Use ports from exisiting interface only. igen.modint Use both module and interface ports. igen.portsel Port Selection igen.portpos Port Positions igen.portpos.keep Keep exiting port positions when possible. igen.portpos.renew Regenerate all port positionings. igen.caption Generate Interface igen.description -begin- Create a new interface for a module. -end- info.script.error Script Errors module.props.title TkGate: Module Properties module.props Module Properties ipanel.plist Port List ipanel.props Interface Properties #ipanel.itype.change Change Type... #ipanel.itype.edsymbol Edit Symbol... ipanel.block Standard ipanel.symbol Symbol ipanel.autogen Auto Generate... ipanel.updateall Synchronize All... ipanel.itype.select Interface Type #ipanel.block.description Standard Interface #ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label Block resize port position handling: ipanel.ppos.fix Fixed ipanel.ppos.scale Scaled #ipanel.ppos.grid Grid ipanel.warn.toblock -begin- You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes # blklst.delete.title TKGate: Module Delete blklst.copy.title TKGate: Module Copy blklst.rename.title TKGate: Module Rename blklst.claim.title TKGate: Claim Module blklst.setroot.title TKGate: Set Root Module blklst.new.title TKGate: Module New blklst.claim Claim Module blklst.to To blklst.from From blklst.name Name blklst.new.cap Create New Module blklst.del.cap Delete Module blklst.copy.cap Copy Module blklst.rename.cap Rename Module blklst.claim.cap Claim Module blklst.setroot.cap Set Root Module blklst.new.exp -fillbegin- Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- Make the specified module the top-level module. -end- find.title TkGate: Find Object find.label Find Objects find.exp -fillbegin- Look for text either in a component name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.ignorecase Ignore Case find.result.module Module find.result.type Type find.result.name Object Name # # These are special tags used by the search feature. Do not change their value. # @find.type.gate gate @find.type.net net @find.type.comment comment find.options Search Options find.results Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Contains... find.qual.begins Begins with... find.qual.ends Ends with... find.qual.matches Matches... find.dom.label Look for objects in: find.dom.gates Components find.dom.nets Nets find.dom.text Comment Text find.search Find: find.target Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in port_in1.gif @portlist.out port_out1.gif @portlist.inout port_inout1.gif @portlist.in2 port_in2.gif @portlist.out2 port_out2.gif @portlist.inout2 port_inout2.gif ############################################################################## # # Circuit Dialog box # circ.wintitle TkGate: Circuit Properties circ.label Circuit Properties circ.ident Identification circ.filev File Version circ.file File Name circ.title Circuit Title circ.encoding File Encoding circ.lang File Language circ.discchg Do not warn about discarding changes. circ.flags Options circ.defaults Component Defaults circ.extbar Use extender bars on AND, OR and XOR gates. circ.shownet Show net name on switches and dips. circ.autostart Enable auto-start of simulation. circ.iniscript Initialization Scripts #circ.noscript No script files selected. #circ.really Do you really want to remove '%s' from the list of initialization scripts. circ.reallyupdate -fillbegin- Do you really want to update the interface of all '%s' instances? -end- circ.reallyoverwrite -fillbegin- Do you really want to overwrite the existing file '%s'? -end- @circ.library.width *500 @circ.library.height *350 circ.general General circ.library Libraries circ.script Scripts circ.simulator Simulation circ.timescale Default Simulation Time Scale circ.timescale.unit Units: circ.timescale.prec Precision: circ.sim.features Features # # Strings for timing violation reporting styles. The "after" case # is broken into the string before the time period box and after the # time period box. You can use the string "-empty-" to make a string # empty if it is not needed in a particular language. # circ.sim.tv.title Timing Violation Handling circ.sim.tv.all Report all timing violations. circ.sim.tv.after.1 Report timing violations after circ.sim.tv.after.2 -empty- circ.sim.tv.never Never report timing violations. circ.exp.general -fillbegin- View and modify circuit specific properties. These properties will be stored with the circuit when you save. -end- circ.exp.library -fillbegin- Select libraries required by this circuit. Library requirements are saved with the circuit and will be automatically loaded the next time you load this circuit. -end- circ.exp.script -fillbegin- Add any simulation scripts that should be automatically read and excuted when this circuit is simulated. -end- circ.exp.simulator -fillbegin- View and modify simulation preferences for this circuit. -end- ############################################################################## # # Library Manager # libmgr.cap Library Manager libmgr.library Library libmgr.description Description libmgr.status Status libmgr.status.load Loaded libmgr.status.unload Not Loaded libmgr.status.loadp [Loaded] libmgr.status.unloadp [Not Loaded] libmgr.exp -fillbegin- Select libraries to be loaded or unloaded. -end- libmgr.load Load libmgr.unload Unload libmgr.unloadall Unload All libmgr.notedit -fillbegin- Must be in circuit edit mode to open library manager. -end- ############################################################################# # # Dynamic Verilog Module Manager # break.tab Breakpoints break.id ID break.state S break.condition Condition break.value Value ############################################################################## # Simulator # #sim.breakpt Breakpoint sim.recursive -fillbegin- Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- sim.hyperlinkstop -fillbegin- The simulator is currently running. Would you like to stop the simulation and follow the link? -end- ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.notinsim Not allowed while simulator is active. err.nomemselect Memory is not selected. err.rootinterface Can not set interface of root module. err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Components(s) are anchored and can not be moved. err.protdata Can not modify contents of protected or library module. err.badfind Can't find target '%s'. err.badopendel Can't delete open module. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.nofunc Bad or missing function name for module interface. err.wirerot Selection can not be rotated due to attaching wires. err.badinadd Can't add any more inputs to selected component. err.badoutadd Can't add any more outputs to selected component. err.badinoutadd Can't add any more inout pins to selected component. err.badpinchg Can't change pin types on selected component. err.badnetname Illegal characters in identifier deleted. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with built-in component name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Connection refused because wires are part of the same net. err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Connection refused because bit widths do not match. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Unable to exectute printer command '%s'. err.badpsopen Unable to open file '%s' for postscript output. err.badid Illegal identifier '%s'. err.noinvgate Inverters are not allowed on components of this type. err.protintf Can't modifiy protected interface on module '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Too many breakpoints. Maximum is %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.badedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Can't find net '%s'. err.sim.nogate Can't find component '%s'. err.sim.badbin Illegal charcter in binary constant '%s'. err.sim.notswitch Component '%s' is not a switch, dip or register. err.sim.badcmd Unrecognized command '%s' in simulation script. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.run Run-time error at time %s: err.sim.cmd Internal Command Error err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Unable to open input file '%s'. err.badlibopen Unable to open library file '%s'. err.nomark Please set a mark with the left mouse button before selecting a component type. err.badgate Unknown component type '%s'. err.badportadd Can't add ports to components of this type. err.modmissing HDL module text missing for module "%s". err.modtoomany Excess module definitions in module "%s". err.modmismatch Name mismatch between text definition and module name in "%s". err.manypages -fillbegin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -fillbegin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot No higher level module opened on the module stack. err.editonly Command not valid when in simulation mode. err.simonly Command valid only in simulation mode. err.deltop Can not delete top-level module '%s'. err.delprot Can not delete protected module '%s'. err.nodel No deletable selection. err.modnotdef Module '%s' is undefined. err.moddef The module '%s' already exists. err.primredef Built-in element name '%s' can not be redefined. err.primprefix Illegal module name '%s' begins with built-in prefix '%s'. err.iskeyword Verilog keyword '%s' can not be used as an identifier. err.noprop Selected component has no editable properites. err.openscript Can't open simulation script file '%s' err.oldversion Loaded file '%s' with obsolete version number %s (current version is %s). err.futureversion Loaded file '%s' saved by future TkGate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.nomodule No selected module. err.nomodop No suitable modules for operation. err.protexec Attempted execution of protected command '%s' in $tkg$exec(). err.notwritable File '%s' is not writable. err.backupfail Unable to create backup file '%s'. err.yy.badprop Ignoring unknown circuit property '%s'. err.yy.badpropval Bad value '%s' for circuit property '%s'. err.yy.baddata Bad data type supplied for circuit property '%s'. err.yy.nosym No current module symbol. err.yy.badicon Bad icon type '%s'. err.yy.toomuchdata Too much icon data. err.yy.nosyminst Missing symbol %d on instance %s of %s. err.yy.badmodprop Ignoring unknown module property '%s'. err.yy.badmoddata Bad data type supplied for module property '%s'. err.yy.badprim Unknown primitive name '%s'. err.yy.nonet Undeclared net '%s'. err.yy.bogussave Bogus save data detected. circuit may be damaged. err.yy.pinformat Illegal pin name format '%s'. err.yy.pinname Pin name '%s' not defined for component type '%s' err.yy.nonetpos No net for position %d on component %s. err.yy.baddirective Illegal or badly formed directive '%s'. err.yy.badlocale Unknown locale '%s' in save file. Using English locale. err.corruptnewsave -fillbegin- TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- File '%s' was created by TkGate %s, and may not be readable by versions earlier than current version (%s) if you save. -end- err.viewfile Can not open file '%s'. ############################################################################## # # Internal error messages (indicating a problem with tkgate) # err.internal.nomod internal error: Failed to find module '%s'. ############################################################################## # Informational messages # msg.selwire Selected %s named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.iselwire Selected port '%s' on block '%s'. msg.iselgate Selected %s named '%s' (huh? this message should be impossible). msg.iselblock Selected module interface for '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Found component named '%s'. msg.foundwire Found wire named '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Saved circuit to '%s'. msg.reallynew Circuit has been modified. Do you really want to discard your changes and create a new circuit? msg.reallyquit Circuit has been modified. Do you really want to exit? msg.notlib Module '%s' is not a library module. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################# # # Error messages generated by verga # verga.err.OK Don't worry, be happy. verga.err.INPORT Port size mismatch on input port '%s'. verga.err.OUTPORT Port size mismatch on output port '%s'. verga.err.FLOATNET Net '%s' has no drivers (floating net). verga.err.DIRECTCONN Direct connect operator '=>' unsupported. Treated as '*>'. verga.err.MEMADDR Attempt to write to memory %s with unknown address. verga.err.MEMBITS Attempt to write to memory %s with unknown bitrange. verga.err.BADARRAYUSG Array '%s' used in expression without index. verga.err.BADARRAYLHS Array '%s' used without index on left-hand-side. verga.err.BADCLOSE Attempt to close non-open descriptor in task '%s'. verga.err.BADAUTORNG Auto range [*] is only valid with 'wire' declaration. verga.err.BADGATERNG Bad component instance range expression. verga.err.BADARGVALUE Bad value for argument '%s' in task '%s'. verga.err.DIVZERO Divide by zero. verga.err.NODIV Divide/module unsupported on this machine - sizeof(short) must be 2. verga.err.BADEDGEEVENT Event on multi-bit net '%s' can not have posedge/negedge. verga.err.NEEDEDGE Must specify posedge or negedge on event for %s. verga.err.ASGNEVENT Event wait on assign is illegal. verga.err.PROTTASK Execution of protected system task '%s' blocked. verga.err.NEEDIDENT Expecting identifier for argument %s of task '%s'. verga.err.BADOP Expression operator error in '%s'. verga.err.NOREAD Failed to load source file '%s'. verga.err.MEMFILE Failed to open memory file '%s'. verga.err.WRONGMOD Found module '%s' when expecting '%s'. verga.err.NOTPARM Identifier '%s' in constant expression is not a parameter. verga.err.BADADDR Illegal address range on port '%s'. verga.err.BADADDRSPEC Illegal address range specification '%s'. verga.err.BADCHAR Illegal character (%s) '%s'. verga.err.BADEVENT Illegal event control expression. verga.err.BADCONSTOP Illegal operator in constant expression. verga.err.BADXOP Illegal operator in expression. verga.err.NETREDEF Illegal redefinition of net '%s'. verga.err.BADINOUT Inout connections must be net-to-net on port '%s'. verga.err.MODUNDEF Instance of undefined module '%s'. verga.err.BADASGNLHS Invalid left-hand-side in 'assign'. verga.err.LHSNOTREG Illegal use of '%s' in left-hand-side of assignment. verga.err.BADLHS Invalid left-hand-side in assignment. verga.err.BADOUT Invalid output assignment. verga.err.NOTREG Memories must be declared as register. verga.err.PORTMIX Mixed named and unnamed ports on interface '%s' of '%s'. verga.err.REPCASE More than one default: in case statement. verga.err.NOMEM No current memory in memory file read. verga.err.BADCMD No such command '%s'. verga.err.CMDNOTNET No such net '%s' in '%s' command. verga.err.MEMNONBLK Non-blocking assignments to memories not implemented. verga.err.NOTPPORT Parameter '%s' is not declared as a port. verga.err.REDEFP Parameter redefines identifier '%s'. verga.err.PORTNOTDEF Port '%s' on interface '%s' is not defined in module '%s'. verga.err.NOCONN Port '%s' has no connections on interface '%s' of '%s'. verga.err.MULTCONN Port '%s' has multiple connections on interface '%s' of '%s'. verga.err.PORTCOUNT Port count does not match definition on interface '%s' of '%s'. verga.err.BADPRTRANGE Range on port '%s' is not numeric. verga.err.BADARRAYRNG Range specification not allowed for memory reference of '%s'. verga.err.CMDMODREDEF Redefinition of dynamic module '%s'. verga.err.REDEF Redefinition of identifier %s. verga.err.PROTTASKSTOP Simulation stopped on attempted execution of protected system task '%s'. verga.err.NOTMEM Specified net '%s' is not a memory. verga.err.CMDNOTMEM Specified net '%s' is not a memory in '%s' command. verga.err.SYNTAX Syntax error. verga.err.TOOFEWPP Too few parameter ports on instance %s. verga.err.OPENTOOMANY Too many files open in task '%s'. verga.err.TOOMANYPP Too many parameter ports on instance %s. verga.err.NOTOP Top-module '%s' not defined. verga.err.BADOPEN Unable to open output file '%s' in task '%s'. verga.err.CMDNOMOD Undefined dynamic module '%s' in '%s' command. verga.err.BADEVENTNET Undefined net '%s' in event control expression. verga.err.NOTASK Undefined task '%s'. verga.err.NOTDEF Undefined variable '%s'. verga.err.BADRANGE Unsupported bit range [%s] on net '%s' (must be of form [n:0]). verga.err.GATEUNIMP Unimplemented primitive component type on instance '%s'. verga.err.USAGE Usage: thyme [options][files...] verga.err.CLSDWRITE Write to closed descriptor. verga.err.PRIMPTCOUNT Wrong number of ports on primitive component instance '%s'. verga.err.CMDARGS Wrong number of arguments in '%s' command. verga.err.YYERROR YYError - %s. verga.err.TASKARGS Task '%s' called with wrong number of arguments. verga.err.BADSTART Illegal start value in task '%s'. verga.err.BADSTOP Illegal stop value in $readmemb. verga.err.SPECTASKUSG Task '%s' must be used in a specify block. verga.err.BADSPECTASK Task '%s' can not be used in a specify block. verga.err.TIMING Timing violation in %s[%s] %s. verga.err.RAMDCHG Data line changed while write enabled on %s verga.err.RAMACHG Address line changed while write enabled on %s verga.err.NOIFDEF No matching `ifdef/`ifndef for %s declaration. verga.err.BADSPECLVAL Bit-ranges on path delay specifiers unsupported. verga.err.PATHDITEM Unsupported construct in module with path-delay specification. verga.err.PATHDINOUT Use of 'inout' in module with path-delay specification is unsupported. verga.err.PATHDLOOP Loops in modules with path-delay specification are unsupported. verga.err.PATHDCOND DelaMust set through both # expression and specify block. verga.err.TASKREDEF Redefinition of task or function '%s' in module '%s'. verga.err.TASKASFUNC Task '%s' used as function. verga.err.FUNCASTASK Function '%s' used as task. verga.err.TASKBADTYPE Non-register type used in task or function. verga.err.TASKBADPORT Only input ports are allowed on functions. verga.err.TIMESCALEU Invalid units '%s' in `timescale declaration. verga.err.TIMESCALEN Invalid scale '%s' in `timescale declaration (must be 1, 10 or 100). verga.err.TIMESCALES Invalid syntax in `timescale declaration. verga.err.TIMESCALEX Units must be larger than precision in `timescale declaration. verga.err.TIMESCALEAN Design contains some modules with `timescale and some without. verga.err.BADPORTTYPE Invalid type declaration used on port '%s' verga.err.BADVALUE Bad numeric value '%s'. verga.err.NONEXPCTL Event control @(*) applied to non-expression. verga.err.NONSTATCTL Event control @(*) applied to non-statment. verga.err.MODREDEF Redefinition of module '%s'. verga.err.IE_TASK Task definition '%s' found outside module - internal error. verga.err.IE_NONET Failed to find net '%s' - internal error. verga.err.IE_NOOP Can not find operator description -- internal error. verga.err.IE_BADEXP Unexpected expression type %s - internal error. verga.err.IE_BADVAR Undefined variable or unknown net - internal error. verga.err.IE_BADSTATE Unexpected internal state at %s - internal error. verga.err.IE_RETURN Executed BCReturn bytecode with empty return stack - internal error. ############################################################################## # # Errors for primitive handling. These are internal errors and probably do # not need to be translated. # primitive.err.missing Internal Error: primitive definition for '%s' is missing. primitive.err.nomodule Internal Error: primitive definition for '%s' is missing 'module'. primitive.err.nomodname Internal Error: missing module name in definition of '%s' module. primitive.err.wrongname Internal Error: module name mismatch in definition of '%s' module. ############################################################################## ############################################################################## ############################################################################## # Balloon Help ############################################################################## ############################################################################## ############################################################################## ho.setsel.allr Move all items to selected list. ho.setsel.alll Move all items to unselected list. ho.setsel.ltor Move highlighted items to selected list. ho.setsel.rtol Move highlighted items to unselected list. ho.net.in Single-Bit Input ho.net.out Single-Bit Output ho.net.inout Single-Bit Inout ho.net.in2 Multi-Bit Input ho.net.out2 Multi-Bit Output ho.net.inout2 Multi-Bit Inout ho.net.wire Single-Bit Wire (Name Visible) ho.net.wire2 Multi-Bit Wire (Name Visible) ho.net.hwire Single-Bit Wire (Name Hidden) ho.net.hwire2 Multi-Bit Wire (Name Hidden) ho.net.reg Single-Bit Register ho.net.reg2 Multi-Bit Register ho.opt.tool.file Save, load of circuit files ho.opt.tool.edit Cut, Paste and Find operations ho.opt.tool.gateopt Component rotation and alignment operations ho.opt.tool.gateprop Basic editing of components ho.opt.tool.undo Undo and redo operations ho.opt.tool.zoom Zoom in and zoom out ho.opt.tool.mode Select the editing tool ho.opt.tool.module Create, delete, rename,etc. of module definitions ho.opt.tool.tech Select default technology for components ho.opt.tool.simctl Start, stop and pause of simulator ho.opt.tool.simaux Auxliary simulator commands (read/write memory files, etc.) ho.opt.tool.simmode Choose between the select and scroll tool in simulator. ho.opt.tool.symmode Selecting editing tool in symbol editor ho.opt.tool.symedit Cut and paste operations for symbol editor ho.opt.tool.symport Port rotation operations for symbol editor ho.opt.tool.symshift Shift the bit map or portion of bitmap ho.opt.tool.symopr Miscellaneous symbol editor operations ho.opt.editor.movesel -begin- If this option is enabled, a selected block of text can be grabbed with the mouse pointer and moved to a new location. -end- ho.opt.editor.format -begin- If enabled, verilog source code will be automatically indented when pressing the tab key. -end- ho.opt.editor.indent -begin- Number of spaces to indent per level. -end- ho.opt.editor.rtab -begin- Automatically indent the current line and tab to the appropriate level when pressing the return key. -end- ho.opt.editor.beginindent -begin- Causes a begin..end block to be indented to the same level as its parent block. -end- ho.opt.editor.colorize -begin- Enable context-dependent colorization of code according to the options listed below. -end- ho.hdl.splitexp -begin- Multiple modules in the HDL text will be split into different modules defining new modules as necessary. Any name conflicts will be resolved by slightly modifying module names as necessary. -end- ho.hdl.commentexp -begin- Modules other than the first module or module matching the expected name will be converted to HDL comments. -end- ho.hdl.autoeditexp -begin- Automatically edit the HDL description to fix the module name. -end- ho.hdl.cancelexp -begin- Take no action and continue editing the current module. -end- ho.hdl.ignoreexp -begin- Ignore the inconsistency and continue with the selected action. -end- ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.saveas Save circuit to specified file. ho.print Print current circuit. ho.library Open the library manager. ho.symed.tab.normal -begin- Edit the unselected symbol bitmap. -end- ho.symed.tab.select -begin- Edit the selected symbol bitmap. -end- ho.simmove -begin- Select wires and modules, flip switches and enter dip values. Clicking and holding on a wire will show its current value. -end- ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new component Move components and wires Connect wires By double-clicking you can: Edit component, wire and port properties Edit comment text -end- ho.delgat -begin- Delete Component - Use this tool to delete components. -end- ho.cutw -begin- Cut Wire - Use this tool to cut wires. -end- ho.scroll -begin- Scroll - Grab and drag the editing canvas. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from component ports. -end- ho.bitw -begin- Net Attributes - Use this tool to change the attributes of a net. The bit size and wire type of nets selected with this tool will be changed to the those shown in the drop-down boxes to the right. -end- ho.ipanel.select -begin- Use "standard" modules for regular rectangular interfaces. Use "symbol" modules for custom bitmaped symbols. -end- ho.ipanel.addport -begin- Add a port to the module. You can also double-click after the last item to add port. -end- ho.ipanel.deleteport -begin- Delete the selected port. -end- ho.ipanel.editport -begin- Edit the selected port. You can also double-click to edit a field in a port. -end- ho.ipanel.generate -begin- Generate a new interface for a module based on ports in the port list and port elements used in the module definition. -end- ho.ipanel.updateall -begin- Replace the interface on all instances of this module with the canonical interface shown here. -end- ho.ipanel.prot -begin- Do not allow the definition of a module to be modified. -end- ho.ipanel.protint -begin- Do not allow the interface of a module to be modified. -end- ho.ipanel.proted -begin- Do not allow the interface of a module to be modified except through the interface editor. Use this to prevent accidental modification of the interface in the main edit window. -end- ho.ipanel.scale -begin- Scale the distance between ports as a module is resized. -end- ho.ipanel.fix -begin- Keep the distance between ports fixed even if the module is resized. -end- ho.mod.open Open the selected module. ho.mod.close Close the current module. ho.mod.new Create a new module type. ho.mod.del Delete a module. ho.mod.copy Copy a module. ho.mod.rename Rename a module. ho.mod.claim -begin- Convert a library module to a regular module. -end- ho.mod.setroot -begin- Designate a module to be the root module. -end- ho.mod.type.allparts Set of Libraries ho.mod.type.partlib Library ho.mod.type.part Library module ho.mod.type.unknown Unknown module type ho.mod.type.unused Set of unused modules ho.mod.type.conflict Module recursion ho.mod.type.root Top-level module ho.mod.type.netlist Netlist module ho.mod.type.Lnetlist Netlist module (locked) ho.mod.type.hdl HDL module ho.mod.type.Lhdl HDL module (locked) ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.tab.edit -begin- Primary editing mode. -end- ho.tab.interface -begin- Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Find critical paths in a circuit. -end- ho.log -begin- Log of TkGate messages including error messages, information messages and simulator console output. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. Breakpoints can be edited in both simulation mode and edit mode. -end- ho.simexec -begin- Manage the set of active scripts. -end- ho.simoptions -begin- Set various options that control the simulation. -end- ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.simview -begin- View/modify the contents of a memory (RAM or ROM). -end- ho.modlist -begin- List of all modules currently loaded in alphabetical order. Drag modules to the edit window to create new instances. -end- ho.modtree -begin- List of all modules currently in a hierarchical list. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- List of nets in the current module. The symbol to the left of the name indicates whether the net is single bit (green) or multi-bit (red). An "A" shown in the symbol indicates that the net name is marked as visible. -end- ho.ports -begin- List of ports on the interface of the module displayed in the edit window. The symbol before the port indicates the direction of the port. -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, TkGate is in edit mode. If the quadrapedal AND gate is shown, TkGate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from TkGate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TkGate. ho.print.selcur Print only the current module in the TkGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.print.timegraph -begin- The display of the region selected to be printed is shown here. The green area is the entire range of trace data available, and the grey area shows the area to be printed. Use the selectors to the left to select a region, or select the region in the scope window before bringing up this diaglog box. -end- ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Newly created basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.circuit.shownet -begin- Newly created switches and dips will initially show the net name next to them. -end- ho.circuit.autostart -begin- If enabled, simulation will begin as soon as the simulation pane is selected. -end- ho.circuit.file -begin- This is the file name from which the current circuit was loaded. -end- ho.circuit.ver -begin- This is the version of TkGate that created the file that is currently loaded. -end- ho.circuit.encoding -begin- Use this encoding for save files. -end- ho.circuit.language -begin- Use fonts for this encoding to display circuit data. -end- ho.circuit.title -begin- Description of your circuit. This title is used on printed output. -end- ho.cmd.bitw -begin- Wires selected with the ribbon cable tool will be set to this bit width. -end- ho.edgat.signam -begin- The name of the selected signal on the selected component. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the component. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected component. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected component. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.hide -begin- Set this flag to disable display of component names. -end- ho.edgat.gtype Type of the component. ho.edgat.gname Name of this component instance. ho.edgat.ganchor Set this flag to anchor the position of a component. ho.edgat.gx X coordinate of component. ho.edgat.gy Y coordinate of component. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint -begin- Print the logic trace range selected using the right mouse button. Shift-right click can be used to expand the selected region. The range visible in the scope view is used when there is no selection. -end- ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.general.fontset -begin- Specifies the basic font size to use in the TkGate interface. This option will not take effect until restarting TkGate. -end- ho.opt.sec.send -begin- Enabling the $tkg$command() system task will allow user circuits to send arbitrary simulator control commands to the TkGate GUI. This includes the ability to execute arbitrary shell commands. If the simulator will be used to execute untrusted circuits, it is recommended that this task be disabled. Enabling this option has a very high security risk. -end- ho.opt.sec.open -begin- Enabling the $fopen() system task will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.writemem -begin- Enabling the $writememb() and $writememh() system tasks will allow user circuits to write to any file that the user invoking TkGate has access to. Enabling this option has a high security risk. -end- ho.opt.sec.enqueue -begin- Enabling the $tkg$recv() and $tkg$send() system tasks will enable virtual peripheral devices to send messages to TkGate circuits. Enabling this option has a low security risk. -end- ho.opt.ssave -begin- Perform consistency checks on circuit files before overwriting existing save file to verify that there are no problems with the save file. -end- ho.opt.sec.exec -begin- Fully enabling the $tkg$exec() system task allows user circuit to execute arbitrary tcl/tk commands including the ability to execute arbitrary shell commands. Enabling this option has a very high security risk. -end- ho.opt.sec.regexec -begin- Enabling the $tkg$exec() system task for registered functions allows user circuits to execute only tcl/tk commands that have been registered as safe. As long has all Virtual Peripheral Device files are trusted, enabling $tkg$exec() at this level should prevent dangerous commands from being executed. Enabling this option has a medium security risk. -end- ho.opt.sec.noexec -begin- Fully disabling the $tkg$exec() command will prevent user circuits from executing tcl/tk commands. This will make it impossible to use Virtual Peripheral Devices. Selecting this option has a minimal security risk. -end- ho.opt.sec.stop -begin- If this setting is enabled, the simulation will be terminated as soon as any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.warn -begin- If this setting is enabled, the simulation will continue, but an error message will be displayed when any attempt is made by the user circuit to execute a disabled feature. -end- ho.opt.sec.ignore -begin- If this setting is enabled, use of any disabled features will be ignored and no error messages will be displayed. -end- ho.opt.html.browser -begin- Command to be execute when the user clicks on a link to an html file. A "%s" in the command will be replaced with the link URL. -end- ho.opt.html.email -begin- Command to be execute when the user clicks on a link to send an e-mail message. A "%s" in the command will be replaced with the link URL. -end- ho.opt.fsave -begin- Save TkGate internal cells with circuit data. This will increase save file size by about 20% for a typical circuit, but will result in save files that can be exported to third party tools. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.sim.noglitch -begin- If this option is enabled, rapidly changing inputs to a component will cause the component to output unknown rather simply the time shifted input signal. This can eliminate spurious events and prevent oscilations in gate-level sequential circuits. -end- ho.opt.sim.savetraces -begin- Probes placed during a simulation run will be remembered and replaced when restarting the simulation of the same circuit. -end- ho.opt.sim.tech -begin- List of files to load as potential "technology" files. Technology files specify delay and area estimates for built-in components. -end- ho.opt.sim.err -begin- Select how warnings from the simulator should be handled. -end- ho.opt.sim.err.stopany -begin- Do not simulate the circuit if there are any warnings in the circuit, even if there are no actual erros. -end- ho.opt.sim.err.showall -begin- Always show warnings in the circuit, even if there are no errors. If there are only warnings, the simualtor will be started and the list of warnings will be displayed in a separate window. -end- ho.opt.sim.err.showiferr -begin- Show warnings only if there are also errors in the circuit. If a circuit contains only warnings, they will be ignored and the simulator will be started. -end- ho.opt.sim.err.ignore -begin- Never display warning messages, even if there are errors in the circuit. -end- ho.opt.lib.vpath -begin- List of directories to search for TkGate library files. Library files should have a .v extention and contain modules useful for use in user circuits. -end- ho.opt.lib.vlib -begin- List of libaries that should automatically be loaded when TkGate starts. -end- ho.opt.lib.vpd -begin- List of directories to search for virtual peripheral devices. Virtual peripheral devices have a .tcl extension and typically implement a GUI representing a peripheral device that can be controlled by a user circuit. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.name -begin- User name to be used on TkGate generated reports such as circuit printouts. -end- ho.opt.site -begin- The name of the site where TkGate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. Unset only if you are having problems on your display. -end- ho.opt.showimage -begin- Unset this option to suppress display of the image and explanitory text at the edge of dialog boxes. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.tearawaymenus -begin- If enabled, the main menues will be detachable from the interface. This option will take effect next time you restart TkGate. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.blockDropConnect -begin- Allow ports on module interfaces to be created by dropping free wires near an edge. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this option, the useless features checkbox will no longer appear in this dialog box. The only way to see the useless features again will be to edit your .tkgate2-properties file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when simulation of any circuit is initiated. Do not use this for circuit specific scripts, use the circuit properties instead. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. Use the name of the net to which the clock is attached. -end- ho.opt.keybind -begin- Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart TkGate to see any user defined keybindings. -end- ho.deftech -begin- Default technology for new components. Affects delay of components. To change the technology of a specific component, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this component. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.symed.point -begin- Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.line -begin- Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.rect -begin- Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.fillrect -begin- Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.symed.select -begin- Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.symed.port -begin- Port select mode. Select ports and move them or rotate them. -end- ho.symed.rshift Shift selected pixels right. ho.symed.lshift Shift selected pixels left. ho.symed.ushift Shift selected pixels up. ho.symed.dshift Shift selected pixels down. ho.symed.cwrotate Rotate selected pixels clockwise. ho.symed.ccwrotate Rotate selected pixels counter-clockwise. ho.symed.autobold Make selected image bold. ho.symed.resize Resize the image editor. ho.symed.import Import image from file. ho.symed.export Export image to file. ho.tool.currot -begin- Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.zoomin Zoom in ho.tool.zoomout Zoom out ho.tool.rotate Rotate selected component(s) counter-clockwise. ho.tool.brotate Rotate selected component(s) clockwise. ho.tool.valgn Align selected component(s) vertically. ho.tool.halgn Align selected component(s) horizontally. ho.tool.cut Cut selection. ho.tool.copy Copy selection. ho.tool.paste Paste from cut buffer. ho.tool.find Find component, wire or text. ho.tool.addport Add a port to the selected component. ho.tool.anchor Anchor the selected component(s). ho.tool.unanchor Unanchor the selected component(s). ho.tool.replicate Replicate a component. ho.tool.delete Delete the selection. #ho.opt.circuit.extbar TODO #ho.opt.circuit.shownet TODO #ho.circuit.shownet TODO tkgate-2.0-b10/locale/en/orig-messages000644 001751 001751 00000134615 10202166146 020347 0ustar00hansenhansen000000 000000 # # Copyright (C) 1987-2000 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Nov 29 00:45:14 2004 ############################################################################## # # Explaination of file format. # # Messages files are used to "localize" tkgate so that it can run under # different languages. Lines beginning with a '#' character are comments. # Most entries in the file are of the form: # # tag value # # A tag is any abitrary string of non-whitespace characters. By convention # a dot notation is used to suggest groups of related tags. The value of the # tag begins at the first non-whitespace character after the tag and can include # white space. Normally the value is the localized text message. By convension, # tags beginning with a '@' character are used to control interface layout # as opposed to being actual text. Explainations for this tags will be given # in preceeding comments. # # Multi-line comments have the form: # # tag -begin- # line1 # line2 # -end- # # or # # tag -fillbegin- # line1 # line2 # -end- # # When -begin- is used, the newlines in the text are preserved as is. When # -fillbegin- is used the newlines are replaced with spaces and it is assumed # that the text will be automatically justified. # # If the first character of a value is a back-quote, then it is interpreted # as a reference to another tag. For example: # # foo This is tag foo. # bar `foo # # In this instance both 'foo' and 'bar' will translate to 'This is tag foo'. # # The last type of entry that can occur in the file, normally at the type is # a declaration. Currently, the only allowed declaration is: # # \font-encoding code # # where "code" is a font encoding such as "iso8859-21". This can be used to # select a font encoding specific to a locale. The default encoding # is "iso8859-1". # ############################################################################## ############################################################################## # # basic strings # b.dismiss Dismiss b.close Close b.ok OK b.clear Clear b.cancel Cancel b.open Open... b.bitw Bit Width b.in in b.out out b.inout inout b.browse Browse... b.label Label b.find Find b.edit Edit... b.add Add... b.delete Delete b.deleteb Delete... b.remove Remove b.apply Apply b.anchor Anchor b.tech Technology ############################################################################## # # Main tab strings # tab.edit Edit tab.editintr Interface tab.simulate Simulate tab.cpath Critical Path ############################################################################## # Menu strings # file File edit Edit tool Tool simulate Simulate module Module gate Gate make Make circ Circuit new New open Open... openlib Open Library... save Save saveas Save As... print Print... options Options... quit Quit undo Undo redo Redo cut Cut copy Copy paste Paste selall Select All find Find... algnv Align Ver. algnh Align Horz. rotate Rotate zoomin Zoom In zoomout Zoom Out move Move/Connect delg Delete Gate cutw Cut Wire inv Invert bitw Bit Width debug Debug rot0 Rot 0 rot90 Rot 90 rot180 Rot 180 rot270 Rot 270 simbegin Begin Simulation simend End Simulation simadprobe Add/Delete Probe simrun Run simpause Pause simstep Step Epoch(s) simcycle Step Cycle simbreak Breakpoint... simscript Exec. Script... simload Load Memory... simdump Dump Memory... sim.recursive -fillbegin- Recursive module definition found at '%s'. Can not start simulator or perform critical path analysis. -end- modopen Open modclose Close modsymed Symbol Editor... modseti Set Interface modediti Edit Interfaces... modnew New... moddel Delete... modcopy Copy... modrename Rename... modclaim Claim... modsetroot Set As Root... modprop Properties... mod.int Edit Interface... circprop Circuit Properties... cpath Critical Path... mod.intf Interface gataddin Add Input gataddout Add Output gataddinout Add BiDir gatiochg Change Type gatioset Set Type gatanchor Anchor Selected gatunanchor Unanchor Selected gatprop Properties... gatrep Replicate gatdel Delete gatsettech Set Technology port.parms Port Parameters port.in In port.out Out port.inout InOut ############################################################################## # # Tags for built-in gate types # gm.io I/O gmgate Gate gmredgate Reduction gmmsi MSI gmalu ALU gmmem Memory gmmod Module gmcomment Comment gmframe Frame gm.io.switch Switch gm.io.dip DIP Switch gm.io.ground Ground gm.io.vdd Vdd gm.io.merge Concat gm.io.clock Clock gm.io.led LED gm.io.ledbar LED Bar gm.io.ledhex 7-Seg. LED (HEX) gm.io.leddec 7-Seg. LED (DEC) gm.io.ledseg 7-Seg. LED (Direct) gm.io.tty TTY gmand AND gmnand NAND gmor OR gmnor NOR gmxor XOR gmxnor XNOR gmbuf Buffer gminv Inverter gmtribuf Tri-Buffer gmnmos NMOS gmpmos PMOS gmrand AND gmrnand NAND gmror OR gmrnor NOR gmrxor XOR gmrxnor XNOR gmadd Adder gmmult Multiplier gmdiv Divider gmlshift Left Shift gmrshift Right Shift gmarshift Arith. Right Shift gmroll Roll gmreg Register gmff Flip-Flop gmram RAM gmrom ROM gm21mux 2-1 Multiplexor gm41mux 4-1 Multiplexor gm81mux 8-1 Multiplexor gm12dec 1-2 Decoder gm14dec 1-4 Decoder gm18dec 1-8 Decoder gmmodinst Module Instance gmmodin Module Input gmmodout Module Output gmmodinout Module InOut ############################################################################## addwireseg Add Wire Segment help Help hlpabout About... hlplicense License... hlpdoc Documentation... hlptut Tutorials hlpexample Examples exampcomb Combinational Logic examp3bit 3-Bit Counter examp8bit 8-Bit Counter examptrff Transistor-Level FF exampcpu Menagerie CPU tutwelcome TkGate Intro tutcreate Creating a Circuit tutedit1 Editing a Circuit (1) tutedit2 Editing a Circuit (2) tutmods Using Modules tutsim Simulating a Circuit ############################################################################## # # Symbol editor strings # symed.bsave Store symed.file File symed.file.load Load Bitmap... symed.file.save Save Bitmap... symed.file.updateclose Close and Update symed.file.discardclose Close and Discard symed.help Help symed.help.about About... symed.edit Edit symed.edit.cut Cut symed.edit.copy Copy symed.edit.paste Paste symed.edit.overlay Overlay Paste symed.edit.rclock Rotate Clockwise symed.edit.rcclock Rotate Counter-Clockwise symed.module Module symed.modes Modes symed.cutpaste Cut/Paste symed.rotate Port Rotation symed.zoom Zoom symed.update Update symed.cancel Cancel # Scope Menu menu.sc.prtrace Print Trace... menu.sc.close Close menu.sc.trace Trace menu.sc.zoomin Zoom In menu.sc.zoomout Zoom Out scope.emptymsg Double-click on a wire to add or delete a trace. comment.empty [Double click to add text.] ############################################################################## # Interface strings # ifile File imodule Module iblmodule Modules iports Ports ibits Bits: ############################################################################# # Module Dialog Box # db.mod.name Name db.mod.file File Name db.mod.type Type db.mod.flags Flags db.mod.dataprot Disallow editing of module definition. db.mod.intfprot Disallow all interface changes. db.mod.edprot Disallow edit mode interface changes. db.mod.props Properties db.mod.inuse.0 Module is not in use. db.mod.inuse.1 Module is in use. db.mod.lmod.0 Module has not been modified since loading. db.mod.lmod.1 Module has been modified since loading. db.mod.smod.0 Module has not been modified since saving. db.mod.smod.1 Module has been modified since saving. db.mod.islib.1 Module is part of [%s] library. db.mod.islib.0 Module is not a library module. db.mod.netlist Netlist db.mod.hdl HDL db.mod.netexpl -begin- Modules of this type are described as a network of connected components. A graphical editor is used to edit the definition. -end- db.mod.hdlexpl -begin- Modules of this type are described in text format. A text editor is used to create the module definition. -end- ############################################################################# # Error List Dialog box # db.err.caption Error List db.err.explain -begin- I am unable to enter simulation mode due to errors in your circuit. Double-click on an error message to see the error location. -end- ############################################################################# # Net Dialog Box # db.net.name Net Name db.net.hide Hide Name db.net.bits Bit Width db.net.port Port Type db.net.in in db.net.out out db.net.inout inout db.net.inets Nets ############################################################################## # # New circuit dialog box # db.newcirc.cap New Circuit db.newcirc.exp -fillbegin- Discard the current circuit and start editing a new circuit. -end- db.newcirc.file File Name db.newcirc.topname Top Module Name ############################################################################## # Gate dialog box # db.gate.signam Signal Name db.gate.portnam Port Name db.gate.iotype Type db.gate.bitw Bit Width db.gate.cyclew Cycle Width db.gate.phase Phase db.gate.duty Duty db.gate.port Port db.gate.bitws Bits db.gate.side Side db.gate.gtype Gate Type db.gate.gname Gate Name db.gate.hidenam Hide Name db.gate.anchor Anchor db.gate.cpbreak Critical Path Partition db.gate.butstate Button State db.gate.dipval Switch Value db.gate.range Bit Range db.gate.memfilenam Memory File db.gate.modname Function db.gate.islink Text is Hyperlink db.gate.link Link to File db.gate.findw Search for wires only db.gate.findg Search for gates only db.gate.findwg Search for wires and gates db.gate.general General db.gate.details Details db.gate.text Text db.gate.ports Port db.gate.delay Delay db.gate.stddelay Standard Delay db.gate.custdelay Custom Delay db.gate.catdiruse Port Placement db.gate.edit Edit db.gate.delete Delete db.gate.add Add db.gate.cat.asc.hdr Ascending db.gate.cat.dec.hdr Decending db.gate.cat.asc.exp -fillbegin- Bits are concatenated in ascending order from top to bottom. -end- db.gate.cat.dec.exp -fillbegin- Bits are concatenated in descending order from top to bottom. -end- db.gate.cat.sigdir Signal Direction db.gate.cat.auto.hdr Auto db.gate.cat.multin.hdr Multi-Input db.gate.cat.singin.hdr Single-Input db.gate.cat.tran.hdr Bidirectional db.gate.cat.auto.exp -fillbegin- Determine signal direction automatically from connected nets. -end- db.gate.cat.multin.exp -fillbegin- Always assume multi-port side is the input. -end- db.gate.cat.singin.exp -fillbegin- Always assume single-port side is the input. -end- db.gate.cat.tran.exp -fillbegin- Allow bidirectional (tran) signal flow. Can not be connected to switches or registers. -end- db.gate.tab.General.cap General Properties db.gate.tab.Ports.cap Port Properties db.gate.tab.Delay.cap Delay Properties db.gate.tab.CLOCK.cap Clock Properties db.gate.tab.SWITCH.cap Switch Properties db.gate.tab.DIP.cap DIP Properties db.gate.tab.TAP.cap Tran Properties db.gate.tab.RAM.cap RAM Properties db.gate.tab.ROM.cap ROM Properties db.gate.tab.BLOCK.cap Module Properties db.gate.tab.FRAME.cap Frame Properties db.gate.tab.LED.cap LED Properties db.gate.tab.AND.cap AND Properties db.gate.tab.OR.cap OR Properties db.gate.tab.XOR.cap XOR Properties db.gate.tab.MUX.cap Mux Properties db.gate.tab.DEMUX.cap Demux Properties db.gate.tab.CONCAT.cap Concat Properties db.gate.tab.COMMENT.cap Text Properties db.gate.tab.General.exp -fillbegin- View and modify basic properties of an instance. -end- db.gate.tab.Ports.exp -fillbegin- Add, edit or delete ports on an instance. -end- db.gate.tab.Delay.exp -fillbegin- Delay can be specified either as a technology or as specific values for this instance. -end- db.gate.tab.details.exp -fillbegin- Set detailed type specific properties of a gate here. -end- db.gate.tab.CLOCK.exp `db.gate.tab.details.exp db.gate.tab.SWITCH.exp `db.gate.tab.details.exp db.gate.tab.DIP.exp `db.gate.tab.details.exp db.gate.tab.TAP.exp `db.gate.tab.details.exp db.gate.tab.RAM.exp `db.gate.tab.details.exp db.gate.tab.ROM.exp `db.gate.tab.details.exp db.gate.tab.BLOCK.exp `db.gate.tab.details.exp db.gate.tab.FRAME.exp `db.gate.tab.details.exp db.gate.tab.LED.exp `db.gate.tab.details.exp db.gate.tab.AND.exp `db.gate.tab.details.exp db.gate.tab.OR.exp `db.gate.tab.details.exp db.gate.tab.XOR.exp `db.gate.tab.details.exp db.gate.tab.MUX.exp `db.gate.tab.details.exp db.gate.tab.DEMUX.exp `db.gate.tab.details.exp db.gate.tab.CONCAT.exp `db.gate.tab.details.exp db.gate.tab.COMMENT.exp -fillbegin- Set the text to be displayed in a comment. Limited html commands including links can be used here. -end- db.gate.mux.dataorder Input Ordering db.gate.mux.ord1.hdr Left-to-Right db.gate.mux.ord2.hdr Right-to-Left db.gate.mux.ord1.exp -fillbegin- Order MUX inputs from left to right. -end- db.gate.mux.ord2.exp -fillbegin- Order MUX inputs from right to left. -end- db.gate.demux.dataorder Output Ordering db.gate.demux.ord1.hdr Left-to-Right db.gate.demux.ord2.hdr Right-to-Left db.gate.demux.ord1.exp -fillbegin- Order DEMUX outputs from left to right. -end- db.gate.demux.ord2.exp -fillbegin- Order DEMUX outputs from right to left. -end- db.gate.mux.select Selector Style db.gate.mux.sel1.hdr Selector on Left db.gate.mux.sel2.hdr Selector on Right db.gate.mux.sel1.exp -fillbegin- Place the data selector on the left side of the gate. -end- db.gate.mux.sel2.exp -fillbegin- Place the data selector on the right side of the gate. -end- db.gate.demux.select `db.gate.mux.select db.gate.demux.sel1.hdr `db.gate.mux.sel1.hdr db.gate.demux.sel2.hdr `db.gate.mux.sel2.hdr db.gate.demux.sel1.exp `db.gate.mux.sel1.exp db.gate.demux.sel2.exp `db.gate.mux.sel2.exp db.gate.aox.extbaruse Extender Bar Use db.gate.aox.use.hdr Extender Bars db.gate.aox.nouse.hdr No Extender Bars db.gate.aox.use.exp -fillbegin- Basic gates (AND, OR, etc.) will use extender bars as inputs are added. -end- db.gate.aox.nouse.exp -fillbegin- Basic gates (AND, OR, etc.) will not use extender bars as inputs are added. -end- db.gate.led.type LED Type db.gate.led.bit.hdr Bit db.gate.led.bar.hdr Bar Graph db.gate.led.hex.hdr 7-Segment (HEX) db.gate.led.dec.hdr 7-Segment (DEC) db.gate.led.seg.hdr 7-Segment (Direct) db.gate.led.bit.exp -fillbegin- Single-lamp led display for 1-bit signals. -end- db.gate.led.bar.exp -fillbegin- LED bar graph with one bar per bit. -end- db.gate.led.hex.exp -fillbegin- Display signal in hexidecimal. -end- db.gate.led.dec.exp -fillbegin- Display signal in decimal. -end- db.gate.led.seg.exp -fillbegin- Signal bits directly control led segments. -end- db.seq.back cpath.cloops -fillbegin- Combinational loops were detected in your circuit. In order to do delay analysis on this circuit, you must either break the loop, or mark some of the gates in the loop as a "Critical Path Partition" point. Nets at which a loop was detected are listed below. -end- ############################################################################## # Print dialog box # print.outto Output to print.printer Printer print.file File print.prcmd Print Command print.prname Printer print.filename File Name print.epssave Save as Encapsulated Postscript. print.doctit Document Title #print.prmod Print Modules print.epcm Epochs/cm print.estpg Estimated pages print.all All print.cur Current print.use Used print.sel Selected print.inclib Include library modules. print.papsz Paper Size print.orient Orientation print.portrait Portrait print.landscape Landscape print.2side Print Double-Sided print.opts Options print.scale Scale large modules to fit page. print.partition Partition large modules into multiple pages. print.incidx Include index. print.incgraph Include hierarchy graph. print.4up Print small modules four per page. print.range Range Selection print.scaleselect Scale Selection print.fulltr Full Trace print.parttr Partial Trace print.start Start print.end End print.outsel Output Selection print.filesel File Selection print.printersel Printer Setup print.pageset Page Setup print.modulesel Module Selection ############################################################################## # # TkGate 2.0 print dialog strings # print.ok Print print.printtrace.cap Print Trace print.printcirc.cap Print Schematic print.printcirc.out.exp -fillbegin- Choose whether to send your schematic to the printer or to a PostScript file. -end- print.printcirc.page.exp -fillbegin- Choose page and printer options here. -end- print.printcirc.mod.exp -fillbegin- Choose which modules are to be printed and set options controlling the presentation. -end- print.printtrace.trace.exp -fillbegin- Choose the time range over which to produce output. Also set the scale to compute the estimated page count. -end- print.tab.output Output print.tab.page Page print.tab.content Content ipop.editintf Edit... ipop.setintf Set as Default ipop.replintf Replace with Default ############################################################################## # # Options dialog # opt.identity Identity opt.site Site Name opt.username User Name opt.inst Instances opt.mods Modules opt.modports Module Ports opt.frames Frames opt.comment Comments opt.hlink Hyperlinks opt.wire Single-Bit Wires opt.bus Multi-Bit Wires opt.tools Gate Tools opt.cpath Critical Path opt.grid Scope Grid opt.logic1 Logic One opt.logic0 Logic Zero opt.float Float opt.unknown Unknown/Conflict opt.offled Off LED opt.onled On LED opt.zled Floating LED opt.restdef Restore Defaults opt.regudate Region Update opt.smoothscroll Smooth Scrolling opt.outmove Outline Move modules opt.balloon Enable Help Balloons opt.safeSave Do safe file saving opt.saveCells Include cells in save files opt.debug Enable Debugging opt.showimage Show side-bar images in dialog boxes opt.novice Novice Mode opt.ckpoint Do Checkpointing opt.freq Interval opt.beak Enable Special Modes opt.mode Mode opt.normal Normal opt.bat Bat opt.trek Star Trek opt.miles Miles opt.contver Automatic Integrity Checking opt.showsimcmd Display Simulator Stream opt.logfile Simulator Log File opt.estepsz Epoch Step Size opt.cstepsz Clock Cycle Step Size opt.overstep Clock Overstep opt.sorttraces Sort traces alphabetically on scope opt.vpopupdelay Pop-Up Delay opt.initscript Initialization script opt.posedge Clock step stops on all clock posedges opt.setclock Clock step stops on clock opt.delayfilepath Delay Files opt.general General opt.interface Interface opt.display Display opt.print Print opt.simulate Simulate opt.analysis Analysis opt.color Color opt.undolen Max Undo opt.keybind Key Binding Style opt.useless Useless Features opt.features Basic Features opt.simbase Basic Simulator Options opt.simclock Clock Options opt.cpopts Critical Path Options opt.maxpath Maximum Number of Paths: opt.cpflash Display with Flashing Path opt.vercheck -begin- Periodically check for new versions of tkgate over the Internet. Do not enable unless you have continuous access to the Internet. -end- opt.general.cap General Options opt.interface.cap Interface Options opt.print.cap Print Options opt.analysis.cap -begin- Critical Path Options -end- opt.simulator.cap Simulator Options opt.color.cap Color Options opt.debug.cap Debug Options opt.color.editwin Edit Window Colors opt.color.scopewin Scope Window Colors opt.general.exp -fillbegin- Set personal identification and basic TkGate options on this page. The personal identification will be used on printed output. -end- opt.interface.exp -fillbegin- Set options controlling the look and feel of the interface. -end- opt.print.exp -fillbegin- Set default printer options on this page. -end- opt.analysis.exp -fillbegin- These options control the critical path analysis function. -end- opt.simulator.exp -fillbegin- These options control the functioning of the simulator. -end- opt.color.exp -fillbegin- Use these options to set the color scheme to use in TkGate. -end- opt.debug.exp -fillbegin- Debugging options can be set here. -end- opt.gen.toolbar Toolbar Options ############################################################################## # # Interface generator # igen.type Type igen.side Side igen.size Size igen.refetch Re-fetch igen.resort Re-sort igen.add Add igen.delete Delete igen.edit Edit igen.auto Auto igen.in in igen.out out igen.inout inout igen.left left igen.right right igen.top top igen.bottom bottom igen.other other igen.mod Use ports used in module only. igen.int Use ports from exisiting interface only. igen.modint Use both module and interface ports. igen.portsel Port Selection igen.portpos Port Positions igen.portpos.keep Keep exiting port positions when possible. igen.portpos.renew Regenerate all port positionings. igen.caption Generate Interface igen.description -begin- Create a new interface for a module. -end- igen.typesel.label -begin- Interface Generator: %s Interface Type -end- igen.typesel.exp -fillbegin- Choose between the standard rectangular module interface and a custom bit-mapped interface. -end- igen.typesel.custom -begin- Use the bitmap editor to create your own circuit element symbols. -end- igen.typesel.std -begin- Use a standard rectangular interface. -end- igen.portsel.label -begin- Interface Generator %s Port Selection -end- igen.portsel.exp -fillbegin- Select the ports to be placed on the reference interface. Use the mouse to drag ports into the desired positon. Double click to change a value or add a new port. -end- igen.portplace.label -begin- Interface Generator %s Port Placement -end- igen.portplace.exp -fillbegin- Set placement options for ports. -end- module.props Module Properties ipanel.plist Port List ipanel.props Interface Properties ipanel.itype.change Change Type... ipanel.itype.generate Auto Generate... ipanel.itype.edsymbol Edit Symbol... ipanel.block Block ipanel.symbol Symbol ipanel.block.props Port Placement... ipanel.block.description Block Interface ipanel.symbol.description Custom Symbol Interface ipanel.ppos.label Block resize port handling: ipanel.ppos.fix Fixed positions ipanel.ppos.scale Scaled positions ipanel.warn.toblock -begin- You are about to change the interface type for this module to "block". This will result in the current interface data being destroyed. Are you sure you want to do this? -end- ipanel.warn.tosymbol -begin- You are about to change the interface type for this module to "symbol". This will result in the current interface data being destroyed. You will also need to create a bitmap image for your new symbol. Are you sure you want to do this? -end- ############################################################################## # # Block list dialog boxes blklst.newmod New Module blklst.delmod Delete Module blklst.frommod Copy Module From blklst.tomod To blklst.oldname Old Name blklst.newname New Name blklst.claim Claim Module blklst.to To blklst.from From blklst.name Name blklst.new.cap Create New Module blklst.del.cap Delete Module blklst.copy.cap Copy Module blklst.rename.cap Rename Module blklst.claim.cap Claim Module blklst.setroot.cap Set Root Module blklst.new.exp -fillbegin- Use this dialog box to create a new module definition. You can create the module as a netlist or an HDL module, but once created you will not be able to modify the type without deleting and rebuilding the module. -end- blklst.del.exp -fillbegin- Delete the definition and interface data for the specified module. Existing instances of the deleted module will be retained but will be marked as undefined. -end- blklst.copy.exp -fillbegin- Create a copy of the specified module definition. Use this to create a new variant of an existing module. -end- blklst.rename.exp -fillbegin- Rename a module definition. This operation will affect only the definition, any existing instances of this module will continue to point to the old module name. -end- blklst.claim.exp -fillbegin- Convert a library module to a user module. This allows the module to be edited and to be saved with the user circuit. -end- blklst.setroot.exp -fillbegin- Make the specified module the top-level module. -end- find.label Find Objects find.exp -fillbegin- Look for text either in a gate name, a wire name or in the text of a comment. Double click on a result to go to that item. -end- find.result.module Module find.result.type Type find.result.name Object Name find.type.gate gate find.type.net net find.type.comment comment find.options Search Options find.results Search Results # # This is a special tag used to indicate whether the position qualifier box # should be "before" or "after" the text entry box. Use the keywords before # or after to indicate the position. # @find.qual.pos before find.qual.contains Contains... find.qual.begins Begins with... find.qual.ends Ends with... find.qual.matches Matches... find.dom.label Look for objects in: find.dom.gates Gates find.dom.nets Nets find.dom.text Comment Text find.search Find: find.target Target # # These are special tags used to indicate the image file to be used for # displaying port types. # @portlist.in input.gif @portlist.out output.gif @portlist.inout pinout.gif ############################################################################## # # Circuit Dialog box # circ.ident Identification circ.filev File Version circ.file File Name circ.title Circuit Title circ.discchg Do not warn about discarding changes. circ.extbar Use extender bars. circ.noextbar Do not use extender bars. circ.iniscript Initialization Scripts circ.noscript No script files selected. circ.really Do you really want to remove '%s' from the list of initialization scripts. ############################################################################## # Simulator # sim.breakpt Breakpoint ############################################################################## # # Critical path messages # cp.delay Path Delay: cp.pathl Path List: cp.numpath Number of Paths: cp.recompute Recompute ############################################################################## # Error messages # err.verilog Errors in file: err.nopin Can't change selected pin. err.badhex Illegal hex value '%s' ignored. err.gatanchor Gate(s) are anchored and can not be moved. err.protdata Can not modify contents of protected or library module. err.badfind Can't find target '%s'. err.badopendel Can't delete open module. err.nosrcmod Source module '%s' not found. err.noerr Can not locate error. err.misserr Error information incomplete (did the simulator crash?) err.pounimpl Unimplemented error in ParseOption err.badinadd Can't add any more inputs to selected gate. err.badoutadd Can't add any more outputs to selected gate. err.badinoutadd Can't add any more inout pins to selected gate. err.badpinchg Can't change pin types on selected gate. err.badnetname Illegal characters in identifier deleted. err.netbcrename Identifier renamed to '%s' because of illegal characters. err.netconfnet Identifier renamed to '%s' because of conflict. err.netconfgat Identifier renamed to avoid conflict with primitive gate name err.netconfkw Identifier renamed to avoid conflict with reserved word. err.badconsame Connection refused because wires are part of the same net. err.badconptsp Connection refused because both wires are module ports or supply. err.badconbitw Connection refused because bit widths do not match. err.badrange Non-positive range for scope trace is not allowed. err.badlprcmd Unable to exectute printer command '%s'. err.badpsopen Unable to open file '%s' for postscript output. err.badid Illegal identifier '%s'. err.protintf Can't modifiy protected interface on module '%s'. err.bkpt.badexp Syntax error in breakpoint expression. Must be one of: 'net', '!net', 'net==value', 'net!=value' err.bkpt.badnet Invalid net name '%s'. Names must start with a letter and contain only letters, digits and '.'. err.bkpt.badval Syntax error in value '%s'. Must be decimal or verilog-style constant. err.bkpt.toomany Too many breakpoints. Maximum is %d. err.sim.badtmp Could not save temporary file '%s' for simulator (disc full?) err.sim.syntx Syntax error in '%s' command. err.sim.noincl Include file '%s' not found. err.sim.clockbadedge Illegal edge indicator '%c' in clock command. err.sim.nobkpt No such breakpoint '%s'. err.sim.nonet Can't find net '%s'. err.sim.nogate Can't find gate '%s'. err.sim.badbin Illegal charcter in binary constant '%s'. err.sim.notswitch Gate '%s' is not a switch, dip or register. err.sim.badcmd Unrecognized command '%s' in simulation script. err.noteditpchg Properties can only be changed in edit mode. err.badeditop Illegal interface edit mode operation. err.badopen Unable to open input file '%s'. err.badlibopen Unable to open library file '%s'. err.nomark Please set a mark with the left mouse button before selecting a gate type. err.badgate Unknown gate type. err.badmake Unable to create gate. err.badportadd Can't add ports to gates of this type. err.badportdel Selected port can not be deleted. err.badportedit Selected port can not be edited. err.noport No port selected. err.manypages -fillbegin- There are an awful lot of pages in this document. Are you sure you want to print it? -end- err.nojump -fillbegin- The 'jump-to-module' feature can not be used in simulation or critical path analysis mode. Please navigate manully to the target block by selecting modules and opening them with the '>' keyboard command. You can leave a module you are in with the '<' keyboard command. -end- err.nomod Module '%s' is not defined. err.modlock Logic Block is Locked! err.closeroot Can't close top-level module. Use quit. err.sim.isrun Simulator is already running (Use 'Ctrl-s e' to end). err.sim.isnotrun Simulator is not running (Use 'Ctrl-s b' to start). err.editonly Command not valid when in simulation mode. err.simonly Command valid only in simulation mode. err.nodel No deletable selection. err.modnotdef Module '%s' is undefined. err.moddef The module '%s' already exists. err.primredef Built-in element name '%s' can not be redefined. err.noprop Selected gate has no editable properites. err.openscript Can't open simulation script file '%s' err.oldversion Loaded file with obsolete version number %s (current version is %s). err.futureversion Loaded file saved by future tkgate version %s (this version is %s). err.badversion Unknown version number. Use at your own risk. err.nodrive Net %s has no driver in module %s. err.noconn Wire %s{%d} has no connections - deleted. err.oldportact Please right click on port or module edge to add/change port. err.nomodule No selected module. err.nomodop No suitable modules for operation. err.backupfail Unable to create backup file '%s'. err.corruptnewsave -fillbegin- TkGate was able to save your file in '%s', but it appears to be corrupted. If you have checkpointing enabled try loading one of the checkpoint files. Use 'tkgate -V' to check the integrety of a save file. -end- err.corruptsave -fillbegin- TkGate detetected a problem while trying to save the file '%s'. The existing file has been left unmodified and the damaged file has been written to '%s'. If you have checkpointing enabled you can try loading one of the checkpoint files. You can also use 'tkgate -V' to check the integrety of a save file. -end- err.badsave -fillbegin- A problem has occured trying to open or write the file '%s'. Check file/directory protections and or disk space. -end- err.nosafesave -fillbegin- A problem has occured attempting to save '%s'. If you wish, you can try again without save validation. If you say "no", the original file will remain unmodified. If you say "yes" the original file will be overwritten, but may be destroyed if a problem occurs. Would you like to attempt an unvalidated save? -end- err.noback -fillbegin- File was created by tkgate %s, and may not be readable by versions earlier than current version (%s) if you save. -end- ############################################################################## # Informational messages # msg.selwire Selected wire named '%s'. msg.selgate Selected %s named '%s'. msg.selblock Selected %s block named '%s'. msg.modoverwt Destination module '%s' already exists. Overwrite? msg.foundgate Found gate named '%s'. msg.foundwire Found wire named '%s'. msg.searchagn Target string '%s' not found. Hit 'find' to restart search again. msg.sim.chgtoroot Simulation mode requires root module at top of edit stack. msg.sim.nogatemod Simulation mode requires concrete module stack. msg.setinterface Set module interface for '%s'. msg.needsel Please select a module instance. msg.wroteckpt Checkpointed to %s... msg.save Saved circuit to '%s'. msg.reallynew Circuit has been modified. Do you really want to discard your changes and create a new circuit? msg.reallyquit Circuit has been modified. Do you really want to exit? msg.notlib Module '%s' is not a library module. ############################################################################## # Miles messages (Activated when Miles Bader uses tkgate) # miles.msg1 Only a fool would put %s%s there, Miles. miles.msg2 That's a really stupid place to put %s%s, Miles. miles.msg3 That's a terrible place for %s%s, Miles. miles.msg4 Miles, you are a fool for putting %s%s there. miles.msg5 Only you would put %s%s there, Miles. miles.msg6 Putting %s%s there is proof of your absolute stupidity, Miles. miles.msg7 Why don't you give up Miles, this is a stupid circuit. miles.msg8a It's pointless to continue, Miles. miles.msg8b It's obvious you can't design a circuit ############################################################################## # Balloon Help # ho.new -begin- Clear the current circuit, and start editing a new one. -end- ho.open Open a circuit from a file. ho.save Save circuit to current file. ho.print Print current circuit. ho.library Load a library file. ho.move -begin- Move/Connect - By clicking and dragging you can: Set the position for a new gate Move gates and wires Connect wires By double-clicking you can: Edit gate, wire and port properties Edit comment text -end- ho.delgat -begin- Delete Gate - Use this tool to delete gates. -end- ho.cutw -begin- Cut Wire - Use this tool to cut wires. -end- ho.inv -begin- Invert - Use this tool to add or remove inverters from gate ports. -end- ho.bitw -begin- Bit Width - Use this tool to change the bit size of a wire. Enter the number of bits in the entry box in the lower right corner of the window. -end- ho.mod.open Open the selected module. ho.mod.close Close the current module. ho.mod.new Create a new module type. ho.mod.del Delete a module. ho.mod.copy Copy a module. ho.mod.rename Rename a module. ho.mod.claim -begin- Convert a library module to a regular module. -end- ho.mod.setroot -begin- Designate a module to be the root module. -end- ho.undo Undo previous action(s) ho.redo Redo undone action(s) ho.tab.edit -begin- Primary editing mode. -end- ho.tab.interface -begin- Edit module interfaces. While in interface mode, double click on a module in the module list to edit its interface, or on the root module to display all interface. -end- ho.tab.simulate -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.tab.cpath -begin- Find critical paths in a circuit. -end- ho.simstart -begin- Start the simulator, open the logic analyzer and execute any initialization scripts if defined. -end- ho.simgo -begin- Run simulator in continuous execution mode. Note that combinational circuits simulate only until the circuit reaches steady state. -end- ho.simpause -begin- Pause a continuously running simulation. -end- ho.simstep -begin- Step a fixed interval of time. Open the simulation options window to set the step size. -end- ho.simclock -begin- Step a fixed number of clock cycles. Open the simulation options window to set the step size. -end- ho.simstop -begin- End the current simulation and return to edit mode. -end- ho.simbreak -begin- Edit the current breakpoints. Simulation will be halted when a breakpoint condition becomes true. -end- ho.simexec Execute a simulation script. ho.simload -begin- Load memory with contents of a .mem file. -end- ho.simdump -begin- Dump the contents of a memory to a .mem file. -end- ho.sim.break -begin- Enter a simulator breakpoint. Breakpoints are expressions which cause the simulator to pause execution when they become true. Currently only simple expressions with a single relational operator such as "w1 == 0" or "w7 != 8" are supported. Expressions such as "w8" or "!w2" may also be used to test for non-zero and zero values respectively. -end- ho.f.modlist -begin- OBSOLETE -end- ho.f.modlisttab -begin- List of all modules currently loaded. You can display the list in either alphabetical or hierarchical form by selecting the appropriate tab. Drag modules to the edit window to create new instances. -end- ho.netlist -begin- List of nets in the current module. The symbol to the left of the name indicates whether the net is single bit (green) or multi-bit (red). An "A" shown in the symbol indicates that the net name is marked as visible. -end- ho.ports -begin- List of ports on the interface of the module displayed in the edit window. The symbol before the port indicates the direction of the port. -end- ho.status.logo -begin- Simulation status indicator. If the iron gate logo is shown, tkgate is in edit mode. If the quadrapedal AND gate is shown, tkgate is in simulation mode. If the AND gate is stationary, the simulation is paused, and if it is walking the simulation is running. -end- ho.status.msg Messages from tkgate are displayed here. ho.status.block The stack of modules being edited. ho.status.file -begin- The current file being edited. A '*' indicates that the buffer has been modifed since the last save. -end- ho.print.selall Print all modules currently loaded by TKGate. ho.print.selcur Print only the current module in the TKGate edit window. ho.print.seluse -begin- Print all modules "in use". In use modues are those that are a decendent of the root module. -end- ho.print.fulltrace Print the entire trace. ho.print.parttrace -begin- Print a portion of the trace. Enter the starting and stopping times in the entry windows below, or use the right mouse button to select a range on the scope window (use shift-right to select long ranges). -end- ho.print.parttracestart Starting time of trace output. ho.print.parttraceend Ending time of trace output. ho.print.selsel -begin- Print only the modules selected below. Use the control key to select multiple modules. -end- ho.print.modlist Select the modules to be printed. ho.circuit.discchg -begin- TkGate will not display a warning if you discard changes without saving. -end- ho.circuit.extbar -begin- Basic gates (AND, OR, XOR) will use extender bars to handle many input gates. -end- ho.cmd.bitw -begin- Wires selected with the cursor will be set to this bit width. -end- ho.edgat.signam -begin- The name of the selected signal on the selected gate. You can change the name of the signal by editing it here. -end- ho.edgat.port -begin- The name of the port for this signal on the gate. This field can only be edited for module instances. -end- ho.edgat.iolab -begin- The direction of the selected signal on the selected gate. This field can only be edited for module instances. -end- ho.edgat.bitlab -begin- The bit width of the selected signal on the selected gate. You can change the bitwidth by editing it here. -end- ho.edgat.cycle The total number of epochs in a clock cycle. ho.edgat.phase The starting point of the cycle (in percent). ho.edgat.duty The percent of the cycle, the clock is low. ho.edgat.cname Name of connected net. ho.edgat.cport Port to which net is connected. ho.edgat.ctype Type of connection. ho.edgat.cbitw Bit width of connected net. ho.edgat.cedit Edit the selected port. ho.edgat.cadd Add a port. ho.edgat.cdel Delete the selected port. ho.edgat.hide -begin- Set this flag to disable display of gate name. -end- ho.edgat.gtype Type of the gate. ho.edgat.gname Name of this gate instance. ho.edgat.ganchor Set this flag to anchor the position of a gate. ho.edgat.gx X coordinate of gate. ho.edgat.gy Y coordinate of gate. ho.edgat.swstate -begin- The initial state of the switch to use when starting a simulation. -end- ho.edgat.dipstate -begin- The initial state of the dip switch to use when starting a simulation. -end- ho.edgat.range The range of bits to pull off a bus. ho.edgat.memfile -begin- The file with the initial state for this memory. This file is read when the simulator is started. -end- ho.edgat.func The function type of this module. ho.edgat.frame The frame label. ho.traceprint Print trace logic trace. ho.showxhair -begin- If this button is depressed, a vertical crosshair line will be displayed in the scope window. -end- ho.opt.sorttraces -begin- If this option is enabled, traces on the scope window will be displayed in sorted order. If this option is disabled, traces on the scope window will be displayed in the order in which the probes were set. -end- ho.opt.undolen -begin- Maximum number of undo actions to retain. -end- ho.opt.site -begin- The name of the site where tkgate is installed. This name will be used on any printer or postscript output. -end- ho.opt.smooth -begin- If this option is enabled, scrolling will be optimized by using bitmap copies instead of a complete redisplay. You can turn this off if there are any problems with your server. -end- ho.opt.clip -begin- If this option is enabled, clipping will be used to update only the exposed portion of the window on a redisplay. Otherwise the entire display will be redrawn for all exposures. -end- ho.opt.outmove -begin- If this option is enabled, only an outline of module instances being moved will be displayed while dragging. Use this feature only on machines with slow displays. -end- ho.opt.bhelp -begin- If this option is enabled, help balloons will be activated. Help balloons, such as this one, provide tips on interface elements when the mouse is over them. -end- ho.opt.novice -begin- If no other circuit is specified on the command line. A TkGate tutorial will be disaplyed as the initial circuit on start up. -end- ho.opt.debug -begin- Enables several debugging features only useful to TkGate developers. -end- ho.opt.ckpt Enable checkpointing of unsaved circuits. ho.opt.ckptfreq Frequency of checkpoints in seconds. ho.opt.beak -begin- Enable these totally useless features. If you disable this feature, these modes (and this checkbox) will no longer appear in the options box. The only way to reenable them will be to edit your .tkgate-properties file. -end- ho.opt.miles -begin- If this mode is enabled, TkGate will periodically insult the intelligence of the user. -end- ho.opt.bat -begin- If this mode is enabled, TkGate will set up an enviornment for designing a bat computer. -end- ho.opt.trek Beam me up Scoty! ho.opt.normal Disable fun Stuff. ho.opt.simstep -begin- The number of epochs to advance when the step command is issued. -end- ho.opt.ckstep -begin- The number of clock cycles to advance when the clock step command is issued. -end- ho.opt.ckover -begin- The number of epochs past rising edge of the clock to advance when the clock step command is issued. -end- ho.opt.vpopupdelay -begin- The delay in milliseconds between pressing and holding the mouse button and the display of a signal value. On some systems, short delay values interfere with the ability to recognize a double click. If you have this problem, increase this value. Values between 1 and 10000 are allowed. -end- ho.opt.init -begin- A simulation script file to execute automatically when the simulation is started. -end- ho.opt.ckall -begin- If this mode is enabled, the clock step command will pause the simulation on the positive edge of any clock in the circuit. -end- ho.opt.ckspec -begin- If this mode is enabled, the clock step command will pause the simulation only on the positive edge of the specified clock. -end- ho.opt.keybind -begin- Specifies the basic style for key bindings. If you change this option, bindings will be updated immediately, but you will need to restart tkgate to see any user defined keybindings. -end- ho.deftech -begin- Default technology for new gates. Affects delay of gates. To change the technology of a specific gate, open its properties box (double click) and select the "Delay" tab. -end- ho.techbut -begin- Use delays from standard technology definition file. To add custom technologies, add them to the list in the "File -> Options -> Simulate" menu. -end- ho.custbut -begin- Set custom delay values for this gate. -end- ho.contver -begin- Continuously verify the integrity of internal data structures after every operation. -end- ho.simwatch -begin- Display commands sent between the GUI and the simulator. -end- ho.simlog -begin- Write commands issued to the simulator to a log file. The log file can then be used as input to the simulator in a debugger. -end- ho.simed.point -begin- Pixel edit mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.simed.line -begin- Line mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.simed.rect -begin- Rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.simed.fillrect -begin- Filled rectangle mode. Use the left mouse button to set pixels and the right button to clear them. -end- ho.simed.select -begin- Bitmap select mode. Use the left mouse buttons to select regions of the bitmap and do cut and paste operations on the selection. -end- ho.simed.port -begin- Port select mode. Select ports and move them or rotate them. -end- ho.tool.currot -begin- Displays the current default rotation. Click on this button to change the current default rotation. -end- ho.tool.rotate Rotate selected gate(s) counter-clockwise. ho.tool.brotate Rotate selected gate(s) clockwise. ho.tool.valgn Align selected gate(s) vertically. ho.tool.halgn Align selected gate(s) horizontally. ho.tool.cut Cut selection. ho.tool.copy Copy selection. ho.tool.paste Paste from cut buffer. ho.tool.find Find gate, wire or text. tkgate-2.0-b10/locale/en/tutorials/modules.v000644 001751 001751 00000047124 11135014240 021533 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "module_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g3 @(259,83) /anc:1 //: /line:"A module is an encapsulated piece of logic that can be made" //: /line:"to serve a purpose in a circuit, similar to a function call" //: /line:"in a program. Each module in TkGate has an \"interface\" and" //: /line:"a \"definition\":" //: /line:"" //: /line:" * The interface describes the external" //: /line:" appearance of a module including the size of the box and" //: /line:" the positions of the ports on it. TkGate supports \"block\"" //: /line:" interfaces and \"symbol\" interfaces." //: /line:" " //: /line:" * The definition describes the internal" //: /line:" logic that the module implements. TkGate supports \"netlist\"" //: /line:" and \"HDL\" modules." //: /line:"" //: /end //: comment g2 @(10,65) /sn:0 /anc:1 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

" //: /line:"" //: /line:"In this chapter, you will learn how to create, edit and manage modules." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(258,177)(273,177){1} wire w3; //: /sn:0 {0}(258,161)(273,161){1} wire w0; //: /sn:0 {0}(200,161)(185,161){1} wire w1; //: /sn:0 {0}(200,177)(185,177){1} wire w2; //: /sn:0 {0}(200,192)(185,192){1} wire w5; //: /sn:0 {0}(258,193)(273,193){1} //: enddecls bar g4 (.C(w2), .B(w1), .A(w0), .Z(w5), .Y(w4), .X(w3)); //: @(201, 145) /sz:(56, 72) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Ro0<0 Ro1<0 Ro2<0 ] //: comment g3 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(editing module definitions)" //: /line:"" //: /line:"To edit the definition of a module you have created, double click on its name in the module name" //: /line:"tree or list view. Alternatively you can right click on an instance of the module and select" //: /line:"Open from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g4 @(576,89) /sn:0 /anc:1 //: /line:"Hint: The pages in this tutorial" //: /line:"are actually modules with the" //: /line:"names PAGE1, PAGE2, etc." //: /end //: comment g3 @(23,72) /sn:0 /anc:1 //: /line:" Top-level or root module." //: /line:"" //: /line:" Netlist module." //: /line:"" //: /line:" Verilog HDL module." //: /line:"" //: /line:" Locked netlist module." //: /line:"" //: /line:" Locked Verilog HDL module." //: /line:"" //: /line:" Container for unused modules." //: /line:"" //: /end //: comment g2 @(257,69) /anc:1 //: /line:" Library module." //: /line:"" //: /line:" Container for all libraries." //: /line:"" //: /line:" Container for a single library." //: /line:"" //: /line:" Use of an undefined module." //: /line:"" //: /line:" Recursive inclusion of a module." //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list symbols)" //: /line:"" //: /line:"The following symbols are used in the module tree and list view:" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin foo module foo(Z2, I3, Z1, I1, I2, Z3); //: interface /sz:(41, 40) /bd:[ ] input I2; //: /sn:0 {0}(245,200)(275,200){1} //: {2}(277,198)(277,153)(292,153){3} //: {4}(277,202)(277,248)(348,248){5} output Z3; //: /sn:0 {0}(369,251)(448,251){1} input I1; //: /sn:0 {0}(292,148)(278,148)(278,128)(246,128){1} output Z2; //: /sn:0 {0}(392,156)(380,156)(380,184){1} //: {2}(382,186)(448,186){3} //: {4}(378,186)(369,186){5} output Z1; //: /sn:0 {0}(448,154)(413,154){1} input I3; //: /sn:0 {0}(348,188)(296,188)(296,251){1} //: {2}(298,253)(348,253){3} //: {4}(294,253)(245,253){5} wire w0; //: /sn:0 {0}(348,183)(338,183)(338,153){1} //: {2}(340,151)(392,151){3} //: {4}(336,151)(313,151){5} //: enddecls _GGAND2 #(6) g8 (.I0(I2), .I1(I3), .Z(Z3)); //: @(359,251) /sn:0 /w:[ 5 3 0 ] /eb:0 //: OUT g4 (Z2) @(445,186) /sn:0 /w:[ 3 ] //: joint g13 (w0) @(338, 151) /w:[ 2 -1 4 1 ] //: IN g2 (I3) @(243,253) /sn:0 /w:[ 5 ] //: OUT g1 (Z1) @(445,154) /sn:0 /w:[ 0 ] //: comment g16 @(585,127) /sn:0 //: /line:"Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end _GGAND2 #(6) g11 (.I0(w0), .I1(Z2), .Z(Z1)); //: @(403,154) /sn:0 /w:[ 3 0 1 ] /eb:0 //: joint g10 (I2) @(277, 200) /w:[ -1 2 1 4 ] //: IN g19 (I1) @(244,128) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g6 (.I0(I1), .I1(I2), .Z(w0)); //: @(303,151) /sn:0 /w:[ 0 3 5 ] /eb:0 //: joint g9 (I3) @(296, 253) /w:[ 2 1 4 -1 ] _GGXOR2 #(8) g7 (.I0(w0), .I1(I3), .Z(Z2)); //: @(359,186) /sn:0 /w:[ 0 0 5 ] /eb:0 //: comment g15 @(22,25) //: /line:"This is the definition for module \"foo\"." //: /end //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: IN g5 (I2) @(243,200) /sn:0 /w:[ 0 ] //: joint g23 (Z2) @(380, 186) /w:[ 2 1 4 -1 ] //: OUT g12 (Z3) @(445,251) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(40, 40) /bd:[ ] input [7:0] B; //: /sn:0 {0}(#:342,147)(342,184){1} //: {2}(344,186)(367,186){3} //: {4}(371,186)(425,186)(425,258){5} //: {6}(369,188)(369,261){7} //: {8}(342,188)(342,258){9} input [1:0] F; //: /sn:0 {0}(#:343,353)(214,353){1} supply0 w0; //: /sn:0 {0}(491,295)(491,272)(465,272){1} input [7:0] A; //: /sn:0 {0}(#:265,147)(265,215){1} //: {2}(267,217)(345,217){3} //: {4}(349,217)(372,217){5} //: {6}(376,217)(457,217)(457,258){7} //: {8}(374,219)(374,261){9} //: {10}(347,219)(347,258){11} //: {12}(265,219)(265,322)(348,322)(348,337){13} output [7:0] Z; //: /sn:0 {0}(#:366,404)(366,366){1} wire [7:0] w14; //: /sn:0 {0}(#:345,279)(345,310)(360,310)(360,337){1} wire w4; //: /sn:0 {0}(417,272)(407,272){1} wire [7:0] w11; //: /sn:0 {0}(#:372,282)(372,337){1} wire [7:0] w10; //: /sn:0 {0}(#:384,337)(384,307)(441,307)(441,287){1} //: enddecls _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4)); //: @(441,274) /sn:0 /w:[ 5 7 1 1 0 ] //: joint g8 (A) @(347, 217) /w:[ 4 -1 3 10 ] //: IN g3 (F) @(212,353) /sn:0 /w:[ 1 ] //: GROUND g13 (w0) @(491,301) /sn:0 /w:[ 0 ] //: IN g2 (A) @(265,145) /sn:0 /R:3 /w:[ 0 ] //: IN g1 (B) @(342,145) /sn:0 /R:3 /w:[ 0 ] //: joint g11 (B) @(369, 186) /w:[ 4 -1 3 6 ] //: joint g10 (A) @(374, 217) /w:[ 6 -1 5 8 ] _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11)); //: @(372,272) /sn:0 /R:3 /w:[ 7 9 0 ] /eb:0 _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14)); //: @(345,269) /sn:0 /R:3 /w:[ 9 11 0 ] /eb:0 //: joint g9 (A) @(265, 217) /w:[ 2 1 -1 12 ] //: OUT g5 (Z) @(366,401) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z)); //: @(366,353) /sn:0 /w:[ 13 1 1 0 0 1 ] /ss:0 /do:0 //: joint g12 (B) @(342, 186) /w:[ 2 1 -1 8 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(573,160) /sn:0 /anc:1 //: /line:"Hint: If you are unable to modify a" //: /line:"module interface, right click on it," //: /line:"select Module Properties..., then" //: /line:"unset the interface protection options" //: /line:"in the dialog box." //: /end foo g2 (); //: @(208, 163) /sz:(40, 40) /sn:0 /p:[ ] //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(manual interface generation)" //: /line:"" //: /line:"You can also manually create and edit the interface of a module:" //: /line:" * To change the size of the interface, left-click on an edge or corner and drag it with the mouse." //: /line:" * To add a port, right click on an edge and choose the port type to create from the popup menu." //: /line:" * To delete a port, select the tool and cut the wire off of the module." //: /line:" * To edit port properties, double click on the port with the tool." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire [1:0] w0; //: /sn:0 {0}(#:257,226)(272,226){1} wire [7:0] w3; //: /sn:0 {0}(#:329,194)(314,194){1} wire [7:0] w1; //: /sn:0 {0}(#:257,210)(272,210){1} wire [7:0] w2; //: /sn:0 {0}(#:257,194)(272,194){1} //: enddecls ALU g3 (.A(w2), .B(w1), .F(w0), .Z(w3)); //: @(273, 178) /sz:(40, 64) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Ro0<1 ] //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(updating the default interface)" //: /line:"" //: /line:"Module interfaces constructed in Edit mode, apply only to the specific instance that you created." //: /line:"To make an interface the default for newly created instance of modules of that type, right click" //: /line:"on an interface and select Interface → Set. Try setting the interface to each of the two instances of" //: /line:"ALU modules below, then try creating new ALU modules by dragging them from the module list." //: /end ALU g0 (); //: @(130, 184) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(automatic interface generation)" //: /line:"" //: /line:"The interface of a module includes the size and shape of the box as well as the location and names" //: /line:"of the ports. The easiest way to create an interface is to use automatic generation. Automatic" //: /line:"generation uses the ports referenced in the definition to create the interface. To automatically" //: /line:"create an interface for the \"bar\" module, first click on the module list tab , then right click on \"bar\"" //: /line:"and select Interface → Auto Generate... Now left click and drag the bar module onto the canvas to see" //: /line:"the new interface." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module definitions)" //: /line:"" //: /line:"To create a new module, press the button. Enter the name for the new module" //: /line:"and select whether you wish to create it as a \"netlist\" (graphical) module or an" //: /line:"HDL (textual) module. Try creating a new module named \"CPU\"." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(548,6) /sn:0 /anc:1 //: /line:"" //: /end //: comment g2 @(554,346) /sn:0 /anc:1 //: /line:"Module Tree View Example" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list)" //: /line:"" //: /line:"The set of modules in the current circuit is shown on the left-hand side of the interface. You" //: /line:"can choose between a tree view (see example) and a list view . The tree view shows" //: /line:"the module hierarchy starting at a top-level root module indicated by the symbol. Modules" //: /line:"which are still in the circuit, but are not used anywhere in the hierarchy are listed under the" //: /line:"\" Unused\" branch. Click on to open a branch on the tree." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(545,102) /sn:0 /anc:1 //: /line:"Hint: You can also drag and drop" //: /line:"module instance from the tree view," //: /line:"but it is easier to use the list view" //: /line:"since that view gives you a straight" //: /line:"alphabetical list of all module." //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module instances)" //: /line:"" //: /line:"The easiest way to create a module instance is to find its name in the module list and" //: /line:"drag it into the current circuit. Try switching to the list view by pressing then" //: /line:"dragging several instances of the \"bar\" module into the current edit window." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(11,22) /anc:1 //: /line:"

Using Modules

(interface editor)" //: /line:"" //: /line:"You can directly edit the module interface using TkGate's interface mode. Click on the Interface" //: /line:"tab over the main canvas to enter this mode. Details on how to use this mode are given in the TkGate" //: /line:"documentation. Click on the Edit tab to return to the normal editing mode." //: /end endmodule //: /netlistEnd //: /netlistBegin bar module bar(Y, X, C, B, Z, A); //: interface /sz:(56, 72) /bd:[ Li0>A(16/72) Li1>B(32/72) Li2>C(48/72) Ro0Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end //: joint g10 (B) @(118, 207) /w:[ -1 2 1 4 ] //: joint g19 (C) @(162, 260) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g6 (.I0(A), .I1(B), .Z(w0)); //: @(144,158) /sn:0 /w:[ 0 3 5 ] /eb:0 //: joint g9 (C) @(137, 260) /w:[ 2 1 8 -1 ] _GGXOR2 #(8) g7 (.I0(w0), .I1(C), .Z(Y)); //: @(200,193) /sn:0 /w:[ 0 0 5 ] /eb:0 //: comment g15 @(22,25) //: /line:"This is the definition for module \"bar\". Ports A, B and C are inputs, and ports X, Y and Z are" //: /line:"outputs. Try adding an additional output port \"W\" from the output of the XOR gate below." //: /line:"Right click at the position you want to create the port then select Make → Module → Module" //: /line:"Output from the popup menu. Enter \"W\" for the net name in the dialog box." //: /line:"" //: /line:"" //: /end _GGXOR2 #(8) g17 (.I0(C), .I1(X), .Z(w3)); //: @(293,129) /sn:0 /w:[ 7 3 0 ] //: OUT g5 (Z) @(343,258) /sn:0 /w:[ 1 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: IN g0 (A) @(84,135) /sn:0 /w:[ 1 ] //: joint g18 (X) @(266, 161) /w:[ 1 2 4 -1 ] //: joint g12 (Y) @(221, 193) /w:[ 2 1 4 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGOR2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/group.v000644 001751 001751 00000025225 11135014231 021215 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(140,67) /sn:0 /anc:1 //: /line:"" //: /end //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

" //: /line:"" //: /line:"In this chapter, you will learn about how to do editing operations on groups of gates." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:183,147)(289,147)(289,189){1} //: {2}(291,191)(314,191){3} //: {4}(289,193)(289,210){5} reg a0; //: {0}(40:183,183)(227,183){1} //: {2}(231,183)(239,183){3} //: {4}(229,185)(229,239)(246,239){5} reg b0; //: {0}(50:183,218)(221,218){1} //: {2}(223,216)(223,188)(239,188){3} //: {4}(223,220)(223,244)(246,244){5} wire w7; //: /sn:0 {0}(267,242)(282,242)(282,254){1} wire s0; //: {0}(36:335,189)(365,189){1} wire w4; //: /sn:0 {0}(287,231)(287,254){1} wire c1; //: {0}(99:285,275)(285,294){1} wire w9; //: /sn:0 {0}(314,186)(286,186){1} //: {2}(282,186)(260,186){3} //: {4}(284,188)(284,210){5} //: enddecls //: LED g37 (s0) @(372,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(285,265) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(257,242) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(166,147) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(284, 186) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(287,221) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(166,183) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(229, 183) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(incremental selection)" //: /line:"" //: /line:"You can add or remove gates from the current selection by holding the Control key while" //: /line:"you click on them. Use the selection box to select the gates below then click on a few" //: /line:"of the gates with the Control key held down. Release the Control key and then try moving" //: /line:"the selection with only some of the gates selected." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(325,189) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(250,186) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(166,218) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (b0) @(223, 218) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(289, 191) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:167,153)(273,153)(273,195){1} //: {2}(275,197)(298,197){3} //: {4}(273,199)(273,216){5} reg a0; //: {0}(40:167,189)(189,189)(189,189)(211,189){1} //: {2}(215,189)(223,189){3} //: {4}(213,191)(213,245)(230,245){5} reg b0; //: {0}(50:167,224)(186,224)(186,224)(205,224){1} //: {2}(207,222)(207,194)(223,194){3} //: {4}(207,226)(207,250)(230,250){5} wire w7; //: /sn:0 {0}(251,248)(266,248)(266,260){1} wire s0; //: {0}(36:319,195)(349,195){1} wire w4; //: /sn:0 {0}(271,237)(271,260){1} wire c1; //: {0}(99:269,281)(269,300){1} wire w9; //: /sn:0 {0}(298,192)(270,192){1} //: {2}(266,192)(244,192){3} //: {4}(268,194)(268,216){5} //: enddecls //: LED g37 (s0) @(356,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(570,113) /sn:0 /anc:1 //: /line:"Hint: If a selection contains any" //: /line:"anchored gates, the entire selection" //: /line:"will act as if it were anchored." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(269,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(241,248) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(150,153) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(268, 192) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(271,227) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(150,189) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(213, 189) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(rotation and anchoring)" //: /line:"" //: /line:"You can rotate (with and ) and anchor (with and ) a group of gates in the same" //: /line:"way as you did for single gates in the Editing Gates chapter. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(309,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(234,192) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(150,224) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(207, 224) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(273, 197) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:174,160)(280,160)(280,202){1} //: {2}(282,204)(305,204){3} //: {4}(280,206)(280,223){5} reg a0; //: {0}(40:174,196)(196,196)(196,196)(218,196){1} //: {2}(222,196)(230,196){3} //: {4}(220,198)(220,252)(237,252){5} reg b0; //: {0}(50:174,231)(193,231)(193,231)(212,231){1} //: {2}(214,229)(214,201)(230,201){3} //: {4}(214,233)(214,257)(237,257){5} wire w7; //: /sn:0 {0}(258,255)(273,255)(273,267){1} wire s0; //: {0}(36:326,202)(356,202){1} wire w4; //: /sn:0 {0}(278,244)(278,267){1} wire c1; //: {0}(99:276,288)(276,307){1} wire w9; //: /sn:0 {0}(305,199)(277,199){1} //: {2}(273,199)(251,199){3} //: {4}(275,201)(275,223){5} //: enddecls //: LED g37 (s0) @(363,202) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(548,117) /sn:0 /anc:1 //: /line:"Hint: Hitting the Delete key will" //: /line:"delete all of the selected gates" //: /line:"without copying it to the clipboard." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(276,278) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(248,255) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(157,160) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(275, 199) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(278,234) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(157,196) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(220, 196) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(clipboard operations)" //: /line:"" //: /line:"You can use Cut and Paste operations to cut or copy a group of gates to the clipboard" //: /line:"and paste it somewhere else. Select a group of gates then press the or buttons to" //: /line:"cut or copy, respectively, the selected gates to the clipboard. To paste the contents of the" //: /line:"clipboard, first set a with the left mouse button, then press the button to paste the" //: /line:"clipboard contents to that location." //: /line:"" //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(316,202) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(241,199) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(157,231) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(214, 231) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(280, 204) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:182,149)(288,149)(288,191){1} //: {2}(290,193)(313,193){3} //: {4}(288,195)(288,212){5} reg a0; //: {0}(40:182,185)(226,185){1} //: {2}(230,185)(238,185){3} //: {4}(228,187)(228,241)(245,241){5} reg b0; //: {0}(50:182,220)(220,220){1} //: {2}(222,218)(222,190)(238,190){3} //: {4}(222,222)(222,246)(245,246){5} wire w7; //: /sn:0 {0}(266,244)(281,244)(281,256){1} wire s0; //: {0}(36:334,191)(364,191){1} wire w4; //: /sn:0 {0}(286,233)(286,256){1} wire c1; //: {0}(99:284,277)(284,296){1} wire w9; //: /sn:0 {0}(313,188)(285,188){1} //: {2}(281,188)(259,188){3} //: {4}(283,190)(283,212){5} //: enddecls //: LED g37 (s0) @(371,191) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(609,113) /sn:0 /anc:1 //: /line:"Hint: Click in a blank area to" //: /line:"unselect a group." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(284,267) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(256,244) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(165,149) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(283, 188) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(286,223) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(165,185) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(228, 185) /w:[ 2 -1 1 4 ] //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(selection and movement)" //: /line:"" //: /line:"To select a group of gates, press and hold the left mouse button above and to the left" //: /line:"of the group, then drag the cursor diagonally accross the group to open the selection box." //: /line:"Release the mouse when the selection box includes all of the gates you wish to select. Drag" //: /line:"any selected gate to move the entire group. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(324,191) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(249,188) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(165,220) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(222, 220) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(288, 193) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/wires.v000644 001751 001751 00000024474 11135014226 021223 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Wires

" //: /line:"" //: /line:"This chapter will introduce the basic wire editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(185,114) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(I/O inverters)" //: /line:"" //: /line:"To place or remove an inverter on a gate input or output, select the tool" //: /line:"and click on the port at which you want to place or remove an inveter. Try" //: /line:"using the inverter tool to place and remove inverters in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:155,153)(261,153)(261,195){1} //: {2}(263,197)(286,197){3} //: {4}(261,199)(261,209){5} reg a0; //: {0}(40:155,189)(199,189){1} //: {2}(203,189)(211,189){3} //: {4}(201,191)(201,245)(218,245){5} reg b0; //: {0}(50:155,224)(193,224){1} //: {2}(195,222)(195,194)(211,194){3} //: {4}(195,226)(195,250)(218,250){5} wire w7; //: /sn:0 {0}(239,248)(254,248)(254,260){1} wire s0; //: {0}(36:307,195)(337,195){1} wire w4; //: /sn:0 {0}(259,230)(259,260){1} wire c1; //: {0}(99:257,281)(257,300){1} wire w9; //: /sn:0 {0}(286,192)(258,192){1} //: {2}(254,192)(232,192){3} //: {4}(256,194)(256,209){5} //: enddecls //: LED g37 (s0) @(344,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Editing Wires

(wire labels)" //: /line:"" //: /line:"Wire label editing is performed with the tool. Select this tool if it is not already selected. Existing" //: /line:"wire labels can be moved by left clicking and dragging the label to a new position. Wire labels can only" //: /line:"be moved to a different locations on the wire from which it was grabbed. If you drop the label too far from" //: /line:"its wire, the label will be discarded. To display a new label right click on the wire and choose the Show" //: /line:"Label option. You can also hide a specific label (Hide Label) or hide all labels for a wire (Hide All Labels)." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(257,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(229,248) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(256, 192) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(138,153) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(259,220) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(201, 189) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(138,189) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(297,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(222,192) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(138,224) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(261, 197) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(195, 224) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] supply1 w7; //: /sn:0 {0}(320,176)(335,176)(335,158){1} reg [7:0] w3; //: /sn:0 {0}(#:184,170)(184,208)(212,208)(212,224){1} supply0 w8; //: /sn:0 {0}(271,250)(271,238)(252,238){1} supply0 w5; //: /sn:0 {0}(339,207)(339,186)(320,186){1} wire [7:0] w6; //: /sn:0 {0}(281,171)(281,146)(371,146)(371,268)(#:228,268)(#:228,253){1} wire w4; //: /sn:0 {0}(204,238)(189,238){1} wire [7:0] w1; //: /sn:0 {0}(244,224)(244,211)(#:281,211)(#:281,192){1} wire w2; //: /sn:0 {0}(85,181)(244,181){1} //: enddecls //: GROUND g4 (w5) @(339,213) /sn:0 /w:[ 0 ] //: DIP g8 (w3) @(184,160) /sn:0 /w:[ 0 ] /st:66 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(bit widths)" //: /line:"" //: /line:"To change the bit size of one or more wires, first enter the desired bit size in the" //: /line:"bit size selector . Next, choose the tool, and click on each wire" //: /line:"to be changed to that size. Try changing the 8-bit wires in the circuit below to 16-bit wires." //: /line:"" //: /end _GGREG8 #(10, 10, 20) g1 (.Q(w1), .D(w6), .EN(w5), .CLR(w7), .CK(w2)); //: @(281,181) /sn:0 /w:[ 1 0 1 0 1 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGCLOCK_P100_0_50 g6 (.Z(w2)); //: @(72,181) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g7 (w8) @(271,256) /sn:0 /w:[ 0 ] //: VDD g5 (w7) @(346,158) /sn:0 /w:[ 1 ] _GGADD8 #(68, 70, 62, 64) g0 (.A(w3), .B(w1), .S(w6), .CI(w8), .CO(w4)); //: @(228,240) /sn:0 /w:[ 1 0 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(cutting)" //: /line:"" //: /line:"To cut a wire, select the tool and click on a wire at the point you wish to cut. Try" //: /line:"using the wire cutter tool to cut some of the wires in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential2.v000644 001751 001751 00000007536 11135014350 022324 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:190,196)(190,222){1} reg w4; //: /sn:0 {0}(245,281)(256,281)(256,269)(266,269){1} supply0 w3; //: /sn:0 {0}(243,246)(243,236)(230,236){1} supply0 w0; //: /sn:0 {0}(245,291)(268,291)(268,306){1} wire [7:0] w2; //: /sn:0 {0}(#:206,276)(206,251){1} wire ck; //: {0}(50:169,286)(104,286){1} wire [7:0] reg_out; //: {0}(#:206,297)(206,327)(263,327){1} //: {2}(267,327)(323,327)(-70:323,200)(222,200)(222,222){3} //: {4}(265,329)(265,342){5} wire w9; //: /sn:0 {0}(182,236)(172,236){1} //: enddecls //: joint g8 (reg_out) @(265, 327) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(268,312) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(stepped simulation)" //: /line:"" //: /line:"Start the simulator by pressing the \" Simulate\" tab just as with a combinational circuit. Next, set probes" //: /line:"on the \"ck\" and \"reg_out\" signals by right clicking and selecting Add/Delete probe. Now advance" //: /line:"the simulator by a several \"clock steps\" by pressing the button or by pressing the Tab key. Notice that" //: /line:"the \"reg_out\" single show an unknown value of \"x\". In order to reset it and start the counter you," //: /line:"must first set the \"reset\" switch to \"off\", advance the simulator by a clock step, then return" //: /line:"the \"reset\" switch to the \"on\" position." //: /end //: comment g3 @(533,149) /sn:0 /anc:1 //: /line:"Hint: In addition to using the scroll bar" //: /line:"on the logic analyzer, you can click and" //: /line:"drag in the main window to fine tune the" //: /line:"the position of the traces." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(206,286) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: DIP g6 (w7) @(190,186) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(243,252) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(265,349) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(206,238) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(91,286) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (w4) @(284,269) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/verilog.v000644 001751 001751 00000006322 11135014272 021532 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "texver_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"The TkGate simulator is based on the Verilog hardware description language. As such, any" //: /line:"modules you design using the graphical editor are translated into Verilog before being simulated." //: /line:"You can also write modules directly in Verilog. Note that this chapter is not designed to teach" //: /line:"Verilog, but rather to teach how to include Verilog modules in TkGate." //: /end //: comment g0 @(145,107) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(55, 80) /bd:[ Li0>d(64/80) Li1>c(48/80) Li2>b(32/80) Li3>a(16/80) Ro0 and set the type to HDL." //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"1) Right click on the module below and select Open." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g5 (w4) @(246,131) /sn:0 /w:[ 1 ] /type:0 foo g0 (.a(w5), .b(w6), .c(w7), .d(w8), .z(w4)); //: @(164, 113) /sz:(55, 80) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>1 Ro0<0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/notes.v000644 001751 001751 00000002474 10012327623 021217 0ustar00hansenhansen000000 000000 //: version "2.0" //: property title = "notes.v" module main; //: root_module //: enddecls //: comment g1 /dolink:1 /link:"@T/welcome_tut.v" @(611,27) /sn:0 //: /line:"Return to welcome." //: /end //: comment g0 /dolink:0 /link:"" @(42,57) /sn:0 //: /line:"* Make sure interface in library matches interfaces used in circuit." //: /line:"* Add HDL module type." //: /line:"* HTML tags in comments instead of all-or-nothing hyperlink." //: /line:"* How about a simulator selection dialog box with options for switches to include, etc." //: /line:"* Bitmap symbol editor for libraries" //: /line:"* HDL modules" //: /line:"* Current module's interface shown in lower left box." //: /line:"" //: /line:"BUGS:" //: /line:"* Landscape printing with A4 paper." //: /line:"* Lack of editing on edit interfaces screen." //: /line:"* Mysterious double modules on interface screen in welcome_tut.v" //: /line:"* Ctl-D duplicate a gate, then double click. prop box doesn't open." //: /line:"" //: /line:"TO DO:" //: /line:"" //: /line:"* Finish module interface generator" //: /line:"* Convert port box to use SpreadSheet" //: /line:"* Verilog Modules" //: /line:"* Custom Module Symbols" //: /line:"* Dialog box images" //: /line:"* Japanese messages.ja" //: /line:"" //: /end endmodule tkgate-2.0-b10/locale/en/tutorials/glossary.v000644 001751 001751 00000002645 10207530263 021734 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module //: enddecls //: frame g15 @(600,25) /sn:0 /wi:213 /ht:149 /tx:"Tutorials" //: comment g14 @(629,42) /sn:0 //: /line:"TkGate Introduction
" //: /line:"Creating a Circuit
" //: /line:"Basic Editing Modes
" //: /line:"Group Editing Features
" //: /line:"Editing Wires
" //: /line:"Using Modules
" //: /line:"Combinational Simulation
" //: /line:"Sequential Simulation" //: /end //: comment g0 @(21,26) /sn:0 //: /line:"

Glossary

" //: /line:"" //: /line:"epoch: The smallest unit of time understood by the simulator." //: /line:"" //: /line:"Verilog format constant: The first number indicates the bit width, the" //: /line:"letter indicates the radix, and the last number the value. For example, the \"1\"" //: /line:"in \"1'b0\" indicates that this is a 1-bit value, the \"b\" indicates the value is" //: /line:"given in binary, and the \"0\" indicates the value of the signal." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/tutorials/combinational2.v000644 001751 001751 00000006767 11135014314 022776 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:153,316)(167,316){1} //: {2}(171,316)(189,316){3} //: {4}(193,316)(241,316){5} //: {6}(191,314)(191,253)(236,253){7} //: {8}(169,314)(169,304){9} reg A; //: {0}(236,248)(204,248){1} //: {2}(202,246)(-86:202,228)(172,228){3} //: {4}(170,226)(170,215){5} //: {6}(168,228)(155,228){7} //: {8}(202,250)(202,311)(241,311){9} reg Cin; //: {0}(271,213)(291,213){1} //: {2}(293,211)(293,202){3} //: {4}(41:293,215)(293,244){5} //: {6}(295,246)(333,246){7} //: {8}(293,248)(293,272){9} wire w6; //: /sn:0 {0}(334,314)(262,314){1} wire w0; //: /sn:0 {0}(334,309)(291,309)(291,293){1} wire w1; //: /sn:0 {0}(333,251)(290,251){1} //: {2}(286,251)(257,251){3} //: {4}(288,253)(288,272){5} wire C; //: {0}(-21:403,221)(403,312)(355,312){1} wire S; //: {0}(354,249)(-39:373,249)(373,221){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(345,312) /sn:0 /w:[ 0 0 1 ] _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(247,251) /sn:0 /w:[ 0 7 3 ] //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(starting the simulator)" //: /line:"" //: /line:"Press the \" Simulate\" tab above the main canvas to enter simulation mode. When you first enter simulation" //: /line:"mode, the simulator will be paused as indicated by the depressed button on the simulator tool bar. Press" //: /line:"the button to begin simulation. Now try clicking on the switches to change their state and observe how the" //: /line:"LEDs change. When you are done, stop the simulator by pressing and go on to the next page." //: /end //: SWITCH g3 (Cin) @(254,213) /sn:0 /w:[ 0 ] /st:1 _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(252,314) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(136,316) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(288, 251) /w:[ 1 -1 2 4 ] //: LED g28 (A) @(170,208) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (Cin) @(293, 246) /w:[ 6 5 -1 8 ] //: joint g27 (Cin) @(293, 213) /w:[ -1 2 1 4 ] //: joint g6 (B) @(191, 316) /w:[ 4 6 3 -1 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(291,283) /sn:0 /R:3 /w:[ 5 9 1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(344,249) /sn:0 /w:[ 7 0 0 ] //: joint g31 (A) @(170, 228) /w:[ 3 4 6 -1 ] //: LED g29 (B) @(169,297) /sn:0 /w:[ 9 ] /type:0 //: LED g25 (C) @(403,214) /sn:0 /w:[ 0 ] /type:0 //: joint g5 (A) @(202, 248) /w:[ 1 2 -1 8 ] //: LED g26 (Cin) @(293,195) /sn:0 /w:[ 3 ] /type:0 //: SWITCH g0 (A) @(138,228) /sn:0 /w:[ 7 ] /st:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g18 (S) @(373,214) /sn:0 /w:[ 1 ] /type:0 //: joint g30 (B) @(169, 316) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/definition.txt000644 001751 001751 00000000000 10222160062 022543 0ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/tutorials/interface.txt000644 001751 001751 00000002275 10472227451 022410 0ustar00hansenhansen000000 000000 Creating and Editing Module Interfaces 1) Select the "Interface" tab in the main window to start the interface editor. 2) Double-click on module "bar" in module list to edit its interface. 3) Double-click on a port name or port property to change it, any changes will be immediately reflected in the interface example. 4) Double-click on the blank line below the last port in the port list to add a new port. 5) You can also add a new port by right-clicking on the edge of the interface example and then selecting one of the "Add..." options. 6) Change the size of the interface by selecting and dragging the edge or corner of the box. 7) Move the position of a port by selecting and dragging it. Autogeneration of Interfaces 1) Double-clock on the module "foo" in the module list to bring it up in the inteface editor. It should have a blank interface with no ports. 2) To automatically generate an interface, click on the "Auto Generate" button, then select "OK". The generate ports on the interface will be determined from the ports used in the module definition. Return to Edit Mode Click on the "Edit" tab in the main window to switch to the definition for the inteface you have been editing. tkgate-2.0-b10/locale/en/tutorials/moddef_tut.v000644 001751 001751 00000001377 10472230574 022232 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "module_tut.v" //: /netlistBegin main module main; //: root_module //: enddecls //: comment g0 @(23,20) /sn:0 //: /line:"

Creating a Module Definition

" //: /line:"" //: /line:"1) Press on the tool bar." //: /line:"" //: /line:"2) Enter the name of the new module." //: /line:"" //: /line:"3) Select the type of module (Netlist or HDL)" //: /line:"" //: /line:"4) Click \"OK\" to create the module." //: /line:"" //: /line:"5) Edit it by double clicking on it in the module list." //: /line:"" //: /line:"Click here to return to the main module tutorial." //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/tutorials/welcome.v000644 001751 001751 00000061602 11150143335 021520 0ustar00hansenhansen000000 000000 //: version "2.0-b7" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: property timingViolationMode = 2 //: property initTime = "0 ns" `timescale 1ns/1ns //: /symbolBegin: 688896144 //: /iconBegin normal 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x92, 0x02, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x40, 0x94, 0x04, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x71, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x81, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x1f, 0x01, 0x71, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x01, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01," //: /data " 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x71, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x81, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x81, 0x22, 0x08, 0x00, 0x00, 0x00, 0x10, 0x01, 0x71, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x10, 0x01, 0x01, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x1f, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x11, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x00, 0x01, 0x09, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01," //: /data " 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0x01, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x04, 0x01, 0x01, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x04, 0x01, 0x01, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x0e, 0x01," //: /data " 0x81, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x04, 0x01, 0x81, 0x28, 0x25, 0x09, 0xa2, 0x94, 0x24, 0x01," //: /data " 0x81, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /iconBegin select 2990 3 3 //: /data "#define bitmap_width 57" //: /data "#define bitmap_height 58" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff," //: /data " 0xff, 0xff, 0xff, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x02," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x80, 0x92, 0x02, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xc0, 0x97, 0x05, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94," //: /data " 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x40, 0x94, 0x04, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x73, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x0b, 0x14, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x3e, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x83, 0x22, 0xf8, 0xff," //: /data " 0xff, 0xff, 0x9f, 0x01, 0x73, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x03, 0x00, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01," //: /data " 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x22, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x73, 0x1e, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x83, 0x22, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x83, 0x22, 0x08, 0x00, 0x00, 0x00, 0x90, 0x01, 0x73, 0x1e, 0x08, 0x00," //: /data " 0x00, 0x00, 0x90, 0x01, 0x03, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x9f, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x13, 0x00, 0x00, 0x00," //: /data " 0x0c, 0x00, 0x80, 0x01, 0x0b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x80, 0x01," //: /data " 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01," //: /data " 0x03, 0x02, 0x00, 0x01, 0x1e, 0x00, 0x84, 0x01, 0x03, 0x05, 0x00, 0x01," //: /data " 0x22, 0x00, 0x84, 0x01, 0x03, 0xc5, 0xa4, 0x03, 0x22, 0x93, 0x8e, 0x01," //: /data " 0x83, 0x2f, 0x25, 0x01, 0x9e, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x01," //: /data " 0xa2, 0x94, 0x84, 0x01, 0x83, 0x28, 0x25, 0x09, 0xa2, 0x94, 0xa4, 0x01," //: /data " 0x83, 0xc8, 0x38, 0x06, 0x1e, 0xe3, 0x98, 0x01, 0x03, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01};" //: /iconEnd //: /port input SA[1:0] @(2, 16) /r:2 //: /port input AIN[7:0] @(31, 2) /r:1 //: /port output AOUT[7:0] @(19, 61) /r:3 //: /port input SB[1:0] @(2, 31) /r:2 //: /port output BOUT[7:0] @(46, 61) /r:3 //: /port input ck @(2, 46) /r:2 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg b; //: {0}(41:73,134)(107,134){1} //: {2}(109,132)(109,84)(127,84){3} //: {4}(109,136)(109,160)(139,160){5} supply1 w7; //: /sn:0 {0}(456,31)(456,18){1} reg [7:0] w19; //: /sn:0 {0}(#:703,66)(703,39){1} reg w0; //: /sn:0 {0}(357,39)(429,39){1} //: {2}(433,39)(442,39){3} //: {4}(431,37)(431,29){5} //: {6}(431,41)(431,141)(481,141){7} reg [1:0] sa; //: /sn:0 {0}(#:136,463)(103,463)(103,428)(90,428){1} reg w28; //: /sn:0 {0}(69,268)(118,268){1} reg w20; //: /sn:0 {0}(661,137)(624,137){1} reg w1; //: /sn:0 {0}(357,87)(392,87){1} //: {2}(396,87)(442,87){3} //: {4}(394,85)(394,78){5} //: {6}(394,89)(394,140)(409,140){7} reg [1:0] sb; //: /sn:0 {0}(#:136,478)(90,478){1} reg [7:0] w25; //: /sn:0 {0}(#:90,208)(131,208)(131,252){1} supply0 w18; //: /sn:0 {0}(741,206)(741,188)(723,188){1} reg ci; //: {0}(12:74,33)(177,33)(177,85){1} //: {2}(179,87)(202,87){3} //: {4}(177,89)(177,116){5} supply0 w11; //: /sn:0 {0}(759,102)(759,80)(743,80){1} supply0 w2; //: /sn:0 {0}(495,150)(495,166)(458,166){1} //: {2}(454,166)(423,166)(423,149){3} //: {4}(456,168)(456,177){5} supply1 w10; //: /sn:0 {0}(723,178)(737,178)(737,160){1} reg a; //: {0}(30:73,79)(115,79){1} //: {2}(119,79)(127,79){3} //: {4}(117,81)(117,155)(139,155){5} supply0 [7:0] w9; //: /sn:0 {0}(#:650,102)(650,92)(674,92)(674,121){1} reg [1:0] w26; //: /sn:0 {0}(#:90,331)(111,331)(111,368)(120,368){1} wire [7:0] w14; //: /sn:0 {0}(#:153,508)(153,545)(248,545)(248,237)(215,237){1} //: {2}(213,235)(213,218){3} //: {4}(211,237)(151,237)(151,252){5} wire w4; //: /sn:0 {0}(205,158)(160,158){1} wire w3; //: /sn:0 {0}(205,153)(175,153)(175,137){1} wire w24; //: /sn:0 {0}(695,80)(685,80){1} wire co; //: {0}(245,146)(-68:245,156)(226,156){1} wire w8; //: /sn:0 {0}(202,82)(174,82){1} //: {2}(170,82)(148,82){3} //: {4}(172,84)(172,116){5} wire [7:0] w30; //: /sn:0 {0}(#:180,508)(180,520)(228,520)(228,310)(215,310){1} //: {2}(213,308)(213,295){3} //: {4}(211,310)(188,310)(188,339){5} wire [7:0] w22; //: /sn:0 {0}(#:694,121)(694,107)(719,107)(719,95){1} wire clk; //: {0}(20:593,183)(647,183){1} wire [7:0] w12; //: /sn:0 {0}(#:165,449)(165,406){1} wire [7:0] w27; //: /sn:0 {0}(#:684,150)(684,173){1} wire s; //: {0}(246,97)(39:246,85)(223,85){1} wire w13; //: /sn:0 {0}(423,132)(423,113)(454,113){1} //: {2}(458,113)(493,113){3} //: {4}(495,111)(495,101){5} //: {6}(495,115)(495,133){7} //: {8}(456,111)(456,96){9} wire w5; //: /sn:0 {0}(456,48)(456,79){1} wire w33; //: /sn:0 {0}(136,493)(86,493)(86,529)(59,529){1} wire [7:0] reg_out; //: {0}(#:684,194)(50:684,230)(729,230){1} //: {2}(-24:733,230)(783,230)(783,55)(735,55)(735,66){3} //: {4}(731,232)(731,249){5} wire [7:0] w29; //: /sn:0 {0}(#:141,339)(141,281){1} //: enddecls //: joint g61 (reg_out) @(731, 230) /w:[ 2 -1 1 4 ] //: VDD g8 (w7) @(467,18) /sn:0 /w:[ 1 ] _GGNMOS #(2, 1) g4 (.Z(w13), .S(w2), .G(w0)); //: @(489,141) /sn:0 /w:[ 7 0 7 ] //: LED g55 (w0) @(431,22) /sn:0 /w:[ 5 ] /type:0 _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co)); //: @(216,156) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g13 (w1) @(394, 87) /w:[ 2 4 1 6 ] //: SWITCH g3 (w0) @(340,39) /sn:0 /w:[ 0 ] /st:0 /dn:1 _GGCLOCK_P200_0_50 g51 (.Z(w33)); //: @(46,529) /sn:0 /w:[ 1 ] /omega:200 /phi:0 /duty:50 REGS g2 (.SA(sa), .AIN(w12), .AOUT(w14), .SB(sb), .BOUT(w30), .ck(w33)); //: @(165, 479) /symbol:688896144 /sn:0 /w:[ 0 0 0 0 0 0 ] //: LED g59 (w30) @(213,288) /sn:0 /w:[ 3 ] /type:2 _GGCLOCK_P120_0_50 g1 (.Z(clk)); //: @(580,183) /sn:0 /w:[ 0 ] /omega:120 /phi:0 /duty:50 //: joint g11 (w2) @(456, 166) /w:[ 1 -1 2 4 ] //: joint g16 (w30) @(213, 310) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4)); //: @(150,158) /sn:0 /w:[ 5 5 1 ] /eb:0 //: GROUND g10 (w2) @(456,183) /sn:0 /w:[ 5 ] //: joint g32 (w8) @(172, 82) /w:[ 1 -1 2 4 ] //: SWITCH g27 (ci) @(57,33) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g19 (w0) @(431, 39) /w:[ 2 4 1 6 ] _GGNMOS #(2, 1) g6 (.Z(w13), .S(w2), .G(w1)); //: @(417,140) /sn:0 /w:[ 0 3 7 ] //: DIP sa (sa) @(52,428) /sn:0 /R:1 /w:[ 1 ] /st:0 /dn:1 //: joint g57 (w13) @(495, 113) /w:[ -1 4 3 6 ] //: joint g9 (w13) @(456, 113) /w:[ 2 8 1 -1 ] _GGPMOS #(2, 1) g7 (.Z(w5), .S(w7), .G(w0)); //: @(450,39) /sn:0 /w:[ 0 0 3 ] _GGMUX2x8 #(8, 8) g53 (.I0(w25), .I1(w14), .S(w28), .Z(w29)); //: @(141,268) /sn:0 /w:[ 1 5 1 1 ] /ss:0 /do:0 _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3)); //: @(175,127) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g15 (s) @(246,104) /sn:0 /R:2 /w:[ 0 ] /type:0 //: DIP sb (sb) @(52,478) /sn:0 /R:1 /w:[ 1 ] /st:1 /dn:1 //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] ALU alu (.B(w30), .A(w29), .F(w26), .Z(w12)); //: @(121, 340) /sz:(89, 65) /p:[ Ti0>5 Ti1>0 Li0>1 Bo0<1 ] //: DIP func (w26) @(52,331) /sn:0 /R:1 /w:[ 0 ] /st:0 /dn:1 //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: joint g29 (a) @(117, 79) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a) @(56,79) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 /dn:1 //: DIP data_in (w25) @(52,208) /sn:0 /R:1 /w:[ 0 ] /st:11 /dn:1 //: LED g56 (w13) @(495,94) /sn:0 /w:[ 5 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,87) /sn:0 /w:[ 9 1 3 ] //: LED g14 (co) @(245,139) /sn:0 /w:[ 0 ] /type:0 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 /dn:1 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,85) /sn:0 /w:[ 0 3 1 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,82) /sn:0 /w:[ 3 3 3 ] /eb:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: LED g54 (w1) @(394,71) /sn:0 /w:[ 5 ] /type:0 //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: SWITCH g26 (b) @(56,134) /sn:0 /w:[ 0 ] /st:1 /dn:1 //: comment g0 @(280,236) /anc:1 //: /line:"

Welcome to TkGate

" //: /line:"[Beta Release]" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to " //: /line:" [released ]" //: /line:"" //: /line:"Click on a link below to start using tkgate!" //: /line:"" //: /line:" * Go to the tutorial" //: /line:"" //: /line:" * Go to the example circuits" //: /line:"" //: /line:" * Edit a new circuit" //: /line:"" //: /line:" * Open the documentation " //: /end //: SWITCH data_select (w28) @(52,268) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: SWITCH g12 (w1) @(340,87) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: joint g33 (ci) @(177, 87) /w:[ 2 1 -1 4 ] //: joint g30 (b) @(109, 134) /w:[ -1 2 1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>A[7:0](21/89) Ti1>B[7:0](67/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z = 1'b0; initial #100 if (0 == 0) forever begin Z = 1'b1; #100; Z = 1'b0; #100; end else forever begin Z = 1'b0; #100; Z = 1'b1; #100; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/index.v000644 001751 001751 00000003703 11135014211 021163 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(433,291) /sn:0 /R:14 //: /line:"Go back to the TkGate main page." //: /end //: comment g0 @(434,49) /sn:0 /anc:1 //: /line:"" //: /end //: comment g18 @(10,10) /sn:0 /anc:1 //: /line:"

Tutorial Chapters:

" //: /line:"" //: /line:"

1. Creating a Circuit

- Get started by creating a simple circuit." //: /line:"" //: /line:"

2. Editing Gates

- The basics of editing gates." //: /line:"" //: /line:"

3. Editing Wires

- The basics of editing wires." //: /line:"" //: /line:"

4. Group Editing Features

- Operate on groups of gates." //: /line:"" //: /line:"

5. Using Modules

- Using modules in your circuit." //: /line:"" //: /line:"

6. Advanced Editing Techniques

- Learn advanced editing tricks." //: /line:"" //: /line:"

7. Combinational Simulation

- Simulate a circuit with" //: /line:" combinational logic." //: /line:"" //: /line:"

8. Sequential Simulation

- Simulate a circuit with sequential logic." //: /line:"" //: /line:"

9. Textual Verilog

- Create modules with textual Verilog descriptions." //: /line:"" //: /line:"

10. Customizing TkGate

- Customize TkGate to suit your tastes." //: /line:"" //: /line:"" //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/tutorials/create.v000644 001751 001751 00000017343 11135014214 021327 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg w3; //: /sn:0 {0}(219,137)(154,137){1} reg w9; //: /sn:0 {0}(314,237)(213,237){1} //: {2}(211,235)(211,142)(219,142){3} //: {4}(209,237)(154,237){5} wire w8; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} wire w10; //: /sn:0 {0}(335,235)(345,235){1} //: enddecls //: comment g8 @(313,208) //: /line:"OR gate" //: /end //: joint g13 (w9) @(211, 237) /w:[ 1 2 4 -1 ] //: comment g1 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w3), .I1(w9), .Z(w8)); //: @(230,140) /sn:0 /w:[ 0 3 1 ] //: comment g6 @(115,104) //: /line:"Switches" //: /end //: comment g7 @(208,112) //: /line:"AND gate" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"In this chapter, we will walk through the steps of creating the simple circuit shown below." //: /end //: SWITCH g14 (w3) @(137,137) /sn:0 /w:[ 1 ] /st:0 _GGOR2 #(6) g0 (.I0(w8), .I1(w9), .Z(w10)); //: @(325,235) /sn:0 /w:[ 0 0 0 ] //: SWITCH g12 (w9) @(137,237) /sn:0 /w:[ 5 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(182,237)(182,237)(314,237){1} reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1} wire w7; //: /sn:0 {0}(335,235)(345,235){1} wire w0; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} //: enddecls _GGOR2 #(6) g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(325,235) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g3 (.I0(w2), .I1(w0), .Z(w5)); //: @(230,140) /sn:0 /w:[ 0 1 1 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /w:[ 0 ] /st:0 //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(537,46) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now make the final connection. Grab the lower input terminal of the AND gate" //: /line:"and drag it down near the wire between the lower switch and the OR gate. Release" //: /line:"the wire to create a joint." //: /line:"" //: /end //: comment g7 @(537,126) /sn:0 /anc:1 //: /line:"Hint: Joints are formed any" //: /line:"time the soldering iron is" //: /line:"active and you release the" //: /line:"wire in the middle of another" //: /line:"wire." //: /end //: SWITCH g5 (w2) @(137,137) /sn:0 /w:[ 1 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w2; //: /sn:0 {0}(240,140)(255,140){1} //: enddecls _GGAND2 #(6) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(230,140) /sn:0 /w:[ 1 1 0 ] //: frame g1 @(283,202) /sn:0 /wi:78 /ht:46 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now create an OR gate. Right click in the dashed line box then select" //: /line:"Make → Gate → OR from the popup menu." //: /end //: comment g0 @(532,85) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"o\" to create an OR gate." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(169,237){1} reg w2; //: /sn:0 {0}(154,137)(169,137){1} wire w7; //: /sn:0 {0}(240,140)(255,140){1} wire w4; //: /sn:0 {0}(204,137)(219,137){1} wire w3; //: /sn:0 {0}(335,235)(350,235){1} wire w0; //: /sn:0 {0}(299,232)(314,232){1} wire w1; //: /sn:0 {0}(299,237)(314,237){1} wire w5; //: /sn:0 {0}(204,142)(219,142){1} //: enddecls //: SWITCH g4 (w2) @(137,137) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGAND2 #(6) g3 (.I0(w4), .I1(w5), .Z(w7)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w1), .Z(w3)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(578,122) /sn:0 /anc:1 //: /line:"Hint: The soldering iron cursor will" //: /line:"show you when you have selected" //: /line:"a connectable wire end." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Finally, connect the wires. Begin by grabbing the end of the wire leading from one of the" //: /line:"switches with the left mouse button and drag it to the upper input terminal of the AND gate." //: /end //: comment g0 @(579,61) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(531,86) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"a\" to create an AND gate." //: /end //: frame g1 @(208,124) /sn:0 /wi:76 /ht:43 /tx:"" //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Start by creating an AND gate. Right click in the dashed line box then select" //: /line:"Make → Gate → AND from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(335,235)(350,235){1} wire w4; //: /sn:0 {0}(299,232)(314,232){1} wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w3; //: /sn:0 {0}(240,140)(255,140){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(299,237)(314,237){1} //: enddecls _GGOR2 #(6) g4 (.I0(w4), .I1(w5), .Z(w7)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g8 @(109,215) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" _GGAND2 #(6) g3 (.I0(w0), .I1(w1), .Z(w3)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g1 @(109,121) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Next create two switches. Right click in each of the two dashed line box then" //: /line:"select Make → I/O → Switch from the popup menu." //: /end //: comment g0 @(532,86) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"s\" to create a switch." //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/wire2.v000644 001751 001751 00000020645 10472740235 021127 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "edwire_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin main module main; //: root_module wire w32; //: /sn:0 {0}(631,288)(641,288){1} wire w6; //: /sn:0 {0}(483,145)(523,145)(523,128)(548,128)(548,140)(573,140)(573,190)(499,190)(499,160){1} wire w7; //: /sn:0 {0}(477,423)(487,423){1} wire w46; //: /sn:0 {0}(731,563)(688,563)(688,554){1} //: {2}(690,552)(704,552)(704,514)(729,514){3} //: {4}(686,552)(653,552){5} wire w16; //: /sn:0 {0}(550,96)(560,96){1} wire w14; //: /sn:0 {0}(529,93)(519,93)(519,74)(538,74)(538,41)(485,41){1} wire w19; //: /sn:0 {0}(611,425)(621,425){1} wire w15; //: /sn:0 {0}(519,98)(529,98){1} wire w4; //: /sn:0 {0}(452,147)(462,147){1} wire w38; //: /sn:0 {0}(754,387)(764,387){1} wire w0; //: /sn:0 {0}(452,142)(462,142){1} wire w3; //: /sn:0 {0}(482,280)(523,280){1} //: {2}(527,280)(580,280){3} //: {4}(525,278)(525,234)(555,234){5} wire w37; //: /sn:0 {0}(728,387)(738,387){1} wire w34; //: /sn:0 {0}(751,356)(761,356){1} wire w43; //: /sn:0 {0}(622,549)(632,549){1} wire w21; //: /sn:0 {0}(611,463)(621,463){1} wire w31; //: /sn:0 {0}(631,283)(641,283){1} wire w28; //: /sn:0 {0}(662,286)(703,286){1} //: {2}(707,286)(760,286){3} //: {4}(705,284)(705,240)(735,240){5} wire w36; //: /sn:0 {0}(639,358)(649,358){1} wire w41; //: /sn:0 {0}(499,551)(509,551){1} wire w23; //: /sn:0 {0}(544,383)(554,383){1} wire w24; //: /sn:0 {0}(554,355)(531,355){1} //: {2}(529,353)(529,324)(555,324){3} //: {4}(527,355)(489,355){5} wire w20; //: /sn:0 {0}(595,463)(583,463)(583,425)(595,425){1} wire w1; //: /sn:0 {0}(451,277)(461,277){1} wire w25; //: /sn:0 {0}(571,324)(581,324){1} wire w35; //: /sn:0 {0}(639,353)(649,353){1} wire w8; //: /sn:0 {0}(576,232)(586,232){1} wire w18; //: /sn:0 {0}(530,472)(540,472){1} wire w40; //: /sn:0 {0}(561,470)(571,470){1} wire w30; //: /sn:0 {0}(756,238)(766,238){1} wire w22; //: /sn:0 {0}(458,357)(468,357){1} wire w17; //: /sn:0 {0}(540,467)(524,467)(524,426)(508,426){1} wire w44; //: /sn:0 {0}(622,554)(632,554){1} wire w12; //: /sn:0 {0}(454,43)(464,43){1} wire w11; //: /sn:0 {0}(454,38)(464,38){1} wire w2; //: /sn:0 {0}(451,282)(461,282){1} wire w10; //: /sn:0 {0}(458,352)(468,352){1} wire w13; //: /sn:0 {0}(499,546)(509,546){1} wire w27; //: /sn:0 {0}(570,383)(580,383){1} wire w48; //: /sn:0 {0}(745,514)(755,514){1} wire w33; //: /sn:0 {0}(735,356)(712,356){1} //: {2}(710,354)(710,325)(736,325){3} //: {4}(708,356)(670,356){5} wire w5; //: /sn:0 {0}(545,229)(555,229){1} wire w47; //: /sn:0 {0}(747,563)(757,563){1} wire w29; //: /sn:0 {0}(725,235)(735,235){1} wire w42; //: /sn:0 {0}(530,549)(548,549)(548,513){1} wire w9; //: /sn:0 {0}(477,428)(487,428){1} wire w39; //: /sn:0 {0}(752,325)(762,325){1} wire w26; //: /sn:0 {0}(570,355)(580,355){1} //: enddecls //: comment g4 @(16,548) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(473,145) /sn:0 /w:[ 1 1 0 ] //: frame g51 @(449,500) /sn:0 /anc:1 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(710, 356) /w:[ 1 2 4 -1 ] //: frame g34 @(444,312) /sn:0 /anc:1 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(525, 280) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(551,470) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(566,232) /sn:0 /w:[ 1 5 0 ] //: comment g1 @(549,50) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(540,96) /sn:0 /w:[ 0 1 0 ] //: joint g50 (w46) @(688, 552) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(560,355) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(475,41) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(746,238) /sn:0 /w:[ 1 5 0 ] //: joint g27 (w24) @(529, 355) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(601,425) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(660,356) /sn:0 /w:[ 1 1 5 ] //: comment g9 @(23,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(705, 286) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(520,549) /sn:0 /w:[ 1 1 0 ] _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(737,563) /sn:0 /w:[ 0 0 ] //: frame g43 @(624,217) /sn:0 /anc:1 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(560,383) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(479,355) /sn:0 /w:[ 1 1 5 ] //: frame g52 @(604,502) /sn:0 /anc:1 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(444,216) /sn:0 /anc:1 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(498,426) /sn:0 /w:[ 1 1 1 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(643,552) /sn:0 /w:[ 1 1 5 ] _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(744,387) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(741,356) /sn:0 /w:[ 0 0 ] //: comment g24 @(492,437) /sn:0 /anc:1 //: /line:"--->" //: /end //: frame g41 @(442,122) /sn:0 /anc:1 /wi:142 /ht:86 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(601,463) /sn:0 /w:[ 0 0 ] //: frame g40 @(441,25) /sn:0 /anc:1 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(447,411) /sn:0 /anc:1 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(742,325) /sn:0 /w:[ 3 0 ] //: frame g35 @(625,313) /sn:0 /anc:1 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(561,324) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(472,280) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(652,286) /sn:0 /w:[ 1 1 0 ] //: comment g30 @(730,252) /sn:0 /anc:1 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(735,514) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/gates.v000644 001751 001751 00000035546 11135014223 021174 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

" //: /line:"" //: /line:"This chapter will introduce some of the basic circuit editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(144,69) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(256,171)(271,171){1} wire w3; //: /sn:0 {0}(256,166)(271,166){1} wire w0; //: /sn:0 {0}(102,172)(117,172){1} wire w1; //: /sn:0 {0}(102,177)(117,177){1} wire w2; //: /sn:0 {0}(138,175)(153,175){1} wire w5; //: /sn:0 {0}(292,169)(307,169){1} //: enddecls //: comment g4 @(247,195) /sn:0 /anc:1 //: /line:"Anchored Gate" //: /end _GGOR2 #(6) g3 (.I0(w3), .I1(w4), .Z(w5)); //: @(282,169) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Anchoring)" //: /line:"" //: /line:"You can prevent a gate from being accidentally moved by selecting it and pressing" //: /line:"the button to set an anchor. You can remove an anchor with the button." //: /line:"Gates which have been anchored (e.g., the OR gate below) can not be moved until" //: /line:"you remove the anchor. Try moving the gates below." //: /line:"" //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(128,175) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(587,112) /sn:0 /anc:1 //: /line:"Hint: An alternate way to add or" //: /line:"remove an anchor on a gate is to" //: /line:"right click and change the anchor" //: /line:"flag in the popup menu." //: /end //: comment g5 @(81,195) /sn:0 /anc:1 //: /line:"Unanchored Gate" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) /anc:1 //: /line:"

Editing Gates

(Repositioning)" //: /line:"" //: /line:"To move a gate, select it with the tool and drag it to a new location. Try" //: /line:"it on the sample circuit below." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(39,221)(54,221){1} wire w7; //: /sn:0 {0}(41,265)(56,265){1} wire w14; //: /sn:0 {0}(169,222)(154,222){1} wire w16; //: /sn:0 {0}(154,267)(169,267){1} wire w4; //: /sn:0 {0}(39,218)(54,218){1} wire w15; //: /sn:0 {0}(154,262)(169,262){1} wire w19; //: /sn:0 {0}(169,277)(154,277){1} wire w3; //: /sn:0 {0}(39,214)(54,214){1} wire w0; //: /sn:0 {0}(37,166)(52,166){1} wire w21; //: /sn:0 {0}(152,167)(167,167){1} wire w23; //: /sn:0 {0}(188,169)(203,169){1} wire w20; //: /sn:0 {0}(41,274)(56,274){1} wire w1; //: /sn:0 {0}(37,171)(52,171){1} wire w8; //: /sn:0 {0}(41,268)(56,268){1} wire w18; //: /sn:0 {0}(190,269)(205,269){1} wire w22; //: /sn:0 {0}(152,172)(167,172){1} wire w17; //: /sn:0 {0}(169,272)(154,272){1} wire w2; //: /sn:0 {0}(73,169)(88,169){1} wire w11; //: /sn:0 {0}(154,212)(169,212){1} wire w12; //: /sn:0 {0}(154,217)(169,217){1} wire w10; //: /sn:0 {0}(41,271)(56,271){1} wire w13; //: /sn:0 {0}(190,217)(205,217){1} wire w5; //: /sn:0 {0}(75,218)(90,218){1} wire w9; //: /sn:0 {0}(77,270)(92,270){1} //: enddecls //: comment g8 @(149,126) /sn:0 /anc:1 //: /line:"gates with" //: /line:"extender bars" //: /end _GGAND4 #(10) g4 (.I0(w7), .I1(w8), .I2(w10), .I3(w20), .Z(w9)); //: @(67,270) /sn:0 /w:[ 1 1 1 1 0 ] _GGAND3 #(8) g3 (.I0(w3), .I1(w4), .I2(w6), .Z(w5)); //: @(65,218) /sn:0 /w:[ 1 1 1 0 ] //: comment g2 @(11,13) /anc:1 //: /line:"

Editing Gates

(Adding Inputs)" //: /line:"" //: /line:"Some gates (e.g., AND gates) can have a variable number of inputs or outputs. To add inputs (or" //: /line:"outputs) to these gates, select the gate and press the button. Also, some gates may have multiple styles" //: /line:"for adding ports that can be selected through the gate properties box. Try adding inputs to the gates below," //: /line:"or create a new gate and add inputs to it." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(63,169) /sn:0 /w:[ 1 1 0 ] _GGAND4 #(10) g6 (.I0(w15), .I1(w16), .I2(w17), .I3(w19), .Z(w18)); //: @(180,269) /sn:0 /w:[ 1 1 0 0 0 ] /eb:1 _GGAND2 #(6) g9 (.I0(w21), .I1(w22), .Z(w23)); //: @(178,169) /sn:0 /w:[ 1 1 0 ] /eb:1 //: comment g7 @(26,127) /sn:0 /anc:1 //: /line:"gates without" //: /line:"extender bars" //: /end _GGAND3 #(8) g5 (.I0(w11), .I1(w12), .I2(w14), .Z(w13)); //: @(180,217) /sn:0 /w:[ 1 1 0 0 ] /eb:1 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: frame g3 @(298,213) /sn:0 /wi:167 /ht:69 /tx:"This is a frame" //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Comments and Frames)" //: /line:"" //: /line:"There are two special \"gates\" that you can use for annotating your circuit specification: comments and frames." //: /line:"Neither of these \"gates\" has any effect on the simulation results." //: /line:"" //: /line:"Comments are blocks of text such as those used to construct this tutorial. Comments are created by right clicking" //: /line:"and selecting Make → Comment from the popup menu. When you create a comment, the properties box will" //: /line:"appear immediately allowing you to enter the text of the comment. Comments can contain limited html tags including links" //: /line:"to other circuit files, or short cuts to specific gates in your circuit." //: /line:"" //: /line:"Frames are annotated boxes for organzing groups of related circuit elements that don't warrant creating a new module. Open" //: /line:"the properties box by double clicking on an edge to set the annotation string. Click and drag on a corner to resize." //: /line:"" //: /end //: comment g1 @(72,233) /sn:0 //: /line:"This is a comment with" //: /line:"some bold text in it." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(118,149)(133,149){1} wire w1; //: /sn:0 {0}(118,154)(133,154){1} wire w2; //: /sn:0 {0}(154,152)(169,152){1} //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Rotation)" //: /line:"" //: /line:"The orientation of a gate can be changed by selecting it and pressing the button" //: /line:"(or Tab key) to rotate it counter-clockwise and the button (or Shift-Tab key) to" //: /line:"rotate it clockwise. Try it on the AND gate below." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(144,152) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(567,92) /sn:0 /anc:1 //: /line:"Hint: You can also use the " //: /line:"button to set the default orientation" //: /line:"for newly created gates." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Deletion)" //: /line:"" //: /line:"To delete a gate, select it with the tool and press the Delete key. Try it on the sample circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Properties)" //: /line:"" //: /line:"You can also open the properties box of a gate by double clicking on it. Try" //: /line:"double clicking on some of the gates in the circuit below. Through the properties" //: /line:"box you can change the label of a gate and make the label visible or invisible" //: /line:"though the \"Hide Name\" property." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: comment g6 @(548,104) /sn:0 /anc:1 //: /line:"Hint: Many properties are gate-" //: /line:"specific. Try opening the property" //: /line:"boxes of different gate types to see" //: /line:"what proprties can be modified." //: /end _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND4 #(.Diz(1)) (I0, I1, I2, I3, Z); output Z; input I0, I1, I2, I3; reg Z; assign #Diz Z = ( I0 & I1 & I2 & I3 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; reg Z; assign #Diz Z = ( I0 & I1 & I2 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/advanced.v000644 001751 001751 00000063761 11135014251 021637 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Advanced Editing Techniques

" //: /line:"" //: /line:"In this chapter you will learn some additional techniques to be more efficient at editing circuits" //: /line:"in TkGate." //: /end //: comment g0 @(150,93) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Now try the same thing again, but this time drop the inverter input closer to the AND gate output" //: /line:"away from the joint. This time a new joint is automatically created." //: /line:"" //: /end _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(162,164)(202,164)(202,147)(227,147)(227,159)(252,159)(252,209)(178,209)(178,179){1} wire w4; //: /sn:0 {0}(131,166)(141,166){1} wire w0; //: /sn:0 {0}(131,161)(141,161){1} //: enddecls _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(152,164) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Loop Deletion)" //: /line:"" //: /line:"Grab the endpoint of the XOR output wire in the circuit below. Drag it up until it crosses the" //: /line:"horizontal segment next to the gate and release it. TkGate will automatically remove the loop." //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w46; //: /sn:0 {0}(421,254)(374,254)(374,196){1} //: {2}(376,194)(397,194)(397,127)(422,127){3} //: {4}(372,194)(339,194){5} wire w0; //: /sn:0 {0}(67,208)(82,208){1} wire w43; //: /sn:0 {0}(308,191)(318,191){1} wire w1; //: /sn:0 {0}(67,213)(82,213){1} wire w2; //: /sn:0 {0}(103,211)(130,211)(130,135){1} wire w44; //: /sn:0 {0}(308,196)(318,196){1} wire w48; //: /sn:0 {0}(438,127)(448,127){1} wire w47; //: /sn:0 {0}(437,254)(447,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(93,211) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) hari (.I0(w43), .I1(w44), .Z(w46)); //: @(329,194) /sn:0 /anc:1 /w:[ 1 1 5 ] /eb:0 //: joint g50 (w46) @(374, 194) /anc:1 /w:[ 2 -1 4 1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Rerouting)" //: /line:"" //: /line:"TkGate will automatically reroute wires that do not leave a gate or joint on the correct" //: /line:"direction. Try grabbing the wire indicated by the arrow in the two examples below and drag" //: /line:"them to the left. In the XOR gate example, two new wire segments are added. In the joint" //: /line:"example, one new segment is added, and the position on the joint is adjusted." //: /line:"" //: /end _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(427,254) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g0 @(405,147) /sn:0 //: /line:"⇐" //: /end //: comment g12 @(141,164) /sn:0 //: /line:"⇐" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(428,127) /sn:0 /anc:1 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(316,199)(316,214){1} wire w6; //: /sn:0 {0}(85,173)(100,173){1} wire w7; //: /sn:0 {0}(85,178)(100,178){1} wire w16; //: /sn:0 {0}(80,237)(95,237){1} wire w14; //: /sn:0 {0}(107,216)(122,216){1} wire w19; //: /sn:0 {0}(85,256)(100,256){1} wire w15; //: /sn:0 {0}(80,232)(95,232){1} wire w4; //: /sn:0 {0}(99,157)(114,157){1} wire w38; //: /sn:0 {0}(335,190)(335,205){1} wire w3; //: /sn:0 {0}(99,152)(114,152){1} wire w0; //: /sn:0 {0}(91,132)(106,132){1} wire w37; //: /sn:0 {0}(333,154)(333,169){1} wire w34; //: /sn:0 {0}(295,168)(295,183){1} wire w21; //: /sn:0 {0}(359,164)(359,179){1} wire w31; //: /sn:0 {0}(314,163)(314,178){1} wire w28; //: /sn:0 {0}(394,182)(394,197){1} wire w41; //: /sn:0 {0}(416,210)(416,225){1} wire w36; //: /sn:0 {0}(338,154)(338,169){1} wire w24; //: /sn:0 {0}(378,168)(378,183){1} wire w23; //: /sn:0 {0}(356,200)(356,215){1} wire w20; //: /sn:0 {0}(121,254)(136,254){1} wire w1; //: /sn:0 {0}(91,137)(106,137){1} wire w25; //: /sn:0 {0}(373,168)(373,183){1} wire w40; //: /sn:0 {0}(414,174)(414,189){1} wire w35; //: /sn:0 {0}(297,204)(297,219){1} wire w18; //: /sn:0 {0}(85,251)(100,251){1} wire w8; //: /sn:0 {0}(121,176)(136,176){1} wire w30; //: /sn:0 {0}(319,163)(319,178){1} wire w22; //: /sn:0 {0}(354,164)(354,179){1} wire w17; //: /sn:0 {0}(116,235)(131,235){1} wire w12; //: /sn:0 {0}(71,213)(86,213){1} wire w11; //: /sn:0 {0}(117,195)(132,195){1} wire w2; //: /sn:0 {0}(127,135)(142,135){1} wire w10; //: /sn:0 {0}(81,197)(96,197){1} wire w27; //: /sn:0 {0}(399,182)(399,197){1} wire w13; //: /sn:0 {0}(71,218)(86,218){1} wire w33; //: /sn:0 {0}(300,168)(300,183){1} wire w5; //: /sn:0 {0}(135,155)(150,155){1} wire w29; //: /sn:0 {0}(396,218)(396,233){1} wire w9; //: /sn:0 {0}(81,192)(96,192){1} wire w39; //: /sn:0 {0}(419,174)(419,189){1} wire w26; //: /sn:0 {0}(375,204)(375,219){1} //: enddecls _GGAND2 #(6) g8 (.I0(w21), .I1(w22), .Z(w23)); //: @(356,190) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g13 (.I0(w33), .I1(w34), .Z(w35)); //: @(297,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w9), .I1(w10), .Z(w11)); //: @(107,195) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g2 (.I0(w6), .I1(w7), .Z(w8)); //: @(111,176) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g1 (.I0(w3), .I1(w4), .Z(w5)); //: @(125,155) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g11 (.I0(w27), .I1(w28), .Z(w29)); //: @(396,208) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g10 (.I0(w24), .I1(w25), .Z(w26)); //: @(375,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g6 (.I0(w15), .I1(w16), .Z(w17)); //: @(106,235) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g7 (.I0(w18), .I1(w19), .Z(w20)); //: @(111,254) /sn:0 /w:[ 1 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gate Alignment)" //: /line:"" //: /line:"You can align a group of gates by selecting them and then pressing the to align them vertically," //: /line:"and to align them horizontally. Try it on the groups of gates below." //: /end _GGAND2 #(6) g15 (.I0(w39), .I1(w40), .Z(w41)); //: @(416,200) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g14 (.I0(w36), .I1(w37), .Z(w38)); //: @(335,180) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g5 (.I0(w12), .I1(w13), .Z(w14)); //: @(97,216) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(117,135) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g12 (.I0(w30), .I1(w31), .Z(w32)); //: @(316,189) /sn:0 /R:3 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(85,137)(95,137){1} wire w19; //: /sn:0 {0}(322,140)(332,140){1} wire w21; //: /sn:0 {0}(321,242)(331,242){1} wire w20; //: /sn:0 {0}(305,242)(288,242)(288,140)(306,140){1} wire w40; //: /sn:0 {0}(193,243)(203,243){1} wire w18; //: /sn:0 {0}(162,245)(172,245){1} wire w17; //: /sn:0 {0}(172,240)(153,240)(153,140)(116,140){1} wire w9; //: /sn:0 {0}(85,142)(95,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(183,243) /sn:0 /anc:1 /w:[ 0 1 0 ] /eb:0 //: comment g1 @(120,178) /sn:0 /anc:1 //: /line:"⇒" //: /end _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(312,140) /sn:0 /anc:1 /w:[ 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Wire Segments)" //: /line:"" //: /line:"Sometime there may not be a free end of two wires you want to connect. Right click on the" //: /line:"wire connected to the AND gate output at the position indicated by the arrow. Select the" //: /line:"Add Wire Segment option from the popup menu. You can now connect" //: /line:"the newly created wire to the buffer inputs." //: /line:"" //: /end _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(106,140) /sn:0 /anc:1 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(311,242) /sn:0 /anc:1 /w:[ 0 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Select the tool and drag the input of the inverter in the circuit below. Drag the input close" //: /line:"to the joint in the middle of the AND gate output and release it. The wire should attach itself to" //: /line:"the joint." //: /line:"" //: /end _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] wire w16; //: /sn:0 {0}(313,266)(323,266){1} wire w14; //: /sn:0 {0}(292,263)(226,263)(226,200)(245,200)(245,140)(178,140){1} wire w15; //: /sn:0 {0}(282,268)(292,268){1} wire w12; //: /sn:0 {0}(147,142)(157,142){1} wire w11; //: /sn:0 {0}(147,137)(157,137){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(303,266) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(168,140) /sn:0 /w:[ 1 1 1 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gravity)" //: /line:"" //: /line:"Click on the wire indicated by the arrow in the circuit below and drag it until it is nearly" //: /line:"alligned with the other vertical segment. When you release the wire, \"gravity\" will cause" //: /line:"the two vertical segments to snap together into a single segment." //: /line:"" //: /end //: comment g0 @(562,122) /sn:0 /anc:1 //: /line:"Hint: You can disable the automatic" //: /line:"cleanup features in wire editing by" //: /line:"holding the Alt key while moving wires." //: /end //: comment g12 @(252,158) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(325,245)(373,245){1} //: {2}(377,245)(468,245){3} //: {4}(375,243)(375,163)(436,163){5} wire w7; //: /sn:0 {0}(421,158)(436,158){1} wire w4; //: /sn:0 {0}(289,247)(304,247){1} wire w0; //: /sn:0 {0}(289,242)(304,242){1} wire w3; //: /sn:0 {0}(61,247)(108,247){1} //: {2}(112,247)(199,247){3} //: {4}(110,245)(110,161)(169,161){5} wire w1; //: /sn:0 {0}(30,244)(40,244){1} wire w8; //: /sn:0 {0}(190,159)(200,159){1} wire w2; //: /sn:0 {0}(30,249)(40,249){1} wire w10; //: /sn:0 {0}(457,161)(472,161){1} wire w5; //: /sn:0 {0}(159,156)(169,156){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g3 (w3) @(110, 247) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(180,159) /sn:0 /anc:1 /w:[ 1 5 0 ] /eb:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w4), .Z(w6)); //: @(315,245) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g11 @(363,264) /sn:0 /anc:1 //: /line:"OR Gate Circuit" //: /end //: comment g10 @(70,271) /sn:0 /anc:1 //: /line:"AND Gate Circuit" //: /end //: joint g6 (w6) @(375, 245) /w:[ 2 4 1 -1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Wire Cleanup)" //: /line:"" //: /line:"Select the tool and cut the wire at the position indicated by the arrow in the AND Gate" //: /line:"Circuit. TkGate will automatically remove the wire joint. Now cut the wire at the position indicated" //: /line:"by the arrow in the OR Gate Circuit. The free wire end is automatically deleted." //: /line:"" //: /end //: comment g7 @(413,213) /sn:0 /anc:1 //: /line:"⇓" //: /end _GGOR2 #(6) g5 (.I0(w7), .I1(w6), .Z(w10)); //: @(447,161) /sn:0 /anc:1 /w:[ 1 5 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(51,247) /sn:0 /anc:1 /w:[ 1 1 0 ] /eb:0 //: comment g12 @(123,184) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] reg ithaca; //: {0}(18:215,183)(259,183){1} //: {2}(263,183)(271,183){3} //: {4}(261,185)(261,238)(278,238){5} reg crete; //: {0}(7:215,136)(359,136)(359,189){1} //: {2}(361,191)(416,191){3} //: {4}(359,193)(359,203){5} reg toledo; //: {0}(-21:213,243)(254,243){1} //: {2}(258,243)(278,243){3} //: {4}(256,241)(256,188)(271,188){5} wire styx; //: {0}(99:355,275)(355,295){1} wire athens; //: {0}(416,186)(356,186){1} //: {2}(71:352,186)(292,186){3} //: {4}(354,188)(354,203){5} wire pheneos; //: {0}(76:357,224)(357,254){1} wire olympus; //: {0}(-15:437,189)(506,189){1} wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: LED g37 (olympus) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGXOR2 #(8) Athena (.I0(ithaca), .I1(toledo), .Z(athens)); //: @(282,186) /w:[ 3 5 3 ] /eb:0 _GGNAND2 #(4) Hermes (.I0(athens), .I1(crete), .Z(pheneos)); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0 _GGNAND2 #(4) Hades (.I0(delphi), .I1(pheneos), .Z(styx)); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0 _GGXOR2 #(8) Zeus (.I0(athens), .I1(crete), .Z(olympus)); //: @(427,189) /w:[ 0 3 0 ] /eb:0 //: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Search)" //: /line:"" //: /line:"You can search your circuit for a wire or gate with a specific name by using the search tool. Click" //: /line:"on the tool to open it. The list of matches will by dynamically updated as you type the target" //: /line:"string. Double click on an entry in the Search Results to go to that object. Try using the search" //: /line:"tool to search for some of the wire and gate names in the circuit below." //: /line:"" //: /end //: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ] //: SWITCH Thesus (crete) @(198,136) /w:[ 0 ] /st:0 //: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 _GGNAND2 #(4) Apollo (.I0(ithaca), .I1(toledo), .Z(delphi)); //: @(289,241) /w:[ 5 3 0 ] /eb:0 //: SWITCH Odyseus (ithaca) @(198,183) /w:[ 0 ] /st:0 //: comment g0 @(588,148) /sn:0 //: /line:"Hint: The search tool will look" //: /line:"in all modules of your circuit for" //: /line:"the target string. Try searching for" //: /line:"a gate named \"hari\"." //: /end //: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ] //: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin OLD module OLD(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(476,150)(516,150)(516,133)(541,133)(541,145)(566,145)(566,195)(492,195)(492,165){1} wire w32; //: /sn:0 {0}(624,293)(634,293){1} wire w7; //: /sn:0 {0}(470,428)(480,428){1} wire w46; //: /sn:0 {0}(724,568)(681,568)(681,559){1} //: {2}(683,557)(697,557)(697,519)(722,519){3} //: {4}(679,557)(646,557){5} wire w14; //: /sn:0 {0}(522,98)(512,98)(512,79)(531,79)(531,46)(478,46){1} wire w16; //: /sn:0 {0}(543,101)(553,101){1} wire w4; //: /sn:0 {0}(445,152)(455,152){1} wire w15; //: /sn:0 {0}(512,103)(522,103){1} wire w19; //: /sn:0 {0}(604,430)(614,430){1} wire w38; //: /sn:0 {0}(747,392)(757,392){1} wire w0; //: /sn:0 {0}(445,147)(455,147){1} wire w3; //: /sn:0 {0}(475,285)(516,285){1} //: {2}(520,285)(573,285){3} //: {4}(518,283)(518,239)(548,239){5} wire w37; //: /sn:0 {0}(721,392)(731,392){1} wire w34; //: /sn:0 {0}(744,361)(754,361){1} wire w43; //: /sn:0 {0}(615,554)(625,554){1} wire w21; //: /sn:0 {0}(604,468)(614,468){1} wire w31; //: /sn:0 {0}(624,288)(634,288){1} wire w28; //: /sn:0 {0}(655,291)(696,291){1} //: {2}(700,291)(753,291){3} //: {4}(698,289)(698,245)(728,245){5} wire w24; //: /sn:0 {0}(547,360)(524,360){1} //: {2}(522,358)(522,329)(548,329){3} //: {4}(520,360)(482,360){5} wire w20; //: /sn:0 {0}(588,468)(576,468)(576,430)(588,430){1} wire w36; //: /sn:0 {0}(632,363)(642,363){1} wire w41; //: /sn:0 {0}(492,556)(502,556){1} wire w23; //: /sn:0 {0}(537,388)(547,388){1} wire w1; //: /sn:0 {0}(444,282)(454,282){1} wire w25; //: /sn:0 {0}(564,329)(574,329){1} wire w18; //: /sn:0 {0}(523,477)(533,477){1} wire w40; //: /sn:0 {0}(554,475)(564,475){1} wire w8; //: /sn:0 {0}(569,237)(579,237){1} wire w35; //: /sn:0 {0}(632,358)(642,358){1} wire w30; //: /sn:0 {0}(749,243)(759,243){1} wire w17; //: /sn:0 {0}(533,472)(517,472)(517,431)(501,431){1} wire w22; //: /sn:0 {0}(451,362)(461,362){1} wire w11; //: /sn:0 {0}(447,43)(457,43){1} wire w12; //: /sn:0 {0}(447,48)(457,48){1} wire w44; //: /sn:0 {0}(615,559)(625,559){1} wire w2; //: /sn:0 {0}(444,287)(454,287){1} wire w10; //: /sn:0 {0}(451,357)(461,357){1} wire w13; //: /sn:0 {0}(492,551)(502,551){1} wire w27; //: /sn:0 {0}(563,388)(573,388){1} wire w33; //: /sn:0 {0}(728,361)(705,361){1} //: {2}(703,359)(703,330)(729,330){3} //: {4}(701,361)(663,361){5} wire w5; //: /sn:0 {0}(538,234)(548,234){1} wire w48; //: /sn:0 {0}(738,519)(748,519){1} wire w29; //: /sn:0 {0}(718,240)(728,240){1} wire w47; //: /sn:0 {0}(740,568)(750,568){1} wire w42; //: /sn:0 {0}(523,554)(541,554)(541,518){1} wire w9; //: /sn:0 {0}(470,433)(480,433){1} wire w26; //: /sn:0 {0}(563,360)(573,360){1} wire w39; //: /sn:0 {0}(745,330)(755,330){1} //: enddecls _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(466,150) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g4 @(10,552) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(544,475) /sn:0 /w:[ 0 1 0 ] /eb:0 //: joint g3 (w3) @(518, 285) /w:[ 2 4 1 -1 ] //: frame g34 @(437,317) /sn:0 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g37 (w33) @(703, 361) /w:[ 1 2 4 -1 ] //: frame g51 @(442,505) /sn:0 /wi:145 /ht:74 /tx:"Fig. 6a" _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(559,237) /sn:0 /w:[ 1 5 0 ] /eb:0 //: comment g1 @(542,55) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(533,101) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(468,46) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(553,360) /sn:0 /w:[ 0 0 ] //: joint g50 (w46) @(681, 557) /w:[ 2 -1 4 1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(594,430) /sn:0 /w:[ 1 0 ] //: joint g27 (w24) @(522, 360) /w:[ 1 2 4 -1 ] _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(739,243) /sn:0 /w:[ 1 5 0 ] /eb:0 _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(653,361) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(698, 291) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(513,554) /sn:0 /w:[ 1 1 0 ] /eb:0 //: frame g43 @(617,222) /sn:0 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(730,568) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(472,360) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(553,388) /sn:0 /w:[ 1 0 ] //: frame g42 @(437,221) /sn:0 /wi:163 /ht:83 /tx:"Fig. 3a" //: frame g52 @(597,507) /sn:0 /wi:189 /ht:73 /tx:"Fig. 6b" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(491,431) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(737,392) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(636,557) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g24 @(485,442) /sn:0 //: /line:"--->" //: /end _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(734,361) /sn:0 /w:[ 0 0 ] _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(594,468) /sn:0 /w:[ 0 0 ] //: frame g41 @(436,127) /sn:0 /wi:141 /ht:77 /tx:"Fig. 2" //: frame g40 @(434,30) /sn:0 /wi:147 /ht:86 /tx:"Fig. 1" _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(465,285) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(554,329) /sn:0 /w:[ 3 0 ] //: frame g35 @(618,318) /sn:0 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(735,330) /sn:0 /w:[ 3 0 ] //: frame g46 @(440,416) /sn:0 /wi:190 /ht:75 /tx:"Fig. 5" //: comment g30 @(723,257) /sn:0 //: /line:"|" //: /line:"v" //: /end _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(645,291) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(728,519) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/options.v000644 001751 001751 00000004712 11135014277 021564 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "options.v" //: property discardChanges = 1 //: require "tty" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(219,134) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

" //: /line:"" //: /line:"This chapter introduces some of the options that can be customized in TkGate. Your option settings" //: /line:"are stored in a file named \".tkgate2-preferences\" in your home directory." //: /line:"" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(134,181) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your key beinding style)" //: /line:"" //: /line:"You can the basic key-binding style that you would like to use on the Interface tab of the options dialog" //: /line:"box. Currently you can choose between \"emacs\"-style and \"Windows\"-style. Chosing one of these" //: /line:"options will make key bindings for operations such as cut/paste similar to either emacs or Windows," //: /line:"although key bindings for gate creation operations will remain the same." //: /end //: comment g0 @(10,310) /sn:0 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(116,149) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your personal identification)" //: /line:"" //: /line:"To set your TkGate options, open the options dilaog box by selecting File → Options from the" //: /line:"main menu. Enter your site name and user name in the \"Identity\" dialog box. The values you enter" //: /line:"here will be used on any printed output from TkGate." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/tutorials/combinational1.v000644 001751 001751 00000001537 11135014260 022763 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

" //: /line:"" //: /line:"TkGate uses a Verilog-based discrete event simulator to simulate your circuit description. In this" //: /line:"chapter the basics needed to simulate a combinational circuit will be presented." //: /end //: comment g0 @(191,165) /sn:0 /anc:1 //: /line:"" //: /end //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/tutorials/sequential1.v000644 001751 001751 00000001514 11135014266 022317 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

" //: /line:"" //: /line:"This chapter builds on the previous chapter about simulating combinational circuits and introduces" //: /line:"simulator features that are useful for simulating sequential circuits." //: /end //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(208,188) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/tutorials/combinational3.v000644 001751 001751 00000007770 11135014317 022775 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:140,305)(154,305){1} //: {2}(158,305)(176,305){3} //: {4}(180,305)(228,305){5} //: {6}(178,303)(178,242)(223,242){7} //: {8}(156,303)(156,293){9} reg A; //: {0}(223,237)(191,237){1} //: {2}(189,235)(-86:189,217)(159,217){3} //: {4}(157,215)(157,204){5} //: {6}(155,217)(142,217){7} //: {8}(189,239)(189,300)(228,300){9} reg Cin; //: {0}(258,202)(278,202){1} //: {2}(280,200)(280,191){3} //: {4}(48:280,204)(280,233){5} //: {6}(282,235)(320,235){7} //: {8}(280,237)(280,261){9} wire w6; //: /sn:0 {0}(321,303)(249,303){1} wire w0; //: /sn:0 {0}(321,298)(278,298)(278,282){1} wire w1; //: /sn:0 {0}(320,240)(277,240){1} //: {2}(273,240)(244,240){3} //: {4}(275,242)(275,261){5} wire C; //: {0}(-21:390,210)(390,301)(342,301){1} wire S; //: {0}(341,238)(-39:360,238)(360,210){1} //: enddecls _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(234,240) /sn:0 /w:[ 0 7 3 ] _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(332,301) /sn:0 /w:[ 0 0 1 ] //: SWITCH g3 (Cin) @(241,202) /sn:0 /w:[ 0 ] /st:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(setting probes)" //: /line:"" //: /line:"Press the \" Simulate\" tab again, to enter simulation mode. This time right click on a wire (e.g., the" //: /line:"one labeled \"S\") and slect \"Add/Delete Probe\" from the popup menu. The will set a probe on that" //: /line:"wire and bring up the logic analyzer window. Set probes on some more wires, then unpause the" //: /line:"simulator by pressing . Click on the switches to change their state and observe how the logic" //: /line:"analyzer is updated." //: /end _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(239,303) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(123,305) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(275, 240) /w:[ 1 -1 2 4 ] //: joint g10 (Cin) @(280, 235) /w:[ 6 5 -1 8 ] //: LED g28 (A) @(157,197) /sn:0 /w:[ 5 ] /type:0 //: joint g27 (Cin) @(280, 202) /w:[ -1 2 1 4 ] //: joint g6 (B) @(178, 305) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(331,238) /sn:0 /w:[ 7 0 0 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(278,272) /sn:0 /R:3 /w:[ 5 9 1 ] //: comment g15 @(585,254) /sn:0 /anc:1 //: /line:"Hint: Normally, TkGate will simulate" //: /line:"combinational circuits until all signals" //: /line:"have reached a steady state. You can" //: /line:"hit the space bar to advance the" //: /line:"simulator by one time unit." //: /end //: joint g31 (A) @(157, 217) /w:[ 3 4 6 -1 ] //: LED g25 (C) @(390,203) /sn:0 /w:[ 0 ] /type:0 //: LED g29 (B) @(156,286) /sn:0 /w:[ 9 ] /type:0 //: joint g5 (A) @(189, 237) /w:[ 1 2 -1 8 ] //: comment g14 @(583,172) /sn:0 /anc:1 //: /line:"Hint: In addition to using probes," //: /line:"you can also see the value of a net" //: /line:"by clicking and holding the mouse" //: /line:"button down for a few seconds." //: /end //: SWITCH g0 (A) @(125,217) /sn:0 /w:[ 7 ] /st:0 //: LED g26 (Cin) @(280,184) /sn:0 /w:[ 3 ] /type:0 //: LED g18 (S) @(360,203) /sn:0 /w:[ 1 ] /type:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (B) @(156, 305) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/combinational5.v000644 001751 001751 00000015325 11135014325 022771 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(the instance hierarchy)" //: /line:"" //: /line:"While the simulator is active, the hierarchical module list displays the hierarchy by instance" //: /line:"rather than by module. This is because the state (i.e., net values) for each instance of a module" //: /line:"in the hierarcy may be different. Invoke and unpause the simulation for the circuit below, then" //: /line:"try examining the nets in different instances of the ADD1 module. Double click on \"g0<ADD1>\"," //: /line:"\"g1<ADD1>\", etc. in the the hierarchical list box to go to each instance." //: /line:"" //: /end //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(580,147) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: comment g7 @(581,227) /sn:0 /anc:1 //: /line:"Hint: You can also navigate to modules" //: /line:"by right clicking and select Open" //: /line:"from the popup menu." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>A(12/50) Li1>B(34/50) Bo05 Ti1>0 Li0>1 Bo0<1 ] //: GROUND g43 (w11) @(759,108) /sn:0 /w:[ 0 ] //: LED g48 (reg_out) @(731,256) /sn:0 /R:2 /w:[ 5 ] /type:1 //: joint g17 (w14) @(213, 237) /w:[ 1 2 4 -1 ] //: SWITCH g25 (a) @(56,79) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a) @(117, 79) /w:[ 2 -1 1 4 ] //: LED g62 (w14) @(213,211) /sn:0 /w:[ 3 ] /type:2 //: DIP g42 (w19) @(703,29) /sn:0 /w:[ 1 ] /st:248 //: DIP data_in (w25) @(52,208) /sn:0 /R:1 /w:[ 0 ] /st:11 //: LED g14 (co) @(245,139) /sn:0 /w:[ 0 ] /type:0 _GGPMOS #(2, 1) g5 (.Z(w13), .S(w5), .G(w1)); //: @(450,87) /sn:0 /w:[ 9 1 3 ] //: LED g56 (w13) @(495,94) /sn:0 /w:[ 5 ] /type:0 //: SWITCH g44 (w20) @(607,137) /sn:0 /w:[ 1 ] /st:1 _GGMUX2x8 #(8, 8) g47 (.I0(w9), .I1(w22), .S(w20), .Z(w27)); //: @(684,137) /sn:0 /w:[ 1 0 0 0 ] /ss:0 /do:0 _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s)); //: @(213,85) /sn:0 /w:[ 0 3 1 ] /eb:0 _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8)); //: @(138,82) /sn:0 /w:[ 3 3 3 ] /eb:0 //: VDD g41 (w10) @(748,160) /sn:0 /w:[ 1 ] //: LED g54 (w1) @(394,71) /sn:0 /w:[ 5 ] /type:0 //: GROUND g40 (w18) @(741,212) /sn:0 /w:[ 0 ] //: SWITCH data_select (w28) @(52,268) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(280,236) /anc:1 //: /line:"

Welcome to TkGate

" //: /line:"[Beta Release]" //: /line:"" //: /line:"" //: /line:" TKGate comes with ABSOLUTELY NO WARRANTY; see 'Help...License' menu" //: /line:" for license and warranty details. Report problems to " //: /line:" [released ]" //: /line:"" //: /line:"Click on a link below to start using tkgate!" //: /line:"" //: /line:" * Go to the tutorial" //: /line:"" //: /line:" * Go to the example circuits" //: /line:"" //: /line:" * Edit a new circuit" //: /line:"" //: /line:" * Open the documentation " //: /end //: SWITCH g26 (b) @(56,134) /sn:0 /w:[ 0 ] /st:1 _GGADD8 #(68, 70, 62, 64) g45 (.A(w19), .B(reg_out), .S(w22), .CI(w11), .CO(w24)); //: @(719,82) /sn:0 /w:[ 0 3 1 1 0 ] //: GROUND g46 (w9) @(650,108) /sn:0 /w:[ 0 ] //: SWITCH g12 (w1) @(340,87) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b) @(109, 134) /w:[ -1 2 1 4 ] //: joint g33 (ci) @(177, 87) /w:[ 2 1 -1 4 ] _GGREG8 #(10, 10, 20) g49 (.Q(reg_out), .D(w27), .EN(w18), .CLR(w10), .CK(clk)); //: @(684,183) /sn:0 /w:[ 0 1 1 0 1 ] endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(89, 65) /bd:[ Ti0>B[7:0](67/89) Ti1>A[7:0](21/89) Li0>F[1:0](39/65) Bo0 S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGCLOCK_P200_0_50 (Z); output Z; reg Z = 1'b0; initial #100 if (0 == 0) forever begin Z = 1'b1; #100; Z = 1'b0; #100; end else forever begin Z = 1'b0; #100; Z = 1'b1; #100; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential3.v000644 001751 001751 00000012063 11135014352 022316 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /symbolBegin: 680294000 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:232,193)(232,219){1} reg w4; //: /sn:0 {0}(287,278)(298,278)(298,266)(308,266){1} supply0 w3; //: /sn:0 {0}(285,243)(285,233)(272,233){1} supply0 w0; //: /sn:0 {0}(287,288)(310,288)(310,303){1} wire [7:0] w2; //: /sn:0 {0}(#:248,273)(248,248){1} wire ck; //: {0}(-39:130,283)(211,283){1} wire [7:0] reg_out; //: {0}(#:248,294)(248,327)(304,327){1} //: {2}(308,327)(364,327)(58:364,206)(264,206)(264,219){3} //: {4}(306,329)(306,342){5} wire w9; //: /sn:0 {0}(224,233)(214,233){1} //: enddecls //: joint g8 (reg_out) @(306, 327) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(310,309) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(continuous simulation)" //: /line:"" //: /line:"Also like with a combinational circuit, you can press the button to unpause and simulate" //: /line:"continously. Try it with the circuit below. This circuit contains a \"real-world-time\" oscilator" //: /line:"that will cycle once per second. Like in the previous example, you will need to reset it by" //: /line:"turning the \"reset\" switch off monentarily." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(248,283) /sn:0 /w:[ 0 0 0 0 1 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end OSCILLATOR g10 (.Z(ck)); //: @(116, 283) /symbol:680294000 /sn:0 /w:[ 0 ] //: DIP g6 (w7) @(232,183) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(285,249) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(306,349) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(248,235) /sn:0 /w:[ 1 3 1 1 0 ] //: SWITCH reset (w4) @(326,266) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/combinational4.v000644 001751 001751 00000014410 11135014322 022757 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(dip switches)" //: /line:"" //: /line:"To change the value of a dip while simulating a circuit, first click on it to open a value dialog" //: /line:"box. Then enter the new value in hexidecimal and click Apply. Start the simulator then try" //: /line:"changing the input values in the four-bit adder below and observe the output." //: /end //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(560,127) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>A[3:0](16/64) Li1>B[3:0](41/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>A(12/50) Li1>B(34/50) Bo0Sequential Simulation (breakpoints)" //: /line:"" //: /line:"You can use breakpoints to simulate a circuit until some condition holds. To add a" //: /line:"breakpoint click on the tab on the information box below the canvas, and press" //: /line:"the Add... button. Enter the breakpoint as a Verilog expression. Start the simulator" //: /line:"and try it with the expresion \"reg_out == 8'h42\" as shown in the example on the right." //: /line:"This will cause the simulator to stop when the reg_out signal has the value 42 hexidecimal." //: /line:"Be sure to press after entering the breakpoint." //: /end //: SWITCH g3 (w4) @(307,295) /sn:0 /R:2 /w:[ 1 ] /st:1 _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(229,312) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(565,96) /sn:0 /anc:1 //: /line:"" //: /line:"" //: /line:"

Breakpoint Entry Example.

" //: /end //: DIP g6 (w7) @(213,212) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(289,366) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(266,278) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(229,264) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(114,312) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential5.v000644 001751 001751 00000007667 11135014357 022343 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:199,201)(199,227){1} supply0 w3; //: /sn:0 {0}(252,251)(252,241)(239,241){1} supply0 w0; //: /sn:0 {0}(254,296)(274,296)(274,307){1} reg clr; //: {0}(32:254,286)(285,286){1} wire [7:0] w2; //: /sn:0 {0}(#:215,281)(215,256){1} wire ck; //: {0}(50:178,291)(113,291){1} wire [7:0] reg_out; //: {0}(#:215,302)(215,328)(273,328){1} //: {2}(277,328)(333,328)(52:333,215)(231,215)(231,227){3} //: {4}(275,330)(275,338){5} wire w9; //: /sn:0 {0}(191,241)(181,241){1} //: enddecls //: joint g8 (reg_out) @(275, 328) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(274,313) /sn:0 /w:[ 1 ] //: comment g13 @(14,12) //: /line:"

Sequential Simulation

(scripts)" //: /line:"" //: /line:"In addition to interactive simulator control, you can also write a simulator script." //: /line:"Simulator script files have the extension \".vs\" and are written using Verilog" //: /line:"syntax. While the simulator is active, press to load a simulator script file." //: /line:"You can use a script file to set and remove probes, advance the simulation time," //: /line:"set signal values and display messages in the TkGate log () window. See" //: /line:"the TkGate 2.0 documentation for details on how to write simulator scripts." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(clr), .CK(ck)); //: @(215,291) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(495,118) /sn:0 /R:14 /anc:1 //: /line:"Simulator Script Example:" //: /line:"" //: /line:"initial" //: /line:" begin" //: /line:" $display(\"%t: Start of script\",$time);" //: /line:" $tkg$probe(ck, reg_out, clr);" //: /line:" $display(\"%t: Set probes\",$time);" //: /line:" clr = 1'b0;" //: /line:" #200;" //: /line:" clr = 1'b1;" //: /line:" $display(\"%t: Done with reset\",$time);" //: /line:" #500;" //: /line:" $stop();" //: /line:" end" //: /line:"" //: /end //: DIP g6 (w7) @(199,191) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(252,257) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(275,345) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(215,243) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(100,291) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (clr) @(303,286) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/index.v~000644 001751 001751 00000003527 11135014211 021365 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(433,291) /sn:0 /R:14 //: /line:"Go back to the TkGate main page." //: /end //: comment g0 @(434,49) /sn:0 /anc:1 //: /line:"" //: /end //: comment g18 @(10,10) /sn:0 /anc:1 //: /line:"

Tutorial Chapters:

" //: /line:"" //: /line:"

1. Creating a Circuit

- Get started by creating a simple circuit." //: /line:"" //: /line:"

2. Editing Gates

- The basics of editing gates." //: /line:"" //: /line:"

3. Editing Wires

- The basics of editing wires." //: /line:"" //: /line:"

4. Group Editing Features

- Operate on groups of gates." //: /line:"" //: /line:"

5. Using Modules

- Using modules in your circuit." //: /line:"" //: /line:"

6. Advanced Editing Techniques

- Learn advanced editing tricks." //: /line:"" //: /line:"

7. Combinational Simulation

- Simulate a circuit with" //: /line:" combinational logic." //: /line:"" //: /line:"

8. Sequential Simulation

- Simulate a circuit with sequential logic." //: /line:"" //: /line:"

9. Textual Verilog

- Create modules with textual Verilog descriptions." //: /line:"" //: /line:"

10. Customizing TkGate

- Customize TkGate to suit your tastes." //: /line:"" //: /line:"" //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/tutorials/create.v~000644 001751 001751 00000017162 11135014214 021524 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "create_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg w3; //: /sn:0 {0}(219,137)(154,137){1} reg w9; //: /sn:0 {0}(314,237)(213,237){1} //: {2}(211,235)(211,142)(219,142){3} //: {4}(209,237)(154,237){5} wire w8; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} wire w10; //: /sn:0 {0}(335,235)(345,235){1} //: enddecls //: comment g8 @(313,208) //: /line:"OR gate" //: /end //: joint g13 (w9) @(211, 237) /w:[ 1 2 4 -1 ] //: comment g1 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w3), .I1(w9), .Z(w8)); //: @(230,140) /sn:0 /w:[ 0 3 1 ] //: comment g6 @(115,104) //: /line:"Switches" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"In this chapter, we will walk through the steps of creating the simple circuit shown below." //: /end //: comment g7 @(208,112) //: /line:"AND gate" //: /end //: SWITCH g14 (w3) @(137,137) /sn:0 /w:[ 1 ] /st:0 _GGOR2 #(6) g0 (.I0(w8), .I1(w9), .Z(w10)); //: @(325,235) /sn:0 /w:[ 0 0 0 ] //: SWITCH g12 (w9) @(137,237) /sn:0 /w:[ 5 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(182,237)(182,237)(314,237){1} reg w2; //: /sn:0 {0}(219,137)(186,137)(186,137)(154,137){1} wire w7; //: /sn:0 {0}(335,235)(345,235){1} wire w0; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(314,232)(294,232)(294,140)(240,140){1} //: enddecls _GGOR2 #(6) g4 (.I0(w5), .I1(w6), .Z(w7)); //: @(325,235) /sn:0 /w:[ 0 1 0 ] _GGAND2 #(6) g3 (.I0(w2), .I1(w0), .Z(w5)); //: @(230,140) /sn:0 /w:[ 0 1 1 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /w:[ 0 ] /st:0 //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(537,46) /sn:0 /anc:1 //: /line:"" //: /end //: comment g7 @(537,126) /sn:0 /anc:1 //: /line:"Hint: Joints are formed any" //: /line:"time the soldering iron is" //: /line:"active and you release the" //: /line:"wire in the middle of another" //: /line:"wire." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now make the final connection. Grab the lower input terminal of the AND gate" //: /line:"and drag it down near the wire between the lower switch and the OR gate. Release" //: /line:"the wire to create a joint." //: /line:"" //: /end //: SWITCH g5 (w2) @(137,137) /sn:0 /w:[ 1 ] /st:0 endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w2; //: /sn:0 {0}(240,140)(255,140){1} //: enddecls _GGAND2 #(6) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(230,140) /sn:0 /w:[ 1 1 0 ] //: frame g1 @(283,202) /sn:0 /wi:78 /ht:46 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Now create an OR gate. Right click in the dashed line box then select" //: /line:"Make → Gate → OR from the popup menu." //: /end //: comment g0 @(532,85) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"o\" to create an OR gate." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg w6; //: /sn:0 {0}(154,237)(169,237){1} reg w2; //: /sn:0 {0}(154,137)(169,137){1} wire w7; //: /sn:0 {0}(240,140)(255,140){1} wire w4; //: /sn:0 {0}(204,137)(219,137){1} wire w0; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(335,235)(350,235){1} wire w1; //: /sn:0 {0}(299,237)(314,237){1} wire w5; //: /sn:0 {0}(204,142)(219,142){1} //: enddecls //: SWITCH g4 (w2) @(137,137) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGAND2 #(6) g3 (.I0(w4), .I1(w5), .Z(w7)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: SWITCH g2 (w6) @(137,237) /sn:0 /anc:1 /w:[ 0 ] /st:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w1), .Z(w3)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g6 @(578,122) /sn:0 /anc:1 //: /line:"Hint: The soldering iron cursor will" //: /line:"show you when you have selected" //: /line:"a connectable wire end." //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Finally, connect the wires. Begin by grabbing the end of the wire leading from one of the" //: /line:"switches with the left mouse button and drag it to the upper input terminal of the AND gate." //: /end //: comment g0 @(579,61) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(335,235)(350,235){1} wire w4; //: /sn:0 {0}(299,232)(314,232){1} wire w3; //: /sn:0 {0}(240,140)(255,140){1} wire w0; //: /sn:0 {0}(204,137)(219,137){1} wire w1; //: /sn:0 {0}(204,142)(219,142){1} wire w5; //: /sn:0 {0}(299,237)(314,237){1} //: enddecls //: frame g8 @(109,215) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" _GGOR2 #(6) g4 (.I0(w4), .I1(w5), .Z(w7)); //: @(325,235) /sn:0 /anc:1 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w0), .I1(w1), .Z(w3)); //: @(230,140) /sn:0 /anc:1 /w:[ 1 1 0 ] //: frame g1 @(109,121) /sn:0 /anc:1 /wi:76 /ht:43 /tx:"" //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Next create two switches. Right click in each of the two dashed line box then" //: /line:"select Make → I/O → Switch from the popup menu." //: /end //: comment g0 @(532,86) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"s\" to create a switch." //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(531,86) /sn:0 /anc:1 //: /line:"Hint: You can also use the keyboard" //: /line:"shortcut. Select the position by left clicking" //: /line:"then use \"a\" to create an AND gate." //: /end //: frame g1 @(208,124) /sn:0 /wi:76 /ht:43 /tx:"" //: comment g9 @(10,10) /anc:1 //: /line:"

Creating a Simple Circuit

" //: /line:"" //: /line:"Start by creating an AND gate. Right click in the dashed line box then select" //: /line:"Make → Gate → AND from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/gates.v~000644 001751 001751 00000035231 11135014223 021361 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

" //: /line:"" //: /line:"This chapter will introduce some of the basic circuit editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(144,69) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(256,171)(271,171){1} wire w0; //: /sn:0 {0}(102,172)(117,172){1} wire w3; //: /sn:0 {0}(256,166)(271,166){1} wire w1; //: /sn:0 {0}(102,177)(117,177){1} wire w2; //: /sn:0 {0}(138,175)(153,175){1} wire w5; //: /sn:0 {0}(292,169)(307,169){1} //: enddecls //: comment g4 @(247,195) /sn:0 /anc:1 //: /line:"Anchored Gate" //: /end _GGOR2 #(6) g3 (.I0(w3), .I1(w4), .Z(w5)); //: @(282,169) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Anchoring)" //: /line:"" //: /line:"You can prevent a gate from being accidentally moved by selecting it and pressing" //: /line:"the button to set an anchor. You can remove an anchor with the button." //: /line:"Gates which have been anchored (e.g., the OR gate below) can not be moved until" //: /line:"you remove the anchor. Try moving the gates below." //: /line:"" //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(128,175) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(587,112) /sn:0 /anc:1 //: /line:"Hint: An alternate way to add or" //: /line:"remove an anchor on a gate is to" //: /line:"right click and change the anchor" //: /line:"flag in the popup menu." //: /end //: comment g5 @(81,195) /sn:0 /anc:1 //: /line:"Unanchored Gate" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) /anc:1 //: /line:"

Editing Gates

(Repositioning)" //: /line:"" //: /line:"To move a gate, select it with the tool and drag it to a new location. Try" //: /line:"it on the sample circuit below." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(39,221)(54,221){1} wire w7; //: /sn:0 {0}(41,265)(56,265){1} wire w16; //: /sn:0 {0}(154,267)(169,267){1} wire w14; //: /sn:0 {0}(169,222)(154,222){1} wire w19; //: /sn:0 {0}(169,277)(154,277){1} wire w15; //: /sn:0 {0}(154,262)(169,262){1} wire w4; //: /sn:0 {0}(39,218)(54,218){1} wire w0; //: /sn:0 {0}(37,166)(52,166){1} wire w3; //: /sn:0 {0}(39,214)(54,214){1} wire w21; //: /sn:0 {0}(152,167)(167,167){1} wire w20; //: /sn:0 {0}(41,274)(56,274){1} wire w23; //: /sn:0 {0}(188,169)(203,169){1} wire w1; //: /sn:0 {0}(37,171)(52,171){1} wire w18; //: /sn:0 {0}(190,269)(205,269){1} wire w8; //: /sn:0 {0}(41,268)(56,268){1} wire w17; //: /sn:0 {0}(169,272)(154,272){1} wire w22; //: /sn:0 {0}(152,172)(167,172){1} wire w12; //: /sn:0 {0}(154,217)(169,217){1} wire w11; //: /sn:0 {0}(154,212)(169,212){1} wire w2; //: /sn:0 {0}(73,169)(88,169){1} wire w10; //: /sn:0 {0}(41,271)(56,271){1} wire w13; //: /sn:0 {0}(190,217)(205,217){1} wire w5; //: /sn:0 {0}(75,218)(90,218){1} wire w9; //: /sn:0 {0}(77,270)(92,270){1} //: enddecls _GGAND4 #(10) g4 (.I0(w7), .I1(w8), .I2(w10), .I3(w20), .Z(w9)); //: @(67,270) /sn:0 /w:[ 1 1 1 1 0 ] //: comment g8 @(149,126) /sn:0 /anc:1 //: /line:"gates with" //: /line:"extender bars" //: /end _GGAND3 #(8) g3 (.I0(w3), .I1(w4), .I2(w6), .Z(w5)); //: @(65,218) /sn:0 /w:[ 1 1 1 0 ] //: comment g2 @(11,13) /anc:1 //: /line:"

Editing Gates

(Adding Inputs)" //: /line:"" //: /line:"Some gates (e.g., AND gates) can have a variable number of inputs or outputs. To add inputs (or" //: /line:"outputs) to these gates, select the gate and press the button. Also, some gates may have multiple styles" //: /line:"for adding ports that can be selected through the gate properties box. Try adding inputs to the gates below," //: /line:"or create a new gate and add inputs to it." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(63,169) /sn:0 /w:[ 1 1 0 ] _GGAND4 #(10) g6 (.I0(w15), .I1(w16), .I2(w17), .I3(w19), .Z(w18)); //: @(180,269) /sn:0 /w:[ 1 1 0 0 0 ] /eb:1 //: comment g7 @(26,127) /sn:0 /anc:1 //: /line:"gates without" //: /line:"extender bars" //: /end _GGAND2 #(6) g9 (.I0(w21), .I1(w22), .Z(w23)); //: @(178,169) /sn:0 /w:[ 1 1 0 ] /eb:1 _GGAND3 #(8) g5 (.I0(w11), .I1(w12), .I2(w14), .Z(w13)); //: @(180,217) /sn:0 /w:[ 1 1 0 0 ] /eb:1 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: frame g3 @(298,213) /sn:0 /wi:167 /ht:69 /tx:"This is a frame" //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Comments and Frames)" //: /line:"" //: /line:"There are two special \"gates\" that you can use for annotating your circuit specification: comments and frames." //: /line:"Neither of these \"gates\" has any effect on the simulation results." //: /line:"" //: /line:"Comments are blocks of text such as those used to construct this tutorial. Comments are created by right clicking" //: /line:"and selecting Make → Comment from the popup menu. When you create a comment, the properties box will" //: /line:"appear immediately allowing you to enter the text of the comment. Comments can contain limited html tags including links" //: /line:"to other circuit files, or short cuts to specific gates in your circuit." //: /line:"" //: /line:"Frames are annotated boxes for organzing groups of related circuit elements that don't warrant creating a new module. Open" //: /line:"the properties box by double clicking on an edge to set the annotation string. Click and drag on a corner to resize." //: /line:"" //: /end //: comment g1 @(72,233) /sn:0 //: /line:"This is a comment with" //: /line:"some bold text in it." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w0; //: /sn:0 {0}(118,149)(133,149){1} wire w1; //: /sn:0 {0}(118,154)(133,154){1} wire w2; //: /sn:0 {0}(154,152)(169,152){1} //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Rotation)" //: /line:"" //: /line:"The orientation of a gate can be changed by selecting it and pressing the button" //: /line:"(or Tab key) to rotate it counter-clockwise and the button (or Shift-Tab key) to" //: /line:"rotate it clockwise. Try it on the AND gate below." //: /end _GGAND2 #(6) g1 (.I0(w0), .I1(w1), .Z(w2)); //: @(144,152) /sn:0 /w:[ 1 1 0 ] //: comment g6 @(567,92) /sn:0 /anc:1 //: /line:"Hint: You can also use the " //: /line:"button to set the default orientation" //: /line:"for newly created gates." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Properties)" //: /line:"" //: /line:"You can also open the properties box of a gate by double clicking on it. Try" //: /line:"double clicking on some of the gates in the circuit below. Through the properties" //: /line:"box you can change the label of a gate and make the label visible or invisible" //: /line:"though the \"Hide Name\" property." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 //: comment g6 @(548,104) /sn:0 /anc:1 //: /line:"Hint: Many properties are gate-" //: /line:"specific. Try opening the property" //: /line:"boxes of different gate types to see" //: /line:"what proprties can be modified." //: /end _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:125,126)(231,126)(231,168){1} //: {2}(233,170)(256,170){3} //: {4}(231,172)(231,183){5} reg a0; //: {0}(40:125,162)(169,162){1} //: {2}(173,162)(181,162){3} //: {4}(171,164)(171,218)(188,218){5} reg b0; //: {0}(50:125,197)(163,197){1} //: {2}(165,195)(165,167)(181,167){3} //: {4}(165,199)(165,223)(188,223){5} wire w7; //: /sn:0 {0}(209,221)(224,221)(224,233){1} wire s0; //: {0}(36:277,168)(307,168){1} wire w4; //: /sn:0 {0}(229,204)(229,233){1} wire c1; //: {0}(99:227,254)(227,273){1} wire w9; //: /sn:0 {0}(256,165)(228,165){1} //: {2}(224,165)(202,165){3} //: {4}(226,167)(226,183){5} //: enddecls //: LED g37 (s0) @(314,168) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Gates

(Deletion)" //: /line:"" //: /line:"To delete a gate, select it with the tool and press the Delete key. Try it on the sample circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(227,244) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(199,221) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g32 (w9) @(226, 165) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(108,126) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(229,194) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(171, 162) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(108,162) /sn:0 /w:[ 0 ] /st:0 _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(267,168) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(192,165) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(108,197) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(231, 170) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(165, 197) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGAND4 #(.Diz(1)) (I0, I1, I2, I3, Z); output Z; input I0; input I1; input I2; input I3; assign #Diz Z = I0 & I1 & I2 & I3; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0; input I1; input I2; assign #Diz Z = I0 & I1 & I2; endmodule //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/wires.v~000644 001751 001751 00000023776 11135014226 021425 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "edit1_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g2 @(10,10) /anc:1 //: /line:"

Editing Wires

" //: /line:"" //: /line:"This chapter will introduce the basic wire editing features of TkGate." //: /end //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(185,114) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(I/O inverters)" //: /line:"" //: /line:"To place or remove an inverter on a gate input or output, select the tool" //: /line:"and click on the port at which you want to place or remove an inveter. Try" //: /line:"using the inverter tool to place and remove inverters in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:155,153)(261,153)(261,195){1} //: {2}(263,197)(286,197){3} //: {4}(261,199)(261,209){5} reg a0; //: {0}(40:155,189)(199,189){1} //: {2}(203,189)(211,189){3} //: {4}(201,191)(201,245)(218,245){5} reg b0; //: {0}(50:155,224)(193,224){1} //: {2}(195,222)(195,194)(211,194){3} //: {4}(195,226)(195,250)(218,250){5} wire w7; //: /sn:0 {0}(239,248)(254,248)(254,260){1} wire s0; //: {0}(36:307,195)(337,195){1} wire w4; //: /sn:0 {0}(259,230)(259,260){1} wire c1; //: {0}(99:257,281)(257,300){1} wire w9; //: /sn:0 {0}(286,192)(258,192){1} //: {2}(254,192)(232,192){3} //: {4}(256,194)(256,209){5} //: enddecls //: LED g37 (s0) @(344,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(11,10) //: /line:"

Editing Wires

(wire labels)" //: /line:"" //: /line:"Wire label editing is performed with the tool. Select this tool if it is not already selected. Existing" //: /line:"wire labels can be moved by left clicking and dragging the label to a new position. Wire labels can only" //: /line:"be moved to a different locations on the wire from which it was grabbed. If you drop the label too far from" //: /line:"its wire, the label will be discarded. To display a new label right click on the wire and choose the Show" //: /line:"Label option. You can also hide a specific label (Hide Label) or hide all labels for a wire (Hide All Labels)." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(257,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(229,248) /sn:0 /w:[ 5 5 0 ] //: SWITCH g27 (c0) @(138,153) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(256, 192) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(259,220) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(138,189) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(201, 189) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(297,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(222,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(138,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g30 (b0) @(195, 224) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(261, 197) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:118,113)(224,113)(224,155){1} //: {2}(226,157)(249,157){3} //: {4}(224,159)(224,169){5} reg a0; //: {0}(40:118,149)(162,149){1} //: {2}(166,149)(174,149){3} //: {4}(164,151)(164,205)(181,205){5} reg b0; //: {0}(50:118,184)(156,184){1} //: {2}(158,182)(158,154)(174,154){3} //: {4}(158,186)(158,210)(181,210){5} wire w7; //: /sn:0 {0}(202,208)(217,208)(217,220){1} wire s0; //: {0}(36:270,155)(300,155){1} wire w4; //: /sn:0 {0}(222,190)(222,220){1} wire c1; //: {0}(99:220,241)(220,260){1} wire w9; //: /sn:0 {0}(249,152)(221,152){1} //: {2}(217,152)(195,152){3} //: {4}(219,154)(219,169){5} //: enddecls //: LED g37 (s0) @(307,155) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(cutting)" //: /line:"" //: /line:"To cut a wire, select the tool and click on a wire at the point you wish to cut. Try" //: /line:"using the wire cutter tool to cut some of the wires in the circuit below." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(220,231) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(192,208) /sn:0 /w:[ 5 5 0 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g27 (c0) @(101,113) /sn:0 /w:[ 0 ] /st:0 //: joint g32 (w9) @(219, 152) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(222,180) /sn:0 /R:3 /w:[ 5 5 0 ] //: SWITCH g25 (a0) @(101,149) /sn:0 /w:[ 0 ] /st:0 //: joint g29 (a0) @(164, 149) /w:[ 2 -1 1 4 ] _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(260,155) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(185,152) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(101,184) /sn:0 /w:[ 0 ] /st:0 //: joint g30 (b0) @(158, 184) /w:[ -1 2 1 4 ] //: joint g33 (c0) @(224, 157) /w:[ 2 1 -1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] supply1 w7; //: /sn:0 {0}(320,176)(335,176)(335,158){1} reg [7:0] w3; //: /sn:0 {0}(#:184,170)(184,208)(212,208)(212,224){1} supply0 w8; //: /sn:0 {0}(271,250)(271,238)(252,238){1} supply0 w5; //: /sn:0 {0}(339,207)(339,186)(320,186){1} wire [7:0] w6; //: /sn:0 {0}(281,171)(281,146)(371,146)(371,268)(#:228,268)(#:228,253){1} wire w4; //: /sn:0 {0}(204,238)(189,238){1} wire [7:0] w1; //: /sn:0 {0}(244,224)(244,211)(#:281,211)(#:281,192){1} wire w2; //: /sn:0 {0}(85,181)(244,181){1} //: enddecls //: DIP g8 (w3) @(184,160) /sn:0 /w:[ 0 ] /st:66 //: GROUND g4 (w5) @(339,213) /sn:0 /w:[ 0 ] //: comment g2 @(9,10) /anc:1 //: /line:"

Editing Wires

(bit widths)" //: /line:"" //: /line:"To change the bit size of one or more wires, first enter the desired bit size in the" //: /line:"bit size selector . Next, choose the tool, and click on each wire" //: /line:"to be changed to that size. Try changing the 8-bit wires in the circuit below to 16-bit wires." //: /line:"" //: /end _GGREG8 #(10, 10, 20) g1 (.Q(w1), .D(w6), .EN(w5), .CLR(w7), .CK(w2)); //: @(281,181) /sn:0 /w:[ 1 0 1 0 1 ] //: comment g10 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end _GGCLOCK_P100_0_50 g6 (.Z(w2)); //: @(72,181) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g7 (w8) @(271,256) /sn:0 /w:[ 0 ] //: VDD g5 (w7) @(346,158) /sn:0 /w:[ 1 ] _GGADD8 #(68, 70, 62, 64) g0 (.A(w3), .B(w1), .S(w6), .CI(w8), .CO(w4)); //: @(228,240) /sn:0 /w:[ 1 0 1 1 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/group.v~000644 001751 001751 00000025044 11135014231 021412 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "edit2_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(140,67) /sn:0 /anc:1 //: /line:"" //: /end //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

" //: /line:"" //: /line:"In this chapter, you will learn about how to do editing operations on groups of gates." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:183,147)(289,147)(289,189){1} //: {2}(291,191)(314,191){3} //: {4}(289,193)(289,210){5} reg a0; //: {0}(40:183,183)(227,183){1} //: {2}(231,183)(239,183){3} //: {4}(229,185)(229,239)(246,239){5} reg b0; //: {0}(50:183,218)(221,218){1} //: {2}(223,216)(223,188)(239,188){3} //: {4}(223,220)(223,244)(246,244){5} wire w7; //: /sn:0 {0}(267,242)(282,242)(282,254){1} wire s0; //: {0}(36:335,189)(365,189){1} wire w4; //: /sn:0 {0}(287,231)(287,254){1} wire c1; //: {0}(99:285,275)(285,294){1} wire w9; //: /sn:0 {0}(314,186)(286,186){1} //: {2}(282,186)(260,186){3} //: {4}(284,188)(284,210){5} //: enddecls //: LED g37 (s0) @(372,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(285,265) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(257,242) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(284, 186) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(166,147) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(287,221) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(229, 183) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(166,183) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(incremental selection)" //: /line:"" //: /line:"You can add or remove gates from the current selection by holding the Control key while" //: /line:"you click on them. Use the selection box to select the gates below then click on a few" //: /line:"of the gates with the Control key held down. Release the Control key and then try moving" //: /line:"the selection with only some of the gates selected." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(325,189) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(250,186) /sn:0 /w:[ 3 3 3 ] //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: SWITCH g26 (b0) @(166,218) /sn:0 /w:[ 0 ] /st:0 //: joint g33 (c0) @(289, 191) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(223, 218) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:167,153)(273,153)(273,195){1} //: {2}(275,197)(298,197){3} //: {4}(273,199)(273,216){5} reg a0; //: {0}(40:167,189)(189,189)(189,189)(211,189){1} //: {2}(215,189)(223,189){3} //: {4}(213,191)(213,245)(230,245){5} reg b0; //: {0}(50:167,224)(186,224)(186,224)(205,224){1} //: {2}(207,222)(207,194)(223,194){3} //: {4}(207,226)(207,250)(230,250){5} wire w7; //: /sn:0 {0}(251,248)(266,248)(266,260){1} wire s0; //: {0}(36:319,195)(349,195){1} wire w4; //: /sn:0 {0}(271,237)(271,260){1} wire c1; //: {0}(99:269,281)(269,300){1} wire w9; //: /sn:0 {0}(298,192)(270,192){1} //: {2}(266,192)(244,192){3} //: {4}(268,194)(268,216){5} //: enddecls //: LED g37 (s0) @(356,195) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(570,113) /sn:0 /anc:1 //: /line:"Hint: If a selection contains any" //: /line:"anchored gates, the entire selection" //: /line:"will act as if it were anchored." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(269,271) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(241,248) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(268, 192) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(150,153) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(271,227) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(213, 189) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(150,189) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(rotation and anchoring)" //: /line:"" //: /line:"You can rotate (with and ) and anchor (with and ) a group of gates in the same" //: /line:"way as you did for single gates in the Editing Gates chapter. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(309,195) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(234,192) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(150,224) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(273, 197) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(207, 224) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:182,149)(288,149)(288,191){1} //: {2}(290,193)(313,193){3} //: {4}(288,195)(288,212){5} reg a0; //: {0}(40:182,185)(226,185){1} //: {2}(230,185)(238,185){3} //: {4}(228,187)(228,241)(245,241){5} reg b0; //: {0}(50:182,220)(220,220){1} //: {2}(222,218)(222,190)(238,190){3} //: {4}(222,222)(222,246)(245,246){5} wire w7; //: /sn:0 {0}(266,244)(281,244)(281,256){1} wire s0; //: {0}(36:334,191)(364,191){1} wire w4; //: /sn:0 {0}(286,233)(286,256){1} wire c1; //: {0}(99:284,277)(284,296){1} wire w9; //: /sn:0 {0}(313,188)(285,188){1} //: {2}(281,188)(259,188){3} //: {4}(283,190)(283,212){5} //: enddecls //: LED g37 (s0) @(371,191) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(609,113) /sn:0 /anc:1 //: /line:"Hint: Click in a blank area to" //: /line:"unselect a group." //: /line:"" //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(284,267) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(256,244) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(283, 188) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(165,149) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(286,223) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(228, 185) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(165,185) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(selection and movement)" //: /line:"" //: /line:"To select a group of gates, press and hold the left mouse button above and to the left" //: /line:"of the group, then drag the cursor diagonally accross the group to open the selection box." //: /line:"Release the mouse when the selection box includes all of the gates you wish to select. Drag" //: /line:"any selected gate to move the entire group. Try it on the circuit below." //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(324,191) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(249,188) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(165,220) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(288, 193) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(222, 220) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] reg c0; //: {0}(18:174,160)(280,160)(280,202){1} //: {2}(282,204)(305,204){3} //: {4}(280,206)(280,223){5} reg a0; //: {0}(40:174,196)(196,196)(196,196)(218,196){1} //: {2}(222,196)(230,196){3} //: {4}(220,198)(220,252)(237,252){5} reg b0; //: {0}(50:174,231)(193,231)(193,231)(212,231){1} //: {2}(214,229)(214,201)(230,201){3} //: {4}(214,233)(214,257)(237,257){5} wire w7; //: /sn:0 {0}(258,255)(273,255)(273,267){1} wire s0; //: {0}(36:326,202)(356,202){1} wire w4; //: /sn:0 {0}(278,244)(278,267){1} wire c1; //: {0}(99:276,288)(276,307){1} wire w9; //: /sn:0 {0}(305,199)(277,199){1} //: {2}(273,199)(251,199){3} //: {4}(275,201)(275,223){5} //: enddecls //: LED g37 (s0) @(363,202) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g2 @(548,117) /sn:0 /anc:1 //: /line:"Hint: Hitting the Delete key will" //: /line:"delete all of the selected gates" //: /line:"without copying it to the clipboard." //: /end _GGNAND2 #(4) g1 (.I0(w7), .I1(w4), .Z(c1)); //: @(276,278) /sn:0 /R:3 /w:[ 1 1 0 ] _GGNAND2 #(4) g28 (.I0(a0), .I1(b0), .Z(w7)); //: @(248,255) /sn:0 /w:[ 5 5 0 ] //: joint g32 (w9) @(275, 199) /w:[ 1 -1 2 4 ] //: SWITCH g27 (c0) @(157,160) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g31 (.I0(w9), .I1(c0), .Z(w4)); //: @(278,234) /sn:0 /R:3 /w:[ 5 5 0 ] //: joint g29 (a0) @(220, 196) /w:[ 2 -1 1 4 ] //: SWITCH g25 (a0) @(157,196) /sn:0 /w:[ 0 ] /st:0 //: comment g5 @(10,10) /anc:1 //: /line:"

Group Editing Features

(clipboard operations)" //: /line:"" //: /line:"You can use Cut and Paste operations to cut or copy a group of gates to the clipboard" //: /line:"and paste it somewhere else. Select a group of gates then press the or buttons to" //: /line:"cut or copy, respectively, the selected gates to the clipboard. To paste the contents of the" //: /line:"clipboard, first set a with the left mouse button, then press the button to paste the" //: /line:"clipboard contents to that location." //: /line:"" //: /end _GGXOR2 #(8) g24 (.I0(w9), .I1(c0), .Z(s0)); //: @(316,202) /sn:0 /w:[ 0 3 0 ] _GGXOR2 #(8) g23 (.I0(a0), .I1(b0), .Z(w9)); //: @(241,199) /sn:0 /w:[ 3 3 3 ] //: SWITCH g26 (b0) @(157,231) /sn:0 /w:[ 0 ] /st:0 //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g33 (c0) @(280, 204) /w:[ 2 1 -1 4 ] //: joint g30 (b0) @(214, 231) /w:[ -1 2 1 4 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = ~(I0 & I1); endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/modules.v~000644 001751 001751 00000046447 11135014240 021740 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "module_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g3 @(259,83) /anc:1 //: /line:"A module is an encapsulated piece of logic that can be made" //: /line:"to serve a purpose in a circuit, similar to a function call" //: /line:"in a program. Each module in TkGate has an \"interface\" and" //: /line:"a \"definition\":" //: /line:"" //: /line:" * The interface describes the external" //: /line:" appearance of a module including the size of the box and" //: /line:" the positions of the ports on it. TkGate supports \"block\"" //: /line:" interfaces and \"symbol\" interfaces." //: /line:" " //: /line:" * The definition describes the internal" //: /line:" logic that the module implements. TkGate supports \"netlist\"" //: /line:" and \"HDL\" modules." //: /line:"" //: /end //: comment g2 @(10,65) /sn:0 /anc:1 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

" //: /line:"" //: /line:"In this chapter, you will learn how to create, edit and manage modules." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w4; //: /sn:0 {0}(258,177)(273,177){1} wire w0; //: /sn:0 {0}(200,161)(185,161){1} wire w3; //: /sn:0 {0}(258,161)(273,161){1} wire w1; //: /sn:0 {0}(200,177)(185,177){1} wire w2; //: /sn:0 {0}(200,192)(185,192){1} wire w5; //: /sn:0 {0}(258,193)(273,193){1} //: enddecls bar g4 (.C(w2), .B(w1), .A(w0), .Z(w5), .Y(w4), .X(w3)); //: @(201, 145) /sz:(56, 72) /sn:0 /p:[ Li0>0 Li1>0 Li2>0 Ro0<0 Ro1<0 Ro2<0 ] //: comment g3 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(editing module definitions)" //: /line:"" //: /line:"To edit the definition of a module you have created, double click on its name in the module name" //: /line:"tree or list view. Alternatively you can right click on an instance of the module and select" //: /line:"Open from the popup menu." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g4 @(576,89) /sn:0 /anc:1 //: /line:"Hint: The pages in this tutorial" //: /line:"are actually modules with the" //: /line:"names PAGE1, PAGE2, etc." //: /end //: comment g3 @(23,72) /sn:0 /anc:1 //: /line:" Top-level or root module." //: /line:"" //: /line:" Netlist module." //: /line:"" //: /line:" Verilog HDL module." //: /line:"" //: /line:" Locked netlist module." //: /line:"" //: /line:" Locked Verilog HDL module." //: /line:"" //: /line:" Container for unused modules." //: /line:"" //: /end //: comment g2 @(257,69) /anc:1 //: /line:" Library module." //: /line:"" //: /line:" Container for all libraries." //: /line:"" //: /line:" Container for a single library." //: /line:"" //: /line:" Use of an undefined module." //: /line:"" //: /line:" Recursive inclusion of a module." //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list symbols)" //: /line:"" //: /line:"The following symbols are used in the module tree and list view:" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ALU module ALU(F, A, B, Z); //: interface /sz:(40, 40) /bd:[ ] input [7:0] B; //: /sn:0 {0}(#:342,147)(342,184){1} //: {2}(344,186)(367,186){3} //: {4}(371,186)(425,186)(425,258){5} //: {6}(369,188)(369,261){7} //: {8}(342,188)(342,258){9} input [1:0] F; //: /sn:0 {0}(#:343,353)(214,353){1} input [7:0] A; //: /sn:0 {0}(#:265,147)(265,215){1} //: {2}(267,217)(345,217){3} //: {4}(349,217)(372,217){5} //: {6}(376,217)(457,217)(457,258){7} //: {8}(374,219)(374,261){9} //: {10}(347,219)(347,258){11} //: {12}(265,219)(265,322)(348,322)(348,337){13} supply0 w0; //: /sn:0 {0}(491,295)(491,272)(465,272){1} output [7:0] Z; //: /sn:0 {0}(#:366,404)(366,366){1} wire [7:0] w14; //: /sn:0 {0}(#:345,279)(345,310)(360,310)(360,337){1} wire w4; //: /sn:0 {0}(417,272)(407,272){1} wire [7:0] w11; //: /sn:0 {0}(#:372,282)(372,337){1} wire [7:0] w10; //: /sn:0 {0}(#:384,337)(384,307)(441,307)(441,287){1} //: enddecls //: joint g8 (A) @(347, 217) /w:[ 4 -1 3 10 ] _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4)); //: @(441,274) /sn:0 /w:[ 5 7 1 1 0 ] //: GROUND g13 (w0) @(491,301) /sn:0 /w:[ 0 ] //: IN g3 (F) @(212,353) /sn:0 /w:[ 1 ] //: IN g2 (A) @(265,145) /sn:0 /R:3 /w:[ 0 ] //: IN g1 (B) @(342,145) /sn:0 /R:3 /w:[ 0 ] //: joint g11 (B) @(369, 186) /w:[ 4 -1 3 6 ] //: joint g10 (A) @(374, 217) /w:[ 6 -1 5 8 ] _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11)); //: @(372,272) /sn:0 /R:3 /w:[ 7 9 0 ] /eb:0 //: joint g9 (A) @(265, 217) /w:[ 2 1 -1 12 ] _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14)); //: @(345,269) /sn:0 /R:3 /w:[ 9 11 0 ] /eb:0 //: OUT g5 (Z) @(366,401) /sn:0 /R:3 /w:[ 0 ] _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z)); //: @(366,353) /sn:0 /w:[ 13 1 1 0 0 1 ] /ss:0 /do:0 //: joint g12 (B) @(342, 186) /w:[ 2 1 -1 8 ] endmodule //: /netlistEnd //: /netlistBegin foo module foo(Z2, I3, Z1, I1, I2, Z3); //: interface /sz:(41, 40) /bd:[ ] input I2; //: /sn:0 {0}(245,200)(275,200){1} //: {2}(277,198)(277,153)(292,153){3} //: {4}(277,202)(277,248)(348,248){5} output Z3; //: /sn:0 {0}(369,251)(448,251){1} input I1; //: /sn:0 {0}(292,148)(278,148)(278,128)(246,128){1} output Z2; //: /sn:0 {0}(392,156)(380,156)(380,184){1} //: {2}(382,186)(448,186){3} //: {4}(378,186)(369,186){5} output Z1; //: /sn:0 {0}(448,154)(413,154){1} input I3; //: /sn:0 {0}(348,188)(296,188)(296,251){1} //: {2}(298,253)(348,253){3} //: {4}(294,253)(245,253){5} wire w0; //: /sn:0 {0}(348,183)(338,183)(338,153){1} //: {2}(340,151)(392,151){3} //: {4}(336,151)(313,151){5} //: enddecls //: OUT g4 (Z2) @(445,186) /sn:0 /w:[ 3 ] _GGAND2 #(6) g8 (.I0(I2), .I1(I3), .Z(Z3)); //: @(359,251) /sn:0 /w:[ 5 3 0 ] /eb:0 //: joint g13 (w0) @(338, 151) /w:[ 2 -1 4 1 ] //: IN g2 (I3) @(243,253) /sn:0 /w:[ 5 ] //: OUT g1 (Z1) @(445,154) /sn:0 /w:[ 0 ] _GGAND2 #(6) g11 (.I0(w0), .I1(Z2), .Z(Z1)); //: @(403,154) /sn:0 /w:[ 3 0 1 ] /eb:0 //: comment g16 @(585,127) /sn:0 //: /line:"Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end //: joint g10 (I2) @(277, 200) /w:[ -1 2 1 4 ] //: IN g19 (I1) @(244,128) /sn:0 /w:[ 1 ] _GGXOR2 #(8) g6 (.I0(I1), .I1(I2), .Z(w0)); //: @(303,151) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(I3), .Z(Z2)); //: @(359,186) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (I3) @(296, 253) /w:[ 2 1 4 -1 ] //: comment g15 @(22,25) //: /line:"This is the definition for module \"foo\"." //: /end //: IN g5 (I2) @(243,200) /sn:0 /w:[ 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: joint g23 (Z2) @(380, 186) /w:[ 2 1 4 -1 ] //: OUT g12 (Z3) @(445,251) /sn:0 /w:[ 1 ] endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(573,160) /sn:0 /anc:1 //: /line:"Hint: If you are unable to modify a" //: /line:"module interface, right click on it," //: /line:"select Module Properties..., then" //: /line:"unset the interface protection options" //: /line:"in the dialog box." //: /end foo g2 (); //: @(208, 163) /sz:(40, 40) /sn:0 /p:[ ] //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(manual interface generation)" //: /line:"" //: /line:"You can also manually create and edit the interface of a module:" //: /line:" * To change the size of the interface, left-click on an edge or corner and drag it with the mouse." //: /line:" * To add a port, right click on an edge and choose the port type to create from the popup menu." //: /line:" * To delete a port, select the tool and cut the wire off of the module." //: /line:" * To edit port properties, double click on the port with the tool." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire [7:0] w3; //: /sn:0 {0}(#:329,194)(314,194){1} wire [1:0] w0; //: /sn:0 {0}(#:257,226)(272,226){1} wire [7:0] w1; //: /sn:0 {0}(#:257,210)(272,210){1} wire [7:0] w2; //: /sn:0 {0}(#:257,194)(272,194){1} //: enddecls ALU g3 (.A(w2), .B(w1), .F(w0), .Z(w3)); //: @(273, 178) /sz:(40, 64) /sn:0 /p:[ Li0>1 Li1>1 Li2>1 Ro0<1 ] //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(updating the default interface)" //: /line:"" //: /line:"Module interfaces constructed in Edit mode, apply only to the specific instance that you created." //: /line:"To make an interface the default for newly created instance of modules of that type, right click" //: /line:"on an interface and select Interface → Set. Try setting the interface to each of the two instances of" //: /line:"ALU modules below, then try creating new ALU modules by dragging them from the module list." //: /end ALU g0 (); //: @(130, 184) /sz:(40, 40) /sn:0 /p:[ ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(automatic interface generation)" //: /line:"" //: /line:"The interface of a module includes the size and shape of the box as well as the location and names" //: /line:"of the ports. The easiest way to create an interface is to use automatic generation. Automatic" //: /line:"generation uses the ports referenced in the definition to create the interface. To automatically" //: /line:"create an interface for the \"bar\" module, first click on the module list tab , then right click on \"bar\"" //: /line:"and select Interface → Auto Generate... Now left click and drag the bar module onto the canvas to see" //: /line:"the new interface." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module definitions)" //: /line:"" //: /line:"To create a new module, press the button. Enter the name for the new module" //: /line:"and select whether you wish to create it as a \"netlist\" (graphical) module or an" //: /line:"HDL (textual) module. Try creating a new module named \"CPU\"." //: /end //: comment g0 @(10,310) /sn:0 /R:14 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(545,102) /sn:0 /anc:1 //: /line:"Hint: You can also drag and drop" //: /line:"module instance from the tree view," //: /line:"but it is easier to use the list view" //: /line:"since that view gives you a straight" //: /line:"alphabetical list of all module." //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(creating module instances)" //: /line:"" //: /line:"The easiest way to create a module instance is to find its name in the module list and" //: /line:"drag it into the current circuit. Try switching to the list view by pressing then" //: /line:"dragging several instances of the \"bar\" module into the current edit window." //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g3 @(548,6) /sn:0 /anc:1 //: /line:"" //: /end //: comment g2 @(554,346) /sn:0 /anc:1 //: /line:"Module Tree View Example" //: /end //: comment g1 @(9,13) /anc:1 //: /line:"

Using Modules

(module list)" //: /line:"" //: /line:"The set of modules in the current circuit is shown on the left-hand side of the interface. You" //: /line:"can choose between a tree view (see example) and a list view . The tree view shows" //: /line:"the module hierarchy starting at a top-level root module indicated by the symbol. Modules" //: /line:"which are still in the circuit, but are not used anywhere in the hierarchy are listed under the" //: /line:"\" Unused\" branch. Click on to open a branch on the tree." //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g2 @(10,310) /sn:0 /R:14 //: /line:"" //: /end //: comment g1 @(11,22) /anc:1 //: /line:"

Using Modules

(interface editor)" //: /line:"" //: /line:"You can directly edit the module interface using TkGate's interface mode. Click on the Interface" //: /line:"tab over the main canvas to enter this mode. Details on how to use this mode are given in the TkGate" //: /line:"documentation. Click on the Edit tab to return to the normal editing mode." //: /end endmodule //: /netlistEnd //: /netlistBegin bar module bar(Y, X, C, B, Z, A); //: interface /sz:(56, 72) /bd:[ Li0>C(48/72) Li1>B(32/72) Li2>A(16/72) Ro0Hint: If you opened this module by" //: /line:"choosing Open from the menu or" //: /line:"toolbar, you can close it by right" //: /line:"clicking in the canvas area and" //: /line:"selecting Close." //: /end _GGAND2 #(6) g11 (.I0(w0), .I1(Y), .Z(X)); //: @(244,161) /sn:0 /w:[ 3 0 5 ] /eb:0 //: joint g10 (B) @(118, 207) /w:[ -1 2 1 4 ] //: joint g19 (C) @(162, 260) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g6 (.I0(A), .I1(B), .Z(w0)); //: @(144,158) /sn:0 /w:[ 0 3 5 ] /eb:0 _GGXOR2 #(8) g7 (.I0(w0), .I1(C), .Z(Y)); //: @(200,193) /sn:0 /w:[ 0 0 5 ] /eb:0 //: joint g9 (C) @(137, 260) /w:[ 2 1 8 -1 ] //: comment g15 @(22,25) //: /line:"This is the definition for module \"bar\". Ports A, B and C are inputs, and ports X, Y and Z are" //: /line:"outputs. Try adding an additional output port \"W\" from the output of the XOR gate below." //: /line:"Right click at the position you want to create the port then select Make → Module → Module" //: /line:"Output from the popup menu. Enter \"W\" for the net name in the dialog box." //: /line:"" //: /line:"" //: /end _GGXOR2 #(8) g17 (.I0(C), .I1(X), .Z(w3)); //: @(293,129) /sn:0 /w:[ 7 3 0 ] //: comment g14 @(76,306) /sn:0 //: /line:"⟨BACK TO TUTORIAL⟩" //: /end //: OUT g5 (Z) @(343,258) /sn:0 /w:[ 1 ] //: IN g0 (A) @(84,135) /sn:0 /w:[ 1 ] //: joint g12 (Y) @(221, 193) /w:[ 2 1 4 -1 ] //: joint g18 (X) @(266, 161) /w:[ 1 2 4 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always @(*) begin case (S) 2'h0: Z <= #Dsz I0; 2'h1: Z <= #Dsz I1; 2'h2: Z <= #Dsz I2; 2'h3: Z <= #Dsz I3; default: Z <= #Dsz 2'h0; endcase end endmodule //: /builtinEnd //: /builtinBegin module _GGOR2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 | I1; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0; input [7:0] I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/advanced.v~000644 001751 001751 00000063662 11135014251 022035 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Advanced Editing Techniques

" //: /line:"" //: /line:"In this chapter you will learn some additional techniques to be more efficient at editing circuits" //: /line:"in TkGate." //: /end //: comment g0 @(150,93) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE6 module PAGE6(); //: interface /sz:(40, 40) /bd:[ ] wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Now try the same thing again, but this time drop the inverter input closer to the AND gate output" //: /line:"away from the joint. This time a new joint is automatically created." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(162,164)(202,164)(202,147)(227,147)(227,159)(252,159)(252,209)(178,209)(178,179){1} wire w4; //: /sn:0 {0}(131,166)(141,166){1} wire w0; //: /sn:0 {0}(131,161)(141,161){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(152,164) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Loop Deletion)" //: /line:"" //: /line:"Grab the endpoint of the XOR output wire in the circuit below. Drag it up until it crosses the" //: /line:"horizontal segment next to the gate and release it. TkGate will automatically remove the loop." //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE8 module PAGE8(); //: interface /sz:(40, 40) /bd:[ ] wire w46; //: /sn:0 {0}(421,254)(374,254)(374,196){1} //: {2}(376,194)(397,194)(397,127)(422,127){3} //: {4}(372,194)(339,194){5} wire w0; //: /sn:0 {0}(67,208)(82,208){1} wire w43; //: /sn:0 {0}(308,191)(318,191){1} wire w1; //: /sn:0 {0}(67,213)(82,213){1} wire w44; //: /sn:0 {0}(308,196)(318,196){1} wire w2; //: /sn:0 {0}(103,211)(130,211)(130,135){1} wire w48; //: /sn:0 {0}(438,127)(448,127){1} wire w47; //: /sn:0 {0}(437,254)(447,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGXOR2 #(8) g2 (.I0(w0), .I1(w1), .Z(w2)); //: @(93,211) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) hari (.I0(w43), .I1(w44), .Z(w46)); //: @(329,194) /sn:0 /anc:1 /w:[ 1 1 5 ] /eb:0 //: joint g50 (w46) @(374, 194) /anc:1 /w:[ 2 -1 4 1 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Rerouting)" //: /line:"" //: /line:"TkGate will automatically reroute wires that do not leave a gate or joint on the correct" //: /line:"direction. Try grabbing the wire indicated by the arrow in the two examples below and drag" //: /line:"them to the left. In the XOR gate example, two new wire segments are added. In the joint" //: /line:"example, one new segment is added, and the position on the joint is adjusted." //: /line:"" //: /end _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(427,254) /sn:0 /anc:1 /w:[ 0 0 ] //: comment g0 @(405,147) /sn:0 //: /line:"⇐" //: /end //: comment g12 @(141,164) /sn:0 //: /line:"⇐" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(428,127) /sn:0 /anc:1 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE9 module PAGE9(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(85,173)(100,173){1} wire w32; //: /sn:0 {0}(316,199)(316,214){1} wire w7; //: /sn:0 {0}(85,178)(100,178){1} wire w14; //: /sn:0 {0}(107,216)(122,216){1} wire w16; //: /sn:0 {0}(80,237)(95,237){1} wire w4; //: /sn:0 {0}(99,157)(114,157){1} wire w15; //: /sn:0 {0}(80,232)(95,232){1} wire w19; //: /sn:0 {0}(85,256)(100,256){1} wire w38; //: /sn:0 {0}(335,190)(335,205){1} wire w0; //: /sn:0 {0}(91,132)(106,132){1} wire w3; //: /sn:0 {0}(99,152)(114,152){1} wire w37; //: /sn:0 {0}(333,154)(333,169){1} wire w34; //: /sn:0 {0}(295,168)(295,183){1} wire w21; //: /sn:0 {0}(359,164)(359,179){1} wire w31; //: /sn:0 {0}(314,163)(314,178){1} wire w28; //: /sn:0 {0}(394,182)(394,197){1} wire w20; //: /sn:0 {0}(121,254)(136,254){1} wire w23; //: /sn:0 {0}(356,200)(356,215){1} wire w24; //: /sn:0 {0}(378,168)(378,183){1} wire w36; //: /sn:0 {0}(338,154)(338,169){1} wire w41; //: /sn:0 {0}(416,210)(416,225){1} wire w1; //: /sn:0 {0}(91,137)(106,137){1} wire w25; //: /sn:0 {0}(373,168)(373,183){1} wire w8; //: /sn:0 {0}(121,176)(136,176){1} wire w18; //: /sn:0 {0}(85,251)(100,251){1} wire w35; //: /sn:0 {0}(297,204)(297,219){1} wire w40; //: /sn:0 {0}(414,174)(414,189){1} wire w30; //: /sn:0 {0}(319,163)(319,178){1} wire w17; //: /sn:0 {0}(116,235)(131,235){1} wire w22; //: /sn:0 {0}(354,164)(354,179){1} wire w2; //: /sn:0 {0}(127,135)(142,135){1} wire w11; //: /sn:0 {0}(117,195)(132,195){1} wire w12; //: /sn:0 {0}(71,213)(86,213){1} wire w10; //: /sn:0 {0}(81,197)(96,197){1} wire w13; //: /sn:0 {0}(71,218)(86,218){1} wire w27; //: /sn:0 {0}(399,182)(399,197){1} wire w5; //: /sn:0 {0}(135,155)(150,155){1} wire w33; //: /sn:0 {0}(300,168)(300,183){1} wire w29; //: /sn:0 {0}(396,218)(396,233){1} wire w9; //: /sn:0 {0}(81,192)(96,192){1} wire w26; //: /sn:0 {0}(375,204)(375,219){1} wire w39; //: /sn:0 {0}(419,174)(419,189){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g8 (.I0(w21), .I1(w22), .Z(w23)); //: @(356,190) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g3 (.I0(w9), .I1(w10), .Z(w11)); //: @(107,195) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g13 (.I0(w33), .I1(w34), .Z(w35)); //: @(297,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g2 (.I0(w6), .I1(w7), .Z(w8)); //: @(111,176) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g1 (.I0(w3), .I1(w4), .Z(w5)); //: @(125,155) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g11 (.I0(w27), .I1(w28), .Z(w29)); //: @(396,208) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g10 (.I0(w24), .I1(w25), .Z(w26)); //: @(375,194) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g6 (.I0(w15), .I1(w16), .Z(w17)); //: @(106,235) /sn:0 /w:[ 1 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gate Alignment)" //: /line:"" //: /line:"You can align a group of gates by selecting them and then pressing the to align them vertically," //: /line:"and to align them horizontally. Try it on the groups of gates below." //: /end _GGAND2 #(6) g7 (.I0(w18), .I1(w19), .Z(w20)); //: @(111,254) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g15 (.I0(w39), .I1(w40), .Z(w41)); //: @(416,200) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g5 (.I0(w12), .I1(w13), .Z(w14)); //: @(97,216) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g14 (.I0(w36), .I1(w37), .Z(w38)); //: @(335,180) /sn:0 /R:3 /w:[ 1 1 0 ] _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(w2)); //: @(117,135) /sn:0 /w:[ 1 1 0 ] _GGAND2 #(6) g12 (.I0(w30), .I1(w31), .Z(w32)); //: @(316,189) /sn:0 /R:3 /w:[ 1 1 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE7 module PAGE7(); //: interface /sz:(40, 40) /bd:[ ] wire w7; //: /sn:0 {0}(85,137)(95,137){1} wire w19; //: /sn:0 {0}(322,140)(332,140){1} wire w21; //: /sn:0 {0}(321,242)(331,242){1} wire w20; //: /sn:0 {0}(305,242)(288,242)(288,140)(306,140){1} wire w18; //: /sn:0 {0}(162,245)(172,245){1} wire w40; //: /sn:0 {0}(193,243)(203,243){1} wire w17; //: /sn:0 {0}(172,240)(153,240)(153,140)(116,140){1} wire w9; //: /sn:0 {0}(85,142)(95,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(183,243) /sn:0 /anc:1 /w:[ 0 1 0 ] /eb:0 //: comment g1 @(120,178) /sn:0 /anc:1 //: /line:"⇒" //: /end _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(312,140) /sn:0 /anc:1 /w:[ 1 0 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Wire Segments)" //: /line:"" //: /line:"Sometime there may not be a free end of two wires you want to connect. Right click on the" //: /line:"wire connected to the AND gate output at the position indicated by the arrow. Select the" //: /line:"Add Wire Segment option from the popup menu. You can now connect" //: /line:"the newly created wire to the buffer inputs." //: /line:"" //: /end _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(106,140) /sn:0 /anc:1 /w:[ 1 1 1 ] /eb:0 _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(311,242) /sn:0 /anc:1 /w:[ 0 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE5 module PAGE5(); //: interface /sz:(40, 40) /bd:[ ] wire w24; //: /sn:0 {0}(319,194)(254,194){1} //: {2}(252,192)(252,134)(318,134){3} //: {4}(250,194)(187,194){5} wire w23; //: /sn:0 {0}(309,247)(319,247){1} wire w25; //: /sn:0 {0}(334,134)(344,134){1} wire w22; //: /sn:0 {0}(156,196)(166,196){1} wire w10; //: /sn:0 {0}(156,191)(166,191){1} wire w27; //: /sn:0 {0}(335,247)(345,247){1} wire w26; //: /sn:0 {0}(335,194)(345,194){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(325,194) /sn:0 /w:[ 0 0 ] //: joint g27 (w24) @(252, 194) /w:[ 1 2 4 -1 ] //: comment g9 @(10,9) /anc:1 //: /line:"

Wire Editing

(Joint Creation)" //: /line:"" //: /line:"Select the tool and drag the input of the inverter in the circuit below. Drag the input close" //: /line:"to the joint in the middle of the AND gate output and release it. The wire should attach itself to" //: /line:"the joint." //: /line:"" //: /end _GGNBUF #(2) g29 (.I(w23), .Z(w27)); //: @(325,247) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(177,194) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(324,134) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd //: /netlistBegin PAGE4 module PAGE4(); //: interface /sz:(40, 40) /bd:[ ] wire w6; //: /sn:0 {0}(325,245)(373,245){1} //: {2}(377,245)(468,245){3} //: {4}(375,243)(375,163)(436,163){5} wire w7; //: /sn:0 {0}(421,158)(436,158){1} wire w4; //: /sn:0 {0}(289,247)(304,247){1} wire w3; //: /sn:0 {0}(61,247)(108,247){1} //: {2}(112,247)(199,247){3} //: {4}(110,245)(110,161)(169,161){5} wire w0; //: /sn:0 {0}(289,242)(304,242){1} wire w1; //: /sn:0 {0}(30,244)(40,244){1} wire w8; //: /sn:0 {0}(190,159)(200,159){1} wire w2; //: /sn:0 {0}(30,249)(40,249){1} wire w10; //: /sn:0 {0}(457,161)(472,161){1} wire w5; //: /sn:0 {0}(159,156)(169,156){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: joint g3 (w3) @(110, 247) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(180,159) /sn:0 /anc:1 /w:[ 1 5 0 ] /eb:0 _GGOR2 #(6) g1 (.I0(w0), .I1(w4), .Z(w6)); //: @(315,245) /sn:0 /anc:1 /w:[ 1 1 0 ] //: comment g11 @(363,264) /sn:0 /anc:1 //: /line:"OR Gate Circuit" //: /end //: comment g10 @(70,271) /sn:0 /anc:1 //: /line:"AND Gate Circuit" //: /end //: joint g6 (w6) @(375, 245) /w:[ 2 4 1 -1 ] //: comment g7 @(413,213) /sn:0 /anc:1 //: /line:"⇓" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Automatic Wire Cleanup)" //: /line:"" //: /line:"Select the tool and cut the wire at the position indicated by the arrow in the AND Gate" //: /line:"Circuit. TkGate will automatically remove the wire joint. Now cut the wire at the position indicated" //: /line:"by the arrow in the OR Gate Circuit. The free wire end is automatically deleted." //: /line:"" //: /end _GGOR2 #(6) g5 (.I0(w7), .I1(w6), .Z(w10)); //: @(447,161) /sn:0 /anc:1 /w:[ 1 5 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(51,247) /sn:0 /anc:1 /w:[ 1 1 0 ] /eb:0 //: comment g12 @(123,184) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] wire w14; //: /sn:0 {0}(292,263)(226,263)(226,200)(245,200)(245,140)(178,140){1} wire w16; //: /sn:0 {0}(313,266)(323,266){1} wire w15; //: /sn:0 {0}(282,268)(292,268){1} wire w11; //: /sn:0 {0}(147,137)(157,137){1} wire w12; //: /sn:0 {0}(147,142)(157,142){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(303,266) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(168,140) /sn:0 /w:[ 1 1 1 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Gravity)" //: /line:"" //: /line:"Click on the wire indicated by the arrow in the circuit below and drag it until it is nearly" //: /line:"alligned with the other vertical segment. When you release the wire, \"gravity\" will cause" //: /line:"the two vertical segments to snap together into a single segment." //: /line:"" //: /end //: comment g0 @(562,122) /sn:0 /anc:1 //: /line:"Hint: You can disable the automatic" //: /line:"cleanup features in wire editing by" //: /line:"holding the Alt key while moving wires." //: /end //: comment g12 @(252,158) /sn:0 /anc:1 //: /line:"⇐" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE10 module PAGE10(); //: interface /sz:(40, 40) /bd:[ ] reg crete; //: {0}(7:215,136)(359,136)(359,189){1} //: {2}(361,191)(416,191){3} //: {4}(359,193)(359,203){5} reg ithaca; //: {0}(18:215,183)(259,183){1} //: {2}(263,183)(271,183){3} //: {4}(261,185)(261,238)(278,238){5} reg toledo; //: {0}(-21:213,243)(254,243){1} //: {2}(258,243)(278,243){3} //: {4}(256,241)(256,188)(271,188){5} wire styx; //: {0}(99:355,275)(355,295){1} wire athens; //: {0}(416,186)(356,186){1} //: {2}(71:352,186)(292,186){3} //: {4}(354,188)(354,203){5} wire pheneos; //: {0}(76:357,224)(357,254){1} wire olympus; //: {0}(-15:437,189)(506,189){1} wire delphi; //: {0}(-22:299,241)(352,241)(352,254){1} //: enddecls //: comment g4 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end //: LED g37 (olympus) @(513,189) /sn:0 /R:3 /w:[ 1 ] /type:0 _GGXOR2 #(8) Athena (.I0(ithaca), .I1(toledo), .Z(athens)); //: @(282,186) /w:[ 3 5 3 ] /eb:0 _GGNAND2 #(4) Hermes (.I0(athens), .I1(crete), .Z(pheneos)); //: @(357,214) /R:3 /w:[ 5 5 0 ] /eb:0 _GGNAND2 #(4) Hades (.I0(delphi), .I1(pheneos), .Z(styx)); //: @(355,265) /R:3 /w:[ 1 1 0 ] /eb:0 _GGXOR2 #(8) Zeus (.I0(athens), .I1(crete), .Z(olympus)); //: @(427,189) /w:[ 0 3 0 ] /eb:0 //: joint g32 (athens) @(354, 186) /w:[ 1 -1 2 4 ] //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

(Search)" //: /line:"" //: /line:"You can search your circuit for a wire or gate with a specific name by using the search tool. Click" //: /line:"on the tool to open it. The list of matches will by dynamically updated as you type the target" //: /line:"string. Double click on an entry in the Search Results to go to that object. Try using the search" //: /line:"tool to search for some of the wire and gate names in the circuit below." //: /line:"" //: /end //: joint g29 (ithaca) @(261, 183) /w:[ 2 -1 1 4 ] //: SWITCH Bob (toledo) @(196,243) /w:[ 0 ] /st:0 //: SWITCH Thesus (crete) @(198,136) /w:[ 0 ] /st:0 _GGNAND2 #(4) Apollo (.I0(ithaca), .I1(toledo), .Z(delphi)); //: @(289,241) /w:[ 5 3 0 ] /eb:0 //: SWITCH Odyseus (ithaca) @(198,183) /w:[ 0 ] /st:0 //: comment g0 @(588,148) /sn:0 //: /line:"Hint: The search tool will look" //: /line:"in all modules of your circuit for" //: /line:"the target string. Try searching for" //: /line:"a gate named \"hari\"." //: /end //: joint g33 (crete) @(359, 191) /w:[ 2 1 -1 4 ] //: joint g30 (toledo) @(256, 243) /w:[ 2 4 1 -1 ] endmodule //: /netlistEnd //: /netlistBegin OLD module OLD(); //: interface /sz:(40, 40) /bd:[ ] wire w32; //: /sn:0 {0}(624,293)(634,293){1} wire w6; //: /sn:0 {0}(476,150)(516,150)(516,133)(541,133)(541,145)(566,145)(566,195)(492,195)(492,165){1} wire w7; //: /sn:0 {0}(470,428)(480,428){1} wire w46; //: /sn:0 {0}(724,568)(681,568)(681,559){1} //: {2}(683,557)(697,557)(697,519)(722,519){3} //: {4}(679,557)(646,557){5} wire w16; //: /sn:0 {0}(543,101)(553,101){1} wire w14; //: /sn:0 {0}(522,98)(512,98)(512,79)(531,79)(531,46)(478,46){1} wire w19; //: /sn:0 {0}(604,430)(614,430){1} wire w15; //: /sn:0 {0}(512,103)(522,103){1} wire w4; //: /sn:0 {0}(445,152)(455,152){1} wire w38; //: /sn:0 {0}(747,392)(757,392){1} wire w3; //: /sn:0 {0}(475,285)(516,285){1} //: {2}(520,285)(573,285){3} //: {4}(518,283)(518,239)(548,239){5} wire w0; //: /sn:0 {0}(445,147)(455,147){1} wire w37; //: /sn:0 {0}(721,392)(731,392){1} wire w34; //: /sn:0 {0}(744,361)(754,361){1} wire w21; //: /sn:0 {0}(604,468)(614,468){1} wire w43; //: /sn:0 {0}(615,554)(625,554){1} wire w31; //: /sn:0 {0}(624,288)(634,288){1} wire w28; //: /sn:0 {0}(655,291)(696,291){1} //: {2}(700,291)(753,291){3} //: {4}(698,289)(698,245)(728,245){5} wire w23; //: /sn:0 {0}(537,388)(547,388){1} wire w41; //: /sn:0 {0}(492,556)(502,556){1} wire w36; //: /sn:0 {0}(632,363)(642,363){1} wire w20; //: /sn:0 {0}(588,468)(576,468)(576,430)(588,430){1} wire w24; //: /sn:0 {0}(547,360)(524,360){1} //: {2}(522,358)(522,329)(548,329){3} //: {4}(520,360)(482,360){5} wire w1; //: /sn:0 {0}(444,282)(454,282){1} wire w25; //: /sn:0 {0}(564,329)(574,329){1} wire w35; //: /sn:0 {0}(632,358)(642,358){1} wire w8; //: /sn:0 {0}(569,237)(579,237){1} wire w40; //: /sn:0 {0}(554,475)(564,475){1} wire w18; //: /sn:0 {0}(523,477)(533,477){1} wire w30; //: /sn:0 {0}(749,243)(759,243){1} wire w22; //: /sn:0 {0}(451,362)(461,362){1} wire w17; //: /sn:0 {0}(533,472)(517,472)(517,431)(501,431){1} wire w2; //: /sn:0 {0}(444,287)(454,287){1} wire w44; //: /sn:0 {0}(615,559)(625,559){1} wire w12; //: /sn:0 {0}(447,48)(457,48){1} wire w11; //: /sn:0 {0}(447,43)(457,43){1} wire w10; //: /sn:0 {0}(451,357)(461,357){1} wire w27; //: /sn:0 {0}(563,388)(573,388){1} wire w13; //: /sn:0 {0}(492,551)(502,551){1} wire w48; //: /sn:0 {0}(738,519)(748,519){1} wire w5; //: /sn:0 {0}(538,234)(548,234){1} wire w33; //: /sn:0 {0}(728,361)(705,361){1} //: {2}(703,359)(703,330)(729,330){3} //: {4}(701,361)(663,361){5} wire w47; //: /sn:0 {0}(740,568)(750,568){1} wire w29; //: /sn:0 {0}(718,240)(728,240){1} wire w9; //: /sn:0 {0}(470,433)(480,433){1} wire w42; //: /sn:0 {0}(523,554)(541,554)(541,518){1} wire w39; //: /sn:0 {0}(745,330)(755,330){1} wire w26; //: /sn:0 {0}(563,360)(573,360){1} //: enddecls //: comment g4 @(10,552) /sn:0 /R:14 //: /line:"<PREVIOUS UP NEXT>" //: /end _GGXOR2 #(8) g8 (.I0(w0), .I1(w4), .Z(w6)); //: @(466,150) /sn:0 /w:[ 1 1 0 ] /eb:0 //: frame g51 @(442,505) /sn:0 /wi:145 /ht:74 /tx:"Fig. 6a" //: joint g37 (w33) @(703, 361) /w:[ 1 2 4 -1 ] //: frame g34 @(437,317) /sn:0 /wi:160 /ht:88 /tx:"Fig. 4a" //: joint g3 (w3) @(518, 285) /w:[ 2 4 1 -1 ] _GGOR2 #(6) g13 (.I0(w17), .I1(w18), .Z(w40)); //: @(544,475) /sn:0 /w:[ 0 1 0 ] /eb:0 _GGAND2 #(6) g2 (.I0(w5), .I1(w3), .Z(w8)); //: @(559,237) /sn:0 /w:[ 1 5 0 ] /eb:0 //: comment g1 @(542,55) /sn:0 //: /line:"<---" //: /end _GGAND2 #(6) g11 (.I0(w14), .I1(w15), .Z(w16)); //: @(533,101) /sn:0 /w:[ 0 1 0 ] /eb:0 //: joint g50 (w46) @(681, 557) /w:[ 2 -1 4 1 ] _GGBUF #(4) g28 (.I(w24), .Z(w26)); //: @(553,360) /sn:0 /w:[ 0 0 ] _GGAND2 #(6) g10 (.I0(w11), .I1(w12), .Z(w14)); //: @(468,46) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g32 (.I0(w29), .I1(w28), .Z(w30)); //: @(739,243) /sn:0 /w:[ 1 5 0 ] /eb:0 //: joint g27 (w24) @(522, 360) /w:[ 1 2 4 -1 ] _GGBUF #(4) g19 (.I(w20), .Z(w19)); //: @(594,430) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g38 (.I0(w35), .I1(w36), .Z(w33)); //: @(653,361) /sn:0 /w:[ 1 1 5 ] /eb:0 //: comment g9 @(10,10) /anc:1 //: /line:"

Wire Editing

" //: /line:"" //: /line:"1) Click on the wire in Fig. 1, drag it until it is nearly alligned" //: /line:"with the other vertical segment and release it. \"Gravity\" will cause" //: /line:"them to snap together into a single segment." //: /line:"" //: /line:"2) Grab the endpoint of the XOR output wire in Fig. 2, drag it up so that" //: /line:"it crosses the horizontal segment next to the gate and release it. TkGate" //: /line:"will automatically remove the loop." //: /line:"" //: /line:"3) Press and click on the vertical wire segment in Fig. 3a. TkGate will" //: /line:"automatically remove the wire joint. Now, click at the point indicated by" //: /line:"the arrow in Fig. 3b. The free wire end is automatically deleted." //: /line:"" //: /line:"4) Press then select and drag the input of the bottom buffer in Fig. 4a" //: /line:"next to the wire joint and release it to connect it to the joint. Try again in" //: /line:"Fig. 4b, this time releasing it between the AND gate and the joint to" //: /line:"create a new joint." //: /line:"" //: /line:"5) Right click on the vertical segment indicated by the arrow in Fig. 5" //: /line:"and select Add Wire Segment from the popup menu. Grab the new wire" //: /line:"end and drag it to the other horizontal segment and release it." //: /line:"" //: /line:"6) In Figs. 6a and 6b, select the wire at the point indicated by the" //: /line:"arrows and drag them left past the output point of the AND gate and" //: /line:"past the position of the joint. Tkgate will reroute the wires as necessary." //: /line:"" //: /line:"" //: /line:"" //: /line:" Hint: You can disable the automatic cleanup features in wire" //: /line:" editing by holding the Alt key while moving wires." //: /end //: joint g31 (w28) @(698, 291) /w:[ 2 4 1 -1 ] _GGAND2 #(6) g39 (.I0(w13), .I1(w41), .Z(w42)); //: @(513,554) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGBUF #(4) g48 (.I(w46), .Z(w47)); //: @(730,568) /sn:0 /w:[ 0 0 ] //: frame g43 @(617,222) /sn:0 /wi:160 /ht:85 /tx:"Fig. 3b" _GGBUF #(4) g29 (.I(w23), .Z(w27)); //: @(553,388) /sn:0 /w:[ 1 0 ] _GGAND2 #(6) g25 (.I0(w10), .I1(w22), .Z(w24)); //: @(472,360) /sn:0 /w:[ 1 1 5 ] /eb:0 //: frame g52 @(597,507) /sn:0 /wi:189 /ht:73 /tx:"Fig. 6b" //: frame g42 @(437,221) /sn:0 /wi:163 /ht:83 /tx:"Fig. 3a" _GGAND2 #(6) g5 (.I0(w7), .I1(w9), .Z(w17)); //: @(491,431) /sn:0 /w:[ 1 1 1 ] /eb:0 _GGAND2 #(6) g47 (.I0(w43), .I1(w44), .Z(w46)); //: @(636,557) /sn:0 /w:[ 1 1 5 ] /eb:0 _GGBUF #(4) g44 (.I(w37), .Z(w38)); //: @(737,392) /sn:0 /w:[ 1 0 ] _GGBUF #(4) g36 (.I(w33), .Z(w34)); //: @(734,361) /sn:0 /w:[ 0 0 ] //: comment g24 @(485,442) /sn:0 //: /line:"--->" //: /end //: frame g41 @(436,127) /sn:0 /wi:141 /ht:77 /tx:"Fig. 2" _GGBUF #(4) g23 (.I(w20), .Z(w21)); //: @(594,468) /sn:0 /w:[ 0 0 ] //: frame g40 @(434,30) /sn:0 /wi:147 /ht:86 /tx:"Fig. 1" //: frame g46 @(440,416) /sn:0 /wi:190 /ht:75 /tx:"Fig. 5" _GGBUF #(4) g45 (.I(w33), .Z(w39)); //: @(735,330) /sn:0 /w:[ 3 0 ] //: frame g35 @(618,318) /sn:0 /wi:159 /ht:88 /tx:"Fig. 4b" _GGBUF #(4) g26 (.I(w24), .Z(w25)); //: @(554,329) /sn:0 /w:[ 3 0 ] _GGAND2 #(6) g0 (.I0(w1), .I1(w2), .Z(w3)); //: @(465,285) /sn:0 /w:[ 1 1 0 ] /eb:0 _GGAND2 #(6) g33 (.I0(w31), .I1(w32), .Z(w28)); //: @(645,291) /sn:0 /w:[ 1 1 0 ] /eb:0 //: comment g30 @(723,257) /sn:0 //: /line:"|" //: /line:"v" //: /end _GGBUF #(4) g49 (.I(w46), .Z(w48)); //: @(728,519) /sn:0 /w:[ 3 0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/combinational1.v~000644 001751 001751 00000001363 11135014260 023156 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

" //: /line:"" //: /line:"TkGate uses a Verilog-based discrete event simulator to simulate your circuit description. In this" //: /line:"chapter the basics needed to simulate a combinational circuit will be presented." //: /end //: comment g0 @(191,165) /sn:0 /anc:1 //: /line:"" //: /end //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/tutorials/sequential1.v~000644 001751 001751 00000001340 11135014266 022512 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

" //: /line:"" //: /line:"This chapter builds on the previous chapter about simulating combinational circuits and introduces" //: /line:"simulator features that are useful for simulating sequential circuits." //: /end //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(208,188) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/tutorials/verilog.v~000644 001751 001751 00000006221 11135014272 021726 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "texver_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"The TkGate simulator is based on the Verilog hardware description language. As such, any" //: /line:"modules you design using the graphical editor are translated into Verilog before being simulated." //: /line:"You can also write modules directly in Verilog. Note that this chapter is not designed to teach" //: /line:"Verilog, but rather to teach how to include Verilog modules in TkGate." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g0 @(145,107) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /hdlBegin foo //: interface /sz:(55, 80) /bd:[ Li0>a(16/80) Li1>b(32/80) Li2>c(48/80) Li3>d(64/80) Ro0 and set the type to HDL." //: /end //: comment g7 @(10,310) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g9 @(8,9) /anc:1 //: /line:"

Textual Verilog

" //: /line:"" //: /line:"1) Right click on the module below and select Open." //: /end //: LED g5 (w4) @(246,131) /sn:0 /w:[ 1 ] /type:0 foo g0 (.a(w5), .b(w6), .c(w7), .d(w8), .z(w4)); //: @(164, 113) /sz:(55, 80) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>1 Ro0<0 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/options.v~000644 001751 001751 00000004613 11135014277 021762 0ustar00hansenhansen000000 000000 //: version "2.0-a8" //: property prefix = "_GG" //: property title = "options.v" //: property discardChanges = 1 //: require "tty" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module //: enddecls //: comment g1 @(219,134) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

" //: /line:"" //: /line:"This chapter introduces some of the options that can be customized in TkGate. Your option settings" //: /line:"are stored in a file named \".tkgate2-preferences\" in your home directory." //: /line:"" //: /line:"" //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE3 module PAGE3(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(134,181) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your key beinding style)" //: /line:"" //: /line:"You can the basic key-binding style that you would like to use on the Interface tab of the options dialog" //: /line:"box. Currently you can choose between \"emacs\"-style and \"Windows\"-style. Chosing one of these" //: /line:"options will make key bindings for operations such as cut/paste similar to either emacs or Windows," //: /line:"although key bindings for gate creation operations will remain the same." //: /end //: comment g0 @(10,310) /sn:0 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin PAGE2 module PAGE2(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls //: comment g1 @(116,149) /sn:0 /anc:1 //: /line:"" //: /end //: comment g9 @(10,10) /anc:1 //: /line:"

Customizing TkGate

(setting your personal identification)" //: /line:"" //: /line:"To set your TkGate options, open the options dilaog box by selecting File → Options from the" //: /line:"main menu. Enter your site name and user name in the \"Identity\" dialog box. The values you enter" //: /line:"here will be used on any printed output from TkGate." //: /end //: comment g0 @(10,310) /sn:0 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/tutorials/combinational2.v~000644 001751 001751 00000006670 11135014314 023165 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:153,316)(167,316){1} //: {2}(171,316)(189,316){3} //: {4}(193,316)(241,316){5} //: {6}(191,314)(191,253)(236,253){7} //: {8}(169,314)(169,304){9} reg A; //: {0}(236,248)(204,248){1} //: {2}(202,246)(-86:202,228)(172,228){3} //: {4}(170,226)(170,215){5} //: {6}(168,228)(155,228){7} //: {8}(202,250)(202,311)(241,311){9} reg Cin; //: {0}(271,213)(291,213){1} //: {2}(293,211)(293,202){3} //: {4}(41:293,215)(293,244){5} //: {6}(295,246)(333,246){7} //: {8}(293,248)(293,272){9} wire w6; //: /sn:0 {0}(334,314)(262,314){1} wire w0; //: /sn:0 {0}(334,309)(291,309)(291,293){1} wire w1; //: /sn:0 {0}(333,251)(290,251){1} //: {2}(286,251)(257,251){3} //: {4}(288,253)(288,272){5} wire C; //: {0}(-21:403,221)(403,312)(355,312){1} wire S; //: {0}(354,249)(-39:373,249)(373,221){1} //: enddecls _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(247,251) /sn:0 /w:[ 0 7 3 ] _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(345,312) /sn:0 /w:[ 0 0 1 ] //: SWITCH g3 (Cin) @(254,213) /sn:0 /w:[ 0 ] /st:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(starting the simulator)" //: /line:"" //: /line:"Press the \" Simulate\" tab above the main canvas to enter simulation mode. When you first enter simulation" //: /line:"mode, the simulator will be paused as indicated by the depressed button on the simulator tool bar. Press" //: /line:"the button to begin simulation. Now try clicking on the switches to change their state and observe how the" //: /line:"LEDs change. When you are done, stop the simulator by pressing and go on to the next page." //: /end _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(252,314) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(136,316) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(288, 251) /w:[ 1 -1 2 4 ] //: joint g10 (Cin) @(293, 246) /w:[ 6 5 -1 8 ] //: LED g28 (A) @(170,208) /sn:0 /w:[ 5 ] /type:0 //: joint g27 (Cin) @(293, 213) /w:[ -1 2 1 4 ] //: joint g6 (B) @(191, 316) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(344,249) /sn:0 /w:[ 7 0 0 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(291,283) /sn:0 /R:3 /w:[ 5 9 1 ] //: joint g31 (A) @(170, 228) /w:[ 3 4 6 -1 ] //: LED g25 (C) @(403,214) /sn:0 /w:[ 0 ] /type:0 //: LED g29 (B) @(169,297) /sn:0 /w:[ 9 ] /type:0 //: joint g5 (A) @(202, 248) /w:[ 1 2 -1 8 ] //: SWITCH g0 (A) @(138,228) /sn:0 /w:[ 7 ] /st:0 //: LED g26 (Cin) @(293,195) /sn:0 /w:[ 3 ] /type:0 //: LED g18 (S) @(373,214) /sn:0 /w:[ 1 ] /type:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: joint g30 (B) @(169, 316) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/combinational3.v~000644 001751 001751 00000007671 11135014317 023173 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg B; //: {0}(50:140,305)(154,305){1} //: {2}(158,305)(176,305){3} //: {4}(180,305)(228,305){5} //: {6}(178,303)(178,242)(223,242){7} //: {8}(156,303)(156,293){9} reg A; //: {0}(223,237)(191,237){1} //: {2}(189,235)(-86:189,217)(159,217){3} //: {4}(157,215)(157,204){5} //: {6}(155,217)(142,217){7} //: {8}(189,239)(189,300)(228,300){9} reg Cin; //: {0}(258,202)(278,202){1} //: {2}(280,200)(280,191){3} //: {4}(48:280,204)(280,233){5} //: {6}(282,235)(320,235){7} //: {8}(280,237)(280,261){9} wire w6; //: /sn:0 {0}(321,303)(249,303){1} wire w0; //: /sn:0 {0}(321,298)(278,298)(278,282){1} wire w1; //: /sn:0 {0}(320,240)(277,240){1} //: {2}(273,240)(244,240){3} //: {4}(275,242)(275,261){5} wire C; //: {0}(-21:390,210)(390,301)(342,301){1} wire S; //: {0}(341,238)(-39:360,238)(360,210){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w0), .I1(w6), .Z(C)); //: @(332,301) /sn:0 /w:[ 0 0 1 ] _GGXOR2 #(8) g4 (.I0(A), .I1(B), .Z(w1)); //: @(234,240) /sn:0 /w:[ 0 7 3 ] //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(setting probes)" //: /line:"" //: /line:"Press the \" Simulate\" tab again, to enter simulation mode. This time right click on a wire (e.g., the" //: /line:"one labeled \"S\") and slect \"Add/Delete Probe\" from the popup menu. The will set a probe on that" //: /line:"wire and bring up the logic analyzer window. Set probes on some more wires, then unpause the" //: /line:"simulator by pressing . Click on the switches to change their state and observe how the logic" //: /line:"analyzer is updated." //: /end //: SWITCH g3 (Cin) @(241,202) /sn:0 /w:[ 0 ] /st:1 _GGNAND2 #(4) g2 (.I0(A), .I1(B), .Z(w6)); //: @(239,303) /sn:0 /w:[ 9 5 1 ] //: SWITCH g1 (B) @(123,305) /sn:0 /w:[ 0 ] /st:1 //: joint g11 (w1) @(275, 240) /w:[ 1 -1 2 4 ] //: LED g28 (A) @(157,197) /sn:0 /w:[ 5 ] /type:0 //: joint g10 (Cin) @(280, 235) /w:[ 6 5 -1 8 ] //: joint g27 (Cin) @(280, 202) /w:[ -1 2 1 4 ] //: joint g6 (B) @(178, 305) /w:[ 4 6 3 -1 ] _GGNAND2 #(4) g9 (.I0(w1), .I1(Cin), .Z(w0)); //: @(278,272) /sn:0 /R:3 /w:[ 5 9 1 ] _GGXOR2 #(8) g7 (.I0(Cin), .I1(w1), .Z(S)); //: @(331,238) /sn:0 /w:[ 7 0 0 ] //: joint g31 (A) @(157, 217) /w:[ 3 4 6 -1 ] //: comment g15 @(585,254) /sn:0 /anc:1 //: /line:"Hint: Normally, TkGate will simulate" //: /line:"combinational circuits until all signals" //: /line:"have reached a steady state. You can" //: /line:"hit the space bar to advance the" //: /line:"simulator by one time unit." //: /end //: LED g29 (B) @(156,286) /sn:0 /w:[ 9 ] /type:0 //: LED g25 (C) @(390,203) /sn:0 /w:[ 0 ] /type:0 //: comment g14 @(583,172) /sn:0 /anc:1 //: /line:"Hint: In addition to using probes," //: /line:"you can also see the value of a net" //: /line:"by clicking and holding the mouse" //: /line:"button down for a few seconds." //: /end //: joint g5 (A) @(189, 237) /w:[ 1 2 -1 8 ] //: LED g26 (Cin) @(280,184) /sn:0 /w:[ 3 ] /type:0 //: SWITCH g0 (A) @(125,217) /sn:0 /w:[ 7 ] /st:0 //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: LED g18 (S) @(360,203) /sn:0 /w:[ 1 ] /type:0 //: joint g30 (B) @(156, 305) /w:[ 2 8 1 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/combinational4.v~000644 001751 001751 00000014150 11135014322 023156 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "sim_tut.v" //: property useExtBars = 0 //: property discardChanges = 1 //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [3:0] w6; //: /sn:0 {0}(#:171,282)(201,282)(201,262)(244,262){1} reg w1; //: /sn:0 {0}(279,220)(279,186){1} reg [3:0] w5; //: /sn:0 {0}(#:168,209)(203,209)(203,237)(244,237){1} wire [3:0] w4; //: /sn:0 {0}(#:310,248)(357,248)(357,228){1} wire w0; //: /sn:0 {0}(277,319)(277,286){1} //: enddecls //: LED g4 (w4) @(357,221) /sn:0 /w:[ 1 ] /type:1 //: comment g13 @(10,10) /anc:1 //: /line:"

Combinational Circuit Simulation

(dip switches)" //: /line:"" //: /line:"To change the value of a dip while simulating a circuit, first click on it to open a value dialog" //: /line:"box. Then enter the new value in hexidecimal and click Apply. Start the simulator then try" //: /line:"changing the input values in the four-bit adder below and observe the output." //: /end //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(560,127) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>B[3:0](41/64) Li1>A[3:0](16/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>B(34/50) Li1>A(12/50) Bo0Combinational Circuit Simulation (the instance hierarchy)" //: /line:"" //: /line:"While the simulator is active, the hierarchical module list displays the hierarchy by instance" //: /line:"rather than by module. This is because the state (i.e., net values) for each instance of a module" //: /line:"in the hierarcy may be different. Invoke and unpause the simulation for the circuit below, then" //: /line:"try examining the nets in different instances of the ADD1 module. Double click on \"g0<ADD1>\"," //: /line:"\"g1<ADD1>\", etc. in the the hierarchical list box to go to each instance." //: /line:"" //: /end //: SWITCH g3 (w1) @(279,173) /sn:0 /R:3 /w:[ 1 ] /st:0 //: DIP g2 (w6) @(133,282) /sn:0 /R:1 /w:[ 0 ] /st:15 //: DIP g1 (w5) @(130,209) /sn:0 /R:1 /w:[ 0 ] /st:3 //: comment g6 @(580,147) /sn:0 /anc:1 //: /line:"Hint: Remember, to start and unpause" //: /line:"the simulator press the \" Simulate\" tab" //: /line:"followed by the button." //: /end //: comment g7 @(581,227) /sn:0 /anc:1 //: /line:"Hint: You can also navigate to modules" //: /line:"by right clicking and select Open" //: /line:"from the popup menu." //: /end //: LED g5 (w0) @(277,326) /sn:0 /R:2 /w:[ 0 ] /type:0 ADD4 g0 (.Cin(w1), .A(w5), .B(w6), .Cout(w0), .S(w4)); //: @(245, 221) /sz:(64, 64) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<0 ] //: comment g12 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end endmodule //: /netlistEnd //: /netlistBegin ADD4 module ADD4(A, Cout, Cin, B, S); //: interface /sz:(64, 64) /bd:[ Ti0>Cin(34/64) Li0>B[3:0](41/64) Li1>A[3:0](16/64) Bo00 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g2 (.Cin(w5), .A(A2), .B(B2), .Cout(w8), .S(w7)); //: @(327, 307) /sz:(63, 50) /sn:0 /p:[ Ti0>0 Li0>1 Li1>1 Bo0<1 Ro0<1 ] ADD1 g1 (.Cin(w3), .A(A1), .B(A6), .Cout(w5), .S(w2)); //: @(327, 223) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<1 Ro0<1 ] //: OUT g11 (Cout) @(358,474) /sn:0 /R:3 /w:[ 0 ] //: IN g10 (Cin) @(358,96) /sn:0 /R:3 /w:[ 0 ] //: IN g6 (B) @(33,285) /sn:0 /w:[ 0 ] //: OUT g9 (S) @(633,288) /sn:0 /w:[ 0 ] assign {B3, B2, A6, B0} = B; //: CONCAT g7 @(50,285) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 assign {A3, A2, A1, A0} = A; //: CONCAT g5 @(80,156) /sn:0 /R:2 /w:[ 0 0 0 0 1 ] /dr:0 /tp:0 /drp:0 ADD1 g0 (.Cin(Cin), .A(A0), .B(B0), .Cout(w3), .S(w1)); //: @(327, 138) /sz:(63, 50) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Bo0<0 Ro0<1 ] endmodule //: /netlistEnd //: /netlistBegin ADD1 module ADD1(B, Cin, Cout, S, A); //: interface /sz:(63, 50) /bd:[ Ti0>Cin(31/63) Li0>B(34/50) Li1>A(12/50) Bo0Hint: In addition to using the scroll bar" //: /line:"on the logic analyzer, you can click and" //: /line:"drag in the main window to fine tune the" //: /line:"the position of the traces." //: /end //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(stepped simulation)" //: /line:"" //: /line:"Start the simulator by pressing the \" Simulate\" tab just as with a combinational circuit. Next, set probes" //: /line:"on the \"ck\" and \"reg_out\" signals by right clicking and selecting Add/Delete probe. Now advance" //: /line:"the simulator by a several \"clock steps\" by pressing the button or by pressing the Tab key. Notice that" //: /line:"the \"reg_out\" single show an unknown value of \"x\". In order to reset it and start the counter you," //: /line:"must first set the \"reset\" switch to \"off\", advance the simulator by a clock step, then return" //: /line:"the \"reset\" switch to the \"on\" position." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(206,286) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: DIP g6 (w7) @(190,186) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(265,349) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(243,252) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(206,238) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(91,286) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (w4) @(284,269) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential3.v~000644 001751 001751 00000011752 11135014352 022520 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /symbolBegin: 706778896 //: /iconBegin normal 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0xc1, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x30, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x30, 0x00, 0xf1, 0x3c, 0xc0, 0x00," //: /data " 0x91, 0x24, 0x00, 0x03, 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x08," //: /data " 0x91, 0x24, 0x00, 0x0c, 0x91, 0x24, 0x00, 0x03, 0x9d, 0xe7, 0xc0, 0x00," //: /data " 0x01, 0x00, 0x30, 0x00, 0x01, 0x00, 0x0c, 0x00, 0x01, 0x00, 0x03, 0x00," //: /data " 0x01, 0xc0, 0x00, 0x00, 0x01, 0x30, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00," //: /data " 0x01, 0x03, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00," //: /data " 0x0d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /iconBegin select 815 5 5 //: /data "#define bitmap_width 28" //: /data "#define bitmap_height 29" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x03, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0xf3, 0x00, 0x00, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0x03, 0x3c, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0x00, 0x0f, 0x00, 0x03, 0x00, 0x3c, 0x00, 0xf3, 0x7d, 0xf0, 0x00," //: /data " 0xf3, 0x7d, 0xc0, 0x03, 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0x00, 0x0c," //: /data " 0xb3, 0x6d, 0x00, 0x0f, 0xb3, 0x6d, 0xc0, 0x03, 0xbf, 0xef, 0xf1, 0x00," //: /data " 0x9f, 0xe7, 0x3c, 0x00, 0x03, 0x00, 0x0f, 0x00, 0x03, 0xc0, 0x03, 0x00," //: /data " 0x03, 0xf0, 0x00, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x03, 0x0f, 0x00, 0x00," //: /data " 0xc3, 0x03, 0x00, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00," //: /data " 0x0f, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00};" //: /iconEnd //: /port output Z @(33, 19) /r:0 //: /symbolEnd //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:232,193)(232,219){1} reg w4; //: /sn:0 {0}(287,278)(298,278)(298,266)(308,266){1} supply0 w0; //: /sn:0 {0}(287,288)(310,288)(310,303){1} supply0 w3; //: /sn:0 {0}(285,243)(285,233)(272,233){1} wire [7:0] w2; //: /sn:0 {0}(#:248,273)(248,248){1} wire ck; //: {0}(-39:130,283)(211,283){1} wire [7:0] reg_out; //: {0}(#:248,294)(248,327)(304,327){1} //: {2}(308,327)(364,327)(58:364,206)(264,206)(264,219){3} //: {4}(306,329)(306,342){5} wire w9; //: /sn:0 {0}(224,233)(214,233){1} //: enddecls //: GROUND g4 (w0) @(310,309) /sn:0 /w:[ 1 ] //: joint g8 (reg_out) @(306, 327) /w:[ 2 -1 1 4 ] //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(continuous simulation)" //: /line:"" //: /line:"Also like with a combinational circuit, you can press the button to unpause and simulate" //: /line:"continously. Try it with the circuit below. This circuit contains a \"real-world-time\" oscilator" //: /line:"that will cycle once per second. Like in the previous example, you will need to reset it by" //: /line:"turning the \"reset\" switch off monentarily." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(248,283) /sn:0 /w:[ 0 0 0 0 1 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end OSCILLATOR g10 (.Z(ck)); //: @(116, 283) /symbol:706778896 /sn:0 /w:[ 0 ] //: DIP g6 (w7) @(232,183) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(306,349) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(285,249) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(248,235) /sn:0 /w:[ 1 3 1 1 0 ] //: SWITCH reset (w4) @(326,266) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _CO, _S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential4.v~000644 001751 001751 00000007043 11135014354 022521 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 //: require "timer" `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:213,222)(213,248){1} reg w4; //: /sn:0 {0}(268,307)(279,307)(279,295)(289,295){1} supply0 w3; //: /sn:0 {0}(266,272)(266,262)(253,262){1} supply0 w0; //: /sn:0 {0}(268,317)(288,317)(288,328){1} wire [7:0] w2; //: /sn:0 {0}(#:229,302)(229,277){1} wire ck; //: {0}(50:192,312)(127,312){1} wire [7:0] reg_out; //: {0}(#:229,323)(229,349)(287,349){1} //: {2}(291,349)(347,349)(52:347,236)(245,236)(245,248){3} //: {4}(289,351)(289,359){5} wire w9; //: /sn:0 {0}(205,262)(195,262){1} //: enddecls //: joint g8 (reg_out) @(289, 349) /w:[ 2 -1 1 4 ] //: GROUND g4 (w0) @(288,334) /sn:0 /w:[ 1 ] //: SWITCH g3 (w4) @(307,295) /sn:0 /R:2 /w:[ 1 ] /st:1 //: comment g13 @(14,12) /anc:1 //: /line:"

Sequential Simulation

(breakpoints)" //: /line:"" //: /line:"You can use breakpoints to simulate a circuit until some condition holds. To add a" //: /line:"breakpoint click on the tab on the information box below the canvas, and press" //: /line:"the Add... button. Enter the breakpoint as a Verilog expression. Start the simulator" //: /line:"and try it with the expresion \"reg_out == 8'h42\" as shown in the example on the right." //: /line:"This will cause the simulator to stop when the reg_out signal has the value 42 hexidecimal." //: /line:"Be sure to press after entering the breakpoint." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(w4), .CK(ck)); //: @(229,312) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(565,96) /sn:0 /anc:1 //: /line:"" //: /line:"" //: /line:"

Breakpoint Entry Example.

" //: /end //: DIP g6 (w7) @(213,212) /sn:0 /w:[ 0 ] /st:1 //: GROUND g9 (w3) @(266,278) /sn:0 /w:[ 0 ] //: LED g7 (reg_out) @(289,366) /sn:0 /R:2 /w:[ 5 ] /type:2 _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(229,264) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(114,312) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _CO, _S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/tutorials/sequential5.v~000644 001751 001751 00000007556 11135014357 022536 0ustar00hansenhansen000000 000000 //: version "2.0-b2" //: property prefix = "_GG" //: property title = "seqsim_tut.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin PAGE1 module PAGE1; //: root_module reg [7:0] w7; //: /sn:0 {0}(#:199,201)(199,227){1} supply0 w0; //: /sn:0 {0}(254,296)(274,296)(274,307){1} supply0 w3; //: /sn:0 {0}(252,251)(252,241)(239,241){1} reg clr; //: {0}(32:254,286)(285,286){1} wire [7:0] w2; //: /sn:0 {0}(#:215,281)(215,256){1} wire ck; //: {0}(50:178,291)(113,291){1} wire [7:0] reg_out; //: {0}(#:215,302)(215,328)(273,328){1} //: {2}(277,328)(333,328)(52:333,215)(231,215)(231,227){3} //: {4}(275,330)(275,338){5} wire w9; //: /sn:0 {0}(191,241)(181,241){1} //: enddecls //: GROUND g4 (w0) @(274,313) /sn:0 /w:[ 1 ] //: joint g8 (reg_out) @(275, 328) /w:[ 2 -1 1 4 ] //: comment g13 @(14,12) //: /line:"

Sequential Simulation

(scripts)" //: /line:"" //: /line:"In addition to interactive simulator control, you can also write a simulator script." //: /line:"Simulator script files have the extension \".vs\" and are written using Verilog" //: /line:"syntax. While the simulator is active, press to load a simulator script file." //: /line:"You can use a script file to set and remove probes, advance the simulation time," //: /line:"set signal values and display messages in the TkGate log () window. See" //: /line:"the TkGate 2.0 documentation for details on how to write simulator scripts." //: /end _GGREG8 #(10, 10, 20) g2 (.Q(reg_out), .D(w2), .EN(w0), .CLR(clr), .CK(ck)); //: @(215,291) /sn:0 /w:[ 0 0 0 0 0 ] //: comment g1 @(10,410) /sn:0 /R:14 /anc:1 //: /line:"" //: /end //: comment g10 @(495,118) /sn:0 /R:14 /anc:1 //: /line:"Simulator Script Example:" //: /line:"" //: /line:"initial" //: /line:" begin" //: /line:" $display(\"%t: Start of script\",$time);" //: /line:" $tkg$probe(ck, reg_out, clr);" //: /line:" $display(\"%t: Set probes\",$time);" //: /line:" clr = 1'b0;" //: /line:" #200;" //: /line:" clr = 1'b1;" //: /line:" $display(\"%t: Done with reset\",$time);" //: /line:" #500;" //: /line:" $stop();" //: /line:" end" //: /line:"" //: /end //: DIP g6 (w7) @(199,191) /sn:0 /w:[ 0 ] /st:1 //: LED g7 (reg_out) @(275,345) /sn:0 /R:2 /w:[ 5 ] /type:2 //: GROUND g9 (w3) @(252,257) /sn:0 /w:[ 0 ] _GGADD8 #(68, 70, 62, 64) g5 (.A(w7), .B(reg_out), .S(w2), .CI(w3), .CO(w9)); //: @(215,243) /sn:0 /w:[ 1 3 1 1 0 ] _GGCLOCK_P100_0_50 g0 (.Z(ck)); //: @(100,291) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: SWITCH reset (clr) @(303,286) /R:2 /w:[ 1 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _CO, _S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex2000777 001751 001751 00000000000 11145151105 020102 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/ex3000777 001751 001751 00000000000 11145151105 020103 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/ex4000777 001751 001751 00000000000 11145151105 020104 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/ex1000777 001751 001751 00000000000 11145151105 020101 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/ex5000777 001751 001751 00000000000 11215075237 020116 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/ex6000777 001751 001751 00000000000 11145151105 020106 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/locale/en/examples/index.v000644 001751 001751 00000004525 11135013747 020773 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "index.v" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module //: enddecls //: comment g4 @(553,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Coke Machine

" //: /line:"This example uses TkGate's Viritual" //: /line:"Peripheral Device (VPD) mechanism to" //: /line:"create an interactive \"Coke Machine\"" //: /line:"that can be controlled by a user circuit." //: /line:"Only the coke machine device itself is" //: /line:"included. Can you build a controller" //: /line:"for it?" //: /line:"" //: /end //: comment g3 @(32,317) /sn:0 /anc:1 //: /line:"" //: /line:"

Transistor-Level FF

" //: /line:"A flop-flop implemented using" //: /line:"nmos and pmos devices." //: /line:"" //: /end //: comment g2 @(551,30) /sn:0 /anc:1 //: /line:"" //: /line:"

8-Bit Counter

" //: /line:"A counter implemented using the" //: /line:"register and adder devices." //: /end //: comment g1 @(299,30) /sn:0 /anc:1 //: /line:"" //: /line:"

3-Bit Counter

" //: /line:"A 3-bitcounter implemented using" //: /line:"three single-bit D-flip-flops." //: /end //: comment g6 @(20,552) /sn:0 //: /line:"Go back to the TkGate main page" //: /end //: comment g5 @(301,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Menagerie CPU

" //: /line:"A simple microcode-based CPU that" //: /line:"will play the \"Animals\" game on a" //: /line:"TTY device when simulated." //: /end //: comment g0 @(32,30) /sn:0 /anc:1 //: /line:"

" //: /line:"Combinational Logic

" //: /line:"A simple 3-bit adder that you" //: /line:"simulate. Push the play button" //: /line:"then click on the switches and" //: /line:"watch how the LEDs change." //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/examples/index.v~000644 001751 001751 00000004525 11135013747 021171 0ustar00hansenhansen000000 000000 //: version "2.0-b5" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "index.v" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module //: enddecls //: comment g4 @(553,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Coke Machine

" //: /line:"This example uses TkGate's Viritual" //: /line:"Peripheral Device (VPD) mechanism to" //: /line:"create an interactive \"Coke Machine\"" //: /line:"that can be controlled by a user circuit." //: /line:"Only the coke machine device itself is" //: /line:"included. Can you build a controller" //: /line:"for it?" //: /line:"" //: /end //: comment g3 @(32,317) /sn:0 /anc:1 //: /line:"" //: /line:"

Transistor-Level FF

" //: /line:"A flop-flop implemented using" //: /line:"nmos and pmos devices." //: /line:"" //: /end //: comment g2 @(551,30) /sn:0 /anc:1 //: /line:"" //: /line:"

8-Bit Counter

" //: /line:"A counter implemented using the" //: /line:"register and adder devices." //: /end //: comment g1 @(299,30) /sn:0 /anc:1 //: /line:"" //: /line:"

3-Bit Counter

" //: /line:"A 3-bitcounter implemented using" //: /line:"three single-bit D-flip-flops." //: /end //: comment g6 @(20,552) /sn:0 //: /line:"Go back to the TkGate main page" //: /end //: comment g5 @(301,317) /sn:0 /anc:1 //: /line:"

" //: /line:"Menagerie CPU

" //: /line:"A simple microcode-based CPU that" //: /line:"will play the \"Animals\" game on a" //: /line:"TTY device when simulated." //: /end //: comment g0 @(32,30) /sn:0 /anc:1 //: /line:"

" //: /line:"Combinational Logic

" //: /line:"A simple 3-bit adder that you" //: /line:"simulate. Push the play button" //: /line:"then click on the switches and" //: /line:"watch how the LEDs change." //: /line:"" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/examples/ex6/coke.v000644 001751 001751 00000012403 11135014423 021271 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg [5:0] w6; //: /sn:0 {0}(#:95,107)(114,107)(114,117)(143,117){1} reg BILLT; //: /sn:0 {0}(143,213)(49,213){1} reg [7:0] w0; //: /sn:0 {0}(#:88,321)(127,321)(127,293)(143,293){1} reg RETINS; //: /sn:0 {0}(143,261)(88,261){1} reg CHGD; //: /sn:0 {0}(143,149)(49,149){1} reg [5:0] w20; //: /sn:0 {0}(#:95,68)(124,68)(124,101)(143,101){1} reg INSACK; //: /sn:0 {0}(143,277)(49,277){1} reg w1; //: /sn:0 {0}(236,375)(236,358){1} reg BILLIN; //: /sn:0 {0}(143,197)(88,197){1} reg BILLOUT; //: /sn:0 {0}(143,229)(88,229){1} reg CHGQ; //: /sn:0 {0}(143,133)(88,133){1} reg NOCHG; //: /sn:0 {0}(143,181)(49,181){1} reg CHGCOM; //: /sn:0 {0}(143,245)(49,245){1} reg CHGN; //: /sn:0 {0}(143,165)(88,165){1} wire w38; //: /sn:0 {0}(326,325)(358,325){1} wire w37; //: /sn:0 {0}(326,309)(358,309){1} wire w34; //: /sn:0 {0}(326,261)(358,261){1} wire [2:0] w21; //: /sn:0 {0}(#:358,197)(326,197){1} wire w31; //: /sn:0 {0}(326,245)(358,245){1} wire w36; //: /sn:0 {0}(326,293)(358,293){1} wire w24; //: /sn:0 {0}(326,149)(358,149){1} wire w23; //: /sn:0 {0}(326,133)(358,133){1} wire [5:0] w18; //: /sn:0 {0}(#:326,117)(354,117){1} wire w30; //: /sn:0 {0}(326,229)(358,229){1} wire INSN; //: /sn:0 {0}(358,165)(326,165){1} wire [5:0] w17; //: /sn:0 {0}(#:326,101)(354,101){1} wire [2:0] w29; //: /sn:0 {0}(#:326,213)(358,213){1} wire [2:0] w26; //: /sn:0 {0}(#:326,181)(358,181){1} wire BILLACK; //: /sn:0 {0}(358,277)(326,277){1} //: enddecls //: SWITCH g8 (BILLOUT) @(71,229) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g4 (CHGN) @(71,165) /sn:0 /w:[ 1 ] /st:0 //: LED g13 (INSN) @(365,165) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g3 (CHGD) @(32,149) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g2 (CHGQ) @(71,133) /sn:0 /w:[ 1 ] /st:0 //: DIP g1 (w20) @(57,68) /sn:0 /R:1 /w:[ 0 ] /st:0 //: DIP g11 (w6) @(57,107) /sn:0 /R:1 /w:[ 0 ] /st:0 //: LED g16 (w21) @(365,197) /sn:0 /R:3 /w:[ 0 ] /type:1 //: LED g28 (w37) @(365,309) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g10 (w23) @(365,133) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g27 (INSACK) @(32,277) /sn:0 /w:[ 1 ] /st:0 //: LED g19 (w31) @(365,245) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g6 (BILLIN) @(71,197) /sn:0 /w:[ 1 ] /st:0 //: LED g9 (w17) @(361,101) /sn:0 /R:3 /w:[ 1 ] /type:1 //: SWITCH g7 (BILLT) @(32,213) /sn:0 /w:[ 1 ] /st:0 //: comment g31 @(20,16) /sn:0 //: /line:"

Coke Machine Problem

" //: /end //: LED g20 (w34) @(365,261) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g15 (w18) @(361,117) /sn:0 /R:3 /w:[ 1 ] /type:1 //: comment g39 @(18,426) /sn:0 //: /line:"[BACK]" //: /end //: LED g29 (w38) @(365,325) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g25 (BILLACK) @(365,277) /sn:0 /R:3 /w:[ 0 ] /type:0 //: LED g17 (w29) @(365,213) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g14 (w26) @(365,181) /sn:0 /R:3 /w:[ 1 ] /type:1 //: SWITCH g5 (NOCHG) @(32,181) /sn:0 /w:[ 1 ] /st:0 cokemachine g21 (.COST(w0), .INSACK(INSACK), .RETINS(RETINS), .CHGCOM(CHGCOM), .BILLOUT(BILLOUT), .BILLLT(BILLT), .BILLIN(BILLIN), .NOCHG(NOCHG), .CHGN(CHGN), .CHGD(CHGD), .CHGQ(CHGQ), .ELIGHT(w6), .DISP(w20), ._RESET(w1), .BILLNG(w38), .DISPACK(w37), .CHGACK(w36), .BILLACK(BILLACK), .CNRET(w34), .BILLOK(w31), .BILLSNS(w30), .NUMN(w29), .NUMD(w21), .NUMQ(w26), .INSN(INSN), .INSD(w24), .INSQ(w23), .EMPTY(w18), .PRESS(w17)); //: @(144, 85) /sz:(181, 272) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>0 Li4>0 Li5>0 Li6>0 Li7>0 Li8>0 Li9>0 Li10>0 Li11>1 Li12>1 Bi0>1 Ro0<0 Ro1<0 Ro2<0 Ro3<1 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<1 Ro9<0 Ro10<1 Ro11<0 Ro12<0 Ro13<0 Ro14<0 ] //: LED g24 (w36) @(365,293) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g23 (RETINS) @(71,261) /sn:0 /w:[ 1 ] /st:0 //: DIP g26 (w0) @(50,321) /sn:0 /R:1 /w:[ 0 ] /st:15 //: comment g0 @(421,39) /sn:0 //: /line:"The module to the left is an interface to a \"coke\" machine." //: /line:"If you switch to simulation mode and press the simulation" //: /line:"\"play\" button, a window showing an external and internal" //: /line:"view of the coke machine will be displayed. You can then" //: /line:"drag coins and bills to the coin slot or bill reader, press" //: /line:"the drink buttons or press the coin return lever. These" //: /line:"actions will cause signals to be sent to your circuit." //: /line:"Inputs to the controller can be used to illuminate lights" //: /line:"and/or dispense drinks and change." //: /line:"" //: /line:"Problems:" //: /line:"" //: /line:"1) Design a controler to control the coke machine via the" //: /line:"interface above." //: /line:"" //: /line:"2) Modify your design so that either of the two \"Coke\"" //: /line:"buttons can always be used when there is any Coke in the" //: /line:"machine." //: /line:"" //: /end //: SWITCH g22 (CHGCOM) @(32,245) /sn:0 /w:[ 1 ] /st:0 //: LED g18 (w30) @(365,229) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g12 (w24) @(365,149) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g30 (w1) @(236,389) /sn:0 /R:1 /w:[ 0 ] /st:1 endmodule //: /netlistEnd `timescale 1ns/1ns tkgate-2.0-b10/locale/en/examples/ex6/coke.v~000644 001751 001751 00000012227 11135014423 021473 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "Welcome to TkGate Page" //: require "tty" //: require "coke" //: /netlistBegin main module main; //: root_module reg [5:0] w6; //: /sn:0 {0}(#:95,107)(114,107)(114,117)(143,117){1} reg BILLT; //: /sn:0 {0}(143,213)(49,213){1} reg [7:0] w0; //: /sn:0 {0}(#:88,321)(127,321)(127,293)(143,293){1} reg RETINS; //: /sn:0 {0}(143,261)(88,261){1} reg CHGD; //: /sn:0 {0}(143,149)(49,149){1} reg INSACK; //: /sn:0 {0}(143,277)(49,277){1} reg [5:0] w20; //: /sn:0 {0}(#:95,68)(124,68)(124,101)(143,101){1} reg BILLOUT; //: /sn:0 {0}(143,229)(88,229){1} reg BILLIN; //: /sn:0 {0}(143,197)(88,197){1} reg w1; //: /sn:0 {0}(236,375)(236,358){1} reg CHGQ; //: /sn:0 {0}(143,133)(88,133){1} reg CHGCOM; //: /sn:0 {0}(143,245)(49,245){1} reg NOCHG; //: /sn:0 {0}(143,181)(49,181){1} reg CHGN; //: /sn:0 {0}(143,165)(88,165){1} wire w38; //: /sn:0 {0}(326,325)(358,325){1} wire w37; //: /sn:0 {0}(326,309)(358,309){1} wire w34; //: /sn:0 {0}(326,261)(358,261){1} wire [2:0] w21; //: /sn:0 {0}(#:358,197)(326,197){1} wire w31; //: /sn:0 {0}(326,245)(358,245){1} wire w23; //: /sn:0 {0}(326,133)(358,133){1} wire w24; //: /sn:0 {0}(326,149)(358,149){1} wire w36; //: /sn:0 {0}(326,293)(358,293){1} wire [5:0] w18; //: /sn:0 {0}(#:326,117)(354,117){1} wire INSN; //: /sn:0 {0}(358,165)(326,165){1} wire w30; //: /sn:0 {0}(326,229)(358,229){1} wire [5:0] w17; //: /sn:0 {0}(#:326,101)(354,101){1} wire [2:0] w29; //: /sn:0 {0}(#:326,213)(358,213){1} wire BILLACK; //: /sn:0 {0}(358,277)(326,277){1} wire [2:0] w26; //: /sn:0 {0}(#:326,181)(358,181){1} //: enddecls //: SWITCH g4 (CHGN) @(71,165) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g8 (BILLOUT) @(71,229) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g3 (CHGD) @(32,149) /sn:0 /w:[ 1 ] /st:0 //: LED g13 (INSN) @(365,165) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g2 (CHGQ) @(71,133) /sn:0 /w:[ 1 ] /st:0 //: DIP g1 (w20) @(57,68) /sn:0 /R:1 /w:[ 0 ] /st:0 //: LED g16 (w21) @(365,197) /sn:0 /R:3 /w:[ 0 ] /type:1 //: DIP g11 (w6) @(57,107) /sn:0 /R:1 /w:[ 0 ] /st:0 //: LED g10 (w23) @(365,133) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g28 (w37) @(365,309) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g19 (w31) @(365,245) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g27 (INSACK) @(32,277) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g6 (BILLIN) @(71,197) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g7 (BILLT) @(32,213) /sn:0 /w:[ 1 ] /st:0 //: LED g9 (w17) @(361,101) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g15 (w18) @(361,117) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g20 (w34) @(365,261) /sn:0 /R:3 /w:[ 1 ] /type:0 //: comment g31 @(20,16) /sn:0 //: /line:"

Coke Machine Problem

" //: /end //: comment g39 @(18,426) /sn:0 //: /line:"[BACK]" //: /end //: LED g17 (w29) @(365,213) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g25 (BILLACK) @(365,277) /sn:0 /R:3 /w:[ 0 ] /type:0 //: LED g29 (w38) @(365,325) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g5 (NOCHG) @(32,181) /sn:0 /w:[ 1 ] /st:0 //: LED g14 (w26) @(365,181) /sn:0 /R:3 /w:[ 1 ] /type:1 //: LED g24 (w36) @(365,293) /sn:0 /R:3 /w:[ 1 ] /type:0 cokemachine g21 (.COST(w0), .INSACK(INSACK), .RETINS(RETINS), .CHGCOM(CHGCOM), .BILLOUT(BILLOUT), .BILLLT(BILLT), .BILLIN(BILLIN), .NOCHG(NOCHG), .CHGN(CHGN), .CHGD(CHGD), .CHGQ(CHGQ), .ELIGHT(w6), .DISP(w20), ._RESET(w1), .BILLNG(w38), .DISPACK(w37), .CHGACK(w36), .BILLACK(BILLACK), .CNRET(w34), .BILLOK(w31), .BILLSNS(w30), .NUMN(w29), .NUMD(w21), .NUMQ(w26), .INSN(INSN), .INSD(w24), .INSQ(w23), .EMPTY(w18), .PRESS(w17)); //: @(144, 85) /sz:(181, 272) /sn:0 /p:[ Li0>1 Li1>0 Li2>0 Li3>0 Li4>0 Li5>0 Li6>0 Li7>0 Li8>0 Li9>0 Li10>0 Li11>1 Li12>1 Bi0>1 Ro0<0 Ro1<0 Ro2<0 Ro3<1 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<1 Ro9<0 Ro10<1 Ro11<0 Ro12<0 Ro13<0 Ro14<0 ] //: SWITCH g23 (RETINS) @(71,261) /sn:0 /w:[ 1 ] /st:0 //: SWITCH g22 (CHGCOM) @(32,245) /sn:0 /w:[ 1 ] /st:0 //: comment g0 @(421,39) /sn:0 //: /line:"The module to the left is an interface to a \"coke\" machine." //: /line:"If you switch to simulation mode and press the simulation" //: /line:"\"play\" button, a window showing an external and internal" //: /line:"view of the coke machine will be displayed. You can then" //: /line:"drag coins and bills to the coin slot or bill reader, press" //: /line:"the drink buttons or press the coin return lever. These" //: /line:"actions will cause signals to be sent to your circuit." //: /line:"Inputs to the controller can be used to illuminate lights" //: /line:"and/or dispense drinks and change." //: /line:"" //: /line:"Problems:" //: /line:"" //: /line:"1) Design a controler to control the coke machine via the" //: /line:"interface above." //: /line:"" //: /line:"2) Modify your design so that either of the two \"Coke\"" //: /line:"buttons can always be used when there is any Coke in the" //: /line:"machine." //: /line:"" //: /end //: DIP g26 (w0) @(50,321) /sn:0 /R:1 /w:[ 0 ] /st:15 //: LED g12 (w24) @(365,149) /sn:0 /R:3 /w:[ 1 ] /type:0 //: LED g18 (w30) @(365,229) /sn:0 /R:3 /w:[ 1 ] /type:0 //: SWITCH g30 (w1) @(236,389) /sn:0 /R:1 /w:[ 0 ] /st:1 endmodule //: /netlistEnd tkgate-2.0-b10/locale/en/examples/ex5/menagerie.v000644 001751 001751 00000275644 11145616427 022342 0ustar00hansenhansen000000 000000 //: version "2.0-b7" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "menagerie.v" //: property simAutoStart = 1 //: property discardChanges = 1 //: property timingViolationMode = 1 //: property initTime = "3 us" //: script "menagerie.vs" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /symbolBegin: 688834864 //: /iconBegin normal 3404 0 0 //: /data "#define bitmap_width 73" //: /data "#define bitmap_height 53" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xe8, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48," //: /data " 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48, 0x80, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x3f, 0x88, 0x48, 0x80, 0x01, 0x00, 0x50," //: /data " 0x00, 0x00, 0x00, 0x50, 0x88, 0x48, 0x80, 0x01, 0x00, 0x28, 0x00, 0x00," //: /data " 0x00, 0x88, 0x88, 0x38, 0x80, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xc4," //: /data " 0x08, 0x00, 0x80, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xa2, 0x08, 0x00," //: /data " 0x80, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x91, 0xe8, 0x38, 0x80, 0x00," //: /data " 0x80, 0x02, 0x00, 0x00, 0x80, 0x88, 0x28, 0x49, 0x80, 0x01, 0x40, 0x01," //: /data " 0x00, 0x00, 0x40, 0x84, 0x28, 0x49, 0x80, 0x01, 0xa0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0x82, 0xe8, 0x48, 0x80, 0x01, 0x60, 0x00, 0x00, 0x00, 0x40, 0x81," //: /data " 0x28, 0x49, 0x80, 0x01, 0x20, 0xff, 0xff, 0xff, 0x8f, 0x80, 0x28, 0x39," //: /data " 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x7c," //: /data " 0xef, 0x03, 0xa0, 0x80, 0xe8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x2f, 0x11, 0x81, 0x00, 0xa0, 0xdc, 0x0f, 0x00, 0xa0, 0x80," //: /data " 0x28, 0x11, 0x87, 0x01, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0xef, 0x10," //: /data " 0x88, 0x01, 0xa0, 0x7c, 0xbf, 0x01, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11, 0x86, 0x00, 0xa0, 0x04," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x0f, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0xc8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11," //: /data " 0x81, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x28, 0x10, 0x8f, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x10, 0x88, 0x01, 0xa0, 0x00," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0xc8, 0x10, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0x08, 0x00, 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00," //: /data " 0x80, 0x00, 0x20, 0xfe, 0xff, 0xff, 0x8f, 0x80, 0xe8, 0x30, 0x87, 0x00," //: /data " 0x60, 0x00, 0x00, 0x00, 0xc0, 0x80, 0x28, 0x09, 0x89, 0x00, 0xa0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0x80, 0x28, 0x79, 0x89, 0x01, 0x10, 0x00, 0x00, 0x00," //: /data " 0x40, 0x80, 0x28, 0x41, 0x87, 0x01, 0xd0, 0xff, 0xff, 0xff, 0x4f, 0x80," //: /data " 0x28, 0x49, 0x89, 0x01, 0xc8, 0xaa, 0xaa, 0xaa, 0x2a, 0x40, 0xe8, 0x30," //: /data " 0x89, 0x00, 0xa8, 0xff, 0xff, 0xff, 0x27, 0x20, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa4, 0xaa, 0xaa, 0xaa, 0x16, 0x10, 0x08, 0x00, 0x80, 0x00, 0xf4, 0xff," //: /data " 0xff, 0xff, 0x13, 0x08, 0xe8, 0x7c, 0x87, 0x00, 0x92, 0xaa, 0xaa, 0xaa," //: /data " 0x0a, 0x04, 0x28, 0x11, 0x89, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x0b, 0x02," //: /data " 0x28, 0x11, 0x89, 0x01, 0x01, 0x00, 0x00, 0x00, 0x04, 0x01, 0x28, 0x11," //: /data " 0x87, 0x01, 0xff, 0xff, 0xff, 0xff, 0x87, 0x00, 0x28, 0x11, 0x89, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x44, 0x00, 0xe8, 0x10, 0x89, 0x00, 0x01, 0x00," //: /data " 0x00, 0x00, 0x24, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00," //: /data " 0x14, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /iconBegin select 3389 0 0 //: /data "#define x_width 73" //: /data "#define x_height 53" //: /data "static unsigned char x_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xf8, 0x7b, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0xd9," //: /data " 0xc0, 0x01, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 0x98, 0xd9, 0xc0, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x70," //: /data " 0x00, 0x00, 0x00, 0xf8, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x38, 0x00, 0x00," //: /data " 0x00, 0xcc, 0x98, 0x79, 0xc0, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0xe6," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0xf3, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x00, 0x07, 0x00, 0x00, 0x80, 0xd9, 0xf8, 0x79, 0xc0, 0x00," //: /data " 0x80, 0x03, 0x00, 0x00, 0xc0, 0xcc, 0x78, 0xdb, 0xc0, 0x01, 0xc0, 0xff," //: /data " 0xff, 0xff, 0x7f, 0xc6, 0x78, 0xdb, 0xc0, 0x01, 0xe0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0xc3, 0xf8, 0xd9, 0xc0, 0x01, 0x60, 0x00, 0x00, 0x00, 0xc0, 0xc1," //: /data " 0x78, 0xdb, 0xc0, 0x01, 0x60, 0xff, 0xff, 0xff, 0x8f, 0xc1, 0x78, 0x7b," //: /data " 0xc0, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x9f, 0xc1, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x7c," //: /data " 0xef, 0x03, 0xb0, 0xc1, 0xf8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x7f, 0x33, 0xc3, 0x00, 0xe0, 0xdc, 0x0f, 0x00, 0xb0, 0xc1," //: /data " 0x78, 0x33, 0xcf, 0x01, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0xff, 0x30," //: /data " 0xd8, 0x01, 0xe0, 0x7c, 0xbf, 0x01, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33, 0xce, 0x00, 0xe0, 0x04," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x1f, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0xd8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33," //: /data " 0xc3, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x30, 0xdf, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x30, 0xd8, 0x01, 0xe0, 0x00," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0xd8, 0x31, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x60, 0x01, 0x00, 0x00, 0x98, 0xc1, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x60, 0xfe, 0xff, 0xff, 0x8f, 0xc1, 0xf8, 0x70, 0xc7, 0x00," //: /data " 0xe0, 0xff, 0xff, 0xff, 0xff, 0xc1, 0x78, 0x1b, 0xdb, 0x00, 0xe0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0xc1, 0x78, 0xfb, 0xdb, 0x01, 0x30, 0x00, 0x00, 0x00," //: /data " 0xe0, 0xc0, 0x78, 0xc3, 0xcf, 0x01, 0xf0, 0xff, 0xff, 0xff, 0x6f, 0xc0," //: /data " 0x78, 0xdb, 0xdb, 0x01, 0xd8, 0xaa, 0xaa, 0xaa, 0x3a, 0x60, 0xf8, 0x70," //: /data " 0xdb, 0x00, 0xb8, 0xff, 0xff, 0xff, 0x37, 0x30, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xac, 0xaa, 0xaa, 0xaa, 0x1e, 0x18, 0x18, 0x00, 0xc0, 0x00, 0xfc, 0xff," //: /data " 0xff, 0xff, 0x1b, 0x0c, 0xf8, 0x7c, 0xc7, 0x00, 0x96, 0xaa, 0xaa, 0xaa," //: /data " 0x0e, 0x06, 0x78, 0x33, 0xdb, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x0f, 0x03," //: /data " 0x78, 0x33, 0xdb, 0x01, 0x03, 0x00, 0x00, 0x00, 0x86, 0x01, 0x78, 0x33," //: /data " 0xc7, 0x01, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x00, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0x67, 0x00, 0xf8, 0x30, 0xdb, 0x00, 0x03, 0x00," //: /data " 0x00, 0x00, 0x36, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x03, 0x00, 0x00, 0x00," //: /data " 0x1e, 0x00, 0xf8, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /port output TD[7:0] @(73, 5) /r:0 //: /port input DSR @(73, 38) /r:0 //: /port output RTS @(73, 22) /r:0 //: /port input RD[7:0] @(73, 13) /r:0 //: /port input CTS @(73, 30) /r:0 //: /port output DTR @(73, 46) /r:0 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg _reset; //: {0}(50:749,83)(749,31)(543,31){1} //: {2}(539,31)(353,31){3} //: {4}(349,31)(154,31){5} //: {6}(351,33)(351,83){7} //: {8}(541,33)(541,83){9} wire w32; //: /sn:0 {0}(589,342)(659,342){1} wire [3:0] w45; //: /sn:0 {0}(#:589,102)(659,102){1} wire [3:0] w46; //: /sn:0 {0}(#:589,117)(659,117){1} wire w56; //: /sn:0 {0}(589,284)(659,284){1} wire w38; //: /sn:0 {0}(455,157)(394,157){1} wire [7:0] w51; //: /sn:0 {0}(#:589,197)(659,197){1} wire w0; //: /sn:0 {0}(455,270)(394,270){1} wire w37; //: /sn:0 {0}(455,172)(394,172){1} wire w34; //: /sn:0 {0}(589,380)(659,380){1} wire w43; //: /sn:0 {0}(455,220)(394,220){1} wire w54; //: /sn:0 {0}(589,249)(659,249){1} wire w58; //: /sn:0 {0}(589,323)(659,323){1} wire [15:0] DATA; //: {0}(#:50:727,438)(727,473)(519,473){1} //: {2}(517,471)(517,438){3} //: {4}(515,473)(328,473)(328,438){5} wire w36; //: /sn:0 {0}(455,188)(394,188){1} wire w41; //: /sn:0 {0}(455,109)(394,109){1} wire w35; //: /sn:0 {0}(589,398)(659,398){1} wire w40; //: /sn:0 {0}(455,126)(394,126){1} wire w53; //: /sn:0 {0}(589,235)(659,235){1} wire w59; //: /sn:0 {0}(455,255)(394,255){1} wire w44; //: /sn:0 {0}(455,204)(394,204){1} wire [1:0] w49; //: /sn:0 {0}(#:589,165)(659,165){1} wire w57; //: /sn:0 {0}(589,304)(659,304){1} wire clk; //: {0}(50:694,83)(694,66)(494,66){1} //: {2}(490,66)(303,66){3} //: {4}(299,66)(146,66){5} //: {6}(301,68)(301,83){7} //: {8}(492,68)(492,83){9} wire w33; //: /sn:0 {0}(589,360)(659,360){1} wire [1:0] w48; //: /sn:0 {0}(#:589,149)(659,149){1} wire w52; //: /sn:0 {0}(589,217)(659,217){1} wire w47; //: /sn:0 {0}(589,134)(659,134){1} wire w42; //: /sn:0 {0}(455,239)(394,239){1} wire [4:0] w50; //: /sn:0 {0}(#:589,179)(659,179){1} wire w39; //: /sn:0 {0}(455,141)(394,141){1} wire w55; //: /sn:0 {0}(589,266)(659,266){1} //: enddecls //: joint g4 (DATA) @(517, 473) /w:[ 1 2 4 -1 ] //: comment g13 @(17,390) /sn:0 //: /line:"Circuit highlights:" //: /line:"* TTY Device" //: /line:"* Micro Program Counter" //: /line:"* ALU" //: /line:"* Main Memory" //: /line:"* Program Counter" //: /line:"" //: /end //: joint g3 (_reset) @(541, 31) /w:[ 1 -1 2 8 ] //: joint g2 (clk) @(492, 66) /w:[ 1 -1 2 8 ] //: comment g1 @(13,90) //: /line:"This circuit is a simple microprocessor." //: /line:"A simulation script will cause it to start" //: /line:"executing the \"Animals\" game as soon" //: /line:"as you start simulation mode. Click on" //: /line:"the various logic blocks and press the '>'" //: /line:"key to look at the sub-circuits inside." //: /line:"You can return to the parent module by" //: /line:"pressing the '<' key. While in" //: /line:"simulation mode, click on a wire to see" //: /line:"its current value, or double-click to" //: /line:"set a trace." //: /line:"" //: /line:"Click on the links below to view the" //: /line:"contents of supporting files for" //: /line:"this circuit:" //: /line:"" //: /line:"* Microcode/Macrocode Definitions" //: /line:"* Memory Initialization File" //: /line:"* Simulator Script" //: /line:"* Symbol Map" //: /line:"" //: /end IUNIT iunit (._CLR(_reset), .CK(clk), .IR(DATA), .COUT(w35), ._Z(w34), ._GT(w33), ._LT(w32), ._rdpc(w59), ._incmar(w0), ._rd(w44), .spc(w43), ._ldhmdr(w42), ._ldpc(w41), ._ldmar(w40), ._ldmdr(w39), ._incpc(w38), ._rdmdr(w37), ._wrt(w36), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), .SA(w45)); //: @(456, 84) /sz:(132, 353) /p:[ Ti0>9 Ti1>9 Bi0>3 Ri0>0 Ri1>0 Ri2>0 Ri3>0 Lo0<0 Lo1<0 Lo2<0 Lo3<0 Lo4<0 Lo5<0 Lo6<0 Lo7<0 Lo8<0 Lo9<0 Lo10<0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 ] //: joint g6 (_reset) @(351, 31) /w:[ 3 -1 4 6 ] //: comment g7 @(43,7) /sn:0 //: /line:"This is the" //: /line:"reset switch." //: /end //: comment g9 @(43,50) //: /line:"This is the" //: /line:"system clock." //: /line:" " //: /end MEMORY memory (._CLR(_reset), .CK(clk), ._incmar(w0), ._rdpc(w59), ._ldhmdr(w42), .spc(w43), ._rd(w44), ._wrt(w36), ._rdmdr(w37), ._incpc(w38), ._ldmdr(w39), ._ldmar(w40), ._ldpc(w41), .DATA(DATA)); //: @(268, 84) /sz:(125, 353) /p:[ Ti0>7 Ti1>7 Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Ri5>1 Ri6>1 Ri7>1 Ri8>1 Ri9>1 Ri10>1 Bt0=5 ] //: comment g39 @(12,517) /sn:0 //: /line:"[BACK]" //: /end EUNIT eunit (._CLR(_reset), .CK(clk), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .SA(w45), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), ._LT(w32), ._GT(w33), ._Z(w34), .COUT(w35), .DATA(DATA)); //: @(660, 84) /sz:(128, 353) /p:[ Ti0>0 Ti1>0 Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Li6>1 Li7>1 Li8>1 Li9>1 Li10>1 Li11>1 Li12>1 Li13>1 Lo0<1 Lo1<1 Lo2<1 Lo3<1 Bt0=0 ] //: joint g5 (clk) @(301, 66) /w:[ 3 -1 4 6 ] _GGCLOCK_P3000_0_50 g0 (.Z(clk)); //: @(133,66) /sn:0 /w:[ 5 ] /omega:3000 /phi:0 /duty:50 //: SWITCH reset (_reset) @(137,31) /sn:0 /w:[ 5 ] /st:1 endmodule //: /netlistEnd //: /netlistBegin MEMORY module MEMORY(DATA, _wrt, _ldpc, spc, _ldmdr, _rd, _rdmdr, _ldhmdr, _CLR, _rdpc, _incmar, _ldmar, CK, _incpc); //: interface /sz:(125, 353) /bd:[ Ti0>_CLR(83/125) Ti1>CK(33/125) Ri0>_incmar(186/353) Ri1>_rdpc(171/353) Ri2>_ldhmdr(155/353) Ri3>spc(136/353) Ri4>_rd(120/353) Ri5>_wrt(104/353) Ri6>_rdmdr(88/353) Ri7>_incpc(73/353) Ri8>_ldmdr(57/353) Ri9>_ldmar(42/353) Ri10>_ldpc(25/353) Bt0=DATA[15:0](60/125) ] supply0 [5:0] w16; //: /sn:0 {0}(#:545,861)(545,840){1} input _rd; //: /sn:0 {0}(671,557)(671,614){1} //: {2}(673,616)(708,616)(708,273)(740,273){3} //: {4}(669,616)(512,616){5} //: {6}(510,614)(510,579){7} //: {8}(508,616)(482,616){9} input _rdpc; //: /sn:0 {0}(259,285)(270,285)(270,306){1} input CK; //: /sn:0 {0}(753,813)(742,813)(742,833)(618,833)(618,815){1} //: {2}(620,813)(631,813){3} //: {4}(616,813)(524,813)(524,438){5} //: {6}(526,436)(641,436)(641,334)(726,334){7} //: {8}(522,436)(130,436){9} //: {10}(128,434)(128,335){11} //: {12}(130,333)(321,333)(321,307)(326,307){13} //: {14}(128,331)(128,253)(151,253){15} //: {16}(126,436)(62,436){17} reg [15:0] w38; //: /sn:0 {0}(#:210,713)(300,713){1} input _CLR; //: /sn:0 {0}(512,218)(512,201){1} //: {2}(514,199)(844,199)(844,327){3} //: {4}(842,329)(802,329){5} //: {6}(844,331)(844,770){7} //: {8}(842,772)(716,772)(716,808)(707,808){9} //: {10}(844,774)(844,808)(829,808){11} //: {12}(510,199)(409,199){13} //: {14}(405,199)(263,199)(263,248)(227,248){15} //: {16}(407,201)(407,302)(402,302){17} supply0 [7:0] w3; //: /sn:0 {0}(#:683,269)(683,251)(662,251){1} input _ldmar; //: /sn:0 {0}(458,247)(458,314)(438,314){1} input _wrt; //: /sn:0 {0}(691,706)(424,706){1} //: {2}(422,704)(422,510){3} //: {4}(424,508)(454,508){5} //: {6}(420,508)(399,508){7} //: {8}(422,708)(422,758)(692,758){9} input _ldhmdr; //: /sn:0 {0}(673,103)(709,103){1} //: {2}(713,103)(871,103)(871,269){3} //: {4}(711,105)(711,137){5} supply0 [15:0] w21; //: /sn:0 {0}(#:220,59)(220,42)(194,42)(194,69){1} inout [15:0] DATA; //: /sn:0 {0}(#:278,311)(297,311)(297,213)(371,213){1} //: {2}(373,211)(373,167){3} //: {4}(375,165)(508,165){5} //: {6}(512,165)(547,165){7} //: {8}(551,165)(568,165){9} //: {10}(549,167)(549,246)(616,246){11} //: {12}(510,163)(510,134){13} //: {14}(371,165)(198,165)(198,188){15} //: {16}(373,215)(373,248){17} input _ldpc; //: /sn:0 {0}(233,131)(217,131)(217,152)(148,152){1} //: {2}(144,152)(131,152){3} //: {4}(146,154)(146,204)(165,204){5} supply0 w23; //: /sn:0 {0}(829,818)(844,818)(844,836){1} supply1 w20; //: /sn:0 {0}(241,70)(241,83)(202,83){1} supply0 [7:0] w24; //: /sn:0 {0}(#:595,538)(595,523){1} supply0 [7:0] w1; //: /sn:0 {0}(#:800,724)(800,677)(825,677)(825,687){1} input _rdmdr; //: /sn:0 {0}(624,284)(624,251){1} reg [15:0] w40; //: /sn:0 {0}(#:212,765)(301,765){1} input _incpc; //: /sn:0 {0}(233,126)(133,126){1} supply0 w17; //: /sn:0 {0}(496,579)(496,592){1} input spc; //: /sn:0 {0}(251,380)(207,380){1} input _ldmdr; //: /sn:0 {0}(876,269)(876,80)(673,80){1} input _incmar; //: /sn:0 {0}(438,309)(448,309)(448,281)(327,281){1} //: {2}(325,279)(325,266){3} //: {4}(327,264)(340,264){5} //: {6}(325,262)(325,243){7} //: {8}(325,283)(325,293)(313,293)(313,326)(223,326)(223,411)(96,411)(96,383){9} wire [15:0] w6; //: /sn:0 {0}(#:162,69)(162,47)(70,47)(70,360)(83,360){1} wire [7:0] mdrin; //: /sn:0 {0}(#:520,552)(557,552){1} //: {2}(561,552)(663,552){3} //: {4}(559,550)(559,523){5} wire w46; //: /sn:0 {0}(402,312)(417,312){1} wire w14; //: /sn:0 {0}(254,129)(272,129)(272,258)(227,258){1} wire [15:0] w4; //: /sn:0 {0}(#:584,165)(614,165){1} wire [15:0] w19; //: /sn:0 {0}(#:188,217)(188,243){1} wire w15; //: /sn:0 {0}(691,711)(645,711){1} //: {2}(643,709)(643,672){3} //: {4}(641,711)(436,711){5} //: {6}(434,709)(434,512)(454,512){7} //: {8}(432,711)(365,711){9} wire w; //: /sn:0 {0}(802,339)(874,339)(874,290){1} wire [15:0] PC; //: /sn:0 {0}(#:188,264)(188,309){1} //: {2}(190,311)(262,311){3} //: {4}(188,313)(188,348){5} //: {6}(190,350)(264,350)(264,364){7} //: {8}(186,350)(112,350){9} wire w37; //: /sn:0 {0}(713,761)(722,761)(722,818)(707,818){1} wire DTR; //: /sn:0 {0}(433,982)(565,982)(565,840){1} wire [7:0] w34; //: /sn:0 {0}(#:555,834)(555,668)(571,668)(571,523){1} wire [15:0] w43; //: /sn:0 {0}(#:363,297)(363,277){1} wire RTS; //: /sn:0 {0}(433,958)(555,958)(555,840){1} wire w31; //: /sn:0 {0}(366,763)(446,763){1} //: {2}(450,763)(631,763){3} //: {4}(635,763)(692,763){5} //: {6}(633,761)(633,672){7} //: {8}(448,761)(448,515)(454,515){9} wire [15:0] w28; //: /sn:0 {0}(#:344,711)(321,711){1} wire [7:0] w36; //: /sn:0 {0}(#:790,753)(790,803){1} wire DSR; //: /sn:0 {0}(433,974)(800,974)(800,858){1} wire CTS; //: /sn:0 {0}(790,858)(790,966)(433,966){1} wire [7:0] w25; //: /sn:0 {0}(#:763,286)(763,324){1} wire [15:0] w18; //: /sn:0 {0}(#:274,393)(274,550){1} //: {2}(276,552)(485,552){3} //: {4}(274,554)(274,706){5} //: {6}(276,708)(300,708){7} //: {8}(274,710)(274,760)(301,760){9} wire [7:0] w8; //: /sn:0 {0}(#:620,170)(695,170){1} wire [5:0] w35; //: /sn:0 {0}(#:780,858)(780,881)(760,881){1} wire [15:0] w30; //: /sn:0 {0}(#:345,763)(322,763){1} wire w22; //: /sn:0 {0}(154,83)(144,83){1} wire w11; //: /sn:0 {0}(503,529)(503,512)(475,512){1} wire [15:0] w2; //: /sn:0 {0}(#:656,246)(632,246){1} wire [7:0] mdr; //: /sn:0 {0}(#:780,724)(780,676)(724,676){1} //: {2}(722,674)(722,552)(699,552){3} //: {4}(697,550)(697,379){5} //: {6}(699,377)(763,377)(763,345){7} //: {8}(697,375)(697,241)(662,241){9} //: {10}(695,552)(679,552){11} //: {12}(720,676)(668,676)(668,803){13} wire [7:0] RD; //: /sn:0 {0}(#:433,949)(668,949)(668,824){1} wire [15:0] mar; //: /sn:0 {0}(#:363,318)(363,349){1} //: {2}(361,351)(284,351)(284,364){3} //: {4}(363,353)(363,400)(136,400)(136,370)(112,370){5} wire [7:0] w13; //: /sn:0 {0}(#:753,257)(753,222)(577,222)(577,494){1} wire [1:0] w27; //: /sn:0 {0}(#:600,507)(638,507)(638,666){1} wire [7:0] w5; //: /sn:0 {0}(#:620,160)(661,160)(661,150)(695,150){1} wire [7:0] w33; //: /sn:0 {0}(#:790,852)(790,824){1} wire [7:0] w42; //: /sn:0 {0}(#:773,257)(773,160)(724,160){1} wire [15:0] w9; //: /sn:0 {0}(#:178,188)(178,114){1} //: {2}(178,110)(178,98){3} //: {4}(180,112)(353,112)(353,248){5} wire [7:0] TD; //: /sn:0 {0}(#:433,941)(583,941)(583,523){1} wire w26; //: /sn:0 {0}(712,709)(745,709)(745,740)(767,740){1} //: enddecls //: joint g61 (w31) @(448, 763) /w:[ 2 8 1 -1 ] //: INOUT g8 (DATA) @(510,128) /sn:0 /R:3 /w:[ 13 ] //: joint g4 (_rd) @(510, 616) /w:[ 5 6 8 -1 ] //: joint g3 (_CLR) @(512, 199) /w:[ 2 -1 12 1 ] //: joint g55 (CK) @(524, 436) /w:[ 6 -1 8 5 ] //: joint g86 (_wrt) @(422, 508) /w:[ 4 -1 6 3 ] //: IN g13 (_wrt) @(397,508) /sn:0 /w:[ 7 ] //: IN g34 (_ldpc) @(129,152) /sn:0 /w:[ 3 ] //: IN g37 (spc) @(205,380) /sn:0 /w:[ 1 ] _GGREG8 #(10, 10, 20) g51 (.Q(RD), .D(mdr), .EN(w37), .CLR(_CLR), .CK(CK)); //: @(668,813) /sn:0 /w:[ 1 13 1 9 3 ] //: joint g58 (_CLR) @(844, 772) /w:[ -1 7 8 10 ] //: comment g89 @(37,543) /sn:0 //: /line:"This is the memory address line." //: /line:"The address can be selected from" //: /line:"the MAR (Memory Address Register)" //: /line:"or from the PC (Program Counter)." //: /end //: IN g77 (_ldmdr) @(671,80) /sn:0 /w:[ 1 ] //: joint g76 (w9) @(178, 112) /w:[ 2 1 4 -1 ] //: joint g65 (mdr) @(722, 676) /w:[ 1 2 12 -1 ] //: IN g2 (_rd) @(480,616) /sn:0 /w:[ 9 ] _GGNAND2 #(6) g59 (.I0(!_wrt), .I1(w31), .Z(w37)); //: @(703,761) /sn:0 /w:[ 9 5 0 ] /eb:0 //: GROUND g1 (w17) @(496,598) /sn:0 /w:[ 1 ] _GGREG16 #(10, 10, 20) PC (.Q(PC), .D(w19), .EN(w14), .CLR(_CLR), .CK(CK)); //: @(188,253) /w:[ 0 1 1 15 15 ] _GGBUFIF16 #(4, 6) g72 (.Z(DATA), .I(PC), .E(~_rdpc)); //: @(268,311) /sn:0 /w:[ 0 3 1 ] //: joint g64 (_wrt) @(422, 706) /w:[ 1 2 -1 8 ] _GGMUX4x8 #(12, 12) g11 (.I0(mdrin), .I1(w34), .I2(TD), .I3(w24), .S(w27), .Z(w13)); //: @(577,507) /sn:0 /R:2 /w:[ 5 1 1 1 0 1 ] /ss:0 /do:1 //: frame g16 @(110,659) /sn:0 /wi:762 /ht:347 /tx:"TTY Control" //: joint g10 (CK) @(128, 333) /w:[ 12 14 -1 11 ] //: comment g87 @(210,776) //: /line:"These dip switches specify the" //: /line:"addresses for the tty status" //: /line:"and data registers." //: /end //: joint g78 (PC) @(188, 350) /w:[ 6 5 8 -1 ] _GGADD16 #(132, 134, 126, 128) g28 (.A(w6), .B(w21), .S(w9), .CI(w20), .CO(w22)); //: @(178,85) /sn:0 /w:[ 0 1 3 1 0 ] assign {w35, CTS, DSR} = w33; //: CONCAT g50 @(790,853) /sn:0 /R:1 /w:[ 0 0 1 0 ] /dr:0 /tp:0 /drp:0 _GGMUX2x16 #(8, 8) g32 (.I0(w9), .I1(DATA), .S(_incmar), .Z(w43)); //: @(363,264) /sn:0 /w:[ 5 17 5 1 ] /ss:0 /do:0 //: joint g19 (mdr) @(697, 552) /w:[ 3 4 10 -1 ] //: joint g27 (DATA) @(373, 165) /w:[ 4 -1 14 3 ] //: IN g6 (_rdmdr) @(624,286) /sn:0 /R:1 /w:[ 0 ] //: IN g69 (_ldhmdr) @(671,103) /sn:0 /w:[ 0 ] //: joint g38 (DATA) @(549, 165) /w:[ 8 -1 7 10 ] _GGRAM16x8 #(10, 60, 70, 10, 10, 10) m1 (.A(w18), .D(mdrin), .WE(w11), .OE(_rd), .CS(w17)); //: @(503,553) /w:[ 3 0 0 7 0 ] //: joint g75 (DATA) @(373, 213) /w:[ -1 2 1 16 ] _GGBUFIF8 #(4, 6) g7 (.Z(mdrin), .I(mdr), .E(_rd)); //: @(673,552) /sn:0 /R:2 /w:[ 3 11 0 ] _GGMUX2x8 #(8, 8) g9 (.I0(w13), .I1(w42), .S(_rd), .Z(w25)); //: @(763,273) /sn:0 /w:[ 0 0 3 0 ] /ss:0 /do:0 _GGREG8 #(10, 10, 20) g53 (.Q(w33), .D(w36), .EN(w23), .CLR(_CLR), .CK(CK)); //: @(790,813) /sn:0 /w:[ 1 1 0 11 0 ] //: joint g57 (_CLR) @(844, 329) /w:[ -1 3 4 6 ] _GGMUX2x16 #(8, 8) g31 (.I0(PC), .I1(mar), .S(~_incmar), .Z(w6)); //: @(96,360) /sn:0 /R:3 /w:[ 9 5 9 1 ] /ss:1 /do:0 //: joint g71 (_ldhmdr) @(711, 103) /w:[ 2 -1 1 4 ] assign {w8, w5} = w4; //: CONCAT g15 @(615,165) /sn:0 /R:2 /w:[ 0 0 1 ] /dr:0 /tp:0 /drp:0 //: GROUND g20 (w3) @(683,275) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g68 (.I0(w5), .I1(w8), .S(~_ldhmdr), .Z(w42)); //: @(711,160) /sn:0 /R:1 /w:[ 1 1 5 1 ] /ss:1 /do:1 //: GROUND g67 (w23) @(844,842) /sn:0 /w:[ 1 ] _GGXOR2x16 #(8) g39 (.I0(w18), .I1(w38), .Z(w28)); //: @(311,711) /sn:0 /w:[ 7 1 1 ] /eb:0 //: joint g43 (w18) @(274, 552) /w:[ 2 1 -1 4 ] //: GROUND g48 (w16) @(545,867) /sn:0 /w:[ 0 ] //: IN g88 (_CLR) @(512,220) /sn:0 /R:1 /w:[ 0 ] //: joint g17 (DATA) @(510, 165) /w:[ 6 12 5 -1 ] _GGMUX2x16 #(8, 8) g25 (.I0(PC), .I1(mar), .S(~spc), .Z(w18)); //: @(274,380) /sn:0 /w:[ 7 3 0 0 ] /ss:0 /do:0 //: VDD g29 (w20) @(252,70) /sn:0 /w:[ 0 ] _GGNAND2 #(6) g62 (.I0(!_wrt), .I1(w15), .Z(w26)); //: @(702,709) /sn:0 /w:[ 0 0 0 ] /eb:0 //: IN g73 (_rdpc) @(257,285) /sn:0 /w:[ 0 ] //: joint g52 (mdr) @(697, 377) /w:[ 6 8 -1 5 ] _GGNOR1x16 #(1) g42 (.I0(w30), .Z(w31)); //: @(356,763) /sn:0 /w:[ 0 0 ] /eb:0 //: joint g63 (w15) @(643, 711) /w:[ 1 2 4 -1 ] _GGNOR2 #(6) g83 (.I0(!_incmar), .I1(!_ldmar), .Z(w46)); //: @(427,312) /sn:0 /R:2 /w:[ 0 1 1 ] /eb:0 //: joint g74 (PC) @(188, 311) /w:[ 2 1 -1 4 ] //: joint g5 (_CLR) @(407, 199) /w:[ 13 -1 14 16 ] //: frame g14 @(536,27) /sn:0 /wi:372 /ht:394 /tx:"MDR Control" //: joint g56 (CK) @(618, 813) /w:[ 2 -1 4 1 ] //: IN g80 (_incmar) @(325,241) /sn:0 /R:3 /w:[ 7 ] //: joint g79 (mar) @(363, 351) /w:[ -1 1 2 4 ] //: joint g44 (w18) @(274, 708) /w:[ 6 5 -1 8 ] assign w34 = {w16, RTS, DTR}; //: CONCAT g47 @(555,835) /sn:0 /R:1 /w:[ 0 1 1 1 ] /dr:0 /tp:0 /drp:1 //: joint g24 (CK) @(128, 436) /w:[ 9 10 16 -1 ] //: joint g85 (w15) @(434, 711) /w:[ 5 6 8 -1 ] _GGOR3 #(8) g84 (.I0(_wrt), .I1(w15), .I2(w31), .Z(w11)); //: @(465,512) /sn:0 /w:[ 5 7 9 1 ] /eb:0 _GGREG8 #(10, 10, 20) mdr (.Q(mdr), .D(w25), .EN(w), .CLR(_CLR), .CK(CK)); //: @(763,334) /w:[ 7 1 0 5 7 ] _GGBUFIF16 #(4, 6) g21 (.Z(DATA), .I(w2), .E(~_rdmdr)); //: @(626,246) /sn:0 /R:2 /w:[ 11 1 1 ] //: joint g36 (_ldpc) @(146, 152) /w:[ 1 -1 2 4 ] //: IN g23 (_ldmar) @(458,245) /sn:0 /R:3 /w:[ 0 ] _GGNOR1x16 #(1) g41 (.I0(w28), .Z(w15)); //: @(355,711) /sn:0 /w:[ 0 9 ] /eb:0 //: DIP TTYSTATUS (w38) @(172,713) /R:1 /w:[ 0 ] /st:16 //: frame g93 @(354,466) /sn:0 /wi:421 /ht:164 /tx:"Main Memory" //: joint g81 (_incmar) @(325, 264) /w:[ 4 6 -1 3 ] _GGMUX2x8 #(8, 8) g54 (.I0(mdr), .I1(w1), .S(w26), .Z(w36)); //: @(790,740) /sn:0 /w:[ 0 0 1 0 ] /ss:0 /do:0 _GGXOR2x16 #(8) g40 (.I0(w18), .I1(w40), .Z(w30)); //: @(312,763) /sn:0 /w:[ 9 1 1 ] /eb:0 //: joint g60 (w31) @(633, 763) /w:[ 4 6 3 -1 ] //: comment g90 @(211,844) /sn:0 //: /line:"This is the tty. When simulation mode" //: /line:"starts, a tty window will be popped up" //: /line:"corresponding to this device. The device" //: /line:"may be accessed through the simulated CPU" //: /line:"by reading or writing the addresses indicated" //: /line:"by the dip switches TTYSTATUS and TTYDATA." //: /end _GGNOR2 #(6) g70 (.I0(!_ldhmdr), .I1(!_ldmdr), .Z(w)); //: @(874,280) /sn:0 /R:3 /w:[ 3 0 1 ] /eb:0 _GGBUF16 #(4) g22 (.I(DATA), .Z(w4)); //: @(574,165) /sn:0 /w:[ 9 0 ] _GGREG16 #(10, 10, 20) mar (.Q(mar), .D(w43), .EN(w46), .CLR(_CLR), .CK(CK)); //: @(363,307) /w:[ 0 0 0 17 13 ] //: IN g0 (CK) @(60,436) /sn:0 /w:[ 17 ] _GGMUX2x16 #(8, 8) g26 (.I0(w9), .I1(DATA), .S(~_ldpc), .Z(w19)); //: @(188,204) /sn:0 /w:[ 0 15 5 0 ] /ss:0 /do:0 _GGNOR2 #(6) g35 (.I0(!_incpc), .I1(!_ldpc), .Z(w14)); //: @(244,129) /sn:0 /w:[ 0 0 0 ] /eb:0 //: joint g45 (mdrin) @(559, 552) /w:[ 2 4 1 -1 ] assign w27 = {w31, w15}; //: CONCAT g46 @(638,667) /sn:0 /R:1 /w:[ 1 7 3 ] /dr:0 /tp:0 /drp:1 TTY tty0 (.TD(TD), .DSR(DSR), .RTS(RTS), .RD(RD), .CTS(CTS), .DTR(DTR)); //: @(396, 962) /symbol:688834864 /w:[ 0 0 0 0 1 0 ] //: joint g82 (_incmar) @(325, 281) /w:[ 1 2 -1 8 ] //: GROUND g66 (w1) @(825,693) /sn:0 /w:[ 1 ] //: DIP TTYDATA (w40) @(174,765) /R:1 /w:[ 0 ] /st:17 assign w2 = {w3, mdr}; //: CONCAT g18 @(657,246) /sn:0 /R:2 /w:[ 0 1 9 ] /dr:0 /tp:0 /drp:1 //: joint g12 (_rd) @(671, 616) /w:[ 2 1 4 -1 ] //: frame g91 @(45,27) /sn:0 /wi:441 /ht:397 /tx:"Address Resolution" //: GROUND g30 (w21) @(220,65) /sn:0 /w:[ 0 ] //: IN g33 (_incpc) @(131,126) /sn:0 /w:[ 1 ] //: GROUND g49 (w24) @(595,544) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin ALUshift module ALUshift(A, B, OUT, FUNC); //: interface /sz:(170, 116) /bd:[ Ti0>FUNC[4:0](121/170) Ti1>B[15:0](82/170) Ti2>A[15:0](34/170) Bo0DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0A[15:0](31/107) Ti1>B[15:0](79/107) Li0>FUNC[4:0](18/127) Li1>CIN(95/127) Bo07 Ti1>5 Ti2>5 Bo0<0 ] //: IN g7 (CIN) @(431,226) /sn:0 /w:[ 0 ] //: OUT g39 (_GT) @(554,503) /sn:0 /w:[ 1 ] //: joint g48 (_Z) @(490, 431) /w:[ 2 -1 1 4 ] _GGOR1x16 #(1) g43 (.I0(OUT), .Z(_Z)); //: @(468,431) /sn:0 /w:[ 3 0 ] /eb:0 //: OUT g42 (_Z) @(553,431) /sn:0 /w:[ 3 ] _GGOR1x3 #(1) g5 (.I0(w0), .Z(w2)); //: @(317,402) /sn:0 /w:[ 0 1 ] /eb:0 _GGNAND2 #(4) g47 (.I0(_LT), .I1(_Z), .Z(_GT)); //: @(522,503) /sn:0 /w:[ 5 5 0 ] /eb:0 //: OUT g41 (OUT) @(406,507) /sn:0 /R:3 /w:[ 7 ] //: OUT g40 (_LT) @(554,467) /sn:0 /w:[ 0 ] ALUbasic g54 (.FUNC(FUNC), .B(B), .A(A), .CIN(CIN), .OUT(w1), .COUT(COUT)); //: @(468, 172) /sz:(165, 122) /sn:0 /p:[ Ti0>5 Ti1>3 Ti2>3 Li0>1 Bo0<1 Ro0<0 ] //: joint g0 (A) @(223, 67) /w:[ 2 -1 1 4 ] assign w3 = OUT[15]; //: TAP g46 @(404,467) /sn:0 /R:2 /w:[ 0 6 5 ] /ss:1 _GGNBUF #(2) g45 (.I(w3), .Z(_LT)); //: @(465,467) /sn:0 /w:[ 1 3 ] //: joint g49 (_LT) @(502, 467) /w:[ 1 -1 2 4 ] endmodule //: /netlistEnd //: /netlistBegin ZREG4 module ZREG4(CK, B, _ENA, SB, _ENB, DIN, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0_CLR(86/132) Ti1>CK(37/132) Li0>_incmar(187/353) Bi0>IR[15:0](62/132) Ri0>COUT(314/353) Ri1>_Z(296/353) Ri2>_GT(276/353) Ri3>_LT(258/353) Lo0<_rd(121/353) Lo10 Ti1>0 Bo0<1 Ro0<1 Ro1<0 Ro2<1 Ro3<0 Ro4<1 Ro5<1 ] //: joint g6 (_CLR) @(525, 74) /w:[ 2 4 6 1 ] //: IN g69 (_CLR) @(525,61) /sn:0 /R:3 /w:[ 5 ] _GGROM8x32 #(10, 30) m1 (.A(mp_nxtaddr), .D(w26), .OE(w5)); //: @(368,710) /w:[ 5 1 1 ] //: joint g7 (CK) @(102, 120) /w:[ 16 18 -1 15 ] //: OUT g53 (_ldmdr) @(701,1017) /sn:0 /w:[ 0 ] //: OUT g57 (SB) @(766,890) /sn:0 /w:[ 0 ] //: GROUND g9 (w5) @(368,751) /sn:0 /w:[ 0 ] //: OUT g75 (_LDQH) @(701,1127) /sn:0 /w:[ 1 ] //: IN g31 (IR) @(57,70) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g20 (.I0(IDATA), .I1(w27), .S(w35), .Z(w12)); //: @(393,390) /sn:0 /R:3 /w:[ 0 0 1 0 ] /ss:1 /do:0 //: GROUND g15 (w15) @(205,723) /sn:0 /w:[ 1 ] _GGMUX2x4 #(8, 8) g71 (.I0(w45), .I1(w46), .S(w47), .Z(SB)); //: @(725,890) /sn:0 /R:1 /w:[ 0 0 0 1 ] /ss:1 /do:1 //: joint g67 (w6) @(151, 65) /w:[ 2 -1 1 4 ] //: VDD g39 (w19) @(421,649) /sn:0 /w:[ 1 ] _GGMUX2x4 #(8, 8) g68 (.I0(w41), .I1(w39), .S(w43), .Z(SA)); //: @(725,818) /sn:0 /R:1 /w:[ 0 1 0 0 ] /ss:1 /do:1 //: joint g48 (IDATA) @(540, 654) /w:[ 2 1 4 -1 ] //: GROUND g43 (w20) @(455,1042) /sn:0 /w:[ 1 ] //: comment g62 @(370,940) //: /line:"This is the high half" //: /line:"of the microinstruction" //: /line:"memory." //: /end //: GROUND g17 (w23) @(360,367) /sn:0 /w:[ 0 ] _GGNOR2 #(6) g25 (.I0(!w55), .I1(!w32), .Z(_SA0)); //: @(890,384) /sn:0 /R:2 /w:[ 13 0 0 ] /eb:0 _GGMUX2x5 #(8, 8) g73 (.I0(w7), .I1(w49), .S(w42), .Z(FUNC)); //: @(725,956) /sn:0 /R:1 /w:[ 1 1 0 1 ] /ss:1 /do:1 //: joint g29 (ww) @(945, 358) /w:[ 2 4 1 -1 ] //: frame g88 @(176,317) /sn:0 /wi:311 /ht:239 /tx:"Microcode Next Address Generation" //: OUT g52 (_ldmar) @(701,1007) /sn:0 /w:[ 1 ] //: GROUND g42 (w30) @(455,678) /sn:0 /w:[ 1 ] //: joint g63 (CK) @(264, 771) /w:[ 2 4 -1 1 ] //: OUT g83 (_incmar) @(701,1177) /sn:0 /w:[ 0 ] //: OUT g74 (_LDQL) @(701,1117) /sn:0 /w:[ 1 ] //: VDD g14 (w21) @(186,641) /sn:0 /w:[ 0 ] //: joint g5 (mp_nxtaddr) @(331, 709) /w:[ 4 6 -1 3 ] //: OUT g56 (SA) @(766,818) /sn:0 /w:[ 1 ] //: OUT g44 (_incpc) @(701,997) /sn:0 /w:[ 1 ] //: OUT g47 (IDATA) @(690,654) /sn:0 /w:[ 3 ] assign {w4, w55, ww, w32} = w3; //: CONCAT g79 @(1030,353) /sn:0 /w:[ 1 0 3 3 1 ] /dr:0 /tp:0 /drp:0 //: joint g80 (CK) @(102, 276) /w:[ 12 14 -1 11 ] //: comment g84 @(694,22) //: /line:"This is a trival example of an" //: /line:"instruction unit. The mpc register" //: /line:"contains the micro-instruction" //: /line:"program counter, and the two" //: /line:"registers on the data out of ROMs" //: /line:"m1 and m2 are the current micro-" //: /line:"instructions. Note that since these" //: /line:"are two separate registers the a" //: /line:"single cycle jump delay." //: /end //: IN g24 (_LT) @(1168,345) /sn:0 /R:2 /w:[ 0 ] //: IN g21 (COUT) @(1163,375) /sn:0 /R:2 /w:[ 1 ] //: OUT g36 (_LDDATA) @(690,734) /sn:0 /w:[ 0 ] //: comment g85 @(16,131) /sn:0 //: /line:"This block" //: /line:"decodes" //: /line:"insructions" //: /line:"producing" //: /line:"a map index," //: /line:"register" //: /line:"numbers," //: /line:"a function" //: /line:"code and a" //: /line:"condition" //: /line:"code." //: /end //: OUT g41 (spc) @(701,1067) /sn:0 /w:[ 1 ] //: IN g23 (_Z) @(1164,361) /sn:0 /R:2 /w:[ 0 ] //: OUT g81 (_ldhmdr) @(701,1157) /sn:0 /w:[ 0 ] //: OUT g60 (_wrt) @(701,1057) /sn:0 /w:[ 1 ] //: OUT g54 (_ldpc) @(701,1027) /sn:0 /w:[ 1 ] //: VDD g40 (w24) @(421,1016) /sn:0 /w:[ 1 ] //: joint g70 (_CLR) @(385, 74) /w:[ 7 -1 8 10 ] //: OUT g46 (BOP) @(690,694) /sn:0 /w:[ 1 ] //: OUT g45 (AOP) @(690,684) /sn:0 /w:[ 1 ] _GGREG32 #(10, 10, 20) g35 (.Q(w8), .D(w10), .EN(w20), .CLR(w24), .CK(CK)); //: @(436,1087) /sn:0 /R:1 /w:[ 1 0 0 0 0 ] //: IN g26 (_GT) @(1165,323) /sn:0 /R:2 /w:[ 0 ] assign {w46, w39, _WA, _ldopr, _LDDATA, _LDQ, _CLQ, CIN, BOP, AOP, _ldir, w18, IDATA, w14} = mp_wrd0; //: CONCAT g0 @(483,709) /sn:0 /R:2 /w:[ 1 0 1 0 1 1 1 1 0 0 0 0 5 0 1 ] /dr:0 /tp:0 /drp:0 //: joint g22 (w55) @(879, 300) /w:[ 3 4 6 -1 ] assign {w25, w6} = IR; //: CONCAT g66 @(85,70) /sn:0 /R:2 /w:[ 1 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g82 (_rdpc) @(701,1167) /sn:0 /w:[ 1 ] _GGMUX8 #(20, 22) g18 (.I0(~w55), .I1(~w4), .I2(w55), .I3(ww), .I4(w32), .I5(_SA), .I6(_SA0), .I7(w28), .S(w44), .Z(w35)); //: @(797,311) /sn:0 /R:3 /w:[ 5 0 7 5 5 1 1 1 0 0 ] /ss:1 /do:0 _GGADD8 #(68, 70, 62, 64) g12 (.A(mp_nxtaddr), .B(w15), .S(w27), .CI(w21), .CO(w22)); //: @(221,657) /sn:0 /R:2 /w:[ 9 0 5 1 0 ] //: joint g33 (w55) @(911, 353) /w:[ -1 9 10 12 ] //: joint g30 (CK) @(102, 511) /w:[ 9 10 20 -1 ] //: OUT g49 (CIN) @(690,704) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin OPRDEC module OPRDEC(SB, SA, FUNC, OPR, OM2, MAP, OM1, COND, IR); //: interface /sz:(192, 126) /bd:[ Ti0>OPR[7:0](148/192) Ti1>IR[7:0](19/192) Bo0DIN[15:0](53/108) Li0>CK(118/138) Li1>SA[3:0](17/138) Li2>SB[3:0](33/138) Li3>_CLR(51/138) Li4>_ENA(66/138) Li5>_ENB(82/138) Li6>_WA(101/138) Bo013 Li0>13 Li1>13 Li2>1 Li3>1 Li4>13 Li5>13 Li6>13 Bo0<13 Bo1<13 ] _GGNDECODER4 #(4, 4) g19 (.I(w15), .E(~_ENB), .Z0(w17), .Z1(w10), .Z2(w25), .Z3(w46)); //: @(222,585) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] /ss:1 /do:1 //: joint g27 (CK) @(512, 403) /w:[ 4 10 3 -1 ] //: IN g32 (_ENA) @(33,453) /sn:0 /w:[ 1 ] //: joint g6 (w50) @(690, 520) /w:[ 6 8 5 -1 ] //: joint g38 (B) @(880, 435) /w:[ 5 6 8 -1 ] //: IN g9 (SA) @(31,525) /sn:0 /w:[ 1 ] //: joint g7 (w49) @(142, 623) /w:[ 2 12 1 -1 ] //: joint g15 (_CLR) @(465, 359) /w:[ 4 10 3 -1 ] //: joint g31 (DIN) @(853, 156) /w:[ 6 -1 5 8 ] //: joint g39 (B) @(1133, 435) /w:[ 1 2 4 -1 ] _GGNDECODER4 #(4, 4) g17 (.I(w37), .E(~_ENA), .Z0(w16), .Z1(w9), .Z2(w26), .Z3(w47)); //: @(222,485) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] /ss:1 /do:1 //: joint g25 (_WA) @(769, 379) /w:[ 6 8 5 -1 ] //: joint g29 (DIN) @(360, 156) /w:[ 2 -1 1 12 ] REG4 RF3 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w47), ._ENB(w46), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(1053, 197) /sz:(109, 138) /p:[ Ti0>7 Li0>7 Li1>7 Li2>7 Li3>1 Li4>1 Li5>7 Li6>7 Bo0<3 Bo1<3 ] assign {w15, w49} = SB; //: CONCAT g5 @(79,628) /sn:0 /R:2 /w:[ 1 0 0 ] /dr:0 /tp:0 /drp:0 //: joint g14 (_CLR) @(163, 359) /w:[ 2 12 1 -1 ] //: joint g24 (_WA) @(500, 379) /w:[ 4 10 3 -1 ] //: joint g36 (A) @(1085, 467) /w:[ 1 2 4 -1 ] //: joint g23 (_WA) @(279, 379) /w:[ 2 12 1 -1 ] //: OUT g41 (A) @(1207,467) /sn:0 /w:[ 0 ] REG4 RF1 (.DIN(DIN), .CK(CK), ._WA(_WA), ._ENB(w10), ._ENA(w9), ._CLR(_CLR), .SB(w49), .SA(w50), .B(B), .A(A)); //: @(567, 198) /sz:(106, 138) /p:[ Ti0>11 Li0>11 Li1>11 Li2>1 Li3>1 Li4>11 Li5>11 Li6>11 Bo0<11 Bo1<11 ] //: OUT g40 (B) @(1205,435) /sn:0 /w:[ 0 ] //: IN g22 (CK) @(40,403) /sn:0 /w:[ 0 ] //: joint g26 (CK) @(294, 403) /w:[ 2 12 1 -1 ] //: joint g35 (A) @(832, 467) /w:[ 5 6 8 -1 ] //: IN g12 (_CLR) @(41,359) /sn:0 /w:[ 0 ] //: IN g18 (_WA) @(40,379) /sn:0 /w:[ 0 ] //: joint g30 (DIN) @(619, 156) /w:[ 4 -1 3 10 ] //: IN g33 (_ENB) @(33,555) /sn:0 /w:[ 1 ] REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(801, 198) /sz:(107, 138) /p:[ Ti0>9 Li0>9 Li1>9 Li2>9 Li3>1 Li4>1 Li5>9 Li6>9 Bo0<7 Bo1<7 ] endmodule //: /netlistEnd //: /netlistBegin ALUbasic module ALUbasic(B, A, OUT, COUT, CIN, FUNC); //: interface /sz:(165, 122) /bd:[ Ti0>FUNC[4:0](125/165) Ti1>B[15:0](84/165) Ti2>A[15:0](38/165) Li0>CIN(54/122) Bo0_CLR(89/128) Ti1>CK(34/128) Li0>_DOUT(239/353) Li1>_LDQL(220/353) Li2>_LDQH(200/353) Li3>_LDDATA(182/353) Li4>SA[3:0](18/353) Li5>CIN(165/353) Li6>_LDQ(150/353) Li7>_CLQ(133/353) Li8>IDATA[7:0](113/353) Li9>FUNC[4:0](95/353) Li10>BOP[1:0](81/353) Li11>AOP[1:0](65/353) Li12>_WA(50/353) Li13>SB[3:0](33/353) Lo0<_LT(258/353) Lo1<_GT(276/353) Lo2<_Z(296/353) Lo31 Li0>0 Li1>1 Li2>1 Li3>3 Li4>0 Li5>3 Li6>0 Bo0<1 Bo1<1 ] assign w12 = w1[15:8]; //: TAP g39 @(678,679) /sn:0 /R:3 /w:[ 0 7 8 ] /ss:0 //: joint g48 (w1) @(844, 676) /w:[ 1 2 4 -1 ] _GGREG8 #(10, 10, 20) QL (.Q(QL), .D(w8), .EN(w9), .CLR(w10), .CK(CK)); //: @(620,829) /w:[ 1 0 0 0 7 ] _GGNOR2 #(6) g43 (.I0(!_LDQL), .I1(!_LDQ), .Z(w9)); //: @(706,783) /sn:0 /R:3 /w:[ 0 7 1 ] /eb:0 ALU alu (.B(w31), .A(w38), .CIN(CIN), .FUNC(FUNC), .OUT(w1), .COUT(COUT), ._LT(_LT), ._GT(_GT), ._Z(_Z)); //: @(500, 523) /sz:(107, 127) /sn:0 /p:[ Ti0>1 Ti1>1 Li0>1 Li1>1 Bo0<9 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] //: OUT g29 (_LT) @(642,575) /sn:0 /w:[ 0 ] //: IN g25 (FUNC) @(475,541) /sn:0 /w:[ 0 ] _GGBUFIF16 #(4, 6) g17 (.Z(DATA), .I(w1), .E(~_DOUT)); //: @(906,676) /sn:0 /cpc:1 /w:[ 13 0 0 ] _GGREG8 #(10, 10, 20) QH (.Q(QH), .D(w2), .EN(w7), .CLR(w10), .CK(CK)); //: @(761,855) /w:[ 1 1 1 3 9 ] //: joint g42 (CK) @(537, 829) /w:[ 6 -1 5 8 ] //: GROUND g14 (w30) @(299,394) /sn:0 /w:[ 0 ] //: joint g5 (w0) @(463, 316) /w:[ 2 1 -1 4 ] //: joint g47 (DATA) @(959, 676) /w:[ 1 2 12 -1 ] //: joint g44 (_LDQ) @(708, 739) /w:[ 2 -1 1 4 ] //: joint g21 (w35) @(486, 418) /w:[ 2 -1 4 1 ] //: IN g24 (_LDQH) @(808,771) /sn:0 /w:[ 1 ] //: joint g36 (w8) @(771, 710) /w:[ -1 2 1 4 ] //: IN g23 (_LDQL) @(677,764) /sn:0 /w:[ 1 ] //: joint g41 (CK) @(195, 409) /w:[ -1 1 2 4 ] //: joint g40 (w10) @(669, 809) /w:[ 2 -1 4 1 ] //: IN g26 (CIN) @(473,618) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g35 (.I0(w12), .I1(w8), .S(_LDQ), .Z(w2)); //: @(761,739) /sn:0 /w:[ 1 5 3 0 ] /ss:0 /do:0 _GGNOR2 #(6) g45 (.I0(!_LDQH), .I1(!_LDQ), .Z(w7)); //: @(840,809) /sn:0 /R:3 /w:[ 0 9 0 ] /eb:0 //: joint g46 (_LDQ) @(708, 757) /w:[ 6 5 8 -1 ] //: joint g0 (DATA) @(864, 437) /w:[ 3 4 6 -1 ] //: joint g22 (DATA) @(608, 437) /w:[ 7 -1 8 10 ] _GGMUX4x16 #(12, 12) g18 (.I0(w21), .I1(DATA), .I2(w35), .I3(w28), .S(BOP), .Z(w31)); //: @(614,481) /sn:0 /w:[ 3 11 3 0 1 0 ] /ss:0 /do:0 //: IN g12 (IDATA) @(296,423) /sn:0 /w:[ 1 ] //: OUT g30 (COUT) @(642,592) /sn:0 /w:[ 0 ] //: IN g49 (_DOUT) @(908,642) /sn:0 /R:3 /w:[ 1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; reg Z; assign #Diz Z = ~( I0 & I1 & I2 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2x2 #(.Diz(1)) (I0, I1, Z); output [1:0] Z; input [1:0] I0, I1; reg [1:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX2x5 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [4:0] I0, I1; input S; output [4:0] Z; reg [4:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 5'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX2x4 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [3:0] I0, I1; input S; output [3:0] Z; reg [3:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 4'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGARSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >>> S); endmodule // arshift //: /builtinEnd //: /builtinBegin module _GGNOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ~( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGXOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX2x3 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [2:0] I0, I1; input S; output [2:0] Z; reg [2:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 3'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; reg [15:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGREG4 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [3:0] D; output [3:0] Q; reg [3:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 4'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x3 #(.Diz(1)) (I0, I1, Z); output [2:0] Z; input [2:0] I0, I1; reg [2:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF3 #(.Diz(1)) (I, Z); input [2:0] I; output [2:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGROM8x32 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [31:0] D; reg [31:0] m[0:255]; wire [31:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 32'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGNOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = ~ | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGLSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I << S); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGROM8x8 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [7:0] D; reg [7:0] m[0:255]; wire [7:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 8'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output Z; reg Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 1'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGOR3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; assign #Diz Z = ( I0 | I1 | I2 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGAND1x4 #(.Diz(1)) (I0, Z); output Z; input [3:0] I0; assign #Diz Z = & I0; endmodule // rand //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR1x3 #(.Diz(1)) (I0, Z); output Z; input [2:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGBUFIF16 #(.Dez(1), .Diz(1)) (Z, I, E); input [15:0] I; input E; output [15:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 16'bz; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGREG32 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [31:0] D; output [31:0] Q; reg [31:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 32'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD16 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [15:0] A,B; output [15:0] S; wire [15:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGRAM16x8 #(.Dout(1), // Output time .Dread(1), // Read time .Dwrite(1), // Write time .Daddr_setup(1), // Address setup time .Daddr_hold(1), // Address hold time .Ddata_hold(1)) // Data hold time (A, D, WE, OE, CS); input OE, WE, CS; input [15:0] A; inout [7:0] D; reg [7:0] m[0:65535]; wire [7:0] X; wire doRead, doWrite; specify $setup(A, posedge doWrite, Daddr_setup); $hold(negedge doWrite, A, Daddr_hold); $hold(negedge doWrite, D, Ddata_hold); $width(posedge doWrite, Dwrite); endspecify assign doRead = (!CS && !OE); assign doWrite = (!CS && !WE); // // Value read from addressed memory // assign #Dread X = m[A]; // // If chip-select and output-enable are asserted, output value from memory // assign #Dout D = doRead ? X : 8'bz; // // Look for conditions on which to write to memory // always @(doWrite or D or A) if (doWrite) m[A] <= #Dwrite D; always @(D) if (doWrite) $error("`RAMDCHG %m[%M]"); always @(A) if (doWrite) $error("`RAMACHG %m[%M]"); endmodule // ram //: /builtinEnd //: /builtinBegin module _GGREG16 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [15:0] D; output [15:0] Q; reg [15:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 16'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGROLL16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ((I << (S % 16)) | (I >> ((16 - S) % 16))); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGMUX2x16 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [15:0] I0, I1; input S; output [15:0] Z; reg [15:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGCLOCK_P3000_0_50 (Z); output Z; reg Z = 1'b0; initial #1500 if (0 == 0) forever begin Z = 1'b1; #1500; Z = 1'b0; #1500; end else forever begin Z = 1'b0; #1500; Z = 1'b1; #1500; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGRSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >> S); endmodule // rshift //: /builtinEnd //: /builtinBegin module _GGDIV16 #(.Dab_q(1), .Dab_r(1)) (A, B, Q, R); input [15:0] A,B; output [15:0] Q,R; assign #Dab_q Q = (A / B); assign #Dab_r R = (A % B); endmodule // div //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUL16 #(.Dab_p(1)) (A, B, P); input [15:0] A,B; output [15:0] P; assign #Dab_p P = (A * B); endmodule //: /builtinEnd //: /builtinBegin module _GGBUF5 #(.Diz(1)) (I, Z); input [4:0] I; output [4:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGMUX8x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input [15:0] I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGBUF16 #(.Diz(1)) (I, Z); input [15:0] I; output [15:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGMUX4x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [15:0] I0, I1, I2, I3; input [1:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGBUFIF8 #(.Dez(1), .Diz(1)) (Z, I, E); input [7:0] I; input E; output [7:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 8'bz; endmodule // buf //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex5/menagerie.gss000644 001751 001751 00000001423 07311226664 022647 0ustar00hansenhansen000000 000000 # # This is the simulator script for the menagerie cpu example. It # is registered to run automatically when the example is simulated. # # # Initialize the memories with the data in the menagerie.mem file. # The menagerie.mem file was compiled using gmac from the menagerie.gm # file. # load "menagerie.mem" # # Set the zoom factor for the scope. This command will zoom out # three steps to show a larger time range. # zoom 3 # # Command such as these can be uncommented to set probes or # breakpoints. # #probe clk #break iunit.extra==8'h15 # # Set the reset (active low) line to '0', step two clocks and # then set the reset line back to '1'. This sequence resets # the cpu. # set reset 1'b0 clock +2 set reset 1'b1 # # Start simulating the circuit in continous mode. # run tkgate-2.0-b10/locale/en/examples/ex5/menagerie.gm000644 001751 001751 00000132563 07311226664 022470 0ustar00hansenhansen000000 000000 // // Copyright (C) 1987-2000 by Jeffery P. Hansen // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. // // Last edit by hansen on Fri Dec 1 14:34:44 2000 // // Microcode memory bank declarations microcode bank[31:0] iunit.m1; microcode bank[63:32] iunit.m2; map bank[7:0] iunit.map; macrocode bank[7:0] memory.m1; // Microcode field declarations // // Microcode branching. mpcop specifies the basic operation. // field mpcop[1:0]={ next=0, // Increment mpc reinit=1, // Restart CPU jmap=2, // Jump from map value jump=3 // Jump from condition }; // // Specifies the condition on which to jump if mpcop is "jump". // field mpccond[12:10]={ jne=0, // Jump if not equal jcarry=1, // Jump on carry jeq=2, // Jump if equal jlt=3, // Jump if less than jgt=4, // Jump if greater than jle=5, // Jump if less than or equal jge=6, // Jump if greater than or equal jmp=7 // Jump always }; // // Address to jump to if mpcop is "jump" and condition specified // by mpccond is true. This field can not be used at the same // time as the idata field. // field mpcaddr[9:2]; // // Specifies 8 bits of data to be used by the EUNIT. This field // can not be used on jump microinstructions. // field idata[9:2]; // // Specifies the A and B operands of the ALU. // // qreg Use Q register // din Use data in // idata Use idata field from microinstruction // reg Use register file // field aop[15:14]={qreg=0, din=1, idata=2, reg=3}; field bop[17:16]={qreg=0, din=1, idata=2, reg=3}; field ~ldir[13]; // Load instruction register field cin[18]; // Carry in field ~clq[19]; // Clear Q register field ~ldq[20]; // 16-bit load of Q register field ~lddata[21]; // Load EUNIT data from external bus field ~ldopr[22]; // Load operand register field ~wa[23]; // Write register file on SA field sa[27:24]; // Register address A field sb[31:28]; // Register address B // // These fields specify the ALU function. // field ALU_FUNC[36:32]; field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3}; field ALU_BCOMP[32]; field ALU_AZERO[33]; field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7}; field ~incpc[37]; // Increment PC field ~ldmar[38]; // Load MAR field ~ldmdr[39]; // Load MDR field ~ldpc[40]; // Load PC field ~rd[41]; // Read main memory field ~rdmdr[42]; // Read MDR onto external data bus field ~wrt[43]; // Write main memory field spc[44]; // Address main memory from PC field ~isa[45]; // Use sa address from macro instruction field ~isb[46]; // Use sb address from macro instruction field ~ifunc[47]; // Use function code from macro instruction field ~icond[48]; // Use branch condition from macro instruction field ~ldql[49]; // 8-bit load of lower half of Q register field ~ldqh[50]; // 8-bit load of upper half of Q register field ~dout[51]; // Output EUNIT data to external bus field ~ldcc[52]; // Load condition code register field ~ldhmdr[53]; // Load mdr from high byte of data bus field ~rdpc[54]; // Read PC onto external bus field ~incmar[55]; // Increment mar (can't use with incpc) field extra[63:56]; // Extra bits ////////////////////////////////////////////////////////////////////// // // +-+-+-+-+-+-+-+-+ // |7|6|5|4|3|2|1|0| // +-+-+-+-+-+-+-+-+ // // Basic instruction types are encoded by the high two bits of the // first byte of the instruction. For certain types (e.g., ALU // types) some bits are masked when forming the map address. Bits // contributing to the map vector are marked with a *. // // Move Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 1 1 s|a a|b b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // s = size (1 = byte, 0 = word) // aa = operand mode 1 // bb = operand mode 2 // // Single operand instruction (push, pop, call, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0| op |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // // Branch instruction (jmp, jne, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|cond |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * // // // ALU Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1| func |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * // // func = ALU function // a = operand mode // // Other instructions // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0| op |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15; operands basic { %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands runiop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; #1 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands wuniop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; // // Operands for move instructions // operands movoprs { %1,%2 = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; %1,(%2) = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; %1,#3(%2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; %1,(#2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),%2 = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#2 = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),(%2) = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#3(%2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; (%1),(#2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; #1(%2),%3 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#3 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; #1(%2),(%3) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; }; #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),%2 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#2 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; (#1),(%2) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),(#2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|1 1 1 1 1|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op nop { map nop : 0x3e; +0=0x3e; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op halt { map halt : 0x0; +0=0; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 1|0| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op cmp { map cmp_rr : 0x2; map cmp_ri : 0x3; +0[7:1]=0x1; operands basic; }; // Generic branch operation // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|x x x|b b| |0 0 0 0| reg1 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // br #7, loop // // Jump always to loop. 7 is a code indicating the condition always. // op jp { map br_r : 0xa0; map br_i : 0xa1; map br_d : 0xa2; map br_x : 0xa3; +0[7:5] = 0x5; operands { #1,%2 = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#2 = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; }; }; }; op jne { +0[7:5] = 0x5; +0[4:2] = 0x0; operands runiop; }; op jcarry { +0[7:5] = 0x5; +0[4:2] = 0x1; operands runiop; }; op jeq { +0[7:5] = 0x5; +0[4:2] = 0x2; operands runiop; }; op jlt { +0[7:5] = 0x5; +0[4:2] = 0x3; operands runiop; }; op jgt { +0[7:5] = 0x5; +0[4:2] = 0x4; operands runiop; }; op jle { +0[7:5] = 0x5; +0[4:2] = 0x5; operands runiop; }; op jge { +0[7:5] = 0x5; +0[4:2] = 0x6; operands runiop; }; op jmp { +0[7:5] = 0x5; +0[4:2] = 0x7; operands runiop; }; // Generic ALU operation // // Note this is not a real instruction but is here for illustrative // purposes only. Map entries must be made for each function code // to use this instruction for real. // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|x x x x x|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // alu #0x14, R1, R2 // // Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1. // //op alu { // map alu_rr : 0x40; // map alu_ri : 0x41; // +0[7:6] = 0x1; // operands { // #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; }; // #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; // }; //}; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op add { map alu_rr : 0x68; map alu_ri : 0x69; +0[7:0]=0x68; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 1|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op sub { map alu_rr : 0x6a; map alu_ri : 0x6b; +0[7:0]=0x6a; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mul { map xalu_rr : 0x60; map xalu_ri : 0x61; +0[7:0]=0x60; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op div { map xalu_rr : 0x78; map xalu_ri : 0x79; +0[7:0]=0x78; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mod { map xalu_rr : 0x70; map xalu_ri : 0x71; +0[7:0]=0x70; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|0 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op and { map alu_rr : 0x50; map alu_ri : 0x51; +0[7:0]=0x50; operands basic; }; // Call subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 0|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // call foo, #8 // // This will perform the following actions: // sp = sp - 2 // [sp] = pc // sp = sp - 2 // [sp] = fp // fp = sp // sp = sp+8 // pc = foo // op call { map call_ri : 0x80; map call_ii : 0x81; map call_di : 0x82; map call_xi : 0x83; +0[7:4] = 0x8; operands { #1,%2 = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1 = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; }; }; }; // Return from subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 1 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // ret // // This will perform the following actions: // sp = fp // fp = [sp] // sp = sp + 2 // pc = [sp] // sp = sp + 2 // // op ret { map ret : 0x4; +0=4; operands { - = { +1=0; }; }; }; // Push a word on the stack // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 1|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // pushw R1 // op pushw { map pushw_r : 0x84; map pushw_i : 0x85; map pushw_d : 0x86; map pushw_x : 0x87; +0[7:2]=0x21; operands runiop; }; op movb { map movb_rr : 0xf0; map movb_ri : 0xf1; map movb_rd : 0xf2; map movb_rx : 0xf3; map movb_dr : 0xf8; map movb_di : 0xf9; map movb_dd : 0xfa; map movb_dx : 0xfb; map movb_xr : 0xfc; map movb_xi : 0xfd; map movb_xd : 0xfe; map movb_xx : 0xff; +0[7:4]=0xf; operands movoprs; }; op movw { map movw_rr : 0xe0; map movw_ri : 0xe1; map movw_rd : 0xe2; map movw_rx : 0xe3; map movw_dr : 0xe8; map movw_di : 0xe9; map movw_dd : 0xea; map movw_dx : 0xeb; map movw_xr : 0xec; map movw_xi : 0xed; map movw_xd : 0xee; map movw_xx : 0xef; +0[7:4]=0xe; operands movoprs; }; ///////////////////////////////////////////////////////////////////////////// // // The microcode for the Menagerie CPU begins here. // // The CPU begins executing microinstuctions at address 0. The instructions // in the start block are executed only once. The next block consists of // the instuction fetch sequnce. The multiple labels account for partial // fetches that are done by some of the macrocode routines. // // For macro instructions which have no operands or have only only one operand, // there is usually a plain label for that instruction. For example the // microinstruction labeled 'ret' implements the 'ret' macroinstruction. This // mapping is defined by the 'map ret : 0x4;' line in the operand declaration // for the ret macroinstruction. // // For macro instructions with multiple addressing modes, labels are generally // of the form 'op_??' where each character after the '_' denotes an addressing // mode for an operand. By convension, the characters: // // r register direct // i immediate // d register indirect // x indexed // // are used. // begin microcode @ 0 start: clq; // Q <- 0 idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh; // Q.H <- 1 ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to 'fetch' mpcop=next; fetch: incpc spc rd ldmdr; // mdr <- [PC]; PC++; fetch1: incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; fetch2: mpcop=jmap rdmdr ldopr; // opr <- mdr; jump to opcode mpcop=next; halt: mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; // // Standard ALU operations (add, sub, and, or, etc.) // alu_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; alu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; // // 2-cycle ALU operations (mul, div, mod). These are the same as the alu_?? // ops except the ALU inputs and function code are held for 2 clock cycles // due to the longer delay in computing these functions. // xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg; // Ra (op) Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; xalu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=next ifunc isa isb aop=reg bop=qreg; // Ra (op) Q; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; cmp_rr: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22 isa isb aop=reg bop=reg ldcc; // Ra - Rb; CC; jump to fetch mpcop=next; cmp_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP aop=reg bop=qreg isa ldcc; // Ra - Q; CC; jump to fetch mpcop=next; br_i: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; btest: mpcop=jump mpcaddr=bdojmp icond; // jump to bdojmp if cond mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to fetch mpcop=next; bdojmp: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q, jump to fetch mpcop=next; br_r: mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10 isa aop=reg sb=0 bop=reg ALU_OP=add ldq; // Q <- Ra; jump to btest mpcop=next; br_d: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; br_x: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; call_ii: // Push the PC aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa extra=0x11; // SP-2 -> mar; SP = SP - 2; rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq; // Q = PC+4 ALU_AZERO ALU_OP=add bop=qreg dout ldmdr; // Q.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr; // Q.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; mpcop=next; // Push the FP aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa; // SP-2 -> mar; SP = SP - 2; ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr; // FP.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldhmdr; // SP.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; aop=reg sa=0xe bop=reg sb=0xf ALU_AZERO ALU_OP=add wa; // FP <- SP // Dec SP incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=qreg ALU_OP=add wa; // SP = SP + Q // PC = branch address incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q mpcop=next; call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_di: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; ret: ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12; // SP <- FP; mar <- FP; aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr; // SP <- SP+4; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr; // FP <- Q; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch1 ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q; jump fetch1 incpc spc rd ldmdr; // mdr <- [PC]; PC++; pushw_d: mpcop=next; pushw_x: mpcop=next; pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Rb.L; wrt; // [mar] <- mdr; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; pushw_i: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Q.L; wrt; // [mar] <- mdr; aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add isa isb wa aop=reg bop=reg ldcc extra=1 incpc spc rd ldmdr; // Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql; // Q.L <- Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata ALU_OP=add ldqh incpc spc rd ldmdr; // Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++; ALU_AZERO ALU_OP=add bop=qreg isa wa incpc spc rd ldmdr rdmdr ldir; // Ra <- Q; mdr <- [PC]; PC++; ir <- mdr; movw_ri: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_ri:incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0; // Q.H = 0; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mbrd: rd ldmdr; // mdr <- [mar] mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa; // Ra <- mdr ALU_OP=add idata=0 bop=idata aop=reg isa ldcc; // CC movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mwrd: rd ldmdr incmar; // mdr <- [mar++] rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql; // Q.L <- mdr; mdr <- [mar++] lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add isa wa ldcc; // Ra <- Q; CC mpcop=next; movb_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mbrd isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q; movw_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mbdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mwdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb.L wrt; // [mar] <- mdr; isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mbdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mwdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xx: mpcop=next extra=7; movb_xx: mpcop=next extra=7; movw_xd: mpcop=next extra=7; movb_xd: mpcop=next extra=7; movw_dd: mpcop=next extra=7; movb_dd: mpcop=next extra=7; movw_dx: mpcop=next extra=7; movb_dx: mpcop=next extra=7; mpcop=next extra=7; movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar; // mar <- Ra _mwdi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L wrt; // [mar] <- mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra _mbdi: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q movb_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q nop: mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15; mpcop=next; end ///////////////////////////////////////////////////////////////////////////// // // General notes on assembler // Registers are not saved accross function calls unless explicitly saved. // Functions return values in R1. // The register R0 is a special "always 0" register. Writing to R0 will have no // effect other than to set condition codes. // // begin macrocode @ 0x100 ttydata: .symbol 0x11 // tty data in/out register ttystatus: .symbol 0x10 // tty status register // // Nodes have the format (note that pointers are two bytes): // // struct node { // struct node *yes_b; // struct node *no_b; // char text[100]; // }; // nsize: .symbol 104 // Size of a tree node. That is "sizeof(struct node)". yes_b: .symbol 0 // Pointer to yes side no_b: .symbol 2 // Pointer to no side text: .symbol 4 // Text of node (animal name or question) // // Execution starts here. // start: movw SP, 0 // Initialize stack pointer movw FP, 0 // Initialize frame pointer call main // Call main program sdone: jmp sdone // Infinite loop when main ends //////////////////// // main() // .proc main movw R13, mend // Use R13 as a sort of heap pointer pushw welcome // Push the "Welcome to" message call printf // Print the message add SP,2 // Restore stack pointer movw (root),top_node // Initialize root node movw (known),1 // Know one animal loop: pushw think // Push the "Think of an animal..." message call printf // Print the message add SP,2 // Restore stack pointer movw R1, (known) // Put number of known animals in R1 pushw R1 // Push that number on the stack pushw numk // Push the "I know %d animals" message call printf // Call printf to print message add SP,4 // Restore stack movw R1,(root) // Put the root pointer in R1 pushw R1 // Push the pointer on the stack call find_animal // Ask questions to find animal add SP,2 // Restore the stack movw (root),R1 // Save new root jmp loop // Go back and guess another animal ret // Return to call (actually we should never get here) .end //////////////////// // find_animal(p) Find the animal. p is the root node in question tree // .proc find_animal tree: .symbol -2 // Local variable for tree pointer sub SP,2 // Allocate space for local variables movw R1, 4(FP) // Get the pointer to top node movw tree(FP),R1 // Store it in "tree" movw R2,yes_b(R1) // Get pointer in "yes" branch of tree cmp R2,0 // Compare against 0 jne get_response // If not 0, then treat as question node pushw R1 // Push pointer to top node call get_final // As the final question, and insert new node if necessary add SP,2 // Restore stack movw tree(FP),R1 // Save new root node in "tree" jmp done // All done, go to final cleanup get_response: movw R1,tree(FP) // Put current node pointer in R1 movw R4,R1 // R4 = R1 add R4,text // Add offset to make R4 pointer to question pushw R4 // Push text of question call print // Print question in tree node add SP,2 // Restore stack pushw qprompt // Push "?" prompt call print // Print the "? " add SP,2 // Restore stack pushw buf // Push address of buffer in which to get response call gets // Read response from user add SP,2 // Restore stack pushw buf // Push users response on stack pushw yes // Push "yes" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_yes // If so, user answered "yes", goto say_yes pushw buf // Push users response on stack pushw no // Push "no" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_no // If so, user answered "no", goto say_no pushw yesno // Push the "yes or no" error message call print // Print error message add SP,2 // Restore stack jmp get_response // Go back and ask again say_yes: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,yes_b(R1) // Put "yes" branch pointer in R2 pushw R2 // Push the yes branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw yes_b(R2),R1 // Update the "yes" branch jmp done // Finish up and prepare to return to caller say_no: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,no_b(R1) // Put "no" branch pointer in R2 pushw R2 // Push the no branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw no_b(R2),R1 // Update the "no" branch jmp done // Finish up and prepare to return to caller done: movw R1,tree(FP) // Put new root node in R1 ret // Return to caller .end //////////////////// // get_final(p) Ask final question (at node p), and update tree if necessary. // .proc get_final tree: .symbol -2 // Local variable for tree pointer animal_node: .symbol -4 // Local variable for new animal node pointer discrim_node: .symbol -6 // Local variable for new question node pointer sub SP,6 // Allocate space for local variables get_response: movw R1, 4(FP) // Get pointer to current node movw tree(FP),R1 // Save it in the 'tree' variable movw R1, 4(FP) // Put pointer to tree in R1 add R1,text // Advance R1 to animal name text pushw R1 // Push pointer to animal name on stack pushw isita // Push the "is it a..." string pointer call printf // Print the final question add SP,4 // Restore stack pushw buf // Push buffer for response call gets // Get the response add SP,2 // Restore the stack pushw buf // Push response on stack pushw yes // Push "yes" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq win // If so, we guessed the animal pushw buf // Push response on stack pushw no // Push "no" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq loose // If so, we did not guess the animal pushw yesno // Push the "yes or no" error message call print // Print it add SP,2 // Restore stack jmp get_response // Go back and ask again win: pushw winmsg // Push the (computer) win message call printf // Print it add SP,2 // Restore stack jmp done // All done, go finish up and return loose: pushw loosemsg // Push the (computer) loose message call printf // Print it add SP,2 // Restore stack pushw nsize // Push number of bytes in a node call malloc // Allocate memory for new animal node add SP,2 // Restore stack movw animal_node(FP),R1 // Put address of new node in animal_node movw yes_b(R1),0 // Intialize yes branches movw no_b(R1),0 // Intialize no branches add R1,text // Move R1 to point to text area pushw R1 // Push text buffer call gets // Get animal name add SP,2 // Restore stack movw R1,tree(FP) // Put pointer to exiting node in R1 add R1,text // Advance to the text field pushw R1 // Push pointer to old animal name movw R1,animal_node(FP) // Put pointer to new node in R1 add R1,text // Advance to the text field pushw R1 // Push new animal name on stack pushw dscrim // Push "what is difference" question call printf // Print the question add SP,6 // Restore pointer pushw nsize // Allocate memory for discrimination node call malloc // Allocate memory for new discrimination node add SP,2 // Restore stack movw discrim_node(FP),R1 // Put address of new node in discrim_node add R1,text // Advance pointer to text field of discrimination node pushw R1 // Push pointer to text buffer to input question call gets // Input the question add SP,2 // Restore pointer movw R1, (known) // Put number of known animals in R1 add R1,1 // Increment R1 movw (known),R1 // Store number of known animals back in "known" L1: movw R1,animal_node(FP) // Put pointer to new animal node in R1 add R1,text // Advance R1 to the text field pushw R1 // Push new animal name on stack pushw which // Push the "..correct answer for..." message. call printf // Print the message add SP,4 // Restore stack pushw buf // Push text buffer on stack call gets // Input a "yes" or "no" add SP,2 // Restore stack pushw buf // Push user response pushw yes // Push string "yes" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L2 // If so, goto L2. New animal is on "yes" branch pushw buf // Push user response pushw no // Push string "no" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L3 // If so, goto L3. New animal is on "no" branch pushw yesno // Push the "yes or no" error message call printf // Print it add SP,2 // Restore stack jmp L1 // Go back and ask again // // Insert new animal on yes branch of new question // L2: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R3 // Set yes branch to new node movw no_b(R1),R2 // Set no branch to old node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return // // Insert new animal on no branch of new question // L3: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R2 // Set yes branch to old node movw no_b(R1),R3 // Set no branch to new node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return done: movw R1,tree(FP) // Put tree pointer into return register R1 ret // Return to caller .end //////////////////// // malloc(n) -> p Allocate n bytes and return address in R1. Allocated memory // can not be freed. // .proc malloc movw R2, 4(FP) // Get number of bytes movw R1,R13 // Pointer to block of memory add R13,R2 // Update heap pointer ret .end //////////////////// // print(s) Print the string s // .proc print movw R1, 4(FP) // Get parameter (string address) loop: movb R2, (R1) // Put character R1 is pointing to in R2 jeq done // If it was a 0, this is the end of the string movb (ttydata),R2 // Move char to the tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Move pointer to next char jmp loop // Go back and print more done: ret .end //////////////////// // printf(s,...) Print the format string // .proc printf ptr: .symbol -2 // Local var for string pointer arg: .symbol -4 // Local var for argument pointer sub SP,4 // Allocate 4 bytes for local variables movw R3,FP // Assign R3 and add an offset so that it points add R3,6 // to the argument after the control string movw R1, 4(FP) // Put the control string pointer in R1 loop: movb R2, (R1) // Get the next char from control string jeq done // If it was a 0, this is the end of the string cmp R2, '%' // See if it is the '%' character jne cout // If not goto cout, and simply print it add R1,1 // Advance the string pointer movb R2,(R1) // Get the next char add R1,1 // Advance the string pointer again //switch (R2) L1: cmp R2,'s' // See if this is a "%s" conversion jne L2 // If not, goto L2 // case 's' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get address of string (from arguments) to print pushw R2 // Push it on the stack call print // Print the string add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more L2: cmp R2,'d' // See if this is a "%d" conversion jne loop // If not, ignore unknown conversion // case 'd' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get number (from arguments) to print pushw R2 // Push it on the stack call nprint // Go print the decimal number add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more cout: movb (ttydata),R2 // Put character in tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Advance to next char in control string jmp loop // Go back and print more done: ret // All done, return to caller .end //////////////////// // nprint(d) Print the number d in decimal // .proc nprint movw R1, 4(FP) // Move argument value to R1 jeq zprint // If it was zero, goto zprint pushw R1 // Push value to print on stack call nprint_aux // Call aux function to print number add SP,2 // Restore stack pointer ret // All done, return to caller zprint: movb (ttydata), '0' // Put the ascii value of '0' in tty data register movb (ttystatus), #1 // Signal tty controller to print character ret // All done, return to caller .end //////////////////// // nprint_aux(d) Print the number d in decimal (but prints nothing if d is zero) // .proc nprint_aux digit: .symbol -2 // Digit to print sub SP, 2 // Allocate space for local variables movw R1, 4(FP) // Get argument jeq done // If zero, return // To print the number n we compute // R2 = n / 10, and // R3 = n % 10 // We can then recursively call nprint_aux to print all // but the lowest digit, then print the lowest digit ourselves // movw R2, R1 // R2 = R1 div R2, 10 // R2 = R2 / 10 movw R3, R1 // R3 = R1 mod R3, 10 // R3 = R3 % 10 movw digit(FP),R3 // save lowest digit value pushw R2 // Push the higher digits call nprint_aux // Recursively call ourselves to print them add SP,2 // Restore stack pointer movw R3,digit(FP) // Restore digit value add R3, '0' // Add ascii for '0' to get ascii for digit movb (ttydata),R3 // Put char in tty data register movb (ttystatus),#1 // Signal tty controller to print character done: ret // All done, resturn to caller .end //////////////////// // strcmp(a,b) Compare strings a and b // .proc strcmp movw R2,4(FP) // Get pointer to first string movw R3,6(FP) // Get pointer to second string loop: movb R1,(R2) // Get next char from R2 jeq eos // If end of string, goto eos movb R4,(R3) // Get next char from R3 jeq eos // If end of string, goto eos sub R1,R4 // Compute difference in R1 jne done // If difference was not 0, we are done add R2,1 // Advance to next char in R2 add R3,1 // Advance to next char in R3 jmp loop // Go compare more eos: movb R4,(R3) // Get next char from R3 again (in case R1 was eos) sub R1,R4 // Compute difference in R1 done: ret // Return to caller, result is in R1 .end //////////////////// // gets(b) Reads chars from tty into b. // .proc gets movw R1, 4(FP) // Get pointer to buffer movw R4,R1 // Save starting pointer in R4 // // Poll for a characcter // cwait: movb R2,(ttystatus) // Get ready status and R2, #2 // Test if a char is ready jeq cwait // If not, go back and wait some more movb R3,(ttydata) // Get char from tty data register movb (ttystatus),#2 // Signal char received cmp R3,'\r' // Compare against return char jeq done // Exit if return received cmp R3,'\b' // Compare against backspace char jeq del_char // Delete char if backspace cmp R3,0x7f // Compare against delete char jeq del_char // Delete char if delete character movb (ttydata),R3 // Put char to echo in tty data register movb (ttystatus),#1 // Signal tty controller to print character movb (R1),R3 // Save in buffer add R1,1 // increment pointer jmp cwait // Go back and get another char del_char: cmp R1,R4 // Compare current pointer against start of line jle bell // If already at start of line, ring bell movb R3, 0x7f // Make sure delete char is in R3 sub R1,1 // Decrement pointer movb (ttydata),R3 // Echo backspace movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char bell: movb R3, 7 // Put bell char in R3 movb (ttydata),R3 // Echo bell movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char done: movb (ttydata),'\n' // Output newline movb (ttystatus),#1 // Signal tty controller to print character movb (R1),0 // Put eos in the string we just read ret // Return to caller .end buf: .bss 128 // Buffer for input known: .bss 2 // Number of animals known root: .bss 2 // root of animals tree top_node: .short 0 // Pointer to "yes" node .short 0 // Pointer to "no" node .byte "aardvark",0 // Animal name or question text welcome: .byte "\nWelcome to Animals.\n", 0 think: .byte "\nThink of an animal and I will try to guess what it is.\n", 0 numk: .byte "I currently know %d animals.\n\n", 0 isita: .byte "Is the animal you are thinking of a %s? ",0 yes: .byte "yes",0 no: .byte "no",0 yesno: .byte "Please type 'yes' or 'no'.\n",0 winmsg: .byte "I guessed your animal!!!\n\n",0 loosemsg: .byte "I could not guess your animal. What was your animal? ",0 dscrim: .byte "Enter a question that would distinguish a %s from a %s.\n> ",0 which: .byte "The correct answer for a %s is? ",0 nl: .byte "\n",0 qprompt: .byte "? ",0 mend: end tkgate-2.0-b10/locale/en/examples/ex5/menagerie.mem000644 001751 001751 00000016360 11131770415 022630 0ustar00hansenhansen000000 000000 @memory iunit.m1 @0 f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 f82000 f82000 d92000 d92000 f7ae008 fa2000 f82000 fa2000 f82000 f83c17 f82000 7bfc1f f80000 fbe000 fabc1f 780000 f82000 d92000 d92000 78fc17 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call_xi 0000004d cmp_ri 0000001d cmp_rr 0000001b fetch 00000005 fetch1 00000006 fetch2 00000007 halt 00000009 movb_dd 000000a4 movb_di 000000b2 movb_dr 0000008c movb_dx 000000a6 movb_rd 0000007a movb_ri 00000075 movb_rr 0000006d movb_rx 00000084 movb_xd 000000a2 movb_xi 000000bc movb_xr 00000097 movb_xx 000000a0 movw_dd 000000a3 movw_di 000000a8 movw_dr 00000090 movw_dx 000000a5 movw_rd 0000007e movw_ri 00000070 movw_rr 0000006b movw_rx 00000088 movw_xd 000000a1 movw_xi 000000b8 movw_xr 0000009b movw_xx 0000009f nop 000000c0 pushw_d 00000058 pushw_i 00000061 pushw_r 0000005a pushw_x 00000059 ret 0000004f start 00000000 xalu_ri 00000015 xalu_rr 00000012 Macrocode Symbols (total=69): Global Local --------------------------------------- buf 000005f8 dscrim 00000795 find_animal 0000017a done 0000025e get_response 000001a6 say_no 0000023e say_yes 0000021e tree fffffffe get_final 00000264 L1 0000037c L2 000003e8 L3 00000404 animal_node fffffffc discrim_node fffffffa done 00000420 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85 0 95 7 81 0 0 0 348/ 4e 4 69 f0 6 0 85 0 350/ 64 0 81 0 0 0 26 4 358/ 69 f0 2 0 ec e1 fa ff 360/ 69 10 4 0 84 10 81 0 368/ 0 0 70 5 69 f0 2 0 370/ e3 10 78 6 69 10 1 0 378/ ec 1 78 6 e3 1e fc ff 380/ 69 10 4 0 84 10 85 0 388/ d0 7 81 0 0 0 4e 4 390/ 69 f0 4 0 85 0 f8 5 398/ 81 0 0 0 70 5 69 f0 3a0/ 2 0 85 0 f8 5 85 0 3a8/ 20 7 81 0 0 0 48 5 3b0/ 69 f0 4 0 3 10 0 0 3b8/ a9 0 e8 3 85 0 f8 5 3c0/ 85 0 24 7 81 0 0 0 3c8/ 48 5 69 f0 4 0 3 10 3d0/ 0 0 a9 0 4 4 85 0 3d8/ 27 7 81 0 0 0 4e 4 3e0/ 69 f0 2 0 bd 0 7c 3 3e8/ e3 1e fa ff e3 2e fe ff 3f0/ e3 3e fc ff ec 13 0 0 3f8/ ec 12 2 0 ec e1 fe ff 400/ bd 0 20 4 e3 1e fa ff 408/ e3 2e fe ff e3 3e fc ff 410/ ec 12 0 0 ec 13 2 0 418/ ec e1 fe ff bd 0 20 4 420/ e3 1e fe ff 4 0 e3 2e 428/ 4 0 e0 1d 68 d2 4 0 430/ e3 1e 4 0 f2 21 a9 0 438/ 4c 4 fc 2 11 0 fd 0 440/ 10 0 1 0 69 10 1 0 448/ bd 0 34 4 4 0 6b f0 450/ 4 0 e0 3e 69 30 6 0 458/ e3 1e 4 0 f2 21 a9 0 460/ e6 4 3 20 25 0 a1 0 468/ d4 4 69 10 1 0 f2 21 470/ 69 10 1 0 3 20 73 0 478/ a1 0 a2 4 ec e1 fe ff 480/ ec e3 fc ff e2 23 84 20 488/ 81 0 0 0 30 4 69 f0 490/ 2 0 e3 1e fe ff e3 3e 498/ fc ff 69 30 2 0 bd 0 4a0/ 5c 4 3 20 64 0 a1 0 4a8/ 5c 4 ec e1 fe ff ec e3 4b0/ fc ff e2 23 84 20 81 0 4b8/ 0 0 e8 4 69 f0 2 0 4c0/ e3 1e fe ff e3 3e fc ff 4c8/ 69 30 2 0 bd 0 5c 4 4d0/ bd 0 5c 4 fc 2 11 0 4d8/ fd 0 10 0 1 0 69 10 4e0/ 1 0 bd 0 5c 4 4 0 4e8/ e3 1e 4 0 a9 0 fe 4 4f0/ 84 10 81 0 0 0 c 5 4f8/ 69 f0 2 0 4 0 fd 0 500/ 11 0 30 0 fd 0 10 0 508/ 1 0 4 0 6b f0 2 0 510/ e3 1e 4 0 a9 0 46 5 518/ e0 21 79 20 a 0 e0 31 520/ 71 30 a 0 ec e3 fe ff 528/ 84 20 81 0 0 0 c 5 530/ 69 f0 2 0 e3 3e fe ff 538/ 69 30 30 0 fc 3 11 0 540/ fd 0 10 0 1 0 4 0 548/ e3 2e 4 0 e3 3e 6 0 550/ f2 12 f2 43 6a 14 a1 0 558/ 6e 5 3 40 0 0 a9 0 560/ 6e 5 69 20 1 0 69 30 568/ 1 0 bd 0 50 5 4 0 570/ e3 1e 4 0 e0 41 f3 20 578/ 10 0 51 20 2 0 a9 0 580/ 76 5 f3 30 11 0 fd 0 588/ 10 0 2 0 3 30 d 0 590/ a9 0 e6 5 3 30 8 0 598/ a9 0 b8 5 3 30 7f 0 5a0/ a9 0 b8 5 fc 3 11 0 5a8/ fd 0 10 0 1 0 f8 13 5b0/ 69 10 1 0 bd 0 76 5 5b8/ 2 14 b5 0 d4 5 f1 30 5c0/ 7f 0 6b 10 1 0 fc 3 5c8/ 11 0 fd 0 10 0 1 0 5d0/ bd 0 76 5 f1 30 7 0 5d8/ fc 3 11 0 fd 0 10 0 5e0/ 1 0 bd 0 76 5 fd 0 5e8/ 11 0 a 0 fd 0 10 0 5f0/ 1 0 f9 10 0 0 4 0 67c/ 0 0 0 0 61 61 72 64 684/ 76 61 72 6b 0 a 57 65 68c/ 6c 63 6f 6d 65 20 74 6f 694/ 20 41 6e 69 6d 61 6c 73 69c/ 2e a 0 a 54 68 69 6e 6a4/ 6b 20 6f 66 20 61 6e 20 6ac/ 61 6e 69 6d 61 6c 20 61 6b4/ 6e 64 20 49 20 77 69 6c 6bc/ 6c 20 74 72 79 20 74 6f 6c4/ 20 67 75 65 73 73 20 77 6cc/ 68 61 74 20 69 74 20 69 6d4/ 73 2e a 0 49 20 63 75 6dc/ 72 72 65 6e 74 6c 79 20 6e4/ 6b 6e 6f 77 20 25 64 20 6ec/ 61 6e 69 6d 61 6c 73 2e 6f4/ a a 0 49 73 20 74 68 6fc/ 65 20 61 6e 69 6d 61 6c 704/ 20 79 6f 75 20 61 72 65 70c/ 20 74 68 69 6e 6b 69 6e 714/ 67 20 6f 66 20 61 20 25 71c/ 73 3f 20 0 79 65 73 0 724/ 6e 6f 0 50 6c 65 61 73 72c/ 65 20 74 79 70 65 20 27 734/ 79 65 73 27 20 6f 72 20 73c/ 27 6e 6f 27 2e a 0 49 744/ 20 67 75 65 73 73 65 64 74c/ 20 79 6f 75 72 20 61 6e 754/ 69 6d 61 6c 21 21 21 a 75c/ a 0 49 20 63 6f 75 6c 764/ 64 20 6e 6f 74 20 67 75 76c/ 65 73 73 20 79 6f 75 72 774/ 20 61 6e 69 6d 61 6c 2e 77c/ 20 20 57 68 61 74 20 77 784/ 61 73 20 79 6f 75 72 20 78c/ 61 6e 69 6d 61 6c 3f 20 794/ 0 45 6e 74 65 72 20 61 79c/ 20 71 75 65 73 74 69 6f 7a4/ 6e 20 74 68 61 74 20 77 7ac/ 6f 75 6c 64 20 64 69 73 7b4/ 74 69 6e 67 75 69 73 68 7bc/ 20 61 20 25 73 20 66 72 7c4/ 6f 6d 20 61 20 25 73 2e 7cc/ a 3e 20 0 54 68 65 20 7d4/ 63 6f 72 72 65 63 74 20 7dc/ 61 6e 73 77 65 72 20 66 7e4/ 6f 72 20 61 20 25 73 20 7ec/ 69 73 3f 20 0 a 0 3f 7f4/ 20 0 tkgate-2.0-b10/locale/en/examples/ex5/menagerie.vs000644 001751 001751 00000000512 10202544261 022466 0ustar00hansenhansen000000 000000 // // Menagerie Initialization Script // initial begin $readmemh("menagerie.mem"); // Load the memory file. _reset = 1'b0; // Assert reset line repeat (3) // Advance three clock steps @ (posedge clk); # 10; // Advance 10 steps past positive clock edge _reset = 1'b1; // Unassert reset line end tkgate-2.0-b10/locale/en/examples/ex5/menagerie.mem.bak000644 001751 001751 00000020560 07311226664 023370 0ustar00hansenhansen000000 000000 memory iunit.m1 0/ f02000 fa2004 f82000 f83c17 f82000 f82000 f80000 b82002 8/ f82000 f83c27 f83c27 7bfc1f f80000 f82000 d92000 d92000 10/ 78fc17 f82000 fbe000 7bfc1f f80000 f82000 d92000 d92000 18/ f8e000 78fc17 f82000 fbfc17 f82000 f82000 d92000 d92000 20/ f8fc17 f82000 f82000 d92000 d92000 f820a7 f82000 f83c17 28/ f82000 f83c17 f82000 ebfc97 f82000 f83c97 f82000 f83c97 30/ f82000 f7ae008 ca6010 f82000 f82000 f82000 f82000 f82000 38/ f82000 f7ae008 e0fb2000 f82000 e0fb2000 f82000 f82000 fe7be000 40/ f82000 d92000 d92000 f78e000 f82000 d92000 d92000 f83c17 48/ f82000 f83c17 f82000 f83c17 f82000 f83c17 f82000 ef7b2000 50/ f7ae010 d92000 d92000 e782000 d92000 d92000 f83c1b f82000 58/ f82000 f82000 f7ae008 fae000 f82000 fae000 f82000 f83c17 60/ f82000 f82000 d92000 d92000 f7ae008 fa2000 f82000 fa2000 68/ f82000 f83c17 f82000 7bfc1f f80000 fbe000 fabc1f 780000 70/ f82000 d92000 d92000 78fc17 f82000 f82000 d92000 fb2000 78/ 78fc17 f82000 fba000 f82000 583c17 fae000 fba000 f82000 80/ d92000 d92000 783c17 f82000 f82000 d92000 d93def fb2000 88/ f82000 d92000 d93dff fb2000 fae000 fba000 f83c17 f82000 90/ fae000 fba000 f82000 fba000 f82000 f83c17 f82000 f82000 98/ d92000 d93e37 f8e000 f82000 d92000 d93e47 f8e000 f82000 a0/ f82000 f82000 f82000 f82000 f82000 f82000 f82000 f82000 a8/ fa2000 f82000 d92000 d92000 f8a000 f82000 f8a000 f82000 b0/ f83c17 f82000 fae000 f82000 d92000 f8a000 f83c17 f82000 b8/ f82000 d92000 d93ea7 f8e000 f82000 d92000 d93ecf f8e000 c0/ f83c17 f82000 memory iunit.m2 0/ ffefe0 fbeff6 f7eef6 ffefe0 ffefe0 fffd40 fff940 ffebe0 8/ ffefe0 1ffefe0 1ffefe0 ef1d40 fff940 fffd40 fdf956 fbebf6 10/ ef4fe0 ffefe0 ff0fe0 ef1d40 fff940 fffd40 fdf956 fbebf6 18/ ff0fe0 ef4fe0 ffefe0 22ef8ff5 ffefe0 fffd40 fdf956 fbebf6 20/ efcff5 ffefe0 fffd40 fdf956 fbebf6 feefe0 ffefe0 ffefe0 28/ ffefe0 f7eef6 ffefe0 10ffcff4 ffefe0 ffefe0 ffefe0 ffefe0 30/ ffefe0 11f7efb5 bfeff4 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 38/ ffefe0 f7efb5 f7ef76 ffe7e0 57eff6 ffefe0 ffe7e0 ffeff6 40/ fffd40 fdf956 fbebf6 ffeff4 fffd40 fdf956 fbebf6 f7eef6 48/ ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 ffefe0 12f7efb6 50/ 7fed74 7de976 fbebf6 7fed76 7de976 fbebf6 f7eef6 fffd40 58/ ffefe0 ffefe0 13f7efb5 f7cf74 ffe7e0 57cff4 ffefe0 ffe7e0 60/ ffefe0 2fffd40 fdf956 fbebf6 13f7efb5 f7ef74 ffe7e0 57eff4 68/ ffefe0 ffe7e0 ffefe0 1ef9d56 fff940 1edaff6 fbfd54 ffd956 70/ 2fffd40 fdf956 fbebf6 efcff6 ffefe0 2fffd40 fdf956 fbebf6 78/ efcff6 ffefe0 3f7afb4 ffed60 ffcbe0 efcff4 3f7afb4 7fed60 80/ fde976 fbebf6 efcff6 ffefe0 9fffd40 fdf956 fbebf6 f7afb4 88/ 9fffd40 fdf956 fbebf6 f7afb4 e7cfb4 f7af74 ffe7e0 ffefe0 90/ e7cfb4 f7af74 ffe7e0 57aff4 ffefe0 ffe7e0 ffefe0 9fffd40 98/ fdf956 fbebf6 e7cfb4 9fffd40 fdf956 fbebf6 e7cfb4 7ffefe0 a0/ 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 7ffefe0 a8/ f7cfb4 2fffd40 fdf956 fbebf6 f7ef74 ffe7e0 57eff4 ffefe0 b0/ ffe7e0 ffefe0 21f7cfb4 fffd40 fdf956 f7ef74 ffe7e0 ffefe0 b8/ 2fffd40 fdf956 fbebf6 f7cfb4 2fffd40 fdf956 fbebf6 f7cfb4 c0/ 15ffefe0 ffefe0 memory iunit.map 3e/ c0 0/ 9 2/ 1b 1d a0/ 2b 22 2d 2f 68/ b d b d 60/ 12 15 78/ 12 15 70/ 12 15 50/ b d 80/ 49 31 4b 4d 4/ 4f 84/ 5a 61 58 59 f0/ 6d 75 7a 84 f8/ 8c b2 a4 a6 97 bc a2 a0 e0/ 6b 70 7e 88 e8/ 90 a8 a3 a5 9b b8 a1 9f memory memory.m1 100/ e1 f0 0 0 e1 e0 0 0 108/ 81 0 0 0 12 1 bd 0 110/ e 1 e1 d0 e6 7 85 0 118/ 79 6 81 0 0 0 3e 4 120/ 69 f0 2 0 ed 0 6a 6 128/ 6c 6 ed 0 68 6 1 0 130/ 85 0 8f 6 81 0 0 0 138/ 3e 4 69 f0 2 0 e3 10 140/ 68 6 84 10 85 0 c8 6 148/ 81 0 0 0 3e 4 69 f0 150/ 4 0 e3 10 6a 6 84 10 158/ 81 0 0 0 6c 1 69 f0 160/ 2 0 ec 1 6a 6 bd 0 168/ 30 1 4 0 6b f0 2 0 170/ e3 1e 4 0 ec e1 fe ff 178/ e3 21 0 0 3 20 0 0 180/ a1 0 98 1 84 10 81 0 188/ 0 0 56 2 69 f0 2 0 190/ ec e1 fe ff bd 0 50 2 198/ e3 1e fe ff e0 41 69 40 1a0/ 4 0 84 40 81 0 0 0 1a8/ 20 4 69 f0 2 0 85 0 1b0/ e3 7 81 0 0 0 20 4 1b8/ 69 f0 2 0 85 0 e8 5 1c0/ 81 0 0 0 60 5 69 f0 1c8/ 2 0 85 0 e8 5 85 0 1d0/ 10 7 81 0 0 0 34 5 1d8/ 69 f0 4 0 3 10 0 0 1e0/ a9 0 10 2 85 0 e8 5 1e8/ 85 0 14 7 81 0 0 0 1f0/ 34 5 69 f0 4 0 3 10 1f8/ 0 0 a9 0 30 2 85 0 200/ 17 7 81 0 0 0 20 4 208/ 69 f0 2 0 bd 0 98 1 210/ e3 1e fe ff e3 21 0 0 218/ 84 20 81 0 0 0 6c 1 220/ 69 f0 2 0 e3 2e fe ff 228/ ec 21 0 0 bd 0 50 2 230/ e3 1e fe ff e3 21 2 0 238/ 84 20 81 0 0 0 6c 1 240/ 69 f0 2 0 e3 2e fe ff 248/ ec 21 2 0 bd 0 50 2 250/ e3 1e fe ff 4 0 6b f0 258/ 6 0 e3 1e 4 0 ec e1 260/ fe ff e3 1e 4 0 69 10 268/ 4 0 84 10 85 0 e7 6 270/ 81 0 0 0 3e 4 69 f0 278/ 4 0 85 0 e8 5 81 0 280/ 0 0 60 5 69 f0 2 0 288/ 85 0 e8 5 85 0 10 7 290/ 81 0 0 0 34 5 69 f0 298/ 4 0 3 10 0 0 a9 0 2a0/ ce 2 85 0 e8 5 85 0 2a8/ 14 7 81 0 0 0 34 5 2b0/ 69 f0 4 0 3 10 0 0 2b8/ a9 0 e0 2 85 0 17 7 2c0/ 81 0 0 0 20 4 69 f0 2c8/ 2 0 bd 0 5a 2 85 0 2d0/ 33 7 81 0 0 0 3e 4 2d8/ 69 f0 2 0 bd 0 10 4 2e0/ 85 0 4e 7 81 0 0 0 2e8/ 3e 4 69 f0 2 0 85 0 2f0/ 68 0 81 0 0 0 16 4 2f8/ 69 f0 2 0 ec e1 fc ff 300/ ed 10 0 0 0 0 ed 10 308/ 2 0 0 0 69 10 4 0 310/ 84 10 81 0 0 0 60 5 318/ 69 f0 2 0 e3 1e fe ff 320/ 69 10 4 0 84 10 e3 1e 328/ fc ff 69 10 4 0 84 10 330/ 85 0 85 7 81 0 0 0 338/ 3e 4 69 f0 6 0 85 0 340/ 68 0 81 0 0 0 16 4 348/ 69 f0 2 0 ec e1 fa ff 350/ 69 10 4 0 84 10 81 0 358/ 0 0 60 5 69 f0 2 0 360/ e3 10 68 6 69 10 1 0 368/ ec 1 68 6 e3 1e fc ff 370/ 69 10 4 0 84 10 85 0 378/ c0 7 81 0 0 0 3e 4 380/ 69 f0 4 0 85 0 e8 5 388/ 81 0 0 0 60 5 69 f0 390/ 2 0 85 0 e8 5 85 0 398/ 10 7 81 0 0 0 34 5 3a0/ 69 f0 4 0 3 10 0 0 3a8/ a9 0 d8 3 85 0 e8 5 3b0/ 85 0 14 7 81 0 0 0 3b8/ 34 5 69 f0 4 0 3 10 3c0/ 0 0 a9 0 f4 3 85 0 3c8/ 17 7 81 0 0 0 3e 4 3d0/ 69 f0 2 0 bd 0 6c 3 3d8/ e3 1e fa ff e3 2e fe ff 3e0/ e3 3e fc ff ec 13 0 0 3e8/ ec 12 2 0 ec e1 fe ff 3f0/ bd 0 10 4 e3 1e fa ff 3f8/ e3 2e fe ff e3 3e fc ff 400/ ec 12 0 0 ec 13 2 0 408/ ec e1 fe ff bd 0 10 4 410/ e3 1e fe ff 4 0 e3 2e 418/ 4 0 e0 1d 68 d2 4 0 420/ e3 1e 4 0 f2 21 a9 0 428/ 3c 4 fc 2 11 0 fd 0 430/ 10 0 1 0 69 10 1 0 438/ bd 0 24 4 4 0 6b f0 440/ 4 0 e0 3e 69 30 6 0 448/ e3 1e 4 0 f2 21 a9 0 450/ d2 4 3 20 25 0 a1 0 458/ c0 4 69 10 1 0 f2 21 460/ 69 10 1 0 3 20 73 0 468/ a1 0 92 4 ec e1 fe ff 470/ ec e3 fc ff e2 23 84 20 478/ 81 0 0 0 20 4 69 f0 480/ 2 0 e3 1e fe ff e3 3e 488/ fc ff 69 30 2 0 bd 0 490/ 4c 4 3 20 64 0 a1 0 498/ 4c 4 ec e1 fe ff ec e3 4a0/ fc ff e2 23 84 20 81 0 4a8/ 0 0 d4 4 69 f0 2 0 4b0/ e3 1e fe ff e3 3e fc ff 4b8/ 69 30 2 0 bd 0 4c 4 4c0/ fc 2 11 0 fd 0 10 0 4c8/ 1 0 69 10 1 0 bd 0 4d0/ 4c 4 4 0 e3 1e 4 0 4d8/ a9 0 ea 4 84 10 81 0 4e0/ 0 0 f8 4 69 f0 2 0 4e8/ 4 0 fd 0 11 0 30 0 4f0/ fd 0 10 0 1 0 4 0 4f8/ 6b f0 2 0 e3 1e 4 0 500/ a9 0 32 5 e0 21 79 20 508/ a 0 e0 31 71 30 a 0 510/ ec e3 fe ff 84 20 81 0 518/ 0 0 f8 4 69 f0 2 0 520/ e3 3e fe ff 69 30 30 0 528/ fc 3 11 0 fd 0 10 0 530/ 1 0 4 0 e3 2e 4 0 538/ e3 3e 6 0 f2 12 a9 0 540/ 5a 5 f2 43 a9 0 5a 5 548/ 6a 14 a1 0 5e 5 69 20 550/ 1 0 69 30 1 0 bd 0 558/ 3c 5 f2 43 6a 14 4 0 560/ e3 1e 4 0 e0 41 f3 20 568/ 10 0 51 20 2 0 a9 0 570/ 66 5 f3 30 11 0 fd 0 578/ 10 0 2 0 3 30 d 0 580/ a9 0 d6 5 3 30 8 0 588/ a9 0 a8 5 3 30 7f 0 590/ a9 0 a8 5 fc 3 11 0 598/ fd 0 10 0 1 0 f8 13 5a0/ 69 10 1 0 bd 0 66 5 5a8/ 2 14 b5 0 c4 5 f1 30 5b0/ 7f 0 6b 10 1 0 fc 3 5b8/ 11 0 fd 0 10 0 1 0 5c0/ bd 0 66 5 f1 30 7 0 5c8/ fc 3 11 0 fd 0 10 0 5d0/ 1 0 bd 0 66 5 fd 0 5d8/ 11 0 a 0 fd 0 10 0 5e0/ 1 0 f9 10 0 0 4 0 66c/ 0 0 0 0 61 61 72 64 674/ 76 61 72 6b 0 a 57 65 67c/ 6c 63 6f 6d 65 20 74 6f 684/ 20 41 6e 69 6d 61 6c 73 68c/ 2e a 0 a 54 68 69 6e 694/ 6b 20 6f 66 20 61 6e 20 69c/ 61 6e 69 6d 61 6c 20 61 6a4/ 6e 64 20 49 20 77 69 6c 6ac/ 6c 20 74 72 79 20 74 6f 6b4/ 20 67 75 65 73 73 20 77 6bc/ 68 61 74 20 69 74 20 69 6c4/ 73 2e a 0 49 20 63 75 6cc/ 72 72 65 6e 74 6c 79 20 6d4/ 6b 6e 6f 77 20 25 64 20 6dc/ 61 6e 69 6d 61 6c 73 2e 6e4/ a a 0 49 73 20 74 68 6ec/ 65 20 61 6e 69 6d 61 6c 6f4/ 20 79 6f 75 20 61 72 65 6fc/ 20 74 68 69 6e 6b 69 6e 704/ 67 20 6f 66 20 61 20 25 70c/ 73 3f 20 0 79 65 73 0 714/ 6e 6f 0 50 6c 65 61 73 71c/ 65 20 74 79 70 65 20 27 724/ 79 65 73 27 20 6f 72 20 72c/ 27 6e 6f 27 2e a 0 49 734/ 20 67 75 65 73 73 65 64 73c/ 20 79 6f 75 72 20 61 6e 744/ 69 6d 61 6c 21 21 21 a 74c/ a 0 49 20 63 6f 75 6c 754/ 64 20 6e 6f 74 20 67 75 75c/ 65 73 73 20 79 6f 75 72 764/ 20 61 6e 69 6d 61 6c 2e 76c/ 20 20 57 68 61 74 20 77 774/ 61 73 20 79 6f 75 72 20 77c/ 61 6e 69 6d 61 6c 3f 20 784/ 0 45 6e 74 65 72 20 61 78c/ 20 71 75 65 73 74 69 6f 794/ 6e 20 74 68 61 74 20 77 79c/ 6f 75 6c 64 20 64 69 73 7a4/ 74 69 6e 67 75 69 73 68 7ac/ 20 61 20 25 73 20 66 72 7b4/ 6f 6d 20 61 20 25 73 2e 7bc/ a 3e 20 0 54 68 65 20 7c4/ 63 6f 72 72 65 63 74 20 7cc/ 61 6e 73 77 65 72 20 66 7d4/ 6f 72 20 61 20 25 73 20 7dc/ 69 73 3f 20 0 a 0 3f 7e4/ 20 0 tkgate-2.0-b10/locale/en/examples/ex5/menagerie.v~000644 001751 001751 00000275644 11145417513 022533 0ustar00hansenhansen000000 000000 //: version "2.0-b7" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "menagerie.v" //: property simAutoStart = 1 //: property discardChanges = 1 //: property timingViolationMode = 1 //: property initTime = "3 us" //: script "menagerie.vs" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /symbolBegin: 688834864 //: /iconBegin normal 3404 0 0 //: /data "#define bitmap_width 73" //: /data "#define bitmap_height 53" //: /data "static unsigned char bitmap_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x08, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xe8, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48," //: /data " 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x48, 0x80, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x3f, 0x88, 0x48, 0x80, 0x01, 0x00, 0x50," //: /data " 0x00, 0x00, 0x00, 0x50, 0x88, 0x48, 0x80, 0x01, 0x00, 0x28, 0x00, 0x00," //: /data " 0x00, 0x88, 0x88, 0x38, 0x80, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xc4," //: /data " 0x08, 0x00, 0x80, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xa2, 0x08, 0x00," //: /data " 0x80, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x91, 0xe8, 0x38, 0x80, 0x00," //: /data " 0x80, 0x02, 0x00, 0x00, 0x80, 0x88, 0x28, 0x49, 0x80, 0x01, 0x40, 0x01," //: /data " 0x00, 0x00, 0x40, 0x84, 0x28, 0x49, 0x80, 0x01, 0xa0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0x82, 0xe8, 0x48, 0x80, 0x01, 0x60, 0x00, 0x00, 0x00, 0x40, 0x81," //: /data " 0x28, 0x49, 0x80, 0x01, 0x20, 0xff, 0xff, 0xff, 0x8f, 0x80, 0x28, 0x39," //: /data " 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x7c," //: /data " 0xef, 0x03, 0xa0, 0x80, 0xe8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x2f, 0x11, 0x81, 0x00, 0xa0, 0xdc, 0x0f, 0x00, 0xa0, 0x80," //: /data " 0x28, 0x11, 0x87, 0x01, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0xef, 0x10," //: /data " 0x88, 0x01, 0xa0, 0x7c, 0xbf, 0x01, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11, 0x86, 0x00, 0xa0, 0x04," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x08, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0x0f, 0x00, 0x80, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0xc8, 0x7c, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x11," //: /data " 0x81, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x28, 0x10, 0x8f, 0x01," //: /data " 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80, 0x2f, 0x10, 0x88, 0x01, 0xa0, 0x00," //: /data " 0x00, 0x00, 0xa0, 0x80, 0x28, 0x11, 0x89, 0x01, 0xa0, 0x00, 0x00, 0x00," //: /data " 0xa0, 0x80, 0xc8, 0x10, 0x86, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xa0, 0x80," //: /data " 0x08, 0x00, 0x80, 0x00, 0x20, 0x01, 0x00, 0x00, 0x90, 0x80, 0x08, 0x00," //: /data " 0x80, 0x00, 0x20, 0xfe, 0xff, 0xff, 0x8f, 0x80, 0xe8, 0x30, 0x87, 0x00," //: /data " 0x60, 0x00, 0x00, 0x00, 0xc0, 0x80, 0x28, 0x09, 0x89, 0x00, 0xa0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0x80, 0x28, 0x79, 0x89, 0x01, 0x10, 0x00, 0x00, 0x00," //: /data " 0x40, 0x80, 0x28, 0x41, 0x87, 0x01, 0xd0, 0xff, 0xff, 0xff, 0x4f, 0x80," //: /data " 0x28, 0x49, 0x89, 0x01, 0xc8, 0xaa, 0xaa, 0xaa, 0x2a, 0x40, 0xe8, 0x30," //: /data " 0x89, 0x00, 0xa8, 0xff, 0xff, 0xff, 0x27, 0x20, 0x08, 0x00, 0x80, 0x00," //: /data " 0xa4, 0xaa, 0xaa, 0xaa, 0x16, 0x10, 0x08, 0x00, 0x80, 0x00, 0xf4, 0xff," //: /data " 0xff, 0xff, 0x13, 0x08, 0xe8, 0x7c, 0x87, 0x00, 0x92, 0xaa, 0xaa, 0xaa," //: /data " 0x0a, 0x04, 0x28, 0x11, 0x89, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x0b, 0x02," //: /data " 0x28, 0x11, 0x89, 0x01, 0x01, 0x00, 0x00, 0x00, 0x04, 0x01, 0x28, 0x11," //: /data " 0x87, 0x01, 0xff, 0xff, 0xff, 0xff, 0x87, 0x00, 0x28, 0x11, 0x89, 0x01," //: /data " 0x01, 0x00, 0x00, 0x00, 0x44, 0x00, 0xe8, 0x10, 0x89, 0x00, 0x01, 0x00," //: /data " 0x00, 0x00, 0x24, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00," //: /data " 0x14, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /iconBegin select 3389 0 0 //: /data "#define x_width 73" //: /data "#define x_height 53" //: /data "static unsigned char x_bits[] = {" //: /data " 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 0x00, 0x00," //: /data " 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00," //: /data " 0xf8, 0x7b, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0xd9," //: /data " 0xc0, 0x01, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 0x98, 0xd9, 0xc0, 0x01," //: /data " 0x00, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x70," //: /data " 0x00, 0x00, 0x00, 0xf8, 0x98, 0xd9, 0xc0, 0x01, 0x00, 0x38, 0x00, 0x00," //: /data " 0x00, 0xcc, 0x98, 0x79, 0xc0, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0xe6," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0xf3, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x00, 0x07, 0x00, 0x00, 0x80, 0xd9, 0xf8, 0x79, 0xc0, 0x00," //: /data " 0x80, 0x03, 0x00, 0x00, 0xc0, 0xcc, 0x78, 0xdb, 0xc0, 0x01, 0xc0, 0xff," //: /data " 0xff, 0xff, 0x7f, 0xc6, 0x78, 0xdb, 0xc0, 0x01, 0xe0, 0xff, 0xff, 0xff," //: /data " 0x3f, 0xc3, 0xf8, 0xd9, 0xc0, 0x01, 0x60, 0x00, 0x00, 0x00, 0xc0, 0xc1," //: /data " 0x78, 0xdb, 0xc0, 0x01, 0x60, 0xff, 0xff, 0xff, 0x8f, 0xc1, 0x78, 0x7b," //: /data " 0xc0, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x9f, 0xc1, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x7c," //: /data " 0xef, 0x03, 0xb0, 0xc1, 0xf8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x7f, 0x33, 0xc3, 0x00, 0xe0, 0xdc, 0x0f, 0x00, 0xb0, 0xc1," //: /data " 0x78, 0x33, 0xcf, 0x01, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0xff, 0x30," //: /data " 0xd8, 0x01, 0xe0, 0x7c, 0xbf, 0x01, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33, 0xce, 0x00, 0xe0, 0x04," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x18, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0x1f, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0xd8, 0x7d, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x33," //: /data " 0xc3, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x30, 0xdf, 0x01," //: /data " 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1, 0x7f, 0x30, 0xd8, 0x01, 0xe0, 0x00," //: /data " 0x00, 0x00, 0xb0, 0xc1, 0x78, 0x33, 0xdb, 0x01, 0xe0, 0x00, 0x00, 0x00," //: /data " 0xb0, 0xc1, 0xd8, 0x31, 0xce, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xb0, 0xc1," //: /data " 0x18, 0x00, 0xc0, 0x00, 0x60, 0x01, 0x00, 0x00, 0x98, 0xc1, 0x18, 0x00," //: /data " 0xc0, 0x00, 0x60, 0xfe, 0xff, 0xff, 0x8f, 0xc1, 0xf8, 0x70, 0xc7, 0x00," //: /data " 0xe0, 0xff, 0xff, 0xff, 0xff, 0xc1, 0x78, 0x1b, 0xdb, 0x00, 0xe0, 0xff," //: /data " 0xff, 0xff, 0xbf, 0xc1, 0x78, 0xfb, 0xdb, 0x01, 0x30, 0x00, 0x00, 0x00," //: /data " 0xe0, 0xc0, 0x78, 0xc3, 0xcf, 0x01, 0xf0, 0xff, 0xff, 0xff, 0x6f, 0xc0," //: /data " 0x78, 0xdb, 0xdb, 0x01, 0xd8, 0xaa, 0xaa, 0xaa, 0x3a, 0x60, 0xf8, 0x70," //: /data " 0xdb, 0x00, 0xb8, 0xff, 0xff, 0xff, 0x37, 0x30, 0x18, 0x00, 0xc0, 0x00," //: /data " 0xac, 0xaa, 0xaa, 0xaa, 0x1e, 0x18, 0x18, 0x00, 0xc0, 0x00, 0xfc, 0xff," //: /data " 0xff, 0xff, 0x1b, 0x0c, 0xf8, 0x7c, 0xc7, 0x00, 0x96, 0xaa, 0xaa, 0xaa," //: /data " 0x0e, 0x06, 0x78, 0x33, 0xdb, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x0f, 0x03," //: /data " 0x78, 0x33, 0xdb, 0x01, 0x03, 0x00, 0x00, 0x00, 0x86, 0x01, 0x78, 0x33," //: /data " 0xc7, 0x01, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x00, 0x78, 0x33, 0xdb, 0x01," //: /data " 0xff, 0xff, 0xff, 0xff, 0x67, 0x00, 0xf8, 0x30, 0xdb, 0x00, 0x03, 0x00," //: /data " 0x00, 0x00, 0x36, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x03, 0x00, 0x00, 0x00," //: /data " 0x1e, 0x00, 0xf8, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00," //: /data " 0xf8, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00," //: /data " 0x00, 0x00};" //: /iconEnd //: /port output TD[7:0] @(73, 5) /r:0 //: /port input DSR @(73, 38) /r:0 //: /port output RTS @(73, 22) /r:0 //: /port input RD[7:0] @(73, 13) /r:0 //: /port input CTS @(73, 30) /r:0 //: /port output DTR @(73, 46) /r:0 //: /symbolEnd //: /netlistBegin main module main; //: root_module reg _reset; //: {0}(50:749,83)(749,31)(543,31){1} //: {2}(539,31)(353,31){3} //: {4}(349,31)(154,31){5} //: {6}(351,33)(351,83){7} //: {8}(541,33)(541,83){9} wire w32; //: /sn:0 {0}(589,342)(659,342){1} wire [3:0] w45; //: /sn:0 {0}(#:589,102)(659,102){1} wire [3:0] w46; //: /sn:0 {0}(#:589,117)(659,117){1} wire w56; //: /sn:0 {0}(589,284)(659,284){1} wire w38; //: /sn:0 {0}(455,157)(394,157){1} wire [7:0] w51; //: /sn:0 {0}(#:589,197)(659,197){1} wire w0; //: /sn:0 {0}(455,270)(394,270){1} wire w37; //: /sn:0 {0}(455,172)(394,172){1} wire w34; //: /sn:0 {0}(589,380)(659,380){1} wire w43; //: /sn:0 {0}(455,220)(394,220){1} wire w54; //: /sn:0 {0}(589,249)(659,249){1} wire w58; //: /sn:0 {0}(589,323)(659,323){1} wire [15:0] DATA; //: {0}(#:50:727,438)(727,473)(519,473){1} //: {2}(517,471)(517,438){3} //: {4}(515,473)(328,473)(328,438){5} wire w36; //: /sn:0 {0}(455,188)(394,188){1} wire w41; //: /sn:0 {0}(455,109)(394,109){1} wire w35; //: /sn:0 {0}(589,398)(659,398){1} wire w40; //: /sn:0 {0}(455,126)(394,126){1} wire w53; //: /sn:0 {0}(589,235)(659,235){1} wire w59; //: /sn:0 {0}(455,255)(394,255){1} wire w44; //: /sn:0 {0}(455,204)(394,204){1} wire [1:0] w49; //: /sn:0 {0}(#:589,165)(659,165){1} wire w57; //: /sn:0 {0}(589,304)(659,304){1} wire clk; //: {0}(50:694,83)(694,66)(494,66){1} //: {2}(490,66)(303,66){3} //: {4}(299,66)(146,66){5} //: {6}(301,68)(301,83){7} //: {8}(492,68)(492,83){9} wire w33; //: /sn:0 {0}(589,360)(659,360){1} wire [1:0] w48; //: /sn:0 {0}(#:589,149)(659,149){1} wire w52; //: /sn:0 {0}(589,217)(659,217){1} wire w47; //: /sn:0 {0}(589,134)(659,134){1} wire w42; //: /sn:0 {0}(455,239)(394,239){1} wire [4:0] w50; //: /sn:0 {0}(#:589,179)(659,179){1} wire w39; //: /sn:0 {0}(455,141)(394,141){1} wire w55; //: /sn:0 {0}(589,266)(659,266){1} //: enddecls //: joint g4 (DATA) @(517, 473) /w:[ 1 2 4 -1 ] //: comment g13 @(17,390) /sn:0 //: /line:"Circuit highlights:" //: /line:"* TTY Device" //: /line:"* Micro Program Counter" //: /line:"* ALU" //: /line:"* Main Memory" //: /line:"* Program Counter" //: /line:"" //: /end //: joint g3 (_reset) @(541, 31) /w:[ 1 -1 2 8 ] //: joint g2 (clk) @(492, 66) /w:[ 1 -1 2 8 ] //: comment g1 @(13,90) //: /line:"This circuit is a simple microprocessor." //: /line:"A simulation script will cause it to start" //: /line:"executing the \"Animals\" game as soon" //: /line:"as you start simulation mode. Click on" //: /line:"the various logic blocks and press the '>'" //: /line:"key to look at the sub-circuits inside." //: /line:"You can return to the parent module by" //: /line:"pressing the '<' key. While in" //: /line:"simulation mode, click on a wire to see" //: /line:"its current value, or double-click to" //: /line:"set a trace." //: /line:"" //: /line:"Click on the links below to view the" //: /line:"contents of supporting files for" //: /line:"this circuit:" //: /line:"" //: /line:"* Microcode/Macrocode Definitions" //: /line:"* Memory Initialization File" //: /line:"* Simulator Script" //: /line:"* Symbol Map" //: /line:"" //: /end IUNIT iunit (._CLR(_reset), .CK(clk), .IR(DATA), .COUT(w35), ._Z(w34), ._GT(w33), ._LT(w32), ._rdpc(w59), ._incmar(w0), ._rd(w44), .spc(w43), ._ldhmdr(w42), ._ldpc(w41), ._ldmar(w40), ._ldmdr(w39), ._incpc(w38), ._rdmdr(w37), ._wrt(w36), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), .SA(w45)); //: @(456, 84) /sz:(132, 353) /p:[ Ti0>9 Ti1>9 Bi0>3 Ri0>0 Ri1>0 Ri2>0 Ri3>0 Lo0<0 Lo1<0 Lo2<0 Lo3<0 Lo4<0 Lo5<0 Lo6<0 Lo7<0 Lo8<0 Lo9<0 Lo10<0 Ro0<0 Ro1<0 Ro2<0 Ro3<0 Ro4<0 Ro5<0 Ro6<0 Ro7<0 Ro8<0 Ro9<0 Ro10<0 Ro11<0 Ro12<0 Ro13<0 ] //: joint g6 (_reset) @(351, 31) /w:[ 3 -1 4 6 ] //: comment g7 @(43,7) /sn:0 //: /line:"This is the" //: /line:"reset switch." //: /end //: comment g9 @(43,50) //: /line:"This is the" //: /line:"system clock." //: /line:" " //: /end MEMORY memory (._CLR(_reset), .CK(clk), ._incmar(w0), ._rdpc(w59), ._ldhmdr(w42), .spc(w43), ._rd(w44), ._wrt(w36), ._rdmdr(w37), ._incpc(w38), ._ldmdr(w39), ._ldmar(w40), ._ldpc(w41), .DATA(DATA)); //: @(268, 84) /sz:(125, 353) /p:[ Ti0>7 Ti1>7 Ri0>1 Ri1>1 Ri2>1 Ri3>1 Ri4>1 Ri5>1 Ri6>1 Ri7>1 Ri8>1 Ri9>1 Ri10>1 Bt0=5 ] //: comment g39 @(12,517) /sn:0 //: /line:"[BACK]" //: /end EUNIT eunit (._CLR(_reset), .CK(clk), ._DOUT(w58), ._LDQL(w57), ._LDQH(w56), ._LDDATA(w55), .SA(w45), .CIN(w54), ._LDQ(w53), ._CLQ(w52), .IDATA(w51), .FUNC(w50), .BOP(w49), .AOP(w48), ._WA(w47), .SB(w46), ._LT(w32), ._GT(w33), ._Z(w34), .COUT(w35), .DATA(DATA)); //: @(660, 84) /sz:(128, 353) /p:[ Ti0>0 Ti1>0 Li0>1 Li1>1 Li2>1 Li3>1 Li4>1 Li5>1 Li6>1 Li7>1 Li8>1 Li9>1 Li10>1 Li11>1 Li12>1 Li13>1 Lo0<1 Lo1<1 Lo2<1 Lo3<1 Bt0=0 ] //: joint g5 (clk) @(301, 66) /w:[ 3 -1 4 6 ] _GGCLOCK_P3000_0_50 g0 (.Z(clk)); //: @(133,66) /sn:0 /w:[ 5 ] /omega:3000 /phi:0 /duty:50 //: SWITCH reset (_reset) @(137,31) /sn:0 /w:[ 5 ] /st:1 endmodule //: /netlistEnd //: /netlistBegin MEMORY module MEMORY(DATA, _wrt, _ldpc, spc, _ldmdr, _rd, _rdmdr, _ldhmdr, _CLR, _rdpc, _incmar, _ldmar, CK, _incpc); //: interface /sz:(125, 353) /bd:[ Ti0>_CLR(83/125) Ti1>CK(33/125) Ri0>_incmar(186/353) Ri1>_rdpc(171/353) Ri2>_ldhmdr(155/353) Ri3>spc(136/353) Ri4>_rd(120/353) Ri5>_wrt(104/353) Ri6>_rdmdr(88/353) Ri7>_incpc(73/353) Ri8>_ldmdr(57/353) Ri9>_ldmar(42/353) Ri10>_ldpc(25/353) Bt0=DATA[15:0](60/125) ] supply0 [5:0] w16; //: /sn:0 {0}(#:545,861)(545,840){1} input _rd; //: /sn:0 {0}(671,557)(671,614){1} //: {2}(673,616)(708,616)(708,273)(740,273){3} //: {4}(669,616)(512,616){5} //: {6}(510,614)(510,579){7} //: {8}(508,616)(482,616){9} input _rdpc; //: /sn:0 {0}(259,285)(270,285)(270,306){1} input CK; //: /sn:0 {0}(753,813)(742,813)(742,833)(618,833)(618,815){1} //: {2}(620,813)(631,813){3} //: {4}(616,813)(524,813)(524,438){5} //: {6}(526,436)(641,436)(641,334)(726,334){7} //: {8}(522,436)(130,436){9} //: {10}(128,434)(128,335){11} //: {12}(130,333)(321,333)(321,307)(326,307){13} //: {14}(128,331)(128,253)(151,253){15} //: {16}(126,436)(62,436){17} reg [15:0] w38; //: /sn:0 {0}(#:210,713)(300,713){1} input _CLR; //: /sn:0 {0}(512,218)(512,201){1} //: {2}(514,199)(844,199)(844,327){3} //: {4}(842,329)(802,329){5} //: {6}(844,331)(844,770){7} //: {8}(842,772)(716,772)(716,808)(707,808){9} //: {10}(844,774)(844,808)(829,808){11} //: {12}(510,199)(409,199){13} //: {14}(405,199)(263,199)(263,248)(227,248){15} //: {16}(407,201)(407,302)(402,302){17} supply0 [7:0] w3; //: /sn:0 {0}(#:683,269)(683,251)(662,251){1} input _ldmar; //: /sn:0 {0}(458,247)(458,314)(438,314){1} input _wrt; //: /sn:0 {0}(691,706)(424,706){1} //: {2}(422,704)(422,510){3} //: {4}(424,508)(454,508){5} //: {6}(420,508)(399,508){7} //: {8}(422,708)(422,758)(692,758){9} input _ldhmdr; //: /sn:0 {0}(673,103)(709,103){1} //: {2}(713,103)(871,103)(871,269){3} //: {4}(711,105)(711,137){5} supply0 [15:0] w21; //: /sn:0 {0}(#:220,59)(220,42)(194,42)(194,69){1} inout [15:0] DATA; //: /sn:0 {0}(#:278,311)(297,311)(297,213)(371,213){1} //: {2}(373,211)(373,167){3} //: {4}(375,165)(508,165){5} //: {6}(512,165)(547,165){7} //: {8}(551,165)(568,165){9} //: {10}(549,167)(549,246)(616,246){11} //: {12}(510,163)(510,134){13} //: {14}(371,165)(198,165)(198,188){15} //: {16}(373,215)(373,248){17} input _ldpc; //: /sn:0 {0}(233,131)(217,131)(217,152)(148,152){1} //: {2}(144,152)(131,152){3} //: {4}(146,154)(146,204)(165,204){5} supply0 w23; //: /sn:0 {0}(829,818)(844,818)(844,836){1} supply1 w20; //: /sn:0 {0}(241,70)(241,83)(202,83){1} supply0 [7:0] w24; //: /sn:0 {0}(#:595,538)(595,523){1} supply0 [7:0] w1; //: /sn:0 {0}(#:800,724)(800,677)(825,677)(825,687){1} input _rdmdr; //: /sn:0 {0}(624,284)(624,251){1} reg [15:0] w40; //: /sn:0 {0}(#:212,765)(301,765){1} input _incpc; //: /sn:0 {0}(233,126)(133,126){1} supply0 w17; //: /sn:0 {0}(496,579)(496,592){1} input spc; //: /sn:0 {0}(251,380)(207,380){1} input _ldmdr; //: /sn:0 {0}(876,269)(876,80)(673,80){1} input _incmar; //: /sn:0 {0}(438,309)(448,309)(448,281)(327,281){1} //: {2}(325,279)(325,266){3} //: {4}(327,264)(340,264){5} //: {6}(325,262)(325,243){7} //: {8}(325,283)(325,293)(313,293)(313,326)(223,326)(223,411)(96,411)(96,383){9} wire [15:0] w6; //: /sn:0 {0}(#:162,69)(162,47)(70,47)(70,360)(83,360){1} wire [7:0] mdrin; //: /sn:0 {0}(#:520,552)(557,552){1} //: {2}(561,552)(663,552){3} //: {4}(559,550)(559,523){5} wire w46; //: /sn:0 {0}(402,312)(417,312){1} wire w14; //: /sn:0 {0}(254,129)(272,129)(272,258)(227,258){1} wire [15:0] w4; //: /sn:0 {0}(#:584,165)(614,165){1} wire [15:0] w19; //: /sn:0 {0}(#:188,217)(188,243){1} wire w15; //: /sn:0 {0}(691,711)(645,711){1} //: {2}(643,709)(643,672){3} //: {4}(641,711)(436,711){5} //: {6}(434,709)(434,512)(454,512){7} //: {8}(432,711)(365,711){9} wire w; //: /sn:0 {0}(802,339)(874,339)(874,290){1} wire [15:0] PC; //: /sn:0 {0}(#:188,264)(188,309){1} //: {2}(190,311)(262,311){3} //: {4}(188,313)(188,348){5} //: {6}(190,350)(264,350)(264,364){7} //: {8}(186,350)(112,350){9} wire w37; //: /sn:0 {0}(713,761)(722,761)(722,818)(707,818){1} wire DTR; //: /sn:0 {0}(433,982)(565,982)(565,840){1} wire [7:0] w34; //: /sn:0 {0}(#:555,834)(555,668)(571,668)(571,523){1} wire [15:0] w43; //: /sn:0 {0}(#:363,297)(363,277){1} wire RTS; //: /sn:0 {0}(433,958)(555,958)(555,840){1} wire w31; //: /sn:0 {0}(366,763)(446,763){1} //: {2}(450,763)(631,763){3} //: {4}(635,763)(692,763){5} //: {6}(633,761)(633,672){7} //: {8}(448,761)(448,515)(454,515){9} wire [15:0] w28; //: /sn:0 {0}(#:344,711)(321,711){1} wire [7:0] w36; //: /sn:0 {0}(#:790,753)(790,803){1} wire DSR; //: /sn:0 {0}(433,974)(800,974)(800,858){1} wire CTS; //: /sn:0 {0}(790,858)(790,966)(433,966){1} wire [7:0] w25; //: /sn:0 {0}(#:763,286)(763,324){1} wire [15:0] w18; //: /sn:0 {0}(#:274,393)(274,550){1} //: {2}(276,552)(485,552){3} //: {4}(274,554)(274,706){5} //: {6}(276,708)(300,708){7} //: {8}(274,710)(274,760)(301,760){9} wire [7:0] w8; //: /sn:0 {0}(#:620,170)(695,170){1} wire [5:0] w35; //: /sn:0 {0}(#:780,858)(780,881)(760,881){1} wire [15:0] w30; //: /sn:0 {0}(#:345,763)(322,763){1} wire w22; //: /sn:0 {0}(154,83)(144,83){1} wire w11; //: /sn:0 {0}(503,529)(503,512)(475,512){1} wire [15:0] w2; //: /sn:0 {0}(#:656,246)(632,246){1} wire [7:0] mdr; //: /sn:0 {0}(#:780,724)(780,676)(724,676){1} //: {2}(722,674)(722,552)(699,552){3} //: {4}(697,550)(697,379){5} //: {6}(699,377)(763,377)(763,345){7} //: {8}(697,375)(697,241)(662,241){9} //: {10}(695,552)(679,552){11} //: {12}(720,676)(668,676)(668,803){13} wire [7:0] RD; //: /sn:0 {0}(#:433,949)(668,949)(668,824){1} wire [15:0] mar; //: /sn:0 {0}(#:363,318)(363,349){1} //: {2}(361,351)(284,351)(284,364){3} //: {4}(363,353)(363,400)(136,400)(136,370)(112,370){5} wire [7:0] w13; //: /sn:0 {0}(#:753,257)(753,222)(577,222)(577,494){1} wire [1:0] w27; //: /sn:0 {0}(#:600,507)(638,507)(638,666){1} wire [7:0] w5; //: /sn:0 {0}(#:620,160)(661,160)(661,150)(695,150){1} wire [7:0] w33; //: /sn:0 {0}(#:790,852)(790,824){1} wire [7:0] w42; //: /sn:0 {0}(#:773,257)(773,160)(724,160){1} wire [15:0] w9; //: /sn:0 {0}(#:178,188)(178,114){1} //: {2}(178,110)(178,98){3} //: {4}(180,112)(353,112)(353,248){5} wire [7:0] TD; //: /sn:0 {0}(#:433,941)(583,941)(583,523){1} wire w26; //: /sn:0 {0}(712,709)(745,709)(745,740)(767,740){1} //: enddecls //: joint g61 (w31) @(448, 763) /w:[ 2 8 1 -1 ] //: INOUT g8 (DATA) @(510,128) /sn:0 /R:3 /w:[ 13 ] //: joint g4 (_rd) @(510, 616) /w:[ 5 6 8 -1 ] //: joint g3 (_CLR) @(512, 199) /w:[ 2 -1 12 1 ] //: joint g55 (CK) @(524, 436) /w:[ 6 -1 8 5 ] //: joint g86 (_wrt) @(422, 508) /w:[ 4 -1 6 3 ] //: IN g13 (_wrt) @(397,508) /sn:0 /w:[ 7 ] //: IN g34 (_ldpc) @(129,152) /sn:0 /w:[ 3 ] //: IN g37 (spc) @(205,380) /sn:0 /w:[ 1 ] _GGREG8 #(10, 10, 20) g51 (.Q(RD), .D(mdr), .EN(w37), .CLR(_CLR), .CK(CK)); //: @(668,813) /sn:0 /w:[ 1 13 1 9 3 ] //: joint g58 (_CLR) @(844, 772) /w:[ -1 7 8 10 ] //: comment g89 @(37,543) /sn:0 //: /line:"This is the memory address line." //: /line:"The address can be selected from" //: /line:"the MAR (Memory Address Register)" //: /line:"or from the PC (Program Counter)." //: /end //: IN g77 (_ldmdr) @(671,80) /sn:0 /w:[ 1 ] //: joint g76 (w9) @(178, 112) /w:[ 2 1 4 -1 ] //: joint g65 (mdr) @(722, 676) /w:[ 1 2 12 -1 ] //: IN g2 (_rd) @(480,616) /sn:0 /w:[ 9 ] _GGNAND2 #(6) g59 (.I0(!_wrt), .I1(w31), .Z(w37)); //: @(703,761) /sn:0 /w:[ 9 5 0 ] /eb:0 //: GROUND g1 (w17) @(496,598) /sn:0 /w:[ 1 ] _GGREG16 #(10, 10, 20) PC (.Q(PC), .D(w19), .EN(w14), .CLR(_CLR), .CK(CK)); //: @(188,253) /w:[ 0 1 1 15 15 ] _GGBUFIF16 #(4, 6) g72 (.Z(DATA), .I(PC), .E(~_rdpc)); //: @(268,311) /sn:0 /w:[ 0 3 1 ] //: joint g64 (_wrt) @(422, 706) /w:[ 1 2 -1 8 ] _GGMUX4x8 #(12, 12) g11 (.I0(mdrin), .I1(w34), .I2(TD), .I3(w24), .S(w27), .Z(w13)); //: @(577,507) /sn:0 /R:2 /w:[ 5 1 1 1 0 1 ] /ss:0 /do:1 //: frame g16 @(110,659) /sn:0 /wi:762 /ht:347 /tx:"TTY Control" //: joint g10 (CK) @(128, 333) /w:[ 12 14 -1 11 ] //: comment g87 @(210,776) //: /line:"These dip switches specify the" //: /line:"addresses for the tty status" //: /line:"and data registers." //: /end //: joint g78 (PC) @(188, 350) /w:[ 6 5 8 -1 ] _GGADD16 #(132, 134, 126, 128) g28 (.A(w6), .B(w21), .S(w9), .CI(w20), .CO(w22)); //: @(178,85) /sn:0 /w:[ 0 1 3 1 0 ] assign {w35, CTS, DSR} = w33; //: CONCAT g50 @(790,853) /sn:0 /R:1 /w:[ 0 0 1 0 ] /dr:0 /tp:0 /drp:0 _GGMUX2x16 #(8, 8) g32 (.I0(w9), .I1(DATA), .S(_incmar), .Z(w43)); //: @(363,264) /sn:0 /w:[ 5 17 5 1 ] /ss:0 /do:0 //: joint g19 (mdr) @(697, 552) /w:[ 3 4 10 -1 ] //: joint g27 (DATA) @(373, 165) /w:[ 4 -1 14 3 ] //: IN g6 (_rdmdr) @(624,286) /sn:0 /R:1 /w:[ 0 ] //: IN g69 (_ldhmdr) @(671,103) /sn:0 /w:[ 0 ] //: joint g38 (DATA) @(549, 165) /w:[ 8 -1 7 10 ] _GGRAM16x8 #(10, 60, 70, 10, 10, 10) m1 (.A(w18), .D(mdrin), .WE(w11), .OE(_rd), .CS(w17)); //: @(503,553) /w:[ 3 0 0 7 0 ] //: joint g75 (DATA) @(373, 213) /w:[ -1 2 1 16 ] _GGBUFIF8 #(4, 6) g7 (.Z(mdrin), .I(mdr), .E(_rd)); //: @(673,552) /sn:0 /R:2 /w:[ 3 11 0 ] _GGMUX2x8 #(8, 8) g9 (.I0(w13), .I1(w42), .S(_rd), .Z(w25)); //: @(763,273) /sn:0 /w:[ 0 0 3 0 ] /ss:0 /do:0 _GGREG8 #(10, 10, 20) g53 (.Q(w33), .D(w36), .EN(w23), .CLR(_CLR), .CK(CK)); //: @(790,813) /sn:0 /w:[ 1 1 0 11 0 ] //: joint g57 (_CLR) @(844, 329) /w:[ -1 3 4 6 ] _GGMUX2x16 #(8, 8) g31 (.I0(PC), .I1(mar), .S(~_incmar), .Z(w6)); //: @(96,360) /sn:0 /R:3 /w:[ 9 5 9 1 ] /ss:1 /do:0 //: joint g71 (_ldhmdr) @(711, 103) /w:[ 2 -1 1 4 ] assign {w8, w5} = w4; //: CONCAT g15 @(615,165) /sn:0 /R:2 /w:[ 0 0 1 ] /dr:0 /tp:0 /drp:0 //: GROUND g20 (w3) @(683,275) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g68 (.I0(w5), .I1(w8), .S(~_ldhmdr), .Z(w42)); //: @(711,160) /sn:0 /R:1 /w:[ 1 1 5 1 ] /ss:1 /do:1 //: GROUND g67 (w23) @(844,842) /sn:0 /w:[ 1 ] _GGXOR2x16 #(8) g39 (.I0(w18), .I1(w38), .Z(w28)); //: @(311,711) /sn:0 /w:[ 7 1 1 ] /eb:0 //: joint g43 (w18) @(274, 552) /w:[ 2 1 -1 4 ] //: GROUND g48 (w16) @(545,867) /sn:0 /w:[ 0 ] //: IN g88 (_CLR) @(512,220) /sn:0 /R:1 /w:[ 0 ] //: joint g17 (DATA) @(510, 165) /w:[ 6 12 5 -1 ] _GGMUX2x16 #(8, 8) g25 (.I0(PC), .I1(mar), .S(~spc), .Z(w18)); //: @(274,380) /sn:0 /w:[ 7 3 0 0 ] /ss:0 /do:0 //: VDD g29 (w20) @(252,70) /sn:0 /w:[ 0 ] _GGNAND2 #(6) g62 (.I0(!_wrt), .I1(w15), .Z(w26)); //: @(702,709) /sn:0 /w:[ 0 0 0 ] /eb:0 //: IN g73 (_rdpc) @(257,285) /sn:0 /w:[ 0 ] //: joint g52 (mdr) @(697, 377) /w:[ 6 8 -1 5 ] _GGNOR1x16 #(1) g42 (.I0(w30), .Z(w31)); //: @(356,763) /sn:0 /w:[ 0 0 ] /eb:0 //: joint g63 (w15) @(643, 711) /w:[ 1 2 4 -1 ] _GGNOR2 #(6) g83 (.I0(!_incmar), .I1(!_ldmar), .Z(w46)); //: @(427,312) /sn:0 /R:2 /w:[ 0 1 1 ] /eb:0 //: joint g74 (PC) @(188, 311) /w:[ 2 1 -1 4 ] //: joint g5 (_CLR) @(407, 199) /w:[ 13 -1 14 16 ] //: frame g14 @(536,27) /sn:0 /wi:372 /ht:394 /tx:"MDR Control" //: joint g56 (CK) @(618, 813) /w:[ 2 -1 4 1 ] //: IN g80 (_incmar) @(325,241) /sn:0 /R:3 /w:[ 7 ] //: joint g79 (mar) @(363, 351) /w:[ -1 1 2 4 ] //: joint g44 (w18) @(274, 708) /w:[ 6 5 -1 8 ] assign w34 = {w16, RTS, DTR}; //: CONCAT g47 @(555,835) /sn:0 /R:1 /w:[ 0 1 1 1 ] /dr:0 /tp:0 /drp:1 //: joint g24 (CK) @(128, 436) /w:[ 9 10 16 -1 ] //: joint g85 (w15) @(434, 711) /w:[ 5 6 8 -1 ] _GGOR3 #(8) g84 (.I0(_wrt), .I1(w15), .I2(w31), .Z(w11)); //: @(465,512) /sn:0 /w:[ 5 7 9 1 ] /eb:0 _GGREG8 #(10, 10, 20) mdr (.Q(mdr), .D(w25), .EN(w), .CLR(_CLR), .CK(CK)); //: @(763,334) /w:[ 7 1 0 5 7 ] _GGBUFIF16 #(4, 6) g21 (.Z(DATA), .I(w2), .E(~_rdmdr)); //: @(626,246) /sn:0 /R:2 /w:[ 11 1 1 ] //: joint g36 (_ldpc) @(146, 152) /w:[ 1 -1 2 4 ] //: IN g23 (_ldmar) @(458,245) /sn:0 /R:3 /w:[ 0 ] _GGNOR1x16 #(1) g41 (.I0(w28), .Z(w15)); //: @(355,711) /sn:0 /w:[ 0 9 ] /eb:0 //: DIP TTYSTATUS (w38) @(172,713) /R:1 /w:[ 0 ] /st:16 //: frame g93 @(354,466) /sn:0 /wi:421 /ht:164 /tx:"Main Memory" //: joint g81 (_incmar) @(325, 264) /w:[ 4 6 -1 3 ] _GGMUX2x8 #(8, 8) g54 (.I0(mdr), .I1(w1), .S(w26), .Z(w36)); //: @(790,740) /sn:0 /w:[ 0 0 1 0 ] /ss:0 /do:0 _GGXOR2x16 #(8) g40 (.I0(w18), .I1(w40), .Z(w30)); //: @(312,763) /sn:0 /w:[ 9 1 1 ] /eb:0 //: joint g60 (w31) @(633, 763) /w:[ 4 6 3 -1 ] //: comment g90 @(211,844) /sn:0 //: /line:"This is the tty. When simulation mode" //: /line:"starts, a tty window will be popped up" //: /line:"corresponding to this device. The device" //: /line:"may be accessed through the simulated CPU" //: /line:"by reading or writing the addresses indicated" //: /line:"by the dip switches TTYSTATUS and TTYDATA." //: /end _GGNOR2 #(6) g70 (.I0(!_ldhmdr), .I1(!_ldmdr), .Z(w)); //: @(874,280) /sn:0 /R:3 /w:[ 3 0 1 ] /eb:0 _GGBUF16 #(4) g22 (.I(DATA), .Z(w4)); //: @(574,165) /sn:0 /w:[ 9 0 ] _GGREG16 #(10, 10, 20) mar (.Q(mar), .D(w43), .EN(w46), .CLR(_CLR), .CK(CK)); //: @(363,307) /w:[ 0 0 0 17 13 ] //: IN g0 (CK) @(60,436) /sn:0 /w:[ 17 ] _GGMUX2x16 #(8, 8) g26 (.I0(w9), .I1(DATA), .S(~_ldpc), .Z(w19)); //: @(188,204) /sn:0 /w:[ 0 15 5 0 ] /ss:0 /do:0 _GGNOR2 #(6) g35 (.I0(!_incpc), .I1(!_ldpc), .Z(w14)); //: @(244,129) /sn:0 /w:[ 0 0 0 ] /eb:0 //: joint g45 (mdrin) @(559, 552) /w:[ 2 4 1 -1 ] assign w27 = {w31, w15}; //: CONCAT g46 @(638,667) /sn:0 /R:1 /w:[ 1 7 3 ] /dr:0 /tp:0 /drp:1 TTY tty0 (.TD(TD), .DSR(DSR), .RTS(RTS), .RD(RD), .CTS(CTS), .DTR(DTR)); //: @(396, 962) /symbol:688834864 /w:[ 0 0 0 0 1 0 ] //: joint g82 (_incmar) @(325, 281) /w:[ 1 2 -1 8 ] //: GROUND g66 (w1) @(825,693) /sn:0 /w:[ 1 ] //: DIP TTYDATA (w40) @(174,765) /R:1 /w:[ 0 ] /st:17 assign w2 = {w3, mdr}; //: CONCAT g18 @(657,246) /sn:0 /R:2 /w:[ 0 1 9 ] /dr:0 /tp:0 /drp:1 //: joint g12 (_rd) @(671, 616) /w:[ 2 1 4 -1 ] //: frame g91 @(45,27) /sn:0 /wi:441 /ht:397 /tx:"Address Resolution" //: GROUND g30 (w21) @(220,65) /sn:0 /w:[ 0 ] //: IN g33 (_incpc) @(131,126) /sn:0 /w:[ 1 ] //: GROUND g49 (w24) @(595,544) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin ALUshift module ALUshift(A, B, OUT, FUNC); //: interface /sz:(170, 116) /bd:[ Ti0>FUNC[4:0](121/170) Ti1>B[15:0](82/170) Ti2>A[15:0](34/170) Bo0DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0A[15:0](31/107) Ti1>B[15:0](79/107) Li0>FUNC[4:0](18/127) Li1>CIN(95/127) Bo07 Ti1>5 Ti2>5 Bo0<0 ] //: IN g7 (CIN) @(431,226) /sn:0 /w:[ 0 ] //: OUT g39 (_GT) @(554,503) /sn:0 /w:[ 1 ] //: joint g48 (_Z) @(490, 431) /w:[ 2 -1 1 4 ] _GGOR1x16 #(1) g43 (.I0(OUT), .Z(_Z)); //: @(468,431) /sn:0 /w:[ 3 0 ] /eb:0 //: OUT g42 (_Z) @(553,431) /sn:0 /w:[ 3 ] _GGOR1x3 #(1) g5 (.I0(w0), .Z(w2)); //: @(317,402) /sn:0 /w:[ 0 1 ] /eb:0 _GGNAND2 #(4) g47 (.I0(_LT), .I1(_Z), .Z(_GT)); //: @(522,503) /sn:0 /w:[ 5 5 0 ] /eb:0 //: OUT g41 (OUT) @(406,507) /sn:0 /R:3 /w:[ 7 ] //: OUT g40 (_LT) @(554,467) /sn:0 /w:[ 0 ] ALUbasic g54 (.FUNC(FUNC), .B(B), .A(A), .CIN(CIN), .OUT(w1), .COUT(COUT)); //: @(468, 172) /sz:(165, 122) /sn:0 /p:[ Ti0>5 Ti1>3 Ti2>3 Li0>1 Bo0<1 Ro0<0 ] //: joint g0 (A) @(223, 67) /w:[ 2 -1 1 4 ] assign w3 = OUT[15]; //: TAP g46 @(404,467) /sn:0 /R:2 /w:[ 0 6 5 ] /ss:1 _GGNBUF #(2) g45 (.I(w3), .Z(_LT)); //: @(465,467) /sn:0 /w:[ 1 3 ] //: joint g49 (_LT) @(502, 467) /w:[ 1 -1 2 4 ] endmodule //: /netlistEnd //: /netlistBegin ZREG4 module ZREG4(CK, B, _ENA, SB, _ENB, DIN, _WA, _CLR, SA, A); //: interface /sz:(107, 138) /bd:[ Ti0>DIN[15:0](52/107) Li0>CK(123/138) Li1>_WA(106/138) Li2>_ENB(88/138) Li3>_ENA(70/138) Li4>_CLR(51/138) Li5>SB[1:0](33/138) Li6>SA[1:0](17/138) Bo0_CLR(86/132) Ti1>CK(37/132) Li0>_incmar(187/353) Bi0>IR[15:0](62/132) Ri0>COUT(314/353) Ri1>_Z(296/353) Ri2>_GT(276/353) Ri3>_LT(258/353) Lo0<_rd(121/353) Lo10 Ti1>0 Bo0<1 Ro0<1 Ro1<0 Ro2<1 Ro3<0 Ro4<1 Ro5<1 ] //: joint g6 (_CLR) @(525, 74) /w:[ 2 4 6 1 ] //: IN g69 (_CLR) @(525,61) /sn:0 /R:3 /w:[ 5 ] _GGROM8x32 #(10, 30) m1 (.A(mp_nxtaddr), .D(w26), .OE(w5)); //: @(368,710) /w:[ 5 1 1 ] //: joint g7 (CK) @(102, 120) /w:[ 16 18 -1 15 ] //: OUT g53 (_ldmdr) @(701,1017) /sn:0 /w:[ 0 ] //: OUT g57 (SB) @(766,890) /sn:0 /w:[ 0 ] //: GROUND g9 (w5) @(368,751) /sn:0 /w:[ 0 ] //: OUT g75 (_LDQH) @(701,1127) /sn:0 /w:[ 1 ] //: IN g31 (IR) @(57,70) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g20 (.I0(IDATA), .I1(w27), .S(w35), .Z(w12)); //: @(393,390) /sn:0 /R:3 /w:[ 0 0 1 0 ] /ss:1 /do:0 //: GROUND g15 (w15) @(205,723) /sn:0 /w:[ 1 ] _GGMUX2x4 #(8, 8) g71 (.I0(w45), .I1(w46), .S(w47), .Z(SB)); //: @(725,890) /sn:0 /R:1 /w:[ 0 0 0 1 ] /ss:1 /do:1 //: joint g67 (w6) @(151, 65) /w:[ 2 -1 1 4 ] //: VDD g39 (w19) @(421,649) /sn:0 /w:[ 1 ] _GGMUX2x4 #(8, 8) g68 (.I0(w41), .I1(w39), .S(w43), .Z(SA)); //: @(725,818) /sn:0 /R:1 /w:[ 0 1 0 0 ] /ss:1 /do:1 //: joint g48 (IDATA) @(540, 654) /w:[ 2 1 4 -1 ] //: GROUND g43 (w20) @(455,1042) /sn:0 /w:[ 1 ] //: comment g62 @(370,940) //: /line:"This is the high half" //: /line:"of the microinstruction" //: /line:"memory." //: /end //: GROUND g17 (w23) @(360,367) /sn:0 /w:[ 0 ] _GGNOR2 #(6) g25 (.I0(!w55), .I1(!w32), .Z(_SA0)); //: @(890,384) /sn:0 /R:2 /w:[ 13 0 0 ] /eb:0 _GGMUX2x5 #(8, 8) g73 (.I0(w7), .I1(w49), .S(w42), .Z(FUNC)); //: @(725,956) /sn:0 /R:1 /w:[ 1 1 0 1 ] /ss:1 /do:1 //: joint g29 (ww) @(945, 358) /w:[ 2 4 1 -1 ] //: frame g88 @(176,317) /sn:0 /wi:311 /ht:239 /tx:"Microcode Next Address Generation" //: OUT g52 (_ldmar) @(701,1007) /sn:0 /w:[ 1 ] //: GROUND g42 (w30) @(455,678) /sn:0 /w:[ 1 ] //: joint g63 (CK) @(264, 771) /w:[ 2 4 -1 1 ] //: OUT g83 (_incmar) @(701,1177) /sn:0 /w:[ 0 ] //: OUT g74 (_LDQL) @(701,1117) /sn:0 /w:[ 1 ] //: VDD g14 (w21) @(186,641) /sn:0 /w:[ 0 ] //: joint g5 (mp_nxtaddr) @(331, 709) /w:[ 4 6 -1 3 ] //: OUT g56 (SA) @(766,818) /sn:0 /w:[ 1 ] //: OUT g44 (_incpc) @(701,997) /sn:0 /w:[ 1 ] //: OUT g47 (IDATA) @(690,654) /sn:0 /w:[ 3 ] assign {w4, w55, ww, w32} = w3; //: CONCAT g79 @(1030,353) /sn:0 /w:[ 1 0 3 3 1 ] /dr:0 /tp:0 /drp:0 //: joint g80 (CK) @(102, 276) /w:[ 12 14 -1 11 ] //: comment g84 @(694,22) //: /line:"This is a trival example of an" //: /line:"instruction unit. The mpc register" //: /line:"contains the micro-instruction" //: /line:"program counter, and the two" //: /line:"registers on the data out of ROMs" //: /line:"m1 and m2 are the current micro-" //: /line:"instructions. Note that since these" //: /line:"are two separate registers the a" //: /line:"single cycle jump delay." //: /end //: IN g24 (_LT) @(1168,345) /sn:0 /R:2 /w:[ 0 ] //: IN g21 (COUT) @(1163,375) /sn:0 /R:2 /w:[ 1 ] //: OUT g36 (_LDDATA) @(690,734) /sn:0 /w:[ 0 ] //: comment g85 @(16,131) /sn:0 //: /line:"This block" //: /line:"decodes" //: /line:"insructions" //: /line:"producing" //: /line:"a map index," //: /line:"register" //: /line:"numbers," //: /line:"a function" //: /line:"code and a" //: /line:"condition" //: /line:"code." //: /end //: OUT g41 (spc) @(701,1067) /sn:0 /w:[ 1 ] //: IN g23 (_Z) @(1164,361) /sn:0 /R:2 /w:[ 0 ] //: OUT g81 (_ldhmdr) @(701,1157) /sn:0 /w:[ 0 ] //: OUT g60 (_wrt) @(701,1057) /sn:0 /w:[ 1 ] //: OUT g54 (_ldpc) @(701,1027) /sn:0 /w:[ 1 ] //: VDD g40 (w24) @(421,1016) /sn:0 /w:[ 1 ] //: joint g70 (_CLR) @(385, 74) /w:[ 7 -1 8 10 ] //: OUT g46 (BOP) @(690,694) /sn:0 /w:[ 1 ] //: OUT g45 (AOP) @(690,684) /sn:0 /w:[ 1 ] _GGREG32 #(10, 10, 20) g35 (.Q(w8), .D(w10), .EN(w20), .CLR(w24), .CK(CK)); //: @(436,1087) /sn:0 /R:1 /w:[ 1 0 0 0 0 ] //: IN g26 (_GT) @(1165,323) /sn:0 /R:2 /w:[ 0 ] assign {w46, w39, _WA, _ldopr, _LDDATA, _LDQ, _CLQ, CIN, BOP, AOP, _ldir, w18, IDATA, w14} = mp_wrd0; //: CONCAT g0 @(483,709) /sn:0 /R:2 /w:[ 1 0 1 0 1 1 1 1 0 0 0 0 5 0 1 ] /dr:0 /tp:0 /drp:0 //: joint g22 (w55) @(879, 300) /w:[ 3 4 6 -1 ] assign {w25, w6} = IR; //: CONCAT g66 @(85,70) /sn:0 /R:2 /w:[ 1 0 1 ] /dr:0 /tp:0 /drp:0 //: OUT g82 (_rdpc) @(701,1167) /sn:0 /w:[ 1 ] _GGMUX8 #(20, 22) g18 (.I0(~w55), .I1(~w4), .I2(w55), .I3(ww), .I4(w32), .I5(_SA), .I6(_SA0), .I7(w28), .S(w44), .Z(w35)); //: @(797,311) /sn:0 /R:3 /w:[ 5 0 7 5 5 1 1 1 0 0 ] /ss:1 /do:0 _GGADD8 #(68, 70, 62, 64) g12 (.A(mp_nxtaddr), .B(w15), .S(w27), .CI(w21), .CO(w22)); //: @(221,657) /sn:0 /R:2 /w:[ 9 0 5 1 0 ] //: joint g33 (w55) @(911, 353) /w:[ -1 9 10 12 ] //: joint g30 (CK) @(102, 511) /w:[ 9 10 20 -1 ] //: OUT g49 (CIN) @(690,704) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin OPRDEC module OPRDEC(SB, SA, FUNC, OPR, OM2, MAP, OM1, COND, IR); //: interface /sz:(192, 126) /bd:[ Ti0>OPR[7:0](148/192) Ti1>IR[7:0](19/192) Bo0DIN[15:0](53/108) Li0>CK(118/138) Li1>SA[3:0](17/138) Li2>SB[3:0](33/138) Li3>_CLR(51/138) Li4>_ENA(66/138) Li5>_ENB(82/138) Li6>_WA(101/138) Bo013 Li0>13 Li1>13 Li2>1 Li3>1 Li4>13 Li5>13 Li6>13 Bo0<13 Bo1<13 ] _GGNDECODER4 #(4, 4) g19 (.I(w15), .E(~_ENB), .Z0(w17), .Z1(w10), .Z2(w25), .Z3(w46)); //: @(222,585) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] /ss:1 /do:1 //: joint g27 (CK) @(512, 403) /w:[ 4 10 3 -1 ] //: IN g32 (_ENA) @(33,453) /sn:0 /w:[ 1 ] //: joint g6 (w50) @(690, 520) /w:[ 6 8 5 -1 ] //: joint g38 (B) @(880, 435) /w:[ 5 6 8 -1 ] //: IN g9 (SA) @(31,525) /sn:0 /w:[ 1 ] //: joint g7 (w49) @(142, 623) /w:[ 2 12 1 -1 ] //: joint g15 (_CLR) @(465, 359) /w:[ 4 10 3 -1 ] //: joint g31 (DIN) @(853, 156) /w:[ 6 -1 5 8 ] //: joint g39 (B) @(1133, 435) /w:[ 1 2 4 -1 ] _GGNDECODER4 #(4, 4) g17 (.I(w37), .E(~_ENA), .Z0(w16), .Z1(w9), .Z2(w26), .Z3(w47)); //: @(222,485) /sn:0 /R:1 /w:[ 0 0 0 0 0 0 ] /ss:1 /do:1 //: joint g25 (_WA) @(769, 379) /w:[ 6 8 5 -1 ] //: joint g29 (DIN) @(360, 156) /w:[ 2 -1 1 12 ] REG4 RF3 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w47), ._ENB(w46), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(1053, 197) /sz:(109, 138) /p:[ Ti0>7 Li0>7 Li1>7 Li2>7 Li3>1 Li4>1 Li5>7 Li6>7 Bo0<3 Bo1<3 ] assign {w15, w49} = SB; //: CONCAT g5 @(79,628) /sn:0 /R:2 /w:[ 1 0 0 ] /dr:0 /tp:0 /drp:0 //: joint g14 (_CLR) @(163, 359) /w:[ 2 12 1 -1 ] //: joint g24 (_WA) @(500, 379) /w:[ 4 10 3 -1 ] //: joint g36 (A) @(1085, 467) /w:[ 1 2 4 -1 ] //: joint g23 (_WA) @(279, 379) /w:[ 2 12 1 -1 ] //: OUT g41 (A) @(1207,467) /sn:0 /w:[ 0 ] REG4 RF1 (.DIN(DIN), .CK(CK), ._WA(_WA), ._ENB(w10), ._ENA(w9), ._CLR(_CLR), .SB(w49), .SA(w50), .B(B), .A(A)); //: @(567, 198) /sz:(106, 138) /p:[ Ti0>11 Li0>11 Li1>11 Li2>1 Li3>1 Li4>11 Li5>11 Li6>11 Bo0<11 Bo1<11 ] //: OUT g40 (B) @(1205,435) /sn:0 /w:[ 0 ] //: IN g22 (CK) @(40,403) /sn:0 /w:[ 0 ] //: joint g26 (CK) @(294, 403) /w:[ 2 12 1 -1 ] //: joint g35 (A) @(832, 467) /w:[ 5 6 8 -1 ] //: IN g12 (_CLR) @(41,359) /sn:0 /w:[ 0 ] //: IN g18 (_WA) @(40,379) /sn:0 /w:[ 0 ] //: joint g30 (DIN) @(619, 156) /w:[ 4 -1 3 10 ] //: IN g33 (_ENB) @(33,555) /sn:0 /w:[ 1 ] REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), .A(A), .B(B)); //: @(801, 198) /sz:(107, 138) /p:[ Ti0>9 Li0>9 Li1>9 Li2>9 Li3>1 Li4>1 Li5>9 Li6>9 Bo0<7 Bo1<7 ] endmodule //: /netlistEnd //: /netlistBegin ALUbasic module ALUbasic(B, A, OUT, COUT, CIN, FUNC); //: interface /sz:(165, 122) /bd:[ Ti0>FUNC[4:0](125/165) Ti1>B[15:0](84/165) Ti2>A[15:0](38/165) Li0>CIN(54/122) Bo0_CLR(89/128) Ti1>CK(34/128) Li0>_DOUT(239/353) Li1>_LDQL(220/353) Li2>_LDQH(200/353) Li3>_LDDATA(182/353) Li4>SA[3:0](18/353) Li5>CIN(165/353) Li6>_LDQ(150/353) Li7>_CLQ(133/353) Li8>IDATA[7:0](113/353) Li9>FUNC[4:0](95/353) Li10>BOP[1:0](81/353) Li11>AOP[1:0](65/353) Li12>_WA(50/353) Li13>SB[3:0](33/353) Lo0<_LT(258/353) Lo1<_GT(276/353) Lo2<_Z(296/353) Lo31 Li0>0 Li1>1 Li2>1 Li3>3 Li4>0 Li5>3 Li6>0 Bo0<1 Bo1<1 ] assign w12 = w1[15:8]; //: TAP g39 @(678,679) /sn:0 /R:3 /w:[ 0 7 8 ] /ss:0 //: joint g48 (w1) @(844, 676) /w:[ 1 2 4 -1 ] _GGREG8 #(10, 10, 20) QL (.Q(QL), .D(w8), .EN(w9), .CLR(w10), .CK(CK)); //: @(620,829) /w:[ 1 0 0 0 7 ] _GGNOR2 #(6) g43 (.I0(!_LDQL), .I1(!_LDQ), .Z(w9)); //: @(706,783) /sn:0 /R:3 /w:[ 0 7 1 ] /eb:0 ALU alu (.B(w31), .A(w38), .CIN(CIN), .FUNC(FUNC), .OUT(w1), .COUT(COUT), ._LT(_LT), ._GT(_GT), ._Z(_Z)); //: @(500, 523) /sz:(107, 127) /sn:0 /p:[ Ti0>1 Ti1>1 Li0>1 Li1>1 Bo0<9 Ro0<1 Ro1<1 Ro2<1 Ro3<1 ] //: OUT g29 (_LT) @(642,575) /sn:0 /w:[ 0 ] //: IN g25 (FUNC) @(475,541) /sn:0 /w:[ 0 ] _GGBUFIF16 #(4, 6) g17 (.Z(DATA), .I(w1), .E(~_DOUT)); //: @(906,676) /sn:0 /cpc:1 /w:[ 13 0 0 ] _GGREG8 #(10, 10, 20) QH (.Q(QH), .D(w2), .EN(w7), .CLR(w10), .CK(CK)); //: @(761,855) /w:[ 1 1 1 3 9 ] //: joint g42 (CK) @(537, 829) /w:[ 6 -1 5 8 ] //: GROUND g14 (w30) @(299,394) /sn:0 /w:[ 0 ] //: joint g5 (w0) @(463, 316) /w:[ 2 1 -1 4 ] //: joint g47 (DATA) @(959, 676) /w:[ 1 2 12 -1 ] //: joint g44 (_LDQ) @(708, 739) /w:[ 2 -1 1 4 ] //: joint g21 (w35) @(486, 418) /w:[ 2 -1 4 1 ] //: IN g24 (_LDQH) @(808,771) /sn:0 /w:[ 1 ] //: joint g36 (w8) @(771, 710) /w:[ -1 2 1 4 ] //: IN g23 (_LDQL) @(677,764) /sn:0 /w:[ 1 ] //: joint g41 (CK) @(195, 409) /w:[ -1 1 2 4 ] //: joint g40 (w10) @(669, 809) /w:[ 2 -1 4 1 ] //: IN g26 (CIN) @(473,618) /sn:0 /w:[ 0 ] _GGMUX2x8 #(8, 8) g35 (.I0(w12), .I1(w8), .S(_LDQ), .Z(w2)); //: @(761,739) /sn:0 /w:[ 1 5 3 0 ] /ss:0 /do:0 _GGNOR2 #(6) g45 (.I0(!_LDQH), .I1(!_LDQ), .Z(w7)); //: @(840,809) /sn:0 /R:3 /w:[ 0 9 0 ] /eb:0 //: joint g46 (_LDQ) @(708, 757) /w:[ 6 5 8 -1 ] //: joint g0 (DATA) @(864, 437) /w:[ 3 4 6 -1 ] //: joint g22 (DATA) @(608, 437) /w:[ 7 -1 8 10 ] _GGMUX4x16 #(12, 12) g18 (.I0(w21), .I1(DATA), .I2(w35), .I3(w28), .S(BOP), .Z(w31)); //: @(614,481) /sn:0 /w:[ 3 11 3 0 1 0 ] /ss:0 /do:0 //: IN g12 (IDATA) @(296,423) /sn:0 /w:[ 1 ] //: OUT g30 (COUT) @(642,592) /sn:0 /w:[ 0 ] //: IN g49 (_DOUT) @(908,642) /sn:0 /R:3 /w:[ 1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNAND3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; reg Z; assign #Diz Z = ~( I0 & I1 & I2 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGAND2x2 #(.Diz(1)) (I0, I1, Z); output [1:0] Z; input [1:0] I0, I1; reg [1:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX2x5 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [4:0] I0, I1; input S; output [4:0] Z; reg [4:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 5'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX2x4 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [3:0] I0, I1; input S; output [3:0] Z; reg [3:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 4'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGARSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >>> S); endmodule // arshift //: /builtinEnd //: /builtinBegin module _GGNOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ~( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGXOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGMUX2x3 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [2:0] I0, I1; input S; output [2:0] Z; reg [2:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 3'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] Z; reg [7:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; reg [15:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGREG4 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [3:0] D; output [3:0] Q; reg [3:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 4'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x3 #(.Diz(1)) (I0, I1, Z); output [2:0] Z; input [2:0] I0, I1; reg [2:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGBUF3 #(.Diz(1)) (I, Z); input [2:0] I; output [2:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGROM8x32 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [31:0] D; reg [31:0] m[0:255]; wire [31:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 32'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGNOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = ~ | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGLSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I << S); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGROM8x8 #(.Dout(1), .Dread(1)) (A, D, OE); input OE; input [7:0] A; output [7:0] D; reg [7:0] m[0:255]; wire [7:0] X; assign #Dread X = m[A]; assign #Dout D = (~OE) ? X : 8'bz; endmodule //: /builtinEnd //: /builtinBegin module _GGMUX8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output Z; reg Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 1'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGOR3 #(.Diz(1)) (I0, I1, I2, Z); output Z; input I0, I1, I2; assign #Diz Z = ( I0 | I1 | I2 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGAND1x4 #(.Diz(1)) (I0, Z); output Z; input [3:0] I0; assign #Diz Z = & I0; endmodule // rand //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGNBUF #(.Diz(1)) (I, Z); input I; output Z; assign #Diz Z = ~I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR1x3 #(.Diz(1)) (I0, Z); output Z; input [2:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGBUFIF16 #(.Dez(1), .Diz(1)) (Z, I, E); input [15:0] I; input E; output [15:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 16'bz; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGREG32 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [31:0] D; output [31:0] Q; reg [31:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 32'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD16 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [15:0] A,B; output [15:0] S; wire [15:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGAND2x8 #(.Diz(1)) (I0, I1, Z); output [7:0] Z; input [7:0] I0, I1; reg [7:0] Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [7:0] I0, I1; input S; output [7:0] Z; reg [7:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 8'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGRAM16x8 #(.Dout(1), // Output time .Dread(1), // Read time .Dwrite(1), // Write time .Daddr_setup(1), // Address setup time .Daddr_hold(1), // Address hold time .Ddata_hold(1)) // Data hold time (A, D, WE, OE, CS); input OE, WE, CS; input [15:0] A; inout [7:0] D; reg [7:0] m[0:65535]; wire [7:0] X; wire doRead, doWrite; specify $setup(A, posedge doWrite, Daddr_setup); $hold(negedge doWrite, A, Daddr_hold); $hold(negedge doWrite, D, Ddata_hold); $width(posedge doWrite, Dwrite); endspecify assign doRead = (!CS && !OE); assign doWrite = (!CS && !WE); // // Value read from addressed memory // assign #Dread X = m[A]; // // If chip-select and output-enable are asserted, output value from memory // assign #Dout D = doRead ? X : 8'bz; // // Look for conditions on which to write to memory // always @(doWrite or D or A) if (doWrite) m[A] <= #Dwrite D; always @(D) if (doWrite) $error("`RAMDCHG %m[%M]"); always @(A) if (doWrite) $error("`RAMACHG %m[%M]"); endmodule // ram //: /builtinEnd //: /builtinBegin module _GGREG16 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [15:0] D; output [15:0] Q; reg [15:0] Qreg; specify $setup(D,posedge CK &&& (!EN && CLR), Dsetup); $hold(posedge CK &&& (!EN && CLR),D, Dhold); endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 16'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGROLL16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = ((I << (S % 16)) | (I >> ((16 - S) % 16))); endmodule // lshift //: /builtinEnd //: /builtinBegin module _GGOR1x16 #(.Diz(1)) (I0, Z); output Z; input [15:0] I0; assign #Diz Z = | I0; endmodule // ror //: /builtinEnd //: /builtinBegin module _GGMUX2x16 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z); input [15:0] I0, I1; input S; output [15:0] Z; reg [15:0] Z; always begin case (S) 1'd0: Z <= #Dsz I0; 1'd1: Z <= #Dsz I1; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGCLOCK_P3000_0_50 (Z); output Z; reg Z = 1'b0; initial #1500 if (0 == 0) forever begin Z = 1'b1; #1500; Z = 1'b0; #1500; end else forever begin Z = 1'b0; #1500; Z = 1'b1; #1500; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGNDECODER4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3); input [1:0] I; input E; output Z0, Z1, Z2, Z3; wire [3:0] Zcat; specify (E *> Z0) = Dez; (E *> Z1) = Dez; (E *> Z2) = Dez; (E *> Z3) = Dez; (I *> Z0) = Diz; (I *> Z1) = Diz; (I *> Z2) = Diz; (I *> Z3) = Diz; endspecify assign Zcat = ~ ({4{E}} & (4'b1 << I)); assign Z0 = Zcat[0]; assign Z1 = Zcat[1]; assign Z2 = Zcat[2]; assign Z3 = Zcat[3]; endmodule // decoder //: /builtinEnd //: /builtinBegin module _GGRSHIFT16 #(.Dsz(1), .Diz(1)) (I, Z , S); input [15:0] I; input [3:0] S; output [15:0] Z; specify (I *> Z) = Diz; (S *> Z) = Dsz; endspecify assign Z = (I >> S); endmodule // rshift //: /builtinEnd //: /builtinBegin module _GGDIV16 #(.Dab_q(1), .Dab_r(1)) (A, B, Q, R); input [15:0] A,B; output [15:0] Q,R; assign #Dab_q Q = (A / B); assign #Dab_r R = (A % B); endmodule // div //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd //: /builtinBegin module _GGMUL16 #(.Dab_p(1)) (A, B, P); input [15:0] A,B; output [15:0] P; assign #Dab_p P = (A * B); endmodule //: /builtinEnd //: /builtinBegin module _GGBUF5 #(.Diz(1)) (I, Z); input [4:0] I; output [4:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGMUX8x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, I4, I5, I6, I7, S, Z); input [15:0] I0, I1, I2, I3, I4, I5, I6, I7; input [2:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 3'd0: Z <= #Dsz I0; 3'd1: Z <= #Dsz I1; 3'd2: Z <= #Dsz I2; 3'd3: Z <= #Dsz I3; 3'd4: Z <= #Dsz I4; 3'd5: Z <= #Dsz I5; 3'd6: Z <= #Dsz I6; 3'd7: Z <= #Dsz I7; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGBUF16 #(.Diz(1)) (I, Z); input [15:0] I; output [15:0] Z; assign #Diz Z = I; endmodule // buf //: /builtinEnd //: /builtinBegin module _GGOR2x16 #(.Diz(1)) (I0, I1, Z); output [15:0] Z; input [15:0] I0, I1; assign #Diz Z = ( I0 | I1 ); endmodule // or //: /builtinEnd //: /builtinBegin module _GGMUX4x16 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z); input [15:0] I0, I1, I2, I3; input [1:0] S; output [15:0] Z; reg [15:0] Z; always begin case (S) 2'd0: Z <= #Dsz I0; 2'd1: Z <= #Dsz I1; 2'd2: Z <= #Dsz I2; 2'd3: Z <= #Dsz I3; default: Z <= #Dsz 16'hx; endcase // case(S) @(S or I0 or I1 or I2 or I3); end endmodule // mux //: /builtinEnd //: /builtinBegin module _GGBUFIF8 #(.Dez(1), .Diz(1)) (Z, I, E); input [7:0] I; input E; output [7:0] Z; specify (E *> Z) = Dez; (I *> Z) = Diz; endspecify assign Z = E ? (I) : 8'bz; endmodule // buf //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex1/combinational.v000644 001751 001751 00000013345 11135014460 023171 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "combinational.v" //: property discardChanges = 1 //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg A0; //: {0}(173,94)(163,94){1} //: {2}(67:159,94)(95,94){3} //: {4}(161,96)(161,154)(173,154){5} reg w0; //: /sn:0 {0}(239,92)(219,92){1} //: {2}(217,90)(217,50){3} //: {4}(217,94)(217,117){5} reg A2; //: {0}(165,415)(155,415){1} //: {2}(60:151,415)(96,415){3} //: {4}(153,417)(153,475)(165,475){5} reg B2; //: {0}(30:100,480)(142,480){1} //: {2}(146,480)(165,480){3} //: {4}(144,478)(144,420)(165,420){5} reg B1; //: {0}(50:98,317)(142,317){1} //: {2}(146,317)(169,317){3} //: {4}(144,315)(144,257)(169,257){5} reg A1; //: {0}(169,252)(159,252){1} //: {2}(61:155,252)(96,252){3} //: {4}(157,254)(157,312)(169,312){5} reg B0; //: {0}(50:93,159)(144,159){1} //: {2}(148,159)(173,159){3} //: {4}(146,157)(146,99)(173,99){5} wire w6; //: /sn:0 {0}(215,171)(215,138){1} wire S1; //: {0}(50:303,253)(257,253){1} wire w14; //: /sn:0 {0}(211,329)(211,296){1} wire w19; //: /sn:0 {0}(231,413)(211,413){1} //: {2}(209,411)(209,350){3} //: {4}(209,415)(209,438){5} wire w4; //: /sn:0 {0}(239,97)(214,97){1} //: {2}(210,97)(194,97){3} //: {4}(212,99)(212,117){5} wire w3; //: /sn:0 {0}(210,171)(210,157)(194,157){1} wire C3; //: {0}(23:303,533)(205,533)(205,513){1} wire w21; //: /sn:0 {0}(202,492)(202,478)(186,478){1} wire S0; //: {0}(50:303,95)(260,95){1} wire w18; //: /sn:0 {0}(231,418)(206,418){1} //: {2}(202,418)(186,418){3} //: {4}(204,420)(204,438){5} wire w22; //: /sn:0 {0}(207,492)(207,459){1} wire w11; //: /sn:0 {0}(236,250)(215,250){1} //: {2}(213,248)(213,192){3} //: {4}(213,252)(213,275){5} wire w10; //: /sn:0 {0}(236,255)(210,255){1} //: {2}(206,255)(190,255){3} //: {4}(208,257)(208,275){5} wire w13; //: /sn:0 {0}(206,329)(206,315)(190,315){1} wire S2; //: {0}(50:303,416)(252,416){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w4), .I1(w0), .Z(w6)); //: @(215,128) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: SWITCH g4 (B0) @(76,159) /sn:0 /w:[ 0 ] /st:1 //: LED g37 (S2) @(310,416) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g34 @(351,22) //: /line:"This circuit is a simple three-bit adder." //: /line:"" //: /line:"Start the simualtor by pressing the \"play\"" //: /line:"button from the button bar. Then, set probes" //: /line:"by double clicking on the S0, S1, S2 and C3" //: /line:"wires (and any additional wires you wish to" //: /line:"probe). Press the \"play\" button again to" //: /line:"enter continuous simulation mode. In this" //: /line:"mode, whenever you change a switch value" //: /line:"(by clicking on it), the simulator will" //: /line:"simulate until all values have stabalized." //: /line:"End the simulation by pressing the \"stop\"" //: /line:"button on the button bar." //: /end _GGXOR2 #(8) g13 (.I0(A1), .I1(B1), .Z(w10)); //: @(180,255) /sn:0 /w:[ 0 5 3 ] /eb:0 //: SWITCH g3 (w0) @(217,37) /sn:0 /R:3 /w:[ 3 ] /st:0 _GGXOR2 #(8) g2 (.I0(w0), .I1(w4), .Z(S0)); //: @(250,95) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGXOR2 #(8) g1 (.I0(A0), .I1(B0), .Z(w4)); //: @(184,97) /sn:0 /w:[ 0 5 3 ] /eb:0 _GGNAND2 #(4) g16 (.I0(A1), .I1(B1), .Z(w13)); //: @(180,315) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g11 (.I0(w3), .I1(w6), .Z(w11)); //: @(213,182) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: joint g28 (A2) @(153, 415) /w:[ 1 -1 2 4 ] //: joint g10 (w4) @(212, 97) /w:[ 1 -1 2 4 ] //: joint g32 (w18) @(204, 418) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g27 (.I0(A2), .I1(B2), .Z(w21)); //: @(176,478) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g19 (.I0(w10), .I1(w11), .Z(w14)); //: @(211,286) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g38 (C3) @(310,533) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g6 (A0) @(161, 94) /w:[ 1 -1 2 4 ] //: joint g9 (w0) @(217, 92) /w:[ 1 2 -1 4 ] //: joint g7 (B0) @(146, 159) /w:[ 2 4 1 -1 ] //: joint g31 (w19) @(209, 413) /w:[ 1 2 -1 4 ] //: joint g20 (w11) @(213, 250) /w:[ 1 2 -1 4 ] //: SWITCH g15 (B1) @(81,317) /sn:0 /w:[ 0 ] /st:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: joint g29 (B2) @(144, 480) /w:[ 2 4 1 -1 ] _GGXOR2 #(8) g25 (.I0(w19), .I1(w18), .Z(S2)); //: @(242,416) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g17 (A1) @(157, 252) /w:[ 1 -1 2 4 ] _GGXOR2 #(8) g14 (.I0(w11), .I1(w10), .Z(S1)); //: @(247,253) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g5 (.I0(A0), .I1(B0), .Z(w3)); //: @(184,157) /sn:0 /w:[ 5 3 1 ] /eb:0 //: LED g36 (S1) @(310,253) /sn:0 /R:3 /w:[ 0 ] /type:0 _GGXOR2 #(8) g24 (.I0(A2), .I1(B2), .Z(w18)); //: @(176,418) /sn:0 /w:[ 0 5 3 ] /eb:0 //: joint g21 (w10) @(208, 255) /w:[ 1 -1 2 4 ] //: SWITCH g23 (A2) @(79,415) /sn:0 /w:[ 3 ] /st:0 //: LED g35 (S0) @(310,95) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g26 (B2) @(83,480) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g22 (.I0(w13), .I1(w14), .Z(w19)); //: @(209,340) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: SWITCH g0 (A0) @(78,94) /sn:0 /w:[ 3 ] /st:0 //: joint g18 (B1) @(144, 317) /w:[ 2 4 1 -1 ] //: SWITCH g12 (A1) @(79,252) /sn:0 /w:[ 3 ] /st:1 _GGNAND2 #(4) g33 (.I0(w21), .I1(w22), .Z(C3)); //: @(205,503) /sn:0 /R:3 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g30 (.I0(w18), .I1(w19), .Z(w22)); //: @(207,449) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex1/combinational.v~000644 001751 001751 00000013345 11135014460 023367 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "combinational.v" //: property discardChanges = 1 //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg A0; //: {0}(173,94)(163,94){1} //: {2}(67:159,94)(95,94){3} //: {4}(161,96)(161,154)(173,154){5} reg w0; //: /sn:0 {0}(239,92)(219,92){1} //: {2}(217,90)(217,50){3} //: {4}(217,94)(217,117){5} reg A2; //: {0}(165,415)(155,415){1} //: {2}(60:151,415)(96,415){3} //: {4}(153,417)(153,475)(165,475){5} reg B2; //: {0}(30:100,480)(142,480){1} //: {2}(146,480)(165,480){3} //: {4}(144,478)(144,420)(165,420){5} reg B1; //: {0}(50:98,317)(142,317){1} //: {2}(146,317)(169,317){3} //: {4}(144,315)(144,257)(169,257){5} reg A1; //: {0}(169,252)(159,252){1} //: {2}(61:155,252)(96,252){3} //: {4}(157,254)(157,312)(169,312){5} reg B0; //: {0}(50:93,159)(144,159){1} //: {2}(148,159)(173,159){3} //: {4}(146,157)(146,99)(173,99){5} wire w6; //: /sn:0 {0}(215,171)(215,138){1} wire S1; //: {0}(50:303,253)(257,253){1} wire w14; //: /sn:0 {0}(211,329)(211,296){1} wire w19; //: /sn:0 {0}(231,413)(211,413){1} //: {2}(209,411)(209,350){3} //: {4}(209,415)(209,438){5} wire w4; //: /sn:0 {0}(239,97)(214,97){1} //: {2}(210,97)(194,97){3} //: {4}(212,99)(212,117){5} wire w3; //: /sn:0 {0}(210,171)(210,157)(194,157){1} wire C3; //: {0}(23:303,533)(205,533)(205,513){1} wire w21; //: /sn:0 {0}(202,492)(202,478)(186,478){1} wire S0; //: {0}(50:303,95)(260,95){1} wire w18; //: /sn:0 {0}(231,418)(206,418){1} //: {2}(202,418)(186,418){3} //: {4}(204,420)(204,438){5} wire w22; //: /sn:0 {0}(207,492)(207,459){1} wire w11; //: /sn:0 {0}(236,250)(215,250){1} //: {2}(213,248)(213,192){3} //: {4}(213,252)(213,275){5} wire w10; //: /sn:0 {0}(236,255)(210,255){1} //: {2}(206,255)(190,255){3} //: {4}(208,257)(208,275){5} wire w13; //: /sn:0 {0}(206,329)(206,315)(190,315){1} wire S2; //: {0}(50:303,416)(252,416){1} //: enddecls _GGNAND2 #(4) g8 (.I0(w4), .I1(w0), .Z(w6)); //: @(215,128) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: SWITCH g4 (B0) @(76,159) /sn:0 /w:[ 0 ] /st:1 //: LED g37 (S2) @(310,416) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g34 @(351,22) //: /line:"This circuit is a simple three-bit adder." //: /line:"" //: /line:"Start the simualtor by pressing the \"play\"" //: /line:"button from the button bar. Then, set probes" //: /line:"by double clicking on the S0, S1, S2 and C3" //: /line:"wires (and any additional wires you wish to" //: /line:"probe). Press the \"play\" button again to" //: /line:"enter continuous simulation mode. In this" //: /line:"mode, whenever you change a switch value" //: /line:"(by clicking on it), the simulator will" //: /line:"simulate until all values have stabalized." //: /line:"End the simulation by pressing the \"stop\"" //: /line:"button on the button bar." //: /end _GGXOR2 #(8) g13 (.I0(A1), .I1(B1), .Z(w10)); //: @(180,255) /sn:0 /w:[ 0 5 3 ] /eb:0 //: SWITCH g3 (w0) @(217,37) /sn:0 /R:3 /w:[ 3 ] /st:0 _GGXOR2 #(8) g2 (.I0(w0), .I1(w4), .Z(S0)); //: @(250,95) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGXOR2 #(8) g1 (.I0(A0), .I1(B0), .Z(w4)); //: @(184,97) /sn:0 /w:[ 0 5 3 ] /eb:0 _GGNAND2 #(4) g16 (.I0(A1), .I1(B1), .Z(w13)); //: @(180,315) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g11 (.I0(w3), .I1(w6), .Z(w11)); //: @(213,182) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: joint g28 (A2) @(153, 415) /w:[ 1 -1 2 4 ] //: joint g10 (w4) @(212, 97) /w:[ 1 -1 2 4 ] //: joint g32 (w18) @(204, 418) /w:[ 1 -1 2 4 ] _GGNAND2 #(4) g27 (.I0(A2), .I1(B2), .Z(w21)); //: @(176,478) /sn:0 /w:[ 5 3 1 ] /eb:0 _GGNAND2 #(4) g19 (.I0(w10), .I1(w11), .Z(w14)); //: @(211,286) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 //: LED g38 (C3) @(310,533) /sn:0 /R:3 /w:[ 0 ] /type:0 //: joint g6 (A0) @(161, 94) /w:[ 1 -1 2 4 ] //: joint g9 (w0) @(217, 92) /w:[ 1 2 -1 4 ] //: joint g7 (B0) @(146, 159) /w:[ 2 4 1 -1 ] //: joint g31 (w19) @(209, 413) /w:[ 1 2 -1 4 ] //: joint g20 (w11) @(213, 250) /w:[ 1 2 -1 4 ] //: SWITCH g15 (B1) @(81,317) /sn:0 /w:[ 0 ] /st:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: joint g29 (B2) @(144, 480) /w:[ 2 4 1 -1 ] _GGXOR2 #(8) g25 (.I0(w19), .I1(w18), .Z(S2)); //: @(242,416) /sn:0 /w:[ 0 0 1 ] /eb:0 //: joint g17 (A1) @(157, 252) /w:[ 1 -1 2 4 ] _GGXOR2 #(8) g14 (.I0(w11), .I1(w10), .Z(S1)); //: @(247,253) /sn:0 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g5 (.I0(A0), .I1(B0), .Z(w3)); //: @(184,157) /sn:0 /w:[ 5 3 1 ] /eb:0 //: LED g36 (S1) @(310,253) /sn:0 /R:3 /w:[ 0 ] /type:0 _GGXOR2 #(8) g24 (.I0(A2), .I1(B2), .Z(w18)); //: @(176,418) /sn:0 /w:[ 0 5 3 ] /eb:0 //: joint g21 (w10) @(208, 255) /w:[ 1 -1 2 4 ] //: SWITCH g23 (A2) @(79,415) /sn:0 /w:[ 3 ] /st:0 //: LED g35 (S0) @(310,95) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g26 (B2) @(83,480) /sn:0 /w:[ 0 ] /st:0 _GGNAND2 #(4) g22 (.I0(w13), .I1(w14), .Z(w19)); //: @(209,340) /sn:0 /R:3 /w:[ 0 0 3 ] /eb:0 //: SWITCH g0 (A0) @(78,94) /sn:0 /w:[ 3 ] /st:0 //: joint g18 (B1) @(144, 317) /w:[ 2 4 1 -1 ] //: SWITCH g12 (A1) @(79,252) /sn:0 /w:[ 3 ] /st:1 _GGNAND2 #(4) g33 (.I0(w21), .I1(w22), .Z(C3)); //: @(205,503) /sn:0 /R:3 /w:[ 0 0 1 ] /eb:0 _GGNAND2 #(4) g30 (.I0(w18), .I1(w19), .Z(w22)); //: @(207,449) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGNAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ~( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex4/trff.v000644 001751 001751 00000013563 11135014121 021312 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "trff.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module supply0 w14; //: /sn:0 {0}(654,415)(654,436)(603,436){1} //: {2}(599,436)(566,436)(566,415){3} //: {4}(601,438)(601,455){5} reg R; //: {0}(606,353)(535,353){1} //: {2}(531,353)(503,353){3} //: {4}(501,351)(501,336){5} //: {6}(59:499,353)(442,353){7} //: {8}(533,355)(533,406)(552,406){9} supply1 w17; //: /sn:0 {0}(620,315)(620,292){1} supply1 w12; //: /sn:0 {0}(625,86)(625,63){1} supply0 w13; //: /sn:0 {0}(650,191)(650,213)(608,213){1} //: {2}(604,213)(571,213)(571,191){3} //: {4}(606,215)(606,231){5} reg S; //: {0}(611,94)(591,94){1} //: {2}(587,94)(505,94){3} //: {4}(503,92)(503,81){5} //: {6}(56:501,94)(436,94){7} //: {8}(589,96)(589,182)(636,182){9} wire w6; //: /sn:0 {0}(625,119)(625,103){1} wire w16; //: /sn:0 {0}(620,345)(620,332){1} wire Q; //: {0}(50:765,383)(656,383){1} //: {2}(654,381)(654,273)(532,273)(532,184){3} //: {4}(534,182)(557,182){5} //: {6}(532,180)(532,127)(611,127){7} //: {8}(652,383)(622,383){9} //: {10}(620,381)(620,362){11} //: {12}(618,383)(566,383)(566,398){13} //: {14}(654,385)(654,398){15} wire _Q; //: {0}(50:759,159)(694,159){1} //: {2}(690,159)(652,159){3} //: {4}(648,159)(627,159){5} //: {6}(625,157)(625,136){7} //: {8}(623,159)(571,159)(571,174){9} //: {10}(650,161)(650,174){11} //: {12}(692,161)(692,252)(584,252)(584,321){13} //: {14}(586,323)(606,323){15} //: {16}(584,325)(584,406)(640,406){17} //: enddecls //: joint g8 (w13) @(606, 213) /anc:1 /w:[ 1 -1 2 4 ] //: VDD g4 (w12) @(636,63) /sn:0 /anc:1 /w:[ 1 ] _GGNMOS #(2, 1) g13 (.Z(Q), .S(w14), .G(_Q)); //: @(648,406) /sn:0 /anc:1 /w:[ 15 0 17 ] _GGPMOS #(2, 1) g3 (.Z(w6), .S(w12), .G(S)); //: @(619,94) /sn:0 /anc:1 /w:[ 1 0 0 ] //: joint g34 (S) @(503, 94) /w:[ 3 4 6 -1 ] _GGPMOS #(2, 1) g2 (.Z(_Q), .S(w6), .G(Q)); //: @(619,127) /sn:0 /anc:1 /w:[ 7 0 7 ] _GGNMOS #(2, 1) g1 (.Z(_Q), .S(w13), .G(S)); //: @(644,182) /sn:0 /anc:1 /w:[ 11 0 9 ] //: VDD g16 (w17) @(631,292) /sn:0 /anc:1 /w:[ 1 ] //: joint g11 (S) @(589, 94) /anc:1 /w:[ 1 -1 2 8 ] //: joint g10 (Q) @(654, 383) /anc:1 /w:[ 1 2 8 14 ] //: comment g28 @(26,299) /anc:1 //: /line:"3) Return the \"S\" switch to the off position" //: /line:"and press the space bar 10 to 20 times. The" //: /line:"\"Q\" and \"_Q\" signals will remain constant." //: /end //: comment g27 @(25,193) /anc:1 //: /line:"2) Press the space bar 10 to 20 times to" //: /line:"advance the simulator. Note that both the" //: /line:"\"Q\" and \"_Q\" signals are in the unknown state." //: /line:"Now turn on the \"S\" switch (by clicking on it)" //: /line:"and press the space bar another 10 to 20" //: /line:"times. The \"Q\" signal will go high and the" //: /line:"\"_Q\" signal will go low." //: /line:"" //: /end //: SWITCH g19 (R) @(425,353) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: LED g32 (Q) @(772,383) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g6 (S) @(419,94) /sn:0 /anc:1 /w:[ 7 ] /st:1 //: joint g7 (Q) @(620, 383) /anc:1 /w:[ 9 10 12 -1 ] //: joint g9 (_Q) @(692, 159) /anc:1 /w:[ 1 -1 2 12 ] //: joint g20 (w14) @(601, 436) /anc:1 /w:[ 1 -1 2 4 ] _GGPMOS #(2, 1) g15 (.Z(w16), .S(w17), .G(_Q)); //: @(614,323) /sn:0 /anc:1 /w:[ 1 0 15 ] //: LED g31 (_Q) @(766,159) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: comment g25 @(26,42) //: /line:"This circuit is a simple flip-flop composed" //: /line:"of two CMOS NOR gates implemented at the" //: /line:"transistor level." //: /end //: GROUND g17 (w14) @(601,461) /sn:0 /anc:1 /w:[ 5 ] //: comment g29 @(26,355) /anc:1 //: /line:"4) Now turn the \"R\" switch off by clicking" //: /line:"on it and press the space bar 10 to 20 times." //: /line:"The \"_Q\" signal will go high and the \"Q\"" //: /line:"signal will go low." //: /end _GGPMOS #(2, 1) g14 (.Z(Q), .S(w16), .G(R)); //: @(614,353) /sn:0 /anc:1 /w:[ 11 0 0 ] //: GROUND g5 (w13) @(606,237) /sn:0 /anc:1 /w:[ 5 ] //: joint g21 (Q) @(532, 182) /anc:1 /w:[ 4 6 -1 3 ] //: joint g24 (_Q) @(625, 159) /anc:1 /w:[ 5 6 8 -1 ] //: joint g36 (R) @(501, 353) /w:[ 3 4 6 -1 ] //: joint g23 (_Q) @(650, 159) /anc:1 /w:[ 3 -1 4 10 ] //: comment g26 @(26,101) /anc:1 //: /line:"1) Begin the simulation by clicking on the" //: /line:"\"Play\" button or by selecting \"Begin" //: /line:"Simulation\" from the \"Simulate\" menu." //: /line:"Set Probes on the \"S\", \"R\", \"Q\" and \"_Q\"" //: /line:"signals by double-clicking them. The \"_Q\"" //: /line:"signal is the \"Q\" with an overline." //: /end //: joint g22 (R) @(533, 353) /anc:1 /w:[ 1 -1 2 8 ] _GGNMOS #(2, 1) g0 (.Z(_Q), .S(w13), .G(Q)); //: @(565,182) /sn:0 /anc:1 /w:[ 9 3 5 ] //: LED g35 (R) @(501,329) /sn:0 /w:[ 5 ] /type:0 //: joint g18 (_Q) @(584, 323) /anc:1 /w:[ 14 13 -1 16 ] _GGNMOS #(2, 1) g12 (.Z(Q), .S(w14), .G(R)); //: @(560,406) /sn:0 /anc:1 /w:[ 13 3 9 ] //: comment g30 @(23,420) /anc:1 //: /line:"5) Return the \"R\" switch to the off position" //: /line:"and press the space bar 10 to 20 times. The" //: /line:"\"Q\" and \"_Q\" signals will remain constant." //: /end //: LED g33 (S) @(503,74) /sn:0 /w:[ 5 ] /type:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex4/trff.v~000644 001751 001751 00000013630 11135014121 021503 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "trff.v" //: property discardChanges = 1 //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module supply0 w14; //: /sn:0 {0}(654,415)(654,436)(603,436){1} //: {2}(599,436)(566,436)(566,415){3} //: {4}(601,438)(601,455){5} reg R; //: {0}(606,353)(535,353){1} //: {2}(531,353)(503,353){3} //: {4}(501,351)(501,336){5} //: {6}(59:499,353)(442,353){7} //: {8}(533,355)(533,406)(552,406){9} supply1 w17; //: /sn:0 {0}(620,315)(620,292){1} supply1 w12; //: /sn:0 {0}(625,86)(625,63){1} supply0 w13; //: /sn:0 {0}(650,191)(650,213)(608,213){1} //: {2}(604,213)(571,213)(571,191){3} //: {4}(606,215)(606,231){5} reg S; //: {0}(611,94)(591,94){1} //: {2}(587,94)(505,94){3} //: {4}(503,92)(503,81){5} //: {6}(56:501,94)(436,94){7} //: {8}(589,96)(589,182)(636,182){9} wire w6; //: /sn:0 {0}(625,119)(625,103){1} wire w16; //: /sn:0 {0}(620,345)(620,332){1} wire Q; //: {0}(50:765,383)(656,383){1} //: {2}(654,381)(654,273)(532,273)(532,184){3} //: {4}(534,182)(557,182){5} //: {6}(532,180)(532,127)(611,127){7} //: {8}(652,383)(622,383){9} //: {10}(620,381)(620,362){11} //: {12}(618,383)(566,383)(566,398){13} //: {14}(654,385)(654,398){15} wire _Q; //: {0}(50:759,159)(694,159){1} //: {2}(690,159)(652,159){3} //: {4}(648,159)(627,159){5} //: {6}(625,157)(625,136){7} //: {8}(623,159)(571,159)(571,174){9} //: {10}(650,161)(650,174){11} //: {12}(692,161)(692,252)(584,252)(584,321){13} //: {14}(586,323)(606,323){15} //: {16}(584,325)(584,406)(640,406){17} //: enddecls //: joint g8 (w13) @(606, 213) /anc:1 /w:[ 1 -1 2 4 ] //: VDD g4 (w12) @(636,63) /sn:0 /anc:1 /w:[ 1 ] _GGNMOS #(2, 1) g13 (.Z(Q), .S(w14), .G(_Q)); //: @(648,406) /sn:0 /anc:1 /w:[ 15 0 17 ] _GGPMOS #(2, 1) g3 (.Z(w6), .S(w12), .G(S)); //: @(619,94) /sn:0 /anc:1 /w:[ 1 0 0 ] //: joint g34 (S) @(503, 94) /w:[ 3 4 6 -1 ] _GGPMOS #(2, 1) g2 (.Z(_Q), .S(w6), .G(Q)); //: @(619,127) /sn:0 /anc:1 /w:[ 7 0 7 ] _GGNMOS #(2, 1) g1 (.Z(_Q), .S(w13), .G(S)); //: @(644,182) /sn:0 /anc:1 /w:[ 11 0 9 ] //: VDD g16 (w17) @(631,292) /sn:0 /anc:1 /w:[ 1 ] //: joint g11 (S) @(589, 94) /anc:1 /w:[ 1 -1 2 8 ] //: joint g10 (Q) @(654, 383) /anc:1 /w:[ 1 2 8 14 ] //: comment g28 @(26,299) /anc:1 //: /line:"3) Return the \"S\" switch to the off position" //: /line:"and press the space bar 10 to 20 times. The" //: /line:"\"Q\" and \"_Q\" signals will remain constant." //: /end //: comment g27 @(25,193) /anc:1 //: /line:"2) Press the space bar 10 to 20 times to" //: /line:"advance the simulator. Note that both the" //: /line:"\"Q\" and \"_Q\" signals are in the unknown state." //: /line:"Now turn on the \"S\" switch (by clicking on it)" //: /line:"and press the space bar another 10 to 20" //: /line:"times. The \"Q\" signal will go high and the" //: /line:"\"_Q\" signal will go low." //: /line:"" //: /end //: SWITCH g19 (R) @(425,353) /sn:0 /anc:1 /w:[ 7 ] /st:0 //: LED g32 (Q) @(772,383) /sn:0 /R:3 /w:[ 0 ] /type:0 //: SWITCH g6 (S) @(419,94) /sn:0 /anc:1 /w:[ 7 ] /st:1 //: joint g7 (Q) @(620, 383) /anc:1 /w:[ 9 10 12 -1 ] //: joint g9 (_Q) @(692, 159) /anc:1 /w:[ 1 -1 2 12 ] //: joint g20 (w14) @(601, 436) /anc:1 /w:[ 1 -1 2 4 ] _GGPMOS #(2, 1) g15 (.Z(w16), .S(w17), .G(_Q)); //: @(614,323) /sn:0 /anc:1 /w:[ 1 0 15 ] //: LED g31 (_Q) @(766,159) /sn:0 /R:3 /w:[ 0 ] /type:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: comment g25 @(26,42) //: /line:"This circuit is a simple flip-flop composed" //: /line:"of two CMOS NOR gates implemented at the" //: /line:"transistor level." //: /end //: GROUND g17 (w14) @(601,461) /sn:0 /anc:1 /w:[ 5 ] //: comment g29 @(26,355) /anc:1 //: /line:"4) Now turn the \"R\" switch off by clicking" //: /line:"on it and press the space bar 10 to 20 times." //: /line:"The \"_Q\" signal will go high and the \"Q\"" //: /line:"signal will go low." //: /end _GGPMOS #(2, 1) g14 (.Z(Q), .S(w16), .G(R)); //: @(614,353) /sn:0 /anc:1 /w:[ 11 0 0 ] //: GROUND g5 (w13) @(606,237) /sn:0 /anc:1 /w:[ 5 ] //: joint g21 (Q) @(532, 182) /anc:1 /w:[ 4 6 -1 3 ] //: joint g24 (_Q) @(625, 159) /anc:1 /w:[ 5 6 8 -1 ] //: joint g36 (R) @(501, 353) /w:[ 3 4 6 -1 ] //: joint g23 (_Q) @(650, 159) /anc:1 /w:[ 3 -1 4 10 ] //: comment g26 @(26,101) /anc:1 //: /line:"1) Begin the simulation by clicking on the" //: /line:"\"Play\" button or by selecting \"Begin" //: /line:"Simulation\" from the \"Simulate\" menu." //: /line:"Set Probes on the \"S\", \"R\", \"Q\" and \"_Q\"" //: /line:"signals by double-clicking them. The \"_Q\"" //: /line:"signal is the \"Q\" with an overline." //: /end //: joint g22 (R) @(533, 353) /anc:1 /w:[ 1 -1 2 8 ] _GGNMOS #(2, 1) g0 (.Z(_Q), .S(w13), .G(Q)); //: @(565,182) /sn:0 /anc:1 /w:[ 9 3 5 ] //: LED g35 (R) @(501,329) /sn:0 /w:[ 5 ] /type:0 //: joint g18 (_Q) @(584, 323) /anc:1 /w:[ 14 13 -1 16 ] _GGNMOS #(2, 1) g12 (.Z(Q), .S(w14), .G(R)); //: @(560,406) /sn:0 /anc:1 /w:[ 13 3 9 ] //: comment g30 @(23,420) /anc:1 //: /line:"5) Return the \"R\" switch to the off position" //: /line:"and press the space bar 10 to 20 times. The" //: /line:"\"Q\" and \"_Q\" signals will remain constant." //: /end //: LED g33 (S) @(503,74) /sn:0 /w:[ 5 ] /type:0 endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGNMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify nmos #Dgz mos (Z, S, G); endmodule // nmos_trans //: /builtinEnd //: /builtinBegin module _GGPMOS #(.Diz(1), .Dgz(1)) (Z, S, G); input S, G; output Z; // specify // (G *> Z) = Dgz; // (S *> Z) = Diz; // endspecify pmos #Dgz pos (Z, S, G); endmodule // pmos_trans //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex3/counter.v000644 001751 001751 00000007651 11135014432 022035 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "counter.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg [7:0] w4; //: /sn:0 {0}(#:208,114)(208,167){1} reg w8; //: /sn:0 {0}(263,269)(325,269)(325,283){1} supply0 w11; //: /sn:0 {0}(269,197)(269,181)(248,181){1} reg w9; //: /sn:0 {0}(263,259)(324,259)(324,245){1} wire w12; //: /sn:0 {0}(200,181)(190,181){1} wire ck; //: {0}(50:187,264)(56,264){1} wire [7:0] w5; //: /sn:0 {0}(#:224,196)(224,254){1} wire [7:0] reg_out; //: {0}(#:50:224,275)(224,332)(297,332)(297,173){1} //: {2}(299,171)(379,171){3} //: {4}(297,169)(297,125)(240,125)(240,167){5} //: enddecls //: comment g8 @(41,205) //: /line:"2) Place a probe" //: /line:"on the clock line by" //: /line:"double-clicking on it." //: /end _GGCLOCK_P100_0_50 g4 (.Z(ck)); //: @(43,264) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g13 @(23,412) //: /line:"7) Now hit a tab to advance one clock cycle." //: /line:"Since the clear line is asserted low, the" //: /line:"register will be cleared. Next set the clear" //: /line:"line to \"on\" and continue pressing the \"tab\"" //: /line:"key. Observe the value of the register counting" //: /line:"up with each clock cycle." //: /end //: DIP g3 (w4) @(208,104) /sn:0 /w:[ 0 ] /st:1 _GGADD8 #(68, 70, 62, 64) g2 (.A(w4), .B(reg_out), .S(w5), .CI(w11), .CO(w12)); //: @(224,183) /sn:0 /w:[ 1 5 0 1 0 ] //: SWITCH g1 (w8) @(325,297) /sn:0 /R:1 /w:[ 1 ] /st:0 //: comment g11 @(348,218) //: /line:"5) Make sure the clear " //: /line:"line CLR is off to clear" //: /line:"the register." //: /end //: comment g10 @(270,64) //: /line:"4) Set the dip switch to 1" //: /line:"by clicking on it, entering" //: /line:"a \"1\" in the dialog box that" //: /line:"appears and pressing \"Apply\"." //: /end //: GROUND g6 (w11) @(269,203) /sn:0 /w:[ 0 ] //: comment g9 @(198,354) //: /line:"3) Place a probe on the" //: /line:"register output by" //: /line:"double-clicking on it." //: /end //: SWITCH g7 (w9) @(324,232) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: LED g17 (reg_out) @(386,171) /sn:0 /R:3 /w:[ 3 ] /type:2 //: joint g14 (reg_out) @(297, 171) /w:[ 2 4 -1 1 ] //: comment g5 @(14,33) //: /line:"8-Bit Counter Example" //: /line:"" //: /line:"1) Start simulation by typing \"Ctl-S b\"" //: /line:"" //: /end _GGREG8 #(10, 10, 20) g0 (.Q(reg_out), .D(w5), .EN(w8), .CLR(w9), .CK(ck)); //: @(224,264) /sn:0 /w:[ 0 1 0 0 0 ] //: comment g12 @(309,316) //: /line:"6) Make sure the enable" //: /line:"line EN is off" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; // specify // $setup(D,posedge CK, Dsetup); // $hold(posedge CK,D, Dhold); // endspecify assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 8'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; wire [7:0] _S; wire _CO; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {_CO,_S} = A + B + CI; assign CO = _CO; assign S = _S; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex3/counter.v~000644 001751 001751 00000007235 11135014432 022231 0ustar00hansenhansen000000 000000 //: version "2.0-a6" //: property prefix = "_GG" //: property title = "counter.v" //: property discardChanges = 1 `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg [7:0] w4; //: /sn:0 {0}(#:208,114)(208,167){1} reg w8; //: /sn:0 {0}(263,269)(325,269)(325,283){1} supply0 w11; //: /sn:0 {0}(269,197)(269,181)(248,181){1} reg w9; //: /sn:0 {0}(263,259)(324,259)(324,245){1} wire w12; //: /sn:0 {0}(200,181)(190,181){1} wire ck; //: {0}(50:187,264)(56,264){1} wire [7:0] w5; //: /sn:0 {0}(#:224,196)(224,254){1} wire [7:0] reg_out; //: {0}(#:50:224,275)(224,332)(297,332)(297,173){1} //: {2}(299,171)(379,171){3} //: {4}(297,169)(297,125)(240,125)(240,167){5} //: enddecls _GGCLOCK_P100_0_50 g4 (.Z(ck)); //: @(43,264) /sn:0 /w:[ 1 ] /omega:100 /phi:0 /duty:50 //: comment g8 @(41,205) //: /line:"2) Place a probe" //: /line:"on the clock line by" //: /line:"double-clicking on it." //: /end //: DIP g3 (w4) @(208,104) /sn:0 /w:[ 0 ] /st:1 //: comment g13 @(23,412) //: /line:"7) Now hit a tab to advance one clock cycle." //: /line:"Since the clear line is asserted low, the" //: /line:"register will be cleared. Next set the clear" //: /line:"line to \"on\" and continue pressing the \"tab\"" //: /line:"key. Observe the value of the register counting" //: /line:"up with each clock cycle." //: /end _GGADD8 #(68, 70, 62, 64) g2 (.A(w4), .B(reg_out), .S(w5), .CI(w11), .CO(w12)); //: @(224,183) /sn:0 /w:[ 1 5 0 1 0 ] //: SWITCH g1 (w8) @(325,297) /sn:0 /R:1 /w:[ 1 ] /st:0 //: comment g11 @(348,218) //: /line:"5) Make sure the clear " //: /line:"line CLR is off to clear" //: /line:"the register." //: /end //: comment g10 @(270,64) //: /line:"4) Set the dip switch to 1" //: /line:"by clicking on it, entering" //: /line:"a \"1\" in the dialog box that" //: /line:"appears and pressing \"Apply\"." //: /end //: GROUND g6 (w11) @(269,203) /sn:0 /w:[ 0 ] //: SWITCH g7 (w9) @(324,232) /sn:0 /R:3 /w:[ 1 ] /st:0 //: comment g9 @(198,354) //: /line:"3) Place a probe on the" //: /line:"register output by" //: /line:"double-clicking on it." //: /end //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: LED g17 (reg_out) @(386,171) /sn:0 /R:3 /w:[ 3 ] /type:2 //: comment g5 @(14,33) //: /line:"8-Bit Counter Example" //: /line:"" //: /line:"1) Start simulation by typing \"Ctl-S b\"" //: /line:"" //: /end //: joint g14 (reg_out) @(297, 171) /w:[ 2 4 -1 1 ] _GGREG8 #(10, 10, 20) g0 (.Q(reg_out), .D(w5), .EN(w8), .CLR(w9), .CK(ck)); //: @(224,264) /sn:0 /w:[ 0 1 0 0 0 ] //: comment g12 @(309,316) //: /line:"6) Make sure the enable" //: /line:"line EN is off" //: /end endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK); input CK,EN,CLR; input [7:0] D; output [7:0] Q; reg [7:0] Qreg; assign #Dck_q Q = Qreg; always @(posedge CK or negedge CLR) begin if (CLR === 1'b0) Qreg = 8'h0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; end endmodule //: /builtinEnd //: /builtinBegin module _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO); input CI; output CO; input [7:0] A,B; output [7:0] S; specify (A,B *> S) = Dab_s; (A,B *> CO) = Dab_co; (CI *> S) = Dci_s; (CI *> CO) = Dci_co; endspecify assign {CO,S} = A + B + CI; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex2/flipflop.v000644 001751 001751 00000010503 11135014451 022157 0ustar00hansenhansen000000 000000 //: version "2.0-b6" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "flipflop.v" //: require "tty" //: require "coke" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg w6; //: /sn:0 {0}(336,226)(336,171){1} //: {2}(338,169)(471,169){3} //: {4}(475,169)(630,169)(630,229){5} //: {6}(473,171)(473,226){7} //: {8}(334,169)(178,169){9} supply0 w4; //: /sn:0 {0}(661,215)(661,212)(640,212)(640,229){1} supply0 w3; //: /sn:0 {0}(499,211)(499,207)(483,207)(483,226){1} supply0 w0; //: /sn:0 {0}(346,226)(346,200)(362,200)(362,210){1} wire w7; //: /sn:0 {0}(494,247)(504,247){1} wire w16; //: /sn:0 {0}(435,235)(446,235)(446,242)(462,242){1} wire w19; //: /sn:0 {0}(555,270)(564,270)(564,247)(574,247){1} wire w15; //: /sn:0 {0}(458,122)(458,139)(380,139)(380,235){1} //: {2}(382,237)(414,237){3} //: {4}(378,237)(357,237){5} //: {6}(380,239)(380,272)(534,272){7} wire w1; //: /sn:0 {0}(357,247)(367,247)(367,277)(312,277)(312,242)(325,242){1} wire [2:0] w17; //: /sn:0 {0}(#:448,116)(448,91){1} wire w12; //: /sn:0 {0}(595,245)(619,245){1} wire w11; //: /sn:0 {0}(438,122)(438,152)(677,152)(677,188){1} //: {2}(675,190)(564,190)(564,242)(574,242){3} //: {4}(677,192)(677,240)(651,240){5} wire w2; //: /sn:0 {0}(175,344)(339,344){1} //: {2}(343,344)(476,344){3} //: {4}(480,344)(635,344)(635,261){5} //: {6}(478,342)(478,258){7} //: {8}(341,342)(341,258){9} wire w13; //: /sn:0 {0}(651,250)(661,250){1} wire w5; //: /sn:0 {0}(494,237)(518,237){1} //: {2}(520,235)(520,194){3} //: {4}(520,190)(520,133)(448,133)(448,122){5} //: {6}(518,192)(404,192)(404,232)(414,232){7} //: {8}(520,239)(520,267)(534,267){9} //: enddecls //: GROUND g8 (w3) @(499,217) /sn:0 /w:[ 0 ] _GGCLOCK_P100_0_50 g4 (.Z(w2)); //: @(162,344) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g3 (w0) @(362,216) /sn:0 /w:[ 1 ] //: LED g13 (w17) @(448,84) /sn:0 /w:[ 1 ] /type:1 _GGFF #(10, 10, 20) g2 (.Q(w11), ._Q(w13), .D(w12), .EN(w4), .CLR(w6), .CK(w2)); //: @(635,245) /sn:0 /w:[ 5 0 1 1 5 5 ] /mi:0 _GGFF #(10, 10, 20) g1 (.Q(w5), ._Q(w7), .D(w16), .EN(w3), .CLR(w6), .CK(w2)); //: @(478,242) /sn:0 /w:[ 0 0 1 1 7 7 ] /mi:0 //: joint g16 (w5) @(520, 192) /w:[ -1 4 6 3 ] //: joint g11 (w2) @(341, 344) /w:[ 2 8 1 -1 ] _GGAND2 #(6) g19 (.I0(w5), .I1(w15), .Z(w19)); //: @(545,270) /sn:0 /w:[ 9 7 0 ] /eb:0 //: joint g6 (w6) @(336, 169) /w:[ 2 -1 8 1 ] //: GROUND g9 (w4) @(661,221) /sn:0 /w:[ 0 ] //: joint g7 (w6) @(473, 169) /w:[ 4 -1 3 6 ] //: joint g20 (w5) @(520, 237) /w:[ -1 2 1 8 ] _GGXOR2 #(8) g15 (.I0(w5), .I1(w15), .Z(w16)); //: @(425,235) /sn:0 /w:[ 7 3 0 ] /eb:0 //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: joint g17 (w15) @(380, 237) /w:[ 2 1 4 6 ] assign w17 = {w11, w5, w15}; //: CONCAT g14 @(448,117) /sn:0 /R:1 /w:[ 0 0 5 0 ] /dr:0 /tp:0 /drp:1 //: SWITCH g5 (w6) @(161,169) /sn:0 /w:[ 9 ] /st:1 //: joint g21 (w11) @(677, 190) /w:[ -1 1 2 4 ] _GGFF #(10, 10, 20) g0 (.Q(w15), ._Q(w1), .D(w1), .EN(w0), .CLR(w6), .CK(w2)); //: @(341,242) /sn:0 /w:[ 5 0 1 0 0 9 ] /mi:0 _GGXOR2 #(8) g18 (.I0(w11), .I1(w19), .Z(w12)); //: @(585,245) /sn:0 /w:[ 3 1 0 ] /eb:0 //: joint g12 (w2) @(478, 344) /w:[ 4 6 3 -1 ] endmodule //: /netlistEnd `timescale 1ns/1ns //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; assign #Diz Z = ( I0 ^ I1 ); endmodule // xor //: /builtinEnd //: /builtinBegin module _GGFF #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, _Q, D, EN, CLR, CK); input CK,EN,CLR; input D; output Q,_Q; reg Qreg; specify $setup(D,posedge CK, Dsetup); $hold(posedge CK,D, Dhold); endspecify assign #Dck_q Q = Qreg; assign #Dck_q _Q = ~Qreg; always @(posedge CK or negedge CLR) if (CLR === 1'b0) Qreg = 1'b0; else if (CK === 1'b1 && EN === 1'b0) Qreg = D; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z = 1'b0; initial #50 forever begin Z = 1'b1; #50; Z = 1'b0; #50; end endmodule // clock //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0, I1; reg Z; assign #Diz Z = ( I0 & I1 ); endmodule // and //: /builtinEnd tkgate-2.0-b10/locale/en/examples/ex2/flipflop.v~000644 001751 001751 00000010136 11135014451 022357 0ustar00hansenhansen000000 000000 //: version "2.0" //: property prefix = "_GG" //: property title = "flipflop.v" //: property useExtBars = 0 //: require "tty" //: require "coke" //: /netlistBegin main module main; //: root_module reg w6; //: /sn:0 {0}(336,226)(336,171){1} //: {2}(338,169)(471,169){3} //: {4}(475,169)(630,169)(630,229){5} //: {6}(473,171)(473,226){7} //: {8}(334,169)(178,169){9} supply0 w4; //: /sn:0 {0}(661,215)(661,212)(640,212)(640,229){1} supply0 w0; //: /sn:0 {0}(346,226)(346,200)(362,200)(362,210){1} supply0 w3; //: /sn:0 {0}(499,211)(499,207)(483,207)(483,226){1} wire w7; //: /sn:0 {0}(494,247)(504,247){1} wire w16; //: /sn:0 {0}(435,235)(446,235)(446,242)(462,242){1} wire w15; //: /sn:0 {0}(458,122)(458,139)(380,139)(380,235){1} //: {2}(382,237)(414,237){3} //: {4}(378,237)(357,237){5} //: {6}(380,239)(380,272)(534,272){7} wire w19; //: /sn:0 {0}(555,270)(564,270)(564,247)(574,247){1} wire w1; //: /sn:0 {0}(357,247)(367,247)(367,277)(312,277)(312,242)(325,242){1} wire [2:0] w17; //: /sn:0 {0}(#:448,116)(448,91){1} wire w2; //: /sn:0 {0}(175,344)(339,344){1} //: {2}(343,344)(476,344){3} //: {4}(480,344)(635,344)(635,261){5} //: {6}(478,342)(478,258){7} //: {8}(341,342)(341,258){9} wire w11; //: /sn:0 {0}(438,122)(438,152)(677,152)(677,188){1} //: {2}(675,190)(564,190)(564,242)(574,242){3} //: {4}(677,192)(677,240)(651,240){5} wire w12; //: /sn:0 {0}(595,245)(619,245){1} wire w13; //: /sn:0 {0}(651,250)(661,250){1} wire w5; //: /sn:0 {0}(494,237)(518,237){1} //: {2}(520,235)(520,194){3} //: {4}(520,190)(520,133)(448,133)(448,122){5} //: {6}(518,192)(404,192)(404,232)(414,232){7} //: {8}(520,239)(520,267)(534,267){9} //: enddecls _GGCLOCK_P100_0_50 g4 (.Z(w2)); //: @(162,344) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50 //: GROUND g8 (w3) @(499,217) /sn:0 /w:[ 0 ] //: LED g13 (w17) @(448,84) /sn:0 /w:[ 1 ] /type:1 //: GROUND g3 (w0) @(362,216) /sn:0 /w:[ 1 ] _GGFF #(10, 10, 20) g2 (.Q(w11), ._Q(w13), .D(w12), .EN(w4), .CLR(w6), .CK(w2)); //: @(635,245) /sn:0 /w:[ 5 0 1 1 5 5 ] _GGFF #(10, 10, 20) g1 (.Q(w5), ._Q(w7), .D(w16), .EN(w3), .CLR(w6), .CK(w2)); //: @(478,242) /sn:0 /w:[ 0 0 1 1 7 7 ] //: joint g11 (w2) @(341, 344) /w:[ 2 8 1 -1 ] //: joint g16 (w5) @(520, 192) /w:[ -1 4 6 3 ] _GGAND2 #(6) g19 (.I0(w5), .I1(w15), .Z(w19)); //: @(545,270) /sn:0 /w:[ 9 7 0 ] //: joint g6 (w6) @(336, 169) /w:[ 2 -1 8 1 ] //: joint g7 (w6) @(473, 169) /w:[ 4 -1 3 6 ] //: GROUND g9 (w4) @(661,221) /sn:0 /w:[ 0 ] _GGXOR2 #(8) g15 (.I0(w5), .I1(w15), .Z(w16)); //: @(425,235) /sn:0 /w:[ 7 3 0 ] //: joint g20 (w5) @(520, 237) /w:[ -1 2 1 8 ] //: comment g39 @(20,12) /sn:0 //: /line:"[BACK]" //: /end //: joint g17 (w15) @(380, 237) /w:[ 2 1 4 6 ] //: SWITCH g5 (w6) @(161,169) /sn:0 /w:[ 9 ] /st:1 assign w17 = {w11, w5, w15}; //: CONCAT g14 @(448,117) /sn:0 /R:1 /w:[ 0 0 5 0 ] /dr:0 /tp:0 /drp:1 //: joint g21 (w11) @(677, 190) /w:[ -1 1 2 4 ] _GGFF #(10, 10, 20) g0 (.Q(w15), ._Q(w1), .D(w1), .EN(w0), .CLR(w6), .CK(w2)); //: @(341,242) /sn:0 /w:[ 5 0 1 0 0 9 ] //: joint g12 (w2) @(478, 344) /w:[ 4 6 3 -1 ] _GGXOR2 #(8) g18 (.I0(w11), .I1(w19), .Z(w12)); //: @(585,245) /sn:0 /w:[ 3 1 0 ] endmodule //: /netlistEnd //: /builtinBegin module _GGXOR2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 ^ I1; endmodule //: /builtinEnd //: /builtinBegin module _GGFF #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, _Q, D, EN, CLR, CK); input CK,EN,CLR; input D; output Q,_Q; reg Qreg; specify $setup(D,posedge CK, Dsetup); $hold(posedge CK,D, Dhold); endspecify assign #Dck_q Q = Qreg; assign #Dck_q _Q = ~Qreg; always @(posedge CK or CLR) if (~CLR) Qreg <= 0; else if (CK) Qreg <= D; endmodule //: /builtinEnd //: /builtinBegin module _GGCLOCK_P100_0_50 (Z); output Z; reg Z; initial #0 begin forever begin Z = 1'b0; #50; Z = 1'b1; #50; end end endmodule //: /builtinEnd //: /builtinBegin module _GGAND2 #(.Diz(1)) (I0, I1, Z); output Z; input I0; input I1; assign #Diz Z = I0 & I1; endmodule //: /builtinEnd tkgate-2.0-b10/images/Uwsdip.gif000644 001751 001751 00000000367 11150117546 017224 0ustar00hansenhansen000000 000000 GIF87a22ð€€€€,22ÖŒ©Ëí£œt[óÃXûÄßh„ähž^ªj—ØÆò¼öçúÎìþìÁh”ЫëK"ÓQyc‘Ó©ÂÙŒ2‘ÛNJyÍr­Ù&R¿C6wœ†‹bx7ÞCÎU4U=Áçåg"·Wç6˜—õDf馆µ%5؇9)户艧ÙFHšiÑ(¹ô¦äúZˆ;ûÃj{‹›»¥÷ñkX¹J, JŒ2j´8\,õæÛÆQ#=J ý„]v|H:lœ¡gmy¬½ò½Î¾A®/?O_;tkgate-2.0-b10/images/smalllogo.xbm000644 001751 001751 00000001322 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0xff, 0xff, 0x01, 0xff, 0xff, 0xef, 0xff, 0xff, 0x01}; tkgate-2.0-b10/images/regLR.b000644 001751 001751 00000012234 07311226663 016441 0ustar00hansenhansen000000 000000 #define regLR_width 75 #define regLR_height 83 static unsigned char regLR_bits[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xe1, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x21, 0x05, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xe1, 0x04, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xa1, 0x04, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x2f, 0x05, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x05, 0x31, 0x00, 0x00, 0x00, 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0x00, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xfb, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07}; tkgate-2.0-b10/images/ram.b000644 001751 001751 00000026664 10011773446 016216 0ustar00hansenhansen000000 000000 #define ram_width 84 #define ram_height 169 static unsigned char ram_bits[] = { 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0xe0, 0x3f, 0x00, 0x0a, 0x00, 0x80, 0x07, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x40, 0x08, 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x20, 0x10, 0x00, 0x00, 0x08, 0x01, 0x20, 0x3a, 0x00, 0x0a, 0x00, 0x20, 0x10, 0x00, 0x52, 0x09, 0x01, 0xa0, 0x0a, 0x00, 0x0a, 0x00, 0xe0, 0x1f, 0x00, 0x52, 0x09, 0x01, 0xa0, 0x3a, 0x00, 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0x00, 0x00, 0x80, 0x0d, 0xc0, 0xcc, 0x00, 0x0c, 0xfb, 0x06, 0x80, 0x7f, 0x00, 0x80, 0x0d, 0xe0, 0xb6, 0x01, 0x0c, 0xfb, 0x06, 0x80, 0x7f, 0x00, 0x80, 0x0d, 0xc0, 0xb6, 0x01, 0x0c, 0xab, 0x06, 0x80, 0x61, 0x00, 0x80, 0x0d, 0xf0, 0x86, 0x01, 0x0c, 0x8b, 0x06, 0x80, 0x61, 0x00, 0x80, 0x0d, 0x00, 0x00, 0x00, 0x0c, 0x03, 0x00, 0x00, 0x3f, 0x00, 0x80, 0x0d, 0xf0, 0xff, 0x01, 0x0c, 0x03, 0x00, 0x00, 0x1e, 0x00, 0x80, 0x0d, 0xf0, 0xff, 0x01, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0d, 0x00, 0x00, 0x00, 0x0c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f}; tkgate-2.0-b10/images/probe.b000644 001751 001751 00000001561 07311226663 016536 0ustar00hansenhansen000000 000000 #define probe_width 30 #define probe_height 30 #define probe_x_hot 7 #define probe_y_hot 23 static unsigned char probe_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0xf0, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x80, 0x0f, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/pmos.b000644 001751 001751 00000004201 07311226663 016377 0ustar00hansenhansen000000 000000 #define pmos_width 33 #define pmos_height 67 static unsigned char pmos_bits[] = { 0x20, 0x80, 0xff, 0x7f, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x3f, 0x00, 0x00, 0x00, 0x19, 0x80, 0xff, 0x7f, 0x00, 0x29, 0x80, 0x00, 0xe0, 0x00, 0x09, 0x80, 0x00, 0x50, 0x01, 0x09, 0x80, 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0x60, 0x00, 0x1b, 0x80, 0x01, 0xf0, 0x00, 0x1b, 0x80, 0x01, 0xf8, 0x01, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x80, 0x01, 0x60, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x1b, 0x00, 0xf8, 0xbf, 0x01, 0xfb, 0x3f, 0xf8, 0xbf, 0x01, 0xfb, 0x3f, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x0c, 0x00, 0x03, 0xb0, 0x01, 0x3f, 0x00, 0x03, 0xb0, 0x01, 0x1e, 0x00, 0x03, 0xb4, 0x01, 0xfc, 0xff, 0x03, 0xbc, 0x01, 0xfc, 0xff, 0xfb, 0xbf, 0x01, 0x00, 0x00, 0xf8, 0xbf, 0x01, 0xfc, 0xff, 0x03, 0x1c, 0x00, 0xfc, 0xff, 0x03, 0x04, 0x00}; tkgate-2.0-b10/images/or.b000644 001751 001751 00000004625 07311226663 016053 0ustar00hansenhansen000000 000000 #define or_width 38 #define or_height 76 static unsigned char or_bits[] = { 0xff, 0x0f, 0x00, 0x20, 0x00, 0x02, 0x30, 0x00, 0x50, 0x00, 0x02, 0xc0, 0x00, 0x88, 0x00, 0x04, 0x00, 0x01, 0x04, 0x01, 0x04, 0x00, 0x02, 0x02, 0x02, 0x08, 0x00, 0x04, 0x01, 0x04, 0x08, 0x00, 0x08, 0x01, 0x04, 0x08, 0x00, 0x90, 0x00, 0x08, 0x08, 0x00, 0x88, 0x00, 0x08, 0x08, 0x00, 0x44, 0x00, 0x10, 0x04, 0x00, 0x42, 0x00, 0x10, 0x04, 0x00, 0x41, 0x00, 0x10, 0x02, 0xc0, 0x40, 0x00, 0x10, 0x02, 0x30, 0x40, 0x00, 0x10, 0xff, 0x0f, 0x40, 0x00, 0x10, 0x00, 0x00, 0x40, 0x00, 0x10, 0x01, 0x40, 0x40, 0x00, 0x10, 0x07, 0x70, 0x40, 0xf8, 0x10, 0x19, 0x4c, 0x40, 0x06, 0x13, 0xe1, 0x43, 0xc0, 0x01, 0x1c, 0x01, 0x40, 0x40, 0x00, 0x10, 0x01, 0x40, 0x00, 0x00, 0x00, 0x01, 0x40, 0x00, 0xfe, 0x1f, 0x01, 0x40, 0x80, 0x01, 0x08, 0x01, 0x40, 0x60, 0x00, 0x08, 0x01, 0x40, 0x10, 0x00, 0x04, 0x01, 0x40, 0x08, 0x00, 0x04, 0x01, 0x40, 0x04, 0x00, 0x02, 0x02, 0x20, 0x02, 0x00, 0x02, 0x02, 0x20, 0x01, 0x00, 0x02, 0x04, 0x10, 0x02, 0x00, 0x02, 0x04, 0x10, 0x04, 0x00, 0x02, 0x08, 0x08, 0x08, 0x00, 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0x06, 0x30, 0x06, 0x00, 0x03, 0x06, 0x30, 0x03, 0x00, 0x03, 0x0c, 0x18, 0x06, 0x00, 0x03, 0x0c, 0x18, 0x0c, 0x00, 0x03, 0x18, 0x0c, 0x18, 0x00, 0x06, 0x30, 0x06, 0x70, 0x00, 0x06, 0x60, 0x03, 0xe0, 0x01, 0x0c, 0xc0, 0x01, 0x80, 0xff, 0x1f, 0x80, 0x00, 0x00, 0xfe, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/nmos.b000644 001751 001751 00000004201 07311226663 016375 0ustar00hansenhansen000000 000000 #define nmos_width 33 #define nmos_height 67 static unsigned char nmos_bits[] = { 0xf9, 0x3f, 0xfe, 0xff, 0x01, 0x09, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0xfe, 0xff, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x00, 0x02, 0x00, 0x01, 0x09, 0x80, 0x0a, 0x00, 0x01, 0x09, 0x00, 0x07, 0x00, 0x01, 0x09, 0x08, 0x02, 0x00, 0x01, 0x09, 0x10, 0x00, 0x00, 0x00, 0xf9, 0x3f, 0x20, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 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0x00, 0x18, 0x30, 0x00, 0x00, 0x00, 0x08, 0xf8, 0xbf, 0x01, 0x00, 0x00, 0xf8, 0xbf, 0x01, 0x03, 0xc0, 0x30, 0xb0, 0x01, 0x03, 0xe0, 0x21, 0xb0, 0x01, 0x03, 0xf0, 0x03, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0x03, 0xc0, 0x00, 0xb0, 0x01, 0xff, 0xff, 0x00, 0xb0, 0x01, 0xff, 0xff, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0xb0, 0x01, 0xff, 0xff, 0xf8, 0xbf, 0x01, 0xff, 0xff, 0xf8, 0xbf, 0x01}; tkgate-2.0-b10/images/mux.b000644 001751 001751 00000032167 07311226663 016246 0ustar00hansenhansen000000 000000 #define mux_width 89 #define mux_height 178 static unsigned char mux_bits[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x18, 0x00, 0x00, 0x00, 0x02, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe0, 0x01, 0x8c, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x30, 0x00, 0x80, 0x07, 0x8c, 0x01, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x30, 0x00, 0x00, 0x1e, 0xcc, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x60, 0x00, 0x00, 0x78, 0xcc, 0x00, 0x00, 0x80, 0x31, 0x00, 0x00, 0x60, 0x00, 0x00, 0xe0, 0x6d, 0x00, 0x00, 0xc0, 0x60, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x80, 0xef, 0xff, 0xff, 0x7f, 0xc0, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0xee, 0xff, 0xff, 0x3f, 0x80, 0xff, 0xff, 0xff}; tkgate-2.0-b10/images/misc.b000644 001751 001751 00000002700 07311226663 016356 0ustar00hansenhansen000000 000000 #define misc_width 41 #define misc_height 37 static unsigned char misc_bits[] = { 0x00, 0x00, 0x00, 0x40, 0x01, 0x01, 0x00, 0x00, 0x00, 0x30, 0x82, 0x00, 0x00, 0x00, 0x00, 0x38, 0x44, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x28, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x31, 0x28, 0x00, 0x00, 0x00, 0x90, 0x01, 0x44, 0x00, 0x00, 0x00, 0x48, 0x02, 0x82, 0x00, 0x00, 0x00, 0x47, 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0x60, 0x01, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/lprobe.b000644 001751 001751 00000001063 07311226663 016707 0ustar00hansenhansen000000 000000 #define probe_width 23 #define probe_height 23 #define probe_x_hot 2 #define probe_y_hot 20 static unsigned char probe_bits[] = { 0x00, 0x00, 0x30, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x1f, 0x00, 0x80, 0x0f, 0x00, 0xc0, 0x07, 0x00, 0xe0, 0x03, 0x00, 0xf0, 0x01, 0x00, 0xf8, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x07, 0x00, 0x80, 0x01, 0x00, 0xc0, 0x00, 0x00, 0x60, 0x00, 0x00, 0x38, 0x00, 0x00, 0x14, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x05, 0x00, 0x00, 0x03, 0x00, 0x00}; tkgate-2.0-b10/images/joint.b000644 001751 001751 00000000201 07311226663 016540 0ustar00hansenhansen000000 000000 #define joint_width 3 #define joint_height 7 static unsigned char joint_bits[] = { 0x07, 0x07, 0x07, 0x00, 0x07, 0x07, 0x07}; tkgate-2.0-b10/images/iodarrow.b000644 001751 001751 00000000646 10152205406 017245 0ustar00hansenhansen000000 000000 #define iodarrow_width 29 #define iodarrow_height 13 static unsigned char iodarrow_bits[] = { 0x04, 0x04, 0x45, 0x04, 0x06, 0x84, 0x8d, 0x02, 0x7f, 0xc4, 0x1f, 0x01, 0x06, 0x84, 0x8d, 0x02, 0x04, 0x1f, 0x45, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x04, 0x04, 0x01, 0x00, 0x0e, 0x80, 0x03, 0x00, 0x1f, 0xc4, 0x07, 0x00, 0x04, 0x0c, 0x01, 0x00, 0xc4, 0xdf, 0x07, 0x00, 0x04, 0x8c, 0x03, 0x00, 0x04, 0x04, 0x01, 0x00}; tkgate-2.0-b10/images/inout.b000644 001751 001751 00000001537 07311226663 016570 0ustar00hansenhansen000000 000000 #define inout_width 31 #define inout_height 31 static unsigned char inout_bits[] = { 0x03, 0x00, 0x60, 0x08, 0x0c, 0x14, 0x18, 0x1c, 0x30, 0x14, 0x06, 0x14, 0x00, 0x22, 0x00, 0x36, 0x30, 0x22, 0x06, 0x22, 0x0c, 0x41, 0x18, 0x63, 0x03, 0x41, 0x60, 0x41, 0x00, 0x00, 0x00, 0x63, 0xe0, 0x40, 0x10, 0x22, 0xb8, 0x43, 0x10, 0x36, 0x0e, 0x8e, 0x08, 0x14, 0x03, 0x98, 0x08, 0x1c, 0x0e, 0x0e, 0x05, 0x08, 0xb8, 0x03, 0x05, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x60, 0x08, 0x0f, 0x14, 0x78, 0x1c, 0x3c, 0x14, 0x1e, 0x1c, 0x00, 0x36, 0x00, 0x36, 0x3c, 0x36, 0x1e, 0x36, 0x0f, 0x63, 0x78, 0x63, 0x03, 0x63, 0x60, 0x63, 0x00, 0x00, 0x00, 0x63, 0xe0, 0xc0, 0x18, 0x36, 0xf8, 0xc3, 0x18, 0x36, 0x1e, 0x8f, 0x0d, 0x1c, 0x07, 0x98, 0x0d, 0x1c, 0x1e, 0x0f, 0x05, 0x08, 0xf8, 0x03, 0x05, 0x00, 0xe0, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/ground.b000644 001751 001751 00000001713 10012272761 016714 0ustar00hansenhansen000000 000000 #define ground_width 23 #define ground_height 47 static unsigned char ground_bits[] = { 0x20, 0x00, 0x01, 0x20, 0x00, 0x09, 0x20, 0x00, 0x09, 0x20, 0x00, 0x09, 0xff, 0x07, 0x49, 0x00, 0xf0, 0x49, 0x00, 0x00, 0x49, 0xfc, 0x03, 0x09, 0x00, 0x00, 0x09, 0x00, 0x00, 0x01, 0x70, 0x00, 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x07, 0x40, 0x00, 0x00, 0x48, 0x00, 0x00, 0x48, 0xe0, 0x1f, 0x49, 0x00, 0x00, 0xc9, 0x07, 0x00, 0x49, 0xf0, 0x7f, 0x48, 0x00, 0x02, 0x48, 0x00, 0x02, 0x48, 0x00, 0x02, 0x40, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x80, 0x01, 0x20, 0x80, 0x0d, 0x20, 0x80, 0x0d, 0xff, 0x87, 0x0d, 0xff, 0x87, 0x6d, 0x00, 0xf0, 0x6d, 0xfc, 0x83, 0x6d, 0xfc, 0x83, 0x0d, 0x00, 0x80, 0x0d, 0x70, 0x80, 0x01, 0x70, 0x80, 0x01, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x07, 0xc0, 0x00, 0x07, 0xd8, 0x00, 0x00, 0xd8, 0xe0, 0x1f, 0xdb, 0xe0, 0x1f, 0xdb, 0x07, 0x00, 0xdb, 0xf0, 0x7f, 0xd8, 0xf0, 0x7f, 0xd8, 0x00, 0x02, 0xd8, 0x00, 0x02, 0xc0, 0x00, 0x02}; tkgate-2.0-b10/images/divide.b000644 001751 001751 00000027745 07311226663 016707 0ustar00hansenhansen000000 000000 #define divide_width 88 #define divide_height 177 static unsigned char divide_bits[] = { 0xff, 0xff, 0xff, 0x01, 0xfc, 0xff, 0xff, 0x77, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x14, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x12, 0x18, 0x00, 0x00, 0x02, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x12, 0x60, 0x00, 0x00, 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0x00, 0x80, 0x07, 0x8c, 0x01, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x30, 0x00, 0x00, 0x1e, 0xcc, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x60, 0x00, 0x00, 0x78, 0xcc, 0x00, 0x00, 0x80, 0x31, 0x00, 0x00, 0x60, 0x00, 0x00, 0xe0, 0x6d, 0x00, 0x00, 0xc0, 0x60, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x80, 0xef, 0xff, 0xff, 0x7f, 0xc0, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0xee, 0xff, 0xff, 0x3f, 0x80, 0xff, 0xff, 0xff}; tkgate-2.0-b10/images/dip.b000644 001751 001751 00000005125 07311226663 016203 0ustar00hansenhansen000000 000000 #define dip_width 75 #define dip_height 41 static unsigned char dip_bits[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xb9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xa9, 0x05, 0x3c, 0x1e, 0x8f, 0xc7, 0xe3, 0xf1, 0x78, 0x04, 0xa9, 0x06, 0x24, 0x12, 0x89, 0x44, 0x22, 0x91, 0x48, 0x04, 0xa9, 0x06, 0x3c, 0x1e, 0x8f, 0xc7, 0xe3, 0xf1, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07}; tkgate-2.0-b10/images/concat.b000644 001751 001751 00000001553 07311226663 016677 0ustar00hansenhansen000000 000000 #define merge_width 23 #define merge_height 42 static unsigned char merge_bits[] = { 0xe2, 0x8c, 0x07, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x66, 0x9c, 0x03, 0x66, 0x9c, 0x03, 0x66, 0x9c, 0x03, 0x66, 0x9c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x42, 0x0c, 0x03, 0x47, 0x1e, 0x03, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x40, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xff, 0xff, 0x7f, 0x01, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x40, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x01, 0x3c, 0x00}; tkgate-2.0-b10/images/clock.b000644 001751 001751 00000011113 07311226663 016514 0ustar00hansenhansen000000 000000 #define clock_width 52 #define clock_height 105 static unsigned char clock_bits[] = { 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x20, 0x02, 0x00, 0x01, 0x0c, 0x00, 0x00, 0x20, 0x02, 0x00, 0x01, 0x30, 0x00, 0x00, 0x10, 0x04, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x10, 0x04, 0x00, 0xf1, 0x01, 0x03, 0x00, 0x08, 0x08, 0x00, 0x11, 0x01, 0x0c, 0x00, 0x08, 0x08, 0x00, 0x11, 0x01, 0x30, 0x00, 0x04, 0x10, 0x00, 0x11, 0x01, 0xc0, 0x00, 0x04, 0x10, 0x00, 0x11, 0x01, 0x00, 0x03, 0x02, 0x20, 0x00, 0x11, 0x01, 0xc0, 0x00, 0x02, 0x20, 0x00, 0x11, 0x01, 0x30, 0x00, 0x01, 0x40, 0x00, 0x11, 0x01, 0x0c, 0x00, 0x01, 0x48, 0x00, 0x1d, 0x07, 0x03, 0x80, 0x00, 0x88, 0x00, 0x01, 0xc0, 0x00, 0x80, 0xf8, 0x8f, 0x00, 0x01, 0x30, 0x00, 0x40, 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0x01, 0x00, 0x03, 0x88, 0x08, 0x00, 0x01, 0x01, 0x00, 0x0c, 0xf8, 0x08, 0x00, 0x82, 0x00, 0x00, 0x30, 0x00, 0x08, 0x00, 0x82, 0x00, 0x00, 0xc0, 0x00, 0x08, 0x00, 0x44, 0x00, 0x00, 0x00, 0x03, 0x08, 0x00, 0x44, 0x00, 0x00, 0x00, 0x0c, 0x08, 0x00, 0x28, 0x00, 0x00, 0x00, 0x30, 0x08, 0x00, 0x28, 0x00, 0x00, 0x00, 0xc0, 0x08, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0xf3, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0xc3, 0x03, 0x00, 0x00, 0x60, 0x03, 0x00, 0x03, 0x0f, 0x00, 0x00, 0x60, 0x03, 0x00, 0x03, 0x3c, 0x00, 0x00, 0x30, 0x06, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x30, 0x06, 0x00, 0xf3, 0xc3, 0x03, 0x00, 0x18, 0x0c, 0x00, 0xf3, 0x03, 0x0f, 0x00, 0x18, 0x0c, 0x00, 0x33, 0x03, 0x3c, 0x00, 0x0c, 0x18, 0x00, 0x33, 0x03, 0xf0, 0x00, 0x0c, 0x18, 0x00, 0x33, 0x03, 0xc0, 0x03, 0x06, 0x30, 0x00, 0x33, 0x03, 0xf0, 0x00, 0x06, 0x30, 0x00, 0x33, 0x03, 0x3c, 0x00, 0x03, 0x6c, 0x00, 0x3f, 0x0f, 0x0f, 0x00, 0x03, 0x6c, 0x00, 0x3f, 0xcf, 0x03, 0x80, 0xf9, 0xcf, 0x00, 0x03, 0xf0, 0x00, 0x80, 0xf9, 0xcf, 0x00, 0x03, 0x3c, 0x00, 0xc0, 0x18, 0x80, 0x01, 0x03, 0x0f, 0x00, 0xc0, 0x18, 0x80, 0x01, 0xc3, 0x03, 0x00, 0x60, 0xf8, 0x0f, 0x03, 0xf3, 0x00, 0x00, 0x60, 0xf8, 0x0f, 0x03, 0x3f, 0x00, 0x00, 0x30, 0x00, 0x0c, 0x06, 0x0f, 0x00, 0x00, 0x30, 0x00, 0x0c, 0x06, 0x03, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x0f, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x0c, 0x06, 0x03, 0xc0, 0x00, 0x00, 0x00, 0x0f, 0x06, 0x03, 0xc0, 0x00, 0x00, 0xc0, 0x0f, 0x0c, 0xff, 0x61, 0x00, 0x00, 0xf0, 0x0c, 0x0c, 0xff, 0x61, 0x00, 0x00, 0x3c, 0x0c, 0x18, 0x80, 0x31, 0x00, 0x00, 0x0f, 0x0c, 0x18, 0x80, 0x31, 0x00, 0xc0, 0x03, 0x0c, 0x30, 0xff, 0x19, 0x00, 0xf0, 0x00, 0x0c, 0x30, 0xff, 0x19, 0x00, 0x3c, 0xcf, 0x0f, 0x60, 0x03, 0x0c, 0x00, 0x0f, 0xcf, 0x0f, 0x60, 0x03, 0x0c, 0xc0, 0x03, 0xcc, 0x0c, 0xc0, 0x00, 0x06, 0xf0, 0x00, 0xcc, 0x0c, 0xc0, 0x00, 0x06, 0x3c, 0x00, 0xcc, 0x0c, 0x80, 0x01, 0x03, 0xf0, 0x00, 0xcc, 0x0c, 0x80, 0x01, 0x03, 0xc0, 0x03, 0xcc, 0x0c, 0x00, 0x83, 0x01, 0x00, 0x0f, 0xfc, 0x0c, 0x00, 0x83, 0x01, 0x00, 0x3c, 0xfc, 0x0c, 0x00, 0xc6, 0x00, 0x00, 0xf0, 0x00, 0x0c, 0x00, 0xc6, 0x00, 0x00, 0xc0, 0x03, 0x0c, 0x00, 0x6c, 0x00, 0x00, 0x00, 0x0f, 0x0c, 0x00, 0x6c, 0x00, 0x00, 0x00, 0x3c, 0x0c, 0x00, 0x38, 0x00, 0x00, 0x00, 0xf0, 0x0c, 0x00, 0x38, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0c}; tkgate-2.0-b10/images/bus.b000644 001751 001751 00000002463 07311226663 016222 0ustar00hansenhansen000000 000000 #define bus_width 40 #define bus_height 40 static unsigned char bus_bits[] = { 0xc0, 0x00, 0x20, 0x00, 0x00, 0x20, 0x01, 0x10, 0x00, 0x00, 0x10, 0x02, 0x08, 0x00, 0x00, 0x08, 0x04, 0xfc, 0xff, 0x7f, 0x0c, 0x0c, 0x02, 0x00, 0x00, 0x0a, 0x14, 0x01, 0x00, 0x00, 0x09, 0xa4, 0x00, 0x00, 0x00, 0x08, 0x84, 0x00, 0x00, 0x00, 0x08, 0x04, 0x01, 0x00, 0x00, 0x08, 0x04, 0x02, 0x00, 0x00, 0x08, 0x04, 0xfc, 0xff, 0x7f, 0x08, 0x04, 0x08, 0x00, 0x00, 0x08, 0x04, 0x10, 0x00, 0x00, 0x08, 0x04, 0x20, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x08, 0x04, 0x00, 0x10, 0x08, 0x00, 0x00, 0x00, 0x10, 0x08, 0x00, 0x00, 0x02, 0x10, 0x08, 0x00, 0x00, 0x04, 0x10, 0x08, 0x00, 0x00, 0x08, 0x10, 0x08, 0xff, 0xff, 0x1f, 0x10, 0x08, 0x00, 0x00, 0x20, 0x10, 0x08, 0x00, 0x00, 0x40, 0x10, 0x08, 0x00, 0x00, 0x80, 0x10, 0x08, 0x00, 0x00, 0x80, 0x12, 0x48, 0x00, 0x00, 0x40, 0x14, 0x28, 0x00, 0x00, 0x20, 0x18, 0x18, 0xff, 0xff, 0x1f, 0x10, 0x08, 0x00, 0x00, 0x08, 0x20, 0x04, 0x00, 0x00, 0x04, 0x40, 0x02, 0x00, 0x00, 0x02, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/buf.b000644 001751 001751 00000003222 07311226663 016177 0ustar00hansenhansen000000 000000 #define buf_width 32 #define buf_height 64 static unsigned char buf_bits[] = { 0x03, 0x00, 0x80, 0x00, 0x0d, 0x00, 0x40, 0x01, 0x31, 0x00, 0x40, 0x01, 0xc1, 0x00, 0x20, 0x02, 0x01, 0x03, 0x20, 0x02, 0x01, 0x0c, 0x10, 0x04, 0x01, 0x30, 0x10, 0x04, 0x01, 0x40, 0x08, 0x08, 0x01, 0x30, 0x08, 0x08, 0x01, 0x0c, 0x04, 0x10, 0x01, 0x03, 0x04, 0x10, 0xc1, 0x00, 0x02, 0x20, 0x31, 0x00, 0x02, 0x20, 0x0d, 0x00, 0x01, 0x40, 0x03, 0x00, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0x00, 0x60, 0x01, 0x40, 0x00, 0x58, 0x02, 0x20, 0x00, 0x46, 0x02, 0x20, 0x80, 0x41, 0x04, 0x10, 0x60, 0x40, 0x04, 0x10, 0x18, 0x40, 0x08, 0x08, 0x06, 0x40, 0x08, 0x08, 0x01, 0x40, 0x10, 0x04, 0x06, 0x40, 0x10, 0x04, 0x18, 0x40, 0x20, 0x02, 0x60, 0x40, 0x20, 0x02, 0x80, 0x41, 0x40, 0x01, 0x00, 0x46, 0x40, 0x01, 0x00, 0x58, 0x80, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x80, 0x00, 0x0f, 0x00, 0xc0, 0x01, 0x3f, 0x00, 0xc0, 0x01, 0xf3, 0x00, 0x60, 0x03, 0xc3, 0x03, 0x60, 0x03, 0x03, 0x0f, 0x30, 0x06, 0x03, 0x3c, 0x30, 0x06, 0x03, 0x70, 0x18, 0x0c, 0x03, 0x3c, 0x18, 0x0c, 0x03, 0x0f, 0x0c, 0x18, 0xc3, 0x03, 0x0c, 0x18, 0xf3, 0x00, 0x06, 0x30, 0x3f, 0x00, 0x06, 0x30, 0x0f, 0x00, 0xff, 0x7f, 0x03, 0x00, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0x00, 0x60, 0xff, 0x7f, 0x00, 0x78, 0x06, 0x30, 0x00, 0x7e, 0x06, 0x30, 0x80, 0x67, 0x0c, 0x18, 0xe0, 0x61, 0x0c, 0x18, 0x78, 0x60, 0x18, 0x0c, 0x1e, 0x60, 0x18, 0x0c, 0x07, 0x60, 0x30, 0x06, 0x1e, 0x60, 0x30, 0x06, 0x78, 0x60, 0x60, 0x03, 0xe0, 0x61, 0x60, 0x03, 0x80, 0x67, 0xc0, 0x01, 0x00, 0x7e, 0xc0, 0x01, 0x00, 0x78, 0x80, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/bat.b000644 001751 001751 00000005417 07311226663 016201 0ustar00hansenhansen000000 000000 #define bat_width 81 #define bat_height 40 static unsigned char bat_bits[] = { 0x00, 0x47, 0x10, 0x07, 0x00, 0x23, 0x88, 0x01, 0x12, 0x24, 0x00, 0xc0, 0xc3, 0x18, 0x1e, 0x80, 0x61, 0x0c, 0x03, 0x33, 0x66, 0x00, 0xe0, 0xc1, 0x1d, 0x3c, 0xc0, 0xe1, 0x0e, 0x07, 0x73, 0x67, 0x00, 0xf8, 0xc1, 0x1f, 0xfc, 0xc0, 0xe1, 0x0f, 0x07, 0xf3, 0x67, 0x00, 0xf8, 0xc0, 0x1f, 0xf8, 0xe0, 0xe1, 0x0f, 0x8f, 0xf7, 0xf7, 0x00, 0xfc, 0xe1, 0x3f, 0xfc, 0xe1, 0xf3, 0x9f, 0x8f, 0xff, 0xff, 0x00, 0xfc, 0xe3, 0x3f, 0xfe, 0xe1, 0xf3, 0x9f, 0x9f, 0xff, 0xff, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xdf, 0xff, 0xff, 0x01, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x9f, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x9f, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xe7, 0xff, 0xff, 0x8f, 0xff, 0xff, 0x00, 0x3e, 0xce, 0x9f, 0xc3, 0xe3, 0xef, 0xef, 0x8f, 0xf7, 0xf7, 0x00, 0x3e, 0x84, 0x0f, 0xc1, 0xc3, 0xc5, 0x47, 0x87, 0xe7, 0xf3, 0x00, 0x3c, 0x80, 0x0f, 0xc0, 0xc1, 0xc1, 0x07, 0x07, 0xe7, 0x73, 0x00, 0x7c, 0x00, 0x07, 0xe0, 0x81, 0x83, 0x83, 0x03, 0xc3, 0x61, 0x00, 0xf8, 0x00, 0x07, 0xf8, 0x00, 0x87, 0xc3, 0x01, 0xc3, 0x61, 0x00, 0xf0, 0x00, 0x02, 0x78, 0x00, 0x06, 0xc1, 0x00, 0x82, 0x20, 0x00, 0xc0, 0x01, 0x02, 0x1c, 0x00, 0x00, 0x01, 0x00, 0x82, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x0d, 0xb0, 0x1a, 0xc0, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x19, 0xb8, 0x32, 0x60, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x31, 0x98, 0x33, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x31, 0x98, 0x33, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0x33, 0xd8, 0x37, 0xb0, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 0xfc, 0x7f, 0xf0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd6, 0x35, 0xb8, 0x3b, 0x70, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x31, 0x98, 0x33, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0x31, 0x98, 0x33, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x19, 0xb8, 0x3b, 0x60, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x08, 0x30, 0x19, 0xc0, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/arshift.b000644 001751 001751 00000033653 07311226663 017076 0ustar00hansenhansen000000 000000 #define arshift_width 117 #define arshift_height 151 static unsigned char arshift_bits[] = { 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0xfc, 0x03, 0x80, 0x7f, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x02, 0x04, 0x40, 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0x60, 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x30, 0x18, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x18, 0x30, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0c, 0x60, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x80, 0x7f, 0x00}; tkgate-2.0-b10/images/xor.b000644 001751 001751 00000006123 07311226663 016236 0ustar00hansenhansen000000 000000 #define xor_width 41 #define xor_height 82 static unsigned char xor_bits[] = { 0xf9, 0x7f, 0x00, 0x00, 0x01, 0x00, 0x12, 0x80, 0x01, 0x80, 0x02, 0x00, 0x12, 0x00, 0x06, 0x40, 0x04, 0x00, 0x24, 0x00, 0x08, 0x20, 0x08, 0x00, 0x24, 0x00, 0x10, 0x10, 0x10, 0x00, 0x48, 0x00, 0x20, 0x08, 0x20, 0x00, 0x48, 0x00, 0x40, 0x08, 0x20, 0x00, 0x48, 0x00, 0x80, 0x04, 0x40, 0x00, 0x48, 0x00, 0x40, 0x04, 0x40, 0x00, 0x48, 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0x00, 0x20, 0x02, 0x60, 0x00, 0x48, 0x00, 0x40, 0x01, 0x80, 0x01, 0x48, 0x00, 0x80, 0x00, 0x00, 0xfe, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x7f, 0x00, 0x00, 0x01, 0x00, 0xf6, 0xff, 0x01, 0x80, 0x03, 0x00, 0x66, 0x80, 0x07, 0xc0, 0x06, 0x00, 0xcc, 0x00, 0x0e, 0x60, 0x0c, 0x00, 0xcc, 0x00, 0x18, 0x30, 0x18, 0x00, 0x98, 0x01, 0x30, 0x18, 0x30, 0x00, 0x98, 0x01, 0x60, 0x18, 0x30, 0x00, 0x98, 0x01, 0xc0, 0x0c, 0x60, 0x00, 0x98, 0x01, 0x60, 0x0c, 0x60, 0x00, 0x98, 0x01, 0x30, 0x06, 0xc0, 0x00, 0xcc, 0x00, 0x18, 0x06, 0xc0, 0x00, 0xcc, 0x00, 0x0e, 0x06, 0xc0, 0x00, 0x66, 0x80, 0x07, 0x06, 0xc0, 0x00, 0xf6, 0xff, 0x01, 0x06, 0xc0, 0x00, 0xf3, 0x7f, 0x00, 0x06, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xc7, 0x00, 0x01, 0x40, 0x00, 0xf6, 0xdf, 0x00, 0x07, 0x70, 0x00, 0x3e, 0xf8, 0x00, 0x1e, 0x3c, 0x00, 0x0e, 0xe0, 0x00, 0xf8, 0x0f, 0x00, 0xc6, 0xc7, 0x00, 0xe3, 0x63, 0x00, 0xf0, 0x1f, 0x00, 0x07, 0x70, 0x00, 0x3c, 0x78, 0x00, 0x1f, 0x7c, 0x00, 0x0e, 0xe0, 0x00, 0xfb, 0x6f, 0x00, 0x02, 0x80, 0x00, 0xe3, 0x63, 0x00, 0x00, 0x00, 0x00, 0x03, 0x60, 0x00, 0xfe, 0xcf, 0x00, 0x03, 0x60, 0x80, 0xff, 0x6f, 0x00, 0x03, 0x60, 0xe0, 0x01, 0x66, 0x00, 0x03, 0x60, 0x70, 0x00, 0x33, 0x00, 0x03, 0x60, 0x18, 0x00, 0x33, 0x00, 0x03, 0x60, 0x0c, 0x80, 0x19, 0x00, 0x06, 0x30, 0x06, 0x80, 0x19, 0x00, 0x06, 0x30, 0x03, 0x80, 0x19, 0x00, 0x0c, 0x18, 0x06, 0x80, 0x19, 0x00, 0x0c, 0x18, 0x0c, 0x80, 0x19, 0x00, 0x18, 0x0c, 0x18, 0x00, 0x33, 0x00, 0x30, 0x06, 0x70, 0x00, 0x33, 0x00, 0x60, 0x03, 0xe0, 0x01, 0x66, 0x00, 0xc0, 0x01, 0x80, 0xff, 0x6f, 0x00, 0x80, 0x00, 0x00, 0xfe, 0xcf, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/led.b000644 001751 001751 00000002741 07311226663 016174 0ustar00hansenhansen000000 000000 #define led_width 28 #define led_height 57 static unsigned char led_bits[] = { 0xe0, 0x00, 0xc0, 0x0f, 0x10, 0x01, 0x38, 0x08, 0x08, 0x02, 0x06, 0x08, 0x04, 0x04, 0x01, 0x08, 0x04, 0x84, 0x00, 0x08, 0x02, 0x48, 0x00, 0x08, 0x02, 0x48, 0x00, 0x08, 0x02, 0x48, 0x00, 0x08, 0x01, 0x90, 0x00, 0x08, 0x01, 0x10, 0x01, 0x08, 0x01, 0x10, 0x06, 0x08, 0x01, 0x10, 0x38, 0x08, 0x01, 0x10, 0xc0, 0x0f, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, 0x3f, 0x80, 0x00, 0x08, 0xc1, 0x81, 0x00, 0x08, 0x01, 0x86, 0x00, 0x08, 0x01, 0x88, 0x00, 0x08, 0x01, 0x90, 0x00, 0x08, 0x01, 0x20, 0x01, 0x04, 0x01, 0x20, 0x01, 0x04, 0x01, 0x20, 0x01, 0x04, 0x01, 0x10, 0x02, 0x02, 0x01, 0x08, 0x02, 0x02, 0x01, 0x06, 0x04, 0x01, 0xc1, 0x01, 0x88, 0x00, 0x3f, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xc0, 0x0f, 0xf0, 0x01, 0xf8, 0x0f, 0x18, 0x03, 0x3e, 0x0c, 0x0c, 0x06, 0x07, 0x0c, 0x0c, 0x86, 0x01, 0x0c, 0x06, 0xcc, 0x00, 0x0c, 0x06, 0xcc, 0x00, 0x0c, 0x06, 0xcc, 0x00, 0x0c, 0x03, 0x98, 0x01, 0x0c, 0x03, 0x18, 0x07, 0x0c, 0x03, 0x18, 0x3e, 0x0c, 0x03, 0x18, 0xf8, 0x0f, 0xff, 0x1f, 0xc0, 0x0f, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, 0x3f, 0x80, 0xff, 0x0f, 0xff, 0x81, 0x01, 0x0c, 0xc3, 0x87, 0x01, 0x0c, 0x03, 0x8e, 0x01, 0x0c, 0x03, 0x98, 0x01, 0x0c, 0x03, 0x30, 0x03, 0x06, 0x03, 0x30, 0x03, 0x06, 0x03, 0x30, 0x03, 0x06, 0x03, 0x18, 0x06, 0x03, 0x03, 0x0e, 0x06, 0x03, 0xc3, 0x07, 0x8c, 0x01, 0xff, 0x01, 0xf8, 0x00, 0x3f, 0x00, 0x70, 0x00}; tkgate-2.0-b10/images/ledinside.b000644 001751 001751 00000002763 07311226663 017374 0ustar00hansenhansen000000 000000 #define ledinside_width 28 #define ledinside_height 57 static unsigned char ledinside_bits[] = { 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xc0, 0x07, 0xf0, 0x01, 0xf8, 0x07, 0xf8, 0x03, 0xfe, 0x07, 0xf8, 0x03, 0xff, 0x07, 0xfc, 0x87, 0xff, 0x07, 0xfc, 0x87, 0xff, 0x07, 0xfc, 0x87, 0xff, 0x07, 0xfe, 0x0f, 0xff, 0x07, 0xfe, 0x0f, 0xfe, 0x07, 0xfe, 0x0f, 0xf8, 0x07, 0xfe, 0x0f, 0xc0, 0x07, 0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x07, 0x3e, 0x00, 0xff, 0x07, 0xfe, 0x01, 0xff, 0x07, 0xfe, 0x07, 0xff, 0x07, 0xfe, 0x0f, 0xff, 0x07, 0xfe, 0x1f, 0xfe, 0x03, 0xfe, 0x1f, 0xfe, 0x03, 0xfe, 0x1f, 0xfe, 0x03, 0xfe, 0x0f, 0xfc, 0x01, 0xfe, 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0x07, 0xf9, 0x13, 0xf3, 0x19, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0x03, 0x18, 0xf9, 0x13, 0xfc, 0x07, 0xf9, 0x13, 0x03, 0x18, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0x07, 0x1c, 0xf3, 0x19, 0xf9, 0x13, 0xfc, 0x07}; tkgate-2.0-b10/images/ledseg1.b000644 001751 001751 00000000544 07311226663 016753 0ustar00hansenhansen000000 000000 #define ledseg1_width 13 #define ledseg1_height 21 static unsigned char ledseg1_bits[] = { 0xfc, 0x07, 0xf8, 0x03, 0xf0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/ledseg2.b000644 001751 001751 00000000544 07311226663 016754 0ustar00hansenhansen000000 000000 #define ledseg2_width 13 #define ledseg2_height 21 static unsigned char ledseg2_bits[] = { 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 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#88888888FFFF", "o c blue", /* pixels */ " ... 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", " XXXX.......o ", " XXX o....o ", " "}; tkgate-2.0-b10/images/replicate.xpm000644 001751 001751 00000000656 10222123210 017741 0ustar00hansenhansen000000 000000 /* XPM */ static char * replicate_xpm[] = { "16 16 4 1", " c yellow", ". c black", "X c blue", "o c white", " ", " . ", " . ", " . ", " XXXX ", " XoooX ", " XooooX ", " XXXXoooX ", " XoooXoX ", " XooooX ", " XXXXoooX ", " XoooXoX ", " XooooX ", " XooooX ", " XoooX ", " XXXX "}; tkgate-2.0-b10/images/replicate.gif000644 001751 001751 00000000127 10222123260 017700 0ustar00hansenhansen000000 000000 GIF89añÿÿÿÿÿÿ!ù,(„©Ë®TÀ#†¶7ëÁ)•:dŠ_¹Œ_Šœl»Â 9ÓÛŒ|;tkgate-2.0-b10/images/delgate.xpm000644 001751 001751 00000000764 10243533727 017423 0ustar00hansenhansen000000 000000 /* XPM */ static char * delgate_xpm[] = { "16 16 8 1", " c magenta", ". c #555565655757", "X c black", "o c yellow", "O c blue", "+ c white", "@ c #008b00", "# c #FFFF55552222", " ", " ", " ..XX ", " .ooXX ", " OOOOOOO.oooo. ", " O+++++.ooooo. ", "@@O++++.ooooo. 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", " O++#ooooo.+O ", " O+##oooo.++O@@", " O####oo.+++O ", " XX#####+++O ", " X###+++O ", " #++OO ", " XOO ", " "}; tkgate-2.0-b10/images/delgate.gif000644 001751 001751 00000000200 10243534015 017334 0ustar00hansenhansen000000 000000 GIF89aòÿÿUeWÿÿÿÿÿÿ‹ÿU"!ù,EºÜþð… DTaŒºˆÿD¦ AWœ§8–†A …ª•f:ÎÍ[7YŒ×·:Z Âp8C•åÐù,©‘ƒñx.`E;tkgate-2.0-b10/images/leftarrow.gif000644 001751 001751 00000000066 10222537055 017752 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù, „w‘Êž“.»L;tkgate-2.0-b10/images/rightarrow.gif000644 001751 001751 00000000067 10222537064 020136 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,bizìL²­I-u;tkgate-2.0-b10/images/symed_point.xpm000644 001751 001751 00000001006 10233071102 020315 0ustar00hansenhansen000000 000000 /* XPM */ static char *symed_point[] = { /* width height num_colors chars_per_pixel */ " 16 16 3 1", /* colors */ ". c #000000", "# c #8b008b", "a c #ffffff", /* pixels */ "aaa#aaaa#aaaa#aa", "aaa#aaaa#aaaa#aa", "################", "aaa#....#aaaa#aa", "aaa#....#aaaa#aa", "aaa#....#aaaa#aa", "aaa#....#aaaa#aa", "################", "aaa#aaaa#....#aa", "aaa#aaaa#....#aa", "aaa#aaaa#....#aa", "aaa#aaaa#....#aa", "################", "aaa#aaaa#aaaa#aa", "aaa#aaaa#aaaa#aa", "aaa#aaaa#aaaa#aa" }; tkgate-2.0-b10/images/symed_line.xpm000644 001751 001751 00000000766 10233071164 020137 0ustar00hansenhansen000000 000000 /* XPM */ static char *symed_line[] = { /* width height num_colors chars_per_pixel */ " 16 16 2 1", /* colors */ ". c #000000", "# c #ffffff", /* pixels */ "################", "################", "##.#############", "###.############", "####.###########", "#####.##########", "######.#########", "#######.########", "########.#######", "#########.######", "##########.#####", "###########.####", "############.###", "#############.##", "################", "################" }; tkgate-2.0-b10/images/symed_rect.xpm000644 001751 001751 00000000766 10233071173 020145 0ustar00hansenhansen000000 000000 /* XPM */ static char *symed_rect[] = { /* width height num_colors chars_per_pixel */ " 16 16 2 1", /* colors */ ". c #000000", "# c #ffffff", /* pixels */ "################", "################", "##............##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##.##########.##", "##............##", "################", "################" }; tkgate-2.0-b10/images/symed_point_S.xpm000644 001751 001751 00000001003 10233071440 020601 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_point_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 4 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c #8b008b", "o c black", /* pixels */ " ", " ..X....X....X. ", " XXXXXXXXXXXXXX ", " ..XooooX....X. ", " ..XooooX....X. ", " ..XooooX....X. ", " ..XooooX....X. ", " XXXXXXXXXXXXXX ", " ..X....XooooX. ", " ..X....XooooX. ", " ..X....XooooX. ", " ..X....XooooX. ", " XXXXXXXXXXXXXX ", " ..X....X....X. ", " ..X....X....X. ", " "}; tkgate-2.0-b10/images/symed_line_S.xpm000644 001751 001751 00000000763 10233071475 020423 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_line_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 3 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c black", /* pixels */ " ", " .............. ", " .X............ ", " ..X........... ", " ...X.......... ", " ....X......... ", " .....X........ ", " ......X....... ", " .......X...... ", " ........X..... ", " .........X.... ", " ..........X... ", " ...........X.. ", " ............X. ", " .............. ", " "}; tkgate-2.0-b10/images/symed_rect_S.xpm000644 001751 001751 00000000763 10233071537 020430 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_rect_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 3 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c black", /* pixels */ " ", " .............. ", " .XXXXXXXXXXXX. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .XXXXXXXXXXXX. ", " .............. ", " "}; tkgate-2.0-b10/images/symed_fillrect_S.xpm000644 001751 001751 00000000767 10233071577 021307 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_fillrect_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 3 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c black", /* pixels */ " ", " .............. ", " .............. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " ..XXXXXXXXXX.. ", " .............. ", " .............. ", " "}; tkgate-2.0-b10/images/symed_port_S.xpm000644 001751 001751 00000000761 10233071636 020455 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_port_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 3 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c red", /* pixels */ " ", " .............. ", " .............. ", " .....XXXX..... ", " ....XXXXXX.... ", " ...XXXXXXXX... ", " XXXXXXXXXXX... ", " XXXXXXXXXXX... ", " ...XXXXXXXX... ", " ....XXXXXX.... ", " .....XXXX..... ", " .............. ", " .............. ", " .............. ", " .............. ", " "}; tkgate-2.0-b10/images/symed_select_S.xpm000644 001751 001751 00000000765 10233071672 020754 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_select_S_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 3 1", /* colors */ " c blue", ". c #BBBBBBBBFFFF", "X c black", /* pixels */ " ", " .............. ", " .XX..XXXX..XX. ", " .X..........X. ", " .............. ", " .............. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .X..........X. ", " .............. ", " .............. ", " .X..........X. ", " .XX..XXXX..XX. ", " .............. ", " "}; tkgate-2.0-b10/images/net_probe.gif000644 001751 001751 00000000162 10235532401 017711 0ustar00hansenhansen000000 000000 GIF87aòÿÿÿÌÌÌÝÝÿ‹,?ÜÎj½ ™¸8AˆÍÚÖ} °‰^Pš§0ªà9\oÜÒ©=c5¶•=ÖêU(Ædï7Ì­2EgJ¥FªX‚";tkgate-2.0-b10/images/symed_fillrect_S.gif000644 001751 001751 00000000122 10233071772 021226 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿ,+„iÁí¾ždQØ‹)`¸ ÍyˆcP™º•*©®© ¿lHß“í<;tkgate-2.0-b10/images/symed_line_S.gif000644 001751 001751 00000000117 10233072000 020336 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿ,(„iÁí¾Ä›aI›½™mž}à$Ž@ag¦z(»vjù`t]½¦ôG;tkgate-2.0-b10/images/symed_point_S.gif000644 001751 001751 00000000135 10233072005 020545 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿ‹‹,6„iÂìž3¢Ú{W|DhBç=M@äwŠ«9Øl‰ðkKxzê] òqb4Z.:ö’Šæ¡;tkgate-2.0-b10/images/symed_port_S.gif000644 001751 001751 00000000123 10233072013 020374 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿÿ,,„iÁí¾žd±‰+^ C`uˆfc˜" 2jF:'ûtZ;ݹ´íA¿S;tkgate-2.0-b10/images/symed_rect_S.gif000644 001751 001751 00000000123 10233072020 020343 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿ,,„iÁí¾„œT†øž¸ ìÜlȈÝGšYr+«¢`Ì®cêÊY\õnÝP;tkgate-2.0-b10/images/symed_select_S.gif000644 001751 001751 00000000122 10233072024 020670 0ustar00hansenhansen000000 000000 GIF87añÿ»»ÿ,+„iÁí¾„`RÒßÃ@û°|O&rÁT‚ú™¬gŠP'7d«žhµÇµª ;tkgate-2.0-b10/images/net_probe.xpm000644 001751 001751 00000001030 10235532235 017750 0ustar00hansenhansen000000 000000 /* XPM */ static char * net_probe_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 6 1", /* colors */ " c white", ". c #cccccc", "X c #ddddff", "o c black", "O c #7f7f7f", "+ c #008b00", /* pixels */ " ............ ", " .............. ", "..XXXXXXXXXXooOO", "..XXXXXXXXXoooOO", "..XXXXXXXXooooOO", "..XXXXXXXooooXOO", "..XXXXXXooooXXOO", "..XXXXXooooXXXOO", "..XXXXXoooXXXXOO", "..XXXXooXXXXXXOO", "..XXXooXXXXXXXOO", "..++++o+++++++OO", "..XXooXXXXXXXXOO", "..XXXXXXXXXXXXOO", " .OOOOOOOOOOOOO ", " OOOOOOOOOOOO "}; tkgate-2.0-b10/images/net_probe2.xpm000644 001751 001751 00000001025 10235532333 020035 0ustar00hansenhansen000000 000000 /* XPM */ static char * net_probe2_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 6 1", /* colors */ " c white", ". c #cccccc", "X c #ddddff", "o c black", "O c #7f7f7f", "+ c red", /* pixels */ " ............ ", " .............. ", "..XXXXXXXXXXooOO", "..XXXXXXXXXoooOO", "..XXXXXXXXooooOO", "..XXXXXXXooooXOO", "..XXXXXXooooXXOO", "..XXXXXooooXXXOO", "..XXXXXoooXXXXOO", "..XXXoooXXXXXXOO", "..++++o+++++++OO", "..++++o+++++++OO", "..XXooXXXXXXXXOO", "..XXXXXXXXXXXXOO", " .OOOOOOOOOOOOO ", " OOOOOOOOOOOO "}; tkgate-2.0-b10/images/net_probe2.gif000644 001751 001751 00000000165 10235532365 020007 0ustar00hansenhansen000000 000000 GIF87aòÿÿÿÌÌÌÝÝÿÿ,BÜÎj½ ™¸8AˆÍÚÖ} °‰^Pš§0ªà9\oÜÒ©=cõug¯‚°0ƒÃ¢QØÛ¬\¹'°èX¯×vK$;tkgate-2.0-b10/images/Umuxord1.gif000644 001751 001751 00000000304 10241537416 017466 0ustar00hansenhansen000000 000000 GIF87a22ñ€€€F€,22„©Ëí£œ´Ú‹³Þ¼û†bP‘c)æ´‚môzñ3suskù²c}ò³CJQU(—̦ó . ‚Ô¤ ÀZ!ZmCIñ~b¶¼˜rèÃùºf;Þ’69=ÎÂç ;=bG•—H¦†7¸%Èç†(gæ8X%6)G©gˆ¹ÙÕ¸Èé x9jYº†©¸ÊÚêú +;K[k{‹›«+[;tkgate-2.0-b10/images/Umuxord2.gif000644 001751 001751 00000000304 10241537465 017473 0ustar00hansenhansen000000 000000 GIF87a22ñ€€€F€,22„©Ëí£œ´Ú‹³Þ¼û†bP‘c)æ´‚môzñ3suskù²c}ò³CJQU(—̦ó . ‚Ô¤ ÀZ!ZmÃQràÄôJ}€Ëf –}(Ããîôw1ÏÖõ x>¯ðvׇw&!F8¸EçàÅöˆ©F·ÆGÙ¶˜ÖÅhÉiçyU9ŠYº(¹¸ÊÚêú +;K[k{‹›«K[;tkgate-2.0-b10/images/Umuxsel1.gif000644 001751 001751 00000000211 10241537537 017466 0ustar00hansenhansen000000 000000 GIF87a22ñ€€€€F,22b„©Ëí£œ´Ú‹³Þ¼û†âH–扦ê´î ÇaÀÎ-â’nï&ÿ‚„¢ÇÈ@n” æ2â|?‚ªõêŒJ§§¨6“M)¿[™ƒ'½†v)ëJ^_í·!{©ë1šýfœs`úö1ÏƧwy//”W´¢WGHö—¨¸ÈØè¨X!9"IQr)‘ù± ÑÙñéº1ÊPšqªz±ŠÐ:iI KH[k{‹›«»ËkQ;tkgate-2.0-b10/images/Udemuxsel1.gif000644 001751 001751 00000000215 10241540146 017771 0ustar00hansenhansen000000 000000 GIF87a22ñ€€€€F,22f„©Ëí£œ´Ú‹³Þ¼û†âH–扦TÀ¶.«ŽŒÒŒ}â‰^ò‡O„ â°1n”&DJ•Î  ©^ªÚŠ¶+ù'à0¹·Ë2»ñŠË[ªºýŽÏë÷ü¾ÿ(8xW;tkgate-2.0-b10/images/Udemuxsel2.gif000644 001751 001751 00000000214 10241540164 017771 0ustar00hansenhansen000000 000000 GIF87a22ñ€€€€F,22e„©Ëí£œ´Ú‹³Þ¼û†âH–扦TÀ¶.«ŽÏ*@/yº'}ùCECá©h«ºhe~³œ(žÛ ïñ­"=Ñ4;tkgate-2.0-b10/images/bp_standby.xpm000644 001751 001751 00000000637 10241762002 020126 0ustar00hansenhansen000000 000000 /* XPM */ static char * bp_standby_xpm[] = { "16 16 3 1", " c blue", ". c red", "X c white", " .. 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", " .... ", " ...... ", " ........ ", ".........."}; tkgate-2.0-b10/images/up.gif000644 001751 001751 00000000076 11125530163 016366 0ustar00hansenhansen000000 000000 GIF89a ðÿÿÿ!ù,  „q›¹Øœ‰ÒV!þwhite;tkgate-2.0-b10/images/down.xpm000644 001751 001751 00000000224 10652753604 016756 0ustar00hansenhansen000000 000000 /* XPM */ static char * down_xpm[] = { "10 5 2 1", " c black", ". c white", " ", ". .", ".. ..", "... ...", ".... ...."}; tkgate-2.0-b10/images/down.gif000644 001751 001751 00000000074 11125530175 016712 0ustar00hansenhansen000000 000000 GIF89a ðÿÿÿ!ù,  „º lf!þwhite;tkgate-2.0-b10/images/symed_import.xpm000644 001751 001751 00000001043 10672114741 020515 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_import_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 7 1", /* colors */ " c magenta", ". c black", "X c #7e7e7e", "o c #d2b48c", "O c white", "+ c blue", "@ c red", /* pixels */ " ", " .. ", ".XX...... ", ".XXXXXXXX. ", ".XXXXXXXXX. ", ".XX.......... ", ".X.ooooooooo. ", ".X.ooo..........", "..oooo.OOOOOOOO.", ".......O++++OOO.", " .O+OOO+OO.", " @ .O+OOOO+O.", " @ @ .O+OOO+OO.", " @@@@ .O++++OOO.", " @ .OOOOOOOO.", " .........."}; tkgate-2.0-b10/images/symed_import.gif000644 001751 001751 00000000201 10672115035 020446 0ustar00hansenhansen000000 000000 GIF89aòÿÿ~~~Ò´Œÿÿÿÿÿ!ù,FºÜÁÉ ¼ÑÑÊkf[Ç}‡  lÛ~ê{În@Üø=CDá8Ò£‡"±x$“›q‰4X£½_pµå¶Ý%;tkgate-2.0-b10/images/symed_export.xpm000644 001751 001751 00000001043 10672114760 020525 0ustar00hansenhansen000000 000000 /* XPM */ static char * symed_export_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 7 1", /* colors */ " c black", ". c magenta", "X c white", "o c red", "O c blue", "+ c #7e7e7e", "@ c #d2b48c", /* pixels */ " ......", " XXXXXXXX .ooo..", " XOOOOXXX ...o..", " XOXXXOXX ..ooo.", " XOXXXXOX ...o..", " XOXXXOXX ......", " XOOOOXXX ......", " XXXXXXXX ......", " ....", "... ++++++++ ...", "... +++++++++ ..", "... ++ ", "... + @@@@@@@@@ ", "... + @@@@@@@@ .", "... @@@@@@@@@ .", "... .."}; tkgate-2.0-b10/images/symed_export.gif000644 001751 001751 00000000201 10672115052 020454 0ustar00hansenhansen000000 000000 GIF89aòÿÿÿÿÿÿÿ~~~Ò´Œ!ù,Fºþ@È)AØEÂɴΠ žT‚˜¸Qx%Y=Ù}ôHá9ã/9MaHº Åä10þ€B€aJ¥ºšÒª•¦ÐVÏF ;tkgate-2.0-b10/images/portcurs.b000644 001751 001751 00000001600 10674112500 017270 0ustar00hansenhansen000000 000000 #define portcurs_width 32 #define portcurs_height 32 static unsigned char portcurs_bits[] = { 0xff, 0x7f, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x80, 0x08, 0x00, 0x01, 0x80, 0x1c, 0x00, 0x01, 0x80, 0x3e, 0x00, 0x01, 0x80, 0x08, 0x00, 0x11, 0x80, 0x08, 0x00, 0x39, 0x80, 0x3e, 0x00, 0x7d, 0x80, 0x1c, 0x00, 0x11, 0x80, 0x08, 0x00, 0x11, 0x80, 0x00, 0x00, 0x7d, 0x80, 0x00, 0x00, 0x39, 0x80, 0x00, 0x00, 0x11, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0xfe, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x91, 0x00, 0x00, 0x89, 0x99, 0x01, 0x80, 0x99, 0xfd, 0x03, 0xc0, 0xbf, 0x99, 0x01, 0x80, 0x99, 0x91, 0x00, 0x00, 0x89, 0x01, 0x00, 0x00, 0x80, 0xff, 0x7f, 0xfe, 0xff, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80}; tkgate-2.0-b10/images/scroll_curs.b000644 001751 001751 00000001526 11121203573 017747 0ustar00hansenhansen000000 000000 #define scroll_curs_width 30 #define scroll_curs_height 30 static unsigned char scroll_curs_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01, 0x00, 0x00, 0xa8, 0x06, 0x00, 0x00, 0xa8, 0x0a, 0x00, 0x00, 0xac, 0x0a, 0x00, 0x00, 0xaa, 0x0a, 0x00, 0x00, 0x0a, 0x08, 0x00, 0x00, 0x0a, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x04, 0x04, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/scroll_curs.gif000644 001751 001751 00000000115 11121204450 020257 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,$„©ìkšdmÍ«žh»zp =ã ‘fƶn ­* §]Œ;tkgate-2.0-b10/images/bigrightarrow.b000644 001751 001751 00000000467 11126034472 020277 0ustar00hansenhansen000000 000000 #define bigrightarrow_width 16 #define bigrightarrow_height 16 static unsigned char bigrightarrow_bits[] = { 0x00, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x03, 0x80, 0x07, 0xfe, 0x0f, 0xfe, 0x1f, 0xfe, 0x3f, 0xfe, 0x7f, 0xfe, 0x3f, 0xfe, 0x1f, 0xfe, 0x0f, 0x80, 0x07, 0x80, 0x03, 0x80, 0x01, 0x80, 0x00}; tkgate-2.0-b10/images/bigleftarrow.b000644 001751 001751 00000000464 11126034517 020111 0ustar00hansenhansen000000 000000 #define bigleftarrow_width 16 #define bigleftarrow_height 16 static unsigned char bigleftarrow_bits[] = { 0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0xc0, 0x01, 0xe0, 0x01, 0xf0, 0x7f, 0xf8, 0x7f, 0xfc, 0x7f, 0xfe, 0x7f, 0xfc, 0x7f, 0xf8, 0x7f, 0xf0, 0x7f, 0xe0, 0x01, 0xc0, 0x01, 0x80, 0x01, 0x00, 0x01}; tkgate-2.0-b10/images/bigleftarrow.gif000644 001751 001751 00000000113 11126034573 020426 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,"„©»Ñ‚QZÞpòÍ|à%ŽdÙ…h‚ff©q83K;tkgate-2.0-b10/images/bigrightarrow.gif000644 001751 001751 00000000112 11126034605 020604 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,!„©ëÑ\‚Q2ª¨Ös{ä…G(ä6ž¨Z&æÂq;;tkgate-2.0-b10/images/allrightarrow.b000644 001751 001751 00000000467 11126212545 020305 0ustar00hansenhansen000000 000000 #define allrightarrow_width 16 #define allrightarrow_height 16 static unsigned char allrightarrow_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x03, 0x38, 0x07, 0x70, 0x0e, 0xe0, 0x1c, 0xc0, 0x39, 0xe0, 0x1c, 0x70, 0x0e, 0x38, 0x07, 0x9c, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/allleftarrow.b000644 001751 001751 00000000464 11126212574 020121 0ustar00hansenhansen000000 000000 #define allleftarrow_width 16 #define allleftarrow_height 16 static unsigned char allleftarrow_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x39, 0xe0, 0x1c, 0x70, 0x0e, 0x38, 0x07, 0x9c, 0x03, 0x38, 0x07, 0x70, 0x0e, 0xe0, 0x1c, 0xc0, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; tkgate-2.0-b10/images/allleftarrow.gif000644 001751 001751 00000000110 11126212660 020425 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,„©Ëí‚42¬J§Â€'îEZøÚeZ xn)ÇO;tkgate-2.0-b10/images/allrightarrow.gif000644 001751 001751 00000000110 11126212700 020603 0ustar00hansenhansen000000 000000 GIF89aðÿÿÿ!ù,„©Ëí¢‰¡Ñ)Ù{í®|Y"Va¥‡ŽÏ Ç@;tkgate-2.0-b10/images/Uoffswitch.gif000644 001751 001751 00000000332 11132375142 020060 0ustar00hansenhansen000000 000000 GIF87a22ð€€€€,22¹Œ©Ëí£œ´Ú‹³Þ¼û†âH–f¤êʶnKcïjÑ“,7}üCÙA‰Î8ôåŠqYsö¤‡£jq2SC7ÉÝ*ÅÞròŽ>ÏffBí:½?t•Œ^m4<ãݤ§så‡UÈÅVeöWÇs¨h‡–Ô¨–øµ§ùXæ8Õצ(ÊgI fJWʲ8‰¨ºséZøD™ uSÛÄyùÁ˸;< D|ìr¢¼ÌÜìü -=M]mýQ;tkgate-2.0-b10/images/Uonswitch.gif000644 001751 001751 00000000333 11132375310 017720 0ustar00hansenhansen000000 000000 GIF87a22ð€€€€,22ºŒ©Ëí£œ´Ú‹³Þ¼û†âH–f¤êʶnKcïjÑ“,ºÑ‹Q6įX9Bx@07\"‡½(Êê`ªšÌ¦OéÝMϱوmt©åj[ΞÍîyX¢Õmƒ¿:ºÆ£G“–E¸ 5Ö%(§ÆȨöEæ3)fXW%¨É¸V”Yjc‡ÄZ–'‰i™jºzjz)›Dšx“ ×+ {ÈK\,TŒìr²ÌÜìü -=M]m}ýQ;tkgate-2.0-b10/images/onswitch.gif000644 001751 001751 00000000333 11132374667 017611 0ustar00hansenhansen000000 000000 GIF87a22ðÿÿÿÿ,22ºŒ©Ëí£œ´Ú‹³Þ¼û†âH–f¤êʶnKcïjÑ“,ºÑ‹Q6įX9Bx@07\"‡½(Êê`ªšÌ¦OéÝMϱوmt©åj[ΞÍîyX¢Õmƒ¿:ºÆ£G“–E¸ 5Ö%(§ÆȨöEæ3)fXW%¨É¸V”Yjc‡ÄZ–'‰i™jºzjz)›Dšx“ ×+ {ÈK\,TŒìr²ÌÜìü -=M]m}ýQ;tkgate-2.0-b10/images/offswitch.gif000644 001751 001751 00000000332 11132374727 017743 0ustar00hansenhansen000000 000000 GIF87a22ðÿÿÿÿ,22¹Œ©Ëí£œ´Ú‹³Þ¼û†âH–f¤êʶnKcïjÑ“,7}üCÙA‰Î8ôåŠqYsö¤‡£jq2SC7ÉÝ*ÅÞròŽ>ÏffBí:½?t•Œ^m4<ãݤ§så‡UÈÅVeöWÇs¨h‡–Ô¨–øµ§ùXæ8Õצ(ÊgI fJWʲ8‰¨ºséZøD™ uSÛÄyùÁ˸;< D|ìr¢¼ÌÜìü -=M]mýQ;tkgate-2.0-b10/images/setdip.gif000644 001751 001751 00000000315 11132376536 017240 0ustar00hansenhansen000000 000000 GIF87aKðÿÿÿÿ,K¬Œ©Ëí´Ú‹³Þ×ð†âä‡)ãÊf¥ ÃݙҦø^Þý‹ŠuR$¢Qu,¢’Ì%òF”õ(¹Ú÷¬ú²XÕ9\‚›È¬qŒ.{Ejò¹~ËÅÓöÞµr¯|îߧ¨'¸çÇ6gF—¨¤è¸v9GÉ趈y(¥D•·UJ(úYuÚ˜zù¸ªzºyJ: h(‹÷¥Ø²ËRÇûûë <¼a|Œœ¬P;tkgate-2.0-b10/images/file_unlib.xpm000644 001751 001751 00000001054 11134415366 020115 0ustar00hansenhansen000000 000000 /* XPM */ static char * file_unlib_xpm[] = { /* width height num_colors chars_per_pixel */ "16 16 7 1", /* colors */ " s None c None", ". c #dd6666", "X c #cccccc", "o c #999999", "O c #882222", "+ c red", "@ c #aa2222", /* pixels */ " .XoX. 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tkgate-2.0-b10/images/jkff.gif000644 001751 001751 00000000374 11135250420 016657 0ustar00hansenhansen000000 000000 GIF89a22ñÿÿÿ‹ÿ!ù,22Í„©ËíB“°Vº°Ýyò¯h‰räq–—§‚)ð¶l'›s½2q)ôþ }<\BPTüDeÒh@‚¤Ç^£y|"¤Ô,S{À:¿SÀÒüèš¹OªZiE£ß·ŠMGöü=ò·fÖ×—%C”guXÆ(÷¡èÈ(yõÉaY—†³¹˜©É6AÈz(pºg—$9h¥šU:uëYƒ»e¡úV7JF»h<†| ì0Üxì,½1d}}†‰¢]²ÃMó½áA.nn1ŽnT;tkgate-2.0-b10/images/jkff.xpm000644 001751 001751 00000005464 11135250402 016723 0ustar00hansenhansen000000 000000 /* XPM */ static char * jkff_xpm[] = { /* width height num_colors chars_per_pixel */ "50 50 3 1", /* colors */ " c white", ". c #008b00", "X c #0000ff", /* pixels */ " ", " . . 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An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is a NAND gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NOR gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive OR { delay = { if ((inv(I) == num(I))) // Determine if an inverter is necessary. An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is an NOR gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NAND gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive XOR { delay = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = 1; if (num(I) == 1) { return 3*bits(I0) + 2*d; } else { return 3*num(I) + 2*d; } } area = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = inv(I); if (num(I) == 1) { return bits(Z)*(3*bits(I0) + 2*d); } else { return bits(Z)*(3*num(I) + 2*d); } } } primitive BUF { delay = 2 + 2*(inv(I) == inv(Z)); area = bits(Z)*(2 + 2*(inv(I) == inv(Z))); } primitive BUFIF { delay = 4; delay = 4 + 2*(inv(I) == inv(Z)); area = bits(Z)*(4 + 2*(inv(I) == inv(Z))); } primitive NMOS { delay = 2; delay = 1; area = bits(Z); } primitive PMOS { delay = 2; delay = 1; area = bits(Z); } primitive ADD { delay = 12 + (bits(S)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(S); delay = 6 + bits(S)*8 + 2*(inv(A) || inv(B)) + 2*inv(CO); delay = 6 + (bits(S)-1)*8 + 2*inv(CI) + 2*inv(S); delay = bits(S)*8 + 2*inv(CI) + 2*inv(CO); area=24*bits(S); } primitive REG { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive FF { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive JKFF { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive MUX { delay = (2*(num(S)+1) + 2*num(I)) + 2*(inv(I) || inv(Z)); delay = (2*(num(S)+1) + 2*num(I)); area = bits(Z)*((2*(num(S)+1) + 2*num(I)) + 2*inv(I)); } primitive DEMUX { delay = 2*(num(I)+1) + 2*(!inv(Z)); delay = 2*(num(I)+1) + 2*(!inv(Z)); area = 2*(num(I)+1)*(2**num(I)) + 2*num(I); } primitive DECODER { delay = 2*(num(I)+1) + 2*(!inv(Z)); delay = 2*(num(I)+1) + 2*(!inv(Z)); area = 2*(num(I)+1)*(2**num(I)) + 2*num(I); } primitive MUL { delay = 12 + 2*(bits(P)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(P); area=bits(A)*bits(B)*30; } primitive DIV { delay = 12 + 4*(bits(Q)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(Q); delay = 12 + 4*(bits(R)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(R); area=bits(A)*bits(B)*30; } primitive RAM { delay = 10; delay = 60; delay = 70; delay = 10; delay = 10; delay = 10; area=0; // Do not include RAMs in area estimate } primitive ROM { delay = 10; delay = 30; area=0; // Do not include ROMs in area estimate } primitive TTY { delay = 150; delay = 2; delay = 8; delay = 150; delay = 2; delay = 2; area=0; // Do not include TTYs in area estimate }; primitive LSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive RSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive ARSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive ROLL { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } } /* * Just use delay of 1 for everything */ technology unit { primitive AND { delay<*> = 1; area = 1; } primitive OR { delay<*> = 1; area = 1; } primitive XOR { delay<*> = 1; area = 1; } primitive BUF { delay<*> = 1; area = 1; } primitive BUFIF { delay<*> = 1; area = 1; } primitive NMOS { delay<*> = 1; area = 1; } primitive PMOS { delay<*> = 1; area = 1; } primitive ADD { delay<*> = 1; area = 1; } primitive REG { delay<*> = 1; area = 1; } primitive FF { delay<*> = 1; area = 1; } primitive MUX { delay<*> = 1; area = 1; } primitive DEMUX { delay<*> = 1; delay<*> = 1; area = 1; } primitive MUL { delay<*> = 1; area = 1; } primitive DIV { delay<*> = 1; area = 1; } primitive RAM { delay<*> = 1; area=1; } primitive ROM { delay<*> = 1; area=1; } primitive TTY { delay<*> = 1; area=1; }; primitive LSHIFT { delay<*> = 1; area = 1; } primitive RSHIFT { delay<*> = 1; area = 1; } primitive ARSHIFT { delay<*> = 1; area = 1; } primitive ROLL { delay<*> = 1; area = 1; } } tkgate-2.0-b10/gdf/pat.gdf000644 001751 001751 00000026635 10000074514 016017 0ustar00hansenhansen000000 000000 /**************************************************************************** Copyright (C) 1987-2000 by Jeffery P. Hansen This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Last edit by hansen on Wed Sep 20 09:55:09 2000 ****************************************************************************/ /* * WARNING: The delay specifications in this file are preliminary and have * not been well tested. Feel free to send me more realistic delay data * if you have any. */ version 1.5 technology pat { primitive and { delay = { if ((inv(I) == num(I))) // Determine if an inverter is necessary. An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is a NAND gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NOR gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive or { delay = { if ((inv(I) == num(I))) // Determine if an inverter is necessary. An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is an NOR gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NAND gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive xor { delay = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = 1; if (num(I) == 1) { return 3*bits(I0) + 2*d; } else { return 3*num(I) + 2*d; } } area = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = inv(I); if (num(I) == 1) { return bits(Z)*(3*bits(I0) + 2*d); } else { return bits(Z)*(3*num(I) + 2*d); } } } primitive buf { delay = 2 + 2*(inv(I) == inv(Z)); area = bits(Z)*(2 + 2*(inv(I) == inv(Z))); } primitive bufif1 { delay = 4; delay = 4 + 2*(inv(I) == inv(Z)); area = bits(Z)*(4 + 2*(inv(I) == inv(Z))); } primitive nmos { delay = 2; delay = 1; area = bits(Z); } primitive pmos { delay = 2; delay = 1; area = bits(Z); } primitive add { delay = 12 + (bits(S)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(S); delay = 6 + bits(S)*8 + 2*(inv(A) || inv(B)) + 2*inv(CO); delay = 6 + (bits(S)-1)*8 + 2*inv(CI) + 2*inv(S); delay = bits(S)*8 + 2*inv(CI) + 2*inv(CO); area=24*bits(S); } primitive register { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive ff { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive mux { delay = (2*(num(S)+1) + 2*num(I)) + 2*(inv(I) || inv(Z)); delay = (2*(num(S)+1) + 2*num(I)); area = bits(Z)*((2*(num(S)+1) + 2*num(I)) + 2*inv(I)); } primitive demux { delay = 2*(num(I)+1) + 2*(!inv(Z)); delay = 2*(num(I)+1) + 2*(!inv(Z)); area = 2*(num(I)+1)*(2**num(I)) + 2*num(I); } primitive mult { delay = 12 + 2*(bits(P)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(P); area=bits(A)*bits(B)*30; } primitive div { delay = 12 + 4*(bits(Q)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(Q); delay = 12 + 4*(bits(R)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(R); area=bits(A)*bits(B)*30; } primitive ram { delay = 10; delay = 10; delay = 70; delay = 10; delay = 10; delay = 10; delay = 10; area=0; // Do not include RAMs in area estimate } primitive rom { delay = 10; delay = 50; area=0; // Do not include ROMs in area estimate } primitive tty { delay = 150; delay = 2; delay = 8; delay = 150; delay = 2; delay = 2; area=0; // Do not include TTYs in area estimate }; primitive lshift { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive rshift { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive arshift { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive roll { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } } /* * Just use delay of 1 for everything */ technology unit { primitive and { delay<*> = 1; area = 1; } primitive or { delay<*> = 1; area = 1; } primitive xor { delay<*> = 1; area = 1; } primitive buf { delay = 1; area = 1; } primitive bufif1 { delay = 1; delay = 1; area = 1; } primitive nmos { delay = 1; delay = 1; area = 1; } primitive pmos { delay = 1; delay = 1; area = 1; } primitive add { delay = 1; delay = 1; delay = 1; delay = 1; area = 1; } primitive register { delay = 1; delay = 1; delay = 1; area = 1; } primitive ff { delay = 1; delay = 1; delay = 1; area = 1; } primitive mux { delay = 1; delay = 1; area = 1; } primitive demux { delay = 1; delay = 1; area = 1; } primitive mult { delay = 1; area = 1; } primitive div { delay = 1; delay = 1; area = 1; } primitive ram { delay = 1; delay = 1; delay = 1; delay = 1; delay = 1; delay = 1; delay = 1; area=1; } primitive rom { delay = 1; delay = 1; area=1; } primitive tty { delay = 1; delay = 1; delay = 1; delay = 1; delay = 1; delay = 1; area=1; }; primitive lshift { delay = 1; delay = 1; area = 1; } primitive rshift { delay = 1; delay = 1; area = 1; } primitive arshift { delay = 1; delay = 1; area = 1; } primitive roll { delay = 1; delay = 1; area = 1; } } tkgate-2.0-b10/gdf/default.gdf~000644 001751 001751 00000026023 11140707200 017045 0ustar00hansenhansen000000 000000 /**************************************************************************** Copyright (C) 1987-2000 by Jeffery P. Hansen This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. Last edit by hansen on Fri Jan 30 18:34:24 2009 ****************************************************************************/ /* * WARNING: The delay specifications in this file are preliminary and have * not been well tested. Feel free to send me more realistic delay data * if you have any. */ version 1.5 technology default { primitive AND { delay = { if ((inv(I) == num(I))) // Determine if an inverter is necessary. An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is a NAND gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NOR gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive OR { delay = { if ((inv(I) == num(I))) // Determine if an inverter is necessary. An d = inv(Z); // inverter is not required if the output is else if ((inv(I) == 0)) // inverting and all inputs are non-inverting d = !inv(Z); // (i.e., it is an NOR gate), or if all inputs else // are inverting and the output is non-inverting d = 1; // (i.e., it is a NAND gate). if (num(I) == 1) { // If one input, treat this as a reduction gate return 2*bits(I0) + 2*d; // one Tr. delay per bit plus inverter delay. } else { // If multiple inputs, treat this as a normal gate return 2*num(I) + 2*d; // one Tr. delay per input plus inverter delay. } } area = { if ((inv(I) == num(I))) // Estimate number of inverters required. If all d = inv(Z); // inputs are inverted, an inverter is required else if ((inv(I) == 0)) // iff the output is inverted. If all inputs d = !inv(Z); // are non-inverted, an inverter is required iff else // the output is non-inverted. Otherwise we need d = inv(I); // an inverter for each inverted input. if (num(I) == 1) { // If one input, treat this as a reduction gate a = 2*bits(I0) + 2*d; // one Tr. per bit plus inverter Trs. } else { // If multiple inputs, treat this as a normal gate a = 2*num(I) + 2*d; // one Tr. per input plus inverter Trs. } return bits(Z)*a; // Multiply by number of bit slices. } } primitive XOR { delay = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = 1; if (num(I) == 1) { return 3*bits(I0) + 2*d; } else { return 3*num(I) + 2*d; } } area = { if ((inv(I) == num(I))) d = inv(Z); else if ((inv(I) == 0)) d = !inv(Z); else d = inv(I); if (num(I) == 1) { return bits(Z)*(3*bits(I0) + 2*d); } else { return bits(Z)*(3*num(I) + 2*d); } } } primitive BUF { delay = 2 + 2*(inv(I) == inv(Z)); area = bits(Z)*(2 + 2*(inv(I) == inv(Z))); } primitive BUFIF { delay = 4; delay = 4 + 2*(inv(I) == inv(Z)); area = bits(Z)*(4 + 2*(inv(I) == inv(Z))); } primitive NMOS { delay = 2; delay = 1; area = bits(Z); } primitive PMOS { delay = 2; delay = 1; area = bits(Z); } primitive ADD { delay = 12 + (bits(S)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(S); delay = 6 + bits(S)*8 + 2*(inv(A) || inv(B)) + 2*inv(CO); delay = 6 + (bits(S)-1)*8 + 2*inv(CI) + 2*inv(S); delay = bits(S)*8 + 2*inv(CI) + 2*inv(CO); area=24*bits(S); } primitive REG { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive FF { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive JKFF { delay = 10; delay = 10; delay = 20; area=16*bits(Q); } primitive MUX { delay = (2*(num(S)+1) + 2*num(I)) + 2*(inv(I) || inv(Z)); delay = (2*(num(S)+1) + 2*num(I)); area = bits(Z)*((2*(num(S)+1) + 2*num(I)) + 2*inv(I)); } primitive DEMUX { delay = 2*(num(I)+1) + 2*(!inv(Z)); delay = 2*(num(I)+1) + 2*(!inv(Z)); area = 2*(num(I)+1)*(2**num(I)) + 2*num(I); } primitive DECODER { delay = 2*(num(I)+1) + 2*(!inv(Z)); delay = 2*(num(I)+1) + 2*(!inv(Z)); area = 2*(num(I)+1)*(2**num(I)) + 2*num(I); } primitive MUL { delay = 12 + 2*(bits(P)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(P); area=bits(A)*bits(B)*30; } primitive DIV { delay = 12 + 4*(bits(Q)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(Q); delay = 12 + 4*(bits(R)-1)*8 + 2*(inv(A) || inv(B)) + 2*inv(R); area=bits(A)*bits(B)*30; } primitive RAM { delay = 10; delay = 30; delay = 40; delay = 10; delay = 10; delay = 10; area=0; // Do not include RAMs in area estimate } primitive ROM { delay = 10; delay = 30; area=0; // Do not include ROMs in area estimate } primitive TTY { delay = 150; delay = 2; delay = 8; delay = 150; delay = 2; delay = 2; area=0; // Do not include TTYs in area estimate }; primitive LSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive RSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive ARSHIFT { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } primitive ROLL { delay = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return 4 + 4*log(bits(S)) + d; } delay = { if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 0; return 4 + 4*log(bits(S)) + 4*inv(S); } area = { if ((inv(I) == num(I))) d = 2*inv(Z); else if ((inv(I) == 0)) d = 2 - 2*inv(Z); else d = 2; return bits(Z)*(4 + 4*bits(S) + d); } } } /* * Just use delay of 1 for everything */ technology unit { primitive AND { delay<*> = 1; area = 1; } primitive OR { delay<*> = 1; area = 1; } primitive XOR { delay<*> = 1; area = 1; } primitive BUF { delay<*> = 1; area = 1; } primitive BUFIF { delay<*> = 1; area = 1; } primitive NMOS { delay<*> = 1; area = 1; } primitive PMOS { delay<*> = 1; area = 1; } primitive ADD { delay<*> = 1; area = 1; } primitive REG { delay<*> = 1; area = 1; } primitive FF { delay<*> = 1; area = 1; } primitive MUX { delay<*> = 1; area = 1; } primitive DEMUX { delay<*> = 1; delay<*> = 1; area = 1; } primitive MUL { delay<*> = 1; area = 1; } primitive DIV { delay<*> = 1; area = 1; } primitive RAM { delay<*> = 1; area=1; } primitive ROM { delay<*> = 1; area=1; } primitive TTY { delay<*> = 1; area=1; }; primitive LSHIFT { delay<*> = 1; area = 1; } primitive RSHIFT { delay<*> = 1; area = 1; } primitive ARSHIFT { delay<*> = 1; area = 1; } primitive ROLL { delay<*> = 1; area = 1; } } tkgate-2.0-b10/doc/fig000777 001751 001751 00000000000 10653513427 015253 5ustar00hansenhansen000000 000000 tkgate-2.0-b10/doc/adding_gate_types.txt000644 001751 001751 00000006110 07311226663 020772 0ustar00hansenhansen000000 000000 This file contains a crude explaination of how to add new primitive gate types to tkgate. It will be made more useful in the future if there is demand for it. In order to add new primitive circuit elements to tkgate, you will need to write a .c file for the editor (in src/tkgate) and for the simulator (in src/gsim). You can look at and.c for the AND gate, and register.c for the register. You will need to create a bitmap file with the symbol for you gate in each of the four rotations in both bold and non-bold. For most gates, all eight icons are in one bitmap file. Look at bitmaps/and.b for an example (if you have the 'bitmap' program, this will allow you to view and edit these files). You then need to create tables for describing the bitmap, the positions of wires, and properties of the circuit element. For example: static iconDimensions and_iconDims[] = { {0, 0, 20, 15, 10, 7}, ... }; Defines the icons to use for each of the four rotations (numbered counter clockwise). This says that in rotation 0, the offset for the AND gate icon has an offset of (0,0) (from upper left), the icon is 20 pixels wide and 15 high, and the center point is 10 pixels from the left side of the icon and 7 from the top. There is also a BoldOffset value which is the y offset to add to the icon offset to get the bold versions of the icons. The "locate" data structures define the position of "pads" and the direction of wires connected to those pads in the standard rotation (rotation 0). A "pad" is specified by two (x,y) values defining a line along which ports for that pad will be placed. Most gates, such as registers allow only one port per pad and the two end points are the same. For AND gates which can have multiple inputs, the endpoints are the coordinates of the two left-hand corners of the gate. You will also have to write a block of postscript code to be able to print circuits with your circuit element. This is what the psAnd declaration in the AND gate definition is doing. The next step is to create the gate info block for your type. This includes pointers to the icon and wire position structures, properties of the gates and function pointers to functions for operating on the gate. For most of these functions you can use the "Generic" functions just as the AND gate does. The last step is to create an init_youtype() function which calls the appropriate registration functions (again you can copy the AND gate example if there is nothing too unusual about the gate). Add a call to the init_ function to the function MakeHashTables() in src/tkgate/functions.c and you are done with the editor-side definition. For the simulator side definition is similar in that you create also create an initialized data structure and define an init_ fuction, but the data is slightly different. The most important function for the simulator is the yourtype_processEvent() function. This is called whenever an input signal on the gate changes values and is responsible for scheduling a change on an output port. It can also read/write state information on the gate or send special internal events to itself. tkgate-2.0-b10/doc/gateEdit.html000644 001751 001751 00000156020 10652372464 017204 0ustar00hansenhansen000000 000000 TKGate User Documentation (Editor)

2. Using the Editor

This chapter will introduce the basic concepts needed to create a graphical circuit in TkGate.

2.1 Understanding the TKGate Interface


(click to enlarge)

Figure 2.1: TkGate Main Window
The main components of the TKGate edit window consists of a menu bar and tool bar at the top, the module, net and port lists on the left, a status bar on the bottom, and the main editing area in the center. The main edit window contains major mode tabs to switch between "Edit" mode for editing your circuit, "Interface" mode for editing the interface of any modules you define, and "Simulate" mode for simulating your circuit. Scroll bars can be used to scroll the circuit, the list of modules or the list of nets. 

2.1.1 Main Menu

The TkGate menu bar appears at the top edge of the main window and is arranged by category. The menus that are available can change when you enter different modes (e.g., editing versus simulation).

2.1.2 Pop-up Menus

Many of the features described in this manual can also be accessed using the context sensitive pop-up menus. The pop-up menus are obtained by pressing the right mouse button, and the menu items that appear depend on what was selected. The menu that appears, depends on where you clicked and what the current mode is.

2.1.3 Toolbar

Frequently used commands can be accessed through the TkGate toolbar. These include commands for opening, saving and printing circuit files, changing the editing tool, opening and closing modules and controlling the simulator. The toolbars that are displayed change dynamically with mode. You can also configure which toolbars you want to use on the Toolbars tab of the Options dialog box. A complete list of the toolbar buttons are given in the List of Toolbar Buttons.

2.1.4 Keyboard Shortcuts

Many of the commands that can be accessed through the menu or toolbar can also be accessed through keyboard shortcuts. Commands for creating gates are typical single character letters. When possible, the letter is the first character of that gate type (e.g., "a" to create an "AND" gate and "r" to create a "register"). By default, file handling commands use Emacs-style shortcuts (e.g., "ctrl-c ctrl-s" to save, "ctrl-x ctrl-f" to load a file, etc.) If you prefer, you can choose to use Windows style shortcuts through the Interface tab on the options dialog box.

2.1.5 Module List and Module Hierarchy

The modules defined in the current circuit can be shown as in an alphabetical list view (press to select), or in a hierarchy view (press to select). The list view simply displays all of the modules in alphabetical order. The hierarchy view displays the module hierarchy starting at the top-level module. Under each module is the list of modules used by that module. There may also be additional hierarchies with the loaded library parts and any unused modules. Modules and the module hierarchy are described in greater detail in Section 3.3 Module Hierarchy.

2.1.6 Net and Port Lists

Below the module list in the lower-left corner of the main window is the list of nets or ports in the current module. A symbol precedes each net name depending on the type and whether the net is 1-bit or multi-bit as shown in the table below:

1-Bit
Symbol		Multi-Bit
Symbol		Description
Wire with a hidden name.
Wire with a visible name.
Register variable (HDL modules only).
Wire with a probe attached to it (in simulation mode).
Module input port.
Module output port.
Module bidirectional port.

The "Ports" list can be used to list the modules nets that are defined as part of the interface for the current module. These are nets that the user is expected to define in the module definition.

2.1.7 Status Bar



Figure 2.2: Status Bar
The status bar on the bottom indicates the file that is being edited, and the current module from that file that is displayed in the circuit window.  A "*" after the file name indicates that the buffer has been modified since the last time the file was saved.  Below the file and module name is a message bar for informational messages from TKGate.  These messages include confirmation for files that are loaded or saved, or information on the currently selected gate or wire.

2.1.8 Major Mode Tabs



Figure 2.3: Major Mode Tabs
The main edit window has three tabs to indicate and select the major mode in TkGate. "Edit" mode is used for creating and editing your circuit. The majority of your time using TkGate is likely to be in this mode. The "Interface" tab is used to design the interface for any modules that you define. You can also use this mode to view the interface of a module without creating a module of that type. The "Simulate" tab is used to perform simulations. When you press this tab, TkGate will send your circuit to the simulator, check for errors, and if your circuit is error free, start the simulator. By default, the simulator will be "paused" and you will need to press the button.

The icon in the upper right corner of the interface can also help show you what mode you are in. The possible icons are:

SymbolDescription
Edit/Interface Mode - The TkGate logo is shown when TkGate is in the "Edit" or "Interface" modes.
Paused Simulation - A stopped AND dragon shows that TkGate is simulation mode, and the simulation is paused.
Running Simulation - A running AND dragon shows that TkGate is in simulation mode, and the simulation is running.

2.1.9 Balloon Help



Figure 2.4: Balloon Help
Balloon help is available for many of the elements in the interface, typically on the prompt text. To use balloon help, simply move the mouse cursor over an interface element. After about one second, an informational help message will be displayed as long as the mouse cursor has not moved. For example, moving the mouse cursor over the "Nets" label on the main window produces a balloon help message as shown below: Balloon help is also available in most of the dialog boxes.  Position the cursor over the text in a dialog box to view a more detailed description.

2.2 Loading and Saving Circuits



Figure 2.5: Open File Dialog Box
Opening and saving circuits as well as circuit printing operations are done through the "File" menu option on the main window.  To load a file into TKGate, you can either specify the file name on the command line when you start, select "Open..." from the "File" menu or use the button on the toolbar. You can also use the keyboard shortcut Ctl-X Ctl-F. When opening a new file, all existing modules will be flushed from the buffer, and the modules in the new file will be loaded. TkGate save files have the extension ".v" and are in a special annotated Verilog format. Files saved from TkGate contain special comments with information such as circuit elements and wire positions. Also, gates with no explicit counter part in Verilog such as switches and clock generators are saved as annotation comments in the save file.

You can also load non-TkGate generated Verilog files. These files will load as a set of HDL modules. When saving from a file that was loaded as a non-TkGate Verilog file, the saved file will contain TkGate annotations.

When you open or save a circuit, you will see a dialog box such as the one shown in the figure on the right. Enter a file name at the prompt and press the "Open" (or "Save") button, or double click on a file name.  Only the appropriate type of files will be displayed.  You can change directories by double clicking on a folder to open it, or by using the button in the upper right corner to move up to the parent folder.

2.3 Loading Libraries


(Click to enlarge)

Figure 2.6: Library Manager
Libraries are loaded and unloaded through the "Library Manager". Select "Library Manager" from the "File" menu or select from the toolbar. This will open the library manager as shown below: To load a library, select it and press the "Load" button. To unload a library, select it and press the "Unload" button. When you have finished selecting which libraries you wish to have loaded, close the dialog box by pressing "OK". If you press "Cancel", all of your changes to the set of loaded libraries will be ignored.

The set of libraries that are displayed in the library are found by searching the TkGate library path. The library path can be set through the library options dialog and can include user-defined libraries.

When you save your design after loading libraries, TkGate will store the names of libraries you have loaded in the save file. Then when you load your design again, TkGate will automatically load the necessary libraries.

2.4 Basic Editing Tools

The basic editing tools are selected through the "Mode" toolbar. While a mode is active, the mouse cursor will change to reflect the active mode. The available editing tools are shown in the table below.

Button Cursor Shortcut Description

F1 The Move/Connect tool is indicated by the arrow cursor.  Use this tool for most editing operations including creating gates, connecting wires, moving gates and wires, opening module instances, opening property boxes of gates and wires, and deleting circuit elements (with the "delete" key).

(F1) The Connect tool is indicated by the soldering iron cursor.  To use this tool, first select the move/connect tool and then press and hold the left mouse button on a wire endpoint.  The cursor will then change to the connect tool as long as you are holding down the mouse button.

F2 The Wire Cutter tool is indicated by the wire cutter cursor.  Use this tool to cut wires by clicking on the wire at the point you want to cut it.  If you cut a wire with an unconnected end, the wire segments between the cut point and the unconnected end will be deleted automatically.

F3 The Inverter tool is indicated by the inverter bubble grabber cursors.  Use this tool to add or remove inverter bubbles on the inputs and outputs of gates.  Click the cursor near an input or output to converter a non-inverting port to an inverting port or vice-versa.

F4 The Wire Size/Type tool is indicated by the ribbon cable cursor. Use this mode to change the bit width of a wire or the type of wire. The desired bit width and wire type should be selected in the selector boxes next to the button on the Mode toolbar. Any wires that are clicked on will have their size and type changed to the selected size/type. The wire type affects how the wire's value will be set when multiple gates drive a wire. You can also change wire bit widths and types using the Wire Properties dialog box.

2.4.1 Creating Gates

There are three main ways to create gates in TkGate: using the menu bar, using pop-up menus, and using keyboard shortcuts. Once you have mastered the keyboard shortcuts, that is generally the preferred way to create gates. These three methods are described in the following sections.
Creating a Gate Using the Menu Bar

1) Left click to select the point.

2) Select gate type from menu bar.

3) Gate is created at location set by point.
Figure 2.7: Creating a Gate
1) To create a gate such as a NAND gate, first select the Move/Connect tool , and then press the left mouse button at the position you wish to create it. While you are holding the mouse button down, the cursor will change to an outline arrow to indicate the current orientation. In the case shown at the left, the current orientation is 0 degrees indicating the standard orientation.

When you release the button the arrow will disappear and the mark symbol will remain. The mark indicates the center point for the new circuit element. Clicking the left mouse button at another location will move the mark, and selecting a gate or wire will clear the mark.

2) Select the gate type by opening the "Make" menu. The circuit elements are organized into seven basic categories:

  • "I/O" types include switches, dip switches, power sources, clocks, etc.
  • "Gate" types include the basic logic gates such as AND and OR gates.
  • "Reduction" types include reduction versions of the basic gates types which combine multi-bit signals into a single bit
  • "MSI/LSI" types include MUXES, DEMUXES, etc.
  • "ALU" types include adders, multiplier, shifters, etc.
  • "Memory" types include registers, RAMs, ROMs, etc.
  • "Module" types include module blocks and ports.
There are also two additional non-circuit element objects that can be created. A "Comment" is an arbitrary block of text that can be used to add documentation to your circuit, and a "Frame" is a labeled box that you can place around a portion of your circuit.

3) After selecting the menu option or typing the shortcut, the circuit element will be created and displayed in bold to indicate that it is selected. While the gate is still selected, you can press the toolbar button or press the Tab key to rotate the gate to the desired orientation.

Creating a Gate Using the Pop-up Menu


Right click to use pop-up menus to create a gate.
Figure 2.8: Creating a Gate with Pop-up Menu
To create a gate using the pop-up menu, right click on the position at which you wish to create a gate. This will both create the position mark and bring up the pop-up menu. Then select "Make", and then maneuver through the gate category to select the appropriate gate type.
Creating a Gate Using Keyboard Shortcuts

To create a gate using keyboard shortcuts, first set a mark in the same way as when creating a gate using the menu bar (Section 2.5.1). Then simply type the shortcut for the gate you wish to create. Most of the gate types have single character commands to create them. For example, you can type "a" to create an AND gate, and "A" to create a NAND gate. A list of the gate types and their keyboard shortcuts are shown in Section 2.16.

2.4.2 Connecting Wires

Port-to-Port Connections

Step 1: select endpoint
Step 2: drag wire end

Step 3: bring wire end
close to other terminal
Step 4: release and connect

Figure 2.9: Port-to-Port Connections
Port-to-port connections are used to connect the end points of two wires. Before making the connections, make sure you have selected the "Move/Connect" tool from the "Tool" menu. Then, click and hold the left mouse button on the endpoint of one of the ends you wish to connect. The mouse cursor will change to a soldering iron to indicate that connect mode is active as shown in Step 1.

Next, drag the mouse toward the other endpoint you wish to connect to as shown in Step 2, TKGate will automatically introduce any necessary bends and maintain connections with only horizontal and vertical segments. Bring the end close the the wire you wish to connect to as shown in Step 3. When you release the mouse button, the wires will connect as shown in Step 4.

Port-to-Joint Connections

Step 1: select endpoint
Step 2: drag wire end

Step 3: bring wire end
close to other wire
and release
Step 4: continue making
connections as necessary

Figure 2.10: Port-to-Joint Connections
Port-to-joint connections are used to connect a wire end point to the center or corner of another wire, or to an existing wire joint. These connections are made essentially the same way as port-to-port connections. First, as in with port-to-port connections, make sure you have selected the "Move/Connect" tool from the "Tool" menu. Then, select a free endpoint to get the soldering iron (Step 1). Drag the wire near the wire you want to connect to (Step 2) and release the wire to connect to the nearby wire segment (or corner) and create a solder joint (Step 3). You can continue the process to connect as many ports to a net as necessary (Step 4).
Creating Bit Taps


Figure 2.11: Bit Tap
When you attempt to do a port-to-joint connection with wires of different sizes, a "bit tap" will be created if you are connecting a wire with smaller bit size to one with a larger bit size. A bit tap element allows you to select one or more bits off of a bigger wire. To set the desired bit, you should double click on the tap to open the Gate Properties box, select the "Details" tab and enter the desired bit or bits. Ranges are indicated as a pair of bit numbers (high number first) separated by a colon (":") character. For example, to select the low four bits you would use the range "3:0". In the bit tap shown here, bit 4 of the register output is used as an input to the AND gate.

Bit taps can only be used to "read" values off of a larger wire. To individually drive bits on a larger wire you should use the "Concat" device. This device can support data flow in either direction.

Creating New Joints


Figure 2.12:
Wire Tap
You can also create joints by right clicking on a wire and selecting "Add Wire Segments". This will create a new unattached wire segment to the wire on which you clicked as shown here.

2.4.3 Moving Gates and Wires

Moving Single Gates

Step 1: select gate
Step 2: drag gate

Figure 2.13: Moving Single Gates
To move a single gate, press and hold the left mouse button on the gate you wish to move. The selected gate will be shown in bold as shown in Step 1. While holding the mouse left mouse button down drag the gate to the new position as shown in Step 2. Any wires connected to the gate will move along with it. For very fine adjustments, you can also move the selected gate using the arrow keys.
Moving Groups of Gates

Step 1: start selection
Step 2: drag selection box

Step 3: grab selection
Step 4: drag selection

Figure 2.14: Moving Groups of Gates
To move a group of gates, first select the Move/Connect tool and press and hold the left mouse button at some point near, but not directly on the group you wish to move. The "X" mark should appear just as if you were going to create a new gate (Step 1). Next, while holding the left mouse button drag the cursor to enclose a group of gates in the selection box (Step 2). The box will appear after moving the cursor a few millimeters. Release the mouse button to select the circuit elements enclosed in the box (Step 3). Then, click and hold the mouse cursor on one of the selected elements (Step 4). You can then move the entire group to a new position.

The gates in a group selection will remain selected until you click on a gate not in the selection, or click on an empty part of the canvas. If you do this operation while holding the control key, you can add gates to the selection rather than create a new selection.

2.4.4 Cut/Paste and Deleting Gates

The selected gate or gates can be deleted by pressing the delete key, or by right clicking and selecting the "Delete" option. The selection may also be cut or copied to the cut buffer by right clicking and selecting "Cut" or "Copy". The original names of the gates and wires in the cut buffer will be remembered and used when pasting if possible, but when pasting multiple copies from the cut buffer, it may be necessary for TkGate to rename those wires and gates.

2.4.5 Rotating Gates

You can rotate single gates, or groups of gates by selecting the single gate or group and using the and toolbar buttons to rotate counter-clockwise or clockwise, respectively. You can also use the Tab or Shift-Tab keys. When rotating a selection, it can not have any wires connecting a selected element to a non-selected element.

You can also set the default rotation by clicking on the button on the toolbar. The inverter symbol on the button will turn to show the current rotation. Any gates that you create will have the default rotation shown on this button.

2.4.6 Wire Cutter Tool


Before Cut
After Cut

Figure 2.15: Cutting Wires
To cut a wire, select the tool from the toolbar to get the wire cutters tool. Click on a wire to cut the wire at the selected point. If there are any loose ends of a wire that is cut, TkGate will automatically delete the loose ends. It will also delete any joints that are no longer needed as the result of a cut. You can also use the wire cutter tool on the edge of a module to "cut off" a port if the module does not have a protected interface.

2.4.7 Inverter Add/Remove Tool


Before Add
After Add

Figure 2.16: Inverting Inputs/Outputs
You can use the tool to add or remove inverters from a gate input or output. Select the tool and click on an input or output port of a gate. If there is currently no inverter on that port, one will be added. If there is already an inverter on that port, the inverter will be removed.

2.4.8 Wire Bit-Size and Type Tool



Figure 2.17: Wire Type Selector
You can use the tool to change the bit-size and type of one or more wires. Use the "Bits" and "Type" selectors next to the button to set the desired bit size and type. Any wires you click on with this cursor will be set to the size and type displayed. The set of possible wire types and their interpretation are described in the section on writing Text Verilog Modules. In most cases you should use the "wire" wire type. The wire size and type can also be set by double clicking on a wire to open the Wire Properties dialog box.

2.4.9 Zoom-In/Zoom-Out

You can use the and buttons to zoom in and zoom out. There are four zoom levels.

2.5 Gate Properties

Gate parameters can be edited by double clicking on a gate, or by selecting the gate and then invoking the "Properties..." command from the "Gate" menu.  The property dialog box is contains up to four pages which can be selected through the tabs at the top. The "General" page contains basic properties that are common to all gate types, the "Port" page allows editing of ports on the gate, the optional "Details" page contains additional properties that are special to particular gate types, and the optional "Delay" page allows editing of delay parameters of gates.

2.5.1 General Properties


(Click to Enlarge)

Figure 2.18: General Properties
The properties which can be edited on the "General" page shown to the right are:
  • Gate Type: The type of the gate.  This property is immutable.
  • Gate Name: The name of the gate.  This must be a unique identifier for the gate within the module.  Gate names must start with a letter or the '_' character, and must contain only letters digits and the '_' character.  If you attempt to use a gate name which is used by another circuit element in the same module, or attempt to use illegal character, the name will by automatically adjusted by removing the illegal characters, or by appending or prepending characters.
  • Hide Name: A flag to indicate whether or not the name for the gate should be displayed.  The default is not to display names unless this option is explicitly set.
  • Anchor: A flag to indicate whether or not the gate can be moved using the mouse.  A selection containing gates with this option active cannot be moved. This option is useful if you want to prevent accidentally moving a gate.
  • X/Y: The screen position of the gate.  Values can be manually entered even if a gate is anchored.
  • Critical Path Partition: Makes the selected element a partition point for the purpose of critical path analysis. Paths through an element with this property will not be considered for the purpose of critical path analysis.

2.5.2 Port Properties


(Click to Enlarge)

Figure 2.19: Port Properties
The "Ports" page contains a list of all the ports on the selected gate. To edit ports on a gate, double click on the port you wish to modify, or select a port and hit the "Edit..." button. You can edit the fields that are modifiable in-line in the dialog box. You can change the signal name or the bit width, but the port name and type may not be editable for all element types. You can also use the "Add.." and "Delete" buttons to add new ports or delete ports for some element types.

The fields in the port list are:

  • Signal Name: The name of the signal. The signal name must be unique within the module and has the same naming restrictions as gate names.
  • Port Name: The name of the port the signal is attached to. The port name can only be changed for module instances.
  • Type: The direction (input, output, bidirectional) of the port. The type can only be changed for module instances.
  • Bit Width: The number of bits in the signal.

2.5.3 Detail Properties


(Click to Enlarge)

Figure 2.20: Detail Properties
The "Details" page of the Gate Parameters dialog box is used to set properties that are specific to a gate type. Not all gates have a "Details" page. The example shown here is for a MUX. There are two possible choices for the ordering of the inputs: left-to-right with the lowest numbered input on the left, and right-to-left with the lowest numbered input on the right. There are also two possible choices for which side the MUX selector is placed on.

Other types of gates which take detailed parameters include modules (which require a function name), memories (for which a memory initialization file can be specified), switches (for which an initial value can be specified) and clocks (for which the clock parameters can be specified).

2.5.3 Parameter Properties


(Click to Enlarge)

Figure 2.21: Parameter Properties
Modules defined as Verilog text can have "parameters" in addition to ports. Parameters are constant values that are used by the module. To change the value of a parameter, double click in the "Value" column and enter the new value for that parameter. See the section on writing text Verilog modules for more information on how to create modules with parameters.

2.5.4 Delay Properties


(Click to Enlarge)

Figure 2.22: Delay Properties
Delay for gates can be set either by specifying a standard technology or by customizing the delay for each individual gate. To use a standard technology, select "Standard Delay" and select a technology from the selector button. You can choose one of the built-in technologies "default" or "unit" that comes with TkGate, or add additional technology definitions (see Gate Delay Files for details). The "default" technology is roughly based on CMOS delays, and the "unit" technology simply sets single epoch delays for everything. Note that the delay values shown here can be affected by the bit-width of the ports, the number of ports and the existence/absence of inverters on the ports of gates. In some cases, adding an inverter to a port on a gate can decrease the delay value (e.g., adding an inverter to change an AND into a NAND).

To set the delay values for an individual gate, select "Custom Delay" and enter values for each of the delay parameters in epochs. Delays values must be integers greater than or equal to one, and less than 4096.

2.6 Wire Properties


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Figure 2.23: Wire Properties
Wire properties can be edited by either double clicking on a wire, by double clicking on a net name from the "Nets" list, or by selecting a net from the "Nets" list and then invoking the "Properties..." command from the "Gate" menu.

The net properties are:

  • Net Name: The signal name of the net.  Signal names must be unique within the module in which they are defined.  Signal names must start with a letter or the '_' character, and must contain only letters digits and the '_' character.  If you attempt to reuse a name within a module, or to use an illegal character, the name will be automatically adjusted by removing the illegal characters, or by appending or prepending characters.  Signal names that begin with a '_', will be displayed with an over-bar to indicate an active low signal.  In this case, the leading '_' itself will not be displayed.
  • Hide Name: A flag to indicate whether or not the name for the signal should be displayed.  The default is not to display names unless this option is explicitly set.
  • Bit Width: The number of bits in the signal.
  • Net Type: The type of the net.
  • Port Type: The direction (input, output, bidirectional) if this signal is a module port.  If the signal is not a module port, this field will not be displayed.

2.7 Wire Name and Bit-Size Labels

One way to display the label of a wire is to uncheck the "Hide" option in the Wire Properties dialog box. Another easier way is to right click on the wire and select "Show Label". This will show the label of the net at the point at which you clicked. A wire may be labeled on one or all segments. You can also click on a wire label and drag it to a new position on the net. When you let go of the label, it will be attached to the closest point on the closest segment. It will also be attached on the same side on which you drop it. You can remove a label from a segment by dragging it far from the wire and dropping it, or by explicitly right clicking and selecting "Hide Label". The "Hide Label" function will hide only the label on the selected segment.

Right clicking and selecting "Hide All Labels" will make all of the labels on a net invisible, but TkGate will remember where they were placed. The next time you select "Show Label", or uncheck "Hide" in the Wire Properties dialog box, all of the hidden labels will become visible again. If you instead select "Clear All Labels", the labels will be hidden, and the original locations forgotten.

You can turn display of the bit width of a multi-bit wire on and off by right clicking and selecting "Show Bit Width" or "Hide Bit Width". The display can be controlled for each segment, but the size is always displayed in the middle of the segment and can not be moved.

2.8 Searching for Gates and Wires


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Figure 2.24: Search Dialog Box
You can search for wires and gates anywhere in your circuit by using the "Find..." option from the "Edit" menu, or by pressing on the toolbar. Enter text into the entry area to search for gates, nets or text in circuit comments. The search results will be updated as you type showing the list of objects that match your search criteria. You can choose to locate objects with names that contain, begin with, end with or exactly match the name you type. You can also choose to ignore case in the match, or limit the search to only gates, nets, comment text, or any combination thereof.



Figure 2.25: Cross-hairs
on Target Device
When you wish to go to an item in the search list, double click on it. TkGate will open the module containing that item, and place cross-hairs on it to show you which item you selected. The search dialog box will remain open until you press "Close" so that you can visit multiple objects until you find the one you are looking for. Press the "Find" button to go to the next object in the list without double clicking.

2.9 HTML in Comments


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Figure 2.26: Comment Editor
TkGate supports a small number of HTML markup elements in comments. The markup commands can be used to change font face, font size, or add hyperlinks to other documents or locations in a circuit. Comments are created by clicking the mouse to set a mark, then selecting "Comment" from the "Gate" menu (or using the "C" shortcut).

When you first create a comment, the properties box for the comment will appear and allow you to enter the text of the comment. You can also double click on an existing comment to edit its text. Hold down the Shift key while clicking to avoid following any hyperlinks in the comment.

When you are done typing the comment, click on the "OK" button to close the comment properties box and update the text of the comment as it is displayed on the screen. Currently, unlike a true HTML document, newlines in comments are not wrapped and are displayed as typed.

The supported markup commands are:

ElementDescription
<value-of name="name"> Replace with value of special TkGate constant.
<a href="url"></a> Insert a hyperlink or link to a Verilog file.
<b></b> Make the enclosed text appear in a bold font.
<i></i> Make the enclosed text appear in an italic font.
<h1></h1> Make the enclosed text appear in Heading 1 font.
<h2></h2> Make the enclosed text appear in Heading 2 font.
<h3></h3> Make the enclosed text appear in Heading 3 font.
<tt></tt> Make the enclosed text appear in fixed-width typewriter (Courier) font.
<small></small> Make the enclosed text appear in a font one step smaller than the current font.
<big></big> Make the enclosed text appear in a font one step bigger than the current font.
<font></font> Set the font characteristics of the enclosed text.
&??; Replaced with a character entity.

2.9.1 Accessing Internal Constants (<value-of>)

This is a special TkGate-specific markup command. It is replaced with the value of the specified variable. The primary purpose of this command is for use on the TkGate start-up page. The possible variable names are "tkgate-version" for the current version of TkGate, "tkgate-homepage" for the current home page of TkGate, "tkgate-mailcontact" for the e-mail address of the TkGate contact person, "tkgate-copyright" for the copyright notice, and "tkgate-release-date" for the release date of this version of TkGate.

2.9.2 Hyperlinks (<a>)

This command inserts a hyperlink into a comment. Different actions are performed depending on the protocol of the link. For "http:" and "mail:" protocol links, TkGate will open the browser or e-mail client that has been registered in the users TkGate options. Use the HTML Tab in the Options dialog box to set your browser and email client.

If the protocol is "file:", then action depends on the extension on the file. If the extension is ".v", then TkGate will load the specified file as if it had been opened through the "File Open..." menu. If the extension is ".html", then TkGate will load the file in a browser, just as with "http:" protocol links. For all other extensions, TkGate will load the file in a text viewer.

Files specified with the "file:" protocol can use one of the following special codes to reference specific TkGate directories:

CodeDirectory
@TTkGate tutorial directory.
@ETkGate examples directory.
@HTkGate home directory.
@CDirectory of currently open circuit.

If a link contains the '#' character, the text after it is treated as a label. A label can reference a gate, wire or module. When the first character is '/', the rest of the label is assumed to reference a module. TkGate will open that module when the link is followed. When the first character is not '/', then the label is assumed to reference a gate or wire instance. A full path specifier must be used. That is a wire "w4" in a module with instance name "m1" (not function name) would be specified with the link "#m1.w4". When instance links are opened, TkGate will go to the containing module and place "cross-hairs" on the item referenced by the label. In the special case where the entire link starts with a '#', these actions are performed in the current circuit.

One additional, TkGate-specific protocol is "action:". Links with the "action:" protocol can be used to invoke TkGate commands. For example "action:newFile" will cause TkGate to open a new file just as if the user had selected "File New..." from the menu. The following actions are supported with the "action:" protocol:

ActionDescription
newFileCreate a new file.
loadFileLoad an existing file.
loadLibraryOpen the library manager.
saveFileSave the current file.
saveAsFileSave the current file to a new name.
editOptionsOpen the options dialog box.
startSimulatorStart the simulator./td>
blockNewCreate a new module.
blockDeleteDelete a module.
blockCopyCopy a module.
blockSetRootSet the root module.
blockRenameRename a module.n
blockClaimClaim a module.
zoomInZoom in.
zoomOutZoom out.

2.9.3 Fonts

Example:

The comment text:

   <font color=toupe family=times size=4>This is a test</font>

Will be rendered as:

  This is a test

There are several command for changing the font size, face and color. The most general of these is the <font> command. TkGate supports the "size", "color" and "face" attributes of this command. The "size" is an integer between 1 and 7 where 1 results in the smallest supported font, and 7 the largest. The "color" attributes specifies the color that should be used for the text. Any color from the X11 color name database may be used. The "face" specifies the font family to use. The supported font families are "courier", "helvetica", "times" and "symbol".

2.9.4 Character entities

Character entities are sequences of characters that are replaced with special symbols. Most of the common character entities available in HTML are supported. For example "&lt;" is replaced with "<", and "&ge;" is replaced with "≥". Greek characters can also be generated. For example, "&alpha;" is replaced with "α".

2.10 Printing a Schematic


(Click to Enlarge)

Figure 2.27: Print Output Page
To print a circuit, choose the "Print..." option from the "File" menu, or press the button on the toolbar. You can choose to print directly to a printer using a specified print command, or you can print to a file. When printing a single-page document to a file, you can also choose to save the circuit in encapsulated postscript. This will suppress printing of the page frame and title.

The print dialog box is divided into two pages. The first page selects the "Output" of the command and has the following options:

  • Output to printer/Output to file: Select one of these to indicate if the schematic should be written to a file, or sent directly to the printer.
  • Printer: If printing to a file, this will indicate the printer to use. The list of printers is determined from /etc/printcap file. You can click on the "Advanced..." button to edit the printer command used to output to that printer.
  • File Name: If output to a file is selected, this field indicates the name of the output file The default name is the name of the current circuit name with the extension renamed to ".ps". You can use the "Browse..." button to bring up a file name browser.
  • Save as Encapsulated Postscript: If this option is enabled, the circuit will be saved as an Encapsulated Postscript file suitable for inclusion into a document. Printing of the title bar and the frame will be suppressed. Only single-page documents can be save In Encapsulated Postscript format.
  • Paper Size: Indicates the paper size of the document. If your printer is multi-tray, the appropriate tray will be selected. A variety of U.S. and European/Asian paper sizes are provided.
  • Orientation: Indicates the orientation of the diagram on the page. If you select "Portrait", the image will be printed so that the long side of the paper is vertical. If you select "Landscape", the image will be printed so that the short side is vertical.
  • Print Double-Sided: Indicates that images should be printed on both sides of the page. This option is only effective on printers capable of double-sided printing.


(Click to Enlarge)

Figure 2.28: Print Content Page
The second page of the print dialog box selects the "Content" to be printed and has the following options:
  • Module Selection: Indicates which modules should be printed. The options are:
    • All: All modules in the current document will be printed.
    • Current: Only the module in displayed in the main editing window will be printed.
    • Used: Only the top-level module and any of its sub-modules will be printed.
    • Selected: Only modules selected in the list box below will be printed.
  • Include library modules: Normally modules marked as being loaded from a library will not be printed.  Enable this option to print these modules.
  • Scale large modules to fit page: Modules which cannot fit on a single page without scaling will be reduced in size so they fit.
  • Partition large modules into multiple pages:Modules which cannot fit on a single page without scaling will be split into multiple pages.  A key indicating which portion a page represents will be printed in the lower right corner of the page.
  • Include index: Prints an index page listing each of the modules in alphabetical order and the pages they are on.
  • Include hierarchy graph: Prints a hierarchy graph rooted at the top-level module showing the relationship between parent and child modules.
  • Print small modules four per page: Causes modules which can fit into a single quadrant to be grouped and printed on the same page. 



2.11 Circuit Properties


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Figure 2.29: General Circuit Properties
Circuits have several global properties which can be set by selecting "Circuit Properties..." from the "Module" menu.  This will cause the dialog box shown at the right to appear.

The circuit properties are organized into two pages. A "General" page listing several miscellaneous properties, and a "Simulation" page listing properties that affect simulation of the circuit. The properties on the "General" page are:

  • File Name: This non-user-modifiable field shows the name of the file from which the circuit was last read or saved to.
  • File Version: This non-user-modifiable field shows the version of TkGate that saved the file from which this circuit was loaded.
  • Circuit Title: This is a text description of the circuit. It will be used when printing a schematic. It is also used for user-defined libraries as the library description in the library manager.
  • Do not warn about discarding changes: Enabling this option disables warnings when discarding a modified circuit by exiting TkGate, by loading a new circuit, or by creating a new circuit. Normally, this option is only used by the example and tutorial circuits that come with TkGate. Enabling this option is not recommended for user circuits.
  • Use extender bars: This determines whether "extender bars" should be used on newly created gates. In older versions of TkGate, the inputs on simple gates such AND and OR were squeezed into a fixed space irregardless of how many inputs their were. Newer versions of TkGate can use extender bars on many-input AND, OR and XOR gates. You can use this option to control the style to be used on newly created gates. Existing gates are unaffected and a circuit can contain a mix of old-style and new-style gates.
  • Enable auto-start of simulation: If this flag is enabled, the simulator will be automatically started when you load this circuit.


(Click to Enlarge)

Figure 2.30: Simulation Circuit Properties
The "Simulation" page of the circuit properties includes the following options:
  • Initialization Scripts: Indicates a list of TkGate simulation scrips which will be automatically executed when the simulator is started. If a file name does not start with a '/', the current directory, the directory containing the circuit file and the user's home directory will be searched for the file.
  • Clock Options: Indicates the behavior of the clock step command or Tab key when in simulation mode. If "Clock step stops on all clock posedges" is selected, then the button will cause the simulation to advance until the rising edge of any clock in the circuit. If "Clock step stops on clock: is selected, then the button will cause the simulation to advance until a rising edge on the specified clock. All other clocks will be ignored.
  • Default Simulation Time Scale This option allows you to set the default time scale for the circuit. The units are the units to use for delay, and the precision sets the time for one simulation epoch.

Last edit by hansen on Fri Jul 27 09:37:56 2007 tkgate-2.0-b10/doc/gateGmac.html000644 001751 001751 00000035227 10652375352 017172 0ustar00hansenhansen000000 000000 TKGate User Documentation (Microcode and Macrocode Compiler)

6. Gate Microcode and Macrocode Compiler

Gmac is a simple microcode and macrocode compiler which can be used to create memory files for TkGate. You can write declarations to define your own microcode and macrocode. The current version of gmac is fairly simple; no attempt is made to handle arbitrary instruction sets with complex addressing modes, but it should be sufficient to create simple micro- and macro-programs. To compile a micro/macro program description, use the command: 
gmac infile.gm -o outfile.mem -l outfile.map
This will read the description in "infile.gm", and generate the memory file "outfile.mem" and and the optional map file "outfile.map". The memory file will contain the appropriate "memory" keywords to load multiple memories. The map file contains the list of symbols defined in the input file in a human-readable form.

Gmac input files consist of a sequence of declarations. Whitespace and newlines are ignored, and comments are indicated by a '//'. A complete example of a Gmac input file is given in Appendix E.

6.1 Defining Memory Banks

The memories which will be generated are declared with "bank" statements. A bank statement has the form:

type bank [msb:lsb] name ?[first:last]?;

The type parameter is one of "microcode", "macrocode" or "map" and specifies what type of memory this is a bank for. Microcode and macrocode banks specify the memories to be used for the micro- and macro-programs respectively. Map banks are typically used to look up the microaddress for implementing a macro-instruction. Each of the memory types is optional and can be omitted.

The bit range [msb:lsb] specifies the portion of the word which will be stored at an address in the memory name. The specified memory should be the full path name of a memory in the circuit file. A word can be broken across multiple memories by using multiple bank statements. A single bank is limited to 32 bits, so memories with very long words, such as a micro-program will probably have to be broken into multiple memories. An optional address specifier after the memory name specifies the range of address which this memory will hold. If no address range is specified, this memory will be used for all words. As an example, consider the set of bank declarations: 

microcode bank[31:0] iunit.m1;
microcode bank[63:32] iunit.m2;
map bank[7:0] iunit.map;
macrocode bank[7:0] memory.m1;
This indicates that the mirco-program will be consist of 64-bit instructions with the low half of the instructions being stored in "iunit.m1" and the high half of the instructions being stored in "iunit.m2". The map memory contains 8-bit data and is stored in "iunit.map". The main macrocode memory has 8-bit words and is stored in "memory.m1".

6.2 Defining the Micro-Instruction Set

Microcode instructions are defined using the 'field' declaration. A field declaration consists of the 'field' keyword followed by one or more comma-separated declarators. A simple declarator is simply a name followed by a bit range in square brackets. For example: 
field cin[18], idata[9:2];
declares that bit 18 of the microinstruction has the name "cin", and the bits 2 through 9 have the name "idata". Single bit fields can optionally be prepended with the "~" to indicate they are active low signals. A set of symbolic values can also be supplied for a field. For example: 
field mpcop[1:0]={
	 next=0,	// Increment mpc
	 reinit=1,	// Restart CPU
	 jmap=2,	// Jump from map value
	 jump=3		// Jump from condition
};
declares a 2-bit field "mpcop" with a set of symbolic names for field values. Hexadecimal symbolic values can be specified by prepending them with a "0x".

6.3 Writing the Micro-Program

A block of microcode is defined using the "begin microcode @" specifier. A start address must be specified after the declaration. The end of the block is indicated with the "end" keyword. The micro-program defined in the block will be stored starting at the specified address. Microinstructions consists of a list of fields (defined by the 'field' keyword described above), with an optional value specification. The microinstruction is ended by a ";". Micro instructions can be labeled by specifying an identifier followed by a colon.

For each single-bit field, the presence of a field name in a microinstruction indicates that that bit should be asserted. For normal fields, this means setting the bit to 1 in the microinstruction. For active low fields (indicated with a "~" symbol in the field declaration) this means setting the bit to 0. The bit corresponding to any active low fields not specified in an instruction will be set to 1. For multi-bit fields, a value should be specified after an '=' symbol. The value can be either a fixed constant, a symbolic value defined for the field, or a label which will be resolved to the appropriate microinstruction address when the specification is compiled.

For example, consider the microcode fragment: 

begin microcode @ 0
start:	clq;								// Q <- 0
	idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh;			// Q.H <- 1
	ALU_AZERO ALU_OP=add bop=qreg dout ldpc;			// PC <- Q
	mpcop=jump mpccond=jmp mpcaddr=fetch;				// jump to 'fetch'
	mpcop=next;
end
This specifies that this fragment will begin at address 0. The first mirco instruction is labeled 'start' and simply asserts the signal 'clq'. In this case, this clears the contents of the Q register. The next micro-instruction puts the value '1' on the field name "idata", asserts the signal "ALU_AZERO", puts the symbolic value "add" on the field "ALU_IP", the symbolic value "idata" on the field "bop" and asserts the signal "ldqh". This set of operations causes a 1 to be stored in the high half of the Q register. The subsequent instructions load the program counter PC from the value stored in the Q register (0x100), and jumps to the label 'fetch'.

6.4 Defining the Macro-Instruction Set

The macro-instruction set is defined using "register", "operands" and "op" declarations. The "register" keyword is used to define the register names used in the macrocode and assign them a numeric value.

For example: 

registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, FP=6, SP=7;
declares 8 registers name R0 through R5, FP and SP. With numeric values as specified in the declaration. The numeric value here will be used in building the macroinstruction using a register.

6.4.1 Operand Declarations

The "operands" declaration specifies a set of operand types that an instruction can have. An operands declaration consists of the "operand" keyword, a symbolic name, and a list of addressing modes. Currently only four addressing modes are recognized: immediate, register direct, register indirect, and indexed. Since the syntax of the operand declarations is rather complicated, it will be explained with an example. For instance, suppose we wish to define an 'add' instruction which can use the following addressing mode combinations: 
   add	R1,#1234	// register direct, immediate
   add  R1,R2		// register direct, register direct
   add  R1,(R2)		// register direct, register indirect
   add  R1,#Array(R3)	// register direct, indexed
We can define the addressing mode combinations with the declaration: 
operands myopts {
    %1,#2     = { +0[1:0]=0; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
    %1,%2     = { +0[1:0]=1; +1[7:4]=%1; +1[3:0]=%2; };
    %1,(%2)   = { +0[1:0]=2; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
    %1,#2(%3) = { +0[1:0]=3; +1[7:4]=%1; +1[3:0]=%3; +2=#2[7:0]; +3=#2[15:8]; };
};
This block defines a set of 4 operand combinations for a two-operand instruction. Each operand combination is specified by a comma separated list of addressing modes. A '-' can be used in place of the operand list to indicate instructions with no operands. Registers are indicated by a '%' followed by an id number, and numbers are indicated by a '#' followed by an id number. The statements in braces following an address mode combination specify a sequence of assignments used to build the macroinstruction. Each assignment contains a word number within the macroinstruction, an optional bit range, and a value to store at the specified location. If the value is a simple number, the specified number will be stored. If the value is prepended with a '%' or '#', then the value is taken to be the id number for a register or number specified in the instruction. For example, on a machine with a byte-addressable main memory, the previous operand declarations will generate the bytes: 
   +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  +-+-+-+-+-+-+-+-+  +-+-+-+-+-+-+-+-+
   | undefined |1 1|   |0 0 0 1|0 1 0 1|  |0 0 1 1|1 0 0 0|  |0 0 0 1|0 0 1 0|
   +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  +-+-+-+-+-+-+-+-+  +-+-+-+-+-+-+-+-+
for the instruction: 
   add  R1, #0x1234(R5)
Since the addressing modes are "register" and "indexed", the last entry in the list of operand combinations applies. The "+0[1:0]=3" statement sets the low two bits of the first byte to binary '11'. The "+1[7:4]=%1" statement sets the high half of the second bytes to the code for the R1 register, and the "+1[3:0]=%3" statement sets the low half of the second word to the code for the R5 register. The "+2=#2[7:0]" and "+3=#2[15:8]" statements store the index value '0x1234' in the third and fourth bytes of the instruction low byte first.

One last type of memory assignment is the relative address assignment. Relative addresses are indicated with the '@' operator. The pair of statements "+2=#2@[7:0]" and "+3=#2@[15:8]" will store the difference of the operand with id 2 and the address of the first byte of the instruction. This feature can be used to define relative branching instructions. An optional value can be specified after the '@' as a further fixed offset.

6.4.2 Macro-Instruction Declarations

After defining a set of operand declarations, you must define the macro-instruction set. A macro-instruction declaration consists of the 'op' keyword, an identifier, and a definition in braces. The definition can include memory assignment statements as described in the section on operands above, 'map' statements and an operand declaration. For example: 
op add {
  map add_ri : 0x68;	// register direct, immediate
  map add_rr : 0x69;	// register direct, register direct
  map add_rd : 0x6a;	// register direct, register indirect
  map add_rx : 0x6b;	// register direct, indexed
 +0[7:0]=0x68;
  operands myopts;
};
defines the 'add' instruction with the operand set defined by myopts. The statement '+0[7:0]=0x68' defines the base opcode for the instruction and the position to store it in the instruction word. The 'map' statements define map memory values that can be used to map an opcode to a microinstruction address. The left side of the 'map' statement specifies a label in the microprogram. The right side specifies an opcode value which maps to that address. Since the low two bits of the first byte are used to indicate the addressing mode, we need four map statements for each of the four operand combinations. The map declarations shown here will cause the map memory to contain the addresses for the microinstructions add_ri, add_rr, add_rd and add_ri at the addresses 0x68, 0x69, 0x6a and 0x6b in the map memory.

6.5 Writing the Macro-Program

Similar to the micro-program block, the macro-program block is started by the "begin macrocode" specifier and ended by the 'end' specifier. For example: 
  begin macrocode @ 0x100
will start a block of macrocode at address 0x100. Unlike other portions of the gmac specification, newlines are significant in the macrocode block and indicate the end of a macroinstruction. A macro program consists of a list of instructions and directives. Any of the macroinstructions defined can be used, and labels can be defined by starting a line with an identifier followed by a ":".

Directive Description
label: .symbol value Defines a label to be a specified value.
.short value, ... Inserts a set of two-byte values at successive memory locations.
.long value, ... Inserts a set of four-byte values at successive memory locations.
.byte value, ... Inserts a set of byte values at successive memory locations. This directive can also take strings denoted by double quotes with each byte of the string being stored at successive locations.
.bss value Reserves value bytes of unallocated memory at the current position. This directive can be used to define uninitialized global variables.
.proc label This directive can be used in conjunction with ".end" to define a procedure. The label specified will be assigned the current address, but any labels defined between the ".proc" and the ".end" directives will be treated as local labels.
.end Ends a procedure definition.


Here is a short example of a macro program: 
begin macrocode @ 0x100
ttydata:	.symbol	0x11	// tty data in/out register
ttystatus:	.symbol	0x10	// tty status register
start:
	movw	SP, 0		// Initialize the stack pointer to 0
	movw	FP, 0		// Initialize the frame pointer to 0

	push	msg		// Push msg on the stack.
	call	print		// Call the procedure 'print'
	add	SP,2		// Reset the stack pointer.

sdone:	jmp	sdone		// Hang in an infinate loop.

////////////////////
//	print(s)	Print the string s
//
.proc print
	movw	R1, 4(FP)	// Store the argument value in R1
loop:	movb	R2, (R1)	// Store the byte addressed by R1 in R2
	jeq	done		// If the byte was a zero, jump to 'done'
	movb	(ttydata),R2	// Store the byte in the tty data register
	movb	(ttystatus),#1	// Write a 1 to the tty status register to output the byte
	add	R1, #1		// Add 1 to the R1 register
	jmp	loop		// Jump back to 'loop' to get the next byte.
done:	ret
.end

msg:	.byte	"Hello World.\n", 0
Given the appropriate circuit, mircrocode and macrocode definitions, this program will print the message "Hello World." on a tty and halt by entering an infinite loop. tkgate-2.0-b10/doc/gateIntro.html000644 001751 001751 00000015772 10652371424 017415 0ustar00hansenhansen000000 000000 TKGate User Documentation (Preface)

1. Introduction to TkGate

TkGate is a digital circuit editor and simulator with a Tcl/Tk-based interface. TkGate includes a large number of built-in devices including basic gates, memories, ttys and modules for hierarchical design. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create TkGate memory files from a high-level description. The simulator supports continuous simulation, single step simulation (by clock or epoch) and breakpoints. Save files are in a Verilog-like format.

A TkGate circuit is divided into one or more modules, with one of the modules being designated the "top-level" or "root" module. A module is composed of zero or more "gates" and wires to connect the gates. We use the term "gate" loosely to refer to any circuit element. Special "comment" gates can be used to place text in the circuit.

Creating a gate in TkGate is simply a matter of clicking the cursor to set a position, and selecting a gate type from the menu. Since most gate types have a one or two character shortcut, once you learn the shortcuts you can perform most of your editing with one hand on the keyboard and the other hand on the mouse. Moving gates is almost as easy as creating them, simply select a gate (or gates) and drag them to a new position, any wires connected to the gates will be moved along with them and adjusted to ensure that they contain only horizontal and vertical segments.

1.1 Command Line Options

Start TkGate with a command of the form: 
% tkgate [options] [files ...]
The following command-line options are supported:
OptionDescription
-vBe verbose about start-up error messages and warnings.
-VRead the TkGate files specified on the command-line and check them for internal errors, but do not start TkGate.
-hPrint the list of options.
-dTurn on debugging.
-xAutomatically starts the simulator on start-up.
-qSuppresses start-up messages.
-sExecutes with a synchronous X server connection. This option is primarily for debugging.
-nDo not display the splash screen on start-up.
-l libLoads the specified library on start-up. Can be specified multiple times.
-L langSpecifies the language to use. TkGate must have been built with multi-lingual support in order to use this option.
-O optsSpecifies a list of printer options.
-P printerPrint the specified circuit to a printer without starting up the GUI.
-p filePrint the specified circuit to a file without starting up the GUI.
-X scriptStarts the simulator and executes the specified simulation script.
The -O switch is used in conjunction with the -p or -P switches to specify any printer options. The printer options are given as a colon separated list of options. The following printer options are supported through this interface:
OptionDescription
epsf=boolUse encapsulated Postscript format
duplex=boolUse duplex printing
index=boolInclude index
hier=boolInclude module hierarchy graph
paper=typeUse the specified paper size
4up=boolDo 4-up printing of small modules
modules=listComma separated list of modules to print

1.2 History of TkGate


(click to enlarge)

Figure 1.1: xgate - An Early XLib Based
Predecessor to TkGate
TkGate begin life as an undergraduate project at Carnegie Mellon University (CMU) in 1987. At that time it was called simply 'gate' and ran under the 'wm' window manager, a windowing system developed at CMU before X11 was widely used. This incarnation was used by students in the computer architecture course at CMU to develop a simple microprocessor (dubbed "The Bat Computer"). Many of the bitmap images for the circuit elements and mode cursors (such as the wire-cutter cursor) used today were originally designed in this version. This version also contained the hidden pancake recipe which is still in TkGate today.

After laying dormant for several years, it was resurrected in 1991 and ported to run under X11 with the Xlib API. A screenshot of this version, which was called "xgate", is shown in Figure 1.1. In this incarnation it was used several times by students in the introductory digital logic course, but after the author graduated and left CMU, it went into hibernation again.

Work on the first Tcl/Tk incarnation begun in 1998 as an exercise in learning Tcl/Tk. It was also the first version to use a Verilog-like save file format. Previous versions of gate/xgate used a Lisp-like save file format.

The current version, TkGate 2.0, represents a substantial effort over the previous 1.8 version. Whereas TkGate 1.8 was comprised of approximately 73,000 lines of C and Tcl, TkGate 2.0 nearly doubles that line count with over 130,000 lines of C and Tcl. Major improvements added to TkGate 2.0 include an improved user interface, true Verilog format save files, Verilog-based simulation, a module interface editor, symbolic module interfaces and virtual peripheral devices. tkgate-2.0-b10/doc/gateSim.html000644 001751 001751 00000130174 10653516220 017040 0ustar00hansenhansen000000 000000 TKGate User Documentation (Simulation)

5. Using the Simulator

The TkGate simulator, Verga (VERilog simulator for GAte), is a discrete time simulator based on Verilog. All modules, including those designed graphically, are converted to Verilog for simulation. Verga is a discrete event simulator. Time advances in discrete time units called "epochs". When simulating, time remains at the current time step (or epoch) until all work scheduled for the epoch as been completed. The simulator will then advance the current simulation to the next epoch that has work scheduled for it.

5.1 Starting the Simulator


Figure 5.1: Simulator Mode Tab
To start the simulator, press the "Simulate" tab at the top of the main window. If you have not enabled "auto-start" in the circuit properties, the simulator will compile your design and wait in paused mode. If you have enabled "auto-start", the simulation will begin immediately.


Figure 5.2: Simulator Mode Module Hierarchy
The simulation will be performed with the designated root module at the top-level. The simulator internally expands any module instances in your circuit. While the simulator is active, the Module Hierarchy View changes to show the hierarchy of module instances as shown in Figure 5.2. In this mode, the display shows each instance of each module, rather than simply one entry per module. The module name for the instance are shown in angle brackets after the instance name. For example, the instance "RF" under "eunit" is an instance of a "REG16" module. That module contains an instance "RF0" of a "ZREG" module, and three instances "RF1", "RF2" and "RF3" of a "REG4" module. Double clicking on an instance in this hierarchy view will move the simulator to that module, and ensure that any probes or signals viewed are for the instance you selected.

While the simulator is active you must navigate using either the Module Hierarchy , or by right clicking on a module and using " Open" and " Close". You can not use the Module List view to navigate since TkGate can not tell which instance of a module to open.

5.1.1 Simulator Console


(Click to Enlarge)

Figure 5.2: Simulator Console
At the bottom of the TkGate main window, is a pull up tab for the simulator console. When you start the simulator, the console will open automatically, but you can view it in edit mode as well by manually pulling up the tab.

The simulator console has four tabs with different pages of information. These four pages are:

PageDescription
Message Page - This page displays messages from the console. Any output from $display or other system tasks generating output will be displayed here.
Breakpoint Page - Displays breakpoints that have been set for the simulation and the status of those breakpoints.
Script Page - Shows the loaded simulation scripts and their status.
Simulation Control Page - Allows you to set options controlling the simulation such as the number of epochs to advance at a time when stepping through a simulation.

5.1.2 Simulator Control

A set of five buttons controls the advance of time in the simulator. These buttons are:

ButtonDescription
Run - Enters continuous simulation mode. The simulation will continue as long as there are events in the event queue. If there are any clock gates in your circuit, this will mean the simulation will continue indefinitely. If the circuit is combinational, the simulation will continue until the circuit reaches quiescence.
Pause - Causes a continuously running simulation to stop.
Step - Causes the simulation to advance a fixed number of epochs. The number of epochs to advance can be set on the simulation options menu. You can also invoke this command with the space-bar.
Clock Step - Causes the simulation to advance to the rising edge of a clock. You can set the number of clock cycles to simulate and the number of epochs past the designated cycle to step (to allow time for registers to change value). The default is to trigger on any clock, but you can designate a specific clock in the simulator options menu. You can also invoke this command with the tab key.
Stop - Causes the simulation to be terminated and all probes to be deleted.


(Click to Enlarge)

Figure 5.3: Simulator Console Control Page
You can use the control page of the simulator console shown in Figure 5.3 to control the effects of the step and clock step buttons. Enter the number of epochs to advance for each press of (or space-bar) into the "Epoch Step Size" box. The clock step button (or tab) will advance by the number of clock steps indicated in "Clock Cycle Step Size", plus an additional number of epochs entered in the "Clock Overstep" entry.

5.2 Observing the Output

Except when otherwise noted, Verilog syntax is used to specify and display values. A Verilog syntax number contains a prefix to specify the bit width, a quote character, a radix character and the digits of the number. The radix characters using in TkGate are "b" for binary, "h" for hexadecimal, "o" for octal and "d" for decimal. For example "8'h3e" is the 8-bit hexadecimal number "3e".

5.2.1 Current Value Display


Figure 5.3: Value Display
To display the current value of a signal in a circuit, click and hold the mouse button on a wire. This will display the current value driven on the wire in Verilog syntax as shown in Figure 5.3. The value will disappear when you release the mouse button. This feature can be used both when the simulator is paused and when it is in continuous simulation mode. When the simulator is in continuous simulation mode, the value displayed will be the value at the time the mouse button was first pressed.

There is a slight delay between pressing the mouse button and displaying the value. This is because double clicks on a wire are used to set probes, so the delay must be long enough to determine that the mouse press is not a double click. By default, this delay is 333ms (1/3 of a second), but the delay may be changed through the Simulate Options dialog box.

5.2.2 Scope View


(Click to Enlarge)

Figure 5.4: Scope Window
To set a permanent probe on a signal, double click on a wire. This will add or remove a probe. When a probe is set on a wire, its value will be continuously displayed in the scope window. The values of multi-bit signals will be displayed as hex numbers. The scope window (Figure 5.4) is viewable any time you have at least one signal with a probe on it. When there are no current probes, the scope window is hidden.

You can slide the range of time displayed in the scope window by using the scroll bar for coarse changes, or by clicking and dragging in the trace part of the window for fine grain control. To zoom in, you can press the left mouse button while holding the shift key, press the '>' key, or press the button on the toolbar. To zoom out, you can press the right mouse button while holding the shift key, press the '<' key or press the button on the toolbar.

ScopeDescription
 0 - Logic 0 or false (1 bit signals only)
 1 - Logic 1 or true (1 bit signals only)
 x - Unknown value
 z - Floating or high impedance
 L - Low (the signal is either floating or zero)
 H - High (the signal is either floating or one)
 Data - Data value on a multi-bit wire.

Figure 5.5: Logic Trace Values

The time-line on the scope window is displayed as a base value shown in the lower left corner, and an offset value shown along the bottom. In the example shown in Figure 5.4, the base value is 50016916ns (i.e., 0.05 simulated seconds). Each tick mark on the x-axis represents an additional 5000ns past the base time value.

The scope includes a cross hair that follows the mouse whenever it is in the scope window to help you correlate events across different traces. You can enable or disable the cross hairs with the button on the toolbar. The scope window toolbar also includes some of the same simulation control and other simulation-related buttons that are on the main TkGate window.

Figure 5.5 shows how the various logic values are displayed in the scope windows. On multi-bit wires, the value of the wire is displayed in hexadecimal, unless the scale is such that there is no room to display the value between when it starts and the next logic transition. In this case, it will first compress the value to a "#", and if there is no room to display that either, no value or symbol will be displayed. The colors used in the scope traces can be configured through the Color Options dialog box.

5.2.3 Printing Scope Traces


Figure 5.6: Print Region Selection
To print a scope trace, first use the right mouse button to select a region to be printed. Click and drag with the right mouse to select the region. The region will be highlighted as shown in Figure 5.6. Once you have an active region, you can press the right mouse button again while holding the Shift key to expand or shrink the selected region. If you print without making a selection, then the area of the trace visible in the scope window will be taken as the selection.

After you chosen a region, push the button on the toolbar of the scope window. This will bring up the Scope Print dialog box having an "Output" and a "Content" page. The "Output" page of this dialog box is the same as the "Output" page of the dialog box used to print circuits.

If you choose the "Save as Encapsulated Postscript" option, the "Content" page will be disabled, and the selected region of the trace will be written as a single Encapsulated Postscript figure suitable for inclusion in a document (e.g., by Latex).


(Click to Enlarge)

Figure 5.7: Scope Print Dialog Box
The "Content" page (Figure 5.7) is divided into a "Range Selection" and a "Scale Selection" portion. The Range Selection portion has a selector to modify the start time of the trace plot, and the range of the selected region in the trace. A diagram showing the total amount of trace data available (in green), and the region selected for printing (in gray) is shown to the right of the selectors.

The "Scale Selection" allows you to set the amount of time to plot per line when generating output. You must be cautious to set this carefully, as too low a setting can result in trace output with a huge number of pages. To help you in setting this value, an estimate of the number of pages needed is displayed next to this selector. The default value for the "Line Length" is one full scale of the scope window at the current zoom setting.

5.3 Controlling the Input

There are two types of built-in circuit elements that can be used to control your circuit: the single-bit switch, the multi-bit dip switch. You can also provide input through VPDs (Virtual Peripheral Devices). An important VPD that is included with TkGate is the TTY which will also be described in this section.

5.3.1 Switches and Dip Switches



Figure 5.8: Dip Value
Dialog Box



Figure 5.9
TTY Device

Switches can be manipulated by simply clicking on them to toggle their values. To change a dip switch value, click on the dip switch to open the dip value dialog box for setting the value of that dip switch. Then, enter a value in the entry area, and press the "Apply" button to set the switch. The value should be a hexadecimal number. The dip value dialog box will remain open until you hit "Close", and you can open as many at once as you like.

5.3.2 TTYs

In versions of TkGate before version 2.0, the TTY device was built into TkGate as a primitive device. As of version 2.0, the TTY is now implemented as a VPD (Virtual Peripheral Device). In order to use the TTY device, you must open the Library Manager and load the "tty" library. You can then create a module of type "TTY" in your design in the same way that you would create a module instance for any other module. Figure 5.9 shows an example of a TTY device. Note that it is displayed in the magenta color of a module, rather than the blue color of built-in devices. See the section on the TTY Library Component for information on how to use this device.

5.4 Setting Breakpoints


(Click to Enlarge)

Figure 5.10: Simulator Console Breakpoint Page
Breakpoints can be used to set conditions which will cause a continuously running simulation to pause. To display the breakpoints, press the tab on the simulator console as shown in Figure 5.10. To add a new breakpoint, press the "Add..." button or double click on the next empty slot under "Condition". You can enter any valid Verilog expression as the breakpoint condition. You can edit the expression of a breakpoint by double clicking on the expression.

Breakpoints will be activated for any non-zero value of their condition expression. When one of the registered breakpoints is activated, the simulation will stop, and a symbol will appear in the "S" column of the breakpoint. Breakpoints are only triggered on transitions. If you press the button to resume the simulation, the simulation will continue until the breakpoint expression makes a new transition to a non-zero value.

The "ID" column of the breakpoint list indicates an identifying number for the breakpoint. The column labeled "S" indicates the state of the breakpoint. The state is indicated by one of the following symbols:

StateDescription
Error - There is an error such as a syntax error or undefined variable error in the breakpoint expression.
Go - The breakpoint is active, but has not been tripped.
Stop - The breakpoint has tripped, and simulation is stopped at this breakpoint.
Disabled - The breakpoint has been temporarily disabled.
Stand By - The breakpoint is ready and will be active when the simulator starts.

The "Value" column shows the current value of the breakpoint expression. If the expression is binary, the value will be a 1 or 0, but if it is a multi-bit expression, then it could be an arbitrary value.

There are two buttons to "Enable" and "Disable" a breakpoint. While a breakpoint is disabled, the breakpoint will remain in the breakpoint list, but its value will be ignored until you re-enable it.

5.5 Initializing Memories

A circuit can contain one or more memories (ROM and RAM gates). You can initialize memories from a file, or dump the contents of a memory to a file. The following toolbar buttons can be used to load or dump memories.

ButtonDescription
Load Memory - Load memories from the selected file. If a memory gate is selected, that memory will be the default memory to load. If the memory file contains one or more "memory" keywords, the specified memory(ies) will be loaded with the contents of the file. When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched.
Dump Memory - Dumps the contents of the selected memory to a file.

Memory files have the extension ".mem" be default. The default format for memory files is slightly different between Version 2.0 memory files, and pre-2.0 memory files, but TkGate 2.0 can read files from either format.

A memory file is composed lines that can contain commands, or memory data. Blank lines and lines beginning with '#' are ignored. The supported commands are:

CommandDescription
@memory nameMemory data after this line will be loaded into the memory given by name. Name should be the fully qualified Verilog name of the memory comprised of a "." separated list of the modules down to the module in which the memory is located. The "@" for this command only can be omitted, since that is the pre-2.0 style for this command.
@radix radixSpecify the radix to use for memory data after this line. The radix can be 2, 8, 10 or 16 with 16 being the default.
@addrSpecifies the address at which to begin loading data. The address should be a hexadecimal number.

Lines that do not contain one of the above commands are assumed to be data in the current radix. For files loaded through the interface, the radix is assumed to be hexadecimal, but can be changed with the @radix command. For files loaded through the Verilog $readmemh system task, the assumed radix is hexadecimal, and for files loaded through the $readmemb system task the assumed radix is binary.

Here is an example of a memory file: 

@100
e1 f0 0 0 e1 e0 0 0
81 0 0 0 12 1 bd 0

@200
e 1 e1 d0 dc 7 85 0
This file will load 16 bytes starting at address 100, then an additional 8 bytes at address 200 (assuming the memory is declared as an 8-bit wide memory).

Old style memory files use a slash after an address to indicate where to load data. For example: 

130/ 2 0 ed 0 60 6 62 6
138/ ed 0 5e 6 1 0 85 0
140/ 81 0 0 0 26 4 69 f0
Here the 130, 138 and 140 are the address in hexadecimal. You can use either syntax in your memory files.

In the above examples, there was no explicit mention of the target memory. For that reason, those file can only be loaded when you explicitly indicate the target memory either by clicking on before pressing , or by specifying the memory as an argument in the $readmemh or $readmemb system task.

Using the @memory command, you can specify the memory (or memories) to be loaded within the file itself. The memory keyword requires a single argument specifying the name of a memory. For example: 

@memory memory.m1
@100
e1 f0 0 0 e1 e0 0 0
81 0 0 0 12 1 bd 0

@memory memory.m2
@100
62 65 61 6b 20 69 73 0a
This memory file will load 16 bytes of data into the memory "m1" in the instance named "memory" which is a sub-module of the root module. It will also load 8 bytes into the memory "m2" in the same module as "m1".

You can also use the "x" and "z" characters in any digit of data values specified in a memory file to indicate unknown or floating values. For example: 

@100
10 x 8x 3e z9 3a zx 9x
will load a memory that includes unknown and floating values.

For RAM memories, the contents of the loaded memory are frozen until first time the write line transitions to a stable value (logic 0 or 1). This prevents the data loaded from being destroyed due to unknown values on the write and address lines until the circuit has time to initialize these signals.

5.5.1 Using GMAC to Create Memory Files

In many cases, memory files are initialized to act as microstores or to contain machine instructions for a user designed processor. In these cases, it is very tedious and error prone to explicitly specify the contents of the memory. For this reason, TkGate includes a tool, gmac, for compiling microcode and macrocode to TkGate-compatible memory files. Complete documentation on Gmac is given in a later section of this document.

5.6 Simulation Scripts


(Click to Enlarge)

Figure 5.11: Simulator Console Script Manager Page
Simulation scripts are useful for setting up a simulation before starting, or for running a simulation in batch mode. You can perform most of the operations you can do manually through the interface including setting and remove probes, changing switch values, loading memories, setting breakpoints, and stepping the simulator.

Simulator script files use Verilog syntax. This section will give some simple examples of how to write scripts. More detailed information on Verilog format can be found in the chapter on Verilog Modules.

5.6.1 Loading Simulator Scripts

To load a simulator script, first press the tab on the simulator console. You can then press the "Add..." button or double click on the next empty slot. The default extension for simulation scripts is ".vs". When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched.

You can also arrange for simulation scripts to be automatically executed when you start the simulator by adding one or more simulation scripts in the circuit options dialog box.

The "S" column next to each simulator script indicates the state of the script. The state is one of the following:

StateDescription
Error - There is an error such as a syntax error or undefined variable error in the script.
Go - The script is active and running.
Stop - The script has completed executing.
Disabled - Execution of the script is disabled.
Stand By - The script is ready and will execute when the simulator is started.

5.6.2 Simulator Script Format

Simulator scripts are fragments of Verilog code assumed to be defined in the context of the body of the top-level module. You can create one or more parallel threads as well as declare local variables for use within the script.

Most scripts are defined as a Verilog initial block. For example: 

  initial
    begin
      $readmemh("test.mem");    // Load memory file "test.mem".
      $tkg$probe(a, b, c);      // Place probes on the signals a, b and c.
      repeat (5)                // Advance the simulator 5 steps of the
        @ (posedge clock);      //    clock named 'clock'.
      # 10;                     // Advance the simulator 10 epochs.
      $stop;                    // Stop the simulator and put it in "pause" mode.
    end
If you define multiple initial blocks in your script file, each block will execute in parallel. You can also use always blocks which execute their bodies in an infinite loop.

You can also define local variables in a simulator script. For example: 

  integer i;

  initial
    begin
      for (i = 0;i < 10;i = i + 1)        // Loop ten times
        begin
          @ (posedge clock);              // Advance to rising edge of "clock".
          $display("%t: x=%h",$time,x);   // Print time and value of x signal.
        end
      $stop;                              // Pause the simulator.
    end
This example will step for 10 clock periods and print the value of the x signal in the simulator console at each of those clock periods.

5.6.3 Setting Signal Values


Figure 5.12: Full Adder Circuit
You can set the value of any register variables in a module using an assignment statement with the "=" operator. For netlist modules, any nets that are attached to a switch or a dip element are considered register variables. However, unlike in TkGate 1.8 script files, you must use the name of the wire, and not the name of the switch itself. For example, the following script will set probes on the inputs and output of the circuit shown in Figure 5.12, then step through each combination of inputs with a delay of 50 epochs after we set the input values: 

  initial
    begin
      $tkg$probe(a,b,ci,s,co);
      ci = 0; a = 0; b = 0;
      #50 ci = 0; a = 0; b = 0;
      #50 ci = 0; a = 0; b = 1;
      #50 ci = 0; a = 1; b = 0;
      #50 ci = 0; a = 1; b = 1;
      #50 ci = 1; a = 0; b = 0;
      #50 ci = 1; a = 0; b = 1;
      #50 ci = 1; a = 1; b = 0;
      #50 ci = 1; a = 1; b = 1;
    end
Note that the left hand side of each assignment statement is a wire name. For example, a is used instead of the name of the switch (g25) to which it is attached. The right-hand side of assignment statements can be arbitrary expressions referencing variables declared in the simulation script and any nets in the design.

You can use fully qualified path names to set the value of switches/nets at levels other than the top level. For example: 

    top.memctl.ttyreg = 8'h
will set the value of ttyreg in the module instance memctl which is instantiated in the top-level module.

5.6.4 Commonly Used System Tasks

Scripts can make calls to system tasks to perform various useful functions. Systems tasks begin with a "$" and are used somewhat like function calls. A complete description of system tasks are given in the System Tasks Appendix. Some of the system tasks that are frequently used in scripts are:
TaskDescription
$display(arg1, arg2, ...) Display messages to the simulator console. Similar to the C printf in functionality.
$readmem(filename [, memory [, start [, stop]]]) Loads the contents of a memory file to one or more memories.
$tkg$probe(sig1, sig2, ...) Places probes on the specified signals.
$tkg$unprobe(sig1, sig2, ...) Removes probes from the specified signals.
$stop Stop the simulation and put it into "paused" mode.
$finish Terminate the simulation and return to "edit" mode.
$random[(seed)] Return a random number, or set the seed if an argument is given.
$time Return the simulation time in epochs as a 64-bit integer.
$tkg$systime Returns the actual system time in milliseconds since January 1, 1970 as a 64-bit integer.

5.6.5 Using Scripts for Test Vector Generation

Another method for using scripts is to generate random test vectors. For example, suppose we wish to test a 32-bit adder that we have designed. The following script will apply 10,000 random vectors to the design and check them against the answer calculated in the script. When a mismatch between the circuit output and the expected output is found, an error message is displayed, and the simulation is paused so the user can view internal signal values. 
  reg tempCout;                                    // Declare 1-bit variable for carry out
  reg [31:0] tempS;                                // Declare 32-bit variable for sum
  integer i;                                       // Declare index variable

  initial
    begin
      $random($tkg$systime);                       // Use system clock to set random seed
      for (i = 0;i < 10000; i = i + 1)             // Loop 10,000 times
        begin
          a = $random;                             // Pick random value for A
          b = $random;                             // Pick random value for B
          cin = $random;                           // Pick random value for carry-in

          # 50;                                    // Step 50 epochs

          tempCout = (33'h0 + a + b + cin) >> 32;  // Get correct carry out value
          tempS = a + b + cin;                     // Get correct sum value

          //
          // If output from the design is not as expected, print an error message
          // and stop the simulator. 
          //
          if ({cout,s} != {tempCout,tempS})
            begin
              $display("error: got 31'h%h + 31'h%h + 31'h%h = {1'h%h, 31'h%h}",a,b,cin,cout,s);
              $display(" -- should have gotten {1'h%h, 31'h%h}", tempCout, tempS);
              $stop;
            end
        end

      $display("test completed.");
      $stop;
    end

5.7 Using the Error Reporter


(Click to Enlarge)

Figure 5.13: Simulator Error List
If there are any errors in the circuit when you start the simulator, an error list box will appear as shown in Figure 5.13. Click on an error message to gave TkGate show you the location of the error. If the error is in a netlist module, TkGate will navigate to the module and place cross-hairs over the as shown in Figure 5.14. If the error is in an HDL module, then the line with the error will be highlighted.


Figure 5.14: Error Location Cross-hairs

In the example shown here, the module "ADD32" had an internal port name of "a", but the name "A" was erroneously used on the interface. The first error message indicates that the external port name "A" does not have a corresponding port inside, and the second error message indicates that the internal port "a", does not have a corresponding port on the outside.

5.8 Gate Delay Files

Gate delay, area and power (power specifications are not used) parameters can be specified through a collection of gdf (Gate Delay File) specification files. The default file "gdf/default.gdf" in the TkGate home directory is always loaded, but the definitions may be replaced by loading additional delay files through the Simulate Options dialog box.

Each gate delay file should contain one or more technology blocks having the form: 

technology cmos {
  ...
}
Technology blocks implement a new set of delay parameters and the specified technology name becomes a name that can be specified as a technology through the "Delay" page of the gate properties box. The body of the technology block should consist of a set of gate primitive declarations. Each gate primitive should be described in a block defining all the delay and possible area and power parameters of the block in terms of number of inputs, bit-widths of inputs and existence of inverters on inputs. For example, the block for the "mux" primitive might look like: 
primitive mux {
  delay<I-Z> = (2*(num(S)+1) + 2*num(I)) + 2*(inv(I) || inv(Z)); 
  delay<S-Z> = (2*(num(S)+1) + 2*num(I));
  area = bits(Z)*((2*(num(S)+1) + 2*num(I)) + 2*inv(I)); 
}
The two "delay" lines define the delay from the input to the output (I-Z) and from the select to the output (S-Z), respectively. The area line defines the estimated area of the gate. Expressions may include the C-style operators "+", "-", "*", "/", "&&", "||", "==", "!=", ">", ">=", "<", "<=", and "!", the "power of" operator "**" and the functions listed in the table below.

FunctionDescription
num(p) Normally, "p" specifies a group of related ports in which case this function returns the number of ports in the group. For example, on an n-input AND gate with inputs I1 through In, the expression num(I) would return n.
bits(p) Returns the number of bits on the specified port. If "p" represents a group of ports, the highest bit-width of the group is returned.
inv(p) When "p" is specific port, a 1 is returned if there is an inverter on the port, 0 otherwise. When "p" specifies a group of ports, the number of ports with inverters is returned.
log(expr)Returns the ceiling of the base-2 log of an expression.

It is also possible to write procedural delay/area definitions. For example, consider the parameter specification for the "and" primitive. 

primitive and {
  delay<I-Z> = {
    if ((inv(I) == num(I)))     // Determine if an inverter is necessary.  An
      d = inv(Z);               //   inverter is not required if the output is
    else if ((inv(I) == 0))     //   inverting and all inputs are non-inverting
      d = !inv(Z);              //   (i.e., it is an AND gate), or if all inputs
    else                        //   are inverting and the output is non-inverting
      d = 1;                    //   (i.e., it is a NOR gate). 

    if (num(I) == 1) {          // If one input, treat this as a reduction gate    
      return 2*bits(I0) + 2*d;  //   one Tr. delay per bit plus inverter delay.    
    } else {                    // If multiple inputs, treat this as a normal gate 
      return 2*num(I) + 2*d;    //   one Tr. delay per input plus inverter delay.  
    }
  }

  area = {
    if ((inv(I) == num(I)))     // Estimate number of inverters required.  If all
      d = inv(Z);               //   inputs are inverted, an inverter is required
    else if ((inv(I) == 0))     //   iff the output is inverted.  If all inputs
      d = !inv(Z);              //   are non-inverted, an inverter is required iff
    else                        //   the output is non-inverted.  Otherwise we need
      d = inv(I);               //   an inverter for each inverted input.

    if (num(I) == 1) {          // If one input, treat this as a reduction gate    
      a = 2*bits(I0) + 2*d;	//   one Tr. per bit plus inverter Trs.    
    } else {			// If multiple inputs, treat this as a normal gate 
      a = 2*num(I) + 2*d;	//   one Tr. per input plus inverter Trs.  
    }
    return bits(Z)*a;           // Multiply by number of bit slices.
  }
}
In a procedural specification, statements are executed sequentially until a "return" statement sets the value for the parameter. C-style if and switch statements may be used in procedural specifications, but there are no looping constructs.

A technology block need not specify every single primitive type. For example, suppose we have a technology definition for CMOS which includes a definition for a buffer as shown here: 

technology CMOS {
  primitive buf {
    delay<I-Z> = 2 + 2*(inv(I) == inv(Z));
    area = bits(Z)*(2 + 2*(inv(I) == inv(Z)));
  }
  ...rest of CMOS definition...
}
We might create a special technology definition "HP_CMOS" which contains high-power versions of a subset of the standard CMOS gates. In the example here, we provide a special high-power buffer that has the delay of a standard buffer, but twice the area (and power). 
/*
 * A high-power buffer with half the delay and double the area/power.
 */
technology HP_CMOS {
  primitive buf {
    delay<I-Z> =  1 + (inv(I) == inv(Z));
    area = 2*bits(Z)*(2 + 2*(inv(I) == inv(Z)));
  }
}

If you assign the technology type HP_CMOS to any gates for which there is no primitive definition, delay values from the technology "default" will be used.

The table below lists all of the primitive gates for which delay may be specified and their delay parameters. The default values given are the values for a "basic" gate created from the "Make" with no changes to the number of inputs, input/output inverters, or bit widths of any of the ports.

Gate TypeParameterDefaultDescription
and I-Z 6Delay from input to output.
or I-Z 6Delay from input to output.
xor I-Z 8Delay from input to output.
buf I-Z 4Delay from input to output.
bufif1 E-Z 4Delay from enable to output.
I-Z 6Delay from data input to output.
nmos I-Z 2Delay from data input to output.
G-Z 1Delay from gate to output.
pmos I-Z 2Delay from data input to output.
G-Z 1Delay from gate to output.
add A/B-S 68Delay from operand input to sum.
A/B-CO 70Delay from operand input to carry out.
CI-S 62Delay from carry in to sum.
CI-CO 64Delay from carry in to carry out.
register setup 10Time before clock edge data-in must be stable.
hold 10Time after clock edge data-in must remain stable.
CK-Q 20Time from clock edge until output changes.
mux S-Z 8Delay from select line to output.
I-Z 8Delay from data input to output.
demux E-Z 6Delay from enable line to output.
I-Z 6Delay from data input to output.
mult A/B-P 252Delay from operand input to output.
div A/B-Q 236Delay from operand input to quotient.
A/B-R 236Delay from operand input to remainder.
ram OE-D 10Delay from output enable to data-out.
CS-D 10Delay from chip select to data out.
A-D 70Delay from the address line to the data out.
addr_setup 10Time before write is asserted that address must be stable.
data_setup 10Time before write is asserted that data-in must be stable.
addr_hold 10Time after write is unasserted that address must remain stable.
data_hold 10Time after write is unasserted that data-in must remain stable.
rom OE-D 10Delay from output enable to data-out.
A-D 50Delay from address to data-out.
lshift S-Z 16Delay from shift select to output.
I-Z 18Delay from data-in to output.
rshift S-Z 16Delay from shift select to output.
I-Z 18Delay from data-in to output.
arshift S-Z 16Delay from shift select to output.
I-Z 18Delay from data-in to output.
roll S-Z 16Delay from shift select to output.
I-Z 18Delay from data-in to output.
tkgate-2.0-b10/doc/index.html000644 001751 001751 00000015463 10652371240 016561 0ustar00hansenhansen000000 000000 TKGate User Documentation (Index)

TKGate 2.0

Copyright (C) 1987-2007 by Jeffery P. Hansen

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

TkGate is a graphical editor and  event-driven simulator for digital circuits with a tcl/tk-based interface.  Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors.  Hierarchical design is also supported with support for user defined modules.  Save files are based on the Verilog netlist format.
 

Contents:

  1. Introduction to TkGate
  2. Using the Editor
  3. Working with Modules
  4. HDL Modules
  5. Using the Simulator with TkGate
  6. Gate Microcode and Assembly Compiler (gmac)
  7. Making Virtual Peripheral Devices (VPDs)
  8. Setting TkGate Options
  9. TkGate Library Components
Appendices
  1. List of Built-In Gate Types
  2. List of System Tasks
  3. List of Simulator Error Messages
  4. Using the Verga Simulator in Stand-Alone Mode
  5. Sample Gmac Input File
    tkgate-2.0-b10/doc/menagerie.gm000644 001751 001751 00000132563 07311226663 017054 0ustar00hansenhansen000000 000000 // // Copyright (C) 1987-2000 by Jeffery P. Hansen // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; either version 2 of the License, or // (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. // // Last edit by hansen on Fri Dec 1 14:34:44 2000 // // Microcode memory bank declarations microcode bank[31:0] iunit.m1; microcode bank[63:32] iunit.m2; map bank[7:0] iunit.map; macrocode bank[7:0] memory.m1; // Microcode field declarations // // Microcode branching. mpcop specifies the basic operation. // field mpcop[1:0]={ next=0, // Increment mpc reinit=1, // Restart CPU jmap=2, // Jump from map value jump=3 // Jump from condition }; // // Specifies the condition on which to jump if mpcop is "jump". // field mpccond[12:10]={ jne=0, // Jump if not equal jcarry=1, // Jump on carry jeq=2, // Jump if equal jlt=3, // Jump if less than jgt=4, // Jump if greater than jle=5, // Jump if less than or equal jge=6, // Jump if greater than or equal jmp=7 // Jump always }; // // Address to jump to if mpcop is "jump" and condition specified // by mpccond is true. This field can not be used at the same // time as the idata field. // field mpcaddr[9:2]; // // Specifies 8 bits of data to be used by the EUNIT. This field // can not be used on jump microinstructions. // field idata[9:2]; // // Specifies the A and B operands of the ALU. // // qreg Use Q register // din Use data in // idata Use idata field from microinstruction // reg Use register file // field aop[15:14]={qreg=0, din=1, idata=2, reg=3}; field bop[17:16]={qreg=0, din=1, idata=2, reg=3}; field ~ldir[13]; // Load instruction register field cin[18]; // Carry in field ~clq[19]; // Clear Q register field ~ldq[20]; // 16-bit load of Q register field ~lddata[21]; // Load EUNIT data from external bus field ~ldopr[22]; // Load operand register field ~wa[23]; // Write register file on SA field sa[27:24]; // Register address A field sb[31:28]; // Register address B // // These fields specify the ALU function. // field ALU_FUNC[36:32]; field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3}; field ALU_BCOMP[32]; field ALU_AZERO[33]; field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7}; field ~incpc[37]; // Increment PC field ~ldmar[38]; // Load MAR field ~ldmdr[39]; // Load MDR field ~ldpc[40]; // Load PC field ~rd[41]; // Read main memory field ~rdmdr[42]; // Read MDR onto external data bus field ~wrt[43]; // Write main memory field spc[44]; // Address main memory from PC field ~isa[45]; // Use sa address from macro instruction field ~isb[46]; // Use sb address from macro instruction field ~ifunc[47]; // Use function code from macro instruction field ~icond[48]; // Use branch condition from macro instruction field ~ldql[49]; // 8-bit load of lower half of Q register field ~ldqh[50]; // 8-bit load of upper half of Q register field ~dout[51]; // Output EUNIT data to external bus field ~ldcc[52]; // Load condition code register field ~ldhmdr[53]; // Load mdr from high byte of data bus field ~rdpc[54]; // Read PC onto external bus field ~incmar[55]; // Increment mar (can't use with incpc) field extra[63:56]; // Extra bits ////////////////////////////////////////////////////////////////////// // // +-+-+-+-+-+-+-+-+ // |7|6|5|4|3|2|1|0| // +-+-+-+-+-+-+-+-+ // // Basic instruction types are encoded by the high two bits of the // first byte of the instruction. For certain types (e.g., ALU // types) some bits are masked when forming the map address. Bits // contributing to the map vector are marked with a *. // // Move Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 1 1 s|a a|b b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // s = size (1 = byte, 0 = word) // aa = operand mode 1 // bb = operand mode 2 // // Single operand instruction (push, pop, call, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0| op |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // // Branch instruction (jmp, jne, etc.) // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|cond |b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * // // // ALU Instruction // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1| func |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * // // func = ALU function // a = operand mode // // Other instructions // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0| op |b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // * * * * * * * * // // registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15; operands basic { %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands runiop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; #1 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; operands wuniop { %1 = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; }; (%1) = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; }; #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; }; // // Operands for move instructions // operands movoprs { %1,%2 = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; %1,#2 = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; %1,(%2) = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; %1,#3(%2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; %1,(#2) = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),%2 = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#2 = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; (%1),(%2) = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; }; (%1),#3(%2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; (%1),(#2) = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; }; #1(%2),%3 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#3 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; #1(%2),(%3) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; }; #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; }; #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),%2 = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#2 = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; (#1),(%2) = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; }; (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; }; (#1),(#2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|1 1 1 1 1|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op nop { map nop : 0x3e; +0=0x3e; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op halt { map halt : 0x0; +0=0; operands { - = { +1=0; }; }; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 0 1|0| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // op cmp { map cmp_rr : 0x2; map cmp_ri : 0x3; +0[7:1]=0x1; operands basic; }; // Generic branch operation // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|1|x x x|b b| |0 0 0 0| reg1 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // br #7, loop // // Jump always to loop. 7 is a code indicating the condition always. // op jp { map br_r : 0xa0; map br_i : 0xa1; map br_d : 0xa2; map br_x : 0xa3; +0[7:5] = 0x5; operands { #1,%2 = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#2 = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; }; #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; }; }; }; op jne { +0[7:5] = 0x5; +0[4:2] = 0x0; operands runiop; }; op jcarry { +0[7:5] = 0x5; +0[4:2] = 0x1; operands runiop; }; op jeq { +0[7:5] = 0x5; +0[4:2] = 0x2; operands runiop; }; op jlt { +0[7:5] = 0x5; +0[4:2] = 0x3; operands runiop; }; op jgt { +0[7:5] = 0x5; +0[4:2] = 0x4; operands runiop; }; op jle { +0[7:5] = 0x5; +0[4:2] = 0x5; operands runiop; }; op jge { +0[7:5] = 0x5; +0[4:2] = 0x6; operands runiop; }; op jmp { +0[7:5] = 0x5; +0[4:2] = 0x7; operands runiop; }; // Generic ALU operation // // Note this is not a real instruction but is here for illustrative // purposes only. Map entries must be made for each function code // to use this instruction for real. // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|x x x x x|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // alu #0x14, R1, R2 // // Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1. // //op alu { // map alu_rr : 0x40; // map alu_ri : 0x41; // +0[7:6] = 0x1; // operands { // #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; }; // #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; }; // }; //}; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op add { map alu_rr : 0x68; map alu_ri : 0x69; +0[7:0]=0x68; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 1 0 1|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op sub { map alu_rr : 0x6a; map alu_ri : 0x6b; +0[7:0]=0x6a; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 0 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mul { map xalu_rr : 0x60; map xalu_ri : 0x61; +0[7:0]=0x60; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 1 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op div { map xalu_rr : 0x78; map xalu_ri : 0x79; +0[7:0]=0x78; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|1 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op mod { map xalu_rr : 0x70; map xalu_ri : 0x71; +0[7:0]=0x70; operands basic; }; // // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 1|0 1 0 0 0|b| | reg1 | reg2 | // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // op and { map alu_rr : 0x50; map alu_ri : 0x51; +0[7:0]=0x50; operands basic; }; // Call subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 0|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // call foo, #8 // // This will perform the following actions: // sp = sp - 2 // [sp] = pc // sp = sp - 2 // [sp] = fp // fp = sp // sp = sp+8 // pc = foo // op call { map call_ri : 0x80; map call_ii : 0x81; map call_di : 0x82; map call_xi : 0x83; +0[7:4] = 0x8; operands { #1,%2 = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2 = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1,(%2) = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; }; #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; }; #1 = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; }; }; }; // Return from subroutine // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |0 0|0 0 0 1 0|0| |0 0 0 0|0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // ret // // This will perform the following actions: // sp = fp // fp = [sp] // sp = sp + 2 // pc = [sp] // sp = sp + 2 // // op ret { map ret : 0x4; +0=4; operands { - = { +1=0; }; }; }; // Push a word on the stack // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ // |1 0|0|0 0 1|b b| | reg1 |0 0 0 0| // +-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ ... // // Example: // // pushw R1 // op pushw { map pushw_r : 0x84; map pushw_i : 0x85; map pushw_d : 0x86; map pushw_x : 0x87; +0[7:2]=0x21; operands runiop; }; op movb { map movb_rr : 0xf0; map movb_ri : 0xf1; map movb_rd : 0xf2; map movb_rx : 0xf3; map movb_dr : 0xf8; map movb_di : 0xf9; map movb_dd : 0xfa; map movb_dx : 0xfb; map movb_xr : 0xfc; map movb_xi : 0xfd; map movb_xd : 0xfe; map movb_xx : 0xff; +0[7:4]=0xf; operands movoprs; }; op movw { map movw_rr : 0xe0; map movw_ri : 0xe1; map movw_rd : 0xe2; map movw_rx : 0xe3; map movw_dr : 0xe8; map movw_di : 0xe9; map movw_dd : 0xea; map movw_dx : 0xeb; map movw_xr : 0xec; map movw_xi : 0xed; map movw_xd : 0xee; map movw_xx : 0xef; +0[7:4]=0xe; operands movoprs; }; ///////////////////////////////////////////////////////////////////////////// // // The microcode for the Menagerie CPU begins here. // // The CPU begins executing microinstuctions at address 0. The instructions // in the start block are executed only once. The next block consists of // the instuction fetch sequnce. The multiple labels account for partial // fetches that are done by some of the macrocode routines. // // For macro instructions which have no operands or have only only one operand, // there is usually a plain label for that instruction. For example the // microinstruction labeled 'ret' implements the 'ret' macroinstruction. This // mapping is defined by the 'map ret : 0x4;' line in the operand declaration // for the ret macroinstruction. // // For macro instructions with multiple addressing modes, labels are generally // of the form 'op_??' where each character after the '_' denotes an addressing // mode for an operand. By convension, the characters: // // r register direct // i immediate // d register indirect // x indexed // // are used. // begin microcode @ 0 start: clq; // Q <- 0 idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh; // Q.H <- 1 ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to 'fetch' mpcop=next; fetch: incpc spc rd ldmdr; // mdr <- [PC]; PC++; fetch1: incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; fetch2: mpcop=jmap rdmdr ldopr; // opr <- mdr; jump to opcode mpcop=next; halt: mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1; // // Standard ALU operations (add, sub, and, or, etc.) // alu_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; alu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; // // 2-cycle ALU operations (mul, div, mod). These are the same as the alu_?? // ops except the ALU inputs and function code are held for 2 clock cycles // due to the longer delay in computing these functions. // xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg; // Ra (op) Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr; // Ra = Ra (op) Rb; CC; jump to fetch incpc spc rd ldmdr rdmdr ldir; xalu_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=next ifunc isa isb aop=reg bop=qreg; // Ra (op) Q; mpcop=jump mpccond=jmp mpcaddr=fetch ifunc aop=reg bop=qreg wa isa ldcc; // Ra = Ra (op) Q; CC; jump to fetch mpcop=next; cmp_rr: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22 isa isb aop=reg bop=reg ldcc; // Ra - Rb; CC; jump to fetch mpcop=next; cmp_ri: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP aop=reg bop=qreg isa ldcc; // Ra - Q; CC; jump to fetch mpcop=next; br_i: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; btest: mpcop=jump mpcaddr=bdojmp icond; // jump to bdojmp if cond mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch; // jump to fetch mpcop=next; bdojmp: mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add bop=qreg dout ldpc; // PC <- Q, jump to fetch mpcop=next; br_r: mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10 isa aop=reg sb=0 bop=reg ALU_OP=add ldq; // Q <- Ra; jump to btest mpcop=next; br_d: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; br_x: mpcop=jump mpccond=jmp mpcaddr=btest; mpcop=next; call_ii: // Push the PC aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa extra=0x11; // SP-2 -> mar; SP = SP - 2; rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq; // Q = PC+4 ALU_AZERO ALU_OP=add bop=qreg dout ldmdr; // Q.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr; // Q.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; mpcop=next; // Push the FP aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP dout ldmar wa; // SP-2 -> mar; SP = SP - 2; ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr; // FP.L -> mdr wrt; // [mar] <- mdr; incmar ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldhmdr; // SP.H -> mdr; mar++; mpcop=next; wrt; // [mar] <- mdr; aop=reg sa=0xe bop=reg sb=0xf ALU_AZERO ALU_OP=add wa; // FP <- SP // Dec SP incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=qreg ALU_OP=add wa; // SP = SP + Q // PC = branch address incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q mpcop=next; call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_di: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch; mpcop=next; ret: ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12; // SP <- FP; mar <- FP; aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr; // SP <- SP+4; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr; // FP <- Q; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr; // Q.L <- mdr; mdr <- [mar++] ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch1 ALU_AZERO bop=qreg ALU_OP=add dout ldpc; // PC <- Q; jump fetch1 incpc spc rd ldmdr; // mdr <- [PC]; PC++; pushw_d: mpcop=next; pushw_x: mpcop=next; pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Rb.L; wrt; // [mar] <- mdr; aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; pushw_i: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP extra=0x13 dout ldmar wa; // mar <- SP-2; SP = SP - 2; aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr; // mdr <- Q.L; wrt; // [mar] <- mdr; aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add isa isb wa aop=reg bop=reg ldcc extra=1 incpc spc rd ldmdr; // Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldir; // mdr <- [PC]; PC++; ir <- mdr; movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql; // Q.L <- Rb; mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata ALU_OP=add ldqh incpc spc rd ldmdr; // Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++; ALU_AZERO ALU_OP=add bop=qreg isa wa incpc spc rd ldmdr rdmdr ldir; // Ra <- Q; mdr <- [PC]; PC++; ir <- mdr; movw_ri: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_ri:incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0; // Q.H = 0; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO aop=reg bop=qreg wa isa ldcc; // Ra = Q; CC; jump to fetch mpcop=next; movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mbrd: rd ldmdr; // mdr <- [mar] mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa; // Ra <- mdr ALU_OP=add idata=0 bop=idata aop=reg isa ldcc; // CC movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout extra=3; // mar <- Rb _mwrd: rd ldmdr incmar; // mdr <- [mar++] rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql; // Q.L <- mdr; mdr <- [mar++] lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh; // Q.H <- mdr; mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg ALU_OP=add isa wa ldcc; // Ra <- Q; CC mpcop=next; movb_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mbrd isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q; movw_rx: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; isb aop=qreg bop=reg ALU_OP=add ldmar dout; // mar <- Rb+Q movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mbdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc; // mar <- Ra _mwdr: isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout; // mdr <- Rb.L wrt; // [mar] <- mdr; isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Rb.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mbdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xr: incpc spc rd ldmdr extra=9; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; jump to _mwdr isa aop=reg bop=qreg ALU_OP=add ldmar dout ldcc; // mar <- Ra+Q movw_xx: mpcop=next extra=7; movb_xx: mpcop=next extra=7; movw_xd: mpcop=next extra=7; movb_xd: mpcop=next extra=7; movw_dd: mpcop=next extra=7; movb_dd: mpcop=next extra=7; movw_dx: mpcop=next extra=7; movb_dx: mpcop=next extra=7; mpcop=next extra=7; movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar; // mar <- Ra _mwdi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L wrt; // [mar] <- mdr; aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar; // mdr <- Q.H; mar++; mpcop=next; mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra _mbdi: incpc spc rd ldmdr; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout; // mdr <- Q.L mpcop=jump mpccond=jmp mpcaddr=fetch wrt; // [mar] <- mdr; jump to fetch mpcop=next; movw_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q movb_xi: incpc spc rd ldmdr extra=2; // mdr <- [PC]; PC++; incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din; // Q.H = mdr; goto _mwdi isa aop=reg bop=qreg ALU_OP=add dout ldmar; // mar <- Ra+Q nop: mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15; mpcop=next; end ///////////////////////////////////////////////////////////////////////////// // // General notes on assembler // Registers are not saved accross function calls unless explicitly saved. // Functions return values in R1. // The register R0 is a special "always 0" register. Writing to R0 will have no // effect other than to set condition codes. // // begin macrocode @ 0x100 ttydata: .symbol 0x11 // tty data in/out register ttystatus: .symbol 0x10 // tty status register // // Nodes have the format (note that pointers are two bytes): // // struct node { // struct node *yes_b; // struct node *no_b; // char text[100]; // }; // nsize: .symbol 104 // Size of a tree node. That is "sizeof(struct node)". yes_b: .symbol 0 // Pointer to yes side no_b: .symbol 2 // Pointer to no side text: .symbol 4 // Text of node (animal name or question) // // Execution starts here. // start: movw SP, 0 // Initialize stack pointer movw FP, 0 // Initialize frame pointer call main // Call main program sdone: jmp sdone // Infinite loop when main ends //////////////////// // main() // .proc main movw R13, mend // Use R13 as a sort of heap pointer pushw welcome // Push the "Welcome to" message call printf // Print the message add SP,2 // Restore stack pointer movw (root),top_node // Initialize root node movw (known),1 // Know one animal loop: pushw think // Push the "Think of an animal..." message call printf // Print the message add SP,2 // Restore stack pointer movw R1, (known) // Put number of known animals in R1 pushw R1 // Push that number on the stack pushw numk // Push the "I know %d animals" message call printf // Call printf to print message add SP,4 // Restore stack movw R1,(root) // Put the root pointer in R1 pushw R1 // Push the pointer on the stack call find_animal // Ask questions to find animal add SP,2 // Restore the stack movw (root),R1 // Save new root jmp loop // Go back and guess another animal ret // Return to call (actually we should never get here) .end //////////////////// // find_animal(p) Find the animal. p is the root node in question tree // .proc find_animal tree: .symbol -2 // Local variable for tree pointer sub SP,2 // Allocate space for local variables movw R1, 4(FP) // Get the pointer to top node movw tree(FP),R1 // Store it in "tree" movw R2,yes_b(R1) // Get pointer in "yes" branch of tree cmp R2,0 // Compare against 0 jne get_response // If not 0, then treat as question node pushw R1 // Push pointer to top node call get_final // As the final question, and insert new node if necessary add SP,2 // Restore stack movw tree(FP),R1 // Save new root node in "tree" jmp done // All done, go to final cleanup get_response: movw R1,tree(FP) // Put current node pointer in R1 movw R4,R1 // R4 = R1 add R4,text // Add offset to make R4 pointer to question pushw R4 // Push text of question call print // Print question in tree node add SP,2 // Restore stack pushw qprompt // Push "?" prompt call print // Print the "? " add SP,2 // Restore stack pushw buf // Push address of buffer in which to get response call gets // Read response from user add SP,2 // Restore stack pushw buf // Push users response on stack pushw yes // Push "yes" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_yes // If so, user answered "yes", goto say_yes pushw buf // Push users response on stack pushw no // Push "no" on stack call strcmp // Compare the strings add SP,4 // Restore stack cmp R1,0 // Check if R1 was 0 jeq say_no // If so, user answered "no", goto say_no pushw yesno // Push the "yes or no" error message call print // Print error message add SP,2 // Restore stack jmp get_response // Go back and ask again say_yes: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,yes_b(R1) // Put "yes" branch pointer in R2 pushw R2 // Push the yes branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw yes_b(R2),R1 // Update the "yes" branch jmp done // Finish up and prepare to return to caller say_no: movw R1,tree(FP) // Put current tree pointer in R1 movw R2,no_b(R1) // Put "no" branch pointer in R2 pushw R2 // Push the no branch on the stack call find_animal // Recursively ask the next question add SP,2 // Restore the stack movw R2,tree(FP) // Get tree pointer again movw no_b(R2),R1 // Update the "no" branch jmp done // Finish up and prepare to return to caller done: movw R1,tree(FP) // Put new root node in R1 ret // Return to caller .end //////////////////// // get_final(p) Ask final question (at node p), and update tree if necessary. // .proc get_final tree: .symbol -2 // Local variable for tree pointer animal_node: .symbol -4 // Local variable for new animal node pointer discrim_node: .symbol -6 // Local variable for new question node pointer sub SP,6 // Allocate space for local variables get_response: movw R1, 4(FP) // Get pointer to current node movw tree(FP),R1 // Save it in the 'tree' variable movw R1, 4(FP) // Put pointer to tree in R1 add R1,text // Advance R1 to animal name text pushw R1 // Push pointer to animal name on stack pushw isita // Push the "is it a..." string pointer call printf // Print the final question add SP,4 // Restore stack pushw buf // Push buffer for response call gets // Get the response add SP,2 // Restore the stack pushw buf // Push response on stack pushw yes // Push "yes" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq win // If so, we guessed the animal pushw buf // Push response on stack pushw no // Push "no" on stack call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // See if a 0 was returned jeq loose // If so, we did not guess the animal pushw yesno // Push the "yes or no" error message call print // Print it add SP,2 // Restore stack jmp get_response // Go back and ask again win: pushw winmsg // Push the (computer) win message call printf // Print it add SP,2 // Restore stack jmp done // All done, go finish up and return loose: pushw loosemsg // Push the (computer) loose message call printf // Print it add SP,2 // Restore stack pushw nsize // Push number of bytes in a node call malloc // Allocate memory for new animal node add SP,2 // Restore stack movw animal_node(FP),R1 // Put address of new node in animal_node movw yes_b(R1),0 // Intialize yes branches movw no_b(R1),0 // Intialize no branches add R1,text // Move R1 to point to text area pushw R1 // Push text buffer call gets // Get animal name add SP,2 // Restore stack movw R1,tree(FP) // Put pointer to exiting node in R1 add R1,text // Advance to the text field pushw R1 // Push pointer to old animal name movw R1,animal_node(FP) // Put pointer to new node in R1 add R1,text // Advance to the text field pushw R1 // Push new animal name on stack pushw dscrim // Push "what is difference" question call printf // Print the question add SP,6 // Restore pointer pushw nsize // Allocate memory for discrimination node call malloc // Allocate memory for new discrimination node add SP,2 // Restore stack movw discrim_node(FP),R1 // Put address of new node in discrim_node add R1,text // Advance pointer to text field of discrimination node pushw R1 // Push pointer to text buffer to input question call gets // Input the question add SP,2 // Restore pointer movw R1, (known) // Put number of known animals in R1 add R1,1 // Increment R1 movw (known),R1 // Store number of known animals back in "known" L1: movw R1,animal_node(FP) // Put pointer to new animal node in R1 add R1,text // Advance R1 to the text field pushw R1 // Push new animal name on stack pushw which // Push the "..correct answer for..." message. call printf // Print the message add SP,4 // Restore stack pushw buf // Push text buffer on stack call gets // Input a "yes" or "no" add SP,2 // Restore stack pushw buf // Push user response pushw yes // Push string "yes" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L2 // If so, goto L2. New animal is on "yes" branch pushw buf // Push user response pushw no // Push string "no" call strcmp // Compare strings add SP,4 // Restore stack cmp R1,0 // Is the result 0? jeq L3 // If so, goto L3. New animal is on "no" branch pushw yesno // Push the "yes or no" error message call printf // Print it add SP,2 // Restore stack jmp L1 // Go back and ask again // // Insert new animal on yes branch of new question // L2: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R3 // Set yes branch to new node movw no_b(R1),R2 // Set no branch to old node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return // // Insert new animal on no branch of new question // L3: movw R1,discrim_node(FP) // Put new question node in R1 movw R2,tree(FP) // Put old animal node in R2 movw R3,animal_node(FP) // Put new animal node in R3 movw yes_b(R1),R2 // Set yes branch to old node movw no_b(R1),R3 // Set no branch to new node movw tree(FP),R1 // Save R1 to tree pointer jmp done // Finish up and return done: movw R1,tree(FP) // Put tree pointer into return register R1 ret // Return to caller .end //////////////////// // malloc(n) -> p Allocate n bytes and return address in R1. Allocated memory // can not be freed. // .proc malloc movw R2, 4(FP) // Get number of bytes movw R1,R13 // Pointer to block of memory add R13,R2 // Update heap pointer ret .end //////////////////// // print(s) Print the string s // .proc print movw R1, 4(FP) // Get parameter (string address) loop: movb R2, (R1) // Put character R1 is pointing to in R2 jeq done // If it was a 0, this is the end of the string movb (ttydata),R2 // Move char to the tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Move pointer to next char jmp loop // Go back and print more done: ret .end //////////////////// // printf(s,...) Print the format string // .proc printf ptr: .symbol -2 // Local var for string pointer arg: .symbol -4 // Local var for argument pointer sub SP,4 // Allocate 4 bytes for local variables movw R3,FP // Assign R3 and add an offset so that it points add R3,6 // to the argument after the control string movw R1, 4(FP) // Put the control string pointer in R1 loop: movb R2, (R1) // Get the next char from control string jeq done // If it was a 0, this is the end of the string cmp R2, '%' // See if it is the '%' character jne cout // If not goto cout, and simply print it add R1,1 // Advance the string pointer movb R2,(R1) // Get the next char add R1,1 // Advance the string pointer again //switch (R2) L1: cmp R2,'s' // See if this is a "%s" conversion jne L2 // If not, goto L2 // case 's' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get address of string (from arguments) to print pushw R2 // Push it on the stack call print // Print the string add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more L2: cmp R2,'d' // See if this is a "%d" conversion jne loop // If not, ignore unknown conversion // case 'd' : movw ptr(FP),R1 // Save the string pointer value movw arg(FP),R3 // Save the argument pointer value movw R2,(R3) // Get number (from arguments) to print pushw R2 // Push it on the stack call nprint // Go print the decimal number add SP,2 // Restore stack pointer movw R1,ptr(FP) // Restore string pointer value movw R3,arg(FP) // Restore argument pointer value add R3,2 // Advance argument pointer to next argument jmp loop // Go back and print more cout: movb (ttydata),R2 // Put character in tty data register movb (ttystatus),#1 // Signal tty controller to print character add R1, #1 // Advance to next char in control string jmp loop // Go back and print more done: ret // All done, return to caller .end //////////////////// // nprint(d) Print the number d in decimal // .proc nprint movw R1, 4(FP) // Move argument value to R1 jeq zprint // If it was zero, goto zprint pushw R1 // Push value to print on stack call nprint_aux // Call aux function to print number add SP,2 // Restore stack pointer ret // All done, return to caller zprint: movb (ttydata), '0' // Put the ascii value of '0' in tty data register movb (ttystatus), #1 // Signal tty controller to print character ret // All done, return to caller .end //////////////////// // nprint_aux(d) Print the number d in decimal (but prints nothing if d is zero) // .proc nprint_aux digit: .symbol -2 // Digit to print sub SP, 2 // Allocate space for local variables movw R1, 4(FP) // Get argument jeq done // If zero, return // To print the number n we compute // R2 = n / 10, and // R3 = n % 10 // We can then recursively call nprint_aux to print all // but the lowest digit, then print the lowest digit ourselves // movw R2, R1 // R2 = R1 div R2, 10 // R2 = R2 / 10 movw R3, R1 // R3 = R1 mod R3, 10 // R3 = R3 % 10 movw digit(FP),R3 // save lowest digit value pushw R2 // Push the higher digits call nprint_aux // Recursively call ourselves to print them add SP,2 // Restore stack pointer movw R3,digit(FP) // Restore digit value add R3, '0' // Add ascii for '0' to get ascii for digit movb (ttydata),R3 // Put char in tty data register movb (ttystatus),#1 // Signal tty controller to print character done: ret // All done, resturn to caller .end //////////////////// // strcmp(a,b) Compare strings a and b // .proc strcmp movw R2,4(FP) // Get pointer to first string movw R3,6(FP) // Get pointer to second string loop: movb R1,(R2) // Get next char from R2 jeq eos // If end of string, goto eos movb R4,(R3) // Get next char from R3 jeq eos // If end of string, goto eos sub R1,R4 // Compute difference in R1 jne done // If difference was not 0, we are done add R2,1 // Advance to next char in R2 add R3,1 // Advance to next char in R3 jmp loop // Go compare more eos: movb R4,(R3) // Get next char from R3 again (in case R1 was eos) sub R1,R4 // Compute difference in R1 done: ret // Return to caller, result is in R1 .end //////////////////// // gets(b) Reads chars from tty into b. // .proc gets movw R1, 4(FP) // Get pointer to buffer movw R4,R1 // Save starting pointer in R4 // // Poll for a characcter // cwait: movb R2,(ttystatus) // Get ready status and R2, #2 // Test if a char is ready jeq cwait // If not, go back and wait some more movb R3,(ttydata) // Get char from tty data register movb (ttystatus),#2 // Signal char received cmp R3,'\r' // Compare against return char jeq done // Exit if return received cmp R3,'\b' // Compare against backspace char jeq del_char // Delete char if backspace cmp R3,0x7f // Compare against delete char jeq del_char // Delete char if delete character movb (ttydata),R3 // Put char to echo in tty data register movb (ttystatus),#1 // Signal tty controller to print character movb (R1),R3 // Save in buffer add R1,1 // increment pointer jmp cwait // Go back and get another char del_char: cmp R1,R4 // Compare current pointer against start of line jle bell // If already at start of line, ring bell movb R3, 0x7f // Make sure delete char is in R3 sub R1,1 // Decrement pointer movb (ttydata),R3 // Echo backspace movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char bell: movb R3, 7 // Put bell char in R3 movb (ttydata),R3 // Echo bell movb (ttystatus),#1 // Signal tty controller to print character jmp cwait // Go back and get another char done: movb (ttydata),'\n' // Output newline movb (ttystatus),#1 // Signal tty controller to print character movb (R1),0 // Put eos in the string we just read ret // Return to caller .end buf: .bss 128 // Buffer for input known: .bss 2 // Number of animals known root: .bss 2 // root of animals tree top_node: .short 0 // Pointer to "yes" node .short 0 // Pointer to "no" node .byte "aardvark",0 // Animal name or question text welcome: .byte "\nWelcome to Animals.\n", 0 think: .byte "\nThink of an animal and I will try to guess what it is.\n", 0 numk: .byte "I currently know %d animals.\n\n", 0 isita: .byte "Is the animal you are thinking of a %s? ",0 yes: .byte "yes",0 no: .byte "no",0 yesno: .byte "Please type 'yes' or 'no'.\n",0 winmsg: .byte "I guessed your animal!!!\n\n",0 loosemsg: .byte "I could not guess your animal. What was your animal? ",0 dscrim: .byte "Enter a question that would distinguish a %s from a %s.\n> ",0 which: .byte "The correct answer for a %s is? ",0 nl: .byte "\n",0 qprompt: .byte "? ",0 mend: end tkgate-2.0-b10/doc/74xx.txt000644 001751 001751 00000051127 10231323404 016124 0ustar00hansenhansen000000 000000 IC Pins #/IC Function -------------------------------------------------------------------------------------- 7400 14 4 Dual Input NAND {MC74ACT00N,DM74ALS00AN} 7401 14 4 Dual Input NAND gate (OC) 7402 14 4 Dual Input NOR gate 7403 14 4 Dual Input NAND gate (OC) 7404 14 6 Inverter {SN7404N} {MC74F04N} 7405 14 6 Inverter (OC) {HD74LS05P} (Keyboard) 7406 14 6 30V/40mA Inverter 7407 14 6 Buffer/Driver (OC) 7408 14 4 Dual Input AND gate 7409 14 4 Dual Input AND gate (OC) {SN74LS09N} 7410 14 3 Triple Input NAND gate {SN74LS10} 7411 14 3 Triple Input AND gate 7412 14 3 Triple Input AND gate 7413 14 2 Schmitt Trigger NAND 7414 14 6 Schmitt Trigger Inverter 7415 14 3 Tri-State AND gate 7416 14 6 15V/40mA Inverter 7417 14 6 15V/40mA Buffer 7420 14 2 Quad Input NAND gate 7421 14 2 Quad Input AND gate 7422 14 2 Quad Input NAND gate (OC) 7423 16 2 Quad Input NOR gate with strobe 7424 - 2 Quad Input NOR gate 7425 14 2 Quad Input NOR gate with strobe 7426 14 4 Dual Input NAND gate 7427 14 3 Triple Input NOR gate 7428 14 4 Dual Input NOR Buffer 7430 14 1 8 Input NAND gate 7432 14 4 Dual Input OR gate 7433 14 4 Dual Input NOR Buffer 7437 14 4 Dual Input NAND Buffer 7438 14 4 Dual Input NAND Buffer (OC) 7439 14 4 Dual Input NAND Buffer (OC) 7440 14 2 Quad Input NAND Buffer 7442 16 - BCD to Decimal Decoder/Driver 7445 16 - BCD to Decimal Decoder/Driver 7446 16 - BCD to 7 Segment LED Decoder/Driver 7447 16 1 BCD to 7 Segment LED Decoder/Driver 7448 16 - BCD to 7 Segment LED Decoder 7449 14 - BCD to 7 Segment LED Decoder 7450 14 2 Dual Input AND inverter 7451 14 2 Dual Input AND/OR 7453 14 - 4 Wide AND/OR inverter gate 7454 14 4 Dual Input Inverter 7464 - - 4-2-3-2 Input AND/OR inverter 7470 14 - Gated edge-triggered JK Flip-Flop 7472 14 - J-K Master/Slave Pulse-Triggered J-K FF 7473 14 2 J-K Flip-Flop with Clear 7474 14 2 D Flip-Flop With Preset and Clear 7475 16 1 4-bit Bistable Latch 7476 16 2 J-K Flip-Flop 7478 14 2 Edge Triggered J-K Flip-Flop 7480 14 - Gated Full Adder 7483 16 1 4-bit Binary Full Adder 7485 16 - 4-bit Magnitude Comparator 7486 14 4 Dual Input XOR gate 7489 16 1 64-bit RAM, open collector output 7490 14 - Decade Counter 7491 14 - 8-bit Shift Register 7492 - - Divide by 12 Counter 7493 14 - Divide by 16 Counter 7495 14 - 4-bit Right/Left Shift Register 7496 - - 5-bit Shift Register 7497 16 - 6-bit Rate Multiplier 74100 - - 8-bit Bistable Latch 74107 14 2 J-K Flip-Flop 74109 16 2 J-K Pos. Flip-Flop 74112 16 2 J-K Neg. Flip-Flop 74113 14 2 J-K edge Triggered Flip-Flop w/ Preset 74114 - 2 J-K Neg. Edge Flip-Flop w/Com Clk & Clr National 74116 24 2 4-bit with clear latch 74120 16 2 Pulse Sync/Driver 74121 14 - Monostable Multivibrator 74122 - - Retriggerable Monostable Multivibrator 74123 16 - Dual Reset Multivibrator 74125 14 - Quad Bus Buffer gate 74126 14 - Quad Bus Buffer gate 74128 14 4 Dual Input Schmitt Trigger NOR Buffer 74132 14 4 Dual Input Schmitt Trigger NAND gate 74133 16 1 13 Input NAND gate 74134 16 1 12 Input NAND gate Tri-State 74135 16 4 XOR/NOR gate 74136 - 4 XOR gate 74137 16 - 3 to 8 line Decoder/Dmultiplexer 74138 16 - Expandable 3/8 Decoder 74139 16 2 Expandable 2/4 Decoder 74140 14 2 Quad Input NAND 50 Driver 74141 - - 1 of 10 Decoder/Driver/Nixie 74143 24 - 4-bit 7-segment counter/latch 74145 16 - 1 of 10 Decoder/Driver 74147 16 - 10-4 Line Encoder 74148 16 - Octal Encoder 74150 24 - 16 Input Multiplexer 74151 16 - 8 Input Multiplexer 74153 16 2 Quad Input Multiplexer 74154 24 - 1 of 16 Decoder/Demultiplexer 74155 16 2 2-4 Decoder/Demultiplexer 74156 16 2 2-4 Decoder/Demultiplexer 74157 16 4 Dual Input Multiplexer 74158 16 4 2/1 Multiplexer 74159 24 - 1 of 16 decoder/demultiplexer (OC) 74160 16 - BCD Decade Counter 74161 16 - Syncronous Binary Counter 4-bit 74162 16 - BCD Decade Counter 74163 16 - Syncronous Binary Counter 74164 14 - Serial In/ Parallel Out Register 74165 - - 8-bit Parallel to Serial Converter 74166 16 - 8-bit Shift Register 74167 16 - Sync Decade Rate Multiplier 74168 16 - 4-bit Up/Down Sync Decade Counter 74169 16 - 4-bit Up/Down Sync Binary Counter 74170 16 - 4x4 Register File 74172 24 - 16-bit Mult Port Register File 74173 16 - 4-bit D Register 3-State 74174 16 6 D Flip-Flop 74175 16 4 D Flip-Flop 74176 14? - Preset Decade Counter 35MHz 74177 14 - Preset Binary Counter 35MHz 74180 14 - 9-bit Odd/Even Parity Generator 74181 24 - 4-bit Arithmetic Logic 74182 16 - Look ahead Carry Generator 74184 - - BCD to Binary Converter 74185 - - Binary to BCD Converter 74188 16 - 256-bit PROM (TBP18SA030) 74189 16 - 16x4 SRAM 74190 16 - BCD/Decade Up/Down Counter 74191 16 - Up/Down Binary Converter 4-bit 74192 16 - Up/Down Decade Counter BCD 74193 16 - Up/Down Binary Counter 4-bit 74194 16 - 4-bit Bidirectional Universal Shift Reg. 74195 16 - Universal 4-bit Shift Register 74196 14 - Preset Decade Counter 74197 14 - Preset Binary Counter 74198 24 - 8-bit Bidirectional Universal Shift Reg. 74219 - - 64-Bit RAM w/ Tristate Outputs National 74221 16 2 Monostable Multivibrator 74238 16 - 3 to 8 line Decoder/Demultiplexer 74240 20 - Tri-State Octal Line Driver 74241 20 - Tri-State Octal Line Driver 74242 - - Quad Bus Transceiver 74243 14 - Tri-State Quad Bus Transceiver 74244 20 8 Tri-State Octal Line Driver 74245 20 - Tri-State Octal Transcender 74247 16 - BCD to 7-Segment Decoder/Driver 74248 16 - BCD to 7-Segment Decoder/Driver 74249 16 - BCD to 7-Segment Decoder/Driver 74251 16 - Tri-State 8/1 Multiplexer 74253 16 2 Tri-State 4/1 Multiplexer 74257 16 4 2/1 Multiplexer 74258 16 4 2/1 Multiplexer 74259 16 - 8-bit Addressable Latch 74260 14 2 5 Input NOR gate 74265 16 4 Comp-Out Element 74266 14 4 Dual Input XNOR gate (OC) 74273 20 8 D Flip-Flop 74278 14 - 4-bit Priority Register 74279 16 - Quad Set/Reset Latch 74280 14 - Octal D Flip-Flop 74283 16 - 4-bit Full Adder 74287 16 - 1024bit PROM (6301) 74288 16 - 256-bit PROM (TB18S030N) 74289 16 - 64-bit RAM Open Collector Outputs 74290 14 - Decade Counter 74293 14 - 4-bit Binary Ripple Counter 74298 16 4 Two Port Register 74299 20 - 8 Input Shift/Storage Register 74322 - 8 Serial/Parallel Register with Sign Extend 74323 - 8 Shift/Storage Reg w/Sync Rst & Common I/O 74348 16 - 8 to 3 Priority Register 74350 - - 4-Bit Shifter with 3-STATE Outputs 74352 - 2 4 input Multiplexer (MUX) 74353 16 2 4-bit Multiplexer, Inverting Output 74365 16 6 Three State Buffer 74366 16 6 Three State Inverting Buffer 74367 16 6 Three State Buffer 74368 16 6 Three State Inverting Buffer 74373 20 - Octal Transparent (D) Latch 74374 20 8 D Flip-Flop Tri-State 74375 16 - 4-bit Bisettable Latch 74377 20 8 D Flip-Flop With Clock Enable 74378 16 6 D Flip-Flop With Clock Enable 74379 16 4 D Flip-Flop With Clock Enable 74381 20 - ALU/Function Generator 74382 - - 4 bit Arithmetic Logic Unit (ALU) 74386 14 4 Dual Input XOR gate 74387 16 - 1024-bit PROM (OC) 74390 16 2 Decade Ripple Counter 74393 14 2 Modulo 16 Counter 74396 16 8 Storage Register 74398 - 4 2 port Register 74399 16 4 Dual Input Multiplexer, Dual Port Register 74401 - - Cyclic Redundancy Check (CRC) Gen/Check 74402 - - Serial Data Polynomial Generator/Checker 74413 - - 64x4 FIFO w/Parallel I/O 74425 14 - Quad Bus Buffer 74426 14 - Quad Bus Buffer 74433 - - FIFO 74472 20 - 512x8 3-state PROM 74474 24 - 512x8 3-State PROM 74490 16 2 BCD decade ripple counter 74521 20 - Octal Comparator 74524 - - Octal Registered Comparator 74533 - - Octal Transparent Latch w/tristate output 74534 - 8 D Flip-Flop 74537 - - 1 of 10 decoder w/tristate outputs 74538 - - 1 of 8 decoder w/tristate outputs 74539 - 2 1 of 4 decoder w/tristate outputs 74540 20 8 Tri-State Inverter Buffer 74541 20 8 Non-Inverting Buffer/ Line Driver 74543 - 8 Registered Transceiver 74544 - 8 Registered Transceiver (Inverting) 74545 - 8 Bidirectional Transceiver w/tristate outputs 74552 - 8 Registered Transceiver w/parity & flags 74563 - 8 D Latch w/tristate outputs 74564 - 8 D Flip-Flop w/tristate outputs 74569 - - 4-bit bidirectional counter w/tristate out 74571 16 - 512x4 3-State PROM 74573 20 8 D Latch w/tristate outputs 74574 20 8 D Flip-Flop w/tristate outputs 74579 - - 8-bit binary counter w/trista 74583 - - 4-bit BCD Adder 74590 16 1 8-bit Three-State Binary Counter 74595 16 - 8-bit Serial to Parallel Shift Register 74620 - 8 Inverting bus transceiver w/tristate outputs 74623 - 8 Inverting bus transceiver w/tristate outputs 74624 14 1 Voltage Controlled Oscillator 74629 16 2 Voltage Controlled Oscillator 74640 20 - Tri-State Octal Bus Transceiver 74641 - - Octal Bus Transceiver (OC) 74644 - - Octal Bus Transceiver (OC) 74645 20 - Tri-State Octal Bus Transceiver 74646 24 8 Trans/Reg Three-State (.3" Wide) 74648 - 8 bus transceiver w/tristate output 74651 - - transceiver/register 74652 - - transceiver/register 74657 - 8 bidir xceive w/8bit parity gen/chk & 3state 74670 16 - 4x4 Register File 3-State 74673 - - 16bit Ser/Parallel shift reg w/com ser i/o 74675 - - 16bit Serial/Parallel shift reg 74676 - - 16bit Parallel/Serial shift reg 74682 20 - 8-bit Comparator 74684 20 - 8-bit Comparator 74685 20 - 8-bit Comparator 74688 20 - 8-bit Magnitude Comparitor (AM25LS2521) 74779 - - 8bit bidir binary counter w/tristate outputs 74794 - - 8bit register w/readback 74821 - - 10bit D Flip Flop 74823 - - 9bit D Flip Flop 74825 - - 8bit D Flip Flop 74827 - - 10bit buffer/line driver 74828 - - 10bit buffer/line driver 74841 - - 10bit transparent latch 74843 - - 9bit transparent latch 74845 - - 8bit transparent latch 74899 - - 9bit latchable transceiver w/parity gen/chk 74900 - - 9bit 3port latchable datapath multiplexer 74902 14 6 Non-Inverting TTL Buffer 74903 14 6 Inverting Buffer 74905 24 - 12-bit Successive Approximation Register 74906 14 6 Open Drain N-Channel Buffer 74907 14 6 Open Drain P-Channel Buffer 74911 28 - 4-digit expandable Display Cont 74914 14 6 Schmitt Trigger ? 74921 22 - 1024-bit Static SG CMOS RAM 74922 18 - 16-key Encoder 74923 20 - 20-key Encoder 74925 16 1 4-digit Counter/Multiplexer/7-Seg Display 74928 18 1 4-digit Counter/Multiplexer/7-Seg Display 74942 20 - {MM74HC942N} (Modem) 741056 - - 8-Bit Schottky Barrier Diode Array 741071 - - 18-Bit Undershoot/Overshoot Clamp w/ESD Prot 741074 - 2 D Flip Flop 742240 - 8 Buffer/Line Drv w/25 Ohm Resistors 742243 - 4 Bus Transceiver w/25 Ohm Resistors 742244 - 8 Buffer/Line Driver w/25 ohm resistors 742245 - 8 bidirectional transceiver w/tristate outputs 744002 - 2 Quad Input NOR 744017 16 - Decade Counter / Divider 744020 16 - 14-Stage Ripple Carry Counter 744024 14 - 7-Stage Ripple Carry Counter 744040 16 - 12-stage Ripple Carry Counter 744046 16 - Phase Locked Loop 744049 16 6 Invering Buffer 744050 16 6 Non-Inverting Buffer 744051 16 - 8-channel Analog Mux/Demux 744060 16 - 14-Stage Ripple Carry Counter 744066 14 4 Analog Switch 744075 - 3 Triple Input OR 744351 20 - Analog Multiplexer with Latch 744511 16 - BCD to 7-Segment Latch/Decoder 744538 16 - Dual Monostable Multivibrator 749240 - - 9bit buffer/line driver w/tristate outputs 749244 - - 9bit buffer/line driver w/tristate outputs 749245 - - 9bit bidir transceiver w/tristate outputs 7416245 - - 16bit transceiver w/tristate outputs 7416540 - - 16bit buffer/line driver w/tristate outputs 7425900 - - 9bit 3port latchable datapath MUX w/25 ohm tkgate-2.0-b10/doc/simErrors.html000644 001751 001751 00000044536 10652507704 017450 0ustar00hansenhansen000000 000000 TKGate User Documentation (Error Messages)

    C. List of Simulator Error Messages

    C.1 Run-Time Warnings/Errors

    • Attempt to write to memory mem with unknown address. - Assigning a value to a memory (e.g, "reg [7:0] mem[0:1023]") with unknown bits in the address potentially invalidates the entire memory since there is no way of knowing which word was written to. This message informs you that such an attempt was made. The memory is not modified. This error message is not issued if the memory is completely uninitialized.
    • Attempt to write to memory mem with unknown bit-range. - The bit-range given for a write to a memory contained unknown bits. For example, given the memory "reg [7:0] mem[0:1023]", the statement "mem[10'h0][8'hx +: 3] = 3'b0;" will generate this error message.
    • Attempt to close non-open descriptor in task 'task'. - This error is generated when you call the $fclose system task with a descriptor that references files that are not open.
    • Divide by zero. - A floating-point divide by zero was attempted.
    • Execution of protected system task 'task' blocked. - The current security settings forbid the use of the task task. Attempts to execute that task result in issuing this error message and ignoring the system task call.
    • Failed to load source file 'file'. - One of the files on the Verga command line could not be read.
    • Failed to open memory file 'file'. - A file specified either through the interface or through a $memreadb or $memreadh system task could not be read.
    • Illegal start value in task 'task'. - The start value in a $readmem(b/h) or $writemem(b/h) task was illegal.
    • Illegal stop value in $readmemb. - The stop value in a $readmem(b/h) task was illegal.
    • Simulation stopped on attempted execution of protected system task 'task'. - The design attempted to execute system task "task" while the current security settings are set to stop the simulation on any attempts to execute that task.
    • Timing violation at line in inst[module] constrain. - This error is generated when a timing constrain specified in a specify block was violated. The line number in the code (line) is given with the instance name (inst), module name (module), and the constraint that was violated (constraint).

    C.2 Compile-Time Warnings

    • Port size mismatch on input port 'A'. - The declared bit-size of input port "A" in the internal and external definitions of the target module do not match.
    • Port size mismatch on output port 'A'. - The declared bit-size of output port "A" in the internal and external definitions of the target module do not match.
    • Net 'A' has no drivers (floating net). - The net "A" has no gates that drive it to a value.
    • Direct connect operator '=>' unsupported. Treated as '*>'. - A specify block is using the "=>" operator, but this operator not currently supported in the TkGate simulator.

    C.3 Compile-Time Errors

    • Array 'mem' used in expression without index. - A variable that was defined as a memory/array such as "reg [7:0] mem[0:1023]" was used in an expression without an index. For example, "r = mem + 4;" would generate this error message.
    • Array 'mem' used without index on left-hand-side. - A variable that was defined as a memory/array such as "reg [7:0] mem[0:1023]" was used in the left-hand side of an assignment without an index. For example, "mem = r;" would generate this error message.
    • Auto range [*] is only valid with 'wire' declaration. - You can implicitly set the range in a wire declaration such as "wire [*] w = 8'h0;". This style of declaration is only valid for wire variables. If you attempt this type of declaration with any other variable type you will get this error.
    • Bad gate instance range expression. - Primitive Verilog gates can take an bit-range to make them operate over multiple bits using the syntax "and g1[3:0] (z,b,c);". If the range expression [3:0] contains errors, this message will be produced.
    • Bit-ranges on path delay specifiers unsupported. - A path delay in a specify block referenced individual bits in a signal. This feature is not supported by Verga.
    • Delay and trigger expressions not allowed in path-delay modules. - Modules using path-delay declarations in a specify block can only be used to define combination logic. You can not use "#num" or "@(expr)" event control expressions.
    • Design contains some modules with `timescale and some without. - You must use the `timescale directive with all modules or none of the modules.
    • Event on multi-bit net 'a' can not have posedge/negedge. - You can not use the posedge and negedge keywords in a event trigger on a multi-bit signal. For example, if a is a multi-bit wire, then @(posedge a) would cause this error.
    • Event wait on assign is illegal. - You attempted to use the @(signal) event trigger in an assign statement.
    • Expecting identifier for argument arg of task 'task'. - You attempted to pass an expression or constant argument to a parameter of a task that requires a net be specified.
    • Expression operator error in 'op'. - The operands used by op where illegal.
    • Found module 'mod1' when expecting 'mod2'. - The module name specified after module keyword does not match the name of the module that was opened in the TkGate HDL module editor.
    • Function 'func' used as task. - The identifier func was defined with the function keyword, but is used like a task.
    • Hierarchical variable 'var' referenced in illegal context. - A hierarchical variable (one containing the "." character) was used in a context were they are forbidden such as in a specify block.
    • Identifier 'a' in constant expression is not a parameter. - The non-parameter variable "a" was used in an expression that must be evaluated at compile time.
    • Illegal address range on port 'p'. - The address range specified on a module port was illegal.
    • Illegal address range specification 'range'. - The indicated address range was illegal.
    • Illegal character (num) 'char'. - The input file contained a character that is not legal in the Verilog language.
    • Illegal declaration of memory 'mem' in path-delay module - unsupported. - Modules using path-delay declarations in a specify block can only be used to define combination logic. Memories and register variables can not be used in such modules.
    • Illegal event control expression. - The expression in an event control statement was illegal. For example "@(4);" will generate this error.
    • Illegal redefinition of net 'net'. - The specified net was declared more than once in the same module.
    • Inout connections must be net-to-net on port 'A'. - You specified an expression as the value of an inout port.
    • Instance of undefined module 'mod'. - You attempted to include an instance of the module mod, but that module is not defined in your design.
    • Invalid left-hand-side in 'assign'. - The left-hand side of an assign statement was illegal.
    • Illegal use of 'v' in left-hand-side of assignment. - v was used in a procedural assignment, but v is not a register type.
    • Invalid left-hand-side in assignment. - The left-hand-side in a procedural assignment is invalid.
    • Invalid output assignment. - An error occurred while generating an implicit assign statement for a module port.
    • Invalid scale 'num' in `timescale declaration (must be 1, 10 or 100). - The numeric portion of the units or precision value must be a 1, 10 or 100, but a different value was used.
    • Invalid syntax in `timescale declaration. - A `timescale directive was use with invalid syntax. A valid `timescale directive has the form "`timescale 1ns / 1 ns".
    • Invalid type declaration used on port 'port'. - The port port was declared with a type other than input, output or inout.
    • Invalid units 'units' in `timescale declaration. - The units specified in a `timescale directive were illegal. The supported units are s, ms, us, ns, ps and fs.
    • Loops in path-delay modules are unsupported. - Modules using path-delay declarations in a specify block can only be used to define combination logic. A feedback loop was detected in the module definition.
    • Memories must be declared as register. - You attempted a declaration such as "wire [7:0] mem[0:1023];" which is illegal.
    • Mixed named and unnamed ports on interface 'intf' of 'mod'. - When declaring module instance you must either use the .port() notation for all ports, or for none of the ports.
    • Mixed named and unnamed parameters on interface 'intf' of 'mod'. When declaring module instance you must either use the .port() notation for all parameters, or for none of the parameters.
    • More than one default: in case statement. - A case statement has more than one default: branch in it.
    • Multiple assignment of net 'net' in path-delay module is unsupported. - Modules using path-delay declarations in a specify block can only be used to define combination logic. Assigning the same net more than once is not supported.
    • Must specify posedge or negedge on event for A. - The $setup, $hold$ and $width timing check tasks require that the reference event use either a posedge or a negedge. This error indicates that that keyword was missing.
    • Net 'net' has no driver and is not an input in path-delay module. - Modules using path-delay declarations in a specify block can only be used to define combination logic. The net net is used in a path-delay module, but has no gates driving it.
    • No current memory in memory file read. - A memory was loaded through the interface or through a $memreadb or $memreadh system task, but no memory was specified with the operation and there was no @memory declaration in the memory file.
    • No matching `ifdef/`ifndef for decl declaration. - An `endif, `else or `elseif was found without a matching `ifdef or `ifndef.
    • Non-blocking assignments to memories not implemented. - Verga only supports blocking assignments to arrays/memories using the "=" operator. The offending line used the "<=" operator to make an assignment to an array/memory.
    • Non-register type used in task or function. - Tasks and functions can only declare and assign to register-type variables.
    • Only input ports are allowed on functions. - A function was declared with ports other than input ports.
    • Parameter 'port' is not declared as a port. - An instance of a module is passed a parameter that is not declared in the parameter list for that module. For example, "foo #(.X(2)) f1(a,b);" was used, but "X" is not declared as a parameter of foo.
    • Parameter redefines identifier 'name'. - The variable name was defined as a parameter, but it has already been previously defined as something else.
    • Port 'port' on interface 'intf' is not defined in module 'mod'. - A ".port()" was used in an instantiation of module mod, but port is not defined as a port on module mod.
    • Port 'port' has no connections on interface 'intf' of 'mod'. - The port port defined as a port on module mod was not connected to anything when instantiating it in another module.
    • Port 'port' has multiple connections on interface 'intf' of 'mod'. - Two ".port()" expressions with the same port name were used in the same module instance.
    • Port count does not match definition on interface 'intf' of 'mod'. - The number of ports used in an instance of mod does not match the number of ports in the definition of mod.
    • Range specification not allowed for memory reference of 'A'. - An attempt was made to reference multiple words of a memory at once. For example, a memory declared as "reg [7:0] mem[0:1023]" was referenced as "mem[0:1]".
    • Redefinition of task or function 'task' in module 'mod'. - There is more than one definition of task in the module mod.
    • Specified net 'net' is not a memory. - An attempt was made to read or write to net as a memory. Usually caused by the $readmem(b/h) or $writemem(b/h) system tasks.
    • Syntax error. - The parser could not understand the syntax of a statement or expression.
    • Task 'task' called with wrong number of arguments. - The number of arguments in a call to task does not match the number of arguments in the definition of task.
    • Task 'task' can not be used in a specify block. - A task other than a constraint task such as $setup, $hold or $width was used in the context of a specify block.
    • Task 'task' must be used in a specify block. - A constraint task such as $setup, $hold or $width was used outside the context of a specify block.
    • Task 'task' used as function. - The identifier task was defined with the task keyword, but is used like a function.
    • Too few parameter ports on instance inst. - An instance uses a parameter port list such as "#(2, 3)" without explicit parameter names, but the number of parameters specified is fewer than the number of parameters on the module definition.
    • Too many files open in task 'task'. - Task task attempted to open a file when the maximum of 31 files are already open.
    • Too many parameter ports on instance A. - An instance uses a parameter port list such as "#(2, 3)" without explicit parameter names, but the number of parameters specified is more than the number of parameters on the module definition.
    • Top-module 'mod' not defined. - "mod" was designated as the top-module, but that module is not defined.
    • Unable to open output file 'file' in task 'task'. - Task task attempted to open the file "file", but the open failed (e.g., because the user did not have write access).
    • Undefined net 'net' in event control expression. - A control expression such as "@(net)" was used, but net is not defined.
    • Undefined task 'task'. - An attempt was made to invoke a task that was not defined either as a system task or as a user task.
    • Undefined variable 'var'. - An attempt was made to use a variable that was not defined.
    • Units must be larger than precision in `timescale declaration. - The value specified as the units (the first number) in a `timescale must be larger than the precision (second number).
    • Unsupported bit range [range] on net net (must be of form [n:0]). - Verga only supports bit ranges were 0 is the least significant bit. An attempt was made to declare a net with a unsupported bit range such as [0:7] or [8:1].
    • Unimplemented primitive gate instance type. - An attempt was made to use a Verilog primitive gate that Verga does not support such as "tran".
    • Use of 'inout' in module with path-delay specification is unsupported. - Modules using path-delay declarations in a specify block can only be used to define combination logic. inout ports can not be used in such modules.
    • Write to closed descriptor. - A system task was called that attempted to write to a descriptor that does not reference an open file.
    • Wrong number of ports on primitive gate instance 'prim'. - A Verilog primitive gate was used with an incorrect number of ports. For example, an and was used with a single port, or a bufif1 was used with other than three ports.
    tkgate-2.0-b10/doc/vpdCreation.html000644 001751 001751 00000052335 10652375623 017740 0ustar00hansenhansen000000 000000 TKGate User Documentation (VPD Creation)

    7. Making Virtual Peripheral Devices (VPDs)

    Virtual Peripheral Devices (VPDs) are a mechanism whereby new and interesting user-define input/output devices can be created and used by TkGate. They can be used to create devices such as TTY Devices, Vending Machine, Robots and any other device that can be imagined.

    TkGate handling of VPDs is designed to be user extensible. Users create a VPD by writing a Tcl/Tk script to define the physical behavior of the device, and a Verilog library file containing a stub module that interacts with the Tcl script. The Tcl/Tk script can create its own GUI through which the user can interact.

    7.1 Overview of Virtual Peripheral Device Design

    Virtual Peripheral Devices are comprised of a Tcl/Tk script file, and a Verilog stub module. The script file implements the graphical interface for the device and handles user interaction. The Verilog stub module encapsulates the behavior of the device into a module that can be included in user circuits. The VPD Tcl/Tk script files are read both from a read-only directory that is part of the TkGate installation, and from a user-defined list of directories that can be specified through the Library Options dialog box. These script files are read at start-up time, so you must restart TkGate if you change the Tcl/Tk portion of a VPD.

    Since a Verilog description can contain multiple instances of a VPD, the Tcl script must be written in such a way so as to allow multiple instances of that interface. This is done by giving each instance a unique instance name. The VPD instance name is typically the same as the Verilog instance name of the stub module for the VPD. The fully instantiated Verilog instance name is dot separated path such as "top.bus1.dm1".

    7.1.1 Named Channels

    Communication between the Tcl-side and Verilog-side of the VPD implementation is performed through a Verga extension to Verilog called a "named channel". A named channel is basically a queue that has a string identifier. TkGate provides Tcl-side and Verilog-side access the named channels allowing data to be passed through the channel. Named channels can be used both to send data from the Tcl side to the Verilog side, and to send data from the Verilog side to the Tcl side.

    7.1.2 Direct Execution of Tcl Commands

    It is also possible for the Verilog stub module to execute Tcl commands directly using the $tkg$exec() system task provided by Verga. However, use of the $tkg$exec() is restricted due to the fact that allowing arbitrary Tcl commands implies allowing arbitrary shell commands. This means that untrusted circuit files could result in damage to the user's system when simulated. For this reason, TkGate provides the capability of choosing a security policy to control the use this system task through the Security Options dialog box.

    Because of the potential security issues and the fact the a user could choose to use a "high" security policy, it is generally recommended that VPD implementers should avoid use of $tkg$exec() and use only named channels when possible.

    7.2 Installing VPDs

    To install a VPD named name, you must install both the "name.tcl" file containing the Tcl implementation, and the "name.v" file containing the Verilog stub module. You can place these files either in the TkGate home directory, or in a user defined directory. To place them in the TkGate home directory, put the "name.tcl" file in the "vpd" sub-directory, and the "name.v" file in the "vlib" sub-directory.

    To place your VPD files a user defined location, you must set the paths for library and VPD files. Open the Library Options dialog box and add the directory containing your "name.v" file to the "Verilog Library Path", and the directory containing your "name.tcl" file to the "VPD () File Path".

    The VPD files will be automatically loaded and registered when TkGate starts. To use a VPD, you should open the library manager and load your VPD.

    7.3 The Tcl-Side Interface

    The Tcl script for a VPD is responsible for creating a window for the device, responding to user input, and communicating with the Verilog stub module.

    7.3.1 Basic Concepts

    A VPD script is a normal Tcl/Tk script and can execute any of the commands that are available through Tcl/Tk. However, since it is loaded with the rest of the TkGate interface, certain design guidelines should be followed to prevent conflicts between the VPD and TkGate. A Tcl-Side API is provided to enable communication between the Verilog portion and the script portion. The VPD API is defined in a Tcl/TK name-space called "VPD". As such, all of the API commands have the prefix "VPD::".

    VPD scripts should begin by executing the VPD::register command to register the name of the VPD. It may then optionally use the VPD::allow (and VPD::disallow) command(s) to register specific commands that are allowed to be executed from the Verilog side using the $tkg$exec() system task if that interface method is used. The body of the VPD should be defined within a name-space having the same name as the registered VPD name. All VPD functions should be defined in that name-space. At a minimum, each VPD is required to provide a "post" method. The " post" method should take an instance name as its first argument, and may optionally define one or more additional arguments. This results in the following recommended structure for a VPD Tcl script: 

    VPD::register TTY
VPD::allow TTY::data

namespace eval TTY {
   proc post {name} {
     ...body of post method...
   }

   ...other functions used by TTY VPD... 
}

    7.3.2 Writing the post Method

    The " post" method is generally responsible for taking the following actions:
    • Create the top-level window for the VPD using the VPD::createWindow command. This window will be automatically destroyed when TkGate exists simulation mode. The -shutdowncommand switch can be used with this command to specify a script to execute when the window is destroyed.
    • Build the widgets for the VPD in the top-level window and set up handlers for user actions.
    • Register input and output signals using the VPD::insignal and VPD::outsignal commands.
    Note that for some VPDs there may be exceptions to these rules. It is also possible to use Tcl as glue to interface the simulation to a real-world device without using a GUI. For example, one could write a VPD to give a Verilog description the ability to access to the Internet. With such a VPD, the VPD::shutdownnotify command can be used to register a script to execute when the simulation is terminated so as to close any open connections.

    An example of a simple post method is given below: 

      proc post {name} {
    variable tty_w

    //
    // Create a VPD window.  The title of the window will be "TTY" followed by the name
    // of the instance.  When the simulation is terminated, the TTY::unpost method
    // will be called.
    //
    set tty_w($name) [VPD::createWindow "TTY $name" -shutdowncommand "TTY::unpost $name"]

    ...build GUI...

    VPD::outsignal $name.TD TTY::TD($name) 
    VPD::insignal $name.RD -command "TTY::data" -format %d
  }
    Since there can be multiple instances of a VPD, it is important to keep state information for each instance separate. This can be done by keeping all such state information in Tcl arrays. For example, the VPD::createWindow method automatically chooses a name for the top-level window in which the GUI will be constructed. Instead of keeping the window id in a flat variable such as "$tty_w", the information should be kept in a variable such as " $tty_w($name)" indexed by the name of the VPD instance, "$name".

    The VPD::outsignal and VPD::insignal methods are used to link Tcl variables or commands to named channels. In the above example, the named channel $name.TD (where $name is the instance name) is associated with the Tcl variable TTY::TD($name). Any time a value is assigned to that variable, the value is transmitted to the Verilog side of the VPD over the named channel. The named channel $name.RD is associated with the Tcl command "TTY::data". Any time data from the Verilog side is available on the named channel $name.RD, that command is executed with the data received on the channel. The -format switch can be used to specify the formatting of the data.

    7.3.3 Tcl/TK Side API for VPDs

    TkGate provides the following Tcl-side API for creating VPDs:

    CommandDescription
    VPD::register name Register a new VPD named name. Registering a VPD allows it to be posted using the Verilog $tkg$post() task.
    VPD::allow names... Register Tcl commands that can be executed from the Verilog simulation when running TkGate with medium or lower security. The '*' character can be used as a wildcard.
    VPD::disallow names... Register Tcl commands for which execution from the Verilog simulation is explicitly disallowed when running TkGate with medium or higher security. The '*' character can be used as a wildcard.
    VPD::isallowed name Test a procedure name to see if it can be executed from the Verilog simulation.
    VPD::shutdownnotify script Register a script to be executed when TkGate exits simulation mode. The registration is deleted after executing the script.
    VPD::createWindow title [options] Create a top-level window that can be used for a VPD and return the name of the window. The window name is automatically generated. Top-level windows created with this command are automatically destroyed when TkGate exits simulation mode. A command to be executed when the simulator shuts down can be specified with the -shutdowncommand option. The shut-down command does any additional cleanup needed by the VPD besides destroying the window.
    VPD::outsignal chan var Cause any value assigned to var to be sent to the simulator over the named channel chan. The channel name is typically formed by using the VPD instance name as a prefix and appending a local name with a dot separator. By default, values assigned to var are interpreted as a decimal integer, but Verilog format constants can also be assigned as well. For example, assigning a value of "8'h3f" would cause the value to be interpreted as the 8-bit hexadecimal value '3F'. The association between the channel and the variable is automatically deleted when TkGate exits simulation mode.
    VPD::insignal chan [options] Register an action to be taken when data is available on the named channel chan. Channel names are chosen in the same manner as VPD::outsignal. One or more options are usually given with this command. The -command option takes a Tcl command to be executed when data is received on chan. The value received on the channel is appended to the command before execution. The -variable option indicates a variable to be assigned. Additionally, the -format switch indicates the format in which data should be reported. The format is given as a Verilog style format string such as "%d" for decimal or "%h" for hexadecimal. The association between the channel and the variable is automatically deleted when TkGate exits simulation mode.

    7.4 The Verilog-Side Interface

    The purpose of the Verilog stub module for a VPD is to encapsulate the channel I/O operations between the Tcl side and the Verilog side into a module that can be included and used like as a regular Verilog module within a user circuit. The stub module is usually defined in a library that is included by user's circuit.

    7.4.1 Writing the Stub Module

    The easiest way to understand how to write a stub module is to look at the following simple example: 

    (1)   module TTY(..., TD, RD, ...);
(2)   output [7:0] TD;
(3)   reg [7:0] RD;
(4)   input RD;
(5)   
(6)     //
(7)     // Execute the TTY::post command to start up the Tcl/Tk interface.
(8)     //
(9)     initial $tkg$post("TTY","%m");
(10)   
(11)    ...
(12)  
(13)    //
(14)    // Respond to changes in the Tcl/Tk TD variable.
(15)    //
(16)    always #10 TD = $tkg$recv("%m.TD");
(17)  
(18)    //
(19)    // Send updated value of RD signal to Tcl/Tk side of VPD.
(20)    //
(21)    always @ (RD) $tkg$send("%m.RD",RD);   
(22)  
(23)  endmodule
    Verilog modules implementing a VPD should invoke the $tkg$post() task in a Verilog "initial" block as shown at Line (9). This will cause each instance of the VPD include in the user design to execute the "TTY::post" method of the Tcl/Tk side as soon as the simulation is started. The $tkg$post() task takes two or more arguments. The first argument is the name of the VPD to be created. The name must be the name of a registered VPD. The second argument is the instance name of the VPD. It must be unique for each instance that VPD. You can use the string "%m", which will be replaced with the name of the module instance in which $tkg$post is invoked. This will guarantee a unique name for the VPD instance. Additional optional arguments of $tkg$post are passed as additional parameters to the VPD::post command.

    Signals received from the Tcl side of the VPD can be handled using a Verilog "always" block as shown on Line (16). An "always" block is essentially an infinite loop executed in its own thread. The "\#10" in this example indicates a delay of 10 time units after which the $tkg$recv task will be executed to read data on the named channel "%m.TD". Again, the "%m" is replaced with the name of the current module instance. The naming convention of prefixing each channel name with "%m." ensures that each instance of the TTY device has its own set of named channels. When a value is received on the named channel, it is placed in the Verilog variable TD, which is declared as a register output.

    Line 21 is an example of how to transmit a Verilog variable to the Tcl side of the VPD implementation. The "always @(RD)" causes the "$tkg$send" task to be called every time the "RD" variable changes value. This will cause the action associated with that channel by the "VPD::insignal" command to be executed in the Tcl side of the VPD implementation.

    The input/output examples at Lines (16) and (21) represent the most simple and direct methods of communication between the Verilog-side and Tcl-side of a VPD implementation. You can also define more complex interactions by encoding some of the communication protocol in Verilog. For example: 

     (1)   input CTS;
 (2)   reg output RTS;
 (3)   reg output [7:0] TD;
 (4)   
 (5)     always
 (6)       begin
 (7)         @ (negedge CTS);               // Wait for CTS falling edge
 (8)         # 10 TD = $tkg$recv("%m.TD");  // Get the next character data
 (9)         # 10 RTS = 1'b1;               // Indicate that data is ready
 (10)        @ (posedge CTS);               // Wait for peer to acknowledge
 (11)        # 10 RTS = 1'b0;               // Reset the protocol
 (12)      end
    This fragment encodes the protocol for receiving data from a TTY as described in the discussion on     Simulation of TTYs. The lines in the "always" block perform the following functions in the protocol: ".
    LineDescription
    (7)Wait for a falling edge of the "CTS" signal. This signal indicates that the peer device is ready to receive data.
    (8)Wait 10 epochs, read the next available character from the "%m.TD" channel, and place it in the "TD" variable.
    (9)Wait 10 epochs, then assert the "RTS" signal to indicate to the peer that new data is available on the "TD" line.
    (10)Wait for the "CTS" line go high, indicating that the peer has read the data from "TD
    (11)Wait 10 epochs, then unassert the "RTS" line to reset the protocol for the next character.

    7.4.2 Instantiating VPDs

    Once the stub module for a VPD has been written, it can then be included in a client Verilog module. For example, the top-level module 
    module top;
  wire [7:0] TD1, TD2;
  wire [7:0] RD1, RD2;
  ...
  TTY tty1(..., TD1, RD1, ...);
  TTY tty2(..., TD2, RD2, ...);
  ...
endmodule
    includes two instances of the TTY VPD. When this Verilog description is simulated, two windows will pop-up with the the titles "TTY top.dm1" and "TTY top.dm2". The names "top.dm1" and "top.dm2" are the instance names of the VPDs (and of their module instances). Each instance can be connected to a separate set of input and output signals.

    7.4.3 Verilog Side API for VPDs

    TaskDescription
    $tkg$exec(arg1, arg2,...) Constructs a string for a Tcl command and sends an execution request from the simulation to the main TkGate executable. The string is constructed similar to the Verilog $display() task (which is in turn similar to the C printf() function). The Tcl command is executed asynchronously with $tkg$exec() not waiting for the command to complete. A "%m" in any string argument will be substituted with the name of the current instance. Use of this task in VPDs is discouraged since it may be disabled through the security settings. $tkg$post(vpdname, instname, [arg1, ...]) Post an instance of the VPD named "vpdname" by invoking the command

        vpdname::post instname

    in the Tcl portion of the VPD. If any arg parameters are specified, they will be passed as additional parameters to the "vpdname::post" function after the instname parameter. Any "[" and "]" characters are treated as ordinary characters. The "vpdname::post" command is executed asynchronously, with $tkg$post returning immediately. A "%m" in any parameter will be substituted with the name of the current instance. In most cases, "%m" should be passed as the instname. $tkg$send(name, data) Send data on the named channel name. If being used to send data to the Tcl side of a VPD, the channel name should correspond to a channel name specified in a VPD::insignal command. The transmitted data will cause either a Tcl variable to be set or a Tcl command to be invoked. A "%m" used in the channel name will be substituted with the name of the current instance. This can be used to create a compound name such as "%m.RD" which will be unique to the instance. data = $tkg$recv(name) Returns data received on the named channel name. If being used to receive data from the Tcl side of a VPD, the channel name should correspond to a channel name specified in a VPD::outsignal command. When the variable declared in the VPD::outsignal command is set, the value of that data, interpreted as a decimal value, will be available to be read by this task. The task will block if there is no data in the channel. A "%m" can be used in the channel name will be substituted with the name of the current instance. This can be used to create a compound name such as "%m.TD" which will be unique to the instance. tkgate-2.0-b10/doc/tkgate.css000644 001751 001751 00000002324 10653523427 016554 0ustar00hansenhansen000000 000000 body { font-family: helvetica; background: beige; } tt { font-size: 14; } img.canvas { background:white ; padding: 2; } img.tool { background:#d9d9d9 ; padding: 2; } font.tool { background:#d9d9d9 ; padding: 2; } div.lfig { float: left; margin: 5; } div.rfig { float: right; margin: 5; } div.frame_rfig { float: right; margin: 5; border: solid black; padding: 5; border-width: 1; } div.display { padding-left: 30; } td { vertical-align: top; } td.wide { padding-bottom: 10; } td.center { text-align: center; vertical-align: center; } td.tlb { text-align: center; vertical-align: top; width: 60; } td.tld { text-align: left; vertical-align: top; } table.display { padding-left: 30; padding-right: 30; } td.tt { font-family: courier; padding-bottom: 10; } table.tbar { padding-left: 30 } th.tbar-b { text-align: left; width: 75;} th.tbar-d { text-align: left; } table.truthtable { table-layout: fixed; font-family: courier; border-collapse: collapse; } td.ttleft { border-right: 1px solid black; width: 45; height: 25; text-align: center;} td.tttop { border-bottom: 1px solid black; width: 25; } td.tttopleft { border-right: 1px solid black; border-bottom: 1px solid black; width: 40; } li.pad { padding-bottom: 10; }tkgate-2.0-b10/doc/temp.html000644 001751 001751 00000002605 10644313146 016413 0ustar00hansenhansen000000 000000



    Connecting a Wire Endpoint to Another Endpoint
    To connect the ports on two gates, first make sure you have selected the "Move/Connect" tool from the "Tool" menu.  Then click and hold the left mouse button on the endpoint of one of the ends you wish to connect.  The mouse cursor will change to a soldering iron to indicate that connect mode is active.
    Next, drag the mouse toward the other endpoint you wish to connect to, TKGate will automatically introduce any necessary bends and maintain connections with only horizontal and vertical segments.
    Finally release the mouse button near the target endpoint.
    TKGate will then connect the wires.
    tkgate-2.0-b10/doc/gateInterface.html000644 001751 001751 00000000561 10645725031 020207 0ustar00hansenhansen000000 000000 TKGate User Documention (Module Interfaces)

    4. Module Interfaces

    tkgate-2.0-b10/doc/gateTypeList.html000644 001751 001751 00000041163 10652376515 020076 0ustar00hansenhansen000000 000000 List of Built-In Gate Types

    A. List of Built-In Gate Types

    Name Keywords(s) Shortcut(s) Symbol Description
    AND and, nand
    a
    A
    		 Outputs the logical AND of the input signals.  All of the inputs must be have either the same bit width as the output, or be single bit.  In the case of a gate with mixed multi- and single-bit inputs, the single-bit inputs are assumed to be connected to across all bits of the multi-bit signals.
    OR or, nor
    o
    O
    		 Outputs the logical OR of the input signals.  All of the inputs must be have either the same bit width as the output, or be single bit.  In the case of a gate with mixed multi- and single-bit inputs, the single-bit inputs are replicated to all of the other bits.
    XOR xor, xnor
    x
    X
    		 Outputs the logical XOR of the input signals.  All of the inputs must be have either the same bit width as the output, or be single bit.  In the case of a gate with mixed multi- and single-bit inputs, the single-bit inputs are replicated to all of the other bits.
    Buffer buf, not
    b
    I
    		 Buffers the input signal.  If the input signal is a value other than logic-1 or logic-0 (e.g., floating) the output will be the unknown signal.  The inputs and outputs must have the same bit width.
    Tri-State Buffer bufif1, bufif0,
    notif1,notif0
    t
    		 Outputs a buffered signal when the enable line (top) is logic-1.  Note that an inverter placed on the output of a tri-state buffer is not equivalent to connecting the output to a separate inverter element.  With an inverted output, a logic-0 on the enable line will result in floating output (i.e., Verilog notif behavior).  The input and output must have the same bit width, and the enable line must be single bit.
    Reduction Gates and, nand,
    or, nor,
    xor, xnor
    Ctl-r aCtl-r A
    Ctl-r oCtl-r O
    Ctl-r xCtl-r X
    		 Outputs the logical AND of all of the bits on the input.  Reduction gates for OR and XOR are also available.  The output must be single-bit.
    Constants supply1, supply0
    gv
    		 Outputs a logic-1 or logic-0.  There are no bit-width restrictions.
    Switch switch
    s
    		 Outputs a single-bit logic value according to the switch setting.  Clicking on a switch while in simulation mode will toggle its state.  The output must be single-bit.
    Dip Switch dip
    d
    		 Outputs a multi-bit signal according to the switch setting.  Clicking on a dip switch while in simulation mode will enable a hex value for the switch to be entered.
    Tty tty
    d
    		 Tty gates can be used to model an interactive terminal.  Your circuit can send characters to be displayed on the tty, or receive

    characters that were typed in the tty.  See the section on ttys in the simulator manual for details on how to use ttys.
    Clock clock
    c
    		 Outputs a clock signal with a specified pulse-width (f), phase (p), and duty width(dw).  The output must be single bit.
    Concat concat
    w
    		 Combines multiple wires into a single multi-bit wire.  The sum of the bits on the left side must add up to the bit width of the right side.  The current implementation has a limitation that all signals must flow in the same direction.  That is, you must put all of the driving gates on either the left or right.
    Wire Tap n/a
    n/a
    		 Pulls off a sub-range of a multi-bit wire.  This gate type is not created through the menus like most other gates, but by dropping the end of a wire on a wire of a larger bit-width.  You can use the "Properties..." option from the "Gate" menu to select the bit range to be extracted.  This gate can only be used to "read" the value of a wire, and cannot be used to "wire" a value on a multi-bit bus.
    Adder add
    +
    		 Outputs the sum of the inputs.  The inputs must have the same bit width as the output, and the carry-in and -out must be single bit.  The carry-in line is indicated by the dot.
    Divider div
    /
    		 Outputs the quotient and remainder of the inputs.  The left input is the dividend, and the right input is the divisor.  There are no bit-width restrictions, but if the result does not fit in the supplied bit-width, it may be truncated.
    Multiplier mult
    *
    		 Outputs the product of the inputs.  There are no bit-width restrictions, but if the result does not fit in the supplied bit-width, it may be truncated.
    Multiplexer mux
    m
    		 Outputs the input selected by the select line.  The bit-width of the inputs must match the bit-width of the output, and the bit-width of the select line must be the ceiling of the base-2 log of the number of input lines.
    Decoder demux
    D 2
    		 Outputs the input selected by the select line.  The bit-width of the inputs must match the bit-width of the output, and the bit-width of the select line must be the ceiling of the base-2 log of the number of input lines.
    Left Shift lshift
    S L
    		 Performs a logical shift-left of the input.  The input and output must have the same bit width, and the bit-width of the shift select line must be the ceiling of the base-2 log of the input/output bit-width.
    Right Shift rshift
    S R
    		 Performs a logical shift-right of the input.  The input and output must have the same bit width, and the bit-width of the shift select line must be the ceiling of the base-2 log of the input/output bit-width.
    Arithmetic Shift arshift
    S A
    		 Performs an arithmetic shift-right of the input.  The input and output must have the same bit width, and the bit-width of the shift select line must be the ceiling of the base-2 log of the input/output bit-width.
    Roll roll
    S O
    		 Rolls the input bits to the left.  The input and output must have the same bit width, and the bit-width of the shift select line must be the ceiling of the base-2 log of the input/output bit-width.
    Register register
    r
    		 Outputs the current value of the register, and stores the input value on a positive edge on the clock line. The data value is only loaded when the active-low enable (EN) line is asserted. The register can be cleared asynchronously with the active-low clear (CL) line. The input and output must have the same bit width, and the clock, EN and CL lines must be single-bit.
    Flip-Flop ff
    f
    		 Outputs the current value and inverted value of the flip-flop, and stores the input value on a positive edge on the clock line. The data value is only loaded when the active-low enable (E) line is asserted. The flip-flop can be cleared asynchronously with the active-low clear (C) line. The input and output must have the same bit width, and the clock, E and C lines must be single-bit.
    RAM ram
    R
    		 When the chip-select line (CS) and output enable (OE) lines are low, the memory value addressed by the address line (A) is output to the data line (D).  When the chip select line and the write enable line (WE) are low, the value present on the data line is stored in the memory at the address specified by the address line.  The control lines, CS, OE, WE must be single-bit.  The address and data lines must be no more than 32 bits.  RAMs can be initialized from a file at simulation time. 
    ROM rom
    u
    		 When the output enable line (OE) is low, the memory value addressed by the address line (A) is output to the data line (D).  The output enable line must be single bit, and the address and data lines must be no more than 32 bits.  ROMs can be initialized from a file at simulation time. 
    NMOS Trans. nmos
    Ctl-t n
    		 Implements a Verilog-style NMOS element.  All signals must have the same bit width.  NMOS elements with multi-bit inputs and outputs are treated as parallel transistors.
    PMOS Trans. pmos
    Ctl-t p
    		 Implements a Verilog-style PMOS element.  All signals must have the same bit width.  PMOS elements with multi-bit inputs and outputs are treated as parallel transistors.
    LED led
    lL 8
     
    L sL h
     
    L d
    		 LED Indicator elements which can display the values of signals in your circuit. The different types of LED are indicated by a property flag of the basic LED circuit element. The types from upper left are: bit, bar graph, direct, hexadecimal and decimal. The number of digits or bars is automatically determined from the size of the input wire. For the three types of 7-segment LEDs, the interpretation of the input data depends on the type. For direct LEDs, each 7-bits of the input signal directly control one segment of the LED numbered from top-to-bottom, left-to-right. For hexadecimal LEDs, each four bit group controls one digit. For decimal LEDs, the value of the input signal is displayed as an unsigned decimal value.
    Module name
    M
    		 Implements a user-defined module.  An arbitrary number of inputs, outputs and inout ports can be used with no restrictions on bit width.  The name of the module is used in the save file and cannot be the same as any of the built-in gates.
    Comment comment
    C
    		 Comments can be used to place embed text into a circuit diagram. Comments have no effect on the behavior of circuits.
    Frame frame
    F
    		 Frames can be used to create visual segmentation of a circuit diagram. Frames have no effect on the behavior of circuits.
    tkgate-2.0-b10/doc/gateHDL.html000644 001751 001751 00000235470 10652374100 016722 0ustar00hansenhansen000000 000000 TKGate User Documentation (HDL)

    4. HDL Modules


    (click to enlarge)

    Figure 4.1: HDL Editor Window
    Verilog is a widely-used textual language for specifying high-level designs for simulation, synthesis and verification. It is an example of a Hardware Description Language (HDL). It is quite versatile allowing specification from CMOS transistor level, up to high-level algorithmic specifications. TkGate supports a subset of the complete Verilog specification. This chapter assumes that the reader is already familiar with Verilog, and is not intended to be a complete description of Verilog and its features. The reader is directed to one of the many books on Verilog for this purpose. Instead, this chapter is intended to document the features of Verilog that are supported in TkGate's implementation.

    The TkGate simulator, called Verga (VERilog simulator for GAte), is a discrete time simulator with time advancing in discrete units called "epochs". All delay must be an integer number of epochs. The Verga simulator is normally used through the TkGate interface, but it can also be run by itself directly on text Verilog files.

    4.1 HDL Editor Window

    When you open a module that you have designated as an HDL module, the HDL editor window will appear as shown in Figure 4.1. This window is essentially a text editor, and you can edit the Verilog text directly in this window. The editing commands that are available depend on which key-binding style you have selected through the Interface Options dialog box. Additional editor options controlling indentation and colorization can be set through the HDL Options dialog box.

    4.1.1 Net List

    The nets in your module are shown in the "Nets" list in the lower left corner. The nets list is updated when you open the module, but may not display correctly if there are too many syntax errors in your module.

    4.1.2 Cut/Paste



    Figure 4.2: Full Adder
    You can use the cut and paste tools to cut and paste blocks of text that you select with the mouse. You can also drag the selected block of text with the mouse to a new location if you have that option enabled in the HDL Options dialog box.

    It is also possible to paste chunks of gates that you have cut or copied from a graphical module. When you paste such modules into a text HDL module, TkGate will convert that chunk into Verilog netlist format. For example, if you cut or copied the full adder shown in Figure 4.2, pasting it into an HDL module would result in the following Verilog code being generated: 

      _GGOR2 #(6) g34 (.I0(w3), .I1(w4), .Z(co));   //: @(216,139) /sn:0 /w:[ 0 0 1 ] /eb:0
  _GGAND2 #(6) g28 (.I0(a), .I1(b), .Z(w4));   //: @(150,141) /sn:0 /w:[ 5 5 1 ] /eb:0
  //: joint g32 (w8) @(172, 65) /w:[ 1 -1 2 4 ]
  //: SWITCH g27 (ci) @(56,26) /sn:0 /w:[ 0 ] /st:0
  _GGAND2 #(6) g31 (.I0(w8), .I1(ci), .Z(w3));   //: @(175,110) /sn:0 /R:3 /w:[ 5 5 1 ] /eb:0
  //: LED g15 (s) @(246,87) /sn:0 /R:2 /w:[ 0 ] /type:0
  //: joint g29 (a) @(117, 62) /w:[ 2 -1 1 4 ]
  //: SWITCH g25 (a) @(56,62) /sn:0 /w:[ 0 ] /st:0
  //: LED g14 (co) @(245,122) /sn:0 /w:[ 0 ] /type:0
  _GGXOR2 #(8) g24 (.I0(w8), .I1(ci), .Z(s));   //: @(213,68) /sn:0 /w:[ 0 3 1 ] /eb:0
  _GGXOR2 #(8) g23 (.I0(a), .I1(b), .Z(w8));   //: @(138,65) /sn:0 /w:[ 3 3 3 ] /eb:0
  //: SWITCH g26 (b) @(56,97) /sn:0 /w:[ 0 ] /st:1
  //: joint g33 (ci) @(177, 70) /w:[ 2 1 -1 4 ]
  //: joint g30 (b) @(111, 97) /w:[ -1 2 1 4 ]
    The generated code includes comments (positions starting with "//") that are included as part of TkGate save files indicating the position information for that circuit element. For circuit elements that do not have direct Verilog counter-parts, such as the LEDs and switches, pure comments are generated. In this example, the only actual Verilog code generated is for the five gates. These are represented in terms of TkGate cells with names beginning in "_GG".

    4.1.3 Module Navigation

    Just as you can open a module in the graphical editor by right clicking on a module and selecting "Open", you can do the same thing with modules in the Verilog text. Right click on the text with the name of the module and select "Open". Right click and select "Close" to close the current module and reopen the next one on the stack. In TkGate, each Verilog module should be opened individually. If you define more than one module, or you change the name in the text description so that it no longer matches the name of the module you have open, TkGate will complain and give you options on how to resolve the problem.

    4.2 Verilog Basics

    This section gives a very brief overview of Verilog.

    4.2.1 Comments

    Comments in Verilog follow the same rules as in C. Block comments are enclosed between "/*" and "*/". Line comments begin with "//" and run to the end of the line.

    4.2.2 Literals

    Verilog literals begin with a letter or a "_" character. The subsequent characters can be letters, digits or "_" characters. TkGate supports escaped literals, but their use is discouraged. Escaped literals begin with a backslash "\" and continue to the next white-space character. "\3+4jk", "\u8[]*9" and "\3342" are examples of escaped literal.

    4.2.3 Numbers and Values

    Sized Numbers
    Verilog numbers can be sized or unsized. Sized numbers have the general form:

        <size>'<base><value>

    where <size> is the number of bits, <base> is a single letter indicating the number base, and <value> is the actual value of the number. The possible bases are 'd for decimal, 'h for hexadecimal, 'o for octal and 'b for binary. Examples of sized numbers include: 
       8'd42        // The 8-bit decimal number 42
   16'h4fe3     // The 16-bit hexadecimal number 4fe3
   8'b10010011  // The 8-bit binary number 10010011
    Unsized Numbers
    Unsized numbers can be those that still include the base, or plain numbers with an implied decimal base such as: 
       83           // The decimal number 83
   'd42         // The decimal number 42
   'o53         // The octal number 53
   'b11         // The binary number 11
    The actual size used to represent unsized numbers is machine dependent, but is guaranteed to be at least 32 bit.
    Special digit values
    Binary, octal and hexadecimal number may also use a "z" digit to indicate the floating or high impedance state in one or more digits. Similarly an "x" or ? digit can be used to indicate an unknown value. Numbers including a base, may also contain one or more "_" characters to help make the number more readable. The "_" characters are ignore in interpreting the value. Some examples are: 
       12'b0101_0111_0010
   16'h7zz3
   1'bx
   8'bx
    When the highest digit of a number is x or z, that value is extended to the highest bit in the number. For example 8'bx is equivalent to 8'bxxxxxxxx not 8'b0000000x. If you really mean the later, you should use 8'b0x.
    Floating Point Numbers
    Verilog specifications can also use floating point numbers. Examples of floating point numbers are "42.0", "0.45" and "3.14". The bit size of floating point numbers is machine dependent, but is at least 32 bits.

    Strings
    Verilog strings are delimited by the double quote character. The backspace character can be used to quote any double quote characters used in the string. Some examples of string values are: 
       "Hello world."
   "Please push \"Enter\" to begin."
   "Exterminate! Exterminate! Exterminate!"
    String values are essentially bit vectors with a size equal to eight times the number of characters.

    4.3 Data Types

    Variables in Verilog can be used to represent registers, or nets connecting components. Each bit in a variables can take on one of six states:

    ValueDescription
    0Logic 0 or false
    1Logic 1 or true
    xUnknown state (could be 0, 1 or z)
    zFloating state
    HHigh unknown state (could be 1 or z)
    LLow unknown state (could be 0 or z)

    4.3.1 Net Types

    Net data types are those that must be driven to have a value. The difference between the types is primarily in how collisions are handled. Collisions occur when two or more gates attempt to drive the wire to different values. The supported net types are:

    TypeDescription
    wireBasic net used to connect components. Collisions result in unknown value.
    wandWired AND net. Collisions result in the AND of the values driven on the net.
    worWired OR net. Collisions result in the OR of the values driven on the net.
    triEquivalent to "wire", but indicates to reader that tri state values will be used.
    tri1Net with resistive pull up. Takes on 1 value if nothing is driving it.
    tri0Net with resistive pull down. Takes on 0 value if nothing is driving it.
    triandSame as wand. Collisions result in the AND of the values driven on the net.
    triorSame as wor. Collisions result in the OR of the values driven on the net.
    triregNet with capacitance store. Retains last value written if all drivers are floating.

    Nets are declared by specifying the data type followed by a comma separated list of variables, and terminated with a semicolon. Some example net declarations are: 
      wire w1;
  wire a,b,c;
  wor p;
  trireg x;

    4.3.2 Supply Types

    Supply types are used to model ground and supply signals fixed to a 0 or 1 value. The supply types are:

    TypeDescription
    supply0Net fixed at logic 0.
    supply1Net fixed at logic 1.

    Examples of supply types are: 
       supply1 vdd;
   supply0 gnd;

    4.3.3 Register Types

    Register types retain their value until they are assigned again. The behave similarly to variables in a C program.

    TypeDescription
    regOne bit register variable.
    integerGeneral purpose integer variable.
    realGeneral purpose floating point variable.
    time64-bit simulation time variable.

    Examples of register types are: 
       reg r1, r2;
   integer i, j;
   time t;
   real f;

    4.3.4 Port Types

    Port types are used to declare the type of a port. Variables using one of these types must also appear in the port list of a module.

    TypeDescription
    inputModule input port.
    outputModule output port.
    inoutModule inout (bidirectional) port.

    The port types normally act like "wire" nets, but the output variables may be also declared as reg in addition to output. This can either be in two separate declarations such as: 
       output z;
   reg z;
    or in a combined declaration: 
       output reg z;

    4.3.5 Event Types

    Event variables do not take on a value per se. Instead, they can be used in signaling from one portion of the design to another. They are declared with the event keyword. For example: 
      event e;

    4.3.6 Parameter Types

    You may also use the parameter type to declare constant variables. Constant variables must be assigned from constant value, or an expression involving only constants and other parameter variables. Examples of parameter declarations are: 
       parameter delay1 = 9;
   parameter delay2 = 2*delay1 + 7;
   parameter myvalue = 8'h4e;
   parameter mystring = "impudent moose";
    Parameters can be used both as values in expressions, and as the value in a delay.

    4.3.7 Bit Size Declaration

    A bit size declaration can be used with any of the net, supply or port data types. In addition they can be used with the reg data type. The bit size is declared right after the keyword and before the variable. The bit size specifier has the form "[msb:lsb]" where msb is the most significant bit and msb is the least significant bit. Currently TkGate Verilog only supports bit ranges with a 0 least significant bit, and a non-negative most significant bit. Examples include: 
       wire [7:0] w1, w2;   // 8-bit wires
   reg [11:0] r1, r2;   // 12-bit registers

    4.3.8 Memories

    Memories are declared by specifying an address range after the variable name in a reg declaration. For example: 
    reg [7:0] m[0:1023];
    Declares a memory with 1024 eight-bit values. TkGate Verilog only supports memories that start at address 0.

    4.3.9 String Variables

    You can store strings in reg variables, but you must allocate enough bits to store the string. For example: 
       reg [8*11-1:0] s = "hello world";

    4.4 Expressions

    Verilog uses an infix notation for expressions similar to expressions in C. A wide range of arithmetic, logical, bit-wise and comparison operators are supported. Operator precedence is similar to C, and parenthesis may be used to group expressions. Some example expressions are: 
       x*u*(3 + j) + 1
   z + 8'h5
   (q*8'h2) < 8'h5
    When the bit sizes of operands in an expression do not match, the bit size of the entire expression is expanded to the bit size of the largest value. For example, when evaluating the expression 16'h3423 + 8'hff, both values are first extended to 16 bits before performing the sum.

    4.4.1 Operators

    The operators supported in TkGate's implementation of Verilog are shown in the table below. Operators are grouped by precedence from highest to lowest.

    OperatorDescription
    {a, b ,...}Concatenation - Concatenates the bits of two or more nets (or expressions) into a single expression. If all of the components are nets, the concatenation may be used as the target of an assignment.
    {n{a}}Bit Replications - Concatenates n copies of a together. n must be a constant.
    ! aLogic NOT - Returns zero if a is zero, one if a is non-zero.
    ~ aBit-wise compliment - Reverses all bits in a.
    - aNegation - Performs an arithmetic negation of a.
    & aReduction AND - ANDs together all the bits of a and returns the 1-bit result.
    | aReduction OR - ORs together all the bits of a and returns the 1-bit result.
    ^ aReduction XOR - XORs together all the bits of a and returns the 1-bit result.
    ~& aReduction NAND - NANDs together all the bits of a and returns the 1-bit result.
    ~| aReduction NOR - NORs together all the bits of a and returns the 1-bit result.
    ~^ aReduction XNOR - XNORs together all the bits of a and returns the 1-bit result.
    a * bMultiplication - Returns the product of a and b.
    a / bDivision - Returns the quotient of a and b.
    a % bRemainder/Modulo - Returns the remainder of a/b.
    a + bAddition - Returns the sum of a and b.
    a - bSubtraction - Returns the difference of a and b.
    a >> bRight Shift - Shifts the bits in a to the right by b places.
    a << bLeft Shift - Shifts the bits in a to the left by b places.
    a >>> bArithmetic Right Shift - Shifts the bits in a to the right by b places arithmetically.
    a <<< bArithmetic Left Shift - Shifts the bits in a to the left by b places arithmetically.
    a > bGreater Than - Returns 1 if a is greater than b, otherwise returns 0.
    a < bLess Than - Returns 1 if a is less than b, otherwise returns 0.
    a >= bGreater Than or Equal - Returns 1 if a is greater than or equal to b, otherwise returns 0.
    a <= bLess Than r Equal - Returns 1 if a is less than or equal to b, otherwise returns 0.
    a == b Equality - Returns 1 if a and b are equal and 0 if they are not equal. Returns unknown (x) if any bits in a or b are unknown or floating.
    a != b Inequality - Returns 0 if a and b are equal and 1 if they are not equal. Returns unknown (x) if any bits in a or b are unknown or floating.
    a === bCase Equality - Returns 1 if a and b match exactly including unknown and floating bits. Returns 0 otherwise.
    a !== bCase Inequality - Returns 0 if a and b match exactly including unknown and floating bits. Returns 1 otherwise.
    a & bBit-wise AND - Each bit of the result is the AND of the corresponding bits of a and b.
    a ~& bBit-wise NAND - Each bit of the result is the NAND of the corresponding bits of a and b.
    a ^ bBit-wise XOR - Each bit of the result is the XOR of the corresponding bits of a and b.
    a ~^ bBit-wise XNOR - Each bit of the result is the XNOR of the corresponding bits of a and b.
    a | bBit-wise OR - Each bit of the result is the OR of the corresponding bits of a and b.
    a ~| bBit-wise NOR - Each bit of the result is the NOR of the corresponding bits of a and b.
    a && bLogical AND - If both a and b have non-zero bits, then return 1, otherwise return 0. However, unknown will be returned if unknown bits in the operands prevent determining the actual result.
    a || bLogical OR - If either a and b have non-zero bits, then return 1, otherwise return 0. However, unknown will be returned if unknown bits in the operands prevent determining the actual result.
    a ? b : cConditional Operator - If a is non-zero, then the result is b. If a is zero, then the result is c. If a is unknown or floating, then the result is the bit-wise XNOR of the bits in b and c.

    4.4.2 Bit and Memory Addressing

    Bits on sized multi-bit variables can be address using the syntax:

         name[bit]

    For example, suppose we have the declaration: 
       reg [7:0] r;
    The expression r[4] represents the single-bit expression for the value of bit-4 in r. This syntax can be used either to use its value in an expression, or in an assignment statement. The bit address can be either a constant or an expression. For example, r[i+1] will address the bit corresponding to the current value of the expression i+1. A run-time error will result if you attempt to simulate a circuit where i+1 goes out of bounds.

    You can also address ranges of bits using the syntax:

         name[high:low]

    For example, r[6:2] is a 5-bit value formed from bits 2 to bit 6 of r. In this syntax, the high and low values specified must be constants, although they can be constant expressions that can be evaluated at compile time.

    In order to get indexable ranges of bits, you can use the syntax:

         name[low+:num]

    In this expression low is the bit number of the lowest bit, and num is the number of bits. num must be a constant expression, but low may be an expression evaluated at execution time. For example r[i +: 3] will address a three bit sub-range of r starting at the bit addressed by i.

    Memories are addressed using the same syntax as bits. For example, if you define the following memory of 1024 8-bit words: 

       reg [7:0] mem[0:1023];
    then mem[45] will address word 45 of the memory and mem[45][6] will address bit 6 of the word 45 of the memory.

    4.5 Compiler Directives

    Verilog compiler directives are similar to the #define and #ifdef directives that are used in C programs. Verilog compiler directives begin with the ` (back-quote) character.

    4.5.1 The `define Directive

    The `define directive is analogous to the #define directive in C. It allows you to associate a value or piece of text with a symbolic macro. For example: 
    `define THEANSWER 42
    To use a macro that you have defined, you must use a back quote in front of the name. For example, to use the value of the macro defined in the example above you might write: 
      x = y + `THEANSWER;

    4.5.3 The `ifdef, `ifndef, `else and `endif Directives

    The `ifdef, `ifndef, `else and `endif directives can be used to conditionally compile Verilog code. They are analogous to the similarly named directives in C. The `ifdef directive causes code to be compiled only if the macro given after it is defined. The `ifndef directive causes code to be compiled only if the macro given after it is not defined. You can nest `ifdef and `ifndef directives and use the `else directive to provide alternatives. The `endif directive marks the end of the conditionally compiled portion.

    An example of conditionally compiled code is shown here: 

      `ifdef INCBY2
     x = x + 2;
  `else
     x = x + 1;
  `endif

    In this example, if the macro INCBY2 has been defined by a `define then the x = x + 2; statement is compiled, otherwise the x = x + 1; statement is compiled. Note that when using macro names in an `ifdef you do not precede them with a ` (backquote).

    4.5.2 The `timescale Directive

    The `timescale directive is used to set the time scale of a module or modules for simulation. It must be followed by a units value and a precision value. These values must be a 1, 10 or 100 followed by time units "s" (seconds), "ms" (milliseconds), "us" (microseconds), "ns" (nanoseconds), "ps" (picoseconds) or "fs" (femotoseconds). For example: 
      `timescale 1ns / 100ps
    would set the time units to 1ns and the simulation precision to 100ps. This would cause any delay specifications in modules defined after the `timescale directive to be counted as 1ns. The simulator itself would simulate in steps of 100ps. It is important not to set the precision value lower than necessary (relative to the delay values of components used in your design) since this can impact simulator performance. If the `timescale directive is not uses, the default time scale and precision is 1ns.

    4.6 Module Declarations

    Module declarations begin with the module keyword, and end with the endmodule keyword. Consider the simple module: 
     (1) module ANDOR(z, a, b, c);
 (2) output z;
 (3) input a,b,c;
 (4) wire x;
 (5)
 (6)   or o1(z,a,x);
 (7)   and a1(z,b,c);
 (8)
 (9) endmodule
    The literal ANDOR after the module keyword is the name of the module. The module name is usually followed by a list of the port names in parenthesis. The port list must be followed by a ";". Inside the body of the module are declarations for any nets used in the module. The nets declared as ports for the module, should also have declarations to indicate if they are input, output or inout ports as shown on lines (2) and (3).

    The port list may be omitted for a module as in this example: 

    module main;
reg a,b,c;
wire x,y,z;

  mycircuit m1(a,b,c,x,y,z);

endmodule
    This is typically done for top-level modules.

    4.7 Netlist Modules

    Netlist modules are those that are defined as a collection of connected components. The components can be built-in Verilog primitives (such as "and" and "or"), library modules, or user-defined modules. Here is a simple example of a module for a 1-bit full adder circuit (the same basic circuit as shown in     Figure 4.2): 
     (1) module ADD(s, co, a, b, ci);
 (2) output s, co;
 (3) input a,b,ci;
 (4) wire w1,w2,w3 ;
 (5) 
 (6)   or (co, w1, w2);
 (7)   and (w2, a, b);
 (8)   and (w1, w3, ci);
 (9)   xor (s, w3, ci);
(10)   xor (w3, a, b);
(11)
(12) endmodule
    The names "or", "and" and "xor" are built-in Verilog primitives for computing the OR, AND and XOR of one or more signals. The first parameter of each of these primitives is the output signal, and the remaining parameters are the inputs. In gate-level descriptions like this, it is easy to see the mapping between the description and the hardware.

    Input ports may be driven by any type of variable, but the outputs of primitives must be a "Net" type variable such as wire, tri or wand.

    It is also possible to give names to the instances of each of the gates. We do this by inserting an instance name after the name of the primitive. For example, we could replace the body of the example above with: 

     (6)   or g1 (co, w1, w2);
 (7)   and g2 (w2, a, b);
 (8)   and g3 (w1, w3, ci);
 (9)   xor g4 (s, w3, ci);
(10)   xor g5 (w3, a, b);
    In this new body, "g1", "g2", etc. are the instance names of the gates and can be used to refer to those gates when necessary. You can also specify more than one instance in a single statement. For example, an alternative way of specifying the above design is: 
     (6)   or g1 (co, w1, w2);
 (7)   and g2 (w2, a, b), g3 (w1, w3, ci);
 (8)   xor g4 (s, w3, ci), g5 (w3, a, b);

    In addition to primitives, netlist modules can also combine other modules. For example, we can connect four of the adders shown above to create a module of a 4-bit adder as shown below: 

     (1) module ADD4(s, co, a, b, ci);
 (2) output [3:0] s;
 (3) output co;
 (4) input [3:0] a,b;
 (5) input ci;
 (6) wire c1,c2,c3;
 (7) 
 (8)    ADD a1 (s[0], c1, a[0], b[0]);
 (9)    ADD a2 (s[1], c2, a[1], b[1]);
(10)    ADD a3 (s[2], c3, a[2], b[2]);
(11)    ADD a4 (s[3], co, a[3], b[3]);
(12)
(13) endmodule
    In this example, we create four instances of our ADD module named a1 through a4. Ports connections are made in the order in which they appear in the port list of the module definition. Alternative, you can explicitly specify the port connections using the syntax:

        .port(net)

    For example, you could replace line (8) with: 
     (8)    ADD a1 (.a(a[0]), .b(b[0]), .s(s[0]), .co(c1));
    Since the ports for each connection are explicitly specified, you can list the connections in any order. However, you must either specify no ports or all ports in this manner. You must also ensure that all ports have exactly one connection.

    4.7.1 Verilog Primitives

    This section will introduce the primitive gates that are supported in TkGate's implementation of Verilog. By default, all primitives are single bit and all inputs and outputs must be single bit. You can declare arrays of primitives by using a bit range after the instance name. For example: 
      and a1[3:0] (x, a, b);
    will perform a bit-wise AND on the four-bit signals a and b and drive the four-bit result to x. The following subsections describe the various types primitives.
    Logic Primitives
    The logic primitives include and, or, xor, nand, nor and xnor. The first parameter is always the output, and the remaining parameters are the inputs. You can specify anywhere from one to an arbitrary number of inputs. The primitives are defined in terms of their truth tables shown below.
    and01xz
    00000
    101xx
    x0xxx
    z0xxx
    or01xz
    00000
    101xx
    x0xxx
    z0xxx
    xor01xz
    00000
    101xx
    x0xxx
    z0xxx
    nand01xz
    00000
    101xx
    x0xxx
    z0xxx
    nor01xz
    00000
    101xx
    x0xxx
    z0xxx
    xnor01xz
    00000
    101xx
    x0xxx
    z0xxx
    Buffer Primitives
    The buffer primitives include buf and not. The last parameter of these primitives is the input, and all of the preceding parameters are outputs being driven with the same value. The buf primitive simply drives its input to the output, while the not primitive drives the compliment logic value. However, if the input is unknown or floating, the output will be unknown for both primitives.

    Consider the example: 

       buf b1 (w1, w2, w3, a);
   not n1 (w4, w5,  b);
    This will drive the value of a to w1, w2 and w3. The compliment of b will be driven to w4 and w5.
    Conditional Buffer Primitives
    The conditional buffer primitives include bufif1, bufif0, notif1 and notif0. These primitives have exactly three ports as shown below: 
       bufif0 b1 (out, in, ctl);
   bufif1 b2 (out, in, ctl);
   notif0 n1 (out, in, ctl);
   notif1 n2 (out, in, ctl);
    The first parameter is the output of the primitive, the second parameter is the input, and the third parameter is the control. The bufif1 and notif1 gates act like buf and not, respectively, when the control signal is 1. They output floating when the control line is 0. Conversely, the bufif0 and notif0 gates act like buf and not, respectively, when the control signal is 0. They output floating when the control line is 1. The truth tables for these primitives are shown in the tables below.
    ctl
    inbufif001xz
    00zLL
    11zHH
    xxzxx
    zxzxx
    ctl
    inbufif101xz
    0z0LL
    1z1HH
    xzxxx
    zzxxx
    ctl
    innotif001xz
    01zHH
    10zLL
    xxzxx
    zxzxx
    ctl
    innotif101xz
    0z1HH
    1z0LL
    xzxxx
    zzxxx
    MOS Transistor Primitives
    Transistor primitives model simple nmos and pmos devices. However, TkGate does not do true transistor-level simulation in the sense of Spice and other such tools. Instead, they are simulated in the same way as the gate primitives, driving an output depending on the value of the input and control signals. Examples of these primitives are: 
      nmos n (out, in, ctl);
  pmos p (out, in, ctl);
    The truth tables for determining the value driven to out from the values on the input in and the control line (or gate) ctl are shown in the table below.
    ctl
    innmos01xz
    0z0LL
    1z1HH
    xzxxx
    zzzzz
    ctl
    inpmos01xz
    00zLL
    11zHH
    xzzxx
    zzzzz
    This level of modeling is generally good enough to create CMOS circuits out of nmos and pmos components. For example: 
      nmos n1 (out, gnd, a);
  nmos n2 (out, gnd, b);
  pmos p1 (x, vdd, a);
  pmos p2 (out, x, b);
    will implement a 2-input OR gate.

    4.7.2 Specifying Delay Values

    In the examples presented so far, all of the primitives had zero delay. In a real circuit, there is propagation delay over a gate. The delay is specified with the syntax #delay. For example, if we add delays to our full adder circuit we get: 
     (1) module ADD(s, co, a, b, ci);
 (2) output s, co;
 (3) input a,b,ci;
 (4) wire w1,w2,w3 ;
 (5) 
 (6)   or #5 g1 (co, w1, w2);
 (7)   and #5 g2 (w2, a, b);
 (8)   and #5 g3 (w1, w3, ci);
 (9)   xor #7 g4 (s, w3, ci);
(10)   xor #7 g5 (w3, a, b);
(11)
(12) endmodule
    The or and and gates will have delays of 5 time units (or whatever was specified as the units in the `timescale directive).

    4.7.3 assign Statements

    Rather than defining complex expression in terms of primitives, you can use an assign statement to assign an expression to an output, with much the same behavior as if you defined it in terms of gates. The general syntax is:

        assign wire = expression;

    The wire must be a net type variable (wire, tri, wand, etc.), but the expression may contain both net and register type variables. The value driven to wire changes whenever the value of the expression changes. You can can also specify a delay value for the assign statement using the syntax:

        assign #delay wire = expression;

    An example of an assign statement with a delay is: 
       assign #5 x = a & (b + c);

    4.8 Behavioral Modules

    In behavioral models, the design is specified algorithmically, more like a C program. Unlike most C programs, however, Verilog specifications tend to be highly parallel with many threads.

    4.8.1 initial and always Statements

    All behavioral Verilog is defined inside an initial or always statement. Both of these statements create a new parallel thread for each statement occurring in the design. The initial statement creates a thread that executes once and terminates, while the always statement creates a thread that repeats in an infinite loop. An example of a clock-generator module defined in behavioral Verilog is shown below: 
     (1)  module myclock(x);
 (2)  output reg x;
 (3)  
 (4)    initial
 (5)       x = 1'b0;
 (6)  
 (7)    always
 (8)       #100 x = ~x;
 (9)  
(10)  endmodule
    When the simulation starts, both the initial statement and the always statement begin execution in parallel. The thread started by the initial statement sets the output register x to 0 as soon as the simulator starts. The always thread waits for 100 simulation time steps, then inverts the value if x. Since always statements repeat, control will go back to the top of the always statement, and after another 100 time units, x will be inverted again. The result is that x will be 0 for the first 100 time units, 1 for time units 100 to 199, 0 again for time units 200 to 299, and so on.

    4.8.2 Blocking Assignments

    Blocking assignments are assignments that use the = operator, and are the most similar to assignments in a C program. Each blocking assignment is executed and the new value assigned to the left-hand side before the next statement is executed. The left-hand side of blocking assignments must be a register type variable.

    An example use of blocking assignments is in the module shown below: 

     (1)  module foo(z,a,b,c)
 (2)  output reg [15:0] z;
 (3)  input [15:0] a,b,c;
 (4)  reg [15:0] r1,r2;
 (5)  
 (6)    always
 (7)      begin
 (8)        r1 = a + b;
 (9)        r2 = r1 *(b + c);
(10)        #5 z = r2 / r1;
(11)      end
(12)
(13)  endmodule
    The statements at Lines (8) and (9) are executed sequentially. The value of r1 used in Line (9) is the value computed at Line (8). The #5 at Line (10) cause execution of the thread to be suspended for 5 time units. After the 5 unit delay has elapsed, the expression r2 / r1 is evaluated and assigned to z. Once the statement at Line (10) has completed, execution of the thread goes back to the top and Lines (8) and (9) are executed again.

    The delay on Line (10) causes evaluation of the left-hand side to wait until the statement after the delay period has elapsed. If some other thread were to change the values of r1 or r2 during the 5 time units Line (10) was delayed, the new values would be used instead. If you wish to ensure that the values at the beginning of the delay period are used, you can use an intra-statement delay such as: 

            z = #5 r2 / r1;
    This will cause r2 / r1 to be evaluated immediately, but the statement will delay 5 time units before assigning z.

    4.8.3 Non-Blocking Assignments

    Non-Blocking assignments use the <= operator and are executed in parallel. The right-hand side expressions are evaluated immediately, but the assignment is deferred until the end of the current time step. Like with blocking assignments, the left-hand side of non-blocking assignments must also be a register type variable.

    An example of using non-blocking assignments to swap the values of two registers are: 

     
 (1)  always
 (2)    begin
 (3)      # 10;
 (4)      a <= b;
 (5)      b <= a;
 (6)    end
    The statement at Line (3) is a delay statement. It waits 10 time units before continuing execution. The next two statements at Lines (4) and (5) are executed in parallel. The current values of b and a are read, then when the next time unit starts, the new values are written to a and b.

    You can specify a delay in non-blocking assignments using a statement such as: 

        a <=  #5 b + x;
    This statement will evaluate b + x, and schedule the assignment of that value to a five time units in the future. Execution of statements after this non-blocking assignment will continue immediately.

    While you can place the delay before a non-blocking assignment as in: 

        #5 a <= b + x;    // A usually incorrect usage of non-blocking assignment
    This usage will result in the thread blocking for 5 time units, then executing the non-blocking assignment. It is equivalent to writing: 
        #5;
    a <= b + x;

    4.8.4 Fully Qualified Path Names

    You can reference variables in other modules of your design by using fully qualified path names. Fully qualified path names start with the name of the top level module, followed by the names of the path of instances down to the level in which the variable you wish to reference is. The "." character is used between each part of the name. Consider the following example: 
      module top;
    wire [15:0] x;
    reg [15:0] a,b;

    foo g1(x,a,b);

    initial 
      begin    
        $monitor("x=%h a=%h b=%h",x,a,b);

        #1 a = 16'h45;
        #1 b = 16'h24;
        #1 top.g1.i = 16'h100;
      end    
  endmodule

  module foo(x,a,b);
   output [15:0] x;
   input [15:0] a,b;
   
    reg [15:0] i = 0;

    assign #1 x = a + b + i;
  endmodule
    The variable name "top.g1.i" used in top references the variable i in the instance g1 of module foo. When this example is simulated, it produces the output: 
    x=x a=45 b=x
x=x a=45 b=24
x=69 a=45 b=24
x=169 a=45 b=24
    Fully qualified path names allow any module to access variables of any other module in your design. Normally, they should only be used in simulation scripts and for debugging.

    4.8.5 System Tasks

    There are a number of system tasks supported in TkGate. They are used somewhat like function calls and are built into the simulator. System tasks begin with a $. One useful system task is the $display task. It is similar to a printf() in a C program. Here is an example of a behavioral description using the $display task: 
       reg [7:0] x;

   initial
     begin
       x = 8'hf;
       $display("Hello world.  The value of x is %d",x);
     end
    Simulating this description will produce the output: 
    Hello world.  The value of x is 15
    The $display task appends a newline to the end of the output. When simulating through the TkGate graphical interface, the output will be directed to the     simulator output console. When using the TkGate simulator stand-alone, output will go to standard output. Like C, the % symbol is used to denote conversions for output. For example: 
        $display("x=%d  x=%o  x=%h  x=%04h",x,x,x,x);
    will produce: 
    x=15  x=17  x=f  x=000f
    Another useful system task is the $monitor task. It has the same calling conventions as $display, except that instead of displaying immediately, it sets a watch on all the nets that are referenced in the statement. Any time a variable referenced by the $monitor task changes value, output will be produced using the rules as in a $display. For example, the module: 
       module top;
   reg [7:0] x, y, z;

     initial
       $monitor("%t: x=%02h  y=%02h  z=%02h",$time,x,y,z);

     initial
       begin
         x = 8'h42; y = 8'h23; z = 8'hfe;
         #5 x = 8'h94;
         #73 y = 8'h6d;
         #21 z = 8'h88;
       end
    endmodule
    will produce the output: 
    0: x=42  y=23  z=fe
5: x=94  y=23  z=fe
78: x=94  y=6d  z=fe
99: x=94  y=6d  z=88
    The $monitor task produces output at most once per simulation time unit. The output is produced at the end of the epoch if the simulator has detected a change on any of the variables references in the $monitor task.

    You may have noticed that we also used the system task $time in this example. This system task returns the current simulation time in simulation time units. You should use the %t conversion when printing out time values. The output produced when using the %t conversion is influenced by the current `timescale in force for the module in which it is used.

    These are only a small fraction of the system tasks supported in TkGate. For a complete list of all the system tasks, see Appendix D. List of System Tasks.

    4.8.6 Delay Triggering

    The delay operator "#delay" has already been touched upon in the previous sections. This operator can be used to suspend/delay execution of a thread for a specified period of time. It can be placed at the beginning of a statement, in-line in a assignment statement, or by itself as a pure delay.

    If a timescale directive has been used, the delay value may be fractional. For example when the module: 

     (1)  `timescale 1ns / 100ps
 (2)  
 (3)  module top;
 (4)  
 (5)    initial
 (6)      begin
 (7)         $display("%t: starting simulation",$time);
 (8)         # 1.5;
 (9)         $display("%t: after delay",$time);
(10)      end
(11)  
(12)  endmodule
    is simulated, the following output is produced: 
    0.0: starting simulation
1.5: after delay
    You can also use a zero delay to ensure that a statement is executed at the end of an epoch. For example: 
       initial
     i = 9;

   initial
     i = 7;

   initial
     #0 i = 42;
    will set i to 42 because the #0 delay ensures that the i = 42; assignment is executed last. If the #0 were not used, then the value of i would be non-deterministic.

    4.8.7 Event-Based Triggering

    Event-based triggering is another way to introduce blocking into your design. Event-based triggers have the syntax:

         @( event-expr )statement;

    They cause the execution of the statement to block until the event described by event-expr occurs. An example use of a event-based trigger is in the following example of a D-flip-flop: 
     (1)  module dff(q, d, clock);
 (2)  input d, clock;
 (3)  output reg q;
 (4)  
 (5)    always @(posedge clock)
 (6)      q = d;
 (7)  
 (8)  endmodule
    The @(posedge clock) expression will cause the execution of the always block to be suspended until the rising edge of the clock signal. The posedge and negedge operators indicate that we should wait for the rising/positive or falling/negative edge of the signal that follows it. If we had instead written Lines (5) and (6) as: 
     (5)    always @(clock)
 (6)      q = d;
    The design would have loaded q with the value of d on both the rising and falling edges of the clock signal.

    You can use the or operator to trigger on the change of one or more signals. For example: 

     (5)    always @(posedge clock or load)
 (6)      q = d;
    would result in the assignment being executed on either the rising edge of clock or any change in the value of load.

    You can also use the event-based trigger with event variables. Event variables are declared with the event keyword. The -> operator is used to raise an event on an event variable. The following example declares and uses an event variable: 

      (1)   module top;
  (2)      event e;
  (3)   
  (4)      initial
  (5)        @ (e) $display($time,": got event");
  (6)   
  (7)      initial
  (8)        #24 -> e;
  (9)      
  (10)  endmodule
    when simulated, this example produces: 
    24: got event
    The event variable e is declared at Line 2. The initial statement at Line 4 executes and uses an event trigger to wait for a signal on e. A parallel initial statement at Line 7 waits for 24 time units, then uses the -> operator to raise an event on e. The raise event operator only has an effect if there are other threads that are blocked waiting for an event.

    4.8.8 The wait Statement

    The wait statement block until a condition is true, then executes its statement. The general syntax is:

         wait ( expr )statement;

    The expr is evaluated any time a variable in it changes, and if the expression is not satisfied, it continued to block, otherwise it executes its statement. As an example, consider the simple latch: 
     (1)  module latch(q, d, load)
 (2)  input d,load;
 (3)  output reg q;
 (4)  
 (5)    always
 (6)        wait (load == 1'b0)
 (7)          #10 q = d;
 (8)  
 (9)  endmodule
    When the load signal becomes zero, the q register is loaded with the value of d after a delay of 10 time units. It is important to include a delay in here to avoid locking up the simulator. With no delay, the statement would continue executing forever without advancing simulation time. This is because simulation time is advanced only after all statements in the current time period (epoch) have been executed.

    4.8.9 Conditional Statements

    Conditional statements are similar to C if statements and use essentially the same syntax. For example: 
        if (load == 1'b0)
      q = d;
    else
      q = q + 1;
    will load the value of d into q if load is zero, otherwise it will increment the value of q. If the value of the expression is unknown (for example, if load had any unknown bits), then the else branch will be taken. if statements may be nested, and the else branch is optional. You may also use a begin...end block in the body as in the example: 
        if (u > x)
      begin
        u = u - 1;
        x = j + k;
      end

    4.8.10 Case Statements

    There are three variants of multi-way branching or case statements: case, casex and casez. They all have the same basic syntax except for which keyword is used. They are similar in purpose to the C switch statement, but have some important differences. An example of a case statement is: 
         case (r)
        2'b00: u = 3;
        2'b0x, 2'b0z: u = 4;
        2'b10, 2'b11, 2'bx1: u = 5;
        2'bxx: u = 6;
        default: u = 7;
     endcase
    This statement will compare r against each of the branches in order until a match is found. Comparison is done with case equality (===) meaning that there must be an exact bit-by-bit match including any unknown (x) or floating (z) bits. You may also specify more than one value for each branch of the case.

    The casez statement differs from case in that any floating (z) bits in the case values or in the expression are treated as don't cares. You may also use a "?" in the case values in place of "z". The casex statement differs in that both floating (z) and unknown (x) bits are treated as don't cares. An example of a casex statement is: 

         casez (r)
        8'b1101????: u = 3;
        8'b1001????: u = 4;
        8'b00????01: u = 5;
        default: u = 7;
     endcase
    Like conditional statements, you may nest case and if statements and use begin...end block in the body of a branch.

    Another difference between the Verilog case, casez and casex statements compared to the C switch statement is that the case values need not be constants. For example, you can write: 

        reg [7:0] r, v1, v2,v3;

    case (r)
       v1: $display("r matched v1"); 
       (v2+1): $display("r matched v2+1"); 
       v3: $display("r matched v3"); 
       default: $display("r didn't match anything"); 
    endcase
    The case expressions are evaluated as the simulator tries r against each expression looking for the first match.

    4.8.11 Loops

    There are four types of looping statements in Verilog that will be described in this section.
    while Loops
    while loops look and behave similarly to while loops in C programs. An example use of a while loop is shown below: 
       always
     begin
       count = 0;
       while (count < 10)
         #12 count = count + 1;
     end
    This description will set count to 0, then increment count ten times with a 12 epoch delay between each time it is incremented.
    for Loops
    for loops also look and behave similarly to for loops in C programs. An example use of a for loop is shown below: 
       reg [7:0] r;
   integer i;

   always @(r)
     for (i = 0;i < 8;i = i + 1)
       $display("Bit %d of r is %b.",i,r[i]);
    This code would wait or the value of r to change, then print out each bit of it individually.
    repeat Loops
    repeat loops can be used to repeat a statement a specified number of times. For example: 
       repeat (10)
     #12 count = count + 1;
    would increment count ten times with a 12 time unit delay between each increment.
    forever Loops
    forever loops can be used to repeat a statement indefinitely . For example: 
       forever
     #12 count = count + 1;
    would increment count every 12 time units. Control would never pass to any statements after the forever statement.

    4.8.12 fork...join Blocks

    fork...join blocks can be used to execute two or more statements in parallel. A new thread is started for each statement in the fork, and the threads are executed in parallel. Execution of the parent thread is suspended until all statements in the fork have completed. The statements in the fork may be begin...end blocks in which case the statements enclosed within each begin...end block will be executed sequentially. Here is an example of a module using a fork...join. 
     (1)  module top;
 (2)    reg [31:0] a,b,c;
 (3)  
 (4)    initial
 (5)      begin
 (6)        fork
 (7)          @(a) $display("%t: got a",$time);
 (8)          @(b) $display("%t: got b",$time);
 (9)          @(c) $display("%t: got c",$time);
(10)        join
(11)        $display("%t: done with fork",$time);
(12)      end
(13)  
(14)    initial
(15)      begin
(16)        #1 a = 1;
(17)        #1 b = 1;
(18)        #1 c = 1;
(19)      end
(20)  
(21)  endmodule
    When simulated, this example would produce the output: 
    1: got a
2: got b
3: got c
3: done with fork
    The three threads at Lines (7), (8) and (9) are started in parallel. Each of those threads immediately suspend waiting for changes in a, b and c, respectively. The initial block at Line (14) also begins executing at time 0, then sets a, b and c in order with a 1 time unit delay between each assignment. As each assignment occurs, one of the forks in the fork...join sees the change, prints its message and terminates. When all three forks of the fork...join have terminated, execution continues in the main thread after the fork...join and the "done with fork" message is displayed.

    4.8.13 Tasks

    Tasks are similar to function calls in C. Tasks are defined in the context of a module. They begin with the task keyword, and are followed by the task name, an optional parameter list, a body, and the endtask keyword. The body can contain any of the statements that may appear of the behavioral Verilog statements described in this section. Tasks may address both local variables defined within them and variables in the parent module. Here is example of a module that defines and uses a task: 
     (1)  module top;
 (2)    reg [15:0] s1,s2;
 (3)  
 (4)     task domult(input [15:0] a, input [15:0] b, output [15:0] z);
 (5)       begin
 (6)         #1 z = a * b;
 (7)       end
 (8)     endtask
 (9)     
(10)     initial
(11)       begin
(12)         domult(3,5,s1);
(13)         $display("%t: s1=%d",$time,s1);
(14)         domult(7,11,s2);
(15)         $display("%t: s2=%d",$time,s2);
(16)       end
(17)  
(18)  endmodule
    The task domul take two inputs a and b, delays for one epoch, then stores their product in the output z. We make two calls in to domul in the main body of the module, assigning values to s1 and s2. When simulated, this module will produce the output: 
    1: s1=15
2: s2=77
    Tasks can use input, output and inout ports declared in their parameter list as shown on Line (4) of the example. These ports can either be declared in a port list as shown in the example, or they may be declared in separate declarations as in: 
        task domult;
    input [15:0] a, b;
    output [15:0] z;
      begin
        #1 z = a * b;
      end
    endtask
    It is also possible to have tasks with no ports as in this example: 
     (1)  module myclock(x);
 (2)  output reg x;
 (3)
 (4)    task initialize_clock;
 (5)      begin
 (6)        x = 1'b0;
 (7)      end
 (8)    endtask
 (9)  
(10)    initial
(11)       initialize_clock();
(12)  
(13)    always
(14)       #100 x = ~x;
(15)  
(16)  endmodule
    In this example, the initialize_clock task sets the register x to 0. By placing all the initialization code in a task, we have made our design more general. If future versions of our module become more complex, we have a place to put any additional initialization code.

    Additional local variables can be declared before the begin...end block inside the task. For example: 

        task printbits(input [7:0] a);
      integer i;

      begin
        $display("Here are the bits in %d:",a);
        for (i = 0;i < 8;i = i + 1)
          $display("   bit %d is %b.",i,a[i]);
      end
    endtask
    will print out: 
    Here are the bits in 184:
   bit 0 is 0  
   bit 1 is 0  
   bit 2 is 0  
   bit 3 is 1  
   bit 4 is 1  
   bit 5 is 1  
   bit 6 is 0  
   bit 7 is 1
    when invoked with printbits(184).

    One important difference between Verilog tasks, and C functions is that local variables are shared across all invocations of the task. This can cause problems when a task is invoked concurrently on two different threads. For example, consider this module in which domult is invoked concurrently in two different threads of a fork...join block: 

     (1) module top;
 (2)   reg [15:0] s1,s2;
 (3) 
 (4)   task domult(input [15:0] a, input [15:0] b, output [15:0] z);
 (5)     begin
 (6)       #1 z = a * b;
 (7)     end
 (8)   endtask
 (9)    
(10)   initial
(11)     fork
(12)       begin
(13)         domult(3,5,s1);
(14)         $display("%t: s1=%d",$time,s1);
(15)       end
(16)       begin
(17)         domult(7,11,s2);
(18)         $display("%t: s2=%d",$time,s2);
(19)       end
(20)    join
(21)  
(22)  endmodule
    When this module was simulated,the following seemingly incorrect output was produced: 
    1: s1=77
1: s2=77
    The problem is that since, the local variables a and b are shared between the two invocations, which ever invocation gets invoked second, will overwrite those values. In this case, the invocation at Line (17) was invoked second, so by the time Line (6) is called, a and b have been set to 7 and 11 in both invocations. In general, the values of a and b are non-deterministic since there is no guarantee as to which thread will execute first. To solve this problem, you can use the automatic keyword in the task declaration, writing: 
     (4)   automatic task domult(input [15:0] a, input [15:0] b, output [15:0] z);
 (5)     begin
 (6)       #1 z = a * b;
 (7)     end
 (8)   endtask
    in place of Lines (4) through (8) above. The automatic keyword causes local variables in a task to be private to each invocation at a slight performance penalty to the simulation. When this corrected design is simulated, the simulator output becomes: 
    1: s1=15
1: s2=77
    This agrees more with our expectations, although technically, the order in which the two output lines is printed is still non-deterministic.

    4.8.14 Functions

    Functions are very similar to tasks, but have some additional restrictions. They must
    • return a single value,
    • use only input ports,
    • must not contain any delay or event-triggered statements, and
    • must not contain any non-blocking assignments.
    Unlike tasks, functions can also be used in assign statements outside of normal behavioral Verilog blocks. Here is an example of a function definition and invocation: 
     (1)  module top;
 (2)    reg [15:0] s1,s2;
 (3)  
 (4)     function [15:0] sqaddmult(input [15:0] a, input [15:0] b, input [15:0] c);
 (5)       reg [15:0] temp;
 (5)       begin
 (6)         temp = b + c;
 (7)         sqaddmult = a * temp * temp;
 (8)       end
 (9)     endtask
(10)     
(11)     initial
(12)       begin
(13)         #1 $display("%t: s1=%d",$time,sqaddmult(3,4,5));
(14)         #1 $display("%t: s2=%d",$time,sqaddmult(6,7,8));
(15)       end
(16)  
(17)  endmodule
    This function adds b and c, squares the sum and puts the result into the temporary variable temp, then multiplies temp by the value of a. The return value of the function is indicated by the assignment to sqaddmult, the name of the function. The [15:0] after the function keyword in Line 4 tells us that the return value is 16 bits.

    Just as with tasks, you can also use the alternate syntax: 

         function [15:0] sqaddmult;
     input [15:0] a, b, c;
    to declare the function and its ports. Also just like with tasks, local variables are shared among invocations unless you use the automatic keyword before function. However, due to a limitation in the TkGate Verilog simulator implementation, you can only use automatic to protect against alternate threads accessing the same function, you can not use it to write recursive functions.

    One use of functions is to define complex combinational logic in a concise algorithmic manner such as: 

     (1)  module mylogic(x,a,b,c);
 (2)  output [15:0] x;
 (3)  input [15:0] a,b,c;
 (4)  
 (5)    function foo(input [15:0] a,input [15:0] b,input [15:0] c);
 (6)      begin
 (7)        r1 = (a[7:0] ^ b[7:0] ^ c[7:0]) + (a[15:8] ^ b[15:8] ^ c[15:8]);
 (8)        r2 = (a[7:0] ^ b[15:8] ^ c[7:0]) + (a[15:8] ^ b[7:0] ^ c[15:8]);
 (9)        r3 = (a[7:0] ^ b[7:0] ^ c[15:8]) + (a[15:8] ^ b[15:8] ^ c[7:0]);
(10)        r4 = (a[7:0] ^ b[15:8] ^ c[15:8]) + (a[15:8] ^ b[7:0] ^ c[7:0])
(11)        foo = r1 ^ r2 ^ r3 ^ r4;
(12)      end
(13)    endfunction
(14)  
(15)    assign x = foo(a,b,c);
(16)  
(17)  endmodule

    4.9 Module Parameters

    The parameter variable type was introduced in Section 4.3.6. You can also declare module parameters that can be overridden by instantiating modules. Module parameters are declared in a separate list before the port list. This list has the syntax:

         #( .name1(value1), .name2(value2), ...)

    The names name1, name2, etc. are the names of the module parameters, and the values value1, value2, etc. are the default values of those parameters. As an example, consider this module implementing and AND gate with a parameter delay for specifying the delay. 
     (1) module AND2 #(.delay(5)) (z, a, b);
 (2) output z;
 (3) input a,b;
 (4)
 (5)   assign #delay z = a & b;
 (6)
 (7) endmodule
    The default value for delay in this example is 5. When overriding the module parameters in an instantiation, the parameter list is specified after the module name, but before any instance names. For example: 
     (1) module ADDER(s, co, a, b, ci);
 (2) output s, co;
 (3) input a,b,ci;
 (4) wire w1,w2,w3 ;
 (5) 
 (6)   OR2 #(6) g1 (.a(w1), .b(w2), .z(co));
 (7)   AND2 #(6) g2 (.a(a), .b(b), .z(w2));
 (8)   AND2 #(7) g3 (.a(w3), .b(ci), .z(w1));
 (9)   XOR2 #(8) g4 (.a(w3), .b(ci), .z(s));
(10)   XOR2 #(8) g5 (.a(a), .b(b), .z(w3));
(11)
(12) endmodule
    This would create a design where the delay of instance g2 is 6, and the delay of g3 is 7. You can also omit the parameter values entirely writing: 
          AND2 g2 (.a(a), .b(b), .z(w2));
    to use the default values of the parameters.

    4.10 Specify Blocks

    Specify blocks are an alternative way to specify the delay of combinational logic without specifying gate-by-gate delay. They can also be used to specify setup and hold times for registers in your design.

    A specify block is delimited by the specify...endspecify keywords. Each statement in a specify block is either a path delay statement, or a constraint task used to verify timing constraints.

    4.10.1 Path Delay Statements

    Path delay statements specify the delay from one or more input ports to one or output ports. The syntax is:

         (in1, in2, ... *> out1, out2, ...) = value;          or          (in1, in2, ... => out1, out2, ...) = value;

    where in1, in2, etc. are input ports and out1, out2, etc. are output ports. These expressions specify a delay of value from each of the input ports to each of the output ports. The Verilog specification differentiates between the => and *> versions in that the => only specifies delay for corresponding bits of each port, while the *> specifies delay from each bit of each input port to every bit of each output port. However, the TkGate Verilog simulator does not support bit-by-bit delay specifications, so in TkGate, both forms are treated the same as *>.

    Here is an example of a combinational logic circuit using a specify block: 

     (1)   module dosomething(a,b,c,x,y,z);
 (2)   input a,b,c;
 (3)   output x,y,z;
 (4)   wire q,r;
 (5)   
 (6)     specify
 (7)       (a,b *> x) = 12;
 (8)       (c *> x) = 8;
 (9)       (a *> y) = 11;
 (10)      (c *> y) = 16;
 (11)      (b *> z) = 23;
 (12)      (c *> z) = 18;
 (13)    endspecify
 (14)   
 (15)    assign r = q & c;
 (16)    assign x = a ^ b ^ r;
 (17)    assign y = a & c;
 (18)    assign z = c & b;
 (19)    assign q = a & b;
 (20)   
 (21)  endmodule
    The statement at Line 7 states that any changes on a or b will be reflected at x after 12 time units. Changes on c will appear at x after 8 time units, and so on.

    A path delay statement may also have a condition attached to it using the if keyword. For example: 

    module XOR(a,b,x);
input a,b;
output x;

  specify
    if (a) (a *> x) = 10;
    if (!a) (a *> x) = 21;
    (b *> x) = 12;
  endspecify

  assign x = a ^ b;

endmodule
    This will implement an XOR gate that has a delay of 10 when a has a 1 value, and a delay of 21 when a has a value of 0. The delay from input b is 12, irregardless of the input values. There is no else in the if clause used with path delay statements, so you must ensure that you cover every possible condition.

    4.10.2 Specparam Declarations

    You can define parameters for use exclusively within a specify block using the specparam keyword. You can assign either a constant, or an expression using other specparam parameters, or parameter variables defined in the module. Here is an example using a specparam: 
      specify
    specparam ab_delay = 7;
    (a *> b) = ab_delay;
  endspecify

    4.10.3 Constraint Tasks

    Another use of specify blocks is to ensure that certain timing constraints are met. For example, most real hardware latches require that the input data line be held constant for some time period before the clock arrives. This is called "setup" time. There is also often a constraint that the input data line hold its value for some time period after the clock pulse. This is called "hold" time. There may also be width restrictions on the clock used to drive the latch. The example below uses a specify block to encode all of these requirements. Each of the statements in the specify block will be addressed in turn. 
    module latch(ck,data,out);
input ck,data;
output out;
reg out = 1'bx;

  specify
    $setup(data, posedge ck, 10);
    $hold(posedge ck, data, 10);
    $width(posedge ck, 25);
  endspecify

  always @(posedge ck)
    out = data;

endmodule
    The $setup Check
    The $setup check has the syntax:

        $setup(data, clock, limit )

    It is used to verify that a setup constraint is satisfied. The data parameter should reference the data line on which you wish to perform the setup check. The clock parameter specifies the clock event for which the data must be set up. The limit parameter specifies the minimum delay time allowed between the data event and the clock event. If this constraint is violated, the TkGate Verilog simulator will issue a warning message, but normal simulation of the circuit will continue.

    You can conditionally execute a check using the &&& operator in the clock parameter. For example: 

        $setup(data, posedge ck &&& enable, 10);
    would only perform the setup check if the enable signal were asserted.
    The $hold Check
    The $hold check has the syntax:

        $hold( clock, data, limit )

    It is used to verify that a hold constraint is satisfied. The clock parameter references the clock event which begins the hold period. The data parameter indicates the data signal that must be held constant during the hold period. The limit indicates the time period for which the data line can not change after the clock event. If this constraint is violated, the TkGate Verilog simulator will issue a warning message, but normal simulation of the circuit will continue.

    Like with the $setup check, you can use the &&& operator in the clock parameter to set a condition on when to do the check.

    The $width Check
    The $width check as the syntax:

        $width( event, limit )

    It is used to verify that the width of a pulse exceeds a minimum value. The event parameter indicates an event (rising or falling) on the signal that is to be tested. The posedge and negedge keyword are used to indicate on which edge to start the test. For example: 
        $width(posedge ck, 25);
    will check that the time the time between the positive/rising edge of ck, and the opposite (in this case negative/falling) edge of ck is at least 25 time units. If this constraint is violated, the TkGate Verilog simulator will issue a warning message, but normal simulation of the circuit will continue.


    tkgate-2.0-b10/doc/gateOptions.html000644 001751 001751 00000044146 10652376210 017750 0ustar00hansenhansen000000 000000 TKGate User Documentation (Options)

    8. Setting TkGate Options

    TKGate has several user configurable parameters that can be set by selecting "Options..." under the "File" menu. The options are divided into nine main tabs. Option settings are persistent, being saved in the file ".tkgate2-preferences" in the user's home directory which is read whenever starting TkGate.

    8.1 General Options

    These options control the general behavior of TkGate. The options that can be set through this page are:
    • Site Name: Indicates the name of the organization where this copy of TkGate is installed. This string will be used on any reports generated by TkGate.
    • User Name: Indicates the name of the TkGate user. This name will be used as the circuit creator name on reports generated by TkGate.
    • Do safe file saving: If enabled, TkGate will use a multi-stage file saving technique to protect the integrity of save files. When saving, TkGate will first save to a temporary file in the same directory as the file being saved. It will then reread that file checking for file inconsistencies. If no inconsistencies are found, it will then rename the temporary file to the target save file. When this option is disabled, the save will occur directly to the target save file with no consistency checks.
    • Include cells in save files: If this option is enabled, Verilog modules for TkGate's primitive cells such as AND gates and OR gates will be included in the save file. These cells are not needed by TkGate, but any external simulation or synthesis tool may need these cells in order to interpret the TkGate save files.
    • Wire drop port creation: If this option is enabled, ports may be added to modules in edit mode by dropping a wire on the edge of the block. This was the standard port creation method in TkGate 1.8. As of TkGate 2.0, there is a separate editor for module interface creation and thus this feature is no longer needed.
    • Do Check-pointing/Frequency: This option enables periodic check-pointing of unsaved files. The checkpoint file will have the same base name as the file you are editing surrounded by '#' characters. It will be saved in the current directory. The frequency specifies a time interval between checkpoints in seconds.
    • Max Undo: This option specifies the maximum number of operations that can be undone using the undo/redo feature.
    • Enable Help Balloons: Causes help messages to be displayed when the mouse cursor is over certain user interface elements.

    8.2 Interface Options

     These options control features of the TkGate interface. The options that can be set through this page are:
    • Key Binding Style: Indicates the basic style for key-bindings. Selecting "emacs" will result in key bindings that are similar to Emacs (e.g., "Ctrl-x Ctrl-s" to save the current file). Selecting "windows" will result in key bindings that are similar to windows (e.g., "Ctrl-s" to save the current file). Selecting "none" will disabled all default bindings. Bindings to not take effect until restarting TkGate.
    • Smooth Scrolling: If this option is enabled, scrolling in the main window will be performed using bitmap copies rather than by using redisplays significantly improving scrolling performance. If your X server has problems with bitmap copies, you can disable this feature.
    • Region Update: Controls the screen redraw algorithm. Enabling this option will cause redraw events to redraw only the portion of the screen which changes rather than the whole screen. Normally this option should be left enabled, but on X servers with poor clipping implementations, enabling this feature may actually result in slower redrawing.
    • Show side-bar images in dialog boxes: Most dialog boxes have side-bars on the left-hand side with an explanation of that dialog box. Unchecking this option will suppress these explanatory messages resulting in slightly smaller dialog boxes.
    • Font Set: This option controls the overall size of the fonts used in the user-interface. Choose between "small", "normal", "large" and "huge".

    8.3 Toolbar Options

     These options control which toolbars will be available. The options that can be set through this page are:
    • Core Editor Toolbars: These are toolbars that are persistent through all modes or are used in circuit edit mode.
    • Simulation Mode Toolbars: These are toolbars that are available only while the simulator is active.
    • Symbol Editor Toolbars: These are toolbars that are available only when the symbol editor is active.

    8.4 HDL Options

     These options control the behavior of TkGate when editing text HDL modules. The options that can be set through this page are:
    • Enable drag-and-drop of selection: When this option is enabled, you can select a block of text with the mouse and drag it to a new location.
    • Enabled Automatic Indenting: When this option is enabled, TkGate will do automatic indentation of the HDL text. When enabled, the following additional indenting options can be set:
      • Indentation per level: This specifies the number of characters to indent for each level of scope in the Verilog module.
      • Make begin..end flush with enclosing level: If this feature is enabled, any "begin..end" blocks will be indented the same amount as the statement that encloses it (e.g., the parent "if" statement).
      • Auto indent after return: If this feature is enabled, TkGate will fix formatting each time you press return.
    • Enabled Code Colorization: If this feature is enabled, the Verilog text will be colorized based in its semantic meaning. You can choose the color, and whether the text should be in bold or italics.

    8.5 Print Options

     These options control the default printing behavior of TkGate. The options that can be set through this page are:
    • Printer: Specifies the printer to use when printing circuits or traces. TkGate will scan the /etc/printcap files to extract the list of available printers. A "Default Printer" will also be included in the list. The "Advanced..." button can be used to edit the printer command that is associated with that printer.
    • Paper Size: Indicates the paper size of the document. If your printer is multi-tray, the appropriate tray will be selected. A variety of U.S. and European/Asian paper sizes are provided.
    • Orientation: Indicates the orientation of the diagram on the page. If you select "Portrait", the image will be printed so that the long side of the paper is vertical. If you select "Landscape", the image will be printed so that the short side is vertical.
    • Print Double-Sided: Indicates that images should be printed on both sides of the page.  This option is only effective on printers capable of double-sided printing.
    • Scale large modules to fit page: Modules which cannot fit on a single page without scaling will be reduced in size so they fit.
    • Partition large modules into multiple pages:Modules which cannot fit on a single page without scaling will be split into multiple pages. A key indicating which portion a page represents will be printed in the lower right corner of the page.
    • Include index: Prints an index page listing each of the modules in alphabetical order and the pages they are on.
    • Include hierarchy graph: Prints a hierarchy graph rooted at the top-level module showing the relationship between parent and child modules.
    • Print small modules four per page: Causes modules which can fit into a single quadrant to be grouped and printed on the same page.

    8.6 Simulate Options

     These options control the simulation behavior of TkGate. The options that can be set through this page are:
    • Epoch Step Size: Specifies the default number of epochs to advance the simulator each time the space bar is pressed.
    • Clock Overstep: Specifies the default number of epochs to advance since a clock event when stepping by clock cycles.
    • Clock Cycle Step Size: Specifies the number of clock cycles to advance when pressing the Tab key.
    • Pop-Up Delay: Specifies the default number of milliseconds to wait before showing the value of a signal when clicking on it.
    • Sort traces alphabetically on scope: If enabled, traces in the scope are sorted alphabetically. If not enabled, the traces are listed in the order in which probes were set.
    • Enable simulator glitch suppression: Enables a simulation feature that suppresses very fast changes on a signal. When this option is on, oscillations on a gate input faster than that gate's delay will produce "unknown" on the output rather than propagating the oscillations.
    • Technology Files: Use this to install additional user-defined delay/area models for gates in addition to the built-in model. Gate delay files have a ".gdf" extension.
    • Error Handling: Use this feature to tell TkGate what to do with simulator errors and warnings. One of the following levels can be selected:
      • Cancel simulation on any warnings: If there are any warning messages about the current circuit, do not allow the simulation to start.
      • Always display warnings: If there are any warning messages about the current circuit, display the warnings, but let the simulation start.
      • Display warnings only with errors:If there are any warning messages about the current circuit but there are no error messages, do not display the warnings and let the simulation start. If there are error messages, the warnings will be displayed along with them.
      • Ignore all warnings:Ignore and do not display any warning messages. Only error messages will be displayed.

    8.7 Library Options

     These options control where TkGate looks for libraries and which libraries should be automatically loaded on start-up. The options that can be set through this page are:
    • Verilog Library Path: Specifies the list of directories in which to search for Verilog library files. The string "${TKGATE_HOME}" is replaced with the TkGate home directory.
    • Base Libraries: Specifies the list of libraries that should be loaded by TkGate on start-up, irregardless of the circuit that is being loaded. Circuit-specific libraries should be specified in the Circuit Properties dialog box.
    • VPD (Virtual Peripheral Device) File Path: Specifies the list of directories in which to search for virtual peripheral device files. Virtual peripheral device files have a ".tcl" extension and contain Tcl code conforming to TkGate's VPD protocol.

    8.8 Security Options

     These options control simulator features such as VPDs (Virtual Peripheral Devices) that have potential security implications. Set these carefully when simulating an unknown or untrusted circuit.
    • Enable the $tkg$command() system task: If enabled, user circuits can use the $tkg$command(). This system task can send a low-level command directly from the simulator to the TkGate interface. For normal circuits, there is seldom a reason to enable this feature.
    • Enable the $fopen() system task: If enabled, user circuits can use the $fopen() system task to open arbitrary files in the user's directory for read and write. This can be useful for debugging circuits, but should not be enabled for untrusted circuits.
    • Enable the $writememb() and $writememh() system tasks: If enabled, user circuits can use the $writememb() and $writememh() system tasks to write the contents of a memory to an arbitrary files in the user's directory. This can be useful for debugging circuits, but should not be enabled for untrusted circuits.
    • Enable the $tkg$recv() and $tkg$send() system tasks: If enabled, user circuits can use the $tkg$recv() and $tkg$send() system tasks. These are necessary for VPDs (Virtual Peripheral Devices) to work properly.
    • The $tkg$exec() system task is: The $tkg$exec() system tasks allows a user to execute an arbitrary Tcl/Tk command in the context of TkGate. Indirectly this could cause an arbitrary shell command to be executed. Some VPD implementations use this mechanism to pass data between the Verilog portion and the Tcl portion. One of the following security settings can be used for this task.
      • fully enabled: Allows unrestricted use of the $tkg$exec() task. This setting is not recommended.
      • enabled only for registered functions: Allows only functions that have been registered as safe or necessary for a VPD to be executed. The '[' and ']' characters are disallowed when this setting is selected.
      • disabled: The $tkg$exec() task is completely disabled and can not be used from user circuits.
    • Security Violation Handling: This option specifies what TkGate should do when a user circuit tries to use a system task that has been disabled through this dialog box.
    • Stop simulator when disabled feature is used: Any attempted use of a disabled system task will cause the simulator to stop and a warning message to be displayed.
    • Display warning message when disabled feature is used: Any use of a disabled system task will cause a warning message to be displayed, but the simulation will continue to execute with the call to the disabled task ignored.
    • Ignore attempted usage of disabled features: Any attempts to use a disabled system task will be silently ignored.

    8.9 Color Options

     These options control the colors used for various elements in the TkGate interface. The options that can be set through this page are:
    • Edit Window Colors These options specify the color of elements in the main editor window.
      • Background: Sets background color for the editing canvas.
      • Instances: Sets the color used for primitive gates and their labels.
      • Modules: Sets the color used for modules, other than the port names.
      • Module Ports: Sets the color used for port names on modules.
      • Frames: Sets the color used for frames.
      • Comments: Sets the color used for normal comments.
      • Hyperlinks: Sets the color used for hyperlink comments.
      • Single-Bit Wires: Sets the color used for single-bit wires and their labels.
      • Multi-Bit Wires: Sets the color used for multi-bit wires and their labels.
      • Gate Tools: Sets the color for other non-cursor objects used by TkGate (e.g., probes).
      • Critical Path: Sets the color used to highlight the critical path in the circuit.
      • Off LED: Sets the color for LEDs which are off.
      • On LED: Sets the color for LEDs which are on.
      • Floating LED: Sets the color for LEDs for which the input signal is a non 0/1 value. in the logic scope.
    • Scope Window Colors
      • Scope Grid: Sets the color for the grid in the logic scope.
      • Logic One: Sets the color for all deterministic non-zero logic values in the logic scope.
      • Logic Zero: Sets the color for zero logic values in the logic scope.
      • Float: Sets the color for floating logic values in the logic scope.
      • Unknown/Conflict: Sets the color for unknown logic values, including the "low" and "high" values, in the logic scope.

    8.10 HTML Options

    These options control what TkGate should do when the user clicks on certain hyperlinks in their circuit.
    • Browser Command: Specifies the command to use when the user clicks on a hyperlink starting with "http:". Normally this should point to the user's browser command. A "%s" in the command will be replaced with the text of the hyperlink the user clicked on.
    • e-Mail Command: Specifies the command to use when the user clicks on a hyperlink starting with "mail:". Normally this should point to the user's e-mail client. A "%s" in the command will be replaced with the text of the hyperlink the user clicked on.

    tkgate-2.0-b10/doc/toolbarList.html000644 001751 001751 00000005066 10647223052 017747 0ustar00hansenhansen000000 000000 List of Toolbar Buttons

    C. Edit-Mode Toolbar Summary

    C.1 Common Toolbars

    C.1.1 File Menu

    ButtonDescription
    Discard the existing circuit and prompt for a new file name.
    Discard the existing circuit and prompt for a file from which to load a new circuit.
    Open the library manager to load or unload libaries.
    Save the circuit to the current file.
    Save the circuit to a specified file.
    Print the current circuit.

    C.1.2 Undo/Redo Menu

    ButtonDescription
    Undo the previous action and place it on the undone list.
    Redo the top action on the undone list.

    C.1.3 Edit Menu

    ButtonDescription
    Cut the selected gates/wires and copy them to the cut buffer.
    Copy the selected gates/wire to the cut buffer.
    Paste the contents of the cut buffer to the circuit.
    Search for a string in gates, wires and comments.

    C.2 Edit-Mode Toolbars

    C.3 Symbol Editor Toolbars

    C.4 Simulator Mode Toolbars

    tkgate-2.0-b10/doc/menuList.html000644 001751 001751 00000026654 10646057021 017257 0ustar00hansenhansen000000 000000 List of Menu Command

    B. Menu Summary

    Menu OptionShortcutDescription
    FileNewCtl-x k Flushes the current circuit and begins a new one.  A dialog box will prompt for a new circuit file and top-level block name.
    Open...Ctl-x Ctl-f Flushes the current circuit and reads a new circuit from a file.
    Open Library...Ctl-x Ctl-l Reads library modules from a file.  The modules will be marked as library modules.  Only modules that to not supersede a current non-library module will be loaded.
    SaveCtl-x Ctl-s Saves the current circuit to the current file.  If there is no current file, TkGate will prompt for a file name.
    Save...Ctl-x Ctl-w Prompts for a file name and saves the circuit.  The specified file name will become the new current file.
    Print...Ctl-x Ctl-p Prints a schematic diagram.  Schematics can be printed directly to the printer or to a file.
    Options...Ctl-x o Brings up a dialog box allowing TkGate options to be set.
    QuitCtl-x Ctl-c Exits TkGate.
    EditCutCtl-w Cuts the selected gates and inserts them into the cut buffer.
    CopyCtl-x x Copies the selected gates into the cut buffer.
    PasteCtl-y Pastes the contents of the cut buffer.  If a mark is set, the gates will be pasted at the mark postion.  If no mark is set, the original position of the gates in the cut buffer will be used.
    Select AllCtl-x a Selects all gates.
    Find...Ctl-f Searches for a gate or wire containing a substring.
    Align Vert.| Positions the selected gates such that they are vertically aligned.
    Align Horz.- Positions the selected gates such that they are horizontally aligned.
    ToolMove/ConnectF1 Enables move/connect mode.
    Delete GateF2 Enables delete gate mode.
    Cut WireF3 Enables cut wire mode.
    InvertF4 Enables invert port mode.
    Bit WidthF5 Enables set bit width mode.
    Rot 0Ctl-F1 Sets rotation for new gates to 0.
    Rot 90Ctl-F2 Sets rotation for new gates to 90.
    Rot 180Ctl-F3 Sets rotation for new gates to 180.
    Rot 270Ctl-F4 Sets rotation for new gates to 270.
    CircuitCircuit Properties...Ctl-x E Sets global properties of a circuit.
    Criticl Path...Ctl-x r List the critical paths of a circuit.
    SimulateBegin SimulationCtl-s b Starts a simulation.
    RunCtl-s g Puts the simulator into continuous simulation mode.
    PauseCtl-s s Puts the simulator into single-step mode.
    Step Epoch(s)space Steps the simulator a fixed number of epochs.  The step size can be set in the TkGate options box.
    Step Cycletab Steps the simulator a fixed number of clock cycles plus a fixed number of epochs.  The number of cycles and the overstep can be set in the TkGate options box.
    Breakpoint...Ctl-s k Creates a condition which will cause the simulator to transition from continuous simulation mode to single step mode.
    Exec. Script...Ctl-s x Reads simulation commands from a script file.
    Load Memory...Ctl-s l Loads a memory(ies) from a file.
    Dump Memory...Ctl-s d Dumps a memory to a file.
    ModuleOpen> Opens the currently selected module instance.
    Close< Closes the current module and makes the next module up on the module stack the current module.  Also exits from "module interface" mode.
    Set InterfaceCtl-b s Makes the interface of the currently selected module instance the default module interface.
    Edit Interfaces...Ctl-b e Enters a mode allowing module interfaces for all module types to be edited.
    New...Ctl-b n Creates a new module definition.
    Delete...Ctl-b d Deletes a module definition.
    Copy...Ctl-b c Copies a module definition to another module.
    Rename...Ctl-b r Renames a module defintion.
    Claim...Ctl-b l Convert a library module to a user module.
    GateAdd Input[ Adds an input to the currently selected gate.  If the gate is a module instance, a special cursor will appear and you can select the position for the port.
    Add Output] Adds an output to the currently selected gate.  If the gate is a module instance, a special cursor will appear and you can select the position for the port.
    Add Bidir- Adds an inout to the currently selected gate.  If the gate is a module instance, a special cursor will appear and you can select the position for the port.
    Change Type@ Changes the type (input, output or inout) of a port on a module instance.
    Anchor SelectedCtl-x f Sets the anchor bit of all selected gates.  Anchored gates can not be moved with the mouse.
    Unanchor SelectedCtl-x u Unsets the anchor bit of all selected gates.
    Properties...E Edit properties of the selected gate.
    ReplicateCtl-v Make multiple replicas of a gate.
    Deletedel Delete the selected gate(s).
    MakeI/OSwitchsMake a switch.
    Dip SwitchdMake a dip switch.
    GroundgMake a constant logic 0 element.
    VddvMake a constant logic 1 element.
    Wire MergewMake a wire merge element.
    LEDlSingle bit LED
    LED Barl[n]LED Bar Graph
    7-Seg. LED (HEX)Lh7-Segment LED with hexidecimal encoding
    7-Seg. LED (DEC)Ld7-Segment LED with decimal encoding.
    7-Seg. LED (Direct)Ls7-Segment LED with direct encoding.
    ClockcMake a clock.
    TtyTMake a tty.
    GateANDaMake a AND gate.
    NANDAMake a NAND gate.
    ORoMake an OR gate.
    NOROMake a NOR gate.
    XORxMake an XOR gate.
    XNORXMake an XNOR gate.
    BufferbMake a buffer.
    InverteriMake an inverter.
    Tri-BuffertMake a tri-state buffer.
    NMOSCtl-t nMake a NMOS transistor.
    PMOSCtl-t pMake a PMOS transistor.
    ReductionANDCtl-r aMake a reduction AND gate.
    NANDCtl-r AMake a reduction NAND gate.
    ORCtl-r oMake a reduction OR gate.
    NORCtl-r OMake a reduction NOR gate.
    XORCtl-r xMake a reduction XOR gate.
    XNORCtl-r XMake a reduction XNOR gate.
    MSI2-1 MultiplexormMake a 2-1 multiplexor.
    4-1 MultiplexorM 4Make a 4-1 multiplexor.
    8-1 MultiplexorM 8Make an 8-1 multiplexor.
    1-2 DecoderD 2Make a 1-2 decoder.
    1-4 DecoderD 4Make a 1-4 decoder.
    1-8 DecoderD 8Make a 1-8 decoder.
    ALUAdder+Make an adder.
    Multiplier*Make a multiplier.
    Divider/Make a divider.
    Left ShiftS LMake a left shifter.
    Right ShiftS RMake a right shifter.
    Arith. Right ShiftS AMake an arithmetic right shifter.
    RollS OMake a roll shifter.
    MemoryRegisterrMake a register.
    RAMRMake a random access memory.
    ROMuMake a read-only memory.
    ModuleModule InstanceBMake a module instance.
    Module Input}Make a module input port.
    Module Output{Make a module output port.
    Module InOut=Make a module inout port.
    CommentCMake a comment.
    FrameFMake a frame box.
    tkgate-2.0-b10/doc/gateModules.html000644 001751 001751 00000072404 10652372651 017730 0ustar00hansenhansen000000 000000 TKGate User Documentation (Modules)

    3. Working with Modules

    While in theory you could create your entire design as a single flat collection of primitive gates, when a design gets too large it becomes too difficult to manage this way. In order to manage the complexity of a large design, we must use hierarchical design practices. As with most other tools, TkGate uses modules to manage this complexity. Modules serve a similar purpose as functions do in a C program. They allow the design to be broken into manageable chunks as well as allow for reuse.

    3.1 Module Implementations versus Module Instances

    TkGate distinguishes between "Modules Implementations" and "Module Instances." A module implementation is analogous to the definition of a C function. It specifies what the module does, and what its interface is. This is divided into an internal definition which is created in an editor window in the same way as any other circuit, and an interface which specified the ports and properties of those ports (analogous to the function prototype or parameter list in a C function).

    A module instance is analogous to an invocation of a function in a C program. It is generally displayed as a box with input and output wire attached to it. Each instance of a module operates independent of the other instances. When realized as a circuit, each instance would take up chip area, and be comprised of its own physical wires and components. When simulating, TkGate maintains separate state for the values of wires in each instance and the values of any registers or memories.

    3.2 Creating Module Instances


    1) Select a module from the module list.


    2) Drag to the insertion location.


    3) Release mouse button to create.

    Figure 3.1: Creating a Module Instance
    The easiest way to create a module instance is to drag the module name from the module list. To do this, first 1) select a module from the module list. In this example, we have selected the "REGS" module. Next, 2) drag the module name onto the canvas. The module name will get dragged onto the canvas. Finally, 3) release the mouse button to create an instance of the module. After you have created the module instance, you can select it and drag it with the mouse to position it exactly where you want it.


    (Click to Enlarge)

    Figure 3.2: Module Function Selection
    Another way to create a module instance is to right click and select "Make → Module → Module Instance" from the pop-up menu, or use the "B" keyboard shortcut. When you do this, the "Details" page of the module properties box will appear to allow you to select which module you wish to create an instance of. Select a name from the list box labeled "Function", or press "New..." to create an instance of a new type of module that you intend to define later. After you have selected the type of module, press "OK" to create the module instance. If you press "Cancel", the operation will be aborted and no module will be created.

    When you create a module instance, that instance will have a unique instance name, distinct from the name of the module type or function. The instance name allows you to distinguish between different instances of a module. For example, if you create two REGS modules, one might have an instance name of "g1" and one might have an instance name of "g2". Normally, TkGate automatically assigns the instance name, but you can change it on the "General" tab of the Gate Properties Box dialog box. Note that this dialog box displays and modifies properties of the module instance, not the underlying module implementation.

    3.3 Module Hierarchy

    Your design in TkGate is comprised of a hierarchy of module instances. There is one module that is designated the top-level module. By default, this module is called "main", but you can rename it to any module you wish. You can also designate any module in your design to be the top-level module. Module instances that are directly included in the top-level module form the next level in the hierarchy, and modules instances included in those 2nd layer modules form the next layer and so on.

    3.3.1 Module Hierarchy View



    Figure 3.3: Module
    Hierarchy View

    TkGate's module hierarchy view displays the module hierarchy of your design. Be sure you have selected to see the hierarchical view. When you are in edit mode, the hierarchy is shown in terms of module implementations. That is, at each node in the tree, the children are the names of the modules which are used as instances at least once in the module.

    Consider the example shown to the right. The top-level module "main" is indicated by the symbol next to it. In this example, "main" uses one or more module instances of the "EUNIT", "IUNIT" and "MEMORY" modules. The "REG16" module uses one or more instances of the "REG4" and "ZREG4" modules, but the symbol next to "REG4" tells us that there is no definition for that module. The module "ZREG4" shown in red with an underline indicates that that module is the current module in the editor. The symbol next to "EUNIT" underneath "ZREG4" indicates a conflict. ZREG4 includes an instance of "EUNIT", but "ZREG4" itself is contained in an "EUNIT" (it is in "REG16" which is in "EUNIT"). Circuits containing conflicts can not be simulated, all conflicts must be resolved before you can simulate.

    Each module in the module list or hierarchy view is preceded by a symbol showing its type. The possible types are:

    SymbolDescription
    The top-level module.
    A normal net-list module.
    A text HDL module.
    Collection of module libraries.
    A module library
    A module defined in a library.
    Collection of modules defined but not used in the circuit.
    Reference to an undefined module in hierarchical list.
    Conflict/recursive definition in hierarchical list.

    HDL and net-list modules may also contain a "lock" on them (for example ). The lock indicates that editing of that module has been disabled in the module options dialog box.

    3.3.2 Navigating to Modules

    Double click on a module in the module hierarchy or module list view to open that module in the editor. You can also right click on a module instance in the main editing window and select " Open". When you use " Open" to open modules, TkGate will remember the modules you have opened on a stack. The modules on the stack will be displayed in red, with an underline under the module currently displayed in the editor. To close a module, and return to the parent module on the stack, right click in a blank area on the canvas and select " Close".

    3.4 Creating and Manipulating Modules

    3.4.1 Creating Modules


    (Click to Enlarge)

    Figure 3.4: Module Creation
    To create a new module, press the button on the toolbar. This will open the dialog box shown in Figure 3.4. After you have opened the dialog box, choose a name for your module and enter it into the "Name" field. Next, choose a module type. A "netlist" module is one that is defined graphically by connecting gates and other modules, and "HDL" module is one that is defined by typing a text description of the module. You can not change the type once the module has been created. In order to change the type, you must delete the module and create a new one of the new type.

    There are also several property flags that you can set for your module:

    • Prevent editing of module definition: While this property is set, editing of the definition (inside) of the module is disabled. However, you can still open the module to view the definition.
    • Prevent all interface changes: While this property is set, editing of the module interface (size of box, position of ports, etc.) is disabled.
    • Prevent edit mode interface changes: While this property is set, editing of the module interface is disabled in the edit window, but the interface can still be modified through the interface editor.
    • Block resize port position handling: This property controls how port positions will be handled when you change the size of the box of a module interface. If you select "scaled" the distance between ports will grow and shrink proportionally as you expand and contract the box. If you select "fixed" the position of the ports will remain constant, and their position will constrain the minimum size of the box you can use for a module.

    3.4.2 Editing Module Properties


    (Click to Enlarge)

    Figure 3.5: Module Properties
    You can edit the property flags of a module by right clicking on the module name in the module list and selecting " Properties...". This will bring up a dialog box like the one shown in Figure 3.5. The dialog box will show the name of the module, the name of the file from which that module was loaded, and the type of the module (netlist or HDL). These properties can not be modified. The modifiable attributes of modules are the same as those previously described in Section 3.4.1 Creating Modules.

    3.4.3 Deleting, Copying and Renaming Modules


    (Click to Enlarge)

    Figure 3.6: Module Deletion
    To delete a module implementation, right click on a module in the module list and select " Delete". This will bring up the dialog box shown in Figure 3.6. Press "OK" to delete the module. You can also change the module to be deleted by selecting its name from the drop down list. Any instances of the deleted module used in your design, will not be deleted. If you attempt to simulate, you will get an undefined module error.

    (Click to Enlarge)

    Figure 3.7: Copying Modules

    To copy a module implementation, right click on the module to be copied from the module list and select " Copy". This will bring up a dialog box like the one shown in Figure 3.7. Make sure the "From" field shows the name of the module you wish to copy. Enter the name of the new module in the "To" field. This will copy both the module definition and the module interface. The new module will appear in the list, or under the "Unused" tree in the hierarchy view.


    (Click to Enlarge)

    Figure 3.8: Renaming Modules
    To rename a module implementation, right click on the module to be copied from the module list and select " Rename". This will bring up a dialog box like the one shown in Figure 3.8. Make sure the "From" field shows the name of the module you wish to copy. Enter the new name for the module in the "To" field.

    3.4.4 Claiming Modules


    (Click to Enlarge)

    Figure 3.9: Claiming Modules
    Sometimes you may wish to modify a module that is part of a library. But since modules that are part of a library can not be modified, you must "claim" that module before you can make any changes. Claiming the module make that module part of your design, rather than part of the library. This allows you to edit and make changes to the module. When you save your design, your version of the module will be saved.

    Since modules that are defined in your design take precedence over library modules, the next time you load your design, the claimed module will continue to be used in lieu of the library version of that module. If you later decide that you would like to revert to the library version, you can delete the module, and reload the library.

    To claim a module, right click on the module to be copied from the module list and select " Claim". This will bring up a dialog box like the one shown in Figure 3.9. Make sure the "Name" field shows the name of the module you wish to claim. The symbol next to the module will change to or to indicate that that module is now part of your design.

    Only modules that are part of a library can be claimed. If you attempt to open the claim dialog box when there are no library modules in your circuit, you will get an error message.

    3.4.5 Setting the Top-Level Module


    (Click to Enlarge)

    Figure 3.10: Setting Top-
    Level Module
    The top-level module is the highest-level module in your hierarchy. It is the module that appears at the top of the hierarchy view and is indicated by the symbol. When simulating your circuit, only modules that are reachable from the top-level module are simulated.

    To set the top-level module, right click on the module and select " Set As Root". This will bring up a dialog box like the one shown in Figure 3.10. Make sure the "Name" field shows the name of the correct module. The module hierarchy view will be recomputed with the new module as the top-level module.

    3.5 Editing Module Definitions

    a) Input Portb) Output Port
    c) Inout Port
    Figure 3.11: Module Ports
    To edit the definition of a netlist module, open the module as described in section 3.3.2 Navigating to Modules. Within the module you can use any of the gates you would use at a higher level including more module instances. Signals as passed between the inside and outside through special circuit elements called ports. There are three types of ports: input, output and inout. These are shown in Figure 3.11a, b and c, respectively. Internal module ports are created the same way as other gates. Right click at the position you wish to create it and select "Module Input", "Module Output" and "Module InOut" from "Module" under the "Make" menu. When you are creating a port, the net properties dialog box will appear to allow you to set the name of the port. Enter a name, and click OK to create it. The wire connected to the port will have the same net name as the port.

    The ports you define as part of the internal definition of a module must match the ports that you define on the interface, both in the names used, the type (input, output or inout), and the bit size. If you have already created the interface, then you can click on the "Ports" tab on the lower left-hand side of the main window to see what ports have been created on the interface.

    3.6 Editing Module Interfaces


    (Click to Enlarge)

    Figure 3.12: Module Interface List
    The interface of a module, is its external appearance when it is included by a higher-level module. It includes the number and names of the ports, as well as their position. Each module has a canonical interface which is stored as part of the module definition when you save your design. Individual instances of a module have an interface as well which may or may not match the canonical interface. If you make changes to the interface of a module after you have created one or more instances of it in your circuit, you may need to go back and fix those instances.

    While it is possible to edit the interface of a module directly in edit mode then choose "Interface → Set" to make that instance the canonical instance, this is not the recommended way of creating interfaces. The preferred way is to use the interface editor. To use the interface editor, select the "Interface" tab in the main edit window.

    If you have the top-level module selected, the interface editor will display a graphical representation for the interfaces of all modules loaded in your design as shown in Figure 3.12. You can edit the interfaces directly on this page, or you can double click on a module, either its graphical form or its name in the module list, to open the single-module interface editor.

    There are two basic types of module interfaces: standard interfaces, and symbol interfaces. A standard interface is a rectangular box with ports on the edges of the box. A symbol interface is an arbitrary user-defined symbol created through a bitmap editor. Most of the time, you will likely use standard interfaces, but if you wish to create your own gates, you can create your own symbols for them.

    3.6.1 Standard Module Interfaces


    (Click to Enlarge)

    Figure 3.13: Module Interface Editor
    Figure 3.13 shows the single-module interface editor for a module with a standard interface. At the top of the "Interface Properties" box, is a selector that lets you choose between the "Standard" and "Symbol" interface types. While the module is open, you can switch back and forth between the two types without losing any work you have done on either interface. Below the interface type selector, are the module properties. These are the same properties that can be specified through the module creation and module properties dialog boxes.

    Editing Through The Port List
    Below the "Interface Properties" box, is the "Port List". The Port List lists all of the ports on the module. For each port, the list includes the name of the port, the type (input, output, or inout), the bit width, and the side of the module box on which the port it attached. To change a value, double click on it. For the port name, you can enter a new port name. Names that begin with a '_' will be displayed with an over-bar to indicate that they are active low signals. For the other fields, a drop down selector will appear allowing you to change the value. Click anywhere outside the open value to close it and make the change effective. Your changes will be reflected in the graphical view of interface. You can also hit the tab key to advance and enter a value for the next field.

    To add a new port, you can either double click on the next empty line in the port list, or press the "Add" button. TkGate will attempt to guess an appropriate name for the new port, but you can type in your own name if you prefer. To delete a port, select it and press the "Delete" button.

    You can reorder the ports by selecting and dragging them up or down in the port list. Ports that are on the same "Side" will be arranged in the same in both the port list and in the graphical representation of the interface.

    Graphical Editing

    (Click to Enlarge)

    Figure 3.14: Port Parameters
    You can also edit the interface graphically. To change the size of the box, grab a corner or side with the mouse and drag in it or out. To edit the properties of a port, double click on its name in the graphical representation of the interface. The Port Parameters dialog box shown in Figure 3.14 will appear allowing you to change the name, type and bit size of the port. The new values will be updated in the port list after you click "OK".

    To add a new port, right click on the edge of the rectangle at the point you wish to add the port and select "Add Input..", "Add Output.." or "Add InOut..". The Port Parameters dialog box will appear in this instance too allowing you to enter the port name and bit size. To delete a port, use the tool and "cut" the wire off the edge of the interface.

    To reposition ports, grab them and slide them back and forth on the edge to which they are attached. However, to change the edge to which they are attached, you will need to change the "Side" in the port list.

    3.6.2 Automatic Interface Generation


    (Click to Enlarge)

    Figure 3.15: Interface Generator
    Rather than manual edit the interface of a module, you can automatically generate an interface after you have completed the internal definition of a module. To do this, open the module in the interface editor and press the "Auto Generate..." button. This will bring up the Interface Generator dialog box shown in Figure 3.15. Select the module for which you wish to create an interface, then choose "Port Selection" and "Port Positions" options.

    The port selection option tells the interface generator which ports should be included on the generated interface. The possible options are:

    • Use ports used in module only: Only ports that are used in the definition of the module will result in ports on the interface. If you have not created the internal definition yet, then no ports will be generated.
    • Use ports from existing interface only: Only ports that are used on the current interface will be used. This option can be used when you want to regenerate the positions of the ports.
    • Use both module and interface ports: Ports that are used either in the definition, or in the current interface will be generated on the new interface.

    The port position option tells the interface generator how the ports on the new interface should be positioned. The possible options are:

    • Keep existing port position when possible: If regenerating an interface, the positions of ports that have already been positioned will not be modified. Only new ports will be positioned.
    • Regenerate all port positions: Existing positions of any ports on the current interface will be ignored, and a new interface will be generated from scratch.

    3.6.3 Symbolic Module Interfaces


    (Click to Enlarge)

    Figure 3.16: Symbol Interface Editor
    You can use the built-in bitmap editor to design your own symbols for modules that you create. Open the module in the interface editor and select "Symbol" for the interface type. The symbol editor includes a bit map editor on the top, and a view of your device on the bottom. You can edit the ports in the port list in the same way as for standard modules. Drag the name of any newly created ports onto the bit-map editor to allow you to position it.

    You must create an "Unselected" and a "Selected" version of your symbol. The "Unselected" version is the appearance when the symbol is not selected, and the "Selected" version is the appearance when you have selected it in the editor. Normally you can just draw the "Unselected" version, copy and paste it into the "Unselected" version, then press the button on the toolbar to automatically boldify your symbol. However, you may want to use the editor to do some final touch-ups.

    There are six symbol editor tools that you can use in designing your symbol:

    ToolDescription
    Bit Tool - Click the left mouse button to set a bit, and the right mouse button to clear a bit. You can also press and hold the mouse button to set/clear multiple bits and you move the mouse.
    Line Tool - Click and hold the left mouse button to set one end of the line, and drag the mouse to the other end and release to draw a line. The same action with the right mouse button will clear a line.
    Rectangle Tool - Click and hold the left mouse button to set one corner of the rectangle, and drag the mouse to the other corner and release to draw a rectangle. The same action with the right mouse button will clear the rectangle.
    Filled Rectangle Tool - Click and hold the left mouse button to set one corner of the filled rectangle, and drag the mouse to the other corner and release to draw a filled rectangle. The same action with the right mouse button will clear the filled rectangle.
    Port Tool - Use this tool to select and manipulate ports. Click and drag the port to move it. Use the and buttons to rotate the port clockwise or counter-clockwise.
    Area Select Tool - This tool allows you to select a rectangular area, then use the cut, copy and paste tools. There are two types of paste operations. A normal paste overwrites all bits with the contents of the cut buffer. The overlay paste , pastes only the bits that are set in the cut buffer, combining the cut buffer with the existing image. The selection also limits the scope of the bit shifting and rotating operations to the selection.

    You can also use the and buttons to rotate the image clockwise or counter-clockwise, or the shift buttons such as to shift the bits left, right, up or down. You can use the area selection tool to limit the scope of these operations to the selected area.
    tkgate-2.0-b10/doc/popupmenu.html000644 001751 001751 00000003522 10645765477 017520 0ustar00hansenhansen000000 000000

    ContextDescription
    WirePopop menus for wires allow you to open the properties box for the wire, or add a branch segment to a wire to allow you to connect it to another gate or wire.
    GatePopup menus for common gates allow you to open the properties box for the gate, set or clear the anchor flag, or delete the gate.
    Variable Input Gate For variable input gates such as AND and OR gates, you can also add inputs through the popup menus in addition to the standard gate functions.
    Multi-Gate SelectionWhen multiple gates are selected, you can set or clear the anchor flag for all of the gates in the selection, or delete the entire selection.
    4-Wire JointThe popup menu for joint with four attached wire contains only the anchor set/clear option.
    3-Wire JointFor joints with three wires attached, an additional add wire segment option allows you to attach a wire to the unused side of the joint.
    ModuleIn addition to the standard gate functions, the popup menu for modules also allows you to open the block, mark the block as the standard interface for a module type, and add/change ports to/on the module.
    CanvasRight clicking on the canvas where there are no objects brings up a popup menu with options to close the current module, create a gate/module or change the current tool.
    Non-Move Mode When TkGate is not in Move/Connect mode, only the close module and change tool options are enabled
    simulationWhen in simulation mode, the popup menu allows you to use any of the simulation menu functions.
    tkgate-2.0-b10/doc/menagerie.html000644 001751 001751 00000133413 10652241314 017400 0ustar00hansenhansen000000 000000 TKGate User Documention (Index)

    E. Sample Gmac Input File

    This appendix contains a complete listing of the Gmac input file for the Menagerie CPU including as a sample circuit. 

    //
//    Copyright (C) 1987-2000 by Jeffery P. Hansen
//
//    This program is free software; you can redistribute it and/or modify
//    it under the terms of the GNU General Public License as published by
//    the Free Software Foundation; either version 2 of the License, or
//    (at your option) any later version.
//
//    This program is distributed in the hope that it will be useful,
//    but WITHOUT ANY WARRANTY; without even the implied warranty of
//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
//    GNU General Public License for more details.
//
//    You should have received a copy of the GNU General Public License
//    along with this program; if not, write to the Free Software
//    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
//
//    Last edit by hansen on Thu Jul 26 20:56:44 2007
//

// Microcode memory bank declarations

microcode bank[31:0] iunit.m1;
microcode bank[63:32] iunit.m2;
map bank[7:0] iunit.map;

macrocode bank[7:0] memory.m1;

// Microcode field declarations

//
// Microcode branching.  mpcop specifies the basic operation.
//
field mpcop[1:0]={
	 next=0,	// Increment mpc
	 reinit=1,	// Restart CPU
	 jmap=2,	// Jump from map value
	 jump=3		// Jump from condition
};

//
// Specifies the condition on which to jump if mpcop is "jump".
//
field mpccond[12:10]={
	jne=0,		// Jump if not equal
	jcarry=1,	// Jump on carry
	jeq=2,		// Jump if equal
	jlt=3,		// Jump if less than
	jgt=4,		// Jump if greater than
	jle=5,		// Jump if less than or equal
	jge=6,		// Jump if greater than or equal
	jmp=7		// Jump always
};

//
// Address to jump to if mpcop is "jump" and condition specified
// by mpccond is true.  This field can not be used at the same
// time as the idata field.  
//
field mpcaddr[9:2];

//
// Specifies 8 bits of data to be used by the EUNIT.  This field
// can not be used on jump microinstructions.
//
field idata[9:2];

//
// Specifies the A and B operands of the ALU.
//
//	qreg		Use Q register
//	din		Use data in
//	idata		Use idata field from microinstruction
//	reg		Use register file
//
field aop[15:14]={qreg=0, din=1, idata=2, reg=3};
field bop[17:16]={qreg=0, din=1, idata=2, reg=3};

field ~ldir[13];	// Load instruction register
field cin[18];		// Carry in
field ~clq[19];		// Clear Q register
field ~ldq[20];		// 16-bit load of Q register
field ~lddata[21];	// Load EUNIT data from external bus
field ~ldopr[22];	// Load operand register
field ~wa[23];		// Write register file on SA
field sa[27:24];	// Register address A
field sb[31:28];	// Register address B

//
// These fields specify the ALU function.
//
field ALU_FUNC[36:32];
field ALU_SHOP[33:32]={arshift=0, lshift=1, rshift=2, roll=3};
field ALU_BCOMP[32];
field ALU_AZERO[33];
field ALU_OP[36:34]={shift=0,xor=1,and=2,or=3,mul=4,add=5,mod=6,div=7};

field ~incpc[37];	// Increment PC
field ~ldmar[38];	// Load MAR
field ~ldmdr[39];	// Load MDR
field ~ldpc[40];	// Load PC
field ~rd[41];		// Read main memory
field ~rdmdr[42];	// Read MDR onto external data bus 
field ~wrt[43];		// Write main memory
field spc[44];		// Address main memory from PC
field ~isa[45];		// Use sa address from macro instruction
field ~isb[46];		// Use sb address from macro instruction
field ~ifunc[47];	// Use function code from macro instruction
field ~icond[48];	// Use branch condition from macro instruction
field ~ldql[49];	// 8-bit load of lower half of Q register
field ~ldqh[50];	// 8-bit load of upper half of Q register
field ~dout[51];	// Output EUNIT data to external bus
field ~ldcc[52];	// Load condition code register
field ~ldhmdr[53];	// Load mdr from high byte of data bus
field ~rdpc[54];	// Read PC onto external bus
field ~incmar[55];	// Increment mar (can't use with incpc)

field extra[63:56];	// Extra bits

//////////////////////////////////////////////////////////////////////
//
// +-+-+-+-+-+-+-+-+
// |7|6|5|4|3|2|1|0|
// +-+-+-+-+-+-+-+-+
//
// Basic instruction types are encoded by the high two bits of the 
// first byte of the instruction.  For certain types (e.g., ALU
// types) some bits are masked when forming the map address.  Bits
// contributing to the map vector are marked with a *.
//
// Move Instruction
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 1 1 s|a a|b b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//  * * * * * * * *
//
//  s  = size (1 = byte, 0 = word)
//  aa = operand mode 1
//  bb = operand mode 2
//
// Single operand instruction (push, pop, call, etc.)
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 0|0| op  |b b|   | reg1  |0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//  * * * * * * * *
//
//
// Branch instruction (jmp, jne, etc.)
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 0|1|cond |b b|   | reg1  |0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//  * * *       * *
//
//
// ALU Instruction
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|  func   |b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//  * *           *
//
//  func = ALU function
//  a = operand mode
//
// Other instructions
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 0|   op    |b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//  * * * * * * * *
//
//

registers R0=0, R1=1, R2=2, R3=3, R4=4, R5=5, R6=6, R7=7, R8=8, R9=9, R10=10, R11=11, R12=12, R13=13, FP=14, SP=15;

operands basic {
    %1,%2 = { +0[0] = 0; +1[7:4]=%1; +1[3:0]=%2; };
    %1,#2 = { +0[0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
};

operands runiop {
    %1     = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; };
    #1     = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; };
    (%1)   = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; };
    #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
};

operands wuniop {
    %1     = { +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=0; };
    (%1)   = { +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=0; };
    #2(%1) = { +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
};

//
// Operands for move instructions
//
operands movoprs {
    %1,%2         = { +0[3:2] = 0; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; };
    %1,#2         = { +0[3:2] = 0; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
    %1,(%2)       = { +0[3:2] = 0; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; };
    %1,#3(%2)     = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; };
    %1,(#2)       = { +0[3:2] = 0; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };


    (%1),%2       = { +0[3:2] = 2; +0[1:0] = 0; +1[7:4]=%1; +1[3:0]=%2; };
    (%1),#2       = { +0[3:2] = 2; +0[1:0] = 1; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };
    (%1),(%2)     = { +0[3:2] = 2; +0[1:0] = 2; +1[7:4]=%1; +1[3:0]=%2; };
    (%1),#3(%2)   = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; };
    (%1),(#2)     = { +0[3:2] = 2; +0[1:0] = 3; +1[7:4]=%1; +1[3:0]=0; +2=#2[7:0]; +3=#2[15:8]; };

    #1(%2),%3     = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; };
    #1(%2),#3     = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; };
    #1(%2),(%3)   = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; };
    #1(%2),#4(%3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=%3; +2=#1[7:0]; +3=#1[15:8]; +4=#4[7:0]; +5=#4[15:8]; };
    #1(%2),(#3) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; };

    (#1),%2     = { +0[3:2] = 3; +0[1:0] = 0; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; };
    (#1),#2     = { +0[3:2] = 3; +0[1:0] = 1; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; };
    (#1),(%2)   = { +0[3:2] = 3; +0[1:0] = 2; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; };
    (#1),#3(%2) = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=%2; +2=#1[7:0]; +3=#1[15:8]; +4=#3[7:0]; +5=#3[15:8]; };
    (#1),(#2)   = { +0[3:2] = 3; +0[1:0] = 3; +1[7:4]=0; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; };
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 0|1 1 1 1 1|0|   |0 0 0 0|0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+
//
op nop {
  map nop : 0x3e;
  +0=0x3e;
  operands {
    - = { +1=0; };
  };
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 0|0 0 0 0 0|0|   |0 0 0 0|0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+
//
op halt {
  map halt : 0x0;
  +0=0;
  operands {
    - = { +1=0; };
  };
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 0|0 0 0 0 1|0|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+
//
op cmp {
  map cmp_rr : 0x2;
  map cmp_ri : 0x3;
  +0[7:1]=0x1;
  operands basic;
};

// Generic branch operation
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 0|1|x x x|b b|   |0 0 0 0| reg1  |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
// Example:
//    br  #7, loop
//
// Jump always to loop.  7 is a code indicating the condition always.
//
op jp {
  map br_r : 0xa0;
  map br_i : 0xa1;
  map br_d : 0xa2;
  map br_x : 0xa3;
  +0[7:5] = 0x5;
  operands {
    #1,%2     = { +0[1:0] = 0; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; };
    #1,#2     = { +0[1:0] = 1; +0[4:2] = #1; +1=0; +2=#2[7:0]; +3=#2[15:8]; };
    #1,(%2)   = { +0[1:0] = 2; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; };
    #1,#3(%2) = { +0[1:0] = 3; +0[4:2] = #1; +1[7:4]=%2; +1[3:0]=0; +2=#3[7:0]; +3=#3[15:8]; };
  };
};

op jne {
  +0[7:5] = 0x5;
  +0[4:2] = 0x0;
  operands runiop;
};

op jcarry {
  +0[7:5] = 0x5;
  +0[4:2] = 0x1;
  operands runiop;
};

op jeq {
  +0[7:5] = 0x5;
  +0[4:2] = 0x2;
  operands runiop;
};

op jlt {
  +0[7:5] = 0x5;
  +0[4:2] = 0x3;
  operands runiop;
};

op jgt {
  +0[7:5] = 0x5;
  +0[4:2] = 0x4;
  operands runiop;
};

op jle {
  +0[7:5] = 0x5;
  +0[4:2] = 0x5;
  operands runiop;
};

op jge {
  +0[7:5] = 0x5;
  +0[4:2] = 0x6;
  operands runiop;
};

op jmp {
  +0[7:5] = 0x5;
  +0[4:2] = 0x7;
  operands runiop;
};


// Generic ALU operation
//
// Note this is not a real instruction but is here for illustrative
// purposes only.  Map entries must be made for each function code
// to use this instruction for real.
//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|x x x x x|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
// Example:
//    alu #0x14, R1, R2
//
// Does ALU operation 0x14 (addition) on R1 and R2, storing result in R1.
//
//op alu {
//  map alu_rr : 0x40;
//  map alu_ri : 0x41;
// +0[7:6] = 0x1;
//  operands {
//    #1,%2,%3 = { +0[0] = 0; +0[5:1]=#1; +1[7:4]=%2; +1[3:0]=%3; };
//    #1,%2,#3 = { +0[0] = 1; +0[5:1]=#1; +1[7:4]=0; +1[3:0]=%2; +2=#3[7:0]; +3=#3[15:8]; };
//  };
//};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|1 0 1 0 0|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op add {
  map alu_rr : 0x68;
  map alu_ri : 0x69;
 +0[7:0]=0x68;
  operands basic;
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|1 0 1 0 1|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op sub {
  map alu_rr : 0x6a;
  map alu_ri : 0x6b;
 +0[7:0]=0x6a;
  operands basic;
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|1 0 0 0 0|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op mul {
  map xalu_rr : 0x60;
  map xalu_ri : 0x61;
 +0[7:0]=0x60;
  operands basic;
};

//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|1 1 1 0 0|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op div {
  map xalu_rr : 0x78;
  map xalu_ri : 0x79;
 +0[7:0]=0x78;
  operands basic;
};


//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|1 1 0 0 0|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op mod {
  map xalu_rr : 0x70;
  map xalu_ri : 0x71;
 +0[7:0]=0x70;
  operands basic;
};


//
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 1|0 1 0 0 0|b|   | reg1  |  reg2 |
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
op and {
  map alu_rr : 0x50;
  map alu_ri : 0x51;
 +0[7:0]=0x50;
  operands basic;
};


// Call subroutine
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 0|0|0 0 0|b b|   | reg1  |0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
// Example:
//
//   call	foo, #8
//
// This will perform the following actions:
//   sp = sp - 2
//   [sp] = pc
//   sp = sp - 2
//   [sp] = fp
//   fp = sp
//   sp = sp+8
//   pc = foo
//
op call {
  map call_ri : 0x80;
  map call_ii : 0x81;
  map call_di : 0x82;
  map call_xi : 0x83;
  +0[7:4] = 0x8;
  operands {
    #1,%2     = { +0[1:0] = 0; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; };
    #1,#2     = { +0[1:0] = 1; +1=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; };
    #1,(%2)   = { +0[1:0] = 2; +1[7:4]=%2; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; };
    #1,#2(%3) = { +0[1:0] = 3; +1[7:4]=%3; +1[3:0]=0; +2=#1[7:0]; +3=#1[15:8]; +4=#2[7:0]; +5=#2[15:8]; };

    #1        = { +0[1:0] = 1; +1=0; +2=0; +3=0; +4=#1[7:0]; +5=#1[15:8]; };
  };
};

// Return from subroutine
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |0 0|0 0 0 1 0|0|   |0 0 0 0|0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
// Example:
//
//    ret
//
// This will perform the following actions:
//    sp = fp
//    fp = [sp]
//    sp = sp + 2
//    pc = [sp]
//    sp = sp + 2
//    
//
op ret {
  map ret : 0x4;
  +0=4;
  operands {
    - = { +1=0; };
  };
};

// Push a word on the stack
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  
// |1 0|0|0 0 1|b b|   | reg1  |0 0 0 0|
// +-+-+-+-+-+-+-+-+   +-+-+-+-+-+-+-+-+  ...
//
// Example:
//
//    pushw	R1
//
op pushw {
  map pushw_r : 0x84;
  map pushw_i : 0x85;
  map pushw_d : 0x86;
  map pushw_x : 0x87;
  +0[7:2]=0x21;
  operands runiop;
};


op movb {
  map movb_rr : 0xf0;
  map movb_ri : 0xf1;
  map movb_rd : 0xf2;
  map movb_rx : 0xf3;

  map movb_dr : 0xf8;
  map movb_di : 0xf9;
  map movb_dd : 0xfa;
  map movb_dx : 0xfb;

  map movb_xr : 0xfc;
  map movb_xi : 0xfd;
  map movb_xd : 0xfe;
  map movb_xx : 0xff;

  +0[7:4]=0xf;
  operands movoprs;
};

op movw {
  map movw_rr : 0xe0;
  map movw_ri : 0xe1;
  map movw_rd : 0xe2;
  map movw_rx : 0xe3;

  map movw_dr : 0xe8;
  map movw_di : 0xe9;
  map movw_dd : 0xea;
  map movw_dx : 0xeb;

  map movw_xr : 0xec;
  map movw_xi : 0xed;
  map movw_xd : 0xee;
  map movw_xx : 0xef;

  +0[7:4]=0xe;
  operands movoprs;
};

/////////////////////////////////////////////////////////////////////////////
//
// The microcode for the Menagerie CPU begins here.
//
// The CPU begins executing microinstuctions at address 0.  The instructions
// in the start block are executed only once.  The next block consists of
// the instuction fetch sequnce.  The multiple labels account for partial
// fetches that are done by some of the macrocode routines.
//
// For macro instructions which have no operands or have only only one operand,
// there is usually a plain label for that instruction.  For example the
// microinstruction labeled 'ret' implements the 'ret' macroinstruction.  This
// mapping is defined by the 'map ret : 0x4;' line in the operand declaration
// for the ret macroinstruction.
//
// For macro instructions with multiple addressing modes, labels are generally
// of the form 'op_??' where each character after the '_' denotes an addressing
// mode for an operand.  By convension, the characters:
//
//     r	register direct
//     i	immediate
//     d	register indirect
//     x	indexed
//
// are used.
//
begin microcode @ 0
start:	clq;								// Q <- 0
	idata=0x1 ALU_AZERO ALU_OP=add bop=idata ldqh;			// Q.H <- 1
	ALU_AZERO ALU_OP=add bop=qreg dout ldpc;			// PC <- Q
	mpcop=jump mpccond=jmp mpcaddr=fetch;				// jump to 'fetch'
	mpcop=next;

fetch: 	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
fetch1: incpc spc rd ldmdr rdmdr ldir;					// mdr <- [PC]; PC++; ir <- mdr;
fetch2:	mpcop=jmap rdmdr ldopr;						// opr <- mdr; jump to opcode
	mpcop=next;

halt:	mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1;
	mpcop=jump mpccond=jmp mpcaddr=halt extra=0x1;

//
// Standard ALU operations (add, sub, and, or, etc.)
//
alu_rr:	mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc
		isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr;	// Ra = Ra (op) Rb; CC; jump to fetch
	incpc spc rd ldmdr rdmdr ldir;

alu_ri:	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch ifunc
		aop=reg bop=qreg wa isa ldcc;				// Ra = Ra (op) Q;  CC; jump to fetch
	mpcop=next;

//
// 2-cycle ALU operations (mul, div, mod).  These are the same as the alu_??
// ops except the ALU inputs and function code are held for 2 clock cycles
// due to the longer delay in computing these functions.
//
xalu_rr: mpcop=next ifunc isa isb aop=reg bop=reg;			// Ra (op) Rb;
	mpcop=jump mpccond=jmp mpcaddr=fetch2 ifunc
		isa isb wa aop=reg bop=reg ldcc incpc spc rd ldmdr;	// Ra = Ra (op) Rb; CC; jump to fetch
	incpc spc rd ldmdr rdmdr ldir;

xalu_ri: incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	mpcop=next ifunc isa isb aop=reg bop=qreg;			// Ra (op) Q;
	mpcop=jump mpccond=jmp mpcaddr=fetch ifunc
		aop=reg bop=qreg wa isa ldcc;				// Ra = Ra (op) Q;  CC; jump to fetch
	mpcop=next;

cmp_rr:	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP extra=0x22	
		isa isb aop=reg bop=reg ldcc;				// Ra - Rb; CC; jump to fetch
	mpcop=next;

cmp_ri:	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_BCOMP
		aop=reg bop=qreg isa ldcc;				// Ra - Q; CC; jump to fetch
	mpcop=next;

br_i:	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;

btest:	mpcop=jump mpcaddr=bdojmp icond;				// jump to bdojmp if cond
	mpcop=next;
	mpcop=jump mpccond=jmp mpcaddr=fetch;				// jump to fetch
	mpcop=next;
bdojmp:	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO ALU_OP=add
		bop=qreg dout ldpc;					// PC <- Q, jump to fetch
	mpcop=next;


br_r:	mpcop=jump mpccond=jmp mpcaddr=btest extra=0x10
		isa aop=reg sb=0 bop=reg ALU_OP=add ldq;		// Q <- Ra; jump to btest
	mpcop=next;

br_d:	mpcop=jump mpccond=jmp mpcaddr=btest;
	mpcop=next;

br_x:	mpcop=jump mpccond=jmp mpcaddr=btest;
	mpcop=next;

call_ii:
	// Push the PC
	aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP
		dout ldmar wa extra=0x11;				// SP-2 -> mar; SP = SP - 2;
	rdpc lddata aop=din bop=idata idata=4 ALU_OP=add ldq;		// Q = PC+4
	ALU_AZERO ALU_OP=add bop=qreg dout ldmdr;			// Q.L -> mdr
	wrt;								// [mar] <- mdr;
	incmar ALU_AZERO ALU_OP=add bop=qreg dout ldhmdr;		// Q.H -> mdr; mar++; 
	mpcop=next;
	wrt;								// [mar] <- mdr;
	mpcop=next;

	// Push the FP
	aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP
			dout ldmar wa;					// SP-2 -> mar; SP = SP - 2;
	ALU_AZERO bop=reg sb=0xe ALU_OP=add dout ldmdr;			// FP.L -> mdr
	wrt;								// [mar] <- mdr;
	incmar ALU_AZERO  bop=reg sb=0xe ALU_OP=add dout ldhmdr; 	// SP.H -> mdr; mar++; 
	mpcop=next;
	wrt;								// [mar] <- mdr;

	aop=reg sa=0xe bop=reg sb=0xf
		ALU_AZERO ALU_OP=add wa;				// FP <- SP

	// Dec SP
	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	aop=reg sa=0xf bop=qreg ALU_OP=add wa;				// SP = SP + Q

	// PC = branch address
	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg
		ALU_OP=add dout ldpc;					// PC <- Q
	mpcop=next;

call_ri: mpcop=jump mpccond=jmp mpcaddr=fetch;
	mpcop=next;

call_di: mpcop=jump mpccond=jmp mpcaddr=fetch;
	mpcop=next;

call_xi: mpcop=jump mpccond=jmp mpcaddr=fetch;
	mpcop=next;

ret:	ALU_AZERO bop=reg sb=0xe ALU_OP=add sa=0xf wa dout ldmar extra=0x12;	// SP <- FP; mar <- FP;
	aop=reg sa=0xf bop=idata idata=4 ALU_OP=add wa rd incmar ldmdr;	// SP <- SP+4; mdr <- [mar++]
	ALU_AZERO bop=din lddata ALU_OP=add ldql rd rdmdr incmar ldmdr;	// Q.L <- mdr; mdr <- [mar++]
	ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr;			// Q.H <- mdr;
	ALU_AZERO bop=qreg ALU_OP=add sa=0xe wa rd incmar ldmdr;	// FP <- Q; mdr <- [mar++]
	ALU_AZERO bop=din lddata ALU_OP=add ldql rd incmar rdmdr ldmdr;	// Q.L <- mdr; mdr <- [mar++]
	ALU_AZERO bop=din lddata ALU_OP=add ldqh rdmdr;			// Q.H <- mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch1 
		ALU_AZERO bop=qreg ALU_OP=add dout ldpc;		// PC <- Q; jump fetch1
 	incpc spc rd ldmdr;						// mdr <- [PC]; PC++;


pushw_d: mpcop=next;
pushw_x: mpcop=next;

pushw_r: aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP
		extra=0x13 dout ldmar wa;				// mar <- SP-2; SP = SP - 2;
	aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmdr;		// mdr <- Rb.L;
	wrt;								// [mar] <- mdr;
	aop=reg isa bop=idata idata=0 ALU_OP=add dout ldhmdr incmar;	// mdr <- Rb.H; mar++;
	mpcop=next;
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

pushw_i: incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	aop=reg sa=0xf bop=idata idata=2 ALU_OP=add ALU_BCOMP
		extra=0x13 dout ldmar wa;				// mar <- SP-2; SP = SP - 2;
	aop=qreg bop=idata idata=0 ALU_OP=add dout ldmdr;		// mdr <- Q.L;
	wrt;								// [mar] <- mdr;
	aop=qreg bop=idata idata=0 ALU_OP=add dout ldhmdr incmar;	// mdr <- Q.H; mar++;
	mpcop=next;
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

movw_rr: mpcop=jump mpccond=jmp mpcaddr=fetch2 ALU_AZERO ALU_OP=add
		isa isb wa aop=reg bop=reg ldcc extra=1 
		incpc spc rd ldmdr;					// Ra <- Rb; jump to fetch2; mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldir;					// mdr <- [PC]; PC++; ir <- mdr;

movb_rr: ALU_AZERO ALU_OP=add isb aop=reg bop=reg ldcc extra=1 ldql;	// Q.L <- Rb;
	mpcop=jump mpccond=jmp mpcaddr=fetch2 aop=idata bop=idata
		ALU_OP=add ldqh incpc spc rd ldmdr;			// Q.H <- 0; jump to fetch2;mdr <- [PC]; PC++;
	ALU_AZERO ALU_OP=add bop=qreg isa wa 
		incpc spc rd ldmdr rdmdr ldir;				// Ra <- Q; mdr <- [PC]; PC++; ir <- mdr;


movw_ri: incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO
		aop=reg bop=qreg wa isa ldcc;				// Ra = Q;  CC; jump to fetch
	mpcop=next;

movb_ri:incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO bop=reg sb=0;			// Q.H = 0;
	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_OP=add ALU_AZERO
		aop=reg bop=qreg wa isa ldcc;				// Ra = Q;  CC; jump to fetch
	mpcop=next;

movb_rd:isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout  extra=3;	// mar <- Rb
_mbrd:	rd ldmdr;							// mdr <- [mar]
	mpcop=jump mpccond=jmp mpcaddr=fetch lddata rdmdr isa wa;	// Ra <- mdr
	ALU_OP=add idata=0 bop=idata aop=reg isa ldcc;			// CC

movw_rd: isb aop=idata bop=reg idata=0 ALU_OP=add ldmar dout  extra=3;	// mar <- Rb
_mwrd:	rd ldmdr incmar;						// mdr <- [mar++]
	rd ldmdr lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldql;	// Q.L <- mdr; mdr <- [mar++]
	lddata rdmdr bop=din ALU_AZERO ALU_OP=add ldqh;			// Q.H <- mdr;
	mpcop=jump mpccond=jmp mpcaddr=fetch ALU_AZERO bop=qreg
		ALU_OP=add isa wa ldcc;					// Ra <- Q; CC
	mpcop=next;

movb_rx: incpc spc rd ldmdr extra=9;					// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mbrd rdmdr ldqh
		ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr; goto _mbrd
	isb aop=qreg bop=reg
		ALU_OP=add ldmar dout;					// mar <- Rb+Q;

movw_rx: incpc spc rd ldmdr extra=9;					// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql
		ALU_OP=add ALU_AZERO lddata bop=din;			// mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mwrd rdmdr ldqh ALU_OP=add
		 ALU_AZERO lddata bop=din;				// Q.H = mdr;
	isb aop=qreg bop=reg ALU_OP=add
		ldmar dout;						// mar <- Rb+Q

movb_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc;	// mar <- Ra
_mbdr:	isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout;		// mdr <- Rb
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

movw_dr: isa aop=reg bop=idata idata=0 ALU_OP=add ldmar dout ldcc;	// mar <- Ra
_mwdr:	isb aop=idata bop=reg idata=0 ALU_OP=add ldmdr dout;		// mdr <- Rb.L
	wrt;								// [mar] <- mdr;
	isb aop=idata bop=reg idata=0 ALU_OP=add ldhmdr dout incmar;	// mdr <- Rb.H; mar++;
	mpcop=next;
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

movb_xr: incpc spc rd ldmdr extra=9;					// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mbdr rdmdr ldqh ALU_OP=add
		 ALU_AZERO lddata bop=din;				// Q.H = mdr; jump to _mbdr
	isa aop=reg bop=qreg ALU_OP=add	ldmar dout ldcc;		// mar <- Ra+Q


movw_xr: incpc spc rd ldmdr extra=9;					// mdr <- [PC]; PC++;
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mwdr rdmdr ldqh ALU_OP=add
		 ALU_AZERO lddata bop=din;				// Q.H = mdr; jump to _mwdr
	isa aop=reg bop=qreg ALU_OP=add	ldmar dout ldcc;		// mar <- Ra+Q

movw_xx: mpcop=next  extra=7;
movb_xx: mpcop=next  extra=7;
movw_xd: mpcop=next  extra=7;
movb_xd: mpcop=next  extra=7;
movw_dd: mpcop=next  extra=7;
movb_dd: mpcop=next  extra=7;
movw_dx: mpcop=next  extra=7;
movb_dx: mpcop=next  extra=7;
	mpcop=next  extra=7;

movw_di: isa bop=idata idata=0 ALU_OP=add dout ldmar;			// mar <- Ra
_mwdi:	incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	rdmdr ldqh ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr;
	aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout;		// mdr <- Q.L
	wrt;								// [mar] <- mdr;
	aop=idata bop=qreg idata=0 ALU_OP=add ldhmdr dout incmar;	// mdr <- Q.H; mar++;
	mpcop=next;
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

movb_di: aop=reg isa bop=idata idata=0 ALU_OP=add dout ldmar extra=0x21;// mar <- Ra
_mbdi:	incpc spc rd ldmdr;						// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	aop=idata bop=qreg idata=0 ALU_OP=add ldmdr dout;		// mdr <- Q.L
	mpcop=jump mpccond=jmp mpcaddr=fetch wrt;			// [mar] <- mdr; jump to fetch
	mpcop=next;

movw_xi: incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mwdi rdmdr ldqh
		ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr; goto _mwdi
	isa aop=reg bop=qreg ALU_OP=add dout ldmar;			// mar <- Ra+Q

movb_xi: incpc spc rd ldmdr extra=2;					// mdr <- [PC]; PC++; 
	incpc spc rd ldmdr rdmdr ldql ALU_OP=add ALU_AZERO lddata bop=din; // mdr <- [PC]; PC++; Q.L <- mdr
	mpcop=jump mpccond=jmp mpcaddr=_mbdi rdmdr ldqh
		ALU_OP=add ALU_AZERO lddata bop=din;			// Q.H = mdr; goto _mwdi
	isa aop=reg bop=qreg ALU_OP=add dout ldmar;			// mar <- Ra+Q



nop:	mpcop=jump mpccond=jmp mpcaddr=fetch extra=0x15;
	mpcop=next;
end

/////////////////////////////////////////////////////////////////////////////
//
// General notes on assembler
// Registers are not saved accross function calls unless explicitly saved.
// Functions return values in R1.
// The register R0 is a special "always 0" register.  Writing to R0 will have no
//  effect other than to set condition codes.
//
//
begin macrocode @ 0x100
ttydata:	.symbol	0x11	// tty data in/out register
ttystatus:	.symbol	0x10	// tty status register

//
// Nodes have the format (note that pointers are two bytes):
//
// struct node {
//   struct node *yes_b;
//   struct node *no_b; 
//   char text[100];
// };
//
nsize:	.symbol 104		// Size of a tree node.  That is "sizeof(struct node)".
yes_b:	.symbol	0		// Pointer to yes side
no_b:	.symbol	2		// Pointer to no side
text:	.symbol 4		// Text of node (animal name or question)

//
// Execution starts here.
//
start:
	movw	SP, 0		// Initialize stack pointer
	movw	FP, 0		// Initialize frame pointer

	call	main		// Call main program

sdone:	jmp	sdone		// Infinite loop when main ends


////////////////////
//	main()
//
.proc main
	movw	R13, mend	// Use R13 as a sort of heap pointer

	pushw	welcome		// Push the "Welcome to" message
	call	printf		// Print the message
	add	SP,2		// Restore stack pointer

	movw	(root),top_node	// Initialize root node
	movw	(known),1	// Know one animal

loop:
	pushw	think		// Push the "Think of an animal..." message
	call	printf		// Print the message
	add	SP,2		// Restore stack pointer

	movw	R1, (known)	// Put number of known animals in R1
	pushw	R1		// Push that number on the stack
	pushw	numk		// Push the "I know %d animals" message
	call	printf		// Call printf to print message
	add	SP,4		// Restore stack

	movw	R1,(root)	// Put the root pointer in R1
	pushw	R1		// Push the pointer on the stack
	call	find_animal	// Ask questions to find animal
	add	SP,2		// Restore the stack
	movw	(root),R1	// Save new root

	jmp	loop		// Go back and guess another animal

	ret			// Return to call (actually we should never get here)
.end

////////////////////
//	find_animal(p)		Find the animal. p is the root node in question tree 
//
.proc find_animal
tree:	.symbol	-2		// Local variable for tree pointer
	sub	SP,2		// Allocate space for local variables

	movw	R1, 4(FP)	// Get the pointer to top node
	movw	tree(FP),R1	// Store it in "tree"

	movw	R2,yes_b(R1)	// Get pointer in "yes" branch of tree
	cmp	R2,0		// Compare against 0
	jne	get_response	// If not 0, then treat as question node

	pushw	R1		// Push pointer to top node
	call	get_final	// As the final question, and insert new node if necessary 
	add	SP,2		// Restore stack
	movw	tree(FP),R1	// Save new root node in "tree"

	jmp	done		// All done, go to final cleanup 

get_response:
	movw	R1,tree(FP)	// Put current node pointer in R1
	movw	R4,R1		// R4 = R1
	add	R4,text		// Add offset to make R4 pointer to question
	pushw	R4		// Push text of question
	call	print		// Print question in tree node
	add	SP,2		// Restore stack

	pushw	qprompt		// Push "?" prompt
	call	print		// Print the "? "
	add	SP,2		// Restore stack

	pushw	buf		// Push address of buffer in which to get response
	call	gets		// Read response from user
	add	SP,2		// Restore stack

	pushw	buf		// Push users response on stack
	pushw	yes		// Push "yes" on stack
	call	strcmp		// Compare the strings
	add	SP,4		// Restore stack
	cmp	R1,0		// Check if R1 was 0
	jeq	say_yes		// If so, user answered "yes", goto say_yes

	pushw	buf		// Push users response on stack
	pushw	no		// Push "no" on stack
	call	strcmp		// Compare the strings
	add	SP,4		// Restore stack
	cmp	R1,0		// Check if R1 was 0
	jeq	say_no		// If so, user answered "no", goto say_no

	pushw	yesno		// Push the "yes or no" error message
	call	print		// Print error message
	add	SP,2		// Restore stack
	jmp	get_response	// Go back and ask again

say_yes:
	movw	R1,tree(FP)	// Put current tree pointer in R1           
	movw	R2,yes_b(R1)	// Put "yes" branch pointer in R2           
	pushw	R2		// Push the yes branch on the stack         
	call	find_animal	// Recursively ask the next question        
	add	SP,2		// Restore the stack                        
	movw	R2,tree(FP)	// Get tree pointer again                   
	movw	yes_b(R2),R1	// Update the "yes" branch                  
	jmp	done		// Finish up and prepare to return to caller 
say_no:
	movw	R1,tree(FP)	// Put current tree pointer in R1           
	movw	R2,no_b(R1)	// Put "no" branch pointer in R2           
	pushw	R2		// Push the no branch on the stack         
	call	find_animal	// Recursively ask the next question        
	add	SP,2		// Restore the stack                        
	movw	R2,tree(FP)	// Get tree pointer again                   
	movw	no_b(R2),R1	// Update the "no" branch                  
	jmp	done		// Finish up and prepare to return to caller

done:
	movw	R1,tree(FP)	// Put new root node in R1
	ret			// Return to caller
.end

////////////////////
//	get_final(p)		Ask final question (at node p), and update tree if necessary.
//
.proc get_final
tree:	.symbol	-2		// Local variable for tree pointer
animal_node:	.symbol	-4	// Local variable for new animal node pointer
discrim_node:	.symbol	-6	// Local variable for new question node pointer
	sub	SP,6		// Allocate space for local variables

get_response:
	movw	R1, 4(FP)	// Get pointer to current node
	movw	tree(FP),R1	// Save it in the 'tree' variable

	movw	R1, 4(FP)	// Put pointer to tree in R1
	add	R1,text		// Advance R1 to animal name text 
	pushw	R1		// Push pointer to animal name on stack
	pushw	isita		// Push the "is it a..." string pointer
	call	printf		// Print the final question
	add	SP,4		// Restore stack

	pushw	buf		// Push buffer for response
	call	gets		// Get the response
	add	SP,2		// Restore the stack

	pushw	buf		// Push response on stack      
	pushw	yes		// Push "yes" on stack         
	call	strcmp		// Compare strings            
	add	SP,4		// Restore stack               
	cmp	R1,0		// See if a 0 was returned     
	jeq	win		// If so, we guessed the animal

	pushw	buf		// Push response on stack      
	pushw	no		// Push "no" on stack         
	call	strcmp		// Compare strings            
	add	SP,4		// Restore stack               
	cmp	R1,0		// See if a 0 was returned     
	jeq	loose		// If so, we did not guess the animal

	pushw	yesno		// Push the "yes or no" error message 
	call	print		// Print it                           
	add	SP,2		// Restore stack                      
	jmp	get_response	// Go back and ask again              

win:
	pushw	winmsg		// Push the (computer) win message
	call	printf		// Print it
	add	SP,2		// Restore stack
	jmp	done		// All done, go finish up and return

loose:
	pushw	loosemsg	// Push the (computer) loose message
	call	printf		// Print it
	add	SP,2		// Restore stack

	pushw	nsize			// Push number of bytes in a node
	call	malloc			// Allocate memory for new animal node
	add	SP,2			// Restore stack
	movw	animal_node(FP),R1	// Put address of new node in animal_node

	movw	yes_b(R1),0		// Intialize yes branches
	movw	no_b(R1),0		// Intialize no branches
	add	R1,text			// Move R1 to point to text area
	pushw	R1			// Push text buffer
	call	gets			// Get animal name
	add	SP,2			// Restore stack

	movw	R1,tree(FP)		// Put pointer to exiting node in R1
	add	R1,text			// Advance to the text field
	pushw	R1			// Push pointer to old animal name
	movw	R1,animal_node(FP)	// Put pointer to new node in R1
	add	R1,text			// Advance to the text field
	pushw	R1			// Push new animal name on stack
	pushw	dscrim			// Push "what is difference" question 
	call	printf			// Print the question 
	add	SP,6			// Restore pointer

	pushw	nsize			// Allocate memory for discrimination node
	call	malloc			// Allocate memory for new discrimination node
	add	SP,2			// Restore stack
	movw	discrim_node(FP),R1	// Put address of new node in discrim_node

	add	R1,text			// Advance pointer to text field of discrimination node
	pushw	R1			// Push pointer to text buffer to input question 
	call	gets			// Input the question
	add	SP,2			// Restore pointer

	movw	R1, (known)		// Put number of known animals in R1
	add	R1,1			// Increment R1
	movw	(known),R1		// Store number of known animals back in "known"

L1:	movw	R1,animal_node(FP)	// Put pointer to new animal node in R1
	add	R1,text			// Advance R1 to the text field
	pushw	R1			// Push new animal name on stack
	pushw	which			// Push the "..correct answer for..." message.
	call	printf			// Print the message
	add	SP,4			// Restore stack

	pushw	buf			// Push text buffer on stack
	call	gets			// Input a "yes" or "no"
	add	SP,2			// Restore stack

	pushw	buf			// Push user response                            
	pushw	yes			// Push string "yes"                             
	call	strcmp			// Compare strings                               
	add	SP,4			// Restore stack                                 
	cmp	R1,0			// Is the result 0?                              
	jeq	L2			// If so, goto L2.  New animal is on "yes" branch

	pushw	buf			// Push user response                            
	pushw	no			// Push string "no"                             
	call	strcmp			// Compare strings                               
	add	SP,4			// Restore stack                                 
	cmp	R1,0			// Is the result 0?                              
	jeq	L3			// If so, goto L3.  New animal is on "no" branch

	pushw	yesno			// Push the "yes or no" error message 
	call	printf			// Print it                           
	add	SP,2			// Restore stack                      
	jmp	L1			// Go back and ask again              

//
// Insert new animal on yes branch of new question
//
L2:	movw	R1,discrim_node(FP)	// Put new question node in R1 
	movw	R2,tree(FP)		// Put old animal node in R2   
	movw	R3,animal_node(FP)	// Put new animal node in R3   
	movw	yes_b(R1),R3		// Set yes branch to new node  
	movw	no_b(R1),R2		// Set no branch to old node   
	movw	tree(FP),R1		// Save R1 to tree pointer     
	jmp	done			// Finish up and return        

//
// Insert new animal on no branch of new question
//
L3:	movw	R1,discrim_node(FP)	// Put new question node in R1 
	movw	R2,tree(FP)		// Put old animal node in R2   
	movw	R3,animal_node(FP)	// Put new animal node in R3   
	movw	yes_b(R1),R2		// Set yes branch to old node  
	movw	no_b(R1),R3		// Set no branch to new node   
	movw	tree(FP),R1		// Save R1 to tree pointer     
	jmp	done			// Finish up and return        

done:
	movw	R1,tree(FP)		// Put tree pointer into return register R1
	ret				// Return to caller
.end

////////////////////
//	malloc(n) -> p	Allocate n bytes and return address in R1.  Allocated memory
//			can not be freed.
//
.proc malloc
	movw	R2, 4(FP)	// Get number of bytes
	movw	R1,R13		// Pointer to block of memory
	add	R13,R2		// Update heap pointer
	ret
.end

////////////////////
//	print(s)	Print the string s
//
.proc print
	movw	R1, 4(FP)	// Get parameter (string address)
loop:	movb	R2, (R1)	// Put character R1 is pointing to in R2
	jeq	done		// If it was a 0, this is the end of the string
	movb	(ttydata),R2	// Move char to the tty data register
	movb	(ttystatus),#1	// Signal tty controller to print character
	add	R1, #1		// Move pointer to next char
	jmp	loop		// Go back and print more
done:	ret
.end

////////////////////
//	printf(s,...)	Print the format string 
//
.proc printf
ptr:	.symbol	-2		// Local var for string pointer
arg:	.symbol -4		// Local var for argument pointer
	sub	SP,4		// Allocate 4 bytes for local variables

	movw	R3,FP		// Assign R3 and add an offset so that it points 
	add	R3,6		//   to the argument after the control string

	movw	R1, 4(FP)	// Put the control string pointer in R1
loop:	movb	R2, (R1)	// Get the next char from control string
	jeq	done		// If it was a 0, this is the end of the string

	cmp	R2, '%'		// See if it is the '%' character
	jne	cout		// If not goto cout, and simply print it

	add	R1,1		// Advance the string pointer
	movb	R2,(R1)		// Get the next char
	add	R1,1		// Advance the string pointer again

//switch (R2)
L1:	cmp	R2,'s'		// See if this is a "%s" conversion
	jne	L2		// If not, goto L2

// case 's' :
	movw	ptr(FP),R1	// Save the string pointer value
	movw	arg(FP),R3	// Save the argument pointer value
	movw	R2,(R3)		// Get address of string (from arguments) to print
	pushw	R2		// Push it on the stack
	call	print		// Print the string
	add	SP,2		// Restore stack pointer
	movw	R1,ptr(FP)	// Restore string pointer value
	movw	R3,arg(FP)	// Restore argument pointer value
	add	R3,2		// Advance argument pointer to next argument
	jmp	loop		// Go back and print more

L2:	cmp	R2,'d'		// See if this is a "%d" conversion
	jne	loop		// If not, ignore unknown conversion

// case 'd' :
	movw	ptr(FP),R1	// Save the string pointer value
	movw	arg(FP),R3	// Save the argument pointer value
	movw	R2,(R3)		// Get number (from arguments) to print
	pushw	R2		// Push it on the stack
	call	nprint		// Go print the decimal number 
	add	SP,2		// Restore stack pointer
	movw	R1,ptr(FP)	// Restore string pointer value
	movw	R3,arg(FP)	// Restore argument pointer value
	add	R3,2		// Advance argument pointer to next argument
	jmp	loop		// Go back and print more

cout:
	movb	(ttydata),R2	// Put character in tty data register
	movb	(ttystatus),#1	// Signal tty controller to print character
	add	R1, #1		// Advance to next char in control string
	jmp	loop		// Go back and print more

done:	ret			// All done, return to caller 
.end

////////////////////
//	nprint(d)	Print the number d in decimal
//
.proc nprint
	movw	R1, 4(FP)	// Move argument value to R1
	jeq	zprint		// If it was zero, goto zprint

	pushw	R1		// Push value to print on stack
	call	nprint_aux 	// Call aux function to print number
	add	SP,2		// Restore stack pointer
	ret			// All done, return to caller 

zprint:	movb	(ttydata), '0'	// Put the ascii value of '0' in tty data register
	movb	(ttystatus), #1	// Signal tty controller to print character
	ret			// All done, return to caller 
.end

////////////////////
//	nprint_aux(d)	Print the number d in decimal (but prints nothing if d is zero)
//
.proc nprint_aux
digit:	.symbol	-2		// Digit to print
	sub	SP, 2		// Allocate space for local variables

	movw	R1, 4(FP)	// Get argument
	jeq	done		// If zero, return

	// To print the number n we compute
	//     R2 = n / 10, and 
	//     R3 = n % 10
	// We can then recursively call nprint_aux to print all
	// but the lowest digit, then print the lowest digit ourselves
	//
	movw	R2, R1		// R2 = R1
	div	R2, 10		// R2 = R2 / 10
	movw	R3, R1		// R3 = R1
	mod	R3, 10		// R3 = R3 % 10
	movw	digit(FP),R3	// save lowest digit value

	pushw	R2		// Push the higher digits
	call	nprint_aux	// Recursively call ourselves to print them
	add	SP,2		// Restore stack pointer

	movw	R3,digit(FP)	// Restore digit value
	add	R3, '0'		// Add ascii for '0' to get ascii for digit
	movb	(ttydata),R3	// Put char in tty data register
	movb	(ttystatus),#1	// Signal tty controller to print character
done:
	ret			// All done, resturn to caller
.end

////////////////////
//	strcmp(a,b)		Compare strings a and b
//
.proc	strcmp
	movw	R2,4(FP)	// Get pointer to first string
	movw	R3,6(FP)	// Get pointer to second string

loop:	movb	R1,(R2)		// Get next char from R2
	jeq	eos		// If end of string, goto eos
	movb	R4,(R3)		// Get next char from R3
	jeq	eos		// If end of string, goto eos

	sub	R1,R4		// Compute difference in R1
	jne	done		// If difference was not 0, we are done

	add	R2,1		// Advance to next char in R2
	add	R3,1		// Advance to next char in R3
	jmp	loop		// Go compare more

eos:
	movb	R4,(R3)		// Get next char from R3 again (in case R1 was eos)
	sub	R1,R4		// Compute difference in R1

done:
	ret			// Return to caller, result is in R1
.end


////////////////////
//	gets(b)		Reads chars from tty into b.
//
.proc gets
	movw	R1, 4(FP)	// Get pointer to buffer
	movw	R4,R1		// Save starting pointer in R4

	//
	// Poll for a characcter
	//
cwait:	movb	R2,(ttystatus)	// Get ready status
	and	R2, #2		// Test if a char is ready
	jeq	cwait		// If not, go back and wait some more

	movb	R3,(ttydata)	// Get char from tty data register
	movb	(ttystatus),#2	// Signal char received
	cmp	R3,'\r'		// Compare against return char
	jeq	done		// Exit if return received

	cmp	R3,'\b'		// Compare against backspace char
	jeq	del_char	// Delete char if backspace

	cmp	R3,0x7f		// Compare against delete char
	jeq	del_char	// Delete char if delete character

	movb	(ttydata),R3	// Put char to echo in tty data register
	movb	(ttystatus),#1	// Signal tty controller to print character

	movb	(R1),R3		// Save in buffer
	add	R1,1		// increment pointer

	jmp	cwait		// Go back and get another char

del_char:
	cmp	R1,R4		// Compare current pointer against start of line
	jle	bell		// If already at start of line, ring bell

	movb	R3, 0x7f	// Make sure delete char is in R3
	sub	R1,1		// Decrement pointer
	movb	(ttydata),R3	// Echo backspace
	movb	(ttystatus),#1	// Signal tty controller to print character

	jmp	cwait		// Go back and get another char

bell:	
	movb	R3, 7		// Put bell char in R3
	movb	(ttydata),R3	// Echo bell
	movb	(ttystatus),#1	// Signal tty controller to print character
	jmp	cwait		// Go back and get another char

done:
	movb	(ttydata),'\n'	// Output newline
	movb	(ttystatus),#1	// Signal tty controller to print character
	movb	(R1),0		// Put eos in the string we just read
	ret			// Return to caller
.end

buf:	.bss	128		// Buffer for input
known:	.bss	2		// Number of animals known
root:	.bss	2		// root of animals tree

top_node:
	.short	0		// Pointer to "yes" node
	.short	0		// Pointer to "no" node
	.byte	"aardvark",0	// Animal name or question text

welcome: .byte	"\nWelcome to Animals.\n", 0
think:	.byte	"\nThink of an animal and I will try to guess what it is.\n", 0
numk:	.byte	"I currently know %d animals.\n\n", 0
isita: 	.byte	"Is the animal you are thinking of a %s? ",0
yes:	.byte	"yes",0
no:	.byte	"no",0
yesno:	.byte	"Please type 'yes' or 'no'.\n",0
winmsg:	.byte	"I guessed your animal!!!\n\n",0
loosemsg: .byte	"I could not guess your animal.  What was your animal? ",0
dscrim:	.byte	"Enter a question that would distinguish a %s from a %s.\n> ",0
which:	.byte	"The correct answer for a %s is? ",0
nl:	.byte	"\n",0
qprompt: .byte	"? ",0
mend:

end
    tkgate-2.0-b10/doc/gateLibrary.html000644 001751 001751 00000037551 10653756674 017744 0ustar00hansenhansen000000 000000 TKGate User Documentation (Libraries)

    9. TkGate Library Components

    The TkGate distribution includes four libraries that can be loaded through the library manager. Components from these libraries can be used to add additional functionality to your designs. To use one of the libraries, open the library manager with the toolbar button and select the library you wish to load. You can then locate the module you wish to use in the module hierarchy and drag it onto the main window canvas to create an instance of it. The libraries that are available with TkGate are described in the following sections.

    9.1 TTY


    (Click to Enlarge)

    Figure 9.2: TTY Device Window
    The TTY library, tty provides a Virtual Peripheral Device (VPD) modeling a TTY device. The TTY supports input and output and models an interactive TTY terminal. You can use it in your design to provide textual interaction with the user. When you start the simulator, one TTY window will appear for each instance of a TTY VPD in your design. Your design can send characters to and receive characters from the TTY device.



    Figure 9.1:
    TTY Device

    To use the TTY device, open the library manager with the toolbar button and load the "tty" library. You can then locate the module in the module list or module hierarchy and drag it onto the main window canvas to create an instance of it. Figure 9.1 shows the external view of the TTY instance which is defined with a symbolic module interface.

    When a design containing the TTY device is simulated, it will open a window such as the one shown in Figure 9.2 (after the design has been running for a while). The text shown in this window was transmitted from the "Menagerie CPU" example. Keys pressed while the window has focus will be transmitted back to the controlling design.



    Figure 9.3:
    Transmit Character
    To send a character to a TTY device, use the following protocol (see Figure 9.3):
    • Unassert the DSR line.
    • Wait for the DTR (Data Terminal Ready) line to be low.
    • Drive the RD line with the ASCII code of the character to be transmitted.
    • Assert the DSR (Data Set Ready) line.
    • Wait for the DTR line to go high.
    • Unassert the DSR line



    Figure 9.4:
    Receive Character
    To receive a character from the TTY device, use the following protocol(see Figure 9.4):
    • Unassert the CTS line.
    • Wait for the RTS line to go high.
    • Read the received value on the TD line.
    • Assert the CTS line.
    • Wait for the RTS line to go low.
    • Unassert the CTS line.

    Note that transmitting a character to the TTY uses "RD" and receiving a character from the TTY uses "TD" because the RD and TD are named from the perspective of the TTY device.

    9.1.1 Forcing TTY Characters from Simulation Scripts

    You can use a simulation script to force input into a TTY device. This is done by using a special named channel "instaname.FORCE" where "instaname" is the fully instantiated instance name of the TTY. You can use the     $tkg$send system task to send the string to be forced. For example, to force the input "Hello World" into the TTY named "main.memory.tty0", you could use the simulation script: 
      initial
    begin
      # 10000 ;
      $tkg$send("main.memory.tty0.FORCE","Hello World");
  end

    9.2 Drink Vending Machine



    Figure 9.5: Drink Machine Device


    (Click to Enlarge)

    Figure 9.6: Drink Machine GUI
    The drink vending machine library, "coke", provides a Virtual Peripheral Device (VPD) modeling a drink vending machine. The device provides input and output signals for the actuators and sensors in the virtual vending machine. You can use this device to design a vending machine circuit that controls an interactive model of a vending machine.

    To use the drink machine device, open the library manager with the toolbar button and load the "coke" library. You can then locate the cokemachine module in the module hierarchy and drag it onto the main window canvas to create an instance of it. Figure 9.5 shows the external view of the cokemachine instance.

    The virtual drink vending window that appears when you start the simulation is shown in Figure 9.6. It is comprised of an external view (left side) and an internal view (right side). The external view includes buttons that can be pressed to make a drink selection, a coin slot, and a bill reader.

    The following interactions can be made through the drink machine GUI:

    • Coins are inserted by dragging them from the user's stock of cash in the upper left corner to the coin slot.
    • Bills are inserted by dragging them from the user's stock of cash in the upper left corner to the bill reader.
    • Fake bills can be dragged to the bill reader to test if the control logic detects and rejects them correctly.
    • Drink selections are made by pressing the drink buttons on the external view.
    • Pressing the coin return lever should cause inserted coins to be returned.
    • Purchased drinks appear in the margin along the bottom.

    The internal view shows the columns of drinks that are available in the machine, the status of the bill scanner, the coins that have been inserted (but not used for a purchase), the coins that have been committed to a purchase, and coins that are available to make change.

    The input signals on the drink machine and their function are as follows:

    SignalDescription
    DISP Dispense - Each of the six bits dispenses a drink from one of the six columns. Drinks are dispensed on the rising edge of the signal. Only one bit should be asserted at a time, and only after ensuring the the DISPACK (Dispense Acknowledge) signal is low. The asserted bit should remain high until the DISPACK signal goes high.
    ELIGHT Empty Light - Each bit corresponds to the empty light on each of the six buttons. If a bit is asserted, then the corresponding empty light will be illuminated.
    CHGQ
    CHGD
    CHGN    		 Dispense Change - Drop a quarter (CHGQ), dime (CHGD) or nickel (CHGN) from the "Change" bin. Only one of these signals (or the CHGCOM or RETINS signals) may be asserted at a time. Change is dropped on the rising edge of the signal. The signal should not be raised unless the CHGACK (Change Acknowledge) signals is low. The Dispense Change signal should be held high until the CHGACK signal goes high.
    NOCHG No Change - If asserted, illuminates the "No Change" light on the vending machine to indicate that change can not be made.
    BILLIN Bill In - Drives the bill motor to feed the inserted bill into the bill tester. Bills in the bill tester will be dropped into the "Collected" bin. The motor is activated on a positive edge of this signal. This signal should not be raised unless the BILLACK (Bill Acknowledge) signal is low. The Bill In signal should be held high until the BILLACK signal goes high.
    BILLLTBill Light - This signal illuminates the light on the bill reader.
    BILLOUT Bill Out - Drives the bill motor to feed out the bill currently in the bill tester. The motor is activated on a positive edge of this signal. This signal should not be raised unless the BILLACK (Bill Acknowledge) signal is low. The Bill Out signal should be held high until the BILLACK signal goes high.
    CHGCOMChange Commit - This signal commits any change in the "Inserted" area to the "Collected" area. Change is committed on the rising edge of this signal. The signal should not be raised unless the CHGACK (Change Acknowledge) signals is low. The Dispense Change signal should be held high until the CHGACK signal goes high.
    RETINSCoin Return - This signal returns any change in the "Inserted" area back to the user. Change is returned on the rising edge of this signal. The signal should not be raised unless the CHGACK (Change Acknowledge) signals is low. The Dispense Change signal should be held high until the CHGACK signal goes high.
    INSACKInsert Acknowledge - This signal should be raised after seeing a positive edge on the INSQ, INSD or INSN signals indicating that a coin was inserted.
    COSTDrink Cost - This signal drives the drink cost displayed on the external view of the vending machine. It should be the cost in nickels.
    RESETReset - Resets the drink machine. This is an active low signal. It should be driven low to reset the machine, then kept high while using the device.

    The output signals on the drink machine and their function are as follows:

    SignalDescription
    PRESSButton Pressed - Each bit is for one of the six buttons on the drink machine and is asserted while the corresponding button is pressed.
    EMPTYEmpty Sensor - Each bit corresponds to one of the drink columns and is asserted when the sensor indicates that there are no more drinks in a column.
    INSQ
    INSD
    INSN    		 Coin Inserted - These signals indicate that a quarter (INSQ), dime (INSD) or nickel (INSN) have been inserted. A rising edge indicates the insertion. The controlling circuit should assert the INSACK signal to acknowledge the insertion.
    NUMQ
    NUMD
    NUMN    		 Change Available - Indicates the number of quarters (NUMQ), dimes (NUMD) and nickels (NUMN) available for making change (up to 7). If there are more than 7 coins of a type available, then the signal will indicate 7.
    BILLSNSBill Sense - A high value indicates that a bill is sensed in the bill insertion slot. The controlling circuit should assert BILLIN to feed the bill into the bill tester
    BILLOKBill OK - A high value indicates that the bill in the bill tester is a valid bill.
    CNRETCoin Return Request - A high value indicates that the user is pressing the coin return lever.
    BILLACKBill Acknowledge - This signal is asserted to acknowledge a BILLIN or BILLOUT signal.
    CHGACKChange Acknowledge - This signal is asserted to acknowledge a CHGQ, CHGD, CHGN, CHGCOM or RETINS signal.
    DISPACKDispense Acknowledge - This signal is asserted to acknowledge a DISP signal.
    BILLNGBill No Good - This signal is asserted to indicate that a fake bill is in the bill tester.

    9.3 Timers and One-Shots

    Timers and one-shots are devices that operate in real time. To use a timer or one-shot device, open the library manager with the toolbar button and load the "timer" library. You can then locate the desired device in the module list or module hierarchy and drag it onto the main window canvas to create an instance of it.

    9.3.1 OSCILLATOR Device


    Figure 9.7:
    Oscillator
    The OSCILLATOR device provides a signal that oscillates at a set frequency in real-world time. You can use it to design circuits such as digital clocks using the LED gates. The default frequency is one hertz. To change the frequency, double click on the OSCILLATOR module to open the     Gate Properties dialog box and select the "Parameters" tab. Set the "HZ" parameter to the desired period in milliseconds.

    9.3.2 ONESHOT Device


    Figure 9.8:
    One Shot
    A one-shot device asserts its output a set time period after being reset by the input. The ONESHOT is triggered by an active low signal. You can connect the input to ground, to cause the ONESHOT device to assert its output after a set amount of real-world time after the simulation begins. Raising the input and lowering it again resets the one-shot. The default delay is one second. To change the time delay of the ONESHOT, double click on it to open the Gate Properties dialog box and select the "Parameters" tab. Set the "HZ" parameter to the desired delay in milliseconds.

    9.4 TTL Devices

    The TTL device library provides access to a small number of commonly used 7400 series TTL modules. To use this library, open the library manager with the toolbar button and load the "74xx" library. You can then locate the desired device in the module list or module hierarchy and drag it onto the main window canvas to create an instance of it. The supported devices are:

    DeviceDescription
    7400Quad 2-input NAND gates
    7402Quad 2-input NOR gates
    7404Hex Inverters
    7408Quad 2-input AND gates
    7410Tri 3-input NAND gates
    74308-input NAND gate
    7432Quad 2-input OR gate
    7474Dual D-Latch, edge triggered with clear and preset
    7486Quad 2-input XOR gates
    741544-16 Decoder
    74157Quad 2-1 Mux
    741634-bit Synchronous Counter
    74175Quad D-Latch, edge triggered with clear

    Please see standard TTL data sheets for a description of these devices. tkgate-2.0-b10/doc/systemTasks.html000644 001751 001751 00000071660 10653756562 020024 0ustar00hansenhansen000000 000000 TKGate User Documentation (System Tasks)

    B. List of System Tasks

    B.1 Data Display Tasks

    The system tasks described in this section generate output to the console. When simulating through the TkGate interface, the output will go to the simulator output console. When simulating in stand-alone mode with "Verga", output will go to the standard output.

    B.1.1 $display

    Usage: $display(arg1, arg2, ... );

    This tasks outputs a message to the standard output when running Verga in standalone mode, and to the simulation console when running under TkGate. A newline is appended to the output. It is similar to the printf() function used in C.

    Unlike the C printf function, the first argument is not necessarily a control string. The $display function can have from zero up to an arbitrary number of control strings. For example: 

         integer r1,r2;

     r1 = 7; r2 = 12;
     $display(r1,r2);
    will print: 
    7 12
    The same output could have been produced with a control string using the statement: 
        $display("%d %d",r1,r2);
    The general rule is that if an argument is a string, then it is treated as a control string and consumes as many arguments after it as there are conversions (e.g., "%d", etc.). If an argument is not a string, its value is printed. The format in which it is printed depends on the variable type. Unsized values are printed in decimal, sized values are printed using the Verilog hexadecimal notation. For example: 
         integer r1;
     reg [16:0] r2;

     r1 = 7; r2 = 12;
     $display(r1,r2);
    will print 
    7 16'hc
    When printing constants and expressions, $display will use the base specified in any constants. For example $display(1'o0+r2) would produce 16'o14.

    You can get greater control of the output using control strings with conversions. Strings are enclosed by the double quote character ("). Use a backslash (\) before a double quote to output the double quote itself and use \\ to output a single backslash character. In addition, you can use "\n" to insert extra newlines into the output.

    The conversions supported in Verga are (case is ignored):

    ConversionDescription
    %%Output a single percent character.
    %mOutput the name of the current module instance.
    %tOutput a simulation time value. The raw simulation time in epochs is converted to the units specified in any `timescale declaration for the current module. If a precision smaller than the units is specified, then the time value will be output with a decimal point and the appropriate number of digits after the decimal point.
    %dOutput a value in decimal format.
    %bOutput a value in binary format.
    %hOutput a value in hexadecimal format.
    %oOutput a value in octal format.
    %cOutput the character with the specified ASCII value.
    %sOutput the value as a string.
    %fOutput the value in floating point format.
    %gOutput the value in floating point format while minimizing the number of characters needed.

    The binary, hexadecimal and octal conversions output the raw number without the leading radix and bit-size indication. For example, 

       $display("%h",8'h1e);
    will output only "1e".

    Like the C printf(), you can specify a number of spaces with the conversion. For example %4h will output a hexadecimal value in a four character field, padding with spaces if necessary. If you use leading zero as in %04h, then Verga will pad the output with zeros if necessary (e.g., "16'h2e" will be output as "002e").

    As a final example including multiple control strings, consider the statement: 

       $display(9," a=%d b=%d ",42, 77, 12,13," c=%d d=%d ",5,9, 88);
    This will produce: 
    9 a=42 b=77 12 13 c=6 d=9 88

    B.1.2 $monitor

    Usage: $monitor(arg1, arg2, ... );

    The $monitor task formats the output from its arguments in exactly the same way as the $display task. The difference is that instead of outputting the text immediately, it places a watch on all variables referenced in the statement and outputs its message any time a variable changes. This can be used to generate a trace of any variable changes.

    As an example, consider this module: 

       module top;
   
     reg [15:0] a,b,c;
     
     initial
       $monitor("%t: a=16'h%04h  b=16'h%04h  c=16'h%04h",$time,a,b,c);
   
     initial
       begin
         #1 a = 'h4ef; b = 'h6def;
         #1 c = 'h84ff;
         #5 b = 42;
   
       end

   endmodule
    When simulated, it will produce the following output: 
    1: a=16'h04ef  b=16'h6def  c=16'hxxxx
2: a=16'h04ef  b=16'h6def  c=16'h84ff
7: a=16'h04ef  b=16'h002a  c=16'h84ff
    Each time any of the variables a, b or c change, the $monitor task will output the stored line. In this example, we set a and b after one time step. The value of c was printed as 16'hxxxx because it is still uninitialized. One time step later, we set c, then five time steps later we set b. This results in output from $monitor at times steps 1, 2 and 7.

    Only one $monitor may be active at a time. If you call $monitor more than once, only the last call will remain in effect.

    B.1.3 $monitoroff

    Usage: $monitoroff;

    This task temporarily disables a $monitor that has been placed. The monitor remains registered, but all output from it is disabled.

    B.1.4 $monitoron

    Usage: $monitoron;

    This task re-enables a $monitor that has been disabled by $monitoroff.

    B.1.5 $strobe

    Usage: $strobe(arg1, arg2, ... );

    The $strobe task formats the output from its arguments in exactly the same way as the $display task. The primary difference is that instead of outputting the message immediately, it waits until the end of the time step and does the output with the values at that time. It can be used when you want to ensure that you are outputting the final value of a variable for the time step. As an example, consider the module: 

     (1)    module top;
 (2)     reg [15:0] a, b, c;
 (3)
 (4)     initial
 (5)       begin
 (6)         a = 4; b = 7; c = a + b;
 (7)         $strobe("%t: strobe a=%d b=%d c=%d",$time,a,b,c);
 (8)         $display("%t: display a=%d b=%d c=%d",$time,a,b,c);
 (9)         a = c*b;
 (10)        c = a + 9;
 (11)        #1 b = a + 99;
 (12)      end
 (13)
 (14)  endmodule
    when this module is simulated, the following output is produced: 
    0: display a=4 b=7 c=11
0: strobe a=77 b=7 c=86
    This $display tasks output the values as they are when $display is called, but $strobe waits until the end of the time step at Line 11 before it generates its output.

    B.1.6 $write

    Usage: $write(arg1, arg2, ... );

    The $strobe task formats the output from its arguments in exactly the same way as the $display task. The only difference is that it does not append a newline. Use this task when you want to use multiple $write statements to construct a line of output. You can use a \n in a string to generate a newline.

    B.2 File Tasks

    The tasks described in this section allow Verilog descriptions to open and write to files.

    B.2.1 $fopen

    Usage: descriptor = $fopen(file-name);

    The $open task opens the specified file and returns a descriptor. The descriptor should be declared as an integer. Files are always open for writing, so any file you specify will be overwritten. You may have at most 31 files open at once. Below is an example, of how to use $open to open a file. 

      integer d;

  initial
    begin
      d = $fopen("myfile.log");
      ...
    You may use the bit-wise OR operator "|" to combine two or more descriptors. This will cause an write operations on that descriptor to output to all of the files combined in this way. You may also OR in the value "1" to include output to the console. For example, given the statements: 
        d1 = $fopen("myfile1.log");
    d2 = $fopen("myfile2.log");
    d = d1 | d2 | 1;
    writing to d will cause that output to be written to myfile1.log, myfile2.log and the standard output.

    B.2.2 $fclose

    Usage: $fclose(descriptor);

    Closes the file or files referenced by the descriptor. If descriptor has been formed by ORing together two or more descriptors, all of the referenced files will be closed.

    B.2.3 $fdisplay, $fmonitor, $fstrobe and $fwrite

    Usage: $fdisplay(descriptor, arg1, arg2, ... );
    Usage: $fmonitor(descriptor, arg1, arg2, ... );
    Usage: $fstrobe(descriptor, arg1, arg2, ... );
    Usage: $write(descriptor, arg1, arg2, ... );

    These tasks operate in exactly the same way as their counter-parts without the leading "f", except that they take a descriptor as the first argument and write their output to the file (or files) referenced by that descriptor.

    B.3 Timing Check Tasks

    The timing check tasks may only be used in the context of a specify...endspecify block. They are described briefly here, but more information on their use can be found in Section 4.10.3 Constraint Tasks.

    B.3.1 $hold

    Usage: $hold( clock, data, limit );

    The $hold task generates a warning message when a hold-time constraint is not satisfied. clock specifies a clock event after which a data line must be held constant. data specifies the data signal that must not change for the hold period, and limit specifies the time periods for which changes in data are forbidden. The $hold task may only be used in a specify block.

    B.3.2 $setup

    Usage: $setup(data, clock, limit );

    The $setup task generates a warning message when a setup-time constraint is not satisfied. data specifies the data signal that must not change for the setup period. clock specifies a clock event that ends the setup period, and limit specifies the length of the setup period. If the clock event occurs less than limit time steps from the last change of data, a warning message is generated. The $setup task may only be used in a specify block.

    B.3.3 $width

    Usage: $width( event, limit );

    The $width task generates a warning message when a pulse width is shorter than a specified limit. event specifies the the leading edge of the pulse that is to be tested. Use the posedge or negedge keyword to indicate which edge is to be tested. limit is the minimum allowable pulse width. If the opposite transition is detected in fewer than limit time steps, then warning message will be generated. The $width task may only be used in a specify block.

    B.4 Simulation Information/Control and Miscellaneous Tasks

    The tasks described in this section can be used to control the simulation, get information about the simulation, and do other miscellaneous tasks.

    B.4.1 $finish

    Usage: $finish;

    This task terminates the simulation. If called while running Verga in stand-along mode, Verga will terminate immediately. If called from a description running under the TkGate, the simulator will terminate, and TkGate will revert to edit mode.

    B.4.2 $stop

    Usage: $stop;

    This task suspends the simulation and puts it into pause mode. If called while running Verga in stand-along mode, it will have the same effect as $finish, terminating the simulation immediately. If called from a description running under the TkGate, the simulator will enter paused mode allowing you to examine the values of variables before unpausing the simulation.

    B.4.3 $time

    Usage: variable = $time;

    This task returns the current simulation time. When assigning it to a variable, that variable should be declared as a time variable. This is normally a 64-bit integer. One of the most useful places to use $time is in conjunction with a $display or $monitor task to show the simulation time at which the output is produced. When using $time in this way, you should use the %t conversion in the control string.

    B.4.4 $stime

    Usage: variable = $stime;

    This task returns the low 32 bits of the current simulation time. You may assign it to an integer variable.

    B.4.5 $random

    Usage: variable = $random;
    Usage: $random(seed);

    When called without an argument, this task returns a random number. When called with an argument, that argument is used as the seed value for the random number generator.

    B.5 Memory Tasks

    These tasks can be used to save and load the contents of a memory to or from a file.

    B.5.1 $readmemb and $readmemh

    Usage: $readmemb(file);
    Usage: $readmemb(file, memory);
    Usage: $readmemb(file, memory, start);
    Usage: $readmemb(file, memory, start, stop);

    Usage: $readmemh(file);
    Usage: $readmemh(file, memory);
    Usage: $readmemh(file, memory, start);
    Usage: $readmemh(file, memory, start, stop);

    These tasks initialize one or more memories in a design from the contents of a file. The forms ending in "b" assume binary formatted data, while the forms ending in "h" assume hexadecimal formatted data. If only a file name is specified, then the name(s) of the memories to be initialized must be encoded in the file. If a memory is specified, than the file is loaded into that memory. You may also specify a start and stop address.

    The file should contain a space separated list of values for the memory. The unknown (x) and floating (z) values may also be used in one or more bits. There are also several special control lines beginning with "@" that can be used to specify the memory, the address, or the radix of the file. An example of a memory file is shown below: 

    @memory top.m
@0
3 4 9 16 25
36 49 64 81

@C
100 x x 99 z 12 x8 z12

@100
4 3 9x x x11

@1000000
12 13 14 z 19 20 x x x 30 31
    The @memory top.m specifies the name of the memory to be loaded. It should be a fully qualified path name. The @0 line indicates that the following data is to be load beginning at address 0, the @C line indicates data to be loaded beginning at address hexadecimal C, and so forth. You can also use a line such as: 
    @radix 8
    To change the radix for data in the file to binary (2), octal (8), decimal (10) or hexadecimal (16).

    B.5.2 $writememb and $writememh

    Usage: $writememb(file);
    Usage: $writememb(file, memory);
    Usage: $writememb(file, memory, start);
    Usage: $writememb(file, memory, start, stop);

    Usage: $writememh(file);
    Usage: $writememh(file, memory);
    Usage: $writememh(file, memory, start);
    Usage: $writememh(file, memory, start, stop);

    These tasks write the contents of one or more memories to a file. The forms ending in "b" write the data in binary, while the forms ending in "h" write the data in hexadecimal. The files written are of a format suitable for being read by the $readmemb and $readmemh tasks. If only a file name is given, the contents of all memories in the design will be written. If a memory name is given, only the contents of that memory will be saved. You can also specify a start and stop address to save a portion of a memory. If there are large regions of uninitialized values in a memory, those values will not be explicitly saved. Only memory pages in which data has been stored will be saved to the file.

    B.6 TkGate-Specific Tasks

    These tasks are tasks that are not part of the normal Verilog specification, but are specific to TkGate descriptions. These tasks all begin with the $tkg prefix. Most of these tasks are only useful when running a simulation under the TkGate GUI.

    B.6.1 $tkg$command

    Usage: $tkg$command(arg1, arg2, ... );

    When the simulator is running under the TkGate GUI, TkGate and the simulator communicate over a pipe. This task writes a command from the simulator to TkGate directly on that pipe. The arguments are combined into a string in the same way as for $display, and the resulting string is feed directly to the TkGate GUI. When running Verga directly, this task performs identically to $display.

    This task is subject to security settings set through the TkGate Security Options dialog box.

    B.6.2 $tkg$exec

    Usage: $tkg$exec(arg1, arg2, ... );

    This task executes a Tcl/Tk command in the context of the TkGate GUI. It can be used to control a Virtual Peripheral Device (VPD), although its use for this purpose is currently discouraged. The $tkg$post, $tkg$send and $tkg$recv tasks are now the preferred tasks to use for interacting with VPDs.

    When executing this task, the arguments are combined into a string in the same way as for $display, and the resulting string is sent to the TkGate GUI to be executed as a Tcl/Tk command. The command will only be executed if it is enabled through the TkGate Security Options dialog box. There are three possible security settings: fully enabled, enabled for registered functions, and disabled. When enabled only for registered functions, only Tcl commands that have been registered by a VPD on loading can be executed. Furthermore, the "[" and "]" characters are not allowed in the string. For more information on how to use this task in designing VPDs, see the section on Creating Virtual Peripheral Devices.

    If running Verga directly, this task will simply print the simulator command requesting a Tcl/Tk command to be executed.

    B.6.3 $tkg$post

    Usage: $tkg$post(name, id);

    This task is used to start/post a Virtual Peripheral Device (VPD). The name argument specifies the name of the VPD. The id argument specifies the name of a unique identifier for this instance of the VPD. Normally, the string "%m" should be specified as the id. The "%m" will be replaced with the instance name of the calling module in the same way that "%m" is expanded in the $display task. For more information on how to use this task in designing VPDs, see the section on Creating Virtual Peripheral Devices.

    If running Verga directly, this task will simply print the simulator command requesting a VPD to be posted.

    B.6.4 $tkg$probe

    Usage: $tkg$probe(signal1, signal2, ...);

    This task is used to set a probe on a signal or signals. You can list an arbitrary number of signals specified either with their local names, or with fully qualified path names. This task will cause the TkGate GUI to display the probed signals in the logic analyzer window and begin displaying value changes on those signals. You can use this task in a simulator script to setup the signals you want to probe at the beginning of a simulation.

    If running Verga directly, this task will simply print the simulator command requesting a probe to be set, and print value changes on that signal until the probe is removed with and $unprobe.

    If running Verga directly, this task will simply print the simulator command setting a probe and reporting the values on the probed signals.

    B.6.5 $tkg$recv

    Usage: value = $tkg$recv(channel);

    The $tkg$recv task is used receive value on a channel from a Virtual Peripheral Device (VPD). A channel is essentially a queue that can be read to or written from either from the Tcl/Tk side of a VPD, or the Verilog side. The $tkg$recv task dequeues and returns the next value in the queue. If the queue is empty, the task blocks until a value is placed on the queue.

    The channel name is an arbitrary string. Channels are dynamically created when referenced by a $tkg$recv or $tkg$send task. When used for communicating with a VPD, the channel name should be constructed from the VPD instance name (the same name used as the id in $tkg$post), followed by a "." character and a local name. This convention ensures that each instance of a VPD has its own set of channels to use. You can use "%m" in place of the instance name which will be replaced with the instance name for the current module.

    For more information on how to use this task in designing VPDs, see the section on Creating Virtual Peripheral Devices.

    While this task is primarily intended to be used for communication with VPDs, you can use it in conjunction with the $tkg$send task to send values from one Verilog thread to another.

    B.6.6 $tkg$reportbreak

    Usage: $tkg$reportbreak(id, value);

    This task pauses the simulation and sends a command indicating that a breakpoint has fired. id is the name of the breakpoint, and value is the value that has caused the break. This task is primarily used for TkGate testing purposes.

    B.6.7 $tkg$send

    Usage: $tkg$send(channel, value);

    The $tkg$send task is used send a value on a channel from the Verilog description to a Virtual Peripheral Device (VPD). A channel is essentially a queue that can be read to or written from either from the Tcl/Tk side of a VPD, or the Verilog side. The $tkg$send task enqueues a value on the queue for the specified channel.

    The channel name is an arbitrary string. Channels are dynamically created when referenced by a $tkg$recv or $tkg$send task. When used for communicating with a VPD, the channel name should be constructed from the VPD instance name (the same name used as the id in $tkg$post), followed by a "." character and a local name. This convention ensures that each instance of a VPD has its own set of channels to use. You can use "%m" in place of the instance name which will be replaced with the instance name for the current module.

    For more information on how to use this task in designing VPDs, see the section on Creating Virtual Peripheral Devices.

    While this task is primarily intended to be used for communication with VPDs, you can use it in conjunction with the $tkg$recv task to send values from one Verilog thread to another.

    B.6.8 $tkg$systime

    Usage: value = $tkg$systime;

    This task returns the current system time as a 64-bit time value with the number of milliseconds since January 1, 1970.

    B.6.9 $tkg$unprobe

    Usage: $tkg$unprobe(signal1, signal2, ...);

    This task removes one or more probes set either with the $probe system task, or manually through the TkGate GUI.

    B.6.10 $tkg$wait

    Usage: $tkg$wait(value);

    This task will block the calling thread for the specified number of milliseconds. The simulation itself will continue, and all other threads will advance normally (unless the calling thread is the only unblocked thread). As an example, consider the code fragment: 

       always
     begin
       $tkg$wait(1000)
       $display("Hello World");
     end
    This will cause the message "Hello World" to be printed once per second.

    B.6.11 $tkg$waituntil

    Usage: $tkg$waituntil(value);

    This task blocks a thread in the same way as $tkg$wait until a specified absolute time. The $tkg$systime task should be used to get a reference time to be used with $tkg$waituntil. If the time specified by value is less than the current time, $tkg$waituntil will return immediately and do nothing. This task can be used to create real time clocks. For example, the following module generates a clock signals that oscillates once per second: 

    module realclock(z);
output reg z;
time t;

  initial
    z = 1'b0;

  initial
    begin
      t = $tkg$systime;
      forever
        begin
          t = t + 500;
          $tkg$waituntil(t);
	  z = ~z;
        end
    end

endmodule

    The advantage of using $tkg$waituntil instead of $tkg$wait to generate the clock signal is to avoid drift. If $tkg$wait were used instead, there would be additional real time delay as the simulation was running between calls to $tkg$wait. This small error would accumulate over time causing the number of oscillations to diverge from the proper value over a long time period.

    Real time clocks such as this can be used to create real-time simulations of devices such as digital clocks, or other simulation using LEDs where you wish to run them synchronized with real time.

    B.6.12 $tkg$zoom

    Usage: $tkg$zoom(factor);

    This task sets the zoom level in the TkGate scope window reletive to the default zoom factor. The factor parameter is an integer representing the zoom factor. A factor of 0 sets the default zoom factor. Negative values represent the number of zoom-out steps (showing more time on the x-axis), and positive values represent the number of zoom-in steps (showing less time on the x-axis). tkgate-2.0-b10/doc/verga.html000644 001751 001751 00000007321 10652377055 016562 0ustar00hansenhansen000000 000000 TKGate User Documentation (Verga)

    D. Using the Verga Simulator in Stand-Alone Mode

    While Verga was written to support use through the TkGate graphical interface, it is possible to use Verga by itself in stand-alone mode. The input files need not be TkGate generated Verilog, and can be arbitrary Verilog code, as long as it uses only the subset of constructs supported by Verga.

    To invoke Verga, use a command of the form:

    verga[options] [files]

    The supported options are:

    OptionDescription
    -iInteractive mode - In this mode, Verga will continue to read from the standard input while the simulation is running to accept commands controlling the simulation. This is the mode that the TkGate GUI uses when invoking Verga, and is generally only useful to TkGate.
    -eList error messages - Dump a list of all the error messages that Verga can generate.
    -lShow License - Print out the license information to the screen.
    -S scriptLoad Script - Load a simulation script on start-up. This switch can be specified multiple times to load multiple scripts.
    -W modeWarning Mode - Sets the warning mode indicating how warnings are to be treated. Mode is a numeric value between 1 and 4. If mode is 1, warning will be ignored. If mode is 2, warnings will be reported only if there are errors. If mode is 3, warnings will always be reports. If mode is 4, warnings will be treated as errors, and the simulator will not start if there are warnings. The default mode value is 3.
    -sScan Mode - Scans the modules in the input file and reports the names of the modules, and the variables declared in them. No simulation is performed.
    -qQuite Mode - Suppress printing of unnecessary messages.
    -PPrint Modules - Echos back the input file from the internal parsed data.
    -B dirBase Directory - Makes dir the default directory when searching for files.
    -t nameSet Top Module - Makes name the top-level module rather than automatically selecting one.
    -d typeDelay Type - Sets the delay values to use. type can be one of min, max or typical.

    Verga will scan all Verilog files specified on the command line. If the -t switch is not used to specify the top-level module, Verga will assume that the first module with no ports is the top-level module. Any output generated by the simulation is printed to the screen.

    If you are using Verga to simulate a file saved from TkGate, you must be sure that you have enabled "Include cells in save files" from the General Options dialog box. If you do not, Verga will be unable to find the definitions for TkGate's built-in devices. tkgate-2.0-b10/doc/license.txt000644 001751 001751 00000001300 07311226663 016736 0ustar00hansenhansen000000 000000 This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. tkgate-2.0-b10/doc/favicon.ico000644 001751 001751 00000007066 10651416323 016706 0ustar00hansenhansen000000 000000 h& ¨Ž( @ÿÿÿ€ë·( @€ÿÿÿÿë·tkgate-2.0-b10/doc/fig/scopeSelection.gif000644 001751 001751 00000010611 10653513415 020770 0ustar00hansenhansen000000 000000 GIF87a÷ÿ‹å‘$"4.$424<2$<:D<<<>>@D<,D>4DBTEEGFFGLB,LB4MMXQQ\SS[TJ9UU[U»»XXdYYdZZf[[g\Zt\]ºbbgbbmdcÆfffhhtiitjjuk:JkkkljÔlntqqzqq{qq}vwywwƒyy…zz†|~„|~Ü‚‚‚…„††ˆ‰ˆˆ“ŠŠ–‹‹–‘‘œ–––™™™šš¥šš¦œ~dœž¤¡¡©¡¡¬¤¤¨¦¦¨¨¨´©©µªª¶¬®´±±½´–lµµ·¶µ¶¶¶Â¸¸Ã»»Æ¼¦|ÂÂÍIJ”ÊÊÕÊÊÖËË×ÌÌÌÌÌ×ÌÌØÒ´ŒÒÒÝÔ¾œÙÙÙÙÙåÚÚæÛp“ÛÛæááìåååååççóèèôééôêêõìÖ”úúþûûþüÕáüüþýýþþþþÿÿÿÿÿÿË]  @hÞÝ¿¿ ð…(%  )€!¼ÈÐÞ¿¿    ÐæÝØ Þ¿ë #(  Vn  ˜T—Ý®¿_F¿# Fë# |uHòƒ((È@Ð'À ‰ÐÜ¿¿Ø\ŸÞ¿;¿(\# €ÿ@ÿ'ÿÿë#¸5Ý¿aþ ÀÝ0ßÐ\¿¿4\ß\¿¿8ßù¿¿<ß ¿ý æР¿ØèC=ƒ ((,þ×|ùb—ƒ*\È°¡Ã‡#JœH±¢Å‹3jÜ(Q AƒCŠI²¤É“(7z,H€Ë—0]f¬A³F Š)ræ Ùf… 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    scopePrint toggleProbe openMod closeMod blockNew blockDelete blockCopy blockRename setBlockDesc editBlockDesc blockClaim blockSetRoot

    blockProp updateInterface updateAllInterface autoGenerateCanvas addPort replicate delete editProps anchor unAnchor nudgeLeft nudgeRight nudgeUp nudgeDown errBoxUp errBoxDown refreshScreen cancel ############################################################################# # # HDL Editor bindings # newFile -groups {hdlmodule} loadFile -groups {hdlmodule} loadLibrary -groups {hdlmodule} saveFile -groups {hdlmodule} saveAsFile -groups {hdlmodule} print -groups {hdlmodule} exit -groups {hdlmodule} editOptions -groups {hdlmodule} undo -groups {hdledit hdlmodule} redo -groups {hdledit hdlmodule} undo -groups {hdledit hdlmodule} redo -groups {hdledit hdlmodule} hdlDeleteForward -groups {hdledit hdlmodule} hdlDeleteForward -groups {hdledit hdlmodule} hdlDeleteBackward -groups {hdledit hdlmodule} hdlDeleteBackward -groups {hdledit hdlmodule} selectAll -groups {hdledit hdlmodule} hdlCut -groups {hdledit hdlmodule} hdlYank -groups {hdledit hdlmodule} copyToBuf -groups {hdledit hdlmodule} hdlKillLine -groups {hdledit hdlmodule} hdlSearch -groups {hdledit hdlmodule} hdlReverseSearch -groups {hdledit hdlmodule} hdlPageDown -groups {hdledit hdlmodule} hdlPageUp -groups {hdledit hdlmodule} hdlDeleteWord -groups {hdledit hdlmodule} hdlOpenLine -groups {hdledit hdlmodule} hdlGotoLineEnd -groups {hdledit hdlmodule} hdlGotoLineStart -groups {hdledit hdlmodule} hdlGotoTop -groups {hdledit hdlmodule} hdlGotoEnd -groups {hdledit hdlmodule} hdlForwardWord -groups {hdledit hdlmodule} hdlBackwardWord -groups {hdledit hdlmodule} hdlBackwardChar -groups {hdledit hdlmodule} hdlForwardChar -groups {hdledit hdlmodule} hdlUpLine -groups {hdledit hdlmodule} hdlDownLine -groups {hdledit hdlmodule} hdlBackwardChar -groups {hdledit hdlmodule} hdlForwardChar -groups {hdledit hdlmodule} hdlUpLine -groups {hdledit hdlmodule} hdlDownLine -groups {hdledit hdlmodule} hdlSetMark -groups {hdledit hdlmodule} hdlSetMark -groups {hdledit hdlmodule} hdlExchangePointAndMark -groups {hdledit hdlmodule} hdlCancel -groups {hdledit hdlmodule} hdlIndent -groups {hdledit hdlmodule} # to be implemented hdlLowercaseWord -groups {hdledit hdlmodule} hdlUppercaseWord -groups {hdledit hdlmodule} hdlCasefyWord -groups {hdledit hdlmodule} hdlSetArgument -groups {hdledit hdlmodule} ############################################################################# # # Scope bindings # scopeZoomIn scopeZoomOut tkgate-2.0-b10/bindings/windows000644 001751 001751 00000010374 11142454761 017232 0ustar00hansenhansen000000 000000 ###################################################################### # # Built-in bindings for "windows"-like mode # newFile loadFile loadLibrary saveFile # saveAsFile print # exit # editOptions undo # redo # undo # redo copyToBuf selectAll cutToBuf yankFromBuf findObject vAlign hAlign simCycleOrRotate backRotate duplicate # zoomIn # zoomOut editMode cutMode invertMode scrollMode sizeMode rot0 rot90 rot180 rot270 # editCProps simStep startSimulator endSimulator simRun simStop editBreakpoints doSimScript simLoadMem simDumpMem scopePrint toggleProbe openMod closeMod blockNew blockDelete blockCopy blockRename setBlockDesc editBlockDesc blockClaim blockSetRoot

    blockProp addIn addOut addInOut replicate delete editProps # anchor # unAnchor nudgeLeft nudgeRight nudgeUp nudgeDown # errBoxUp # errBoxDown # refreshScreen cancel ############################################################################# # # HDL Editor bindings # newFile -groups {hdlmodule} loadFile -groups {hdlmodule} # loadLibrary -groups {hdlmodule} saveFile -groups {hdlmodule} # saveAsFile -groups {hdlmodule} print -groups {hdlmodule} # exit -groups {hdlmodule} # editOptions -groups {hdlmodule} undo -groups {hdledit hdlmodule} # redo -groups {hdledit hdlmodule} # undo -groups {hdledit hdlmodule} # undo -groups {hdledit hdlmodule} hdlDeleteForward -groups {hdledit hdlmodule} # hdlDeleteForward -groups {hdledit hdlmodule} hdlDeleteBackward -groups {hdledit hdlmodule} # hdlDeleteBackward -groups {hdledit hdlmodule} hdlCut -groups {hdledit hdlmodule} hdlYank -groups {hdledit hdlmodule} # hdlKillLine -groups {hdledit hdlmodule} # hdlTransposeChar -groups {hdledit hdlmodule} hdlSearch -groups {hdledit hdlmodule} hdlReverseSearch -groups {hdledit hdlmodule} # hdlPageDown -groups {hdledit hdlmodule} # hdlPageUp -groups {hdledit hdlmodule} # hdlDeleteWord -groups {hdledit hdlmodule} # hdlOpenLine -groups {hdledit hdlmodule} # hdlGotoLineEnd -groups {hdledit hdlmodule} # hdlGotoLineStart -groups {hdledit hdlmodule} # hdlGotoTop -groups {hdledit hdlmodule} # hdlGotoEnd -groups {hdledit hdlmodule} # hdlForwardWord -groups {hdledit hdlmodule} # hdlBackwardWord -groups {hdledit hdlmodule} # hdlBackwardChar -groups {hdledit hdlmodule} # hdlForwardChar -groups {hdledit hdlmodule} # hdlUpLine -groups {hdledit hdlmodule} # hdlDownLine -groups {hdledit hdlmodule} hdlBackwardChar -groups {hdledit hdlmodule} hdlForwardChar -groups {hdledit hdlmodule} hdlUpLine -groups {hdledit hdlmodule} hdlDownLine -groups {hdledit hdlmodule} # hdlSetMark -groups {hdledit hdlmodule} # hdlSetMark -groups {hdledit hdlmodule} # hdlExchangePointAndMark -groups {hdledit hdlmodule} hdlCancel -groups {hdledit hdlmodule} hdlIndent -groups {hdledit hdlmodule} tkgate-2.0-b10/bindings/none000644 001751 001751 00000000000 10140606105 016444 0ustar00hansenhansen000000 000000 tkgate-2.0-b10/bindings/emacs~000644 001751 001751 00000011417 11142452166 017022 0ustar00hansenhansen000000 000000 ###################################################################### # # Built-in bindings for "emacs"-like mode # newFile loadFile loadLibrary saveFile saveAsFile print exit editOptions undo redo copyToBuf selectAll cutToBuf yankFromBuf findObject vAlign hAlign simCycleOrRotate backRotate duplicate zoomIn zoomOut editMode cutMode invertMode scrollMode sizeMode rot0 rot90 rot180 rot270 editCProps simStep startSimulator endSimulator simRun simStop editBreakpoints doSimScript simLoadMem simDumpMem

    scopePrint toggleProbe openMod closeMod blockNew blockDelete blockCopy blockRename setBlockDesc editBlockDesc blockClaim blockSetRoot

    blockProp updateInterface updateAllInterface autoGenerateCanvas addPort replicate delete editProps anchor unAnchor nudgeLeft nudgeRight nudgeUp nudgeDown errBoxUp errBoxDown refreshScreen cancel ############################################################################# # # HDL Editor bindings # newFile -groups {hdlmodule} loadFile -groups {hdlmodule} loadLibrary -groups {hdlmodule} saveFile -groups {hdlmodule} saveAsFile -groups {hdlmodule} print -groups {hdlmodule} exit -groups {hdlmodule} editOptions -groups {hdlmodule} undo -groups {hdledit hdlmodule} redo -groups {hdledit hdlmodule} undo -groups {hdledit hdlmodule} redo -groups {hdledit hdlmodule} hdlDeleteForward -groups {hdledit hdlmodule} hdlDeleteForward -groups {hdledit hdlmodule} hdlDeleteBackward -groups {hdledit hdlmodule} hdlDeleteBackward -groups {hdledit hdlmodule} hdlCut -groups {hdledit hdlmodule} hdlYank -groups {hdledit hdlmodule} hdlKillLine -groups {hdledit hdlmodule} hdlTransposeChar -groups {hdledit hdlmodule} hdlSearch -groups {hdledit hdlmodule} hdlReverseSearch -groups {hdledit hdlmodule} hdlPageDown -groups {hdledit hdlmodule} hdlPageUp -groups {hdledit hdlmodule} hdlDeleteWord -groups {hdledit hdlmodule} hdlOpenLine -groups {hdledit hdlmodule} hdlGotoLineEnd -groups {hdledit hdlmodule} hdlGotoLineStart -groups {hdledit hdlmodule} hdlGotoTop -groups {hdledit hdlmodule} hdlGotoEnd -groups {hdledit hdlmodule} hdlForwardWord -groups {hdledit hdlmodule} hdlBackwardWord -groups {hdledit hdlmodule} hdlBackwardChar -groups {hdledit hdlmodule} hdlForwardChar -groups {hdledit hdlmodule} hdlUpLine -groups {hdledit hdlmodule} hdlDownLine -groups {hdledit hdlmodule} hdlBackwardChar -groups {hdledit hdlmodule} hdlForwardChar -groups {hdledit hdlmodule} hdlUpLine -groups {hdledit hdlmodule} hdlDownLine -groups {hdledit hdlmodule} hdlSetMark -groups {hdledit hdlmodule} hdlSetMark -groups {hdledit hdlmodule} hdlExchangePointAndMark -groups {hdledit hdlmodule} hdlCancel -groups {hdledit hdlmodule} hdlIndent -groups {hdledit hdlmodule} # to be implemented hdlLowercaseWord -groups {hdledit hdlmodule} hdlUppercaseWord -groups {hdledit hdlmodule} hdlCasefyWord -groups {hdledit hdlmodule} hdlSetArgument -groups {hdledit hdlmodule} ############################################################################# # # Scope bindings # scopeZoomIn scopeZoomOut tkgate-2.0-b10/bindings/windows~000644 001751 001751 00000007440 11121206727 017422 0ustar00hansenhansen000000 000000 ###################################################################### # # Built-in bindings for "windows"-like mode # newFile loadFile loadLibrary saveFile # saveAsFile print # exit # editOptions undo # redo # undo # redo copyToBuf selectAll cutToBuf yankFromBuf findObject vAlign hAlign simCycleOrRotate backRotate duplicate # zoomIn # zoomOut editMode cutMode invertMode scrollMode sizeMode rot0 rot90 rot180 rot270 # editCProps simStep startSimulator endSimulator simRun simStop editBreakpoints doSimScript simLoadMem simDumpMem scopePrint toggleProbe openMod closeMod blockNew blockDelete blockCopy blockRename setBlockDesc editBlockDesc blockClaim blockSetRoot

    blockProp addIn addOut addInOut replicate delete editProps # anchor # unAnchor nudgeLeft nudgeRight nudgeUp nudgeDown # errBoxUp # errBoxDown # refreshScreen cancel ############################################################################# # # HDL Editor bindings # newFile -groups hdledit loadFile -groups hdledit # loadLibrary -groups hdledit saveFile -groups hdledit # saveAsFile -groups hdledit print -groups hdledit # exit -groups hdledit # editOptions -groups hdledit undo -groups hdledit # redo -groups hdledit # undo -groups hdledit # undo -groups hdledit hdlDeleteForward -groups hdledit # hdlDeleteForward -groups hdledit hdlDeleteBackward -groups hdledit # hdlDeleteBackward -groups hdledit hdlCut -groups hdledit hdlYank -groups hdledit # hdlKillLine -groups hdledit # hdlTransposeChar -groups hdledit hdlSearch -groups hdledit hdlReverseSearch -groups hdledit # hdlPageDown -groups hdledit # hdlPageUp -groups hdledit # hdlDeleteWord -groups hdledit # hdlOpenLine -groups hdledit # hdlGotoLineEnd -groups hdledit # hdlGotoLineStart -groups hdledit # hdlGotoTop -groups hdledit # hdlGotoEnd -groups hdledit # hdlForwardWord -groups hdledit # hdlBackwardWord -groups hdledit # hdlBackwardChar -groups hdledit # hdlForwardChar -groups hdledit # hdlUpLine -groups hdledit # hdlDownLine -groups hdledit hdlBackwardChar -groups hdledit hdlForwardChar -groups hdledit hdlUpLine -groups hdledit hdlDownLine -groups hdledit # hdlSetMark -groups hdledit # hdlSetMark -groups hdledit # hdlExchangePointAndMark -groups hdledit hdlCancel -groups hdledit hdlIndent -groups hdledit tkgate-2.0-b10/scripts/library.tcl~000644 001751 001751 00000015033 11131271674 020050 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2005 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed Jan 7 22:32:12 2009 # namespace eval LibraryMgr { variable libTitle variable libStatus variable libReqStatus variable leftMargin 8 variable topMargin 8 variable boldFont checklistBoldFont variable normalFont checklistFont variable lineHeight variable lineAscent variable lineDescent variable boxSize variable libraryList variable yPos ############################################################################# # # Called at start-up to load the base libraries # proc loadBaseLibraries {} { global tkg_simVLibNames foreach name $tkg_simVLibNames { catch { gat_loadLibrary $name } } } ############################################################################# # # Get the title of a library file. # proc gettitle {name} { set f [open $name] if { $f == "" } { return "" } while {![eof $f]} { set s [gets $f] if {[lindex $s 0] == "//:" && [lindex $s 1] == "property" && [lindex $s 2] == "title"} { close $f return [lindex $s 4] } } close $f return "" } ############################################################################# # # Scan the library path for the list of available libraries. # proc scanlibs args { global tkg_simVLibPath variable libTitle variable libStatus variable libReqStatus set path $tkg_simVLibPath if {[llength $args] > 0} { set path [lindex $args 0] } set L {} foreach directory $path { set directory [namespace eval :: "eval concat $directory"] foreach file [glob -nocomplain $directory/*.v] { set lib [file rootname [file tail $file]] set title [gettitle $file] lappend L $lib set libTitle($lib) $title set libStatus($lib) [gat_libIsLoaded $lib] set libReqStatus($lib) $libStatus($lib) } } return [lsort -dictionary $L] } proc drawBox {w name} { variable libStatus variable libReqStatus variable boxSize variable leftMargin variable yPos set x $leftMargin set y $yPos($name) $w delete $name.box set x2 [expr $x + $boxSize] set y2 [expr $y - $boxSize] set tags [list box $name.box] $w create rectangle $x $y $x2 $y2 -tags $tags -fill white if { $libReqStatus($name) != 0} { $w create image [expr $x+1] $y -anchor sw -image [gifI checkon.gif] -tags $tags } } proc makeLibLine {w name} { variable leftMargin variable libTitle variable libStatus variable libReqStatus variable lineDescent variable boldFont variable normalFont variable boxSize variable yPos set x $leftMargin set y $yPos($name) $w delete $name # # Draw the box # set boxTags [list $name box $name.box] set x2 [expr $x + $boxSize] set y2 [expr $y - $boxSize] $w create rectangle $x $y $x2 $y2 -tags $boxTags -fill white if { $libReqStatus($name) != 0} { $w create image [expr $x+1] $y -anchor sw -image [gifI checkon.gif] -tags $boxTags } set x [expr $x + $boxSize + [rescale *8]] set y [expr $y + $lineDescent] # # Draw the library name # $w create text $x $y -text $name -anchor sw -font $boldFont -tags $name set x [expr $x + [font measure $boldFont $name]] # # Draw load/unload status # if { $libStatus($name) != $libReqStatus($name) } { if { $libReqStatus($name) } { set status " \[load\]" } else { set status " \[unload\]" } $w create text $x $y -text $status -anchor sw -font $boldFont -fill red -tags $name set x [expr $x + [font measure $boldFont $status]] } # # Draw the library description # $w create text $x $y -text " - $libTitle($name)" -anchor sw -font $normalFont -tags $name } proc toggleBox {w y args} { variable lineHeight variable libraryList variable libReqStatus set index [expr int($y/$lineHeight-1)] if {$index >= [llength $libraryList]} return set name [lindex $libraryList $index] set libReqStatus($name) [expr !$libReqStatus($name)] makeLibLine $w $name } ############################################################################# # # Commit library changes # proc commit {} { variable libraryList variable libReqStatus variable libStatus # # If variable does not exist, then we have not visited library page # and thus there is no reason to update library status # if {![info exists libraryList]} return foreach name $libraryList { if {$libReqStatus($name) != $libStatus($name)} { if { $libReqStatus($name) } { gat_loadLibrary $name } else { gat_unloadLibrary $name } } } } ############################################################################# # # Dialog for loading and unloading libraries. # proc create {w} { variable topMargin variable boldFont variable normalFont variable lineHeight variable lineAscent variable lineDescent variable boxSize variable libraryList variable yPos set lineAscent [font metrics $boldFont -ascent] set lineDescent [font metrics $boldFont -descent] set lineHeight [expr $lineAscent + $lineDescent] set boxSize 9 frame $w set width [rescale [m @circ.library.width]] set height [rescale [m @circ.library.height]] canvas $w.c -bg white -bd 1 -relief sunken -yscrollcommand "$w.vb set" -width $width -height $height scrollbar $w.vb -command "$w.c yview" pack $w.c -fill both -expand 1 -side left pack $w.vb -side left -fill y $w.c bind box "LibraryMgr::toggleBox %W %y" set y [expr $topMargin + $lineHeight] set libraryList [scanlibs] foreach name $libraryList { set yPos($name) $y makeLibLine $w.c $name incr y $lineHeight } $w.c configure -scrollregion [list 0 0 0 $y] } } tkgate-2.0-b10/scripts/parms.tcl000644 001751 001751 00000011055 11134352133 017321 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Jan 17 07:51:39 2009 # # ###################################################################### # # Basic constants # set tkg_progName TKGate set tkg_prefFile "~/.tkgate2-preferences" set tkg_errorLogFile "tkgate-error.log" set tkg_splashWait 1500 set tkg_pastelHighlight "\#bbbbff" set tkg_tabHighlight "\#ffaaaa" set tkg_enableCPath 0 set tkg_doBackupOnSave 1 set tkg_wantCheckpoint 0 set tkg_simDefaultDelayFile "${tkg_gateHome}/gdf/default.gdf" set treeItemHeight 17 set tkg_standardEncodings {iso8859-1 iso8859-2 euc-jp utf-8} set lastKeyPressTime 0 ###################################################################### # # Set the current directory # set cwd [pwd]/ ###################################################################### # # Initial size of main canvas # set tkg_initialWidth 1024 set tkg_initialHeight 650 set tkg_minWidth 830 set tkg_minHeight 585 set tkg_borderSize 2 ###################################################################### # # Executable for simulator # set simExec "${tkg_gateHome}/libexec/verga" ###################################################################### # # InfoPanel position information # # current size for InfoPanel in edit mode set tkg_mmSplitEdit 0 # current size for InfoPanel in simulate mode set tkg_mmSplitSimulate 0.15 # Minimum size for InfoPanel when switching to edit mode set tkg_mmSplitEditMin 0 # Minimum size for InfoPanel when switching to simulate mode set tkg_mmSplitEditLog 0.15 # Minimum size for InfoPanel when logging a message set tkg_mmSplitSimulateMin 0.15 ###################################################################### # # Basic global variables and initial values # # Name of file being edited with user specified (possibly relative) path. set tkg_currentFile "" # Full path name of file being edited. set tkg_currentPath "/" # Base name of file to be displayed on status line. set tkg_displayFile "" # Non-zero if circuit data has been modified since the last save. set tkg_modifiedFlag 0 # Name of the module currently being edited. set tkg_currentModule "main" # Text currently displayed on the status line. set tkg_statusMessage "" # List of possible numbers of critical paths to search for. set tkg_cpathListLengths {1 5 10 25 50 100} # Name of the current default technology set tkg_defaultTech "default" # Name of the current default wire type set tkg_defaultWType "wire" # List of built-in wire types set tkg_wtypeList {wire tri wand triand wor trior tri0 tri1 trireg} # Current and previous edit tool mode set mode 1 set old_mode 0 # Currently selected bit width set tkg_bitWidth 1 # Current default rotation for new gates. set rot 0 # Non-zero if it is OK to discard edits in the current circuit. set tkg_discardChanges 0 # Non-zero if extender bars are being used on gates in the current circuit. set tkg_useExtBars 1 # Indicates the state of the selection buffer set tkg_cutBufferActive 0 set tkg_selectionActive 0 # Indicates if we are doing a replicate set tkg_replicateOn 0 # Alternate name for the TkGate home directory. set TKGATE_HOME $tkg_gateHome ###################################################################### # # Constants for file name selectors. # set gf_file "" set gf_result "" set gf_filter ".v" set gf_filetypes { {{Verilog Netlist} {.v} } {{All Files} * } } set gf_vfiletypes { {{Verilog Netlist} {.v} } {{All Files} * } } set gf_imageFiletypes { {{X11 Bitmap} {.xbm} } {{All Files} * } } set simScript_filter ".vs" set simScript_filetypes { {{Verilog Script Files} {.vs} } {{All Files} * } } set mem_filter ".mem" set mem_filetypes { {{Gate Memory Image Files} {.mem} } {{All Files} * } } set gdf_filter ".gdf" set gdf_filetypes { {{Gate Delay File} {.gdf} } {{All Files} * } } tkgate-2.0-b10/scripts/blocklist.tcl000644 001751 001751 00000016404 11132230273 020166 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Jan 10 18:35:23 2009 # #set modtabImageMap(NList) [gifI modlist.gif] #set modtabImageMap(List) [gifI modlist.gif] #set modtabImageMap(Tree) [gifI modtree.gif] ############################################################################# # # New-style block lists goes here # namespace eval BlockList { variable bl_w "" variable typeimages variable typeimagehelp variable moduletypes variable mouseset_x variable mouseset_y variable drag_obj # # Respond to motion of the mouse with button 1 depressed # proc seeMotion {x y} { variable bl_w variable drag_obj variable mouseset_x variable mouseset_y if { $drag_obj != "" } { set dx [expr $mouseset_x - $x] set dy [expr $mouseset_y - $y] if { [expr $dx*$dx + $dy*$dy] > 25 } { set i [string last / $drag_obj] if {$i >= 0 } { set lbl [string range $drag_obj [expr $i + 1] end] } else { set lbl $drag_obj } set icon [Tree::geticon $bl_w.t $drag_obj] set dw [Dragger::make -command "seeModuleDrop $lbl"] if { $dw != "" } { label $dw.icon -image $icon label $dw.label -text $lbl pack $dw.icon $dw.label -padx 2 -pady 2 -side left } } } } proc seeB1Press {w x y X Y} { action -Unselect { tkg_undoSelections blocks } set lbl [Tree::labelat $w $x $y] Tree::setselection $w $lbl set BlockList::mouseset_x $X set BlockList::mouseset_y $Y set BlockList::drag_obj $lbl } proc seeB3Press {w x y X Y} { action -Unselect { tkg_undoSelections blocks } set lbl [Tree::labelat $w $x $y] Tree::setselection $w $lbl if { $lbl != ""} { tk_popup .pop_modlist $X $Y } } proc seeDoubleB1 {w x y X Y} { set lbl [Tree::labelat $w $x $y] if { $lbl != "" } { continueAction GotoBlock "gat_openBox $lbl" } } proc create {w} { variable bl_w frame $w set bl_w $w setupImages Tree::create $w.t -width 50 -height 50 -bd 2 -relief sunken \ -yscrollcommand "$w.vb set" -xscrollcommand "$w.hb set" -nolines 1 scrollbar $w.vb -orient vertical -command "$w.t yview" -takefocus 0 scrollbar $w.hb -orient horizontal -command "$w.t xview" -takefocus 0 grid rowconfigure $w 0 -weight 1 grid columnconfigure $w 0 -weight 1 grid $w.t -row 0 -column 0 -sticky nsew -padx 1 -pady 1 grid $w.vb -row 0 -column 1 -sticky ns -padx 1 -pady 1 grid $w.hb -row 1 -column 0 -sticky ew -padx 1 -pady 1 bind $w.t <1> { BlockList::seeB1Press %W %x %y %X %Y } bind $w.t <3> { BlockList::seeB3Press %W %x %y %X %Y } bind $w.t { BlockList::seeMotion %X %Y } bind $w.t { BlockList::seeDoubleB1 %W %x %y %X %Y } } proc clearselection {} { variable bl_w Tree::setselection $bl_w.t "" } proc getselection {args} { variable bl_w set path [Tree::getselection $bl_w.t] return [string trimleft $path "/" ] } proc add {name args} { global tkg_currentModule variable bl_w variable typeimages variable typeimagehelp variable moduletypes set locks "" parseargs $args {-locks -type} set moduletypes($name) module if {$locks == "D" || $locks == "ID" } { set mtype mod_${type}_lock } else { set mtype mod_${type} } Tree::newitem $bl_w.t /$name -image $typeimages($mtype) -imagehelp $typeimagehelp($mtype) if { $name == $tkg_currentModule } { Tree::setactive $bl_w.t /$name } } proc addPart {name} { global tkg_currentModule variable bl_w variable typeimages variable typeimagehelp variable moduletypes set moduletypes($name) part Tree::newitem $bl_w.t /$name -image $typeimages(part) -imagehelp $typeimagehelp(part) if { $name == $tkg_currentModule } { Tree::setactive $bl_w.t /$name } } proc setRoot {name} { global tkg_currentModule variable bl_w variable typeimages variable typeimagehelp variable moduletypes set moduletypes($name) root Tree::delitem $bl_w.t /$name Tree::newitem $bl_w.t /$name -image $typeimages(root) -imagehelp $typeimagehelp(root) if { $name == $tkg_currentModule } { Tree::setactive $bl_w.t /$name } } proc flush {} { variable bl_w variable moduletypes array unset moduletypes "*" Tree::delitem $bl_w.t / } proc setupImages {} { variable typeimages variable typeimagehelp set typeimages(part) [gifI chip.gif] set typeimages(root) [gifI document.gif] set typeimages(mod_netlist) [gifI mod_net.gif] set typeimages(mod_hdl) [gifI mod_hdl.gif] set typeimages(mod_netlist_lock) [gifI mod_netL.gif] set typeimages(mod_hdl_lock) [gifI mod_hdlL.gif] # # Set up help messages # set typeimagehelp(part) [m ho.mod.type.part] set typeimagehelp(root) [m ho.mod.type.root] set typeimagehelp(mod_netlist) [m ho.mod.type.netlist] set typeimagehelp(mod_hdl) [m ho.mod.type.hdl] set typeimagehelp(mod_netlist_lock) [m ho.mod.type.Lnetlist] set typeimagehelp(mod_hdl_lock) [m ho.mod.type.Lhdl] } proc getallmodules args { variable bl_w # -types is a list of one or more of: module, root, part set exclude {} set types {} parseargs $args {-types -exclude} set L [Tree::getchildren $bl_w.t /] set L2 $L set L {} foreach m $L2 { if {[lsearch $exclude [getType $m]] >= 0} { continue } if {[llength $types] == 0 || [lsearch $types [getType $m]] >= 0} { lappend L $m } } return $L } proc getType {name} { variable moduletypes return $moduletypes($name) } proc isLibrary {name} { variable bl_w variable moduletypes if { $moduletypes($name) == "part" } { return 1 } else { return 0 } } } ############################################################################# # # This is called when a tab is pressed to switch the visible item in the # block-list/block-tree tab box interface. # proc blocklist_tabs {w tab} { switch $tab { List { catch { pack forget $w.tree } catch { pack forget $w.nlist } # catch { pack $w.list -fill both -expand 1 -padx 2 -pady 2 } } Tree { # catch { pack forget $w.list } catch { pack forget $w.nlist } catch { pack $w.tree -fill both -expand 1 -padx 2 -pady 2 } } NList { # catch { pack forget $w.list } catch { pack forget $w.tree } catch { pack $w.nlist -fill both -expand 1 -padx 2 -pady 2 } } } } proc tkg_blockListTest {} { button .open -text Open -command tkg_blockListTestSetup pack .open } tkgate-2.0-b10/scripts/misc.tcl000644 001751 001751 00000104071 11141424210 017125 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sun Feb 1 17:56:08 2009 # # # Function summary: # mr Get a message and apply [rescale] to it. # ul Underline position generator. # offsetgeometry Generate geometry string relative to another window. # okcancel Create an OK/Cancel bar for dialogs. # replaceExtension Replace the extension of a file name. # toolbutton Button for a toolbar # ldelete Remove a named item from a list. # lsubtract Do a list "set subtraction" option # lpop Pop an item from the end of a list # lscan Partition elements of a list # assoc Find an item from a list of pairs and return value. # assocn Generalized version of assoc # assocg Find an item from a list of lists and return indexed list. # assocset Find an item from a list of pairs and change its value # assocsetc Find an item from a list of pairs and change its value (create if necessary) # parseargs Parse an argument list. # viewFile View the contents of a file in a separate window. # min Minimum value # max Maximum value # ceil Ceiling function # floor Floor function # labelframe Labled groove frame # checkframe Labled groove frame with checkbutton label # radioframe Labled groove frame with radiobutton label # windowframe Labled groove frame with arbitrary window label # gifI Get a gif image from a file or from cache # start_splash Display the "splash" window # end_splash End the "splash" window. # yesno Generic yes/no dialog box # frb_trace Flat radio button variable change notifier # frb_setMouseOverBackground Set the mouseover background for flat radio buttons. # frb_seeB1press See a B1 mouse press on a flat radio button. # flatradiobutton Create a flat radio button. # paneDecoration Create the decoration for a resizable pane slider. # dialogImage Create the image bar for a dialog box. # gettoplevel Get the top level window from a path # Option:: Options management class # sfix Fix any special characters in a string befor saving it. # dialogLoad Load new option variables from the dialog box # dialogSave Save option variables to the dialog box # writePreferences Write current option settings to prefernces file. # new Declare a new option. # restoreDefaults Restore defaults of all options or of a class of options # TimeCheck Procedure timing check # begin Begin a timer # end End a timer # unqiueName Generate a unique name. # hexEntrySetup Setup for hex only entry widgets. # encodeBits Encode list of numbers into a single number # incdecEntry Numeric entry with inc/dec buttons # chooseInterval Choose an interval to use for a range # colortree Set background color of a window and all its children # packPad Add font-size scaled padding to the top and bottom of a frame. # linkVars Link two variables # proc mr {tag} { return [rescale [m $tag]] } proc getFontScale {fontName baseEmSize} { return [expr [font measure $fontName "M"] / ($baseEmSize+0.0)] } proc colortree {w args} { if {[lindex $args 0] == "-list"} { set args [lindex $args 1] } foreach {sw val} $args { catch { $w configure $sw $val } } foreach cw [winfo children $w] { colortree $cw -list $args } } proc dobell args { bell } proc ul {n} { global lang if { $lang == "en" } { return $n } else { return -1 } } proc safeeval {bad cmd args} { set L {} set skip 0 foreach p $args { if {[lsearch -exact $bad $p] >= 0} { set skip 1 } elseif {$skip == 0} { lappend L $p } else { set skip 0 } } eval $cmd $L } # offsetgeometry win dx dy # # Return a geomtry string with the specified offset from the specified window. # # proc offsetgeometry { win dx dy } { set g [wm geometry $win] set x [string range $g [expr [string first "+" $g] + 1] end] set p [string first "+" $x] set y [string range $x [expr $p + 1] end] set x [string range $x 0 [expr $p - 1]] return +[expr $x + $dx ]+[expr $y + $dy] } proc okcancel {w args} { frame $w set cancelcommand "destroy $w" set okcommand "destroy $w" set oktext [m b.ok] set canceltext [m b.cancel] set bd [option get $w TkgDialog.borderWidth {}] set relief [option get $w TkgDialog.relief {}] parseargs $args {-oktext -canceltext -okcommand -cancelcommand -bd} $w configure -relief $relief -bd $bd button $w.ok -text $oktext -command $okcommand button $w.cancel -text $canceltext -command $cancelcommand pack $w.cancel -side right -padx 5 -pady 5 pack $w.ok -side right -padx 5 -pady 5 } # # Replace the extension of name with ext. "ext" should # include the '.' character if it is desired. # proc replaceExtension {name ext} { set p [string last "." $name ] if { $p >= 0 } { set name [string range $name 0 [expr $p - 1]] } return "$name$ext" } # # Remove all elements from d from l # proc lsubtract {l d} { foreach x $d { set l [ldelete $l $x] } return $l } # # remove i from list l # proc ldelete {l i} { set p [lsearch $l $i] if { $p >= 0 } { return [lreplace $l $p $p] } { return $l } } # # Given a list of the form {{t1 v1} {t2 v2} ... } # return the value from the pair having the tag 'tag'. # proc assoc {tag l} { set value "" catch { foreach p $l { if {[lindex $p 0] == $tag } { set value [lindex $p 1] break } } } return $value } # # Given a list of the form {{a1 b1 ...} {a2 b2 ...} ... } return # the value for which l matches the nth (starting at zero) item # in a sub-list # proc assocn {tag n l} { set value {} catch { foreach p $l { # puts "testing string equal [lindex $p $n] $tag" if {[string equal [lindex $p $n] $tag]} { set value $p break } } } return $value } proc assocg {tag l} { set value "" catch { foreach p $l { if {[lindex $p 0] == $tag } { set value $p break } } } return $value } proc assocset {tag l newV} { set value "" set L {} foreach p $l { if {[lindex $p 0] == $tag } { lappend L [list $tag $newV] } else { lappend L $p } } return $L } proc assocsetc {tag l newV} { set value "" set L {} set found 0 foreach p $l { if {[lindex $p 0] == $tag } { lappend L [list $tag $newV] set found 1 } else { lappend L $p } } if {!$found} { lappend L [list $tag $newV] } return $L } ############################################################################## # # Parse an argument list # proc parseargs {argv nameset args} { set R {} set is_partial 0 set index "" if {[lsearch $args "-partial"] >= 0} { set is_partial 1 } set array [lsearch $args "-array"] if { $array >= 0} { set index [lindex $args [expr $array+1]] } while { [llength $argv] > 0 } { set sw [lindex $argv 0] if { [lsearch -exact $nameset $sw] >= 0 } { set vname [string range $sw 1 end] set val [lindex $argv 1] set argv [lrange $argv 2 end] if { $index == "" } { upvar $vname local_$vname } else { upvar ${vname}($index) local_$vname } set local_$vname $val } elseif { $is_partial } { lappend R $sw set argv [lrange $argv 1 end] } else { error "bad option \"$sw\" must be one of: $nameset" return } } return $R } proc viewFile {label file} { if {[catch { set f [open $file]}]} { errmsg [format [m err.viewfile] $file] return } set w .vfwin set i 0 while { [catch { toplevel $w$i}] } { incr i } set w $w$i wm title $w $label frame $w.main text $w.main.text -yscrollcommand "$w.main.vb set" -xscrollcommand "$w.main.hb set" scrollbar $w.main.vb -command "$w.main.text yview" scrollbar $w.main.hb -orient horizontal -command "$w.main.text xview" grid rowconfigure $w.main 0 -weight 1 grid columnconfigure $w.main 0 -weight 1 grid $w.main.text -row 0 -column 0 -sticky nsew grid $w.main.vb -row 0 -column 1 -sticky ns grid $w.main.hb -row 1 -column 0 -sticky ew button $w.dismiss -text [m b.dismiss] -command "destroy $w" pack $w.main -fill both -expand 1 pack $w.dismiss -fill x catch { $w.main.text insert end [read $f] close $f } $w.main.text configure -state disabled } proc ceil {n} { set n [format %f $n] set d [string first "." $n] if { $d < 0 } { return $n } if { [string trim [string range $n [expr $d+1] end] "0"] == "" } { return [expr [string range $n 0 $d] + 0.0] } else { return [expr [string range $n 0 $d] + 1.0] } } proc floor {n} { set n [format %f $n] set d [string first "." $n] if { $d < 0 } { return $n } return [expr [string range $n 0 $d] + 0.0] } proc min args { if {[llength $args] == 0 } { return 0 } set m [lindex $args 0] foreach v $args { if {$v < $m} { set m $v } } return $m } proc max args { if {[llength $args] == 0 } { return 0 } set m [lindex $args 0] foreach v $args { if {$v > $m} { set m $v } } return $m } proc vmin {v} { if {[llength $v] == 0} { return "" } set M [lindex $v 0] foreach e $v { if { $e < $M } { set M $e } } return $M } proc vmax {v} { if {[llength $v] == 0} { return "" } set M [lindex $v 0] foreach e $v { if { $e > $M } { set M $e } } return $M } proc imin {args} { return [vmin $args]} proc imax {args} { return [vmax $args]} # # Create a labeled grooved frame. # proc labelframe {w lab args} { frame $w set borderwidth [option get $w LabelFrame.borderWidth {}] set relief [option get $w LabelFrame.relief {}] parseargs $args {-borderwidth -bd -relief} if {[info exists bd]} {set borderwidth $bd} $w configure -bd $borderwidth -relief $relief # eval "$w configure $args" # frame $w.labelframe_pad -height 10 # pack $w.labelframe_pad label ${w}_label -text $lab place ${w}_label -in $w -x 10 -y -10 } # # Create a labeled grooved frame with a checkbutton # proc checkframe {w lab args} { frame $w set borderwidth [option get $w LabelFrame.borderWidth {}] set relief [option get $w LabelFrame.relief {}] set variable "checkframe$w" set command "" parseargs $args {-bd -relief -variable -command} if {[info exists bd]} {set borderwidth $bd} $w configure -borderwidth $borderwidth -relief $relief checkbutton ${w}_label -text $lab -variable $variable -command $command place ${w}_label -in $w -x 10 -y -10 } # # Create a labeled grooved frame with a radiobutton # proc radioframe {w lab args} { frame $w set borderwidth [option get $w LabelFrame.borderWidth {}] set relief [option get $w LabelFrame.relief {}] set variable "checkframe$w" set value "0" set command "" parseargs $args {-bd -relief -variable -value -command} if {[info exists bd]} {set borderwidth $bd} $w configure -borderwidth $borderwidth -relief $relief radiobutton ${w}_label -text $lab -variable $variable -value $value -command $command place ${w}_label -in $w -x 10 -y -10 } # # Create a grooved frame with another window as a label # proc windowframe {w lw args} { frame $w set borderwidth [option get $w LabelFrame.borderWidth {}] set relief [option get $w LabelFrame.relief {}] set dy 0 parseargs $args {-bd -relief -dy} if {[info exists bd]} {set borderwidth $bd} $w configure -borderwidth $borderwidth -relief $relief place $lw -in $w -x 10 -y [expr -10 + $dy] raise $lw } # # Create an image radiobutton with accompaning text and explaination. # proc imageRadioButton {w args} { set onimage "" set offimage "" set variable "" set label "" set description "" set value "" set wraplength 200 parseargs $args {-onimage -offimage -variable -value -label -description -wraplength} frame $w radiobutton $w.button -image $offimage -selectimage $onimage -variable $variable -value $value -indicatoron 0 label $w.header -text $label -font dialogBigExpFont label $w.details -text $description -justify left -wraplength $wraplength -font dialogExpFont frame $w.pad -width 4 pack $w.button -side left -anchor nw pack $w.pad -side left pack $w.header -anchor nw pack $w.details -anchor nw -pady 2 } # # Create an image object from a .gif file name. # proc gifI {f} { global bd global gifTable if { [string index $f 0] != "/" } { set f "$bd/$f" } # # Try to get the image from the image table first. If we don't find it, # create the image and save it in the table. # catch { return $gifTable($f) } if { [ catch { set gifTable($f) [image create photo -file $f] }]} { set gifTable($f) [image create photo -file "$bd/broken-img.gif" ] } return $gifTable($f) } # # Post the splash window. # proc start_splash {} { global sd bd splash_start_time tkg_doSplash if { ! $tkg_doSplash} { return } if {[catch { set splash_start_time [clock clicks -milliseconds] }]} { set splash_start_time "rawdelay" } if {[catch { wm state . withdrawn }]} { wm iconify . } update toplevel .splash -class Splash label .splash.logo -image [gifI "$bd/biggatelogo.gif"] pack .splash.logo wm overrideredirect .splash 1 wm transient .splash "" set iwidth [image width [.splash.logo cget -image]] set iheight [image height [.splash.logo cget -image]] set x [expr ([winfo screenwidth .] - $iwidth)/2 ] set y [expr ([winfo screenheight .] - $iheight)/2 ] wm geometry .splash +${x}+${y} update } # # Remove the splash window # proc end_splash {} { global bd splash_start_time tkg_doSplash tkg_splashWait if { ! $tkg_doSplash} { return } if { $splash_start_time == "rawdelay" } { set time_to_go 1000 } else { set time_to_go [expr $tkg_splashWait - ([clock clicks -milliseconds] - $splash_start_time)] } if { $time_to_go < 1 } { set time_to_go 1 } after $time_to_go { update destroy .splash wm deiconify . update } } proc yesno {msg} { return [tk_messageBox -default no -type yesno -icon warning -message $msg] } # # Respond to a variable change in a flatradiobutton # proc frb_trace {w v args} { catch { global flatradiobutton_details set variable [assoc variable $flatradiobutton_details($w)] global $variable set v [set $variable] set bg [assoc bg $flatradiobutton_details($w)] set value [assoc value $flatradiobutton_details($w)] if {$v == $value } { $w configure -relief sunken } else { $w configure -relief flat $w configure -bg $bg } } } # # Set brackground of flat radio button based on mouseover state # proc frb_setMouseOverBackground {w ismouseover} { global flatradiobutton_details set bg [assoc bg $flatradiobutton_details($w)] set activebackground [assoc activebackground $flatradiobutton_details($w)] set selectcolor [assoc selectcolor $flatradiobutton_details($w)] set value [assoc value $flatradiobutton_details($w)] set variable [assoc variable $flatradiobutton_details($w)] global $variable set v [set $variable] if { $ismouseover } { if { $v == $value } { $w configure -bg $selectcolor -activebackground $selectcolor -relief raised } else { $w configure -bg $activebackground -activebackground $activebackground -relief raised } } else { if { $v == $value } { $w configure -bg $selectcolor -relief sunken } else { $w configure -bg $bg -relief flat } } } proc frb_seeB1press {w} { global flatradiobutton_details set command [assoc command $flatradiobutton_details($w)] set value [assoc value $flatradiobutton_details($w)] set var [assoc variable $flatradiobutton_details($w)] global $var set $var $value frb_setMouseOverBackground $w 1 eval $command } # # tcl/tk 8.3 and earlier does not support flat radio buttons with "-indicatoron false". # This is a limited implementation and only supports the features we need for the mode # selectors. # proc flatradiobutton {w args} { global flatradiobutton_details set image "" set variable "" set value "" set command "" set selectcolor "\#aaaacc" set activebackground [option get . FlatRadioButton.activeBackground {}] set bg [option get . FlatRadioButton.background {}] parseargs $args {-image -variable -value -command -selectcolor -bg -activebackground} set flatradiobutton_details($w) {} lappend flatradiobutton_details($w) [list image $image] lappend flatradiobutton_details($w) [list variable $variable] lappend flatradiobutton_details($w) [list value $value] lappend flatradiobutton_details($w) [list command $command] lappend flatradiobutton_details($w) [list selectcolor $selectcolor] lappend flatradiobutton_details($w) [list bg $bg] lappend flatradiobutton_details($w) [list activebackground $activebackground] global $variable if {[catch {button $w -takefocus 0 -image $image -bd 1 -relief flat -overrelief raised}]} { button $w -takefocus 0 -image $image -bd 1 -relief flat } set v [set $variable] if {$v == $value } { $w configure -relief sunken $w configure -bg $selectcolor } else { $w configure -relief flat } trace variable $variable w "frb_trace $w" bind $w "trace vdelete $variable w \"frb_trace $w\"" bind $w "frb_seeB1press $w" bind $w "+ frb_setMouseOverBackground %W 1" bind $w "+ frb_setMouseOverBackground %W 0" } proc paneDecoration {w args} { set orient vertical parseargs $args {-orient} if { $orient == "vertical" } { set width 50 set height 2 } else { set width 2 set height 50 } frame $w.v1 -bd 1 -relief raised -width $width -height $height frame $w.v2 -bd 1 -relief raised -width $width -height $height frame $w.v3 -bd 1 -relief raised -width $width -height $height if { $orient == "vertical" } { pack $w.v1 pack $w.v2 pack $w.v3 } else { pack $w.v1 -side left pack $w.v2 -side left pack $w.v3 -side left } } proc dialogImage {w args} { global tkg_showDialogImage set fontScale [getFontScale dialogExpFont 10] set image "" set caption "" set font dialogCapFont set bd 0 set width [rescale [m @opt.sidebar.width]] set height 0 set relief flat set explaination "" set labelheight [rescale 50] set imgbd 0 set force 0 set imgrelief flat set expfont dialogExpFont parseargs $args {-image -caption -font -bd -imgbd -imgrelief -width -relief -explaination -labelheight -force -expfont} if {!$tkg_showDialogImage && !$force} { frame $w return } set iheight [image height $image] set iwidth [image width $image] set height [expr $iheight + 100 ] frame $w -bd $bd -relief $relief -width $width -height $height label $w.cap -text $caption -font $font label $w.img -image $image -bd $imgbd -relief $imgrelief # label $w.exp -text $explaination -justify left -wraplength [expr 155 * $fontScale] -font $expfont label $w.exp -text $explaination -justify left -wraplength [expr $width - 10] -font $expfont set x [expr $width/2] set y [expr $labelheight/2] place $w.cap -x $x -y $y -anchor center set y [expr $y + $iheight/2 + $labelheight] place $w.img -x $x -y $y -anchor center set y [expr $y + [image height $image]/2 + 30] place $w.exp -x $x -y $y -anchor n set bottom [expr [winfo reqheight $w.exp] + $y + 15] if { $bottom > $height } { $w configure -height $bottom } } # # Validate function for bit size selector. All chars must be digits, and there # is a 3 char maximum. # proc bsValidate {w act cur c newv} { # puts "bsValidate $w <$act> <$cur> <$c> <$newv>" # if {[string length $newv] == 0} { return 0 } if {$act == 1} { if {[string length $cur] > 2} { return 0 } return [string is digit $c] } return 1 } proc bitsizeselector {w args} { set entry 1 parseargs $args {-variable -value -width -entry -takefocus} set argv {} if {[info exists variable]} { lappend argv -variable $variable } if {[info exists value]} { lappend argv -value $value } if {[info exists width]} { lappend argv -width $width } if {[info exists entry]} { lappend argv -entry $entry } if {[info exists takefocus]} { lappend argv -takefocus $takefocus } eval "Dropbox::new $w $argv -entry $entry -validatecommand bsValidate" for { set i 1} { $i <= 32 } { incr i } { Dropbox::itemadd $w $i } } namespace eval TimeCheck { variable timer proc begin {e} { variable timer set timer($e) [clock clicks -milliseconds] puts "begin $e" } proc end {e} { variable timer set t [clock clicks -milliseconds] set dt [expr ($t - $timer($e) + 0.0)/1000.0] puts "end $e $dt" } } # # Fix name so as not to have special characters and make sure it does # not conflict with names in l. # proc unqiueName {name l} { puts "unqiueName $name" return $name } # # Setup for hex only entry widgets # proc hexEntrySetup {} { bind HexEntry { continue } bind HexEntry { continue } bind HexEntry { continue } bind HexEntry { set c [string tolower %A] if { $c == "" } { continue } if { [string first $c "0123456789abcdef"] < 0 } { break } if {[%W selection present]} { %W delete sel.first sel.last } else { %W delete insert } set L [string length [%W get]] if { $L >= 8 } { break } # # Temporarily disable the "HexEntry" event handler and send a regular # event to insert the character. # bindtags %W [lrange [bindtags %W] 1 end] event generate %W -keysym $c bindtags %W [concat [list HexEntry] [bindtags %W]] break } } # # Setup for number only entry widgets # proc numEntrySetup {} { bind NumEntry { continue } bind NumEntry { continue } bind NumEntry { continue } bind NumEntry { set c [string tolower %A] if { $c == "" } { continue } if { [string first $c "0123456789"] < 0 } { break } if {[%W selection present]} { %W delete sel.first sel.last } else { %W delete insert } set L [string length [%W get]] if { $L >= 8 } { break } # # Temporarily disable the "NumEntry" event handler and send a regular # event to insert the character. # bindtags %W [lrange [bindtags %W] 1 end] event generate %W -keysym $c bindtags %W [concat [list NumEntry] [bindtags %W]] break } } # # Setup for number only entry widgets # proc floatEntrySetup {} { bind FloatEntry { continue } bind FloatEntry { continue } bind FloatEntry { continue } bind FloatEntry { set c [string tolower %A] if { $c == "" } { continue } if { [string first $c "0123456789."] < 0 } { break } if {[%W selection present]} { %W delete sel.first sel.last } else { %W delete insert } set L [string length [%W get]] if { $L >= 8 } { break } # # Temporarily disable the "FloatEntry" event handler and send a regular # event to insert the character. # bindtags %W [lrange [bindtags %W] 1 end] if { $c == "." } { set c period } event generate %W -keysym $c bindtags %W [concat [list FloatEntry] [bindtags %W]] break } } ############################################################################# # # Helping function for shellWindow. # ############################################################################# proc shellExec {args} { global shellCommand set w .shell_win $w.text insert end "${shellCommand}\n" cmd $w.text tag configure cmd -foreground blue if {[catch { set result [namespace eval :: "$shellCommand"] } err]} { $w.text insert end "${err}\n" err $w.text tag configure err -foreground red } else { $w.text insert end "${result}\n" result $w.text tag configure result -foreground black } $w.text see end set shellCommand "" } ############################################################################# # # Create a shell window in which we can type an execute tcl commands for # debugging purposes. # ############################################################################# proc shellWindow {} { set w .shell_win if {[catch {toplevel $w}]} { raise $w return } wm title $w "TKGate: Tcl Shell" button $w.dismiss -text Dismiss -command "destroy $w" pack $w.dismiss -side bottom -anchor e -padx 5 -pady 5 frame $w.b pack $w.b -side bottom -fill x -expand 1 label $w.b.l -text "Command: " pack $w.b.l -side left -padx 5 -pady 5 entry $w.b.e -textvariable shellCommand pack $w.b.e -fill x -padx 5 -pady 5 -expand 1 bind $w.b.e shellExec focus $w.b.e text $w.text -bd 2 -relief sunken -width 60 -height 20 -yscrollcommand "$w.vb set" pack $w.text -padx 5 -pady 5 -fill both -expand 1 -side left scrollbar $w.vb -orient vertical -command "$w.text yview" pack $w.vb -side right -padx 5 -pady 5 -fill y -expand 1 } ############################################################################# # # Perform a standard wait for a dialog box. We update all events, set # a grab on the dialog box and wait for the dialog box to be destroyed. # We then release the grab and call gat_syncInterface to cause any # internal circuit changes to be synchronized with tcl/tk elements. # ############################################################################# set dialogWaitStack {} proc dialogWait {w args} { global dialogWaitStack set dosync 1 parseargs $args {-dosync} # # Put window on stack # lappend dialogWaitStack $w update grab set $w tkwait window $w if {[llength $dialogWaitStack] > 1 } { set dialogWaitStack [lrange $dialogWaitStack 0 end-1] set lastW [lindex $dialogWaitStack [expr [llength $dialogWaitStack]-1]] catch { grab release $w } grab set $lastW } else { catch { grab release $w } set dialogWaitStack {} } if {$dosync} { gat_syncInterface } } ############################################################################# # # Return the top-level window that w is contained in. # proc gettoplevel {w} { while {1} { set pw [winfo parent $w] if { $pw == "" || $pw == "."} break set w $pw } return $w } ############################################################################# # # If a number is prepended with a '*', scale it by the current font scale. # proc rescale {n} { if {[string index $n 0] == "*"} { return [expr int([getFontScale dialogExpFont 13] * [string range $n 1 end])] } return $n } ############################################################################# # # Return non-zero if $c is a character from a word ( alphanumeric or "_"). # proc iswordchar {c} { if { [string is alnum $c] || $c == "_" } { return 1 } return 0 } ############################################################################# # # Return non-zero if $c is a character from a word including task names ( alphanumeric, "_" or "$"). # proc istaskwordchar {c} { if { [string is alnum $c] || $c == "_" || $c == "\$" } { return 1 } return 0 } ############################################################################# # # Find the position of the first occurance of $word in $line with the # restriction that $word must be surrounded by non-word characters or at the # start or end of a line. Returns -1 if $word is not found # proc findword {line word} { set llen [string length $line] set wlen [string length $word] set p 0 while {[set p [string first $word [string range $line $p end]]] >= 0 } { if { ($p == 0 || ! [iswordchar [string index $line [expr $p - 1 ]]]) \ && ($p+$wlen >= $llen || ! [iswordchar [string index $line [expr $p + $wlen ]]]) } { break } } return $p } proc lpop {_l} { upvar $_l l set l [lrange $l 0 [expr [llength $l] - 2]] } proc lscan {l args} { set i 0 foreach v $args { upvar $v _v$i set _v$i [lindex $l $i] incr i } } proc llast {l} { set n [llength $l] if {$n > 0} { return [lindex $l [expr $n - 1]] } else { return "" } } proc makeFriendlyChar {c} { if {[string is graph $c] || $c == " " } { return $c } set n 0 binary scan $c c n return \\[format %03o $n] } proc findLibraryFile {name} { global tkg_simVLibPath foreach directory $tkg_simVLibPath { set directory [namespace eval :: "eval concat $directory"] if {[file exists $directory/$name]} { return $directory/$name } if {[file exists $directory/$name.v]} { return $directory/$name.v } } return "" } proc encodeBits {b value} { set n [llength $value] set out 0 for {set i 0} {$i < $n} {incr i} { if {[lindex $value $i]} { set out [expr $out | (1 << $i)] } } return $out } proc validate_hex {s} { if {[scan $s %x n] != 1} { set n 0 } return $n } proc validate_posint {s} { if {[scan $s %d n] != 1 || $n < 1} { set n 1 } return $n } proc validate_nonnegint {s} { if {[scan $s %d n] != 1 || $n < 0} { set n 0 } return $n } proc validate_int {s} { if {[scan $s %d n] != 1} { set n 0 } return $n } # # Create a basic toolbar button # proc toolbutton {w img act help args} { set state normal parseargs $args {-state} if {[catch {button $w -image [gifI $img] -takefocus 0 -relief flat -command $act -overrelief raised -state $state}]} { button $w -image [gifI $img] -takefocus 0 -relief flat -command $act -state $state } if { $help != ""} { helpon $w [m $help] } } # # Validate function for bit size selector. All chars must be digits, and there # is a 3 char maximum. # proc hexValidate {w act cur c newv} { if {$act == 1} { return [string is xdigit $c] } return 1 } proc _incdecDelta {varName args} { upvar \#0 $varName v set min 0 set max 2147483648 set format %f set delta 1 parseargs $args {-delta -min -max -format} scan $v $format n set newValue [expr $n + $delta] if { $newValue < $min } { set newValue $min } if { $newValue > $max } { set newValue $max } set v [format $format $newValue] } proc incdecEntry {w args} { frame $w entry $w.e set class "" set variable "" set min 0 set max 1e20 set width 8 set format %f set justify right set validatecommand "" set font [$w.e cget -font] set delta 1 parseargs $args {-variable -width -min -max -class -delta -format -justify -validatecommand -font} if { $validatecommand != "" } { $w.e configure -bg white -width $width -textvariable $variable -justify $justify \ -validate key -validatecommand "$validatecommand %W %d %s %S %P" \ -invalidcommand bell -font $font } else { $w.e configure -bg white -width $width -textvariable $variable -justify $justify -font $font } button $w.up -image [gifI up.gif] -command "_incdecDelta $variable -delta $delta -max $max -min $min -format $format" button $w.dn -image [gifI down.gif] -command "_incdecDelta $variable -delta [expr -$delta] -max $max -min $min -format $format" if { $class != "" } { bindtags $w.e [concat [list $class] [bindtags $w.e]] } pack $w.e -side left pack $w.up -side top -fill y -expand 1 pack $w.dn -side bottom -fill y -expand 1 } proc replaceSwitchValue {cmd sname value} { set i [lsearch $cmd $sname] if {$i < 0} return $cmd incr i return [lreplace $cmd $i $i $value] } proc incdecEntry_configure {w args} { parseargs $args {-min -max -delta} set upcommand [$w.up cget -command] set dncommand [$w.dn cget -command] if {[info exists min]} { set upcommand [replaceSwitchValue $upcommand -min $min] set dncommand [replaceSwitchValue $dncommand -min $min] } if {[info exists max]} { set upcommand [replaceSwitchValue $upcommand -max $max] set dncommand [replaceSwitchValue $dncommand -max $max] } if {[info exists delta]} { set upcommand [replaceSwitchValue $upcommand -delta $delta] set dncommand [replaceSwitchValue $dncommand -delta [expr -$delta]] } $w.up configure -command $upcommand $w.dn configure -command $dncommand } proc chooseInterval {D} { set G [expr exp(int(log($D)/log(10.0)+0.999999999)*log(10.0))] set Q [expr ($G-$D)/$G ] if {$Q >= 0.8} { return [expr $G*0.02 ] } if {$Q >= 0.6} { return [expr $G*0.05 ] } return [expr $G*0.1 ] } # # add pads on the top and botton of a window packed with "pack" # proc packPad {w args} { set toppad 10 set bottompad 10 parseargs $args {-pad -toppad -bottompad} if {[info exists pad]} { set toppad $pad set bottompad $pad } frame $w.pad_top -height [rescale *$toppad] frame $w.pad_bottom -height [rescale *$bottompad] pack $w.pad_top -side top pack $w.pad_bottom -side bottom } proc linkVars_change {v1 v2 n args} { global linkVars_assoc upvar \#0 $v1 _v1 upvar \#0 $v2 _v2 set assoc $linkVars_assoc($v1:$v2) if {$n == 1} { set p [assocn $_v1 0 $assoc] set new_v2 [lindex $p 1] # puts "$v1 changed to $_v1, $v2 will become $new_v2" if { $new_v2 != $_v2 } { set _v2 $new_v2 } } else { set p [assocn $_v2 1 $assoc] set new_v1 [lindex $p 0] # puts "$v2 changed to $_v2, $v1 will become $new_v1" if { $new_v1 != $_v1 } { set _v1 $new_v1 } } } ############################################################################# # # Link values of v1 and v2 with an association list. When one variable # changes, the other will change to reflect corresponding value in the # association list. # proc linkVars {v1 v2 assoc} { global linkVars_assoc upvar \#0 $v1 _v1 upvar \#0 $v2 _v2 set linkVars_assoc($v1:$v2) $assoc trace variable _v1 w "linkVars_change $v1 $v2 1" trace variable _v2 w "linkVars_change $v1 $v2 2" } tkgate-2.0-b10/scripts/status.tcl000644 001751 001751 00000011103 11145421176 017522 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Feb 13 20:46:38 2009 # set runlogo_state -1 set runlogo_speed 50 set runlogo_startstate 27 set runlogo_maxstate 50 proc updateStatus args { global tkg_displayFile tkg_currentModule tkg_modifiedFlag tkg_statusMessage global tkg_progName tkg_progVer if { $tkg_modifiedFlag } { set mod "*" } else { set mod "" } .status.file configure -text "[m ifile]: $tkg_displayFile$mod" .status.block configure -text "[m imodule]: $tkg_currentModule" .status.msg configure -text "$tkg_statusMessage" -anchor w wm title . "$tkg_displayFile$mod - $tkg_progName $tkg_progVer" } proc tkg_resetLogo {} { global bd runlogo_state runlogo_startstate logo_w catch { $logo_w configure -image "" -image [gifI [format "run%02d.gif" $runlogo_startstate]] set runlogo_state $runlogo_startstate } } proc tkg_pauseLogo {} { global bd runlogo_ev catch { after cancel $runlogo_ev } } proc tkg_stepLogo {} { global bd runlogo_state runlogo_speed runlogo_ev runlogo_maxstate logo_w catch { set filename [format "run%02d.gif" ${runlogo_state}] $logo_w configure -image "" -image [gifI "$filename"] set runlogo_state [expr $runlogo_state + 1 ] if { $runlogo_state > $runlogo_maxstate } { set runlogo_state 1 } } } proc tkg_stepRunLogo {} { global bd runlogo_state runlogo_speed runlogo_ev runlogo_maxstate logo_w catch { set filename [format "run%02d.gif" ${runlogo_state}] $logo_w configure -image "" -image [gifI "$filename"] set runlogo_state [expr $runlogo_state + 1 ] if { $runlogo_state > $runlogo_maxstate } { set runlogo_state 1 } set runlogo_ev [after $runlogo_speed tkg_stepRunLogo] } } proc tkg_runLogo {} { global bd runlogo_speed runlogo_ev catch { catch { after cancel $runlogo_ev } set runlogo_ev [after $runlogo_speed tkg_stepRunLogo] } } proc tkg_editLogo {} { global bd runlogo_ev logo_w catch { catch { after cancel $runlogo_ev } $logo_w configure -image [gifI "gatelogo.gif"] } } proc tkg_analysisLogo {} { global bd runlogo_ev logo_w catch { catch { after cancel $runlogo_ev } $logo_w configure -image [gifI "anallogo.gif"] } } proc tkg_checkpointReq {} { global tkg_wantCheckpoint tkg_checkpointEnabled tkg_checkpointFreq if { $tkg_checkpointEnabled } { set tkg_wantCheckpoint 1 } after [expr $tkg_checkpointFreq * 1000] tkg_checkpointReq } ############################################################################# # # Add or remove the simulation time window # proc updateSimTimeWin {w args} { global simOn if {$simOn} { pack $w.simtime -side right -padx 3 -pady 3 -ipadx 2 -ipady 2 } else { pack forget $w.simtime } } proc makeStatus {w} { global tkg_displayFile tkg_currentModule tkg_modifiedFlag tkg_statusMessage global simOn currentSimTime label $w.file -relief sunken -bg "\#ffbbbb" -width 30 -height 1 -justify left -anchor w label $w.block -relief sunken -bg "\#ffbbbb" -width 25 -height 1 -justify left -anchor w label $w.msg -relief sunken -bg "\#ffbbbb" -height 1 label $w.simtime -relief sunken -bg "\#ffbbbb" -height 1 -width 15 -textvariable ::currentSimTime -anchor w pack $w.file -side left -padx 3 -pady 3 -ipadx 2 -ipady 2 -anchor w pack $w.block -side left -padx 3 -pady 3 -ipadx 2 -ipady 2 -anchor w pack $w.msg -side left -padx 3 -pady 3 -ipadx 2 -ipady 2 -fill x -expand 1 updateStatus trace variable tkg_displayFile w updateStatus trace variable tkg_currentModule w updateStatus trace variable tkg_modifiedFlag w updateStatus trace variable tkg_statusMessage w updateStatus trace variable simOn w "updateSimTimeWin $w" helpon $w.msg [m ho.status.msg] helpon $w.block [m ho.status.block] helpon $w.file [m ho.status.file] } proc tkg_cancel {} { global tkg_statusMessage set tkg_statusMessage "" updateStatus } tkgate-2.0-b10/scripts/message.tcl000644 001751 001751 00000004546 10675073746 017655 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Fri Sep 21 22:03:18 2007 # set cms_status 0 set debugMessageNum 0 ###################################################################### # # Display a simple error message with an OK button to dismiss # proc errmsg {msg} { tk_messageBox -default ok -icon error -type ok -message $msg } proc tkScreenChanged args { # puts "tkScreenChanged $args" } proc confirmMsg {msg} { global msg_font cms_status set cms_status 0 set result [tk_messageBox -default ok -icon question -type okcancel -message $msg] if { "$result" == "ok" } { set cms_status 1 } return $cms_status } proc tkg_verilogErr {fn msg} { InfoPanel::log "$fn, $msg" -color red } # # Post a debugging message with a dismiss button # proc tkg_debugMessage {msg} { global debugMessageNum scan [winfo pointerxy .] "%d %d" x y set w .tempmsg$debugMessageNum incr debugMessageNum toplevel $w -bg bisque wm geometry $w +[expr $x + 5]+[expr $y - 30] label $w.l -text $msg -bg bisque -justify left -font boldLabelFont button $w.d -text [m b.dismiss] -command "destroy $w" pack $w.l -padx 4 -pady 4 pack $w.d -padx 4 -pady 4 -fill x } # # Post a message which lasts only as long as the mouse is depressed # proc tkg_tempMessage {msg} { scan [winfo pointerxy .] "%d %d" x y catch { destroy .tempmsg } toplevel .tempmsg -bg bisque wm geometry .tempmsg +[expr $x + 5]+[expr $y - 30] wm transient .tempmsg . wm overrideredirect .tempmsg 1 label .tempmsg.l -text $msg -bg bisque -justify left -font boldLabelFont pack .tempmsg.l -padx 4 -pady 4 } proc tkg_hideTempMessage {} { catch { destroy .tempmsg } } tkgate-2.0-b10/scripts/editgate.tcl000644 001751 001751 00000172341 11257466131 020005 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2009 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Sep 26 15:32:41 2009 # # # Wire Ops: Changes to the port list are passed back through the variable "edgat_wops". The # variable contains a list of "wire ops". Wire ops can be one of the following: # # {add I} Add a wire to port group I # {delete I2} Delete 2nd wire of port group I # {edit Pold w Pnew io n} Edit port. Pold is old port name, w is signal name, # Pnew is new port name, io is the I/O type, # and n is the number of bits. set edgat_wires {} set edgat_wops {} set edgat_portOpCount 0 set edgat_dtype "huh?" set edgat_type "huh?" set edgat_name "huh?" set edgat_hideName 1 set edgat_cpbreak 0 set edgat_anchor 0 set edgat_xpos 0 set edgat_ypos 0 set edgat_blockFunc "huh?" set edgat_newBlock 0 set edgat_newPort 0 set edgat_geom "+0+0" set ecpOmega 100 set ecpPhi 50 set ecpDuty 50 set edgat_switch 0 set edgat_extbar 0 set edgat_dip 0 set edgat_tap 0 set edgat_memFile "" set edgat_ok 0 set edgat_commentLen 0 set edgat_dolink 0 set edgat_link "" set edport_hidename 0 set edport_ok 0 set edport_idx 0 set edport_sig "huh" set edport_port "huh" set edport_basePort "huh" set edport_type "huh" set edport_bits "huh" set clkFrame [list] array set editgate_caps { AND {sig size add} OR {sig size add} XOR {sig size add} MUX {sig size add} DEMUX {sig size add} CONCAT {sig size add} Module {sig size type port add side} TAP {} } proc trace_edgat_tech args { global edgat_tech edgatdelay_w edgat_techdelay gat_setGateTechDelays $edgat_tech } trace variable edgat_tech w trace_edgat_tech ############################################################################# # # Dialog box for editing a single port on a module. # namespace eval PortEdit { proc ok {} { global edport_ok set edport_ok 1 destroy .edport } ######################################## # # Throw up a dialog box for changing port values (Now only used when creating ports) # proc post {pos args} { global edport_idx edport_sig edport_basePort edport_port edport_type edport_bits edport_hidename global edgat_type edgat_wops edport_ok global edgatio_w set showsig 1 set interface 0 parseargs $args {-ismodule -showsig} set edport_ok 0 set oldPort $edport_port set edport_hidename 1 set p [string first ":" $edport_port] if { $p > 0 } { set edport_basePort [string range $edport_port 0 $p] set edport_port [string range $edport_port [expr $p + 1] end] set isBlock 1 } { set edport_basePort "" set isBlock 0 } toplevel .edport wm transient .edport . wm resizable .edport 0 0 wm title .edport [m port.title] wm geometry .edport $pos frame .edport.box -relief raised -bd 1 dialogImage .edport.box.image -image [gifI port.gif] -caption [m port.parms] grid .edport.box.image -sticky nsew -column 0 -row 0 -rowspan 6 grid rowconfigure .edport.box 5 -weight 1 if { $showsig } { label .edport.box.siglab -text "[m db.gate.signam]:" entry .edport.box.sig -textvariable edport_sig -bg white } label .edport.box.portlab -text "[m db.gate.portnam]:" entry .edport.box.port -textvariable edport_port -bg white label .edport.box.iolab -text "[m db.gate.iotype]:" label .edport.box.bitlab -text "[m db.gate.bitw]:" frame .edport.box.io radiobutton .edport.box.io.in -text [m b.in] -variable edport_type -value in radiobutton .edport.box.io.out -text [m b.out] -variable edport_type -value out radiobutton .edport.box.io.bdir -text [m b.inout] -variable edport_type -value inout pack .edport.box.io.in .edport.box.io.out .edport.box.io.bdir -side left # entry .edport.box.bit -textvariable edport_bits -bg white bitsizeselector .edport.box.bit -variable edport_bits -width 3 if { $showsig } { bind .edport.box.sig PortEdit::ok } bind .edport.box.port PortEdit::ok bind .edport.box.bit PortEdit::ok frame .edport.box.pad -height 10 grid .edport.box.pad -column 1 -row 0 grid .edport.box.portlab -column 1 -row 1 -sticky e -padx 5 -pady 2 grid .edport.box.port -column 2 -row 1 -sticky w -padx 5 -pady 2 grid .edport.box.iolab -column 1 -row 2 -sticky e -padx 5 -pady 2 grid .edport.box.io -column 2 -row 2 -sticky w -padx 5 -pady 2 grid .edport.box.bitlab -column 1 -row 3 -sticky e -padx 5 -pady 2 grid .edport.box.bit -column 2 -row 3 -sticky w -padx 5 -pady 2 if { $showsig } { grid .edport.box.siglab -column 1 -row 4 -sticky e -padx 5 -pady 2 grid .edport.box.sig -column 2 -row 4 -sticky w -padx 5 -pady 2 } frame .edport.confirm -relief raised -bd 1 button .edport.confirm.ok -text [m b.ok] -command PortEdit::ok button .edport.confirm.cancel -text [m b.cancel] -command { destroy .edport } pack .edport.confirm.ok -side left -padx 5 -pady 5 pack .edport.confirm.cancel -side right -padx 5 -pady 5 pack .edport.box -fill x pack .edport.confirm -fill both # # Select port name # .edport.box.port selection range 0 end .edport.box.port icursor end focus .edport.box.port if { $showsig } { helpon .edport.box.siglab [m ho.edgat.signam] } helpon .edport.box.portlab [m ho.edgat.port] helpon .edport.box.iolab [m ho.edgat.iolab] helpon .edport.box.bitlab [m ho.edgat.bitlab] dialogWait .edport return $edport_ok } } ############################################################################# # # Methods for editing module parameters. # namespace eval ModParmMgr { variable pmlb_w ############################################################################# # # Entry manager for the module parameter manager # proc manager {cmd args} { variable pmlb_w if { [lindex $args 0] == "-args" } { set args [lindex $args 1] } switch $cmd { canenter { # check to see if we can enter data set c [lindex $args 2] if { $c == 1} { return 1 } else { return 0 } } entrywidget { return 0 } close { set data [lindex $args 3] return $data } delete { # respond to the delete key } canappend { return 0 } } } proc seeDestroy args { variable pmlb_w global edgat_modParms set N [SpreadSheet::size $pmlb_w] for { set i 0 } { $i < $N } { incr i } { set entry [SpreadSheet::get $pmlb_w $i] set edgat_modParms([lindex $entry 0]) [lindex $entry 1] } } proc create {w} { variable pmlb_w global edgat_modParms frame $w.mparms set pmlb_w $w.mparms.lb # # Parameter names # set names [lsort [array names edgat_modParms]] if {[llength $names] > 0 } { SpreadSheet::create $w.mparms.lb -height 15 -bd 1 -relief sunken -yscrollcommand "$w.mparms.vb set" -expandcol 1 -entrycommand ModParmMgr::manager scrollbar $w.mparms.vb -orient vertical -command "SpreadSheet::yview $w.mparms.lb" SpreadSheet::addcolumn $w.mparms.lb -width 25 -header [m db.gate.mparm.parameter] SpreadSheet::addcolumn $w.mparms.lb -width 20 -header [m db.gate.mparm.value] pack $w.mparms.lb $w.mparms.vb -side left -fill both foreach n $names { SpreadSheet::insert $w.mparms.lb end [list $n $edgat_modParms($n)] } bind $w.mparms.lb ModParmMgr::seeDestroy } else { label $w.mparms.exampleA -text [m db.gate.mparm.exampleA] -justify left pack $w.mparms.exampleA -padx 10 -pady 10 label $w.mparms.exampleB -text [m db.gate.mparm.exampleB] -justify left -font hdlFont pack $w.mparms.exampleB -padx 10 -pady 10 -anchor w } pack $w.mparms -padx 10 -pady 10 } } ############################################################################# # # Methods for editing the port list of an instance. # namespace eval PortMgr { variable io_w "" variable iolb_w "" variable doIdleUpdate 0 variable edcap_sig variable edcap_port variable edcap_type variable edcap_size variable edcap_add variable edcap_side ############################################################################# # # Add a new port (used on initial load of gate) # proc add {p n} { variable iolb_w SpreadSheet::insert $iolb_w $p $n } ############################################################################# # # Respond to a press of the "New" button # proc addNew {w} { set r [SpreadSheet::size $w] set r [SpreadSheet::getPhysicalRow $w $r] SpreadSheet::entrySelect $w $r 0 } ############################################################################# # # Respond to a press of the "Delete" button # proc deletePort {w} { variable edcap_add variable edport_type global edgat_wops # # Deletions only allowed when adds are also valid. # if {!$edcap_add} { return } # # If nothing is selected, then do nothing # set items [SpreadSheet::getselection $w] if {[llength $items] == 0} { return } # # Count number of variable ports # set N [SpreadSheet::size $w] set Nvar 0 for { set i 0 } { $i < $N } { incr i } { set E [SpreadSheet::get $w $i] set P [lindex $E 1] if {[regexp {^([A-Za-z]+)([0-9]+)$} $P X B pnum]} { incr Nvar } } # # If all remaining variable ports are selected, then do nothing. # if {[llength $items] == $Nvar} { return } # # Make sure selected ports are all of the same variable type # set ok 1 set baseName "" set plist {} foreach i $items { set P [lindex [SpreadSheet::get $w $i] 1] if {![regexp {^([A-Za-z]+)([0-9]+)$} $P X B pnum]} { set ok 0 } if {$baseName == "" } { set baseName $B } if { $baseName != $B } { set ok 0 } lappend plist $pnum } if { !$ok } { return } # # Deletion is ok # SpreadSheet::delete $w $items # # Create wire ops for deletions in reverse order of port number # foreach pn [lsort -integer -decreasing $plist] { lappend edgat_wops [list delete $baseName$pn] } # # Go get the undeleted entries from the variable pad and sort them # set N [SpreadSheet::size $w] set L {} for { set i 0 } { $i < $N } { incr i } { set E [SpreadSheet::get $w $i] set P [lindex $E 1] if {[regexp {^([A-Za-z]+)([0-9]+)$} $P X B pnum]} { lappend L [list $pnum $i] } } set L [lsort -index 0 $L] # # Now relable the variable pad ports # set n 0 foreach p $L { set i [lindex $p 1] set E [SpreadSheet::get $w $i] if {[regexp {^([A-Za-z]+)([0-9]+)$} [lindex $E 1] X B pnum]} { set E [lreplace $E 1 1 $B$n] incr n } SpreadSheet::put $w $i $E } } ############################################################################# # # Respond to a press of the "Edit" button # proc editSelected {w} { set items [SpreadSheet::getselection $w] if { [llength $items] < 1 } { return } set r [lindex $items 0] set r [SpreadSheet::getPhysicalRow $w $r] SpreadSheet::entrySelect $w $r 0 } ############################################################################# # # Generate a new port entry # proc newPortEntry {} { variable iolb_w variable edcap_side global edgat_wops edgatio_w edport_basePort global edport_sig edport_port edport_type edport_bits edport_ok set Q -1 set E "" set N [SpreadSheet::size $iolb_w] for {set i 0} { $i < $N } {incr i} { set item [SpreadSheet::get $iolb_w $i] set P [lindex $item 1] if {[regexp {^([A-Za-z]+)([0-9]+)$} $P X B Nbits]} { if { $Nbits > $Q} { set edport_idx [expr $i + 1] set Q $Nbits set E $item } } } if { $Q < 0 } { errmsg [m err.badportadd] return } incr Q set portName [string trimright [lindex $E 1] 0123456789]$Q set item [list "*autoname*" $portName [lindex $E 2] [lindex $E 3]] if { $edcap_side } { lappend item [lindex $E 4] } return $item } ############################################################################# # # Entry manager for the port editor # proc manager {cmd args} { variable edcap_sig variable edcap_port variable edcap_type variable edcap_size variable edcap_side variable edcap_add variable iolb_w global edgat_wops global edgat_oldentry global edgat_portOpCount if { [lindex $args 0] == "-args" } { set args [lindex $args 1] } switch $cmd { canenter { # check to see if we can enter data set c [lindex $args 2] switch $c { 0 { return $edcap_sig } 1 { return $edcap_port } 2 { return $edcap_type } 3 { return $edcap_size } 4 { return $edcap_side } } return 0 } entrywidget { # use a special widget for some cells (return 0 for normal entry) set w [lindex $args 0] set r [lindex $args 1] set c [lindex $args 2] set W [lindex $args 3] set width [lindex $args 4] set variable [lindex $args 5] set edgat_oldentry [SpreadSheet::get $iolb_w [SpreadSheet::getEffectiveRow $iolb_w $r]] switch $c { 0 { return 0 } 1 { return 0 } 2 { Dropbox::new $W -variable $variable -width [expr $width - 3] -bd 1 -highlightthickness 0 SpreadSheet::tabBindings $W.e $w $r $c Dropbox::itemadd $W "in" Dropbox::itemadd $W "out" Dropbox::itemadd $W "inout" update focus $W.e return 1 } 3 { bitsizeselector $W -variable $variable -width [expr $width - 3] # Dropbox::new $W -variable $variable -width [expr $width - 3] -bd 1 -highlightthickness 0 SpreadSheet::tabBindings $W.e $w $r $c # for { set i 1 } { $i <= 32 } { incr i } { # Dropbox::itemadd $W $i # } update focus $W.e return 1 } 4 { Dropbox::new $W -variable $variable -width [expr $width - 3] -bd 1 -highlightthickness 0 SpreadSheet::tabBindings $W.e $w $r $c Dropbox::itemadd $W "left" Dropbox::itemadd $W "right" Dropbox::itemadd $W "top" Dropbox::itemadd $W "bottom" update focus $W.e return 1 } } return 0 } delete { # respond to the delete key deletePort $iolb_w } closenotify { incr edgat_portOpCount } close { set r [SpreadSheet::getEffectiveRow $iolb_w [lindex $args 1]] set c [lindex $args 2] set data [lindex $args 3] if { [lindex $edgat_oldentry $c] != $data } { set wop [concat [list edit [lindex $edgat_oldentry 1]] [lreplace $edgat_oldentry $c $c $data]] lappend edgat_wops $wop } return $data } canappend { return $edcap_add } initentry { set w [lindex $args 0] set r [lindex $args 1] set new_ent [newPortEntry] set base_name [string trimright [lindex $new_ent 1] 0123456789] lappend edgat_wops [list add $base_name] return $new_ent } } } proc seeDestroy args { variable iolb_w global edgat_wires set N [SpreadSheet::size $iolb_w] set edgat_wires {} for { set i 0 } { $i < $N } { incr i } { lappend edgat_wires [SpreadSheet::get $iolb_w $i] } } ############################################################################# # # Create the port manager window. # proc create {w args} { variable io_w variable iolb_w variable edcap_sig variable edcap_port variable edcap_type variable edcap_size variable edcap_add variable edcap_side global edgat_wires set edcap_sig 0 set edcap_port 0 set edcap_type 0 set edcap_size 0 set edcap_add 0 set edcap_side 0 parseargs $args {-editcaps} foreach cap $editcaps { set edcap_$cap 1 } set io_w $w.io set iolb_w $w.io.ports.lb frame $w.io frame $w.io.but button $w.io.but.edit -text [m db.gate.edit] -command "PortMgr::editSelected $iolb_w" button $w.io.but.add -text [m db.gate.add] -command "PortMgr::addNew $iolb_w" button $w.io.but.delete -text [m db.gate.delete] -command "PortMgr::deletePort $iolb_w" pack $w.io.but.edit $w.io.but.add $w.io.but.delete -padx 5 -pady 5 -side left pack $w.io.but -side bottom -anchor e if { !$edcap_add } { $w.io.but.add configure -state disabled $w.io.but.delete configure -state disabled } pack $w.io -expand 1 -fill both frame $w.io.ports SpreadSheet::create $w.io.ports.lb -height 10 -bd 1 -relief sunken -yscrollcommand "$w.io.ports.vb set" -entrycommand PortMgr::manager -expandcol 1 SpreadSheet::addcolumn $iolb_w -width 13 -header [m db.gate.signam] SpreadSheet::addcolumn $iolb_w -width 8 -header [m db.gate.port] SpreadSheet::addcolumn $iolb_w -width 6 -header [m db.gate.iotype] SpreadSheet::addcolumn $iolb_w -width 6 -header [m db.gate.bitws] if { $edcap_side } { SpreadSheet::addcolumn $iolb_w -width 6 -header [m db.gate.side] } scrollbar $w.io.ports.vb -orient vertical -command "SpreadSheet::yview $iolb_w" pack $w.io.ports.lb -fill both -side left -expand 1 pack $w.io.ports.vb -fill both -side left pack $w.io.ports -padx 10 -pady 10 -fill x -expand 1 foreach n $edgat_wires { PortMgr::add end $n } # updateWhenIdle bind $w.io.ports.lb PortMgr::seeDestroy } } namespace eval EditGate { variable clock_line_len 320.0 variable tap_size variable wire_size variable tap_lsbMax ################################################# # # Select interval and total width from an omega value. # # P Power of ten >= to omega # Q Normalized omega value # V Size of interval # proc chooseW {omega} { set omega [expr 1.2*$omega ] if { $omega < 10 } {set omega 10 } for {set P 1.0} {$P < $omega} {set P [expr $P * 10.0]} {} set Q [expr ($P - $omega)/$P ] if { $Q >= 0.8 } { set V $P*0.02 } elseif { $Q >= 0.6 } { set V $P*0.05 } else { set V $P*0.1 } set W 0 for {set I 0} { $W <= $omega } { incr I } { set W [expr int($I * $V) ] } set W [expr int($I * $V) ] return [list $I $W] } ############################################################################# # # Create the frame for the clock diagram. # proc clockFrame {w} { global ecpI ecpW variable clock_line_len $w.wave delete frame set clkFrame [list] for {set i 0} {$i <= $ecpI } {incr i} { set x [expr 15 + ($i)*$clock_line_len/$ecpI ] $w.wave create line ${x} 75 ${x} 85 -tag frame $w.wave create text ${x} 100 -text [expr $i*$ecpW/$ecpI ] -anchor s -tag frame } } ######################################## # # Update clock display from value change # proc setClockTrace {w} { global ecpl1 ecpl2 ecpl3 ecpl4 ecpl5 global ecpE0 ecpE1 ecpE2 $w.wave coords $ecpl1 $ecpE0 5 $ecpE0 75 $w.wave coords $ecpl2 15 65 $ecpE1 65 $w.wave coords $ecpl3 $ecpE1 65 $ecpE1 15 $w.wave coords $ecpl4 $ecpE1 15 $ecpE2 15 $w.wave coords $ecpl5 $ecpE2 15 $ecpE2 65 } ######################################## # # Translate movement of a clock graph component to actual new positons # and new parameter values. # # proc moveClock {w x} { global ecpS ecpE0 ecpE1 ecpE2 global ecpl1 ecpl2 ecpl3 ecpl4 ecpl5 global ecpPhi ecpDuty ecpOmega ecpW variable clock_line_len trace vdelete ecpOmega w EditGate::clockPUpdate trace vdelete ecpPhi w EditGate::clockPUpdate trace vdelete ecpDuty w EditGate::clockPUpdate if { $ecpS == $ecpl1 } { set ecpE0 $x if { $ecpE0 < 15 } { set ecpE0 15 } if { $ecpE0 >= $ecpE2 } { set ecpE0 $ecpE2 } set ecpPhi [expr int(100*($ecpE0 - 15)/($ecpE2 - 15)) ] } elseif { $ecpS == $ecpl3 } { set ecpE1 $x if { $ecpE1 <= 15 } { set ecpE1 15 } if { $ecpE1 >= $ecpE2 } { set ecpE1 [expr $ecpE2 - 1] } set ecpDuty [expr int(100*($ecpE1 - 15)/($ecpE2 - 15)) ] } elseif { $ecpS == $ecpl5 } { set ecpE2 $x if { $ecpE2 <= $ecpE1 } { set ecpE2 [expr $ecpE1 + 1] } if { $ecpE2 <= $ecpE0 } { set ecpE2 [expr $ecpE0 + 1] } if { $ecpE2 >= [expr $clock_line_len + 15] } { set ecpE2 [expr $clock_line_len + 15] } set ecpE0 [expr 15 + int($ecpPhi*($ecpE2-15.0)/100.0)] set ecpE1 [expr 15 + int($ecpDuty*($ecpE2-15.0)/100.0)] set ecpOmega [expr int($ecpW*($ecpE2 - 15)/$clock_line_len) ] } trace variable ecpOmega w EditGate::clockPUpdate trace variable ecpPhi w EditGate::clockPUpdate trace variable ecpDuty w EditGate::clockPUpdate setClockTrace $w } ######################################## # # Translate change in parameter values to change in graph # proc clockPUpdate args { global ecpl1 ecpl2 ecpl3 ecpl4 ecpl5 global ecpE0 ecpE1 ecpE2 global ecpW ecpI ecpOmega ecpPhi ecpDuty global edgatclk_w variable clock_line_len catch { if { [scan $ecpPhi "%d" P] != 1 } { set P 0 } if { [scan $ecpDuty "%d" D] != 1 } { set D 50 } if { [scan $ecpOmega "%d" O] != 1 } { set O $ecpW } set IW [chooseW $ecpOmega] set ecpI [lindex $IW 0] set ecpW [lindex $IW 1] if { $P <= 0 } { set P 0 } if { $P >= 99 } { set P 99 } if { $D <= 0 } { set D 1 } if { $D >= 99 } { set D 99 } if { $O <= 0 } { set O 1 } set X [expr $clock_line_len*$O/$ecpW ] set ecpE2 [expr 15 + $X ] set ecpE0 [expr 15 + $X*$P/100 ] set ecpE1 [expr 15 + $X*$D/100 ] clockFrame $edgatclk_w setClockTrace $edgatclk_w } } ######################################## # # Clock parameter edit window # proc tabClockParms {w omega phi duty} { global ecpS ecpl1 ecpl2 ecpl3 ecpl4 ecpl5 global ecpE0 ecpE1 ecpE2 global ecpW ecpI ecpOmega ecpPhi ecpDuty global edgatclk_w variable clock_line_len set edgatclk_w $w set IW [chooseW $omega] set ecpI [lindex $IW 0] set ecpW [lindex $IW 1] set ecpOmega $omega set ecpPhi $phi set ecpDuty $duty frame $edgatclk_w.cycle label $edgatclk_w.cycle.lab -text "[m db.gate.cyclew]: " -anchor e -width 18 incdecEntry $edgatclk_w.cycle.ent -width 6 -variable ecpOmega -format %d pack $edgatclk_w.cycle.lab $edgatclk_w.cycle.ent -side left -pady 2 frame $edgatclk_w.phase label $edgatclk_w.phase.lab -text "[m db.gate.phase](%): " -anchor e -width 18 incdecEntry $edgatclk_w.phase.ent -width 6 -variable ecpPhi -format %d pack $edgatclk_w.phase.lab $edgatclk_w.phase.ent -side left -pady 2 frame $edgatclk_w.duty label $edgatclk_w.duty.lab -text "[m db.gate.duty](%): " -anchor e -width 18 incdecEntry $edgatclk_w.duty.ent -width 6 -variable ecpDuty -format %d pack $edgatclk_w.duty.lab $edgatclk_w.duty.ent -side left -pady 2 bind $edgatclk_w.cycle.ent "EditGate::ok" bind $edgatclk_w.phase.ent "EditGate::ok" bind $edgatclk_w.duty.ent "EditGate::ok" canvas $edgatclk_w.wave -width [expr $clock_line_len + 30] -height 110 -closeenough 5.0 -bg white -bd 2 -relief sunken $edgatclk_w.wave create line 15 75 [expr $clock_line_len + 15] 75 clockFrame $w set ecpl1 [$edgatclk_w.wave create line 0 0 0 0 -tags edge ] set ecpl2 [$edgatclk_w.wave create line 0 0 0 0 ] set ecpl3 [$edgatclk_w.wave create line 0 0 0 0 -tags edge ] set ecpl4 [$edgatclk_w.wave create line 0 0 0 0 ] set ecpl5 [$edgatclk_w.wave create line 0 0 0 0 -tags edge ] clockPUpdate $edgatclk_w.wave bind edge { set ecpS [$edgatclk_w.wave find withtag current] } $edgatclk_w.wave bind edge "EditGate::moveClock $w %x" $edgatclk_w.wave bind edge "EditGate::clockPUpdate" label $edgatclk_w.l -text [m db.gate.waveform] pack $edgatclk_w.l -anchor w pack $edgatclk_w.wave pack $edgatclk_w.cycle $edgatclk_w.phase $edgatclk_w.duty -anchor w pack $edgatclk_w -fill both -padx 5 -pady 20 helpon $edgatclk_w.cycle.lab [m ho.edgat.cycle] helpon $edgatclk_w.phase.lab [m ho.edgat.phase] helpon $edgatclk_w.duty.lab [m ho.edgat.duty] } ############################################################################# # # Gate delay properties # proc tabDelay {w} { global edgat_delays edgat_dtype edgat_techList edgat_tech edgat_techdelay frame $w.delay set wd $w.delay frame $wd.pad pack $wd.pad -pady 3 frame $wd.tech_label radiobutton $wd.tech_label.b -text [m db.gate.stddelay] -variable edgat_dtype -value tech -command "EditGate::dvalSetState $wd" # eval "tk_optionMenu $wd.tech_label.opt edgat_tech $edgat_techList" Dropbox::new $wd.tech_label.opt -variable edgat_tech -width 10 foreach item $edgat_techList { Dropbox::itemadd $wd.tech_label.opt $item } pack $wd.tech_label.b -side left pack $wd.tech_label.opt -side left -padx 3 # radiobutton $wd.tech_label -text [m db.gate.stddelay] -variable edgat_dtype -value tech -command "EditGate::dvalSetState $wd" windowframe $wd.tech $wd.tech_label -bd 2 -relief groove -dy -3 # radioframe $wd.tech [m db.gate.stddelay] -bd 2 -relief groove -variable edgat_dtype -value tech -command "EditGate::dvalSetState $wd" # radiobutton $wd.tech.b -text [m db.gate.stddelay] -variable edgat_dtype -value tech -command "EditGate::dvalSetState $wd" # eval "tk_optionMenu $wd.tech.opt edgat_tech $edgat_techList" frame $wd.tech.pad pack $wd.tech.pad -pady 5 set idx 0 set r 0 set c 0 frame $wd.tech.dtab set dtw $wd.tech.dtab foreach d $edgat_delays { label $dtw.l${r}_$c -text "$d:" label $dtw.e${r}_$c -textvariable edgat_techdelay($d) -width 4 -justify left grid $dtw.l${r}_$c -row $r -column [expr 3*$c] -padx 2 -pady 3 -sticky e grid $dtw.e${r}_$c -row $r -column [expr 3*$c+1] -padx 2 -pady 3 -sticky w incr idx incr c if { $c == 3 } { set c 0 incr r } } grid columnconfigure $wd.tech.dtab 2 -minsize 20 grid columnconfigure $wd.tech.dtab 5 -minsize 20 pack $wd.tech.dtab -padx 5 -pady 5 -side bottom # pack $wd.tech.opt -padx 5 -pady 5 -anchor w -side left radioframe $wd.cust [m db.gate.custdelay] -bd 2 -relief groove -variable edgat_dtype -value cust -command "EditGate::dvalSetState $wd" # radiobutton $wd.cust.b -text [m db.gate.custdelay] -variable edgat_dtype -value cust -command "EditGate::dvalSetState $wd" frame $wd.cust.pad pack $wd.cust.pad -pady 5 set r 0 set c 0 frame $wd.cust.dtab set dtw $wd.cust.dtab foreach d $edgat_delays { label $dtw.l${r}_$c -text "$d:" entry $dtw.e${r}_$c -width 4 -textvariable edgat_delayvalue($d) -bg white grid $dtw.l${r}_$c -row $r -column [expr 3*$c] -padx 2 -pady 3 -sticky e grid $dtw.e${r}_$c -row $r -column [expr 3*$c+1] -padx 2 -pady 3 incr c if { $c == 3 } { set c 0 incr r } } grid columnconfigure $wd.cust.dtab 2 -minsize 20 grid columnconfigure $wd.cust.dtab 5 -minsize 20 pack $wd.cust.dtab -padx 5 -pady 5 frame $wd.pad2 pack $wd.tech $wd.pad2 $wd.cust -padx 5 -pady 3 -fill both pack $wd -padx 5 -pady 20 -fill both dvalSetState $wd gat_setGateTechDelays $edgat_tech helpon $wd.tech_label [m ho.techbut] helpon $wd.cust_label [m ho.custbut] } ############################################################################# # # Gate properties for general properties shared by all gate types. # proc tabBasic {w args} { global edgat_type edgat_name edgat_hideName edgat_blockFunc if { [lindex $args 0] == "-raised" } { frame $w.basic -bd 1 -relief raised } else { frame $w.basic } pack $w.basic frame $w.basic.props set wb $w.basic.props label $wb.type_l -text "[m db.gate.gtype]:" -anchor e label $wb.type_e -text "$edgat_type" -width 12 -anchor w grid $wb.type_l -row 0 -column 0 -sticky e -padx 5 -pady 3 grid $wb.type_e -row 0 -column 1 -sticky w -padx 5 -pady 3 label $wb.name_l -text "[m db.gate.gname]:" -anchor e entry $wb.name_e -width 15 -textvariable edgat_name -bg white grid $wb.name_l -row 1 -column 0 -sticky e -padx 5 -pady 3 grid $wb.name_e -row 1 -column 1 -sticky w -padx 5 -pady 3 if { $edgat_type != "COMMENT" && $edgat_type != "FRAME" && $edgat_type != "SCRIPT" } { label $wb.hide_l -text "[m db.gate.hidenam]:" -anchor e checkbutton $wb.hide_e -variable edgat_hideName grid $wb.hide_l -row 2 -column 0 -sticky e -padx 5 -pady 3 grid $wb.hide_e -row 2 -column 1 -sticky w -padx 5 -pady 3 helpon $wb.hide_l [m ho.edgat.hide] } label $wb.anchor_l -text "[m db.gate.anchor]:" -anchor e frame $wb.anchor_f grid $wb.anchor_l -row 3 -column 0 -sticky e -padx 5 -pady 3 grid $wb.anchor_f -row 3 -column 1 -sticky w -pady 3 checkbutton $wb.anchor_f.ent -variable edgat_anchor label $wb.anchor_f.xlab -text "X:" entry $wb.anchor_f.xent -width 4 -textvariable edgat_xpos -bg white label $wb.anchor_f.ylab -text "Y:" entry $wb.anchor_f.yent -width 4 -textvariable edgat_ypos -bg white pack $wb.anchor_f.ent $wb.anchor_f.xlab $wb.anchor_f.xent $wb.anchor_f.ylab $wb.anchor_f.yent -padx 5 -pady 3 -side left if { $edgat_type != "Module" } { label $wb.cpbreak_l -text "[m db.gate.cpbreak]:" -anchor e checkbutton $wb.cpbreak_e -variable edgat_cpbreak grid $wb.cpbreak_l -row 4 -column 0 -sticky e -padx 5 -pady 3 grid $wb.cpbreak_e -row 4 -column 1 -sticky w -padx 5 -pady 3 } # checkbutton $w. bind $wb.name_e "EditGate::ok" if { [lindex $args 0] == "-raised" } { pack $wb -fill both } else { pack $wb -padx 5 -pady 20 } helpon $wb.type_l [m ho.edgat.gtype] helpon $wb.name_l [m ho.edgat.gname] helpon $wb.anchor_l [m ho.edgat.ganchor] helpon $wb.anchor_f.xlab [m ho.edgat.gx] helpon $wb.anchor_f.ylab [m ho.edgat.gy] } proc dvalSetState {w} { global edgat_delays edgat_dtype catch { if { $edgat_dtype == "tech" } { set state "disabled" } else { set state "normal" } set r 0 set c 0 set tdtw $w.tech.dtab set dtw $w.cust.dtab foreach d $edgat_delays { $dtw.e${r}_$c configure -state $state if { $state == "normal" } { $dtw.e${r}_$c configure -foreground black $dtw.l${r}_$c configure -foreground black $tdtw.e${r}_$c configure -foreground dimgray $tdtw.l${r}_$c configure -foreground dimgray } else { $dtw.e${r}_$c configure -foreground dimgray $dtw.l${r}_$c configure -foreground dimgray $tdtw.e${r}_$c configure -foreground black $tdtw.l${r}_$c configure -foreground black } incr c if { $c == 3 } { set c 0 incr r } } } } # # Pin placement properties of mux and demux. # proc tabMux {w} { global edgat_type switch $edgat_type { MUX { set prefix db.gate.mux set ord1 [gifI muxord1.gif] set ord2 [gifI muxord2.gif] set sel1 [gifI muxsel1.gif] set sel2 [gifI muxsel2.gif] set uord1 [gifI Umuxord1.gif] set uord2 [gifI Umuxord2.gif] set usel1 [gifI Umuxsel1.gif] set usel2 [gifI Umuxsel2.gif] } DECODER { set prefix db.gate.decoder set ord1 [gifI demuxord1.gif] set ord2 [gifI demuxord2.gif] set sel1 [gifI demuxsel1.gif] set sel2 [gifI demuxsel2.gif] set uord1 [gifI Udemuxord1.gif] set uord2 [gifI Udemuxord2.gif] set usel1 [gifI Udemuxsel1.gif] set usel2 [gifI Udemuxsel2.gif] } DEMUX { set prefix db.gate.demux set ord1 [gifI demuxord1.gif] set ord2 [gifI demuxord2.gif] set sel1 [gifI demuxsel1.gif] set sel2 [gifI demuxsel2.gif] set uord1 [gifI Udemuxord1.gif] set uord2 [gifI Udemuxord2.gif] set usel1 [gifI Udemuxsel1.gif] set usel2 [gifI Udemuxsel2.gif] } } set wraplength 130 ############################################################################# labelframe $w.dataord [m $prefix.dataorder] imageRadioButton $w.dataord.ascend -onimage $ord1 -offimage $uord1 -wraplength $wraplength \ -variable edgat_dataOrder -value 0 -label [m $prefix.ord1.hdr] -description [m $prefix.ord1.exp] imageRadioButton $w.dataord.descend -onimage $ord2 -offimage $uord2 -wraplength $wraplength \ -variable edgat_dataOrder -value 1 -label [m $prefix.ord2.hdr] -description [m $prefix.ord2.exp] frame $w.dataord.toppad -height 10 frame $w.dataord.botpad -height 5 pack $w.dataord.toppad pack $w.dataord.botpad -side bottom pack $w.dataord.ascend $w.dataord.descend -padx 4 -side left ############################################################################# labelframe $w.selsty [m $prefix.select] imageRadioButton $w.selsty.onleft -onimage $sel1 -offimage $usel1 -wraplength $wraplength \ -variable edgat_selectSide -value 0 -label [m $prefix.sel1.hdr] -description [m $prefix.sel1.exp] imageRadioButton $w.selsty.onright -onimage $sel2 -offimage $usel2 -wraplength $wraplength \ -variable edgat_selectSide -value 1 -label [m $prefix.sel2.hdr] -description [m $prefix.sel2.exp] frame $w.selsty.toppad -height 10 frame $w.selsty.botpad -height 5 pack $w.selsty.toppad pack $w.selsty.botpad -side bottom pack $w.selsty.onleft $w.selsty.onright -padx 4 -side left ############################################################################# frame $w.pad -height 10 frame $w.pad2 -height 10 pack $w.pad pack $w.dataord -anchor w -fill both -padx 5 pack $w.pad2 pack $w.selsty -anchor w -fill both -padx 5 } ############################################################################# # # Gate property tab for flip-flop gates. # proc tabFF {w ff} { global edgat_ffmirror labelframe $w.fftype [m db.gate.$ff.type] set wraplength 130 imageRadioButton $w.fftype.normal -onimage [gifI $ff.gif] -offimage [gifI U$ff.gif] -wraplength $wraplength \ -variable edgat_ffmirror -value 0 -label [m db.gate.$ff.normal.hdr] -description [m db.gate.$ff.normal.exp] imageRadioButton $w.fftype.reverse -onimage [gifI r$ff.gif] -offimage [gifI Ur$ff.gif] -wraplength $wraplength \ -variable edgat_ffmirror -value 1 -label [m db.gate.$ff.reverse.hdr] -description [m db.gate.$ff.reverse.exp] frame $w.fftype.toppad -height 10 frame $w.fftype.botpad -height 5 pack $w.fftype.toppad pack $w.fftype.botpad -side bottom pack $w.fftype.normal $w.fftype.reverse -padx 4 -side left pack $w.fftype -fill both -padx 5 -pady 20 } ############################################################################# # # Gate property tab for concat gates. # proc tabConcatPlace {w} { labelframe $w.catdir [m db.gate.catdiruse] set wraplength 130 # # The "ascending" button # imageRadioButton $w.catdir.ascend -onimage [gifI cat_asc.gif] -offimage [gifI Ucat_asc.gif] -wraplength $wraplength \ -variable edgat_catdir -value 1 -label [m db.gate.cat.asc.hdr] -description [m db.gate.cat.asc.exp] # # The "descending" button # imageRadioButton $w.catdir.descend -onimage [gifI cat_dec.gif] -offimage [gifI Ucat_dec.gif] -wraplength $wraplength \ -variable edgat_catdir -value 0 -label [m db.gate.cat.dec.hdr] -description [m db.gate.cat.dec.exp] # # Button layout # grid $w.catdir.ascend -row 0 -column 0 -padx 3 -pady 8 -sticky nw grid $w.catdir.descend -row 0 -column 1 -padx 3 -pady 8 -sticky nw ############################################################################# labelframe $w.sigdir [m db.gate.cat.sigdir] frame $w.sigdir.toppad -height 5 frame $w.sigdir.botpad -height 5 # # The "auto" button # imageRadioButton $w.sigdir.auto -onimage [gifI cat_auto.gif] -offimage [gifI Ucat_auto.gif] -wraplength $wraplength \ -variable edgat_sigdir -value 2 -label [m db.gate.cat.auto.hdr] -description [m db.gate.cat.auto.exp] # # The "Multi-Input" button # imageRadioButton $w.sigdir.multin -onimage [gifI cat_multin.gif] -offimage [gifI Ucat_multin.gif] -wraplength $wraplength \ -variable edgat_sigdir -value 1 -label [m db.gate.cat.multin.hdr] -description [m db.gate.cat.multin.exp] # # The "Single-Input" button # imageRadioButton $w.sigdir.singin -onimage [gifI cat_singin.gif] -offimage [gifI Ucat_singin.gif] -wraplength $wraplength \ -variable edgat_sigdir -value 0 -label [m db.gate.cat.singin.hdr] -description [m db.gate.cat.singin.exp] # # The "tran" button # imageRadioButton $w.sigdir.tran -onimage [gifI cat_tran.gif] -offimage [gifI Ucat_tran.gif] -wraplength $wraplength \ -variable edgat_sigdir -value 3 -label [m db.gate.cat.tran.hdr] -description [m db.gate.cat.tran.exp] grid $w.sigdir.toppad -row 0 grid $w.sigdir.auto -row 1 -column 0 -padx 3 -pady 3 -sticky nw grid $w.sigdir.multin -row 1 -column 1 -padx 3 -pady 3 -sticky nw grid $w.sigdir.tran -row 2 -column 0 -padx 3 -pady 3 -sticky nw grid $w.sigdir.singin -row 2 -column 1 -padx 3 -pady 3 -sticky nw grid $w.sigdir.botpad -row 3 ############################################################################# frame $w.pad -height 10 frame $w.pad2 -height 10 pack $w.pad pack $w.catdir -anchor w -fill both -padx 5 pack $w.pad2 pack $w.sigdir -anchor w -fill both -padx 5 } ############################################################################# # # Gate property tab for gates that can have extender bars. # proc tabCrunchExtGate {w} { global edgat_extbar frame $w.pad -height 10 pack $w.pad set wraplength 130 ############################################################################# labelframe $w.extbar [m db.gate.aox.extbaruse] imageRadioButton $w.extbar.use -onimage [gifI extbarand.gif] -offimage [gifI Uextbarand.gif] -wraplength $wraplength \ -variable edgat_extbar -value 1 -label [m db.gate.aox.use.hdr] -description [m db.gate.aox.use.exp] imageRadioButton $w.extbar.nouse -onimage [gifI crunchand.gif] -offimage [gifI Ucrunchand.gif] -wraplength $wraplength \ -variable edgat_extbar -value 0 -label [m db.gate.aox.nouse.hdr] -description [m db.gate.aox.nouse.exp] frame $w.extbar.toppad -height 10 frame $w.extbar.botpad -height 10 pack $w.extbar.toppad pack $w.extbar.botpad -side bottom pack $w.extbar.use $w.extbar.nouse -padx 4 -side left ############################################################################# pack $w.extbar -anchor w -fill both -padx 5 # helpon $w.extbar.use.b [m ho.edgat.extbar] # helpon $w.extbar.nouse.b [m ho.edgat.extbar] # helpon $w.extbar.use.i [m ho.edgat.extbar] # helpon $w.extbar.nouse.i [m ho.edgat.extbar] } ############################################################################# # # Gate property tab for setting Switch properties. # proc tabSwitch {w} { global edgat_switch set wraplength 130 labelframe $w.state [m db.gate.switch.state] packPad $w.state imageRadioButton $w.state.on -onimage [gifI onswitch.gif] -offimage [gifI Uonswitch.gif] \ -wraplength $wraplength -variable edgat_switch -value 1 \ -label [m db.gate.switch.state.on.hdr] -description [m db.gate.switch.state.on.exp] imageRadioButton $w.state.off -onimage [gifI offswitch.gif] -offimage [gifI Uoffswitch.gif] \ -wraplength $wraplength -variable edgat_switch -value 0 \ -label [m db.gate.switch.state.off.hdr] -description [m db.gate.switch.state.off.exp] pack $w.state.on $w.state.off -padx 4 -pady 5 -side left labelframe $w.shownet [m db.gate.switch.shownet] packPad $w.shownet imageRadioButton $w.shownet.on -onimage [gifI wsswitch.gif] -offimage [gifI Uwsswitch.gif] \ -wraplength $wraplength -variable edgat_shownet -value 1 \ -label [m db.gate.switch.shownet.on.hdr] -description [m db.gate.switch.shownet.on.exp] imageRadioButton $w.shownet.off -onimage [gifI nwsswitch.gif] -offimage [gifI Unwsswitch.gif] \ -wraplength $wraplength -variable edgat_shownet -value 0 \ -label [m db.gate.switch.shownet.off.hdr] -description [m db.gate.switch.shownet.off.exp] pack $w.shownet.on $w.shownet.off -padx 4 -pady 5 -side left -anchor n packPad $w pack $w.state -fill both -padx 5 -pady 5 pack $w.shownet -fill both -padx 5 -pady 5 # helpon $w.switch.state [m ho.edgat.swstate] } proc dipValChange {w args} { global edgat_dip set n $edgat_dip if { $n == ""} { set n "0" } $w.dip.c itemconfigure value -text $n } ############################################################################# # # Gate property tab for setting wire tab properties. # proc tabDip {w} { global edgat_dip # # State Property # labelframe $w.state [m db.gate.dip.value] packPad $w.state canvas $w.state.c -width 150 -height 70 -bg white -bd 1 -relief sunken $w.state.c create image 100 35 -image [gifI setdip.gif] $w.state.c create text 100 18 -text $edgat_dip -font dipFont -fill blue -tags value set wrap [rescale [m @db.gate.dip.value.exp.width]] label $w.state.e -text [m db.gate.dip.value.exp] -justify left -wraplength $wrap -font dialogExpFont label $w.state.l -text [m db.gate.dip.value.hex] incdecEntry $w.state.ent -width 12 -variable edgat_dip -format %x -validatecommand hexValidate pack $w.state.e -side left -fill both -padx 5 pack $w.state.c -padx 5 -pady 5 -side bottom -fill x pack $w.state.ent -padx 5 -pady 5 -side right -anchor w pack $w.state.l -side right -anchor w trace variable ::edgat_dip w "EditGate::dipValChange $w" bind $w.state "trace vdelete ::edgat_dip w \"EditGate::dipValChange $w\"" # # Show Net Property # set wraplength 130 labelframe $w.shownet [m db.gate.dip.shownet] packPad $w.shownet imageRadioButton $w.shownet.on -onimage [gifI wsdip.gif] -offimage [gifI Uwsdip.gif] \ -wraplength $wraplength -variable edgat_shownet -value 1 \ -label [m db.gate.dip.shownet.on.hdr] -description [m db.gate.dip.shownet.on.exp] imageRadioButton $w.shownet.off -onimage [gifI nwsdip.gif] -offimage [gifI Unwsdip.gif] \ -wraplength $wraplength -variable edgat_shownet -value 0 \ -label [m db.gate.dip.shownet.off.hdr] -description [m db.gate.dip.shownet.off.exp] pack $w.shownet.on $w.shownet.off -padx 4 -pady 5 -side left -anchor n # # Final layout # packPad $w pack $w.state -fill both -padx 5 -pady 5 pack $w.shownet -fill both -padx 5 -pady 5 # frame $w.dip # label $w.dip.label -text "[m db.gate.dipval]:" # entry $w.dip.state -textvariable edgat_dip -bg white # pack $w.dip.label $w.dip.state -padx 5 -pady 5 -side left -anchor w # bind $w.dip.state "EditGate::ok" # helpon $w.dip.label [m ho.edgat.dipstate] } proc tabTapUpdateRange {w args} { global edgat_tap $w.tap.c itemconfig range -text $edgat_tap } proc tabTapBuild {w args} { global edgat_tap edgatTap_lsb global tkg_wireColor tkg_busColor tkg_instColor variable tap_size variable wire_size variable tap_lsbMax set n [SpreadSheet::size $PortMgr::iolb_w] for { set i 0} {$i < $n} {incr i} { set row [SpreadSheet::get $PortMgr::iolb_w $i] set name [lindex $row 1] set bits [lindex $row 3] if { $name == "Z" } { set tap_size $bits } if { $name == "D" } { set wire_size $bits } } # # The wire sizing is currently illegal, so just treat # tap as the same size as the wire. # if { $tap_size > $wire_size} { set tap_size $wire_size } # # Maximum value for LSB # set tap_lsbMax [expr $wire_size-$tap_size] # # Fix LSB if it is out of range # if {$edgatTap_lsb > $tap_lsbMax} { set edgatTap_lsb $tap_lsbMax } incdecEntry_configure $w.tap.lsb -max $tap_lsbMax $w.tap.c delete all # # wire tap position # set width [$w.tap.c cget -width] set height [$w.tap.c cget -height] set x 20 set y [expr $height/2] set tap_len [expr $width - 25] set wire_len [expr $height/2 -5] set x1 [expr $x + $tap_len] set y1 [expr $y - $wire_len] set y2 [expr $y + $wire_len] if { $tap_size > 1 } { $w.tap.c create line $x $y $x1 $y -width 2 -fill $tkg_busColor set x3 [expr $x + $tap_len - 15] $w.tap.c create line [expr $x3-4] [expr $y+4] [expr $x3+4] [expr $y-4] -fill red $w.tap.c create text $x3 [expr $y-8] -text $tap_size -fill red -anchor s $w.tap.exp configure -text [m db.gate.tap.exp.bus] $w.tap.l configure -text [m db.gate.tap.lbl.bus] } else { $w.tap.c create line $x $y $x1 $y -width 1 -fill $tkg_wireColor $w.tap.exp configure -text [m db.gate.tap.exp.bit] $w.tap.l configure -text [m db.gate.tap.lbl.bit] } if { $wire_size > 1 } { $w.tap.c create line $x $y1 $x $y2 -width 2 -fill $tkg_busColor set y3 [expr ($y+$y2)/2] $w.tap.c create line [expr $x-4] [expr $y3+4] [expr $x+4] [expr $y3-4] -fill red $w.tap.c create text [expr $x+8] $y3 -text $wire_size -fill red -anchor w } else { $w.tap.c create line $x $y1 $x $y2 -width 1 -fill $tkg_wireColor } $w.tap.c create polygon [expr $x+1] [expr $y -5] [expr $x + 5] $y [expr $x+1] [expr $y + 5] -fill $tkg_instColor $w.tap.c create text [expr $x+8] [expr $y-5] -text $edgat_tap -anchor sw -fill $tkg_instColor -tags range } proc tabTapUpdateLSB {w args} { global edgat_tap edgatTap_lsb variable tap_size variable wire_size variable tap_lsbMax # # Do range checking of lsb before we use it for bit-tap expression # set lsb $edgatTap_lsb # # Fix LSB if it is out of range # if {$lsb > $tap_lsbMax} { set lsb $tap_lsbMax } if {$lsb < 0} { set lsb 0 } if { $tap_size > 1 } { set edgat_tap [expr $lsb + $tap_size - 1]:$lsb } else { set edgat_tap $lsb } } ############################################################################# # # Gate property tab for setting wire tab properties. # proc tabTap {w} { global edgat_tap edgatTap_lsb variable tap_size variable wire_size set tap_size 0 set wire_size 0 labelframe $w.tap [m db.gate.tap.select] packPad $w.tap if { [scan $edgat_tap %*d:%d edgatTap_lsb] == 1} { } else { set edgatTap_lsb $edgat_tap } label $w.tap.exp -wraplength [mr @db.gate.tap.exp.width] -justify left label $w.tap.l incdecEntry $w.tap.lsb -width 5 -variable edgatTap_lsb -format %d -min 0 canvas $w.tap.c -width 100 -height 100 -bg white -bd 1 -relief sunken tabTapBuild $w pack $w.tap.c -padx 5 -pady 5 -side right pack $w.tap.exp -padx 5 -pady 5 -side top -anchor w pack $w.tap.l -padx 5 -pady 5 -side left -anchor w pack $w.tap.lsb -padx 5 -pady 5 -side left -anchor w pack $w.tap -fill both -padx 5 -pady 20 trace variable ::edgat_portOpCount w "EditGate::tabTapBuild $w" trace variable ::edgat_tap w "EditGate::tabTapUpdateRange $w" trace variable ::edgatTap_lsb w "EditGate::tabTapUpdateLSB $w" bind $w "trace vdelete ::edgat_portOpCount w \"EditGate::tabTapBuild $w\"" bind $w "+ trace vdelete ::edgat_tap w \"EditGate::tabTapUpdateRange $w\"" bind $w "+ trace vdelete ::edgatTap_lsb w \"EditGate::tabTapUpdateLSB $w\"" } ############################################################################# # # Gate property tab for setting Memory properties. # proc tabMem {w} { global edgat_memFile edgatmem_w set edgatmem_w $w.mem frame $w.mem label $w.mem.label -text "[m db.gate.memfilenam]:" entry $w.mem.file -textvariable edgat_memFile -bg white button $w.mem.browse -text [m b.browse] -command { global mem_filter mem_filetypes edgate_memFile edgatmem_w set file [tk_getOpenFile -defaultextension $mem_filter -filetypes $mem_filetypes -parent .edgat] if { $file != "" } { set edgat_memFile $file $edgatmem_w.file icursor end $edgatmem_w.file xview end } } pack $w.mem.label $w.mem.file $w.mem.browse -padx 5 -pady 5 -side left -anchor w pack $w.mem -fill both -padx 5 -pady 20 bind $w.mem.file "EditGate::ok" helpon $w.mem.label [m ho.edgat.memfile] } ############################################################################# # # User requested a new module on the edgat box # proc newModule {w} { global edgat_blockFunc BlockOp::new -parent .edgat if { $BlockOp::props(ok) == 1 } { Dropbox::flush $w.mod.funcF.name foreach m [BlockList::getallmodules -types {module part}] { Dropbox::itemadd $w.mod.funcF.name $m } set edgat_blockFunc $BlockOp::props(name) } } ############################################################################# # # Gate property tab for setting Module properties. # proc tabModule {w} { global edgat_newBlock edgat_blockFunc frame $w.mod label $w.mod.funcL -text "[m db.gate.modname]:" -width 12 -anchor e frame $w.mod.funcF tkg_moduleSelector $w.mod.funcF.name -width 20 -variable edgat_blockFunc -value $edgat_blockFunc -entry 0 -nomain 1 button $w.mod.funcF.new -text [m b.new]... -command "EditGate::newModule $w" pack $w.mod.funcF.name $w.mod.funcF.new -anchor w -side left -padx 5 pack $w.mod.funcL -padx 5 -pady 5 -side left pack $w.mod.funcF -pady 5 -side left focus $w.mod.funcF.name.e helpon $w.mod.funcL [m ho.edgat.func] pack $w.mod -fill both -padx 5 -pady 20 } ############################################################################# # # Gate property tab for setting Frame properties. # proc tabFrame {w} { global edgat_newBlock frame $w.frm label $w.frm.lab -text "[m b.label]:" -anchor e entry $w.frm.ent -width 30 -textvariable edgat_frameLabel -bg white bind $w.frm.ent "EditGate::ok" pack $w.frm.lab -padx 5 -pady 5 -side left pack $w.frm.ent -padx 5 -pady 5 -side left -fill both -expand 1 pack $w.frm -anchor w if { $edgat_newBlock } { # $w.frm.ent selection range 0 end focus $w.frm.ent } helpon $w.frm.lab [m ho.edgat.frame] pack $w.frm -fill both -padx 5 -pady 20 focus $w.frm.ent $w.frm.ent selection range 0 end $w.frm.ent icursor end } ############################################################################# # # Gate property tab for setting LED properties. # proc tabLED {w} { global edgat_newBlock set wraplength 130 labelframe $w.led [m db.gate.led.type] imageRadioButton $w.led.bit -onimage [gifI led_bit.gif] -offimage [gifI Uled_bit.gif] -wraplength $wraplength \ -variable edgat_ledType -value 0 -label [m db.gate.led.bit.hdr] -description [m db.gate.led.bit.exp] imageRadioButton $w.led.bar -onimage [gifI led_bar.gif] -offimage [gifI Uled_bar.gif] -wraplength $wraplength \ -variable edgat_ledType -value 1 -label [m db.gate.led.bar.hdr] -description [m db.gate.led.bar.exp] imageRadioButton $w.led.hex -onimage [gifI led_hex.gif] -offimage [gifI Uled_hex.gif] -wraplength $wraplength \ -variable edgat_ledType -value 2 -label [m db.gate.led.hex.hdr] -description [m db.gate.led.hex.exp] imageRadioButton $w.led.dec -onimage [gifI led_dec.gif] -offimage [gifI Uled_dec.gif] -wraplength $wraplength \ -variable edgat_ledType -value 3 -label [m db.gate.led.dec.hdr] -description [m db.gate.led.dec.exp] imageRadioButton $w.led.seg -onimage [gifI led_direct.gif] -offimage [gifI Uled_direct.gif] -wraplength $wraplength \ -variable edgat_ledType -value 4 -label [m db.gate.led.seg.hdr] -description [m db.gate.led.seg.exp] frame $w.led.pad1 -height 10 frame $w.led.pad2 -height 10 frame $w.led.pad3 -height 10 frame $w.led.pad4 -height 10 grid $w.led.pad1 -row 0 -column 0 grid $w.led.bit -row 1 -column 0 -sticky w grid $w.led.bar -row 1 -column 1 -sticky w grid $w.led.pad2 -row 2 -column 0 grid $w.led.hex -row 3 -column 0 -sticky w grid $w.led.dec -row 3 -column 1 -sticky w grid $w.led.pad3 -row 4 -column 0 grid $w.led.seg -row 5 -column 0 -sticky w grid $w.led.pad4 -row 6 -column 0 pack $w.led -fill both -padx 5 -pady 20 } ############################################################################# # # This procedure is called when the OK button is pressed # proc ok {} { global edgat_ok edgat_type edgat_blockFunc set edgat_ok 1 switch $edgat_type { COMMENT { # The saveComment will fail if the Text tab is not active, but that is ok # since in this case the edgat_commentLines() array will be up to date. # JPH 1/19/09 - The above statement may no longer be true due to the new # tabbox implementation. We may not need the "catch" anymore. catch { saveComment } } SCRIPT { # Reusing comment editing for script editing catch { saveComment } } MODULE { if { $edgat_blockFunc == "" } { errmsg [m err.nofunc] set edgat_ok 0 } } SYMMODULE { if { $edgat_blockFunc == "" } { errmsg [m err.nofunc] set edgat_ok 0 } } } destroy .edgat } ############################################################################# # # This procedure is called when the Cancel button is pressed # proc cancel {} { global edgat_ok set edgat_ok 0 destroy .edgat } proc saveScript {w} { global edgat_commentLen edgat_commentLines edgat_ok for { set i 1 } { [$w compare $i.end < end] } { incr i } { set x [$w get $i.0 $i.end] set j [expr $i - 1] set edgat_commentLines($j) $x } set edgat_commentLen [expr $i - 1] HdlEditor::dbHide } proc tabScriptText {w} { global edgat_commentLines edgat_commentLen global edgat_comment_w HdlEditor::new $w.script -width 1 -height 1 -keygroup hdledit pack $w.script -expand 1 -fill both HdlEditor::dbShow $w.script set tw $w.script.pane.main.t for {set i 0 } { $i < $edgat_commentLen } { incr i } { if { $i > 0 } { $tw insert end "\n" } $tw insert end $edgat_commentLines($i) } HdlEditor::recolorize 1.0 end frame $tw.destroyDetect bind $tw.destroyDetect "EditGate::saveScript $tw" } ############################################################################# # # Save contents of the comment text # proc saveComment {} { global edgat_commentLen edgat_commentLines edgat_ok global edgat_comment_w set w $edgat_comment_w for { set i 1 } { [$w.f.t compare $i.end < end] } { incr i } { set x [$w.f.t get $i.0 $i.end] set j [expr $i - 1] set edgat_commentLines($j) $x } set edgat_commentLen [expr $i - 1] } ############################################################################# # # Gate property tab for editing comment text. # proc tabCommentText {w} { global edgat_commentLines edgat_commentLen global edgat_comment_w frame $w.ctext set edgat_comment_w $w.ctext frame $w.ctext.f text $w.ctext.f.t -yscrollcommand "$w.ctext.f.vb set" -xscrollcommand "$w.ctext.f.hb set" -width 1 -height 1 -bg white # -width [m @db.gate.comment.width] -height [m @db.gate.comment.height] scrollbar $w.ctext.f.vb -command "$w.ctext.f.t yview" scrollbar $w.ctext.f.hb -command "$w.ctext.f.t xview" -orient horizontal grid rowconfig $w.ctext.f 0 -weight 1 -minsize 0 grid columnconfig $w.ctext.f 0 -weight 1 -minsize 0 grid $w.ctext.f.t -row 0 -column 0 -sticky news grid $w.ctext.f.vb -row 0 -column 1 -sticky news grid $w.ctext.f.hb -row 1 -column 0 -sticky news pack $w.ctext.f -ipadx 5 -ipady 5 -fill both -expand 1 -padx 5 -pady 5 for {set i 0 } { $i < $edgat_commentLen } { incr i } { if { $i > 0 } { $w.ctext.f.t insert end "\n" } $w.ctext.f.t insert end $edgat_commentLines($i) } # # This sub-window is created but not packed. It is used to detect a destroy of the # text window and get control before the text window is actually destroyed. # frame $w.ctext.f.t.destroyDetect bind $w.ctext.f.t.destroyDetect EditGate::saveComment pack $w.ctext -fill both -expand 1 focus $w.ctext.f.t } ############################################################################# # # Handle a tab selection in the edit gate dialog box # proc dotab {w tab} { global edgat_type edgat_name edgat_hideName edgat_geom global ecpOmega ecpPhi ecpDuty global editgate_caps frame $w frame $w.props pack $w.props -side right -fill both -expand 1 set gif general.gif set explaination [m db.gate.tab.${tab}.exp] set caption [m db.gate.tab.${tab}.cap] switch $tab { General { tabBasic $w.props set gif gateprops.gif } Ports { if { [catch { set caplist $editgate_caps($edgat_type)}]} { set caplist { sig size } } PortMgr::create $w.props -editcaps $caplist # edgatIO $w.props set gif port.gif } Delay { tabDelay $w.props set gif delay.gif } Parameters { ModParmMgr::create $w.props } CLOCK { tabClockParms $w.props $ecpOmega $ecpPhi $ecpDuty set gif details.gif } SWITCH { tabSwitch $w.props set gif details.gif } DIP { tabDip $w.props set gif details.gif } TAP { tabTap $w.props set gif details.gif } RAM { tabMem $w.props set gif details.gif } ROM { tabMem $w.props set gif details.gif } MODULE { tabModule $w.props set gif details.gif } FRAME { tabFrame $w.props set gif details.gif } LED { tabLED $w.props set gif details.gif } AND { tabCrunchExtGate $w.props set gif details.gif } OR { tabCrunchExtGate $w.props set gif details.gif } XOR { tabCrunchExtGate $w.props set gif details.gif } MUX { tabMux $w.props set gif details.gif } DEMUX { tabMux $w.props set gif details.gif } DECODER { tabMux $w.props set gif details.gif } FF { tabFF $w.props ff set gif details.gif } JKFF { tabFF $w.props jkff set gif details.gif } CONCAT { tabConcatPlace $w.props set gif details.gif } COMMENT { tabCommentText $w.props set gif details.gif } SCRIPT { tabScriptText $w.props set gif details.gif } } dialogImage $w.image -image [gifI $gif] -caption $caption -explaination $explaination pack $w.image -fill both -side left -pady 10 } ############################################################################# # # Post the gate parameters dialog box # proc post args { global edgat_type edgat_name edgat_hideName edgat_geom edgat_wops edgat_dtype global ecpOmega ecpPhi ecpDuty # puts "EditGate::post type=$edgat_type" set edgat_wops {} set start_page General if { $args != "" } { set start_page $args } set w .edgat if { [catch { toplevel $w }] } { return } wm withdraw $w wm title $w [m db.gate.title] wm geometry $w $edgat_geom wm transient $w . switch $edgat_type { COMMENT { set start_page COMMENT wm geometry $w [mr @db.gate.comment.width]x[mr @db.gate.comment.height] } SCRIPT { set start_page SCRIPT wm geometry $w [mr @db.gate.comment.width]x[mr @db.gate.comment.height] } FRAME { set start_page FRAME wm resizable $w 0 0 } default { wm resizable $w 0 0 } } set tabs { General } set labels [list [m db.gate.general]] if { $edgat_type != "FRAME" && $edgat_type != "COMMENT" && $edgat_type != "SCRIPT" } { lappend tabs Ports lappend labels [m db.gate.ports] } # # If this is a gate type that has a details tab, add the tab # if {[lsearch {CLOCK SWITCH DIP TAP RAM ROM MODULE FRAME LED AND OR XOR MUX DECODER DEMUX JKFF FF CONCAT} $edgat_type] >= 0 } { lappend tabs $edgat_type; lappend labels [m db.gate.details] } if { $edgat_type == "MODULE" || $edgat_type == "SYMMODULE" } { lappend tabs Parameters lappend labels [m db.gate.parameters] } # # Add special tab for comments # if { $edgat_type == "COMMENT" } { lappend tabs COMMENT lappend labels [m db.gate.text] } if { $edgat_type == "SCRIPT" } { lappend tabs SCRIPT lappend labels [m db.gate.text] } if { $edgat_dtype != "none" } { lappend tabs Delay lappend labels [m db.gate.delay] } TabBox::new $w.tbox -command EditGate::dotab -tabs $tabs -tablabels $labels -startpage $start_page -takefocus 1 pack $w.tbox -fill both -expand 1 okcancel $w.ok -okcommand EditGate::ok -cancelcommand EditGate::cancel pack $w.ok -fill both trace variable ecpOmega w EditGate::clockPUpdate trace variable ecpPhi w EditGate::clockPUpdate trace variable ecpDuty w EditGate::clockPUpdate wm deiconify $w dialogWait $w trace vdelete ecpOmega w EditGate::clockPUpdate trace vdelete ecpPhi w EditGate::clockPUpdate trace vdelete ecpDuty w EditGate::clockPUpdate } } tkgate-2.0-b10/scripts/optdefaults.tcl000644 001751 001751 00000022350 11150146105 020527 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2009 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Feb 21 22:53:41 2009 # ###################################################################### # # Option Definitions # # This file defines all of options and their default values. Note that # the default values here, can be overriddeng in the site-preferences # file. # ###################################################################### # # General settings # Option::new siteName Earth -optclass /General Option::new userName "" -optclass /General Option::new doSafeSave 1 -optclass /General Option::new saveWithCells 0 -optclass /General Option::new checkpointEnabled 0 -optclass /General Option::new checkpointFreq 300 -optclass /General -minvalue 1 -maxvalue 9999 ###################################################################### # # Special settings # Option::new enableBeakModes 0 -optclass Special Option::new baderMode 0 -optclass Special Option::new trekMode 0 -optclass Special Option::new batMode 0 -optclass Special Option::new allowDebug 0 -optclass Special Option::new batRate 200 -optclass Special Option::new fakeDoubleClicks 1 -optclass Special Option::new fakeDCInterval 300 -optclass Special Option::new checkVersion 0 -optclass Special ###################################################################### # # Do continuous verification # Option::new simDebugInterface 0 -optclass /Debug Option::new contVerify 0 -optclass /Debug ###################################################################### # # Obsolete settings # Option::new simInitScript "" -optclass Obsolete Option::new simCustomDelay 0 -optclass Obsolete Option::new simLogFile "" -optclass Obsolete ###################################################################### # # Interface settings # Option::new keyBindings emacs -optclass /Interface Option::new smoothScroll 1 -optclass /Interface Option::new regionUpdate 1 -optclass /Interface Option::new showDialogImage 1 -optclass /Interface Option::new fontSet normal -optclass /Interface Option::new blockDropConnect 0 -optclass /Interface Option::new undoLength 50 -optclass /Interface -minvalue 1 -maxvalue 999 Option::new helpBalloons 1 -optclass /Interface Option::new tearawayMenus 0 -optclass /Interface ###################################################################### # # Circuit default options # Option::new extendBars 1 -optclass /Circuit Option::new showSwitchNets 1 -optclass /Circuit ###################################################################### # # Toolbar options # Option::new filetb 1 -optclass /Toolbars/Edit Option::new edittb 1 -optclass /Toolbars/Edit Option::new gateoptb 1 -optclass /Toolbars/Edit Option::new gateprop 1 -optclass /Toolbars/Edit Option::new undotb 1 -optclass /Toolbars/Edit Option::new zoomtb 1 -optclass /Toolbars/Edit Option::new modetb 1 -optclass /Toolbars/Edit Option::new moduletb 1 -optclass /Toolbars/Edit Option::new techtb 1 -optclass /Toolbars/Edit Option::new zoomtb 1 -optclass /Toolbars/Edit Option::new simctltb 1 -optclass /Toolbars/Simulation Option::new simauxtb 1 -optclass /Toolbars/Simulation Option::new simmodestb 1 -optclass /Toolbars/Simulation Option::new symporttb 1 -optclass /Toolbars/Symboledit Option::new symshifttb 1 -optclass /Toolbars/Symboledit Option::new symoprtb 1 -optclass /Toolbars/Symboledit Option::new symmodestb 1 -optclass /Toolbars/Symboledit Option::new symedittb 1 -optclass /Toolbars/Symboledit ###################################################################### # # HDL text colors/fontification # Option::new hdlDragSel 1 -optclass /HDL Option::new hdlIndenting 1 -optclass /HDL Option::new hdlIndentLevel 2 -optclass /HDL -minvalue 0 -maxvalue 16 Option::new hdlIndentNoBegin 0 -optclass /HDL Option::new hdlIndentReturn 1 -optclass /HDL Option::new hdlColorize 1 -optclass /Color/HDL Option::new hdlCommentColor "firebrick" -optclass /Color/HDL Option::new hdlCommentBold 0 -optclass /Color/HDL Option::new hdlCommentItalic 1 -optclass /Color/HDL Option::new hdlStringColor "RosyBrown" -optclass /Color/HDL Option::new hdlStringBold 0 -optclass /Color/HDL Option::new hdlStringItalic 0 -optclass /Color/HDL Option::new hdlReservedColor "magenta4" -optclass /Color/HDL Option::new hdlReservedBold 1 -optclass /Color/HDL Option::new hdlReservedItalic 0 -optclass /Color/HDL Option::new hdlGateWordColor "red" -optclass /Color/HDL Option::new hdlGateWordBold 1 -optclass /Color/HDL Option::new hdlGateWordItalic 0 -optclass /Color/HDL Option::new hdlInstWordColor "black" -optclass /Color/HDL Option::new hdlInstWordBold 1 -optclass /Color/HDL Option::new hdlInstWordItalic 0 -optclass /Color/HDL Option::new hdlTaskWordColor "green4" -optclass /Color/HDL Option::new hdlTaskWordBold 1 -optclass /Color/HDL Option::new hdlTaskWordItalic 0 -optclass /Color/HDL ###################################################################### # # Simulator settings # Option::new simStepSize 1 -optclass /Simulate/Basic -minvalue 1 -maxvalue 1000000 Option::new valuePopUpDelay 333 -optclass /Simulate/Basic -minvalue 1 -maxvalue 10000 Option::new simClockStepSize 1 -optclass /Simulate/Basic -minvalue 1 -maxvalue 1000000 Option::new simClockOverStep 21 -optclass /Simulate/Basic -minvalue 0 -maxvalue 1000000 Option::new simSortTraces 1 -optclass /Simulate/Basic Option::new saveTraces 1 -optclass /Simulate/Basic Option::new glitchSuppress 1 -optclass /Simulate/Basic Option::new simDelayFile "" -optclass /Simulate/Technology Option::new warningMode 3 -optclass /Simulate/Error -minvalue 1 -maxvalue 4 ###################################################################### # # Library Options # Option::new simVPDPath "\${TKGATE_HOME}/vpd" -optclass /Library/VPD Option::new simVLibPath "\${TKGATE_HOME}/vlib" -optclass /Library/Path Option::new simVLibNames "" -optclass /Library/Load ###################################################################### # # Security Options # Option::new securityHandling 1 -optclass /Security Option::new securityExec 1 -optclass /Security Option::new securityWriteMem 0 -optclass /Security Option::new securityOpen 0 -optclass /Security Option::new securitySend 0 -optclass /Security Option::new securityEnqueue 1 -optclass /Security ###################################################################### # # HTML Options # Option::new browserCommand "firefox %s" -optclass /HTML Option::new emailCommand "thunderbird %s" -optclass /HTML ###################################################################### # # Critical Path Options # Option::new flashCPath 1 Option::new numCPath 10 ###################################################################### # # Default colors # Option::new instColor "blue" -optclass /Color/Edit Option::new moduleColor "magenta4" -optclass /Color/Edit Option::new modulePortColor "cyan4" -optclass /Color/Edit Option::new frameColor "black" -optclass /Color/Edit Option::new commentColor "black" -optclass /Color/Edit Option::new hyperlinkColor "blue3" -optclass /Color/Edit Option::new wireColor "green4" -optclass /Color/Edit Option::new busColor "red" -optclass /Color/Edit Option::new toolColor "black" -optclass /Color/Edit Option::new cpathColor "red" -optclass /Color/Edit Option::new offLedColor "lavender" -optclass /Color/Edit Option::new onLedColor "red" -optclass /Color/Edit Option::new zLedColor "yellow" -optclass /Color/Edit Option::new backgroundColor "white" -optclass /Color/Edit Option::new gridColor "black" -optclass /Color/Scope Option::new oneColor "green4" -optclass /Color/Scope Option::new zeroColor "magenta" -optclass /Color/Scope Option::new floatColor "blue" -optclass /Color/Scope Option::new unknownColor "red" -optclass /Color/Scope ###################################################################### # # Print options # Option::new printer default -optclass /Print/Output Option::new printDefCmdTmp "lpr" -optclass /Print/Output Option::new printCmdTmp "lpr -P\${PRINTER}" -optclass /Print/Output Option::new printCommands {} -optclass /Print/Output Option::new printPgSize(US) Letter -optclass /Print/Output Option::new printPgSize(*) A4 -optclass /Print/Output Option::new printPgOrient landscape -optclass /Print/Output Option::new printDuplex 0 -optclass /Print/Output Option::new printStyle fit -optclass /Print/Content Option::new printIndex 0 -optclass /Print/Content Option::new printGraph 0 -optclass /Print/Content Option::new printMergeSmall 1 -optclass /Print/Content tkgate-2.0-b10/scripts/license.tcl000644 001751 001751 00000006277 10661451776 017654 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Wed Mar 30 00:19:59 2005 # proc showDocFile {label file L} { global tkg_gateHome set w .docwin set i 0 while { [catch { toplevel $w$i}] } { incr i } set w $w$i wm resizable $w 0 0 wm title $w $label wm transient $w . button $w.dismiss -text [m b.dismiss] -command "destroy $w" scrollbar $w.scroll -command "$w.text yview" text $w.text -yscrollcommand "$w.scroll set" pack $w.dismiss -side bottom -fill x pack $w.text $w.scroll -side left -fill y foreach s $L { $w.text insert end "$s\n" } if { $file != "" } { set f [open $tkg_gateHome/doc/$file] $w.text insert end [read $f] close $f } $w.text configure -state disabled } proc showLicense {} { global bd tkg_progVer tkg_copyright tkg_mailContact tkg_description set L {} lappend L " TKGate $tkg_progVer - $tkg_description" lappend L "" lappend L " $tkg_copyright" lappend L "" showDocFile "TkGate License" "license.txt" $L } proc showDocumentation {} { global bd tkg_progVer tkg_copyright tkg_mailContact tkg_description tkg_homepage tkg_localdoc gat_dohyperlink $tkg_localdoc if {0} { set L {} lappend L "TKGate $tkg_progVer - $tkg_description" lappend L "" lappend L "$tkg_copyright" lappend L "" lappend L "Currently there is no built-in documentation for TkGate other than the" lappend L "balloon help which can be activated by placing the mouse cursor over" lappend L "interface elements, and the online tutorials availble. Documentation" lappend L "can be found by pointing your Web browser at the TkGate home page:" lappend L "" lappend L " $tkg_homepage" lappend L "" lappend L "or through the copy of the documentation included in this distribution at:" lappend L "" lappend L " $tkg_localdoc" showDocFile "TkGate Documentation" "" $L } } proc showAbout {} { global bd tkg_progVer tkg_copyright tkg_mailContact tkg_description if { [catch { toplevel .about}] } { catch { raise .about } return; } wm title .about "About TkGate $tkg_progVer" button .about.dismiss -text [m b.dismiss] -command "destroy .about" label .about.logo -relief groove -image [gifI biggatelogo.gif] label .about.label -text "TKGate $tkg_progVer - $tkg_description\n$tkg_copyright\n$tkg_mailContact" pack .about.logo -padx 10 -pady 10 -ipadx 10 -ipady 10 pack .about.label -padx 10 -pady 10 pack .about.dismiss -padx 10 -pady 10 } tkgate-2.0-b10/scripts/simulator.tcl000644 001751 001751 00000031035 11257511454 020227 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Sep 26 18:18:20 2009 # set simId 0 set simOn 0 set currentSimTime 0ns set tkg_simDisplayedVal 0 namespace eval SimWatcher { variable w "" proc addText {s} { variable w if {$w == ""} return if {[string range $s 0 2] == "<--" } { $w.text insert end "$s\n" red } else { $w.text insert end "$s\n" blue } $w.text see end } proc flushText {} { variable w if {$w == ""} return $w.text delete 1.0 end } proc destroyNotify {} { variable w set w "" } proc post {} { variable w set w .simwatcher if { [catch { toplevel $w }] } { flushText return } wm resizable $w 0 0 wm title $w "TkGate: Simulation Watch" wm geometry $w [offsetgeometry . 50 50] bind $w SimWatcher::destroyNotify button $w.dismiss -text [m b.dismiss] -command "destroy $w" text $w.text -yscrollcommand "$w.vb set" scrollbar $w.vb -command "$w.text yview" pack $w.dismiss -side bottom -fill x pack $w.text $w.vb -side left -fill y $w.text tag configure blue -foreground blue $w.text tag configure red -foreground red } } ############################################################################# # # Verifiy that simulator is running # proc tkg_simCheck {} { global simOn if { $simOn == 0 } { errmsg [m err.simonly] return 0 } return 1 } ######################################## # # start up the simulator # proc tkg_startSim {fname initTime} { global simId simOn mode simExec tkg_simDelayFile tkg_simDefaultDelayFile tkg_simCustomDelay global tkg_currentFile tkg_simDebugInterface tkg_warningMode set basename "" if { $simOn } { return } set p [string last "/" $tkg_currentFile] if { $p > 0 } { set basename [string range $tkg_currentFile 0 $p] } else { set basename "/" } if { $tkg_simCustomDelay } { set delayFile $tkg_simDelayFile } { set delayFile $tkg_simDefaultDelayFile } set delayFile $tkg_simDefaultDelayFile foreach f $tkg_simDelayFile { set delayFile "${delayFile}:$f" } # # Construct the commmand line to use for starting the simulator. # set simCmd "$simExec -i $fname -B $basename -D [gat_computestrhash $fname] -W $tkg_warningMode -I $initTime" # # Start up the simulator # if { [catch { set simId [open "|$simCmd" r+ ] } ] } { errmsg "Failed to start simulator '${simExec}'" return } if { $tkg_simDebugInterface } { SimWatcher::post } fileevent $simId readable { tkg_readSim; update idletasks } set simOn 1 set mode 1 tkg_resetLogo return $simId } ######################################## # # read a command from simulator # proc tkg_readSim {} { global simId simOn tkg_simDebugInterface if { !$simOn } { return } if { [catch { set command [gets $simId] } ] } { gat_setMajorMode edit errmsg "Simulator has died (read error)." return } if { $command == "" && [eof $simId] } { gat_setMajorMode edit errmsg "Simulator has died (eof in read)." return } if { $tkg_simDebugInterface } { SimWatcher::addText "--> $command" } gat_scopeCommand $command return 0 } proc tkg_endSim {} { global simId simOn catch { fileevent $simId readable } catch { close $simId } set simOn 0 gat_breakpoint -clear gat_setMajorMode edit tkg_editLogo } ############################################################################# # # Simulation script handling # proc tkg_doSimScript args { global simScript_filter simScript_filetypes if { ![tkg_simCheck] } return set parent "." parseargs $args {-parent} set fileName [tk_getOpenFile -defaultextension $simScript_filter -parent $parent -filetypes $simScript_filetypes ] if { $fileName != "" } { ScriptMgr::load $fileName } } ############################################################################# # # Load a memory from a file. # proc tkg_simLoadMem args { global mem_filetypes mem_filter if { ![tkg_simCheck] } return set parent "." parseargs $args {-parent} set g [gat_simSelected ram rom] set load [tk_getOpenFile -defaultextension $mem_filter -parent $parent -filetypes $mem_filetypes ] if { $load != "" } { # tkg_simGateCmd $g load $load Simulator::cmdSend "\$memload $load $g" } } ############################################################################# # # Dump a memory to a file. # proc tkg_simDumpMem args { global mem_filetypes mem_filter if { ![tkg_simCheck] } return set parent "." parseargs $args {-parent} set g [gat_simSelected ram rom] set dump [tk_getSaveFile -defaultextension $mem_filter -parent $parent -filetypes $mem_filetypes ] if { $dump != "" } { if { $g == "" } { Simulator::cmdSend "\$memdump $dump" } else { Simulator::cmdSend "\$memdump $dump $g" } } } ############################################################################# # # basic commands # proc tkg_simNetSet {net val} { if { ![tkg_simCheck] } return Simulator::cmdSend "\$set $net $val" } ############################################################################# # # Put simulator in continuous run mode. # proc tkg_simRun {} { global simOn if { $simOn == 0 } { gat_setMajorMode simulate } { gat_breakpoint -clear Simulator::cmdSend "\$go" } } ############################################################################# # # Stop the simulator (put it in pause mode) # proc tkg_simStop {} { global simOn if { $simOn == 0 } { } { Simulator::cmdSend "\$stop" } } ############################################################################# # # args: +/- # after [clock] # proc tkg_simCycle args { global tkg_simClockOverStep tkg_simActClock tkg_simUseActClock tkg_simClockStepSize global simOn if { $simOn == 0 } return gat_editCircProps load simProps set tkg_simClockStepSize [validate_posint $tkg_simClockStepSize] set tkg_simClockOverStep [validate_nonnegint $tkg_simClockOverStep] gat_breakpoint -clear if { $args == "" } { if { $::simProps(clockMode) == 1 } { Simulator::cmdSend "\$clock + $tkg_simClockStepSize $tkg_simClockOverStep $::simProps(clockName).Z" } else { Simulator::cmdSend "\$clock + $tkg_simClockStepSize $tkg_simClockOverStep" } } { Simulator::cmdSend "\$clock $args" } } ############################################################################# # # Simulator interface # namespace eval Simulator { variable dipValue variable dipWindow variable timeUpdate_ev proc doTimeUpdate {} { variable timeUpdate_ev if { [cmdSend -ignoreerrors "\$time"] } { set timeUpdate_ev [after 500 Simulator::doTimeUpdate] } } proc startTimeUpdates {} { variable timeUpdate_ev catch { catch { after cancel $timeUpdate_ev } set timeUpdate_ev [after 500 Simulator::doTimeUpdate] } } proc stopTimeUpdates {} { variable timeUpdate_ev catch { after cancel $timeUpdate_ev } } ############################################################################# # # Step simulator by a single epoch. # proc stepEpoch args { global tkg_simStepSize global simOn if { $simOn == 0 } return gat_breakpoint -clear set tkg_simStepSize [validate_posint $tkg_simStepSize] if { $args == "" } { Simulator::cmdSend "\$step $tkg_simStepSize" } { Simulator::cmdSend "\$step $args" } } proc showValue {n} { global tkg_simDisplayedVal tkg_showValueEv tkg_valuePopUpDelay set tkg_simDisplayedVal "-" Simulator::cmdSend "\$show $n" scan [winfo pointerxy .] "%d %d" x y set tkg_showValueEv [after $tkg_valuePopUpDelay "Simulator::postShowValue $x $y"] } proc postShowValue {x y} { global tkg_simDisplayedVal catch { destroy .showv } toplevel .showv -bg bisque wm geometry .showv +[expr $x + 5]+[expr $y - 30] wm transient .showv . wm overrideredirect .showv 1 label .showv.l -textvariable tkg_simDisplayedVal -bg bisque pack .showv.l -padx 4 -pady 4 } proc hideValue {} { global tkg_showValueEv catch { after cancel $tkg_showValueEv } catch { destroy .showv } } # # Apply value in dip value selector # proc dipApply {w g} { variable dipValue set q [ gat_setDip $g $dipValue($g) ] set dipValue($g) $q dipSetIndicator $w 0 } # # Destroy a DIP entry window # proc dipDestroy {w g} { variable dipWindow set dipWindow($g) "" catch { trace vdelete Simulator::dipValue($g) w "Simulator::dipSetIndicator $w 1" } catch { destroy $w } } # # Set the "changed" indicator # proc dipSetIndicator {w changed args} { if { $changed } { set color red } else { set color green } $w.top.indicator itemconfigure indicator -fill $color -outline $color } # # Create a window for entering a dip value. # proc dipEntry {g v x y} { variable dipValue variable dipWindow # # If DIP window is already open, just raise it. # if { [catch { set w $dipWindow($g) } ] } { set w "" } if { $w != "" } { raise $w return } # # Choose a top-level window for the dip setter # for {set i 0} { [catch { set w [toplevel .dipe$i] }] } { incr i } { } set dipWindow($g) $w wm resizable $w 0 0 wm title $w [m db.dip.title] wm geometry $w [offsetgeometry . $x $y] wm transient $w . set dipValue($g) $v frame $w.top canvas $w.top.indicator -width 12 -height 12 -bd 0 -bg [$w cget -bg] -highlightthickness 0 $w.top.indicator create oval 2 2 10 10 -fill green -outline green -tags indicator label $w.top.label -text "$g:" incdecEntry $w.entr -width 10 -font dipFont -variable Simulator::dipValue($g) \ -format %x -validatecommand hexValidate button $w.apply -text [m b.apply] -command "Simulator::dipApply $w $g" button $w.close -text [m b.close] -command "Simulator::dipDestroy $w $g" bindtags $w.entr [concat [list HexEntry] [bindtags $w.entr]] pack $w.top.indicator -side left pack $w.top.label -side left -fill both -padx 2 pack $w.top -side top -fill both pack $w.close -side bottom -fill both -pady 3 pack $w.entr $w.apply -side left -pady 5 -padx 5 trace variable Simulator::dipValue($g) w "Simulator::dipSetIndicator $w 1" bind $w "Simulator::dipDestroy $w $g" bind $w.entr.e "Simulator::dipApply $w $g" bind .scope "+ Simulator::dipDestroy $w $g" } #tkg_simWrite proc cmdSend {args} { global simId tkg_simDebugInterface set ignoreerrors 0 if {[llength $args] > 1} { if {[lsearch $args -ignoreerrors] >= 0} { set ignoreerrors 1 } set msg [lindex $args [expr [llength $args]-1]] } else { set msg [lindex $args 0] } if { $tkg_simDebugInterface } { SimWatcher::addText "<-- $msg" } if { [catch { puts $simId $msg }] } { gat_setMajorMode edit if {!$ignoreerrors} { errmsg "Simulator has died (in write)." } return 0 } cmdFlush return 1 } #tkg_simFlush proc cmdFlush {} { global simId if { [catch { flush $simId } ] } { gat_setMajorMode edit errmsg "Simulator has died (in flush)." return } } ############################################################################# # # Inform simulator of security settings # proc setupSecurity {} { global tkg_securityHandling tkg_securityExec tkg_securityWriteMem tkg_securityOpen global tkg_securitySend tkg_securityEnqueue Simulator::cmdSend "\$option sec.send $tkg_securitySend" Simulator::cmdSend "\$option sec.fopen $tkg_securityOpen" Simulator::cmdSend "\$option sec.writemem $tkg_securityWriteMem" Simulator::cmdSend "\$option sec.queue $tkg_securityEnqueue" Simulator::cmdSend "\$option sec.exec $tkg_securityExec" Simulator::cmdSend "\$option sec.handling $tkg_securityHandling" } } tkgate-2.0-b10/scripts/scope.tcl000644 001751 001751 00000013166 11140474320 017315 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Thu Jan 29 22:49:36 2009 # namespace eval Scope { proc makeToolbar {w} { global bd tkg_showXHair tbr frame $w frame $w.f toolbutton $w.f.print "file_print.gif" ScopePrintDlg::post ho.traceprint pack $w.f.print -side left -pady 5 frame $w.z toolbutton $w.z.zoomin "zoom_in.gif" { .scope.main.frame.canvas zoom -1 } ho.tool.zoomin toolbutton $w.z.zoomout "zoom_out.gif" { .scope.main.frame.canvas zoom 1 } ho.tool.zoomout pack $w.z.zoomin $w.z.zoomout -side left -pady 5 frame $w.s toolbutton $w.s.simgo "sim_go.gif" tkg_simRun ho.simgo toolbutton $w.s.simpause "sim_pause.gif" tkg_simStop ho.simpause toolbutton $w.s.simstep "sim_step.gif" Simulator::stepEpoch ho.simstep toolbutton $w.s.simclock "sim_clock.gif" tkg_simCycle ho.simclock toolbutton $w.s.simstop "sim_stop.gif" { gat_setMajorMode edit } ho.simstop pack $w.s.simgo $w.s.simpause $w.s.simstep $w.s.simclock $w.s.simstop -side left -pady 5 frame $w.scope toolbutton $w.scope.simbreak "sim_break.gif" Action::editBreakpoints ho.simbreak toolbutton $w.scope.simscript "sim_script.gif" Action::doSimScript ho.simexec toolbutton $w.scope.simload "sim_load.gif" Action::simLoadMem ho.simload toolbutton $w.scope.simdump "sim_dump.gif" Action::simDumpMem ho.simdump pack $w.scope.simbreak $w.scope.simscript $w.scope.simload $w.scope.simdump -side left -pady 5 pack $w.scope.simload $w.scope.simdump -side left -pady 5 frame $w.extra set tkg_showXHair 1 checkbutton $w.extra.showxhair -indicatoron 0 -image [gifI "show_xhair.gif"] -variable tkg_showXHair -takefocus 0 -command { gat_setShowXHairState $tkg_showXHair } -selectcolor "\#b9b9b9" -relief flat pack $w.extra.showxhair -side left -pady 5 pack $w.f $w.z $w.s $w.scope $w.extra -side left -padx 5 # pack $w.f $w.z $w.s $w.sc -side left -padx 5 helpon $w.extra.showxhair [m ho.showxhair] } proc makeHidden {} { wm withdraw .scope } proc makeVisible {} { wm deiconify .scope } # proc makeHidden {} { } # proc makeVisible {} { } proc post {} { toplevel .scope -takefocus 0 wm geometry .scope +70+0 wm minsize .scope 500 300 wm title .scope [m scope.title] makeHidden # tkg_scopeMenu .scope.mbar Menu::makeBar .scope.mbar scope frame .scope.bar1 -bd 1 -relief sunken -height 2 makeToolbar .scope.tbar frame .scope.main frame .scope.main.frame -relief sunken -bd 2 bind .scope { gat_setMajorMode edit } bind .scope Scope::hideTraceName gat_scope .scope.main.frame.canvas -width 600 -height 400 -bg white scrollbar .scope.main.vert -command ".scope.main.frame.canvas yview" -takefocus 0 scrollbar .scope.main.horz -orient horizontal -command ".scope.main.frame.canvas xview" -takefocus 0 # pack .scope.main.vert -side right -fill y # pack .scope.main.horz -side bottom -fill x # pack .scope.main.frame -side top -fill both -expand 1 -padx 5 -pady 5 pack .scope.main.frame.canvas -fill both -expand 1 grid .scope.main.frame -row 0 -column 0 -sticky nsew grid .scope.main.horz -row 1 -column 0 -sticky ew grid .scope.main.vert -row 0 -column 1 -sticky ns grid rowconfigure .scope.main 0 -weight 1 grid columnconfigure .scope.main 0 -weight 1 pack .scope.mbar -fill x pack .scope.bar1 -fill x -padx 3 -pady 1 pack .scope.tbar -fill x pack .scope.main -fill both -expand 1 -padx 5 -pady 5 KeyBinding::listener .scope.mbar main -unmatchedcommand dobell focus .scope.mbar bind .scope.main.frame.canvas { gat_scopeButton %x %y %X %Y 1 %s } bind .scope.main.frame.canvas { gat_scopeButton %x %y %X %Y 3 %s } bind .scope.main.frame.canvas { gat_scopeMotion %x %y %X %Y 0 %s } bind .scope.main.frame.canvas { gat_scopeRelease %x %y %X %Y 1 %s } bind .scope.main.frame.canvas { gat_scopeRelease %x %y %X %Y 3 %s } } proc unpost {} { catch { destroy .scope } } variable pvEvent "" # # Post the full name of a net near the mouse pointer # proc showTraceName {n} { variable pvEvent catch { after cancel $pvEvent } scan [winfo pointerxy .] "%d %d" x y set pvEvent [after 50 Scope::postName $x $y $n] } proc hideTraceName {} { catch { after cancel $pvEvent } catch { destroy .stName } } proc postName {x y name} { catch { destroy .stName } toplevel .stName -bg bisque wm geometry .stName +[expr $x + 5]+[expr $y - 30] wm transient .stName . wm overrideredirect .stName 1 bind .stName { destroy .stName } label .stName.l -text $name -bg bisque pack .stName.l -padx 4 -pady 4 } } proc scope_test {} { button .make -text Scope -command makeScope button .print -text Print -command printDlg pack .make .print -fill x wm geometry . +0+0 } tkgate-2.0-b10/scripts/helpon.tcl000644 001751 001751 00000005061 10210762264 017470 0ustar00hansenhansen000000 000000 # Copyright (C) 1987-2004 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Mon Feb 28 22:42:44 2005 # set ho_ReqWin "" set ho_ReqTag "" set ho_PostWin "" set ho_delay 500 set ho_color "bisque" proc post_help {win tag} { global ho_ReqWin ho_ReqTag ho_PostWin ho_color tkg_helpBalloons global helpon_msg set msg "" catch { set msg $helpon_msg($tag) } if { $tkg_helpBalloons == 0 } { return } if { $win != $ho_ReqWin } { return } if { $tag != $ho_ReqTag } { return } if { $win == $ho_PostWin } { return } catch { destroy .helpon } scan [winfo pointerxy .] "%d %d" X Y catch { bind $win { catch { destroy .helpon } } toplevel .helpon wm geometry .helpon +[expr $X + 5]+[expr $Y + 5] wm transient .helpon . wm overrideredirect .helpon 1 label .helpon.msg -text $msg -justify left -bg $ho_color pack .helpon.msg bind .helpon { raise .helpon } set ho_PostWin $win } } proc req_help {win tag} { global ho_ReqWin ho_ReqTag ho_delay set ho_ReqWin $win set ho_ReqTag $tag after $ho_delay "post_help $win $tag" } proc cancel_help {} { global ho_ReqWin ho_ReqTag ho_PostWin catch { destroy .helpon } set ho_ReqWin "" set ho_ReqTag "" set ho_PostWin "" } proc helpon {win msg} { global helpon_msg set helpon_msg($win) $msg if {$msg == ""} { bind $win "" bind $win "" } else { bind $win "+req_help $win $win" bind $win "+cancel_help" } } proc helponitemcancel {win item} { global helpon_msg catch { unset helpon_msg(${win}:$item) } } proc helponitem {win item msg} { global helpon_msg set helpon_msg(${win}:$item) $msg if {$msg == ""} { $win bind $item "" $win bind $item "" } else { $win bind $item "+req_help $win ${win}:$item" $win bind $item "+cancel_help" } } tkgate-2.0-b10/scripts/tkgate.tcl000644 001751 001751 00000026215 11150143537 017466 0ustar00hansenhansen000000 000000 ############################################################################# # # Copyright (C) 1987-2009 by Jeffery P. Hansen # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # # Last edit by hansen on Sat Feb 21 22:32:47 2009 # ############################################################################# # # This file is the entry point into the tcl/tk code executed by tkgate. Before # this file is executed, the following variables are set in the C portion of # tkgate: # # sd The directory with tcl script files # bd The directory with bitmaps/images # lang Language code (e.g. "en", "ja", "fr", ...) # territory Territory code (e.g., "US", "GB", "JP", ...) # simOn Flag indicating if the simulator is active. # tkg_gateHome The home directory for tkgate. # tkg_doSplash Indicates if a splash window should be displayed. # tkg_currentFile Name of current file being edited. # tkg_tutotialDir Directory with tutorial files. # tkg_exampleDir Directory with example files. # tkg_progVer TkGate version number # tkg_description Text descrition of tkgate # tkg_copyright Copyright message # tkg_mailContact E-mail address of tkgate maintainer # tkg_homepage Homepage of tkgate maintainer # tkg_localdoc Location of local html format documentation ############################################################################# # # Minimm scripts we need to begin tkgate initialization # set startScriptSet { misc options optdefaults parms} ############################################################################# # # The rest of tkgate's scripts # set baseScriptSet { keys ipanel dragger tabbox notebook pane dropbox helpon tree spreadsheet wizard frame info blocktree blockops blocklist netlist portlist sidebar menu memview popups setselector status print scope toolbar message errbox editgate find circuit simulator simopts breakpoint scriptmgr vpd file optionsdialog cpath license undo action symboledit hdledit library debug init } proc mainWinButton12Press {w x y s b} { global tkg_fakeDoubleClicks global tkg_fakeDCInterval global lastKeyPressTime action -Press { tkg_buttonPress $w $x $y $s $b } if {$tkg_fakeDoubleClicks} { set t [clock clicks -milliseconds] set interval [expr $t-$lastKeyPressTime] if {$interval < $tkg_fakeDCInterval} { mainWinButton12DoublePress $w $x $y $s } set lastKeyPressTime $t } } proc mainWinButton12DoublePress {w x y s} { continueAction -DblPress { tkg_buttonDoublePress $w $x $y $s } } proc mainWinButton12Release {w x y s} { continueAction - { tkg_buttonRelease $w $x $y $s } } proc mainWinButtonMotion {w x y s} { continueAction - { tkg_buttonMotion $w $x $y $s} } proc mainWinButton3Press {w x y s X Y} { action -Select { PopupMenu::post $w $x $y $s $X $Y } } ############################################################################# # # This is the function that is called to start up tkgate. # proc startTkGate {argv} { global tkgate_isInitialized mode tkg_allowDebug global tkg_progName tkg_progVer tkg_gateHome tkg_prefFile global main_w tkg_checkpointFreq tkg_keyBindings global tkg_minWidth tkg_minHeight global tkg_fontSet global bd sd global tkg_fakeDoubleClicks global startScriptSet baseScriptSet ############################################################################# # # Set flag to indicate that initialization is not complete. # set tkgate_isInitialized 0 ############################################################################# # # If argument list starts with "--", remove it. # if { [lindex $argv 0] == "--" } { set argv [lrange $argv 1 end] } ############################################################################# # # If the tcl/tk version is less than 8.4, then there are certain # unsupported options for menus that we must remember. # global menu_forbidden if {[info tclversion] < 8.4} { set menu_forbidden {-compound -image -selectimage} } else { set menu_forbidden {} } ############################################################################# # # Set up pointers to important directories. # set sd [file dirname [info script]] set bd [file dirname $sd]/images ############################################################################# # # Run tkgate's main # eval tkgate_main $argv catch { package require Tk } tkgate_posttk ############################################################################# # # Load in the minimum tcl files we need to start the splash screen. # foreach f $startScriptSet { uplevel "source $sd/${f}.tcl" } ############################################################################# # # Read the site default preferences (global to all users) # if {[file exists $tkg_gateHome/site-preferences]} { uplevel "source $tkg_gateHome/site-preferences" } ############################################################################# # # Read the user specific preferences (in user's home directory) # if {[file exists $tkg_prefFile]} { uplevel "source $tkg_prefFile" } ############################################################################# # # Begin display of the splash window (if it has not been disabled) # start_splash ############################################################################# # # Load the rest of the tcl/tk code for tkgate. # foreach f $baseScriptSet { uplevel "source $sd/${f}.tcl" } ############################################################################# # # Define fonts to be used. # setFontSet ${tkg_fontSet} ############################################################################# # # Initialize the options database # setupOptions ############################################################################# # # Printer dialog box initializations # printDlgInit ############################################################################# # # Make all of the popup menus # makePopups ############################################################################# # # If debugging is enabled, set up debugging key bindings. # if { $tkg_allowDebug } { KeyBinding::new Action::dumpWires KeyBinding::new Action::verify KeyBinding::new Action::debugMode } ############################################################################# # # Set up hex and number entry tags # hexEntrySetup numEntrySetup floatEntrySetup ############################################################################# # # Set up main window panes. # setupMainWindowPanes wm title . "$tkg_progName $tkg_progVer" wm minsize . $tkg_minWidth $tkg_minHeight setupIconWindow ############################################################################# # # Side bar setup # SideBar::new .pane.sbar ############################################################################# # # Status bar setup # makeStatus .status after [expr $tkg_checkpointFreq * 1000] tkg_checkpointReq ############################################################################# # # Set key bindings # KeyBinding::loadBindings $tkg_gateHome/bindings/$tkg_keyBindings ############################################################################# # # Toolbar initialization # ToolBar::init if { $tkg_allowDebug } { Menu::setFlags D } ############################################################################# # # Create the main canvas and define bindings for mouse activity actions. # tkg_gatewin $main_w.main -width 100 -height 100 -takefocus 0 \ -xscrollcommand "$main_w.horz set" -yscrollcommand "$main_w.vert set" -bg seashell grid $main_w.main -row 0 -column 0 -sticky nsew bind $main_w.main { mainWinButton12Press %W %x %y %s %b } bind $main_w.main { mainWinButton12Press %W %x %y %s %b } if {!$tkg_fakeDoubleClicks} { bind $main_w.main { mainWinButton12DoublePress %W %x %y %s } bind $main_w.main { mainWinButton12DoublePress %W %x %y %s } } bind $main_w.main { mainWinButton12Release %W %x %y %s } bind $main_w.main { mainWinButton12Release %W %x %y %s } bind $main_w.main { mainWinButtonMotion %W %x %y %s } bind $main_w.main { mainWinButton3Press %W %x %y %s %X %Y } bind $main_w.main { puts mouseWheel } ############################################################################# # # The focus should stay here automatically, but in case it doesn't make sure # a click restores focus to the menu bar to key commands can be processed # properly. # bind $main_w.main {+ focus .tbar.m } bind $main_w.main {+ focus .tbar.m } ############################################################################# # # This forces the forces the focus to be returned to the menu bar (which # processes keyboard commands) any time the mouse is pressed in the main # window. In most cases, the focus should stay there automatically. This # handler is a contingency. # bind $main_w

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