pax_global_header00006660000000000000000000000064151475202500014513gustar00rootroot0000000000000052 comment=bc3df10ff30ee342b944aff5d85283a26b7de342 prjpeppercorn-1.12/000077500000000000000000000000001514752025000143275ustar00rootroot00000000000000prjpeppercorn-1.12/.gitignore000066400000000000000000000000441514752025000163150ustar00rootroot00000000000000#python __pycache__/ *.pyc *.tar.gz prjpeppercorn-1.12/.readthedocs.yaml000066400000000000000000000002751514752025000175620ustar00rootroot00000000000000version: 2 build: os: ubuntu-22.04 tools: python: '3.11' sphinx: configuration: docs/source/conf.py python: install: - requirements: docs/source/requirements.txt prjpeppercorn-1.12/COPYING000066400000000000000000000013551514752025000153660ustar00rootroot00000000000000Copyright (C) 2024 The Project Peppercorn Authors. Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. prjpeppercorn-1.12/README.md000066400000000000000000000010471514752025000156100ustar00rootroot00000000000000# Project Peppercorn GateMate FPGAs Bitstream Documentation and Tools ## Credits Code is heavily based on [prjtrellis](https://github.com/YosysHQ/prjtrellis). Special thanks goes to [@gatecat](https://github.com/gatecat) ### License All software (code, associated documentation, support files, etc) in the Project Peppercorn repository are licensed under the very permissive [ISC Licence](https://opensource.org/licenses/ISC). A copy can be found in the [`COPYING`](COPYING) file. All new contributions must also be released under this license. prjpeppercorn-1.12/decompress.py000066400000000000000000000513371514752025000170560ustar00rootroot00000000000000import zlib import struct from dataclasses import dataclass from typing import List @dataclass class T_delay_tri: min: int typ: int max: int @staticmethod def from_bytes(data: bytes) -> 'T_delay_tri': min_val, typ_val, max_val = struct.unpack('<3i', data) return T_delay_tri(min_val, typ_val, max_val) @dataclass class T_delay: rise: T_delay_tri fall: T_delay_tri @staticmethod def from_bytes(data: bytes) -> 'T_delay': rise = T_delay_tri.from_bytes(data[:12]) fall = T_delay_tri.from_bytes(data[12:24]) return T_delay(rise, fall) @dataclass class Tpin_pair: i: int o_or_clk: int # Represents either 'o' or 'clk' depending on the boolean case @staticmethod def from_bytes(data: bytes) -> 'Tpin_pair': i_val, o_or_clk_val = struct.unpack('<2h', data) return Tpin_pair(i_val, o_or_clk_val) @dataclass class Tentry_rec: pins: Tpin_pair entry_no: int @staticmethod def from_bytes(data: bytes) -> 'Tentry_rec': pins = Tpin_pair.from_bytes(data[:4]) entry_no = struct.unpack(' 'Tdel_entry': key, edge1, edge2 = struct.unpack('<3i', data[:12]) time1 = T_delay_tri.from_bytes(data[12:24]) time2 = T_delay_tri.from_bytes(data[24:36]) return Tdel_entry(key, edge1, edge2, time1, time2) @dataclass class TRAM_del_rec: iopath: List[Tentry_rec] setuphold: List[Tentry_rec] width: List[Tentry_rec] del_entry: List[Tdel_entry] @staticmethod def from_bytes(data: bytes) -> 'TRAM_del_rec': offset = 0 iopath = [Tentry_rec.from_bytes(data[offset + i*6:offset + (i+1)*6]) for i in range(3001)] offset += 3001 * 6 setuphold = [Tentry_rec.from_bytes(data[offset + i*6:offset + (i+1)*6]) for i in range(8001)] offset += 8001 * 6 width = [Tentry_rec.from_bytes(data[offset + i*6:offset + (i+1)*6]) for i in range(51)] offset += 51 * 6 del_entry = [Tdel_entry.from_bytes(data[offset + i*36:offset + (i+1)*36]) for i in range(101)] return TRAM_del_rec(iopath, setuphold, width, del_entry) @dataclass class Tdel_rec: val: T_delay conf_mux: int name: str x: int y: int plane: int dir: int inv: int cnt: int con_type: int @staticmethod def from_bytes(data: memoryview, offset: int) -> ('Tdel_rec', int): val = T_delay.from_bytes(data[offset:offset + 24]) offset += 24 conf_mux = struct.unpack_from(' ('Tdel_rec_tri', int): val = T_delay_tri.from_bytes(mv[offset:offset+12]) offset += 12 conf_mux = struct.unpack_from(' (List, int): SB_del_tile_arr = [] for i1 in range(4): # [1..4] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(4): # [1..4] level3 = [] for i4 in range(12): # [1..12] level4 = [] for i5 in range(5): # [0..4] level5 = [] for i6 in range(8): # [0..7] chunk = mv[offset:offset + 24] if len(chunk) < 24: raise EOFError("Unexpected end of data") delay = T_delay.from_bytes(chunk) offset += 24 level5.append(delay) level4.append(level5) level3.append(level4) level2.append(level3) level1.append(level2) SB_del_tile_arr.append(level1) return SB_del_tile_arr, offset @dataclass class ExtraTimingDelays: skew_report_del: int fix_skew_del: int del_rec_0: Tdel_rec del_min_route_SB: Tdel_rec del_violation_common: Tdel_rec_tri del_dummy: Tdel_rec del_Hold_D_L: Tdel_rec_tri del_Hold_RAM: Tdel_rec_tri del_Setup_D_L: Tdel_rec_tri del_Setup_RAM: Tdel_rec_tri del_Hold_SN_RN: Tdel_rec_tri del_Setup_SN_RN: Tdel_rec_tri del_Hold_RN_SN: Tdel_rec_tri del_Setup_RN_SN: Tdel_rec_tri del_bot_couty2: Tdel_rec del_bot_glb_couty2: Tdel_rec del_bot_SB_couty2: Tdel_rec del_bot_pouty2: Tdel_rec del_bot_glb_pouty2: Tdel_rec del_bot_SB_pouty2: Tdel_rec del_left_couty2: Tdel_rec del_left_glb_couty2: Tdel_rec del_left_SB_couty2: Tdel_rec del_left_pouty2: Tdel_rec del_left_glb_pouty2: Tdel_rec del_left_SB_pouty2: Tdel_rec del_inp: List[Tdel_rec] del_CPE_out_mux: List[Tdel_rec] del_CPE_CP_Q: Tdel_rec del_CPE_S_Q: Tdel_rec del_CPE_R_Q: Tdel_rec del_CPE_D_Q: Tdel_rec del_RAM_CLK_DO: Tdel_rec del_GLBOUT_sb_big: Tdel_rec del_sb_drv: Tdel_rec del_CP_carry_path: Tdel_rec del_CP_prop_path: Tdel_rec del_special_RAM_I: Tdel_rec del_RAMO_xOBF: Tdel_rec del_GLBOUT_IO_SEL: Tdel_rec del_IO_SEL_Q_out: Tdel_rec del_IO_SEL_Q_in: Tdel_rec in_delayline_per_stage: Tdel_rec out_delayline_per_stage: Tdel_rec del_IBF: Tdel_rec del_OBF: Tdel_rec del_r_OBF: Tdel_rec del_TOBF_ctrl: Tdel_rec del_LVDS_IBF: Tdel_rec del_LVDS_OBF: Tdel_rec del_LVDS_r_OBF: Tdel_rec del_LVDS_TOBF_ctrl: Tdel_rec del_CP_clkin: Tdel_rec del_CP_enin: Tdel_rec del_preplace: Tdel_rec del_CPE_timing_mod: List[Tdel_rec] @staticmethod def from_bytes(mv: memoryview, offset: int) -> ('ExtraTimingDelays', int): skew_report_del, fix_skew_del = struct.unpack_from('<2i', mv, offset) offset += 8 del_rec_0, offset = Tdel_rec.from_bytes(mv, offset) del_min_route_SB, offset = Tdel_rec.from_bytes(mv, offset) del_violation_common, offset = Tdel_rec_tri.from_bytes(mv, offset) del_dummy, offset = Tdel_rec.from_bytes(mv, offset) del_Hold_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_bot_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_inp = [] for _ in range(8): rec, offset = Tdel_rec.from_bytes(mv, offset) del_inp.append(rec) del_CPE_out_mux = [] for _ in range(4): rec, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_out_mux.append(rec) del_CPE_CP_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_S_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_R_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_D_Q, offset = Tdel_rec.from_bytes(mv, offset) del_RAM_CLK_DO, offset = Tdel_rec.from_bytes(mv, offset) del_GLBOUT_sb_big, offset = Tdel_rec.from_bytes(mv, offset) del_sb_drv, offset = Tdel_rec.from_bytes(mv, offset) del_CP_carry_path, offset = Tdel_rec.from_bytes(mv, offset) del_CP_prop_path, offset = Tdel_rec.from_bytes(mv, offset) del_special_RAM_I, offset = Tdel_rec.from_bytes(mv, offset) del_RAMO_xOBF, offset = Tdel_rec.from_bytes(mv, offset) del_GLBOUT_IO_SEL, offset = Tdel_rec.from_bytes(mv, offset) del_IO_SEL_Q_out, offset = Tdel_rec.from_bytes(mv, offset) del_IO_SEL_Q_in, offset = Tdel_rec.from_bytes(mv, offset) in_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset) out_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset) del_IBF, offset = Tdel_rec.from_bytes(mv, offset) del_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_r_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_IBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_r_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset) del_CP_clkin, offset = Tdel_rec.from_bytes(mv, offset) del_CP_enin, offset = Tdel_rec.from_bytes(mv, offset) del_preplace, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_timing_mod = [] for _ in range(42): rec, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_timing_mod.append(rec) return ExtraTimingDelays( skew_report_del, fix_skew_del, del_rec_0, del_min_route_SB, del_violation_common, del_dummy, del_Hold_D_L, del_Hold_RAM, del_Setup_D_L, del_Setup_RAM, del_Hold_SN_RN, del_Setup_SN_RN, del_Hold_RN_SN, del_Setup_RN_SN, del_bot_couty2, del_bot_glb_couty2, del_bot_SB_couty2, del_bot_pouty2, del_bot_glb_pouty2, del_bot_SB_pouty2, del_left_couty2, del_left_glb_couty2, del_left_SB_couty2, del_left_pouty2, del_left_glb_pouty2, del_left_SB_pouty2, del_inp, del_CPE_out_mux, del_CPE_CP_Q, del_CPE_S_Q, del_CPE_R_Q, del_CPE_D_Q, del_RAM_CLK_DO, del_GLBOUT_sb_big, del_sb_drv, del_CP_carry_path, del_CP_prop_path, del_special_RAM_I, del_RAMO_xOBF, del_GLBOUT_IO_SEL, del_IO_SEL_Q_out, del_IO_SEL_Q_in, in_delayline_per_stage, out_delayline_per_stage, del_IBF, del_OBF, del_r_OBF, del_TOBF_ctrl, del_LVDS_IBF, del_LVDS_OBF, del_LVDS_r_OBF, del_LVDS_TOBF_ctrl, del_CP_clkin, del_CP_enin, del_preplace, del_CPE_timing_mod ), offset def read_IM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(2): # [1..2] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(8): # [1..8] level3 = [] for i4 in range(12): # [1..12] level4 = [] for i5 in range(8): # [0..7] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level4.append(delay) level3.append(level4) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_OM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(8): # [1..8] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(4): # [9..12] level3 = [] for i4 in range(4): # [0..3] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level3.append(delay) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_CPE_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(10): # [0..9] level1 = [] for i2 in range(19): # [1..19] level2 = [] for i3 in range(10): # [1..10] rec, offset = Tdel_rec.from_bytes(mv, offset) level2.append(rec) level1.append(level2) result.append(level1) return result, offset def read_SB_del_rim_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(165): # [-2..162] level1 = [] for i2 in range(4): # [1..4] level2 = [] for i3 in range(12): # [1..12] level3 = [] for i4 in range(5): # [0..4] level4 = [] for i5 in range(8): # [0..7] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level4.append(delay) level3.append(level4) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_Edge_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(165): # [-2..162] level1 = [] for i2 in range(4): # [1..4] level2 = [] for i3 in range(24): # [1..24] level3 = [] for i4 in range(8): # [1..8] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level3.append(delay) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_IO_SEL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(11): # [1..11] level1 = [] for i2 in range(4): # [1..4] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_CLKIN_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(7): level1 = [] for i2 in range(4): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_GLBOUT_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(28): level1 = [] for i2 in range(8): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_PLL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(7): level1 = [] for i2 in range(6): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_Tentry_rec_from_bytes(data: memoryview, offset: int) -> ('Tentry_rec', int): pins_i, pins_val, entry_no = struct.unpack_from('<3h', data, offset) return Tentry_rec(Tpin_pair(pins_i, pins_val), entry_no), offset + 6 def read_Tdel_entry_from_bytes(data: memoryview, offset: int) -> ('Tdel_entry', int): key, edge1, edge2 = struct.unpack_from('<3i', data, offset) time1 = T_delay_tri.from_bytes(data[offset + 12:offset + 24]) time2 = T_delay_tri.from_bytes(data[offset + 24:offset + 36]) return Tdel_entry(key, edge1, edge2, time1, time2), offset + 36 def read_TRAM_del_rec_from_bytes(mv: memoryview, offset: int) -> (TRAM_del_rec, int): iopath = [] for _ in range(3001): entry, offset = read_Tentry_rec_from_bytes(mv, offset) iopath.append(entry) setuphold = [] for _ in range(8001): entry, offset = read_Tentry_rec_from_bytes(mv, offset) setuphold.append(entry) width = [] for _ in range(51): entry, offset = read_Tentry_rec_from_bytes(mv, offset) width.append(entry) del_entry = [] for _ in range(101): entry, offset = read_Tdel_entry_from_bytes(mv, offset) del_entry.append(entry) offset += 2 # alignment added return TRAM_del_rec(iopath, setuphold, width, del_entry), offset def read_IO_SEL_io_coef_from_bytes(mv: memoryview, offset: int) -> (list, int): result = [] for i1 in range(4): # [1..4] row = [] for i2 in range(27): # [1..27] value = struct.unpack_from(' 'Tdel_all_rec': offset = 0 sb_del_tile_arr, offset = read_SB_del_tile_arr_from_bytes(data, offset) im, offset = read_IM_del_tile_arr_from_bytes(data, offset) om, offset = read_OM_del_tile_arr_from_bytes(data, offset) cpe, offset = read_CPE_del_tile_arr_from_bytes(data, offset) sb_del_rim, offset = read_SB_del_rim_arr_from_bytes(data, offset) edge, offset = read_Edge_del_arr_from_bytes(data, offset) io_sel, offset = read_IO_SEL_del_arr_from_bytes(data, offset) clkin, offset = read_CLKIN_del_arr_from_bytes(data, offset) glbout, offset = read_GLBOUT_del_arr_from_bytes(data, offset) pll_del, offset = read_PLL_del_arr_from_bytes(data, offset) fpga_ram_del_1, offset = read_TRAM_del_rec_from_bytes(data, offset) fpga_ram_del_2, offset = read_TRAM_del_rec_from_bytes(data, offset) fpga_ram_del_3, offset = read_TRAM_del_rec_from_bytes(data, offset) io_sel_coef, offset = read_IO_SEL_io_coef_from_bytes(data, offset) timing_delays, offset = ExtraTimingDelays.from_bytes(data, offset) return Tdel_all_rec(sb_del_tile_arr, im, om, cpe, sb_del_rim, edge, io_sel, clkin, glbout, pll_del, fpga_ram_del_1, fpga_ram_del_2, fpga_ram_del_3,io_sel_coef, timing_delays) def decompress_file(input_path, output_path): with open(input_path, 'rb') as f_in: compressed_data = f_in.read() try: decompressed_data = zlib.decompress(compressed_data) except zlib.error as e: print(f"Decompression failed: {e}") return all = Tdel_all_rec.from_bytes(decompressed_data) #print(all.GLBOUT_del_arr) with open(output_path, 'wb') as f_out: f_out.write(decompressed_data) # Example usage #decompress_file("cc_best_eco_dly.dly", "cc_best_eco_dly.bin") #decompress_file("cc_best_lpr_dly.dly", "cc_best_lpr_dly.bin") #decompress_file("cc_best_spd_dly.dly", "cc_best_spd_dly.bin") # #decompress_file("cc_typ_eco_dly.dly", "cc_typ_eco_dly.bin") #decompress_file("cc_typ_lpr_dly.dly", "cc_typ_lpr_dly.bin") #decompress_file("cc_typ_spd_dly.dly", "cc_typ_spd_dly.bin") # #decompress_file("cc_worst_eco_dly.dly", "cc_worst_eco_dly.bin") #decompress_file("cc_worst_lpr_dly.dly", "cc_worst_lpr_dly.bin") decompress_file("cc_worst_spd_dly.dly", "cc_worst_spd_dly.bin") prjpeppercorn-1.12/delay.sh000077500000000000000000000005031514752025000157620ustar00rootroot00000000000000#!/bin/bash set -e ARCHIVE="gatemate-timings-latest.tar.gz" rm -rf delay mkdir -p delay wget -O "$ARCHIVE" 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SPHINXOPTS ?= SPHINXBUILD ?= sphinx-build SOURCEDIR = source BUILDDIR = build PYTHON ?= python3 # Put it first so that "make" without argument is like "make help". help: @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) .PHONY: help Makefile # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). %: Makefile @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) clean: @$(SPHINXBUILD) -M clean "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) $(MAKE) -C clean .PHONY: reqs reqs: $(PYTHON) -m pip install -r source/requirements.txt prjpeppercorn-1.12/docs/README.md000066400000000000000000000002661514752025000165420ustar00rootroot00000000000000Project Peppercorn Documentation =================================== Setting up environment ---------------------- ``` python -m venv .venv source .venv/bin/activate make reqs ``` prjpeppercorn-1.12/docs/source/000077500000000000000000000000001514752025000165575ustar00rootroot00000000000000prjpeppercorn-1.12/docs/source/architecture/000077500000000000000000000000001514752025000212415ustar00rootroot00000000000000prjpeppercorn-1.12/docs/source/architecture/global.rst000066400000000000000000000000371514752025000232330ustar00rootroot00000000000000Global Routing =============== prjpeppercorn-1.12/docs/source/architecture/overview.rst000066400000000000000000000000231514752025000236340ustar00rootroot00000000000000Overview ========= prjpeppercorn-1.12/docs/source/architecture/routing.rst000066400000000000000000000000411514752025000234550ustar00rootroot00000000000000General Routing ================ prjpeppercorn-1.12/docs/source/architecture/tiles.rst000066400000000000000000000000141514752025000231060ustar00rootroot00000000000000Tiles ===== prjpeppercorn-1.12/docs/source/bitstream/000077500000000000000000000000001514752025000205515ustar00rootroot00000000000000prjpeppercorn-1.12/docs/source/bitstream/bitstream.rst000066400000000000000000000053571514752025000233070ustar00rootroot00000000000000Bitstream Format ================= Structure ---------- GateMate bitstreams consist of command blocks. There is no specific header to distinguish them from other files, but each one starts with the CMD_PATH command to set the first die on the chip. .. list-table:: :widths: 20 20 10 35 15 :header-rows: 1 * - Command - Length - CRC1 - Data - CRC2 * - 1 byte - 1 or 2 bytes - 2 bytes - n bytes - 2 bytes Each command byte is followed by data length, and that is one byte, except in the case of the CMD_FRAM command where we used two bytes in little endian format. CRC following it, contains current (header only) CRC and is written in big endian format. CRC is calculated with the so-called CRC-16/ISO-HDLC or CRC-16/X-25 algorithm ( poly 0x1021, init 0xffff, xored output 0xffff). Number of data bytes following is defined in the header. Second CRC contains complete CRC for all previous bytes delivered in block (including header). Some commands require additional bytes after CRC and those are fixed valued, in some cases they are just NOP bytes (0x00), and some require “execute command byte” (0x33) surrounded by multiple NOPs. Command list ------------------ .. list-table:: :widths: 25 5 7 63 :header-rows: 1 * - Command - Hex - Len Size - Description * - **CMD_PLL** - C1 - 1 - PLL configuration * - **CMD_CFGMODE** - C2 - 1 - Change configuration mode * - **CMD_CFGRST** - C3 - 1 - Reset all configuration latches * - **CMD_FLASH** - C5 - 1 - SPI flash access * - **CMD_DLXP** - C6 - 1 - Latch configuration X pattern * - **CMD_DLYP** - C7 - 1 - Latch configuration Y pattern * - **CMD_LXLYS** - C8 - 1 - Latch configuration X,Y location * - **CMD_ACLCU** - C9 - 1 - Address counter * - **CMD_DLCU** - CA - 1 - Configuration data * - **CMD_DRXP** - CC - 1 - RAM configuration X pattern * - **CMD_RXRYS** - CE - 1 - RAM configuration X,Y location * - **CMD_FRAM** - D2 - 2 - Block ram fill data * - **CMD_SERDES** - D7 - 1 - Serdes configuration * - **CMD_D2D** - D8 - 1 - Enable/disable die-to-die direction * - **CMD_PATH** - D9 - 1 - Enable forwarding configuration to die * - **CMD_JUMP** - DA - 1 - Jump to address in configuration * - **CMD_CHG_STATUS** - DB - 1 - FPGA configuration change * - **CMD_WAIT_PLL** - DC - 1 - Wait for PLL lock * - **CMD_SPLL** - DD - 1 - Select PLLs * - **CMD_SLAVE_MODE** - DE - 1 - Set SPI slave mode prjpeppercorn-1.12/docs/source/bitstream/commands.rst000066400000000000000000000237111514752025000231100ustar00rootroot00000000000000Bitstream Commands =================== CMD_PATH --------- To be able to specify die to program it is required to properly forward JTAG to specific direction and set mode accordingly. To program first die we use 0x10 value for this command and it first one to be executed. .. list-table:: :widths: 10 40 :header-rows: 1 * - Bit - Description * - 0 - Reset to default state * - 1 - Set to path to top * - 2 - Set to path to right * - 3 - Enable forwarding mode * - 4 - Enable programming mode .. warning:: This command have data after payload, and it consists of 9 bytes ``0x00 0x00 0x00 0x00 0x33 0x00 0x00 0x00 0x00`` and it is used to execute this JTAG command. CMD_LXLYS ---------- Before sending any configuration data it is required to specify location of a specific TILE, and for latch configuration that configures all logic and IO blocks it is this command. .. list-table:: :widths: 10 10 40 :header-rows: 1 * - Byte - Range - Description * - 0 - 0..81 - X location (column) * - 1 - 0..65 - Y location (row) CMD_DLXP --------- Alternate way of setting location for configuration data is by setting pattern for both column and row. This commands sets row pattern and each bit represent one of the rows. There are total of 9 bytes used in payload. CMD_DLYP --------- This commands sets column pattern and each bit represent one of the columns. There are total of 11 bytes used in payload. CMD_DLCU --------- After location is set with one of previous commands, it is required to set a data payload. For configuring logic and IO tiles data payload is 112 bytes max. Payload can be smaller, but programming will act as it is zero padded till full size. This command is also used to configure RAM blocks, there we expect 27 bytes of payload maximum. CMD_RXRYS ---------- Similar to **CMD_LXLYS** command, there is a command to specify RAM block to program. .. list-table:: :widths: 10 10 40 :header-rows: 1 * - Byte - Range - Description * - 0 - 0..3 - X location (column) * - 1 - 0..7 - Y location (row) CMD_DRXP --------- As alternative to **CMD_RXRYS** command we can use this one to specify a pattern, note that each bit of one byte payload is used to set one of 4 columns. CMD_CFGRST ----------- Resets all configuration latches to value of a byte from payload, except active SPI controller and configuration PLL. CMD_ACLCU ---------- Defines start address for following block memory init data. .. list-table:: :widths: 10 40 :header-rows: 1 * - Byte - Description * - 0 - addr[ 7:0] * - 1 - addr[15:8] CMD_FRAM --------- Payload contains up to 5120 bytes of RAM content. Start address must be previously defined by **CMD_ACLCU** command. And RAM block must be selected with **CMD_RXRYS** or **CMD_DRXP** command. CMD_PLL -------- .. list-table:: :widths: 10 40 :header-rows: 1 * - Byte - Description * - 0 - PLL Config data 0 * - 1 - PLL Config data 1 * - 2 - PLL Config data 2 * - 3 - PLL Config data 3 * - 4 - PLL Config data 4 * - 5 - PLL Config data 5 * - 6 - PLL Config data 6 * - 7 - PLL Config data 7 * - 8 - PLL Config data 8 * - 9 - PLL Config data 9 * - 10 - PLL Config data 10 * - 11 - PLL Config data 11 * - 12 - Config data for clock matrix CLKIN PLL0 * - 13 - Config data for clock matrix CLKIN PLL1 * - 14 - Config data for clock matrix CLKIN PLL2 * - 15 - Config data for clock matrix CLKIN PLL3 * - 16 - Config data for clock matrix CLKMUX PLL0 byte 0 * - 17 - Config data for clock matrix CLKMUX PLL0 byte 1 * - 18 - Config data for clock matrix CLKMUX PLL1 byte 0 * - 19 - Config data for clock matrix CLKMUX PLL1 byte 1 * - 20 - Config data for clock matrix CLKMUX PLL2 byte 0 * - 21 - Config data for clock matrix CLKMUX PLL2 byte 1 * - 22 - Config data for clock matrix CLKMUX PLL3 byte 0 * - 23 - Config data for clock matrix CLKMUX PLL3 byte 1 .. warning:: This command have data after payload, and it consists of 6 NOP bytes ``0x00 0x00 0x00 0x00 0x00 0x00``. CMD_SPLL --------- .. list-table:: :widths: 10 40 :header-rows: 1 * - Bit - Description * - 0 - Write config for PLL0 * - 1 - Write config for PLL1 * - 2 - Write config for PLL2 * - 3 - Write config for PLL2 * - 4 - Configuration set for PLL0 * - 5 - Configuration set for PLL1 * - 6 - Configuration set for PLL2 * - 7 - Configuration set for PLL3 There are two configuration sets, that could be set for each PLL. .. warning:: Value 0x00 is special case and it is used for writing to all 4 PLLs, same as 0x0F CMD_WAIT_PLL ------------- Wait for PLL lock. .. list-table:: :widths: 10 40 :header-rows: 1 * - Bit - Description * - 0 - Wait for PLL0 * - 1 - Wait for PLL1 * - 2 - Wait for PLL2 * - 3 - Wait for PLL3 CMD_CHG_STATUS --------------- .. list-table:: :widths: 10 10 40 :header-rows: 1 * - Byte - Bit - Description * - 0 - 0 - Configuration done * - - 1 - Stop configuration * - - 2 - Reconfiguration enable * - - 3 - Enable CPE configuration * - - 4 - CPE reset * - - 5 - Fill RAM enable * - - 6..7 - Unused * - 1 - 0..3 - Configuration mode * - - 4 - Select configuration mode * - - 5..7 - Unused * - 2 - 0 - Enable GPIO bank S1 * - - 1 - Enable GPIO bank S2 * - - 2 - Unused * - - 3 - Enable GPIO bank S3 (CFG) * - - 4 - Enable GPIO bank E1 * - - 5 - Enable GPIO bank E2 * - - 6..7 - Unused * - 3 - 0 - Enable GPIO bank N1 * - - 1 - Enable GPIO bank N2 * - - 2..3 - Unused * - - 4 - Enable GPIO bank W1 * - - 5 - Enable GPIO bank W2 * - - 6..7 - Unused * - 4 - 0 - PLL0 PLL_RST_N * - - 1 - PLL0 PLL_EN * - - 2 - PLL0 PLL_AUTN * - - 3 - PLL0 SET_SEL * - - 4 - PLL0 USR_SET * - - 5 - PLL0 USR_CLK_REF * - - 6 - PLL0 CLK_OUT_EN * - - 7 - PLL0 LOCK_REQ * - 5 - 0..2 - PLL0 AUTN_CT_I[2:0], should be 001 * - - 3 - PLL0 CLK180_DOUB * - - 4 - PLL0 CLK270_DOUB * - - 5..6 - Unused * - - 7 - PLL0 USR_CLK_OUT * - 6 - 0 - PLL1 PLL_RST_N * - - 1 - PLL1 PLL_EN * - - 2 - Unused * - - 3 - PLL1 SET_SEL * - - 4 - PLL1 USR_SET * - - 5 - PLL1 USR_CLK_REF * - - 6 - PLL1 CLK_OUT_EN * - - 7 - PLL1 LOCK_REQ * - 7 - 0..2 - Unused * - - 3 - PLL1 CLK180_DOUB * - - 4 - PLL1 CLK270_DOUB * - - 5..6 - Unused * - - 7 - PLL1 USR_CLK_OUT * - 8 - 0 - PLL2 PLL_RST_N * - - 1 - PLL2 PLL_EN * - - 2 - Unused * - - 3 - PLL2 SET_SEL * - - 4 - PLL2 USR_SET * - - 5 - PLL2 USR_CLK_REF * - - 6 - PLL2 CLK_OUT_EN * - - 9 - PLL2 LOCK_REQ * - 7 - 0..2 - Unused * - - 3 - PLL2 CLK180_DOUB * - - 4 - PLL2 CLK270_DOUB * - - 5..6 - Unused * - - 7 - PLL2 USR_CLK_OUT * - 10 - 0 - PLL3 PLL_RST_N * - - 1 - PLL3 PLL_EN * - - 2 - Unused * - - 3 - PLL3 SET_SEL * - - 4 - PLL3 USR_SET * - - 5 - PLL3 USR_CLK_REF * - - 6 - PLL3 CLK_OUT_EN * - - 9 - PLL3 LOCK_REQ * - 11 - 0..2 - Unused * - - 3 - PLL3 CLK180_DOUB * - - 4 - PLL3 CLK270_DOUB * - - 5..6 - Unused * - - 7 - PLL3 USR_CLK_OUT .. warning:: This command have data after payload, and it consists of 9 bytes ``0x00 0x00 0x00 0x00 0x33 0x00 0x00 0x00 0x00`` and it is used to execute this JTAG command. CMD_D2D -------- .. list-table:: :widths: 10 40 :header-rows: 1 * - Bit - Description * - 0 - Enable D2D on north * - 1 - Enable D2D on east * - 2 - Enable D2D on south * - 3 - Enable D2D on west CMD_SERDES ----------- CMD_JUMP -------- Jump to address in SPI flash. .. list-table:: :widths: 10 40 :header-rows: 1 * - Byte - Description * - 0 - addr[7:0] * - 1 - addr[15:8] * - 2 - addr[23:16] * - 3 - addr[31:24] .. warning:: This command requires data after payload, and it consists of 2 NOP bytes ``0x00 0x00``. CMD_CFGMODE ------------ .. list-table:: :widths: 10 10 40 :header-rows: 1 * - Byte - Bit - Description * - 0 - - Number of CRC retries * - 1 - - CRC error behaviour (0: checked, 1: ignored, 2: unused) * - 2 - 0..1 - SPI bus IO width for `cmd` (0: single, 1: dual, 3: quad) * - - 2..3 - SPI bus IO width for `addr` (0: single, 1: dual, 3: quad) * - - 4..5 - SPI bus IO width for `mode` (0: single, 1: dual, 3: quad) * - - 6..7 - SPI bus IO width for `txdata` (0: single, 1: dual, 3: quad) * - 3 - 0..1 - SPI bus IO width for `rxdata` (0: single, 1: dual, 3: quad) * - - 2..7 - Number of dummy cycles between `addr` and `rxdata` * - 4 - - Flash `addr` field length * - 5 - - Flash `READ` command .. warning:: This command have data after payload, and it consists of 3 NOP bytes ``0x00 0x00 0x00``. CMD_FLASH ---------- CMD_SLAVE_MODE --------------- .. warning:: This command have data after payload, and it consists of 3 NOP bytes ``0x00 0x00 0x00``. prjpeppercorn-1.12/docs/source/conf.py000066400000000000000000000021171514752025000200570ustar00rootroot00000000000000# Configuration file for the Sphinx documentation builder. # # For the full list of built-in configuration values, see the documentation: # https://www.sphinx-doc.org/en/master/usage/configuration.html # -- Project information ----------------------------------------------------- # https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information project = 'Project Peppercorn' copyright = '2024, YosysHQ' author = 'YosysHQ' # -- General configuration --------------------------------------------------- # https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration extensions = ['sphinx_rtd_theme'] templates_path = ['_templates'] exclude_patterns = [] # -- Options for HTML output ------------------------------------------------- # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output html_theme = 'sphinx_rtd_theme' html_theme_options = { "collapse_navigation": True, "sticky_navigation": True, "includehidden": True, "navigation_depth": 4, "titles_only": False } html_static_path = ['_static'] prjpeppercorn-1.12/docs/source/index.rst000066400000000000000000000005171514752025000204230ustar00rootroot00000000000000Welcome to Project Peppercorn ============================== .. toctree:: :maxdepth: 2 :caption: Architecture architecture/overview.rst architecture/tiles.rst architecture/routing.rst architecture/global.rst .. toctree:: :maxdepth: 2 :caption: Bitstream bitstream/bitstream.rst bitstream/commands.rst prjpeppercorn-1.12/docs/source/requirements.txt000066400000000000000000000000311514752025000220350ustar00rootroot00000000000000sphinx sphinx_rtd_theme prjpeppercorn-1.12/environment.sh000066400000000000000000000003061514752025000172260ustar00rootroot00000000000000#!/usr/bin/env bash SCRIPT_PATH=$(readlink -f "${BASH_SOURCE:-$0}") SCRIPT_DIR=$(dirname "$SCRIPT_PATH") PYTHONLIBS_DIR="${SCRIPT_DIR}/gatemate" export PYTHONPATH="${PYTHONLIBS_DIR}:${PYTHONPATH}" prjpeppercorn-1.12/gatemate/000077500000000000000000000000001514752025000161165ustar00rootroot00000000000000prjpeppercorn-1.12/gatemate/__init__.py000066400000000000000000000000001514752025000202150ustar00rootroot00000000000000prjpeppercorn-1.12/gatemate/chip.py000066400000000000000000000610461514752025000174220ustar00rootroot00000000000000# # prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools # # Copyright (C) 2024 The Project Peppercorn Authors. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import die import os from die import Die, Location, Connection from dataclasses import dataclass from typing import List, Dict from timing import decompress_timing DATABASE_VERSION = 1.12 @dataclass(eq=True, order=True) class Pad: x : int y : int name : str bel : str function : str bank : int flags : int ddr : Location @dataclass class Bank: die : str bank: str @dataclass class TimingDelay: min : int typ : int max : int def __add__(self, other): if not isinstance(other, TimingDelay): return NotImplemented return TimingDelay(self.min + other.min, self.typ + other.typ, self.max + other.max) def __sub__(self, other): if not isinstance(other, TimingDelay): return NotImplemented return TimingDelay(self.min - other.min, self.typ - other.typ, self.max - other.max) @dataclass class Timing: rise : TimingDelay fall : TimingDelay def __add__(self, other): if not isinstance(other, Timing): return NotImplemented return Timing(self.rise + other.rise, self.fall + other.fall) def __sub__(self, other): if not isinstance(other, Timing): return NotImplemented return Timing(self.rise - other.rise, self.fall - other.fall) @dataclass class Chip: name : str die_width : int die_height : int dies : Dict[str,Die] packages: Dict[str,Dict[str, List[Bank]]] not_exist: Dict[str,List[str]] def max_row(self): return self.die_height * die.num_rows() - 3 def max_col(self): return self.die_width * die.num_cols() - 3 def get_tile_types(self,x,y): x_pos = (x + 2) % die.num_cols() - 2 y_pos = (y + 2) % die.num_rows() - 2 return die.get_tile_types(x_pos,y_pos) def get_tile_type(self,x,y): x_pos = (x + 2) % die.num_cols() - 2 y_pos = (y + 2) % die.num_rows() - 2 return die.get_tile_type(x_pos,y_pos) def get_tile_info(self,x,y): x_pos = (x + 2) % die.num_cols() - 2 y_pos = (y + 2) % die.num_rows() - 2 x_die = (x + 2) // die.num_cols() y_die = (y + 2) // die.num_rows() die_num = x_die + y_die * self.die_width return die.get_tile_info(die_num, x_pos, y_pos) def create_conn(self, conn, src_x,src_y, src, dst_x, dst_y, dst, delay="del_dummy"): key_val = f"{src_x}/{src_y}/{src}" key = Connection(src_x, src_y, src, "", False) item = Connection(dst_x, dst_y, dst, delay,True) if key_val not in conn: conn[key_val] = list() conn[key_val].append(key) conn[key_val].append(item) def get_connections(self): conn = dict() for d in self.dies.values(): d.create_in_die_connections(conn) if self.name=="CCGM1A2": for x in range(27, 163): if x == 27: # only 7 signals only from bottom of upper to top of lower p_range = range(2, 9) else: p_range = range(1, 9) for p in p_range: plane = f"{p:02d}" offset_y = 132 + 2 sbb_y = -1 + offset_y if x % 2 == 1 else 0 + offset_y sbt_y = 129 if x % 2 == 1 else 130 self.create_conn(conn, x, sbb_y, f"{die.get_sb_type(x,sbb_y-offset_y)}.P{plane}.Y4", x, sbt_y, f"{die.get_sb_type(x,sbt_y)}.P{plane}.D2_4_D2D", delay="del_D2D") if x > 27 and (x != 28 or p > 4): # no connection for 27, and for 28 just 4 signals from lower to upper if x > 160: self.create_conn(conn, x, sbt_y, f"{die.get_sb_type(x,sbt_y)}.P{plane}.Y2", x, sbb_y, f"{die.get_sb_type(x,sbb_y-offset_y)}.P{plane}.D2_2_D2D", delay="del_D2D") else: self.create_conn(conn, x, 131, f"TES.MDIE2.P{p}", x, sbb_y, f"{die.get_sb_type(x,sbb_y-offset_y)}.P{plane}.D2_2_D2D", delay="del_D2D") return conn.items() def get_packages(self): return self.packages def get_bank_number(self, bank): match bank: case 'N1' : return 0 case 'N2' : return 1 case 'E1' : return 2 case 'E2' : return 3 case 'W1' : return 4 case 'W2' : return 5 case 'S1' : return 6 case 'S2' : return 7 case 'S3' : return 8 case _ : return -1 def get_package_pads(self, package): pads = [] pkg = self.packages[package] not_exist = self.not_exist[package] for name, banks in pkg.items(): for bank in banks: for p in ["A","B"]: for num in range(9): d = self.dies[bank.die] ddr = d.ddr_i[bank.bank] loc = d.io_pad_names[bank.bank][p][num] pad_name = f"IO_{name}_{p}{num}" flags = 0 # mark clock sources if bank.bank == "W2" and p == "A" and num in [5,6,7,8]: flags = 8-num+1 # will be 1-4 for different clock sources if pad_name not in not_exist: pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"IOSEL","",self.get_bank_number(bank.bank),flags,ddr)) return pads CCGM1_DEVICES = { "CCGM1A1": Chip("CCGM1A1", 1, 1, { "1A" : Die("1A", 0, 0) }, { "FBGA324" : { "EA" : [ Bank("1A", "N1") ], "EB" : [ Bank("1A", "N2") ], "NA" : [ Bank("1A", "E1") ], "NB" : [ Bank("1A", "E2") ], "WA" : [ Bank("1A", "S3") ], "WB" : [ Bank("1A", "S1") ], "WC" : [ Bank("1A", "S2") ], "SA" : [ Bank("1A", "W1") ], "SB" : [ Bank("1A", "W2") ] } }, { # non existing pins "FBGA324" : [] }), "CCGM1A2": Chip("CCGM1A2", 1, 2, { "1A" : Die("1A", 0, 0), "1B" : Die("1B", 0, 1) }, { "FBGA324" : { "EA" : [ Bank("1B", "N1") ], "EB" : [ Bank("1B", "N2") ], "NA" : [ Bank("1A", "E1"), Bank("1B", "E1") ], "NB" : [ Bank("1A", "E2") ], "WA" : [ Bank("1A", "S3") ], "WB" : [ Bank("1A", "N1"), Bank("1B", "S1") ], "WC" : [ Bank("1A", "S2") ], "SA" : [ Bank("1A", "W1") ], "SB" : [ Bank("1A", "W2"), Bank("1B", "W2") ] } }, { # non existing pins "FBGA324" : [] }), "CCGM1A4": Chip("CCGM1A4", 2, 2, { "1A" : Die("1A", 0, 0), "1B" : Die("1B", 0, 1), "2A" : Die("2A", 1, 0), "2B" : Die("2B", 1, 1) }, { "FBGA324" : { "EA" : [ Bank("1B", "N1") ], "EB" : [ Bank("1B", "N2") ], "NA" : [ Bank("1A", "E1"), Bank("1B", "E1"), Bank("2A", "E1"), Bank("2B", "E1") ], "NB" : [ Bank("2A", "N1"), Bank("2B", "S1") ], "WA" : [ Bank("1A", "S3") ], "WB" : [ Bank("1A", "N1"), Bank("1B", "S1") ], "WC" : [ Bank("1A", "S2") ], "SA" : [ Bank("1A", "W1") ], "SB" : [ Bank("1A", "W2"), Bank("1B", "W2"), Bank("2A", "W2"), Bank("2B", "W2") ] } }, { # non existing pins "FBGA324" : [ "IO_SB_A0","IO_SB_B0", "IO_SB_A1","IO_SB_B1", "IO_SB_A2","IO_SB_B2", "IO_SB_A3","IO_SB_B3" ] }), } def get_version(): return DATABASE_VERSION def get_all_devices(): return CCGM1_DEVICES def get_device(name): return CCGM1_DEVICES[name] def convert_delay(d): return Timing(TimingDelay(d.rise.min, d.rise.typ, d.rise.max), TimingDelay(d.fall.min, d.fall.typ, d.fall.max)) def convert_delay_val(d): return Timing(TimingDelay(d.min, d.typ, d.max), TimingDelay(d.min, d.typ, d.max)) def convert_ram_delay(d): return Timing(TimingDelay(d.time1.min, d.time1.typ, d.time1.max), TimingDelay(d.time2.min, d.time2.typ, d.time2.max)) def check_dly_available(): current_dir = os.path.dirname(os.path.abspath(__file__)) return os.path.exists(os.path.join(current_dir, "..", "delay", "cc_worst_spd_dly.dly")) def get_timings(name): val = dict() current_dir = os.path.dirname(os.path.abspath(__file__)) timing_data = decompress_timing(os.path.join(current_dir, "..", "delay", f"cc_{name}_dly.dly")) for i1 in range(4): # [1..4] for i2 in range(8): # [1..8] for i3 in range(4): # [1..4] for i4 in range(12): # [1..12] for i5 in range(5): # [0..4] for i6 in range(8): # [0..7] d = timing_data.SB_del_tile_arr[i1][i2][i3][i4][i5][i6] if d.rise.min == 123456: # not connected continue x = i2+1 y = i3+1 y = 2*y if (x % 2 == 0) else 2*y-1 name = f"sb_del_t{i1+1}_x{x}_y{y}_p{i4+1}_d{i5}_s{i6}" val[name] = convert_delay(d) for i1 in range(2): # [1..2] for i2 in range(8): # [1..8] for i3 in range(8): # [1..8] for i4 in range(12): # [1..12] for i5 in range(8): # [0..7] d = timing_data.IM_del_tile_arr[i1][i2][i3][i4][i5] if d.rise.min == 123456: # not connected continue name = f"im_x{i2+1}_y{i3+1}_p{i4+1}_d{i5}_path{i1+1}" val[name] = convert_delay(d) for i1 in range(8): # [1..8] for i2 in range(8): # [1..8] for i3 in range(4): # [9..12] for i4 in range(4): # [0..3] d = timing_data.OM_del_tile_arr[i1][i2][i3][i4] if d.rise.min == 123456: # not connected continue name = f"om_x{i1+1}_y{i2+1}_p{i3+9}_d{i4}" val[name] = convert_delay(d) cnt_ccy1 = 1 cnt_cpy1 = 1 cnt_pcy1 = 1 cnt_ppy1 = 1 for i1 in range(10): # [0..9] for i2 in range(19): # [1..19] for i3 in range(10): # [1..10] d = timing_data.CPE_del_tile_arr[i1][i2][i3] if d.name == "CPE": # not used continue # These are wrong names in timing database # and need fixing if d.name == "_ROUTING_CINY2_COUTY": d.name = "_ROUTING_CINY2_COUTY2" if d.name == "_ROUTING_PINY2_POUTY": d.name = "_ROUTING_PINY2_POUTY2" if d.name == "_ROUTING_CINY1_COUTY": if cnt_ccy1 == 1: d.name = "_ROUTING_CINY1_COUTY1" cnt_ccy1 = 2 else: d.name = "_ROUTING_CINY1_COUTY2" cnt_ccy1 = 1 if d.name == "_ROUTING_CINY1_POUTY": if cnt_cpy1 == 1: d.name = "_ROUTING_CINY1_POUTY1" cnt_cpy1 = 2 else: d.name = "_ROUTING_CINY1_POUTY2" cnt_cpy1 = 1 if d.name == "_ROUTING_PINY1_COUTY": if cnt_pcy1 == 1: d.name = "_ROUTING_PINY1_COUTY1" cnt_pcy1 = 2 else: d.name = "_ROUTING_PINY1_COUTY2" cnt_pcy1 = 1 if d.name == "_ROUTING_PINY1_POUTY": if cnt_ppy1 == 1: d.name = "_ROUTING_PINY1_POUTY1" cnt_ppy1 = 2 else: d.name = "_ROUTING_PINY1_POUTY2" cnt_ppy1 = 1 val[d.name] = convert_delay(d.val) for i1 in range(165): # [-2..162] for i2 in range(4): # [1..4] for i3 in range(12): # [1..12] for i4 in range(5): # [0..4] for i5 in range(8): # [0..7] d = timing_data.SB_del_rim_arr[i1][i2][i3][i4][i5] if d.rise.min == 123456: # not connected continue name = f"sb_rim_xy{i1-2}_s{i2+1}_p{i3+1}_d{i4}_s{i5}" val[name] = convert_delay(d) inputs_all = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3', 'SB_P1', 'SB_P2', 'SB_P3', 'SB_P4', 'SB_P5', 'SB_P6', 'SB_P7', 'SB_P8'] inputs_left_bot = [ 'MDIE_P1', 'MDIE_P2', 'MDIE_P3', 'MDIE_P4', 'MDIE_P5', 'MDIE_P6', 'MDIE_P7', 'MDIE_P8' ] inputs_right_top = [ 'COUTX', 'COUTY1', 'COUTY2', 'POUTX', 'POUTY1', 'POUTY2', 'RAM_O1', 'RAM_O2' ] inputs_bot = [ 'P_CINY1', 'P_CINY2', 'P_PINY1', 'P_PINY2'] outputs_right_top = [ 'MDIE_P1', 'MDIE_P2', 'MDIE_P3', 'MDIE_P4', 'MDIE_P5', 'MDIE_P6', 'MDIE_P7', 'MDIE_P8' ] outputs_left_bot = [ 'CINX', 'CINY1', 'CINY2', 'PINX', 'PINY1', 'PINY2', 'DUMMY', 'DUMMY'] for i1 in range(165): # [-2..162] for i2 in range(4): # [1..4] inputs = inputs_all outputs = [] match i2: case 0 | 1 : # right, top inputs += inputs_right_top inputs += [ 'DUMMY', 'DUMMY', 'DUMMY' ,'DUMMY'] outputs += outputs_right_top case 2: # left inputs += inputs_left_bot inputs += [ 'DUMMY', 'DUMMY', 'DUMMY' ,'DUMMY'] outputs += outputs_left_bot case 3: # bottom inputs += inputs_left_bot + inputs_bot outputs += outputs_left_bot for i3 in range(24): # [1..24] for i4 in range(8): # [1..8] d = timing_data.Edge_del_arr[i1][i2][i3][i4] if d.rise.min == 123456: # not connected continue name = f"edge_xy{i1-2}_s{i2+1}_{inputs[i3]}_{outputs[i4]}" val[name] = convert_delay(d) inputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3','OUT1','OUT2','OUT3','OUT4','GPIO_IN','RESET','DDR'] outputs = [ 'IN1','IN2','GPIO_OUT','GPIO_EN' ] for i1 in range(11): # [1..11] for i2 in range(4): # [1..4] d = timing_data.IO_SEL_del_arr[i1][i2] if d.rise.min == 123456: # not connected continue name = f"io_sel_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) inputs = [ 'CLK0','CLK1','CLK2','CLK3','SER_CLK','SPI_CLK','JTAG_CLK'] outputs = [ 'CLK_REF0','CLK_REF1','CLK_REF2','CLK_REF3' ] for i1 in range(7): # [1..7] for i2 in range(4): # [1..4] d = timing_data.CLKIN_del_arr[i1][i2] if d.rise.min == 123456: # not connected continue name = f"clkin_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) inputs = [ 'CLK0_0','CLK90_0','CLK180_0','CLK270_0','CLK_REF_OUT0', 'CLK0_1','CLK90_1','CLK180_1','CLK270_1','CLK_REF_OUT1', 'CLK0_2','CLK90_2','CLK180_2','CLK270_2','CLK_REF_OUT2', 'CLK0_3','CLK90_3','CLK180_3','CLK270_3','CLK_REF_OUT3', 'USR_GLB0','USR_GLB1','USR_GLB2','USR_GLB3', 'USR_FB0', 'USR_FB1', 'USR_FB2', 'USR_FB3' ] outputs = [ 'GLB0','GLB1','GLB2','GLB3', 'CLK_FB0','CLK_FB1','CLK_FB2','CLK_FB3'] for i1 in range(28): # [1..28] for i2 in range(8): # [1..8] d = timing_data.GLBOUT_del_arr[i1][i2] if d.rise.min == 123456: # not connected continue name = f"glbout_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) # All feedback delays calculated are same, we just take one val["glbout_FEEDBACK_delay"] = val["glbout_CLK0_0_CLK_FB0"] - val["glbout_CLK0_0_GLB0"] inputs = ['clk_ref_i','clock_core0_i','adpll_enable_i','adpll_status_read_i','locked_steady_reset_i','autn_en_i','reset_n_i'] outputs = ['clk_core0_o','clk_core90_o','clk_core180_o','clk_core270_o', 'pll_locked_o', 'pll_locked_steady_o'] for i1 in range(7): # [1..7] for i2 in range(6): # [1..6] d = timing_data.PLL_del_arr[i1][i2] if d.rise.min == 123456: # not connected continue name = f"pll_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) for i in range(1,15): item = timing_data.FPGA_ram_del_1.del_entry[i] name = "RAM_NOECC_" match item.key: case 1: name += f"IOPATH_{i}" case 2: name += f"SETUPHOLD_{i-3}" case 4: name += "WIDTH" val[name] = convert_ram_delay(timing_data.FPGA_ram_del_1.del_entry[i]) val["RAM_NOECC_IOPATH_4"] = Timing(TimingDelay(0,0,0), TimingDelay(0,0,0)) for i in range(1,16): item = timing_data.FPGA_ram_del_2.del_entry[i] name = "RAM_ECC_" match item.key: case 1: name += f"IOPATH_{i}" case 2: name += f"SETUPHOLD_{i-4}" case 4: name += "WIDTH" val[name] = convert_ram_delay(timing_data.FPGA_ram_del_2.del_entry[i]) for i in range(1,16): item = timing_data.FPGA_ram_del_3.del_entry[i] name = "RAM_REG_" match item.key: case 1: name += f"IOPATH_{i}" case 2: name += f"SETUPHOLD_{i-4}" case 4: name += "WIDTH" val[name] = convert_ram_delay(timing_data.FPGA_ram_del_3.del_entry[i]) #val["del_rec_0"] = convert_delay(timing_data.timing_delays.del_rec_0.val) val["del_min_route_SB"] = convert_delay(timing_data.timing_delays.del_min_route_SB.val) val["del_violation_common"] = convert_delay_val(timing_data.timing_delays.del_violation_common.val) val["del_dummy"] = convert_delay(timing_data.timing_delays.del_dummy.val) val["del_Hold_D_L"] = convert_delay_val(timing_data.timing_delays.del_Hold_D_L.val) val["del_Setup_D_L"] = convert_delay_val(timing_data.timing_delays.del_Setup_D_L.val) val["del_Hold_RAM"] = convert_delay_val(timing_data.timing_delays.del_Hold_RAM.val) val["del_Setup_RAM"] = convert_delay_val(timing_data.timing_delays.del_Setup_RAM.val) val["del_Hold_SN_RN"] = convert_delay_val(timing_data.timing_delays.del_Hold_SN_RN.val) val["del_Setup_SN_RN"] = convert_delay_val(timing_data.timing_delays.del_Setup_SN_RN.val) val["del_Hold_RN_SN"] = convert_delay_val(timing_data.timing_delays.del_Hold_RN_SN.val) val["del_Setup_RN_SN"] = convert_delay_val(timing_data.timing_delays.del_Setup_RN_SN.val) val["del_bot_couty2"] = convert_delay(timing_data.timing_delays.del_bot_couty2.val) val["del_bot_glb_couty2"] = convert_delay(timing_data.timing_delays.del_bot_glb_couty2.val) val["del_bot_SB_couty2"] = convert_delay(timing_data.timing_delays.del_bot_SB_couty2.val) val["del_bot_pouty2"] = convert_delay(timing_data.timing_delays.del_bot_pouty2.val) val["del_bot_glb_pouty2"] = convert_delay(timing_data.timing_delays.del_bot_glb_pouty2.val) val["del_bot_SB_pouty2"] = convert_delay(timing_data.timing_delays.del_bot_SB_pouty2.val) val["del_left_couty2"] = convert_delay(timing_data.timing_delays.del_left_couty2.val) val["del_left_glb_couty2"] = convert_delay(timing_data.timing_delays.del_left_glb_couty2.val) val["del_left_SB_couty2"] = convert_delay(timing_data.timing_delays.del_left_SB_couty2.val) val["del_left_pouty2"] = convert_delay(timing_data.timing_delays.del_left_pouty2.val) val["del_left_glb_pouty2"] = convert_delay(timing_data.timing_delays.del_left_glb_pouty2.val) val["del_left_SB_pouty2"] = convert_delay(timing_data.timing_delays.del_left_SB_pouty2.val) val["del_CPE_CP_Q"] = convert_delay(timing_data.timing_delays.del_CPE_CP_Q.val) val["del_CPE_S_Q"] = convert_delay(timing_data.timing_delays.del_CPE_S_Q.val) val["del_CPE_R_Q"] = convert_delay(timing_data.timing_delays.del_CPE_R_Q.val) val["del_CPE_D_Q"] = convert_delay(timing_data.timing_delays.del_CPE_D_Q.val) val["del_RAM_CLK_DO"] = convert_delay(timing_data.timing_delays.del_RAM_CLK_DO.val) val["del_GLBOUT_sb_big"] = convert_delay(timing_data.timing_delays.del_GLBOUT_sb_big.val) val["del_sb_drv"] = convert_delay(timing_data.timing_delays.del_sb_drv.val) val["del_CP_carry_path"] = convert_delay(timing_data.timing_delays.del_CP_carry_path.val) val["del_CP_prop_path"] = convert_delay(timing_data.timing_delays.del_CP_prop_path.val) val["del_special_RAM_I"] = convert_delay(timing_data.timing_delays.del_special_RAM_I.val) val["del_RAMO_xOBF"] = convert_delay(timing_data.timing_delays.del_RAMO_xOBF.val) val["del_GLBOUT_IO_SEL"] = convert_delay(timing_data.timing_delays.del_GLBOUT_IO_SEL.val) val["del_IO_SEL_Q_out"] = convert_delay(timing_data.timing_delays.del_IO_SEL_Q_out.val) val["del_IO_SEL_Q_in"] = convert_delay(timing_data.timing_delays.del_IO_SEL_Q_in.val) val["in_delayline_per_stage"] = convert_delay(timing_data.timing_delays.in_delayline_per_stage.val) val["out_delayline_per_stage"] = convert_delay(timing_data.timing_delays.out_delayline_per_stage.val) val["del_IBF"] = convert_delay(timing_data.timing_delays.del_IBF.val) val["del_OBF"] = convert_delay(timing_data.timing_delays.del_OBF.val) val["del_r_OBF"] = convert_delay(timing_data.timing_delays.del_r_OBF.val) val["del_TOBF_ctrl"] = convert_delay(timing_data.timing_delays.del_TOBF_ctrl.val) val["del_LVDS_IBF"] = convert_delay(timing_data.timing_delays.del_LVDS_IBF.val) val["del_LVDS_OBF"] = convert_delay(timing_data.timing_delays.del_LVDS_OBF.val) val["del_ddel_LVDS_r_OBFummy"] = convert_delay(timing_data.timing_delays.del_LVDS_r_OBF.val) val["del_LVDS_TOBF_ctrl"] = convert_delay(timing_data.timing_delays.del_LVDS_TOBF_ctrl.val) val["del_CP_clkin"] = convert_delay(timing_data.timing_delays.del_CP_clkin.val) val["del_CP_enin"] = convert_delay(timing_data.timing_delays.del_CP_enin.val) val["del_D2D"] = Timing(TimingDelay(1000,1000,1000), TimingDelay(1000,1000,1000)) #val["del_preplace"] = convert_delay(timing_data.timing_delays.del_preplace.val) cnt_comb_cy1 = 1 cnt_comb_py1 = 1 for i1 in range(42): # [1..42] d = timing_data.timing_delays.del_CPE_timing_mod[i1] if d.name == "": # not used continue if d.name == "comb12_compout_COUTY": if cnt_comb_cy1 == 1: d.name = "comb12_compout_COUTY1" cnt_comb_cy1 = 2 else: d.name = "comb12_compout_COUTY2" cnt_comb_cy1 = 1 if d.name == "comb12_compout_POUTY": if cnt_comb_py1 == 1: d.name = "comb12_compout_POUTY1" cnt_comb_py1 = 2 else: d.name = "comb12_compout_POUTY2" cnt_comb_py1 = 1 val[d.name] = convert_delay(d.val) return val prjpeppercorn-1.12/gatemate/die.py000066400000000000000000007233421514752025000172440ustar00rootroot00000000000000# # prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools # # Copyright (C) 2024 The Project Peppercorn Authors. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import re from enum import Enum from dataclasses import dataclass PLL_X_POS = 33 PLL_Y_POS = 131 SERDES_X_POS = 1 SERDES_Y_POS = 121 CTRL_X_POS = -2 CTRL_Y_POS = -2 RAM_INPUT = 0 RAM_OUTPUT = 1 def max_row(): return 131 def max_col(): return 163 def num_rows(): return max_row() + 3 def num_cols(): return max_col() + 3 def is_sb(x,y): if (x>=-1 and x<=162 and y>=-1 and y<=130): return (x+1) % 2 == (y+1) % 2 return False def is_sb_big(x,y): if (x>=-1 and x<=162 and y>=-1 and y<=130): if (x+1) % 2 == 1 and (y+1) % 2 == 1: return False if (x+1) % 4 == (y+1) % 4 else True if (x+1) % 2 == 0 and (y+1) % 2 == 0: return False if (x+1) % 4 != (y+1) % 4 else True return False def is_sb_sml(x,y): if (x>=-1 and x<=162 and y>=-1 and y<=130): if (x+1) % 2 == 1 and (y+1) % 2 == 1: return True if (x+1) % 4 == (y+1) % 4 else False if (x+1) % 2 == 0 and (y+1) % 2 == 0: return True if (x+1) % 4 != (y+1) % 4 else False return False def get_sb_type(x,y): return "SB_BIG" if is_sb_big(x,y) else "SB_SML" def is_cpe(x,y): return x>=1 and x<=160 and y>=1 and y<=128 def is_outmux(x,y): return is_cpe(x,y) and (x+1) % 2 == (y+1) % 2 def is_edge_left(x,y): return x==-2 and y>=1 and y<=128 def is_edge_right(x,y): return x==max_col() and y>=1 and y<=128 def is_edge_bottom(x,y): return y==-2 and x>=1 and x<=160 def is_edge_top(x,y): return y==max_row() and x>=28 and x<=160 def is_edge_io(x,y): if (y==-2 and x>=5 and x<=40): # IO Bank S3/WA return True if (y==-2 and x>=57 and x<=92): # IO Bank S1/WB return True if (y==-2 and x>=101 and x<=136): # IO Bank S2/WC return True if (x==-2 and y>=25 and y<=60): # IO Bank W1/SA return True if (x==-2 and y>=69 and y<=104): # IO Bank W2/SB return True if (x==max_col() and y>=25 and y<=60): # IO Bank E1/NA return True if (x==max_col() and y>=69 and y<=104): # IO Bank E2/NB return True if (y==max_row() and x>=57 and x<=92): # IO Bank N1/EA return True if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB return True def is_ram_u(x,y): return x in [33,65,97,129] and y in [1,17,33,49,65,81,97,113] def is_ram_l(x,y): return x in [33,65,97,129] and y in [1+8,17+8,33+8,49+8,65+8,81+8,97+8,113+8] def get_full_tile_loc_str(x,y): tile_x = 1 # ((x-1)+16) % 8 + 1 tile_y = 1 # ((y-1)+16) % 8 + 1 tile = 1 # ((((x+16-1) // 8)+2) % 4) + 1 return f"t{tile}_x{tile_x}_y{tile_y}" def get_tile_loc_str(x,y): tile_x = 1 # ((x-1)+16) % 8 + 1 tile_y = 1 # ((y-1)+16) % 8 + 1 return f"x{tile_x}_y{tile_y}" @dataclass class IOName: bank : str port : str num : int def get_io_name(x,y): if (y==-2 and x>=5 and x<=40): # IO Bank S3/WA x-=5 return IOName("S3", "A" if x % 4==0 else "B", x//4) if (y==-2 and x>=57 and x<=92): # IO Bank S1/WB x-=57 return IOName("S1", "A" if x % 4==0 else "B", x//4) if (y==-2 and x>=101 and x<=136): # IO Bank S2/WC x-=101 return IOName("S2", "A" if x % 4==0 else "B", x//4) if (x==-2 and y>=25 and y<=60): # IO Bank W1/SA y-=25 return IOName("W1", "A" if y % 4==0 else "B", y//4) if (x==-2 and y>=69 and y<=104): # IO Bank W2/SB y-=69 return IOName("W2", "A" if y % 4==0 else "B", y//4) if (x==max_col() and y>=25 and y<=60): # IO Bank E1/NA y-=25 return IOName("E1", "A" if y % 4==0 else "B", y//4) if (x==max_col() and y>=69 and y<=104): # IO Bank E2/NB y-=69 return IOName("E2", "A" if y % 4==0 else "B", y//4) if (y==max_row() and x>=57 and x<=92): # IO Bank N1/EA x-=57 return IOName("N1", "A" if x % 4==0 else "B", x//4) if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB x-=101 return IOName("N2", "A" if x % 4==0 else "B", x//4) def is_gpio(x,y): if is_edge_io(x,y): if (y==-2 or y==max_row()): return x % 2==1 if (x==-2 or x==max_col()): return y % 2==1 return False def is_pll(x,y): return x==PLL_X_POS and y==PLL_Y_POS def is_serdes(x,y): return x==SERDES_X_POS and y==SERDES_Y_POS def is_cfg_ctrl(x,y): return x==CTRL_X_POS and y==CTRL_Y_POS def base_loc(x,y): return (((x-1) & ~1) + 1, ((y-1) & ~1) + 1) class PinType(Enum): INPUT = 0 OUTPUT = 1 INOUT = 2 @dataclass(eq=True, order=True) class Primitive: name : str type : str z : int @dataclass(eq=True, order=True) class Pin: name : str dir : PinType wire_type : str use_alias_conn: bool = False @dataclass(eq=True, order=True) class PinConstr: name : str rel_x : int rel_y : int output: int pin_num : int @dataclass(eq=True, order=True) class Group: name : str type : str @dataclass(eq=True, order=True) class Endpoint: name : str type : str @dataclass(eq=True, order=True) class MUX: src : str dst : str name : str bits : int value : int invert: bool visible: bool config: bool delay: str block: int resource : int @dataclass class Location: x : int y : int z : int @dataclass(eq=True, order=True) class Connection: x : int y : int name : str delay: str endpoint: bool @dataclass(eq=True, order=True) class TileInfo: die : int bit_x : int bit_y : int tile_x : int tile_y : int prim_index : int RAM_HALF_PINS = [ Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE", True), Pin("ENA[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("ENA[1]", PinType.INPUT,"RAM_WIRE", True), Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE", True), Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE", True), Pin("ENB[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("ENB[1]", PinType.INPUT,"RAM_WIRE", True), Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[0]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[1]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[2]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[3]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[4]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[5]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[6]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[7]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[8]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[9]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[10]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[11]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[12]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[13]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[14]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[15]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[16]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[17]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[18]", PinType.INPUT,"RAM_WIRE", True), Pin("WEA[19]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[0]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[1]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[2]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[3]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[4]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[5]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[6]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[7]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[8]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[9]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[10]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[11]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[12]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[13]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[14]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[15]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[16]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[17]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[18]", PinType.INPUT,"RAM_WIRE", True), Pin("WEB[19]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE", True), Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE", True), #Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[0]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[1]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[2]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[3]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[4]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[5]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[6]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[7]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[8]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[9]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[10]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[11]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[12]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[13]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[14]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[15]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[16]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[17]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[18]", PinType.INPUT,"RAM_WIRE", True), Pin("DIA[19]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[0]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[1]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[2]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[3]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[4]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[5]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[6]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[7]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[8]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[9]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[10]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[11]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[12]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[13]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[14]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[15]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[16]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[17]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[18]", PinType.INPUT,"RAM_WIRE", True), Pin("DIB[19]", PinType.INPUT,"RAM_WIRE", True), Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE, True), Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE", True), Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE", True), Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True), #Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True), Pin("CLOCK1", PinType.INPUT,"RAM_WIRE", True), Pin("CLOCK2", PinType.INPUT,"RAM_WIRE", True), Pin("CLOCK3", PinType.INPUT,"RAM_WIRE", True), Pin("CLOCK4", PinType.INPUT,"RAM_WIRE", True), ] PRIMITIVES_PINS = { "CPE_LT_U": [ # LUT2 first level Pin("D0_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_01" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_01" ,PinType.INPUT, "CPE_WIRE", True), # LUT2 2nd level Pin("D0_10" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_10" ,PinType.INPUT, "CPE_WIRE", True), # regular inputs Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True), Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), ], "CPE_FF_U": [ Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True), Pin("CLK_INT",PinType.INPUT, "CPE_WIRE", True), Pin("EN_INT" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY2", PinType.INPUT, "CPE_WIRE", True), Pin("PINY2", PinType.INPUT, "CPE_WIRE", True), Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True), Pin("EN" ,PinType.INPUT, "CPE_WIRE", True), Pin("SR" ,PinType.INPUT, "CPE_WIRE", True), Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_RAMIO_U": [ Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True), Pin("I" ,PinType.INPUT, "CPE_WIRE", True), Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_LT_L": [ # LUT2 first level Pin("D0_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_01" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_01" ,PinType.INPUT, "CPE_WIRE", True), # LUT2 2nd level Pin("D0_10" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_10" ,PinType.INPUT, "CPE_WIRE", True), # LUT2 3rd level input Pin("COMBIN" ,PinType.INPUT, "CPE_WIRE", True), # regular inputs Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True), # outputs Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_FF_L": [ Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True), Pin("CLK_INT",PinType.INPUT, "CPE_WIRE", True), Pin("EN_INT" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY2", PinType.INPUT, "CPE_WIRE", True), Pin("PINY2", PinType.INPUT, "CPE_WIRE", True), Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True), Pin("EN" ,PinType.INPUT, "CPE_WIRE", True), Pin("SR" ,PinType.INPUT, "CPE_WIRE", True), Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_RAMIO_L": [ Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True), Pin("I" ,PinType.INPUT, "CPE_WIRE", True), Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_BRIDGE": [ Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN5" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN6" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN7" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN8" ,PinType.INPUT, "CPE_WIRE", True), Pin("MUXOUT" ,PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_LT_FULL": [ Pin("D0_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_00" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_01" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_01" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_02" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_02" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_03" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_03" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_10" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_10" ,PinType.INPUT, "CPE_WIRE", True), Pin("D0_11" ,PinType.INPUT, "CPE_WIRE", True), Pin("D1_11" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN5" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN6" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN7" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN8" ,PinType.INPUT, "CPE_WIRE", True), Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CPOUT1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CPOUT2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("MUXOUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), # For MX8 Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True), Pin("EN" ,PinType.INPUT, "CPE_WIRE", True), Pin("SR" ,PinType.INPUT, "CPE_WIRE", True), ], "CPE_COMP": [ Pin("COMB1" ,PinType.INPUT, "CPE_WIRE", True), Pin("COMB2" ,PinType.INPUT, "CPE_WIRE", True), Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_CPLINES": [ Pin("OUT1" ,PinType.INPUT, "CPE_WIRE", True), Pin("OUT2" ,PinType.INPUT, "CPE_WIRE", True), Pin("COMPOUT",PinType.INPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True), Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), ], "IOSEL" : [ Pin("GPIO_OUT", PinType.OUTPUT,"GPIO_WIRE"), Pin("GPIO_EN" , PinType.OUTPUT,"GPIO_WIRE"), Pin("GPIO_IN" , PinType.INPUT, "GPIO_WIRE"), Pin("IN1" , PinType.OUTPUT,"GPIO_WIRE"), Pin("IN2" , PinType.OUTPUT,"GPIO_WIRE"), Pin("OUT1" , PinType.INPUT, "GPIO_WIRE"), Pin("OUT2" , PinType.INPUT, "GPIO_WIRE"), Pin("OUT3" , PinType.INPUT, "GPIO_WIRE"), Pin("OUT4" , PinType.INPUT, "GPIO_WIRE"), Pin("DDR" , PinType.INPUT, "GPIO_WIRE"), # Reset is global but no control over it #Pin("RESET" , PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK1", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK2", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK3", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK4", PinType.INPUT, "GPIO_WIRE"), ], "GPIO" : [ Pin("Y", PinType.INPUT, "GPIO_WIRE"), Pin("T", PinType.INPUT, "GPIO_WIRE"), Pin("A", PinType.OUTPUT,"GPIO_WIRE"), # PAD wires Pin("I", PinType.INPUT, "GPIO_WIRE"), Pin("O", PinType.OUTPUT,"GPIO_WIRE"), Pin("IO", PinType.INOUT, "GPIO_WIRE"), # LVDS PAD wires Pin("I_P", PinType.INPUT, "GPIO_WIRE"), Pin("I_N", PinType.INPUT, "GPIO_WIRE"), Pin("O_P", PinType.OUTPUT,"GPIO_WIRE"), Pin("O_N", PinType.OUTPUT,"GPIO_WIRE"), Pin("IO_P", PinType.INOUT, "GPIO_WIRE"), Pin("IO_N", PinType.INOUT, "GPIO_WIRE"), ], "CLKIN" : [ Pin("CLK0" , PinType.INPUT, "CLKIN_WIRE"), Pin("CLK1" , PinType.INPUT, "CLKIN_WIRE"), Pin("CLK2" , PinType.INPUT, "CLKIN_WIRE"), Pin("CLK3" , PinType.INPUT, "CLKIN_WIRE"), Pin("SER_CLK" , PinType.INPUT, "CLKIN_WIRE"), Pin("CLK_REF0" , PinType.OUTPUT,"CLKIN_WIRE"), Pin("CLK_REF1" , PinType.OUTPUT,"CLKIN_WIRE"), Pin("CLK_REF2" , PinType.OUTPUT,"CLKIN_WIRE"), Pin("CLK_REF3" , PinType.OUTPUT,"CLKIN_WIRE"), ], "GLBOUT" : [ Pin("CLK0_0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK90_0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK180_0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK270_0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_REF_OUT0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_GLB0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_FB0" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_FB0" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("GLB0" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("CLK0_1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK90_1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK180_1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK270_1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_REF_OUT1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_GLB1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_FB1" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_FB1" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("GLB1" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("CLK0_2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK90_2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK180_2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK270_2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_REF_OUT2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_GLB2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_FB2" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_FB2" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("GLB2" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("CLK0_3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK90_3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK180_3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK270_3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_REF_OUT3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_GLB3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("USR_FB3" , PinType.INPUT, "GLBOUT_WIRE"), Pin("CLK_FB3" , PinType.OUTPUT,"GLBOUT_WIRE"), Pin("GLB3" , PinType.OUTPUT,"GLBOUT_WIRE"), ], "PLL" : [ Pin("CLK_REF", PinType.INPUT, "PLL_WIRE"), Pin("USR_CLK_REF", PinType.INPUT, "PLL_WIRE"), Pin("USR_SEL_A_B", PinType.INPUT, "PLL_WIRE"), Pin("CLK_FEEDBACK", PinType.INPUT, "PLL_WIRE"), Pin("USR_LOCKED_STDY_RST", PinType.INPUT, "PLL_WIRE"), Pin("CLK0", PinType.OUTPUT,"PLL_WIRE"), Pin("CLK90", PinType.OUTPUT,"PLL_WIRE"), Pin("CLK180", PinType.OUTPUT,"PLL_WIRE"), Pin("CLK270", PinType.OUTPUT,"PLL_WIRE"), Pin("CLK_REF_OUT", PinType.OUTPUT,"PLL_WIRE"), Pin("USR_PLL_LOCKED_STDY", PinType.OUTPUT,"PLL_WIRE"), Pin("USR_PLL_LOCKED", PinType.OUTPUT,"PLL_WIRE"), ], "USR_RSTN" : [ Pin("USR_RSTN", PinType.OUTPUT,"USR_RSTN_WIRE"), ], "CFG_CTRL" : [ Pin("DATA[7]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[6]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[5]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[4]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[3]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[2]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[1]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("DATA[0]", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("CLK", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("EN", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("VALID", PinType.INPUT,"CFG_CTRL_WIRE"), Pin("RECFG", PinType.INPUT,"CFG_CTRL_WIRE"), ], "RAM" : [ Pin("C_ADDRA[0]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[1]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[2]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[3]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[4]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[5]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[6]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRA[7]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[0]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[1]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[2]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[3]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[4]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[5]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[6]", PinType.INPUT,"RAM_WIRE"), Pin("C_ADDRB[7]", PinType.INPUT,"RAM_WIRE"), Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE"), Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE"), Pin("ENA[0]", PinType.INPUT,"RAM_WIRE"), Pin("ENA[1]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[0]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[1]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[2]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[3]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[4]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[5]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[6]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[7]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[8]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[9]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[10]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[11]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[12]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[13]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[14]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[16]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[17]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[18]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[19]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[0]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[1]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[2]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[3]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[4]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[5]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[6]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[7]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[8]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[9]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[10]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[11]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[12]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[13]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[14]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[15]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[16]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[17]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[18]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[19]", PinType.INPUT,"RAM_WIRE"), Pin("CLKA[2]", PinType.INPUT,"RAM_WIRE"), Pin("CLKA[3]", PinType.INPUT,"RAM_WIRE"), Pin("ENA[2]", PinType.INPUT,"RAM_WIRE"), Pin("ENA[3]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEA[2]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEA[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1[15]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRA1X[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[20]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[21]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[22]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[23]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[24]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[25]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[26]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[27]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[28]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[29]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[30]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[31]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[32]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[33]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[34]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[35]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[36]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[37]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[38]", PinType.INPUT,"RAM_WIRE"), Pin("DIA[39]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[20]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[21]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[22]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[23]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[24]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[25]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[26]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[27]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[28]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[29]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[30]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[31]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[32]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[33]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[34]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[35]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[36]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[37]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[38]", PinType.INPUT,"RAM_WIRE"), Pin("WEA[39]", PinType.INPUT,"RAM_WIRE"), Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE"), Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE"), Pin("ENB[0]", PinType.INPUT,"RAM_WIRE"), Pin("ENB[1]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[0]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[1]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[2]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[3]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[4]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[5]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[6]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[7]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[8]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[9]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[10]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[11]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[12]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[13]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[14]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[16]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[17]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[18]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[19]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[0]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[1]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[2]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[3]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[4]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[5]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[6]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[7]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[8]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[9]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[10]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[11]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[12]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[13]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[14]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[15]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[16]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[17]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[18]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[19]", PinType.INPUT,"RAM_WIRE"), Pin("CLKB[2]", PinType.INPUT,"RAM_WIRE"), Pin("CLKB[3]", PinType.INPUT,"RAM_WIRE"), Pin("ENB[2]", PinType.INPUT,"RAM_WIRE"), Pin("ENB[3]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEB[2]", PinType.INPUT,"RAM_WIRE"), Pin("GLWEB[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1[15]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[0]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[1]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[2]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[3]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[4]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[5]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[6]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[7]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[8]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[9]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[10]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[11]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[12]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[13]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[14]", PinType.INPUT,"RAM_WIRE"), Pin("ADDRB1X[15]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[20]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[21]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[22]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[23]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[24]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[25]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[26]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[27]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[28]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[29]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[30]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[31]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[32]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[33]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[34]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[35]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[36]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[37]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[38]", PinType.INPUT,"RAM_WIRE"), Pin("DIB[39]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[20]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[21]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[22]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[23]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[24]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[25]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[26]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[27]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[28]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[29]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[30]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[31]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[32]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[33]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[34]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[35]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[36]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[37]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[38]", PinType.INPUT,"RAM_WIRE"), Pin("WEB[39]", PinType.INPUT,"RAM_WIRE"), Pin("F_RSTN", PinType.INPUT,"RAM_WIRE"), Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[20]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[20]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[21]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[21]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[22]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[22]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[23]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[23]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[24]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[24]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[25]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[25]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[26]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[26]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[27]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[27]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[28]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[28]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[29]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[29]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[30]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[30]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[31]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[31]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[32]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[32]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[33]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[33]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[34]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[34]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[35]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[35]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[36]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[36]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[37]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[37]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[38]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[38]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOA[39]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOAX[39]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKA[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKA[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKA[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKA[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[20]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[20]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[21]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[21]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[22]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[22]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[23]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[23]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[24]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[24]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[25]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[25]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[26]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[26]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[27]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[27]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[28]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[28]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[29]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[29]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[30]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[30]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[31]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[31]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[32]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[32]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[33]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[33]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[34]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[34]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[35]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[35]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[36]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[36]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[37]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[37]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[38]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[38]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOB[39]", PinType.OUTPUT,"RAM_WIRE"), Pin("DOBX[39]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKB[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKB[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKB[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCKB[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRA[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRA[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRB[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC1B_ERRB[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRA[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRA[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRB[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("ECC2B_ERRB[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_FULL[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_FULL[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_EMPTY[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_EMPTY[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_AL_FULL[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_AL_FULL[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_AL_EMPTY[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("F_AL_EMPTY[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ERR[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ERR[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ERR[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ERR[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDR[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("FWR_ADDRX[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[0]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[1]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[2]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[3]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[4]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[5]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[6]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[7]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[8]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[9]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[10]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[11]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[12]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[13]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[14]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDR[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("FRD_ADDRX[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("CLOCK1", PinType.INPUT,"RAM_WIRE"), Pin("CLOCK2", PinType.INPUT,"RAM_WIRE"), Pin("CLOCK3", PinType.INPUT,"RAM_WIRE"), Pin("CLOCK4", PinType.INPUT,"RAM_WIRE"), ], "RAM_HALF_L" : RAM_HALF_PINS, "SERDES" : [ Pin("TX_DETECT_RX_I", PinType.INPUT,"SERDES_WIRE"), Pin("PLL_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_CLK_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CLK_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_CLK_I", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_WE_I", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_EN_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PCS_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PMA_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PRBS_FORCE_ERR_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_POLARITY_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_EN_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PMA_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_EQA_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_CDR_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PCS_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_BUF_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PRBS_CNT_RESET_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_EN_EI_DETECTOR_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_COMMA_DETECT_EN_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_SLIDE_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_POLARITY_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_EN_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_MCOMMA_ALIGN_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PCOMMA_ALIGN_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_NOT_IN_TABLE_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_COMMA_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_ADDR_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_IS_K_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_8B10B_BYPASS_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_8B10B_BYPASS_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPMODE_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_CHAR_DISPVAL_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[63]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[62]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[61]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[60]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[59]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[58]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[57]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[56]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[55]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[54]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[53]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[52]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[51]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[50]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[49]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[48]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[47]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[46]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[45]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[44]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[43]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[42]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[41]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[40]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[39]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[38]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[37]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[36]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[35]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[34]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[33]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[32]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[31]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[30]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[29]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[28]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[27]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[26]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[25]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[24]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[23]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[22]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[21]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[20]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[19]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[18]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[17]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[16]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[15]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[14]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[13]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[12]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[11]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[10]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[9]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[8]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_DATA_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[15]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[14]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[13]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[12]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[11]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[10]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[9]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[8]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DO_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[15]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[14]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[13]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[12]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[11]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[10]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[9]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[8]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_DI_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[15]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[14]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[13]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[12]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[11]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[10]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[9]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[8]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[7]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[6]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[5]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[4]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[3]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("REGFILE_MASK_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CHAR_IS_K_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DISP_ERR_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[63]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[62]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[61]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[60]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[59]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[58]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[57]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[56]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[55]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[54]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[53]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[52]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[51]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[50]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[49]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[48]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[47]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[46]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[45]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[44]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[43]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[42]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[41]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[40]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[39]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[38]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[37]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[36]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[35]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[34]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[33]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[32]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[31]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[30]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[29]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[28]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[27]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[26]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[25]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[24]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[23]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[22]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[21]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[20]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[19]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[18]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[17]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[16]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[15]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[14]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[13]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[12]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[11]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[10]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[9]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[8]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[7]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[6]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[5]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[4]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[3]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[2]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[1]", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_DATA_O[0]", PinType.OUTPUT,"SERDES_WIRE"), Pin("TX_DETECT_RX_DONE_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("TX_DETECT_RX_PRESENT_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_CLK_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("PLL_CLK_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("TX_BUF_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("TX_RESET_DONE_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("REGFILE_RDY_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_PRBS_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_BUF_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_BYTE_IS_ALIGNED_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_BYTE_REALIGN_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_RESET_DONE_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("RX_EI_EN_O", PinType.OUTPUT,"SERDES_WIRE"), Pin("LOOPBACK_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("LOOPBACK_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("LOOPBACK_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PRBS_SEL_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PRBS_SEL_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_PRBS_SEL_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PRBS_SEL_I[2]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PRBS_SEL_I[1]", PinType.INPUT,"SERDES_WIRE"), Pin("RX_PRBS_SEL_I[0]", PinType.INPUT,"SERDES_WIRE"), Pin("TX_POWER_DOWN_N_I", PinType.INPUT,"SERDES_WIRE"), Pin("RX_POWER_DOWN_N_I", PinType.INPUT,"SERDES_WIRE"), Pin("TX_ELEC_IDLE_I", PinType.INPUT,"SERDES_WIRE"), ], } def get_groups_for_type(type): groups = [] def create_group(name, type): groups.append(Group(name,type)) if "CPE" in type: # CPE for p in range(1,13): create_group(f"IM_P{p:02d}", "IM") if "OM" in type and p>=9: create_group(f"OM_P{p:02d}", "OM") if "SB_BIG" in type: # SB_BIG for p in range(1,13): create_group(f"SB_BIG_P{p:02d}", "SB_BIG") if "SB_SML" in type: # SB_SML for p in range(1,13): create_group(f"SB_SML_P{p:02d}", "SB_SML") #if "GPIO" in type: # # GPIO if "IOES" in type: # IOES create_group("IOES", "IOES") if "LES" in type: # LES create_group("LES", "LES") if "RES" in type: # RES create_group("RES", "RES") if "TES" in type: # TES create_group("TES", "TES") if "BES" in type: # BES create_group("BES", "BES") return groups def get_primitives_for_type(type): primitives = [] if "CPE" in type: primitives.append(Primitive("CPE_LT_U","CPE_LT_U",0)) primitives.append(Primitive("CPE_LT_L","CPE_LT_L",1)) primitives.append(Primitive("CPE_FF_U","CPE_FF_U",2)) primitives.append(Primitive("CPE_FF_L","CPE_FF_L",3)) primitives.append(Primitive("CPE_RAMIO_U","CPE_RAMIO_U",4)) primitives.append(Primitive("CPE_RAMIO_L","CPE_RAMIO_L",5)) primitives.append(Primitive("CPE_COMP","CPE_COMP",6)) primitives.append(Primitive("CPE_CPLINES","CPE_CPLINES",7)) primitives.append(Primitive("CPE_LT_FULL","CPE_LT_FULL",8)) primitives.append(Primitive("CPE_BRIDGE","CPE_BRIDGE",9)) if "RAM_U" in type: primitives.append(Primitive("RAM","RAM",10)) if "RAM_L" in type: primitives.append(Primitive("RAM_HALF_L","RAM_HALF_L",11)) if "SERDES" in type: primitives.append(Primitive("SERDES","SERDES",10)) if "GPIO" in type: primitives.append(Primitive("GPIO","GPIO",0)) primitives.append(Primitive("IOSEL","IOSEL",1)) if "PLL" in type: primitives.append(Primitive("CLKIN","CLKIN",0)) primitives.append(Primitive("GLBOUT","GLBOUT",1)) primitives.append(Primitive("PLL0","PLL",2)) primitives.append(Primitive("PLL1","PLL",3)) primitives.append(Primitive("PLL2","PLL",4)) primitives.append(Primitive("PLL3","PLL",5)) if "CFG_CTRL" in type: primitives.append(Primitive("CFG_CTRL","CFG_CTRL",10)) primitives.append(Primitive("USR_RSTN","USR_RSTN",11)) return primitives def get_primitive_pins(bel): return PRIMITIVES_PINS[bel] def get_pins_constraint(type_name, prim_name, prim_type): val = [] if prim_type=="USR_RSTN": val.append(PinConstr("USR_RSTN", -CTRL_X_POS+1, -CTRL_Y_POS+66, RAM_INPUT, 2)) elif prim_type=="CFG_CTRL": val.append(PinConstr("DATA[7]", -CTRL_X_POS+1, -CTRL_Y_POS+16, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[6]", -CTRL_X_POS+1, -CTRL_Y_POS+15, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[5]", -CTRL_X_POS+1, -CTRL_Y_POS+14, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[4]", -CTRL_X_POS+1, -CTRL_Y_POS+13, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[3]", -CTRL_X_POS+1, -CTRL_Y_POS+12, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[2]", -CTRL_X_POS+1, -CTRL_Y_POS+11, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[1]", -CTRL_X_POS+1, -CTRL_Y_POS+10, RAM_OUTPUT, 1)) val.append(PinConstr("DATA[0]", -CTRL_X_POS+1, -CTRL_Y_POS+ 9, RAM_OUTPUT, 1)) val.append(PinConstr("CLK",-CTRL_X_POS+1, -CTRL_Y_POS+6, RAM_OUTPUT, 1)) val.append(PinConstr("EN",-CTRL_X_POS+1, -CTRL_Y_POS+7, RAM_OUTPUT, 1)) val.append(PinConstr("VALID",-CTRL_X_POS+1, -CTRL_Y_POS+8, RAM_OUTPUT, 1)) val.append(PinConstr("RECFG",-CTRL_X_POS+1, -CTRL_Y_POS+5, RAM_OUTPUT, 1)) elif prim_type=="RAM": val.append(PinConstr("C_ADDRA[0]", -3, 2, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRA[1]", -3, 2, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRA[2]", -3, 3, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRA[3]", -3, 3, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRA[4]", -3, 4, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRA[5]", -3, 4, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRA[6]", -3, 5, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRA[7]", -3, 5, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRB[0]", 2, 2, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRB[1]", 2, 2, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRB[2]", 2, 3, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRB[3]", 2, 3, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRB[4]", 2, 4, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRB[5]", 2, 4, RAM_OUTPUT, 2)) val.append(PinConstr("C_ADDRB[6]", 2, 5, RAM_OUTPUT, 1)) val.append(PinConstr("C_ADDRB[7]", 2, 5, RAM_OUTPUT, 2)) val.append(PinConstr("CLKA[0]", -6, 0, RAM_OUTPUT, 1)) val.append(PinConstr("CLKA[1]", -3, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ENA[0]", -6, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ENA[1]", -3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEA[0]", -6, 0, RAM_OUTPUT, 2)) val.append(PinConstr("GLWEA[1]", -3, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[0]", -5, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[1]", -5, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[2]", -5, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[3]", -5, 1, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[4]", -5, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[5]", -5, 2, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[6]", -5, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[7]", -5, 3, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[8]", -5, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[9]", -5, 4, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[10]", -5, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[11]", -5, 5, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[12]", -5, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[13]", -5, 6, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[14]", -5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[15]", -5, 7, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0X[0]", -5, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[1]", -4, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[2]", -5, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[3]", -4, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[4]", -5, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[5]", -4, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[6]", -5, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[7]", -4, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[8]", -5, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[9]", -4, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[10]", -5, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[11]", -4, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[12]", -6, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[13]", -5, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[14]", -6, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0X[15]", -5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[0]", -1, 0, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[1]", -1, 0, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[2]", -1, 1, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[3]", -1, 1, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[4]", -1, 2, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[5]", -1, 2, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[6]", -1, 3, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[7]", -1, 3, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[8]", -1, 4, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[9]", -1, 4, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[10]", -1, 5, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[11]", -1, 5, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[12]", -1, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[13]", -1, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[14]", -1, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[15]", -1, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[16]", -3, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[17]", -3, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[18]", -3, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[19]", -3, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[0]", -2, 0, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[1]", -2, 0, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[2]", -2, 1, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[3]", -2, 1, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[4]", -2, 2, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[5]", -2, 2, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[6]", -2, 3, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[7]", -2, 3, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[8]", -2, 4, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[9]", -2, 4, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[10]", -2, 5, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[11]", -2, 5, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[12]", -2, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[13]", -2, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[14]", -2, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[15]", -2, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[16]", -4, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[17]", -4, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[18]", -4, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[19]", -4, 7, RAM_OUTPUT, 2)) val.append(PinConstr("CLKA[2]", -6, 8, RAM_OUTPUT, 1)) val.append(PinConstr("CLKA[3]", -3, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ENA[2]", -6, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ENA[3]", -3, 9, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEA[2]", -6, 8, RAM_OUTPUT, 2)) val.append(PinConstr("GLWEA[3]", -3, 8, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[0]", -5, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[1]", -5, 8, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[2]", -5, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[3]", -5, 9, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[4]", -5, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[5]", -5, 10, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[6]", -5, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[7]", -5, 11, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[8]", -5, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[9]", -5, 12, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[10]", -5, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[11]", -5, 13, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[12]", -5, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[13]", -5, 14, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1[14]", -5, 15, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1[15]", -5, 15, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA1X[0]", -5, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[1]", -4, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[2]", -5, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[3]", -4, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[4]", -5, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[5]", -4, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[6]", -5, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[7]", -4, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[8]", -5, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[9]", -4, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[10]", -5, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[11]", -4, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[12]", -6, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[13]", -5, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[14]", -6, 15, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA1X[15]", -5, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[20]", -1, 8, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[21]", -1, 8, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[22]", -1, 9, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[23]", -1, 9, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[24]", -1, 10, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[25]", -1, 10, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[26]", -1, 11, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[27]", -1, 11, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[28]", -1, 12, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[29]", -1, 12, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[30]", -1, 13, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[31]", -1, 13, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[32]", -1, 14, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[33]", -1, 14, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[34]", -1, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[35]", -1, 15, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[36]", -3, 14, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[37]", -3, 14, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[38]", -3, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[39]", -3, 15, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[20]", -2, 8, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[21]", -2, 8, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[22]", -2, 9, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[23]", -2, 9, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[24]", -2, 10, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[25]", -2, 10, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[26]", -2, 11, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[27]", -2, 11, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[28]", -2, 12, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[29]", -2, 12, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[30]", -2, 13, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[31]", -2, 13, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[32]", -2, 14, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[33]", -2, 14, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[34]", -2, 15, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[35]", -2, 15, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[36]", -4, 14, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[37]", -4, 14, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[38]", -4, 15, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[39]", -4, 15, RAM_OUTPUT, 2)) val.append(PinConstr("CLKB[0]", 2, 0, RAM_OUTPUT, 1)) val.append(PinConstr("CLKB[1]", 5, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ENB[0]", 2, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ENB[1]", 5, 1, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEB[0]", 2, 0, RAM_OUTPUT, 2)) val.append(PinConstr("GLWEB[1]", 5, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[0]", 4, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[1]", 4, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[2]", 4, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[3]", 4, 1, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[4]", 4, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[5]", 4, 2, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[6]", 4, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[7]", 4, 3, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[8]", 4, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[9]", 4, 4, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[10]", 4, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[11]", 4, 5, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[12]", 4, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[13]", 4, 6, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[14]", 4, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[15]", 4, 7, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0X[0]", 3, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[1]", 4, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[2]", 3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[3]", 4, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[4]", 3, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[5]", 4, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[6]", 3, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[7]", 4, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[8]", 3, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[9]", 4, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[10]", 3, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[11]", 4, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[12]", 4, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[13]", 5, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[14]", 4, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0X[15]", 5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[0]", 1, 0, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[1]", 1, 0, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[2]", 1, 1, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[3]", 1, 1, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[4]", 1, 2, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[5]", 1, 2, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[6]", 1, 3, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[7]", 1, 3, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[8]", 1, 4, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[9]", 1, 4, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[10]", 1, 5, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[11]", 1, 5, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[12]", 1, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[13]", 1, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[14]", 1, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[15]", 1, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[16]", 3, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[17]", 3, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[18]", 3, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[19]", 3, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[0]", 0, 0, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[1]", 0, 0, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[2]", 0, 1, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[3]", 0, 1, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[4]", 0, 2, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[5]", 0, 2, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[6]", 0, 3, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[7]", 0, 3, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[8]", 0, 4, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[9]", 0, 4, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[10]", 0, 5, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[11]", 0, 5, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[12]", 0, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[13]", 0, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[14]", 0, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[15]", 0, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[16]", 2, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[17]", 2, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[18]", 2, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[19]", 2, 7, RAM_OUTPUT, 2)) val.append(PinConstr("CLKB[2]", 2, 8, RAM_OUTPUT, 1)) val.append(PinConstr("CLKB[3]", 5, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ENB[2]", 2, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ENB[3]", 5, 9, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEB[2]", 2, 8, RAM_OUTPUT, 2)) val.append(PinConstr("GLWEB[3]", 5, 8, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[0]", 4, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[1]", 4, 8, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[2]", 4, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[3]", 4, 9, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[4]", 4, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[5]", 4, 10, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[6]", 4, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[7]", 4, 11, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[8]", 4, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[9]", 4, 12, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[10]", 4, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[11]", 4, 13, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[12]", 4, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[13]", 4, 14, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1[14]", 4, 15, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1[15]", 4, 15, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB1X[0]", 3, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[1]", 4, 8, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[2]", 3, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[3]", 4, 9, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[4]", 3, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[5]", 4, 10, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[6]", 3, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[7]", 4, 11, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[8]", 3, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[9]", 4, 12, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[10]", 3, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[11]", 4, 13, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[12]", 4, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[13]", 5, 14, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[14]", 4, 15, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB1X[15]", 5, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[20]", 1, 8, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[21]", 1, 8, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[22]", 1, 9, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[23]", 1, 9, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[24]", 1, 10, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[25]", 1, 10, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[26]", 1, 11, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[27]", 1, 11, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[28]", 1, 12, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[29]", 1, 12, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[30]", 1, 13, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[31]", 1, 13, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[32]", 1, 14, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[33]", 1, 14, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[34]", 1, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[35]", 1, 15, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[36]", 3, 14, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[37]", 3, 14, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[38]", 3, 15, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[39]", 3, 15, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[20]", 0, 8, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[21]", 0, 8, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[22]", 0, 9, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[23]", 0, 9, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[24]", 0, 10, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[25]", 0, 10, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[26]", 0, 11, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[27]", 0, 11, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[28]", 0, 12, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[29]", 0, 12, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[30]", 0, 13, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[31]", 0, 13, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[32]", 0, 14, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[33]", 0, 14, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[34]", 0, 15, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[35]", 0, 15, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[36]", 2, 14, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[37]", 2, 14, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[38]", 2, 15, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[39]", 2, 15, RAM_OUTPUT, 2)) val.append(PinConstr("F_RSTN", -6, 2, RAM_OUTPUT, 2)) val.append(PinConstr("DOA[0]", -1, 0, RAM_INPUT, 1)) val.append(PinConstr("DOAX[0]", -2, 0, RAM_INPUT, 2)) val.append(PinConstr("DOA[1]", -1, 0, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[1]", -1, 0, RAM_INPUT, 2)) val.append(PinConstr("DOA[2]", -1, 1, RAM_INPUT, 1)) val.append(PinConstr("DOAX[2]", -2, 1, RAM_INPUT, 2)) val.append(PinConstr("DOA[3]", -1, 1, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[3]", -1, 1, RAM_INPUT, 2)) val.append(PinConstr("DOA[4]", -1, 2, RAM_INPUT, 1)) val.append(PinConstr("DOAX[4]", -2, 2, RAM_INPUT, 2)) val.append(PinConstr("DOA[5]", -1, 2, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[5]", -1, 2, RAM_INPUT, 2)) val.append(PinConstr("DOA[6]", -1, 3, RAM_INPUT, 1)) val.append(PinConstr("DOAX[6]", -2, 3, RAM_INPUT, 2)) val.append(PinConstr("DOA[7]", -1, 3, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[7]", -1, 3, RAM_INPUT, 2)) val.append(PinConstr("DOA[8]", -1, 4, RAM_INPUT, 1)) val.append(PinConstr("DOAX[8]", -2, 4, RAM_INPUT, 2)) val.append(PinConstr("DOA[9]", -1, 4, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[9]", -1, 4, RAM_INPUT, 2)) val.append(PinConstr("DOA[10]", -1, 5, RAM_INPUT, 1)) val.append(PinConstr("DOAX[10]", -2, 5, RAM_INPUT, 2)) val.append(PinConstr("DOA[11]", -1, 5, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[11]", -1, 5, RAM_INPUT, 2)) val.append(PinConstr("DOA[12]", -1, 6, RAM_INPUT, 1)) val.append(PinConstr("DOAX[12]", -2, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[13]", -1, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[13]", -1, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[14]", -1, 7, RAM_INPUT, 1)) val.append(PinConstr("DOAX[14]", -2, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[15]", -1, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[15]", -1, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[16]", -3, 6, RAM_INPUT, 1)) val.append(PinConstr("DOAX[16]", -4, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[17]", -3, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[17]", -3, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[18]", -3, 7, RAM_INPUT, 1)) val.append(PinConstr("DOAX[18]", -4, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[19]", -3, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[19]", -3, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[20]", -1, 8, RAM_INPUT, 1)) val.append(PinConstr("DOAX[20]", -2, 8, RAM_INPUT, 2)) val.append(PinConstr("DOA[21]", -1, 8, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[21]", -1, 8, RAM_INPUT, 2)) val.append(PinConstr("DOA[22]", -1, 9, RAM_INPUT, 1)) val.append(PinConstr("DOAX[22]", -2, 9, RAM_INPUT, 2)) val.append(PinConstr("DOA[23]", -1, 9, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[23]", -1, 9, RAM_INPUT, 2)) val.append(PinConstr("DOA[24]", -1, 10, RAM_INPUT, 1)) val.append(PinConstr("DOAX[24]", -2, 10, RAM_INPUT, 2)) val.append(PinConstr("DOA[25]", -1, 10, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[25]", -1, 10, RAM_INPUT, 2)) val.append(PinConstr("DOA[26]", -1, 11, RAM_INPUT, 1)) val.append(PinConstr("DOAX[26]", -2, 11, RAM_INPUT, 2)) val.append(PinConstr("DOA[27]", -1, 11, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[27]", -1, 11, RAM_INPUT, 2)) val.append(PinConstr("DOA[28]", -1, 12, RAM_INPUT, 1)) val.append(PinConstr("DOAX[28]", -2, 12, RAM_INPUT, 2)) val.append(PinConstr("DOA[29]", -1, 12, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[29]", -1, 12, RAM_INPUT, 2)) val.append(PinConstr("DOA[30]", -1, 13, RAM_INPUT, 1)) val.append(PinConstr("DOAX[30]", -2, 13, RAM_INPUT, 2)) val.append(PinConstr("DOA[31]", -1, 13, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[31]", -1, 13, RAM_INPUT, 2)) val.append(PinConstr("DOA[32]", -1, 14, RAM_INPUT, 1)) val.append(PinConstr("DOAX[32]", -2, 14, RAM_INPUT, 2)) val.append(PinConstr("DOA[33]", -1, 14, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[33]", -1, 14, RAM_INPUT, 2)) val.append(PinConstr("DOA[34]", -1, 15, RAM_INPUT, 1)) val.append(PinConstr("DOAX[34]", -2, 15, RAM_INPUT, 2)) val.append(PinConstr("DOA[35]", -1, 15, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[35]", -1, 15, RAM_INPUT, 2)) val.append(PinConstr("DOA[36]", -3, 14, RAM_INPUT, 1)) val.append(PinConstr("DOAX[36]", -4, 14, RAM_INPUT, 2)) val.append(PinConstr("DOA[37]", -3, 14, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[37]", -3, 14, RAM_INPUT, 2)) val.append(PinConstr("DOA[38]", -3, 15, RAM_INPUT, 1)) val.append(PinConstr("DOAX[38]", -4, 15, RAM_INPUT, 2)) val.append(PinConstr("DOA[39]", -3, 15, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[39]", -3, 15, RAM_INPUT, 2)) val.append(PinConstr("CLOCKA[1]", -3, 10, RAM_INPUT, 1)) val.append(PinConstr("CLOCKA[2]", -3, 11, RAM_INPUT, 1)) val.append(PinConstr("CLOCKA[3]", -3, 12, RAM_INPUT, 1)) val.append(PinConstr("CLOCKA[4]", -3, 13, RAM_INPUT, 1)) val.append(PinConstr("DOB[0]", 1, 0, RAM_INPUT, 1)) val.append(PinConstr("DOBX[0]", 0, 0, RAM_INPUT, 2)) val.append(PinConstr("DOB[1]", 1, 0, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[1]", 1, 0, RAM_INPUT, 2)) val.append(PinConstr("DOB[2]", 1, 1, RAM_INPUT, 1)) val.append(PinConstr("DOBX[2]", 0, 1, RAM_INPUT, 2)) val.append(PinConstr("DOB[3]", 1, 1, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[3]", 1, 1, RAM_INPUT, 2)) val.append(PinConstr("DOB[4]", 1, 2, RAM_INPUT, 1)) val.append(PinConstr("DOBX[4]", 0, 2, RAM_INPUT, 2)) val.append(PinConstr("DOB[5]", 1, 2, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[5]", 1, 2, RAM_INPUT, 2)) val.append(PinConstr("DOB[6]", 1, 3, RAM_INPUT, 1)) val.append(PinConstr("DOBX[6]", 0, 3, RAM_INPUT, 2)) val.append(PinConstr("DOB[7]", 1, 3, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[7]", 1, 3, RAM_INPUT, 2)) val.append(PinConstr("DOB[8]", 1, 4, RAM_INPUT, 1)) val.append(PinConstr("DOBX[8]", 0, 4, RAM_INPUT, 2)) val.append(PinConstr("DOB[9]", 1, 4, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[9]", 1, 4, RAM_INPUT, 2)) val.append(PinConstr("DOB[10]", 1, 5, RAM_INPUT, 1)) val.append(PinConstr("DOBX[10]", 0, 5, RAM_INPUT, 2)) val.append(PinConstr("DOB[11]", 1, 5, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[11]", 1, 5, RAM_INPUT, 2)) val.append(PinConstr("DOB[12]", 1, 6, RAM_INPUT, 1)) val.append(PinConstr("DOBX[12]", 0, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[13]", 1, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[13]", 1, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[14]", 1, 7, RAM_INPUT, 1)) val.append(PinConstr("DOBX[14]", 0, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[15]", 1, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[15]", 1, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[16]", 3, 6, RAM_INPUT, 1)) val.append(PinConstr("DOBX[16]", 2, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[17]", 3, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[17]", 3, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[18]", 3, 7, RAM_INPUT, 1)) val.append(PinConstr("DOBX[18]", 2, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[19]", 3, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[19]", 3, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[20]", 1, 8, RAM_INPUT, 1)) val.append(PinConstr("DOBX[20]", 0, 8, RAM_INPUT, 2)) val.append(PinConstr("DOB[21]", 1, 8, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[21]", 1, 8, RAM_INPUT, 2)) val.append(PinConstr("DOB[22]", 1, 9, RAM_INPUT, 1)) val.append(PinConstr("DOBX[22]", 0, 9, RAM_INPUT, 2)) val.append(PinConstr("DOB[23]", 1, 9, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[23]", 1, 9, RAM_INPUT, 2)) val.append(PinConstr("DOB[24]", 1, 10, RAM_INPUT, 1)) val.append(PinConstr("DOBX[24]", 0, 10, RAM_INPUT, 2)) val.append(PinConstr("DOB[25]", 1, 10, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[25]", 1, 10, RAM_INPUT, 2)) val.append(PinConstr("DOB[26]", 1, 11, RAM_INPUT, 1)) val.append(PinConstr("DOBX[26]", 0, 11, RAM_INPUT, 2)) val.append(PinConstr("DOB[27]", 1, 11, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[27]", 1, 11, RAM_INPUT, 2)) val.append(PinConstr("DOB[28]", 1, 12, RAM_INPUT, 1)) val.append(PinConstr("DOBX[28]", 0, 12, RAM_INPUT, 2)) val.append(PinConstr("DOB[29]", 1, 12, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[29]", 1, 12, RAM_INPUT, 2)) val.append(PinConstr("DOB[30]", 1, 13, RAM_INPUT, 1)) val.append(PinConstr("DOBX[30]", 0, 13, RAM_INPUT, 2)) val.append(PinConstr("DOB[31]", 1, 13, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[31]", 1, 13, RAM_INPUT, 2)) val.append(PinConstr("DOB[32]", 1, 14, RAM_INPUT, 1)) val.append(PinConstr("DOBX[32]", 0, 14, RAM_INPUT, 2)) val.append(PinConstr("DOB[33]", 1, 14, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[33]", 1, 14, RAM_INPUT, 2)) val.append(PinConstr("DOB[34]", 1, 15, RAM_INPUT, 1)) val.append(PinConstr("DOBX[34]", 0, 15, RAM_INPUT, 2)) val.append(PinConstr("DOB[35]", 1, 15, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[35]", 1, 15, RAM_INPUT, 2)) val.append(PinConstr("DOB[36]", 3, 14, RAM_INPUT, 1)) val.append(PinConstr("DOBX[36]", 2, 14, RAM_INPUT, 2)) val.append(PinConstr("DOB[37]", 3, 14, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[37]", 3, 14, RAM_INPUT, 2)) val.append(PinConstr("DOB[38]", 3, 15, RAM_INPUT, 1)) val.append(PinConstr("DOBX[38]", 2, 15, RAM_INPUT, 2)) val.append(PinConstr("DOB[39]", 3, 15, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[39]", 3, 15, RAM_INPUT, 2)) val.append(PinConstr("CLOCKB[1]", 2, 10, RAM_INPUT, 2)) val.append(PinConstr("CLOCKB[2]", 2, 11, RAM_INPUT, 2)) val.append(PinConstr("CLOCKB[3]", 2, 12, RAM_INPUT, 2)) val.append(PinConstr("CLOCKB[4]", 2, 13, RAM_INPUT, 2)) val.append(PinConstr("ECC1B_ERRA[0]", -4, 0, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRA[1]", -4, 8, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRA[2]", 5, 0, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRA[3]", 5, 8, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRB[0]", -4, 1, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRB[1]", -4, 9, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRB[2]", 5, 1, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRB[3]", 5, 9, RAM_INPUT, 1)) val.append(PinConstr("ECC2B_ERRA[0]", -4, 0, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRA[1]", -4, 8, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRA[2]", 5, 0, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRA[3]", 5, 8, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRB[0]", -4, 1, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRB[1]", -4, 9, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRB[2]", 5, 1, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRB[3]", 5, 9, RAM_INPUT, 2)) val.append(PinConstr("F_FULL[0]", -4, 10, RAM_INPUT, 2)) val.append(PinConstr("F_FULL[1]", -4, 12, RAM_INPUT, 2)) val.append(PinConstr("F_EMPTY[0]", -4, 10, RAM_INPUT, 1)) val.append(PinConstr("F_EMPTY[1]", -4, 13, RAM_INPUT, 2)) val.append(PinConstr("F_AL_FULL[0]", -4, 11, RAM_INPUT, 2)) val.append(PinConstr("F_AL_FULL[1]", -4, 12, RAM_INPUT, 1)) val.append(PinConstr("F_AL_EMPTY[0]", -4, 11, RAM_INPUT, 1)) val.append(PinConstr("F_AL_EMPTY[1]", -4, 13, RAM_INPUT, 1)) val.append(PinConstr("FWR_ERR[0]", -4, 4, RAM_INPUT, 1)) val.append(PinConstr("FWR_ERR[1]", -4, 5, RAM_INPUT, 1)) val.append(PinConstr("FRD_ERR[0]", -4, 4, RAM_INPUT, 2)) val.append(PinConstr("FRD_ERR[1]", -4, 5, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[0]", -6, 8, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[0]", -5, 8, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[1]", -6, 8, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[1]", -5, 8, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[2]", -6, 9, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[2]", -5, 9, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[3]", -6, 9, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[3]", -5, 9, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[4]", -6, 10, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[4]", -5, 10, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[5]", -6, 10, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[5]", -5, 10, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[6]", -6, 11, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[6]", -5, 11, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[7]", -6, 11, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[7]", -5, 11, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[8]", -6, 12, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[8]", -5, 12, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[9]", -6, 12, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[9]", -5, 12, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[10]", -6, 13, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[10]", -5, 13, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[11]", -6, 13, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[11]", -5, 13, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[12]", -6, 14, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[12]", -5, 14, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[13]", -6, 14, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[13]", -5, 14, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDR[14]", -6, 15, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDRX[14]", -5, 15, RAM_INPUT, 1)) val.append(PinConstr("FWR_ADDR[15]", -6, 15, RAM_INPUT, 2)) val.append(PinConstr("FWR_ADDRX[15]", -5, 15, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[0]", -6, 0, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[0]", -5, 0, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[1]", -6, 0, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[1]", -5, 0, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[2]", -6, 1, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[2]", -5, 1, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[3]", -6, 1, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[3]", -5, 1, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[4]", -6, 2, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[4]", -5, 2, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[5]", -6, 2, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[5]", -5, 2, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[6]", -6, 3, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[6]", -5, 3, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[7]", -6, 3, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[7]", -5, 3, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[8]", -6, 4, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[8]", -5, 4, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[9]", -6, 4, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[9]", -5, 4, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[10]", -6, 5, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[10]", -5, 5, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[11]", -6, 5, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[11]", -5, 5, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[12]", -6, 6, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[12]", -5, 6, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[13]", -6, 6, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[13]", -5, 6, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDR[14]", -6, 7, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDRX[14]", -5, 7, RAM_INPUT, 1)) val.append(PinConstr("FRD_ADDR[15]", -6, 7, RAM_INPUT, 2)) val.append(PinConstr("FRD_ADDRX[15]", -5, 7, RAM_INPUT, 2)) elif prim_type == "RAM_HALF_L": val.append(PinConstr("CLKA[0]", -6, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("CLKA[1]", -3, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ENA[0]", -6, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ENA[1]", -3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEA[0]", -6, 0, RAM_OUTPUT, 2)) #val.append(PinConstr("GLWEA[1]", -3, 0, RAM_OUTPUT, 2)) val.append(PinConstr("CLKB[0]", 2, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("CLKB[1]", 5, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ENB[0]", 2, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ENB[1]", 5, 1, RAM_OUTPUT, 1)) val.append(PinConstr("GLWEB[0]", 2, 0, RAM_OUTPUT, 2)) #val.append(PinConstr("GLWEB[1]", 5, 0, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[0]", -2, 0, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[1]", -2, 0, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[2]", -2, 1, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[3]", -2, 1, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[4]", -2, 2, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[5]", -2, 2, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[6]", -2, 3, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[7]", -2, 3, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[8]", -2, 4, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[9]", -2, 4, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[10]", -2, 5, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[11]", -2, 5, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[12]", -2, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[13]", -2, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[14]", -2, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[15]", -2, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[16]", -4, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[17]", -4, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEA[18]", -4, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEA[19]", -4, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[0]", 0, 0, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[1]", 0, 0, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[2]", 0, 1, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[3]", 0, 1, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[4]", 0, 2, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[5]", 0, 2, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[6]", 0, 3, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[7]", 0, 3, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[8]", 0, 4, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[9]", 0, 4, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[10]", 0, 5, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[11]", 0, 5, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[12]", 0, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[13]", 0, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[14]", 0, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[15]", 0, 7, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[16]", 2, 6, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[17]", 2, 6, RAM_OUTPUT, 2)) val.append(PinConstr("WEB[18]", 2, 7, RAM_OUTPUT, 1)) val.append(PinConstr("WEB[19]", 2, 7, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[0]", -5, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[1]", -5, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[2]", -5, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[3]", -5, 1, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[4]", -5, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[5]", -5, 2, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[6]", -5, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[7]", -5, 3, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[8]", -5, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[9]", -5, 4, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[10]", -5, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[11]", -5, 5, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[12]", -5, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[13]", -5, 6, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRA0[14]", -5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRA0[15]", -5, 7, RAM_OUTPUT, 2)) #val.append(PinConstr("ADDRA0X[0]", -5, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[1]", -4, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[2]", -5, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[3]", -4, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[4]", -5, 2, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[5]", -4, 2, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[6]", -5, 3, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[7]", -4, 3, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[8]", -5, 4, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[9]", -4, 4, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[10]", -5, 5, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[11]", -4, 5, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[12]", -6, 6, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[13]", -5, 6, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[14]", -6, 7, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRA0X[15]", -5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[0]", 4, 0, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[1]", 4, 0, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[2]", 4, 1, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[3]", 4, 1, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[4]", 4, 2, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[5]", 4, 2, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[6]", 4, 3, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[7]", 4, 3, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[8]", 4, 4, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[9]", 4, 4, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[10]", 4, 5, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[11]", 4, 5, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[12]", 4, 6, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[13]", 4, 6, RAM_OUTPUT, 2)) val.append(PinConstr("ADDRB0[14]", 4, 7, RAM_OUTPUT, 1)) val.append(PinConstr("ADDRB0[15]", 4, 7, RAM_OUTPUT, 2)) #val.append(PinConstr("ADDRB0X[0]", 3, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[1]", 4, 0, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[2]", 3, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[3]", 4, 1, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[4]", 3, 2, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[5]", 4, 2, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[6]", 3, 3, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[7]", 4, 3, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[8]", 3, 4, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[9]", 4, 4, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[10]", 3, 5, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[11]", 4, 5, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[12]", 4, 6, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[13]", 5, 6, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[14]", 4, 7, RAM_OUTPUT, 1)) #val.append(PinConstr("ADDRB0X[15]", 5, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[0]", -1, 0, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[1]", -1, 0, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[2]", -1, 1, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[3]", -1, 1, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[4]", -1, 2, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[5]", -1, 2, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[6]", -1, 3, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[7]", -1, 3, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[8]", -1, 4, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[9]", -1, 4, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[10]", -1, 5, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[11]", -1, 5, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[12]", -1, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[13]", -1, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[14]", -1, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[15]", -1, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[16]", -3, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[17]", -3, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIA[18]", -3, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIA[19]", -3, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[0]", 1, 0, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[1]", 1, 0, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[2]", 1, 1, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[3]", 1, 1, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[4]", 1, 2, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[5]", 1, 2, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[6]", 1, 3, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[7]", 1, 3, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[8]", 1, 4, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[9]", 1, 4, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[10]", 1, 5, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[11]", 1, 5, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[12]", 1, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[13]", 1, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[14]", 1, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[15]", 1, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[16]", 3, 6, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[17]", 3, 6, RAM_OUTPUT, 2)) val.append(PinConstr("DIB[18]", 3, 7, RAM_OUTPUT, 1)) val.append(PinConstr("DIB[19]", 3, 7, RAM_OUTPUT, 2)) val.append(PinConstr("DOA[0]", -1, 0, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[0]", -2, 0, RAM_INPUT, 2)) val.append(PinConstr("DOA[1]", -1, 0, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[1]", -1, 0, RAM_INPUT, 2)) val.append(PinConstr("DOA[2]", -1, 1, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[2]", -2, 1, RAM_INPUT, 2)) val.append(PinConstr("DOA[3]", -1, 1, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[3]", -1, 1, RAM_INPUT, 2)) val.append(PinConstr("DOA[4]", -1, 2, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[4]", -2, 2, RAM_INPUT, 2)) val.append(PinConstr("DOA[5]", -1, 2, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[5]", -1, 2, RAM_INPUT, 2)) val.append(PinConstr("DOA[6]", -1, 3, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[6]", -2, 3, RAM_INPUT, 2)) val.append(PinConstr("DOA[7]", -1, 3, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[7]", -1, 3, RAM_INPUT, 2)) val.append(PinConstr("DOA[8]", -1, 4, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[8]", -2, 4, RAM_INPUT, 2)) val.append(PinConstr("DOA[9]", -1, 4, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[9]", -1, 4, RAM_INPUT, 2)) val.append(PinConstr("DOA[10]", -1, 5, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[10]", -2, 5, RAM_INPUT, 2)) val.append(PinConstr("DOA[11]", -1, 5, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[11]", -1, 5, RAM_INPUT, 2)) val.append(PinConstr("DOA[12]", -1, 6, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[12]", -2, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[13]", -1, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[13]", -1, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[14]", -1, 7, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[14]", -2, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[15]", -1, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[15]", -1, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[16]", -3, 6, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[16]", -4, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[17]", -3, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[17]", -3, 6, RAM_INPUT, 2)) val.append(PinConstr("DOA[18]", -3, 7, RAM_INPUT, 1)) #val.append(PinConstr("DOAX[18]", -4, 7, RAM_INPUT, 2)) val.append(PinConstr("DOA[19]", -3, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOAX[19]", -3, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[0]", 1, 0, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[0]", 0, 0, RAM_INPUT, 2)) val.append(PinConstr("DOB[1]", 1, 0, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[1]", 1, 0, RAM_INPUT, 2)) val.append(PinConstr("DOB[2]", 1, 1, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[2]", 0, 1, RAM_INPUT, 2)) val.append(PinConstr("DOB[3]", 1, 1, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[3]", 1, 1, RAM_INPUT, 2)) val.append(PinConstr("DOB[4]", 1, 2, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[4]", 0, 2, RAM_INPUT, 2)) val.append(PinConstr("DOB[5]", 1, 2, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[5]", 1, 2, RAM_INPUT, 2)) val.append(PinConstr("DOB[6]", 1, 3, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[6]", 0, 3, RAM_INPUT, 2)) val.append(PinConstr("DOB[7]", 1, 3, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[7]", 1, 3, RAM_INPUT, 2)) val.append(PinConstr("DOB[8]", 1, 4, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[8]", 0, 4, RAM_INPUT, 2)) val.append(PinConstr("DOB[9]", 1, 4, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[9]", 1, 4, RAM_INPUT, 2)) val.append(PinConstr("DOB[10]", 1, 5, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[10]", 0, 5, RAM_INPUT, 2)) val.append(PinConstr("DOB[11]", 1, 5, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[11]", 1, 5, RAM_INPUT, 2)) val.append(PinConstr("DOB[12]", 1, 6, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[12]", 0, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[13]", 1, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[13]", 1, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[14]", 1, 7, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[14]", 0, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[15]", 1, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[15]", 1, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[16]", 3, 6, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[16]", 2, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[17]", 3, 6, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[17]", 3, 6, RAM_INPUT, 2)) val.append(PinConstr("DOB[18]", 3, 7, RAM_INPUT, 1)) #val.append(PinConstr("DOBX[18]", 2, 7, RAM_INPUT, 2)) val.append(PinConstr("DOB[19]", 3, 7, RAM_INPUT, 2)) # val.append(PinConstr("DOBX[19]", 3, 7, RAM_INPUT, 2)) val.append(PinConstr("ECC1B_ERRA[0]", -4, 0, RAM_INPUT, 1)) #val.append(PinConstr("ECC1B_ERRA[2]", 5, 0, RAM_INPUT, 1)) val.append(PinConstr("ECC1B_ERRB[0]", -4, 1, RAM_INPUT, 1)) #val.append(PinConstr("ECC1B_ERRB[2]", 5, 1, RAM_INPUT, 1)) val.append(PinConstr("ECC2B_ERRA[0]", -4, 0, RAM_INPUT, 2)) #val.append(PinConstr("ECC2B_ERRA[2]", 5, 0, RAM_INPUT, 2)) val.append(PinConstr("ECC2B_ERRB[0]", -4, 1, RAM_INPUT, 2)) #val.append(PinConstr("ECC2B_ERRB[2]", 5, 1, RAM_INPUT, 2)) elif prim_type=="SERDES": val.append(PinConstr("TX_DETECT_RX_I", 6, 6, RAM_OUTPUT, 1)) val.append(PinConstr("PLL_RESET_I", 6, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_CLK_I", 6, 5, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CLK_I", 6, 4, RAM_OUTPUT, 2)) val.append(PinConstr("RX_CLK_I", 6, 4, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_WE_I", 6, 3, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_EN_I", 6, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_RESET_I", 6, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_PCS_RESET_I", 6, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_PMA_RESET_I", 6, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_PRBS_FORCE_ERR_I", 6, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_POLARITY_I", 6, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_8B10B_EN_I", 6, 0, RAM_OUTPUT, 1)) val.append(PinConstr("RX_RESET_I", 7, 6, RAM_OUTPUT, 2)) val.append(PinConstr("RX_PMA_RESET_I", 7, 6, RAM_OUTPUT, 1)) val.append(PinConstr("RX_EQA_RESET_I", 7, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_CDR_RESET_I", 7, 5, RAM_OUTPUT, 1)) val.append(PinConstr("RX_PCS_RESET_I", 7, 4, RAM_OUTPUT, 2)) val.append(PinConstr("RX_BUF_RESET_I", 7, 4, RAM_OUTPUT, 1)) val.append(PinConstr("RX_PRBS_CNT_RESET_I", 7, 3, RAM_OUTPUT, 2)) val.append(PinConstr("RX_EN_EI_DETECTOR_I", 7, 3, RAM_OUTPUT, 1)) val.append(PinConstr("RX_COMMA_DETECT_EN_I", 7, 2, RAM_OUTPUT, 2)) val.append(PinConstr("RX_SLIDE_I", 7, 2, RAM_OUTPUT, 1)) val.append(PinConstr("RX_POLARITY_I", 7, 1, RAM_OUTPUT, 2)) val.append(PinConstr("RX_8B10B_EN_I", 7, 1, RAM_OUTPUT, 1)) val.append(PinConstr("RX_MCOMMA_ALIGN_I", 7, 0, RAM_OUTPUT, 2)) val.append(PinConstr("RX_PCOMMA_ALIGN_I", 7, 0, RAM_OUTPUT, 1)) val.append(PinConstr("RX_NOT_IN_TABLE_O[7]", 8, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_NOT_IN_TABLE_O[6]", 8, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_NOT_IN_TABLE_O[5]", 9, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_NOT_IN_TABLE_O[4]", 9, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_NOT_IN_TABLE_O[3]", 10, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_NOT_IN_TABLE_O[2]", 10, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_NOT_IN_TABLE_O[1]", 11, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_NOT_IN_TABLE_O[0]", 11, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[7]", 12, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[6]", 12, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[5]", 13, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[4]", 13, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[3]", 14, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[2]", 14, 7, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[1]", 15, 7, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_COMMA_O[0]", 15, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_ADDR_I[7]", 8, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_ADDR_I[6]", 8, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_ADDR_I[5]", 9, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_ADDR_I[4]", 9, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_ADDR_I[3]", 10, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_ADDR_I[2]", 10, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_ADDR_I[1]", 11, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_ADDR_I[0]", 11, 6, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_IS_K_I[7]", 12, 6, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_IS_K_I[6]", 12, 6, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_IS_K_I[5]", 13, 6, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_IS_K_I[4]", 13, 6, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_IS_K_I[3]", 14, 6, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_IS_K_I[2]", 14, 6, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_IS_K_I[1]", 15, 6, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_IS_K_I[0]", 15, 6, RAM_OUTPUT, 2)) val.append(PinConstr("TX_8B10B_BYPASS_I[7]", 8, 5, RAM_OUTPUT, 1)) val.append(PinConstr("TX_8B10B_BYPASS_I[6]", 8, 5, RAM_OUTPUT, 2)) val.append(PinConstr("TX_8B10B_BYPASS_I[5]", 9, 5, RAM_OUTPUT, 1)) val.append(PinConstr("TX_8B10B_BYPASS_I[4]", 9, 5, RAM_OUTPUT, 2)) val.append(PinConstr("TX_8B10B_BYPASS_I[3]", 10, 5, RAM_OUTPUT, 1)) val.append(PinConstr("TX_8B10B_BYPASS_I[2]", 10, 5, RAM_OUTPUT, 2)) val.append(PinConstr("TX_8B10B_BYPASS_I[1]", 11, 5, RAM_OUTPUT, 1)) val.append(PinConstr("TX_8B10B_BYPASS_I[0]", 11, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_8B10B_BYPASS_I[7]", 12, 5, RAM_OUTPUT, 1)) val.append(PinConstr("RX_8B10B_BYPASS_I[6]", 12, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_8B10B_BYPASS_I[5]", 13, 5, RAM_OUTPUT, 1)) val.append(PinConstr("RX_8B10B_BYPASS_I[4]", 13, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_8B10B_BYPASS_I[3]", 14, 5, RAM_OUTPUT, 1)) val.append(PinConstr("RX_8B10B_BYPASS_I[2]", 14, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_8B10B_BYPASS_I[1]", 15, 5, RAM_OUTPUT, 1)) val.append(PinConstr("RX_8B10B_BYPASS_I[0]", 15, 5, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPMODE_I[7]", 8, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPMODE_I[6]", 8, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPMODE_I[5]", 9, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPMODE_I[4]", 9, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPMODE_I[3]", 10, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPMODE_I[2]", 10, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPMODE_I[1]", 11, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPMODE_I[0]", 11, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPVAL_I[7]", 12, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPVAL_I[6]", 12, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPVAL_I[5]", 13, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPVAL_I[4]", 13, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPVAL_I[3]", 14, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPVAL_I[2]", 14, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_CHAR_DISPVAL_I[1]", 15, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_CHAR_DISPVAL_I[0]", 15, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[63]", 8, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[62]", 8, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[61]", 9, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[60]", 9, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[59]", 10, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[58]", 10, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[57]", 11, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[56]", 11, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[55]", 12, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[54]", 12, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[53]", 13, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[52]", 13, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[51]", 14, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[50]", 14, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[49]", 15, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[48]", 15, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[47]", 8, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[46]", 8, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[45]", 9, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[44]", 9, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[43]", 10, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[42]", 10, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[41]", 11, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[40]", 11, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[39]", 12, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[38]", 12, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[37]", 13, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[36]", 13, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[35]", 14, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[34]", 14, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[33]", 15, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[32]", 15, 2, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[31]", 8, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[30]", 8, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[29]", 9, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[28]", 9, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[27]", 10, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[26]", 10, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[25]", 11, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[24]", 11, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[23]", 12, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[22]", 12, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[21]", 13, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[20]", 13, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[19]", 14, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[18]", 14, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[17]", 15, 1, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[16]", 15, 1, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[15]", 8, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[14]", 8, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[13]", 9, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[12]", 9, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[11]", 10, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[10]", 10, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[9]", 11, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[8]", 11, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[7]", 12, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[6]", 12, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[5]", 13, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[4]", 13, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[3]", 14, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[2]", 14, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_DATA_I[1]", 15, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_DATA_I[0]", 15, 0, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DO_O[15]", 16, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[14]", 16, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[13]", 17, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[12]", 17, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[11]", 18, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[10]", 18, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[9]", 19, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[8]", 19, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[7]", 20, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[6]", 20, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[5]", 21, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[4]", 21, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[3]", 22, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[2]", 22, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DO_O[1]", 23, 7, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_DO_O[0]", 23, 7, RAM_INPUT, 2)) val.append(PinConstr("REGFILE_DI_I[15]", 16, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[14]", 16, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[13]", 17, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[12]", 17, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[11]", 18, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[10]", 18, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[9]", 19, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[8]", 19, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[7]", 20, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[6]", 20, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[5]", 21, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[4]", 21, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[3]", 22, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[2]", 22, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_DI_I[1]", 23, 6, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_DI_I[0]", 23, 6, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[15]", 16, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[14]", 16, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[13]", 17, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[12]", 17, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[11]", 18, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[10]", 18, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[9]", 19, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[8]", 19, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[7]", 20, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[6]", 20, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[5]", 21, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[4]", 21, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[3]", 22, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[2]", 22, 5, RAM_OUTPUT, 2)) val.append(PinConstr("REGFILE_MASK_I[1]", 23, 5, RAM_OUTPUT, 1)) val.append(PinConstr("REGFILE_MASK_I[0]", 23, 5, RAM_OUTPUT, 2)) val.append(PinConstr("RX_CHAR_IS_K_O[7]", 16, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_K_O[6]", 16, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_K_O[5]", 17, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_K_O[4]", 17, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_K_O[3]", 18, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_K_O[2]", 18, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_CHAR_IS_K_O[1]", 19, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_CHAR_IS_K_O[0]", 19, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_DISP_ERR_O[7]", 20, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_DISP_ERR_O[6]", 20, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_DISP_ERR_O[5]", 21, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_DISP_ERR_O[4]", 21, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_DISP_ERR_O[3]", 22, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_DISP_ERR_O[2]", 22, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_DISP_ERR_O[1]", 23, 4, RAM_INPUT, 1)) val.append(PinConstr("RX_DISP_ERR_O[0]", 23, 4, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[63]", 16, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[62]", 16, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[61]", 17, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[60]", 17, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[59]", 18, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[58]", 18, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[57]", 19, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[56]", 19, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[55]", 20, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[54]", 20, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[53]", 21, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[52]", 21, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[51]", 22, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[50]", 22, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[49]", 23, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[48]", 23, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[47]", 16, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[46]", 16, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[45]", 17, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[44]", 17, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[43]", 18, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[42]", 18, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[41]", 19, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[40]", 19, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[39]", 20, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[38]", 20, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[37]", 21, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[36]", 21, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[35]", 22, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[34]", 22, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[33]", 23, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[32]", 23, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[31]", 16, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[30]", 16, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[29]", 17, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[28]", 17, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[27]", 18, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[26]", 18, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[25]", 19, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[24]", 19, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[23]", 20, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[22]", 20, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[21]", 21, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[20]", 21, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[19]", 22, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[18]", 22, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[17]", 23, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[16]", 23, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[15]", 16, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[14]", 16, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[13]", 17, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[12]", 17, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[11]", 18, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[10]", 18, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[9]", 19, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[8]", 19, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[7]", 20, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[6]", 20, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[5]", 21, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[4]", 21, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[3]", 22, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[2]", 22, 0, RAM_INPUT, 2)) val.append(PinConstr("RX_DATA_O[1]", 23, 0, RAM_INPUT, 1)) val.append(PinConstr("RX_DATA_O[0]", 23, 0, RAM_INPUT, 2)) val.append(PinConstr("TX_DETECT_RX_DONE_O", 24, 6, RAM_INPUT, 2)) val.append(PinConstr("TX_DETECT_RX_PRESENT_O", 24, 6, RAM_INPUT, 1)) val.append(PinConstr("RX_CLK_O", 24, 5, RAM_INPUT, 2)) val.append(PinConstr("PLL_CLK_O", 24, 5, RAM_INPUT, 1)) val.append(PinConstr("TX_BUF_ERR_O", 24, 4, RAM_INPUT, 2)) val.append(PinConstr("TX_RESET_DONE_O", 24, 4, RAM_INPUT, 1)) val.append(PinConstr("REGFILE_RDY_O", 24, 3, RAM_INPUT, 2)) val.append(PinConstr("RX_PRBS_ERR_O", 24, 3, RAM_INPUT, 1)) val.append(PinConstr("RX_BUF_ERR_O", 24, 2, RAM_INPUT, 2)) val.append(PinConstr("RX_BYTE_IS_ALIGNED_O", 24, 2, RAM_INPUT, 1)) val.append(PinConstr("RX_BYTE_REALIGN_O", 24, 1, RAM_INPUT, 2)) val.append(PinConstr("RX_RESET_DONE_O", 24, 1, RAM_INPUT, 1)) val.append(PinConstr("RX_EI_EN_O", 24, 0, RAM_INPUT, 2)) val.append(PinConstr("LOOPBACK_I[2]", 25, 5, RAM_OUTPUT, 1)) val.append(PinConstr("LOOPBACK_I[1]", 25, 5, RAM_OUTPUT, 2)) val.append(PinConstr("LOOPBACK_I[0]", 25, 4, RAM_OUTPUT, 2)) val.append(PinConstr("TX_PRBS_SEL_I[2]", 25, 3, RAM_OUTPUT, 1)) val.append(PinConstr("TX_PRBS_SEL_I[1]", 25, 3, RAM_OUTPUT, 2)) val.append(PinConstr("TX_PRBS_SEL_I[0]", 25, 2, RAM_OUTPUT, 2)) val.append(PinConstr("RX_PRBS_SEL_I[2]", 25, 1, RAM_OUTPUT, 1)) val.append(PinConstr("RX_PRBS_SEL_I[1]", 25, 1, RAM_OUTPUT, 2)) val.append(PinConstr("RX_PRBS_SEL_I[0]", 25, 0, RAM_OUTPUT, 2)) val.append(PinConstr("TX_POWER_DOWN_N_I", 25, 4, RAM_OUTPUT, 1)) val.append(PinConstr("RX_POWER_DOWN_N_I", 25, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_ELEC_IDLE_I", 25, 0, RAM_OUTPUT, 1)) elif prim_type=="IOSEL": if "LES" in type_name: val.append(PinConstr("OUT4", 3, 1, RAM_OUTPUT, 2)) val.append(PinConstr("OUT3", 3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("OUT2", 3, 0, RAM_OUTPUT, 2)) val.append(PinConstr("OUT1", 3, 0, RAM_OUTPUT, 1)) if "RES" in type_name: val.append(PinConstr("OUT1", -3, 0, RAM_OUTPUT, 1)) val.append(PinConstr("OUT2", -3, 0, RAM_OUTPUT, 2)) val.append(PinConstr("OUT3", -3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("OUT4", -3, 1, RAM_OUTPUT, 2)) if "TES" in type_name: val.append(PinConstr("OUT1", 0, -3, RAM_OUTPUT, 1)) val.append(PinConstr("OUT2", 0, -3, RAM_OUTPUT, 2)) val.append(PinConstr("OUT3", 1, -3, RAM_OUTPUT, 1)) val.append(PinConstr("OUT4", 1, -3, RAM_OUTPUT, 2)) if "BES" in type_name: val.append(PinConstr("OUT4", 1, 3, RAM_OUTPUT, 2)) val.append(PinConstr("OUT3", 1, 3, RAM_OUTPUT, 1)) val.append(PinConstr("OUT2", 0, 3, RAM_OUTPUT, 2)) val.append(PinConstr("OUT1", 0, 3, RAM_OUTPUT, 1)) elif prim_type=="PLL": pll_num = int(prim_name[3]) val.append(PinConstr("USR_CLK_REF", -PLL_X_POS+1, -PLL_Y_POS+124 - pll_num, RAM_OUTPUT, 1)) val.append(PinConstr("USR_LOCKED_STDY_RST", -PLL_X_POS+1, -PLL_Y_POS+120 - pll_num, RAM_OUTPUT, 1)) val.append(PinConstr("USR_SEL_A_B", -PLL_X_POS+1, -PLL_Y_POS+116 - pll_num, RAM_OUTPUT, 1)) val.append(PinConstr("USR_PLL_LOCKED", -PLL_X_POS+1, -PLL_Y_POS+128 - pll_num, RAM_INPUT, 2)) val.append(PinConstr("USR_PLL_LOCKED_STDY", -PLL_X_POS+1, -PLL_Y_POS+124 - pll_num, RAM_INPUT, 2)) val.append(PinConstr("CLK0", -PLL_X_POS+39 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) val.append(PinConstr("CLK90", -PLL_X_POS+40 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) val.append(PinConstr("CLK180", -PLL_X_POS+41 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) val.append(PinConstr("CLK270", -PLL_X_POS+42 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) elif prim_type=="GLBOUT": val.append(PinConstr("USR_GLB0", -PLL_X_POS+1, -PLL_Y_POS+128, RAM_OUTPUT, 1)) val.append(PinConstr("USR_GLB1", -PLL_X_POS+1, -PLL_Y_POS+127, RAM_OUTPUT, 1)) val.append(PinConstr("USR_GLB2", -PLL_X_POS+1, -PLL_Y_POS+126, RAM_OUTPUT, 1)) val.append(PinConstr("USR_GLB3", -PLL_X_POS+1, -PLL_Y_POS+125, RAM_OUTPUT, 1)) val.append(PinConstr("USR_FB0", -PLL_X_POS+1, -PLL_Y_POS+128, RAM_OUTPUT, 2)) val.append(PinConstr("USR_FB1", -PLL_X_POS+1, -PLL_Y_POS+127, RAM_OUTPUT, 2)) val.append(PinConstr("USR_FB2", -PLL_X_POS+1, -PLL_Y_POS+126, RAM_OUTPUT, 2)) val.append(PinConstr("USR_FB3", -PLL_X_POS+1, -PLL_Y_POS+125, RAM_OUTPUT, 2)) return val def get_pin_connection_name(prim, pin): if prim.type == "CPE_LT_U": match pin.name: case "OUT": return "CPE.COMBOUT2_int" case "CPOUT": return "CPE.CPOUT2_int" case "D0_00": return "CPE.D0_00_int" case "D1_00": return "CPE.D1_00_int" case "D0_01": return "CPE.D0_01_int" case "D1_01": return "CPE.D1_01_int" case "D0_10": return "CPE.D0_10_int" case "D1_10": return "CPE.D1_10_int" case "IN1": return "CPE.IN1_int" case "IN2": return "CPE.IN2_int" case "IN3": return "CPE.IN3_int" case "IN4": return "CPE.IN4_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_FF_U": match pin.name: case "DIN": return "CPE.DIN2_int" case "DOUT": return "CPE.DOUT2_int" case "CLK_INT": return "CPE.CLK_int" case "EN_INT": return "CPE.EN_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_RAMIO_U": match pin.name: case "OUT": return "CPE.OUT2" case "RAM_O": return "CPE.RAM_O2" case "RAM_I": return "CPE.RAM_I2" case "I": return "CPE.OUT2_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_LT_L": match pin.name: case "OUT": return "CPE.COMBOUT1_int" case "CPOUT": return "CPE.CPOUT1_int" case "D0_00": return "CPE.D0_02_int" case "D1_00": return "CPE.D1_02_int" case "D0_01": return "CPE.D0_03_int" case "D1_01": return "CPE.D1_03_int" case "D0_10": return "CPE.D0_11_int" case "D1_10": return "CPE.D1_11_int" case "IN1": return "CPE.IN5_int" case "IN2": return "CPE.IN6_int" case "IN3": return "CPE.IN7_int" case "IN4": return "CPE.IN8_int" case "COMBIN": return "CPE.COMBIN_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_LT_FULL": match pin.name: case "D0_00": return "CPE.D0_00_int" case "D1_00": return "CPE.D1_00_int" case "D0_01": return "CPE.D0_01_int" case "D1_01": return "CPE.D1_01_int" case "D0_10": return "CPE.D0_10_int" case "D1_10": return "CPE.D1_10_int" case "D0_02": return "CPE.D0_02_int" case "D1_02": return "CPE.D1_02_int" case "D0_03": return "CPE.D0_03_int" case "D1_03": return "CPE.D1_03_int" case "D0_11": return "CPE.D0_11_int" case "D1_11": return "CPE.D1_11_int" case "OUT1": return "CPE.COMBOUT1_int" case "OUT2": return "CPE.COMBOUT2_int" case "CPOUT1": return "CPE.CPOUT1_int" case "CPOUT2": return "CPE.CPOUT2_int" case "MUXOUT": return "CPE.MUXOUT_int" case "IN1": return "CPE.IN1_int" case "IN2": return "CPE.IN2_int" case "IN3": return "CPE.IN3_int" case "IN4": return "CPE.IN4_int" case "IN5": return "CPE.IN5_int" case "IN6": return "CPE.IN6_int" case "IN7": return "CPE.IN7_int" case "IN8": return "CPE.IN8_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_BRIDGE": match pin.name: case "MUXOUT": return "CPE.MUXOUT_int" case "IN1": return "CPE.IN1_int" case "IN2": return "CPE.IN2_int" case "IN3": return "CPE.IN3_int" case "IN4": return "CPE.IN4_int" case "IN5": return "CPE.IN5_int" case "IN6": return "CPE.IN6_int" case "IN7": return "CPE.IN7_int" case "IN8": return "CPE.IN8_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_FF_L": match pin.name: case "DIN": return "CPE.DIN1_int" case "DOUT": return "CPE.DOUT1_int" case "CLK_INT": return "CPE.CLK_int" case "EN_INT": return "CPE.EN_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_RAMIO_L": match pin.name: case "OUT": return "CPE.OUT1" case "RAM_O": return "CPE.RAM_O1" case "RAM_I": return "CPE.RAM_I1" case "I": return "CPE.OUT1_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_COMP": match pin.name: case "COMB1": return "CPE.COMBIN1_int" case "COMB2": return "CPE.COMBIN2_int" case "COMPOUT": return "CPE.COMPOUT_int" case _: return f"CPE.{pin.name}" elif prim.type == "CPE_CPLINES": match pin.name: case "OUT1": return "CPE.OUT1_IN_int" case "OUT2": return "CPE.OUT2_IN_int" case "COMPOUT": return "CPE.COMPOUT_IN_int" case _: return f"CPE.{pin.name}" elif prim.type == "RAM_HALF_L": match = re.match(r"([A-Za-z0-9_]+)\[(\d+)\]$", pin.name.strip()) if not match: return f"RAM.{pin.name}" base, index = match.group(1), int(match.group(2)) if base in ("CLKA", "CLKB", "ENA", "ENB", "GLWEA", "GLWEB"): return f"RAM.{base}[{index + 2}]" elif base in ("ADDRA0"): return f"RAM.ADDRA1[{index}]" elif base in ("ADDRB0"): return f"RAM.ADDRB1[{index}]" elif base in ("ECC1B_ERRA", "ECC1B_ERRB", "ECC2B_ERRA", "ECC2B_ERRB"): return f"RAM.{base}[{index + 1}]" elif base in ("WEA", "WEB", "DIA", "DIB", "DOA", "DOB"): return f"RAM.{base}[{index + 20}]" else: return f"RAM.{pin.name}" return f"{prim.name}.{pin.name}" def get_endpoints_for_type(type): wires = [] def create_wire(name, type): wires.append(Endpoint(name,type)) for prim in get_primitives_for_type(type): for pin in get_primitive_pins(prim.type): if not pin.use_alias_conn: create_wire(f"{prim.name}.{pin.name}", type=f"{pin.wire_type}") if "CPE" in type: create_wire("CPE.RAM_I1" , type="CPE_WIRE_L") create_wire("CPE.RAM_I2" , type="CPE_WIRE_L") create_wire("CPE.IN1" , type="CPE_WIRE_L") create_wire("CPE.IN2" , type="CPE_WIRE_L") create_wire("CPE.IN3" , type="CPE_WIRE_L") create_wire("CPE.IN4" , type="CPE_WIRE_L") create_wire("CPE.IN5" , type="CPE_WIRE_L") create_wire("CPE.IN6" , type="CPE_WIRE_L") create_wire("CPE.IN7" , type="CPE_WIRE_L") create_wire("CPE.IN8" , type="CPE_WIRE_L") create_wire("CPE.D0_00_int", type="CPE_WIRE_INT") create_wire("CPE.D1_00_int", type="CPE_WIRE_INT") create_wire("CPE.D0_01_int", type="CPE_WIRE_INT") create_wire("CPE.D1_01_int", type="CPE_WIRE_INT") create_wire("CPE.D0_10_int", type="CPE_WIRE_INT") create_wire("CPE.D1_10_int", type="CPE_WIRE_INT") create_wire("CPE.D0_02_int", type="CPE_WIRE_INT") create_wire("CPE.D1_02_int", type="CPE_WIRE_INT") create_wire("CPE.D0_03_int", type="CPE_WIRE_INT") create_wire("CPE.D1_03_int", type="CPE_WIRE_INT") create_wire("CPE.D0_11_int", type="CPE_WIRE_INT") create_wire("CPE.D1_11_int", type="CPE_WIRE_INT") create_wire("CPE.IN1_int", type="CPE_WIRE_INT") create_wire("CPE.IN2_int", type="CPE_WIRE_INT") create_wire("CPE.IN3_int", type="CPE_WIRE_INT") create_wire("CPE.IN4_int", type="CPE_WIRE_INT") create_wire("CPE.IN5_int", type="CPE_WIRE_INT") create_wire("CPE.IN6_int", type="CPE_WIRE_INT") create_wire("CPE.IN7_int", type="CPE_WIRE_INT") create_wire("CPE.IN8_int", type="CPE_WIRE_INT") create_wire("CPE.TI2_int", type="CPE_WIRE_INT") create_wire("CPE.TI4_int", type="CPE_WIRE_INT") create_wire("CPE.TI6_int", type="CPE_WIRE_INT") create_wire("CPE.TI8_int", type="CPE_WIRE_INT") create_wire("CPE.OUT1_int", type="CPE_WIRE_INT") create_wire("CPE.OUT2_int", type="CPE_WIRE_INT") create_wire("CPE.COMBOUT1_int", type="CPE_WIRE_INT") create_wire("CPE.COMBOUT2_int", type="CPE_WIRE_INT") create_wire("CPE.COMBIN1_int", type="CPE_WIRE_INT") create_wire("CPE.COMBIN2_int", type="CPE_WIRE_INT") create_wire("CPE.MUXOUT_int", type="CPE_WIRE_INT") create_wire("CPE.COMPOUT_int", type="CPE_WIRE_INT") create_wire("CPE.OUT1_IN_int", type="CPE_WIRE_INT") create_wire("CPE.OUT2_IN_int", type="CPE_WIRE_INT") create_wire("CPE.COMPOUT_IN_int", type="CPE_WIRE_INT") create_wire("CPE.CPOUT1_int", type="CPE_WIRE_INT") create_wire("CPE.CPOUT2_int", type="CPE_WIRE_INT") create_wire("CPE.COMBIN_int", type="CPE_WIRE_INT") create_wire("CPE.DIN1_int", type="CPE_WIRE_INT") create_wire("CPE.DIN2_int", type="CPE_WIRE_INT") create_wire("CPE.DOUT1_int", type="CPE_WIRE_INT") create_wire("CPE.DOUT2_int", type="CPE_WIRE_INT") create_wire("CPE.CLK" , type="CPE_WIRE_L") create_wire("CPE.EN" , type="CPE_WIRE_L") create_wire("CPE.CLK_int", type="CPE_WIRE_INT") create_wire("CPE.EN_int" , type="CPE_WIRE_INT") create_wire("CPE.SR" , type="CPE_WIRE_L") create_wire("CPE.OUT1" , type="CPE_WIRE_B") create_wire("CPE.OUT2" , type="CPE_WIRE_B") create_wire("CPE.RAM_O1" , type="CPE_WIRE_B") create_wire("CPE.RAM_O2" , type="CPE_WIRE_B") create_wire("CPE.CINX" , type="CPE_WIRE_L") create_wire("CPE.PINX" , type="CPE_WIRE_L") create_wire("CPE.CINY1" , type="CPE_WIRE_B") create_wire("CPE.PINY1" , type="CPE_WIRE_B") create_wire("CPE.CINY2" , type="CPE_WIRE_B") create_wire("CPE.PINY2" , type="CPE_WIRE_B") create_wire("CPE.COUTX" , type="CPE_WIRE_B") create_wire("CPE.POUTX" , type="CPE_WIRE_B") create_wire("CPE.COUTY1" , type="CPE_WIRE_T") create_wire("CPE.POUTY1" , type="CPE_WIRE_T") create_wire("CPE.COUTY2" , type="CPE_WIRE_T") create_wire("CPE.POUTY2" , type="CPE_WIRE_T") create_wire("CPE.CX_OUT" , type="CPE_WIRE_INT") create_wire("CPE.CY1_OUT", type="CPE_WIRE_INT") create_wire("CPE.CY2_OUT", type="CPE_WIRE_INT") create_wire("CPE.PX_OUT" , type="CPE_WIRE_INT") create_wire("CPE.PY1_OUT", type="CPE_WIRE_INT") create_wire("CPE.PY2_OUT", type="CPE_WIRE_INT") create_wire("CPE.CX_OUT2" , type="CPE_WIRE_INT") create_wire("CPE.CY1_OUT2", type="CPE_WIRE_INT") create_wire("CPE.CY2_OUT2", type="CPE_WIRE_INT") create_wire("CPE.PX_OUT2" , type="CPE_WIRE_INT") create_wire("CPE.PY1_OUT2", type="CPE_WIRE_INT") create_wire("CPE.PY2_OUT2", type="CPE_WIRE_INT") create_wire("CPE.CX_VAL" , type="CPE_WIRE_INT") create_wire("CPE.CY1_VAL", type="CPE_WIRE_INT") create_wire("CPE.CY2_VAL", type="CPE_WIRE_INT") create_wire("CPE.PX_VAL" , type="CPE_WIRE_INT") create_wire("CPE.PY1_VAL", type="CPE_WIRE_INT") create_wire("CPE.PY2_VAL", type="CPE_WIRE_INT") create_wire("CPE.CIY12" , type="CPE_WIRE_INT") create_wire("CPE.PIY12", type="CPE_WIRE_INT") for p in range(1,13): plane = f"{p:02d}" for i in range(8): create_wire(f"IM.P{plane}.D{i}", type="IM_WIRE") create_wire(f"IM.P{plane}.Y", type="IM_WIRE") if "OM" in type and p>=9: for i in range(4): create_wire(f"OM.P{plane}.D{i}", type="OM_WIRE") create_wire(f"OM.P{plane}.Y", type="OM_WIRE") if "RAM_L" in type: create_wire("RAM.CLKA[2]" , type="RAM_WIRE") create_wire("RAM.CLKB[2]" , type="RAM_WIRE") create_wire("RAM.ENA[2]" , type="RAM_WIRE") create_wire("RAM.ENB[2]" , type="RAM_WIRE") create_wire("RAM.GLWEA[2]" , type="RAM_WIRE") create_wire("RAM.GLWEB[2]" , type="RAM_WIRE") for i in range(0,16+1): create_wire(f"RAM.ADDRA1[{i}]" , type="RAM_WIRE") create_wire(f"RAM.ADDRB1[{i}]" , type="RAM_WIRE") for i in range(20,40): create_wire(f"RAM.WEA[{i}]" , type="RAM_WIRE") create_wire(f"RAM.WEB[{i}]" , type="RAM_WIRE") create_wire(f"RAM.DIA[{i}]" , type="RAM_WIRE") create_wire(f"RAM.DIB[{i}]" , type="RAM_WIRE") create_wire(f"RAM.DOA[{i}]" , type="RAM_WIRE") create_wire(f"RAM.DOB[{i}]" , type="RAM_WIRE") for i in range(1,5): create_wire(f"RAM.CLOCK{i}" , type="RAM_WIRE") create_wire("RAM.ECC1B_ERRA[1]" , type="RAM_WIRE") create_wire("RAM.ECC1B_ERRB[1]" , type="RAM_WIRE") create_wire("RAM.ECC2B_ERRA[1]" , type="RAM_WIRE") create_wire("RAM.ECC2B_ERRB[1]" , type="RAM_WIRE") if "SB_BIG" in type: for p in range(1,13): plane = f"{p:02d}" create_wire(f"SB_BIG.P{plane}.D0", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D0_IO", type="SB_BIG_WIRE") for i in range(1,5): create_wire(f"SB_BIG.P{plane}.D2_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D2_{i}_D2D", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D3_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D4_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D5_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D6_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D7_{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.D7_{i}_CLK", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.Y{i}", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.YDIAG", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.X34", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.X14", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.X12", type="SB_BIG_WIRE") create_wire(f"SB_BIG.P{plane}.X23", type="SB_BIG_WIRE") for i in range(1,5): create_wire(f"SB_DRIVE.P{plane}.D{i}.IN", type="SB_DRIVE_WIRE") create_wire(f"SB_DRIVE.P{plane}.D{i}.OUT", type="SB_DRIVE_WIRE") create_wire(f"SB_DRIVE.P{plane}.D{i}.OUT_NOINV", type="SB_DRIVE_INT_WIRE") if "SB_SML" in type: for p in range(1,13): plane = f"{p:02d}" create_wire(f"SB_SML.P{plane}.D0", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.D0_IO", type="SB_SML_WIRE") for i in range(1,5): create_wire(f"SB_SML.P{plane}.D2_{i}", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.D2_{i}_D2D", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.D3_{i}", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.Y{i}", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.Y{i}_int", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.YDIAG", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.YDIAG_int", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.X34", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.X14", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.X12", type="SB_SML_WIRE") create_wire(f"SB_SML.P{plane}.X23", type="SB_SML_WIRE") if "IOES" in type: create_wire("IOES.IO_IN1", type="IOES_WIRE") create_wire("IOES.IO_IN2", type="IOES_WIRE") for p in range(1,13): plane = f"{p:02d}" create_wire(f"IOES.SB_IN_{plane}", type="IOES_WIRE") create_wire(f"IOES.ALTIN_{plane}", type="IOES_WIRE") if "LES" in type: for p in range(1,9): create_wire(f"LES.SB_Y3.P{p}", type="LES_WIRE") create_wire(f"LES.MDIE1.P{p}", type="LES_WIRE") for i in range(4): create_wire(f"LES.CLOCK{i}", type="LES_WIRE") create_wire("LES.CPE_CINX", type="LES_WIRE") create_wire("LES.CPE_PINX", type="LES_WIRE") # Internal wires create_wire("LES.SB_Y3_SEL1_int", type="LES_INT_WIRE") create_wire("LES.MDIE1_SEL1_int", type="LES_INT_WIRE") create_wire("LES.CLOCK_SEL1_int", type="LES_INT_WIRE") create_wire("LES.SB_Y3_SEL2_int", type="LES_INT_WIRE") create_wire("LES.MDIE1_SEL2_int", type="LES_INT_WIRE") create_wire("LES.CLOCK_SEL2_int", type="LES_INT_WIRE") if "BES" in type: for p in range(1,9): create_wire(f"BES.SB_Y4.P{p}", type="BES_WIRE") create_wire(f"BES.MDIE2.P{p}", type="BES_WIRE") for i in range(4): create_wire(f"BES.CLOCK{i}", type="BES_WIRE") create_wire("BES.P_CINY1", type="BES_WIRE") create_wire("BES.P_PINY1", type="BES_WIRE") create_wire("BES.P_CINY2", type="BES_WIRE") create_wire("BES.P_PINY2", type="BES_WIRE") create_wire("BES.CPE_CINY1", type="BES_WIRE") create_wire("BES.CPE_PINY1", type="BES_WIRE") create_wire("BES.CPE_CINY2", type="BES_WIRE") create_wire("BES.CPE_PINY2", type="BES_WIRE") # Internal wires create_wire("BES.SB_Y4_SEL1_int", type="BES_INT_WIRE") create_wire("BES.MDIE2_SEL1_int", type="BES_INT_WIRE") create_wire("BES.CLOCK_SEL1_int", type="BES_INT_WIRE") create_wire("BES.SB_Y4_SEL2_int", type="BES_INT_WIRE") create_wire("BES.MDIE2_SEL2_int", type="BES_INT_WIRE") create_wire("BES.CLOCK_SEL2_int", type="BES_INT_WIRE") create_wire("BES.SB_Y4_SEL3_int", type="BES_INT_WIRE") create_wire("BES.MDIE2_SEL3_int", type="BES_INT_WIRE") create_wire("BES.CLOCK_SEL3_int", type="BES_INT_WIRE") create_wire("BES.SB_Y4_SEL4_int", type="BES_INT_WIRE") create_wire("BES.MDIE2_SEL4_int", type="BES_INT_WIRE") create_wire("BES.CLOCK_SEL4_int", type="BES_INT_WIRE") create_wire("BES.CPE_CINY1_int", type="BES_INT_WIRE") create_wire("BES.CPE_PINY1_int", type="BES_INT_WIRE") create_wire("BES.CPE_CINY2_int", type="BES_INT_WIRE") create_wire("BES.CPE_PINY2_int", type="BES_INT_WIRE") if "RES" in type: create_wire("RES.CPE_RAM_O1", type="RES_WIRE") create_wire("RES.CPE_RAM_O2", type="RES_WIRE") create_wire("RES.CPE_COUTX", type="RES_WIRE") create_wire("RES.CPE_POUTX", type="RES_WIRE") for p in range(1,9): create_wire(f"RES.SB_Y1.P{p}", type="RES_WIRE") create_wire(f"RES.MDIE1.P{p}", type="RES_WIRE") for i in range(4): create_wire(f"RES.CLOCK{i}", type="RES_WIRE") # Internal wires create_wire("RES.SIG_SEL1_int", type="RES_INT_WIRE") create_wire("RES.SIG_SEL2_int", type="RES_INT_WIRE") create_wire("RES.SIG_SEL3_int", type="RES_INT_WIRE") create_wire("RES.SIG_SEL4_int", type="RES_INT_WIRE") if "TES" in type: create_wire("TES.CPE_RAM_O1", type="TES_WIRE") create_wire("TES.CPE_RAM_O2", type="TES_WIRE") create_wire("TES.CPE_COUTY1", type="TES_WIRE") create_wire("TES.CPE_POUTY1", type="TES_WIRE") create_wire("TES.CPE_COUTY2", type="TES_WIRE") create_wire("TES.CPE_POUTY2", type="TES_WIRE") for p in range(1,9): create_wire(f"TES.SB_Y2.P{p}", type="TES_WIRE") create_wire(f"TES.MDIE2.P{p}", type="TES_WIRE") for i in range(4): create_wire(f"TES.CLOCK{i}", type="TES_WIRE") # Internal wires create_wire("TES.SIG_SEL1_int", type="TES_INT_WIRE") create_wire("TES.SIG_SEL2_int", type="TES_INT_WIRE") create_wire("TES.SIG_SEL3_int", type="TES_INT_WIRE") create_wire("TES.SIG_SEL4_int", type="TES_INT_WIRE") return wires C_SELX = 1 << 0 C_SELY1 = 1 << 1 C_SELY2 = 1 << 2 C_SEL_C = 1 << 3 C_SEL_P = 1 << 4 C_Y12 = 1 << 5 C_CX_I = 1 << 6 C_CY1_I = 1 << 7 C_CY2_I = 1 << 8 C_PX_I = 1 << 9 C_PY1_I = 1 << 10 C_PY2_I = 1 << 11 IS_MULT = 1 << 29 IS_ADDF = 1 << 30 IS_COMP = 1 << 31 def get_mux_connections_for_type(type): muxes = [] def create_mux(src, dst, bits, value, invert, name = None, visible = True, config = False, delay = "del_dummy", block = 0, resource = 0): name = dst if name is None else name muxes.append(MUX(src, dst, name, bits, value, invert, visible, config, delay, block, resource)) def create_direct(src,dst, delay = "del_dummy"): create_mux(src,dst,0,0,False, None, visible=False, delay = delay) if "CPE" in type: # CPE for i in range(1,9): create_direct(f"CPE.IN{i}", f"CPE.IN{i}_int", delay="del_dummy") create_mux("CPE.IN2_int", "CPE.TI2_int", 1, 0, False, "C_I1", False, delay="del_dummy") create_mux("CPE.IN4_int", "CPE.TI4_int", 1, 0, False, "C_I2", False, delay="del_dummy") create_mux("CPE.IN6_int", "CPE.TI6_int", 1, 0, False, "C_I3", False, delay="del_dummy") create_mux("CPE.IN8_int", "CPE.TI8_int", 1, 0, False, "C_I4", False, delay="del_dummy") create_mux("CPE.PINY1", "CPE.TI2_int", 1, 1, False, "C_I1", False, delay="PINY1_IN2_6") create_mux("CPE.CINX", "CPE.TI4_int", 1, 1, False, "C_I2", False, delay="CINX_IN4") create_mux("CPE.PINY1", "CPE.TI6_int", 1, 1, False, "C_I3", False, delay="PINY1_IN2_6") create_mux("CPE.PINX", "CPE.TI8_int", 1, 1, False, "C_I4", False, delay="PINX_IN8") create_mux("CPE.IN1_int", "CPE.D0_00_int", 1, 0, False, "LUT2_00", False, delay="del_dummy") create_mux("CPE.TI2_int", "CPE.D1_00_int", 1, 0, False, "LUT2_00", False, delay="del_dummy") create_mux("CPE.TI2_int", "CPE.D0_00_int", 1, 1, False, "LUT2_00", False, delay="del_dummy") create_mux("CPE.IN1_int", "CPE.D1_00_int", 1, 1, False, "LUT2_00", False, delay="del_dummy") create_mux("CPE.IN3_int", "CPE.D0_01_int", 1, 0, False, "LUT2_01", False, delay="del_dummy") create_mux("CPE.TI4_int", "CPE.D1_01_int", 1, 0, False, "LUT2_01", False, delay="del_dummy") create_mux("CPE.TI4_int", "CPE.D0_01_int", 1, 1, False, "LUT2_01", False, delay="del_dummy") create_mux("CPE.IN3_int", "CPE.D1_01_int", 1, 1, False, "LUT2_01", False, delay="del_dummy") create_mux("CPE.D0_00_int", "CPE.D0_10_int", 1, 0, False, "LUT2_10", False, delay="del_dummy") create_mux("CPE.D0_01_int", "CPE.D1_10_int", 1, 0, False, "LUT2_10", False, delay="del_dummy") create_mux("CPE.D0_01_int", "CPE.D0_10_int", 1, 1, False, "LUT2_10", False, delay="del_dummy") create_mux("CPE.D0_00_int", "CPE.D1_10_int", 1, 1, False, "LUT2_10", False, delay="del_dummy") create_mux("CPE.IN5_int", "CPE.D0_02_int", 1, 0, False, "LUT2_02", False, delay="del_dummy") create_mux("CPE.TI6_int", "CPE.D1_02_int", 1, 0, False, "LUT2_02", False, delay="del_dummy") create_mux("CPE.TI6_int", "CPE.D0_02_int", 1, 1, False, "LUT2_02", False, delay="del_dummy") create_mux("CPE.IN5_int", "CPE.D1_02_int", 1, 1, False, "LUT2_02", False, delay="del_dummy") create_mux("CPE.IN7_int", "CPE.D0_03_int", 1, 0, False, "LUT2_03", False, delay="del_dummy") create_mux("CPE.TI8_int", "CPE.D1_03_int", 1, 0, False, "LUT2_03", False, delay="del_dummy") create_mux("CPE.TI8_int", "CPE.D0_03_int", 1, 1, False, "LUT2_03", False, delay="del_dummy") create_mux("CPE.IN7_int", "CPE.D1_03_int", 1, 1, False, "LUT2_03", False, delay="del_dummy") create_mux("CPE.D0_02_int", "CPE.D0_11_int", 1, 0, False, "LUT2_11", False, delay="del_dummy") create_mux("CPE.D0_03_int", "CPE.D1_11_int", 1, 0, False, "LUT2_11", False, delay="del_dummy") create_mux("CPE.D0_03_int", "CPE.D0_11_int", 1, 1, False, "LUT2_11", False, delay="del_dummy") create_mux("CPE.D0_02_int", "CPE.D1_11_int", 1, 1, False, "LUT2_11", False, delay="del_dummy") create_mux("CPE.CLK", "CPE.CLK_int", 1, 0, False, "C_CLKSEL", False, delay="del_dummy") create_mux("CPE.CINY2", "CPE.CLK_int", 1, 1, False, "C_CLKSEL", False, delay="del_dummy") create_mux("CPE.EN", "CPE.EN_int", 1, 0, False, "C_ENSEL", False, delay="del_dummy") create_mux("CPE.PINY2", "CPE.EN_int", 1, 1, False, "C_ENSEL", False, delay="del_dummy") create_mux("CPE.CINX", "CPE.COUTX", 1, 0, False, "CPE.C_CX_I", True, delay="_ROUTING_CINX_COUTX", resource=C_CX_I, block=IS_MULT | IS_ADDF) create_mux("CPE.CINY1", "CPE.COUTY1", 1, 0, False, "CPE.C_CY1_I", True, delay="_ROUTING_CINY1_COUTY1", resource=C_CY1_I, block=IS_ADDF) create_mux("CPE.CINY2", "CPE.COUTY2", 1, 0, False, "CPE.C_CY2_I", True, delay="_ROUTING_CINY2_COUTY2", resource=C_CY2_I, block=IS_MULT) create_mux("CPE.PINX", "CPE.POUTX", 1, 0, False, "CPE.C_PX_I", True, delay="_ROUTING_PINX_POUTX", resource=C_PX_I, block=IS_MULT | IS_COMP) create_mux("CPE.PINY1", "CPE.POUTY1", 1, 0, False, "CPE.C_PY1_I", True, delay="_ROUTING_PINY1_POUTY1", resource=C_PY1_I, block=IS_COMP) create_mux("CPE.PINY2", "CPE.POUTY2", 1, 0, False, "CPE.C_PY2_I", True, delay="_ROUTING_PINY2_POUTY2", resource=C_PY2_I, block=IS_MULT) create_mux("CPE.OUT1_IN_int", "CPE.CX_OUT", 1, 0, False, "CPE.C_SELX", True, delay="comb12_COUTX", resource=C_SELX) create_mux("CPE.OUT2_IN_int", "CPE.CX_OUT", 1, 1, False, "CPE.C_SELX", True, delay="comb12_COUTX", resource=C_SELX) create_mux("CPE.OUT1_IN_int", "CPE.CY1_OUT", 1, 1, False, "CPE.C_SELY1", True, delay="comb12_COUTY1", resource=C_SELY1) create_mux("CPE.OUT2_IN_int", "CPE.CY1_OUT", 1, 0, False, "CPE.C_SELY1", True, delay="comb12_COUTY1", resource=C_SELY1) create_mux("CPE.OUT1_IN_int", "CPE.CY2_OUT", 1, 0, False, "CPE.C_SELY2", True, delay="comb12_COUTY2", resource=C_SELY2) create_mux("CPE.OUT2_IN_int", "CPE.CY2_OUT", 1, 1, False, "CPE.C_SELY2", True, delay="comb12_COUTY2", resource=C_SELY2) create_mux("CPE.OUT1_IN_int", "CPE.PX_OUT", 1, 1, False, "CPE.C_SELX", True, delay="comb12_POUTX", resource=C_SELX) create_mux("CPE.OUT2_IN_int", "CPE.PX_OUT", 1, 0, False, "CPE.C_SELX", True, delay="comb12_POUTX", resource=C_SELX) create_mux("CPE.OUT1_IN_int", "CPE.PY1_OUT", 1, 0, False, "CPE.C_SELY1", True, delay="comb12_POUTY1", resource=C_SELY1) create_mux("CPE.OUT2_IN_int", "CPE.PY1_OUT", 1, 1, False, "CPE.C_SELY1", True, delay="comb12_POUTY1", resource=C_SELY1) create_mux("CPE.OUT1_IN_int", "CPE.PY2_OUT", 1, 1, False, "CPE.C_SELY2", True, delay="comb12_POUTY2", resource=C_SELY2) create_mux("CPE.OUT2_IN_int", "CPE.PY2_OUT", 1, 0, False, "CPE.C_SELY2", True, delay="comb12_POUTY2", resource=C_SELY2) create_mux("CPE.CINY1", "CPE.CIY12", 1, 0, False, "CPE.C_Y12", True, delay="_ROUTING_CINY1_COUTX", resource=C_Y12) create_mux("CPE.CINY2", "CPE.CIY12", 1, 1, False, "CPE.C_Y12", True, delay="_ROUTING_CINY2_COUTX", resource=C_Y12) create_mux("CPE.PINY1", "CPE.PIY12", 1, 0, False, "CPE.C_Y12", True, delay="_ROUTING_PINY1_POUTX", resource=C_Y12) create_mux("CPE.PINY2", "CPE.PIY12", 1, 1, False, "CPE.C_Y12", True, delay="_ROUTING_PINY1_POUTX", resource=C_Y12) # No data in timing info for this create_mux("CPE.CIY12", "CPE.CX_OUT2", 1, 1, False, "CPE.C_SELX", True, delay="del_dummy", resource=C_SELX) create_mux("CPE.COMPOUT_IN_int", "CPE.CX_OUT2", 1, 0, False, "CPE.C_SELX", True, delay="comb12_compout_COUTX", resource=C_SELX) create_mux("CPE.CINX", "CPE.CY1_OUT2", 1, 1, False, "CPE.C_SELY1", True, delay="_ROUTING_CINX_COUTY1", resource=C_SELY1) create_mux("CPE.COMPOUT_IN_int", "CPE.CY1_OUT2", 1, 0, False, "CPE.C_SELY1", True, delay="comb12_compout_COUTY1", resource=C_SELY1) create_mux("CPE.CINX", "CPE.CY2_OUT2", 1, 1, False, "CPE.C_SELY2", True, delay="_ROUTING_CINX_COUTY2", resource=C_SELY2) create_mux("CPE.COMPOUT_IN_int", "CPE.CY2_OUT2", 1, 0, False, "CPE.C_SELY2", True, delay="comb12_compout_COUTY2", resource=C_SELY2) create_mux("CPE.PIY12", "CPE.PX_OUT2", 1, 1, False, "CPE.C_SELX", True, delay="del_dummy", resource=C_SELX) create_mux("CPE.COMPOUT_IN_int", "CPE.PX_OUT2", 1, 0, False, "CPE.C_SELX", True, delay="comb12_compout_POUTX", resource=C_SELX) create_mux("CPE.PINX", "CPE.PY1_OUT2", 1, 1, False, "CPE.C_SELY1", True, delay="_ROUTING_PINX_POUTY1", resource=C_SELY1) create_mux("CPE.COMPOUT_IN_int", "CPE.PY1_OUT2", 1, 0, False, "CPE.C_SELY1", True, delay="comb12_compout_POUTY1", resource=C_SELY1) create_mux("CPE.PINX", "CPE.PY2_OUT2", 1, 1, False, "CPE.C_SELY2", True, delay="_ROUTING_PINX_POUTY2", resource=C_SELY2) create_mux("CPE.COMPOUT_IN_int", "CPE.PY2_OUT2", 1, 0, False, "CPE.C_SELY2", True, delay="comb12_compout_POUTY2", resource=C_SELY2) create_mux("CPE.CX_OUT", "CPE.CX_VAL", 1, 0, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.CY1_OUT", "CPE.CY1_VAL", 1, 0, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.CY2_OUT", "CPE.CY2_VAL", 1, 0, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.PX_OUT", "CPE.PX_VAL", 1, 0, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.PY1_OUT", "CPE.PY1_VAL", 1, 0, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.PY2_OUT", "CPE.PY2_VAL", 1, 0, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.CX_OUT2", "CPE.CX_VAL", 1, 1, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.CY1_OUT2", "CPE.CY1_VAL", 1, 1, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.CY2_OUT2", "CPE.CY2_VAL", 1, 1, False, "CPE.C_SEL_C", True, delay="del_dummy", resource=C_SEL_C) create_mux("CPE.PX_OUT2", "CPE.PX_VAL", 1, 1, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.PY1_OUT2", "CPE.PY1_VAL", 1, 1, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.PY2_OUT2", "CPE.PY2_VAL", 1, 1, False, "CPE.C_SEL_P", True, delay="del_dummy", resource=C_SEL_P) create_mux("CPE.CX_VAL", "CPE.COUTX", 1, 1, False, "CPE.C_CX_I", True, delay="del_dummy", resource=C_CX_I, block=IS_MULT | IS_ADDF) create_mux("CPE.CY1_VAL", "CPE.COUTY1", 1, 1, False, "CPE.C_CY1_I", True, delay="del_dummy", resource=C_CY1_I, block=IS_ADDF) create_mux("CPE.CY2_VAL", "CPE.COUTY2", 1, 1, False, "CPE.C_CY2_I", True, delay="del_dummy", resource=C_CY2_I, block=IS_MULT) create_mux("CPE.PX_VAL", "CPE.POUTX", 1, 1, False, "CPE.C_PX_I", True, delay="del_dummy", resource=C_PX_I, block=IS_MULT | IS_COMP) create_mux("CPE.PY1_VAL", "CPE.POUTY1", 1, 1, False, "CPE.C_PY1_I", True, delay="del_dummy", resource=C_PY1_I, block=IS_COMP) create_mux("CPE.PY2_VAL", "CPE.POUTY2", 1, 1, False, "CPE.C_PY2_I", True, delay="del_dummy", resource=C_PY2_I, block=IS_MULT) for p in range(1,13): plane = f"{p:02d}" for i in range(8): create_mux(f"IM.P{plane}.D{i}", f"IM.P{plane}.Y", 3, i, True, f"IM.P{plane}", delay = f"im_x1_y1_p{p}_d{i}_path2") if "OM" in type and p>=9: for i in range(4): create_mux(f"OM.P{plane}.D{i}", f"OM.P{plane}.Y", 2, i, True, f"OM.P{plane}", delay = f"om_x1_y1_p{p}_d{i}") for i in range(1,9): create_mux(f"CPE.IN{i}_int", "CPE.MUXOUT_int", 3, i-1, False, "CPE.C_SN", True, delay=f"_MX8_IN{i}_OUT1") create_direct("IM.P01.Y","CPE.IN1") create_direct("IM.P02.Y","CPE.IN2") create_direct("IM.P03.Y","CPE.IN3") create_direct("IM.P04.Y","CPE.IN4") create_direct("IM.P05.Y","CPE.IN5") create_direct("IM.P06.Y","CPE.IN6") create_direct("IM.P07.Y","CPE.IN7") create_direct("IM.P08.Y","CPE.IN8") create_direct("IM.P09.Y","CPE.CLK") create_direct("IM.P10.Y","CPE.EN") create_direct("IM.P11.Y","CPE.SR") for p in range(1,13): plane = f"{p:02d}" # D6 and D7 are from alternate planes alt = f"{alt_plane(0,p):02d}" create_direct(f"IM.P{alt}.Y", f"IM.P{plane}.D6", f"im_x1_y1_p{p}_d6_path1") alt = f"{alt_plane(1,p):02d}" create_direct(f"IM.P{alt}.Y", f"IM.P{plane}.D7", f"im_x1_y1_p{p}_d7_path1") create_mux("CPE.DOUT1_int", "CPE.OUT1_int", 2, 0, False, "CPE.C_O1", delay="del_dummy") create_mux("CPE.MUXOUT_int", "CPE.OUT1_int", 2, 1, False, "CPE.C_O1", delay="del_dummy") create_mux("CPE.CPOUT1_int", "CPE.OUT1_int", 2, 2, False, "CPE.C_O1", delay="del_dummy") create_mux("CPE.COMBOUT1_int", "CPE.OUT1_int", 2, 3, False, "CPE.C_O1", delay="del_dummy") create_direct("CPE.COMBOUT1_int", "CPE.DIN1_int", delay="del_dummy") create_mux("CPE.DOUT2_int", "CPE.OUT2_int", 2, 0, False, "CPE.C_O2", delay="del_dummy") create_mux("CPE.MUXOUT_int", "CPE.OUT2_int", 2, 1, False, "CPE.C_O2", delay="del_dummy") create_mux("CPE.CPOUT2_int", "CPE.OUT2_int", 2, 2, False, "CPE.C_O2", delay="del_dummy") create_mux("CPE.COMBOUT2_int", "CPE.OUT2_int", 2, 3, False, "CPE.C_O2", delay="del_dummy") create_mux("CPE.MUXOUT_int", "CPE.DIN2_int", 1, 1, False, "CPE.C_BR", delay="del_dummy") create_mux("CPE.COMBOUT1_int", "CPE.DIN2_int", 1, 0, False, "CPE.C_2D_IN", delay="del_dummy") create_mux("CPE.COMBOUT2_int", "CPE.DIN2_int", 1, 1, False, "CPE.C_2D_IN", delay="del_dummy") # Virtual connections create_direct("CPE.COMBOUT1_int", "CPE.COMBIN1_int", delay="del_dummy") create_direct("CPE.COMBOUT2_int", "CPE.COMBIN2_int", delay="del_dummy") create_direct("CPE.OUT1", "CPE.OUT1_IN_int", delay="del_dummy") create_direct("CPE.OUT2", "CPE.OUT2_IN_int", delay="del_dummy") create_direct("CPE.COMPOUT_int", "CPE.COMPOUT_IN_int", delay="del_dummy") create_direct("CPE.OUT1_int", "CPE.OUT1", delay="del_dummy") create_direct("CPE.OUT2_int", "CPE.OUT2", delay="del_dummy") # Connecting upper and lower L2T4 create_direct("CPE.COMBOUT2_int", "CPE.COMBIN_int", delay="del_dummy") if "SB_BIG" in type: # SB_BIG for p in range(1,13): delay = "sb_del_t1_x1_y1" plane = f"{p:02d}" # Per Y output mux for i in range(1,5): create_mux(f"SB_BIG.P{plane}.D0", f"SB_BIG.P{plane}.Y{i}", 3, 0, True, delay=f"{delay}_p{p}_d{i}_s0") create_mux(f"SB_BIG.P{plane}.YDIAG", f"SB_BIG.P{plane}.Y{i}", 3, 1, True, delay=f"{delay}_p{p}_d{i}_s1") create_mux(f"SB_BIG.P{plane}.D2_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 2, True, delay=f"{delay}_p{p}_d{i}_s2") create_mux(f"SB_BIG.P{plane}.D3_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 3, True, delay=f"{delay}_p{p}_d{i}_s3") create_mux(f"SB_BIG.P{plane}.D4_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 4, True, delay=f"{delay}_p{p}_d{i}_s4") create_mux(f"SB_BIG.P{plane}.D5_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 5, True, delay=f"{delay}_p{p}_d{i}_s5") create_mux(f"SB_BIG.P{plane}.D6_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 6, True, delay=f"{delay}_p{p}_d{i}_s6") create_mux(f"SB_BIG.P{plane}.D7_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 7, True, delay=f"{delay}_p{p}_d{i}_s7") # YDIAG output mux create_mux(f"SB_BIG.P{plane}.Y1", f"SB_BIG.P{plane}.YDIAG", 3, 0, True, delay=f"{delay}_p{p}_d0_s0") create_mux(f"SB_BIG.P{plane}.Y2", f"SB_BIG.P{plane}.YDIAG", 3, 1, True, delay=f"{delay}_p{p}_d0_s1") create_mux(f"SB_BIG.P{plane}.Y3", f"SB_BIG.P{plane}.YDIAG", 3, 2, True, delay=f"{delay}_p{p}_d0_s2") create_mux(f"SB_BIG.P{plane}.Y4", f"SB_BIG.P{plane}.YDIAG", 3, 3, True, delay=f"{delay}_p{p}_d0_s3") create_mux(f"SB_BIG.P{plane}.X34", f"SB_BIG.P{plane}.YDIAG", 3, 4, True, delay=f"{delay}_p{p}_d0_s4") create_mux(f"SB_BIG.P{plane}.X14", f"SB_BIG.P{plane}.YDIAG", 3, 5, True, delay=f"{delay}_p{p}_d0_s5") create_mux(f"SB_BIG.P{plane}.X12", f"SB_BIG.P{plane}.YDIAG", 3, 6, True, delay=f"{delay}_p{p}_d0_s6") create_mux(f"SB_BIG.P{plane}.X23", f"SB_BIG.P{plane}.YDIAG", 3, 7, True, delay=f"{delay}_p{p}_d0_s7") for i in range(1,5): create_mux(f"SB_DRIVE.P{plane}.D{i}.IN", f"SB_DRIVE.P{plane}.D{i}.OUT", 1, 1, True, f"SB_DRIVE.P{plane}.D{i}", delay="del_sb_drv") create_mux(f"SB_DRIVE.P{plane}.D{i}.IN", f"SB_DRIVE.P{plane}.D{i}.OUT_NOINV", 1, 1, False, f"SB_DRIVE.P{plane}.D{i}", delay="del_sb_drv") create_direct(f"SB_BIG.P{plane}.Y{i}", f"SB_DRIVE.P{plane}.D{i}.IN",delay="del_dummy") create_direct(f"SB_BIG.P{plane}.D0_IO", f"SB_BIG.P{plane}.D0",delay="del_dummy") for i in range(1,5): create_direct(f"SB_BIG.P{plane}.D7_{i}_CLK", f"SB_BIG.P{plane}.D7_{i}",delay="del_dummy") create_direct(f"SB_BIG.P{plane}.D2_{i}_D2D", f"SB_BIG.P{plane}.D2_{i}",delay="del_dummy") if "SB_SML" in type: # SB_SML for p in range(1,13): delay = "sb_del_t1_x2_y2" plane = f"{p:02d}" # Per Y output mux for i in range(1,5): create_mux(f"SB_SML.P{plane}.D0", f"SB_SML.P{plane}.Y{i}_int", 2, 0, False, f"SB_SML.P{plane}.Y{i}", delay=f"{delay}_p{p}_d{i}_s0") create_mux(f"SB_SML.P{plane}.YDIAG_int",f"SB_SML.P{plane}.Y{i}_int", 2, 1, False, f"SB_SML.P{plane}.Y{i}", delay=f"{delay}_p{p}_d{i}_s1") create_mux(f"SB_SML.P{plane}.D2_{i}", f"SB_SML.P{plane}.Y{i}_int", 2, 2, False, f"SB_SML.P{plane}.Y{i}", delay=f"{delay}_p{p}_d{i}_s2") create_mux(f"SB_SML.P{plane}.D3_{i}", f"SB_SML.P{plane}.Y{i}_int", 2, 3, False, f"SB_SML.P{plane}.Y{i}", delay=f"{delay}_p{p}_d{i}_s3") # YDIAG output mux create_mux(f"SB_SML.P{plane}.Y1_int", f"SB_SML.P{plane}.YDIAG_int", 3, 0, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s0") create_mux(f"SB_SML.P{plane}.Y2_int", f"SB_SML.P{plane}.YDIAG_int", 3, 1, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s1") create_mux(f"SB_SML.P{plane}.Y3_int", f"SB_SML.P{plane}.YDIAG_int", 3, 2, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s2") create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.YDIAG_int", 3, 3, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s3") create_mux(f"SB_SML.P{plane}.X34", f"SB_SML.P{plane}.YDIAG_int", 3, 4, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s4") create_mux(f"SB_SML.P{plane}.X14", f"SB_SML.P{plane}.YDIAG_int", 3, 5, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s5") create_mux(f"SB_SML.P{plane}.X12", f"SB_SML.P{plane}.YDIAG_int", 3, 6, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s6") create_mux(f"SB_SML.P{plane}.X23", f"SB_SML.P{plane}.YDIAG_int", 3, 7, False, f"SB_SML.P{plane}.YDIAG", delay=f"{delay}_p{p}_d0_s7") create_mux(f"SB_SML.P{plane}.Y1_int", f"SB_SML.P{plane}.Y1", 1, 1, True, f"SB_SML.P{plane}.Y1_INT", False) create_mux(f"SB_SML.P{plane}.Y2_int", f"SB_SML.P{plane}.Y2", 1, 1, True, f"SB_SML.P{plane}.Y2_INT", False) create_mux(f"SB_SML.P{plane}.Y3_int", f"SB_SML.P{plane}.Y3", 1, 1, True, f"SB_SML.P{plane}.Y3_INT", False) create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.Y4", 1, 1, True, f"SB_SML.P{plane}.Y4_INT", False) create_mux(f"SB_SML.P{plane}.YDIAG_int", f"SB_SML.P{plane}.YDIAG", 1, 1, True, f"SB_SML.P{plane}.YDIAG_INT", False) for i in range(1,5): create_direct(f"SB_SML.P{plane}.D2_{i}_D2D", f"SB_SML.P{plane}.D2_{i}",delay="del_dummy") create_direct(f"SB_SML.P{plane}.D0_IO", f"SB_SML.P{plane}.D0",delay="del_dummy") if "GPIO" in type: # GPIO create_direct("IOSEL.GPIO_OUT", "GPIO.A", delay="del_dummy") create_direct("IOSEL.GPIO_EN", "GPIO.T", delay="del_dummy") create_direct("GPIO.Y", "IOSEL.GPIO_IN", delay="del_dummy") if "IOES" in type: # IOES for p in range(1,13): plane = f"{p:02d}" io_in = 1 if p % 2 else 2 create_mux(f"IOES.IO_IN{io_in}", f"IOES.SB_IN_{plane}", 1, 0, False) create_mux(f"IOES.ALTIN_{plane}", f"IOES.SB_IN_{plane}", 1, 1, False) if "LES" in type: for p in range(1,9): create_mux(f"LES.SB_Y3.P{p}", "LES.SB_Y3_SEL1_int", 3, p-1, False, "LES.SB_Y3_SEL1", delay="del_dummy") create_mux(f"LES.MDIE1.P{p}", "LES.MDIE1_SEL1_int", 3, p-1, False, "LES.MDIE1_SEL1", delay="del_dummy") create_mux(f"LES.SB_Y3.P{p}", "LES.SB_Y3_SEL2_int", 3, p-1, False, "LES.SB_Y3_SEL2", delay="del_dummy") create_mux(f"LES.MDIE1.P{p}", "LES.MDIE1_SEL2_int", 3, p-1, False, "LES.MDIE1_SEL2", delay="del_dummy") for i in range(4): create_mux(f"LES.CLOCK{i}", "LES.CLOCK_SEL1_int", 2, i, False, "LES.CLOCK_SEL1", delay="del_dummy") create_mux(f"LES.CLOCK{i}", "LES.CLOCK_SEL2_int", 2, i, False, "LES.CLOCK_SEL2", delay="del_dummy") # Note there is error in schematics create_mux("LES.SB_Y3_SEL1_int", "LES.CPE_CINX", 2, 1, False, "LES.CINX_SEL", delay="del_left_SB_couty2") create_mux("LES.MDIE1_SEL1_int", "LES.CPE_CINX", 2, 2, False, "LES.CINX_SEL", delay="del_left_couty2") create_mux("LES.CLOCK_SEL1_int", "LES.CPE_CINX", 2, 3, False, "LES.CINX_SEL", delay="del_left_glb_couty2") create_mux("LES.SB_Y3_SEL2_int", "LES.CPE_PINX", 2, 1, False, "LES.PINX_SEL", delay="del_left_SB_pouty2") create_mux("LES.MDIE1_SEL2_int", "LES.CPE_PINX", 2, 2, False, "LES.PINX_SEL", delay="del_left_pouty2") create_mux("LES.CLOCK_SEL2_int", "LES.CPE_PINX", 2, 3, False, "LES.PINX_SEL", delay="del_left_glb_pouty2") if "BES" in type: for p in range(1,9): create_mux(f"BES.SB_Y4.P{p}", "BES.SB_Y4_SEL1_int", 3, p-1, False, "BES.SB_Y4_SEL1", delay="del_dummy") create_mux(f"BES.MDIE2.P{p}", "BES.MDIE2_SEL1_int", 3, p-1, False, "BES.MDIE2_SEL1", delay="del_dummy") create_mux(f"BES.SB_Y4.P{p}", "BES.SB_Y4_SEL2_int", 3, p-1, False, "BES.SB_Y4_SEL2", delay="del_dummy") create_mux(f"BES.MDIE2.P{p}", "BES.MDIE2_SEL2_int", 3, p-1, False, "BES.MDIE2_SEL2", delay="del_dummy") create_mux(f"BES.SB_Y4.P{p}", "BES.SB_Y4_SEL3_int", 3, p-1, False, "BES.SB_Y4_SEL3", delay="del_dummy") create_mux(f"BES.MDIE2.P{p}", "BES.MDIE2_SEL3_int", 3, p-1, False, "BES.MDIE2_SEL3", delay="del_dummy") create_mux(f"BES.SB_Y4.P{p}", "BES.SB_Y4_SEL4_int", 3, p-1, False, "BES.SB_Y4_SEL4", delay="del_dummy") create_mux(f"BES.MDIE2.P{p}", "BES.MDIE2_SEL4_int", 3, p-1, False, "BES.MDIE2_SEL4", delay="del_dummy") for i in range(4): create_mux(f"BES.CLOCK{i}", "BES.CLOCK_SEL1_int", 2, i, False, "BES.CLOCK_SEL1", delay="del_dummy") create_mux(f"BES.CLOCK{i}", "BES.CLOCK_SEL2_int", 2, i, False, "BES.CLOCK_SEL2", delay="del_dummy") create_mux(f"BES.CLOCK{i}", "BES.CLOCK_SEL3_int", 2, i, False, "BES.CLOCK_SEL3", delay="del_dummy") create_mux(f"BES.CLOCK{i}", "BES.CLOCK_SEL4_int", 2, i, False, "BES.CLOCK_SEL4", delay="del_dummy") create_mux("BES.SB_Y4_SEL1_int", "BES.CPE_CINY1_int", 2, 1, False, "BES.CINY1_SEL", delay="del_bot_SB_couty2") create_mux("BES.MDIE2_SEL1_int", "BES.CPE_CINY1_int", 2, 2, False, "BES.CINY1_SEL", delay="del_bot_couty2") create_mux("BES.CLOCK_SEL1_int", "BES.CPE_CINY1_int", 2, 3, False, "BES.CINY1_SEL", delay="del_bot_glb_couty2") create_mux("BES.SB_Y4_SEL2_int", "BES.CPE_PINY1_int", 2, 1, False, "BES.PINY1_SEL", delay="del_bot_SB_pouty2") create_mux("BES.MDIE2_SEL2_int", "BES.CPE_PINY1_int", 2, 2, False, "BES.PINY1_SEL", delay="del_bot_pouty2") create_mux("BES.CLOCK_SEL2_int", "BES.CPE_PINY1_int", 2, 3, False, "BES.PINY1_SEL", delay="del_bot_glb_pouty2") create_mux("BES.SB_Y4_SEL3_int", "BES.CPE_CINY2_int", 2, 1, False, "BES.CINY2_SEL", delay="del_bot_SB_couty2") create_mux("BES.MDIE2_SEL3_int", "BES.CPE_CINY2_int", 2, 2, False, "BES.CINY2_SEL", delay="del_bot_couty2") create_mux("BES.CLOCK_SEL3_int", "BES.CPE_CINY2_int", 2, 3, False, "BES.CINY2_SEL", delay="del_bot_glb_couty2") create_mux("BES.SB_Y4_SEL4_int", "BES.CPE_PINY2_int", 2, 1, False, "BES.PINY2_SEL", delay="del_bot_SB_pouty2") create_mux("BES.MDIE2_SEL4_int", "BES.CPE_PINY2_int", 2, 2, False, "BES.PINY2_SEL", delay="del_bot_pouty2") create_mux("BES.CLOCK_SEL4_int", "BES.CPE_PINY2_int", 2, 3, False, "BES.PINY2_SEL", delay="del_bot_glb_pouty2") create_mux("BES.CPE_CINY1_int", "BES.CPE_CINY1", 1, 0, False, "BES.P_CINY1", delay="del_dummy") create_mux("BES.P_CINY1", "BES.CPE_CINY1", 1, 1, False, "BES.P_CINY1", delay="del_dummy") create_mux("BES.CPE_PINY1_int", "BES.CPE_PINY1", 1, 0, False, "BES.P_PINY1", delay="del_dummy") create_mux("BES.P_PINY1", "BES.CPE_PINY1", 1, 1, False, "BES.P_PINY1", delay="del_dummy") create_mux("BES.CPE_CINY2_int", "BES.CPE_CINY2", 1, 0, False, "BES.P_CINY2", delay="del_dummy") create_mux("BES.P_CINY2", "BES.CPE_CINY2", 1, 1, False, "BES.P_CINY2", delay="del_dummy") create_mux("BES.CPE_PINY2_int", "BES.CPE_PINY2", 1, 0, False, "BES.P_PINY2", delay="del_dummy") create_mux("BES.P_PINY2", "BES.CPE_PINY2", 1, 1, False, "BES.P_PINY2", delay="del_dummy") if "RES" in type: for sel in range(4): create_mux("RES.CPE_RAM_O1", f"RES.SIG_SEL{sel+1}_int", 3, 0, False, f"RES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("RES.CPE_RAM_O2", f"RES.SIG_SEL{sel+1}_int", 3, 1, False, f"RES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("RES.CPE_COUTX", f"RES.SIG_SEL{sel+1}_int", 3, 2, False, f"RES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("RES.CPE_POUTX", f"RES.SIG_SEL{sel+1}_int", 3, 3, False, f"RES.SIG_SEL{sel+1}", delay="del_dummy") for i in range(4): create_mux(f"RES.CLOCK{i}", f"RES.SIG_SEL{sel+1}_int", 3, 4 + i, False, f"RES.SIG_SEL{sel+1}", delay="del_dummy") for p in range(1,9): create_mux(f"RES.SB_Y1.P{p}", f"RES.MDIE1.P{p}", 1, 0, False, f"RES.SEL_MDIE{p}", delay="del_dummy") sel = ((p - 1) & 3) + 1 create_mux(f"RES.SIG_SEL{sel}_int", f"RES.MDIE1.P{p}", 1, 1, False, f"RES.SEL_MDIE{p}", delay="del_dummy") if "TES" in type: for sel in range(4): create_mux("TES.CPE_RAM_O1", f"TES.SIG_SEL{sel+1}_int", 3, 0, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("TES.CPE_RAM_O2", f"TES.SIG_SEL{sel+1}_int", 3, 1, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("TES.CPE_COUTY1", f"TES.SIG_SEL{sel+1}_int", 3, 2, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("TES.CPE_POUTY1", f"TES.SIG_SEL{sel+1}_int", 3, 3, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("TES.CPE_COUTY2", f"TES.SIG_SEL{sel+1}_int", 3, 4, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux("TES.CPE_POUTY2", f"TES.SIG_SEL{sel+1}_int", 3, 5, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") clk = 0 if sel < 2 else 2 create_mux(f"TES.CLOCK{clk+0}", f"TES.SIG_SEL{sel+1}_int", 3, 6, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") create_mux(f"TES.CLOCK{clk+1}", f"TES.SIG_SEL{sel+1}_int", 3, 7, False, f"TES.SIG_SEL{sel+1}", delay="del_dummy") for p in range(1,9): create_mux(f"TES.SB_Y2.P{p}", f"TES.MDIE2.P{p}", 1, 0, False, f"TES.SEL_MDIE{p}", delay="del_dummy") sel = ((p - 1) & 3) + 1 create_mux(f"TES.SIG_SEL{sel}_int", f"TES.MDIE2.P{p}", 1, 1, False, f"TES.SEL_MDIE{p}", delay="del_dummy") if "PLL" in type: for i in range(0,4): create_direct(f"CLKIN.CLK_REF{i}", f"PLL{i}.CLK_REF", delay="del_dummy") create_direct(f"PLL{i}.CLK0", f"GLBOUT.CLK0_{i}", delay="del_dummy") create_direct(f"PLL{i}.CLK90", f"GLBOUT.CLK90_{i}", delay="del_dummy") create_direct(f"PLL{i}.CLK180", f"GLBOUT.CLK180_{i}", delay="del_dummy") create_direct(f"PLL{i}.CLK270", f"GLBOUT.CLK270_{i}", delay="del_dummy") create_direct(f"PLL{i}.CLK_REF_OUT", f"GLBOUT.CLK_REF_OUT{i}", delay="del_dummy") create_direct(f"GLBOUT.CLK_FB{i}", f"PLL{i}.CLK_FEEDBACK", delay="del_dummy") create_mux(f"CLKIN.CLK_REF{i}", f"GLBOUT.CLK_REF_OUT{i}", 1, 0, False, f"PLL{i}.USR_CLK_OUT", config=True, delay="del_dummy") create_mux(f"PLL{i}.USR_CLK_REF", f"GLBOUT.CLK_REF_OUT{i}", 1, 1, False, f"PLL{i}.USR_CLK_OUT", config=True, delay="del_dummy") return muxes def get_tile_types(x,y): val = list() if is_cpe(x,y): val.append("CPE") val.append("IM") if is_outmux(x,y): val.append("OM") if is_sb_big(x,y): val.append("SB_BIG") if is_sb_sml(x,y): val.append("SB_SML") if is_gpio(x,y): val.append("GPIO") if is_edge_io(x,y): val.append("IOES") if is_edge_top(x,y): val.append("TES") if is_edge_bottom(x,y): val.append("BES") if is_edge_left(x,y): val.append("LES") if is_edge_right(x,y): val.append("RES") if is_pll(x,y): val.append("PLL") if is_serdes(x,y): val.append("SERDES") if is_cfg_ctrl(x,y): val.append("CFG_CTRL") if is_ram_u(x,y): val.append("RAM_U") if is_ram_l(x,y): val.append("RAM_L") return val def get_tile_type(x,y): val = get_tile_types(x,y) if not val: val.append("NONE") return "_".join(val) def get_tile_type_list(): tt = set() for y in range(-2, max_row()+1): for x in range(-2, max_col()+1): tt.add(get_tile_type(x,y)) return tt def get_bitstream_tile(x, y): # Edge blocks are bit bigger if x == -2: x += 1 if x == max_col(): x -= 1 if y == -2: y += 1 if y == max_row(): y -= 1 return (x + 1) // 2, (y + 1) // 2 def get_tile_info(d,x,y): bx, by = get_bitstream_tile(x,y) pos = 0 if is_cpe(x,y): pos = ((x+1) % 2) * 2 + ((y+1) % 2) + 1 if is_edge_top(x,y): pos = (x - 1) % 2 + 1 if is_edge_bottom(x,y): pos = (x - 1) % 2 + 1 if is_edge_left(x,y): pos = (y - 1) % 2 + 1 if is_edge_right(x,y): pos = (y - 1) % 2 + 1 tile_x = ((x-1)+16) % 8 tile_y = ((y-1)+16) % 8 return TileInfo(d, bx, by, tile_x, tile_y, pos) def alt_plane(dir,plane): alt = [[5, 6, 7, 8, 1, 2, 3, 4,11,12, 9,10], [9,10,11,12, 9,10,11,12,12,11,10, 9]] return alt[dir][plane-1] def prev_plane(p): return (p-2) % 12 + 1 def next_plane(p): return p % 12 + 1 class Die: def __init__(self, name : str, die_x : int, die_y : int): self.name = name self.die_x = die_x self.die_y = die_y self.debug_conn = False self.offset_x = die_x * num_cols() self.offset_y = die_y * num_rows() self.io_pad_names = dict() self.gpio_to_loc = dict() self.conn = dict() self.rev_conn = dict() self.ddr_i = dict() for y in range(-2, max_row()+1): for x in range(-2, max_col()+1): if is_gpio(x,y): io = get_io_name(x,y) if io.bank not in self.io_pad_names: self.io_pad_names[io.bank] = dict() if io.port not in self.io_pad_names[io.bank]: self.io_pad_names[io.bank][io.port] = dict() if io.num not in self.io_pad_names[io.bank][io.port]: self.io_pad_names[io.bank][io.port][io.num] = dict() self.gpio_to_loc[f"GPIO_{io.bank}_{io.port}[{io.num}]"] = Location(x, y, 0) self.io_pad_names[io.bank][io.port][io.num] = Location(x, y, 0) def create_conn(self, src_x,src_y, src, dst_x, dst_y, dst, delay="del_dummy"): key_val = f"{src_x + self.offset_x}/{src_y + self.offset_y}/{src}" key = Connection(src_x + self.offset_x, src_y + self.offset_y, src, "" , False) item = Connection(dst_x + self.offset_x, dst_y + self.offset_y, dst, delay, True) if key_val not in self.conn: self.conn[key_val] = list() self.conn[key_val].append(key) self.conn[key_val].append(item) if "CPE.RAM_I" in dst: rev_key_val = f"{dst_x + self.offset_x}/{dst_y + self.offset_y}/{dst}" if rev_key_val not in self.rev_conn: self.rev_conn[rev_key_val] = list() self.rev_conn[rev_key_val].append(item) self.rev_conn[rev_key_val].append(key) if self.debug_conn: print(f"({src_x + self.offset_x},{src_y}) {src} => ({dst_x + self.offset_x},{dst_y + self.offset_y}) {dst}") def get_connections_for(self, src_x,src_y, src): key_val = f"{src_x + self.offset_x}/{src_y + self.offset_y}/{src}" if key_val in self.conn: return self.conn[key_val] return list() def get_connections_to(self, dst_x, dst_y, dst): rev_key_val = f"{dst_x + self.offset_x}/{dst_y + self.offset_y}/{dst}" if rev_key_val in self.rev_conn: return self.rev_conn[rev_key_val] return list() def create_cpe(self, x,y): if is_cpe(x,y-1): self.create_conn(x,y-1,"CPE.COUTY1", x,y,"CPE.CINY1") self.create_conn(x,y-1,"CPE.COUTY2", x,y,"CPE.CINY2") self.create_conn(x,y-1,"CPE.POUTY1", x,y,"CPE.PINY1") self.create_conn(x,y-1,"CPE.POUTY2", x,y,"CPE.PINY2") if is_cpe(x-1,y): self.create_conn(x-1,y,"CPE.COUTX", x,y,"CPE.CINX") self.create_conn(x-1,y,"CPE.POUTX", x,y,"CPE.PINX") def create_inmux(self, x,y): for p in range(1,13): plane = f"{p:02d}" # D0 - D3 are from nearby SBs offset = 2 if is_sb(x,y) else 1 self.create_conn(x-offset,y,f"{get_sb_type(x-offset,y)}.P{plane}.Y1", x,y,f"IM.P{plane}.D0", f"im_x1_y1_p{p}_d0_path1") self.create_conn(x,y-offset,f"{get_sb_type(x,y-offset)}.P{plane}.Y2", x,y,f"IM.P{plane}.D1", f"im_x1_y1_p{p}_d1_path1") self.create_conn(x+offset,y,f"{get_sb_type(x+offset,y)}.P{plane}.Y3", x,y,f"IM.P{plane}.D2", f"im_x1_y1_p{p}_d2_path1") self.create_conn(x,y+offset,f"{get_sb_type(x,y+offset)}.P{plane}.Y4", x,y,f"IM.P{plane}.D3", f"im_x1_y1_p{p}_d3_path1") # D4 and D5 are from diagonal INMUX if is_cpe(x-1,y-1): self.create_conn(x-1,y-1,f"IM.P{plane}.Y", x,y,f"IM.P{plane}.D4", f"im_x1_y1_p{p}_d4_path1") if is_cpe(x+1,y+1): self.create_conn(x+1,y+1,f"IM.P{plane}.Y", x,y,f"IM.P{plane}.D5", f"im_x1_y1_p{p}_d5_path1") def create_sb(self, x,y): x_0,y_0 = base_loc(x,y) sb_type = get_sb_type(x,y) for p in range(1,13): plane = f"{p:02d}" # Handling input D0 if is_cpe(x,y): # Core section SBs are connected to CPE if p < 9: # planes 1..8 x_cpe = x_0 + (1 if (p-1) & 2 else 0) y_cpe = y_0 + (1 if (p-1) & 1 else 0) # alternate patterns for lower-left SB(1,1) and upper-right SB(2,2) out = [ 2, 1, 2, 1, 1, 2, 1, 2] if x & 1 else [ 1, 2, 1, 2, 2, 1, 2, 1] self.create_conn(x_cpe,y_cpe,f"CPE.OUT{out[p-1]}", x,y,f"{sb_type}.P{plane}.D0") else: # planes 9..12 self.create_conn(x,y,f"OM.P{plane}.Y", x,y,f"{sb_type}.P{plane}.D0") # Handling GPIO connections is done in create_io # Handling inputs D2_* till D7_* distances = [2, 4, 8, 12, 16, 20] if is_sb_big(x,y) else [2, 4] for i,distance in enumerate(distances): for direction in range(4): sb_x, sb_y = x, y match direction: case 0 : sb_x -= distance case 1 : sb_y -= distance case 2 : sb_x += distance case 3 : sb_y += distance if is_sb(sb_x,sb_y): src = f"{get_sb_type(sb_x,sb_y)}.P{plane}.Y{direction+1}" # Long distance signals are coming from SB_DRIVE if distance > 4: t1x, t1y = (sb_x+16-1) // 8, (sb_y+16-1) // 8 t2x, t2y = (x+16-1) // 8, (y+16-1) // 8 # depending on distance there are additional inverters # that signal is passing through each 8x8 tile dist = abs(t1x-t2x) + abs(t1y-t2y) if dist % 2 == 1: src = f"SB_DRIVE.P{plane}.D{direction+1}.OUT" else: src = f"SB_DRIVE.P{plane}.D{direction+1}.OUT_NOINV" self.create_conn(sb_x,sb_y, src, x,y,f"{get_sb_type(x,y)}.P{plane}.D{i+2}_{direction+1}") # Diagonal inputs # X12 and X34 on edges are unconnected if is_sb(x-1,y-1): self.create_conn(x-1,y-1,f"{get_sb_type(x-1,y-1)}.P{plane}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X12") if is_sb(x+1,y+1): self.create_conn(x+1,y+1,f"{get_sb_type(x+1,y+1)}.P{plane}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X34") self.create_conn(x,y,f"{get_sb_type(x,y)}.P{prev_plane(p):02d}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X14") self.create_conn(x,y,f"{get_sb_type(x,y)}.P{next_plane(p):02d}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X23") def create_outmux(self, x,y): x_0,y_0 = base_loc(x,y) for p in range(9,13): plane = f"{p:02d}" # alternating patters depending of plane and outmux position outputs = [2, 2, 1, 1] if p % 2 == x & 1 else [1, 1, 2, 2] self.create_conn(x_0, y_0, f"CPE.OUT{outputs[0]}", x,y, f"OM.P{plane}.D0") self.create_conn(x_0, y_0+1, f"CPE.OUT{outputs[1]}", x,y, f"OM.P{plane}.D1") self.create_conn(x_0+1, y_0, f"CPE.OUT{outputs[2]}", x,y, f"OM.P{plane}.D2") self.create_conn(x_0+1, y_0+1, f"CPE.OUT{outputs[3]}", x,y, f"OM.P{plane}.D3") def get_pin_real_name(self, prim_name, pin): prim_type = prim_name num = 0 if prim_name.startswith("PLL"): num = int(prim_name[3]) + 2 prim_type = "PLL" prim = Primitive(prim_name, prim_type, num) return get_pin_connection_name(prim, Pin(pin,PinType.INPUT,"",False)) def create_ram_io_conn(self, prim_name, prim_type, loc_x, loc_y): for c in get_pins_constraint(get_tile_type(loc_x,loc_y),prim_name, prim_type): name = self.get_pin_real_name(prim_name, c.name) if c.output == RAM_OUTPUT: self.create_conn(loc_x + c.rel_x, loc_y + c.rel_y, f"CPE.RAM_O{c.pin_num}", loc_x, loc_y, f"{name}") else: self.create_conn(loc_x, loc_y, f"{name}", loc_x + c.rel_x, loc_y + c.rel_y, f"CPE.RAM_I{c.pin_num}", delay="del_special_RAM_I") def create_io(self, x,y): cpe_x, cpe_y = gpio_x, gpio_y = sb_x, sb_y = x, y alt = False if is_edge_left(sb_x,sb_y): output = "Y3" cpe_x += 3 if is_sb(sb_x+1,sb_y): sb_x += 1 else: sb_x += 2 gpio_y -= 1 alt = True elif is_edge_right(sb_x,sb_y): output = "Y1" cpe_x -= 3 if is_sb(sb_x-1,sb_y): sb_x -= 1 gpio_y -= 1 alt = True else: sb_x -= 2 elif is_edge_bottom(sb_x,sb_y): output = "Y4" cpe_y += 3 if is_sb(sb_x,sb_y+1): sb_y += 1 else: sb_y += 2 gpio_x -= 1 alt = True else: output = "Y2" cpe_y -= 3 if is_sb(sb_x,sb_y-1): sb_y -= 1 gpio_x -= 1 alt = True else: sb_y -= 2 for p in range(1,13): plane = f"{p:02d}" self.create_conn(sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.{output}", x,y, f"IOES.ALTIN_{plane}") self.create_conn(x,y, f"IOES.SB_IN_{plane}", sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.D0_IO") self.create_conn(gpio_x,gpio_y,"IOSEL.IN1", x,y, "IOES.IO_IN1") self.create_conn(gpio_x,gpio_y,"IOSEL.IN2", x,y, "IOES.IO_IN2") if not alt: self.create_ram_io_conn("IOSEL", "IOSEL", x, y) self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "IOSEL.CLOCK1", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "IOSEL.CLOCK2", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "IOSEL.CLOCK3", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "IOSEL.CLOCK4", "del_GLBOUT_IO_SEL") def create_pll(self): # GPIO_W2_A[8] CLK0 # GPIO_W2_A[7] CLK1 # GPIO_W2_A[6] CLK2 # GPIO_W2_A[5] CLK3 # SER_CLK SER_CLK # GPIO_S3_B[8] SPI_CLK # GPIO_S3_A[5] JTAG_CLK loc = self.gpio_to_loc["GPIO_W2_A[8]"] self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0") loc = self.gpio_to_loc["GPIO_W2_A[7]"] self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK1") loc = self.gpio_to_loc["GPIO_W2_A[6]"] self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK2") loc = self.gpio_to_loc["GPIO_W2_A[5]"] self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3") self.create_ram_io_conn("GLBOUT", "GLBOUT", PLL_X_POS, PLL_Y_POS) self.create_ram_io_conn("PLL0", "PLL", PLL_X_POS, PLL_Y_POS) self.create_ram_io_conn("PLL1", "PLL", PLL_X_POS, PLL_Y_POS) self.create_ram_io_conn("PLL2", "PLL", PLL_X_POS, PLL_Y_POS) self.create_ram_io_conn("PLL3", "PLL", PLL_X_POS, PLL_Y_POS) def global_mesh(self): def global_mesh_conn(x,y,inp): for p in range(1,13): plane = f"{p:02d}" if is_sb_big(x,y): # Clock#1: p1, p5,p9 # Clock#2: p2, p6,p10 # Clock#3: p3, p7,p11 # Clock#4: p4, p8,p12 self.create_conn(PLL_X_POS, PLL_Y_POS, f"GLBOUT.GLB{(p-1) & 3}", x,y,f"SB_BIG.P{plane}.{inp}_CLK", "del_GLBOUT_sb_big") # Connecting Global Mesh signals to Switch Boxes # Left edge for y in range(0,130+1): x = 2 - (y % 4) global_mesh_conn(x,y,"D7_1") global_mesh_conn(-1,-1,"D7_1") # Bottom edge for x in range(0,162+1): y = 2 - (x % 4) global_mesh_conn(x,y,"D7_2") global_mesh_conn(-1,-1,"D7_2") # Right edge for y in range(0,130+1): x = 2 - (y % 4) + 160 global_mesh_conn(x,y,"D7_3") global_mesh_conn(159,-1,"D7_3") # Top edge for x in range(0,162+1): y = 2 - (x % 4) + 128 global_mesh_conn(x,y,"D7_4") global_mesh_conn(-1,127,"D7_4") # Connecting Global Mesh signals to CPEs #for m in range (0,3+1): # for n in range (0,7+1): # x0 = 33 + m * 32 # y0 = 1 + n * 16 # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x0 - 3, y0 + 10 , "CPE.RAM_I1") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x0 - 3, y0 + 11 , "CPE.RAM_I1") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x0 - 3, y0 + 12 , "CPE.RAM_I1") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x0 - 3, y0 + 13 , "CPE.RAM_I1") # # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x0 + 2, y0 + 10 , "CPE.RAM_I2") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x0 + 2, y0 + 11 , "CPE.RAM_I2") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x0 + 2, y0 + 12 , "CPE.RAM_I2") # self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x0 + 2, y0 + 13 , "CPE.RAM_I2") def edge_select(self): # Left edge for y in range(1,128+1): self.create_conn(-2, y, "LES.CPE_CINX", 1, y ,"CPE.CINX") self.create_conn(-2, y, "LES.CPE_PINX", 1, y ,"CPE.PINX") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", -2, y, "LES.CLOCK0") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", -2, y, "LES.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", -2, y, "LES.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", -2, y, "LES.CLOCK3") for p in range(1,9): plane = f"{p:02d}" sb_x = -1 if y % 2==1 else 0 self.create_conn(sb_x, y, f"{get_sb_type(sb_x,y)}.P{plane}.Y3", -2, y, f"LES.SB_Y3.P{p}") # Bottom edge for x in range(1,160+1): self.create_conn(x, -2, "BES.CPE_CINY1", x, 1 ,"CPE.CINY1") self.create_conn(x, -2, "BES.CPE_PINY1", x, 1 ,"CPE.PINY1") self.create_conn(x, -2, "BES.CPE_CINY2", x, 1 ,"CPE.CINY2") self.create_conn(x, -2, "BES.CPE_PINY2", x, 1 ,"CPE.PINY2") if x>1: self.create_conn(x-1, -2, "BES.CPE_CINY1", x, -2 ,"BES.P_CINY1") self.create_conn(x-1, -2, "BES.CPE_PINY1", x, -2 ,"BES.P_PINY1") self.create_conn(x-1, -2, "BES.CPE_CINY2", x, -2 ,"BES.P_CINY2") self.create_conn(x-1, -2, "BES.CPE_PINY2", x, -2 ,"BES.P_PINY2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, -2, "BES.CLOCK0") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, -2, "BES.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, -2, "BES.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, -2, "BES.CLOCK3") for p in range(1,9): plane = f"{p:02d}" sb_y = -1 if x % 2==1 else 0 self.create_conn(x, sb_y, f"{get_sb_type(x,sb_y)}.P{plane}.Y4", x, -2, f"BES.SB_Y4.P{p}") # Right edge for y in range(1,128+1): self.create_conn(160, y, "CPE.RAM_O1", 163, y ,"RES.CPE_RAM_O1") self.create_conn(160, y, "CPE.RAM_O2", 163, y ,"RES.CPE_RAM_O2") self.create_conn(160, y, "CPE.COUTX", 163, y ,"RES.CPE_COUTX") self.create_conn(160, y, "CPE.POUTX", 163, y ,"RES.CPE_POUTX") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", 163, y, "RES.CLOCK0") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", 163, y, "RES.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", 163, y, "RES.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", 163, y, "RES.CLOCK3") for p in range(1,9): plane = f"{p:02d}" sb_x = 161 if y % 2==1 else 162 self.create_conn(sb_x, y, f"{get_sb_type(sb_x,y)}.P{plane}.Y1", 163, y, f"RES.SB_Y1.P{p}") # Top edge for x in range(28,160+1): self.create_conn(x, 128 ,"CPE.RAM_O1", x, 131, "TES.CPE_RAM_O1") self.create_conn(x, 128 ,"CPE.RAM_O2", x, 131, "TES.CPE_RAM_O2") self.create_conn(x, 128 ,"CPE.COUTY1", x, 131, "TES.CPE_COUTY1") self.create_conn(x, 128 ,"CPE.POUTY1", x, 131, "TES.CPE_POUTY1") self.create_conn(x, 128 ,"CPE.COUTY2", x, 131, "TES.CPE_COUTY2") self.create_conn(x, 128 ,"CPE.POUTY2", x, 131, "TES.CPE_POUTY2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, 131, "TES.CLOCK0") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, 131, "TES.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, 131, "TES.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, 131, "TES.CLOCK3") for p in range(1,9): plane = f"{p:02d}" sb_y = 129 if x % 2==1 else 130 self.create_conn(x, sb_y, f"{get_sb_type(x,sb_y)}.P{plane}.Y2", x, 131, f"TES.SB_Y2.P{p}") def connect_ddr_i(self, x, y, out, bank): for port in ['A','B']: for num in range(0,9): loc = self.io_pad_names[bank][port][num] self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "IOSEL.DDR") self.ddr_i[bank] = Location(x+self.offset_x,y+self.offset_y,2-out) def misc_connections(self): self.create_ram_io_conn("CFG_CTRL", "CFG_CTRL", CTRL_X_POS, CTRL_Y_POS) self.create_ram_io_conn("USR_RSTN", "USR_RSTN", CTRL_X_POS, CTRL_Y_POS) self.connect_ddr_i(97,128,1,'N1') self.connect_ddr_i(97,128,2,'N2') self.connect_ddr_i(160,65,1,'E1') self.connect_ddr_i(160,65,2,'E2') self.connect_ddr_i(1,65,1,'W1') self.connect_ddr_i(1,65,2,'W2') self.connect_ddr_i(97,1,1,'S1') self.connect_ddr_i(97,1,2,'S2') self.connect_ddr_i(49,1,1,'S3') def create_serdes(self, x, y): self.create_ram_io_conn("SERDES", "SERDES", x, y) def create_ram(self, x, y): self.create_ram_io_conn("RAM", "RAM", x, y) # No actuall need for connections to RAMI/O # for halfs, they create conflicts and we # later anyway merge to full RAM self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, y, "RAM.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, y, "RAM.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, y, "RAM.CLOCK3") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, y, "RAM.CLOCK4") def create_in_die_connections(self, conn): self.conn = conn for y in range(-2, max_row()+1): for x in range(-2, max_col()+1): if is_cpe(x,y): self.create_cpe(x,y) self.create_inmux(x,y) if is_outmux(x,y): self.create_outmux(x,y) if is_sb(x,y): self.create_sb(x,y) if is_edge_io(x,y): self.create_io(x,y) if is_ram_u(x,y): self.create_ram(x,y) if is_serdes(x,y): self.create_serdes(x,y) self.create_pll() self.global_mesh() self.edge_select() self.misc_connections() prjpeppercorn-1.12/gatemate/timing.py000066400000000000000000000500021514752025000177540ustar00rootroot00000000000000# # prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools # # Copyright (C) 2024 The Project Peppercorn Authors. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import zlib import struct from dataclasses import dataclass from typing import List @dataclass class T_delay_tri: min: int typ: int max: int @staticmethod def from_bytes(data: bytes) -> 'T_delay_tri': min_val, typ_val, max_val = struct.unpack('<3i', data) return T_delay_tri(min_val, typ_val, max_val) @dataclass class T_delay: rise: T_delay_tri fall: T_delay_tri @staticmethod def from_bytes(data: bytes) -> 'T_delay': rise = T_delay_tri.from_bytes(data[:12]) fall = T_delay_tri.from_bytes(data[12:24]) return T_delay(rise, fall) @dataclass class Tpin_pair: i: int o_or_clk: int # Represents either 'o' or 'clk' depending on the boolean case @dataclass class Tentry_rec: pins: Tpin_pair entry_no: int @dataclass class Tdel_entry: key: int edge1: int edge2: int time1: T_delay_tri time2: T_delay_tri @dataclass class TRAM_del_rec: iopath: List[Tentry_rec] setuphold: List[Tentry_rec] width: List[Tentry_rec] del_entry: List[Tdel_entry] @dataclass class Tdel_rec: val: T_delay conf_mux: int name: str x: int y: int plane: int dir: int inv: int cnt: int con_type: int @staticmethod def from_bytes(data: memoryview, offset: int) -> ('Tdel_rec', int): val = T_delay.from_bytes(data[offset:offset + 24]) offset += 24 conf_mux = struct.unpack_from(' ('Tdel_rec_tri', int): val = T_delay_tri.from_bytes(mv[offset:offset+12]) offset += 12 conf_mux = struct.unpack_from(' (List, int): SB_del_tile_arr = [] for i1 in range(4): # [1..4] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(4): # [1..4] level3 = [] for i4 in range(12): # [1..12] level4 = [] for i5 in range(5): # [0..4] level5 = [] for i6 in range(8): # [0..7] chunk = mv[offset:offset + 24] if len(chunk) < 24: raise EOFError("Unexpected end of data") delay = T_delay.from_bytes(chunk) offset += 24 level5.append(delay) level4.append(level5) level3.append(level4) level2.append(level3) level1.append(level2) SB_del_tile_arr.append(level1) return SB_del_tile_arr, offset @dataclass class ExtraTimingDelays: skew_report_del: int fix_skew_del: int del_rec_0: Tdel_rec del_min_route_SB: Tdel_rec del_violation_common: Tdel_rec_tri del_dummy: Tdel_rec del_Hold_D_L: Tdel_rec_tri del_Hold_RAM: Tdel_rec_tri del_Setup_D_L: Tdel_rec_tri del_Setup_RAM: Tdel_rec_tri del_Hold_SN_RN: Tdel_rec_tri del_Setup_SN_RN: Tdel_rec_tri del_Hold_RN_SN: Tdel_rec_tri del_Setup_RN_SN: Tdel_rec_tri del_bot_couty2: Tdel_rec del_bot_glb_couty2: Tdel_rec del_bot_SB_couty2: Tdel_rec del_bot_pouty2: Tdel_rec del_bot_glb_pouty2: Tdel_rec del_bot_SB_pouty2: Tdel_rec del_left_couty2: Tdel_rec del_left_glb_couty2: Tdel_rec del_left_SB_couty2: Tdel_rec del_left_pouty2: Tdel_rec del_left_glb_pouty2: Tdel_rec del_left_SB_pouty2: Tdel_rec del_inp: List[Tdel_rec] del_CPE_out_mux: List[Tdel_rec] del_CPE_CP_Q: Tdel_rec del_CPE_S_Q: Tdel_rec del_CPE_R_Q: Tdel_rec del_CPE_D_Q: Tdel_rec del_RAM_CLK_DO: Tdel_rec del_GLBOUT_sb_big: Tdel_rec del_sb_drv: Tdel_rec del_CP_carry_path: Tdel_rec del_CP_prop_path: Tdel_rec del_special_RAM_I: Tdel_rec del_RAMO_xOBF: Tdel_rec del_GLBOUT_IO_SEL: Tdel_rec del_IO_SEL_Q_out: Tdel_rec del_IO_SEL_Q_in: Tdel_rec in_delayline_per_stage: Tdel_rec out_delayline_per_stage: Tdel_rec del_IBF: Tdel_rec del_OBF: Tdel_rec del_r_OBF: Tdel_rec del_TOBF_ctrl: Tdel_rec del_LVDS_IBF: Tdel_rec del_LVDS_OBF: Tdel_rec del_LVDS_r_OBF: Tdel_rec del_LVDS_TOBF_ctrl: Tdel_rec del_CP_clkin: Tdel_rec del_CP_enin: Tdel_rec del_preplace: Tdel_rec del_CPE_timing_mod: List[Tdel_rec] @staticmethod def from_bytes(mv: memoryview, offset: int) -> ('ExtraTimingDelays', int): skew_report_del, fix_skew_del = struct.unpack_from('<2i', mv, offset) offset += 8 del_rec_0, offset = Tdel_rec.from_bytes(mv, offset) del_min_route_SB, offset = Tdel_rec.from_bytes(mv, offset) del_violation_common, offset = Tdel_rec_tri.from_bytes(mv, offset) del_dummy, offset = Tdel_rec.from_bytes(mv, offset) del_Hold_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Hold_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_Setup_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset) del_bot_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_bot_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_left_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset) del_inp = [] for _ in range(8): rec, offset = Tdel_rec.from_bytes(mv, offset) del_inp.append(rec) del_CPE_out_mux = [] for _ in range(4): rec, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_out_mux.append(rec) del_CPE_CP_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_S_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_R_Q, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_D_Q, offset = Tdel_rec.from_bytes(mv, offset) del_RAM_CLK_DO, offset = Tdel_rec.from_bytes(mv, offset) del_GLBOUT_sb_big, offset = Tdel_rec.from_bytes(mv, offset) del_sb_drv, offset = Tdel_rec.from_bytes(mv, offset) del_CP_carry_path, offset = Tdel_rec.from_bytes(mv, offset) del_CP_prop_path, offset = Tdel_rec.from_bytes(mv, offset) del_special_RAM_I, offset = Tdel_rec.from_bytes(mv, offset) del_RAMO_xOBF, offset = Tdel_rec.from_bytes(mv, offset) del_GLBOUT_IO_SEL, offset = Tdel_rec.from_bytes(mv, offset) del_IO_SEL_Q_out, offset = Tdel_rec.from_bytes(mv, offset) del_IO_SEL_Q_in, offset = Tdel_rec.from_bytes(mv, offset) in_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset) out_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset) del_IBF, offset = Tdel_rec.from_bytes(mv, offset) del_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_r_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_IBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_r_OBF, offset = Tdel_rec.from_bytes(mv, offset) del_LVDS_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset) del_CP_clkin, offset = Tdel_rec.from_bytes(mv, offset) del_CP_enin, offset = Tdel_rec.from_bytes(mv, offset) del_preplace, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_timing_mod = [] for _ in range(42): rec, offset = Tdel_rec.from_bytes(mv, offset) del_CPE_timing_mod.append(rec) return ExtraTimingDelays( skew_report_del, fix_skew_del, del_rec_0, del_min_route_SB, del_violation_common, del_dummy, del_Hold_D_L, del_Hold_RAM, del_Setup_D_L, del_Setup_RAM, del_Hold_SN_RN, del_Setup_SN_RN, del_Hold_RN_SN, del_Setup_RN_SN, del_bot_couty2, del_bot_glb_couty2, del_bot_SB_couty2, del_bot_pouty2, del_bot_glb_pouty2, del_bot_SB_pouty2, del_left_couty2, del_left_glb_couty2, del_left_SB_couty2, del_left_pouty2, del_left_glb_pouty2, del_left_SB_pouty2, del_inp, del_CPE_out_mux, del_CPE_CP_Q, del_CPE_S_Q, del_CPE_R_Q, del_CPE_D_Q, del_RAM_CLK_DO, del_GLBOUT_sb_big, del_sb_drv, del_CP_carry_path, del_CP_prop_path, del_special_RAM_I, del_RAMO_xOBF, del_GLBOUT_IO_SEL, del_IO_SEL_Q_out, del_IO_SEL_Q_in, in_delayline_per_stage, out_delayline_per_stage, del_IBF, del_OBF, del_r_OBF, del_TOBF_ctrl, del_LVDS_IBF, del_LVDS_OBF, del_LVDS_r_OBF, del_LVDS_TOBF_ctrl, del_CP_clkin, del_CP_enin, del_preplace, del_CPE_timing_mod ), offset def read_IM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(2): # [1..2] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(8): # [1..8] level3 = [] for i4 in range(12): # [1..12] level4 = [] for i5 in range(8): # [0..7] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level4.append(delay) level3.append(level4) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_OM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(8): # [1..8] level1 = [] for i2 in range(8): # [1..8] level2 = [] for i3 in range(4): # [9..12] level3 = [] for i4 in range(4): # [0..3] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level3.append(delay) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_CPE_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(10): # [0..9] level1 = [] for i2 in range(19): # [1..19] level2 = [] for i3 in range(10): # [1..10] rec, offset = Tdel_rec.from_bytes(mv, offset) level2.append(rec) level1.append(level2) result.append(level1) return result, offset def read_SB_del_rim_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(165): # [-2..162] level1 = [] for i2 in range(4): # [1..4] level2 = [] for i3 in range(12): # [1..12] level3 = [] for i4 in range(5): # [0..4] level4 = [] for i5 in range(8): # [0..7] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level4.append(delay) level3.append(level4) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_Edge_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(165): # [-2..162] level1 = [] for i2 in range(4): # [1..4] level2 = [] for i3 in range(24): # [1..24] level3 = [] for i4 in range(8): # [1..8] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level3.append(delay) level2.append(level3) level1.append(level2) result.append(level1) return result, offset def read_IO_SEL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(11): # [1..11] level1 = [] for i2 in range(4): # [1..4] delay = T_delay.from_bytes(mv[offset:offset+24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_CLKIN_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(7): level1 = [] for i2 in range(4): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_GLBOUT_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(28): level1 = [] for i2 in range(8): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_PLL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int): result = [] for i1 in range(7): level1 = [] for i2 in range(6): delay = T_delay.from_bytes(mv[offset:offset + 24]) offset += 24 level1.append(delay) result.append(level1) return result, offset def read_Tentry_rec_from_bytes(data: memoryview, offset: int) -> ('Tentry_rec', int): pins_i, pins_val, entry_no = struct.unpack_from('<3h', data, offset) return Tentry_rec(Tpin_pair(pins_i, pins_val), entry_no), offset + 6 def read_Tdel_entry_from_bytes(data: memoryview, offset: int) -> ('Tdel_entry', int): key, edge1, edge2 = struct.unpack_from('<3i', data, offset) time1 = T_delay_tri.from_bytes(data[offset + 12:offset + 24]) time2 = T_delay_tri.from_bytes(data[offset + 24:offset + 36]) return Tdel_entry(key, edge1, edge2, time1, time2), offset + 36 def read_TRAM_del_rec_from_bytes(mv: memoryview, offset: int) -> (TRAM_del_rec, int): iopath = [] for _ in range(3001): entry, offset = read_Tentry_rec_from_bytes(mv, offset) iopath.append(entry) setuphold = [] for _ in range(8001): entry, offset = read_Tentry_rec_from_bytes(mv, offset) setuphold.append(entry) width = [] for _ in range(51): entry, offset = read_Tentry_rec_from_bytes(mv, offset) width.append(entry) del_entry = [] offset += 2 # alignment added for _ in range(101): entry, offset = read_Tdel_entry_from_bytes(mv, offset) del_entry.append(entry) return TRAM_del_rec(iopath, setuphold, width, del_entry), offset def read_IO_SEL_io_coef_from_bytes(mv: memoryview, offset: int) -> (list, int): result = [] for i1 in range(4): # [1..4] row = [] for i2 in range(27): # [1..27] value = struct.unpack_from(' 'Tdel_all_rec': offset = 0 sb_del_tile_arr, offset = read_SB_del_tile_arr_from_bytes(data, offset) im, offset = read_IM_del_tile_arr_from_bytes(data, offset) om, offset = read_OM_del_tile_arr_from_bytes(data, offset) cpe, offset = read_CPE_del_tile_arr_from_bytes(data, offset) sb_del_rim, offset = read_SB_del_rim_arr_from_bytes(data, offset) edge, offset = read_Edge_del_arr_from_bytes(data, offset) io_sel, offset = read_IO_SEL_del_arr_from_bytes(data, offset) clkin, offset = read_CLKIN_del_arr_from_bytes(data, offset) glbout, offset = read_GLBOUT_del_arr_from_bytes(data, offset) pll_del, offset = read_PLL_del_arr_from_bytes(data, offset) fpga_ram_del_1, offset = read_TRAM_del_rec_from_bytes(data, offset) fpga_ram_del_2, offset = read_TRAM_del_rec_from_bytes(data, offset) fpga_ram_del_3, offset = read_TRAM_del_rec_from_bytes(data, offset) io_sel_coef, offset = read_IO_SEL_io_coef_from_bytes(data, offset) timing_delays, offset = ExtraTimingDelays.from_bytes(data, offset) return Tdel_all_rec(sb_del_tile_arr, im, om, cpe, sb_del_rim, edge, io_sel, clkin, glbout, pll_del, fpga_ram_del_1, fpga_ram_del_2, fpga_ram_del_3,io_sel_coef, timing_delays) def decompress_timing(input_path) -> 'Tdel_all_rec': with open(input_path, 'rb') as f_in: compressed_data = f_in.read() try: decompressed_data = zlib.decompress(compressed_data) except zlib.error as e: print(f"Decompression failed: {e}") return return Tdel_all_rec.from_bytes(decompressed_data) # Example usage #decompress_timing("cc_best_eco_dly.dly") #decompress_timing("cc_best_lpr_dly.dly") #decompress_timing("cc_best_spd_dly.dly") # #decompress_timing("cc_typ_eco_dly.dly") #decompress_timing("cc_typ_lpr_dly.dly") #decompress_timing("cc_typ_spd_dly.dly") # #decompress_timing("cc_worst_eco_dly.dly") #decompress_timing("cc_worst_lpr_dly.dly") #decompress_timing("cc_worst_spd_dly.dly") prjpeppercorn-1.12/libgm/000077500000000000000000000000001514752025000154215ustar00rootroot00000000000000prjpeppercorn-1.12/libgm/.clang-format000066400000000000000000000047541514752025000200060ustar00rootroot00000000000000--- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -2 AlignAfterOpenBracket: Align AlignConsecutiveAssignments: false AlignConsecutiveDeclarations: false AlignEscapedNewlinesLeft: false AlignOperands: true AlignTrailingComments: true AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: false AllowShortCaseLabelsOnASingleLine: false AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: false AllowShortLoopsOnASingleLine: false AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: false BinPackArguments: true BinPackParameters: true BraceWrapping: AfterClass: true AfterControlStatement: false AfterEnum: true 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)prjpeppercorn-1.12/libgm/include/000077500000000000000000000000001514752025000170445ustar00rootroot00000000000000prjpeppercorn-1.12/libgm/include/Bitstream.hpp000066400000000000000000000036701514752025000215150ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_BITSTREAM_HPP #define LIBGATEMATE_BITSTREAM_HPP #include #include #include #include #include #include #include namespace GateMate { class Chip; class Bitstream { public: static Bitstream read(std::istream &in); // Serialise a Chip back to a bitstream static Bitstream serialise_chip(const Chip &chip, const std::map options); // Deserialise a bitstream to a Chip Chip deserialise_chip(); void write_bit(std::ostream &out); int determine_size(int *max_die_x, int *max_die_y); private: Bitstream(const std::vector &data); // Bitstream raw data std::vector data; }; class BitstreamParseError : std::runtime_error { public: explicit BitstreamParseError(const std::string &desc); BitstreamParseError(const std::string &desc, size_t offset); const char *what() const noexcept override; private: std::string desc; int offset; }; } // namespace GateMate #endif // LIBGATEMATE_BITSTREAM_HPP prjpeppercorn-1.12/libgm/include/Chip.hpp000066400000000000000000000025711514752025000204450ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_CHIP_HPP #define LIBGATEMATE_CHIP_HPP #include #include #include "Die.hpp" namespace GateMate { class Chip { public: explicit Chip(std::string name); explicit Chip(int num); int get_max_die() const; std::string get_name() const; const Die &get_die(int num) const { return dies.at(num); } Die &get_die(int num) { return dies.at(num); } private: int die_num; std::vector dies; }; } // namespace GateMate #endif // LIBGATEMATE_CHIP_HPP prjpeppercorn-1.12/libgm/include/ChipConfig.hpp000066400000000000000000000041431514752025000215700ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_CHIPCONFIG_HPP #define LIBGATEMATE_CHIPCONFIG_HPP #include #include #include #include #include "TileConfig.hpp" namespace GateMate { class Chip; struct CfgLoc { int die; int x; int y; inline bool operator==(const CfgLoc &other) const { return other.die == die && other.x == x && other.y == y; } inline bool operator!=(const CfgLoc &other) const { return other.die != die || x != other.x || y == other.y; } inline bool operator<(const CfgLoc &other) const { return die < other.die || ((die == other.die && y < other.y) || (die == other.die && y == other.y && x < other.x)); } }; class ChipConfig { public: std::string chip_name; std::string chip_package; std::map tiles; std::map brams; std::map serdes; std::map configs; // Block RAM initialisation std::map> bram_data; std::string to_string() const; static ChipConfig from_string(const std::string &config); Chip to_chip() const; static ChipConfig from_chip(const Chip &chip); }; } // namespace GateMate #endif // LIBGATEMATE_CHIPCONFIG_HPP prjpeppercorn-1.12/libgm/include/Die.hpp000066400000000000000000000103411514752025000202550ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_DIE_HPP #define LIBGATEMATE_DIE_HPP #include #include #include #include namespace GateMate { class Die { public: static constexpr int MAX_ROWS = 66; static constexpr int MAX_COLS = 82; static constexpr int MAX_RAM = 32; static constexpr int MAX_RAM_ROWS = 8; static constexpr int MAX_RAM_COLS = 4; static constexpr int LATCH_BLOCK_SIZE = 112 + 1; // Added one more byte for FF_INIT static constexpr int RAM_BLOCK_SIZE = 27; static constexpr int MEMORY_SIZE = 5120; static constexpr int MAX_PLL = 4; static constexpr int PLL_CFG_SIZE = 12; static constexpr int CLKIN_CFG_SIZE = 4; static constexpr int GLBOUT_CFG_SIZE = 8; static constexpr int STATUS_CFG_SIZE = 12; static constexpr int STATUS_CFG_START = PLL_CFG_SIZE * MAX_PLL * 2 + CLKIN_CFG_SIZE + GLBOUT_CFG_SIZE; static constexpr int DIE_CONFIG_SIZE = STATUS_CFG_START + STATUS_CFG_SIZE + 1; static constexpr int FF_INIT_RESET = 2; static constexpr int FF_INIT_SET = 3; static constexpr int SERDES_CFG_SIZE = 186; public: explicit Die(); // Get max row and column int get_max_row() const { return MAX_ROWS; } int get_max_col() const { return MAX_COLS; } int get_max_ram_row() const { return MAX_RAM_ROWS; } int get_max_ram_col() const { return MAX_RAM_COLS; } bool is_latch_empty(int x, int y) const; bool is_cpe_empty(int x, int y) const; bool is_ram_empty(int x, int y) const; bool is_ram_data_empty(int x, int y) const; bool is_pll_cfg_empty(int index) const; bool is_clkin_cfg_empty() const; bool is_glbout_cfg_empty() const; bool is_status_cfg_empty() const; bool is_using_cfg_gpios() const; bool is_serdes_cfg_empty() const; uint8_t get_d2d_config() const; void write_latch(int x, int y, const std::vector &data); void write_ram(int x, int y, const std::vector &data); void write_ram_data(int x, int y, const std::vector &data, uint16_t addr); void write_pll_select(uint8_t select, const std::vector &data); void write_d2d_config(uint8_t data); void write_die_cfg(const std::vector &data) { die_cfg = data; } void write_serdes_cfg(const std::vector &data) { serdes_cfg = data; } void write_ff_init(int x, int y, uint8_t data); void write_status(const std::vector &data); const std::vector get_latch_config(int x, int y) const { return latch.at(std::make_pair(x, y)); } const std::vector get_ram_config(int x, int y) const { return ram.at(std::make_pair(x, y)); } const std::vector get_ram_data(int x, int y) const { return ram_data.at(std::make_pair(x, y)); } const std::vector get_serdes_config() const { return serdes_cfg; } const std::vector get_die_config() const { return die_cfg; } private: std::map, std::vector> latch; // Config latches std::map, std::vector> ram; // Config RAM std::map, std::vector> ram_data; // RAM data content FRAM std::vector serdes_cfg; // Config for SERDES std::vector die_cfg; // Config for all PLLs, CLKIN and GLBOUT }; } // namespace GateMate #endif // LIBGATEMATE_DIE_HPP prjpeppercorn-1.12/libgm/include/TileBitDatabase.hpp000066400000000000000000000061411514752025000225400ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_TILEBITDATABASE_HPP #define LIBGATEMATE_TILEBITDATABASE_HPP #include #include #include #include #include "TileConfig.hpp" namespace GateMate { struct WordSettingBits { int start; int end; std::vector get_value(const std::vector &tile) const; void set_value(std::vector &tile, const std::vector &value) const; inline bool operator==(const WordSettingBits &other) const { return (start == other.start) && (end == other.end); } }; class BaseBitDatabase { public: BaseBitDatabase(int num_bits); virtual ~BaseBitDatabase(); TileConfig data_to_config(const std::vector &data); std::vector config_to_data(const TileConfig &cfg); protected: void add_word_settings(const std::string &name, int start, int len); void add_unknowns(); std::vector bits_to_bytes(std::vector &bits); int num_bits; std::map words; std::vector known_bits; }; class TileBitDatabase : public BaseBitDatabase { public: TileBitDatabase(const int x, const int y); private: void add_sb_big(int index, int start); void add_sb_sml(int index, int start); void add_sb_drive(int index, int start); void add_cpe(int index, int start); void add_ff_init(int index, int start); void add_inmux(int index, int plane, int start); void add_outmux(int index, int plane, int start); void add_gpio(int start); void add_edge_io(int index, int start); void add_right_edge(int index, int start); void add_left_edge(int index, int start); void add_top_edge(int index, int start); void add_bottom_edge(int index, int start); }; class RamBitDatabase : public BaseBitDatabase { public: RamBitDatabase(); }; class SerdesBitDatabase : public BaseBitDatabase { public: SerdesBitDatabase(); }; class ConfigBitDatabase : public BaseBitDatabase { public: ConfigBitDatabase(); private: void add_pll_cfg(int index, char cfg, int start); }; class DatabaseConflictError : public std::runtime_error { public: explicit DatabaseConflictError(const std::string &desc); }; } // namespace GateMate #endif // LIBGATEMATE_TILEBITDATABASE_HPP prjpeppercorn-1.12/libgm/include/TileConfig.hpp000066400000000000000000000035051514752025000216030ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_TILECONFIG_HPP #define LIBGATEMATE_TILECONFIG_HPP #include #include #include #include #include namespace GateMate { struct ConfigWord { std::string name; std::vector value; inline bool operator==(const ConfigWord &other) const { return other.name == name && other.value == value; } }; std::ostream &operator<<(std::ostream &out, const ConfigWord &cw); std::istream &operator>>(std::istream &in, ConfigWord &cw); struct TileConfig { std::vector cwords; int total_known_bits = 0; void add_word(const std::string &name, const std::vector &value); std::string to_string() const; static TileConfig from_string(const std::string &str); bool empty() const; }; std::ostream &operator<<(std::ostream &out, const TileConfig &tc); std::istream &operator>>(std::istream &in, TileConfig &ce); } // namespace GateMate #endif // LIBGATEMATE_TILECONFIG_HPP prjpeppercorn-1.12/libgm/include/Util.hpp000066400000000000000000000070711514752025000204770ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef LIBGATEMATE_UTIL_HPP #define LIBGATEMATE_UTIL_HPP #include #include #include #include #include #include #include namespace GateMate { enum class VerbosityLevel { ERROR, NOTE, DEBUG, }; extern VerbosityLevel verbosity; inline std::string uint32_to_hexstr(uint32_t val) { std::ostringstream os; os << "0x" << std::hex << std::setw(8) << std::setfill('0') << val; return os.str(); } // Hex is not allowed in JSON, to avoid an ugly decimal integer use a string // instead But we need to parse this back to a uint32_t inline uint32_t parse_uint32(std::string str) { return uint32_t(strtoul(str.c_str(), nullptr, 0)); } inline std::string to_string(const std::vector &bv) { std::ostringstream os; for (auto it = bv.rbegin(); it != bv.rend(); ++it) os << (*it ? '1' : '0'); return os.str(); } inline std::istream &operator>>(std::istream &in, std::vector &bv) { bv.clear(); std::string s; in >> s; for (auto it = s.rbegin(); it != s.rend(); ++it) { char c = *it; assert((c == '0') || (c == '1')); bv.push_back((c == '1')); } return in; } // Skip whitespace, optionally including newlines inline void skip_blank(std::istream &in, bool nl = false) { int c = in.peek(); while (in && (((c == ' ') || (c == '\t')) || (nl && ((c == '\n') || (c == '\r'))))) { in.get(); c = in.peek(); } } // Return true if end of line (or file) inline bool skip_check_eol(std::istream &in) { skip_blank(in, false); if (!in) return false; int c = in.peek(); // Comments count as end of line if (c == '#') { in.get(); c = in.peek(); while (in && c != EOF && c != '\n') { in.get(); c = in.peek(); } return true; } return (c == EOF || c == '\n'); } // Skip past blank lines and comments inline void skip(std::istream &in) { skip_blank(in, true); while (in && (in.peek() == '#')) { // Skip comment line skip_check_eol(in); skip_blank(in, true); } } // Return true if at the end of a record (or file) inline bool skip_check_eor(std::istream &in) { skip(in); int c = in.peek(); return (c == EOF || c == '.'); } // Return true if at the end of file inline bool skip_check_eof(std::istream &in) { skip(in); int c = in.peek(); return (c == EOF); } std::string stringf(const char *fmt, ...); std::string vstringf(const char *fmt, va_list ap); } // namespace GateMate #define fmt(x) (static_cast(std::ostringstream() << x).str()) #define UNUSED(x) (void)(x) #endif // LIBGATEMATE_UTIL_HPP prjpeppercorn-1.12/libgm/src/000077500000000000000000000000001514752025000162105ustar00rootroot00000000000000prjpeppercorn-1.12/libgm/src/Bitstream.cpp000066400000000000000000001176131514752025000206570ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "Bitstream.hpp" #include #include #include #include "Chip.hpp" #include "Util.hpp" namespace GateMate { static constexpr const uint8_t CMD_PLL = 0xc1; static constexpr const uint8_t CMD_CFGMODE = 0xc2; static constexpr const uint8_t CMD_CFGRST = 0xc3; static constexpr const uint8_t CMD_FLASH = 0xc5; static constexpr const uint8_t CMD_DLXP = 0xc6; // static constexpr const uint8_t CMD_DLYP = 0xc7; // static constexpr const uint8_t CMD_LXLYS = 0xc8; static constexpr const uint8_t CMD_ACLCU = 0xc9; static constexpr const uint8_t CMD_DLCU = 0xca; static constexpr const uint8_t CMD_DRXP = 0xcc; // static constexpr const uint8_t CMD_RXRYS = 0xce; static constexpr const uint8_t CMD_FRAM = 0xd2; static constexpr const uint8_t CMD_SERDES = 0xd7; // static constexpr const uint8_t CMD_D2D = 0xd8; // static constexpr const uint8_t CMD_PATH = 0xd9; static constexpr const uint8_t CMD_JUMP = 0xda; static constexpr const uint8_t CMD_CHG_STATUS = 0xdb; static constexpr const uint8_t CMD_WAIT_PLL = 0xdc; // static constexpr const uint8_t CMD_SPLL = 0xdd; static constexpr const uint8_t CMD_SLAVE_MODE = 0xde; static constexpr const uint8_t CFG_NONE = 0x00; static constexpr const uint8_t CFG_DONE = 0x01; static constexpr const uint8_t CFG_STOP = 0x02; static constexpr const uint8_t CFG_RECONFIG = 0x04; static constexpr const uint8_t CFG_CPE_CFG = 0x08; static constexpr const uint8_t CFG_CPE_RESET = 0x10; static constexpr const uint8_t CFG_FILL_RAM = 0x20; static constexpr const uint8_t CFG_SERDES = 0x40; // PLL register A static constexpr const uint8_t CFG_PLL_RST_N = 0x01; static constexpr const uint8_t CFG_PLL_EN = 0x02; static constexpr const uint8_t CFG_PLL_AUTN = 0x04; // only available for PLL0 static constexpr const uint8_t CFG_SET_SEL = 0x08; static constexpr const uint8_t CFG_USR_SET = 0x10; static constexpr const uint8_t CFG_USR_CLK_REF = 0x20; static constexpr const uint8_t CFG_CLK_OUT_EN = 0x40; static constexpr const uint8_t CFG_LOCK_REQ = 0x80; // PLL register B static constexpr const uint8_t CFG_AUTN_CT_I = 0x01; // only available for PLL0 static constexpr const uint8_t CFG_CLK180_DOUB = 0x08; static constexpr const uint8_t CFG_CLK270_DOUB = 0x10; static constexpr const uint8_t CFG_USR_CLK_OUT = 0x80; static const std::vector> crc_modes = { {"check", 0x00}, // Check CRC {"ignore", 0x01}, // Ignore added CRC {"unused", 0x02} // CRC is unused }; static const std::vector>> spi_modes = { {"single", {}}, // Single SPI mode {"dual", {0x50, 0x21, 0x18, 0x3B}}, // Dual SPI mode {"quad", {0xF0, 0x23, 0x18, 0x6B}} // Quad SPI mode }; static const uint16_t crc_table_x25[256] = { 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78}; class Crc16 { public: uint16_t crc16 = 0xFFFF; void update_crc16(uint8_t val) { crc16 = (crc16 >> 8) ^ crc_table_x25[(crc16 & 0xFF) ^ val]; } uint16_t get_crc16() { return crc16 ^ 0xFFFF; } void reset_crc16() { crc16 = 0xFFFF; } }; // The BitstreamReadWriter class stores state (including CRC16) whilst reading // the bitstream class BitstreamReadWriter { public: BitstreamReadWriter() : data(), iter(data.begin()) {}; BitstreamReadWriter(const std::vector &data) : data(data), iter(this->data.begin()) {}; std::vector data; std::vector::iterator iter; bool crc_unused = false; Crc16 crc16; // Return a single byte and update CRC inline uint8_t get_byte() { assert(iter < data.end()); uint8_t val = *(iter++); crc16.update_crc16(val); return val; } // Read a little endian uint16 from the bitstream and update CRC uint16_t get_uint16() { uint8_t tmp[2]; get_bytes(tmp, 2); return (tmp[0] << 8UL) | (tmp[1]); } // Read a little endian uint32 from the bitstream and update CRC uint32_t get_uint32() { uint8_t tmp[4]; get_bytes(tmp, 4); return (tmp[0] << 24UL) | (tmp[1] << 16UL) | (tmp[2] << 8UL) | (tmp[3]); } // CRC is in big endian order uint16_t get_crc() { uint8_t tmp[2]; get_bytes(tmp, 2); return (tmp[1] << 8UL) | (tmp[0]); } // The command opcode is a byte so this works like get_byte inline uint8_t get_command_opcode() { assert(iter < data.end()); uint8_t val = *(iter++); crc16.update_crc16(val); return val; } // Write a single byte and update CRC inline void write_byte(uint8_t b) { data.push_back(b); crc16.update_crc16(b); } // Copy multiple bytes into an OutputIterator and update CRC template void get_bytes(T out, size_t count) { for (size_t i = 0; i < count; i++) { *out = get_byte(); ++out; } } void get_vector(std::vector &out, size_t count) { for (size_t i = 0; i < count; i++) { out.push_back(get_byte()); } } // Write multiple bytes from an InputIterator and update CRC template void write_bytes(T in, size_t count) { for (size_t i = 0; i < count; i++) write_byte(*(in++)); } void write_bytes(std::vector in) { for (auto val : in) write_byte(val); } // Skip over bytes while updating CRC void skip_bytes(size_t count) { for (size_t i = 0; i < count; i++) get_byte(); } // Write a little endian uint16_t into the bitstream void write_uint16(uint16_t val) { write_byte(uint8_t((val >> 8UL) & 0xFF)); write_byte(uint8_t(val & 0xFF)); } // Write a little endian uint32_t into the bitstream void write_uint32(uint32_t val) { write_byte(uint8_t((val >> 24UL) & 0xFF)); write_byte(uint8_t((val >> 16UL) & 0xFF)); write_byte(uint8_t((val >> 8UL) & 0xFF)); write_byte(uint8_t(val & 0xFF)); } // Get the offset into the bitstream size_t get_offset() { return size_t(distance(data.begin(), iter)); } void set_crc_unused(bool val) { crc_unused = val; } bool get_crc_unused() { return crc_unused; } // Insert the calculated CRC16 into the bitstream void insert_crc16() { if (crc_unused) return; uint16_t actual_crc = crc16.get_crc16(); write_byte(uint8_t((actual_crc) & 0xFF)); write_byte(uint8_t((actual_crc >> 8) & 0xFF)); } bool is_end() { return (iter >= data.end()); } const std::vector &get() { return data; }; void write_nops(size_t count) { for (size_t i = 0; i < count; i++) write_byte(0); } // Writing commands void write_header(uint8_t cmd, uint16_t len) { crc16.reset_crc16(); write_byte(cmd); if (cmd == CMD_FRAM) write_uint16(len); else write_byte(len & 0xff); insert_crc16(); } void write_cmd_path(uint8_t data) { write_header(CMD_PATH, 1); write_byte(data); insert_crc16(); write_nops(4); write_byte(0x33); write_nops(4); } void write_cmd_jump(uint32_t addr) { write_header(CMD_JUMP, 4); write_byte(uint8_t(addr & 0xFF)); write_byte(uint8_t((addr >> 8UL) & 0xFF)); write_byte(uint8_t((addr >> 16UL) & 0xFF)); write_byte(uint8_t((addr >> 24UL) & 0xFF)); insert_crc16(); write_nops(2); } void write_cmd_cfgmode(uint8_t crcmode, std::vector spimode) { write_header(CMD_CFGMODE, spimode.size() > 0 ? 6 : 2); write_byte(0xFF); // crc retries write_byte(crcmode); // crc error behaviour if (spimode.size() > 0) { write_byte(spimode[0]); // spi io width write_byte(spimode[1]); // spi dummy cycles write_byte(spimode[2]); // flash address field length write_byte(spimode[3]); // flash READ command } insert_crc16(); write_nops(4); if (crcmode == 0x02) { crc_unused = true; } } void write_cmd_spll(uint8_t data) { write_header(CMD_SPLL, 1); write_byte(data); insert_crc16(); } void write_cmd_wait_pll(uint8_t data) { write_header(CMD_WAIT_PLL, 1); write_byte(data); insert_crc16(); } void write_cmd_cfgrst(uint8_t data) { write_header(CMD_CFGRST, 1); write_byte(data); insert_crc16(); } void write_cmd_slave_mode(uint8_t data) { write_header(CMD_SLAVE_MODE, 1); write_byte(data); insert_crc16(); write_nops(3); } void write_cmd_d2d(uint8_t data) { write_header(CMD_D2D, 1); write_byte(data); insert_crc16(); } void write_cmd_rxrys(uint8_t x_ram_sel, uint8_t y_ram_sel) { write_header(CMD_RXRYS, 2); write_byte(x_ram_sel); write_byte(y_ram_sel); insert_crc16(); } void write_cmd_lxlys(uint8_t x_sel, uint8_t y_sel) { write_header(CMD_LXLYS, 2); write_byte(x_sel); write_byte(y_sel); insert_crc16(); } void write_cmd_aclcu(uint16_t data) { write_header(CMD_ACLCU, 2); write_uint16(data); insert_crc16(); } void write_cmd_pll(int index, std::vector data, int size) { write_header(CMD_PLL, size); for (int i = 0; i < Die::PLL_CFG_SIZE; i++) write_byte(data[i + index * Die::PLL_CFG_SIZE]); int pos = Die::PLL_CFG_SIZE * Die::MAX_PLL * 2; for (int i = pos; i < pos + size - Die::PLL_CFG_SIZE; i++) write_byte(data[i]); insert_crc16(); write_nops(6); } void write_cmd_chg_status(uint8_t data) { write_header(CMD_CHG_STATUS, 1); write_byte(data); insert_crc16(); write_nops(4); write_byte(0x33); write_nops(4); } void write_cmd_chg_status(uint8_t cfg, uint8_t next_mode, std::vector data) { write_header(CMD_CHG_STATUS, 12); write_byte(cfg); write_byte(next_mode); for (int i = 2; i < 12; i++) write_byte(data[Die::STATUS_CFG_START + i]); insert_crc16(); write_nops(4); write_byte(0x33); write_nops(4); } }; void check_crc(BitstreamReadWriter &rd) { if (rd.get_crc_unused()) return; uint16_t actual_crc = rd.crc16.get_crc16(); uint16_t exp_crc = rd.get_crc(); // crc if (actual_crc != exp_crc) { std::ostringstream err; err << "crc fail, calculated 0x" << std::hex << actual_crc << " but expecting 0x" << exp_crc; throw BitstreamParseError(err.str()); } } #define BITSTREAM_DEBUG(x) \ if (verbosity >= VerbosityLevel::DEBUG) \ std::cerr << "bitstream: " << x << std::endl #define BITSTREAM_NOTE(x) \ if (verbosity >= VerbosityLevel::NOTE) \ std::cerr << "bitstream: " << x << std::endl #define BITSTREAM_FATAL(x, pos) \ { \ std::ostringstream ss; \ ss << x; \ throw BitstreamParseError(ss.str(), pos); \ } Bitstream::Bitstream(const std::vector &data) : data(data) {} Bitstream Bitstream::read(std::istream &in) { std::vector bytes; in.seekg(0, in.end); size_t length = size_t(in.tellg()); in.seekg(0, in.beg); bytes.resize(length); in.read(reinterpret_cast(&(bytes[0])), length); return Bitstream(bytes); } int Bitstream::determine_size(int *max_die_x, int *max_die_y) { BitstreamReadWriter rd(data); int die_x = 0; int die_y = 0; while (!rd.is_end()) { rd.crc16.reset_crc16(); uint8_t cmd = rd.get_command_opcode(); uint16_t length = (cmd == CMD_FRAM) ? rd.get_uint16() : rd.get_byte(); std::vector block; switch (cmd) { case CMD_DLCU: case CMD_FRAM: case CMD_FLASH: case CMD_SERDES: case CMD_PLL: case CMD_CHG_STATUS: case CMD_SLAVE_MODE: case CMD_CFGMODE: case CMD_SPLL: case CMD_LXLYS: case CMD_ACLCU: case CMD_RXRYS: case CMD_D2D: case CMD_CFGRST: case CMD_JUMP: // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); // Set CRC flag if (cmd == CMD_CFGMODE) rd.set_crc_unused(block[1] == 0x02); // Skip bytes if (cmd == CMD_SLAVE_MODE) rd.skip_bytes(3); if (cmd == CMD_CFGMODE) rd.skip_bytes(4); if (cmd == CMD_PLL) rd.skip_bytes(6); if (cmd == CMD_CHG_STATUS) rd.skip_bytes(9); if (cmd == CMD_JUMP) rd.skip_bytes(2); break; case CMD_PATH: // Check header CRC check_crc(rd); // Read data block switch (rd.get_byte()) { case 0x01: // reset die_x = 0; die_y = 0; break; case 0x02: // top die_y += 1; break; case 0x04: // right die_x += 1; break; case 0x08: // TODO : forward break; case 0x10: // prog *max_die_x = std::max(*max_die_x, die_x); *max_die_y = std::max(*max_die_y, die_y); break; default: break; } // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(9); break; default: BITSTREAM_FATAL("Unhandled command 0x" << std::hex << std::setw(2) << std::setfill('0') << int(cmd), rd.get_offset()); break; } } return (*max_die_x + 1) * (*max_die_y + 1); } Chip Bitstream::deserialise_chip() { std::cerr << "bitstream size: " << data.size() * 8 << " bits" << std::endl; int max_die_x = 0; int max_die_y = 0; int max_dies = determine_size(&max_die_x, &max_die_y); Chip chip(max_dies); Die *die = &chip.get_die(0); BitstreamReadWriter rd(data); bool is_block_ram = false; uint8_t x_pos = 0, y_pos = 0; uint8_t pll_select = 0x0f; uint16_t aclcu = 0; int die_x = 0; int die_y = 0; std::map, int> tile_iteration; while (!rd.is_end()) { rd.crc16.reset_crc16(); uint8_t cmd = rd.get_command_opcode(); uint16_t length = (cmd == CMD_FRAM) ? rd.get_uint16() : rd.get_byte(); std::vector block; switch (cmd) { case CMD_DLCU: BITSTREAM_DEBUG("CMD_DLCU"); // if (length>112) // BITSTREAM_FATAL("DLCU data longer than expected", rd.get_offset()); if (is_block_ram) { if (length > 27) BITSTREAM_FATAL("RAM configuration must be up to 27 bytes", rd.get_offset()); } else { if (length > 112) BITSTREAM_FATAL("Tile configuration must be up to 112 bytes", rd.get_offset()); } // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); if (is_block_ram) die->write_ram(x_pos, y_pos, block); else { int iteration = -1; if (tile_iteration.count(std::make_pair(x_pos, y_pos))) iteration = tile_iteration[std::make_pair(x_pos, y_pos)]; tile_iteration[std::make_pair(x_pos, y_pos)] = ++iteration; if (iteration != 0) BITSTREAM_DEBUG("iteration " << (iteration + 1)); // Detection of FF initialization is possible on // last iteration if (iteration == 2) { std::vector data = die->get_latch_config(x_pos, y_pos); // Make sure we have CPE data // even if uninitialized block.resize(40, 0x00); uint8_t val = 0x00; for (int i = 0; i < 4; i++) { uint8_t v = block[i * 10 + 8] ^ data[i * 10 + 8]; if (v & 0x30) val |= Die::FF_INIT_RESET << (i * 2); else if (v & 0xc0) val |= Die::FF_INIT_SET << (i * 2); else if (v != 0x00) BITSTREAM_FATAL(stringf("Unknown CPE state %d on pos 0x%02x,0x%02x\n", v, x_pos, y_pos), rd.get_offset()); } die->write_ff_init(x_pos, y_pos, val); } die->write_latch(x_pos, y_pos, block); } break; case CMD_PATH: BITSTREAM_DEBUG("CMD_PATH"); tile_iteration.clear(); if (length != 1) BITSTREAM_FATAL("PATH data must be one byte long", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block switch (rd.get_byte()) { case 0x01: // reset die_x = 0; die_y = 0; break; case 0x02: // top die_y += 1; break; case 0x04: // right die_x += 1; break; case 0x08: // TODO : forward break; case 0x10: // prog die = &chip.get_die(die_x * (max_die_y + 1) + die_y); break; default: break; } // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(9); break; case CMD_D2D: BITSTREAM_DEBUG("CMD_D2D"); if (length != 1) BITSTREAM_FATAL("CMD_D2D data must be one byte long", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block die->write_d2d_config(rd.get_byte()); // Check data CRC check_crc(rd); break; case CMD_SPLL: BITSTREAM_DEBUG("CMD_SPLL"); if (length != 1) BITSTREAM_FATAL("SPLL data must be one byte long", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block pll_select = rd.get_byte(); // Check data CRC check_crc(rd); break; case CMD_PLL: BITSTREAM_DEBUG("CMD_PLL"); if (length < 12) BITSTREAM_FATAL("PLL data smaller than expected", rd.get_offset()); if (length > 24) BITSTREAM_FATAL("PLL data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); die->write_pll_select(pll_select, block); // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(6); break; case CMD_LXLYS: if (length != 2) BITSTREAM_FATAL("LXLYS data must be two bytes long", rd.get_offset()); // Check header CRC check_crc(rd); BITSTREAM_DEBUG("CMD_LXLYS"); is_block_ram = false; x_pos = rd.get_byte(); if (x_pos > 81) BITSTREAM_FATAL("Tile column (X) must be in range 0-81, current value " << x_pos, rd.get_offset()); y_pos = rd.get_byte(); if (y_pos > 65) BITSTREAM_FATAL("Tile row (Y) must be in range 0-65, current value " << y_pos, rd.get_offset()); // Check data CRC check_crc(rd); break; case CMD_ACLCU: BITSTREAM_DEBUG("CMD_ACLCU"); if (length != 2) BITSTREAM_FATAL("ACLCU data must be two bytes long", rd.get_offset()); // Check header CRC check_crc(rd); aclcu = rd.get_uint16(); // Check data CRC check_crc(rd); break; case CMD_RXRYS: BITSTREAM_DEBUG("CMD_RXRYS"); if (length != 2) BITSTREAM_FATAL("RXRYS data must be two bytes long", rd.get_offset()); // Check header CRC check_crc(rd); is_block_ram = true; x_pos = rd.get_byte(); if (x_pos > 3) BITSTREAM_FATAL("RAM column (X) must be in range 0-3, current value " << x_pos, rd.get_offset()); y_pos = rd.get_byte(); if (y_pos > 7) BITSTREAM_FATAL("RAM row (Y) must be in range 0-7, current value " << y_pos, rd.get_offset()); // Check data CRC check_crc(rd); break; case CMD_FRAM: BITSTREAM_DEBUG("CMD_FRAM"); if (length > 5120) BITSTREAM_FATAL("FRAM data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); die->write_ram_data(x_pos, y_pos, block, aclcu); break; case CMD_CHG_STATUS: BITSTREAM_DEBUG("CMD_CHG_STATUS"); if (length > 12) BITSTREAM_FATAL("CHG_STATUS data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); die->write_status(block); // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(9); break; case CMD_SLAVE_MODE: BITSTREAM_DEBUG("CMD_SLAVE_MODE"); if (length > 1) BITSTREAM_FATAL("SLAVE_MODE must be one byte long", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_byte(); // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(3); break; case CMD_FLASH: BITSTREAM_DEBUG("CMD_FLASH"); if (length > 11) BITSTREAM_FATAL("FLASH data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); break; case CMD_CFGMODE: BITSTREAM_DEBUG("CMD_CFGMODE"); if (length > 20) BITSTREAM_FATAL("CFGMODE data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); rd.set_crc_unused(block[1] == 0x02); // Skip bytes rd.skip_bytes(4); break; case CMD_SERDES: BITSTREAM_DEBUG("CMD_SERDES"); if (length != 186) BITSTREAM_FATAL("SERDES data does not match size", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); die->write_serdes_cfg(block); // Check data CRC check_crc(rd); break; case CMD_CFGRST: BITSTREAM_DEBUG("CMD_CFGRST"); if (length > 1) BITSTREAM_FATAL("CFGRST data longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); break; case CMD_JUMP: BITSTREAM_DEBUG("CMD_JUMP"); if (length > 4) BITSTREAM_FATAL("JUMP addr longer than expected", rd.get_offset()); // Check header CRC check_crc(rd); // Read data block rd.get_vector(block, length); // Check data CRC check_crc(rd); // Skip bytes rd.skip_bytes(2); break; default: BITSTREAM_FATAL("Unhandled command 0x" << std::hex << std::setw(2) << std::setfill('0') << int(cmd), rd.get_offset()); break; } } return chip; } bool is_edge_location(int x, int y) { return ((x == 0) || (x == Die::MAX_COLS - 1) || (y == 0) || (y == Die::MAX_ROWS - 1)); } Bitstream Bitstream::serialise_chip(const Chip &chip, const std::map options) { BitstreamReadWriter wr; for (int d = chip.get_max_die() - 1; d >= 0; d--) { auto &die = chip.get_die(d); if (chip.get_max_die() != 1) { wr.write_cmd_path(0x01); // Need to reset PATH switch (chip.get_max_die()) { case 2: // CCGM1A2 switch (d) { case 0: // 1A break; case 1: // 1B wr.write_cmd_path(0x02); // top break; } break; case 4: // CCGM1A4 switch (d) { case 0: // 1A break; case 1: // 1B wr.write_cmd_path(0x02); // top break; case 2: // 2A wr.write_cmd_path(0x04); // _right break; case 3: // 2B wr.write_cmd_path(0x02); // top wr.write_cmd_path(0x04); // _right break; } break; default: throw BitstreamParseError("Unsupported number of dies.\n"); } } wr.write_cmd_path(0x10); if (options.count("reset") && !options.count("background")) { wr.write_cmd_cfgrst(0x00); } bool change_crc = false; auto crcmode = crc_modes.begin(); if (options.count("crcmode")) { change_crc = true; crcmode = find_if(crc_modes.begin(), crc_modes.end(), [&](const std::pair &fp) { return fp.first == options.at("crcmode"); }); if (crcmode == crc_modes.end()) { throw std::runtime_error("bad crcmode option " + options.at("crcmode")); } } bool change_spi = false; auto spimode = spi_modes.begin(); if (options.count("spimode")) { change_spi = true; spimode = find_if(spi_modes.begin(), spi_modes.end(), [&](const std::pair> &fp) { return fp.first == options.at("spimode"); }); if (spimode == spi_modes.end()) { throw std::runtime_error("bad spimode option " + options.at("spimode")); } } if (change_crc || change_spi) { wr.write_cmd_cfgmode(uint8_t(crcmode->second), std::vector(spimode->second)); } uint8_t d2d = die.get_d2d_config(); if (d2d) wr.write_cmd_d2d(d2d); // PLL setup std::vector die_config = die.get_die_config(); bool pll_written = false; for (int i = 0; i < Die::MAX_PLL; i++) { bool cfg_a = !die.is_pll_cfg_empty(i * 2 + 0); bool cfg_b = !die.is_pll_cfg_empty(i * 2 + 1); int size = Die::PLL_CFG_SIZE; if (!die.is_clkin_cfg_empty()) size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE; if (!die.is_glbout_cfg_empty()) size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE + Die::GLBOUT_CFG_SIZE; if (cfg_a || cfg_b) { wr.write_cmd_spll(1 << i); wr.write_cmd_pll(i * 2, die_config, size); if (cfg_b) { wr.write_cmd_spll(1 << i | 1 << (i + 4)); wr.write_cmd_pll(i * 2 + 1, die_config, size); } pll_written = true; } } if (!pll_written) { int size = Die::PLL_CFG_SIZE; if (!die.is_clkin_cfg_empty()) size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE; if (!die.is_glbout_cfg_empty()) size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE + Die::GLBOUT_CFG_SIZE; // Since it is not possible to skip writing to PLL configuration // we overwrite B configuration of last PLL with all zeros in this case. // This is needed for reconfigurable bitstreams not to affect PLL of bootloader. wr.write_cmd_spll(0x80); wr.write_cmd_pll(0, die_config, size); } // Write RAM configuration bool ram_used = false; for (int y = Die::MAX_RAM_ROWS - 1; y >= 0; y--) { for (int x = Die::MAX_RAM_COLS - 1; x >= 0; x--) { // Empty configuration is skipped if (die.is_ram_empty(x, y)) continue; std::vector data = std::vector(die.get_ram_config(x, y)); wr.write_cmd_rxrys(x, y); wr.write_header(CMD_DLCU, data.size()); wr.write_bytes(data); wr.insert_crc16(); ram_used = true; } } // Write RAM contents if (ram_used) { wr.write_cmd_chg_status(CFG_FILL_RAM); for (int y = Die::MAX_RAM_ROWS - 1; y >= 0; y--) { for (int x = Die::MAX_RAM_COLS - 1; x >= 0; x--) { // Empty configuration is skipped if (die.is_ram_data_empty(x, y)) continue; std::vector data = std::vector(die.get_ram_data(x, y)); wr.write_cmd_rxrys(x, y); wr.write_cmd_aclcu(0); wr.write_header(CMD_FRAM, data.size()); wr.write_bytes(data); wr.insert_crc16(); ram_used = true; } } wr.write_cmd_chg_status(CFG_NONE); } // Write latch configuration int scrubaddr = 0; for (int iteration = 0; iteration < 3; iteration++) { for (int y = 0; y < Die::MAX_ROWS; y++) { for (int x = 0; x < Die::MAX_COLS; x++) { // Empty configuration is skipped if (die.is_latch_empty(x, y)) continue; // Only tiles with CPE can have multiple iterations if (iteration != 0 && is_edge_location(x, y)) continue; // If CPE empty skip other iterations if (iteration != 0 && die.is_cpe_empty(x, y)) continue; if (iteration == 1 && scrubaddr == 0) scrubaddr = wr.data.size(); std::vector data = std::vector(die.get_latch_config(x, y)); uint8_t ff_init = data.back(); data.pop_back(); if (!is_edge_location(x, y)) { if (iteration == 0) { // First iteration does not setup CPE at all std::fill(data.begin(), data.begin() + 40, 0); // Empty configuration is skipped if (std::all_of(data.begin(), data.end(), [](uint8_t i) { return i == 0; })) continue; } // 2nd iteration with no changes if no FF initialization if (iteration == 1 && ff_init) { // Only CPE data is exported data.resize(40); // Set initial FFs states for (int i = 0; i < 4; i++) { uint8_t ff = (ff_init >> (i * 2)) & 0x03; if (ff == Die::FF_INIT_RESET) data[i * 10 + 8] &= 0x30 ^ 0xff; else if (ff == Die::FF_INIT_SET) data[i * 10 + 8] &= 0xc0 ^ 0xff; } } // 3rd iteration only if there was FF initialization if (iteration == 2) { if (!ff_init) continue; // Only CPE data is exported data.resize(40); } } // minimize output auto rit = std::find_if(data.rbegin(), data.rend(), [](uint8_t val) { return val != 0; }); data.erase(rit.base(), end(data)); wr.write_cmd_lxlys(x, y); wr.write_header(CMD_DLCU, data.size()); wr.write_bytes(data); wr.insert_crc16(); } } } uint8_t cfg_stat = CFG_CPE_RESET; uint8_t cfg_mode = 0x1F; // unused mode enforces controller to stop // Only for die 0 if (d == 0) { // Write change status if (die.is_using_cfg_gpios()) wr.write_cmd_chg_status(CFG_DONE); cfg_stat |= CFG_DONE; if (!options.count("background")) { cfg_stat |= CFG_STOP; } if (options.count("bootaddr")) { cfg_stat |= CFG_RECONFIG; } if (options.count("reconfig")) { cfg_stat |= CFG_CPE_CFG; } if (options.count("bootaddr") || options.count("background")) { cfg_mode = 0x10; // active spi // Enable autonomous clock if PLL not enabled if (die.is_pll_cfg_empty(0)) { die_config[Die::STATUS_CFG_START + 2 + 2] |= CFG_PLL_AUTN; die_config[Die::STATUS_CFG_START + 2 + 3] |= CFG_AUTN_CT_I; } } } if (!die.is_serdes_cfg_empty()) { cfg_stat |= CFG_SERDES; wr.write_header(CMD_SERDES, die.get_serdes_config().size()); wr.write_bytes(die.get_serdes_config()); wr.insert_crc16(); } wr.write_cmd_chg_status(cfg_stat, cfg_mode, die_config); if (d == 0) { if (options.count("bootaddr") && !options.count("background")) { uint32_t bootaddr = std::strtoul(options.at("bootaddr").c_str(), nullptr, 0); wr.write_cmd_cfgrst(0x00); wr.write_cmd_jump(bootaddr); } if (options.count("background") && !options.count("bootaddr")) { wr.write_cmd_jump(scrubaddr); } } } return Bitstream(wr.get()); } void Bitstream::write_bit(std::ostream &out) { // Dump raw bitstream out.write(reinterpret_cast(&(data[0])), data.size()); } BitstreamParseError::BitstreamParseError(const std::string &desc) : runtime_error(desc.c_str()), desc(desc), offset(-1) { } BitstreamParseError::BitstreamParseError(const std::string &desc, size_t offset) : runtime_error(desc.c_str()), desc(desc), offset(int(offset)) { } const char *BitstreamParseError::what() const noexcept { std::ostringstream ss; ss << "Bitstream Parse Error: "; ss << desc; if (offset != -1) ss << " [at 0x" << std::hex << std::setw(8) << std::setfill('0') << offset << "]"; return strdup(ss.str().c_str()); } } // namespace GateMate prjpeppercorn-1.12/libgm/src/Chip.cpp000066400000000000000000000032521514752025000176010ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "Chip.hpp" #include "Util.hpp" namespace GateMate { Chip::Chip(std::string name) { const std::string prefix = "CCGM1A"; if (name.rfind(prefix, 0) == 0) { std::string numberPart = name.substr(prefix.size()); if (!numberPart.empty() && std::all_of(numberPart.begin(), numberPart.end(), ::isdigit)) { int num = std::stoi(numberPart); *this = Chip(num); return; } else { throw std::invalid_argument("Invalid format after CCGM1A"); } } die_num = -1; } Chip::Chip(int num) : die_num(num) { Die die; for (int i = 0; i < num; i++) dies.push_back(die); } int Chip::get_max_die() const { return die_num; } std::string Chip::get_name() const { return stringf("CCGM1A%d", die_num); } } // namespace GateMate prjpeppercorn-1.12/libgm/src/ChipConfig.cpp000066400000000000000000000161621514752025000207330ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "ChipConfig.hpp" #include #include #include #include "Chip.hpp" #include "TileBitDatabase.hpp" #include "Util.hpp" namespace GateMate { std::string ChipConfig::to_string() const { std::stringstream ss; ss << ".device " << chip_name << std::endl << std::endl; for (const auto &config : configs) { if (!config.second.empty()) { ss << ".config " << config.first << " " << std::endl; ss << config.second; ss << std::endl; } } for (const auto &ser : serdes) { if (!ser.second.empty()) { ss << ".serdes " << ser.first << " " << std::endl; ss << ser.second; ss << std::endl; } } for (const auto &tile : tiles) { if (!tile.second.empty()) { ss << ".tile " << tile.first.die << " " << tile.first.x << " " << tile.first.y << std::endl; ss << tile.second; ss << std::endl; } } for (const auto &bram : brams) { if (!bram.second.empty()) { ss << ".bram " << bram.first.die << " " << bram.first.x << " " << bram.first.y << std::endl; ss << bram.second; ss << std::endl; } } for (const auto &bram : bram_data) { if (!bram.second.empty()) { ss << ".bram_init " << bram.first.die << " " << bram.first.x << " " << bram.first.y << std::endl; std::ios_base::fmtflags f(ss.flags()); for (size_t i = 0; i < bram.second.size(); i++) { ss << std::setw(2) << std::setfill('0') << std::hex << (int)bram.second.at(i); if (i % 40 == 39) ss << std::endl; else ss << " "; } ss.flags(f); ss << std::endl; } } return ss.str(); } ChipConfig ChipConfig::from_string(const std::string &config) { std::stringstream ss(config); ChipConfig cc; while (!skip_check_eof(ss)) { std::string verb; ss >> verb; if (verb == ".device") { ss >> cc.chip_name; } else if (verb == ".config") { int die; ss >> die; TileConfig tc; ss >> tc; cc.configs.emplace(die, tc); } else if (verb == ".serdes") { int die; ss >> die; TileConfig tc; ss >> tc; cc.serdes.emplace(die, tc); } else if (verb == ".tile") { CfgLoc loc; ss >> loc.die; ss >> loc.x; ss >> loc.y; TileConfig tc; ss >> tc; cc.tiles.emplace(loc, tc); } else if (verb == ".bram") { CfgLoc loc; ss >> loc.die; ss >> loc.x; ss >> loc.y; TileConfig tc; ss >> tc; cc.brams.emplace(loc, tc); } else if (verb == ".bram_init") { CfgLoc loc; ss >> loc.die; ss >> loc.x; ss >> loc.y; std::ios_base::fmtflags f(ss.flags()); while (!skip_check_eor(ss)) { uint16_t value; ss >> std::hex >> value; cc.bram_data[loc].push_back(value); } ss.flags(f); } else { throw std::runtime_error("unrecognised config entry " + verb); } } return cc; } Chip ChipConfig::to_chip() const { Chip chip(chip_name); for (int d = 0; d < chip.get_max_die(); d++) { auto &die = chip.get_die(d); CfgLoc loc; loc.die = d; for (int y = 0; y < die.get_max_row(); y++) { loc.y = y; for (int x = 0; x < die.get_max_col(); x++) { loc.x = x; if (tiles.count(loc)) { TileBitDatabase db(x, y); const TileConfig &cfg = tiles.at(loc); die.write_latch(x, y, db.config_to_data(cfg)); } } } RamBitDatabase ram_db; for (int y = 0; y < die.get_max_ram_row(); y++) { loc.y = y; for (int x = 0; x < die.get_max_ram_col(); x++) { loc.x = x; if (brams.count(loc)) { const TileConfig &cfg = brams.at(loc); die.write_ram(x, y, ram_db.config_to_data(cfg)); } if (bram_data.count(loc)) die.write_ram_data(x, y, bram_data.at(loc), 0); } } ConfigBitDatabase cfg_db; if (configs.count(d)) { const TileConfig &cfg = configs.at(d); die.write_die_cfg(cfg_db.config_to_data(cfg)); } SerdesBitDatabase ser_db; if (serdes.count(d)) { const TileConfig &cfg = serdes.at(d); die.write_serdes_cfg(ser_db.config_to_data(cfg)); } } return chip; } ChipConfig ChipConfig::from_chip(const Chip &chip) { ChipConfig cc; cc.chip_name = chip.get_name(); for (int d = 0; d < chip.get_max_die(); d++) { auto &die = chip.get_die(d); CfgLoc loc; loc.die = d; for (int y = 0; y < die.get_max_row(); y++) { loc.y = y; for (int x = 0; x < die.get_max_col(); x++) { loc.x = x; TileBitDatabase db(x, y); if (!die.is_latch_empty(x, y)) cc.tiles.emplace(loc, db.data_to_config(die.get_latch_config(x, y))); } } RamBitDatabase ram_db; for (int y = 0; y < die.get_max_ram_row(); y++) { loc.y = y; for (int x = 0; x < die.get_max_ram_col(); x++) { loc.x = x; if (!die.is_ram_empty(x, y)) { cc.brams.emplace(loc, ram_db.data_to_config(die.get_ram_config(x, y))); if (!die.is_ram_data_empty(x, y)) { cc.bram_data.emplace(loc, die.get_ram_data(x, y)); } } } } ConfigBitDatabase cfg_db; cc.configs.emplace(d, cfg_db.data_to_config(die.get_die_config())); SerdesBitDatabase ser_db; cc.serdes.emplace(d, ser_db.data_to_config(die.get_serdes_config())); } return cc; } } // namespace GateMate prjpeppercorn-1.12/libgm/src/Die.cpp000066400000000000000000000121341514752025000174160ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "Die.hpp" #include "Util.hpp" namespace GateMate { Die::Die() { for (int y = 0; y < MAX_ROWS; y++) { for (int x = 0; x < MAX_COLS; x++) { latch[std::make_pair(x, y)] = std::vector(); latch[std::make_pair(x, y)].reserve(LATCH_BLOCK_SIZE); } } for (int y = 0; y < MAX_RAM_ROWS; y++) { for (int x = 0; x < MAX_RAM_COLS; x++) { ram[std::make_pair(x, y)] = std::vector(); ram[std::make_pair(x, y)].reserve(RAM_BLOCK_SIZE); ram_data[std::make_pair(x, y)] = std::vector(); } } serdes_cfg = std::vector(SERDES_CFG_SIZE, 0x00); die_cfg = std::vector(DIE_CONFIG_SIZE, 0x00); } bool Die::is_latch_empty(int x, int y) const { return latch.at(std::make_pair(x, y)).empty(); } bool Die::is_cpe_empty(int x, int y) const { auto &block = latch.at(std::make_pair(x, y)); for (int i = 0; i < 40; i++) if (block[i] != 0x00) return false; return true; } bool Die::is_ram_empty(int x, int y) const { return ram.at(std::make_pair(x, y)).empty(); } bool Die::is_ram_data_empty(int x, int y) const { return ram_data.at(std::make_pair(x, y)).empty(); } bool Die::is_pll_cfg_empty(int index) const { int pos = index * PLL_CFG_SIZE; for (int i = 0; i < PLL_CFG_SIZE; i++) if (die_cfg[i + pos] != 0x00) return false; return true; } bool Die::is_clkin_cfg_empty() const { int pos = PLL_CFG_SIZE * MAX_PLL * 2; for (int i = 0; i < CLKIN_CFG_SIZE; i++) if (die_cfg[i + pos] != 0x00) return false; return true; } bool Die::is_glbout_cfg_empty() const { int pos = PLL_CFG_SIZE * MAX_PLL * 2 + CLKIN_CFG_SIZE; for (int i = 0; i < GLBOUT_CFG_SIZE; i++) if (die_cfg[i + pos] != 0x00) return false; return true; } bool Die::is_status_cfg_empty() const { int pos = STATUS_CFG_START; // First two bytes contain status change commands for (int i = 2; i < STATUS_CFG_SIZE; i++) if (die_cfg[i + pos] != 0x00) return false; return true; } bool Die::is_serdes_cfg_empty() const { for (int i = 0; i < SERDES_CFG_SIZE; i++) if (serdes_cfg[i] != 0x00) return false; return true; } bool Die::is_using_cfg_gpios() const { return die_cfg[STATUS_CFG_START + 2] & 0x08; } uint8_t Die::get_d2d_config() const { return die_cfg[DIE_CONFIG_SIZE - 1]; } void Die::write_latch(int x, int y, const std::vector &data) { int pos = 0; auto &block = latch.at(std::make_pair(x, y)); block.resize(LATCH_BLOCK_SIZE, 0x00); for (auto d : data) block[pos++] = d; } void Die::write_ff_init(int x, int y, uint8_t data) { auto &block = latch.at(std::make_pair(x, y)); block.resize(LATCH_BLOCK_SIZE, 0x00); block[LATCH_BLOCK_SIZE - 1] = data; } void Die::write_ram(int x, int y, const std::vector &data) { int pos = 0; auto &block = ram.at(std::make_pair(x, y)); block.resize(RAM_BLOCK_SIZE, 0x00); for (auto d : data) block[pos++] = d; } void Die::write_ram_data(int x, int y, const std::vector &data, uint16_t addr) { int pos = addr; auto &block = ram_data.at(std::make_pair(x, y)); block.resize(MEMORY_SIZE, 0x00); for (auto d : data) block[pos++] = d; } void Die::write_status(const std::vector &data) { int pos = STATUS_CFG_START; for (auto d : data) die_cfg[pos++] = d; // Clean command bits, we do not wish this exported pos = STATUS_CFG_START; die_cfg[pos++] = 0x00; die_cfg[pos++] = 0x00; } void Die::write_pll_select(uint8_t select, const std::vector &data) { for (int i = 0; i < MAX_PLL; i++) { if (select & (1 << i)) { int pos = i * 2 * PLL_CFG_SIZE; if (select & (1 << (i + 4))) { pos += PLL_CFG_SIZE; } for (size_t j = 0; j < PLL_CFG_SIZE; j++) die_cfg[pos++] = data[j]; } } int pos = PLL_CFG_SIZE * MAX_PLL * 2; // start after PLL data; for (size_t j = PLL_CFG_SIZE; j < data.size(); j++) die_cfg[pos++] = data[j]; } void Die::write_d2d_config(uint8_t data) { die_cfg[DIE_CONFIG_SIZE - 1] = data; } } // namespace GateMate prjpeppercorn-1.12/libgm/src/TileBitDatabase.cpp000066400000000000000000001222421514752025000217000ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "TileBitDatabase.hpp" #include #include #include #include "Chip.hpp" #include "ChipConfig.hpp" #include "Util.hpp" namespace GateMate { std::vector data_bytes_to_array(const std::vector &data, size_t count) { std::vector result(count * 8); for (size_t j = 0; j < count; j++) { uint8_t val = data[j]; for (size_t i = 0; i < 8; i++) { uint8_t temp = 1 << i; if (val & temp) result[j * 8 + i] = true; else result[j * 8 + i] = false; } } return result; } bool is_array_empty(std::vector &array) { for (bool val : array) if (val) return false; return true; } BaseBitDatabase::BaseBitDatabase(int num_bits) : num_bits(num_bits), known_bits(num_bits, false) {} BaseBitDatabase::~BaseBitDatabase() {} void BaseBitDatabase::add_word_settings(const std::string &name, int start, int len) { if (words.find(name) != words.end()) throw DatabaseConflictError(fmt("word " << name << " already exists in DB")); for (int i = start; i < start + len; i++) { if (known_bits[i]) throw DatabaseConflictError(fmt("bit " << i << " for word " << name << " already mapped")); known_bits[i] = true; } words[name] = {start, start + len}; } void BaseBitDatabase::add_unknowns() { for (int i = 0; i < num_bits; i++) { if (!known_bits[i]) words[stringf("UNKNOWN_%03d", i)] = {i, i + 1}; } } std::vector BaseBitDatabase::bits_to_bytes(std::vector &bits) { std::vector val; size_t pos = 0; for (size_t j = 0; j < bits.size() / 8; j++) { uint8_t data = 0; for (int i = 0; i < 8; i++) { data >>= 1; data |= bits[pos] ? 0x80 : 0x00; pos++; } val.push_back(data); } return val; } std::vector BaseBitDatabase::config_to_data(const TileConfig &cfg) { std::vector tile(num_bits, false); for (auto &w : cfg.cwords) { if (words.count(w.name)) { words[w.name].set_value(tile, w.value); } else { throw std::runtime_error(fmt("unknown word " << w.name << " found while converting data")); } } return bits_to_bytes(tile); } TileConfig BaseBitDatabase::data_to_config(const std::vector &data) { TileConfig cfg; std::vector d = data_bytes_to_array(data, num_bits * 8); for (auto &w : words) { auto val = w.second.get_value(d); if (is_array_empty(val)) continue; cfg.add_word(w.first, val); } return cfg; } void TileBitDatabase::add_sb_big(int index, int start) { add_word_settings(stringf("SB_BIG.P%02d.YDIAG", index), start + 0, 3); add_word_settings(stringf("SB_BIG.P%02d.Y1", index), start + 3, 3); add_word_settings(stringf("SB_BIG.P%02d.Y2", index), start + 6, 3); add_word_settings(stringf("SB_BIG.P%02d.Y3", index), start + 9, 3); add_word_settings(stringf("SB_BIG.P%02d.Y4", index), start + 12, 3); } void TileBitDatabase::add_sb_sml(int index, int start) { add_word_settings(stringf("SB_SML.P%02d.YDIAG", index), start + 0, 3); add_word_settings(stringf("SB_SML.P%02d.Y1", index), start + 3, 2); add_word_settings(stringf("SB_SML.P%02d.Y2", index), start + 5, 2); add_word_settings(stringf("SB_SML.P%02d.Y3", index), start + 7, 2); add_word_settings(stringf("SB_SML.P%02d.Y4", index), start + 9, 2); } void TileBitDatabase::add_sb_drive(int index, int start) { for (int i = 0; i < 4; i++) add_word_settings(stringf("SB_DRIVE.P%02d.D%d", index, i + 1), start + i, 1); } void TileBitDatabase::add_cpe(int index, int start) { add_word_settings(stringf("CPE%d.INIT_L00", index), start + 0, 4); add_word_settings(stringf("CPE%d.INIT_L01", index), start + 4, 4); add_word_settings(stringf("CPE%d.INIT_L02", index), start + 8, 4); add_word_settings(stringf("CPE%d.INIT_L03", index), start + 12, 4); add_word_settings(stringf("CPE%d.INIT_L10", index), start + 16, 4); add_word_settings(stringf("CPE%d.INIT_L11", index), start + 20, 4); add_word_settings(stringf("CPE%d.INIT_L20", index), start + 24, 4); add_word_settings(stringf("CPE%d.INIT_L30", index), start + 28, 4); add_word_settings(stringf("CPE%d.C_I1", index), start + 32, 1); add_word_settings(stringf("CPE%d.C_I2", index), start + 33, 1); add_word_settings(stringf("CPE%d.C_I3", index), start + 34, 1); add_word_settings(stringf("CPE%d.C_I4", index), start + 35, 1); add_word_settings(stringf("CPE%d.C_FUNCTION", index), start + 36, 3); add_word_settings(stringf("CPE%d.C_COMP", index), start + 39, 1); add_word_settings(stringf("CPE%d.C_COMP_I", index), start + 40, 1); add_word_settings(stringf("CPE%d.C_HORIZ", index), start + 41, 1); add_word_settings(stringf("CPE%d.C_SELX", index), start + 42, 1); add_word_settings(stringf("CPE%d.C_SELY1", index), start + 43, 1); add_word_settings(stringf("CPE%d.C_SELY2", index), start + 44, 1); add_word_settings(stringf("CPE%d.C_SEL_C", index), start + 45, 1); add_word_settings(stringf("CPE%d.C_SEL_P", index), start + 46, 1); add_word_settings(stringf("CPE%d.C_Y12", index), start + 47, 1); add_word_settings(stringf("CPE%d.C_CX_I", index), start + 48, 1); add_word_settings(stringf("CPE%d.C_CY1_I", index), start + 49, 1); add_word_settings(stringf("CPE%d.C_CY2_I", index), start + 50, 1); add_word_settings(stringf("CPE%d.C_PX_I", index), start + 51, 1); add_word_settings(stringf("CPE%d.C_PY1_I", index), start + 52, 1); add_word_settings(stringf("CPE%d.C_PY2_I", index), start + 53, 1); add_word_settings(stringf("CPE%d.C_C_P", index), start + 54, 1); add_word_settings(stringf("CPE%d.C_2D_IN", index), start + 55, 1); add_word_settings(stringf("CPE%d.C_SN", index), start + 56, 3); add_word_settings(stringf("CPE%d.C_O1", index), start + 59, 2); add_word_settings(stringf("CPE%d.C_O2", index), start + 61, 2); add_word_settings(stringf("CPE%d.C_BR", index), start + 63, 1); add_word_settings(stringf("CPE%d.C_CPE_CLK", index), start + 64, 2); add_word_settings(stringf("CPE%d.C_CPE_EN", index), start + 66, 2); add_word_settings(stringf("CPE%d.C_CPE_RES", index), start + 68, 2); add_word_settings(stringf("CPE%d.C_CPE_SET", index), start + 70, 2); add_word_settings(stringf("CPE%d.C_RAM_I1", index), start + 72, 1); add_word_settings(stringf("CPE%d.C_RAM_I2", index), start + 73, 1); add_word_settings(stringf("CPE%d.C_RAM_O1", index), start + 74, 1); add_word_settings(stringf("CPE%d.C_RAM_O2", index), start + 75, 1); add_word_settings(stringf("CPE%d.C_L_D", index), start + 76, 1); add_word_settings(stringf("CPE%d.C_EN_SR", index), start + 77, 1); add_word_settings(stringf("CPE%d.C_CLKSEL", index), start + 78, 1); add_word_settings(stringf("CPE%d.C_ENSEL", index), start + 79, 1); } void TileBitDatabase::add_ff_init(int index, int start) { add_word_settings(stringf("CPE%d.FF_INIT", index), start, 2); } void TileBitDatabase::add_inmux(int index, int plane, int start) { add_word_settings(stringf("IM%d.P%02d", index, plane), start, 3); } void TileBitDatabase::add_outmux(int index, int plane, int start) { add_word_settings(stringf("OM%d.P%02d", index, plane), start, 2); } void TileBitDatabase::add_gpio(int start) { add_word_settings("GPIO.OPEN_DRAIN", start + 0, 1); add_word_settings("GPIO.SLEW", start + 1, 1); add_word_settings("GPIO.DRIVE", start + 2, 2); add_word_settings("GPIO.INPUT_ENABLE", start + 4, 1); add_word_settings("GPIO.PULLDOWN", start + 5, 1); add_word_settings("GPIO.PULLUP", start + 6, 1); add_word_settings("GPIO.SCHMITT_TRIGGER", start + 7, 1); add_word_settings("GPIO.OUT_SIGNAL", start + 8, 1); add_word_settings("GPIO.OUT1_4", start + 9, 1); add_word_settings("GPIO.OUT2_3", start + 10, 1); add_word_settings("GPIO.OUT23_14_SEL", start + 11, 1); add_word_settings("GPIO.USE_CFG_BIT", start + 12, 1); // Use bit 9 for clock, error in silicon add_word_settings("GPIO.USE_DDR", start + 13, 1); add_word_settings("GPIO.SEL_IN_CLOCK", start + 14, 1); // Use clock signals for IN CLK add_word_settings("GPIO.SEL_OUT_CLOCK", start + 15, 1); // Use clock signals for OUT CLK add_word_settings("GPIO.OE_ENABLE", start + 16, 1); add_word_settings("GPIO.OE_SIGNAL", start + 17, 2); // 0 is constant 1 // 19 unused add_word_settings("GPIO.OUT1_FF", start + 20, 1); add_word_settings("GPIO.OUT2_FF", start + 21, 1); add_word_settings("GPIO.IN1_FF", start + 22, 1); add_word_settings("GPIO.IN2_FF", start + 23, 1); add_word_settings("GPIO.OUT_CLOCK", start + 24, 2); add_word_settings("GPIO.INV_OUT1_CLOCK", start + 26, 1); add_word_settings("GPIO.INV_OUT2_CLOCK", start + 27, 1); add_word_settings("GPIO.IN_CLOCK", start + 28, 2); add_word_settings("GPIO.INV_IN1_CLOCK", start + 30, 1); add_word_settings("GPIO.INV_IN2_CLOCK", start + 31, 1); add_word_settings("GPIO.DELAY_OBF", start + 32, 16); add_word_settings("GPIO.DELAY_IBF", start + 48, 16); add_word_settings("GPIO.LVDS_EN", start + 64, 1); add_word_settings("GPIO.LVDS_BOOST", start + 65, 1); add_word_settings("GPIO.LVDS_IE", start + 66, 1); add_word_settings("GPIO.LVDS_RTERM", start + 67, 1); } void TileBitDatabase::add_edge_io(int index, int start) { for (int i = 0; i < 12; i++) add_word_settings(stringf("IOES%d.SB_IN_%02d", index, i + 1), start + i, 1); } void TileBitDatabase::add_right_edge(int index, int start) { add_word_settings(stringf("RES%d.SEL_MDIE1", index), start + 0, 1); add_word_settings(stringf("RES%d.SEL_MDIE2", index), start + 1, 1); add_word_settings(stringf("RES%d.SEL_MDIE3", index), start + 2, 1); add_word_settings(stringf("RES%d.SEL_MDIE4", index), start + 3, 1); add_word_settings(stringf("RES%d.SEL_MDIE5", index), start + 4, 1); add_word_settings(stringf("RES%d.SEL_MDIE6", index), start + 5, 1); add_word_settings(stringf("RES%d.SEL_MDIE7", index), start + 6, 1); add_word_settings(stringf("RES%d.SEL_MDIE8", index), start + 7, 1); add_word_settings(stringf("RES%d.SIG_SEL1", index), start + 8, 3); add_word_settings(stringf("RES%d.SIG_SEL2", index), start + 11, 3); add_word_settings(stringf("RES%d.SIG_SEL3", index), start + 14, 3); add_word_settings(stringf("RES%d.SIG_SEL4", index), start + 17, 3); } void TileBitDatabase::add_left_edge(int index, int start) { add_word_settings(stringf("LES%d.SB_Y3_SEL1", index), start + 0, 3); add_word_settings(stringf("LES%d.MDIE1_SEL1", index), start + 3, 3); add_word_settings(stringf("LES%d.CLOCK_SEL1", index), start + 6, 2); add_word_settings(stringf("LES%d.SB_Y3_SEL2", index), start + 8, 3); add_word_settings(stringf("LES%d.MDIE1_SEL2", index), start + 11, 3); add_word_settings(stringf("LES%d.CLOCK_SEL2", index), start + 14, 2); add_word_settings(stringf("LES%d.CINX_CONST", index), start + 16, 1); add_word_settings(stringf("LES%d.CINX_SEL", index), start + 17, 2); add_word_settings(stringf("LES%d.PINX_CONST", index), start + 19, 1); add_word_settings(stringf("LES%d.PINX_SEL", index), start + 20, 2); } void TileBitDatabase::add_top_edge(int index, int start) { add_word_settings(stringf("TES%d.SEL_MDIE1", index), start + 0, 1); add_word_settings(stringf("TES%d.SEL_MDIE2", index), start + 1, 1); add_word_settings(stringf("TES%d.SEL_MDIE3", index), start + 2, 1); add_word_settings(stringf("TES%d.SEL_MDIE4", index), start + 3, 1); add_word_settings(stringf("TES%d.SEL_MDIE5", index), start + 4, 1); add_word_settings(stringf("TES%d.SEL_MDIE6", index), start + 5, 1); add_word_settings(stringf("TES%d.SEL_MDIE7", index), start + 6, 1); add_word_settings(stringf("TES%d.SEL_MDIE8", index), start + 7, 1); add_word_settings(stringf("TES%d.SIG_SEL1", index), start + 8, 3); add_word_settings(stringf("TES%d.SIG_SEL2", index), start + 11, 3); add_word_settings(stringf("TES%d.SIG_SEL3", index), start + 14, 3); add_word_settings(stringf("TES%d.SIG_SEL4", index), start + 17, 3); } void TileBitDatabase::add_bottom_edge(int index, int start) { add_word_settings(stringf("BES%d.SB_Y4_SEL1", index), start + 0, 3); add_word_settings(stringf("BES%d.MDIE2_SEL1", index), start + 3, 3); add_word_settings(stringf("BES%d.CLOCK_SEL1", index), start + 6, 2); add_word_settings(stringf("BES%d.SB_Y4_SEL2", index), start + 8, 3); add_word_settings(stringf("BES%d.MDIE2_SEL2", index), start + 11, 3); add_word_settings(stringf("BES%d.CLOCK_SEL2", index), start + 14, 2); add_word_settings(stringf("BES%d.SB_Y4_SEL3", index), start + 16, 3); add_word_settings(stringf("BES%d.MDIE2_SEL3", index), start + 19, 3); add_word_settings(stringf("BES%d.CLOCK_SEL3", index), start + 22, 2); add_word_settings(stringf("BES%d.SB_Y4_SEL4", index), start + 24, 3); add_word_settings(stringf("BES%d.MDIE2_SEL4", index), start + 27, 3); add_word_settings(stringf("BES%d.CLOCK_SEL4", index), start + 30, 2); add_word_settings(stringf("BES%d.CINY1_CONST", index), start + 32, 1); add_word_settings(stringf("BES%d.CINY1_SEL", index), start + 33, 2); add_word_settings(stringf("BES%d.PINY1_CONST", index), start + 35, 1); add_word_settings(stringf("BES%d.PINY1_SEL", index), start + 36, 2); add_word_settings(stringf("BES%d.CINY2_CONST", index), start + 38, 1); add_word_settings(stringf("BES%d.CINY2_SEL", index), start + 39, 2); add_word_settings(stringf("BES%d.PINY2_CONST", index), start + 41, 1); add_word_settings(stringf("BES%d.PINY2_SEL", index), start + 42, 2); add_word_settings(stringf("BES%d.P_CINY1", index), start + 44, 1); add_word_settings(stringf("BES%d.P_PINY1", index), start + 45, 1); add_word_settings(stringf("BES%d.P_CINY2", index), start + 46, 1); add_word_settings(stringf("BES%d.P_PINY2", index), start + 47, 1); } TileBitDatabase::TileBitDatabase(const int x, const int y) : BaseBitDatabase(Die::LATCH_BLOCK_SIZE * 8) { bool is_core = false; if (y == 0) { add_bottom_edge(1, 13 * 8); add_bottom_edge(2, 19 * 8); } else if (x == 0) { add_left_edge(1, 13 * 8); add_left_edge(2, 16 * 8); } else if (y == 66 - 1) { add_top_edge(1, 13 * 8); add_top_edge(2, 16 * 8); } else if (x == 82 - 1) { add_right_edge(1, 13 * 8); add_right_edge(2, 16 * 8); } else { is_core = true; for (int i = 0; i < 4; i++) { add_cpe(i + 1, 10 * i * 8); add_ff_init(i + 1, (Die::LATCH_BLOCK_SIZE - 1) * 8 + i * 2); } int pos = 40; for (int i = 0; i < 4; i++) { for (int j = 0; j < 6; j++) { add_inmux(i + 1, j * 2 + 1, pos * 8); add_inmux(i + 1, j * 2 + 2, pos * 8 + 3); pos++; } } for (int i = 0; i < 2; i++) { pos = 54 + i * 6; for (int j = 9; j <= 12; j++) { add_outmux(i ? 4 : 1, j, pos * 8 + 6); pos++; } } } if (!is_core) { add_gpio(0); add_edge_io(1, 9 * 8); add_edge_io(2, 11 * 8); } int pos = 64; // All tiles have switch boxes // 64 SB_BIG plane 1 // 65 SB_BIG plane 1 // 66 SB_DRIVE plane 2,1 // 67 SB_BIG plane 2 // 68 SB_BIG plane 2 // repeated to cover all 12 planes for (int i = 0; i < 6; i++) { add_sb_big(i * 2 + 1, pos * 8); add_sb_drive(i * 2 + 1, (pos + 2) * 8); add_sb_drive(i * 2 + 2, (pos + 2) * 8 + 4); add_sb_big(i * 2 + 2, (pos + 3) * 8); pos += 5; } // 94 SB_SML plane 1 // 95 SB_SML plane 2,1 // 96 SB_SML plane 2 // repeated to cover all 12 planes for (int i = 0; i < 6; i++) { add_sb_sml(i * 2 + 1, pos * 8); add_sb_sml(i * 2 + 2, (pos + 1) * 8 + 4); pos += 3; } add_unknowns(); } SerdesBitDatabase::SerdesBitDatabase() : BaseBitDatabase(Die::SERDES_CFG_SIZE * 8) { add_word_settings("RX_BUF_RESET_TIME", (0x00 << 4) + 0, 5); add_word_settings("RX_PCS_RESET_TIME", (0x00 << 4) + 5, 5); add_word_settings("RX_RESET_TIMER_PRESC", (0x00 << 4) + 10, 5); add_word_settings("RX_RESET_DONE_GATE", (0x00 << 4) + 15, 1); add_word_settings("RX_CDR_RESET_TIME", (0x01 << 4) + 0, 5); add_word_settings("RX_EQA_RESET_TIME", (0x01 << 4) + 5, 5); add_word_settings("RX_PMA_RESET_TIME", (0x01 << 4) + 10, 5); add_word_settings("RX_WAIT_CDR_LOCK", (0x01 << 4) + 15, 1); add_word_settings("RX_CALIB_EN", (0x02 << 4) + 0, 1); add_word_settings("RX_CALIB_DONE", (0x02 << 4) + 1, 1); add_word_settings("RX_CALIB_OVR", (0x02 << 4) + 2, 1); add_word_settings("RX_CALIB_VAL", (0x02 << 4) + 3, 4); add_word_settings("RX_CALIB_CAL", (0x02 << 4) + 7, 4); add_word_settings("RX_RTERM_VCMSEL", (0x02 << 4) + 11, 3); add_word_settings("RX_RTERM_PD", (0x02 << 4) + 14, 1); add_word_settings("RX_EQA_CKP_LF", (0x03 << 4) + 0, 8); add_word_settings("RX_EQA_CKP_HF", (0x03 << 4) + 8, 8); add_word_settings("RX_EQA_CKP_OFFSET", (0x04 << 4) + 0, 8); add_word_settings("RX_EN_EQA", (0x04 << 4) + 8, 1); add_word_settings("RX_EQA_LOCK_CFG", (0x04 << 4) + 9, 4); add_word_settings("RX_EQA_LOCKED", (0x04 << 4) + 13, 1); add_word_settings("RX_TH_MON1", (0x05 << 4) + 0, 5); add_word_settings("RX_EN_EQA_EXT_VALUE_0", (0x05 << 4) + 5, 1); add_word_settings("RX_TH_MON2", (0x05 << 4) + 6, 5); add_word_settings("RX_EN_EQA_EXT_VALUE_1", (0x05 << 4) + 11, 1); add_word_settings("RX_TAPW", (0x06 << 4) + 0, 5); add_word_settings("RX_EN_EQA_EXT_VALUE_2", (0x06 << 4) + 5, 1); add_word_settings("RX_AFE_OFFSET", (0x06 << 4) + 6, 5); add_word_settings("RX_EN_EQA_EXT_VALUE_3", (0x06 << 4) + 11, 1); add_word_settings("RX_EQA_TAPW", (0x07 << 4) + 0, 5); add_word_settings("RX_TH_MON", (0x07 << 4) + 5, 5); add_word_settings("RX_OFFSET", (0x07 << 4) + 10, 4); add_word_settings("RX_EQA_CONFIG", (0x08 << 4) + 0, 16); add_word_settings("RX_AFE_PEAK", (0x09 << 4) + 0, 5); add_word_settings("RX_AFE_GAIN", (0x09 << 4) + 5, 4); add_word_settings("RX_AFE_VCMSEL", (0x09 << 4) + 9, 3); add_word_settings("RX_CDR_CKP", (0x0a << 4) + 0, 8); add_word_settings("RX_CDR_CKI", (0x0a << 4) + 8, 8); add_word_settings("RX_CDR_LOCK_CFG", (0x0b << 4) + 0, 8); add_word_settings("RX_CDR_TRANS_TH", (0x0b << 4) + 8, 7); add_word_settings("RX_CDR_LOCKED", (0x0b << 4) + 15, 1); add_word_settings("RX_CDR_FREQ_ACC_VAL", (0x0c << 4) + 0, 15); add_word_settings("RX_CDR_PHASE_ACC_VAL", (0x0d << 4) + 0, 16); add_word_settings("RX_CDR_FREQ_ACC", (0x0e << 4) + 0, 15); add_word_settings("RX_CDR_PHASE_ACC", (0x0f << 4) + 0, 16); add_word_settings("RX_CDR_SET_ACC_CONFIG", (0x10 << 4) + 0, 2); add_word_settings("RX_CDR_FORCE_LOCK", (0x10 << 4) + 2, 1); add_word_settings("RX_ALIGN_MCOMMA_VALUE", (0x11 << 4) + 0, 10); add_word_settings("RX_MCOMMA_ALIGN_OVR", (0x11 << 4) + 10, 1); add_word_settings("RX_MCOMMA_ALIGN", (0x11 << 4) + 11, 1); add_word_settings("RX_ALIGN_PCOMMA_VALUE", (0x12 << 4) + 0, 10); add_word_settings("RX_PCOMMA_ALIGN_OVR", (0x12 << 4) + 10, 1); add_word_settings("RX_PCOMMA_ALIGN", (0x12 << 4) + 11, 1); add_word_settings("RX_ALIGN_COMMA_WORD", (0x12 << 4) + 12, 2); add_word_settings("RX_ALIGN_COMMA_ENABLE", (0x13 << 4) + 0, 10); add_word_settings("RX_SLIDE_MODE", (0x13 << 4) + 10, 2); add_word_settings("RX_COMMA_DETECT_EN_OVR", (0x13 << 4) + 12, 1); add_word_settings("RX_COMMA_DETECT_EN", (0x13 << 4) + 13, 1); add_word_settings("RX_SLIDE", (0x13 << 4) + 14, 2); add_word_settings("RX_EYE_MEAS_EN", (0x14 << 4) + 0, 1); add_word_settings("RX_EYE_MEAS_CFG", (0x14 << 4) + 1, 15); add_word_settings("RX_MON_PH_OFFSET", (0x15 << 4) + 0, 6); add_word_settings("RX_EYE_MEAS_CORRECT_11S", (0x16 << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_WRONG_11S", (0x17 << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_CORRECT_00S", (0x18 << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_WRONG_00S", (0x19 << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_CORRECT_001S", (0x1a << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_WRONG_001S", (0x1b << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_CORRECT_110S", (0x1c << 4) + 0, 16); add_word_settings("RX_EYE_MEAS_WRONG_110S", (0x1d << 4) + 0, 16); add_word_settings("RX_EI_BIAS", (0x1e << 4) + 0, 4); add_word_settings("RX_EI_BW_SEL", (0x1e << 4) + 4, 4); add_word_settings("RX_EN_EI_DETECTOR_OVR", (0x1e << 4) + 8, 1); add_word_settings("RX_EN_EI_DETECTOR", (0x1e << 4) + 9, 1); add_word_settings("RX_EI_EN", (0x1e << 4) + 10, 1); add_word_settings("RX_PRBS_ERR_CNT", (0x1f << 4) + 0, 15); add_word_settings("RX_PRBS_LOCKED", (0x1f << 4) + 15, 1); add_word_settings("RX_DATA_SEL", (0x20 << 4) + 0, 1); add_word_settings("RX_DATA", (0x20 << 4) + 1, 15 + 16 * 4); add_word_settings("RX_BUF_BYPASS", (0x25 << 4) + 0, 1); add_word_settings("RX_CLKCOR_USE", (0x25 << 4) + 1, 1); add_word_settings("RX_CLKCOR_MIN_LAT", (0x25 << 4) + 2, 6); add_word_settings("RX_CLKCOR_MAX_LAT", (0x25 << 4) + 8, 6); add_word_settings("RX_CLKCOR_SEQ_1_0", (0x26 << 4) + 0, 10); add_word_settings("RX_CLKCOR_SEQ_1_1", (0x27 << 4) + 0, 10); add_word_settings("RX_CLKCOR_SEQ_1_2", (0x28 << 4) + 0, 10); add_word_settings("RX_CLKCOR_SEQ_1_3", (0x29 << 4) + 0, 10); add_word_settings("RX_PMA_LOOPBACK", (0x2a << 4) + 0, 1); add_word_settings("RX_PCS_LOOPBACK", (0x2a << 4) + 1, 1); add_word_settings("RX_DATAPATH_SEL", (0x2a << 4) + 2, 2); add_word_settings("RX_PRBS_OVR", (0x2a << 4) + 4, 1); add_word_settings("RX_PRBS_SEL", (0x2a << 4) + 5, 3); add_word_settings("RX_LOOPBACK_OVR", (0x2a << 4) + 8, 1); add_word_settings("RX_PRBS_CNT_RESET", (0x2a << 4) + 9, 1); add_word_settings("RX_POWER_DOWN_OVR", (0x2a << 4) + 10, 1); add_word_settings("RX_POWER_DOWN_N", (0x2a << 4) + 11, 1); add_word_settings("RX_PRESENT", (0x2a << 4) + 12, 1); add_word_settings("RX_DETECT_DONE", (0x2a << 4) + 13, 1); add_word_settings("RX_BUF_ERR", (0x2a << 4) + 14, 1); add_word_settings("RX_RESET_OVR", (0x2b << 4) + 0, 1); add_word_settings("RX_RESET", (0x2b << 4) + 1, 1); add_word_settings("RX_PMA_RESET_OVR", (0x2b << 4) + 2, 1); add_word_settings("RX_PMA_RESET", (0x2b << 4) + 3, 1); add_word_settings("RX_EQA_RESET_OVR", (0x2b << 4) + 4, 1); add_word_settings("RX_EQA_RESET", (0x2b << 4) + 5, 1); add_word_settings("RX_CDR_RESET_OVR", (0x2b << 4) + 6, 1); add_word_settings("RX_CDR_RESET", (0x2b << 4) + 7, 1); add_word_settings("RX_PCS_RESET_OVR", (0x2b << 4) + 8, 1); add_word_settings("RX_PCS_RESET", (0x2b << 4) + 9, 1); add_word_settings("RX_BUF_RESET_OVR", (0x2b << 4) + 10, 1); add_word_settings("RX_BUF_RESET", (0x2b << 4) + 11, 1); add_word_settings("RX_POLARITY_OVR", (0x2b << 4) + 12, 1); add_word_settings("RX_POLARITY", (0x2b << 4) + 13, 1); add_word_settings("RX_8B10B_EN_OVR", (0x2b << 4) + 14, 1); add_word_settings("RX_8B10B_EN", (0x2b << 4) + 15, 1); add_word_settings("RX_8B10B_BYPASS", (0x2c << 4) + 0, 8); add_word_settings("RX_BYTE_IS_ALIGNED", (0x2c << 4) + 8, 1); add_word_settings("RX_BYTE_REALIGN", (0x2c << 4) + 9, 1); add_word_settings("RX_RESET_DONE", (0x2c << 4) + 10, 1); add_word_settings("RX_DBG_EN", (0x2d << 4) + 0, 1); add_word_settings("RX_DBG_SEL", (0x2d << 4) + 1, 4); add_word_settings("RX_DBG_MODE", (0x2d << 4) + 5, 1); add_word_settings("RX_DBG_SRAM_DELAY", (0x2d << 4) + 6, 6); add_word_settings("RX_DBG_ADDR", (0x2e << 4) + 0, 10); add_word_settings("RX_DBG_RE", (0x2e << 4) + 10, 1); add_word_settings("RX_DBG_WE", (0x2e << 4) + 11, 1); add_word_settings("RX_DBG_DATA", (0x2e << 4) + 12, 20); add_word_settings("TX_SEL_PRE", (0x30 << 4) + 0, 5); add_word_settings("TX_SEL_POST", (0x30 << 4) + 5, 5); add_word_settings("TX_AMP", (0x30 << 4) + 10, 5); add_word_settings("TX_BRANCH_EN_PRE", (0x31 << 4) + 0, 5); add_word_settings("TX_BRANCH_EN_MAIN", (0x31 << 4) + 5, 6); add_word_settings("TX_BRANCH_EN_POST", (0x31 << 4) + 11, 5); add_word_settings("TX_TAIL_CASCODE", (0x32 << 4) + 0, 3); add_word_settings("TX_DC_ENABLE", (0x32 << 4) + 3, 7); add_word_settings("TX_DC_OFFSET", (0x32 << 4) + 10, 5); add_word_settings("TX_CM_RAISE", (0x33 << 4) + 0, 5); add_word_settings("TX_CM_THRESHOLD_0", (0x33 << 4) + 5, 5); add_word_settings("TX_CM_THRESHOLD_1", (0x33 << 4) + 10, 5); add_word_settings("TX_SEL_PRE_EI", (0x34 << 4) + 0, 5); add_word_settings("TX_SEL_POST_EI", (0x34 << 4) + 5, 5); add_word_settings("TX_AMP_EI", (0x34 << 4) + 10, 5); add_word_settings("TX_BRANCH_EN_PRE_EI", (0x35 << 4) + 0, 5); add_word_settings("TX_BRANCH_EN_MAIN_EI", (0x35 << 4) + 5, 6); add_word_settings("TX_BRANCH_EN_POST_EI", (0x35 << 4) + 11, 5); add_word_settings("TX_TAIL_CASCODE_EI", (0x36 << 4) + 0, 3); add_word_settings("TX_DC_ENABLE_EI", (0x36 << 4) + 3, 7); add_word_settings("TX_DC_OFFSET_EI", (0x36 << 4) + 10, 5); add_word_settings("TX_CM_RAISE_EI", (0x37 << 4) + 0, 5); add_word_settings("TX_CM_THRESHOLD_0_EI", (0x37 << 4) + 5, 5); add_word_settings("TX_CM_THRESHOLD_1_EI", (0x37 << 4) + 10, 5); add_word_settings("TX_SEL_PRE_RXDET", (0x38 << 4) + 0, 5); add_word_settings("TX_SEL_POST_RXDET", (0x38 << 4) + 5, 5); add_word_settings("TX_AMP_RXDET", (0x38 << 4) + 10, 5); add_word_settings("TX_BRANCH_EN_PRE_RXDET", (0x39 << 4) + 0, 5); add_word_settings("TX_BRANCH_EN_MAIN_RXDET", (0x39 << 4) + 5, 6); add_word_settings("TX_BRANCH_EN_POST_RXDET", (0x39 << 4) + 11, 5); add_word_settings("TX_TAIL_CASCODE_RXDET", (0x3a << 4) + 0, 3); add_word_settings("TX_DC_ENABLE_RXDET", (0x3a << 4) + 3, 7); add_word_settings("TX_DC_OFFSET_RXDET", (0x3a << 4) + 10, 5); add_word_settings("TX_CM_RAISE_RXDET", (0x3b << 4) + 0, 5); add_word_settings("TX_CM_THRESHOLD_0_RXDET", (0x3b << 4) + 5, 5); add_word_settings("TX_CM_THRESHOLD_1_RXDET", (0x3b << 4) + 10, 5); add_word_settings("TX_CALIB_EN", (0x3c << 4) + 0, 1); add_word_settings("TX_CALIB_DONE", (0x3c << 4) + 1, 1); add_word_settings("TX_CALIB_OVR", (0x3c << 4) + 2, 1); add_word_settings("TX_CALIB_VAL", (0x3c << 4) + 3, 4); add_word_settings("TX_CALIB_CAL", (0x3c << 4) + 7, 4); add_word_settings("TX_CM_REG_KI", (0x3d << 4) + 0, 8); add_word_settings("TX_CM_SAR_EN", (0x3d << 4) + 8, 1); add_word_settings("TX_CM_REG_EN", (0x3d << 4) + 9, 1); add_word_settings("TX_CM_SAR_RESULT_0", (0x3e << 4) + 0, 5); add_word_settings("TX_CM_SAR_RESULT_1", (0x3e << 4) + 5, 5); add_word_settings("TX_PMA_RESET_TIME", (0x3f << 4) + 0, 5); add_word_settings("TX_PCS_RESET_TIME", (0x3f << 4) + 5, 5); add_word_settings("TX_PCS_RESET_OVR", (0x3f << 4) + 10, 1); add_word_settings("TX_PCS_RESET", (0x3f << 4) + 11, 1); add_word_settings("TX_PMA_RESET_OVR", (0x3f << 4) + 12, 1); add_word_settings("TX_PMA_RESET", (0x3f << 4) + 13, 1); add_word_settings("TX_RESET_OVR", (0x3f << 4) + 14, 1); add_word_settings("TX_RESET", (0x3f << 4) + 15, 1); add_word_settings("TX_PMA_LOOPBACK", (0x40 << 4) + 0, 2); add_word_settings("TX_PCS_LOOPBACK", (0x40 << 4) + 2, 1); add_word_settings("TX_DATAPATH_SEL", (0x40 << 4) + 3, 2); add_word_settings("TX_PRBS_OVR", (0x40 << 4) + 5, 1); add_word_settings("TX_PRBS_SEL", (0x40 << 4) + 6, 3); add_word_settings("TX_PRBS_FORCE_ERR", (0x40 << 4) + 9, 1); add_word_settings("TX_LOOPBACK_OVR", (0x40 << 4) + 10, 1); add_word_settings("TX_POWER_DOWN_OVR", (0x40 << 4) + 11, 1); add_word_settings("TX_POWER_DOWN_N", (0x40 << 4) + 12, 1); add_word_settings("TX_ELEC_IDLE_OVR", (0x41 << 4) + 0, 1); add_word_settings("TX_ELEC_IDLE", (0x41 << 4) + 1, 1); add_word_settings("TX_DETECT_RX_OVR", (0x41 << 4) + 2, 1); add_word_settings("TX_DETECT_RX", (0x41 << 4) + 3, 1); add_word_settings("TX_POLARITY_OVR", (0x41 << 4) + 4, 1); add_word_settings("TX_POLARITY", (0x41 << 4) + 5, 1); add_word_settings("TX_8B10B_EN_OVR", (0x41 << 4) + 6, 1); add_word_settings("TX_8B10B_EN", (0x41 << 4) + 7, 1); add_word_settings("TX_DATA_OVR", (0x41 << 4) + 8, 1); add_word_settings("TX_DATA_CNT", (0x41 << 4) + 9, 3); add_word_settings("TX_DATA_VALID", (0x41 << 4) + 12, 1); add_word_settings("TX_BUF_ERR", (0x41 << 4) + 13, 1); add_word_settings("TX_RESET_DONE", (0x41 << 4) + 14, 1); add_word_settings("TX_DATA", (0x42 << 4) + 0, 16); add_word_settings("PLL_EN_ADPLL_CTRL", (0x50 << 4) + 0, 1); add_word_settings("PLL_CONFIG_SEL", (0x50 << 4) + 1, 1); add_word_settings("PLL_SET_OP_LOCK", (0x50 << 4) + 2, 1); add_word_settings("PLL_ENFORCE_LOCK", (0x50 << 4) + 3, 1); add_word_settings("PLL_DISABLE_LOCK", (0x50 << 4) + 4, 1); add_word_settings("PLL_LOCK_WINDOW", (0x50 << 4) + 5, 1); add_word_settings("PLL_FAST_LOCK", (0x50 << 4) + 6, 1); add_word_settings("PLL_SYNC_BYPASS", (0x50 << 4) + 7, 1); add_word_settings("PLL_PFD_SELECT", (0x50 << 4) + 8, 1); add_word_settings("PLL_REF_BYPASS", (0x50 << 4) + 9, 1); add_word_settings("PLL_REF_SEL", (0x50 << 4) + 10, 1); add_word_settings("PLL_REF_RTERM", (0x50 << 4) + 11, 1); add_word_settings("PLL_FCNTRL", (0x51 << 4) + 0, 6); add_word_settings("PLL_MAIN_DIVSEL", (0x51 << 4) + 6, 6); add_word_settings("PLL_OUT_DIVSEL", (0x51 << 4) + 12, 2); add_word_settings("PLL_CI", (0x52 << 4) + 0, 5); add_word_settings("PLL_CP", (0x52 << 4) + 5, 10); add_word_settings("PLL_AO", (0x53 << 4) + 0, 4); add_word_settings("PLL_SCAP", (0x53 << 4) + 4, 3); add_word_settings("PLL_FILTER_SHIFT", (0x53 << 4) + 7, 2); add_word_settings("PLL_SAR_LIMIT", (0x53 << 4) + 9, 3); add_word_settings("PLL_FT", (0x54 << 4) + 0, 11); add_word_settings("PLL_OPEN_LOOP", (0x54 << 4) + 11, 1); add_word_settings("PLL_SCAP_AUTO_CAL", (0x54 << 4) + 12, 1); add_word_settings("PLL_LOCKED", (0x55 << 4) + 0, 1); add_word_settings("PLL_CAP_FT_OF", (0x55 << 4) + 1, 1); add_word_settings("PLL_CAP_FT_UF", (0x55 << 4) + 2, 1); add_word_settings("PLL_CAP_FT", (0x55 << 4) + 3, 10); add_word_settings("PLL_CAP_STATE", (0x55 << 4) + 13, 2); add_word_settings("PLL_SYNC_VALUE", (0x56 << 4) + 0, 8); add_word_settings("PLL_BISC_MODE", (0x57 << 4) + 0, 3); add_word_settings("PLL_BISC_TIMER_MAX", (0x57 << 4) + 3, 4); add_word_settings("PLL_BISC_OPT_DET_IND", (0x57 << 4) + 7, 1); add_word_settings("PLL_BISC_PFD_SEL", (0x57 << 4) + 8, 1); add_word_settings("PLL_BISC_DLY_DIR", (0x57 << 4) + 9, 1); add_word_settings("PLL_BISC_COR_DLY", (0x57 << 4) + 10, 3); add_word_settings("PLL_BISC_CAL_SIGN", (0x57 << 4) + 13, 1); add_word_settings("PLL_BISC_CAL_AUTO", (0x57 << 4) + 14, 1); add_word_settings("PLL_BISC_CP_MIN", (0x58 << 4) + 0, 5); add_word_settings("PLL_BISC_CP_MAX", (0x58 << 4) + 5, 5); add_word_settings("PLL_BISC_CP_START", (0x58 << 4) + 10, 5); add_word_settings("PLL_BISC_DLY_PFD_MON_REF", (0x59 << 4) + 0, 5); add_word_settings("PLL_BISC_DLY_PFD_MON_DIV", (0x59 << 4) + 5, 5); add_word_settings("PLL_BISC_TIMER_DONE", (0x5a << 4) + 0, 1); add_word_settings("PLL_BISC_CP", (0x5a << 4) + 1, 7); add_word_settings("PLL_BISC_CO", (0x5b << 4) + 0, 16); add_word_settings("SERDES_ENABLE", (0x5c << 4) + 0, 1); add_word_settings("SERDES_AUTO_INIT", (0x5c << 4) + 1, 1); add_word_settings("SERDES_TESTMODE", (0x5c << 4) + 2, 1); } RamBitDatabase::RamBitDatabase() : BaseBitDatabase(Die::RAM_BLOCK_SIZE * 8) { add_word_settings("RAM_cfg_forward_a_addr", 0 * 8, 8); add_word_settings("RAM_cfg_forward_b_addr", 1 * 8, 8); add_word_settings("RAM_cfg_forward_a0_clk", 2 * 8, 8); add_word_settings("RAM_cfg_forward_a0_en", 3 * 8, 8); add_word_settings("RAM_cfg_forward_a0_we", 4 * 8, 8); add_word_settings("RAM_cfg_forward_a1_clk", 5 * 8, 8); add_word_settings("RAM_cfg_forward_a1_en", 6 * 8, 8); add_word_settings("RAM_cfg_forward_a1_we", 7 * 8, 8); add_word_settings("RAM_cfg_forward_b0_clk", 8 * 8, 8); add_word_settings("RAM_cfg_forward_b0_en", 9 * 8, 8); add_word_settings("RAM_cfg_forward_b0_we", 10 * 8, 8); add_word_settings("RAM_cfg_forward_b1_clk", 11 * 8, 8); add_word_settings("RAM_cfg_forward_b1_en", 12 * 8, 8); add_word_settings("RAM_cfg_forward_b1_we", 13 * 8, 8); add_word_settings("RAM_cfg_sram_mode", 14 * 8, 2); add_word_settings("RAM_cfg_input_config_a0", 14 * 8 + 2, 3); add_word_settings("RAM_cfg_input_config_a1", 14 * 8 + 5, 3); add_word_settings("RAM_cfg_input_config_b0", 15 * 8 + 1, 3); add_word_settings("RAM_cfg_input_config_b1", 15 * 8 + 4, 3); add_word_settings("RAM_cfg_output_config_a0", 15 * 8 + 7, 3); add_word_settings("RAM_cfg_output_config_a1", 16 * 8 + 2, 3); add_word_settings("RAM_cfg_output_config_b0", 16 * 8 + 5, 3); add_word_settings("RAM_cfg_output_config_b1", 17 * 8, 3); add_word_settings("RAM_cfg_a0_writemode", 18 * 8 + 0, 1); add_word_settings("RAM_cfg_a1_writemode", 18 * 8 + 1, 1); add_word_settings("RAM_cfg_b0_writemode", 18 * 8 + 2, 1); add_word_settings("RAM_cfg_b1_writemode", 18 * 8 + 3, 1); add_word_settings("RAM_cfg_a0_set_outputreg", 18 * 8 + 4, 1); add_word_settings("RAM_cfg_a1_set_outputreg", 18 * 8 + 5, 1); add_word_settings("RAM_cfg_b0_set_outputreg", 18 * 8 + 6, 1); add_word_settings("RAM_cfg_b1_set_outputreg", 18 * 8 + 7, 1); add_word_settings("RAM_cfg_inversion_a0", 19 * 8, 3); add_word_settings("RAM_cfg_inversion_a1", 19 * 8 + 3, 3); add_word_settings("RAM_cfg_inversion_b0", 19 * 8 + 6, 3); add_word_settings("RAM_cfg_inversion_b1", 20 * 8 + 1, 3); add_word_settings("RAM_cfg_ecc_enable", 20 * 8 + 4, 2); add_word_settings("RAM_cfg_dyn_stat_select", 20 * 8 + 6, 2); add_word_settings("RAM_cfg_almost_empty_offset", 21 * 8, 15); add_word_settings("RAM_cfg_fifo_sync_enable", 22 * 8 + 7, 1); add_word_settings("RAM_cfg_almost_full_offset", 23 * 8, 15); add_word_settings("RAM_cfg_fifo_async_enable", 24 * 8 + 7, 1); add_word_settings("RAM_cfg_sram_delay", 25 * 8, 6); add_word_settings("RAM_cfg_datbm_sel", 26 * 8, 4); add_word_settings("RAM_cfg_cascade_enable", 26 * 8 + 4, 2); add_unknowns(); } void ConfigBitDatabase::add_pll_cfg(int index, char cfg, int start) { add_word_settings(stringf("PLL%d.CFG_%c_CI_FILTER_CONST", index, cfg), start + 0, 5); add_word_settings(stringf("PLL%d.CFG_%c_CP_FILTER_CONST", index, cfg), start + 5, 5); add_word_settings(stringf("PLL%d.CFG_%c_N1", index, cfg), start + 10, 6); add_word_settings(stringf("PLL%d.CFG_%c_N2", index, cfg), start + 16, 10); add_word_settings(stringf("PLL%d.CFG_%c_M1", index, cfg), start + 26, 6); add_word_settings(stringf("PLL%d.CFG_%c_M2", index, cfg), start + 32, 10); add_word_settings(stringf("PLL%d.CFG_%c_K", index, cfg), start + 42, 12); add_word_settings(stringf("PLL%d.CFG_%c_FB_PATH", index, cfg), start + 54, 1); add_word_settings(stringf("PLL%d.CFG_%c_FINE_TUNE", index, cfg), start + 55, 11); add_word_settings(stringf("PLL%d.CFG_%c_COARSE_TUNE", index, cfg), start + 66, 3); add_word_settings(stringf("PLL%d.CFG_%c_AO_SW", index, cfg), start + 69, 5); add_word_settings(stringf("PLL%d.CFG_%c_OPEN_LOOP", index, cfg), start + 74, 1); add_word_settings(stringf("PLL%d.CFG_%c_ENFORCE_LOCK", index, cfg), start + 75, 1); add_word_settings(stringf("PLL%d.CFG_%c_PFD_SEL", index, cfg), start + 76, 1); add_word_settings(stringf("PLL%d.CFG_%c_LOCK_DETECT_WIN", index, cfg), start + 77, 1); add_word_settings(stringf("PLL%d.CFG_%c_SYNC_BYPASS", index, cfg), start + 78, 1); add_word_settings(stringf("PLL%d.CFG_%c_FILTER_SHIFT", index, cfg), start + 79, 2); add_word_settings(stringf("PLL%d.CFG_%c_FAST_LOCK", index, cfg), start + 81, 1); add_word_settings(stringf("PLL%d.CFG_%c_SAR_LIMIT", index, cfg), start + 82, 3); add_word_settings(stringf("PLL%d.CFG_%c_OP_LOCK", index, cfg), start + 85, 1); add_word_settings(stringf("PLL%d.CFG_%c_PDIV1_SEL", index, cfg), start + 86, 1); add_word_settings(stringf("PLL%d.CFG_%c_PDIV0_MUX", index, cfg), start + 87, 1); add_word_settings(stringf("PLL%d.CFG_%c_EN_COARSE_TUNE", index, cfg), start + 88, 1); add_word_settings(stringf("PLL%d.CFG_%c_EN_USR_CFG", index, cfg), start + 89, 1); add_word_settings(stringf("PLL%d.CFG_%c_PLL_EN_SEL", index, cfg), start + 90, 1); } ConfigBitDatabase::ConfigBitDatabase() : BaseBitDatabase(Die::DIE_CONFIG_SIZE * 8) { int pos = 0; for (int i = 0; i < 4; i++) { add_pll_cfg(i, 'A', pos); pos += 96; add_pll_cfg(i, 'B', pos); pos += 96; } // CLKIN matrix add_word_settings("CLKIN.REF0", pos + 0, 3); add_word_settings("CLKIN.REF0_INV", pos + 3, 1); add_word_settings("CLKIN.REF1", pos + 8, 3); add_word_settings("CLKIN.REF1_INV", pos + 8 + 3, 1); add_word_settings("CLKIN.REF2", pos + 16, 3); add_word_settings("CLKIN.REF2_INV", pos + 16 + 3, 1); add_word_settings("CLKIN.REF3", pos + 24, 3); add_word_settings("CLKIN.REF3_INV", pos + 24 + 3, 1); pos += 32; // GLBOUT matrix add_word_settings("GLBOUT.GLB0_CFG", pos + 0, 3); add_word_settings("GLBOUT.USR_GLB0_EN", pos + 3, 1); add_word_settings("GLBOUT.GLB0_EN", pos + 4, 1); // bits 5-7 not used add_word_settings("GLBOUT.FB0_CFG", pos + 8, 2); add_word_settings("GLBOUT.USR_FB0_EN", pos + 10, 1); // bits 11-15 not used add_word_settings("GLBOUT.GLB1_CFG", pos + 16, 3); add_word_settings("GLBOUT.USR_GLB1_EN", pos + 19, 1); add_word_settings("GLBOUT.GLB1_EN", pos + 20, 1); // bits 21-23 not used add_word_settings("GLBOUT.FB1_CFG", pos + 24, 2); add_word_settings("GLBOUT.USR_FB1_EN", pos + 26, 1); // bits 27-31 not used add_word_settings("GLBOUT.GLB2_CFG", pos + 32, 3); add_word_settings("GLBOUT.USR_GLB2_EN", pos + 35, 1); add_word_settings("GLBOUT.GLB2_EN", pos + 36, 1); // bits 37-39 not used add_word_settings("GLBOUT.FB2_CFG", pos + 40, 2); add_word_settings("GLBOUT.USR_FB2_EN", pos + 42, 1); // bits 43-47 not used add_word_settings("GLBOUT.GLB3_CFG", pos + 48, 3); add_word_settings("GLBOUT.USR_GLB3_EN", pos + 51, 1); add_word_settings("GLBOUT.GLB3_EN", pos + 52, 1); // bits 53-55 not used add_word_settings("GLBOUT.FB3_CFG", pos + 56, 2); add_word_settings("GLBOUT.USR_FB3_EN", pos + 58, 1); // bits 59-63 not used pos = Die::STATUS_CFG_START * 8; add_word_settings("GPIO.BANK_S1", pos + 16, 1); add_word_settings("GPIO.BANK_S2", pos + 17, 1); add_word_settings("GPIO.BANK_CFG", pos + 19, 1); add_word_settings("GPIO.BANK_E1", pos + 20, 1); add_word_settings("GPIO.BANK_E2", pos + 21, 1); add_word_settings("GPIO.BANK_N1", pos + 24, 1); add_word_settings("GPIO.BANK_N2", pos + 25, 1); add_word_settings("GPIO.BANK_W1", pos + 28, 1); add_word_settings("GPIO.BANK_W2", pos + 29, 1); pos += 32; for (int i = 0; i < Die::MAX_PLL; i++) { add_word_settings(stringf("PLL%d.PLL_RST", i), pos + 0, 1); add_word_settings(stringf("PLL%d.PLL_EN", i), pos + 1, 1); add_word_settings(stringf("PLL%d.PLL_AUTN", i), pos + 2, 1); add_word_settings(stringf("PLL%d.SET_SEL", i), pos + 3, 1); add_word_settings(stringf("PLL%d.USR_SET", i), pos + 4, 1); add_word_settings(stringf("PLL%d.USR_CLK_REF", i), pos + 5, 1); add_word_settings(stringf("PLL%d.CLK_OUT_EN", i), pos + 6, 1); add_word_settings(stringf("PLL%d.LOCK_REQ", i), pos + 7, 1); add_word_settings(stringf("PLL%d.AUTN_CT_I", i), pos + 8 + 0, 3); add_word_settings(stringf("PLL%d.CLK180_DOUB", i), pos + 8 + 3, 1); add_word_settings(stringf("PLL%d.CLK270_DOUB", i), pos + 8 + 4, 1); // bits 6 and 7 are unused add_word_settings(stringf("PLL%d.USR_CLK_OUT", i), pos + 8 + 7, 1); pos += 16; } add_word_settings("D2D.N", pos + 0, 1); add_word_settings("D2D.E", pos + 1, 1); add_word_settings("D2D.S", pos + 2, 1); add_word_settings("D2D.W", pos + 3, 1); add_unknowns(); } std::vector WordSettingBits::get_value(const std::vector &tile) const { std::vector val; for (int i = start; i < end; i++) val.push_back(tile[i]); return val; } void WordSettingBits::set_value(std::vector &tile, const std::vector &value) const { for (int i = start; i < end; i++) tile[i] = value[i - start]; } DatabaseConflictError::DatabaseConflictError(const std::string &desc) : runtime_error(desc) {} } // namespace GateMate prjpeppercorn-1.12/libgm/src/TileConfig.cpp000066400000000000000000000040371514752025000207430ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "TileConfig.hpp" #include #include #include "Util.hpp" namespace GateMate { std::ostream &operator<<(std::ostream &out, const ConfigWord &cw) { out << cw.name << " " << to_string(cw.value) << std::endl; return out; } std::istream &operator>>(std::istream &in, ConfigWord &cw) { in >> cw.name; in >> cw.value; return in; } std::ostream &operator<<(std::ostream &out, const TileConfig &tc) { for (const auto &cword : tc.cwords) out << cword; return out; } std::istream &operator>>(std::istream &in, TileConfig &tc) { tc.cwords.clear(); while (!skip_check_eor(in)) { ConfigWord w; in >> w; tc.cwords.push_back(w); } return in; } void TileConfig::add_word(const std::string &name, const std::vector &value) { cwords.push_back({name, value}); } std::string TileConfig::to_string() const { std::stringstream ss; ss << *this; return ss.str(); } TileConfig TileConfig::from_string(const std::string &str) { std::stringstream ss(str); TileConfig tc; ss >> tc; return tc; } bool TileConfig::empty() const { return cwords.empty(); } } // namespace GateMate prjpeppercorn-1.12/libgm/src/Util.cpp000066400000000000000000000034101514752025000176270ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "Util.hpp" #include #include namespace GateMate { VerbosityLevel verbosity = VerbosityLevel::DEBUG; std::string stringf(const char *fmt, ...) { std::string string; va_list ap; va_start(ap, fmt); string = vstringf(fmt, ap); va_end(ap); return string; } std::string vstringf(const char *fmt, va_list ap) { std::string string; char *str = NULL; #if defined(_WIN32) || defined(__CYGWIN__) int sz = 64 + strlen(fmt); while (1) { va_list apc; va_copy(apc, ap); str = (char *)realloc(str, sz); int rc = vsnprintf(str, sz, fmt, apc); va_end(apc); if (rc >= 0 && rc < sz) break; sz *= 2; } #else if (vasprintf(&str, fmt, ap) < 0) str = NULL; #endif if (str != NULL) { string = str; free(str); } return string; } } // namespace GateMate prjpeppercorn-1.12/libgm/tools/000077500000000000000000000000001514752025000165615ustar00rootroot00000000000000prjpeppercorn-1.12/libgm/tools/gmpack.cpp000066400000000000000000000113441514752025000205320ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include #include #include #include #include #include #include #include "Bitstream.hpp" #include "Chip.hpp" #include "ChipConfig.hpp" #include "version.hpp" int main(int argc, char *argv[]) { using namespace GateMate; namespace po = boost::program_options; po::options_description options("Allowed options"); options.add_options()("help,h", "show help"); options.add_options()("verbose,v", "verbose output"); options.add_options()("reset", "reset all configuration latches with CMD_CFGRST"); options.add_options()("crcmode", po::value(), "CRC error behaviour (check, ignore, unused)"); options.add_options()("spimode", po::value(), "SPI Mode to use (single, dual, quad)"); options.add_options()("reconfig", "enable reconfiguration in bitstream"); options.add_options()("background", "enable background reconfiguration in bitstream"); options.add_options()("bootaddr", po::value(), "boot address for secondary bitstream"); po::positional_options_description pos; options.add_options()("input", po::value()->required(), "input textual configuration"); pos.add("input", 1); options.add_options()("bit", po::value(), "output bitstream file"); pos.add("bit", 1); po::variables_map vm; try { po::parsed_options parsed = po::command_line_parser(argc, argv).options(options).positional(pos).run(); po::store(parsed, vm); po::notify(vm); } catch (po::required_option &e) { std::cerr << "Error: input file is mandatory." << std::endl << std::endl; goto help; } catch (std::exception &e) { std::cerr << "Error: " << e.what() << std::endl << std::endl; goto help; } if (vm.count("help")) { help: std::filesystem::path path(argv[0]); std::cerr << "Open Source Tools for GateMate FPGAs Version " << git_describe_str << std::endl; std::cerr << "Copyright (C) 2024 The Project Peppercorn Authors" << std::endl; std::cerr << std::endl; std::cerr << path.stem().c_str() << ": GateMate bitstream packer" << std::endl; std::cerr << std::endl; std::cerr << "Usage: " << argv[0] << " input.config [output.bit] [options]" << std::endl; std::cerr << std::endl; std::cerr << options << std::endl; return vm.count("help") ? 0 : 1; } std::ifstream config_file(vm["input"].as()); if (!config_file) { std::cerr << "Failed to open input file" << std::endl; return 1; } std::map bitopts; if (vm.count("reset")) { bitopts["reset"] = "yes"; } if (vm.count("crcmode")) { bitopts["crcmode"] = vm["crcmode"].as(); } if (vm.count("spimode")) { bitopts["spimode"] = vm["spimode"].as(); } if (vm.count("reconfig")) { bitopts["reconfig"] = "yes"; } if (vm.count("background")) { bitopts["background"] = "yes"; } if (vm.count("bootaddr")) { bitopts["bootaddr"] = std::to_string(vm["bootaddr"].as()); } std::string textcfg((std::istreambuf_iterator(config_file)), std::istreambuf_iterator()); ChipConfig cc; try { cc = ChipConfig::from_string(textcfg); } catch (std::runtime_error &e) { std::cerr << "Failed to process input config: " << e.what() << std::endl; return 1; } Chip c = cc.to_chip(); Bitstream b = Bitstream::serialise_chip(c, bitopts); if (vm.count("bit")) { std::ofstream bit_file(vm["bit"].as(), std::ios::binary); if (!bit_file) { std::cerr << "Failed to open output file" << std::endl; return 1; } b.write_bit(bit_file); } return 0; } prjpeppercorn-1.12/libgm/tools/gmunpack.cpp000066400000000000000000000071321514752025000210750ustar00rootroot00000000000000/* * prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools * * Copyright (C) 2024 The Project Peppercorn Authors. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include #include #include #include #include #include #include "Bitstream.hpp" #include "Chip.hpp" #include "ChipConfig.hpp" #include "version.hpp" int main(int argc, char *argv[]) { using namespace GateMate; namespace po = boost::program_options; po::options_description options("Allowed options"); options.add_options()("help,h", "show help"); options.add_options()("verbose,v", "verbose output"); po::positional_options_description pos; options.add_options()("input", po::value()->required(), "input bitstream file"); pos.add("input", 1); options.add_options()("textcfg", po::value()->required(), "output textual configuration"); pos.add("textcfg", 1); po::variables_map vm; try { po::parsed_options parsed = po::command_line_parser(argc, argv).options(options).positional(pos).run(); po::store(parsed, vm); po::notify(vm); } catch (po::required_option &e) { std::cerr << "Error: input file is mandatory." << std::endl << std::endl; goto help; } catch (std::exception &e) { std::cerr << "Error: " << e.what() << std::endl << std::endl; goto help; } if (vm.count("help")) { help: std::filesystem::path path(argv[0]); std::cerr << "Open Source Tools for GateMate FPGAs Version " << git_describe_str << std::endl; std::cerr << "Copyright (C) 2024 The Project Peppercorn Authors" << std::endl; std::cerr << std::endl; std::cerr << path.stem().c_str() << ": GateMate bitstream to text config converter" << std::endl; std::cerr << std::endl; std::cerr << "Usage: " << argv[0] << " input.bit [output.config] [options]" << std::endl; std::cerr << std::endl; std::cerr << options << std::endl; return vm.count("help") ? 0 : 1; } std::ifstream bit_file(vm["input"].as(), std::ios::binary); if (!bit_file) { std::cerr << "Failed to open input file" << std::endl; return 1; } try { Chip c = Bitstream::read(bit_file).deserialise_chip(); ChipConfig cc = ChipConfig::from_chip(c); std::ofstream out_file(vm["textcfg"].as()); if (!out_file) { std::cerr << "Failed to open output file" << std::endl; return 1; } out_file << cc.to_string(); return 0; } catch (BitstreamParseError &e) { std::cerr << "Failed to process input bitstream: " << e.what() << std::endl; return 1; } catch (std::runtime_error &e) { std::cerr << "Failed to process input bitstream: " << e.what() << std::endl; return 1; } } prjpeppercorn-1.12/libgm/tools/version.cpp.in000066400000000000000000000001251514752025000213550ustar00rootroot00000000000000#include "version.hpp" const std::string git_describe_str = "@CURRENT_GIT_VERSION@"; prjpeppercorn-1.12/libgm/tools/version.hpp000066400000000000000000000001501514752025000207530ustar00rootroot00000000000000#ifndef VERSION_H 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0) (effects (font (size 1 1) ) ) (uuid "0a02cf64-b982-440f-8346-b4d3eb411a30") ) (text "L00" (exclude_from_sim no) (at 30.48 77.724 0) (effects (font (size 1.27 1.27) ) ) (uuid "0f11b300-4d65-4122-9bd8-68b3c632301e") ) (text "MUX4b" (exclude_from_sim no) (at 43.18 137.16 0) (effects (font (size 1.27 1.27) ) ) (uuid "14318a55-a872-4a75-8dc6-dc0c58ae5c90") ) (text "C_PY1_I" (exclude_from_sim no) (at 368.3 174.244 0) (effects (font (size 1.27 1.27) ) ) (uuid "14a1f5f8-9860-45e4-931a-5730410465b1") ) (text "In multiplier mode,\nthe LUTs should be set up as:\nL10 = (A[1] & B[0]) ^ SI[1]\nL11 = (A[0] & B[0]) ^ SI[0]" (exclude_from_sim no) (at 57.15 159.004 0) (effects (font (size 1.27 1.27) ) ) (uuid "150332c5-ea70-4510-94cf-69a669adcc7d") ) (text "D LATCH" (exclude_from_sim no) (at 224.79 91.44 0) (effects (font (size 1.27 1.27) ) ) (uuid "16e8c2dd-0234-434e-b328-56fb082a5f62") ) (text "C_SN[0]" (exclude_from_sim no) (at 26.67 175.514 0) (effects (font (size 1 1) ) ) (uuid "17d31f77-cc32-43c8-9aca-dbe0be6c3a58") ) (text "C_SELY1" (exclude_from_sim no) (at 336.55 186.944 0) (effects (font (size 1 1) ) ) (uuid "194e341c-6ac6-4446-844e-dd92045b8f20") ) (text "C_I2" (exclude_from_sim no) (at 25.4 89.154 0) (effects (font (size 1.27 1.27) ) ) (uuid "1aad5126-7799-4d7b-babb-cda8ad3cfda9") ) (text "C = L10\nX = L11" (exclude_from_sim no) (at 30.48 64.262 0) (effects (font (size 1 1) ) ) (uuid "1b8a4096-7b5f-45d3-9674-5f6edeb3ab49") ) (text "C_FUNCTION=\n0: (none)\n1; \"C_ADDF\": C_ADDF, C_ADDCIN\n2; \"C_ADDF2\": C_ADDF, C_ADDF2, C_ADDCIN\n3; \"C_MULT\": C_MULT, C_ADDF, C_ADDF2, C_ADDCIN\n4; \"C_MX4\": C_MX4\n5; \"C_EN_CIN\": C_EN_CIN\n6; \"C_CONCAT\": C_ADDF\n7; \"C_ADDCIN\": C_ADDCIN" (exclude_from_sim no) (at 47.752 36.83 0) (effects (font (size 1.27 1.27) ) (justify left) ) (uuid "1fa9241d-d7f0-4e8c-a209-30223160859e") ) (text "C_2D_IN" (exclude_from_sim no) (at 177.8 132.334 0) (effects (font (size 1 1) ) ) (uuid "1fc4ea99-595c-4f8b-905a-0feec334a802") ) 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(at 179.07 82.804 0) (effects (font (size 1 1) ) ) (uuid "65d82ff9-10eb-4ad3-8c76-e7a21b77fcad") ) (text "Because of the inverted D input,\nthe SET/RST signals go to the\nR/S ports of the flops and\nlatches respectively." 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98.806 193.294 0) (effects (font (size 1.27 1.27) ) ) (uuid "986a1e47-cd84-4e16-8f61-5149c6eec5fb") ) (text "SYMBOL LEGEND" (exclude_from_sim no) (at 231.14 185.674 0) (effects (font (size 1.27 1.27) ) ) (uuid "98e06da0-1198-4619-b017-7033f8353935") ) (text "C_COMP_I" (exclude_from_sim no) (at 373.38 162.814 0) (effects (font (size 1.27 1.27) ) ) (uuid "99b6407b-9ac3-4df4-a0b8-a55f742917eb") ) (text "C_EN" (exclude_from_sim no) (at 25.4 193.802 0) (effects (font (size 1.27 1.27) ) ) (uuid "9dd9812e-0a28-49d9-993a-ee75d4d4d968") ) (text "C_SELY1" (exclude_from_sim no) (at 336.55 100.584 0) (effects (font (size 1 1) ) ) (uuid "9e191ea6-8cc1-494d-939d-c9ef1de022e7") ) (text "C_R" (exclude_from_sim no) (at 25.4 183.388 0) (effects (font (size 1.27 1.27) ) ) (uuid "9ea31464-1e10-4ed2-bef5-85fc0a115774") ) (text "L03" (exclude_from_sim no) (at 30.48 115.824 0) (effects (font (size 1.27 1.27) ) ) (uuid "a1e000ca-4487-4b55-b99b-6032c298f5c9") ) (text "C_EN_SR" (exclude_from_sim no) (at 172.72 96.774 0) (effects (font (size 1.27 1.27) ) ) (uuid "a26bc271-1d34-4b2b-a291-9020f6891c8f") ) (text "C_RAMI1" (exclude_from_sim no) (at 302.006 108.204 0) (effects (font (size 1.27 1.27) ) ) (uuid "a509d996-b2ec-4715-997c-79132afbc777") ) (text "PROPAGATE" (exclude_from_sim no) (at 140.97 77.978 0) (effects (font (size 1.27 1.27) ) ) (uuid "a68854e0-59ad-4d4a-a901-0ac76e1749e1") ) (text "D FLIP FLOP" (exclude_from_sim no) (at 224.79 106.68 0) (effects (font (size 1.27 1.27) ) ) (uuid "a720b461-0483-4226-badf-e4cbb9c35f99") ) (text "C_SEL_P" (exclude_from_sim no) (at 336.55 184.404 0) (effects (font (size 1 1) ) ) (uuid "ad956325-12b2-4c37-af2f-49bb93bc8220") ) (text "SEQUENTIAL LOGIC" (exclude_from_sim no) (at 299.72 151.384 0) (effects (font (size 1.27 1.27) ) ) (uuid "aed34ca7-becd-4272-9df7-1c090e99ee33") ) (text "C_SEL_P" (exclude_from_sim no) (at 336.55 203.454 0) (effects (font (size 1 1) ) ) (uuid "b00bd420-c46e-4640-b960-947c66689548") ) (text "C_L_D" (exclude_from_sim no) (at 241.3 138.684 0) (effects (font (size 1.27 1.27) ) ) (uuid "b31231dd-d6f0-470b-af2a-c3bf8d7e8f33") ) (text "L10" (exclude_from_sim no) (at 63.5 89.154 0) (effects (font (size 1.27 1.27) ) ) (uuid "b404cdd8-9b3e-4c26-933c-a9583cd38d13") ) (text "MUX4a" (exclude_from_sim no) (at 48.26 61.214 0) (effects (font (size 1.27 1.27) ) ) (uuid "ba55d24b-a8d1-48b4-8402-8b169cace1cd") ) (text "C_SEL_C" (exclude_from_sim no) (at 336.55 117.094 0) (effects (font (size 1 1) ) ) (uuid "bb971507-bb9d-48d2-82ee-284fdff3ff57") ) (text "C_I4" (exclude_from_sim no) (at 25.4 114.554 0) (effects (font (size 1.27 1.27) ) ) (uuid "bf6efa09-22bc-4118-9823-973d264ee7b0") ) (text "C_RAM_O2" (exclude_from_sim no) (at 287.02 147.574 0) (effects (font (size 1.27 1.27) ) ) (uuid "c1cb4017-a053-4b6f-9f08-4415ac31fdbb") ) (text "GENERATE" (exclude_from_sim no) (at 141.986 114.554 0) (effects (font (size 1.27 1.27) ) ) (uuid "c20f2d8d-2bd7-4250-aaed-2869f565373a") ) (text "L11" (exclude_from_sim no) (at 63.5 104.394 0) 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0] /Dest [1000 0 R /FitB] >> endobj 3562 0 obj << /Type /Annot /Subtype /Link /Rect [80.8435 713.601 105.264 718.191] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3563 0 obj << /Type /Annot /Subtype /Link /Rect [113.373 778.401 137.793 782.991] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3564 0 obj << /Type /Annot /Subtype /Link /Rect [113.373 771.201 137.793 775.791] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3565 0 obj << /Type /Annot /Subtype /Link /Rect [80.8435 692.001 105.264 696.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3566 0 obj << /Type /Annot /Subtype /Link /Rect [185.244 512.001 209.664 516.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3567 0 obj << /Type /Annot /Subtype /Link /Rect [185.244 584.001 209.664 588.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3568 0 obj << /Type /Annot /Subtype /Link /Rect [185.244 497.601 209.664 502.191] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3569 0 obj << /Type /Annot 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0] /Dest [1000 0 R /FitB] >> endobj 3977 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 465.201 287.899 469.791] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3978 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 503.001 287.899 507.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3979 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 450.801 287.899 455.391] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3980 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 472.401 287.899 476.991] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3981 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 413.001 287.899 417.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3982 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 319.401 287.899 323.991] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3983 0 obj << /Type /Annot /Subtype /Link /Rect [254.736 341.001 287.899 345.591] /Border [16 16 0] /Dest [1000 0 R /FitB] >> endobj 3984 0 obj << /Type /Annot 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451.84 228.223 458.533] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 549 0 obj << /Type /Annot /Subtype /Link /Rect [327.15 1067.44 361.423 1074.13] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 550 0 obj << /Type /Annot /Subtype /Link /Rect [193.95 480.64 228.223 487.333] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 551 0 obj << /Type /Annot /Subtype /Link /Rect [193.95 466.24 228.223 472.933] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 552 0 obj << /Type /Annot /Subtype /Link /Rect [975.15 1067.44 1009.42 1074.13] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved 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/JavaScript /JS (ShM\([ ["Net = /CPE22.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 576 0 obj << /Type /Annot /Subtype /Link /Rect [327.15 743.44 361.423 750.133] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 577 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 1467.04 1200.22 1473.73] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 578 0 obj << /Type /Annot /Subtype /Link /Rect [327.15 1391.44 361.423 1398.13] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 579 0 obj << /Type /Annot /Subtype /Link /Rect [1299.15 743.44 1333.42 750.133] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 580 0 obj << /Type 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["Resolved netclass = Default"], ]\);) >> >> endobj 603 0 obj << /Type /Annot /Subtype /Link /Rect [517.95 804.64 552.223 811.333] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 604 0 obj << /Type /Annot /Subtype /Link /Rect [517.95 819.04 552.223 825.733] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 605 0 obj << /Type /Annot /Subtype /Link /Rect [517.95 826.24 552.223 832.933] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 606 0 obj << /Type /Annot /Subtype /Link /Rect [975.15 1391.44 1009.42 1398.13] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 607 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 775.84 1200.22 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>> >> endobj 621 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 1438.24 1200.22 1444.93] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 622 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 1452.64 1200.22 1459.33] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 623 0 obj << /Type /Annot /Subtype /Link /Rect [975.15 1384.24 1009.42 1390.93] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 624 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 1431.04 1200.22 1437.73] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 625 0 obj << /Type /Annot /Subtype /Link /Rect [841.95 1107.04 876.223 1113.73] /Border [16 16 0] /A << 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630 0 obj << /Type /Annot /Subtype /Link /Rect [1165.95 1445.44 1200.22 1452.13] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 631 0 obj << /Type /Annot /Subtype /Link /Rect [416.088 411.48 530.712 414.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer1/P01.D1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 632 0 obj << /Type /Annot /Subtype /Link /Rect [747.288 343.08 750.312 421.704] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Big Switch Box/Y1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 633 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 472.68 231.912 475.704] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 634 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 501.48 231.912 504.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 635 0 obj << /Type /Annot /Subtype /Link /Rect [106.488 404.28 206.712 407.304] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 636 0 obj << /Type /Annot /Subtype /Link /Rect [106.488 1052.28 206.712 1055.3] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Big Switch Box3/Y3"], ["Resolved netclass = Default"], ]\);) >> >> endobj 637 0 obj << /Type /Annot /Subtype /Link /Rect [99.288 418.68 206.712 421.704] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 638 0 obj << /Type /Annot /Subtype /Link /Rect [92.088 411.48 206.712 414.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 639 0 obj << /Type /Annot /Subtype /Link /Rect [99.288 991.08 102.312 1069.7] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer4/P01.D0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 640 0 obj << /Type /Annot /Subtype /Link /Rect [416.088 411.48 419.112 738.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer1/P01.D1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 641 0 obj << /Type /Annot /Subtype /Link /Rect [416.088 1059.48 419.112 1386.5] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer5/P01.D1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 642 0 obj << /Type /Annot /Subtype /Link /Rect [92.088 501.48 95.1123 630.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 643 0 obj << /Type /Annot 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/Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 648 0 obj << /Type /Annot /Subtype /Link /Rect [214.488 1250.28 426.312 1253.3] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer12/P01.D0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 649 0 obj << /Type /Annot /Subtype /Link /Rect [135.288 1279.08 138.312 1310.9] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer6/P01.D1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 650 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 451.08 231.912 454.104] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 651 0 obj << /Type /Annot /Subtype /Link /Rect [318.888 411.48 368.712 414.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = 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188.712 972.504] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D3"], ["Resolved netclass = Default"], ]\);) >> >> endobj 657 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 458.28 231.912 461.304] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 658 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 991.08 102.312 994.104] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer4/P01.D0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 659 0 obj << /Type /Annot /Subtype /Link /Rect [84.888 976.68 87.9123 1202.9] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Small Switch Box1/Y3"], ["Resolved netclass = Default"], ]\);) >> >> endobj 660 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 976.68 87.9123 979.704] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ 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/JavaScript /JS (ShM\([ ["Net = /CPE11/CADD_S"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1274 0 obj << /Type /Annot /Subtype /Link /Rect [1057.95 625.144 1079.19 631.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/CADD_A"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1275 0 obj << /Type /Annot /Subtype /Link /Rect [1029.15 661.144 1050.57 667.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MULT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1276 0 obj << /Type /Annot /Subtype /Link /Rect [60.7499 373.144 73.7663 379.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/CI_0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1277 0 obj << /Type /Annot /Subtype /Link /Rect [215.55 625.144 226.852 631.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L10"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1278 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 286.744 968.795 293.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1279 0 obj << /Type /Annot /Subtype /Link /Rect [74.5194 499.144 101.25 505.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_EN_CIN"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1280 0 obj << /Type /Annot /Subtype /Link /Rect [755.55 427.144 785.881 433.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMB2OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1281 0 obj << /Type /Annot /Subtype /Link /Rect [215.55 617.944 226.852 624.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L11"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1282 0 obj << /Type /Annot /Subtype /Link /Rect [240.75 481.144 251.366 487.837] /Border [16 16 0] /A << /Type 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endobj 1287 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 301.144 954.395 307.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1288 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 293.944 954.395 300.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1289 0 obj << /Type /Annot /Subtype /Link /Rect [1032.75 254.344 1054.17 261.037] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MULT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1290 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 232.744 968.795 239.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1291 0 obj << /Type /Annot /Subtype /Link /Rect [1029.15 416.344 1050.57 423.037] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MULT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1292 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 383.944 954.395 390.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1293 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 369.544 968.795 376.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1294 0 obj << /Type /Annot /Subtype /Link /Rect [570.059 510.246 576.752 521.205] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/SET"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1295 0 obj << /Type /Annot /Subtype /Link /Rect [226.35 589.144 245.195 595.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MX4"], ["Resolved netclass = Default"], ]\);) >> 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0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1310 0 obj << /Type /Annot /Subtype /Link /Rect [392.862 383.944 414.45 390.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COY2_S"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1311 0 obj << /Type /Annot /Subtype /Link /Rect [255.15 646.744 279.823 653.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_ADDF2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1312 0 obj << /Type /Annot /Subtype /Link /Rect [215.55 643.144 226.852 649.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L10"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1313 0 obj << /Type /Annot /Subtype /Link /Rect [392.177 369.544 414.45 376.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/MULTO2"], ["Resolved netclass = Default"], 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/Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1319 0 obj << /Type /Annot /Subtype /Link /Rect [102.805 715.144 130.05 721.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_ADDCIN"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1320 0 obj << /Type /Annot /Subtype /Link /Rect [393.034 409.144 414.45 415.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COY2_a"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1321 0 obj << /Type /Annot /Subtype /Link /Rect [291.15 430.744 302.452 437.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L10"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1322 0 obj << /Type /Annot /Subtype /Link /Rect [233.55 387.544 244.852 394.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L11"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1323 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 491.944 954.395 498.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1324 0 obj << /Type /Annot /Subtype /Link /Rect [1057.95 358.744 1080.22 365.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/MULTO1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1325 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 484.744 954.395 491.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1326 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 538.744 954.395 545.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1327 0 obj << /Type /Annot /Subtype /Link /Rect [111.205 743.944 130.05 750.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MX4"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1328 0 obj << /Type /Annot /Subtype /Link /Rect [103.319 736.744 130.05 743.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_EN_CIN"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1329 0 obj << /Type /Annot /Subtype /Link /Rect [1011.15 527.944 1032.39 534.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/CADD_A"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1330 0 obj << /Type /Annot /Subtype /Link /Rect [105.377 722.344 130.05 729.037] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_ADDF2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1331 0 obj << /Type /Annot /Subtype /Link /Rect [939.15 477.544 968.795 484.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1332 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 509.944 154.852 516.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L01"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1333 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 517.144 154.852 523.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L00"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1334 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 524.344 154.852 531.037] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L02"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1335 0 obj << /Type /Annot /Subtype /Link /Rect [60.7499 473.944 79.5946 480.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MX4"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1336 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 488.344 154.166 495.037] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/CIN"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1337 0 obj << /Type /Annot /Subtype /Link /Rect [755.55 441.544 778.681 448.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/MUXOUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1338 0 obj << /Type /Annot /Subtype /Link /Rect [1025.55 499.144 1047.14 505.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COY2_S"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1339 0 obj << /Type /Annot /Subtype /Link /Rect [1025.55 491.944 1046.97 498.637] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/C_MULT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1340 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 495.544 154.852 502.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L02"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1341 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 531.544 154.852 538.237] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L01"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1342 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 538.744 154.852 545.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L00"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1343 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 502.744 154.852 509.437] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L02"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1344 0 obj << /Type /Annot /Subtype /Link /Rect [143.55 481.144 154.166 487.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/CIN"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1345 0 obj << /Type /Annot /Subtype /Link /Rect [391.319 193.144 414.45 199.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/MUXOUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1346 0 obj << /Type /Annot /Subtype /Link /Rect [138.059 575.444 144.752 586.746] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L03"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1347 0 obj << /Type /Annot /Subtype /Link /Rect [1029.15 337.144 1058.79 343.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/COMP_OUT"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1348 0 obj << /Type /Annot /Subtype /Link /Rect [130.859 575.444 137.552 586.746] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/L02"], ["Resolved netclass = Default"], ]\);) >> >> endobj 1349 0 obj << /Type /Annot /Subtype /Link /Rect [755.55 535.144 778.681 541.837] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11/MUXOUT"], ["Resolved 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Default"], ]\);) >> >> endobj 3658 0 obj << /Type /Annot /Subtype /Link /Rect [52.488 404.784 55.5123 731.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P09.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3659 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 671.184 174.312 699.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P09.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3660 0 obj << /Type /Annot /Subtype /Link /Rect [59.688 397.584 62.7123 609.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3661 0 obj << /Type /Annot /Subtype /Link /Rect [66.888 534.384 69.9123 681.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3662 0 obj << /Type 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332.712 256.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P12.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3667 0 obj << /Type /Annot /Subtype /Link /Rect [264.888 285.984 282.312 289.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P08.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3668 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 267.984 181.512 321.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P04.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3669 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 476.784 210.312 479.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P07.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3670 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 696.384 174.312 731.808] /Border [16 16 0] /A << /Type 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obj << /Type /Annot /Subtype /Link /Rect [214.488 318.384 224.712 328.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P08.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3684 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 728.784 217.512 731.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P01.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3685 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 357.984 332.712 361.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P04.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3686 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 390.384 332.712 393.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3687 0 obj << /Type /Annot /Subtype /Link /Rect [52.488 260.784 55.5123 407.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P09.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3688 0 obj << /Type /Annot /Subtype /Link /Rect [59.688 267.984 105.912 271.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3689 0 obj << /Type /Annot /Subtype /Link /Rect [52.488 260.784 105.912 263.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P09.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3690 0 obj << /Type /Annot /Subtype /Link /Rect [59.688 267.984 62.7123 400.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3691 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 397.584 210.312 400.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3692 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 397.584 174.312 425.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3693 0 obj << /Type /Annot /Subtype /Link /Rect [264.888 357.984 282.312 361.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P04.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3694 0 obj << /Type /Annot /Subtype /Link /Rect [221.688 325.584 282.312 328.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P04.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3695 0 obj << /Type /Annot /Subtype /Link /Rect [264.888 422.784 282.312 425.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = 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462.384 217.512 465.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P07.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3709 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 462.384 181.512 479.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P07.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3710 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 462.384 282.312 497.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P03.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3711 0 obj << /Type /Annot /Subtype /Link /Rect [74.088 541.584 105.912 544.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P12.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3712 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 494.784 332.712 497.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P03.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3713 0 obj << /Type /Annot /Subtype /Link /Rect [214.488 455.184 224.712 465.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P07.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3714 0 obj << /Type /Annot /Subtype /Link /Rect [160.488 285.984 174.312 289.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P12.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3715 0 obj << /Type /Annot /Subtype /Link /Rect [74.088 332.784 174.312 335.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P12.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3716 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 325.584 282.312 361.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = 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= Default"], ]\);) >> >> endobj 3721 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 599.184 282.312 634.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P02.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3722 0 obj << /Type /Annot /Subtype /Link /Rect [66.888 469.584 174.312 472.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3723 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 678.384 210.312 681.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P01.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3724 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 613.584 210.312 616.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P06.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3725 0 obj << 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599.184 217.512 602.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P06.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3730 0 obj << /Type /Annot /Subtype /Link /Rect [178.488 599.184 181.512 616.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P06.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3731 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 559.584 174.312 609.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3732 0 obj << /Type /Annot /Subtype /Link /Rect [66.888 469.584 69.9123 537.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3733 0 obj << /Type /Annot /Subtype /Link /Rect [264.888 631.584 282.312 634.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P02.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3734 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 663.984 332.712 667.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P09.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3735 0 obj << /Type /Annot /Subtype /Link /Rect [66.888 534.384 105.912 537.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P11.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3736 0 obj << /Type /Annot /Subtype /Link /Rect [279.288 559.584 282.312 595.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P06.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3737 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 332.784 210.312 335.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = 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Default"], ]\);) >> >> endobj 3742 0 obj << /Type /Annot /Subtype /Link /Rect [135.288 746.784 152.712 749.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D5"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3743 0 obj << /Type /Annot /Subtype /Link /Rect [146.088 753.984 149.112 767.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/P01.D4"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3744 0 obj << /Type /Annot /Subtype /Link /Rect [214.488 591.984 224.712 602.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P02.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3745 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 527.184 332.712 530.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3746 0 obj << /Type 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332.712 699.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P05.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3751 0 obj << /Type /Annot /Subtype /Link /Rect [171.288 527.184 174.312 537.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P10.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3752 0 obj << /Type /Annot /Subtype /Link /Rect [221.688 591.984 282.312 595.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Input Multiplexer/IM.P06.Y"], ["Resolved netclass = Default"], ]\);) >> >> endobj 3995 0 obj << /Type /Annot /Subtype /Link /Rect [200.52 490.896 231.48 526.192] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Reference = M14"], ["Value = ~"], ]\);) >> >> endobj 3996 0 obj << /Type /Annot /Subtype /Link /Rect [229.32 538.056 253.08 551.392] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ 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134.712 384.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4016 0 obj << /Type /Annot /Subtype /Link /Rect [131.688 381.384 134.712 420.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4017 0 obj << /Type /Annot /Subtype /Link /Rect [124.488 388.584 127.512 427.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4018 0 obj << /Type /Annot /Subtype /Link /Rect [138.888 374.184 141.912 413.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4019 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 341.784 127.512 344.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT1"], 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0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4029 0 obj << /Type /Annot /Subtype /Link /Rect [124.488 514.584 127.512 553.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4030 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 465.984 134.712 469.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4031 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 473.184 127.512 476.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4032 0 obj << /Type /Annot /Subtype /Link /Rect [70.488 451.584 149.112 454.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> 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<< /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4038 0 obj << /Type /Annot /Subtype /Link /Rect [131.688 543.384 203.112 546.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4039 0 obj << /Type /Annot /Subtype /Link /Rect [138.888 536.184 203.112 539.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4040 0 obj << /Type /Annot /Subtype /Link /Rect [146.088 492.984 149.112 532.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4041 0 obj << /Type /Annot /Subtype /Link /Rect [124.488 550.584 203.112 553.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4042 0 obj << /Type /Annot /Subtype /Link /Rect [131.688 334.584 257.112 337.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4043 0 obj << /Type /Annot /Subtype /Link /Rect [138.888 500.184 141.912 539.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4044 0 obj << /Type /Annot /Subtype /Link /Rect [138.888 500.184 203.112 503.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE21.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4045 0 obj << /Type /Annot /Subtype /Link /Rect [146.088 492.984 203.112 496.008] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE22.OUT1"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4046 0 obj << /Type /Annot /Subtype /Link /Rect [131.688 507.384 134.712 546.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4047 0 obj << /Type /Annot /Subtype /Link /Rect [250.488 539.784 257.112 542.808] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /Output Multiplexer \\u00281,1\\u0029/SB.P11.D0"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4048 0 obj << /Type /Annot /Subtype /Link /Rect [124.488 473.184 257.112 476.208] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4049 0 obj << /Type /Annot /Subtype /Link /Rect [131.688 465.984 134.712 510.408] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE12.OUT2"], ["Resolved netclass = Default"], ]\);) >> >> endobj 4050 0 obj << /Type /Annot /Subtype /Link /Rect [124.488 473.184 127.512 517.608] /Border [16 16 0] /A << /Type /Action /S /JavaScript /JS (ShM\([ ["Net = /CPE11.OUT2"], ["Resolved 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prjpeppercorn-1.12/schematics/cpe/sym-lib-table000077500000000000000000000002131514752025000216040ustar00rootroot00000000000000(sym_lib_table (version 7) (lib (name "peppercorn")(type "KiCad")(uri "${KIPRJMOD}/peppercorn.kicad_sym")(options "")(descr "")) ) prjpeppercorn-1.12/tools/000077500000000000000000000000001514752025000154675ustar00rootroot00000000000000prjpeppercorn-1.12/tools/__init__.py000066400000000000000000000000001514752025000175660ustar00rootroot00000000000000prjpeppercorn-1.12/tools/extract_constids.py000066400000000000000000000041131514752025000214200ustar00rootroot00000000000000import argparse import sys import os import die consts = set() parser = argparse.ArgumentParser(description=__doc__) parser.add_argument('-yosys', dest='yosys', type=str, help="Yosys share directory", default="/usr/local/share/yosys") parser.add_argument('-o', '--outfile', dest='outfile', type=argparse.FileType('w'), help="output HTML file") def export_name(name,fout): if name not in consts and "[" not in name: print(f"X({name})", file=fout) consts.add(name) else: print(f"//X({name})", file=fout) def parse_line(item,fout): line = item.strip().split() if len(line)==0: return if line[0] == "module": name = line[1].split("(")[0] print(f"// primitive {name}", file=fout) export_name(name, fout) elif line[0] == "parameter": name = line[1] if name.startswith("["): name = line[2] export_name(name, fout) elif line[0] in ["input", "output" ,"inout"]: items = " ".join(line[1:]).strip().split(",") for it in items: if "=" in it: it = it[:it.find("=")].strip() name = it.split(" ")[-1].strip() if len(name)>0: export_name(name, fout) elif line[0].startswith("endmodule"): print(file=fout) def main(argv): args = parser.parse_args(argv[1:]) fout = args.outfile print("// autogenerated items", file=fout) with open(os.path.join(args.yosys, "gatemate", "cells_sim.v"), "r") as f: for item in f: parse_line(item,fout) with open(os.path.join(args.yosys, "gatemate", "cells_bb.v"), "r") as f: for item in f: parse_line(item,fout) for name,v in die.PRIMITIVES_PINS.items(): print(f"// hardware primitive {name}", file=fout) export_name(name, fout) print(f"// {name} pins", file=fout) for pin in v: export_name(pin.name, fout) print(file=fout) print("// end of autogenerated items", file=fout) print(file=fout) if __name__ == "__main__": main(sys.argv) prjpeppercorn-1.12/tools/html_all.py000066400000000000000000000050721514752025000176410ustar00rootroot00000000000000#!/usr/bin/env python3 # # prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools # # Copyright (C) 2024 The Project Peppercorn Authors. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import os, time from os import path from string import Template import html_tilegrid import shutil import chip GM_DOCS_INDEX = """ Project Peppercorn HTML Documentation

Project Peppercorn HTML Documentation

Project Peppercorn is a project to document the GateMate bitstream and internal architecture.

This repository contains HTML documentation automatically generated from the Project Peppercorn database. Data generated includes tilemap data and bitstream data for many tile types. Click on any tile to see its bitstream documentation.

$docs_toc

Licensed under a very permissive CC0 1.0 Universal license.

""" def main(): shutil.rmtree("work_html", ignore_errors=True) os.mkdir("work_html") commit_hash = "" #database.get_db_commit() build_dt = time.strftime('%Y-%m-%d %H:%M:%S') docs_toc = "" family = "CCGM1" print("Family: " + family) docs_toc += f"

{family.upper()} Family

" docs_toc += "

Bitstream Documentation

" docs_toc += "
    " for device in chip.get_all_devices(): print("Device: " + device) docs_toc += f'
  • {device} Documentation
    • ' html_tilegrid.main(["html_tilegrid", family, device, path.join("work_html",device + ".html")]) docs_toc += "
" index_html = Template(GM_DOCS_INDEX).substitute( datetime=build_dt, commit=commit_hash, docs_toc=docs_toc ) with open(path.join("work_html", "index.html"), 'w') as f: f.write(index_html) if __name__ == "__main__": main() prjpeppercorn-1.12/tools/html_tilegrid.py000066400000000000000000000065421514752025000206770ustar00rootroot00000000000000#!/usr/bin/env python3 # # prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools # # Copyright (C) 2024 The Project Peppercorn Authors. # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import sys import argparse import chip import die parser = argparse.ArgumentParser(description=__doc__) parser.add_argument('family', type=str, help="FPGA family (e.g. CCGM1)") parser.add_argument('device', type=str, help="FPGA device (e.g. A1)") parser.add_argument('outfile', type=argparse.FileType('w'), help="output HTML file") def get_colour(ttype): match ttype: case "CPE": colour = "#ACC8E6" case "SB_BIG": colour = "#9CC763" case "SB_SML": colour = "#F8EA56" case "GPIO": colour = "#B699D4" case "IM": colour = "#FFC51F" case "OM": colour = "#D19537" case "IOES": colour = "#6D6D6D" case "LES" | "RES" | "TES" | "BES": colour = "#FDD3D3" case "PLL": colour = "#FF7ABE" case "SERDES": colour = "#64FF65" case "CFG_CTRL": colour = "#999999" case _: colour = "#FFFFFF" return colour def main(argv): args = parser.parse_args(argv[1:]) ch = chip.get_device(args.device) max_row = ch.max_row() max_col = ch.max_col() tiles = [] for i in range(-2, max_row+1): row = [] for j in range(-2, max_col+1): row.append([]) tiles.append(row) for y in range(-2, max_row+1): for x in range(-2, max_col+1): for type in ch.get_tile_types(x,y): tiles[max_row-y][x+2].append((f"{x},{y}", type)) f = args.outfile print( f""" {args.family} Tiles

{args.device} Tilegrid

""", file=f) for trow in tiles: print("", file=f) row_max_height = 0 for tloc in trow: row_max_height = max(row_max_height, len(tloc)) row_height = max(90, 30 * row_max_height) for tloc in trow: print(f"", file=f) print("", file=f) print("
", file=f) for tile in tloc: print(f"
{tile[0]}
{tile[1]}
", file=f) print("
", file=f) if __name__ == "__main__": main(sys.argv)