pax_global_header00006660000000000000000000000064144677224120014523gustar00rootroot0000000000000052 comment=ef0f3e7ac2d49d5eb36adb45c12b3b64fb8dd46f armnn-23.08/000077500000000000000000000000001446772241200126525ustar00rootroot00000000000000armnn-23.08/Android.bp000066400000000000000000000003001446772241200145460ustar00rootroot00000000000000// // Copyright © 2017 ARM Ltd. All rights reserved. // SPDX-License-Identifier: MIT // // Dummy Android.bp file to keep backward compatibility with previous // build systems/environments. armnn-23.08/Android.mk000066400000000000000000000545551446772241200146010ustar00rootroot00000000000000# # Copyright © 2017-2023 ARM Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # LOCAL_PATH := $(call my-dir) ARMNN_ANDROID_MK_ENABLED := 1 ifeq ($(ARMNN_ANDROID_MK_ENABLE),0) ARMNN_ANDROID_MK_ENABLED := 0 endif ifeq ($(ARMNN_ANDROID_MK_ENABLED),1) # Configure these paths if you move the source or Khronos headers ARMNN_GENERATED_HEADER_PATH := $(LOCAL_PATH)/generated OPENCL_HEADER_PATH := $(LOCAL_PATH)/../clframework/include NN_HEADER_PATH := $(LOCAL_PATH)/../../../../frameworks/ml/nn/runtime/include ARMNN_HEADER_PATH := $(LOCAL_PATH)/include ARMNN_PROFILING_INCLUDE_PATH := $(LOCAL_PATH)/profiling ARMNN_PROFILING_CLIENT_INCLUDE_PATH := $(LOCAL_PATH)/profiling/client/include ARMNN_PROFILING_COMMON_INCLUDE_PATH := $(LOCAL_PATH)/profiling/common/include ARMNN_TIMELINE_DECODER_INCLUDE_PATH := $(LOCAL_PATH)/src/timelineDecoder ARMNN_THIRD_PARTY_INCLUDE_PATH := $(LOCAL_PATH)/third-party ARMNN_MAIN_HEADER_PATH := $(LOCAL_PATH)/src ARMNN_SOURCE_HEADER_PATH := $(LOCAL_PATH)/src/armnn ARMNN_SOURCE_UTILS_HEADER_PATH := $(LOCAL_PATH)/src/armnnUtils ARMNN_TEST_UTILS_SOURCE_PATH := $(LOCAL_PATH)/src/armnnTestUtils ARMNN_BACKENDS_HEADER_PATH := $(LOCAL_PATH)/src/backends ARMNN_PROFILING_HEADER_PATH := $(LOCAL_PATH)/src/profiling ARMNN_SERIALIZER_HEADER_PATH := $(LOCAL_PATH)/src/armnnSerializer ARMNN_DESERIALIZER_HEADER_PATH := $(LOCAL_PATH)/src/armnnDeserializer # find the common.mk and backend.mk files in the backend source folders ARMNN_BACKEND_COMMON_MAKEFILE_LOCAL_PATHS := $(wildcard $(LOCAL_PATH)/src/backends/*/common.mk) ARMNN_BACKEND_COMMON_MAKEFILE_PATHS := $(subst $(LOCAL_PATH),,$(ARMNN_BACKEND_COMMON_MAKEFILE_LOCAL_PATHS)) ARMNN_BACKEND_COMMON_MAKEFILE_DIRS := $(subst /common.mk,,$(ARMNN_BACKEND_COMMON_MAKEFILE_PATHS)) ARMNN_BACKEND_MAKEFILE_LOCAL_PATHS := $(wildcard $(LOCAL_PATH)/src/backends/*/backend.mk) ARMNN_BACKEND_MAKEFILE_PATHS := $(subst $(LOCAL_PATH),,$(ARMNN_BACKEND_MAKEFILE_LOCAL_PATHS)) ARMNN_BACKEND_MAKEFILE_DIRS := $(subst /backend.mk,,$(ARMNN_BACKEND_MAKEFILE_PATHS)) ############## # libarmnn.a # ############## include $(CLEAR_VARS) LOCAL_MODULE := libarmnn ifeq ($(Q_OR_LATER),1) # "eng" is deprecated in Android Q LOCAL_MODULE_TAGS := optional else LOCAL_MODULE_TAGS := eng optional endif LOCAL_ARM_MODE := arm LOCAL_PROPRIETARY_MODULE := true # Placeholder to hold all backend source files and include paths, common and specific to the backends ARMNN_BACKEND_SOURCES := ARMNN_BACKEND_INCLUDES := # # Iterate through the backend common and specific include paths, include them into the # current makefile and append the sources held by the COMMON_SOURCES and BACKEND_SOURCES variable # (included from the given makefile) to the ARMNN_BACKEND_SOURCES list # and optional include paths set by BACKEND_INCLUDES to the ARMNN_BACKEND_INCLUDES list # $(foreach mkPath,$(ARMNN_BACKEND_COMMON_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/common.mk)\ $(eval ARMNN_BACKEND_SOURCES := $(ARMNN_BACKEND_SOURCES)\ $(patsubst %,$(mkPath)/%,$(COMMON_SOURCES)))) $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk)\ $(eval ARMNN_BACKEND_SOURCES := $(ARMNN_BACKEND_SOURCES)\ $(patsubst %,$(mkPath)/%,$(BACKEND_SOURCES)))) $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk)\ $(eval ARMNN_BACKEND_INCLUDES += $(BACKEND_INCLUDES))) # Mark source files as dependent on Android.mk and backend makefiles LOCAL_ADDITIONAL_DEPENDENCIES := $(LOCAL_PATH)/Android.mk \ $(ARMNN_BACKEND_MAKEFILE_LOCAL_PATHS) LOCAL_EXPORT_C_INCLUDES := \ $(ARMNN_PROFILING_INCLUDE_PATH) \ $(ARMNN_PROFILING_COMMON_INCLUDE_PATH) \ $(ARMNN_PROFILING_CLIENT_INCLUDE_PATH) \ $(ARMNN_MAIN_HEADER_PATH) \ $(ARMNN_SOURCE_HEADER_PATH) \ $(ARMNN_TIMELINE_DECODER_INCLUDE_PATH) \ $(ARMNN_THIRD_PARTY_INCLUDE_PATH) \ $(ARMNN_SOURCE_UTILS_HEADER_PATH) \ $(ARMNN_PROFILING_HEADER_PATH) \ $(ARMNN_BACKENDS_HEADER_PATH) \ $(ARMNN_SERIALIZER_HEADER_PATH) \ $(ARMNN_DESERIALIZER_HEADER_PATH) LOCAL_C_INCLUDES := \ $(OPENCL_HEADER_PATH) \ $(NN_HEADER_PATH) \ $(ARMNN_GENERATED_HEADER_PATH) \ $(ARMNN_PROFILING_INCLUDE_PATH) \ $(ARMNN_PROFILING_COMMON_INCLUDE_PATH) \ $(ARMNN_PROFILING_CLIENT_INCLUDE_PATH) \ $(ARMNN_HEADER_PATH) \ $(ARMNN_TIMELINE_DECODER_INCLUDE_PATH) \ $(ARMNN_THIRD_PARTY_INCLUDE_PATH) \ $(ARMNN_MAIN_HEADER_PATH) \ $(ARMNN_SOURCE_HEADER_PATH) \ $(ARMNN_SOURCE_UTILS_HEADER_PATH) \ $(ARMNN_PROFILING_HEADER_PATH) \ $(ARMNN_BACKENDS_HEADER_PATH) \ $(ARMNN_SERIALIZER_HEADER_PATH) \ $(ARMNN_DESERIALIZER_HEADER_PATH) \ $(ARMNN_BACKEND_INCLUDES) LOCAL_SRC_FILES := \ $(ARMNN_BACKEND_SOURCES) \ profiling/common/src/CommandHandlerFunctor.cpp \ profiling/common/src/CommandHandlerKey.cpp \ profiling/common/src/CommandHandlerRegistry.cpp \ profiling/common/src/CommonProfilingUtils.cpp \ profiling/common/src/CounterDirectory.cpp \ profiling/common/src/LabelsAndEventClasses.cpp \ profiling/common/src/Logging.cpp \ profiling/common/src/NetworkSockets.cpp \ profiling/common/src/PacketVersionResolver.cpp \ profiling/common/src/Processes.cpp \ profiling/common/src/SwTrace.cpp \ profiling/common/src/Threads.cpp \ profiling/client/src/ActivateTimelineReportingCommandHandler.cpp \ profiling/client/src/BufferManager.cpp \ profiling/client/src/CommandHandler.cpp \ profiling/client/src/ConnectionAcknowledgedCommandHandler.cpp \ profiling/client/src/CounterIdMap.cpp \ profiling/client/src/DeactivateTimelineReportingCommandHandler.cpp \ profiling/client/src/FileOnlyProfilingConnection.cpp \ profiling/client/src/Holder.cpp \ profiling/client/src/IProfilingService.cpp \ profiling/client/src/PacketBuffer.cpp \ profiling/client/src/PeriodicCounterCapture.cpp \ profiling/client/src/PeriodicCounterSelectionCommandHandler.cpp \ profiling/client/src/PerJobCounterSelectionCommandHandler.cpp \ profiling/client/src/ProfilingConnectionDumpToFileDecorator.cpp \ profiling/client/src/ProfilingConnectionFactory.cpp \ profiling/client/src/ProfilingService.cpp \ profiling/client/src/ProfilingStateMachine.cpp \ profiling/client/src/ProfilingUtils.cpp \ profiling/client/src/RegisterBackendCounters.cpp \ profiling/client/src/RequestCounterDirectoryCommandHandler.cpp \ profiling/client/src/SendCounterPacket.cpp \ profiling/client/src/SendThread.cpp \ profiling/client/src/SendTimelinePacket.cpp \ profiling/client/src/SocketProfilingConnection.cpp \ profiling/client/src/TimelinePacketWriterFactory.cpp \ profiling/client/src/TimelineUtilityMethods.cpp \ profiling/client/src/backends/BackendProfiling.cpp \ profiling/client/src/backends/IBackendProfiling.cpp \ profiling/server/src/timelineDecoder/DirectoryCaptureCommandHandler.cpp \ profiling/server/src/timelineDecoder/TimelineCaptureCommandHandler.cpp \ profiling/server/src/timelineDecoder/TimelineDecoder.cpp \ profiling/server/src/timelineDecoder/TimelineDirectoryCaptureCommandHandler.cpp \ src/armnn/ArmNNProfilingServiceInitialiser.cpp \ src/armnn/BackendHelper.cpp \ src/armnn/BackendRegistry.cpp \ src/armnn/Descriptors.cpp \ src/armnn/Exceptions.cpp \ src/armnn/Graph.cpp \ src/armnn/ILayerSupport.cpp \ src/armnn/InternalTypes.cpp \ src/armnn/JsonPrinter.cpp \ src/armnn/Layer.cpp \ src/armnn/LoadedNetwork.cpp \ src/armnn/Logging.cpp \ src/armnn/Network.cpp \ src/armnn/NetworkUtils.cpp \ src/armnn/Observable.cpp \ src/armnn/Optimizer.cpp \ src/armnn/OutputHandler.cpp \ src/armnn/ProfilingEvent.cpp \ src/armnn/Profiling.cpp \ src/armnn/Runtime.cpp \ src/armnn/SerializeLayerParameters.cpp \ src/armnn/SubgraphView.cpp \ src/armnn/SubgraphViewSelector.cpp \ src/armnn/Tensor.cpp \ src/armnn/Threadpool.cpp \ src/armnn/TypesUtils.cpp \ src/armnn/Utils.cpp \ src/armnn/WallClockTimer.cpp \ src/armnn/WorkingMemHandle.cpp \ src/armnnUtils/CompatibleTypes.cpp \ src/armnnUtils/DataLayoutIndexed.cpp \ src/armnnUtils/DotSerializer.cpp \ src/armnnUtils/FloatingPointConverter.cpp \ src/armnnUtils/HeapProfiling.cpp \ src/armnnUtils/LeakChecking.cpp \ src/armnnUtils/ParserHelper.cpp \ src/armnnUtils/Permute.cpp \ src/armnnUtils/TensorUtils.cpp \ src/armnnUtils/VerificationHelpers.cpp \ src/armnnUtils/Filesystem.cpp \ src/armnnUtils/ProfilingOptionsConverter.cpp \ src/armnnUtils/Transpose.cpp \ src/armnn/layers/ActivationLayer.cpp \ src/armnn/layers/AdditionLayer.cpp \ src/armnn/layers/ArgMinMaxLayer.cpp \ src/armnn/layers/BatchMatMulLayer.cpp \ src/armnn/layers/BatchNormalizationLayer.cpp \ src/armnn/layers/BatchToSpaceNdLayer.cpp \ src/armnn/layers/CastLayer.cpp \ src/armnn/layers/ChannelShuffleLayer.cpp \ src/armnn/layers/ComparisonLayer.cpp \ src/armnn/layers/ConcatLayer.cpp \ src/armnn/layers/ConstantLayer.cpp \ src/armnn/layers/Convolution2dLayer.cpp \ src/armnn/layers/Convolution3dLayer.cpp \ src/armnn/layers/ConvertFp16ToFp32Layer.cpp \ src/armnn/layers/ConvertFp32ToFp16Layer.cpp \ src/armnn/layers/DebugLayer.cpp \ src/armnn/layers/DepthToSpaceLayer.cpp \ src/armnn/layers/DepthwiseConvolution2dLayer.cpp \ src/armnn/layers/DequantizeLayer.cpp \ src/armnn/layers/DetectionPostProcessLayer.cpp \ src/armnn/layers/DivisionLayer.cpp \ src/armnn/layers/ElementwiseBaseLayer.cpp \ src/armnn/layers/ElementwiseBinaryLayer.cpp \ src/armnn/layers/ElementwiseUnaryLayer.cpp \ src/armnn/layers/FakeQuantizationLayer.cpp \ src/armnn/layers/FillLayer.cpp \ src/armnn/layers/FloorLayer.cpp \ src/armnn/layers/FullyConnectedLayer.cpp \ src/armnn/layers/GatherLayer.cpp \ src/armnn/layers/GatherNdLayer.cpp \ src/armnn/layers/InputLayer.cpp \ src/armnn/layers/InstanceNormalizationLayer.cpp \ src/armnn/layers/L2NormalizationLayer.cpp \ src/armnn/layers/LogicalBinaryLayer.cpp \ src/armnn/layers/LogSoftmaxLayer.cpp \ src/armnn/layers/LstmLayer.cpp \ src/armnn/layers/MapLayer.cpp \ src/armnn/layers/MaximumLayer.cpp \ src/armnn/layers/MeanLayer.cpp \ src/armnn/layers/MemCopyLayer.cpp \ src/armnn/layers/MemImportLayer.cpp \ src/armnn/layers/MergeLayer.cpp \ src/armnn/layers/MinimumLayer.cpp \ src/armnn/layers/MultiplicationLayer.cpp \ src/armnn/layers/NormalizationLayer.cpp \ src/armnn/layers/OutputLayer.cpp \ src/armnn/layers/PadLayer.cpp \ src/armnn/layers/PermuteLayer.cpp \ src/armnn/layers/Pooling2dLayer.cpp \ src/armnn/layers/Pooling3dLayer.cpp \ src/armnn/layers/PreCompiledLayer.cpp \ src/armnn/layers/PreluLayer.cpp \ src/armnn/layers/QLstmLayer.cpp \ src/armnn/layers/QuantizeLayer.cpp \ src/armnn/layers/QuantizedLstmLayer.cpp \ src/armnn/layers/RankLayer.cpp \ src/armnn/layers/ReduceLayer.cpp \ src/armnn/layers/ReshapeLayer.cpp \ src/armnn/layers/ResizeLayer.cpp \ src/armnn/layers/ReverseV2Layer.cpp \ src/armnn/layers/ShapeLayer.cpp \ src/armnn/layers/SliceLayer.cpp \ src/armnn/layers/SoftmaxLayer.cpp \ src/armnn/layers/SpaceToBatchNdLayer.cpp \ src/armnn/layers/SpaceToDepthLayer.cpp \ src/armnn/layers/SplitterLayer.cpp \ src/armnn/layers/StackLayer.cpp \ src/armnn/layers/StandInLayer.cpp \ src/armnn/layers/StridedSliceLayer.cpp \ src/armnn/layers/SubtractionLayer.cpp \ src/armnn/layers/SwitchLayer.cpp \ src/armnn/layers/TileLayer.cpp \ src/armnn/layers/TransposeConvolution2dLayer.cpp \ src/armnn/layers/TransposeLayer.cpp \ src/armnn/layers/UnidirectionalSequenceLstmLayer.cpp \ src/armnn/layers/UnmapLayer.cpp \ src/armnnSerializer/Serializer.cpp \ src/armnnSerializer/SerializerUtils.cpp \ src/armnnDeserializer/Deserializer.cpp LOCAL_STATIC_LIBRARIES := \ libflatbuffers-framework \ arm_compute_library LOCAL_SHARED_LIBRARIES := \ liblog LOCAL_CFLAGS := \ -std=$(CPP_VERSION) \ -fexceptions \ -Wno-unused-parameter \ -frtti \ -DFMT_HEADER_ONLY LOCAL_LDFLAGS += \ -Wl,-Map=libarmnnMapFile.map # The variable to enable/disable the CL backend (ARMNN_COMPUTE_CL_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_COMPUTE_CL_ENABLED),1) LOCAL_CFLAGS += \ -DARMCOMPUTECL_ENABLED endif # ARMNN_COMPUTE_CL_ENABLED == 1 # The variable to enable/disable the NEON backend (ARMNN_COMPUTE_NEON_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_COMPUTE_NEON_ENABLED),1) LOCAL_CFLAGS += \ -DARMCOMPUTENEON_ENABLED endif # ARMNN_COMPUTE_NEON_ENABLED == 1 # The variable to enable/disable the REFERENCE backend (ARMNN_REF_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_REF_ENABLED),1) LOCAL_CFLAGS += \ -DARMNNREF_ENABLED endif # ARMNN_REF_ENABLED == 1 ifeq ($(Q_OR_LATER),1) LOCAL_CFLAGS += \ -DARMNN_MIXED_PRECISION_FP16_POOLING endif # PLATFORM_VERSION == Q or later include $(BUILD_STATIC_LIBRARY) ############### # armnn-tests # ############### include $(CLEAR_VARS) LOCAL_MODULE := armnn-tests ifeq ($(Q_OR_LATER),1) # "eng" is deprecated in Android Q LOCAL_MODULE_TAGS := optional else LOCAL_MODULE_TAGS := eng optional endif LOCAL_ARM_MODE := arm LOCAL_PROPRIETARY_MODULE := true # placeholder to hold all backend unit test source files ARMNN_BACKEND_TEST_SOURCES := ARMNN_BACKEND_TEST_INCLUDES := # # iterate through the backend common and specific include paths, include them into the current # makefile and append the sources held by the COMMON_TEST_SOURCES and BACKEND_TEST_SOURCES # (included from the given makefile) to the ARMNN_BACKEND_TEST_SOURCES list # $(foreach mkPath,$(ARMNN_BACKEND_COMMON_MAKEFILE_DIRS), \ $(eval include $(LOCAL_PATH)/$(mkPath)/common.mk) \ $(eval ARMNN_BACKEND_TEST_SOURCES := $(ARMNN_BACKEND_TEST_SOURCES) \ $(patsubst %,$(mkPath)/%,$(COMMON_TEST_SOURCES)))) $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS), \ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk) \ $(eval ARMNN_BACKEND_TEST_SOURCES := $(ARMNN_BACKEND_TEST_SOURCES) \ $(patsubst %,$(mkPath)/%,$(BACKEND_TEST_SOURCES)))) $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk)\ $(eval ARMNN_BACKEND_TEST_INCLUDES += $(BACKEND_TEST_INCLUDES))) # Placeholder to hold all backend link files. ARMNN_BACKEND_TEST_STATIC_LIBRARIES := ARMNN_BACKEND_TEST_SHARED_LIBRARIES := # Iterate through the Arm NN backends and specific include paths, include them into the # current makefile and append the linkfiles held by # the optional BACKEND_STATIC_LIBRARIES and optional BACKEND_SHARED_LIBRARIES variable # (included from the given makefile) to # the ARMNN_BACKEND_STATIC_LIBRARIES and ARMNN_BACKEND_SHARED_LIBRARIES lists $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk)\ $(eval ARMNN_BACKEND_TEST_STATIC_LIBRARIES += $(BACKEND_TEST_STATIC_LIBRARIES))) $(foreach mkPath,$(ARMNN_BACKEND_MAKEFILE_DIRS),\ $(eval include $(LOCAL_PATH)/$(mkPath)/backend.mk)\ $(eval ARMNN_BACKEND_TEST_SHARED_LIBRARIES += $(BACKEND_TEST_SHARED_LIBRARIES))) # Mark source files as dependent on Android.mk LOCAL_ADDITIONAL_DEPENDENCIES := $(LOCAL_PATH)/Android.mk LOCAL_C_INCLUDES := \ $(OPENCL_HEADER_PATH) \ $(NN_HEADER_PATH) \ $(ARMNN_GENERATED_HEADER_PATH) \ $(ARMNN_PROFILING_INCLUDE_PATH) \ $(ARMNN_PROFILING_COMMON_INCLUDE_PATH) \ $(ARMNN_PROFILING_CLIENT_INCLUDE_PATH) \ $(ARMNN_HEADER_PATH) \ $(ARMNN_TIMELINE_DECODER_INCLUDE_PATH) \ $(ARMNN_THIRD_PARTY_INCLUDE_PATH) \ $(ARMNN_MAIN_HEADER_PATH) \ $(ARMNN_SOURCE_HEADER_PATH) \ $(ARMNN_SOURCE_UTILS_HEADER_PATH) \ $(ARMNN_TEST_UTILS_SOURCE_PATH) \ $(ARMNN_PROFILING_HEADER_PATH) \ $(ARMNN_BACKENDS_HEADER_PATH) \ $(ARMNN_SERIALIZER_HEADER_PATH) \ $(ARMNN_DESERIALIZER_HEADER_PATH) \ $(ARMNN_BACKEND_INCLUDES) LOCAL_CFLAGS := \ -std=$(CPP_VERSION) \ -fexceptions \ -frtti \ # The variable to enable/disable the CL backend (ARMNN_COMPUTE_CL_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_COMPUTE_CL_ENABLED),1) LOCAL_CFLAGS += \ -DARMCOMPUTECL_ENABLED endif # ARMNN_COMPUTE_CL_ENABLED == 1 # The variable to enable/disable the NEON backend (ARMNN_COMPUTE_NEON_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_COMPUTE_NEON_ENABLED),1) LOCAL_CFLAGS += \ -DARMCOMPUTENEON_ENABLED endif # ARMNN_COMPUTE_NEON_ENABLED == 1 # The variable to enable/disable the REFERENCE backend (ARMNN_REF_ENABLED) is declared in android-nn-driver/Android.mk ifeq ($(ARMNN_REF_ENABLED),1) LOCAL_CFLAGS += \ -DARMNNREF_ENABLED endif # ARMNN_REF_ENABLED == 1 LOCAL_SRC_FILES := \ $(ARMNN_BACKEND_TEST_SOURCES) \ src/armnn/test/ConstTensorLayerVisitor.cpp \ src/armnn/test/EndToEndTest.cpp \ src/armnn/ExecutionFrame.cpp \ src/armnn/test/ExecutionFrameTest.cpp \ src/armnn/test/FloatingPointConverterTest.cpp \ src/armnn/test/FlowControl.cpp \ src/armnn/test/GraphTests.cpp \ src/armnn/test/InferOutputTests.cpp \ src/armnn/test/InstrumentTests.cpp \ src/armnn/test/LayerTests.cpp \ src/armnnUtils/ModelAccuracyChecker.cpp \ src/armnn/test/ModelAccuracyCheckerTest.cpp \ src/armnn/test/NetworkTests.cpp \ src/armnn/test/ObservableTest.cpp \ src/armnn/test/optimizations/ConvertConstantsFloatToHalfTests.cpp \ src/armnn/test/optimizations/ConvertConstantsHalfToFloatTests.cpp \ src/armnn/test/optimizations/Fp32NetworkToFp16ConverterTests.cpp \ src/armnn/test/optimizations/FuseActivationTests.cpp \ src/armnn/test/optimizations/InsertDebugLayerTests.cpp \ src/armnn/test/optimizations/MovePermuteUpTests.cpp \ src/armnn/test/optimizations/OptimizeConsecutiveReshapesTests.cpp \ src/armnn/test/optimizations/OptimizeInverseConversionsTests.cpp \ src/armnn/test/optimizations/OptimizeInversePermutesTests.cpp \ src/armnn/test/optimizations/PermuteAndBatchToSpaceAsDepthToSpaceTests.cpp \ src/armnn/test/optimizations/PermuteAsReshapeTests.cpp \ src/armnn/test/optimizations/ReduceMultipleAxesTests.cpp \ src/armnn/test/optimizations/SquashEqualSiblingsTests.cpp \ src/armnn/test/optimizations/TransposeAsReshapeTests.cpp \ src/armnn/test/OptimizerTests.cpp \ src/armnn/test/OptionalTest.cpp \ src/armnn/test/ProfilerTests.cpp \ src/armnn/test/ProfilingEventTest.cpp \ src/armnnUtils/PrototxtConversions.cpp \ src/armnnUtils/test/PrototxtConversionsTest.cpp \ src/armnn/test/SubgraphViewTests.cpp \ src/armnn/test/TensorHandleStrategyTest.cpp \ src/armnn/test/TensorTest.cpp \ src/armnn/test/TestInputOutputLayerVisitor.cpp \ src/armnn/test/TestLayerVisitor.cpp \ src/armnn/test/TestNameAndDescriptorLayerVisitor.cpp \ src/armnn/test/TestNameOnlyLayerVisitor.cpp \ src/armnn/test/UtilsTests.cpp \ src/armnnUtils/test/ParserHelperTest.cpp \ src/armnnUtils/test/QuantizeHelperTest.cpp \ src/armnnUtils/test/TensorUtilsTest.cpp \ src/armnnTestUtils/CommonTestUtils.cpp \ src/armnnTestUtils/GraphUtils.cpp \ src/armnnTestUtils/MockBackend.cpp \ src/armnnTestUtils/MockMemoryManager.cpp \ src/armnnTestUtils/MockTensorHandle.cpp \ src/armnnTestUtils/MockTensorHandleFactory.cpp \ src/armnnTestUtils/TensorCopyUtils.cpp \ src/armnnTestUtils/TestUtils.cpp \ src/armnnTestUtils/UnitTests.cpp \ src/profiling/test/BufferTests.cpp \ src/profiling/test/FileOnlyProfilingDecoratorTests.cpp \ src/profiling/test/PrintPacketHeaderHandler.cpp \ src/profiling/test/ProfilingConnectionDumpToFileDecoratorTests.cpp \ src/profiling/test/ProfilingGuidTest.cpp \ src/profiling/test/ProfilingTests.cpp \ src/profiling/test/ProfilingTestUtils.cpp \ src/profiling/test/SendCounterPacketTests.cpp \ src/profiling/test/SendTimelinePacketTests.cpp \ src/profiling/test/TestTimelinePacketHandler.cpp \ src/profiling/test/TimelineModel.cpp \ src/profiling/test/TimelinePacketTests.cpp \ src/profiling/test/TimelineUtilityMethodsTests.cpp \ src/armnnSerializer/test/ActivationSerializationTests.cpp \ src/armnnSerializer/test/ComparisonSerializationTests.cpp \ src/armnnSerializer/test/LstmSerializationTests.cpp \ src/armnnSerializer/test/SerializerTests.cpp \ src/armnnSerializer/test/SerializerTestUtils.cpp ifeq ($(ARMNN_REF_ENABLED),1) LOCAL_SRC_FILES += \ src/armnn/test/DebugCallbackTest.cpp \ src/armnn/test/RuntimeTests.cpp endif LOCAL_STATIC_LIBRARIES := \ libneuralnetworks_common \ libflatbuffers-framework \ arm_compute_library \ $(ARMNN_BACKEND_TEST_STATIC_LIBRARIES) LOCAL_WHOLE_STATIC_LIBRARIES := libarmnn LOCAL_SHARED_LIBRARIES := \ libbase \ libhidlbase \ libhidltransport \ libhidlmemory \ liblog \ libutils \ android.hardware.neuralnetworks@1.0 \ android.hidl.allocator@1.0 \ android.hidl.memory@1.0 \ $(ARMNN_BACKEND_TEST_SHARED_LIBRARIES) ifeq ($(ARMNN_INCLUDE_LIBOPENCL),1) LOCAL_SHARED_LIBRARIES += \ libOpenCL endif include $(BUILD_EXECUTABLE) endif # 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Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/BuildGuideAndroidNDK.md000066400000000000000000000364441446772241200170620ustar00rootroot00000000000000# How to use the Android NDK to build Arm NN - [Introduction](#introduction) - [Initial Setup](#initial-setup) - [Download the Android NDK and make a standalone toolchain](#download-the-android-ndk-and-make-a-standalone-toolchain) - [Install Cmake](#install-cmake) - [Build Flatbuffers](#build-flatbuffers) - [Download Arm NN](#download-arm-nn) - [Get And Build TFLite](#get-and-build-tflite) - [Build Arm Compute Library](#build-arm-compute-library) - [Build Arm NN](#build-arm-nn) - [Build Standalone Sample Dynamic Backend](#build-standalone-sample-dynamic-backend) - [Run the Arm NN unit tests on an Android device](#run-the-arm-nn-unit-tests-on-an-android-device) ## Introduction These are step-by-step instructions for using the Android NDK to build Arm NN. They have been tested on a clean installation of Ubuntu 18.04 and 20.04, and should also work with other OS versions. The instructions show how to build the Arm NN core library and its dependencies. For ease of use there is a shell script version of this guide located in the scripts directory called [build_android_ndk_guide.sh](scripts/build_android_ndk_guide.sh). Run the script with a -h flag to see the command line parameters. The shell script version of this guide (build_android_ndk_guide.sh) also provides user the option to use the Arm NN and ComputeLibrary available in your BASE_DIR, instead of downloading a new version. BASE_DIR is path to the script file, which is armnn/scripts/. ## Initial Setup First, we need to specify the Android version and the directories you want to build Arm NN in and to install some applications required to build Arm NN and its dependencies. ```bash export ANDROID_API=30 export WORKING_DIR=$HOME/armnn-devenv export NDK_DIR=$WORKING_DIR/android-ndk-r25 export NDK_TOOLCHAIN_ROOT=$NDK_DIR/toolchains/llvm/prebuilt/linux-x86_64 export PATH=$NDK_TOOLCHAIN_ROOT/bin/:$PATH ``` You may want to append the above export variables commands to your `~/.bashrc` (or `~/.bash_profile` in macOS). The ANDROID_API variable should be set to the Android API version number you are using. For example, "30" for Android R. The WORKING_DIR can be any directory you have write permissions to. ### Required Applications Git is required to obtain Arm NN. If this has not been already installed then install it using: ```bash sudo apt install git ``` Arm Compute Library requires SCons. If this has not been already installed then install it using: ```bash sudo apt install scons ``` CMake is required to build Arm NN and its dependencies. If this has not been already installed then install it using: ```bash sudo apt install cmake ``` ## Download the Android NDK and make a standalone toolchain Download the Android NDK from [the official website](https://developer.android.com/ndk/downloads/index.html): ```bash mkdir -p $WORKING_DIR cd $WORKING_DIR # For Mac OS, change the NDK download link accordingly. wget https://dl.google.com/android/repository/android-ndk-r25-linux.zip unzip android-ndk-r25-linux.zip ``` With Android NDK-25, you no longer need to use the make_standalone_toolchain script to create a toolchain for a specific version of Android. Android's current preference is for you to just specify the architecture and operating system while setting the compiler and just use the ndk directory. ## Install Cmake Cmake 3.19rc3 or later is required to build Arm NN. If you are using Ubuntu 20.04 the command given in [Initial Setup](#initial-setup) should install a usable version. If you're using Ubuntu 18.04 you may need to compile cmake yourself. ```bash cd $WORKING_DIR sudo apt-get install libssl-dev wget https://github.com/Kitware/CMake/releases/download/v3.19.0-rc3/cmake-3.19.0-rc3.tar.gz tar -zxvf cmake-3.19.0-rc3.tar.gz cd cmake-3.19.0-rc3 ./bootstrap --prefix=$WORKING_DIR/cmake/install make all install cd.. ``` ## Build Flatbuffers Download Flatbuffers: ```bash cd $WORKING_DIR wget https://github.com/google/flatbuffers/archive/v2.0.6.tar.gz tar xf v2.0.6.tar.gz ``` Build Flatbuffers for x86: ```bash cd $WORKING_DIR/flatbuffers-2.0.6 rm -f CMakeCache.txt rm -rf build-x86 mkdir build-x86 cd build-x86 rm -rf $WORKING_DIR/flatbuffers-x86 mkdir $WORKING_DIR/flatbuffers-x86 CXXFLAGS="-fPIC" $CMAKE .. \ -DFLATBUFFERS_BUILD_FLATC=1 \ -DCMAKE_INSTALL_PREFIX:PATH=$WORKING_DIR/flatbuffers-x86 make all install -j16 ``` Note: -fPIC is added to allow users to use the libraries in shared objects. Build Flatbuffers for Android: ```bash cd $WORKING_DIR/flatbuffers-2.0.6 rm -f CMakeCache.txt rm -rf build-android mkdir build-android cd build-android rm -rf $WORKING_DIR/flatbuffers-android mkdir $WORKING_DIR/flatbuffers-android CC=/usr/bin/aarch64-linux-gnu-gcc CXX=/usr/bin/aarch64-linux-gnu-g++ \ CXXFLAGS="-fPIC" \ cmake .. \ -DCMAKE_ANDROID_NDK=$NDK_DIR \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION=$ANDROID_API \ -DCMAKE_ANDROID_ARCH_ABI=arm64-v8a \ -DCMAKE_CXX_FLAGS=--std=c++14 \ -DFLATBUFFERS_BUILD_FLATC=OFF \ -DCMAKE_BUILD_TYPE=Release \ -DFLATBUFFERS_BUILD_TESTS=OFF \ -DCMAKE_INSTALL_PREFIX=$WORKING_DIR/flatbuffers-android make all install -j16 ``` ## Download Arm NN Clone Arm NN: ```bash cd $WORKING_DIR git clone https://github.com/ARM-software/armnn.git ``` Checkout the Arm NN branch: ```bash cd armnn git checkout git pull ``` For example, if you want to check out the 23.02 release branch: ```bash cd armnn git checkout branches/armnn_23_02 git pull ``` ## Get And Build TFLite This optional step is only required if you intend to build the TFLite delegate or parser for Arm NN. First clone Tensorflow manually and check out the version Arm NN was tested with: ```bash cd $WORKING_DIR git clone https://github.com/tensorflow/tensorflow.git cd tensorflow git fetch && git checkout "6f692f73cb2043b4a0b0446539cd8c15b3dd9220" ``` Or use the script that Arm NN provides: ```bash git fetch && git checkout $(../armnn/scripts/get_tensorflow.sh -p) ``` Next, set variable TFLITE_ROOT_DIR and build Tensorflow Lite: ```bash export TFLITE_ROOT_DIR=$WORKING_DIR/tensorflow/tensorflow/lite cd $WORKING_DIR mkdir -p tflite-out/android cd tflite-out/android CMARGS="-DTFLITE_ENABLE_XNNPACK=OFF \ -DFLATBUFFERS_BUILD_FLATC=OFF \ -DBUILD_SHARED_LIBS=OFF \ -DBUILD_TESTING=OFF" CMARGS="$CMARGS -DCMAKE_TOOLCHAIN_FILE=$NDK_DIR/build/cmake/android.toolchain.cmake \ -DANDROID_ABI=arm64-v8a \ -DANDROID_PLATFORM=$ANDROID_API" cmake $CMARGS $TFLITE_ROOT_DIR cd $WORKING_DIR cmake --build tflite-out/android -j 16 ``` Now generate the Tensorflow Lite Schema for the TFLite parser: ```bash cd $WORKING_DIR mkdir -p $WORKING_DIR/tflite-out/tensorflow/tensorflow/lite/schema SCHEMA_LOCATION=$WORKING_DIR/tensorflow/tensorflow/lite/schema/schema.fbs cp $SCHEMA_LOCATION $WORKING_DIR/tflite-out/tensorflow/tensorflow/lite/schema cd $WORKING_DIR/tflite-out/tensorflow/tensorflow/lite/schema $WORKING_DIR/flatbuffers-x86/bin/flatc -c --gen-object-api --reflect-types --reflect-names schema.fbs ``` ## Build Arm Compute Library Clone Arm Compute Library: ```bash cd $WORKING_DIR git clone https://github.com/ARM-software/ComputeLibrary.git ``` Checkout Arm Compute Library release tag: ```bash cd ComputeLibrary git checkout ``` For example, if you want to check out the 23.02 release tag: ```bash cd ComputeLibrary git checkout v23.02 ``` Arm NN and Arm Compute Library are developed closely together. To use a particular version of Arm NN you will need a compatible version of ACL. Arm NN provides a script that downloads the version of Arm Compute Library that Arm NN was tested with: ```bash git checkout $(../armnn/scripts/get_compute_library.sh -p) ``` Build the Arm Compute Library: ```bash scons arch=arm64-v8a os=android toolchain_prefix=llvm- compiler_prefix=aarch64-linux-android$ANDROID_API- \ neon=1 opencl=1 embed_kernels=1 extra_cxx_flags="-fPIC" \ benchmark_tests=0 validation_tests=0 -j16 ``` ## Build Arm NN Build Arm NN: ```bash mkdir $WORKING_DIR/armnn/build cd $WORKING_DIR/armnn/build CXX=aarch64-linux-android$ANDROID_API-clang++ \ CC=aarch64-linux-android$ANDROID_API-clang \ CXX_FLAGS="-fPIE -fPIC" \ cmake .. \ -DCMAKE_BUILD_TYPE=Release \ -DCMAKE_ANDROID_NDK=$NDK_DIR \ -DNDK_VERSION=r25 \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION=$ANDROID_API \ -DCMAKE_ANDROID_ARCH_ABI=arm64-v8a \ -DCMAKE_SYSROOT=$WORKING_DIR/android-ndk-r25/toolchains/llvm/prebuilt/linux-x86_64/sysroot \ -DARMCOMPUTE_ROOT=$WORKING_DIR/ComputeLibrary \ -DARMCOMPUTE_BUILD_DIR=$WORKING_DIR/ComputeLibrary/build \ -DARMCOMPUTENEON=1 -DARMCOMPUTECL=1 -DARMNNREF=1 \ -DFLATBUFFERS_INCLUDE_PATH=$WORKING_DIR/flatbuffers-x86/include \ -DFLATBUFFERS_ROOT=$WORKING_DIR/flatbuffers-android \ -DFLATC_DIR=$WORKING_DIR/flatbuffers-x86 \ -DBUILD_UNIT_TESTS=1 \ -DBUILD_TESTS=1 \ -fexception \ ``` To include the Arm NN TFLite delegate add these arguments to the above list: ```bash -DBUILD_ARMNN_TFLITE_DELEGATE=1 \ -DTENSORFLOW_ROOT=$WORKING_DIR/tensorflow \ -DTFLITE_LIB_ROOT=$WORKING_DIR/tflite-out/android \ -DTFLITE_ROOT_DIR=$WORKING_DIR/tensorflow/tensorflow/lite \ ``` To include the Arm NN TFLite Parser add these arguments to the above list: ```bash -DBUILD_TF_LITE_PARSER=1 \ -DTF_LITE_GENERATED_PATH=$WORKING_DIR/tflite-out/tensorflow/tensorflow/lite/schema \ -DTENSORFLOW_ROOT=$WORKING_DIR/tensorflow \ -DTFLITE_LIB_ROOT=$WORKING_DIR/tflite-out/android \ ``` To include standalone sample dynamic backend tests, add these arguments to enable the tests and the dynamic backend path to the CMake command: ```bash -DSAMPLE_DYNAMIC_BACKEND=1 \ -DDYNAMIC_BACKEND_PATHS=$SAMPLE_DYNAMIC_BACKEND_PATH # Where $SAMPLE_DYNAMIC_BACKEND_PATH is the path where libArm_SampleDynamic_backend.so library file is pushed ``` * Run the build ```bash make -j16 ``` ## Build Standalone Sample Dynamic Backend This step is optional. The sample dynamic backend is located in armnn/src/dynamic/sample ```bash mkdir build cd build ``` * Use CMake to configure the build environment, update the following script and run it from the armnn/src/dynamic/sample/build directory to set up the Arm NN build: ```bash #!/bin/bash CXX=aarch64-linux-android$ANDROID_API-clang++ \ CC=aarch64-linux-android$ANDROID_API-clang \ CXX_FLAGS="-fPIE -fPIC" \ cmake \ -DCMAKE_C_COMPILER_WORKS=TRUE \ -DCMAKE_CXX_COMPILER_WORKS=TRUE \ -DCMAKE_ANDROID_NDK=$NDK_DIR \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION=$ANDROID_API \ -DCMAKE_ANDROID_ARCH_ABI=arm64-v8a \ -DCMAKE_SYSROOT=$WORKING_DIR/android-ndk-r25/toolchains/llvm/prebuilt/linux-x86_64/sysroot \ -DCMAKE_CXX_FLAGS=--std=c++14 \ -DCMAKE_EXE_LINKER_FLAGS="-pie -llog" \ -DCMAKE_MODULE_LINKER_FLAGS="-llog" \ -DARMNN_PATH=$WORKING_DIR/armnn/build/libarmnn.so .. ``` * Run the build ```bash make ``` ## Run the Arm NN unit tests on an Android device * Push the build results to an Android device and make symbolic links for shared libraries: Currently adb version we have used for testing is 1.0.41. ```bash adb push libarmnn.so /data/local/tmp/ adb push libtimelineDecoder.so /data/local/tmp/ adb push libtimelineDecoderJson.so /data/local/tmp/ adb push GatordMock /data/local/tmp/ adb push libarmnnBasePipeServer.so /data/local/tmp/ adb push libarmnnTestUtils.so /data/local/tmp/ adb push UnitTests /data/local/tmp/ adb push $NDK_DIR/sources/cxx-stl/llvm-libc++/libs/arm64-v8a/libc++_shared.so /data/local/tmp/ ``` * Push the files needed for the unit tests (they are a mix of files, directories and symbolic links): ```bash adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/testSharedObject adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/testSharedObject/* /data/local/tmp/src/backends/backendsCommon/test/testSharedObject/ adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/testDynamicBackend adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/testDynamicBackend/* /data/local/tmp/src/backends/backendsCommon/test/testDynamicBackend/ adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath1 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath1/* /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath1/ adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath2/Arm_CpuAcc_backend.so /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/ adb shell ln -s Arm_CpuAcc_backend.so /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/Arm_CpuAcc_backend.so.1 adb shell ln -s Arm_CpuAcc_backend.so.1 /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/Arm_CpuAcc_backend.so.1.2 adb shell ln -s Arm_CpuAcc_backend.so.1.2 /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/Arm_CpuAcc_backend.so.1.2.3 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath2/Arm_GpuAcc_backend.so /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/ adb shell ln -s nothing /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath2/Arm_no_backend.so adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath3 adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath5 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath5/* /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath5/ adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath6 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath6/* /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath6/ adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath7 adb shell mkdir -p /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath9 adb push -p $WORKING_DIR/armnn/build/src/backends/backendsCommon/test/backendsTestPath9/* /data/local/tmp/src/backends/backendsCommon/test/backendsTestPath9/ adb shell mkdir -p /data/local/tmp/src/backends/dynamic/reference adb push -p $WORKING_DIR/armnn/build/src/backends/dynamic/reference/Arm_CpuRef_backend.so /data/local/tmp/src/backends/dynamic/reference/ ``` If the standalone sample dynamic tests are enabled, also push libArm_SampleDynamic_backend.so library file to the folder specified as $SAMPLE_DYNAMIC_BACKEND_PATH when Arm NN is built. This is the example when $SAMPLE_DYNAMIC_BACKEND_PATH is specified as /data/local/tmp/dynamic/sample/: ```bash adb shell mkdir -p /data/local/tmp/dynamic/sample/ adb push -p $WORKING_DIR/armnn/src/dynamic/sample/build/libArm_SampleDynamic_backend.so /data/local/tmp/dynamic/sample/ ``` If the delegate was built, push the delegate unit tests too. ```bash adb push $WORKING_DIR/armnn/build/delegate/DelegateUnitTests /data/local/tmp/ adb push $WORKING_DIR/armnn/build/delegate/libarmnnDelegate.so /data/local/tmp/ ``` Run Arm NN unit tests: ```bash adb shell 'LD_LIBRARY_PATH=/data/local/tmp:/vendor/lib64:/vendor/lib64/egl /data/local/tmp/UnitTests' ``` If the delegate was built run Arm Delegate NN unit tests: ```bash adb shell 'LD_LIBRARY_PATH=/data/local/tmp:/vendor/lib64:/vendor/lib64/egl /data/local/tmp/DelegateUnitTests' ``` If libarmnnUtils.a is present in `$WORKING_DIR/armnn/build/` and the unit tests run without failure then the build was successful. armnn-23.08/BuildGuideAndroidNDK.md.license000066400000000000000000000001531446772241200204670ustar00rootroot00000000000000# # Copyright © 2018-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/CMakeLists.txt000066400000000000000000001267451446772241200154310ustar00rootroot00000000000000# # Copyright © 2017-2023 Arm Ltd and Contributors. All rights reserved. # Copyright © 2020 NXP # SPDX-License-Identifier: MIT # cmake_minimum_required (VERSION 3.7.0) project(armnn) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(additional_cmake_files) list(APPEND additional_cmake_files cmake/ArmnnVersion.cmake cmake/ClassicDelegateVersion.cmake cmake/OpaqueDelegateVersion.cmake cmake/ParserVersion.cmake cmake/Utils.cmake cmake/GlobalConfig.cmake cmake/AddDllCopyCommands.cmake cmake/ArmnnTestUtilsVersion.cmake) foreach(cmake_file ${additional_cmake_files}) include(${cmake_file}) endforeach() cmake_policy(SET CMP0057 NEW) # If the root of the tensorflow source tree has not been specified # and we are trying to build the tensorflow lite parser make # our best guess as to where it will be i.e. one directory above # the one this CMakeLists.txt file lives in, in a subdirectory # called tensorflow if (BUILD_TF_LITE_PARSER AND "${TENSORFLOW_ROOT}" STREQUAL "") set(TENSORFLOW_ROOT "${PROJECT_SOURCE_DIR}/../tensorflow" CACHE INTERNAL "") message(STATUS "Set TENSORFLOW_ROOT: ${TENSORFLOW_ROOT}") else() message(STATUS "TENSORFLOW_ROOT: ${TENSORFLOW_ROOT}") endif() set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${PROJECT_SOURCE_DIR}/delegate/cmake/Modules/") set(as_subproject Armnn) macro(find_package) if(NOT ${ARGV0} IN_LIST as_subproject) _find_package(${ARGV}) endif() endmacro() if (DYNAMIC_BACKEND_PATHS) # It's expected to have the format: DYNAMIC_BACKEND_PATHS="PATH_1:PATH_2...:PATH_N" add_definitions('-DDYNAMIC_BACKEND_PATHS="${DYNAMIC_BACKEND_PATHS}"') endif() include(GNUInstallDirs) add_subdirectory(profiling/common/src) add_subdirectory(profiling/client/src) if(ARMNN_SAMPLE_APPS_ENABLED) add_subdirectory(samples) endif() add_subdirectory(src/armnnTfLiteParser) add_subdirectory(src/armnnSerializer) add_subdirectory(src/armnnDeserializer) if(BUILD_UNIT_TESTS) add_subdirectory(src/armnnTestUtils) endif() if (BUILD_TESTS) add_subdirectory(tests) endif() # Include the additional cmake files in their own target so that they will appear nicely in IDEs add_custom_target(AdditionalCMakeFiles SOURCES ${additional_cmake_files}) set(armnnUtils_sources) list(APPEND armnnUtils_sources include/armnnUtils/CompatibleTypes.hpp include/armnnUtils/DataLayoutIndexed.hpp include/armnnUtils/Permute.hpp include/armnnUtils/Filesystem.hpp include/armnnUtils/FloatingPointComparison.hpp include/armnnUtils/FloatingPointConverter.hpp include/armnnUtils/QuantizeHelper.hpp include/armnnUtils/TContainer.hpp include/armnnUtils/TensorUtils.hpp include/armnnUtils/Transpose.hpp src/armnnUtils/BFloat16.hpp src/armnnUtils/CompatibleTypes.cpp src/armnnUtils/Filesystem.cpp src/armnnUtils/GraphTopologicalSort.hpp src/armnnUtils/Half.hpp src/armnnUtils/Permute.cpp src/armnnUtils/DataLayoutIndexed.cpp src/armnnUtils/DotSerializer.cpp src/armnnUtils/DotSerializer.hpp src/armnnUtils/HeapProfiling.cpp src/armnnUtils/HeapProfiling.hpp src/armnnUtils/LeakChecking.cpp src/armnnUtils/LeakChecking.hpp src/armnnUtils/ModelAccuracyChecker.cpp src/armnnUtils/ModelAccuracyChecker.hpp src/armnnUtils/FloatingPointConverter.cpp src/armnnUtils/VerificationHelpers.hpp src/armnnUtils/VerificationHelpers.cpp src/armnnUtils/ParserHelper.hpp src/armnnUtils/ParserHelper.cpp src/armnnUtils/ParserPrototxtFixture.hpp src/armnnUtils/ProfilingOptionsConverter.hpp src/armnnUtils/ProfilingOptionsConverter.cpp src/armnnUtils/PrototxtConversions.hpp src/armnnUtils/PrototxtConversions.cpp src/armnnUtils/TensorIOUtils.hpp src/armnnUtils/TensorUtils.cpp src/armnnUtils/Transpose.cpp ) add_library_ex(armnnUtils STATIC ${armnnUtils_sources}) target_include_directories(armnnUtils PRIVATE src/backends) if(BUILD_ONNX_PARSER) set(armnn_onnx_parser_sources) list(APPEND armnn_onnx_parser_sources include/armnnOnnxParser/IOnnxParser.hpp include/armnnOnnxParser/Version.hpp src/armnnOnnxParser/OnnxParser.hpp src/armnnOnnxParser/OnnxParser.cpp ${ONNX_GENERATED_SOURCES}/onnx/onnx.pb.cc ) # The generated onnx protobuf .cc files are not warning clean and we can't fix them. if(COMPILER_IS_GNU_LIKE) set_source_files_properties(${ONNX_GENERATED_SOURCES}/onnx/onnx.pb.cc PROPERTIES COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion") endif() add_library_ex(armnnOnnxParser SHARED ${armnn_onnx_parser_sources}) target_include_directories(armnnOnnxParser PRIVATE src/armnnUtils) target_link_libraries(armnnOnnxParser armnn) # Protobuf target_link_libraries(armnnOnnxParser ${PROTOBUF_LIBRARIES}) set_target_properties(armnnOnnxParser PROPERTIES VERSION ${ONNX_PARSER_LIB_VERSION} SOVERSION ${ONNX_PARSER_LIB_SOVERSION}) endif() list(APPEND armnn_sources include/armnn/ArmNN.hpp include/armnn/BackendHelper.hpp include/armnn/BackendId.hpp include/armnn/BackendOptions.hpp include/armnn/BackendRegistry.hpp include/armnn/Conversion.hpp include/armnn/Deprecated.hpp include/armnn/Descriptors.hpp include/armnn/DescriptorsFwd.hpp include/armnn/Exceptions.hpp include/armnn/backends/ILayerSupport.hpp include/armnn/backends/ICustomAllocator.hpp include/armnn/IAsyncExecutionCallback.hpp include/armnn/INetwork.hpp include/armnn/IProfiler.hpp include/armnn/IRuntime.hpp include/armnn/IStrategy.hpp include/armnn/IWorkingMemHandle.hpp include/armnn/Logging.hpp include/armnn/LstmParams.hpp include/armnn/MemorySources.hpp include/armnn/NetworkFwd.hpp include/armnn/Optional.hpp include/armnn/QuantizedLstmParams.hpp include/armnn/StrategyBase.hpp include/armnn/Tensor.hpp include/armnn/TensorFwd.hpp include/armnn/Threadpool.hpp include/armnn/Types.hpp include/armnn/TypesUtils.hpp include/armnn/Utils.hpp include/armnn/Version.hpp include/armnn/utility/Assert.hpp include/armnn/utility/IgnoreUnused.hpp include/armnn/utility/NumericCast.hpp include/armnn/utility/PolymorphicDowncast.hpp include/armnn/utility/StringUtils.hpp include/armnn/utility/TransformIterator.hpp include/armnn/backends/SubgraphView.hpp src/armnn/layers/LayerCloneBase.hpp src/armnn/layers/LayerWithParameters.hpp src/armnn/layers/ActivationLayer.hpp src/armnn/layers/ActivationLayer.cpp src/armnn/layers/AdditionLayer.hpp src/armnn/layers/AdditionLayer.cpp src/armnn/layers/ArgMinMaxLayer.hpp src/armnn/layers/ArgMinMaxLayer.cpp src/armnn/layers/BatchMatMulLayer.hpp src/armnn/layers/BatchMatMulLayer.cpp src/armnn/layers/BatchNormalizationLayer.hpp src/armnn/layers/BatchNormalizationLayer.cpp src/armnn/layers/BatchToSpaceNdLayer.hpp src/armnn/layers/BatchToSpaceNdLayer.cpp src/armnn/layers/CastLayer.hpp src/armnn/layers/CastLayer.cpp src/armnn/layers/ChannelShuffleLayer.hpp src/armnn/layers/ChannelShuffleLayer.cpp src/armnn/layers/ComparisonLayer.hpp src/armnn/layers/ComparisonLayer.cpp src/armnn/layers/ConcatLayer.hpp src/armnn/layers/ConcatLayer.cpp src/armnn/layers/ConstantLayer.hpp src/armnn/layers/ConstantLayer.cpp src/armnn/layers/Convolution2dLayer.hpp src/armnn/layers/Convolution2dLayer.cpp src/armnn/layers/Convolution3dLayer.hpp src/armnn/layers/Convolution3dLayer.cpp src/armnn/layers/ConvertFp16ToFp32Layer.hpp src/armnn/layers/ConvertFp16ToFp32Layer.cpp src/armnn/layers/ConvertFp32ToFp16Layer.hpp src/armnn/layers/ConvertFp32ToFp16Layer.cpp src/armnn/layers/DebugLayer.hpp src/armnn/layers/DebugLayer.cpp src/armnn/layers/DepthToSpaceLayer.hpp src/armnn/layers/DepthToSpaceLayer.cpp src/armnn/layers/DepthwiseConvolution2dLayer.hpp src/armnn/layers/DepthwiseConvolution2dLayer.cpp src/armnn/layers/DequantizeLayer.hpp src/armnn/layers/DequantizeLayer.cpp src/armnn/layers/DetectionPostProcessLayer.hpp src/armnn/layers/DetectionPostProcessLayer.cpp src/armnn/layers/ElementwiseBaseLayer.hpp src/armnn/layers/ElementwiseBaseLayer.cpp src/armnn/layers/ElementwiseBinaryLayer.hpp src/armnn/layers/ElementwiseBinaryLayer.cpp src/armnn/layers/ElementwiseUnaryLayer.hpp src/armnn/layers/ElementwiseUnaryLayer.cpp src/armnn/layers/FakeQuantizationLayer.hpp src/armnn/layers/FakeQuantizationLayer.cpp src/armnn/layers/FillLayer.hpp src/armnn/layers/FillLayer.cpp src/armnn/layers/FloorLayer.hpp src/armnn/layers/FloorLayer.cpp src/armnn/layers/FullyConnectedLayer.hpp src/armnn/layers/FullyConnectedLayer.cpp src/armnn/layers/GatherLayer.cpp src/armnn/layers/GatherLayer.hpp src/armnn/layers/GatherNdLayer.cpp src/armnn/layers/GatherNdLayer.hpp src/armnn/layers/InputLayer.hpp src/armnn/layers/InputLayer.cpp src/armnn/layers/InstanceNormalizationLayer.hpp src/armnn/layers/InstanceNormalizationLayer.cpp src/armnn/layers/L2NormalizationLayer.hpp src/armnn/layers/L2NormalizationLayer.cpp src/armnn/layers/LogicalBinaryLayer.hpp src/armnn/layers/LogicalBinaryLayer.cpp src/armnn/layers/LogSoftmaxLayer.hpp src/armnn/layers/LogSoftmaxLayer.cpp src/armnn/layers/LstmLayer.cpp src/armnn/layers/LstmLayer.hpp src/armnn/layers/MapLayer.cpp src/armnn/layers/MapLayer.hpp src/armnn/layers/MaximumLayer.cpp src/armnn/layers/MaximumLayer.hpp src/armnn/layers/MeanLayer.hpp src/armnn/layers/MeanLayer.cpp src/armnn/layers/MemCopyLayer.hpp src/armnn/layers/MemCopyLayer.cpp src/armnn/layers/MemImportLayer.hpp src/armnn/layers/MemImportLayer.cpp src/armnn/layers/MergeLayer.hpp src/armnn/layers/MergeLayer.cpp src/armnn/layers/MinimumLayer.cpp src/armnn/layers/MinimumLayer.hpp src/armnn/layers/MultiplicationLayer.hpp src/armnn/layers/MultiplicationLayer.cpp src/armnn/layers/NormalizationLayer.hpp src/armnn/layers/NormalizationLayer.cpp src/armnn/layers/OutputLayer.hpp src/armnn/layers/OutputLayer.cpp src/armnn/layers/PadLayer.hpp src/armnn/layers/PadLayer.cpp src/armnn/layers/PermuteLayer.hpp src/armnn/layers/PermuteLayer.cpp src/armnn/layers/Pooling2dLayer.hpp src/armnn/layers/Pooling2dLayer.cpp src/armnn/layers/Pooling3dLayer.hpp src/armnn/layers/Pooling3dLayer.cpp src/armnn/layers/QuantizeLayer.cpp src/armnn/layers/QuantizeLayer.hpp src/armnn/layers/QLstmLayer.hpp src/armnn/layers/QLstmLayer.cpp src/armnn/layers/QuantizedLstmLayer.hpp src/armnn/layers/QuantizedLstmLayer.cpp src/armnn/layers/DivisionLayer.cpp src/armnn/layers/DivisionLayer.hpp src/armnn/layers/PreCompiledLayer.hpp src/armnn/layers/PreCompiledLayer.cpp src/armnn/layers/PreluLayer.hpp src/armnn/layers/PreluLayer.cpp src/armnn/layers/RankLayer.hpp src/armnn/layers/RankLayer.cpp src/armnn/layers/ReduceLayer.hpp src/armnn/layers/ReduceLayer.cpp src/armnn/layers/ReshapeLayer.hpp src/armnn/layers/ReshapeLayer.cpp src/armnn/layers/ResizeLayer.hpp src/armnn/layers/ResizeLayer.cpp src/armnn/layers/ReverseV2Layer.hpp src/armnn/layers/ReverseV2Layer.cpp src/armnn/layers/ShapeLayer.cpp src/armnn/layers/ShapeLayer.hpp src/armnn/layers/SliceLayer.cpp src/armnn/layers/SliceLayer.hpp src/armnn/layers/SoftmaxLayer.hpp src/armnn/layers/SoftmaxLayer.cpp src/armnn/layers/SpaceToBatchNdLayer.hpp src/armnn/layers/SpaceToBatchNdLayer.cpp src/armnn/layers/SpaceToDepthLayer.hpp src/armnn/layers/SpaceToDepthLayer.cpp src/armnn/layers/SplitterLayer.hpp src/armnn/layers/SplitterLayer.cpp src/armnn/layers/StackLayer.hpp src/armnn/layers/StackLayer.cpp src/armnn/layers/StandInLayer.cpp src/armnn/layers/StandInLayer.hpp src/armnn/layers/StridedSliceLayer.cpp src/armnn/layers/StridedSliceLayer.hpp src/armnn/layers/SubtractionLayer.cpp src/armnn/layers/SubtractionLayer.hpp src/armnn/layers/SwitchLayer.cpp src/armnn/layers/SwitchLayer.hpp src/armnn/layers/TileLayer.cpp src/armnn/layers/TileLayer.hpp src/armnn/layers/TransposeConvolution2dLayer.cpp src/armnn/layers/TransposeConvolution2dLayer.hpp src/armnn/layers/TransposeLayer.hpp src/armnn/layers/TransposeLayer.cpp src/armnn/layers/UnidirectionalSequenceLstmLayer.cpp src/armnn/layers/UnidirectionalSequenceLstmLayer.hpp src/armnn/layers/UnmapLayer.cpp src/armnn/layers/UnmapLayer.hpp src/armnn/ArmNNProfilingServiceInitialiser.cpp src/armnn/ArmNNProfilingServiceInitialiser.hpp src/armnn/AsyncExecutionCallback.cpp src/armnn/AsyncExecutionCallback.hpp src/armnn/BackendRegistry.cpp src/armnn/BackendSettings.hpp src/armnn/BackendHelper.cpp src/armnn/Descriptors.cpp src/armnn/DeviceSpec.hpp src/armnn/DllExport.hpp src/armnn/Exceptions.cpp src/armnn/ExecutionData.hpp src/armnn/ExecutionFrame.cpp src/armnn/ExecutionFrame.hpp src/armnn/Graph.cpp src/armnn/Graph.hpp src/armnn/IGraphObservable.hpp src/armnn/ILayerSupport.cpp src/armnn/Instrument.hpp src/armnn/InternalTypes.cpp src/armnn/InternalTypes.hpp src/armnn/ISubgraphViewConverter.hpp src/armnn/JsonPrinter.cpp src/armnn/JsonPrinter.hpp src/armnn/Layer.cpp src/armnn/LayerFwd.hpp src/armnn/Layer.hpp src/armnn/LayersFwd.hpp src/armnn/LayerSupportCommon.hpp src/armnn/LoadedNetwork.cpp src/armnn/LoadedNetwork.hpp src/armnn/Logging.cpp src/armnn/Network.cpp src/armnn/Network.hpp src/armnn/NetworkUtils.cpp src/armnn/NetworkUtils.hpp src/armnn/Observable.cpp src/armnn/Observable.hpp src/armnn/Optimizer.cpp src/armnn/Optimizer.hpp src/armnn/OutputHandler.cpp src/armnn/OutputHandler.hpp src/armnn/Profiling.cpp src/armnn/ProfilingEvent.cpp src/armnn/ProfilingDetails.hpp src/armnn/ProfilingEvent.hpp src/armnn/Profiling.hpp src/armnn/Runtime.cpp src/armnn/Runtime.hpp src/armnn/RangeTracker.cpp src/armnn/RangeTracker.hpp src/armnn/ResolveType.hpp src/armnn/SerializeLayerParameters.cpp src/armnn/SerializeLayerParameters.hpp src/armnn/SubgraphView.cpp src/armnn/SubgraphViewSelector.cpp src/armnn/SubgraphViewSelector.hpp src/armnn/Tensor.cpp src/armnn/Threadpool.cpp src/armnn/TypesUtils.cpp src/armnn/Utils.cpp src/armnn/WallClockTimer.cpp src/armnn/WallClockTimer.hpp src/armnn/WorkingMemDescriptor.hpp src/armnn/WorkingMemHandle.cpp src/armnn/WorkingMemHandle.hpp src/armnn/optimizations/AddBroadcastReshapeLayer.hpp src/armnn/optimizations/AddDebug.hpp src/armnn/optimizations/All.hpp src/armnn/optimizations/ConvertConstants.hpp src/armnn/optimizations/ConvertFp32NetworkToFp16.hpp src/armnn/optimizations/FoldPadIntoLayer2d.hpp src/armnn/optimizations/MovePermuteUp.hpp src/armnn/optimizations/MoveTransposeUp.hpp src/armnn/optimizations/Optimization.hpp src/armnn/optimizations/OptimizeConsecutiveReshapes.hpp src/armnn/optimizations/OptimizeInverseConversions.hpp src/armnn/optimizations/OptimizeInversePermutes.hpp src/armnn/optimizations/PermuteAndBatchToSpaceAsDepthToSpace.hpp src/armnn/optimizations/PermuteAsReshape.hpp src/armnn/optimizations/SquashEqualSiblings.hpp third-party/cxxopts/cxxopts.hpp third-party/ghc/filesystem.hpp third-party/half/half.hpp third-party/mapbox/optional.hpp third-party/mapbox/recursive_wrapper.hpp third-party/mapbox/variant.hpp third-party/mapbox/variant_cast.hpp third-party/mapbox/variant_io.hpp third-party/mapbox/variant_visitor.hpp ) # Files used for Streamline-based profiling backend if(PROFILING_BACKEND_STREAMLINE) list(APPEND armnn_sources ${GATOR_ROOT}/annotate/streamline_annotate.h ${GATOR_ROOT}/annotate/streamline_annotate.c) endif() # the backends under src/backends extend the list of # object libs armnn to include in the build include(src/backends/backends.cmake) foreach(lib ${armnnLibraries}) message(STATUS "Adding object library dependency to armnn: ${lib}") list(APPEND armnn_sources $) endforeach() # The delegate needs to be placed after armnnLibraries has been fully populated. The armnn_delegate_jni library # requires a static armnn build. # Explanation: # Because backends are added as object libraries they won't be linked to armnn when building armnn statically. # A target that uses a static armnn library has to link to the object libraries in the variable armnnLibraries # manually to include all symbols from backends. if (BUILD_CLASSIC_DELEGATE OR BUILD_OPAQUE_DELEGATE) set(ARMNN_SUB_PROJECT ON) set(ARMNN_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) add_subdirectory(delegate) endif() if (BUILD_CLASSIC_DELEGATE) add_definitions(-DARMNN_TFLITE_DELEGATE) endif() if (BUILD_OPAQUE_DELEGATE) add_definitions(-DARMNN_TFLITE_OPAQUE_DELEGATE) endif() if (BUILD_SHARED_LIBS) add_library_ex(armnn SHARED ${armnn_sources}) else() add_library(armnn STATIC ${armnn_sources}) endif() target_compile_definitions(armnn PRIVATE "ARMNN_COMPILING_DLL") # Generate a map file for all build modes set_property(TARGET armnn APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=libarmnnMapFile.map") message(STATUS "Linker will generate mapfile ") target_include_directories(armnn PUBLIC $ $ PRIVATE src/armnn src/armnnUtils src/backends src/profiling profiling/common/include profiling/client/include ) # Link fmt third-party library add_subdirectory(third-party/fmt) target_link_libraries(armnn PUBLIC fmt) target_link_libraries(armnn PUBLIC armnnUtils) target_link_libraries(armnn PUBLIC pipeCommon) target_link_libraries(armnn PUBLIC pipeClient) if(NOT BUILD_BARE_METAL AND NOT EXECUTE_NETWORK_STATIC) target_link_libraries(armnn PUBLIC ${CMAKE_DL_LIBS}) endif() if ("${CMAKE_SYSTEM_NAME}" STREQUAL Windows) target_link_libraries(armnn PUBLIC Ws2_32.lib) endif() if(BUILD_ONNX_PARSER) install(TARGETS armnnOnnxParser LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) endif() install(DIRECTORY include/ DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) if(ARMCOMPUTENEON OR ARMCOMPUTECL) target_link_libraries(armnn PUBLIC ${ARMCOMPUTE_LIBRARIES}) endif() # Flatbuffers is not included in armnn if the armnnSerializer is not present # Required to target link both flatbuffers and tosa_serialization_lib to armnn if(ARMNNTOSACOMMON) if (FLATBUFFERS_LIBRARY) target_link_libraries(armnn PUBLIC ${FLATBUFFERS_LIBRARY}) else() # Use PATH_SUFFIXES to help find separate libs for debug/release on Windows builds find_library(FLATBUFFERS_LIBRARY_DEBUG NAMES flatbuffers HINTS ${FLATBUFFERS_BUILD_DIR} PATH_SUFFIXES "Debug") find_library(FLATBUFFERS_LIBRARY_RELEASE NAMES flatbuffers HINTS ${FLATBUFFERS_BUILD_DIR} PATH_SUFFIXES "Release") target_link_libraries(armnn PUBLIC debug ${FLATBUFFERS_LIBRARY_DEBUG} optimized ${FLATBUFFERS_LIBRARY_RELEASE}) endif() if (TOSA_SERIALIZATION_LIB) target_link_libraries(armnn PUBLIC -Wl,--whole-archive ${TOSA_SERIALIZATION_LIB} -Wl,--no-whole-archive) else() find_library(TOSA_SERIALIZATION_LIB NAMES libtosa_serialization_lib.a tosa_serialization_lib HINTS ${TOSA_SERIALIZATION_LIB_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "TOSA serialization library set to ${TOSA_SERIALIZATION_LIB}") target_link_libraries(armnn PUBLIC -Wl,--whole-archive ${TOSA_SERIALIZATION_LIB} -Wl,--no-whole-archive) endif() endif() if (ARMNNTOSAREF) if (TOSA_REFERENCE_MODEL_LIB) target_link_libraries(armnn PUBLIC -Wl,--whole-archive ${TOSA_REFERENCE_MODEL_LIB} -Wl,--no-whole-archive) else() find_library(TOSA_REFERENCE_MODEL_LIB NAMES libtosa_reference_model_lib.a tosa_reference_model_lib HINTS ${TOSA_REFERENCE_MODEL_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "TOSA Reference Model set to ${TOSA_REFERENCE_MODEL_LIB}") target_link_libraries(armnn PUBLIC -Wl,--whole-archive ${TOSA_REFERENCE_MODEL_LIB} -Wl,--no-whole-archive) endif() endif() if(PROFILING_BACKEND_STREAMLINE AND (NOT ("${CMAKE_SYSTEM_NAME}" STREQUAL Android))) target_link_libraries(armnn PUBLIC ${CMAKE_THREAD_LIBS_INIT}) endif() set_target_properties(armnn PROPERTIES VERSION ${GENERIC_LIB_VERSION} SOVERSION ${GENERIC_LIB_SOVERSION}) if(BUILD_UNIT_TESTS) set(unittest_sources) list(APPEND unittest_sources src/armnn/test/CloneTests.cpp src/armnn/test/ConstTensorLayerVisitor.hpp src/armnn/test/ConstTensorLayerVisitor.cpp src/armnn/test/EndToEndTest.cpp src/armnn/test/ExecutionFrameTest.cpp src/armnn/test/FloatingPointConverterTest.cpp src/armnn/test/FlowControl.cpp src/armnn/test/GraphTests.cpp src/armnn/test/InstrumentTests.cpp src/armnn/test/LayerTests.cpp src/armnn/test/InferOutputTests.cpp src/armnn/test/InferOutputTests.hpp src/armnn/test/ModelAccuracyCheckerTest.cpp src/armnn/test/NetworkTests.cpp src/armnn/test/ObservableTest.cpp src/armnn/test/OptimizerTests.cpp src/armnn/test/optimizations/AddBroadcastReshapeLayerTests.cpp src/armnn/test/optimizations/ConvertConstDequantisationLayersToConstLayersTest.cpp src/armnn/test/optimizations/ConvertConstPermuteLayersToConstLayersTest.cpp src/armnn/test/optimizations/ConvertConstantsFloatToHalfTests.cpp src/armnn/test/optimizations/ConvertConstantsHalfToFloatTests.cpp src/armnn/test/optimizations/FoldPadIntoQuantizedAveragePooling2DTests.cpp src/armnn/test/optimizations/FoldPadTests.cpp src/armnn/test/optimizations/Fp32NetworkToFp16ConverterTests.cpp src/armnn/test/optimizations/FuseActivationTests.cpp src/armnn/test/optimizations/InsertDebugLayerTests.cpp src/armnn/test/optimizations/MovePermuteUpTests.cpp src/armnn/test/optimizations/MoveTransposeUpTests.cpp src/armnn/test/optimizations/OptimizeConsecutiveReshapesTests.cpp src/armnn/test/optimizations/OptimizeInverseConversionsTests.cpp src/armnn/test/optimizations/OptimizeInversePermutesTests.cpp src/armnn/test/optimizations/PermuteAndBatchToSpaceAsDepthToSpaceTests.cpp src/armnn/test/optimizations/PermuteAsReshapeTests.cpp src/armnn/test/optimizations/ReduceMultipleAxesTests.cpp src/armnn/test/optimizations/SquashEqualSiblingsTests.cpp src/armnn/test/optimizations/TransposeAsReshapeTests.cpp src/armnn/test/OptionalTest.cpp src/armnn/test/ProfilerTests.cpp src/armnn/test/ProfilingEventTest.cpp src/armnn/test/ShapeInferenceTests.cpp src/armnn/test/SubgraphViewTests.cpp src/armnn/test/TensorHandleStrategyTest.cpp src/armnn/test/TensorTest.cpp src/armnn/test/TestInputOutputLayerVisitor.cpp src/armnn/test/TestInputOutputLayerVisitor.hpp src/armnn/test/TestLayerVisitor.cpp src/armnn/test/TestLayerVisitor.hpp src/armnn/test/TestNameOnlyLayerVisitor.cpp src/armnn/test/TestNameOnlyLayerVisitor.hpp src/armnn/test/TestNameAndDescriptorLayerVisitor.hpp src/armnn/test/TestNameAndDescriptorLayerVisitor.cpp src/armnn/test/UtilityTests.cpp src/armnn/test/UtilsTests.cpp src/armnnUtils/test/FloatingPointComparisonTest.cpp src/armnnUtils/test/ParserHelperTest.cpp src/armnnUtils/test/PrototxtConversionsTest.cpp src/armnnUtils/test/QuantizeHelperTest.cpp src/armnnUtils/test/TensorUtilsTest.cpp src/armnnUtils/test/TransformIteratorTest.cpp src/profiling/test/BufferTests.cpp src/profiling/test/FileOnlyProfilingDecoratorTests.cpp src/profiling/test/PrintPacketHeaderHandler.cpp src/profiling/test/PrintPacketHeaderHandler.hpp src/profiling/test/ProfilingConnectionDumpToFileDecoratorTests.cpp src/profiling/test/ProfilingGuidTest.cpp src/profiling/test/ProfilingMocks.hpp src/profiling/test/ProfilingTests.cpp src/profiling/test/ProfilingTests.hpp src/profiling/test/ProfilingTestUtils.cpp src/profiling/test/ProfilingTestUtils.hpp src/profiling/test/RequestCountersPacketHandler.cpp src/profiling/test/RequestCountersPacketHandler.hpp src/profiling/test/SendCounterPacketTests.cpp src/profiling/test/SendCounterPacketTests.hpp src/profiling/test/TestTimelinePacketHandler.cpp src/profiling/test/TestTimelinePacketHandler.hpp src/profiling/test/TimelineModel.cpp src/profiling/test/TimelineModel.hpp src/profiling/test/SendTimelinePacketTests.cpp src/profiling/test/TimelinePacketTests.cpp src/profiling/test/TimelineUtilityMethodsTests.cpp third-party/doctest/doctest.h ) if(ARMNNREF) list(APPEND unittest_sources src/armnn/test/optimizations/FuseBatchNormTests.cpp src/armnn/test/DebugCallbackTest.cpp src/armnn/test/RuntimeTests.cpp src/armnn/test/RuntimeTests.hpp ) endif() if(BUILD_TF_LITE_PARSER AND ARMNNREF) list(APPEND unittest_sources src/armnnTfLiteParser/test/Activations.cpp src/armnnTfLiteParser/test/Addition.cpp src/armnnTfLiteParser/test/ArgMinMax.cpp src/armnnTfLiteParser/test/AvgPool2D.cpp src/armnnTfLiteParser/test/BatchMatMul.cpp src/armnnTfLiteParser/test/BatchToSpaceND.cpp src/armnnTfLiteParser/test/Cast.cpp src/armnnTfLiteParser/test/Comparison.cpp src/armnnTfLiteParser/test/Concatenation.cpp src/armnnTfLiteParser/test/Constant.cpp src/armnnTfLiteParser/test/Conv2D.cpp src/armnnTfLiteParser/test/Conv3D.cpp src/armnnTfLiteParser/test/DepthwiseConvolution2D.cpp src/armnnTfLiteParser/test/DepthToSpace.cpp src/armnnTfLiteParser/test/Dequantize.cpp src/armnnTfLiteParser/test/DetectionPostProcess.cpp src/armnnTfLiteParser/test/Div.cpp src/armnnTfLiteParser/test/ElementWiseUnary.cpp src/armnnTfLiteParser/test/ExpandDims.cpp src/armnnTfLiteParser/test/FloorDiv.cpp src/armnnTfLiteParser/test/FullyConnected.cpp src/armnnTfLiteParser/test/Gather.cpp src/armnnTfLiteParser/test/GatherNd.cpp src/armnnTfLiteParser/test/L2Normalization.cpp src/armnnTfLiteParser/test/LeakyRelu.cpp src/armnnTfLiteParser/test/LoadScopeDynamicTensor.cpp src/armnnTfLiteParser/test/LocalResponseNormalization.cpp src/armnnTfLiteParser/test/Maximum.cpp src/armnnTfLiteParser/test/MaxPool2D.cpp src/armnnTfLiteParser/test/Mean.cpp src/armnnTfLiteParser/test/Minimum.cpp src/armnnTfLiteParser/test/MirrorPad.cpp src/armnnTfLiteParser/test/Multiplication.cpp src/armnnTfLiteParser/test/Pack.cpp src/armnnTfLiteParser/test/Pad.cpp src/armnnTfLiteParser/test/PadV2.cpp src/armnnTfLiteParser/test/Power.cpp src/armnnTfLiteParser/test/Prelu.cpp src/armnnTfLiteParser/test/Reduce.cpp src/armnnTfLiteParser/test/Reshape.cpp src/armnnTfLiteParser/test/ReshapeDynamic.cpp src/armnnTfLiteParser/test/ResizeBilinear.cpp src/armnnTfLiteParser/test/ResizeNearestNeighbor.cpp src/armnnTfLiteParser/test/ReverseV2.cpp src/armnnTfLiteParser/test/Quantize.cpp src/armnnTfLiteParser/test/Softmax.cpp src/armnnTfLiteParser/test/SpaceToBatchND.cpp src/armnnTfLiteParser/test/Shape.cpp src/armnnTfLiteParser/test/Slice.cpp src/armnnTfLiteParser/test/Split.cpp src/armnnTfLiteParser/test/SplitV.cpp src/armnnTfLiteParser/test/Squeeze.cpp src/armnnTfLiteParser/test/Square.cpp src/armnnTfLiteParser/test/SquaredDifference.cpp src/armnnTfLiteParser/test/StridedSlice.cpp src/armnnTfLiteParser/test/Sub.cpp src/armnnTfLiteParser/test/Sum.cpp src/armnnTfLiteParser/test/Tile.cpp src/armnnTfLiteParser/test/TransposeConv.cpp src/armnnTfLiteParser/test/Transpose.cpp src/armnnTfLiteParser/test/Unpack.cpp src/armnnTfLiteParser/test/Unsupported.cpp src/armnnTfLiteParser/test/LoadModel.cpp src/armnnTfLiteParser/test/GetBuffer.cpp src/armnnTfLiteParser/test/OutputShapeOfSqueeze.cpp src/armnnTfLiteParser/test/InputOutputTensorNames.cpp src/armnnTfLiteParser/test/GetTensorIds.cpp src/armnnTfLiteParser/test/GetSubgraphInputsOutputs.cpp src/armnnTfLiteParser/test/GetInputsOutputs.cpp src/armnnTfLiteParser/test/TfLiteParser.cpp ) # Generate SchemaText.cpp file which contains the TfLite schema text as a # static C-array of bytes. This is needed at runtime for TfLite parser tests. add_custom_command( OUTPUT SchemaText.cpp COMMAND cp ${TF_LITE_SCHEMA_INCLUDE_PATH}/schema.fbs g_TfLiteSchemaText COMMAND xxd -i g_TfLiteSchemaText SchemaText.cpp WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} DEPENDS ${TF_LITE_SCHEMA_INCLUDE_PATH}/schema.fbs ) list(APPEND unittest_sources ${CMAKE_CURRENT_BINARY_DIR}/SchemaText.cpp) endif() if(BUILD_ONNX_PARSER AND ARMNNREF) list(APPEND unittest_sources src/armnnOnnxParser/test/Addition.cpp src/armnnOnnxParser/test/BatchNorm.cpp src/armnnOnnxParser/test/Clip.cpp src/armnnOnnxParser/test/Concat.cpp src/armnnOnnxParser/test/Const.cpp src/armnnOnnxParser/test/Constructor.cpp src/armnnOnnxParser/test/Conv2D.cpp src/armnnOnnxParser/test/CreateNetwork.cpp src/armnnOnnxParser/test/DepthConv.cpp src/armnnOnnxParser/test/Flatten.cpp src/armnnOnnxParser/test/FullyConnected.cpp src/armnnOnnxParser/test/Gather.cpp src/armnnOnnxParser/test/Gemm.cpp src/armnnOnnxParser/test/GetInputsOutputs.cpp src/armnnOnnxParser/test/LoadScopeDynamicTensor.cpp src/armnnOnnxParser/test/OnnxParserTestUtils.cpp src/armnnOnnxParser/test/OnnxParserTestUtils.hpp src/armnnOnnxParser/test/Pooling.cpp src/armnnOnnxParser/test/Relu.cpp src/armnnOnnxParser/test/Reshape.cpp src/armnnOnnxParser/test/Shape.cpp src/armnnOnnxParser/test/Unsqueeze.cpp ) endif() if(BUILD_ARMNN_SERIALIZER AND ARMNNREF) enable_language(ASM) list(APPEND unittest_sources src/armnnSerializer/test/ActivationSerializationTests.cpp src/armnnSerializer/test/ComparisonSerializationTests.cpp src/armnnSerializer/test/LstmSerializationTests.cpp src/armnnSerializer/test/SerializerTests.cpp src/armnnSerializer/test/SerializerTestUtils.cpp src/armnnSerializer/test/SerializerTestUtils.hpp src/armnnDeserializer/test/DeserializeAbs.cpp src/armnnDeserializer/test/DeserializeActivation.cpp src/armnnDeserializer/test/DeserializeAdd.cpp src/armnnDeserializer/test/DeserializeArgMinMax.cpp src/armnnDeserializer/test/DeserializeBatchMatMul.cpp src/armnnDeserializer/test/DeserializeBatchToSpaceNd.cpp src/armnnDeserializer/test/DeserializeBatchNormalization.cpp src/armnnDeserializer/test/DeserializeCast.cpp src/armnnDeserializer/test/DeserializeChannelShuffle.cpp src/armnnDeserializer/test/DeserializeComparison.cpp src/armnnDeserializer/test/DeserializeConstant.cpp src/armnnDeserializer/test/DeserializeConvolution2d.cpp src/armnnDeserializer/test/DeserializeConvolution3d.cpp src/armnnDeserializer/test/DeserializeDepthToSpace.cpp src/armnnDeserializer/test/DeserializeDepthwiseConv2d.cpp src/armnnDeserializer/test/DeserializeElementWiseBinary.cpp src/armnnDeserializer/test/DeserializeDivision.cpp src/armnnDeserializer/test/DeserializeFill.cpp src/armnnDeserializer/test/DeserializeFloor.cpp src/armnnDeserializer/test/DeserializeFullyConnected.cpp src/armnnDeserializer/test/DeserializeGather.cpp src/armnnDeserializer/test/DeserializeGatherNd.cpp src/armnnDeserializer/test/DeserializeInstanceNormalization.cpp src/armnnDeserializer/test/DeserializeL2Normalization.cpp src/armnnDeserializer/test/DeserializeLogSoftmax.cpp src/armnnDeserializer/test/DeserializeMean.cpp src/armnnDeserializer/test/DeserializeMultiplication.cpp src/armnnDeserializer/test/DeserializeNormalization.cpp src/armnnDeserializer/test/DeserializePad.cpp src/armnnDeserializer/test/DeserializePermute.cpp src/armnnDeserializer/test/DeserializePooling2d.cpp src/armnnDeserializer/test/DeserializePooling3d.cpp src/armnnDeserializer/test/DeserializeRank.cpp src/armnnDeserializer/test/DeserializeReduceSum.cpp src/armnnDeserializer/test/DeserializeReshape.cpp src/armnnDeserializer/test/DeserializeResizeBilinear.cpp src/armnnDeserializer/test/DeserializeReverseV2.cpp src/armnnDeserializer/test/DeserializeRsqrt.cpp src/armnnDeserializer/test/DeserializeShape.cpp src/armnnDeserializer/test/DeserializeSlice.cpp src/armnnDeserializer/test/DeserializeSpaceToBatchNd.cpp src/armnnDeserializer/test/DeserializeStridedSlice.cpp src/armnnDeserializer/test/DeserializeSubtraction.cpp src/armnnDeserializer/test/ParserFlatbuffersSerializeFixture.hpp src/armnnDeserializer/test/SchemaSerialize.s ) set_source_files_properties(src/armnnDeserializer/test/SchemaSerialize.s PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp") endif() if(BUILD_GATORD_MOCK) list(APPEND unittest_sources tests/profiling/gatordmock/tests/GatordMockTests.cpp ) endif() if(BUILD_TIMELINE_DECODER) list(APPEND unittest_sources src/timelineDecoder/tests/JSONTimelineDecoderTests.cpp profiling/server/src/timelineDecoder/tests/TimelineTests.cpp ) endif() if(BUILD_BASE_PIPE_SERVER) list(APPEND unittest_sources profiling/server/src/basePipeServer/tests/BasePipeServerTests.cpp ) endif() if(BUILD_TESTS) list(APPEND unittest_sources ./tests/ExecuteNetwork/FileComparisonExecutor.hpp ./tests/ExecuteNetwork/FileComparisonExecutor.cpp ./tests/ExecuteNetwork/test/FileComparisonExecutorTests.cpp ./tests/NetworkExecutionUtils/NetworkExecutionUtils.cpp ./tests/NetworkExecutionUtils/test/NetworkExecutionUtilsTests.cpp) endif() foreach(lib ${armnnUnitTestLibraries}) message(STATUS "Adding object library dependency to UnitTests: ${lib}") list(APPEND unittest_sources $) endforeach() add_executable(UnitTests ${unittest_sources}) target_include_directories(UnitTests PRIVATE delegate/common/include src/armnn src/armnnUtils src/armnnTestUtils src/backends src/profiling tests) if(VALGRIND_FOUND) if(HEAP_PROFILING OR LEAK_CHECKING) message(STATUS "Valgrind is disabled for heap profiling and leak checking builds.") else() # Valgrind works with gperftools version number <= 2.4 target_compile_definitions(UnitTests PRIVATE "WITH_VALGRIND=1") endif() endif() target_link_libraries(UnitTests ${CMAKE_THREAD_LIBS_INIT}) target_link_libraries(UnitTests armnn) target_link_libraries(UnitTests armnnTestUtils) if(BUILD_GATORD_MOCK) target_link_libraries(UnitTests gatordMockService) endif() if(BUILD_TIMELINE_DECODER) target_link_libraries(UnitTests timelineDecoder) target_link_libraries(UnitTests timelineDecoderJson) endif() if(BUILD_TF_LITE_PARSER) target_include_directories(UnitTests SYSTEM PRIVATE "${TF_LITE_SCHEMA_INCLUDE_PATH}") target_include_directories(UnitTests SYSTEM PRIVATE "${FLATBUFFERS_INCLUDE_PATH}") target_link_libraries(UnitTests armnnTfLiteParser) endif() if(BUILD_ARMNN_SERIALIZER AND ARMNNREF) target_include_directories(UnitTests SYSTEM PRIVATE generated) target_include_directories(UnitTests SYSTEM PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/src/armnnSerializer) target_include_directories(UnitTests SYSTEM PRIVATE "${FLATBUFFERS_INCLUDE_PATH}") target_link_libraries(UnitTests armnnSerializer) endif() if(BUILD_ONNX_PARSER) target_link_libraries(UnitTests armnnOnnxParser) endif() if(BUILD_BASE_PIPE_SERVER) target_link_libraries(UnitTests armnnBasePipeServer) endif() addDllCopyCommands(UnitTests) endif() if (BUILD_ARMNN_SERIALIZER AND (BUILD_TF_LITE_PARSER OR BUILD_ONNX_PARSER) AND ARMNNREF) set(ArmnnConverter_sources src/armnnConverter/ArmnnConverter.cpp) add_executable_ex(ArmnnConverter ${ArmnnConverter_sources}) target_include_directories(ArmnnConverter PRIVATE src/armnn) target_include_directories(ArmnnConverter PRIVATE src/armnnUtils) if(BUILD_ONNX_PARSER) target_link_libraries(ArmnnConverter armnnOnnxParser) endif() if(BUILD_TF_LITE_PARSER) target_link_libraries(ArmnnConverter armnnTfLiteParser) endif() target_link_libraries(ArmnnConverter armnnSerializer) target_link_libraries(ArmnnConverter armnn) target_link_libraries(ArmnnConverter ${CMAKE_THREAD_LIBS_INIT}) addDllCopyCommands(ArmnnConverter) install(TARGETS ArmnnConverter RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) endif() if(BUILD_BASE_PIPE_SERVER) add_subdirectory(profiling/server/src/basePipeServer) endif() if(BUILD_TIMELINE_DECODER) add_subdirectory(profiling/server/src/timelineDecoder) add_subdirectory(src/timelineDecoder) endif() if(BUILD_GATORD_MOCK AND NOT BUILD_BASE_PIPE_SERVER) message(ERROR, "In order to build GatordMock you must set BUILD_BASE_PIPE_SERVER = YES") endif() if(BUILD_GATORD_MOCK AND NOT BUILD_TIMELINE_DECODER) message(ERROR, "In order to build GatordMock you must set BUILD_TIMELINE_DECODER = YES") endif() if(BUILD_GATORD_MOCK) set(gatord_mock_sources) list(APPEND gatord_mock_sources tests/profiling/gatordmock/CommandFileParser.hpp tests/profiling/gatordmock/CommandFileParser.cpp tests/profiling/gatordmock/CommandLineProcessor.hpp tests/profiling/gatordmock/CommandLineProcessor.cpp tests/profiling/gatordmock/GatordMockService.hpp tests/profiling/gatordmock/GatordMockService.cpp tests/profiling/gatordmock/PeriodicCounterCaptureCommandHandler.cpp tests/profiling/gatordmock/PeriodicCounterCaptureCommandHandler.hpp tests/profiling/gatordmock/PeriodicCounterSelectionResponseHandler.cpp tests/profiling/gatordmock/PeriodicCounterSelectionResponseHandler.hpp tests/profiling/gatordmock/StreamMetadataCommandHandler.cpp tests/profiling/gatordmock/StreamMetadataCommandHandler.hpp tests/profiling/gatordmock/StubCommandHandler.hpp ) add_library_ex(gatordMockService STATIC ${gatord_mock_sources}) target_include_directories(gatordMockService PRIVATE profiling/common/include profiling/client/include profiling/server/src/basePipeServer src/armnnUtils src/profiling src/timelineDecoder) if(BUILD_UNIT_TESTS) target_include_directories(UnitTests PRIVATE tests/profiling/gatordmock) target_include_directories(UnitTests PRIVATE src/backends/backendsCommon/test) endif() add_executable_ex(GatordMock tests/profiling/gatordmock/GatordMockMain.cpp) target_include_directories(GatordMock PRIVATE profiling/common/include profiling/client/include profiling/server/src/basePipeServer src/armnnUtils src/profiling src/timelineDecoder) target_link_libraries(GatordMock PUBLIC armnn armnnBasePipeServer timelineDecoder gatordMockService) if(Threads_FOUND AND (NOT ("${CMAKE_SYSTEM_NAME}" STREQUAL Android))) target_link_libraries(GatordMock PUBLIC ${CMAKE_THREAD_LIBS_INIT}) endif() endif() #################################################### # export targets set(armnn_export_targets) list(APPEND armnn_export_targets armnn armnnUtils ) install( TARGETS ${armnn_export_targets} EXPORT armnn-targets LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} ) #################################################### ## Set export alias set_target_properties(armnn PROPERTIES EXPORT_NAME Armnn ) ## Export target scrips install( EXPORT armnn-targets FILE ArmnnTargets.cmake NAMESPACE Armnn:: DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PROJECT_NAME} ) #################################################### ## Create ArmnnConfig.cmake include(CMakePackageConfigHelpers) set(INSTALL_CONFIGDIR ${CMAKE_INSTALL_LIBDIR}) message(STATUS "CMAKE_CURRENT_LIST_DIR ${CMAKE_CURRENT_LIST_DIR}" ) message(STATUS "CMAKE_CURRENT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}" ) configure_package_config_file( ${CMAKE_CURRENT_LIST_DIR}/cmake/ArmnnConfig.cmake.in ${CMAKE_CURRENT_BINARY_DIR}/ArmnnConfig.cmake INSTALL_DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PROJECT_NAME} ) #################################################### ## Install Armnn config file install( FILES ${CMAKE_CURRENT_BINARY_DIR}/ArmnnConfig.cmake DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PROJECT_NAME} ) #################################################### ## Export from build tree export( EXPORT armnn-targets FILE ${CMAKE_CURRENT_BINARY_DIR}/ArmnnTargets.cmake NAMESPACE Armnn:: ) add_library(Armnn::Armnn ALIAS armnn) add_library(Armnn::armnnUtils ALIAS armnnUtils) #################################################### ## Build Python bindings if (BUILD_PYTHON_WHL OR BUILD_PYTHON_SRC) add_subdirectory(python/pyarmnn) endif() armnn-23.08/CONTRIBUTING.md000066400000000000000000000063601446772241200151100ustar00rootroot00000000000000# Contribution Guidelines The Arm NN project is open for external contributors and welcomes contributions. Arm NN is licensed under the [MIT license](https://spdx.org/licenses/MIT.html) and all accepted contributions must have the same license. Below is an overview on contributing code to ArmNN. For more details on contributing to Arm NN see the [Contributing page](https://mlplatform.org/contributing/) on the [MLPlatform.org](https://mlplatform.org/) website. ## Contributing code to Arm NN - All code reviews are performed on [Linaro ML Platform Gerrit](https://review.mlplatform.org) - GitHub account credentials are required for creating an account on ML Platform - Setup Arm NN git repo - git clone https://review.mlplatform.org/ml/armnn - cd armnn - git checkout main - git pull (not required upon initial clone but good practice before creating a patch) - git config user.name "FIRST_NAME SECOND_NAME" - git config user.email your@email.address - Commit using sign-off and push patch for code review - git commit -s - git push origin HEAD:refs/for/main - Patch will appear on ML Platform Gerrit [here](https://review.mlplatform.org/q/is:open+project:ml/armnn+branch:main) - See below for adding details of copyright notice and developer certificate of origin sign off ## Developer Certificate of Origin (DCO) Before the Arm NN project accepts your contribution, you need to certify its origin and give us your permission. To manage this process we use Developer Certificate of Origin (DCO) V1.1 (https://developercertificate.org/). To indicate that you agree to the the terms of the DCO, you "sign off" your contribution by adding a line with your name and e-mail address to every git commit message: Signed-off-by: John Doe You must use your real name, no pseudonyms or anonymous contributions are accepted. ## In File Copyright Notice In each source file, include the following copyright notice: // // Copyright © ` ` and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // Note: if an existing file does not conform, update it when you next modify it, as convenient. ## Releases Official Arm NN releases are published through the official [Arm NN Github repository](https://github.com/ARM-software/armnn). ## Development repository The Arm NN development repository is hosted on the [mlplatform.org git repository](https://git.mlplatform.org/ml/armnn.git/) hosted by [Linaro](https://www.linaro.org/). ## Code reviews Contributions must go through code review. Code reviews are performed through the [mlplatform.org Gerrit server](https://review.mlplatform.org). Contributors need to signup to this Gerrit server with their GitHub account credentials. Only reviewed contributions can go to the main branch of Arm NN. ## Continuous integration Contributions to Arm NN go through testing at the Arm CI system. All unit, integration and regression tests must pass before a contribution gets merged to the Arm NN main branch. ## Communications We encourage all Arm NN developers to subscribe to the [Arm NN developer mailing list](https://lists.linaro.org/mailman3/lists/armnn-dev.lists.linaro.org/). armnn-23.08/CONTRIBUTING.md.license000066400000000000000000000001531446772241200165230ustar00rootroot00000000000000# # Copyright © 2018-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/InstallationViaAptRepository.md000066400000000000000000000230241446772241200210430ustar00rootroot00000000000000# How to install ArmNN via our APT repository on Ubuntu's Launchpad * [Introduction](#introduction) * [Add the Ubuntu Launchpad PPA to your system](#add-the-ubuntu-launchpad-ppa-to-your-system) * [Outline of available packages](#outline-of-available-packages) + [x86_64](#x86_64) + [arm64](#arm64) + [armhf](#armhf) * [Install desired combination of packages](#install-desired-combination-of-packages) * [Installation of specific ABI versioned packages](#installation-of-specific-abi-versioned-packages) * [Uninstall packages](#uninstall-packages) ## Introduction These are the step by step instructions on how to install the Arm NN core, TensorflowLite Parser as well as PyArmNN for x86_64, Arm64 and Armhf for Ubuntu 20.04. The packages will also be added to Debian Bullseye, their progress can be tracked here: https://tracker.debian.org/pkg/armnn. ## Add the Ubuntu Launchpad PPA to your system * Add the PPA to your sources using a command contained in software-properties-common package: ``` sudo apt install software-properties-common sudo add-apt-repository ppa:armnn/ppa sudo apt update ``` * More information about our PPA and the Ubuntu Launchpad service can be found at [launchpad.net](https://launchpad.net/~armnn/+archive/ubuntu/ppa) ## Outline of available packages We provide a number of packages for each architecture; x86_64, aarch64 and armhf as outlined below. ARMNN_MAJOR_VERSION: This is the ABI version of the Arm NN source that has been packaged based on include/armnn/Version.hpp. ARMNN_RELEASE_VERSION: This is the marketing release version based on the date source was released on github e.g. 20.11. PACKAGE_VERSION: This is the version of the source package used to build the binaries packages from. ### x86_64 * Runtime Packages ``` libarmnn-cpuref-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb libarmnntfliteparser{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb libarmnn{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb python3-pyarmnn_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb ``` * Development Packages ``` libarmnn-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb libarmnntfliteparser-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb ``` * Dependency Packages (These are empty packages that provide a user-friendly name for other packages they will install) ``` armnn-latest-all_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb armnn-latest-ref_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb ``` ### arm64 * Runtime Packages ``` libarmnn-aclcommon{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnn-cpuacc-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnn-cpuref-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnn-gpuacc-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnntfliteparser{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnn{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb python3-pyarmnn_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb ``` * Development Packages ``` libarmnn-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb libarmnntfliteparser-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb ``` * Dependency Packages (These are empty packages that provide a user-friendly name for other packages they will install) ``` armnn-latest-all_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb armnn-latest-cpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb armnn-latest-cpu-gpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb armnn-latest-cpu-gpu-ref_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb armnn-latest-gpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb armnn-latest-ref_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_arm64.deb ``` ### armhf * Runtime Packages ``` libarmnn-aclcommon{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnn-cpuacc-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnn-cpuref-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnn-gpuacc-backend{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnntfliteparser{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnn{ARMNN_MAJOR_VERSION}_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb python3-pyarmnn_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb ``` * Development Packages ``` libarmnn-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb libarmnntfliteparser-dev_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb ``` * Dependency Packages (These are empty packages that provide a user-friendly name for other packages they will install) ``` armnn-latest-all_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb armnn-latest-cpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb armnn-latest-cpu-gpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb armnn-latest-cpu-gpu-ref_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb armnn-latest-gpu_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_armhf.deb armnn-latest-ref_{ARMNN_RELEASE_VERSION}-{PACKAGE_VERSION}_amd64.deb ``` ## Install desired combination of packages The easiest way to install all of the available packages for your systems architecture is to run the command: ``` sudo apt-get install -y python3-pyarmnn armnn-latest-all # Verify installation via python: python3 -c "import pyarmnn as ann;print(ann.GetVersion())" # Returns '{ARMNN_MAJOR_VERSION}.0.0' e.g. 33.0.0 ``` This will install PyArmNN and the three backends for Neon (CpuAcc), OpenCL (GpuAcc) and our Reference Backend. It will also install their dependencies including the arm-compute-library package along with the Tensorflow Lite Parser and it's dependency Arm NN Core. If the user does not wish to use PyArmNN they can go up a level of dependencies and instead just install the armnn-latest-all package: ``` # Install ArmNN Core, CpuAcc Backend, GpuAcc Backend and Reference Backend as well as the TensorFlow Lite Parser: # (This will only install CpuAcc and GpuAcc Backends on arm64 and armhf architectures) sudo apt-get install -y armnn-latest-all # Install ArmNN Core, CpuAcc Backend as well as the TensorFlow Lite Parser: sudo apt-get install -y armnn-latest-cpu # Install ArmNN Core, CpuAcc Backend, GpuAcc Backend as well as the TensorFlow Lite Parser: sudo apt-get install -y armnn-latest-cpu-gpu # Install ArmNN Core, GpuAcc Backend as well as the TensorFlow Lite Parser: sudo apt-get install -y armnn-latest-gpu # Install ArmNN Core, Reference Backend as well as the TensorFlow Lite Parser: sudo apt-get install -y armnn-latest-ref ``` ## Installation of specific ABI versioned packages Due to Debian Packaging requiring the pristine tarball from our Github release, the version on Launchpad may not align with the released version on Github depending on the complexity of newly added features. In order to check for the latest available Arm NN version use apt-cache search: ``` apt-cache search libarmnn # This returns a list of matching packages including versions from previous releases libarmnn-cpuref-backend23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-cpuref-backend24 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-dev - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnntfliteparser-dev - Arm NN is an inference engine for CPUs, GPUs and NPUs # Note: removal of dash to suit debian naming conventions libarmnn-tfliteparser23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnntfliteparser24 - Arm NN is an inference engine for CPUs, GPUs and NPUs # Note: removal of dash to suit debian naming conventions libarmnntfliteparser24.5 - Arm NN is an inference engine for CPUs, GPUs and NPUs # Note: removal of dash to suit debian naming conventions libarmnn23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn24 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn25 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn30 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-aclcommon23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnnaclcommon24 - Arm NN is an inference engine for CPUs, GPUs and NPUs # Note: removal of dash to suit debian naming conventions libarmnn-cpuacc-backend23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-cpuacc-backend24 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-gpuacc-backend23 - Arm NN is an inference engine for CPUs, GPUs and NPUs libarmnn-gpuacc-backend24 - Arm NN is an inference engine for CPUs, GPUs and NPUs # Export the ARMNN_MAJOR_VERSION to the latest visible e.g. libarmnn30 to allow installation using the below examples export ARMNN_MAJOR_VERSION=30 # As the Tensorflow Lite Parser is now ABI stable it will have a different version to ARMNN_MAJOR_VERSION please choose latest version: apt-cache search libarmnntfliteparser # Returns e.g. libarmnntfliteparser24.5 so we then export that version, for reference this comes from include/armnnTfLiteParser/Version.hpp: export TFLITE_PARSER_VERSION=24.5 sudo apt-get install -y libarmnntfliteparser${TFLITE_PARSER_VERSION} libarmnn-cpuacc-backend${ARMNN_MAJOR_VERSION} ``` ## Uninstall packages The easiest way to uninstall all of the previously installed packages is to run the command: ``` sudo apt-get purge -y armnn-latest-all sudo apt autoremove -y armnn-latest-all ``` armnn-23.08/InstallationViaAptRepository.md.license000066400000000000000000000001531446772241200224620ustar00rootroot00000000000000# # Copyright © 2020-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/LICENSE000066400000000000000000000020551446772241200136610ustar00rootroot00000000000000MIT License Copyright (c) 2017 ARM Limited. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. armnn-23.08/LICENSE.spdx000066400000000000000000032731171446772241200146520ustar00rootroot00000000000000SPDXVersion: SPDX-2.1 DataLicense: CC0-1.0 SPDXID: SPDXRef-DOCUMENT DocumentName: armnn DocumentNamespace: http://spdx.org/spdxdocs/spdx-v2.1-785b703b-da92-41e9-983f-49a5a3b5e86f Creator: Person: Anonymous () Creator: Organization: Anonymous () Creator: Tool: reuse-1.0.0 Created: 2022-08-03T11:04:56Z CreatorComment: This document was created automatically using available reuse information consistent with REUSE. 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dependencies PackageName: cxxopts SPDXID: SPDXRef-cxxopts FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText: Copyright (c) 2014, 2015, 2016, 2017 Jarryd Beck PackageName: doctest SPDXID: SPDXRef-doctest FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText: Copyright (c) 2016-2021 Viktor Kirilov PackageName: fmt SPDXID: SPDXRef-fmt FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText: Copyright (c) 2012 - present, Victor Zverovich PackageName: ghc SPDXID: SPDXRef-ghc FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText: Copyright (c) 2018, Steffen Schümann PackageName: half SPDXID: SPDXRef-half FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText:Copyright (c) 2012-2017 Christian Rau PackageName: MapBox SPDXID: SPDXRef-MapBox FilesAnalyzed: true PackageLicenseConcluded: BSD-3-Clause PackageLicenseInfoFromFiles: BSD-3-Clause PackageLicenseDeclared: BSD-3-Clause PackageCopyrightText: Copyright (c) MapBox All rights reserved. PackageName: stb SPDXID: SPDXRef-stb FilesAnalyzed: true PackageLicenseConcluded: MIT PackageLicenseInfoFromFiles: MIT PackageLicenseDeclared: MIT PackageCopyrightText: Copyright (c) 2017 Sean Barrett ##### Individual Files FileName: ./Android.bp SPDXID: SPDXRef-6023602810befa9adda44114844d090b FileChecksum: SHA1: 8181f188f6d5c1bfde1256daf5c6cd39dd7b8987 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 ARM Ltd. All rights reserved. FileName: ./Android.mk SPDXID: SPDXRef-2716bc1ed4229fa725d3289dfebf305f FileChecksum: SHA1: 22c385a1bedb462228b3511d9876f38a8cea4a69 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 ARM Ltd. All rights reserved. FileName: ./BuildGuideAndroidNDK.md SPDXID: SPDXRef-950af7814f60dff224a7339016ce4409 FileChecksum: SHA1: 39d573fad2cc91dac6a4996df981719dc8be02a6 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2018-2022 Arm Ltd and Contributors. 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FileName: ./profiling/client/src/IProfilingService.cpp SPDXID: SPDXRef-ffe1adeb0c86f8b21d7b381f5c7fd7e7 FileChecksum: SHA1: 54331dcd610df2f4d085f85ff98bb6572fd1a86d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ISendThread.hpp SPDXID: SPDXRef-c114312cca7401bab2a45a63de92b3b3 FileChecksum: SHA1: e7645c598cbcb161042dabbb679ab84fb4a3db6c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/NullProfilingConnection.hpp SPDXID: SPDXRef-57099a78548ae165561e9f6be2384b03 FileChecksum: SHA1: a7e6ea6e0e7014fbd987f4b87879efd4ec3dede9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/PacketBuffer.cpp SPDXID: SPDXRef-4c68107bd3f55d8722d3f642b22e6437 FileChecksum: SHA1: 4fa1bd22a78fe91f6ce9f384b7d66f2529403d4e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/PacketBuffer.hpp SPDXID: SPDXRef-809948d3d959068fe40be1513ae1de5e FileChecksum: SHA1: 610b70949b013cd7cb12a0fc9d8323cd61188e5c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/PerJobCounterSelectionCommandHandler.cpp SPDXID: SPDXRef-417502f7717fb4dede7a3dd0d82ade65 FileChecksum: SHA1: ac364df19e9ede2d7fca0776c04ec30e20839472 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/PerJobCounterSelectionCommandHandler.hpp SPDXID: SPDXRef-53f921512e218e6c177c1af8f643853b FileChecksum: SHA1: 79a39c196df0fd7f21f7cb8271497b9dbaaacccf LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/PeriodicCounterCapture.cpp SPDXID: SPDXRef-bb93b6234c7527c5df98038f75f0d8be FileChecksum: SHA1: dff9a8d39a331faecafe721803df248abb99c036 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/PeriodicCounterCapture.hpp SPDXID: SPDXRef-8ee87e342cfec8c857806162e2661d6f FileChecksum: SHA1: 22d408a1dbd058784124365e1cbf68a50bff0d36 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./profiling/client/src/PeriodicCounterSelectionCommandHandler.cpp SPDXID: SPDXRef-aef07b02cea4fcca79ef15ae82b18084 FileChecksum: SHA1: f28d1e43cc9868ec33ce95a0c10dc4ba928131be LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/PeriodicCounterSelectionCommandHandler.hpp SPDXID: SPDXRef-d92c16efad6846e086ec1ebaff4ec54a FileChecksum: SHA1: d6e408a41771dce2f35f2f40bd2ef45343544db1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingConnectionDumpToFileDecorator.cpp SPDXID: SPDXRef-8386cdb406dec88a8ba9d7318772463b FileChecksum: SHA1: 3ec72ad9c758bb4f07343e4fc40c14699c21945f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingConnectionDumpToFileDecorator.hpp SPDXID: SPDXRef-2d3ce28732264f66fb50dbaf29875f10 FileChecksum: SHA1: 8dfe9c4e1415914d3c2c8f7276619cbba0529393 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingConnectionFactory.cpp SPDXID: SPDXRef-e2c12c86031977a5b5a0dcba8109e977 FileChecksum: SHA1: a11e6e15fba2c6926d63e7dcf698495b997d19be LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingConnectionFactory.hpp SPDXID: SPDXRef-4c433342e4f80f442f6ef20b2b2501ab FileChecksum: SHA1: 8ca90cabf32b4940f0eb0f2a9d5cca0ea5183752 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingService.cpp SPDXID: SPDXRef-052bbf27cf3b1420b3f60287a0d1c840 FileChecksum: SHA1: 8ad8e88319fd85241809e53290f03ed5a4db184c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingService.hpp SPDXID: SPDXRef-a497d4ddc2cb9fdc97767ce31ed06059 FileChecksum: SHA1: 2db03b46f83ae72c75e2176f659f83dc91dafca0 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./profiling/client/src/ProfilingStateMachine.cpp SPDXID: SPDXRef-91d6731cb80d1048e03d3c17b735c7ce FileChecksum: SHA1: 9ae964442663480190f6ed5f46d3511b7070dd9a LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. 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FileName: ./src/armnn/layers/BatchMatMulLayer.cpp SPDXID: SPDXRef-10d7775f0081cf5ebcad0564e1a6771f FileChecksum: SHA1: 40cccc20bef5e36e5770f8685d8eafaa3151a395 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/BatchMatMulLayer.hpp SPDXID: SPDXRef-d540552c041624ef1df66f76adf0ee77 FileChecksum: SHA1: 16ba287eb09e398f1653923f8d78f2349b25b924 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/BatchNormalizationLayer.cpp SPDXID: SPDXRef-319f438aee8730f551da3e3f91a33cc7 FileChecksum: SHA1: ad996c6eef968fbdaeb4cee385b0473ccf8d6d72 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/BatchNormalizationLayer.hpp SPDXID: SPDXRef-45bcd545949a90a1c6fc3e38bf56c37b FileChecksum: SHA1: acba026af400914245f9eb966f1fedaf6a9eb215 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/BatchToSpaceNdLayer.cpp SPDXID: SPDXRef-a927de17fc4645f0358523e2a1e647a9 FileChecksum: SHA1: 758865d11d55d5b2c296270939bc67b366bf86d2 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/BatchToSpaceNdLayer.hpp SPDXID: SPDXRef-a8cc20df16ac4b76d4266c03628dc908 FileChecksum: SHA1: fbac9b1d4e25ce676be4f6f37c94c5512710170d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/CastLayer.cpp SPDXID: SPDXRef-952e236d3d5064b7679a831725426427 FileChecksum: SHA1: 254591d602229d4321f948c99be3a264bae8d702 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/CastLayer.hpp SPDXID: SPDXRef-3d073d3e2e38843f2ae1ffd63ccb3ca6 FileChecksum: SHA1: e87e025c01b8c8f3f74f09db7c3776be859ceee8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ChannelShuffleLayer.cpp SPDXID: SPDXRef-56a6c45a1ddb6f4452dadd23bfbf6070 FileChecksum: SHA1: de726b38dd4262d530bc9f8d84c9ddf7b3a0b464 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ChannelShuffleLayer.hpp SPDXID: SPDXRef-990b12c3e5bcd56325f879d97cb155e2 FileChecksum: SHA1: 086c2e9db287403a48ba3529fa6fe209d67dab67 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ComparisonLayer.cpp SPDXID: SPDXRef-45aa83d7d5299bb6bba349a5f6d9f253 FileChecksum: SHA1: 03e2cfca67a4e30733f778c0f222ce8410af9c9e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ComparisonLayer.hpp SPDXID: SPDXRef-b75f61f50420f83af505ad802ea1255f FileChecksum: SHA1: 08c55bf00d64b58cc30e006a26e6f63cc8024450 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConcatLayer.cpp SPDXID: SPDXRef-178b11b781a33125f80c7a7f9a338041 FileChecksum: SHA1: 5667d0d86286cc42f8c336906aa5151a70809f64 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConcatLayer.hpp SPDXID: SPDXRef-1a2dc90bed3255d00365a4e8f1514296 FileChecksum: SHA1: 90db48a75f329c87892c5948cbd095517306fbd7 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConstantLayer.cpp SPDXID: SPDXRef-3f2f51df25f176be8635370bb3909288 FileChecksum: SHA1: 2a9dbc5395b5b3cfa1cc1a9be9530ba998371b6c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConstantLayer.hpp SPDXID: SPDXRef-d9e4bd149c655f998dfe6bdb76593b48 FileChecksum: SHA1: 6049e93683051007e7cac28c47aa529a629fca86 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertBf16ToFp32Layer.cpp SPDXID: SPDXRef-d69c6daa53dda82a019abd3a38c723d0 FileChecksum: SHA1: c5a9a048a9beb1734fd9475e72025b96475c6213 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertBf16ToFp32Layer.hpp SPDXID: SPDXRef-7488b00f65298d4943d2e1f885101a0c FileChecksum: SHA1: e1bd545d01da4145a091ba027e1e2f457c6e7841 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp16ToFp32Layer.cpp SPDXID: SPDXRef-3ee61341dce5be792676bd19b5960467 FileChecksum: SHA1: c9a787c62eae7cb83edfacb0708a68b1595cf0ea LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp16ToFp32Layer.hpp SPDXID: SPDXRef-4c8519ab59e5c219d2a7ca40372e25ba FileChecksum: SHA1: 8711cc3b79c3c8f191cb9086c70a6c91dc8cf3fa LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp32ToBf16Layer.cpp SPDXID: SPDXRef-949f7a792b6ec7d24c30354218c66347 FileChecksum: SHA1: 604613a801a21a41db258c50d2d6e4c8babda602 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp32ToBf16Layer.hpp SPDXID: SPDXRef-7582f29c33f3750415fff5a6cb783323 FileChecksum: SHA1: 82c1c9e6d2680a17d343a1c8a41a41792f4d7804 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp32ToFp16Layer.cpp SPDXID: SPDXRef-558d9f55d95bd3569aad9d44f8443294 FileChecksum: SHA1: 428f091fe32fd3e126676d908424239aeec7d381 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ConvertFp32ToFp16Layer.hpp SPDXID: SPDXRef-5b40eece2aafb29a8fa8ba0e0bd14dd2 FileChecksum: SHA1: 52050c0c77e4b8eab75dc5140b3973d8b4d7705b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Convolution2dLayer.cpp SPDXID: SPDXRef-b325904d00783bd0755057d3fb71eed4 FileChecksum: SHA1: 8261029d4ca5a951bb00ade9d7a762c81c1d267d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Convolution2dLayer.hpp SPDXID: SPDXRef-a8f4ee0ec1e8ab623ac0c8e80b1c25ce FileChecksum: SHA1: 8d5ea77df2151c9cbeb1b5a1893a0db4ff1ace2b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Convolution3dLayer.cpp SPDXID: SPDXRef-3fe02d927785c331b377427b4cffed60 FileChecksum: SHA1: aaeb80cbf8aee1ad1a20a0625dba0ed5fd2f66b8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Convolution3dLayer.hpp SPDXID: SPDXRef-35bf0d3e516235a210c804027574ef51 FileChecksum: SHA1: 2f5643328ab53e1fce2103cd3d38885c7d765033 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DebugLayer.cpp SPDXID: SPDXRef-7d89136cd6a42560a3070acc8bfea3a7 FileChecksum: SHA1: 8c849002414a28266075399d2b24ae57882a5c2e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DebugLayer.hpp SPDXID: SPDXRef-faa72adf2d36bd3816cd6add2f855abe FileChecksum: SHA1: 8cd0e9ab256c8857edc37b0313875570a57bd25c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DepthToSpaceLayer.cpp SPDXID: SPDXRef-e91a67130a3d7f17c940afd6a49f90ad FileChecksum: SHA1: 74287f8cb9aa25ca8aa58664e430589049d0e39c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DepthToSpaceLayer.hpp SPDXID: SPDXRef-b5edcc0eb5c832320d389413a6544e94 FileChecksum: SHA1: b503531a6bbe4ec246683a9e627c9bbf343080e5 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DepthwiseConvolution2dLayer.cpp SPDXID: SPDXRef-155243f2d5696f2616c1892521fcb157 FileChecksum: SHA1: 974b7cdc1d52a8c489fd7aa33852d9721c372028 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DepthwiseConvolution2dLayer.hpp SPDXID: SPDXRef-336386178b668f83656a4be63542b406 FileChecksum: SHA1: 71eeba5eeddd29f156a4d7d43125c32121bcdb01 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DequantizeLayer.cpp SPDXID: SPDXRef-76986c67647f0e920734d0ab7957041d FileChecksum: SHA1: 0c0453ff21222e336c97cf0e02c1b19ffad8c392 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DequantizeLayer.hpp SPDXID: SPDXRef-0b2ec2bcbd54f67843edddd9619858cd FileChecksum: SHA1: c32ddaf6e9744735e85006d4036f8daf8211eea1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DetectionPostProcessLayer.cpp SPDXID: SPDXRef-9a4a2d388bc7b1bd4f44dae48c413e18 FileChecksum: SHA1: 3c627667841e649133ec82efd1e3388a4ee2c93f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DetectionPostProcessLayer.hpp SPDXID: SPDXRef-2334d8bc4b4af905620dc3d8f2ed5c95 FileChecksum: SHA1: cf07a58850c0df9151ee4e33a9691e16e32dd252 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DivisionLayer.cpp SPDXID: SPDXRef-5b197a1fd5f2a691fd0d87c7a7244802 FileChecksum: SHA1: a26e9183709fb997f41ebad45343897c7404212f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/DivisionLayer.hpp SPDXID: SPDXRef-ab3c6860fb47c56e3b8a3a48e4217dd6 FileChecksum: SHA1: 2b1cc3933bd17ab5905e9d1c5d1443ee6be6a63e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ElementwiseBaseLayer.cpp SPDXID: SPDXRef-26f6cb1caaf6236db88a65d83feb144c FileChecksum: SHA1: a26f6e1dc58cf0d48b1e3bf7ca1cf1ce2dec6cb3 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ElementwiseBaseLayer.hpp SPDXID: SPDXRef-1aff26a1c628a7335e71d7e1670f90ac FileChecksum: SHA1: 0a021bc0ad2ed7b463472f8c4a1f77448ee3eccc LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ElementwiseUnaryLayer.cpp SPDXID: SPDXRef-0df0052bb2cad44144080026b253258e FileChecksum: SHA1: 553d88878010e4aefbc6708b09bcda1657f586aa LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ElementwiseUnaryLayer.hpp SPDXID: SPDXRef-b3a1c29bdcf8550d38d46c7caf474f8b FileChecksum: SHA1: 9a33ddd749aba426fff2ad48664cfa06a9220ece LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FakeQuantizationLayer.cpp SPDXID: SPDXRef-643e0e1ffc2e8a3978669142b4c1c0db FileChecksum: SHA1: 4f8dbe8fb8c00b97466bb46e98d55d7c1a456c1b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FakeQuantizationLayer.hpp SPDXID: SPDXRef-aafac79bc7d40b0f0017e8a4a8186788 FileChecksum: SHA1: 0d80473518293f537ccdd9947f6509aa59094b14 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FillLayer.cpp SPDXID: SPDXRef-ffb042a79dbc8281bbe43433a5aaac4a FileChecksum: SHA1: 1338e167f2fe5b1049794b1005d7790b642e7aa2 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FillLayer.hpp SPDXID: SPDXRef-d4717fc7554f5f536e35bc412ba779ac FileChecksum: SHA1: 18465250d6cc5e66c943c96fa0f8d105ad40a669 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FloorLayer.cpp SPDXID: SPDXRef-1677eec4470f8a38ba6cea8bfaba2580 FileChecksum: SHA1: 958001409bf5539fc188494086911089cdce3734 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FloorLayer.hpp SPDXID: SPDXRef-5901de01741211f26858aaa800ad6234 FileChecksum: SHA1: 88b1dfcf1e31b13a3059f4910f6d28f6a9b74ce4 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FullyConnectedLayer.cpp SPDXID: SPDXRef-0d0b45dfb438d347d92be515367dfbe0 FileChecksum: SHA1: 78756d9006f43771a308b5e8190b5232d45abea6 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/FullyConnectedLayer.hpp SPDXID: SPDXRef-0fa42f5d62e27184e79c2d0773f8c13e FileChecksum: SHA1: 78f2b84e58fe0db9ce781c2a257c51604ff994cd LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/GatherLayer.cpp SPDXID: SPDXRef-21f5d85b410ddb634344828d831eedd0 FileChecksum: SHA1: 2d6f5aeb09da91baa2b46aa6a2619619f14ad89a LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/GatherLayer.hpp SPDXID: SPDXRef-3022b7bbfe03d2f86d0325f1b970154b FileChecksum: SHA1: ae951fabb8c9eabcddc4d00b90627988445a94be LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/GatherNdLayer.cpp SPDXID: SPDXRef-dd822eaa74957781dd56182d0ed06a6c FileChecksum: SHA1: ab7d5a11ddd24a7eeb0f6766985b8cd833c99297 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/GatherNdLayer.hpp SPDXID: SPDXRef-83e041096e65e0db574c0a6a79e2a5fa FileChecksum: SHA1: 5c7aaeaf91d0c848f4ce9acbb217ea53824a7d70 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/InputLayer.cpp SPDXID: SPDXRef-70df466c875d66b91255f57fe2fea1ba FileChecksum: SHA1: b726691b8f82e9570bb411ae4097848b5069a4df LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/InputLayer.hpp SPDXID: SPDXRef-96ca34722e202a1a92ac80f9fd85e990 FileChecksum: SHA1: 5c0e2fc348d7fec775220d6ea4251db526a31ff1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/InstanceNormalizationLayer.cpp SPDXID: SPDXRef-45d36224db0009ac9ef1dc641fd0b406 FileChecksum: SHA1: dd9e3eb765aa5e17709f68aadf82f75a2dc92f1f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/InstanceNormalizationLayer.hpp SPDXID: SPDXRef-14014b1f92ef68fe9b1f6f5446402bdb FileChecksum: SHA1: 75480a0757fe7231010c52f0d493635a19716017 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/L2NormalizationLayer.cpp SPDXID: SPDXRef-5113ff2aade07edff72b78537d641629 FileChecksum: SHA1: 137fba8e163885d68f927d04a2b365f48c471ff4 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/L2NormalizationLayer.hpp SPDXID: SPDXRef-b0fc78a05c84a059abef171053795381 FileChecksum: SHA1: 5faa47bc927af5f7e572f33bb240fe7131829a16 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LayerCloneBase.hpp SPDXID: SPDXRef-a1bcdd433f3122d3b2893070dc3166f2 FileChecksum: SHA1: 45d859ca5e050728d419e39afd3db181ecb737d8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LayerWithParameters.hpp SPDXID: SPDXRef-82974e5756642587053820a074343045 FileChecksum: SHA1: 3eac421a7aefb876390f2b439b36d18b842d1e98 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/armnn/layers/LogSoftmaxLayer.cpp SPDXID: SPDXRef-4418cabcf35591c1be5b7041bc4843a4 FileChecksum: SHA1: 814714e400bde30f6c1bae1e813f03b84c3a11bd LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LogSoftmaxLayer.hpp SPDXID: SPDXRef-e17fde662f18c286e47ff29bcdc4035b FileChecksum: SHA1: 394b068427f783f0819ac272e27cbbbe17d02dde LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LogicalBinaryLayer.cpp SPDXID: SPDXRef-b8477159a2d10c1d723311f6a14851de FileChecksum: SHA1: 7136a161ed6cff12e78c1da0db95d351b0e2b12e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LogicalBinaryLayer.hpp SPDXID: SPDXRef-7adb9c97b80bf9c7d3744dfd86243cdf FileChecksum: SHA1: 468848907cea0cb5af0f68a8fb68e62db23b0bf7 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LstmLayer.cpp SPDXID: SPDXRef-d977601b4b231eee09059d540e56e0b1 FileChecksum: SHA1: e8dcfd4da986c41cc3b2b6b8de7d5dca37f2ed26 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LstmLayer.hpp SPDXID: SPDXRef-e30c9e79c98a290580b7830d6a4dbd29 FileChecksum: SHA1: 7d66c7446237ec18723795a6288454cca5656426 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/LstmParameters.hpp SPDXID: SPDXRef-ef251b376c4fdeafe85f2f59f0e327b5 FileChecksum: SHA1: 34030fd4b34d42caa262b5bbd50db6247e6fac16 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MapLayer.cpp SPDXID: SPDXRef-3d4271a25f28192cc75bbc410cc93a29 FileChecksum: SHA1: c493dfa07a2c3ac44c04b11ea523a83190f190a2 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MapLayer.hpp SPDXID: SPDXRef-50223a6c2b4bc6cdae12af40375c85eb FileChecksum: SHA1: 16269103d04e2217b1fab3558c970b8f0e9fd61e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MaximumLayer.cpp SPDXID: SPDXRef-67a80b3dbb5a98abf9a2d0f5af5e8f5e FileChecksum: SHA1: 6852fb5776cc0c01869f1109804027f9a97e7c81 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MaximumLayer.hpp SPDXID: SPDXRef-a2c8ce8ddd767bbd0feb4ee3d4b6cdf8 FileChecksum: SHA1: 445e23d5672a389ba7108110a23330c836af2691 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MeanLayer.cpp SPDXID: SPDXRef-4a5559009e6c379aa8ad9073792e2674 FileChecksum: SHA1: a032f6fe48a970f2a3a7281c480182ffec61eb1b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MeanLayer.hpp SPDXID: SPDXRef-26b5426bdc6faa3641c02c365ad0868b FileChecksum: SHA1: 494e9653b1a6bf14dd9bdd515df2b1108ed39c60 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MemCopyLayer.cpp SPDXID: SPDXRef-77db75c556e78dea668e0877b8de39f9 FileChecksum: SHA1: ac04213fba627042dd1975d102a14d8ca07f3bc6 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MemCopyLayer.hpp SPDXID: SPDXRef-449d02a1336495e6d27b81d314415d95 FileChecksum: SHA1: 188897b556a0fcae07d64251b7e73715d1f86986 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MemImportLayer.cpp SPDXID: SPDXRef-7b1761a0e8e579fd506f7a3a054a900b FileChecksum: SHA1: fa544475a733610b458e3313450b8d1b8ddc631e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MemImportLayer.hpp SPDXID: SPDXRef-8fb341c07d81eca71d4c2ef948860846 FileChecksum: SHA1: 5238fa4c299439a7266204e5e38fabc984dc277f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MergeLayer.cpp SPDXID: SPDXRef-c387fc195142d9b23a2550d3be0b9ae8 FileChecksum: SHA1: f3ea571109cf991c3dd7dfa442fc6bd7fd1370c0 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MergeLayer.hpp SPDXID: SPDXRef-d37b6fa0840411c3fb37295624003cd7 FileChecksum: SHA1: b615cc2ff5f2c7ead193f41c5b4d9bb802e549cf LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MergerLayer.hpp SPDXID: SPDXRef-8d3705a850005f67342e7b23a20903c9 FileChecksum: SHA1: d0bbaf41bbdeb0398bf943f603369411e344a0c3 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MinimumLayer.cpp SPDXID: SPDXRef-b1a12e660154665d988d249407198b80 FileChecksum: SHA1: 4ce9d4d128de2de2489b26e17f8a55b49b6ac99b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MinimumLayer.hpp SPDXID: SPDXRef-a5789d776e359440e023ebdee6cfc2aa FileChecksum: SHA1: f78c7de19871e62feb1f496964fb3a03aed6eca3 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MultiplicationLayer.cpp SPDXID: SPDXRef-a46031c3d412b08ead55bfcb78dcafbd FileChecksum: SHA1: 93890b40cbcdd3bd073fb0a11538a5952ccd6660 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/MultiplicationLayer.hpp SPDXID: SPDXRef-7e4ae9750c550944009c6a953ee38913 FileChecksum: SHA1: 9417329f6b866b5f12b23156955f7a3b1594f5ed LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/NormalizationLayer.cpp SPDXID: SPDXRef-617b0ba70f55d9e288142c77e935f3e4 FileChecksum: SHA1: ba5ee6199be96822c7f08aaac721568e302d0c95 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/NormalizationLayer.hpp SPDXID: SPDXRef-cb35a2c81e0600c7ebd529317b2d608b FileChecksum: SHA1: c3572fc70795042947b8b7e5e71facaa6078d615 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/OutputLayer.cpp SPDXID: SPDXRef-a030e81586139348bed8d6b1211e90f7 FileChecksum: SHA1: d7f92214be55e9ee16a62a20856798a485064a7d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/OutputLayer.hpp SPDXID: SPDXRef-fc68a320ddd8f4289b1c3f6faf2e5167 FileChecksum: SHA1: 8df66bb2b9f7dedbec1d740c7f0e390499117d02 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PadLayer.cpp SPDXID: SPDXRef-920404bc1ab3c597a02fc69d6bc28589 FileChecksum: SHA1: f012578e7f9ce2bdd9b3f48981f4d43d292a2195 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PadLayer.hpp SPDXID: SPDXRef-4dcb94bafc65de4d880f53bf2ee41b53 FileChecksum: SHA1: f2a0868ff48dd6d44d5ddf7820d02c5afbd4a14b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PermuteLayer.cpp SPDXID: SPDXRef-70b2259bd66c3666de55b1c179b11c57 FileChecksum: SHA1: f1b4a9eace19962c69a252e642d2fef0e616a1d9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PermuteLayer.hpp SPDXID: SPDXRef-681ffbb7c9a792e9300cb0be0fa2c144 FileChecksum: SHA1: f0e5da93451ef2372d8ed94c6b3bb87ec57e23fa LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Pooling2dLayer.cpp SPDXID: SPDXRef-2617e9c119c11734058c8f4e0e5a1014 FileChecksum: SHA1: c6c98c53492425ec9d8680dee56bd65faa4809e5 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Pooling2dLayer.hpp SPDXID: SPDXRef-b1a1aaf270a1e004a4767d7edb72f70b FileChecksum: SHA1: 8a8cfedc6f8170e1482f85921d8ad368e3ad27be LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Pooling3dLayer.cpp SPDXID: SPDXRef-3d2f82b24dbdb839030f3fb8e6b6f670 FileChecksum: SHA1: d3c2d38c5cf633b3f8216ce269e8f0f592b93bca LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/Pooling3dLayer.hpp SPDXID: SPDXRef-f1b16c54510d70ae90160af8cba356bf FileChecksum: SHA1: 52be7a7e814dae01aa49c733babb2650bf29d2f2 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PreCompiledLayer.cpp SPDXID: SPDXRef-f536e48c9727ae37fd463bd0cf0d890f FileChecksum: SHA1: f510ea234567eaa306b21c07e0c737dc40d1aed3 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PreCompiledLayer.hpp SPDXID: SPDXRef-e0bc475f36a0953926a5462e4486a8bc FileChecksum: SHA1: 58af43fc509913ec567150d2936d724dae3d7fa1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PreluLayer.cpp SPDXID: SPDXRef-c8a73f7e85ce916d0f79abc20bf041b1 FileChecksum: SHA1: 848926e5d176d52ee054e41ac4cac04bcf149f7f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/PreluLayer.hpp SPDXID: SPDXRef-59e708e9fa9dc3c58fdf4605bfc27b4c FileChecksum: SHA1: f2d93184364119f9f41ca9ac05397a74f2cff715 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QLstmLayer.cpp SPDXID: SPDXRef-f775ff5acd00c3535c8981d5042cd9ce FileChecksum: SHA1: 0bc9ff031d68db91d37a8ff31846271436f82042 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QLstmLayer.hpp SPDXID: SPDXRef-061b724c148e28f991c4e237adc7c2fe FileChecksum: SHA1: c36693cf208ba664f700fc42042cc80e61565222 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QuantizeLayer.cpp SPDXID: SPDXRef-0f79a4b9917e3f13360b4e042a976288 FileChecksum: SHA1: 1d741b2c92eb95c8bd95428672c0c2548478da5c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QuantizeLayer.hpp SPDXID: SPDXRef-27e01c37626591d7aef0a8e2522fe51c FileChecksum: SHA1: af8141579350b34ef560beb7efb520870307009b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QuantizedLstmLayer.cpp SPDXID: SPDXRef-bd9b6338e6607a1f90e27d0ea69f99a2 FileChecksum: SHA1: 5b5943bd633a058fb40cd47a4bf40487be6d63ae LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/QuantizedLstmLayer.hpp SPDXID: SPDXRef-d8570a310f9f0a5c082bbcebd00e245e FileChecksum: SHA1: 2216cc017c54891c70f0f9492f125bff5f7e3490 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/RankLayer.cpp SPDXID: SPDXRef-1251a6dca6649eee23f5828e4c6048a7 FileChecksum: SHA1: 5b9b2599cdf213f6813fa0886cbf830b824340ac LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/RankLayer.hpp SPDXID: SPDXRef-917774ebca102b2e42dacab1c86a380b FileChecksum: SHA1: c599419628d8eb044f5abbae3f8a96b7a4520885 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ReduceLayer.cpp SPDXID: SPDXRef-3cfffaf79a0e0ca7aea946d5f850e8bb FileChecksum: SHA1: b870c5e5581affbdaf69a0a42375f40318f5f7e8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ReduceLayer.hpp SPDXID: SPDXRef-d5ff86531b540f5736ee8f114a7c3f79 FileChecksum: SHA1: 2492047faa3f368ce90823a91eeedce5b03de036 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ReshapeLayer.cpp SPDXID: SPDXRef-30fbe21ae8c3bb9d4d61807227cfe561 FileChecksum: SHA1: 5871375ec8222866c867256c40a873ca435f85bd LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ReshapeLayer.hpp SPDXID: SPDXRef-47e0b2d2e9f33cfedd3560ef81d5fe04 FileChecksum: SHA1: 3862b26015f7dd8a6ccc3baae918431089bb274e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ResizeLayer.cpp SPDXID: SPDXRef-d2126e659e47cbce0c17b172549a063e FileChecksum: SHA1: e303d6202fc74210122cd24b18cdb31ba70ccda1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ResizeLayer.hpp SPDXID: SPDXRef-16d87a7e9c8e40cbeda02cc9cde5e3a7 FileChecksum: SHA1: 53a812be49b56321d558e0d77c280fc736a8e8b8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/RsqrtLayer.cpp SPDXID: SPDXRef-01672cdb760694eb9835d3deac6ce53a FileChecksum: SHA1: 418fd70a1aee1e35fa7a782d84b37c1b7cd12528 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/RsqrtLayer.hpp SPDXID: SPDXRef-037fae5b7dc3077c3901e21f97bfabad FileChecksum: SHA1: 9ec5ed22d8b6e6f89ea50902e9764c3bc9ff9dd9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ShapeLayer.cpp SPDXID: SPDXRef-9a50c80c85adbd110eee66f5778d427e FileChecksum: SHA1: 7bbd89995a05035a8d06e02b8921774ff02c303f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/ShapeLayer.hpp SPDXID: SPDXRef-73273140c3e31f7a27f6458f89d7e97a FileChecksum: SHA1: 00e17b2b17fde88d8040a4602dd77e6faf20bf06 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SliceLayer.cpp SPDXID: SPDXRef-1f4d489bf90b3c98516f40dd4713fb3d FileChecksum: SHA1: 30019c0dda86ecb8f7334a05daa265087527fa03 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SliceLayer.hpp SPDXID: SPDXRef-52885c33731258dc6a6ef2aeaece1575 FileChecksum: SHA1: d46f93ea79e530f76d2de3e956b20cf0a79d2879 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SoftmaxLayer.cpp SPDXID: SPDXRef-09deba9ce72df7b2f9d15ea47c04c8eb FileChecksum: SHA1: d949dbeea6af506a6a521fe1b758d6359b8b44db LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SoftmaxLayer.hpp SPDXID: SPDXRef-be091217d1ed9fbda558dbcfe6a36609 FileChecksum: SHA1: 24ee0770b8b2f9522ecb2be523d253cfd00ab95d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SpaceToBatchNdLayer.cpp SPDXID: SPDXRef-0ef1ec22957a356cac2712b5f0b5af6d FileChecksum: SHA1: ca5b86b2df1696638129e7a8db2546b5d9106941 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SpaceToBatchNdLayer.hpp SPDXID: SPDXRef-46bc4b6d841cc8a3a84adb10e8feec0d FileChecksum: SHA1: 23dad7522624d28fd256079a2453019e3ca4adb9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SpaceToDepthLayer.cpp SPDXID: SPDXRef-5e9e190f5cfaa2f8decf360157edea5b FileChecksum: SHA1: 3c3e45c6f990b4940f473ce7f2ca688d94a4bc99 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SpaceToDepthLayer.hpp SPDXID: SPDXRef-bc83a3af86350dd6d25d5a28700d9e2b FileChecksum: SHA1: 6a5a06fb61811211c0c01c47ec6e9b13377eaa31 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SplitterLayer.cpp SPDXID: SPDXRef-db784ccd99ca547c643904db00e4ddb3 FileChecksum: SHA1: 95b15ead3eee5524fb81715c745d3d5b54c0cd01 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/SplitterLayer.hpp SPDXID: SPDXRef-bc861b1faa042975bb4237ba76e16594 FileChecksum: SHA1: 602cdeaabc343e7eb3dfd9963e12fd3be0eff52c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. 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FileName: ./src/armnn/layers/StandInLayer.hpp SPDXID: SPDXRef-8631a6c9fff531d51a53fac9aa8dc589 FileChecksum: SHA1: 5fd038c2599201ee29d3d9abec0ef3f76d2449e1 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/StridedSliceLayer.cpp SPDXID: SPDXRef-c8093a05f88a7291b153443a2e86bf2e FileChecksum: SHA1: dea20edc60ba4516d5d262f61309da5d9193562f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/armnn/layers/StridedSliceLayer.hpp SPDXID: SPDXRef-477511e3aaf3967b99aeff4bde284d46 FileChecksum: SHA1: a8d007c586791ea8aca4924224e4b4e245b9659c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/ChannelShuffleTestImpl.cpp SPDXID: SPDXRef-a6d23087347ea211b2035e9f1f6ef37e FileChecksum: SHA1: d44308c66f45e382cbefebb43d95aaa4f1abde25 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ChannelShuffleTestImpl.hpp SPDXID: SPDXRef-74f3a9258a4eb2759b97671f2b33c0f9 FileChecksum: SHA1: f7a909d4de749f1a75a78f740a2fa1766f79cd57 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ComparisonTestImpl.cpp SPDXID: SPDXRef-974d006525d8ce53c004bd0508355fa1 FileChecksum: SHA1: dd6607ad083dfcd695639b74039ed158b365e482 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ComparisonTestImpl.hpp SPDXID: SPDXRef-75c573fd15f7ad159b3245d218415cbe FileChecksum: SHA1: 2fb42702e7d2552a0ad1d1adb3502ae03ab0c2ec LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConcatTestImpl.cpp SPDXID: SPDXRef-fdd67b5e016f98007f84e30b6e239e7f FileChecksum: SHA1: 8035612ca4f17834a583f421d5bc71284c78fb71 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConcatTestImpl.hpp SPDXID: SPDXRef-36b84c5f182e34566a03a8fae04a4e85 FileChecksum: SHA1: 120a6f9164590d97f4bca967a90796682a4ac423 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConstantTestImpl.cpp SPDXID: SPDXRef-e6140658206acdeb42f3001d443a90b0 FileChecksum: SHA1: faeba98ce2c4736ece19cbf0b792f5e303b0caff LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConstantTestImpl.hpp SPDXID: SPDXRef-21a1313b3520189370a237dadc63bd28 FileChecksum: SHA1: 94ed2c6582b23390880dfe7b94f4174ff49e42c6 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Conv2dTestImpl.cpp SPDXID: SPDXRef-28e9de4d792d746ce6c63025d7acf51e FileChecksum: SHA1: a783d320c567a6a1afa868e9bf999b17cf523dca LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Conv2dTestImpl.hpp SPDXID: SPDXRef-5672b240488dc6806451c92bf38261ae FileChecksum: SHA1: 6b588a0a64c702dc1e5a8ab53746de04b34ec87a LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Conv3dTestImpl.cpp SPDXID: SPDXRef-66a3240a34c1177f67849a3ddc946950 FileChecksum: SHA1: c798e36fcc33c684c3d96852c60c3817a8c001de LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Conv3dTestImpl.hpp SPDXID: SPDXRef-8a4b79abdb24d0aef680c77788783f06 FileChecksum: SHA1: dd614d8b221159c6e8623a7c4f40a8930f429c9d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertBf16ToFp32TestImpl.cpp SPDXID: SPDXRef-e6ffe13a8e84128a992cc0adade430c7 FileChecksum: SHA1: 295b8edc1e6187cff9a6399034cc31028eac179d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertBf16ToFp32TestImpl.hpp SPDXID: SPDXRef-e2303bfb1aed6b6839b602ad574a88d8 FileChecksum: SHA1: a560e4866490e29a874edf5cb87a853928ac55da LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp16ToFp32TestImpl.cpp SPDXID: SPDXRef-df7171868a8214dec5e6ffe19b19490b FileChecksum: SHA1: 7c4cfc896b5ab6b577dc46b3d0ed515625708940 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp16ToFp32TestImpl.hpp SPDXID: SPDXRef-f2993d88b14e629e4e06430677310960 FileChecksum: SHA1: 67b396d0575d7666dad05e4734be8e6a5a9bae2c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp32ToBf16TestImpl.cpp SPDXID: SPDXRef-442001dbe522260b8b108186da733569 FileChecksum: SHA1: ac5652351a98289a8cff19d3bf40c998feffbc6a LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp32ToBf16TestImpl.hpp SPDXID: SPDXRef-9cb4e1356b16a6c27af0baaf1078397a FileChecksum: SHA1: ad8f13a03af3e250ccb39fac097d1f9680518fdd LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp32ToFp16TestImpl.cpp SPDXID: SPDXRef-aab70103d66041a1b6be7e773e7da801 FileChecksum: SHA1: b431146c7d14da9cd9630782becfee2472ddffbc LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ConvertFp32ToFp16TestImpl.hpp SPDXID: SPDXRef-9a4d633884573140a373b063533162af FileChecksum: SHA1: f0eac8bfff1b20f62b19caae8d059955f7456291 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DebugTestImpl.cpp SPDXID: SPDXRef-511ab7ce85e73610ea3cdc120c82860a FileChecksum: SHA1: 286e7552a0e86c4624f448ee4192fc3ecb237846 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DebugTestImpl.hpp SPDXID: SPDXRef-1f4ded710fe84c45fe75c123fcc30b31 FileChecksum: SHA1: 74ca654275a08d3185bdd3be7bc140b87ea63034 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DepthToSpaceTestImpl.cpp SPDXID: SPDXRef-501ac7f8c89cbc085791b16bf0d6bd92 FileChecksum: SHA1: 62d27414fbc1fea336987f41c6384140fae159fd LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DepthToSpaceTestImpl.hpp SPDXID: SPDXRef-9b8003fc0a64ea17624d4cd21f86470a FileChecksum: SHA1: 58fa0f0b119e62cf928e9a2668ce23e67c4ad694 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DequantizeTestImpl.cpp SPDXID: SPDXRef-d45100252cefee0134370260ab1a5ca2 FileChecksum: SHA1: 953fedb88fe8918447de3096b3f561e4e76c3527 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DequantizeTestImpl.hpp SPDXID: SPDXRef-a43fb599e520c03e68739f5f79bfc993 FileChecksum: SHA1: 138ab9cb6e61fb173f8e41e3577a29fba37da638 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DetectionPostProcessTestImpl.hpp SPDXID: SPDXRef-86ce88ca6251283f34ba1ee3782fd798 FileChecksum: SHA1: dd7a20261446e69d66a2eaabc10909aa462f0dd7 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DivisionTestImpl.cpp SPDXID: SPDXRef-f4210cd64cb11d1afc2a0c2897452f9e FileChecksum: SHA1: b27804e249a892f88a74d23f0371b2588af95f61 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/DivisionTestImpl.hpp SPDXID: SPDXRef-85906328eecf9fdabfc69acdd8216470 FileChecksum: SHA1: e8bf7d5c61cac20a1292c5f47403ebb846c65600 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ElementwiseTestImpl.hpp SPDXID: SPDXRef-82772f5a8b5be11eac906e12e4237b57 FileChecksum: SHA1: c0446d15ef59d610451a79389acf1011abfb8441 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ElementwiseUnaryTestImpl.cpp SPDXID: SPDXRef-b88b0c48da1d6aba89d94ba308638e69 FileChecksum: SHA1: d7267533a782c3fc924b8e5efcbbc0dcda255491 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ElementwiseUnaryTestImpl.hpp SPDXID: SPDXRef-191c7251a9474ff5902c4e34262d4350 FileChecksum: SHA1: b841a431b0783685591ece4253a69bcb5babd18c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ExpTestImpl.cpp SPDXID: SPDXRef-1ddf24a462b56af37cf1cb0078d8bb42 FileChecksum: SHA1: 37edc64271a8a1c81fd0fc19fdb2e7c936208c8b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ExpTestImpl.hpp SPDXID: SPDXRef-3e83c3481e1bcfa1f7f79a36f9e232fe FileChecksum: SHA1: ab67bfd702406fb87d6bcd6ba50bb7b0eed7d69f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FakeQuantizationTestImpl.cpp SPDXID: SPDXRef-b24a2d113be2c68e4b66e88ac323c11c FileChecksum: SHA1: 1049289b1873a780b37aac008614867125c3b0cc LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FakeQuantizationTestImpl.hpp SPDXID: SPDXRef-c44a92e039a38a36bfa267a90f6183d5 FileChecksum: SHA1: 9bffd7a46fa07dcbbb4486d476a8d6e64bc3f1ba LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FillTestImpl.cpp SPDXID: SPDXRef-bf001dc0eae05b9da9c24ae56db4f440 FileChecksum: SHA1: 99fbb10d424107ec4143a4736ad417eed717af78 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FillTestImpl.hpp SPDXID: SPDXRef-8be84bbc06f02a893a3545e653708b1e FileChecksum: SHA1: cd57f1b165cc64a94c0cc1cafa87d2b4bbeb12b9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FloorTestImpl.cpp SPDXID: SPDXRef-1831b4525969d1d39de744756e27f9a4 FileChecksum: SHA1: 1824cfec2aba25e8e998066a3d1da1cc61830c80 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FloorTestImpl.hpp SPDXID: SPDXRef-5e5b2328ec9979b354cd18edb1680784 FileChecksum: SHA1: 1623b35678db8023474c162af33c0bfc90429e8d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FullyConnectedTestImpl.cpp SPDXID: SPDXRef-286087eee6282e0786f982aa8a7ff209 FileChecksum: SHA1: 1c139c752e4a9d240f931ce9545d2a4954efeccb LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/FullyConnectedTestImpl.hpp SPDXID: SPDXRef-7bda5af556d935564e2ceacdcc37f6a5 FileChecksum: SHA1: 3daa4dfbc6f189f4bfffdcab4161b59c7501eaaa LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/GatherNdTestImpl.cpp SPDXID: SPDXRef-fee2f7a4f92daa642b53b6288d96bfb0 FileChecksum: SHA1: c5506dfa95a7fdc51f38096c9219b4b58a8b41b4 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/GatherNdTestImpl.hpp SPDXID: SPDXRef-1955cf1807e99d00b41e9702b03dd178 FileChecksum: SHA1: cdcdf8030e790dc56152a018364ccc10c519351f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2022 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/GatherTestImpl.cpp SPDXID: SPDXRef-960b06e2a90822f903e68ba37b9e0ae1 FileChecksum: SHA1: 1ac518877a6e29bc6453dd1304720dbacaf3350e LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/GatherTestImpl.hpp SPDXID: SPDXRef-ac60a99c59d8c979c89137d68881b53e FileChecksum: SHA1: ccd4af77278490b80ff9f6593d598ae882b97278 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/InstanceNormalizationTestImpl.cpp SPDXID: SPDXRef-981040ec422173e115e8af473f35dd67 FileChecksum: SHA1: e2c98130f7b33a04a3406c8f66291aa483bde23d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/InstanceNormalizationTestImpl.hpp SPDXID: SPDXRef-cf9a7063e604d206021629e6f06f1106 FileChecksum: SHA1: e8dad6b1a0c164e597695d507faf97ec7c3813d8 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/L2NormalizationTestImpl.cpp SPDXID: SPDXRef-07bbd884dba8aac37afe644b79267461 FileChecksum: SHA1: 867e0011d5b76bb5ffff1e37d7a5f14b7d20e7d9 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/L2NormalizationTestImpl.hpp SPDXID: SPDXRef-76960fd7f2bcd9044f6aa34751b9813f FileChecksum: SHA1: a7c622f20ca17bb106ab4e8b0936810a31b353c0 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/LayerTestResult.hpp SPDXID: SPDXRef-08a85a0e1ad6c4d40234e62a5f344a2f FileChecksum: SHA1: c67305f621cdf3a8f59f8bb1c84be7cd5ac8983c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/LogTestImpl.hpp SPDXID: SPDXRef-3670e5aa24d403783dedd348f9754c03 FileChecksum: SHA1: 985fd37f1aa214362276b1786ca428333641c0da LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/LogicalTestImpl.cpp SPDXID: SPDXRef-7209aa2a921f71851cbde505f2f8ef45 FileChecksum: SHA1: 600eba3d59bdca6c12853d8570b9674843fd58b7 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/LogicalTestImpl.hpp SPDXID: SPDXRef-d8df06019420ee0cd6b60ed3e06db2c3 FileChecksum: SHA1: c692fd430484d84368d504c119172808812f6a8a LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/LstmTestImpl.cpp SPDXID: SPDXRef-e81b80ec2500e234fd420be9a221f688 FileChecksum: SHA1: 6091f9019257cffdec488b8444455bd3a60bb03f LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/LstmTestImpl.hpp SPDXID: SPDXRef-63eb0769b3a20557829572ce5d4ebe9a FileChecksum: SHA1: b7f99595d9f0101c475806029bdccf36c3c9ed26 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/MaximumTestImpl.cpp SPDXID: SPDXRef-f227ebd1528c21c47177440c34ca8b3f FileChecksum: SHA1: 60abb0f1b8922e09ed238a8094aee8bf3ce0336d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/MinimumTestImpl.hpp SPDXID: SPDXRef-edfb9135286981e74137c143fe4bfa8a FileChecksum: SHA1: 2ad0d8db477cb0e82cbb96bc16e1cfd85b25de82 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/MirrorPadTestImpl.cpp SPDXID: SPDXRef-fc7624bad3019682bead6f05dc75a354 FileChecksum: SHA1: 6960a3b210c8177dce7038a829aa816a7b109064 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/MirrorPadTestImpl.hpp SPDXID: SPDXRef-3c40670478fed97085eadabae1ea1433 FileChecksum: SHA1: e1ec656ca91aaf8e18069b87bacff84be968e15c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/MultiplicationTestImpl.cpp SPDXID: SPDXRef-709c09fdc0f525b21390c01ef2ed1d23 FileChecksum: SHA1: 92f1938abad34c5e571a58db1a26c1091a65d759 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/MultiplicationTestImpl.hpp SPDXID: SPDXRef-c8fbabdcac65e65e0043b2cd76d1c399 FileChecksum: SHA1: ab8a0f3512c41da589e673a90e06e24ee3c3b3bf LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/NegTestImpl.cpp SPDXID: SPDXRef-f244fbf943cbc383f129d30e1d7a53a0 FileChecksum: SHA1: 4073510366e7b5bcf10f84ce073aaa84a19834dc LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Arm Ltd. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/PadTestImpl.cpp SPDXID: SPDXRef-f28e0efab22d3ff9f7ca3a425b0c5959 FileChecksum: SHA1: f9156cd95390d77a6f7594495313d205f9317b48 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/PadTestImpl.hpp SPDXID: SPDXRef-906f340f4243d5a97b9424d015c13493 FileChecksum: SHA1: cc8b6722945f07405152d10afb4eca82c19a39e4 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/PermuteTestImpl.hpp SPDXID: SPDXRef-02a3679f2a8da502d644f99fdb96241a FileChecksum: SHA1: d52b27ae9d5b8eb587a9671aa264de40c1af4602 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Pooling2dTestImpl.cpp SPDXID: SPDXRef-bd12bd47e530ee9a01ab7afa81c3d6b4 FileChecksum: SHA1: 86a38b18a3f2d97196af2dc99459689fed312ae5 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Pooling2dTestImpl.hpp SPDXID: SPDXRef-62d2b181e2d8b178911eef6a10f4573f FileChecksum: SHA1: f9b7037b1e881b94ba276267fcf8e1789ac6ef16 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/Pooling3dTestImpl.cpp SPDXID: SPDXRef-e90c90ab58f584c593f327f8248f7cbc FileChecksum: SHA1: a71077eb54ac0e40e50d3994dfa6589ae11a411c LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/ReduceProdTestImpl.cpp SPDXID: SPDXRef-2ffa86f2b39682ce217d39d18bd6e75e FileChecksum: SHA1: 2fa7c5b93b737b1fa44dce1012a944752e8bbfdc LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ReduceProdTestImpl.hpp SPDXID: SPDXRef-d06ebaaf09dceece9f3d5ba4ad78a751 FileChecksum: SHA1: 1447e5e490fd12e0cbddff8d6c8b551ac8d4b54b LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2021 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ReduceSumTestImpl.cpp SPDXID: SPDXRef-dc827d4dcbc2311bcc13ebfeb139eebf FileChecksum: SHA1: 390d091f7a41d71b51b80e326aae07d6defde77d LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/ReshapeTestImpl.cpp SPDXID: SPDXRef-8064f2a2eddba2214314f497ec392dc9 FileChecksum: SHA1: df5e0d177aaa8e69ada04fce201bf4a98fbbcd27 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ReshapeTestImpl.hpp SPDXID: SPDXRef-6b1c9a715dbbfb02f4687518f29fe4e1 FileChecksum: SHA1: f68a54463d42e040d357bb9bcecbe43e66d66b89 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/ResizeTestImpl.cpp SPDXID: SPDXRef-f1367b484912363cfc024a2db802b0d5 FileChecksum: SHA1: 4f61804257a2317a1605cd1c693113ed88f16f97 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2019 Arm Ltd and Contributors. All rights reserved. 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FileName: ./src/backends/backendsCommon/test/layerTests/SoftmaxTestImpl.cpp SPDXID: SPDXRef-d5f585a41fbaf802020069228afea3f5 FileChecksum: SHA1: 00582340c2e64e331e4459e189f1cab6fa4329b2 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/SoftmaxTestImpl.hpp SPDXID: SPDXRef-a20dc238eebfa9bd2d62d4aaed0468e7 FileChecksum: SHA1: e4e163e84c33f54d79f43c140be3be5660b57e41 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. FileName: ./src/backends/backendsCommon/test/layerTests/SpaceToBatchNdTestImpl.cpp SPDXID: SPDXRef-f0478a40f7df77d9d3e136ee065452d7 FileChecksum: SHA1: 81421d4218fba8e72114724682cfa6c5d0146396 LicenseConcluded: NOASSERTION LicenseInfoInFile: MIT FileCopyrightText: Copyright © 2017 Arm Ltd and Contributors. All rights reserved. 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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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* [Quick Start Guides](#quick-start-guides) * [Pre-Built Binaries](#pre-built-binaries) * [Software Overview](#software-overview) * [Get Involved](#get-involved) * [Contributions](#contributions) * [Disclaimer](#disclaimer) * [License](#license) * [Third-Party](#third-party) * [Build Flags](#build-flags) # Arm NN **Arm NN** is the **most performant** machine learning (ML) inference engine for Android and Linux, accelerating ML on **Arm Cortex-A CPUs and Arm Mali GPUs**. This ML inference engine is an open source SDK which bridges the gap between existing neural network frameworks and power-efficient Arm IP. Arm NN outperforms generic ML libraries due to **Arm architecture-specific optimizations** (e.g. SVE2) by utilizing **[Arm Compute Library (ACL)](https://github.com/ARM-software/ComputeLibrary/)**. To target Arm Ethos-N NPUs, Arm NN utilizes the [Ethos-N NPU Driver](https://github.com/ARM-software/ethos-n-driver-stack). For Arm Cortex-M acceleration, please see [CMSIS-NN](https://github.com/ARM-software/CMSIS_5). Arm NN is written using portable **C++14** and built using [CMake](https://cmake.org/) - enabling builds for a wide variety of target platforms, from a wide variety of host environments. **Python** developers can interface with Arm NN through the use of our **Arm NN TF Lite Delegate**. ## Quick Start Guides **The Arm NN TF Lite Delegate provides the widest ML operator support in Arm NN** and is an easy way to accelerate your ML model. To start using the TF Lite Delegate, first download the **[Pre-Built Binaries](#pre-built-binaries)** for the latest release of Arm NN. Using a Python interpreter, you can load your TF Lite model into the Arm NN TF Lite Delegate and run accelerated inference. Please see this **[Quick Start Guide](delegate/DelegateQuickStartGuide.md)** on GitHub or this more comprehensive **[Arm Developer Guide](https://developer.arm.com/documentation/102561/latest/)** for information on how to accelerate your TF Lite model using the Arm NN TF Lite Delegate. The fastest way to integrate Arm NN into an **Android app** is by using our **Arm NN AAR (Android Archive) file with Android Studio**. The AAR file nicely packages up the Arm NN TF Lite Delegate, Arm NN itself and ACL; ready to be integrated into your Android ML application. Using the AAR allows you to benefit from the **vast operator support** of the Arm NN TF Lite Delegate. We held an **[Arm AI Tech Talk](https://www.youtube.com/watch?v=Zu4v0nqq2FA)** on how to accelerate an ML Image Segmentation app in 5 minutes using this AAR file. To download the Arm NN AAR file, please see the **[Pre-Built Binaries](#pre-built-binaries)** section below. We also provide Debian packages for Arm NN, which are a quick way to start using Arm NN and the TF Lite Parser (albeit with less ML operator support than the TF Lite Delegate). There is an installation guide available [here](InstallationViaAptRepository.md) which provides instructions on how to install the Arm NN Core and the TF Lite Parser for Ubuntu 20.04. To build Arm NN from scratch, we provide the **[Arm NN Build Tool](build-tool/README.md)**. This tool consists of **parameterized bash scripts** accompanied by a **Dockerfile** for building Arm NN and its dependencies, including **[Arm Compute Library (ACL)](https://github.com/ARM-software/ComputeLibrary/)**. This tool replaces/supersedes the majority of the existing Arm NN build guides as a user-friendly way to build Arm NN. The main benefit of building Arm NN from scratch is the ability to **exactly choose which components to build, targeted for your ML project**.
## Pre-Built Binaries | Operating System | Architecture-specific Release Archive (Download) | |-----------------------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Android (AAR) | [![](https://img.shields.io/badge/download-android--aar-orange)](https://github.com/ARM-software/armnn/releases/download/v23.08/armnn_delegate_jni-23.08.aar) | | Android 10 "Q/Quince Tart" (API level 29) | [![](https://img.shields.io/badge/download-arm64--v8.2-a-blue)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-29-arm64-v8.2-a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8a-red)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-29-arm64-v8a.tar.gz) | | Android 11 "R/Red Velvet Cake" (API level 30) | [![](https://img.shields.io/badge/download-arm64--v8.2-a-blue)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-30-arm64-v8.2-a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8a-red)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-30-arm64-v8a.tar.gz) | | Android 12 "S/Snow Cone" (API level 31) | [![](https://img.shields.io/badge/download-arm64--v8.2-a-blue)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-31-arm64-v8.2-a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8a-red)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-31-arm64-v8a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8.6-a-purple)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-31-arm64-v8.6-a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8.6-a-sve-grey)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-31-arm64-v8.6-a-sve.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8.6-a-sve2-grey)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-31-arm64-v8.6-a-sve2.tar.gz) | | Android 13 "T/Tiramisu" (API level 32) | [![](https://img.shields.io/badge/download-arm64--v8.2-a-blue)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-32-arm64-v8.2-a.tar.gz) [![](https://img.shields.io/badge/download-arm64--v8a-red)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-android-32-arm64-v8a.tar.gz) | | Linux | [![](https://img.shields.io/badge/download-aarch64-green)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-linux-aarch64.tar.gz) [![](https://img.shields.io/badge/download-x86__64-yellow)](https://github.com/ARM-software/armnn/releases/download/v23.08/ArmNN-linux-x86_64.tar.gz) | **Note: Android 10 testing will be dropped from next release onwards.** ## Software Overview The Arm NN SDK supports ML models in **TensorFlow Lite** (TF Lite) and **ONNX** formats. **Arm NN's TF Lite Delegate** accelerates TF Lite models through **Python or C++ APIs**. Supported TF Lite operators are accelerated by Arm NN and any unsupported operators are delegated (fallback) to the reference TF Lite runtime - ensuring extensive ML operator support. **The recommended way to use Arm NN is to [convert your model to TF Lite format](https://www.tensorflow.org/lite/convert) and use the TF Lite Delegate.** Please refer to the [Quick Start Guides](#quick-start-guides) for more information on how to use the TF Lite Delegate. Arm NN also provides **TF Lite and ONNX parsers** which are C++ libraries for integrating TF Lite or ONNX models into your ML application. Please note that these parsers do not provide extensive ML operator coverage as compared to the Arm NN TF Lite Delegate. **Android** ML application developers have a number of options for using Arm NN: * Use our Arm NN AAR (Android Archive) file with **Android Studio** as described in the [Quick Start Guides](#quick-start-guides) section * Download and use our [Pre-Built Binaries](#pre-built-binaries) for the Android platform * Build Arm NN from scratch with the Android NDK using this [GitHub guide](BuildGuideAndroidNDK.md) Arm also provides an [Android-NN-Driver](https://github.com/ARM-software/android-nn-driver) which implements a hardware abstraction layer (HAL) for the Android NNAPI. When the Android NN Driver is integrated on an Android device, ML models used in Android applications will automatically be accelerated by Arm NN. **For more information about the Arm NN components, please refer to our [documentation](https://github.com/ARM-software/armnn/wiki/Documentation).** Arm NN is a key component of the [machine learning platform](https://mlplatform.org/), which is part of the [Linaro Machine Intelligence Initiative](https://www.linaro.org/news/linaro-announces-launch-of-machine-intelligence-initiative/). For FAQs and troubleshooting advice, see the [FAQ](docs/FAQ.md) or take a look at previous [GitHub Issues](https://github.com/ARM-software/armnn/issues). ## Get Involved The best way to get involved is by using our software. If you need help or encounter an issue, please raise it as a [GitHub Issue](https://github.com/ARM-software/armnn/issues). Feel free to have a look at any of our open issues too. We also welcome feedback on our documentation. Feature requests without a volunteer to implement them are closed, but have the 'Help wanted' label, these can be found [here](https://github.com/ARM-software/armnn/issues?q=is%3Aissue+label%3A%22Help+wanted%22+). Once you find a suitable Issue, feel free to re-open it and add a comment, so that Arm NN engineers know you are working on it and can help. When the feature is implemented the 'Help wanted' label will be removed. ## Contributions The Arm NN project welcomes contributions. For more details on contributing to Arm NN please see the [Contributing page](https://mlplatform.org/contributing/) on the [MLPlatform.org](https://mlplatform.org/) website, or see the [Contributor Guide](CONTRIBUTING.md). Particularly if you'd like to implement your own backend next to our CPU, GPU and NPU backends there are guides for backend development: [Backend development guide](src/backends/README.md), [Dynamic backend development guide](src/dynamic/README.md). ## Disclaimer The armnn/tests directory contains tests used during Arm NN development. Many of them depend on third-party IP, model protobufs and image files not distributed with Arm NN. The dependencies for some tests are available freely on the Internet, for those who wish to experiment, but they won't run out of the box. ## License Arm NN is provided under the [MIT](https://spdx.org/licenses/MIT.html) license. See [LICENSE](LICENSE) for more information. Contributions to this project are accepted under the same license. Individual files contain the following tag instead of the full license text. SPDX-License-Identifier: MIT This enables machine processing of license information based on the SPDX License Identifiers that are available here: http://spdx.org/licenses/ ## Inclusive language commitment Arm NN conforms to Arm's inclusive language policy and, to the best of our knowledge, does not contain any non-inclusive language. If you find something that concerns you, please email terms@arm.com ## Third-party Third party tools used by Arm NN: | Tool | License (SPDX ID) | Description | Version | Provenience | |----------------|-------------------|------------------------------------------------------------------|---------|--------------------------------------| | cxxopts | MIT | A lightweight C++ option parser library | 3.1.1 | https://github.com/jarro2783/cxxopts | | doctest | MIT | Header-only C++ testing framework | 2.4.6 | https://github.com/onqtam/doctest | | fmt | MIT | {fmt} is an open-source formatting library providing a fast and safe alternative to C stdio and C++ iostreams. | 8.30 | https://github.com/fmtlib/fmt | | ghc | MIT | A header-only single-file std::filesystem compatible helper library | 1.3.2 | https://github.com/gulrak/filesystem | | half | MIT | IEEE 754 conformant 16-bit half-precision floating point library | 1.12.0 | http://half.sourceforge.net | | mapbox/variant | BSD | A header-only alternative to 'boost::variant' | 1.1.3 | https://github.com/mapbox/variant | | stb | MIT | Image loader, resize and writer | 2.16 | https://github.com/nothings/stb | ## Build Flags Arm NN uses the following security related build flags in their code: | Build flags | |---------------------| | -Wall | | -Wextra | | -Wold-style-cast | | -Wno-missing-braces | | -Wconversion | | -Wsign-conversion | | -Werror | armnn-23.08/README.md.license000066400000000000000000000001531446772241200155510ustar00rootroot00000000000000# # Copyright © 2018-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/SECURITY.md000066400000000000000000000101401446772241200144370ustar00rootroot00000000000000**Reporting vulnerabilities** Arm takes security issues seriously and welcomes feedback from researchers and the security community in order to improve the security of its products and services. We operate a coordinated disclosure policy for disclosing vulnerabilities and other security issues. Security issues can be complex and one single timescale doesn't fit all circumstances. We will make best endeavours to inform you when we expect security notifications and fixes to be available and facilitate coordinated disclosure when notifications and patches/mitigations are available. **Report** For all security issues, contact Arm by email at [arm-security@arm.com](mailto:arm-security@arm.com). **Secure submission using PGP** We support and encourage secure submission of vulnerability reports using PGP, using the key below. If you would like replies to be encrypted, please provide your own public key through a secure mechanism. ~~~ -----BEGIN PGP PUBLIC KEY BLOCK----- mQINBFr7/RMBEACjHR5QZL/z1t2aLCRNXLE4KJiQmCo7edU5Be+7MTjIJDzZNu68 lNEUYRoLexeayif8eC4T19bUsSbGpxHiYsFFjV8ewLXDyDJRRuaBGPfQ5rn/mE6X Nvu+9Pputr+mB1R3CXcvrNkhmzPkK7zVM15oeyBMhogqPssuT4OeMduQdip8smfK xTMk91RrJTLb+G3eE1tf+81kXBYvzp2e24Sn0/VeYe0IWnBobjVBZk3TmcYxDvz5 Y47fU9V6cNj3Zq4VYrgxuLoFCA2VtetyiFQm5IYa3Bt3SWcAwihr8nbR2HoNdWyA u8wJYYVzSq3hvT5l/IjTHxEcY+6RBq8poDSsftzvX386u9hmw7sJQFlTw6/pUjdr gbsZ2ZzRBzKtU17ercpn4kU6VgVP3WRB5HiTFFkEpZuqAznOYaHbMq4dfd/g7Quq C0VTbWiJnhku2i+g4BdHHRDtIF6U3aVQAfbrDb1LjVTa65p5ULOeY3HRAWtMNtu/ Cj8cD98JDanzXtcnisds8vMQ8LZ6iMFChEnF8K4V0eLw9Ju6CMNiFYY7SEBndD/H M4KcU4li7mROSbJcshgEbe1SYkxdMuI9eY4DNYxl3VjxoPUGzeqXo/ADFKE9bHsi GTyEoij4ku0HspLVKnYHXn/LqHGwEcwjF8zphS+w5cn/e01akYwz5EVSQwARAQAB tB1Bcm0gU3VwcG9ydCA8c3VwcG9ydEBhcm0uY29tPokCTgQTAQgAOBYhBN9zqDwZ RL/vF0ihcdfNKdz4bBRiBQJa+/0TAhsDBQsJCAcCBhUKCQgLAgQWAgMBAh4BAheA AAoJENfNKdz4bBRibK0P/jLlJR/QYypcjb+8BnHT9tCDgcV2KFYXS15VpbSNviN9 Xs/UOnSadoGUMGCXDyb1PRNn98yUn7JlNR9rtsqPRmkpbo5cuw46ehgxjVlfcHnk CttaE8Davx6zo0fyrBib2+oVVW8usi9+uRK4vhhPUicO3oXwzldsVFz+RbpubZxc Bg/CZ+dQ2jMKOv1zDtInOG6OBnbQZRAeiWXgGhcIoPZ4zBQOi8nr0+bLcfvMeZi2 uz6uKnylpXwZbl4ijcG8MKV/ei+7du+SzA9NY0WOT2g3FXDREWUhjKs8bmEZgIx4 QgvDNpxAUThF+TqQ7zrsA8nT8POvDD0MhN/Z+A3QdPTdcaZFaXzIdxbDg+0FKmzu OgtQBH4C01RWrkmZlhO5w7/Qjt0vLlhfyQIL9BW/HeEPtjnH2Hnq8xYnZhlVqJEh FJU7F9sMvyiJiKviobFTd6AmpVkhxhcJ3k2L2C03imTsmUwAoejQCXwiYcOhyQ2t Z9Nk8YIZTEw2urGFi4HSQPwPq2j/2j7ABJ4rlzJvO6vs5ppGkumvzIIP9JnpVXbp wcbK6Ev6KdkX4s14Mzd6Hsd8LpL8t5nHhxUey6G0xKe2eSlHVm5Mlfhoete9UmIZ dzIOZkgTgWXlYXRIxwGQ2Pss7pURtofykvLklq4jcobQuHxurl9cteodETfbWk/J uQINBFr7/RMBEADWZG8eqt5D22g3T7ehnH/T3fuTX8LPUBnODMWGAEUY8uv64To8 46odvrXFgWBgCf0sROEyJchc3SGLyR9S4lJsVJRde3QLN3WZkHlB4pSn4IQHFyQd wsLQi+S9uggHMPlQ6MNvc5n0P3k5bT9fLUmtJWJ3QVjW7k963ZXpzf1zbQJqs30w rlqGUZllfRoYQTfcYxFEaUFhwRJ//skNImWH8Vz+PTnqg2zRtFn3usrBV4GpNvsM 6jy+YEsSvUa7IY8k4wpPzEhIfqDjGbZxFSQ1H1G+mLUL+DD7oGffej/ZoC86TIdM p6ew1rGhJdQBLh9nx+1ADOLWjNo2R0h60u7VR5q/K6V4fwWmeGFipPXZCD92I+nR t/cjznwNyD/6J9YrBMF7mbGrS1TyfLaLt4tpdcBnsgqDTodd5OmG65mroXsg/lNO 7YZdecLZ34krfaLrWTtKkqULXbppB+uQvbVj8p8ONRImn6bZ+iAhnNaH9wJ06ico b1F0imJ2SJWnFr6PzPRr0gPStLgu9wrRKheaORwF/H/HxSyPZxNVxFqu81q518A/ plhub9INQLaxHf/TTjXpqZCcfdNTYUAW8rwbQfW9doSIT4lHY8bJXktb6BsVjkFj PzDeYpXeOoTWetQqsEuTdg/F+qg041QBLtNj9Lr3Vy3StgMciRUIP8m0XwARAQAB iQI2BBgBCAAgFiEE33OoPBlEv+8XSKFx180p3PhsFGIFAlr7/RMCGwwACgkQ180p 3PhsFGLWMA//V/XKrnI2YBh/SptUrgg7knPXva45bb7tGSH1fJg8f/wqycOSFFCY ES45boA5jlQ3z8uw6BYCz5KeOucGhxAMw+x5EDdxZ33ksY5zqXB35WaMXzEwGYYb E113/yhOsTbzu4bBKABSXbJO98MdAWvWpyCpp2MHIR3S9+ycM7/FMZ5xi3czZNRg 9+WZP+7W4qWhJptQ0kBh5C3N/tiltju5WQ2Y7XIn+5dMOJdtseFS7CNerxXZGAtH nfRxaD/4ENdbWOwaVJiVW7+ioUJz09OWgy0gLYSDW+hciDnW1QAaJLpdAbniGZ0S JsTmaZla8JnUKqZPgbFfA2OcnH9H+DWc0pHv17c5tJzTMP7rgirgGRX/U2LOzmFZ 1UxjQj5nn3Oa5frXbIAzb8xKiR0VDaquCM/3sti1AesYiS0Gw0Sqnw8qpFypgFXN CKVgYXppIT+TmbDbNJDOB2UycxeI4vbiBwU8fI4qSpW12WsGdAJt/rx3UsyhZ+02 4aSqDHzhJmtDPQ6lnaKe1fUkC90tgp8loVGmriWQx82jAQMqATVjIklTpE4vm00f ocQIWOKEE90mKNEoV6rNbfl5QevmapTVdV/pmrRBzhbsa1uAUS4HZdH0Nf/OXEyv yYCr2gCFPymkkRYhPr2w5EgbWyzLaBIwqjyIbXaveuB3DYi2Lhbf64I= =EaN7 -----END PGP PUBLIC KEY BLOCK----- ~~~ For more information visit https://developer.arm.com/support/arm-security-updates/report-security-vulnerabilities armnn-23.08/SECURITY.md.license000066400000000000000000000001461446772241200160650ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/build-tool/000077500000000000000000000000001446772241200147245ustar00rootroot00000000000000armnn-23.08/build-tool/README.md000066400000000000000000000703271446772241200162140ustar00rootroot00000000000000# Arm NN Build Tool The **_Arm NN Build Tool_** provides a collection of **parameterized bash scripts** accompanied by a **Dockerfile** for building Arm NN and its dependencies, including **[Arm Compute Library (ACL)](https://github.com/ARM-software/ComputeLibrary/)**. This tool replaces/supersedes the majority of the existing Arm NN build guides as a user-friendly way to build Arm NN from scratch. The main benefit of building Arm NN from scratch is the ability to **exactly choose which components to build, targeted for your ML project**.
The Arm NN Build Tool is tested on **x86_64 (Intel) and aarch64 (Arm) build hosts** for the **Ubuntu** platform. Other host platforms such as Windows and Mac **should** work (with Docker installed), but have not been officially tested.
At present, the tool supports **targeting Linux devices (Ubuntu 20.04) on x86_64, aarch64 and android64** architectures.
We recommend using the Arm NN Build Tool through the use of Docker. However, the scripts may be [executed directly on your machine](#build-arm-nn-without-docker) if desired. **If you already have Docker installed** and want to quickly build the Arm NN Dockerfile with some default build arguments, please follow the [Docker Build Steps](#docker-build-steps). * [Overview](#overview) * [System Requirements](#system-requirements) * [Install Docker](#install-docker) * [Ubuntu / Linux](#ubuntu--linux) * [Windows and Mac](#windows-and-mac) * [Docker Build Arguments Reference](#docker-build-arguments-reference) * [SETUP_ARGS](#setup_args) * [BUILD_ARGS](#build_args) * [Docker Build Steps](#docker-build-steps) * [Build Arm NN Without Docker](#build-arm-nn-without-docker) * [Advanced Usage](#advanced-usage) * [Use custom Arm NN and ACL repository versions during build](#use-custom-arm-nn-and-acl-repository-versions-during-build) * [Additional Docker Build Arguments](#additional-docker-build-arguments) * [Inspect the contents of the Docker Image](#inspect-the-contents-of-the-docker-image) * [Bind Mounts](#bind-mounts) ## Overview The Arm NN Build Tool consists of an official Arm NN **Dockerfile** with associated **scripts** for building Arm NN: 1. **```install-packages.sh```:** builds CMake from source and installs system-wide **apt packages** 2. **```setup-armnn.sh```:** downloads and builds Arm NN **dependencies** (e.g. Flatbuffers, TF Lite, Protobuf) 3. **```build-armnn.sh```:** builds Arm NN and ACL 4. **```common.sh```:** common variables and functions used by ```setup-armnn.sh``` and ```build-armnn.sh``` 5. **```validation.sh```:** validation of common command-line arguments to ```setup-armnn.sh``` and ```build-armnn.sh``` 6. **```docker-copy-to-host```:** helpful script to copy contents of a Docker Image to the host machine A **Dockerfile** is a text document which outlines the instructions for building a **Docker Image**. Running ```docker build``` on the Arm NN Dockerfile will result in a Docker Image that contains: 1. The Ubuntu operating system 2. Installed system-wide packages required by Arm NN 3. Source code for Arm NN and its dependencies 4. The build for Arm NN and its dependencies All scripts except ```docker-copy-to-host.sh``` are used during the ```docker build``` process. The ```docker-copy-to-host.sh``` script creates a temporary [**Docker Container**](https://www.docker.com/resources/what-container/) which is required to retrieve files from the Docker Image. A Docker Container is a **runtime** version of a Docker Image. It can be interacted with through a command-line terminal, like a lightweight virtual machine (VM). The ```docker-copy-to-host.sh``` script is designed to run on the host machine after ```docker build``` to copy the Arm NN build to the host. The **diagram below** outlines the operation of the Arm NN **Dockerfile** and the contents of the resulting **Docker Image** after running ```docker build```. During ```docker build```, the provided **```SETUP_ARGS```** determine which of Arm NN's dependencies to download and build. The **```BUILD_ARGS```** Docker argument determines which components of Arm NN to build. The resulting Docker Image contains the Arm NN build (along with everything required to build it) in the home directory ```/home/arm-user```. There are two directories: **```source```** which contains the source code of Arm NN and its dependencies, and **```build```** which contains the Arm NN build and the builds of each dependency of Arm NN. The **```armnn_aarch64_build.tar.gz``` tarball** in the home directory is a compressed archive of the Arm NN build which is located at ```/home/arm-user/build/armnn```. The home directory also contains the **scripts** mentioned above (not pictured in the diagram), which are copied into the Docker Image during the ```docker build``` process.
Arm NN Dockerfile

**Benefits of using Docker:** 1. Run one ```docker build``` command instead of executing multiple scripts, saving developer time 2. Can easily manage multiple different build configurations at once, each in their own Docker Image 3. System packages are installed in the Docker Image only, isolated from the host machine 4. Build in the exact environment the Arm NN Team used during testing, ensuring consistency in builds 5. Allows Arm NN to be built on a wide range of hosts, as long as they support Docker **Disadvantages of using Docker:** 1. Requires the developer to install Docker on their host machine 2. Requires the developer to get familiar with Docker (this guide should help) 3. Possible incompatibilities/limitations if the host machine's Linux Kernel version is too different than that of the base OS in the Docker Image. This is due to the fact that Docker Containers share the Linux Kernel of the host machine (unlike VM's which each have their own Kernel).
## System Requirements This guide will not provide the system requirements for installing Docker - please refer to the Docker documentation during installation. The built Docker Image has disk requirements of **less than 6GB**, depending on the Arm NN components chosen and whether the build included a cross compile (i.e. building aarch64 on x86_64). Repeated builds may cause the total disk usage to increase beyond 6GB. The ```docker images``` command shows the disk usage of each Docker Image. To view total disk space used by all Docker Images and Docker Containers, use the command ```docker system df```. This Dockerfile was built on a **Ubuntu 20.04 host machine with Docker version 20.10.14**. Other Linux distros such as **Debian** should also work as long as the Docker version is similar to **20.10.14**. The build outputs from this Dockerfile have been tested on an **Odroid N2+ target device with Ubuntu 20.04** installed. The build outputs should also work on newer versions of Ubuntu (and Debian) but this has not been exhaustively tested. To view the system packages that are installed during ```docker build```, please refer to the ```install-packages.sh``` script.
## Install Docker Builds of the official Arm NN Dockerfile have been tested on the **Ubuntu 20.04** host platform. Whilst other platforms have not been tested, Docker should be able to build the Arm NN Dockerfile on other platforms such as Windows and Mac. On **Linux**, we recommend using **Docker Engine** which is used through the command-line interface (CLI). For **Windows and Mac** users, **Docker Desktop** is available which allows the use of the CLI plus a graphical interface.
This guide will **only** provide steps on using Docker through the use of the CLI and not Docker Desktop. ### Ubuntu / Linux For Ubuntu users, we recommend installing **Docker Engine** with the following steps from the Docker documentation:
1. [Uninstall any old versions of Docker](https://docs.docker.com/engine/install/ubuntu/#uninstall-old-versions) 2. [Install using the repository](https://docs.docker.com/engine/install/ubuntu/#install-using-the-repository) 3. [Add user to Docker Unix Group](https://docs.docker.com/engine/install/linux-postinstall/#manage-docker-as-a-non-root-user) (**recommended**: allows running of Docker commands **without ```sudo```**) Similar steps for installing Docker Engine on other Linux distributions can be found by clicking on your distro under the Server table on [this page](https://docs.docker.com/engine/install/#server). ### Windows and Mac We do not officially test the building of the Arm NN Dockerfile on Windows or Mac. However, it's likely that it will work if your system supports Docker. For **Windows**, use the Docker Desktop download link on [this page](https://docs.docker.com/desktop/install/windows-install/). For **Mac** users, please use the Docker Desktop download link on [this page](https://docs.docker.com/desktop/install/mac-install/).
**Note:** we unfortunately cannot provide support for the installation of Docker and/or the use of the Arm NN Dockerfile on Windows and Mac platforms.
## Docker Build Arguments Reference The following describes the ```docker build``` arguments that can be used to customize the Arm NN build. Docker build arguments such as ```SETUP_ARGS``` and ```BUILD_ARGS``` are provided in the ```docker build``` as a ```--build-arg```. ### SETUP_ARGS These arguments are eventually passed to ```setup-armnn.sh``` which downloads and builds Arm NN dependencies. For ease of use (but longer initial docker build), use ```--all``` to have all Arm NN dependencies available for use during Arm NN builds. Repeated docker builds with the same ```SETUP_ARGS``` will skip the setup process (using [caching](https://docs.docker.com/develop/develop-images/dockerfile_best-practices/#leverage-build-cache) of previous Docker build steps). The ```SETUP_ARGS``` string should start and end with **double quotes** ```"```. | SETUP_ARGS | Description | |----------------------------|:-------------------------------------------------------------------------------------| | --tflite-classic-delegate | **flag:** setup dependencies for the existing Arm NN TF Lite Delegate | | --tflite-opaque-delegate | **flag:** setup dependencies for the new Arm NN Opaque Delegate | | --tflite-parser | **flag:** setup dependencies for the Arm NN TF Lite Parser | | --onnx-parser | **flag:** setup dependencies for the Arm NN ONNX parser | | --all | **flag:** setup dependencies for all Arm NN components listed above | | --target-arch= | **mandatory option:** specify a target architecture ```aarch64, x86_64, android64``` | **At least one component** (e.g. ```--tflite-classic-delegate```) must be provided **or** else provide ```--all``` to setup dependencies for all components. **Examples:**
Setup for aarch64 with all Arm NN dependencies:
```SETUP_ARGS="--target-arch=aarch64 --all"``` Setup for aarch64 with the existing TF Lite Delegate and TF Lite Parser dependencies only:
```SETUP_ARGS="--target-arch=aarch64 --tflite-classic-delegate --tflite-parser"```
### BUILD_ARGS The following arguments are given to ```build-armnn.sh``` and define which components of Arm NN to include in the build. The ```BUILD_ARGS``` string should start and end with **double quotes** ```"```. | BUILD_ARGS | Description | |---------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | --tflite-classic-delegate | **flag:** build the existing Arm NN TF Lite Delegate component | | --tflite-opaque-delegate | **flag:** build the new Arm NN Opaque Delegate | | --tflite-parser | **flag:** build the Arm NN TF Lite Parser component | | --onnx-parser | **flag:** build the Arm NN ONNX parser component | | --all | **flag:** build all Arm NN components listed above | | --target-arch= | **mandatory option:** specify a target architecture ```aarch64, x86_64, android64``` | | --neon-backend | **flag:** build Arm NN with the NEON backend (CPU acceleration from ACL) | | --cl-backend | **flag:** build Arm NN with the OpenCL backend (GPU acceleration from ACL) | | --ref-backend | **flag:** build Arm NN with the reference backend
**Should be used for verification purposes only.
Does not provide any performance acceleration.** | | --debug | **flag:** build Arm NN (and ACL) with debug turned on (optional: defaults to off) | | --armnn-cmake-args= | **option:** provide additional comma-separated CMake arguments string for building Arm NN (optional)
String should start and end with **single quotes** ```'```
Please refer to **armnn/cmake/GlobalConfig.cmake** | | --acl-scons-params= | **option**: provide additional comma-separated scons parameters string for building ACL (optional)
String should start and end with **single quotes** ```'```
ACL provide [documentation](https://arm-software.github.io/ComputeLibrary/latest/how_to_build.xhtml#S1_1_build_options) for their build options | **At least one component** (i.e. ```--tflite-classic-delegate```, ```--tflite-opaque-delegate```, ```--tflite-parser```, ```--onnx-parser```) must be provided or else provide ```--all``` to build all Arm NN components.
**A component given in ```BUILD_ARGS``` must also have been given in ```SETUP_ARGS``` previously**, or else Arm NN will fail to build.
**At least one backend** (i.e. ```--neon-backend```, ```--cl-backend```, ```--ref-backend```) must be chosen.
**Examples:**
Build for aarch64 with all Arm NN components, NEON enabled and OpenCL enabled:
```BUILD_ARGS="--target-arch=aarch64 --all --neon-backend --cl-backend"``` Build for aarch64 with the existing Arm NN TF Lite Delegate, OpenCL enabled and additional ACL scons params:
```BUILD_ARGS="--target-arch=aarch64 --tflite-classic-delegate --cl-backend --acl-scons-params='compress_kernels=1,benchmark_examples=1'"``` Setup for aarch64 with all Arm NN dependencies, OpenCL enabled and additional Arm NN cmake args:
```BUILD_ARGS="--target-arch=aarch64 --all --cl-backend --armnn-cmake-args='-DBUILD_SAMPLE_APP=1,-DBUILD_UNIT_TESTS=0'"``` **Example _valid_ combination of SETUP_ARGS and BUILD_ARGS:**
``` SETUP_ARGS="--target-arch=aarch64 --all" BUILD_ARGS="--target-arch=aarch64 --tflite-classic-delegate --neon-backend --cl-backend" ``` **Example _invalid_ combination of SETUP_ARGS and BUILD_ARGS:**
``` SETUP_ARGS="--target-arch=aarch64 --tflite-classic-delegate" BUILD_ARGS="--target-arch=aarch64 --all --neon-backend --cl-backend" ``` The example above is invalid since it tries to build all Arm NN components after **only** building the dependencies required by the TF Lite Delegate.
## Docker Build Steps First clone the Arm NN repo to obtain the build-tool. This automatically downloads the latest release version of Arm NN. ``` git clone https://github.com/ARM-software/armnn.git armnn ```
Enter into the Arm NN build-tool directory where the Dockerfile and associated scripts are located. ``` cd armnn/build-tool ```
Run the ```docker build```, which downloads and builds Arm NN and its dependencies. This process is isolated from the host machine's filesystem and the result is a Docker Image being created.
Dockerfile arguments are provided using ```--build-arg```, the relative path to the Dockerfile is given with ```--file``` and the current directory is given with ```.```
Provide a descriptive name for the Image with ```--tag``` in the form of ```image_name:tag``` (example given below). The backslashes ```\``` tell Bash to expect a continuation of the command on the next line. This example's choice of **[SETUP_ARGS](#setup_args)** and **[BUILD_ARGS](#build_args)** builds all Arm NN components with NEON and OpenCL accelerated backends for aarch64 target. This process should take **less than an hour** with a modern machine but will vary depending on the arguments chosen and host machine specification. ``` docker build \ --build-arg SETUP_ARGS="--target-arch=aarch64 --all" \ --build-arg BUILD_ARGS="--target-arch=aarch64 --all --neon-backend --cl-backend" \ --tag armnn:aarch64 \ --file docker/Dockerfile . ```
Arm NN and all of its dependencies are now built within a Docker Image. Built Docker images can be listed with ```docker images```. ``` docker images REPOSITORY TAG IMAGE ID CREATED SIZE armnn aarch64 cc623174fd98 7 seconds ago 5.02GB ```
A tarball archive of the Arm NN build is located inside the Docker home directory (```/home/arm-user/```), named ```armnn__build.tar.gz```. If the ```--debug``` build flag is provided in the ```BUILD_ARGS``` above, the tarball will be named ```armnn__build_debug.tar.gz```.
The ```docker-copy-to-host.sh``` script will copy a file from the Docker Image (in arm-user's home directory) to the host machine.
The script copies the tarball into a new directory on the host in ```build-tool/docker_output```. It takes two arguments: ```image_name:tag``` and ```filename```.
The filename is a relative path from the home directory created inside the Docker Image (```/home/arm-user/```). ``` ./scripts/docker-copy-to-host.sh armnn:aarch64 armnn_aarch64_build.tar.gz ```
This tarball can now be used for integration in an ML application. The method of extraction is given below.
If the ```--target-arch``` chosen in the arguments above matches the host machine, the build can be tested locally (else copy the tarball to a remote device). ``` cd docker_output # Extract the tarball into a directory called _build # If --debug is enabled, the extracted build directory will be called _build_debug tar -xzf armnn_aarch64_build.tar.gz cd aarch64_build # Set LD_LIBRARY_PATH to the current aarch64_build directory (.) export LD_LIBRARY_PATH=.; ./UnitTests # If the Arm NN TF Lite Delegate is built, we can also run DelegateUnitTests cd delegate # Set LD_LIBRARY_PATH to the current delegate directory (.) and the aarch64_build directory (..) export LD_LIBRARY_PATH=.:..; ./DelegateUnitTests ```
**Note:** Repeated Docker builds may result in an accumulation of unwanted, dangling images. **To remove dangling images** (good practice), run the following command: ```docker image prune```
## Build Arm NN without Docker For ease of use, we recommend that the official Arm NN Dockerfile is used to build Arm NN. If you'd like to build locally on a Ubuntu host machine without Docker, execute the build-tool scripts directly instead. This involves running ```install-packages.sh``` followed by ```setup-armnn.sh``` and ```build-armnn.sh```. The arguments for ```setup-armnn.sh``` and ```build-armnn.sh``` are very much the same as ```SETUP_ARGS``` and ```BUILD_ARGS```. Please use ```--help``` for more specific information. ``` cd build-tool/scripts sudo ./install-packages.sh ./setup-armnn.sh --target-arch=aarch64 --all ./build-armnn.sh --target-arch=aarch64 --all --neon-backend --cl-backend ./setup-armnn.sh --help ./build-armnn.sh --help ```
## Advanced Usage ### Use custom Arm NN and ACL repository versions during build By default, the docker build process (specifically, during ```build-armnn.sh```) will download the latest release versions of Arm NN and ACL. If you'd like to use different versions during the build, check them out in the ```build-tool``` directory on the host.
When providing custom repositories, the following ```docker build``` argument must be provided ```--build-arg BUILD_TYPE=dev```. This will trigger Docker to copy the custom repos into the Docker Image during build. The ACL repo is only required if supplying the ```--neon-backend``` or ```--cl-backend``` BUILD_ARGS options. **Note:** the Arm NN version used for build-tool (Dockerfile and scripts) is not the same version of Arm NN that is used during the build. This means that separate versions of Arm NN can be used for the build-tool and for building Arm NN itself.
If you repeat the ```docker build``` process multiple times (e.g. with different ```BUILD_ARGS```), the setup process will be skipped as long as ```SETUP_ARGS``` remains the same. ``` cd build-tool git clone https://github.com/ARM-software/armnn.git armnn cd armnn git checkout cd .. # custom ACL repo only required when supplying --neon-backend or --cl-backend BUILD_ARGS options git clone https://github.com/ARM-software/ComputeLibrary.git acl cd acl git checkout cd .. # Example docker build with BUILD_TYPE=dev, ran inside the build-tool directory docker build \ --build-arg BUILD_TYPE=dev \ --build-arg SETUP_ARGS="--target-arch=aarch64 --all" \ --build-arg BUILD_ARGS="--target-arch=aarch64 --all --neon-backend --cl-backend" \ --tag armnn:aarch64 \ --file docker/Dockerfile . ```
### Additional Docker Build Arguments #### UBUNTU_VERSION The default base Image used during ```docker build``` is ```ubuntu:20.04```. Building Arm NN with this default image should be sufficient for a wide range of target devices. To use a different Ubuntu base Image, provide ```UBUNTU_VERSION``` during ```docker build``` e.g. ```--build-arg UBUNTU_VERSION=20.04```. #### BUILD_TYPE By default, ```BUILD_TYPE``` is set to ```production```. This means that the latest release versions of Arm NN and ACL are used during builds. To use custom repositories as explained [above](#Use-custom-Arm-NN-and-ACL-repository-versions-during-build), provide ```--build-arg BUILD_TYPE=dev```. #### Additional SETUP_ARGS and BUILD_ARGS The following are additional ```SETUP_ARGS``` and ```BUILD_ARGS``` that can be provided to the ```docker build```. | SETUP_ARGS / BUILD_ARGS | Description | |-------------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------| | --num-threads= | **option:** specify number of threads/cores to build Arm NN and its dependencies with (this defaults to number of online cores on the host)
e.g. --num-threads=4 | | -x | **flag:** enable shell tracing during setup-armnn.sh and build-armnn.sh script execution | #### USER_ID and GROUP_ID By default, the Docker Image creates a user called ```arm-user``` with user/group ID of 1000. This ensures the build outputs can be used by a wide range of users on target devices.
To provide a more specific user and group ID to be associated with the build, provide ```--build-arg USER_ID=XXXX``` and ```--build-arg GROUP_ID=YYYY```.
### Inspect the contents of the Docker Image To inspect the full contents of the Docker Image, the Image must be run as a **Docker Container**. A Container is a runtime version of the Image, like a **lightweight virtual machine** with its own filesystem. The following shows how to run a container with an interactive terminal based on a specified Docker Image ```image_name:tag```. The ID of the generated container in this example is ```4da7c575a95a```. An ```ls``` command shows the contents of the ```/home/arm-user``` directory. ``` docker run --interactive --tty armnn:aarch64 arm-user@4da7c575a95a:~$ ls armnn_aarch64_build.tar.gz build build-armnn.sh common.sh setup-armnn.sh source validation.sh ``` The ```source``` directory contains the downloaded dependencies for building Arm NN.
The ```build``` directory contains the built Arm NN dependencies and the Arm NN build itself.
The ```armnn_aarch64_build.tar.gz``` tarball is an archive of the build located at ```build/armnn/aarch64_build```.
The scripts (e.g. ```build-armnn.sh```) in this directory can be run as you wish, changes will persist within the container but not the Docker Image. To exit the docker container, run ```CTRL-D```. A list of Docker containers can be obtained with the following command: ``` # --all shows both running and non-running containers docker ps --all CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES 4da7c575a95a armnn:aarch64 "bash" 7 minutes ago Exited (0) 7 seconds ago pedantic_joliot ``` To restart the same container (and any changes made to it) in a terminal again, use the following commands: ``` # 4da7c575a95a in this case is the CONTAINER ID from above docker start 4da7c575a95a # restart container in background docker attach 4da7c575a95a # re-attach to terminal # After exiting with CTRL-D docker stop 4da7c575a95a ``` To save space over time, stopped Docker containers can be deleted with the following command:
```docker container prune```.
### Bind Mounts **Bind Mounts** may be used to mount directories from the host machine to inside a Docker container. This could be useful when frequently changing the contents of the Arm NN or ACL source repositories (in ```/home/arm-user/source```) between runs of build-armnn.sh inside the container. Note that bind mounts are a feature that apply to runtime versions of Docker images i.e. Docker Containers (```docker run```, not ```docker build```). Please refer to the [Docker documentation for more information about bind mounts](https://docs.docker.com/storage/bind-mounts/).armnn-23.08/build-tool/README.md.license000066400000000000000000000001461446772241200176250ustar00rootroot00000000000000# # Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/build-tool/docker/000077500000000000000000000000001446772241200161735ustar00rootroot00000000000000armnn-23.08/build-tool/docker/Dockerfile000066400000000000000000000054251446772241200201730ustar00rootroot00000000000000# # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Default build type is 'production'. Use 'dev' if supplying custom Arm NN / ACL repos from host ARG BUILD_TYPE=production ARG UBUNTU_VERSION=20.04 FROM ubuntu:${UBUNTU_VERSION} AS build-production ENV DEBIAN_FRONTEND noninteractive # Install basic packages for Docker container (not specific to Arm NN) RUN apt-get update && \ apt-get install -y --no-install-recommends \ ca-certificates \ locales \ vim \ && \ apt-get clean && \ rm -rf /var/lib/apt/lists/* # Set locale for Docker container RUN locale-gen en_GB.UTF-8 && \ update-locale LC_ALL=en_GB.UTF-8 LANG=en_GB.UTF-8 ENV LANG en_GB.UTF-8 ENV LC_ALL en_GB.UTF-8 WORKDIR /root # Install system-wide packages specific to Arm NN COPY ./scripts/install-packages.sh . RUN ./install-packages.sh # Define user for non-root processes (overwriteable during 'docker build' with --build-arg) ARG USER_ID=1000 ARG GROUP_ID=1000 # Create non-root user 'arm-user' based on $USER_ID and $GROUP_ID above RUN addgroup --gid $GROUP_ID arm-user RUN useradd --create-home --shell /bin/bash --uid $USER_ID --gid $GROUP_ID arm-user # Switch to non-root user USER arm-user WORKDIR /home/arm-user # Copy scripts required by Setup into WORKDIR COPY --chown=arm-user:arm-user ./scripts/validation.sh . COPY --chown=arm-user:arm-user ./scripts/common.sh . COPY --chown=arm-user:arm-user ./scripts/setup-armnn.sh . # Run setup-armnn.sh: download and install Arm NN dependencies ARG SETUP_ARGS="" RUN echo "SETUP_ARGS: $SETUP_ARGS" RUN ./setup-armnn.sh $SETUP_ARGS # This build-dev stage (inherits 'build-production' stage) is only used in final image if $BUILD_TYPE is 'dev' FROM build-production as build-dev # Create directory for source repos in WORKDIR RUN mkdir -p source/armnn source/acl # Copy custom armnn/acl source repos from the build-tool directory on the host, if they exist (optional) # The 'acl' repo must be provided if --neon-backend or --cl-backend is given in the BUILD_ARGS, otherwise only custom "armnn" is required # If custom repos not provided, the build-armnn.sh script will automatically download the latest release branches of Arm NN and ACL # Copies Dockerfile to ensure COPY works - at least one file must exist for COPY to work COPY --chown=arm-user:arm-user ./docker/Dockerfile ./armnn* ./source/armnn/ COPY --chown=arm-user:arm-user ./docker/Dockerfile ./acl* ./source/acl/ # Final stage which inherits either 'build-production' or 'build-dev' stage FROM build-${BUILD_TYPE} as final # Copy build script into WORKDIR COPY --chown=arm-user:arm-user ./scripts/build-armnn.sh . # Run build-armnn.sh: build Arm NN and ACL ARG BUILD_ARGS="" RUN echo "BUILD_ARGS: $BUILD_ARGS" RUN ./build-armnn.sh $BUILD_ARGSarmnn-23.08/build-tool/dockerfile_armnn.png000066400000000000000000003376301446772241200207500ustar00rootroot00000000000000PNG  IHDRCw}sRGBgAMA a pHYs+IDATx^Uϲ. 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All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/build-tool/scripts/000077500000000000000000000000001446772241200164135ustar00rootroot00000000000000armnn-23.08/build-tool/scripts/build-armnn.sh000077500000000000000000000375301446772241200211720ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Script which builds Arm NN and ACL # setup-armnn.sh must be executed in the same directory, before running this script set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. rel_path=$(dirname "$0") # relative path from where script is executed to script location build_acl() { cd "$ACL_SRC" # $acl_scons_params are additional options provided by the user and will overwrite any previously defined args local acl_params="neon=$flag_neon_backend opencl=$flag_cl_backend Werror=0 embed_kernels=1 examples=0 validation_tests=0 benchmark_tests=0 benchmark_examples=0 $acl_scons_params" if [ "$flag_debug" -eq 1 ]; then acl_params="$acl_params debug=1 asserts=1" fi local native_flag="" if [ "$NATIVE_BUILD" ]; then native_flag="build=native" fi # Force -fPIC so that ACL is suitable for inclusion in Arm NN library local extra_cxx_flags="extra_cxx_flags='-fPIC'" local compile_flags="" local acl_arch="" case "$TARGET_ARCH" in "aarch64") compile_flags+="$AARCH64_COMPILER_FLAGS" acl_arch="arch=arm64-v8a" ;; "android64") compile_flags+="$AARCH64_COMPILER_FLAGS" acl_arch="arch=arm64-v8a" ;; "x86_64") acl_arch="arch=x86_64" ;; esac echo -e "\n***** Building ACL for $TARGET_ARCH *****" if [ "$flag_clean" -eq 1 ]; then echo -e "\n***** Clean flag detected: removing existing ACL build *****" rm -rf "$ACL_BUILD_TARGET" fi mkdir -p "$ACL_BUILD_TARGET" if [ "$TARGET_ARCH" == "android64" ]; then eval "$compile_flags" \ scons toolchain_prefix=llvm- \ compiler_prefix=aarch64-linux-android$ANDROID_API_VERSION- \ "$acl_arch" \ "$acl_params" \ "$extra_cxx_flags" \ os=android -j "$NUM_THREADS" else eval "$compile_flags" \ scons "$native_flag" \ "$acl_arch" \ "$acl_params" \ build_dir="$ACL_BUILD_TARGET" \ "$extra_cxx_flags" \ -j "$NUM_THREADS" fi echo -e "\n***** Built ACL for $TARGET_ARCH *****" return 0 } build_armnn() { mkdir -p "$ARMNN_BUILD_TARGET" cd "$ARMNN_BUILD_TARGET" local build_type="Release" if [ "$flag_debug" -eq 1 ]; then build_type="Debug" fi local cmake_flags="" local compile_flags="" local android_cmake_args="" case "$TARGET_ARCH" in "aarch64") compile_flags+="$AARCH64_COMPILER_FLAGS" ;; "android64") compile_flags+="$ANDROID64_COMPILER_FLAGS" cmake_flags+="CXXFLAGS='-fPIE -fPIC'" android_cmake_args+="-DCMAKE_ANDROID_NDK=$NDK_SRC \ -DNDK_VERSION=r$NDK_VERSION \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION=$ANDROID_API_VERSION \ -DCMAKE_ANDROID_ARCH_ABI=$ANDROID_ARM_ARCH \ -DCMAKE_SYSROOT=$ANDROID64_x86_TOOLCHAIN/sysroot \ -DCMAKE_EXE_LINKER_FLAGS='-pie -llog'" ;; esac if [ "$flag_clean" -eq 1 ]; then echo -e "\n***** Clean flag detected: removing existing Arm NN build *****" rm -rf "$ARMNN_BUILD_TARGET" fi echo -e "\n***** Building Arm NN for $TARGET_ARCH *****" eval "$compile_flags" \ cmake "$android_cmake_args" \ -DCMAKE_BUILD_TYPE="$build_type" \ -DBUILD_CLASSIC_DELEGATE="$flag_tflite_classic_delegate" \ -DBUILD_OPAQUE_DELEGATE="$flag_tflite_opaque_delegate" \ -DBUILD_TF_LITE_PARSER="$flag_tflite_parser" \ -DBUILD_DELEGATE_JNI_INTERFACE="$flag_jni" \ -DBUILD_ONNX_PARSER="$flag_onnx_parser" \ -DARMCOMPUTENEON="$flag_neon_backend" \ -DARMCOMPUTECL="$flag_cl_backend" \ -DARMNNREF="$flag_ref_backend" \ -DARMCOMPUTE_ROOT="$ACL_SRC" \ -DARMCOMPUTE_BUILD_DIR="$ACL_BUILD_TARGET" \ -DTENSORFLOW_ROOT="$TENSORFLOW_SRC" \ -DTFLITE_ROOT_DIR="$TFLITE_SRC" \ -DTF_LITE_GENERATED_PATH="$TFLITE_SRC"/schema \ -DTF_LITE_SCHEMA_INCLUDE_PATH="$TFLITE_SRC"/schema \ -DTFLITE_LIB_ROOT="$TFLITE_BUILD_TARGET" \ -DFLATBUFFERS_ROOT="$FLATBUFFERS_BUILD_TARGET" \ -DFLATC_DIR="$FLATBUFFERS_BUILD_HOST" \ -DONNX_GENERATED_SOURCES="$ONNX_BUILD_TARGET" \ -DPROTOBUF_ROOT="$PROTOBUF_BUILD_TARGET" \ "$armnn_cmake_args" \ "$ARMNN_SRC" make -j "$NUM_THREADS" # Copy protobuf library into Arm NN build directory, if ONNX Parser is enabled if [ "$flag_onnx_parser" -eq 1 ]; then cd "$ARMNN_BUILD_TARGET" rm -f libprotobuf.so libprotobuf.so.23 libprotobuf.so.23.0.0 if [ "$TARGET_ARCH" != "android64" ]; then cp "$PROTOBUF_LIBRARY_TARGET" . ln -s libprotobuf.so.23.0.0 ./libprotobuf.so.23 ln -s libprotobuf.so.23.0.0 ./libprotobuf.so else cp "$PROTOBUF_ANDROID_LIB_TARGET" . fi fi # Copy Arm NN include directory into build output cd "$ARMNN_BUILD_TARGET" rm -rf include cp -r "$SOURCE_DIR"/armnn/include . echo -e "\n***** Built Arm NN for $TARGET_ARCH *****" local tarball_path="$ROOT_DIR/armnn_$ARMNN_BUILD_DIR_NAME.tar.gz" echo -e "\n***** Creating tarball of Arm NN build at $tarball_path *****" cd "$ARMNN_BUILD_ROOT" rm -f "$tarball_path" tar -czf "$tarball_path" "$ARMNN_BUILD_DIR_NAME" echo -e "\n***** Created tarball of Arm NN build at $ROOT_DIR/armnn_$ARMNN_BUILD_DIR_NAME.tar.gz *****" echo -e "\n***** To extract tarball, run: tar -xzf armnn_$ARMNN_BUILD_DIR_NAME.tar.gz *****\n" return 0 } download_armnn() { cd "$SOURCE_DIR" echo -e "\n***** Downloading Arm NN *****" rm -rf "$ARMNN_SRC" # Latest release branch of Arm NN is checked out by default git clone https://github.com/ARM-software/armnn.git armnn cd "$ARMNN_SRC" local armnn_branch="$(git rev-parse --abbrev-ref HEAD)" echo -e "\n***** Arm NN Downloaded: $armnn_branch *****" } download_acl() { # First get Arm NN branch so that we can download corresponding ACL tag cd "$ARMNN_SRC" local armnn_branch="$(git rev-parse --abbrev-ref HEAD)" echo -e "\n***** Downloading corresponding ACL version using Arm NN branch: $armnn_branch *****" cd "$SOURCE_DIR" rm -rf "$ACL_SRC" git clone https://github.com/ARM-software/ComputeLibrary.git acl # Get corresponding release tag for ACL by parsing release branch number for Arm NN local acl_tag="" acl_tag="$(echo "$armnn_branch" | tr '\n' ' ' | sed -e 's/[^0-9]/ /g' -e 's/^ *//g' -e 's/ *$//g' | tr -s ' ' | sed 's/ /./g')" cd "$ACL_SRC" git checkout v"$acl_tag" echo -e "\n***** ACL Downloaded: $acl_tag *****" } usage() { cat < provide additional comma-separated CMake arguments string for building Arm NN (optional) --acl-scons-params= provide additional comma-separated scons parameters string for building ACL (optional) --num-threads= specify number of threads/cores to build dependencies with (optional: defaults to number of online CPU cores on host) -h, --help print brief usage information and exit -x enable shell tracing in this script At least one component (i.e. --tflite-classic-delegate, --tflite-opaque-delegate, --tflite-parser, --onnx-parser) must be provided or else provide --all to build all Arm NN components. At least one backend (i.e. --neon-backend, --cl-backend, --ref-backend) must be chosen. This script must be executed from the same root directory in which setup-armnn.sh was executed from. The first execution of this script will download the latest release branches of Arm NN and ACL, by default. Alternatively, place custom/modified repositories named "armnn" and (optionally) "acl" in /source. Providing custom "acl" repo is optional since it is only required if backend flags --neon-backend or --cl-backend are chosen. By default, a tarball tar.gz archive of the Arm NN build will be created in the directory from which this script is called from. Examples: Build for aarch64 with all Arm NN components, NEON enabled and OpenCL enabled: /build-armnn.sh --target-arch=aarch64 --all --neon-backend --cl-backend Build for aarch64 with TF Lite Delegate, OpenCL enabled and additional ACL scons params: /build-armnn.sh --target-arch=aarch64 --tflite-classic-delegate --cl-backend --acl-scons-params='compress_kernels=1,benchmark_examples=1' Setup for aarch64 with all Arm NN dependencies, OpenCL enabled and additional Arm NN cmake args: /build-armnn.sh --target-arch=aarch64 --all --cl-backend --armnn-cmake-args='-DBUILD_SAMPLE_APP=1,-DBUILD_UNIT_TESTS=0' EOF } # This will catch in validation.sh if not set target_arch="" # Default flag values flag_tflite_classic_delegate=0 flag_tflite_opaque_delegate=0 flag_tflite_parser=0 flag_onnx_parser=0 flag_neon_backend=0 flag_cl_backend=0 flag_ref_backend=0 flag_clean=0 flag_debug=0 flag_jni=0 # Empty strings for optional additional args by default armnn_cmake_args="" acl_scons_params="" # If --num-threads is not set, the default NUM_THREADS value in common.sh will be used num_threads=0 name=$(basename "$0") # If no options provided, show help if [ $# -eq 0 ]; then usage exit 1 fi args=$(getopt -ohx -l tflite-classic-delegate,tflite-opaque-delegate,tflite-parser,onnx-parser,all,target-arch:,neon-backend,cl-backend,ref-backend,clean,debug,armnn-cmake-args:,acl-scons-params:,num-threads:,help -n "$name" -- "$@") eval set -- "$args" while [ $# -gt 0 ]; do if [ -n "${opt_prev:-}" ]; then eval "$opt_prev=\$1" opt_prev= shift 1 continue elif [ -n "${opt_append:-}" ]; then if [ -n "$1" ]; then eval "$opt_append=\"\${$opt_append:-} \$1\"" fi opt_append= shift 1 continue fi case $1 in --tflite-parser) flag_tflite_parser=1 ;; --tflite-classic-delegate) flag_tflite_classic_delegate=1 ;; --tflite-opaque-delegate) flag_tflite_opaque_delegate=1 ;; --onnx-parser) flag_onnx_parser=1 ;; --all) flag_tflite_classic_delegate=1 flag_tflite_opaque_delegate=1 flag_tflite_parser=1 flag_onnx_parser=1 ;; --target-arch) opt_prev=target_arch ;; --neon-backend) flag_neon_backend=1 ;; --cl-backend) flag_cl_backend=1 ;; --ref-backend) flag_ref_backend=1 ;; --clean) flag_clean=1 ;; --debug) flag_debug=1 ;; --armnn-cmake-args) opt_prev=armnn_cmake_args ;; --acl-scons-params) opt_prev=acl_scons_params ;; --num-threads) opt_prev=num_threads ;; -h | --help) usage exit 0 ;; -x) set -x ;; --) shift break 2 ;; esac shift 1 done # shellcheck source=common.sh source "$rel_path"/common.sh # Validation of chosen Arm NN backends if [ "$flag_neon_backend" -eq 0 ] && [ "$flag_cl_backend" -eq 0 ] && [ "$flag_ref_backend" -eq 0 ]; then echo -e "\n$name: at least one of flags --neon-backend, --cl-backend or --ref-backend must be set." exit 1 fi if [ "$target_arch" == "x86_64" ]; then if [ "$flag_neon_backend" -eq 1 ] || [ "$flag_cl_backend" -eq 1 ]; then echo "$name: Accelerated backends --neon-backend and --cl-backend are supported on Arm targets only (x86_64 chosen)." exit 1 fi fi # Verify that root source and build directories are present (post execution of setup-armnn.sh) if [ ! -d "$SOURCE_DIR" ]; then echo -e "\nERROR: Root source directory does not exist at $SOURCE_DIR" echo "Please check that:" echo "1. setup-armnn.sh was executed successfully prior to running this script" echo "2. This script is being executed in the same directory as setup-armnn.sh" exit 1 fi if [ ! -d "$BUILD_DIR" ]; then echo -e "\nERROR: Root build directory does not exist at $BUILD_DIR" echo "Please check that:" echo "1. setup-armnn.sh was executed successfully prior to running this script" echo "2. This script is being executed in the same directory as setup-armnn.sh" exit 1 fi # Download Arm NN if not done already in a previous execution of this script # Check if Arm NN source directory exists AND that it is a repository (not empty) if [ -d "$ARMNN_SRC" ] && check_if_repository "$ARMNN_SRC"; then echo -e "\n***** Arm NN source repository already located at $ARMNN_SRC. Skipping cloning of Arm NN. *****" else # Download latest release branch of Arm NN download_armnn fi # Download ACL if not done already in a previous execution of this script # Only download ACL if backend options --neon-backend and --cl-backend are chosen if [ "$flag_neon_backend" -eq 1 ] || [ "$flag_cl_backend" -eq 1 ]; then # Check if Arm NN source directory exists AND that it is a repository (not empty) if [ -d "$ACL_SRC" ] && check_if_repository "$ACL_SRC"; then echo -e "\n***** ACL source repository already located at $ACL_SRC. Skipping cloning of ACL. *****" else # Download latest release branch of ACL download_acl fi else echo -e "\n***** Backend options --neon-backend and --cl-backend not selected - skipping cloning of ACL *****" fi # Adjust output build directory names for Arm NN and ACL if debug is enabled DEBUG_POSTFIX="" if [ "$flag_debug" -eq 1 ]; then DEBUG_POSTFIX="_debug" fi # Replace commas with spaces in additional Arm NN / ACL build args # shellcheck disable=SC2001 armnn_cmake_args="$(echo "$armnn_cmake_args" | sed 's/,/ /g')" # shellcheck disable=SC2001 acl_scons_params="$(echo "$acl_scons_params" | sed 's/,/ /g')" # Directories for Arm NN and ACL build outputs ARMNN_BUILD_ROOT="$BUILD_DIR"/armnn ARMNN_BUILD_DIR_NAME="$TARGET_ARCH"_build"$DEBUG_POSTFIX" ARMNN_BUILD_TARGET="$ARMNN_BUILD_ROOT"/"$ARMNN_BUILD_DIR_NAME" ACL_BUILD_TARGET="$BUILD_DIR"/acl/"$TARGET_ARCH"_build"$DEBUG_POSTFIX" echo -e "\nINFO: Displaying configuration information before execution of $name" echo " target-arch: $TARGET_ARCH" echo " host-arch: $HOST_ARCH" echo "tflite-classic-delegate: $flag_tflite_classic_delegate" echo "tflite-opaque-delegate : $flag_tflite_opaque_delegate" echo " tflite-parser: $flag_tflite_parser" echo " onnx-parser: $flag_onnx_parser" echo " neon-backend: $flag_neon_backend" echo " cl-backend: $flag_cl_backend" echo " ref-backend: $flag_ref_backend" echo " clean: $flag_clean" echo " debug: $flag_debug" echo " armnn-cmake-args: $armnn_cmake_args" echo " acl-scons-params: $acl_scons_params" echo " num-threads: $NUM_THREADS" echo " root directory: $ROOT_DIR" echo " source directory: $SOURCE_DIR" echo " build directory: $BUILD_DIR" echo " armnn build dir: $ARMNN_BUILD_TARGET" echo -e "\nScript execution will begin in 10 seconds..." sleep 10 if [ "$flag_neon_backend" -eq 1 ] || [ "$flag_cl_backend" -eq 1 ]; then build_acl else echo -e "\n***** Skipping ACL build: --neon-backend and --cl-backend not set in options. *****" fi build_armnn exit 0 armnn-23.08/build-tool/scripts/common.sh000077500000000000000000000063231446772241200202460ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Script which stores common variables and paths used by setup-armnn.sh and build-armnn.sh # shellcheck disable=SC2034 # SC2034: false positives for variables appear unused - variables are used in setup-armnn.sh and build-armnn.sh set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. # ROOT_DIR is the directory in which a script is called from ROOT_DIR=$(pwd) SOURCE_DIR="$ROOT_DIR"/source BUILD_DIR="$ROOT_DIR"/build # Host architecture e.g. x86_64, aarch64 HOST_ARCH=$(uname -m) # Number of online cores on host NUM_THREADS=$(getconf _NPROCESSORS_ONLN) # Validate common user-defined options # shellcheck source=validation.sh source "$rel_path"/validation.sh # target_arch supplied as command line arg TARGET_ARCH="$target_arch" NATIVE_BUILD=0 if [ "$TARGET_ARCH" == "$HOST_ARCH" ]; then NATIVE_BUILD=1 fi AARCH64_COMPILER_FLAGS+="CC=/usr/bin/aarch64-linux-gnu-gcc CXX=/usr/bin/aarch64-linux-gnu-g++ " # NDK NDK_VERSION=25 NDK_SRC="$SOURCE_DIR"/android-ndk-r"$NDK_VERSION" # ANDROID ANDROID_API_VERSION=30 ANDROID_ARM_ARCH="arm64-v8a" ANDROID64_x86_TOOLCHAIN+="$NDK_SRC/toolchains/llvm/prebuilt/linux-x86_64" ANDROID64_COMPILER_FLAGS+="CC="$ANDROID64_x86_TOOLCHAIN"/bin/aarch64-linux-android"$ANDROID_API_VERSION"-clang \ CXX="$ANDROID64_x86_TOOLCHAIN"/bin/aarch64-linux-android"$ANDROID_API_VERSION"-clang++ " # Flatbuffers FLATBUFFERS_VERSION=2.0.6 FLATBUFFERS_SRC="$SOURCE_DIR"/flatbuffers-"$FLATBUFFERS_VERSION" FLATBUFFERS_BUILD_ROOT="$BUILD_DIR"/flatbuffers FLATBUFFERS_BUILD_TARGET="$FLATBUFFERS_BUILD_ROOT"/"$TARGET_ARCH"_build FLATBUFFERS_BUILD_HOST="$FLATBUFFERS_BUILD_ROOT"/"$HOST_ARCH"_build # Location of flatc compiler # Tensorflow TENSORFLOW_VERSION="6f692f73cb2043b4a0b0446539cd8c15b3dd9220" #2.12 RC1 + PR #60015 to fix Cmake build. TENSORFLOW_SRC="$SOURCE_DIR"/tensorflow TFLITE_SRC="$TENSORFLOW_SRC"/tensorflow/lite SCHEMA_SRC="$TFLITE_SRC"/schema/schema.fbs # TF Lite Schema FLATC="$FLATBUFFERS_BUILD_HOST"/bin/flatc TFLITE_BUILD_ROOT="$BUILD_DIR"/tflite # Generated TF Lite Schema location TFLITE_BUILD_TARGET="$TFLITE_BUILD_ROOT"/"$TARGET_ARCH"_build # Protobuf PROTOBUF_VERSION=3.12.0 PROTOBUF_SRC="$SOURCE_DIR"/protobuf-"$PROTOBUF_VERSION" PROTOBUF_BUILD_ROOT="$BUILD_DIR"/protobuf PROTOBUF_BUILD_HOST="$PROTOBUF_BUILD_ROOT"/"$HOST_ARCH"_build PROTOCOL_COMPILER_HOST="$PROTOBUF_BUILD_HOST"/bin/protoc PROTOBUF_BUILD_TARGET="$PROTOBUF_BUILD_ROOT"/"$TARGET_ARCH"_build PROTOBUF_LIBRARY_TARGET="$PROTOBUF_BUILD_TARGET"/lib/libprotobuf.so.23.0.0 PROTOBUF_ANDROID_LIB_TARGET="$PROTOBUF_BUILD_TARGET"/lib/libprotobuf.so # ONNX ONNX_VERSION=1.6.0 ONNX_SRC="$SOURCE_DIR"/onnx-"$ONNX_VERSION" ONNX_BUILD_TARGET="$BUILD_DIR"/onnx/"$TARGET_ARCH"_build # Arm NN / ACL ARMNN_SRC="$SOURCE_DIR"/armnn ACL_SRC="$SOURCE_DIR"/acl # Check if directory at $1 is a repository or not check_if_repository() { pushd "$1" > /dev/null if [ "$(git rev-parse --is-inside-work-tree 2> /dev/null)" ]; then popd > /dev/null return 0 else popd > /dev/null return 1 fi }armnn-23.08/build-tool/scripts/docker-copy-to-host.sh000077500000000000000000000041561446772241200225720ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Script which copies a file or directory from the /home/arm-user/ directory in Docker to the host machine # This script creates a directory called 'docker_output' in the current directory and places the copied contents there # Takes two arguments: # 1. Name of created Docker image i.e. "--tag " provided at 'docker build' stage (tag is optional in image naming) # 2. Relative path to file or directory to copy from the Docker /home/arm-user/ directory # # Examples: # 1. Copy the tarball of the aarch64 build from the /home/arm-user/ directory # ./scripts/docker-copy-to-host.sh armnn_image armnn_aarch64_build.tar.gz # 2. Copy the unarchived Arm NN build # ./scripts/docker-copy-to-host.sh armnn_image build/armnn # 3. Copy the unarchived ACL build # ./scripts/docker-copy-to-host.sh armnn_image build/acl set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. image_name="$1" file_path="$2" name=$(basename "$0") echo "***** $name: Copying file(s) from path /home/arm-user/$file_path inside Docker image '$image_name' to host *****" echo -e "\n***** Creating directory docker_output on host *****" mkdir -p docker_output # Cleanup old 'armnn_temp' container in case a previous run of this script was not successful docker rm --force armnn_temp 2> /dev/null echo -e "\n***** Creating temporary Docker container named armnn_temp using Docker image '$image_name' *****" docker create --interactive --tty --name armnn_temp "$image_name" bash > /dev/null echo -e "\n***** Running Docker command: docker cp armnn_temp:/home/arm-user/$file_path ./docker_output *****" docker cp armnn_temp:/home/arm-user/"$file_path" ./docker_output > /dev/null echo -e "\n***** Successfully copied file(s) to host in directory docker_output *****" # Remove temporary docker container 'armnn_temp' docker rm --force armnn_temp > /dev/null echo -e "\n***** Deleted temporary Docker container armnn_temp *****"armnn-23.08/build-tool/scripts/install-packages.sh000077500000000000000000000066031446772241200222010ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Script which installs system-wide packages required by setup-armnn.sh and build-armnn.sh # Downloads and builds CMake from source in the current directory from which this script is called # CMake will be installed system-wide once this script has completed execution # Requires sudo privileges set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. # Host architecture e.g. x86_64, aarch64 HOST_ARCH=$(uname -m) # Number of online cores on host NUM_THREADS=$(getconf _NPROCESSORS_ONLN) # CMake is downloaded and built in the current directory from which this script is called ROOT_DIR=$(pwd) # CMake CMAKE_VERSION=3.19 CMAKE_VERSION_FULL=3.19.0 CMAKE_SRC="$ROOT_DIR"/cmake-"$CMAKE_VERSION_FULL" CMAKE_BUILD="$ROOT_DIR"/cmake_build download_cmake() { cd "$ROOT_DIR" echo -e "\n***** Downloading CMake $CMAKE_VERSION *****" wget -O cmake-"$CMAKE_VERSION_FULL".tar.gz https://cmake.org/files/v"$CMAKE_VERSION"/cmake-"$CMAKE_VERSION_FULL".tar.gz echo -e "\n***** Extracting archive *****" tar -xzf cmake-"$CMAKE_VERSION_FULL".tar.gz echo -e "\n***** Removing archive *****" rm cmake-"$CMAKE_VERSION_FULL".tar.gz echo -e "\n***** CMake $CMAKE_VERSION Downloaded *****" } install_cmake() { mkdir -p "$CMAKE_BUILD" cd "$CMAKE_BUILD" apt-get purge -y cmake echo -e "\n***** Building CMake $CMAKE_VERSION ***** " "$CMAKE_SRC"/bootstrap make make install -j "$NUM_THREADS" if [[ "$(cmake --version 2> /dev/null | grep "$CMAKE_VERSION" )" == *"$CMAKE_VERSION"* ]]; then echo -e "\n***** Built and Installed CMake $CMAKE_VERSION *****" else echo -e "\nERROR: CMake $CMAKE_VERSION not installed correctly after building from source" exit 1 fi } install_apt_packages() { apt-get update && apt-get install -y --no-install-recommends \ autoconf \ automake \ build-essential \ curl \ git \ libssl-dev \ libtool \ make \ scons \ unzip \ wget \ xxd # Install cross compile toolchains if host is x86_64 if [ "$HOST_ARCH" == "x86_64" ]; then apt-get update && apt-get install -y --no-install-recommends \ crossbuild-essential-arm64 fi apt-get clean rm -rf /var/lib/apt/lists/* } name=$(basename "$0") if [ ! "$(id -u)" -eq 0 ]; then echo -e "\nERROR: $name must be ran as root (i.e. sudo ./$name)" exit 1 fi echo -e "\n***** $name: Installing system-wide packages required by setup-armnn.sh and build-armnn.sh *****" echo -e "\nINFO: This script downloads and builds CMake from source in the current directory from which this script is called" echo -e "\nINFO: CMake and other apt packages will be installed system-wide once this script has completed execution" echo -e "\nScript execution will begin in 10 seconds..." sleep 10 install_apt_packages # Download, Build and Install CMake if not already present if [[ "$(cmake --version 2> /dev/null | grep "$CMAKE_VERSION" )" == *"$CMAKE_VERSION"* ]]; then echo -e "\n***** CMake $CMAKE_VERSION already installed, skipping CMake install *****" else download_cmake install_cmake fi echo -e "\n***** $name: Successfully installed system-wide packages required by setup-armnn.sh and build-armnn.sh *****\n" exit 0armnn-23.08/build-tool/scripts/setup-armnn.sh000077500000000000000000000307531446772241200212330ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Script which downloads and builds Arm NN dependencies # Perquisite to running build-armnn.sh set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. rel_path=$(dirname "$0") # relative path from where script is executed to script location # Download an archive using wget and extract using tar # Takes three arguments: # 1. Name of dependency being downloaded e.g. Flatbuffers # 2. Link to archive # 3. Filename given to archive upon downloading download_and_extract() { cd "$SOURCE_DIR" echo -e "\n***** Downloading $1 *****\n" wget -O "$3" "$2" echo -e "\n***** Extracting archive *****" tar -xzf "$3" echo -e "\n***** Removing archive *****" rm "$3" echo -e "\n***** $1 downloaded *****" } download_androidndk() { cd "$SOURCE_DIR" echo -e "\n***** Downloading Android NDK *****\n" wget https://dl.google.com/android/repository/android-ndk-r25-linux.zip echo -e "\n***** Extracting archive *****" unzip android-ndk-r25-linux.zip echo -e "\n***** Removing archive *****" rm android-ndk-r25-linux.zip echo -e "\n***** Android NDK downloaded *****" } download_protobuf() { download_and_extract \ "Protobuf" \ "https://github.com/protocolbuffers/protobuf/releases/download/v$PROTOBUF_VERSION/protobuf-all-$PROTOBUF_VERSION.tar.gz" \ "protobuf-all-$PROTOBUF_VERSION.tar.gz" } build_protobuf() { local native_build=$1 local build_dir="$PROTOBUF_BUILD_TARGET" local cmake_flags="" local target_arch="$TARGET_ARCH" local additional_cmds="" if [ "$native_build" -eq 0 ]; then mkdir -p "$PROTOBUF_BUILD_TARGET" additional_cmds+="--with-protoc=$PROTOCOL_COMPILER_HOST " if [ "$TARGET_ARCH" == "aarch64" ]; then cmake_flags+="$AARCH64_COMPILER_FLAGS" additional_cmds+="--host=aarch64-linux " fi if [ "$TARGET_ARCH" == "android64" ]; then additional_cmds+="--host=aarch64-linux-android " cmake_flags+="$ANDROID64_COMPILER_FLAGS" fi else target_arch="$HOST_ARCH" mkdir -p "$PROTOBUF_BUILD_HOST" build_dir="$PROTOBUF_BUILD_HOST" fi echo -e "\n***** Building Protobuf for $target_arch ***** " cd "$PROTOBUF_BUILD_ROOT" # Cleanup any previous cmake files, except actual builds which we keep find . -mindepth 1 -name "*_build" -prune -o -exec rm -rf {} + if [ "$native_build" -eq 0 ] && [ "$TARGET_ARCH" == "android64" ]; then eval "$cmake_flags" cmake -DCMAKE_ANDROID_NDK="$NDK_SRC" \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION="$ANDROID_API_VERSION" \ -DCMAKE_ANDROID_ARCH_ABI="$ANDROID_ARM_ARCH" \ -DCMAKE_CXX_FLAGS=--std=c++14 \ -Dprotobuf_BUILD_TESTS=OFF \ -Dprotobuf_BUILD_SHARED_LIBS=ON \ -Dprotobuf_WITH_ZLIB=OFF \ -DCMAKE_BUILD_TYPE=Release \ $PROTOBUF_SRC/cmake/ make libprotobuf -j "$NUM_THREADS" cmake -DCMAKE_INSTALL_PREFIX=$PROTOBUF_BUILD_TARGET -DCOMPONENT=libprotobuf -P cmake_install.cmake cmake -DCMAKE_INSTALL_PREFIX=$PROTOBUF_BUILD_TARGET -DCOMPONENT=protobuf-headers -P cmake_install.cmake else eval "$cmake_flags" \ "$PROTOBUF_SRC"/configure --prefix="$build_dir" "$additional_cmds" make install -j "$NUM_THREADS" fi echo -e "\n***** Protobuf built for $target_arch ***** " } download_flatbuffers() { download_and_extract \ "Flatbuffers" \ "https://github.com/google/flatbuffers/archive/v$FLATBUFFERS_VERSION.tar.gz" \ "flatbuffers-$FLATBUFFERS_VERSION.tar.gz" } build_flatbuffers() { local native_build=$1 local build_dir="$FLATBUFFERS_BUILD_TARGET" local target_arch="$TARGET_ARCH" local cmake_flags="CXXFLAGS=-fPIC " if [ "$native_build" -eq 0 ]; then mkdir -p "$FLATBUFFERS_BUILD_TARGET" if [ "$TARGET_ARCH" == "aarch64" ] || [ "$TARGET_ARCH" == "android64" ]; then cmake_flags+="$AARCH64_COMPILER_FLAGS" fi else target_arch="$HOST_ARCH" mkdir -p "$FLATBUFFERS_BUILD_HOST" build_dir="$FLATBUFFERS_BUILD_HOST" fi echo -e "\n***** Building flatbuffers for $target_arch *****" mkdir -p "$FLATBUFFERS_BUILD_ROOT" cd "$FLATBUFFERS_BUILD_ROOT" # Cleanup any previous cmake files, except actual builds which we keep find . -mindepth 1 -name "*_build" -prune -o -exec rm -rf {} + if [ "$native_build" -eq 0 ] && [ "$TARGET_ARCH" == "android64" ]; then eval "$cmake_flags" \ cmake -DCMAKE_ANDROID_NDK="$NDK_SRC" \ -DCMAKE_SYSTEM_NAME=Android \ -DCMAKE_SYSTEM_VERSION="$ANDROID_API_VERSION" \ -DCMAKE_ANDROID_ARCH_ABI="$ANDROID_ARM_ARCH" \ -DCMAKE_CXX_FLAGS=--std=c++14 \ -DFLATBUFFERS_BUILD_FLATC=0 \ -DCMAKE_INSTALL_PREFIX:PATH="$build_dir" \ -DCMAKE_BUILD_TYPE=Release \ -DFLATBUFFERS_BUILD_TESTS=0 \ "$FLATBUFFERS_SRC" else eval "$cmake_flags" \ cmake -DFLATBUFFERS_BUILD_FLATC="$native_build" \ -DCMAKE_INSTALL_PREFIX:PATH="$build_dir" \ -DFLATBUFFERS_BUILD_TESTS=0 \ "$FLATBUFFERS_SRC" fi make all install -j "$NUM_THREADS" echo -e "\n***** Built flatbuffers for $target_arch *****" } download_tensorflow() { cd "$SOURCE_DIR" echo -e "\n***** Downloading TensorFlow *****" git clone https://github.com/tensorflow/tensorflow.git cd "$TENSORFLOW_SRC" git checkout "$TENSORFLOW_VERSION" echo -e "\n***** TensorFlow downloaded *****" } build_tflite() { mkdir -p "$TFLITE_BUILD_TARGET" cd "$TFLITE_BUILD_TARGET" local target_arch_cmd="" # default is native, no command needed local cmake_flags="" case "$TARGET_ARCH" in "aarch64") cmake_flags+="$AARCH64_COMPILER_FLAGS" target_arch_cmd="-DCMAKE_SYSTEM_PROCESSOR=aarch64 \ -DCMAKE_SYSTEM_NAME=Linux " if [ "$NATIVE_BUILD" -eq 0 ]; then cmake_flags+="ARMCC_FLAGS='-funsafe-math-optimizations' " fi ;; "android64") cmake_flags+="$AARCH64_COMPILER_FLAGS" if [ "$NATIVE_BUILD" -eq 0 ]; then target_arch_cmd="-DCMAKE_TOOLCHAIN_FILE=$NDK_SRC/build/cmake/android.toolchain.cmake \ -DANDROID_ABI=$ANDROID_ARM_ARCH \ -DANDROID_PLATFORM=$ANDROID_API_VERSION" fi ;; esac echo -e "\n***** Building TF Lite for $TARGET_ARCH *****" # Cleanup any previous cmake files, except actual builds which we keep find . -mindepth 1 -name "*_build" -prune -o -exec rm -rf {} + eval "$cmake_flags" \ cmake -DTFLITE_ENABLE_XNNPACK=OFF \ -DFLATBUFFERS_BUILD_FLATC=OFF \ -DBUILD_SHARED_LIBS=OFF \ -DBUILD_TESTING=OFF \ "$target_arch_cmd" \ "$TFLITE_SRC" cmake --build . -j "$NUM_THREADS" echo -e "\n***** Built TF Lite for $TARGET_ARCH *****" } generate_tflite_schema() { echo -e "\n***** Generating TF Lite Schema *****" mkdir -p "$TFLITE_BUILD_ROOT" cd "$TFLITE_BUILD_ROOT" cp "$SCHEMA_SRC" . $FLATC -c --gen-object-api --reflect-types --reflect-names schema.fbs echo -e "\n***** Generated TF Lite Schema *****" } download_onnx() { download_and_extract \ "ONNX" \ "https://github.com/onnx/onnx/releases/download/v$ONNX_VERSION/onnx-$ONNX_VERSION.tar.gz" \ "onnx-$ONNX_VERSION.tar.gz" } generate_onnx_sources() { mkdir -p "$ONNX_BUILD_TARGET" cd "$ONNX_SRC" echo -e "\n***** Generating ONNX sources for $TARGET_ARCH *****" export LD_LIBRARY_PATH="$PROTOBUF_BUILD_HOST"/lib${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH} eval "$PROTOCOL_COMPILER_HOST" onnx/onnx.proto \ --proto_path=. \ --proto_path="$ONNX_SRC" \ --proto_path="$PROTOBUF_BUILD_HOST"/include \ --cpp_out "$ONNX_BUILD_TARGET" echo -e "\n***** Generated ONNX sources for $TARGET_ARCH *****" } usage() { cat < specify number of threads/cores to build dependencies with (optional: defaults to number of online CPU cores on host) -h, --help print brief usage information and exit -x enable shell tracing in this script At least one dependency flag (e.g. --tflite-classic-delegate) must be provided or else provide --all to setup all dependencies. Directories called "source" and "build" will be generated in the current directory (ROOT_DIR) from which this script is called. It's recommended to call this script in a directory outside of this Arm NN source repo, to avoid nested repositories. Examples: Setup for aarch64 with all Arm NN dependencies: /setup-armnn.sh --target-arch=aarch64 --all Setup for aarch64 with the existing TF Lite Delegate and TF Lite Parser dependencies only: /setup-armnn.sh --target-arch=aarch64 --tflite-classic-delegate --tflite-parser EOF } # This will catch in validation.sh if not set target_arch="" # Default flag values flag_tflite_classic_delegate=0 flag_tflite_opaque_delegate=0 flag_tflite_parser=0 flag_onnx_parser=0 # If --num-threads is not set, the default NUM_THREADS value in common.sh will be used num_threads=0 name=$(basename "$0") # If no options provided, show help if [ $# -eq 0 ]; then usage exit 1 fi args=$(getopt -ohx -l tflite-classic-delegate,tflite-opaque-delegate,tflite-parser,onnx-parser,all,target-arch:,num-threads:,help -n "$name" -- "$@") eval set -- "$args" while [ $# -gt 0 ]; do if [ -n "${opt_prev:-}" ]; then eval "$opt_prev=\$1" opt_prev= shift 1 continue elif [ -n "${opt_append:-}" ]; then if [ -n "$1" ]; then eval "$opt_append=\"\${$opt_append:-} \$1\"" fi opt_append= shift 1 continue fi case $1 in --tflite-parser) flag_tflite_parser=1 ;; --tflite-classic-delegate) flag_tflite_classic_delegate=1 ;; --tflite-opaque-delegate) flag_tflite_opaque_delegate=1 ;; --onnx-parser) flag_onnx_parser=1 ;; --all) flag_tflite_classic_delegate=1 flag_tflite_opaque_delegate=1 flag_tflite_parser=1 flag_onnx_parser=1 ;; --target-arch) opt_prev=target_arch ;; --num-threads) opt_prev=num_threads ;; -h | --help) usage exit 0 ;; -x) set -x ;; --) shift break 2 ;; esac shift 1 done # shellcheck source=common.sh source "$rel_path"/common.sh echo -e "\nINFO: Displaying configuration information before execution of $name" echo " target-arch: $TARGET_ARCH" echo " host-arch: $HOST_ARCH" echo "tflite-classic-delegate: $flag_tflite_classic_delegate" echo "tflite-opaque-delegate : $flag_tflite_opaque_delegate" echo " tflite-parser: $flag_tflite_parser" echo " onnx-parser: $flag_onnx_parser" echo " num-threads: $NUM_THREADS" echo " root directory: $ROOT_DIR" echo " source directory: $SOURCE_DIR" echo " build directory: $BUILD_DIR" if check_if_repository .; then echo -e "\n***** WARNING: Running script inside a git repository. To avoid nested repos, call this script from outside of this repo. *****" fi echo -e "\nScript execution will begin in 10 seconds..." sleep 10 mkdir -p "$SOURCE_DIR" mkdir -p "$BUILD_DIR" if [ "$TARGET_ARCH" == "android64" ]; then download_androidndk fi if [ "$flag_tflite_classic_delegate" -eq 1 ] || [ "$flag_tflite_opaque_delegate" -eq 1 ] || [ "$flag_tflite_parser" -eq 1 ]; then download_flatbuffers # Host build build_flatbuffers 1 # Target build for cross compile if [ "$NATIVE_BUILD" -eq 0 ]; then build_flatbuffers 0 fi download_tensorflow fi if [ "$flag_tflite_parser" -eq 1 ]; then generate_tflite_schema fi if [ "$flag_tflite_classic_delegate" -eq 1 ] || [ "$flag_tflite_opaque_delegate" -eq 1 ]; then build_tflite fi if [ "$flag_onnx_parser" -eq 1 ]; then download_protobuf # Host build build_protobuf 1 # Target build for cross compile if [ "$NATIVE_BUILD" -eq 0 ]; then build_protobuf 0 fi download_onnx generate_onnx_sources fi echo -e "\n***** Arm NN setup complete. Now build with build-armnn.sh. *****\n" exit 0armnn-23.08/build-tool/scripts/validation.sh000077500000000000000000000036221446772241200211070ustar00rootroot00000000000000#!/bin/bash # # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Common validation of command line arguments provided to setup-armnn.sh and build-armnn.sh # shellcheck disable=SC2034,SC2154 # SC2034: false positives for variables appear unused - variables are used in setup-armnn.sh and build-armnn.sh # SC2154: false positives for variables referenced but not assigned - variables are assigned in setup-armnn.sh and build-armnn.sh set -o nounset # Catch references to undefined variables. set -o pipefail # Catch non zero exit codes within pipelines. set -o errexit # Catch and propagate non zero exit codes. # Host and target architecture validation if [ "$target_arch" == "" ]; then echo "$name: --target-arch is not set. Example usage: --target-arch=aarch64" exit 1 fi if [ "$target_arch" != "aarch64" ] && [ "$target_arch" != "android64" ] && [ "$target_arch" != "x86_64" ]; then echo "$name: --target-arch is not valid. Valid options are: aarch64, android64, x86_64" exit 1 fi if [ "$HOST_ARCH" == "aarch64" ]; then if [ "$target_arch" != "aarch64" ]; then echo "$name: aarch64 is the only supported --target_arch when host is aarch64" exit 1 fi fi if [ "$target_arch" == "android64" ]; then if [ "$HOST_ARCH" != "x86_64" ]; then echo "$name: --target_arch android64 is only supported when host is x86_64" exit 1 fi fi # Validation of chosen Arm NN dependencies if [ "$flag_tflite_classic_delegate" -eq 0 ] && [ "$flag_tflite_opaque_delegate" -eq 0 ] && [ "$flag_tflite_parser" -eq 0 ] && [ "$flag_onnx_parser" -eq 0 ]; then echo "$name: at least one of flags --tflite-classic-delegate, --tflite-opaque-delegate, --tflite-parser or --onnx-parser must be set (or --all)." exit 1 fi # If --num-threads is set, overwrite default NUM_THREADS with user-defined value if [ ! "$num_threads" -eq 0 ]; then NUM_THREADS="$num_threads" fiarmnn-23.08/cmake/000077500000000000000000000000001446772241200137325ustar00rootroot00000000000000armnn-23.08/cmake/AddDllCopyCommands.cmake000066400000000000000000000033141446772241200203760ustar00rootroot00000000000000# # Copyright © 2018-2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # macro (addDllCopyCommand target sourceDebug sourceRelease) add_custom_command(TARGET ${target} POST_BUILD COMMAND ${CMAKE_COMMAND} -E copy_if_different "$<$:${sourceDebug}>$<$:${sourceRelease}>$<$:${sourceRelease}>$<$:${sourceRelease}>" $) endmacro() # Checks if the given list contains an entry which matches the given regex. function(listContainsRegex result list regex) set(${result} 0 PARENT_SCOPE) foreach(element ${list}) if(${element} MATCHES ${regex}) set(${result} 1 PARENT_SCOPE) return() endif() endforeach() endfunction() macro(addDllCopyCommands target) if(${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC) # Get the list of dependencies for the given target, so we can copy just the DLLs we need. get_target_property(target_deps_str ${target} LINK_LIBRARIES) set(target_deps) list(APPEND target_deps ${target_deps_str}) cmake_policy(SET CMP0057 NEW) # Enable the "IN_LIST" operator # armnn.dll if ("armnn" IN_LIST target_deps) addDllCopyCommand(${target} "$/armnn.dll" "$/armnn.dll") endif() # armnnTfLiteParser.dll if ("armnnTfLiteParser" IN_LIST target_deps) addDllCopyCommand(${target} "$/armnnTfLiteParser.dll" "$/armnnTfLiteParser.dll") endif() endif() endmacro() armnn-23.08/cmake/ArmnnConfig.cmake.in000066400000000000000000000010701446772241200175400ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # get_filename_component(ARMNN_CMAKE_DIR "${CMAKE_CURRENT_LIST_FILE}" DIRECTORY) set(ARMNN_CONFIG_FILE ${CMAKE_CURRENT_LIST_FILE}) MESSAGE(STATUS "Found Armnn: ${ARMNN_CONFIG_FILE}") include(CMakeFindDependencyMacro) list(APPEND CMAKE_MODULE_PATH ${ARMNN_CMAKE_DIR}) if(NOT TARGET Armnn::Armnn) MESSAGE(STATUS "Armnn Import: ${ARMNN_CMAKE_DIR}/ArmnnTargets.cmake") include("${ARMNN_CMAKE_DIR}/ArmnnTargets.cmake") endif() set(ARMNN_LIBRARIES Armnn::Armnn)armnn-23.08/cmake/ArmnnTestUtilsVersion.cmake000066400000000000000000000015021446772241200212340ustar00rootroot00000000000000# # Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Read the ArmNN armnnTestUtils version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../include/armnnTestUtils/Version.hpp armnnTestUtilsVersion) # Parse the ArmNN armnnTestUtils version components string(REGEX MATCH "#define ARMNN_TEST_UTILS_MAJOR_VERSION ([0-9]*)" _ ${armnnTestUtilsVersion}) set(ARMNN_TEST_UTILS_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define ARMNN_TEST_UTILS_MINOR_VERSION ([0-9]*)" _ ${armnnTestUtilsVersion}) set(ARMNN_TEST_UTILS_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(ARMNN_TEST_UTILS_LIB_VERSION "${ARMNN_TEST_UTILS_MAJOR_VERSION}.${ARMNN_TEST_UTILS_MINOR_VERSION}") # Define LIB soversion set(ARMNN_TEST_UTILS_LIB_SOVERSION "${ARMNN_TEST_UTILS_MAJOR_VERSION}")armnn-23.08/cmake/ArmnnVersion.cmake000066400000000000000000000012221446772241200173520ustar00rootroot00000000000000# # Copyright © 2019 Arm Ltd. All rights reserved. # SPDX-License-Identifier: MIT # # Read the ArmNN version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../include/armnn/Version.hpp armnnVersion) # Parse the ArmNN version components string(REGEX MATCH "#define ARMNN_MAJOR_VERSION ([0-9]*)" _ ${armnnVersion}) set(ARMNN_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define ARMNN_MINOR_VERSION ([0-9]*)" _ ${armnnVersion}) set(ARMNN_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(GENERIC_LIB_VERSION "${ARMNN_MAJOR_VERSION}.${ARMNN_MINOR_VERSION}") # Define LIB soversion set(GENERIC_LIB_SOVERSION "${ARMNN_MAJOR_VERSION}") armnn-23.08/cmake/ClassicDelegateVersion.cmake000066400000000000000000000013701446772241200213170ustar00rootroot00000000000000# # Copyright © 2021,2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Read the ArmNN Delegate version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../delegate/classic/include/Version.hpp ClassicDelegateVersion) # Parse the ArmNN Delegate version components string(REGEX MATCH "#define DELEGATE_MAJOR_VERSION ([0-9]*)" _ ${ClassicDelegateVersion}) set(DELEGATE_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define DELEGATE_MINOR_VERSION ([0-9]*)" _ ${ClassicDelegateVersion}) set(DELEGATE_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(DELEGATE_LIB_VERSION "${DELEGATE_MAJOR_VERSION}.${DELEGATE_MINOR_VERSION}") # Define LIB soversion set(DELEGATE_LIB_SOVERSION "${DELEGATE_MAJOR_VERSION}")armnn-23.08/cmake/GlobalConfig.cmake000066400000000000000000000537551446772241200173010ustar00rootroot00000000000000# # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # Copyright 2020 NXP # SPDX-License-Identifier: MIT # option(BUILD_ONNX_PARSER "Build Onnx parser" OFF) option(BUILD_UNIT_TESTS "Build unit tests" ON) option(BUILD_TESTS "Build test applications" OFF) option(ARMNN_SAMPLE_APPS_ENABLED "Build Sample ArmNN Applications" ON) option(BUILD_FOR_COVERAGE "Use no optimization and output .gcno and .gcda files" OFF) option(ARMCOMPUTENEON "Build with ARM Compute NEON support" OFF) option(ARMCOMPUTECL "Build with ARM Compute OpenCL support" OFF) option(ARMNNREF "Build with ArmNN reference support" ON) option(ARMNNTOSAREF "Build with TOSA reference support" OFF) option(PROFILING_BACKEND_STREAMLINE "Forward the armNN profiling events to DS-5/Streamline as annotations" OFF) # options used for heap profiling and leak checking option(HEAP_PROFILING "Build with heap profiling enabled" OFF) option(LEAK_CHECKING "Build with leak checking enabled" OFF) option(GPERFTOOLS_ROOT "Location where the gperftools 'include' and 'lib' folders to be found" Off) # options used for tensorflow lite support option(BUILD_TF_LITE_PARSER "Build Tensorflow Lite parser" OFF) option(BUILD_ARMNN_SERIALIZER "Build Armnn Serializer" OFF) option(BUILD_ACCURACY_TOOL "Build Accuracy Tool" OFF) option(FLATC_DIR "Path to Flatbuffers compiler" OFF) option(TF_LITE_GENERATED_PATH "Tensorflow lite generated C++ schema location" OFF) option(FLATBUFFERS_ROOT "Location where the flatbuffers 'include' and 'lib' folders to be found" Off) option(TOSA_SERIALIZATION_LIB_ROOT "Location where the TOSA Serialization Library 'include' and 'lib' folders can be found" OFF) option(TOSA_REFERENCE_MODEL_ROOT "Location where the TOSA Reference Model 'include' and 'lib' folders can be found" OFF) option(TOSA_REFERENCE_MODEL_OUTPUT "TOSA Reference Model output is printed during layer support checks" ON) option(DYNAMIC_BACKEND_PATHS "Colon seperated list of paths where to load the dynamic backends from" "") option(SAMPLE_DYNAMIC_BACKEND "Include the sample dynamic backend and its tests in the build" OFF) option(BUILD_GATORD_MOCK "Build the Gatord simulator for external profiling testing." ON) option(BUILD_TIMELINE_DECODER "Build the Timeline Decoder for external profiling." ON) option(BUILD_BASE_PIPE_SERVER "Build the server to handle external profiling pipe traffic" ON) option(BUILD_PYTHON_WHL "Build Python wheel package" OFF) option(BUILD_PYTHON_SRC "Build Python source package" OFF) option(BUILD_STATIC_PIPE_LIBS "Build Static PIPE libraries" OFF) option(BUILD_PIPE_ONLY "Build the PIPE libraries only" OFF) option(BUILD_CLASSIC_DELEGATE "Build the Arm NN TfLite delegate" OFF) option(BUILD_OPAQUE_DELEGATE "Build the Arm NN TfLite Opaque delegate" OFF) option(BUILD_MEMORY_STRATEGY_BENCHMARK "Build the MemoryBenchmark" OFF) option(BUILD_BARE_METAL "Disable features requiring operating system support" OFF) option(BUILD_SHARED_LIBS "Determines if Armnn will be built statically or dynamically. This is an experimental feature and not fully supported. Only the ArmNN core and the Delegate can be built statically." ON) option(EXECUTE_NETWORK_STATIC " This is a limited experimental build that is entirely static. It currently only supports being set by changing the current CMake default options like so: BUILD_TF_LITE_PARSER=1/0 BUILD_ARMNN_SERIALIZER=1/0 ARMCOMPUTENEON=1/0 ARMNNREF=1/0 ARMCOMPUTECL=0 BUILD_ONNX_PARSER=0 BUILD_CLASSIC_DELEGATE=0 BUILD_OPAQUE_DELEGATE=0 BUILD_TIMELINE_DECODER=0 BUILD_BASE_PIPE_SERVER=0 BUILD_UNIT_TESTS=0 ARMNN_SAMPLE_APPS_ENABLED=0 BUILD_SHARED_LIBS=0 BUILD_GATORD_MOCK=0 HEAP_PROFILING=0 LEAK_CHECKING=0" OFF) if(BUILD_ARMNN_TFLITE_DELEGATE) message(BUILD_ARMNN_TFLITE_DELEGATE option is deprecated, it will be removed in 24.02, please use BUILD_CLASSIC_DELEGATE instead) set(BUILD_CLASSIC_DELEGATE 1) endif() include(SelectLibraryConfigurations) set(COMPILER_IS_GNU_LIKE 0) if(${CMAKE_CXX_COMPILER_ID} STREQUAL GNU OR ${CMAKE_CXX_COMPILER_ID} STREQUAL Clang OR ${CMAKE_CXX_COMPILER_ID} STREQUAL AppleClang) set(COMPILER_IS_GNU_LIKE 1) endif() # Enable CCache if available and not disabled option(USE_CCACHE "USE_CCACHE" ON) find_program(CCACHE_FOUND ccache) if(CCACHE_FOUND AND USE_CCACHE) get_property(rule_launch_compile DIRECTORY PROPERTY RULE_LAUNCH_COMPILE) set_property(DIRECTORY PROPERTY RULE_LAUNCH_COMPILE "CCACHE_CPP2=yes ${rule_launch_compile} ccache") endif() # Enable distcc if available and not disabled option(USE_DISTCC "USE_DISTCC" OFF) find_program(DISTCC_FOUND distcc) if(DISTCC_FOUND AND USE_DISTCC) get_property(rule_launch_compile DIRECTORY PROPERTY RULE_LAUNCH_COMPILE) set_property(DIRECTORY PROPERTY RULE_LAUNCH_COMPILE "${rule_launch_compile} distcc") endif() # Set to release configuration by default if(NOT CMAKE_BUILD_TYPE) set(CMAKE_BUILD_TYPE "Release") endif() # Compiler flags that are always set set(CMAKE_POSITION_INDEPENDENT_CODE ON) if(COMPILER_IS_GNU_LIKE) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++17 -Wall -Wextra -Werror -Wold-style-cast -Wno-missing-braces -Wconversion -Wsign-conversion") if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-psabi") endif() elseif(${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC) # Disable C4996 (use of deprecated identifier) due to # https://developercommunity.visualstudio.com/content/problem/252574/deprecated-compilation-warning-for-virtual-overrid.html set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} /EHsc /MP /wd4996") add_definitions(-DNO_STRICT=1) endif() if("${CMAKE_SYSTEM_NAME}" STREQUAL Android) # -lz is necessary for when building with ACL set with compressed kernels set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -llog -lz") set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -llog -lz") endif() # Compiler flags for Release builds set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -DNDEBUG") if(COMPILER_IS_GNU_LIKE) set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3") elseif(${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC) set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MD /O2") endif() # Compiler flags for Debug builds if(COMPILER_IS_GNU_LIKE) set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -g -O0") elseif(${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC) set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MDd /ZI /Od") # Disable SAFESEH which is necessary for Edit and Continue to work set(CMAKE_EXE_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} /SAFESEH:NO") set(CMAKE_SHARED_LINKER_FLAGS_DEBUG "${CMAKE_EXE_LINKER_FLAGS_DEBUG} /SAFESEH:NO") endif() # Modify RelWithDebInfo so that NDEBUG isn't defined. # This enables asserts. if (COMPILER_IS_GNU_LIKE) string(REPLACE "-DNDEBUG" "" CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO}") elseif (${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC) string(REPLACE "/DNDEBUG" "" CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO}") endif() # Compiler flags for code coverage measurements if(BUILD_FOR_COVERAGE) if(NOT CMAKE_BUILD_TYPE EQUAL "Debug") message(WARNING "BUILD_FOR_COVERAGE set so forcing to Debug build") set(CMAKE_BUILD_TYPE "Debug") endif() set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} --coverage") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} --coverage") endif() if(BUILD_FOR_COVERAGE AND NOT BUILD_UNIT_TESTS) message(WARNING "BUILD_FOR_COVERAGE set but not BUILD_UNIT_TESTS, so code coverage will not be able to run") endif() set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules ${CMAKE_MODULE_PATH}) include(CMakeFindDependencyMacro) if(EXECUTE_NETWORK_STATIC) add_definitions(-DARMNN_DISABLE_SOCKETS -DARMNN_STUB_PROFILING -DARMNN_DISABLE_DYNAMIC_BACKENDS) set(ARMNN_SAMPLE_APPS_ENABLED 0) set(DISABLE_DYNAMIC_BACKENDS 1) set(BUILD_SHARED_LIBS 0) endif() if(BUILD_BARE_METAL) add_definitions(-DARMNN_BUILD_BARE_METAL -DARMNN_DISABLE_FILESYSTEM -DARMNN_DISABLE_PROCESSES -DARMNN_DISABLE_THREADS -DARMNN_DISABLE_SOCKETS -DARMNN_STUB_PROFILING -DARMNN_DISABLE_DYNAMIC_BACKENDS) set(DISABLE_DYNAMIC_BACKENDS 1) set(BUILD_SHARED_LIBS 0) endif() if (NOT BUILD_PIPE_ONLY) # cxxopts (Alternative to boost::program_options) find_path(CXXOPTS_INCLUDE cxxopts/cxxopts.hpp PATHS third-party NO_CMAKE_FIND_ROOT_PATH) include_directories(SYSTEM "${CXXOPTS_INCLUDE}") endif() if (NOT BUILD_PIPE_ONLY) # ghc (Alternative to boost::filesystem) find_path(GHC_INCLUDE ghc/filesystem.hpp PATHS third-party NO_CMAKE_FIND_ROOT_PATH) include_directories(SYSTEM "${GHC_INCLUDE}") endif() # JNI_BUILD has DBUILD_SHARED_LIBS set to 0 and not finding libs while building # hence added NOT BUILD_CLASSIC_DELEGATE/BUILD_OPAQUE_DELEGATE condition if(NOT BUILD_SHARED_LIBS AND NOT BUILD_CLASSIC_DELEGATE AND NOT BUILD_OPAQUE_DELEGATE) set(CMAKE_FIND_LIBRARY_SUFFIXES .a .lib) endif() # pthread if (NOT BUILD_BARE_METAL) find_package(Threads) endif() if (EXECUTE_NETWORK_STATIC) set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static-libstdc++ -static-libgcc -static -pthread") endif() # Favour the protobuf passed on command line if(BUILD_ONNX_PARSER) find_library(PROTOBUF_LIBRARY_DEBUG NAMES "protobufd" PATHS ${PROTOBUF_ROOT}/lib NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_library(PROTOBUF_LIBRARY_DEBUG NAMES "protobufd") find_library(PROTOBUF_LIBRARY_RELEASE NAMES "protobuf" PATHS ${PROTOBUF_ROOT}/lib NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_library(PROTOBUF_LIBRARY_RELEASE NAMES "protobuf") select_library_configurations(PROTOBUF) find_path(PROTOBUF_INCLUDE_DIRS "google/protobuf/message.h" PATHS ${PROTOBUF_ROOT}/include NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_path(PROTOBUF_INCLUDE_DIRS "google/protobuf/message.h") include_directories(SYSTEM "${PROTOBUF_INCLUDE_DIRS}") add_definitions(-DPROTOBUF_USE_DLLS) add_definitions(-DARMNN_ONNX_PARSER) find_path(ONNX_GENERATED_SOURCES "onnx/onnx.pb.cc") # C++ headers generated for onnx protobufs include_directories(SYSTEM "${ONNX_GENERATED_SOURCES}") endif() if(BUILD_CLASSIC_DELEGATE) add_definitions(-DARMNN_TFLITE_DELEGATE) endif() if(BUILD_OPAQUE_DELEGATE) add_definitions(-DARMNN_TFLITE_OPAQUE_DELEGATE) endif() # Flatbuffers support for TF Lite, Armnn Serializer or the TOSA backend. if(BUILD_TF_LITE_PARSER OR BUILD_ARMNN_SERIALIZER OR ARMNNTOSAREF) # verify we have a valid flatbuffers include path find_path(FLATBUFFERS_INCLUDE_PATH flatbuffers/flatbuffers.h HINTS ${FLATBUFFERS_ROOT}/include /usr/local/include /usr/include) message(STATUS "Flatbuffers headers are located at: ${FLATBUFFERS_INCLUDE_PATH}") find_library(FLATBUFFERS_LIBRARY NAMES libflatbuffers.a flatbuffers HINTS ${FLATBUFFERS_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "Flatbuffers library located at: ${FLATBUFFERS_LIBRARY}") endif() # Flatbuffers schema support for TF Lite if(BUILD_TF_LITE_PARSER) find_path(TF_LITE_SCHEMA_INCLUDE_PATH schema_generated.h HINTS ${TF_LITE_GENERATED_PATH}) message(STATUS "Tf Lite generated header found at: ${TF_LITE_SCHEMA_INCLUDE_PATH}") add_definitions(-DARMNN_TF_LITE_PARSER) endif() if(BUILD_ARMNN_SERIALIZER) add_definitions(-DARMNN_SERIALIZER) add_definitions(-DARMNN_SERIALIZER_SCHEMA_PATH="${CMAKE_CURRENT_SOURCE_DIR}/src/armnnSerializer/ArmnnSchema.fbs") endif() include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) include_directories(${CMAKE_CURRENT_SOURCE_DIR}/profiling) # ARM Compute # Note that ARM Compute has a different folder layout depending on the branch but also on # whether it comes from a prepackaged archive (this is why we add several hints below) if(ARMCOMPUTENEON OR ARMCOMPUTECL) find_path(ARMCOMPUTE_INCLUDE arm_compute/core/CL/OpenCL.h PATHS ${ARMCOMPUTE_ROOT}/include PATHS ${ARMCOMPUTE_ROOT}/applications/arm_compute PATHS ${ARMCOMPUTE_ROOT} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_path(ARMCOMPUTE_INCLUDE arm_compute/core/CL/OpenCL.h) include_directories(SYSTEM "${ARMCOMPUTE_INCLUDE}") # Find the Arm Compute libraries if not already specified (the user may have already defined this in advance, # e.g. if building clframework as a dependent cmake project) if (NOT DEFINED ARMCOMPUTE_LIBRARIES) # We link to the static variant so that customers don't need to find and build a compatible version of clframework. # First try the folders specified ARMCOMPUTE_BUILD_DIR (with PATH_SUFFIXES for # Windows builds) if ((NOT DEFINED ARMCOMPUTE_BUILD_DIR) AND (DEFINED ARMCOMPUTE_ROOT)) # Default build directory for ComputeLibrary is under the root set(ARMCOMPUTE_BUILD_DIR ${ARMCOMPUTE_ROOT}/build) endif() find_library(ARMCOMPUTE_LIBRARY_DEBUG NAMES arm_compute-static PATHS ${ARMCOMPUTE_BUILD_DIR} PATH_SUFFIXES "Debug" NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_library(ARMCOMPUTE_LIBRARY_RELEASE NAMES arm_compute-static PATHS ${ARMCOMPUTE_BUILD_DIR} PATH_SUFFIXES "Release" NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_library(ARMCOMPUTE_CORE_LIBRARY_DEBUG NAMES arm_compute_core-static PATHS ${ARMCOMPUTE_BUILD_DIR} PATH_SUFFIXES "Debug" NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) find_library(ARMCOMPUTE_CORE_LIBRARY_RELEASE NAMES arm_compute_core-static PATHS ${ARMCOMPUTE_BUILD_DIR} PATH_SUFFIXES "Release" NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) # In case it wasn't there, try a default search (will work in cases where # the library has been installed into a standard location) find_library(ARMCOMPUTE_LIBRARY_DEBUG NAMES arm_compute-static) find_library(ARMCOMPUTE_LIBRARY_RELEASE NAMES arm_compute-static) find_library(ARMCOMPUTE_CORE_LIBRARY_DEBUG NAMES arm_compute_core-static) find_library(ARMCOMPUTE_CORE_LIBRARY_RELEASE NAMES arm_compute_core-static) # In case it wasn't there, try the dynamic libraries # This case will get used in a linux setup where the Compute Library # has been installed in a standard system library path as a dynamic library find_library(ARMCOMPUTE_LIBRARY_DEBUG NAMES arm_compute) find_library(ARMCOMPUTE_LIBRARY_RELEASE NAMES arm_compute) find_library(ARMCOMPUTE_CORE_LIBRARY_DEBUG NAMES arm_compute_core) find_library(ARMCOMPUTE_CORE_LIBRARY_RELEASE NAMES arm_compute_core) set(ARMCOMPUTE_LIBRARIES debug ${ARMCOMPUTE_LIBRARY_DEBUG} ${ARMCOMPUTE_CORE_LIBRARY_DEBUG} optimized ${ARMCOMPUTE_LIBRARY_RELEASE} ${ARMCOMPUTE_CORE_LIBRARY_RELEASE} ) endif() endif() # ARM Compute NEON backend if(ARMCOMPUTENEON) # Add preprocessor definition for ARM Compute NEON add_definitions(-DARMCOMPUTENEON_ENABLED) # The ARM Compute headers contain some NEON intrinsics, so we need to build armnn with NEON support on armv7 if(${CMAKE_SYSTEM_PROCESSOR} MATCHES armv7 AND COMPILER_IS_GNU_LIKE) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mfpu=neon") endif() endif() # ARM Compute OpenCL backend if(ARMCOMPUTECL) # verify we have a valid flatbuffers include path find_path(FLATBUFFERS_INCLUDE_PATH flatbuffers/flatbuffers.h HINTS ${FLATBUFFERS_ROOT}/include /usr/local/include /usr/include) message(STATUS "Flatbuffers headers are located at: ${FLATBUFFERS_INCLUDE_PATH}") find_library(FLATBUFFERS_LIBRARY NAMES libflatbuffers.a flatbuffers HINTS ${FLATBUFFERS_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "Flatbuffers library located at: ${FLATBUFFERS_LIBRARY}") # Always use Arm compute library OpenCL headers find_path(OPENCL_INCLUDE CL/opencl.hpp PATHS ${ARMCOMPUTE_ROOT}/include NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) # Link against libOpenCL in opencl-1.2-stubs, but don't search there at runtime link_libraries(-L${ARMCOMPUTE_BUILD_DIR}/opencl-1.2-stubs) set(OPENCL_LIBRARIES OpenCL) include_directories(SYSTEM ${OPENCL_INCLUDE}) # Add preprocessor definition for ARM Compute OpenCL add_definitions(-DARMCOMPUTECL_ENABLED) set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -DARM_COMPUTE_DEBUG_ENABLED") endif() # Used by both Arm Compute backends, but should be added # to the search path after the system directories if necessary if(ARMCOMPUTENEON OR ARMCOMPUTECL) find_path(HALF_INCLUDE half/half.hpp) find_path(HALF_INCLUDE half/half.hpp PATHS ${ARMCOMPUTE_ROOT}/include NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) include_directories(SYSTEM ${HALF_INCLUDE}) endif() # ArmNN reference backend if(ARMNNREF) add_definitions(-DARMNNREF_ENABLED) endif() # If a backend requires TOSA common, add it here. if(ARMNNTOSAREF) set(ARMNNTOSACOMMON ON) endif() if(ARMNNTOSACOMMON) # Locate the includes for the TOSA serialization library as it is needed for TOSA common and TOSA backends. message(STATUS "TOSA serialization library root set to ${TOSA_SERIALIZATION_LIB_ROOT}") find_path(TOSA_SERIALIZATION_LIB_INCLUDE tosa_serialization_handler.h HINTS ${TOSA_SERIALIZATION_LIB_ROOT}/include) message(STATUS "TOSA serialization library include directory located at: ${TOSA_SERIALIZATION_LIB_INCLUDE}") find_library(TOSA_SERIALIZATION_LIB NAMES tosa_serialization_lib.a tosa_serialization_lib HINTS ${TOSA_SERIALIZATION_LIB_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "TOSA serialization library set to ${TOSA_SERIALIZATION_LIB}") # Include required headers for TOSA Serialization Library include_directories(SYSTEM ${FLATBUFFERS_INCLUDE_PATH}) include_directories(SYSTEM ${PROJECT_SOURCE_DIR}/third-party/half) include_directories(SYSTEM ${TOSA_SERIALIZATION_LIB_INCLUDE}) endif() # ArmNN TOSA reference backend if(ARMNNTOSAREF) # Locate the includes for the TOSA Reference Model, which is specific to the TOSA Reference Backend. message(STATUS "TOSA Reference Model root set to ${TOSA_REFERENCE_MODEL_ROOT}") find_path(TOSA_REFERENCE_MODEL_INCLUDE model_runner.h HINTS ${TOSA_REFERENCE_MODEL_ROOT}/include) message(STATUS "TOSA Reference Model include directory located at: ${TOSA_REFERENCE_MODEL_INCLUDE}") include_directories(SYSTEM ${TOSA_REFERENCE_MODEL_INCLUDE}) find_library(TOSA_REFERENCE_MODEL_LIB NAMES tosa_reference_model_lib.a tosa_reference_model_lib HINTS ${TOSA_REFERENCE_MODEL_ROOT}/lib /usr/local/lib /usr/lib) message(STATUS "TOSA Reference Model set to ${TOSA_REFERENCE_MODEL_LIB}") if(TOSA_REFERENCE_MODEL_OUTPUT) add_definitions("-DTOSA_REFERENCE_MODEL_OUTPUT=1") endif() endif() # This is the root for the dynamic backend tests to search for dynamic # backends. By default it will be the project build directory. add_definitions(-DDYNAMIC_BACKEND_BUILD_DIR="${PROJECT_BINARY_DIR}") # ArmNN dynamic backend if(DYNAMIC_BACKEND_PATHS) add_definitions(-DARMNN_DYNAMIC_BACKEND_ENABLED) endif() if(SAMPLE_DYNAMIC_BACKEND) add_definitions(-DSAMPLE_DYNAMIC_BACKEND_ENABLED) endif() # Streamline annotate if(PROFILING_BACKEND_STREAMLINE) include_directories("${GATOR_ROOT}/annotate") add_definitions(-DARMNN_STREAMLINE_ENABLED) endif() if(HEAP_PROFILING OR LEAK_CHECKING) find_path(HEAP_PROFILER_INCLUDE gperftools/heap-profiler.h PATHS ${GPERFTOOLS_ROOT}/include NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) include_directories(SYSTEM "${HEAP_PROFILER_INCLUDE}") find_library(GPERF_TOOLS_LIBRARY NAMES tcmalloc_debug HINTS ${GPERFTOOLS_ROOT}/lib) link_directories(${GPERFTOOLS_ROOT}/lib) link_libraries(${GPERF_TOOLS_LIBRARY}) if (HEAP_PROFILING) add_definitions("-DARMNN_HEAP_PROFILING_ENABLED=1") endif() if (LEAK_CHECKING) add_definitions("-DARMNN_LEAK_CHECKING_ENABLED=1") endif() else() # Valgrind only works with gperftools version number <= 2.4 include(CheckIncludeFiles) CHECK_INCLUDE_FILES("valgrind/memcheck.h" VALGRIND_FOUND) endif() if(NOT BUILD_TF_LITE_PARSER) message(STATUS "Tensorflow Lite parser support is disabled") endif() if(NOT BUILD_ARMNN_SERIALIZER) message(STATUS "Armnn Serializer support is disabled") endif() if(NOT BUILD_PYTHON_WHL) message(STATUS "PyArmNN wheel package is disabled") endif() if(NOT BUILD_PYTHON_SRC) message(STATUS "PyArmNN source package is disabled") endif() if(BUILD_PYTHON_WHL OR BUILD_PYTHON_SRC) find_package(PythonInterp 3 REQUIRED) if(NOT ${PYTHONINTERP_FOUND}) message(FATAL_ERROR "Python 3.x required to build PyArmNN, but not found") endif() find_package(PythonLibs 3 REQUIRED) if(NOT ${PYTHONLIBS_FOUND}) message(FATAL_ERROR "Python 3.x development package required to build PyArmNN, but not found") endif() find_package(SWIG 4 REQUIRED) if(NOT ${SWIG_FOUND}) message(FATAL_ERROR "SWIG 4.x requried to build PyArmNN, but not found") endif() endif() # ArmNN source files required for all build options include_directories(SYSTEM third-party) armnn-23.08/cmake/OpaqueDelegateVersion.cmake000066400000000000000000000014561446772241200211750ustar00rootroot00000000000000# # Copyright © 2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Read the ArmNN Delegate version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../delegate/opaque/include/Version.hpp opaqueDelegateVersion) # Parse the ArmNN Delegate version components string(REGEX MATCH "#define OPAQUE_DELEGATE_MAJOR_VERSION ([0-9]*)" _ ${opaqueDelegateVersion}) set(OPAQUE_DELEGATE_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define OPAQUE_DELEGATE_MINOR_VERSION ([0-9]*)" _ ${opaqueDelegateVersion}) set(OPAQUE_DELEGATE_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(OPAQUE_DELEGATE_LIB_VERSION "${OPAQUE_DELEGATE_MAJOR_VERSION}.${OPAQUE_DELEGATE_MINOR_VERSION}") # Define LIB soversion set(OPAQUE_DELEGATE_LIB_SOVERSION "${OPAQUE_DELEGATE_MINOR_VERSION}")armnn-23.08/cmake/ParserVersion.cmake000066400000000000000000000026041446772241200175400ustar00rootroot00000000000000# # Copyright © 2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Read the OnnxParser version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../include/armnnOnnxParser/Version.hpp onnxVersion) # Parse the OnnxParser version components string(REGEX MATCH "#define ONNX_PARSER_MAJOR_VERSION ([0-9]*)" _ ${onnxVersion}) set(ONNX_PARSER_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define ONNX_PARSER_MINOR_VERSION ([0-9]*)" _ ${onnxVersion}) set(ONNX_PARSER_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(ONNX_PARSER_LIB_VERSION "${ONNX_PARSER_MAJOR_VERSION}.${ONNX_PARSER_MINOR_VERSION}") # Define LIB soversion set(ONNX_PARSER_LIB_SOVERSION "${ONNX_PARSER_MAJOR_VERSION}") # Read the TfLiteParser version components from file file(READ ${CMAKE_CURRENT_LIST_DIR}/../include/armnnTfLiteParser/Version.hpp tfLiteVersion) # Parse the TfLiteParser version components string(REGEX MATCH "#define TFLITE_PARSER_MAJOR_VERSION ([0-9]*)" _ ${tfLiteVersion}) set(TFLITE_PARSER_MAJOR_VERSION ${CMAKE_MATCH_1}) string(REGEX MATCH "#define TFLITE_PARSER_MINOR_VERSION ([0-9]*)" _ ${tfLiteVersion}) set(TFLITE_PARSER_MINOR_VERSION ${CMAKE_MATCH_1}) # Define LIB version set(TFLITE_PARSER_LIB_VERSION "${TFLITE_PARSER_MAJOR_VERSION}.${TFLITE_PARSER_MINOR_VERSION}") # Define LIB soversion set(TFLITE_PARSER_LIB_SOVERSION "${TFLITE_PARSER_MAJOR_VERSION}")armnn-23.08/cmake/Utils.cmake000066400000000000000000000042441446772241200160400ustar00rootroot00000000000000# # Copyright © 2018 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # # Function which creates appropriate "source groups" (filter folders in Visual Studio) for the given list of source files function(createSourceGroups source1) set(sources ${source1} ${ARGN}) foreach(source ${sources}) get_filename_component(source_path ${source} PATH) string(REPLACE "/" "\\" source_path_backslashes "${source_path}") source_group(${source_path_backslashes} FILES ${source}) endforeach() endfunction() # Further processes a target and its list of source files adding extra touches useful for some generators # (filter folders, group targets in folders, etc.). # All optional arguments are treated as additional source files. function(setup_target targetName source1) set(sources ${source1} ${ARGN}) createSourceGroups(${sources}) # Enable USE_FOLDERS. This is required by the set_target_properties(... FOLDER ...) call below. # We prefer to set it here rather than globally at the top of the file so that we only modify # the Cmake environment if/when the functionality is actually required. set_property(GLOBAL PROPERTY USE_FOLDERS ON) file(RELATIVE_PATH projectFolder ${CMAKE_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}) set_target_properties(${targetName} PROPERTIES FOLDER "${projectFolder}") endfunction() # Convenience replacement of add_executable(), which besides adding an executable to the project # further configures the target via setup_target(). # All optional arguments are treated as additional source files. function(add_executable_ex targetName source1) set(sources ${source1} ${ARGN}) add_executable(${targetName} ${sources}) setup_target(${targetName} ${sources}) endfunction() # Convenience replacement of add_library(), which besides adding a library to the project # further configures the target via setup_target(). # All optional arguments are treated as additional source files. function(add_library_ex targetName libraryType source1) set(sources ${source1} ${ARGN}) add_library(${targetName} ${libraryType} ${sources}) setup_target(${targetName} ${sources}) endfunction() armnn-23.08/delegate/000077500000000000000000000000001446772241200144245ustar00rootroot00000000000000armnn-23.08/delegate/BuildGuideNative.md000066400000000000000000000112741446772241200201370ustar00rootroot00000000000000# Delegate Build Guide This guide assumes that Arm NN has been built with the Arm NN TF Lite Delegate with the [Arm NN Build Tool](../build-tool/README.md).
The Arm NN TF Lite Delegate can also be obtained from downloading the [Pre-Built Binaries on the GitHub homepage](../README.md). **Table of Contents:** - [Running DelegateUnitTests](#running-delegateunittests) - [Run the TF Lite Benchmark Tool](#run-the-tflite-model-benchmark-tool) - [Download the TFLite Model Benchmark Tool](#download-the-tflite-model-benchmark-tool) - [Execute the benchmarking tool with the Arm NN TF Lite Delegate](#execute-the-benchmarking-tool-with-the-arm-nn-tf-lite-delegate) - [Integrate the Arm NN TfLite Delegate into your project](#integrate-the-arm-nn-tflite-delegate-into-your-project) ## Running DelegateUnitTests To ensure that the build was successful you can run the unit tests for the delegate that can be found in the build directory for the delegate. [Doctest](https://github.com/onqtam/doctest) was used to create those tests. Using test filters you can filter out tests that your build is not configured for. In this case, we run all test suites that have `CpuAcc` in their name. ```bash cd /delegate/build ./DelegateUnitTests --test-suite=*CpuAcc* ``` If you have built for Gpu acceleration as well you might want to change your test-suite filter: ```bash ./DelegateUnitTests --test-suite=*CpuAcc*,*GpuAcc* ``` ## Run the TFLite Model Benchmark Tool The [TFLite Model Benchmark](https://github.com/tensorflow/tensorflow/tree/master/tensorflow/lite/tools/benchmark) Tool has a useful command line interface to test the TF Lite Delegate. We can use this to demonstrate the use of the Arm NN TF Lite Delegate and its options. Some examples of this can be viewed in this [YouTube demonstration](https://www.youtube.com/watch?v=NResQ1kbm-M&t=920s). ### Download the TFLite Model Benchmark Tool Binary builds of the benchmarking tool for various platforms are available [here](https://www.tensorflow.org/lite/performance/measurement#native_benchmark_binary). In this example I will target an aarch64 Linux environment. I will also download a sample uint8 tflite model from the [Arm ML Model Zoo](https://github.com/ARM-software/ML-zoo). ```bash mkdir $BASEDIR/benchmarking cd $BASEDIR/benchmarking # Get the benchmarking binary. wget https://storage.googleapis.com/tensorflow-nightly-public/prod/tensorflow/release/lite/tools/nightly/latest/linux_aarch64_benchmark_model -O benchmark_model # Make it executable. chmod +x benchmark_model # and a sample model from model zoo. wget https://github.com/ARM-software/ML-zoo/blob/master/models/image_classification/mobilenet_v2_1.0_224/tflite_uint8/mobilenet_v2_1.0_224_quantized_1_default_1.tflite?raw=true -O mobilenet_v2_1.0_224_quantized_1_default_1.tflite ``` ### Execute the benchmarking tool with the Arm NN TF Lite Delegate You are already at $BASEDIR/benchmarking from the previous stage. ```bash LD_LIBRARY_PATH= ./benchmark_model --graph=mobilenet_v2_1.0_224_quantized_1_default_1.tflite --external_delegate_path="/delegate/libarmnnDelegate.so" --external_delegate_options="backends:CpuAcc;logging-severity:info" ``` The "external_delegate_options" here are specific to the Arm NN delegate. They are used to specify a target Arm NN backend or to enable/disable various options in Arm NN. A full description can be found in the parameters of function tflite_plugin_create_delegate. ## Integrate the Arm NN TfLite Delegate into your project The delegate can be integrated into your c++ project by creating a TfLite Interpreter and instructing it to use the Arm NN delegate for the graph execution. This should look similar to the following code snippet. ```objectivec // Create TfLite Interpreter std::unique_ptr armnnDelegateInterpreter; InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) (&armnnDelegateInterpreter) // Create the Arm NN Delegate armnnDelegate::DelegateOptions delegateOptions(backends); std::unique_ptr theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), armnnDelegate::TfLiteArmnnDelegateDelete); // Instruct the Interpreter to use the armnnDelegate armnnDelegateInterpreter->ModifyGraphWithDelegate(theArmnnDelegate.get()); ``` For further information on using TfLite Delegates please visit the [TensorFlow website](https://www.tensorflow.org/lite/guide). For more details of the kind of options you can pass to the Arm NN delegate please check the parameters of function tflite_plugin_create_delegate. armnn-23.08/delegate/BuildGuideNative.md.license000066400000000000000000000001531446772241200215520ustar00rootroot00000000000000# # Copyright © 2020-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/CMakeLists.txt000066400000000000000000000345451446772241200171770ustar00rootroot00000000000000# # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # cmake_minimum_required (VERSION 3.7.0) project(armnnDelegate) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++17 -Wall -Wextra -Werror -Wold-style-cast -Wno-missing-braces -Wconversion -Wsign-conversion -Wno-comment") set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${PROJECT_SOURCE_DIR}/cmake/Modules/") option(BUILD_UNIT_TESTS "Build unit tests" ON) option(BUILD_CLASSIC_DELEGATE "Build classic delegate" ON) option(BUILD_OPAQUE_DELEGATE "Build opaque delegate" OFF) option(BUILD_SHARED_LIBS "Build share libs" ON) option(BUILD_DELEGATE_JNI_INTERFACE "Builds a library to allow accessing the Arm NN delegate from Java code. This is an experimental feature." ON) set(armnnDelegate_sources) list(APPEND armnnDelegate_sources common/include/DelegateOptions.hpp common/src/DelegateOptions.cpp common/src/DelegateUtils.hpp common/src/MultiLayerFacade.hpp) ## Add Armnn as a Dependency if(NOT ARMNN_SUB_PROJECT) find_package(Armnn REQUIRED CONFIG HINTS ${Armnn_DIR}) endif() if (BUILD_CLASSIC_DELEGATE) add_subdirectory(classic) add_library(armnnDelegate ${armnnDelegate_sources}) target_include_directories(armnnDelegate PUBLIC $ $ PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/common/src) endif() if (BUILD_OPAQUE_DELEGATE) add_subdirectory(opaque) add_library(armnnOpaqueDelegate ${armnnDelegate_sources}) target_include_directories(armnnOpaqueDelegate PUBLIC $ $ PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/common/src) endif() include(GNUInstallDirs) if (BUILD_CLASSIC_DELEGATE) target_link_libraries(armnnDelegate PUBLIC Armnn::Armnn) ## Add armnnClassicDelegateObject as a Dependency target_link_libraries(armnnDelegate PUBLIC armnnClassicDelegateObject) endif() if (BUILD_OPAQUE_DELEGATE) target_link_libraries(armnnOpaqueDelegate PUBLIC Armnn::Armnn) ## Add armnnOpaqueDelegateObject as a Dependency target_link_libraries(armnnOpaqueDelegate PUBLIC armnnOpaqueDelegateObject) endif() ## Add TfLite dependency find_package(TfLiteSrc REQUIRED MODULE) find_package(TfLite REQUIRED MODULE) if (BUILD_CLASSIC_DELEGATE) target_link_libraries(armnnDelegate PUBLIC ${TfLite_LIB}) # lpthread and ldl are not required for Android if(NOT "${CMAKE_SYSTEM_NAME}" STREQUAL Android) target_link_libraries(armnnDelegate PUBLIC -lpthread) target_link_libraries(armnnDelegate PUBLIC -ldl) endif() endif() if (BUILD_OPAQUE_DELEGATE) target_link_libraries(armnnOpaqueDelegate PUBLIC ${TfLite_LIB}) # lpthread and ldl are not required for Android if(NOT "${CMAKE_SYSTEM_NAME}" STREQUAL Android) target_link_libraries(armnnOpaqueDelegate PUBLIC -lpthread) target_link_libraries(armnnOpaqueDelegate PUBLIC -ldl) endif() endif() # Add libraries from armnn third-party libraries # Third-party header files are not warning clean # We can't change compilation flags on header files directly, so we need to add them to an interface library first add_library(thirdparty_headers INTERFACE) target_include_directories(thirdparty_headers INTERFACE $ $) target_compile_options(thirdparty_headers INTERFACE -Wno-old-style-cast) if (BUILD_CLASSIC_DELEGATE) target_link_libraries(armnnDelegate PUBLIC thirdparty_headers) endif() if (BUILD_OPAQUE_DELEGATE) target_link_libraries(armnnOpaqueDelegate PUBLIC thirdparty_headers) endif() add_library(profiling_library_headers INTERFACE) target_include_directories(profiling_library_headers INTERFACE $ $) if (BUILD_CLASSIC_DELEGATE) target_link_libraries(armnnDelegate PUBLIC profiling_library_headers) target_link_libraries(armnnDelegate PUBLIC Armnn::armnnUtils) set_target_properties(armnnDelegate PROPERTIES VERSION ${DELEGATE_LIB_VERSION} SOVERSION ${DELEGATE_LIB_SOVERSION}) endif() if (BUILD_OPAQUE_DELEGATE) target_link_libraries(armnnOpaqueDelegate PUBLIC profiling_library_headers) target_link_libraries(armnnOpaqueDelegate PUBLIC Armnn::armnnUtils) set_target_properties(armnnOpaqueDelegate PROPERTIES VERSION ${OPAQUE_DELEGATE_LIB_VERSION} SOVERSION ${OPAQUE_DELEGATE_LIB_SOVERSION}) endif() if(BUILD_UNIT_TESTS) set(commonDelegate_unittest_sources) list(APPEND commonDelegate_unittest_sources common/src/test/DelegateTestInterpreter.hpp common/src/test/DelegateTestInterpreterUtils.hpp test/ActivationTest.cpp test/ActivationTestHelper.hpp test/ArgMinMaxTest.cpp test/ArgMinMaxTestHelper.hpp test/BatchMatMulTest.cpp test/BatchMatMulTestHelper.hpp test/BatchSpaceTest.cpp test/BatchSpaceTestHelper.hpp test/CastTest.cpp test/CastTestHelper.hpp test/ComparisonTest.cpp test/ComparisonTestHelper.hpp test/ControlTest.cpp test/ControlTestHelper.hpp test/Convolution2dTest.cpp test/Convolution3dTest.cpp test/ConvolutionTestHelper.hpp test/DepthwiseConvolution2dTest.cpp test/ElementwiseBinaryTest.cpp test/ElementwiseBinaryTestHelper.hpp test/ElementwiseUnaryTest.cpp test/ElementwiseUnaryTestHelper.hpp test/ExpandDimsTest.cpp test/FillTest.cpp test/FillTestHelper.hpp test/FullyConnectedTest.cpp test/FullyConnectedTestHelper.hpp test/GatherTest.cpp test/GatherTestHelper.hpp test/GatherNdTest.cpp test/GatherNdTestHelper.hpp test/LogicalTest.cpp test/LogicalTestHelper.hpp test/LstmTest.cpp test/LstmTestHelper.hpp test/MirrorPadTest.cpp test/NormalizationTest.cpp test/NormalizationTestHelper.hpp test/PackTest.cpp test/PackTestHelper.hpp test/PadTest.cpp test/PadTestHelper.hpp test/Pooling2dTest.cpp test/Pooling2dTestHelper.hpp test/Pooling3dTest.cpp test/Pooling3dTestHelper.hpp test/PreluTest.cpp test/PreluTestHelper.hpp test/QuantizationTest.cpp test/QuantizationTestHelper.hpp test/RedefineTestHelper.hpp test/ReduceTest.cpp test/ReduceTestHelper.hpp test/ReshapeTest.cpp test/ResizeTest.cpp test/ResizeTestHelper.hpp test/ReverseV2Test.cpp test/ReverseV2TestHelper.hpp test/RoundTest.cpp test/RoundTestHelper.hpp test/SoftmaxTest.cpp test/SoftmaxTestHelper.hpp test/SpaceDepthTest.cpp test/SpaceDepthTestHelper.hpp test/ShapeTest.cpp test/ShapeTestHelper.hpp test/SliceTest.cpp test/SliceTestHelper.hpp test/SqueezeTest.cpp test/StridedSliceTest.cpp test/StridedSliceTestHelper.hpp test/SplitTest.cpp test/SplitTestHelper.hpp test/TestUtils.hpp test/TestUtils.cpp test/TileTest.cpp test/TileTestHelper.hpp test/TransposeConvolution2dTest.cpp test/TransposeTest.cpp test/TransposeTestHelper.hpp test/UnidirectionalSequenceLstmTest.cpp test/UnidirectionalSequenceLstmTestHelper.hpp test/UnpackTest.cpp test/UnpackTestHelper.hpp) # There's a known Android NDK bug which causes a subset of NeonLayerTests to # fail. We'll exclude these tests in NeonLayerTests_NDK_Bug.cpp if we're doing # a debug build and NDK is less than r21. # https://github.com/android/ndk/issues/1135 # Default to always including these tests. set(INCLUDE_NDK_BUG_TESTS "ON") # Reconsider if we in a debug build. string( TOLOWER ${CMAKE_BUILD_TYPE} BUILD_TYPE_LOWERCASE ) if ( NOT BUILD_TYPE_LOWERCASE STREQUAL "release" ) message("CMAKE:: BUILD TYPE IS ${CMAKE_BUILD_TYPE}") # And NDK_VERSION has been set. if ( DEFINED NDK_VERSION ) message("CMAKE:: NDK DEFINED") # And the version is less than r21. if ( ${NDK_VERSION} STRLESS "r21" ) message("CMAKE:: BUG TESTS OFF") set(INCLUDE_NDK_BUG_TESTS "OFF") endif() endif() endif() if ( INCLUDE_NDK_BUG_TESTS STREQUAL "ON" ) list(APPEND commonDelegate_unittest_sources test/NeonDelegateTests_NDK_Issue.cpp) endif() if (BUILD_CLASSIC_DELEGATE) set(classicDelegate_unittest_sources) list(APPEND classicDelegate_unittest_sources classic/src/test/ArmnnClassicDelegateTest.cpp classic/src/test/DelegateTestInterpreter.cpp test/DelegateOptionsTest.cpp test/DelegateOptionsTestHelper.hpp) add_executable(DelegateUnitTests ${commonDelegate_unittest_sources} ${classicDelegate_unittest_sources}) target_include_directories(DelegateUnitTests SYSTEM PRIVATE "${TF_LITE_SCHEMA_INCLUDE_PATH}") target_include_directories(DelegateUnitTests SYSTEM PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/common/src/test") target_include_directories(DelegateUnitTests PUBLIC ${PROJECT_SOURCE_DIR}) # Add half library from armnn third-party libraries target_link_libraries(DelegateUnitTests PRIVATE thirdparty_headers) target_link_libraries(DelegateUnitTests PRIVATE armnnDelegate) target_link_libraries(DelegateUnitTests PRIVATE Armnn::armnnUtils) target_link_libraries(DelegateUnitTests PRIVATE profiling_library_headers) endif() if (BUILD_OPAQUE_DELEGATE) set(opaqueDelegate_unittest_sources) list(APPEND opaqueDelegate_unittest_sources opaque/src/test/ArmnnOpaqueDelegateTest.cpp opaque/src/test/DelegateTestInterpreter.cpp) # Until all operators are supported, we have to add tests one by one above to opaqueDelegate_unittest_sources. # After we add can add commonDelegate_unittest_sources to the add_executable below. add_executable(OpaqueDelegateUnitTests ${opaqueDelegate_unittest_sources} ${commonDelegate_unittest_sources}) target_include_directories(OpaqueDelegateUnitTests SYSTEM PRIVATE "${TF_LITE_SCHEMA_INCLUDE_PATH}") target_include_directories(OpaqueDelegateUnitTests SYSTEM PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/common/src/test") target_include_directories(OpaqueDelegateUnitTests PUBLIC ${PROJECT_SOURCE_DIR}) # Add half library from armnn third-party libraries target_link_libraries(OpaqueDelegateUnitTests PRIVATE thirdparty_headers) target_link_libraries(OpaqueDelegateUnitTests PRIVATE armnnOpaqueDelegate) target_link_libraries(OpaqueDelegateUnitTests PRIVATE Armnn::armnnUtils) target_link_libraries(OpaqueDelegateUnitTests PRIVATE profiling_library_headers) endif() endif() if(BUILD_DELEGATE_JNI_INTERFACE AND BUILD_CLASSIC_DELEGATE) add_subdirectory(armnnDelegateJNI) endif() #################################################### ## Export targets if (BUILD_CLASSIC_DELEGATE) set(armnn_delegate_export_targets) list(APPEND armnn_delegate_export_targets armnnClassicDelegateObject armnnDelegate tflite_headers flatbuffer_headers profiling_library_headers thirdparty_headers) install( TARGETS ${armnn_delegate_export_targets} EXPORT armnn-delegate-targets LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) ## Set export alias set_target_properties(armnnDelegate PROPERTIES EXPORT_NAME ArmnnDelegate) ## Export target scrips install( EXPORT armnn-delegate-targets FILE ArmnnDelegateTargets.cmake NAMESPACE ArmnnDelegate:: DESTINATION ${CMAKE_INSTALL_LIBDIR}) ## Create ArmnnDelegateConfig.cmake include(CMakePackageConfigHelpers) set(INSTALL_CONFIGDIR ${CMAKE_INSTALL_LIBDIR}) message(STATUS "CMAKE_CURRENT_LIST_DIR ${CMAKE_CURRENT_LIST_DIR}" ) message(STATUS "CMAKE_CURRENT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}" ) SET(Armnn_DIR "${Armnn_DIR}") configure_package_config_file( ${CMAKE_CURRENT_LIST_DIR}/cmake/Modules/ArmnnDelegateConfig.cmake.in ${CMAKE_CURRENT_BINARY_DIR}/ArmnnDelegateConfig.cmake INSTALL_DESTINATION ${INSTALL_CONFIGDIR} PATH_VARS Armnn_DIR) ## Install ArmNN Delegate config file install( FILES ${CMAKE_CURRENT_BINARY_DIR}/ArmnnDelegateConfig.cmake DESTINATION ${INSTALL_CONFIGDIR}) ## Export from build tree export( EXPORT armnn-delegate-targets FILE ${CMAKE_CURRENT_BINARY_DIR}/ArmnnDelegateTargets.cmake NAMESPACE ArmnnDelegate::) add_library(ArmnnDelegate::ArmnnDelegate ALIAS armnnDelegate) endif() #################################################### ## Export opaque delegate targets if(BUILD_OPAQUE_DELEGATE) set(armnn_opaque_delegate_export_targets) list(APPEND armnn_opaque_delegate_export_targets armnnOpaqueDelegateObject armnnOpaqueDelegate tflite_headers flatbuffer_headers profiling_library_headers thirdparty_headers) install( TARGETS armnnOpaqueDelegate EXPORT armnn-opaque-delegate-targets LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) ## Set export alias set_target_properties(armnnOpaqueDelegate PROPERTIES EXPORT_NAME ArmnnOpaqueDelegate) add_library(ArmnnDelegate::ArmnnOpaqueDelegate ALIAS armnnOpaqueDelegate) endif() ####################################################armnn-23.08/delegate/DelegateQuickStartGuide.md000066400000000000000000000126251446772241200214570ustar00rootroot00000000000000# TfLite Delegate Quick Start Guide If you have downloaded the Arm NN Github binaries or built the TfLite delegate yourself, then this tutorial will show you how you can integrate it into TfLite to run models using python. Here is an example python script showing how to do this. In this script we are making use of the [external adaptor](https://www.tensorflow.org/lite/performance/implementing_delegate#option_2_leverage_external_delegate) tool of TfLite that allows you to load delegates at runtime. ```python import numpy as np import tflite_runtime.interpreter as tflite # Load TFLite model and allocate tensors. # (if you are using the complete tensorflow package you can find load_delegate in tf.experimental.load_delegate) armnn_delegate = tflite.load_delegate( library="/libarmnnDelegate.so", options={"backends": "CpuAcc,GpuAcc,CpuRef", "logging-severity":"info"}) # Delegates/Executes all operations supported by Arm NN to/with Arm NN interpreter = tflite.Interpreter(model_path="/delegate/python/test/test_data/mock_model.tflite", experimental_delegates=[armnn_delegate]) interpreter.allocate_tensors() # Get input and output tensors. input_details = interpreter.get_input_details() output_details = interpreter.get_output_details() # Test model on random input data. input_shape = input_details[0]['shape'] input_data = np.array(np.random.random_sample(input_shape), dtype=np.uint8) interpreter.set_tensor(input_details[0]['index'], input_data) interpreter.invoke() # Print out result output_data = interpreter.get_tensor(output_details[0]['index']) print(output_data) ``` # Prepare the environment Pre-requisites: * Dynamically build Arm NN Delegate library or download the Arm NN binaries (built with a particular SHA of Tensorflow 2.12.0, which is 6f692f73cb2043b4a0b0446539cd8c15b3dd9220) * python3 (Depends on TfLite version) * virtualenv * numpy (Depends on TfLite version) * tflite_runtime (2.12 currently available) If you haven't built the delegate yet then take a look at the [build guide](./BuildGuideNative.md). Otherwise, you can download the binaries [here](https://github.com/ARM-software/armnn/releases/). Set the following environment variable to the location of the .so binary files: ```bash export LD_LIBRARY_PATH= ``` We recommend creating a virtual environment for this tutorial. For the following code to work python3 is needed. Please also check the documentation of the TfLite version you want to use. There might be additional prerequisites for the python version. We will use Tensorflow Lite 2.12.0 for this guide. ```bash # Install python3 (We ended up with python3.5.3) and virtualenv sudo apt-get install python3-pip sudo pip3 install virtualenv # create a virtual environment cd your/tutorial/dir # creates a directory myenv at the current location virtualenv -p python3 myenv # activate the environment source myenv/bin/activate ``` Now that the environment is active we can install additional packages we need for our example script. As you can see in the python script at the start of this page, this tutorial uses the `tflite_runtime` rather than the whole tensorflow package. The `tflite_runtime` is a package that wraps the TfLite Interpreter. Therefore it can only be used to run inferences of TfLite models. But since Arm NN is only an inference engine itself this is a perfect match. The `tflite_runtime` is also much smaller than the whole tensorflow package and better suited to run models on mobile and embedded devices. The TfLite [website](https://www.tensorflow.org/lite/guide/python) shows you two methods to download the `tflite_runtime` package. In our experience, the use of the pip command works for most systems including debian. However, if you're using an older version of Tensorflow, you may need to build the pip package from source. You can find more information [here](https://github.com/tensorflow/tensorflow/blob/master/tensorflow/lite/tools/pip_package/README.md). But in our case, with Tensorflow Lite 2.12.0, we can install through: ``` pip3 install --extra-index-url https://google-coral.github.io/py-repo/ tflite_runtime==2.12.0 ``` Your virtual environment is now all setup. Copy the final python script into a python file e.g. `ExternalDelegatePythonTutorial.py`. Modify the python script above and replace `` and `` with the directories you have set up. If you've been using the [native build guide](./BuildGuideNative.md) this will be `$BASEDIR/armnn/build` and `$BASEDIR/armnn`. Finally, execute the script: ```bash python ExternalDelegatePythonTutorial.py ``` The output should look similar to this: ```bash Info: Arm NN v32.1.0 Info: Initialization time: 0.56 ms INFO: TfLiteArmnnDelegate: Created TfLite Arm NN delegate. [[ 12 123 16 12 11 14 20 16 20 12]] Info: Shutdown time: 0.28 ms ``` For more details of the kind of options you can pass to the Arm NN delegate please check the parameters of function tflite_plugin_create_delegate. You can also test the functionality of the external delegate adaptor by running some unit tests: ```bash pip install pytest cd armnn/delegate/python/test # You can deselect tests that require backends that your hardware doesn't support using markers e.g. -m "not GpuAccTest" pytest --delegate-dir="/libarmnnDelegate.so" -m "not GpuAccTest" ``` armnn-23.08/delegate/DelegateQuickStartGuide.md.license000066400000000000000000000001541446772241200230720ustar00rootroot00000000000000# # Copyright © 2020, 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/README.md000066400000000000000000000006471446772241200157120ustar00rootroot00000000000000# The Arm NN TensorFlow Lite delegate 'armnnDelegate' is a library for accelerating certain TensorFlow Lite operators on Arm hardware by providing the TensorFlow Lite interpreter with an alternative implementation of the operators via its delegation mechanism. For more information, like a list of supported operators, please visit our [doxygen documentation](https://arm-software.github.io/armnn/latest/delegate.xhtml). armnn-23.08/delegate/README.md.license000066400000000000000000000001531446772241200173230ustar00rootroot00000000000000# # Copyright © 2020-2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/armnnDelegateJNI/000077500000000000000000000000001446772241200175335ustar00rootroot00000000000000armnn-23.08/delegate/armnnDelegateJNI/CMakeLists.txt000066400000000000000000000040711446772241200222750ustar00rootroot00000000000000# # Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # cmake_minimum_required(VERSION 3.7.0) project("armnn_delegate_jni") # JNI is needed for jni calls find_package(JNI) list(APPEND jni_delegate_sources src/armnn_delegate_jni.cpp) # the backends under src/backends extend the list of # object libs armnn to include in the build # If armnn is a static library (which it should be to make armnn_delegate_jni a stand alone library) then # the object libraries of the backends need to be linked manually include(${ARMNN_SOURCE_DIR}/src/backends/backends.cmake) foreach(lib ${armnnLibraries}) message(STATUS "Adding object library dependency to armnn_delegate_jni: ${lib}") list(APPEND jni_delegate_sources $) endforeach() if (JNI_FOUND) message (STATUS "JNI_INCLUDE_DIRS=${JNI_INCLUDE_DIRS}") message (STATUS "JNI_LIBRARIES=${JNI_LIBRARIES}") else() message (FATAL_ERROR "JNI library could not be found") endif() include_directories(${JNI_INCLUDE_DIRS}) add_library(armnn_delegate_jni SHARED ${jni_delegate_sources}) target_link_libraries(armnn_delegate_jni PRIVATE Armnn::Armnn ArmnnDelegate::ArmnnDelegate ) # A version script is used to hide all symbols that are not required to use the jni interface # This is mostly required to avoid symbol conflicts between libc++_shared used to compile armnn # and an eventual other version used somewhere else: https://developer.android.com/ndk/guides/cpp-support # This also requires to tell the compiler to link to the static version of libc++_shared. This can be accomplished # by adding -DCMAKE_ANDROID_STL_TYPE=c++_static to the cmake command when building for android set(version_script "${CMAKE_CURRENT_SOURCE_DIR}/version_script") # Generate a map file for debug mode only set_property(TARGET armnn_delegate_jni APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--version-script=${version_script},-Map=mapfile.map") set_target_properties(armnn_delegate_jni PROPERTIES LINK_DEPENDS ${version_script}) armnn-23.08/delegate/armnnDelegateJNI/README.md000066400000000000000000000017201446772241200210120ustar00rootroot00000000000000# The Arm NN TensorFlow Lite delegate JNI (Experimental) NOTE: This library is an experimental feature. We cannot guarentee full support for this. 'armnnDelegateJNI' is a library for accelerating certain TensorFlow Lite operators on Arm hardware specifically through Android applications. Each release is packaged in an AAR which can be found on Maven Central. The pre-built library contains the ArmNN Core, ArmNN Utils, Neon backend, CL Backend, and the ArmNN Delegate. It is essential to only build these. The backends you choose are optional. It requires a static build which can be switched on through setting BUILD_SHARED_LIBS=OFF. You will also have to set CMAKE_ANDROID_STL_TYPE=c++_static when building ArmNN. BUILD_DELEGATE_JNI_INTERFACE will also have to be set to true. To download the prebuilt ArmNN Delegate JNI AAR from Maven Central, please go to [ArmNN Maven Central Release Page](https://search.maven.org/artifact/io.github.arm-software/armnn.delegate). armnn-23.08/delegate/armnnDelegateJNI/README.md.license000066400000000000000000000001451446772241200224330ustar00rootroot00000000000000# # Copyright © 2022 ARM Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT #armnn-23.08/delegate/armnnDelegateJNI/src/000077500000000000000000000000001446772241200203225ustar00rootroot00000000000000armnn-23.08/delegate/armnnDelegateJNI/src/armnn_delegate_jni.cpp000066400000000000000000000066641446772241200246470ustar00rootroot00000000000000// // Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #if defined(ARMCOMPUTECL_ENABLED) #include #endif #include #include extern "C" { /// Creates an Arm NN Delegate object. /// Options are passed in form of String arrays. For details about what options_keys and option_values /// are supported please see: // armnnDelegate::DelegateOptions::DelegateOptions(char const* const*, char const* const*,size_t,void (*)(const char*)) JNIEXPORT jlong JNICALL Java_com_arm_armnn_delegate_ArmnnDelegate_createDelegate(JNIEnv* env, jclass clazz, jobjectArray optionKeys, jobjectArray optionValues) { int numOptions = env->GetArrayLength(optionKeys); const char* nativeOptionKeys[numOptions]; const char* nativeOptionValues[numOptions]; jstring jKeyStrings[numOptions]; jstring jValueStrings[numOptions]; // Convert java array of string into char so we can make use of it in cpp code for (int i = 0; i < numOptions; i++) { jKeyStrings[i] = static_cast(env->GetObjectArrayElement(optionKeys, i)); jValueStrings[i] = static_cast(env->GetObjectArrayElement(optionValues, i)); nativeOptionKeys[i] = env->GetStringUTFChars(jKeyStrings[i], 0); nativeOptionValues[i] = env->GetStringUTFChars(jValueStrings[i], 0); } armnnDelegate::DelegateOptions delegateOptions(nativeOptionKeys, nativeOptionValues, numOptions, nullptr); // Release jni memory. After the delegate options are created there is no need to hold on to it anymore. for (int i = 0; i < numOptions; i++) { env->ReleaseStringUTFChars(jKeyStrings[i], nativeOptionKeys[i]); env->ReleaseStringUTFChars(jValueStrings[i], nativeOptionValues[i]); } return reinterpret_cast(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions)); } /// Destroys a given Arm NN Delegate object JNIEXPORT void JNICALL Java_com_arm_armnn_delegate_ArmnnDelegate_deleteDelegate(JNIEnv* env, jclass clazz, jlong delegate) { armnnDelegate::TfLiteArmnnDelegateDelete(reinterpret_cast(delegate)); } /// Returns true if a Arm Mali GPU is detected. /// Can be used to ensure that GpuAcc is supported on a device. JNIEXPORT jboolean JNICALL Java_com_arm_armnn_delegate_ArmnnUtils_IsGpuAccSupported(JNIEnv* env, jclass clazz) { #if defined(ARMCOMPUTECL_ENABLED) cl::Device device = cl::Device::getDefault(); char device_name[32]; cl_int err = clGetDeviceInfo(device.get(), CL_DEVICE_NAME, sizeof(device_name), &device_name, NULL); if (err != CL_SUCCESS) { return false; } // search for "Mali" in the devices name if (strstr(device_name, "Mali")) { return true; } #endif return false; } /// Returns true if the current device supports Neon instructions. /// Can be used to ensure the CpuAcc backend is supported. JNIEXPORT jboolean JNICALL Java_com_arm_armnn_delegate_ArmnnUtils_IsNeonDetected(JNIEnv* env, jclass clazz) { return armnn::NeonDetected(); } } armnn-23.08/delegate/armnnDelegateJNI/version_script000066400000000000000000000006151446772241200225310ustar00rootroot00000000000000/* Copyright © 2022 Arm Ltd and Contributors. All rights reserved. SPDX-License-Identifier: MIT */ LIBARMNN_DELEGATE_JNI { global: Java_com_arm_armnn_delegate_ArmnnDelegate_createDelegate; Java_com_arm_armnn_delegate_ArmnnDelegate_deleteDelegate; Java_com_arm_armnn_delegate_ArmnnUtils_IsGpuAccSupported; Java_com_arm_armnn_delegate_ArmnnUtils_IsNeonDetected; local: *; };armnn-23.08/delegate/classic/000077500000000000000000000000001446772241200160455ustar00rootroot00000000000000armnn-23.08/delegate/classic/CMakeLists.txt000066400000000000000000000065261446772241200206160ustar00rootroot00000000000000# # Copyright © 2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # set(armnnClassicDelegateObject_sources) list(APPEND armnnClassicDelegateObject_sources include/armnn_delegate.hpp include/Version.hpp src/armnn_delegate.cpp src/armnn_external_delegate.cpp src/Activation.hpp src/ArgMinMax.hpp src/BatchMatMul.hpp src/BatchSpace.hpp src/ClassicDelegateUtils.hpp src/Comparison.hpp src/Convolution.hpp src/Control.hpp src/ElementwiseBinary.hpp src/ElementwiseUnary.hpp src/Fill.hpp src/FullyConnected.hpp src/Gather.hpp src/GatherNd.hpp src/LogicalBinary.hpp src/Lstm.hpp src/Normalization.hpp src/Pack.hpp src/Pad.hpp src/Pooling.hpp src/Prelu.hpp src/Quantization.hpp src/Redefine.hpp src/Reduce.hpp src/Resize.hpp src/ReverseV2.hpp src/Round.hpp src/Shape.hpp src/SharedFunctions.hpp src/SharedFunctions.cpp src/Slice.hpp src/Softmax.hpp src/SpaceDepth.hpp src/Split.hpp src/Unpack.hpp src/Tile.hpp src/Transpose.hpp) add_library(armnnClassicDelegateObject OBJECT ${armnnClassicDelegateObject_sources}) target_include_directories(armnnClassicDelegateObject PUBLIC $ $ $ PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src ${PROJECT_SOURCE_DIR}/common/src) ## Add Tflite dependency if(NOT TfLite_INCLUDE_DIR OR NOT TfLite_Schema_INCLUDE_PATH) find_package(TfLiteSrc REQUIRED MODULE) endif() # Various tflite header files are not warning clean # We can't change compilation flags on header files directly, so we need to add them to an interface library first add_library(tflite_headers INTERFACE) target_include_directories(tflite_headers INTERFACE $ $) target_compile_options(tflite_headers INTERFACE -Wno-conversion -Wno-sign-conversion -Wno-unused-parameter -Wno-unused-function) target_link_libraries(armnnClassicDelegateObject PUBLIC tflite_headers) ## Add Flatbuffers dependency find_package(Flatbuffers REQUIRED MODULE) target_link_libraries(armnnClassicDelegateObject PRIVATE ${Flatbuffers_LIB}) # include/flatbuffers/flatbuffers.h is not warning clean # We can't change compilation flags on header files directly, so we need to add them to an interface library first add_library(flatbuffer_headers INTERFACE) target_include_directories(flatbuffer_headers INTERFACE $ $) target_compile_options(flatbuffer_headers INTERFACE -Wno-sign-conversion) target_link_libraries(armnnClassicDelegateObject PUBLIC flatbuffer_headers) #################################################### ## Export targets install(TARGETS armnnClassicDelegateObject LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR})armnn-23.08/delegate/classic/include/000077500000000000000000000000001446772241200174705ustar00rootroot00000000000000armnn-23.08/delegate/classic/include/Version.hpp000066400000000000000000000013541446772241200216310ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once namespace armnnDelegate { /// Macro utils #define STRINGIFY_VALUE(s) STRINGIFY_MACRO(s) #define STRINGIFY_MACRO(s) #s // ArmNN Delegate version components #define DELEGATE_MAJOR_VERSION 29 #define DELEGATE_MINOR_VERSION 0 #define DELEGATE_PATCH_VERSION 0 /// DELEGATE_VERSION: "X.Y.Z" /// where: /// X = Major version number /// Y = Minor version number /// Z = Patch version number #define DELEGATE_VERSION STRINGIFY_VALUE(DELEGATE_MAJOR_VERSION) "." \ STRINGIFY_VALUE(DELEGATE_MINOR_VERSION) "." \ STRINGIFY_VALUE(DELEGATE_PATCH_VERSION) } //namespace armnnDelegatearmnn-23.08/delegate/classic/include/armnn_delegate.hpp000066400000000000000000000112771446772241200231560ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #if TF_MAJOR_VERSION > 2 || (TF_MAJOR_VERSION == 2 && TF_MINOR_VERSION > 3) #define ARMNN_POST_TFLITE_2_3 #endif #if TF_MAJOR_VERSION > 2 || (TF_MAJOR_VERSION == 2 && TF_MINOR_VERSION > 4) #define ARMNN_POST_TFLITE_2_4 #endif #if TF_MAJOR_VERSION > 2 || (TF_MAJOR_VERSION == 2 && TF_MINOR_VERSION > 5) #define ARMNN_POST_TFLITE_2_5 #endif namespace armnnDelegate { struct DelegateData { DelegateData(const std::vector& backends) : m_Backends(backends) , m_Network(nullptr, nullptr) {} const std::vector m_Backends; armnn::INetworkPtr m_Network; std::vector m_OutputSlotForNode; }; // Forward decleration for functions initializing the ArmNN Delegate DelegateOptions TfLiteArmnnDelegateOptionsDefault(); TfLiteDelegate* TfLiteArmnnDelegateCreate(armnnDelegate::DelegateOptions options); void TfLiteArmnnDelegateDelete(TfLiteDelegate* tfLiteDelegate); TfLiteStatus DoPrepare(TfLiteContext* context, TfLiteDelegate* delegate); /// ArmNN Delegate class Delegate { friend class ArmnnSubgraph; public: explicit Delegate(armnnDelegate::DelegateOptions options); TfLiteIntArray* IdentifyOperatorsToDelegate(TfLiteContext* context); TfLiteDelegate* GetDelegate(); /// Retrieve version in X.Y.Z form static const std::string GetVersion(); private: /** * Returns a pointer to the armnn::IRuntime* this will be shared by all armnn_delegates. */ armnn::IRuntime* GetRuntime(const armnn::IRuntime::CreationOptions& options) { static armnn::IRuntimePtr instance = armnn::IRuntime::Create(options); // Instantiated on first use. return instance.get(); } TfLiteDelegate m_Delegate = { reinterpret_cast(this), // .data_ DoPrepare, // .Prepare nullptr, // .CopyFromBufferHandle nullptr, // .CopyToBufferHandle nullptr, // .FreeBufferHandle kTfLiteDelegateFlagsNone, // .flags nullptr, // .opaque_delegate_builder }; /// ArmNN Runtime pointer armnn::IRuntime* m_Runtime; /// ArmNN Delegate Options armnnDelegate::DelegateOptions m_Options; }; /// ArmnnSubgraph class where parsing the nodes to ArmNN format and creating the ArmNN Graph class ArmnnSubgraph { public: static ArmnnSubgraph* Create(TfLiteContext* tfLiteContext, const TfLiteDelegateParams* parameters, const Delegate* delegate); TfLiteStatus Prepare(TfLiteContext* tfLiteContext); TfLiteStatus Invoke(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode); static TfLiteStatus VisitNode(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteRegistration* tfLiteRegistration, TfLiteNode* tfLiteNode, int nodeIndex); private: ArmnnSubgraph(armnn::NetworkId networkId, armnn::IRuntime* runtime, std::vector& inputBindings, std::vector& outputBindings) : m_NetworkId(networkId), m_Runtime(runtime), m_InputBindings(inputBindings), m_OutputBindings(outputBindings) {} static TfLiteStatus AddInputLayer(DelegateData& delegateData, TfLiteContext* tfLiteContext, const TfLiteIntArray* inputs, std::vector& inputBindings); static TfLiteStatus AddOutputLayer(DelegateData& delegateData, TfLiteContext* tfLiteContext, const TfLiteIntArray* outputs, std::vector& outputBindings); /// The Network Id armnn::NetworkId m_NetworkId; /// ArmNN Runtime armnn::IRuntime* m_Runtime; // Binding information for inputs and outputs std::vector m_InputBindings; std::vector m_OutputBindings; }; } // armnnDelegate namespacearmnn-23.08/delegate/classic/src/000077500000000000000000000000001446772241200166345ustar00rootroot00000000000000armnn-23.08/delegate/classic/src/Activation.hpp000066400000000000000000000122471446772241200214540ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateActivationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, armnn::ActivationDescriptor& activationDesc) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("ACTIVATION", tfLiteContext, IsActivationSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, activationDesc); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitActivationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ActivationDescriptor activationDesc; switch(operatorCode) { case kTfLiteBuiltinRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } case kTfLiteBuiltinRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; break; } case kTfLiteBuiltinLogistic: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteBuiltinTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } case kTfLiteBuiltinElu: { activationDesc.m_Function = armnn::ActivationFunction::Elu; activationDesc.m_A = 1.0f; break; } case kTfLiteBuiltinHardSwish: { activationDesc.m_Function = armnn::ActivationFunction::HardSwish; break; } case kTfLiteBuiltinLeakyRelu: { // Get the alpha param from builtin data auto* leakyReluParameters = reinterpret_cast(tfLiteNode->builtin_data); activationDesc.m_Function = armnn::ActivationFunction::LeakyReLu; activationDesc.m_A = leakyReluParameters->alpha; break; } default: { return kTfLiteError; } } if (!delegateData.m_Network) { return ValidateActivationOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, activationDesc); } auto layerName = GetLayerName(activationDesc.m_Function, nodeIndex); armnn::IConnectableLayer* activationLayer = delegateData.m_Network->AddActivationLayer(activationDesc, layerName.c_str()); ARMNN_ASSERT(activationLayer != nullptr); armnn::IOutputSlot& outputSlot = activationLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(activationLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(activationLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/ArgMinMax.hpp000066400000000000000000000120021446772241200211630ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitArgMinMaxOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t argMinMaxOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteAxisTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::ArgMinMaxDescriptor desc; // Get the axis value from the input tensor switch (tfLiteAxisTensor.type) { case kTfLiteInt32: case kTfLiteInt64: desc.m_Axis = tflite::GetTensorData(&tfLiteAxisTensor)[0]; break; default: TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Axis value data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } // If output_type is int32 then set Signed32 else Signed64. Default type is Signed64. if (argMinMaxOperatorCode == kTfLiteBuiltinArgMax) { desc.m_Function = armnn::ArgMinMaxFunction::Max; auto* argMaxParameters = reinterpret_cast(tfLiteNode->builtin_data); if (argMaxParameters->output_type != kTfLiteInt32 && argMaxParameters->output_type != kTfLiteInt64) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: output_type data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } } else { desc.m_Function = armnn::ArgMinMaxFunction::Min; auto* argMinParameters = reinterpret_cast(tfLiteNode->builtin_data); if (argMinParameters->output_type != kTfLiteInt32 && argMinParameters->output_type != kTfLiteInt64) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: output_type data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("ARGMINMAX", tfLiteContext, IsArgMinMaxSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add an ArgMinMax layer auto layerName = GetLayerName(desc.m_Function, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddArgMinMaxLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/BatchMatMul.hpp000066400000000000000000000106631446772241200215140ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitBatchMatMulOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& kTfLiteLHSInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; const TfLiteTensor& kTfLiteRHSInputTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, kTfLiteLHSInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } if (!IsValid(tfLiteContext, kTfLiteRHSInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } if (IsDynamicTensor(kTfLiteLHSInputTensor) || IsDynamicTensor(kTfLiteRHSInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& kTfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(kTfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& armnnLHSInputTensorInfo = GetTensorInfoForTfLiteTensor(kTfLiteLHSInputTensor); const armnn::TensorInfo& armnnRHSInputTensorInfo = GetTensorInfoForTfLiteTensor(kTfLiteRHSInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(kTfLiteOutputTensor, true); armnn::BatchMatMulDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); // Tensorflow params are called adjoint, however they are actually just transposes behind the scene. They do // not perform ajoint. descriptor.m_TransposeX = params->adj_x; descriptor.m_TransposeY = params->adj_y; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("BATCH_MATMUL", tfLiteContext, IsBatchMatMulSupported, delegateData.m_Backends, isSupported, setBackend, armnnLHSInputTensorInfo, armnnRHSInputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::BatchMatMul, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddBatchMatMulLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/BatchSpace.hpp000066400000000000000000000215321446772241200213450ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitBatchToSpaceNdOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteBlockShapeTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteBlockShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteCropsTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteCropsTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& cropsTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteCropsTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::vector blockShape(blockShapeTensorInfo.GetNumElements()); ::memcpy(blockShape.data(), tfLiteBlockShapeTensor.data.data, blockShapeTensorInfo.GetNumBytes()); std::vector cropsVector(cropsTensorInfo.GetNumElements()); std::memcpy(cropsVector.data(), tfLiteCropsTensor.data.data, cropsTensorInfo.GetNumBytes()); size_t step = 2; std::vector> crops; for (unsigned int i = 0; i < cropsTensorInfo.GetNumElements() / step; ++i) { crops.emplace_back(cropsVector[i * step], cropsVector[i * step + 1]); } armnn::BatchToSpaceNdDescriptor descriptor; descriptor.m_BlockShape = blockShape; descriptor.m_Crops = crops; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("BATCH_TO_SPACE_ND", tfLiteContext, IsBatchToSpaceNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitBatchToSpaceNdOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a BatchToSpace layer auto layerName = GetLayerName(armnn::LayerType::BatchToSpaceNd, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddBatchToSpaceNdLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitSpaceToBatchNdOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteBlockShapeTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteBlockShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLitePadListTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLitePadListTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& padListTensorInfo = GetTensorInfoForTfLiteTensor(tfLitePadListTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::vector blockShape(blockShapeTensorInfo.GetNumElements()); std::memcpy(blockShape.data(), tfLiteBlockShapeTensor.data.data, blockShapeTensorInfo.GetNumBytes()); std::vector padListVector(padListTensorInfo.GetNumElements()); std::memcpy(padListVector.data(), tfLitePadListTensor.data.data, padListTensorInfo.GetNumBytes()); size_t step = 2; std::vector> padList; for (unsigned int i = 0; i < padListTensorInfo.GetNumElements() / step; ++i) { padList.emplace_back(padListVector[i * step], padListVector[i * step + 1]); } armnn::SpaceToBatchNdDescriptor descriptor; descriptor.m_BlockShape = blockShape; descriptor.m_PadList = padList; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SPACE_TO_BATCH_ND", tfLiteContext, IsSpaceToBatchNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitSpaceToBatchNdOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a SpaceToBatch layer armnn::IConnectableLayer* layer = delegateData.m_Network->AddSpaceToBatchNdLayer(descriptor); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/ClassicDelegateUtils.hpp000066400000000000000000000503151446772241200234060ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include namespace { // Macro to call an IsSupported function and log caller name together with reason for lack of support #define FORWARD_LAYER_SUPPORT_FUNC(opName, tfLiteContext, func, backends, supported, setBackend, ...) \ try \ { \ for (auto&& backendId : backends) \ { \ auto layerSupportObject = armnn::GetILayerSupportByBackendId(backendId); \ if (layerSupportObject.IsBackendRegistered()) \ { \ std::string reasonIfUnsupported; \ supported = \ layerSupportObject.func(__VA_ARGS__, armnn::Optional(reasonIfUnsupported)); \ if (supported) \ { \ setBackend = backendId; \ break; \ } \ else \ { \ if (reasonIfUnsupported.size() > 0) \ { \ TFLITE_LOG_PROD(tflite::TFLITE_LOG_WARNING, \ "%s: not supported by armnn: %s", opName, reasonIfUnsupported.c_str()); \ } \ else \ { \ TFLITE_LOG_PROD(tflite::TFLITE_LOG_WARNING, \ "%s: not supported by armnn", opName); \ } \ } \ } \ else \ { \ TF_LITE_KERNEL_LOG(tfLiteContext, "%s: backend not registered: %s", opName, backendId.Get().c_str()); \ } \ } \ if (!supported) \ { \ TF_LITE_KERNEL_LOG(tfLiteContext, "%s: not supported by any specified backend", opName); \ } \ } \ catch (const armnn::InvalidArgumentException &e) \ { \ throw armnn::InvalidArgumentException(e, "Failed to check layer support", CHECK_LOCATION()); \ } std::string GetLayerName(armnn::ActivationFunction function, int nodeIndex) { return fmt::format("{}:{}", GetActivationFunctionAsCString(function), nodeIndex); } std::string GetLayerName(armnn::ArgMinMaxFunction function, int nodeIndex) { return fmt::format("{}:{}", GetArgMinMaxFunctionAsCString(function), nodeIndex); } std::string GetLayerName(armnn::BinaryOperation opType, int nodeIndex) { return fmt::format("{}:{}", GetBinaryOperationAsCString(opType), nodeIndex); } std::string GetLayerName(armnn::ComparisonOperation layerType, int nodeIndex) { return fmt::format("{}:{}", GetComparisonOperationAsCString(layerType), nodeIndex); } std::string GetLayerName(armnn::LogicalBinaryOperation operation, int nodeIndex) { return fmt::format("{}:{}", GetLogicalBinaryOperationAsCString(operation), nodeIndex); } std::string GetLayerName(armnn::UnaryOperation opType, int nodeIndex) { return fmt::format("{}:{}", GetUnaryOperationAsCString(opType), nodeIndex); } std::string GetLayerName(armnn::LayerType layerType, int nodeIndex, std::string name = "") { return fmt::format("{}{}:{}", GetLayerTypeAsCString(layerType), name, nodeIndex); } TfLiteStatus ValidateNumInputs(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, const unsigned int expectedSize, int nodeIndex) { auto numInputs = tfLiteNode->inputs->size; if (static_cast(numInputs) != expectedSize) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Unexpected number of inputs (%d != %d) in node #%d", numInputs, expectedSize, nodeIndex); return kTfLiteError; } return kTfLiteOk; } TfLiteStatus ValidateNumOutputs(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, const unsigned int expectedSize, int nodeIndex) { auto numOutputs = tfLiteNode->outputs->size; if (static_cast(numOutputs) != expectedSize) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Unexpected number of outputs (%d != %d) in node #%d", numOutputs, expectedSize, nodeIndex); return kTfLiteError; } return kTfLiteOk; } bool IsDynamicTensor(const TfLiteTensor& tfLiteTensor) { auto tensorAllocationType = tfLiteTensor.allocation_type; if (tensorAllocationType == kTfLiteDynamic) { return true; } return false; } bool IsValid(const TfLiteTensor* tfLiteTensor) { return tfLiteTensor == nullptr ? false : true; } bool IsValid(TfLiteContext* tfLiteContext, const TfLiteTensor& tfLiteTensor, int32_t operatorCode, int32_t nodeIndex) { if(!IsValid(&tfLiteTensor)) { std::cout << "..Is Not Valid" << std::endl; TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid TfLite tensor in operator #%d node #%d: ", operatorCode, nodeIndex); return false; } if (IsDynamicTensor(tfLiteTensor)) { std::cout << "..IsDynamicTensor" << std::endl; TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic tensors are not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return false; } return true; } bool IsAffineQuantization(const TfLiteTensor& tfLiteTensor) { auto quantizationInfo = tfLiteTensor.quantization; if (quantizationInfo.type == kTfLiteAffineQuantization) { return true; } return false; } TfLiteStatus Connect(armnn::IConnectableLayer* layer, TfLiteNode* tfLiteNode, armnnDelegate::DelegateData& data) { if (static_cast(tfLiteNode->outputs->size) != layer->GetNumOutputSlots()) { return kTfLiteError; } // Connect the input slots for (unsigned int inputIndex = 0; inputIndex < layer->GetNumInputSlots(); ++inputIndex) { if (data.m_OutputSlotForNode[tfLiteNode->inputs->data[inputIndex]] != nullptr) { data.m_OutputSlotForNode[tfLiteNode->inputs->data[inputIndex]]->Connect(layer->GetInputSlot(inputIndex)); } } // Prepare output slots for (unsigned int outputIndex = 0; outputIndex < layer->GetNumOutputSlots(); ++outputIndex) { armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast(tfLiteNode->outputs->data[outputIndex])] = &outputSlot; } return kTfLiteOk; } TfLiteStatus FusedActivation(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, TfLiteFusedActivation activationType, armnn::IConnectableLayer* prevLayer, unsigned int outputSlotIndex, armnnDelegate::DelegateData& data, int nodeIndex) { const armnn::TensorInfo& activationOutputInfo = prevLayer->GetOutputSlot(outputSlotIndex).GetTensorInfo(); armnn::ActivationDescriptor activationDesc; switch (activationType) { case kTfLiteActNone: { // No Activation return kTfLiteOk; } case kTfLiteActRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } // The name of kTfLiteActRelu1 changed after TF Lite v2.3 #if defined(ARMNN_POST_TFLITE_2_3) case kTfLiteActReluN1To1: #else case kTfLiteActRelu1: #endif { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 1.0f; activationDesc.m_B = -1.0f; break; } case kTfLiteActRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; activationDesc.m_B = 0.0f; break; } case kTfLiteActSigmoid: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteActTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } default: return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_SUPPORT_FUNC("ACTIVATION", tfLiteContext, IsActivationSupported, data.m_Backends, isSupported, setBackend, activationOutputInfo, activationOutputInfo, activationDesc); if (!isSupported) { return kTfLiteError; } auto layerName = GetLayerName(activationDesc.m_Function, nodeIndex); armnn::IConnectableLayer* activationLayer = data.m_Network->AddActivationLayer(activationDesc, layerName.c_str()); activationLayer->SetBackendId(setBackend); ARMNN_ASSERT(activationLayer != nullptr); activationLayer->GetOutputSlot(0).SetTensorInfo(activationOutputInfo); // Connect and prepare output slots for (unsigned int outputIndex = 0; outputIndex < activationLayer->GetNumOutputSlots(); ++outputIndex) { data.m_OutputSlotForNode[static_cast( tfLiteNode->outputs->data[outputIndex])]->Connect(activationLayer->GetInputSlot(0)); armnn::IOutputSlot& outputSlot = activationLayer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast( tfLiteNode->outputs->data[outputIndex])] = &outputSlot; } return kTfLiteOk; } armnn::IConnectableLayer* AddReshapeLayer(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, armnn::IConnectableLayer* prevLayer, armnn::TensorInfo reshapedOutputTensorInfo, armnn::TensorInfo outputTensorInfo, armnnDelegate::DelegateData& data, int nodeIndex) { armnn::ReshapeDescriptor desc; desc.m_TargetShape = outputTensorInfo.GetShape(); bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, data.m_Backends, isSupported, setBackend, reshapedOutputTensorInfo, outputTensorInfo, desc); if (!isSupported) { return nullptr; } auto layerName = GetLayerName(armnn::LayerType::Reshape, nodeIndex); armnn::IConnectableLayer* reshapeLayer = data.m_Network->AddReshapeLayer(desc, layerName.c_str()); reshapeLayer->SetBackendId(setBackend); ARMNN_ASSERT(reshapeLayer != nullptr); prevLayer->GetOutputSlot(0).SetTensorInfo(reshapedOutputTensorInfo); reshapeLayer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); // Connect and prepare output slots for (unsigned int outputIndex = 0; outputIndex < reshapeLayer->GetNumOutputSlots(); ++outputIndex) { data.m_OutputSlotForNode[static_cast( tfLiteNode->outputs->data[outputIndex])]->Connect(reshapeLayer->GetInputSlot(0)); armnn::IOutputSlot& outputSlot = reshapeLayer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast( tfLiteNode->outputs->data[outputIndex])] = &outputSlot; } return reshapeLayer; } armnn::DataType GetDataType(const TfLiteTensor& tfLiteTensor) { switch (tfLiteTensor.type) { case kTfLiteBool: return armnn::DataType::Boolean; case kTfLiteFloat32: return armnn::DataType::Float32; case kTfLiteFloat16: return armnn::DataType::Float16; case kTfLiteUInt8: return armnn::DataType::QAsymmU8; case kTfLiteInt8: { auto quantizationInfo = tfLiteTensor.quantization; if (quantizationInfo.type == kTfLiteAffineQuantization) { auto* quantization = reinterpret_cast(tfLiteTensor.quantization.params); if (quantization->zero_point != nullptr && quantization->zero_point->size == 1) { return armnn::DataType::QAsymmS8; } else { return armnn::DataType::QSymmS8; } } else { return armnn::DataType::QAsymmS8; } } case kTfLiteInt16: return armnn::DataType::QSymmS16; case kTfLiteInt32: return armnn::DataType::Signed32; case kTfLiteInt64: return armnn::DataType::Signed64; default: throw armnn::Exception(&"TfLiteArmnnDelegate: Unsupported data type: " [ tfLiteTensor.type]); } } armnn::TensorInfo GetTensorInfoForTfLiteTensor(const TfLiteTensor& tfLiteTensor, bool isOutput = false) { armnn::DataType type = GetDataType(tfLiteTensor); armnn::TensorInfo ret; auto tensorDimensionSize = tfLiteTensor.dims->size; if (tensorDimensionSize == 0) { // If input tensor does not have a shape // assuming that it has 1D tensor if (!isOutput) { std::vector safeShape = { 1 }; bool dimensionsSpecificity[1] = { true }; armnn::TensorShape tensorShape(safeShape.size(), safeShape.data(), dimensionsSpecificity); ret = armnn::TensorInfo(tensorShape, type); if(tflite::IsConstantTensor(&tfLiteTensor)) { ret.SetConstant(true); } } else { armnn::TensorShape tensorShape(armnn::Dimensionality::NotSpecified); ret = armnn::TensorInfo(tensorShape, type); } } else { std::vector tensorDims(tensorDimensionSize); std::vector dimensionsSpecificity(tensorDimensionSize, true); for (int i = 0; i < tensorDimensionSize; ++i) { auto dim = tfLiteTensor.dims->data[i]; if (dim <= 0) { dimensionsSpecificity[i] = false; } tensorDims[i] = static_cast(dim); } armnn::TensorShape tensorShape(tensorDimensionSize, tensorDims.data(), reinterpret_cast(dimensionsSpecificity.data())); if (tflite::IsConstantTensor(&tfLiteTensor)) { ret = armnn::TensorInfo(tensorShape, type); ret.SetConstant(true); } else { ret = armnn::TensorInfo(tensorShape, type); } } auto quantizationInfo = tfLiteTensor.quantization; if (quantizationInfo.type == kTfLiteAffineQuantization) { // get per-channel quantization parameters const auto* affineQuantization = reinterpret_cast(tfLiteTensor.quantization.params); if (affineQuantization->scale->size > 1) { std::vector quantizationScales; for (unsigned int i = 0; i < static_cast(affineQuantization->scale->size); ++i) { quantizationScales.push_back(affineQuantization->scale->data[i]); } ret.SetQuantizationScales(quantizationScales); ret.SetQuantizationDim(armnn::numeric_cast(affineQuantization->quantized_dimension)); } else { ret.SetQuantizationScale(affineQuantization->scale->data[0]); ret.SetQuantizationOffset(affineQuantization->zero_point->data[0]); } } else { auto quantizationParameters = tfLiteTensor.params; ret.SetQuantizationScale(quantizationParameters.scale); ret.SetQuantizationOffset(quantizationParameters.zero_point); } return ret; } armnn::ConstTensor CreateConstTensor(const TfLiteTensor* tfLiteTensor, const armnn::TensorInfo& tensorInfo) { if (tfLiteTensor->allocation_type != kTfLiteMmapRo) { throw armnn::Exception( "TfLiteArmnnDelegate: Not constant allocation type: " + std::to_string(tfLiteTensor->allocation_type)); } return armnn::ConstTensor(tensorInfo, tfLiteTensor->data.data); } armnn::ConstTensor* GetConstTensorForTfLiteTensor(const TfLiteTensor* tfLiteTensors, TfLiteNode* tfLiteNode, int index) { const TfLiteTensor &tfLiteTensor = tfLiteTensors[tfLiteNode->inputs->data[index]]; armnn::TensorInfo tensorInfo = GetTensorInfoForTfLiteTensor(tfLiteTensor); return new armnn::ConstTensor(tensorInfo, tfLiteTensor.data.data); } bool IsOptionalOperandPresent(TfLiteNode* tfLiteNode, const int operandIndex) { // If the inputs array has fewer than operandIndex entries or if the entry at operandIndex has a value of -1 or // less then the input is not present. if (tfLiteNode->inputs->size > operandIndex && tfLiteNode->inputs->data[operandIndex] >= 0) { return true; } return false; } TfLiteStatus ProcessInputs(armnn::IConnectableLayer* layer, armnnDelegate::DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex) { const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; // Process input tensors // If input tensor is a Constant tensor create a constant layer and connect it to the network for (unsigned int inputIndex = 0; inputIndex < layer->GetNumInputSlots(); ++inputIndex) { const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[inputIndex]]; if (tflite::IsConstantTensor(&tfLiteInputTensor)) { armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_SUPPORT_FUNC("CONSTANT", tfLiteContext, IsConstantSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo); if (!isSupported) { return kTfLiteError; } auto constantInput = CreateConstTensor(&tfLiteInputTensor, inputTensorInfo); auto layerName = GetLayerName(armnn::LayerType::Constant, nodeIndex); armnn::IConnectableLayer* constantLayer = delegateData.m_Network->AddConstantLayer(constantInput, layerName.c_str()); constantLayer->SetBackendId(setBackend); armnn::IOutputSlot& outputSlot = constantLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(inputTensorInfo); delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[inputIndex]] = &outputSlot; } } return kTfLiteOk; } } // namespace anonymous armnn-23.08/delegate/classic/src/Comparison.hpp000066400000000000000000000124231446772241200214610ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitComparisonOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteComparisonOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor0 = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor0)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLiteComparisonOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor1 = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteInputTensor1)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLiteComparisonOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLiteComparisonOperatorCode, nodeIndex); return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of any of the input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } armnn::ComparisonOperation comparisonOperation = armnn::ComparisonOperation::Equal; switch(tfLiteComparisonOperatorCode) { case kTfLiteBuiltinEqual: comparisonOperation = armnn::ComparisonOperation::Equal; break; case kTfLiteBuiltinGreater: comparisonOperation = armnn::ComparisonOperation::Greater; break; case kTfLiteBuiltinGreaterEqual: comparisonOperation = armnn::ComparisonOperation::GreaterOrEqual; break; case kTfLiteBuiltinLess: comparisonOperation = armnn::ComparisonOperation::Less; break; case kTfLiteBuiltinLessEqual: comparisonOperation = armnn::ComparisonOperation::LessOrEqual; break; case kTfLiteBuiltinNotEqual: comparisonOperation = armnn::ComparisonOperation::NotEqual; break; default: return kTfLiteError; } armnn::ComparisonDescriptor descriptor(comparisonOperation); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("COMPARISON", tfLiteContext, IsComparisonSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, inputTensorInfo1, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(descriptor.m_Operation, nodeIndex); armnn::IConnectableLayer* comparisonLayer = delegateData.m_Network->AddComparisonLayer(descriptor, layerName.c_str()); comparisonLayer->SetBackendId(setBackend); ARMNN_ASSERT(comparisonLayer != nullptr); armnn::IOutputSlot& outputSlot = comparisonLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(comparisonLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(comparisonLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Control.hpp000066400000000000000000000277611446772241200210020ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitConcatenationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteConcatOperatorCode) { unsigned int numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; std::vector inputTensorInfos; for (unsigned int i = 0; i < numInputs; ++i) { const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[i]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteConcatOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); inputTensorInfos.emplace_back(inputTensorInfo); } // Convert input tensors to const armnn::TensorInfo* type for FORWARD_LAYER_SUPPORT_FUNC. std::vector inputConstTensorInfos; std::transform(inputTensorInfos.begin(), inputTensorInfos.end(), std::back_inserter(inputConstTensorInfos), [](armnn::TensorInfo& t)->const armnn::TensorInfo*{ return &t; }); const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteConcatOperatorCode, nodeIndex)) { return kTfLiteError; } // Setup OriginsDescriptor, axis and view origin unsigned int numConcatView = static_cast(numInputs); uint32_t inputRank = tfLiteTensors[tfLiteNode->inputs->data[0]].dims->size; auto* concatenationParameters = reinterpret_cast(tfLiteNode->builtin_data); if(!concatenationParameters) { throw armnn::Exception(&"TfLiteArmnnDelegate: Concat parameters are null in: " [ nodeIndex]); } const unsigned int concatDimInput = static_cast( (static_cast(inputRank) + concatenationParameters->axis) % static_cast(inputRank)); armnn::OriginsDescriptor concatDescriptor(static_cast(numConcatView), inputRank); concatDescriptor.SetConcatAxis(concatDimInput); unsigned int mergeDimOrigin = 0; for (unsigned int viewIndex = 0; viewIndex < numConcatView; ++viewIndex) { armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor( tfLiteTensors[tfLiteNode->inputs->data[viewIndex]]); // Sets up concatDescriptor view origin SetupConcatViewOrigin(inputTensorInfo, concatDescriptor, concatDimInput, viewIndex, mergeDimOrigin); } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Verify we support the fused activation before attempting to create a layer TfLiteFusedActivation activationType = concatenationParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("CONCATENATION", tfLiteContext, IsConcatSupported, delegateData.m_Backends, isSupported, setBackend, inputConstTensorInfos, outputTensorInfo, concatDescriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Setup layer and connect. auto layerName = GetLayerName(armnn::LayerType::Concat, nodeIndex); armnn::IConnectableLayer* concatenationLayer = delegateData.m_Network->AddConcatLayer(concatDescriptor, layerName.c_str()); concatenationLayer->SetBackendId(setBackend); ARMNN_ASSERT(concatenationLayer != nullptr); // Connect the Constant Inputs auto inputsTensorsProcess = ProcessInputs(concatenationLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } armnn::IOutputSlot& outputSlot = concatenationLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(concatenationLayer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (activationType == kTfLiteActNone) { // No Activation return kTfLiteOk; } // Check and Create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, concatenationLayer, 0, delegateData, nodeIndex); } TfLiteStatus VisitMeanOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteMeanOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if(!IsValid(&tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid input tensor in operator #%d node #%d: ", tfLiteMeanOperatorCode, nodeIndex); return kTfLiteError; } if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLiteMeanOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if(!IsValid(&tfLiteAxisTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid axis tensor in operator #%d node #%d: ", tfLiteMeanOperatorCode, nodeIndex); return kTfLiteError; } if (IsDynamicTensor(tfLiteAxisTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic axis tensors are not supported in operator #%d node #%d: ", tfLiteMeanOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if(!IsValid(&tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid output tensor in operator #%d node #%d: ", tfLiteAxisTensor, nodeIndex); return kTfLiteError; } if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLiteMeanOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAxisTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* axisTensorData = tflite::GetTensorData(&tfLiteAxisTensor); std::vector axis; // Add axis data to vector to be converter to unsigned int and assigned to descriptor axis. for (unsigned int i = 0; i < axisTensorInfo.GetNumElements(); ++i) { axis.emplace_back(axisTensorData[i]); } // Convert the axis to unsigned int and remove duplicates. unsigned int rank = inputTensorInfo.GetNumDimensions(); std::set uniqueAxis; std::transform(axis.begin(), axis.end(), std::inserter(uniqueAxis, uniqueAxis.begin()), [rank](int i)->unsigned int{ return (i + rank) % rank; }); // Setup MeanDescriptor and assign axis and keepDims armnn::MeanDescriptor desc; desc.m_Axis.assign(uniqueAxis.begin(), uniqueAxis.end()); desc.m_KeepDims = inputTensorInfo.GetNumDimensions() == outputTensorInfo.GetNumDimensions() ? true : false; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("MEAN", tfLiteContext, IsMeanSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Setup layer and connect. auto layerName = GetLayerName(armnn::LayerType::Mean, nodeIndex); armnn::IConnectableLayer* meanLayer = delegateData.m_Network->AddMeanLayer(desc, layerName.c_str()); meanLayer->SetBackendId(setBackend); ARMNN_ASSERT(meanLayer != nullptr); armnn::IOutputSlot& outputSlot = meanLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(meanLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(meanLayer, tfLiteNode, delegateData); } TfLiteStatus VisitControlOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { switch(operatorCode) { case kTfLiteBuiltinConcatenation: return VisitConcatenationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinMean: return VisitMeanOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); default: return kTfLiteError; } } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Convolution.hpp000066400000000000000000001013361446772241200216700ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitConv2dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); armnn::Convolution2dDescriptor descriptor; const auto params = reinterpret_cast(tfLiteNode->builtin_data); bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(params->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_DilationX = NonNegative(params->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(params->dilation_height_factor, nodeIndex); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteFilterTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType=kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); armnn::TensorInfo biasTensorInfo; if(biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::Optional optionalBiasInfo(biasTensorInfo); // TfLite uses NHWC tensors const unsigned int inputHeight = inputTensorInfo.GetShape()[1]; const unsigned int inputWidth = inputTensorInfo.GetShape()[2]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, params->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, params->padding); armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("CONV2D", tfLiteContext, IsConvolution2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, optionalBiasInfo); return isSupported ? kTfLiteOk : kTfLiteError; } // Set up filter and biases auto layerName = GetLayerName(armnn::LayerType::Convolution2d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddConvolution2dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); if (filterTensorInfo.IsConstant()) { auto filter = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[1]], filterTensorInfo); auto filterName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if (biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if(biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(&tfLiteBiasTensor, biasTensorInfo); auto biasName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if (inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[0]], inputTensorInfo); auto inputName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(layer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } // Conv3d is only correctly supported for external delegates from TF Lite v2.6, as there was a breaking bug in v2.5. #if defined(ARMNN_POST_TFLITE_2_5) TfLiteStatus VisitConv3dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); armnn::Convolution3dDescriptor descriptor; const auto params = reinterpret_cast(tfLiteNode->builtin_data); bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_DataLayout = armnn::DataLayout::NDHWC; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(params->stride_height, nodeIndex); descriptor.m_StrideZ = NonNegative(params->stride_depth, nodeIndex); descriptor.m_DilationX = NonNegative(params->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(params->dilation_height_factor, nodeIndex); descriptor.m_DilationZ = NonNegative(params->dilation_depth_factor, nodeIndex); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteFilterTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType=kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); armnn::TensorInfo biasTensorInfo; if(biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::Optional optionalBiasInfo(biasTensorInfo); // TfLite uses NDHWC tensors const unsigned int inputDepth = inputTensorInfo.GetShape()[1]; const unsigned int inputHeight = inputTensorInfo.GetShape()[2]; const unsigned int inputWidth = inputTensorInfo.GetShape()[3]; // Assuming the filter is DHWIO : Depth, Height, Width, OutputChannels, InputChannels const unsigned int filterDepth = filterTensorInfo.GetShape()[0]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputDepth, filterDepth, descriptor.m_StrideZ, descriptor.m_DilationZ, descriptor.m_PadFront, descriptor.m_PadBack, params->padding); CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, params->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, params->padding); // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitConvolutionOperator will be called again to add the layer to the network as seen below. armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("CONV3D", tfLiteContext, IsConvolution3dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, optionalBiasInfo); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Convolution3d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddConvolution3dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Add a constant layer for weights and biases if inputs are constant, // which are connected to the Convolution3d layer as inputs. if (filterTensorInfo.IsConstant()) { auto filter = CreateConstTensor(&tfLiteFilterTensor, filterTensorInfo); auto filterName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); ARMNN_ASSERT(weightsLayer != nullptr); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if(biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if(biasTensorInfo.IsConstant()) { auto biases = CreateConstTensor(&tfLiteBiasTensor, biasTensorInfo); auto biasName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biases, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[0]], inputTensorInfo); auto inputName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(layer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } #endif TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); armnn::DepthwiseConvolution2dDescriptor descriptor; const auto params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(params->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_DilationX = NonNegative(params->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(params->dilation_height_factor, nodeIndex); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteFilterTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); // Assuming input is NHWC unsigned int inputHeight = inputTensorInfo.GetShape()[1]; unsigned int inputWidth = inputTensorInfo.GetShape()[2]; // TensorflowLite weights come in the format [1, H, W, I * M] unsigned int filterHeight = filterTensorInfo.GetShape()[1]; unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, params->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, params->padding); armnn::TensorInfo biasTensorInfo; if(biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("DEPTHWISE_CONV2D", tfLiteContext, IsDepthwiseConvolutionSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, armnn::Optional(biasTensorInfo)); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Convolution3d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddDepthwiseConvolution2dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); if(filterTensorInfo.IsConstant()) { // For depthwise the weights layout is the same as for tflite [1, H, W, I*M]. No permutation required. auto filter = CreateConstTensor(&tfLiteFilterTensor, filterTensorInfo); auto filterName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if (biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if(biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(&tfLiteBiasTensor, biasTensorInfo); auto biasName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[0]], inputTensorInfo); auto inputName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(layer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } TfLiteStatus VisitTransposeConv2dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); armnn::TransposeConvolution2dDescriptor descriptor; auto* parameters = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_BiasEnabled = false; descriptor.m_StrideX = NonNegative(parameters->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(parameters->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteOutputShapeTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteFilterTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); // TfLite uses NHWC tensors const unsigned int inputHeight = inputTensorInfo.GetShape()[1]; const unsigned int inputWidth = inputTensorInfo.GetShape()[2]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // This block determines the output shape of the transpose convolution. // If the output shape tensor is a constant, we can access the data at load time and set the shape of the layer. // If this is not constant, we do not have access to the shape data, so we have to use infer output shape. if (tflite::IsConstantTensor(&tfLiteOutputShapeTensor)) { const armnn::TensorInfo outputShapeTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputShapeTensor); std::vector outputShape(outputShapeTensorInfo.GetNumElements()); if (outputShapeTensorInfo.GetDataType() == armnn::DataType::Signed32) { for(unsigned int i=0; i < outputShapeTensorInfo.GetNumElements(); ++i) { outputShape[i] = ::tflite::GetTensorData(&tfLiteOutputShapeTensor)[i]; } } if (outputShapeTensorInfo.GetDataType() == armnn::DataType::QAsymmU8) { for(unsigned int i=0; i < outputShapeTensorInfo.GetNumElements(); ++i) { outputShape[i] = ::tflite::GetTensorData(&tfLiteOutputShapeTensor)[i]; } } // Change from signed to unsigned int to store in TransposeConvolution2dDescriptor. for (int dimension : outputShape) { descriptor.m_OutputShape.push_back(static_cast(dimension)); } descriptor.m_OutputShapeEnabled = true; // TfLite uses NHWC tensors const unsigned int outputHeight = descriptor.m_OutputShape[1]; const unsigned int outputWidth = descriptor.m_OutputShape[2]; CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, 1, // DilationY descriptor.m_PadTop, descriptor.m_PadBottom, parameters->padding, outputHeight); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, 1, // DilationX descriptor.m_PadLeft, descriptor.m_PadRight, parameters->padding, outputWidth); } else { CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, 1, // DilationY descriptor.m_PadTop, descriptor.m_PadBottom, parameters->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, 1, // DilationX descriptor.m_PadLeft, descriptor.m_PadRight, parameters->padding); } // Set up filter auto filterTensor = CreateConstTensor(&tfLiteFilterTensor, filterTensorInfo); armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("TRANSPOSE_CONV2D", tfLiteContext, IsTransposeConvolution2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, armnn::EmptyOptional()); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::TransposeConvolution2d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddTransposeConvolution2dLayer(descriptor, filterTensor, armnn::EmptyOptional(), layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // The data input can be constant, so we must check that this is allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[2]], inputTensorInfo); auto inputName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect if (delegateData.m_OutputSlotForNode[static_cast(tfLiteNode->inputs->data[2])] != nullptr) { delegateData.m_OutputSlotForNode[static_cast(tfLiteNode->inputs->data[2])]-> Connect(layer->GetInputSlot(0)); } // Prepare output slots for (unsigned int outputIndex = 0; outputIndex < layer->GetNumOutputSlots(); ++outputIndex) { armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(outputIndex); delegateData.m_OutputSlotForNode[static_cast(tfLiteNode->outputs->data[outputIndex])] = &outputSlot; } return kTfLiteOk; } TfLiteStatus VisitConvolutionOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { switch(operatorCode) { case kTfLiteBuiltinConv2d: return VisitConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); // Conv3d is only correctly supported for external delegates from TF Lite v2.6, as there was a breaking bug in v2.5. #if defined(ARMNN_POST_TFLITE_2_5) case kTfLiteBuiltinConv3d: return VisitConv3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); #endif case kTfLiteBuiltinDepthwiseConv2d: return VisitDepthwiseConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinTransposeConv: return VisitTransposeConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); default: return kTfLiteError; } } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/ElementwiseBinary.hpp000066400000000000000000000527751446772241200230130ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include "MultiLayerFacade.hpp" #include "SharedFunctions.hpp" #include #include #include #include #include "tensorflow/lite/delegates/utils.h" namespace armnnDelegate { TfLiteStatus ValidateAddOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { std::vector infos { inputInfo1, inputInfo2, outputInfo }; FORWARD_LAYER_SUPPORT_FUNC("ADD", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputInfo, armnn::BinaryOperation::Add); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateDivOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("DIV", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Div); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateFloorDivOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { // need first to validate that the div operator is supported // then that the floor operator is supported TfLiteStatus status = ValidateDivOperator(delegateData, tfLiteContext, inputInfo1, inputInfo2, outputInfo); if (status != kTfLiteOk) { return status; } // if the inputs and output of the div are all Signed32 we don't need to add the floor operator afterward. if (AreAllSigned32(inputInfo1, inputInfo2, outputInfo)) { return status; } // in case broadcasting is being done from one of the inputs to the div // choose the full sized input tensor to pass to the floor validation routine armnn::TensorInfo floorInputInfo = inputInfo1; if (inputInfo1.GetNumDimensions() < inputInfo2.GetNumDimensions()) { floorInputInfo = inputInfo2; } status = ValidateFloorOperator(delegateData, tfLiteContext, floorInputInfo, outputInfo); return status; } TfLiteStatus ValidateMaximumOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("MAXIMUM", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Maximum); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateMinimumOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("MINIMUM", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Minimum); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateMulOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("MUL", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Mul); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidatePowerOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("POWER", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Power); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateSquaredDifferenceOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SQUAREDDIFFERENCE", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::SqDiff); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateSubOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SUB", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Sub); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } std::pair AddFloorDivLayer( DelegateData& delegateData, const armnn::TensorInfo& outputTensorInfo, int nodeIndex) { auto divName = GetLayerName(armnn::BinaryOperation::Div, nodeIndex); armnn::IConnectableLayer* divisionLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Div, divName.c_str()); // if the output of the div is Signed32 the Floor layer is not required if (armnn::DataType::Signed32 == outputTensorInfo.GetDataType()) { return std::make_pair(divisionLayer, divisionLayer); } armnn::IOutputSlot& outputSlot = divisionLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto floorName = GetLayerName(armnn::LayerType::Floor, nodeIndex); armnn::IConnectableLayer* floorLayer = delegateData.m_Network->AddFloorLayer(floorName.c_str()); outputSlot.Connect(floorLayer->GetInputSlot(0)); return std::make_pair(divisionLayer, floorLayer); } TfLiteStatus VisitElementwiseBinaryOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t elementwiseBinaryOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor0 = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor0)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", elementwiseBinaryOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor1 = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteInputTensor1)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", elementwiseBinaryOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", elementwiseBinaryOperatorCode, nodeIndex); return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of the input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } if (!delegateData.m_Network) { switch(elementwiseBinaryOperatorCode) { case kTfLiteBuiltinAdd: return ValidateAddOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinDiv: return ValidateDivOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinFloorDiv: return ValidateFloorDivOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMaximum: return ValidateMaximumOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMinimum: return ValidateMinimumOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMul: return ValidateMulOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinPow: return ValidatePowerOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinSquaredDifference: return ValidateSquaredDifferenceOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinSub: return ValidateSubOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); default: return kTfLiteError; } } armnn::IConnectableLayer* elementwiseBinaryLayer = nullptr; MultiLayerFacade multiLayer; std::string layerName; switch(elementwiseBinaryOperatorCode) { case kTfLiteBuiltinAdd: layerName = GetLayerName(armnn::BinaryOperation::Add, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Add, layerName.c_str()); break; case kTfLiteBuiltinDiv: layerName = GetLayerName(armnn::BinaryOperation::Div, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Div, layerName.c_str()); break; case kTfLiteBuiltinFloorDiv: { auto layers = AddFloorDivLayer(delegateData, outputTensorInfo, nodeIndex); multiLayer.AssignValues(layers.first, layers.second); elementwiseBinaryLayer = &multiLayer; } break; case kTfLiteBuiltinMaximum: layerName = GetLayerName(armnn::BinaryOperation::Maximum, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Maximum, layerName.c_str()); break; case kTfLiteBuiltinMinimum: layerName = GetLayerName(armnn::BinaryOperation::Minimum, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Minimum, layerName.c_str()); break; case kTfLiteBuiltinMul: layerName = GetLayerName(armnn::BinaryOperation::Mul, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Mul, layerName.c_str()); break; case kTfLiteBuiltinPow: layerName = GetLayerName(armnn::BinaryOperation::Power, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Power, layerName.c_str()); break; case kTfLiteBuiltinSquaredDifference: layerName = GetLayerName(armnn::BinaryOperation::SqDiff, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::SqDiff, layerName.c_str()); break; case kTfLiteBuiltinSub: layerName = GetLayerName(armnn::BinaryOperation::Sub, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Sub, layerName.c_str()); break; default: return kTfLiteError; } ARMNN_ASSERT(elementwiseBinaryLayer != nullptr); armnn::IOutputSlot& outputSlot = elementwiseBinaryLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(elementwiseBinaryLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } if(Connect(elementwiseBinaryLayer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create Activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, elementwiseBinaryLayer, 0, delegateData, nodeIndex); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/ElementwiseUnary.hpp000066400000000000000000000065361446772241200226570ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitElementwiseUnaryOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, armnn::UnaryOperation unaryOperation) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in node #%d: ", nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ElementwiseUnaryDescriptor descriptor(unaryOperation); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("ELEMENTWISE_UNARY", tfLiteContext, IsElementwiseUnarySupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(descriptor.m_Operation, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddElementwiseUnaryLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Fill.hpp000066400000000000000000000100241446772241200202300ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitFillOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteFillOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); switch(tfLiteFillOperatorCode) { case kTfLiteBuiltinFill: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); break; default: return kTfLiteError; } const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteFillTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteFillTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::FillDescriptor descriptor; switch (tfLiteFillTensor.type) { case kTfLiteFloat32: descriptor.m_Value = tflite::GetTensorData(&tfLiteFillTensor)[0]; break; case kTfLiteInt32: descriptor.m_Value = tflite::GetTensorData(&tfLiteFillTensor)[0]; break; default: TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: FILL value data type is not supported in operator #%d node #%d: ", tfLiteFillOperatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("FILL", tfLiteContext, IsFillSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Fill, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFillLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/FullyConnected.hpp000066400000000000000000000265671446772241200223030ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include "armnnUtils/TensorUtils.hpp" #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitFullyConnectedOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteWeightsTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteWeightsTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& weightsTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteWeightsTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Check that we support fused activation before we attempt to create a layer auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType=kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } // Fully Connected Layer accepts two dimensional weights input int32_t weightsDimension = static_cast(weightsTensorInfo.GetNumDimensions()); if (weightsDimension != 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dimension #$d for Fully Connected weights is not supported by Armnn" " in operator #%d node #%d: ", weightsDimension, operatorCode, nodeIndex); return kTfLiteError; } armnn::TensorInfo biasTensorInfo; if (biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::TensorInfo reshapedTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); if (inputTensorInfo.GetNumDimensions() > 2) { // Calculate reshape to flatten to 2D [batch_size, input_size] std::vector reshapedDimensions(2); reshapedDimensions[1] = weightsTensorInfo.GetShape()[1]; reshapedDimensions[0] = inputTensorInfo.GetNumElements() / reshapedDimensions[1]; if (inputTensorInfo.GetNumElements() % reshapedDimensions[1] != 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Failed to deduce input tensor shape from filter size #%d #%d node #%d: ", reshapedDimensions[1], operatorCode, nodeIndex); return kTfLiteError; } reshapedTensorInfo.SetShape(armnn::TensorShape{ 2, reshapedDimensions.data() }); } armnn::TensorInfo reshapedOutputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); if (outputTensorInfo.GetNumDimensions() > 2) { // Calculate reshape to flatten to 2D [batch_size, input_size] std::vector reshapedDimensions(2); reshapedDimensions[1] = weightsTensorInfo.GetShape()[0]; reshapedDimensions[0] = outputTensorInfo.GetNumElements() / reshapedDimensions[1]; if (outputTensorInfo.GetNumElements() % reshapedDimensions[1] != 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Failed to deduce output tensor shape from filter size #%d #%d node #%d: ", reshapedDimensions[1], operatorCode, nodeIndex); return kTfLiteError; } reshapedOutputTensorInfo.SetShape(armnn::TensorShape{ 2, reshapedDimensions.data() }); } armnn::FullyConnectedDescriptor descriptor; descriptor.m_TransposeWeightMatrix = true; descriptor.m_BiasEnabled = biasEnabled; descriptor.m_ConstantWeights = weightsTensorInfo.IsConstant(); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("FULLY_CONNECTED", tfLiteContext, IsFullyConnectedSupported, delegateData.m_Backends, isSupported, setBackend, reshapedTensorInfo, outputTensorInfo, weightsTensorInfo, biasTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(reshapedOutputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::FullyConnected, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFullyConnectedLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Add a constant layer for weights and biases if inputs are constant. if (weightsTensorInfo.IsConstant()) { auto weightsTensor = CreateConstTensor(&tfLiteWeightsTensor, weightsTensorInfo); auto weightsName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Weights"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(weightsTensor, weightsName.c_str()); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(weightsTensorInfo); } if (biasEnabled) { const TfLiteTensor& tfLiteBiasTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if(biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(&tfLiteBiasTensor, biasTensorInfo); auto biasName = GetLayerName(armnn::LayerType::FullyConnected, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if (inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[0]], inputTensorInfo); auto constantName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer *inputLayer = delegateData.m_Network->AddConstantLayer(input, constantName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); armnn::IConnectableLayer* reshapeLayer = nullptr; if (inputTensorInfo.GetNumDimensions() > 2) { // Add reshape to flatten to 2D [batch_size, input_size] armnn::ReshapeDescriptor reshapeDescriptor; reshapeDescriptor.m_TargetShape = reshapedTensorInfo.GetShape(); auto reshapeName = GetLayerName(armnn::LayerType::Reshape, nodeIndex, "Input"); reshapeLayer = delegateData.m_Network->AddReshapeLayer(reshapeDescriptor, reshapeName.c_str()); ARMNN_ASSERT(reshapeLayer != nullptr); reshapeLayer->GetOutputSlot(0).SetTensorInfo(reshapedTensorInfo); // Connect delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[0]]->Connect(reshapeLayer->GetInputSlot(0)); reshapeLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0)); if (!descriptor.m_ConstantWeights) { delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[1]]->Connect(layer->GetInputSlot(1)); } if (biasEnabled && !biasTensorInfo.IsConstant()) { delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[2]]->Connect(layer->GetInputSlot(2)); } delegateData.m_OutputSlotForNode[tfLiteNode->outputs->data[0]] = &outputSlot; } if (reshapeLayer == nullptr) { if(Connect(layer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } } if (outputTensorInfo.GetNumDimensions() > 2) { layer = AddReshapeLayer(tfLiteContext, tfLiteNode, layer, reshapedOutputTensorInfo, outputTensorInfo, delegateData, nodeIndex); if (!layer) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Failed to add reshape for FullyConnected #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create Activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/Gather.hpp000066400000000000000000000104111446772241200205540ustar00rootroot00000000000000// // Copyright © 2020,2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitGatherOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteIndicesTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteIndicesTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } auto* gatherParameters = reinterpret_cast(tfLiteNode->builtin_data); auto axis = gatherParameters->axis; const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteIndicesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::GatherDescriptor gatherDescriptor; gatherDescriptor.m_Axis = axis; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); auto indicesDimensions = indicesTensorInfo.GetNumDimensions(); auto outputDimensions = outputTensorInfo.GetNumDimensions(); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Operation has invalid axis: %d. It is out of bounds [-%d, %d))", axis, inputDimensions, inputDimensions); return kTfLiteError; } if (outputDimensions != static_cast(inputDimensions) + indicesDimensions - 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "Operation has invalid output dimensions: %d. Output must be an (%d + %d - 1)-D tensor", outputDimensions, inputDimensions, indicesDimensions); return kTfLiteError; } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("GATHER", tfLiteContext, IsGatherSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, indicesTensorInfo, outputTensorInfo, gatherDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Gather, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddGatherLayer(gatherDescriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/GatherNd.hpp000066400000000000000000000061411446772241200210430ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitGatherNdOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteIndicesTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteIndicesTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteIndicesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("GATHER_ND", tfLiteContext, IsGatherNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, indicesTensorInfo, outputTensorInfo); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::GatherNd, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddGatherNdLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/LogicalBinary.hpp000066400000000000000000000101601446772241200220620ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitLogicalBinaryOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t logicalOperatorCode, armnn::LogicalBinaryOperation binaryOperation) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor0 = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor0, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor1 = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteInputTensor1, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of any of the input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } // Setup descriptor and assign operation armnn::LogicalBinaryDescriptor desc; desc.m_Operation = binaryOperation; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("LOGICAL_BINARY", tfLiteContext, IsLogicalBinarySupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, inputTensorInfo1, outputTensorInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(desc.m_Operation, nodeIndex); armnn::IConnectableLayer* logicalBinaryLayer = delegateData.m_Network->AddLogicalBinaryLayer(desc, layerName.c_str()); logicalBinaryLayer->SetBackendId(setBackend); ARMNN_ASSERT(logicalBinaryLayer != nullptr); armnn::IOutputSlot& outputSlot = logicalBinaryLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(logicalBinaryLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(logicalBinaryLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Lstm.hpp000066400000000000000000000267311446772241200202750ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitLstmOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } const auto nodeParams = reinterpret_cast(tfLiteNode->builtin_data); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Set the params structure for the AddLstmLayer call armnn::LstmInputParams params; if (IsOptionalOperandPresent(tfLiteNode, 1)) { params.m_InputToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 1); } params.m_InputToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 2); params.m_InputToCellWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 3); params.m_InputToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 4); // Recurrent weight tensors of size {n_cell, n_output} if (IsOptionalOperandPresent(tfLiteNode, 5)) { params.m_RecurrentToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 5); } params.m_RecurrentToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 6); params.m_RecurrentToCellWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 7); params.m_RecurrentToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 8); // Peephole weights tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 9)) { params.m_CellToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 9); } if (IsOptionalOperandPresent(tfLiteNode, 10)) { params.m_CellToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 10); } if (IsOptionalOperandPresent(tfLiteNode, 11)) { params.m_CellToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 11); } // Gates bias tensors of size {n_cell} if (IsOptionalOperandPresent(tfLiteNode, 12)) { params.m_InputGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 12); } params.m_ForgetGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 13); params.m_CellBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 14); params.m_OutputGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 15); // Projection weight tensor of size {n_output, n_cell} if (IsOptionalOperandPresent(tfLiteNode, 16)) { params.m_ProjectionWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 16); } // Projection bias tensor of size {n_output} if (IsOptionalOperandPresent(tfLiteNode, 17)) { params.m_ProjectionBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 17); } // These state tensors are defined as variable tensors, and will be modified by this op. armnn::TensorInfo outputStateInInfo = GetTensorInfoForTfLiteTensor(tfLiteTensors[tfLiteNode->inputs->data[18]]); armnn::TensorInfo cellStateInInfo = GetTensorInfoForTfLiteTensor(tfLiteTensors[tfLiteNode->inputs->data[19]]); // Layer norm coefficient tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 20)) { params.m_InputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 20); } if (IsOptionalOperandPresent(tfLiteNode, 21)) { params.m_ForgetLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 21); } if (IsOptionalOperandPresent(tfLiteNode, 22)) { params.m_CellLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 22); } if (IsOptionalOperandPresent(tfLiteNode, 23)) { params.m_OutputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 23); } // set the layer descriptor armnn::LstmDescriptor desc; desc.m_ActivationFunc = NonNegative(nodeParams->activation, nodeIndex); desc.m_ClippingThresCell = nodeParams->cell_clip; desc.m_ClippingThresProj = nodeParams->proj_clip; desc.m_CifgEnabled = (params.m_InputToInputWeights == nullptr || params.m_RecurrentToInputWeights == nullptr || params.m_InputGateBias == nullptr); desc.m_PeepholeEnabled = (params.m_CellToForgetWeights != nullptr || params.m_CellToOutputWeights != nullptr); desc.m_ProjectionEnabled = (params.m_ProjectionWeights != nullptr); desc.m_LayerNormEnabled = (params.m_InputLayerNormWeights != nullptr || params.m_ForgetLayerNormWeights != nullptr || params.m_CellLayerNormWeights != nullptr || params.m_OutputLayerNormWeights != nullptr); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[1]; unsigned int numUnits = cellStateInInfo.GetShape()[1]; armnn::DataType dataType = inputTensorInfo.GetDataType(); float qScale = inputTensorInfo.GetQuantizationScale(); float qOffset = inputTensorInfo.GetQuantizationOffset(); armnn::TensorInfo scratchBufferTensorInfo({batchSize, numUnits * 3}, dataType, qScale, qOffset); if (!desc.m_CifgEnabled) { scratchBufferTensorInfo = armnn::TensorInfo({batchSize, numUnits * 4}, dataType, qScale, qOffset); } armnn::TensorInfo cellStateOutTensorInfo({batchSize, numUnits}, dataType, qScale, qOffset); armnn::TensorInfo outputStateOutTensorInfo({batchSize, outputSize}, dataType, qScale, qOffset); armnn::LstmInputParamsInfo paramsInfo; paramsInfo.m_InputToForgetWeights = &(params.m_InputToForgetWeights->GetInfo()); paramsInfo.m_InputToCellWeights = &(params.m_InputToCellWeights->GetInfo()); paramsInfo.m_InputToOutputWeights = &(params.m_InputToOutputWeights->GetInfo()); paramsInfo.m_RecurrentToForgetWeights = &(params.m_RecurrentToForgetWeights->GetInfo()); paramsInfo.m_RecurrentToCellWeights = &(params.m_RecurrentToCellWeights->GetInfo()); paramsInfo.m_RecurrentToOutputWeights = &(params.m_RecurrentToOutputWeights->GetInfo()); paramsInfo.m_ForgetGateBias = &(params.m_ForgetGateBias->GetInfo()); paramsInfo.m_CellBias = &(params.m_CellBias->GetInfo()); paramsInfo.m_OutputGateBias = &(params.m_OutputGateBias->GetInfo()); if (!desc.m_CifgEnabled) { paramsInfo.m_InputToInputWeights = &(params.m_InputToInputWeights->GetInfo()); paramsInfo.m_RecurrentToInputWeights = &(params.m_RecurrentToInputWeights->GetInfo()); if (params.m_CellToInputWeights != nullptr) { paramsInfo.m_CellToInputWeights = &(params.m_CellToInputWeights->GetInfo()); } paramsInfo.m_InputGateBias = &(params.m_InputGateBias->GetInfo()); } if (desc.m_ProjectionEnabled) { paramsInfo.m_ProjectionWeights = &(params.m_ProjectionWeights->GetInfo()); if (params.m_ProjectionBias != nullptr) { paramsInfo.m_ProjectionBias = &(params.m_ProjectionBias->GetInfo()); } } if (desc.m_PeepholeEnabled) { paramsInfo.m_CellToForgetWeights = &(params.m_CellToForgetWeights->GetInfo()); paramsInfo.m_CellToOutputWeights = &(params.m_CellToOutputWeights->GetInfo()); } if (desc.m_LayerNormEnabled) { if(!desc.m_CifgEnabled) { paramsInfo.m_InputLayerNormWeights = &(params.m_InputLayerNormWeights->GetInfo()); } paramsInfo.m_ForgetLayerNormWeights = &(params.m_ForgetLayerNormWeights->GetInfo()); paramsInfo.m_CellLayerNormWeights = &(params.m_CellLayerNormWeights->GetInfo()); paramsInfo.m_OutputLayerNormWeights = &(params.m_OutputLayerNormWeights->GetInfo()); } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("LSTM", tfLiteContext, IsLstmSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputStateInInfo, cellStateInInfo, scratchBufferTensorInfo, outputStateOutTensorInfo, cellStateOutTensorInfo, outputInfo, desc, paramsInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Lstm, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddLstmLayer(desc, params, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(scratchBufferTensorInfo); layer->GetOutputSlot(1).SetTensorInfo(outputStateOutTensorInfo); layer->GetOutputSlot(2).SetTensorInfo(cellStateOutTensorInfo); layer->GetOutputSlot(3).SetTensorInfo(outputTensorInfo); // Connect the inputs // input_layer delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[0]]->Connect(layer->GetInputSlot(0)); // cellStateIn delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[18]]->Connect(layer->GetInputSlot(1)); //outputStateIn delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[19]]->Connect(layer->GetInputSlot(2)); // In the test_model there is only 1 Output armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(1); delegateData.m_OutputSlotForNode[static_cast(tfLiteNode->outputs->data[0])] = &outputSlot; return kTfLiteOk; } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/Normalization.hpp000066400000000000000000000146051446772241200222010ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitL2NormalizationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::L2NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("L2_NORMALIZATION", tfLiteContext, IsL2NormalizationSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a L2Normalization layer auto layerName = GetLayerName(armnn::LayerType::L2Normalization, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddL2NormalizationLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitLocalResponseNormalizationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t normalizationOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, normalizationOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, normalizationOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_NormChannelType = armnn::NormalizationAlgorithmChannel::Across; descriptor.m_NormMethodType = armnn::NormalizationAlgorithmMethod::LocalBrightness; auto* params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_NormSize = params->radius; descriptor.m_K = params->bias; descriptor.m_Alpha = params->alpha; descriptor.m_Beta = params->beta; // ArmNN expects normSize to be the full size of the normalization window descriptor.m_NormSize = 1 + (2 * descriptor.m_NormSize); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("NORMALIZATION", tfLiteContext, IsNormalizationSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Normalization layer auto layerName = GetLayerName(armnn::LayerType::Normalization, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddNormalizationLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Pack.hpp000066400000000000000000000112561446772241200202300ustar00rootroot00000000000000// // Copyright © 2021,2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitPackOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { unsigned int numInputs = tfLiteNode->inputs->size; if (numInputs < 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Must have at least one input in (%d != %d) in node #%d", 1, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; // Validate all inputs and get TensorInfo std::vector inputTensorInfos; for (unsigned int i = 0; i < numInputs; ++i) { const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[i]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); inputTensorInfos.emplace_back(inputTensorInfo); } // Convert input tensors to const armnn::TensorInfo* type for FORWARD_LAYER_SUPPORT_FUNC. std::vector inputConstTensorInfos; std::transform(inputTensorInfos.begin(), inputTensorInfos.end(), std::back_inserter(inputConstTensorInfos), [](armnn::TensorInfo& t)->const armnn::TensorInfo*{ return &t; }); // Validate output and get TensorInfo const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::StackDescriptor desc; desc.m_NumInputs = static_cast(numInputs); // Get axis from TfLite parameters auto* params = reinterpret_cast(tfLiteNode->builtin_data); desc.m_Axis = static_cast(params->axis); // Use the tensor shape of the first input as the "correct" input shape in the descriptor desc.m_InputShape = inputTensorInfos[0].GetShape(); // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("STACK", tfLiteContext, IsStackSupported, delegateData.m_Backends, isSupported, setBackend, inputConstTensorInfos, outputTensorInfo, desc); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitPackOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // The TfLite Pack operator is equivalent to the ArmNN Stack operator auto layerName = GetLayerName(armnn::LayerType::Stack, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddStackLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Connect the Constant Inputs auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Pad.hpp000066400000000000000000000161311446772241200200530ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitPadOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLitePadOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); switch(tfLitePadOperatorCode) { case kTfLiteBuiltinMirrorPad: case kTfLiteBuiltinPad: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); break; case kTfLiteBuiltinPadv2: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); break; default: return kTfLiteError; } const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; const TfLiteTensor& tfLitepaddingTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& paddingTensorInfo = GetTensorInfoForTfLiteTensor(tfLitepaddingTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get the padding data from the input tensor auto* paddingData = tflite::GetTensorData(&tfLitepaddingTensor); size_t step = 2; armnn::PadDescriptor descriptor; for (unsigned int i = 0; i < paddingTensorInfo.GetNumElements() / step; ++i) { descriptor.m_PadList.emplace_back(paddingData[i * step], paddingData[i * step + 1]); } if (tfLitePadOperatorCode == kTfLiteBuiltinPad && inputTensorInfo.IsQuantized()) { descriptor.m_PadValue = inputTensorInfo.GetQuantizationOffset(); } else if (tfLitePadOperatorCode == kTfLiteBuiltinPadv2) { const TfLiteTensor& tfLitepaddingValue = tfLiteTensors[tfLiteNode->inputs->data[2]]; armnn::TensorInfo paddingValueTensorInfo = GetTensorInfoForTfLiteTensor(tfLitepaddingValue); if (paddingValueTensorInfo.GetNumElements() != 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Multiple padding value are not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } // Get the padding value from the input tensor switch (tfLitepaddingValue.type) { case kTfLiteFloat32: descriptor.m_PadValue = tflite::GetTensorData(&tfLitepaddingValue)[0]; break; case kTfLiteUInt8: descriptor.m_PadValue = tflite::GetTensorData(&tfLitepaddingValue)[0]; break; case kTfLiteInt8: descriptor.m_PadValue = tflite::GetTensorData(&tfLitepaddingValue)[0]; break; default: TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Padding value datatype is not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } } else if (tfLitePadOperatorCode == kTfLiteBuiltinMirrorPad) { TfLiteMirrorPaddingParams* options = reinterpret_cast(tfLiteNode->builtin_data); if (options->mode == TfLiteMirrorPaddingMode::kTfLiteMirrorPaddingReflect) { descriptor.m_PaddingMode = armnn::PaddingMode::Reflect; } else if (options->mode == TfLiteMirrorPaddingMode::kTfLiteMirrorPaddingSymmetric) { descriptor.m_PaddingMode = armnn::PaddingMode::Symmetric; } else { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: PaddingMode must be either REFLECT or SYMMETRIC in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); } // If padding mode is Reflect then both paddings must be no greater than inputShape(i) - 1. // If padding mode is Symmetric then both paddings must be no greater than inputShape(i). auto inputShape = inputTensorInfo.GetShape(); auto padList = descriptor.m_PadList; const unsigned int isReflect = static_cast(descriptor.m_PaddingMode == armnn::PaddingMode::Reflect); for(unsigned int i = 0; i < padList.size(); ++i) { if(padList.at(i).first > (inputShape[i] - isReflect) || padList.at(i).second > (inputShape[i] - isReflect)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Padding values must be less (Reflect) or " "equal (Symmetric) to the dimension size in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); } } } armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("PAD", tfLiteContext, IsPadSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Pad, nodeIndex); armnn::IConnectableLayer* padLayer = delegateData.m_Network->AddPadLayer(descriptor, layerName.c_str()); padLayer->SetBackendId(setBackend); ARMNN_ASSERT(padLayer != nullptr); armnn::IOutputSlot& outputSlot = padLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); return Connect(padLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Pooling.hpp000066400000000000000000000314061446772241200207600ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitPooling2dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLitePoolingOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLitePoolingOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLitePoolingOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(tfLiteNode->builtin_data); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } armnn::PoolingAlgorithm poolingAlgorithm; switch(tfLitePoolingOperatorCode) { case kTfLiteBuiltinAveragePool2d: poolingAlgorithm = armnn::PoolingAlgorithm::Average; break; case kTfLiteBuiltinL2Pool2d: poolingAlgorithm = armnn::PoolingAlgorithm::L2; break; case kTfLiteBuiltinMaxPool2d: poolingAlgorithm = armnn::PoolingAlgorithm::Max; break; default: return kTfLiteError; } armnn::Pooling2dDescriptor descriptor; descriptor.m_PoolType = poolingAlgorithm; descriptor.m_PoolWidth = tfLiteNodeParameters->filter_width; descriptor.m_PoolHeight = tfLiteNodeParameters->filter_height; descriptor.m_StrideX = tfLiteNodeParameters->stride_width; descriptor.m_StrideY = tfLiteNodeParameters->stride_height; descriptor.m_DataLayout = armnn::DataLayout::NHWC; unsigned int inputHeight = inputTensorInfo.GetShape()[1]; unsigned int inputWidth = inputTensorInfo.GetShape()[2]; CalcPadding(inputHeight, descriptor.m_PoolHeight, descriptor.m_StrideY, 1u, descriptor.m_PadTop, descriptor.m_PadBottom, tfLiteNodeParameters->padding); CalcPadding(inputWidth, descriptor.m_PoolWidth, descriptor.m_StrideX, 1u, descriptor.m_PadLeft, descriptor.m_PadRight, tfLiteNodeParameters->padding); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("POOLING_2D", tfLiteContext, IsPooling2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Pooling2d, nodeIndex); armnn::IConnectableLayer* poolingLayer = delegateData.m_Network->AddPooling2dLayer(descriptor, layerName.c_str()); poolingLayer->SetBackendId(setBackend); ARMNN_ASSERT(poolingLayer != nullptr); armnn::IOutputSlot& outputSlot = poolingLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(poolingLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } if (Connect(poolingLayer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, poolingLayer, 0, delegateData, nodeIndex); } TfLiteStatus VisitPooling3dOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, std::string customOperatorName) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", customOperatorName.c_str(), nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", customOperatorName.c_str(), nodeIndex); return kTfLiteError; } // Set the input and output info const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Custom Operators are defined by the name string associated to the operator. Use this to determine // which pooling algorithm to create the armnn operator with. L2 Pooling3D is unsupported in TfLite. armnn::PoolingAlgorithm poolingAlgorithm; if (customOperatorName == "MaxPool3D") { poolingAlgorithm = armnn::PoolingAlgorithm::Max; } else if (customOperatorName == "AveragePool3D") { poolingAlgorithm = armnn::PoolingAlgorithm::Average; } else { return kTfLiteError; } // Create the armnn pool3d descriptor and set the algorithm parsed above. armnn::Pooling3dDescriptor descriptor; descriptor.m_PoolType = poolingAlgorithm; // custom_initial_data and custom_initial_data_size are void* variables defined in the tflite registration // used to access the custom option buffer for the operator. auto custom_data = tfLiteNode->custom_initial_data; auto custom_data_size = tfLiteNode->custom_initial_data_size; // Reinterpret the void* to a byte buffer to access the options data in the flexbuffers map. const flexbuffers::Map& m = flexbuffers::GetRoot(reinterpret_cast(custom_data), custom_data_size).AsMap(); // poolDims is a vector of [ 1, Depth, Height, Width, 1 ] const auto poolDims = m["ksize"].AsTypedVector(); descriptor.m_PoolWidth = poolDims[3].AsInt32(); descriptor.m_PoolHeight = poolDims[2].AsInt32(); descriptor.m_PoolDepth = poolDims[1].AsInt32(); // strideDimes is a vector of [ 1, Z, Y, X, 1] const auto strideDims = m["strides"].AsTypedVector(); descriptor.m_StrideX = strideDims[3].AsInt32(); descriptor.m_StrideY = strideDims[2].AsInt32(); descriptor.m_StrideZ = strideDims[1].AsInt32(); descriptor.m_DataLayout = armnn::DataLayout::NDHWC; unsigned int inputDepth = inputTensorInfo.GetShape()[1]; unsigned int inputHeight = inputTensorInfo.GetShape()[2]; unsigned int inputWidth = inputTensorInfo.GetShape()[3]; // CalcPadding expects a TfLitePadding type. Parse flexbuffers to extract padding string and create TfLitePadding. std::string paddingStr = m["padding"].AsString().str(); TfLitePadding padding; if (paddingStr == "VALID") { padding = kTfLitePaddingValid; } else if (paddingStr == "SAME") { padding = kTfLitePaddingSame; } else { padding = kTfLitePaddingUnknown; } // Calculates padding for each pooling dimension separately CalcPadding(inputHeight, descriptor.m_PoolHeight, descriptor.m_StrideY, 1u, descriptor.m_PadTop, descriptor.m_PadBottom, padding); CalcPadding(inputWidth, descriptor.m_PoolWidth, descriptor.m_StrideX, 1u, descriptor.m_PadLeft, descriptor.m_PadRight, padding); CalcPadding(inputDepth, descriptor.m_PoolDepth, descriptor.m_StrideZ, 1u, descriptor.m_PadFront, descriptor.m_PadBack, padding); // Check activation by parsing the string from the flexbuffer map std::string activationTypeStr = m["activation"].AsString().str(); TfLiteFusedActivation activationType = kTfLiteActNone; if (activationTypeStr == "kTfLiteActRelu") { activationType = kTfLiteActRelu; } else if (activationTypeStr == "kTfLiteActReluN1To1") { activationType = kTfLiteActReluN1To1; } else if (activationTypeStr == "kTfLiteActRelu6") { activationType = kTfLiteActRelu6; } else if (activationTypeStr == "kTfLiteActTanh") { activationType = kTfLiteActTanh; } else if (activationTypeStr == "kTfLiteActSignBit") { activationType = kTfLiteActSignBit; } else if (activationTypeStr == "kTfLiteActSigmoid") { activationType = kTfLiteActSigmoid; } else { activationType = kTfLiteActNone; } TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } // Validate the output info. bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("POOLING_3D", tfLiteContext, IsPooling3dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Create the Layer auto layerName = GetLayerName(armnn::LayerType::Pooling3d, nodeIndex); armnn::IConnectableLayer* poolingLayer = delegateData.m_Network->AddPooling3dLayer(descriptor); poolingLayer->SetBackendId(setBackend); ARMNN_ASSERT(poolingLayer != nullptr); // Create and set output slots armnn::IOutputSlot& outputSlot = poolingLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(poolingLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } if (Connect(poolingLayer, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } return FusedActivation(tfLiteContext, tfLiteNode, activationType, poolingLayer, 0, delegateData, nodeIndex); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Prelu.hpp000066400000000000000000000103361446772241200204370ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidatePreluOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& alphaInfo, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("PRELU", tfLiteContext, IsPreluSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, alphaInfo, outputInfo); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitPreluOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteAlphaTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteAlphaTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& alphaTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAlphaTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { return ValidatePreluOperator(delegateData, tfLiteContext, inputTensorInfo, alphaTensorInfo, outputTensorInfo); } auto layerName = GetLayerName(armnn::LayerType::Prelu, nodeIndex); armnn::IConnectableLayer* preluLayer = delegateData.m_Network->AddPreluLayer(layerName.c_str()); ARMNN_ASSERT(preluLayer != nullptr); bool isConstantAlpha = tflite::IsConstantTensor(&tfLiteAlphaTensor); // Add constant layer for constant alpha if (isConstantAlpha) { auto constAlphaTensor = armnn::ConstTensor(alphaTensorInfo, tfLiteAlphaTensor.data.data); auto alphaName = GetLayerName(armnn::LayerType::Constant, nodeIndex, "Alpha"); armnn::IConnectableLayer* constLayer = delegateData.m_Network->AddConstantLayer(constAlphaTensor, alphaName.c_str()); ARMNN_ASSERT(constLayer != nullptr); constLayer->GetOutputSlot(0).SetTensorInfo(alphaTensorInfo); constLayer->GetOutputSlot(0).Connect(preluLayer->GetInputSlot(1)); } armnn::IOutputSlot& outputSlot = preluLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(preluLayer, tfLiteNode, delegateData); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/Quantization.hpp000066400000000000000000000154021446772241200220350ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitDequantizeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteDequantizeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLiteDequantizeOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLiteDequantizeOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); armnn::TensorInfo outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); UpdateConstantTensorOutputs(inputTensorInfo, outputTensorInfo); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("DEQUANTIZE", tfLiteContext, IsDequantizeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Dequantize, nodeIndex); armnn::IConnectableLayer* dequantizeLayer = delegateData.m_Network->AddDequantizeLayer(layerName.c_str()); dequantizeLayer->SetBackendId(setBackend); ARMNN_ASSERT(dequantizeLayer != nullptr); armnn::IOutputSlot& outputSlot = dequantizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(dequantizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(dequantizeLayer, tfLiteNode, delegateData); } TfLiteStatus VisitQuantizeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteQuantizeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tfLiteQuantizeOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tfLiteQuantizeOperatorCode, nodeIndex); return kTfLiteError; } // Only affine per-layer quantization is supported. if (!IsAffineQuantization(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Only affine per-layer quantization is supported in operator #%d node #%d: ", tfLiteQuantizeOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("QUANTIZE", tfLiteContext, IsQuantizeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Quantize, nodeIndex); armnn::IConnectableLayer* quantizeLayer = delegateData.m_Network->AddQuantizeLayer(layerName.c_str()); quantizeLayer->SetBackendId(setBackend); ARMNN_ASSERT(quantizeLayer != nullptr); armnn::IOutputSlot& outputSlot = quantizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(quantizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(quantizeLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Redefine.hpp000066400000000000000000000376121446772241200210770ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitCastOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("CAST", tfLiteContext, IsCastSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitCastOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Cast layer auto layerName = GetLayerName(armnn::LayerType::Cast, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddCastLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitReshapeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs == 2) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); } else { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor0 = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor0, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ReshapeDescriptor reshapeDesc; std::vector targetShape; TfLiteReshapeParams* reshapeOptions = reinterpret_cast(tfLiteNode->builtin_data); // The new shape can be defined by either a second input tensor or by a builtin option, we need to check for both. // Options might be set without valid data. we need to check the dimensions are in a valid range. if (reshapeOptions && reshapeOptions->num_dimensions > 0 && reshapeOptions->num_dimensions <= 8) { for (int i=0; i < reshapeOptions->num_dimensions; ++i) { targetShape.push_back(reshapeOptions->shape[i]); } } else if (numInputs == 2) { // Get shape from the second input tensor const TfLiteTensor& tfLiteShapeInputTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteShapeInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } if (tfLiteShapeInputTensor.dims->size != 1) { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Target 'shape' input is not a 1D tensor in " "operator #%d node #%d: Falling back to TfLiteOptions.", operatorCode, nodeIndex); } else { // Get the shape data out of the input tensor auto* shapeTensorDataPtr = tflite::GetTensorData(&tfLiteShapeInputTensor); auto shapeTensorNumValues = tfLiteShapeInputTensor.dims->data[0]; for (auto i=0; i < shapeTensorNumValues; ++i) { targetShape.push_back(*(shapeTensorDataPtr+i)); } } } else { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "Target shape not defined in reshape parameters or input tensor. " "At least one method required in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } // Use the data to create the required tensor shape. if (CreateOutputTensorShape(inputTensorInfo0, targetShape, reshapeDesc) != kTfLiteOk) { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: At most one component of shape can be -1 in: " "operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } if (reshapeDesc.m_TargetShape.GetNumElements() != inputTensorInfo0.GetNumElements()) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Reshape, number of elements in output shape does not match input " "operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Reshape, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitSqueezeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } auto* options = reinterpret_cast(tfLiteNode->builtin_data); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); std::vector squeezeDim; // A single negative dim index is interpreted as a negative index in python // Meaning the index will be the shape size plus the negative index value if (options->num_squeeze_dims == 1 && options->squeeze_dims[0] < 0) { int32_t dim = static_cast(inputTensorInfo.GetShape().GetNumDimensions()) + options->squeeze_dims[0]; squeezeDim.push_back(static_cast(dim)); } else { for (int32_t i = 0; i < options->num_squeeze_dims; ++i) { squeezeDim.push_back(static_cast(options->squeeze_dims[i])); } } armnn::TensorInfo outputTensorInfo = OutputShapeOfSqueeze(squeezeDim, inputTensorInfo); armnn::ReshapeDescriptor reshapeDesc; reshapeDesc.m_TargetShape = outputTensorInfo.GetShape(); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SQUEEZE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Reshape, nodeIndex, "Squeeze"); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitExpandDimsOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteAxisTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); armnn::TensorInfo outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); auto* axisTensorData = tflite::GetTensorData(&tfLiteAxisTensor); int32_t axis = axisTensorData[0]; int32_t inputDimSize = static_cast(inputTensorInfo.GetShape().GetNumDimensions()); if (axis > inputDimSize || axis < 0 - (inputDimSize + 1)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Axis must be in range " "[0 - (inputDimSize + 1), inputDimSize] inclusive."); return kTfLiteError; } if(axis < 0) { axis = inputDimSize + axis + 1; } std::vector shape(static_cast(inputDimSize) + 1); unsigned int inputShapeIndex = 0; for (unsigned int i = 0; i < static_cast(inputDimSize + 1); ++i) { if (i == static_cast(axis)) { shape[i] = 1; } else { shape[i] = inputTensorInfo.GetShape()[inputShapeIndex]; ++inputShapeIndex; } } armnn::ReshapeDescriptor reshapeDesc; reshapeDesc.m_TargetShape = armnn::TensorShape(static_cast(inputDimSize + 1), shape.data()); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("EXPAND_DIMS", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Reshape, nodeIndex, "ExpandDims"); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputTensorInfo.SetShape(reshapeDesc.m_TargetShape); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Reduce.hpp000066400000000000000000000122471446772241200205620ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitReduceOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t reduceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteAxisTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAxisTensor); auto* axisTensorData = tflite::GetTensorData(&tfLiteAxisTensor); std::vector axis; // Add axis data to vector to be converter to unsigned int and assigned to descriptor axis. if (axisTensorData != nullptr) { for (unsigned int i = 0; i < axisTensorInfo.GetNumElements(); ++i) { axis.emplace_back(axisTensorData[i]); } } else { for (unsigned int i = 0; i < inputTensorInfo.GetNumDimensions(); ++i) { axis.push_back(i); } } // Convert the axis to unsigned int and remove duplicates. unsigned int rank = inputTensorInfo.GetNumDimensions(); std::set uniqueAxis; std::transform(axis.begin(), axis.end(), std::inserter(uniqueAxis, uniqueAxis.begin()), [rank](int i)->unsigned int{ return (i + rank) % rank; }); armnn::ReduceDescriptor desc; desc.m_vAxis.assign(uniqueAxis.begin(), uniqueAxis.end()); auto* reducerParameters = reinterpret_cast(tfLiteNode->builtin_data); desc.m_KeepDims = reducerParameters->keep_dims; if (reduceOperatorCode == kTfLiteBuiltinReduceMax) { desc.m_ReduceOperation = armnn::ReduceOperation::Max; } else if (reduceOperatorCode == kTfLiteBuiltinReduceMin) { desc.m_ReduceOperation = armnn::ReduceOperation::Min; } else if (reduceOperatorCode == kTfLiteBuiltinSum) { desc.m_ReduceOperation = armnn::ReduceOperation::Sum; } else if (reduceOperatorCode == kTfLiteBuiltinReduceProd) { desc.m_ReduceOperation = armnn::ReduceOperation::Prod; } else { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Unsupported Reduction Operator #%d node #%d: ", reduceOperatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("REDUCE", tfLiteContext, IsReduceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Reduce layer auto layerName = GetLayerName(armnn::LayerType::Reduce, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReduceLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Resize.hpp000066400000000000000000000177721446772241200206240ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateResizeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, const armnn::ResizeDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("RESIZE", tfLiteContext, IsResizeSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitResizeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t resizeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; // The first input contains the data of the image that should be resized [batch, height, width, channels] const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // The second input contains a size tensor. The size tensor contains two integer values // that describe the new height and width of the image [new_height, new_width] const TfLiteTensor& tfLiteSizeTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteSizeTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // The output tensor should have the shape [batch, new_height, new_width, channels] const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::string layerName("Resize"); // Fill descriptor armnn::ResizeDescriptor desc; switch (resizeOperatorCode) { case kTfLiteBuiltinResizeBilinear: { desc.m_Method = armnn::ResizeMethod::Bilinear; layerName += "Bilinear:" + std::to_string(nodeIndex); TfLiteResizeBilinearParams* biliniarOptions = reinterpret_cast(tfLiteNode->builtin_data); desc.m_AlignCorners = biliniarOptions->align_corners; desc.m_HalfPixelCenters = biliniarOptions->half_pixel_centers; break; } case kTfLiteBuiltinResizeNearestNeighbor: { desc.m_Method = armnn::ResizeMethod::NearestNeighbor; layerName += "NearestNeighbor:" + std::to_string(nodeIndex); TfLiteResizeNearestNeighborParams* nearestNeighborOptions = reinterpret_cast(tfLiteNode->builtin_data); desc.m_AlignCorners = nearestNeighborOptions->align_corners; desc.m_HalfPixelCenters = nearestNeighborOptions->half_pixel_centers; break; } default: { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Unknown TfLite built in operation for Resize. Given operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } } // In armnn the values of the size input tensor [new_hight, new_width] is saved in the operator // descriptor. We have to read it from the input tensor and write it to the descriptor. auto* sizeTensorDataPtr = tflite::GetTensorData(&tfLiteSizeTensor); auto sizeTensorNumDimensions = tfLiteSizeTensor.dims->size; // The size tensor is only a 1D tensor -> [new_hight, new width] if (sizeTensorNumDimensions != 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Size-Input-Tensor of the Resize operation is not allowed to be a " "dynamic tensor. Operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // Get number of values in the size tensor auto sizeTensorNumValues = tfLiteSizeTensor.dims->data[0]; if (sizeTensorNumValues == 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Size-Input-Tensor of the Resize operation is not allowed to be a " "dynamic tensor. Operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } else if (sizeTensorNumValues != 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Size-Input-Tensor of the Resize operation requires to " "have a dimension of 2 [new_hight, new width] but a tensor with a dimension of #%d was given. " "Operator: #%d node #%d: ", sizeTensorNumValues, resizeOperatorCode, nodeIndex); return kTfLiteError; } // get size tensor data std::vector sizeTensorData(sizeTensorDataPtr, sizeTensorDataPtr+sizeTensorNumValues); desc.m_TargetHeight = static_cast (sizeTensorData[0]); desc.m_TargetWidth = static_cast (sizeTensorData[1]); desc.m_DataLayout = armnn::DataLayout::NHWC; // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateResizeOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, desc); } auto resizeName = GetLayerName(armnn::LayerType::Resize, nodeIndex); armnn::IConnectableLayer* resizeLayer = delegateData.m_Network->AddResizeLayer(desc, resizeName.c_str()); armnn::IOutputSlot& outputSlot = resizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(resizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } ARMNN_ASSERT(resizeLayer != nullptr); return Connect(resizeLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/ReverseV2.hpp000066400000000000000000000134501446772241200211730ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateReverseV2Operator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo0, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& outputInfo) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("REVERSEV2", tfLiteContext, IsReverseV2Supported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo0, inputInfo1, outputInfo); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitReverseV2Operator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t reverseV2OperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; // The first input contains the data that should be reversed const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // The second input contains an axis tensor. const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteAxisTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // Get the output tensor const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteAxisTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (inputTensorInfo0.GetNumDimensions() != outputTensorInfo.GetNumDimensions()) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: input tensor dimension and output tensor dimension differ #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } for (unsigned i=0; i < inputTensorInfo0.GetNumDimensions(); i++) { if (inputTensorInfo0.GetShape()[i] != outputTensorInfo.GetShape()[i]) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: input tensor dimension and output tensor differ #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } } const auto maxDimension = 4; const auto axisTensorNumValues = static_cast(tfLiteAxisTensor.dims->size); if (axisTensorNumValues > maxDimension) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Axis-Input-Tensor of the ReverseV2 operation requires a " "dimension of <= %d but a tensor with a dimension of %d was given. " "Operator: #%d node #%d: ", maxDimension, axisTensorNumValues, reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateReverseV2Operator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); } auto layerName = GetLayerName(armnn::LayerType::ReverseV2, nodeIndex); armnn::IConnectableLayer* reverseV2Layer = delegateData.m_Network->AddReverseV2Layer(layerName.c_str()); armnn::IOutputSlot& outputSlot = reverseV2Layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Try to connect the Constant Inputs if there are any if (ProcessInputs(reverseV2Layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } ARMNN_ASSERT(reverseV2Layer != nullptr); return Connect(reverseV2Layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Round.hpp000066400000000000000000000053311446772241200204360ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "SharedFunctions.hpp" #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitFloorOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); // NOTE: looks like the outputTensorInfo is the only thing that is required for the case // where we are adding the floor layer so maybe move the other stuff inside the // if !delegateData block for efficiency. const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitFloorOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { return ValidateFloorOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo); } // Add a Floor layer auto layerName = GetLayerName(armnn::LayerType::Floor, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFloorLayer(layerName.c_str()); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Shape.hpp000066400000000000000000000070111446772241200204040ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitShapeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* shapeParameters = reinterpret_cast(tfLiteNode->builtin_data); if (shapeParameters->out_type != kTfLiteInt32 && shapeParameters->out_type != kTfLiteInt64) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: output_type data type is not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SHAPE", tfLiteContext, IsShapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitShapeOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Shape layer auto layerName = GetLayerName(armnn::LayerType::Shape, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddShapeLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/SharedFunctions.cpp000066400000000000000000000073331446772241200224450ustar00rootroot00000000000000// // Copyright © 2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SharedFunctions.hpp" #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateFloorOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputTensorInfo, const armnn::TensorInfo& outputTensorInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("FLOOR", tfLiteContext, IsFloorSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputTensorInfo, outInfo); }; validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateFusedActivationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, TfLiteFusedActivation activationType) { armnn::ActivationDescriptor activationDesc; switch (activationType) { case kTfLiteActNone: { // No Activation return kTfLiteOk; } case kTfLiteActRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } // The name of kTfLiteActRelu1 changed after TF Lite v2.3 #if defined(ARMNN_POST_TFLITE_2_3) case kTfLiteActReluN1To1: #else case kTfLiteActRelu1: #endif { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 1.0f; activationDesc.m_B = -1.0f; break; } case kTfLiteActRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; activationDesc.m_B = 0.0f; break; } case kTfLiteActSigmoid: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteActTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } default: return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("ACTIVATION", tfLiteContext, IsActivationSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, activationDesc); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/SharedFunctions.hpp000066400000000000000000000016001446772241200224410ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnDelegate { TfLiteStatus ValidateFloorOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputTensorInfo, const armnn::TensorInfo& outputTensorInfo); TfLiteStatus ValidateFusedActivationOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, TfLiteFusedActivation activationType); } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Slice.hpp000066400000000000000000000145131446772241200204100ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitSliceOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t sliceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Read inputs [input, begin, size] int numInputs = tfLiteNode->inputs->size; std::vector tfLiteInputs; tfLiteInputs.reserve(numInputs); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; for (int i = 0; i < numInputs; i++) { const TfLiteTensor* inputTensor = &tfLiteTensors[tfLiteNode->inputs->data[i]]; tfLiteInputs.push_back(inputTensor); if (!IsValid(tfLiteContext, *inputTensor, sliceOperatorCode, nodeIndex)) { return kTfLiteError; } } // We save the begin and size tensors in our descriptor. Therefore we have to read those values from inputs int inputRank = tfLiteInputs[0]->dims->size; auto ReadInt32Input = [&](int inputIndex, std::vector& outputData, const char* name) -> TfLiteStatus { if (tfLiteInputs[inputIndex]->type != kTfLiteInt32) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The %s Tensor of the Slice operation needs to " "be of type int32. Operator: #%d node #%d: ", name, sliceOperatorCode, nodeIndex); return kTfLiteError; } int rank = tfLiteInputs[inputIndex]->dims->size; if (rank != 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The %s Tensor of the Slice operation needs to " "be a 1D-Tensor. Operator: #%d node #%d: ", name, sliceOperatorCode, nodeIndex); return kTfLiteError; } int numValues = tfLiteInputs[inputIndex]->dims->data[0]; if (numValues != inputRank) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The number of values in the %s Tensor of the " "Slice operation needs to be equal to the rank of the Input Tensor. Operator: #%d node #%d: ", name, sliceOperatorCode, nodeIndex); return kTfLiteError; } // return tensor data auto* tensorDataPtr = tflite::GetTensorData(tfLiteInputs[inputIndex]); outputData.assign(tensorDataPtr, tensorDataPtr + numValues); return kTfLiteOk; }; std::vector signedBegin; if (ReadInt32Input(1, signedBegin, "Begin") != kTfLiteOk) { return kTfLiteError; } std::vector signedSize; if (ReadInt32Input(2, signedSize, "Size") != kTfLiteOk) { return kTfLiteError; } std::vector begin({ signedBegin.begin(), signedBegin.end() }); std::vector size(signedSize.size()); for (unsigned int i = 0; i < signedSize.size(); ++i) { int signedValue = signedSize[i]; if (signedValue < -1 || signedValue > tfLiteInputs[0]->dims->data[i] - signedBegin[i]) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid value for Size. Size must be in range [-1, inputDimSize - begin] " "[-1, %d] inclusive but was %d Operator: #%d node #%d: ", tfLiteInputs[0]->dims->data[i] - signedBegin[i], signedValue, sliceOperatorCode, nodeIndex); return kTfLiteError; } if (signedValue == -1) { size[i] = tfLiteInputs[0]->dims->data[i] - signedBegin[i]; } else { size[i] = static_cast(signedValue); } } // Write all data to the descriptor armnn::SliceDescriptor descriptor(begin, size); // Validate output const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, sliceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(*tfLiteInputs[0]); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SLICE", tfLiteContext, IsSliceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Slice layer auto layerName = GetLayerName(armnn::LayerType::Slice, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSliceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Softmax.hpp000066400000000000000000000136621446772241200207760ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateSoftmaxOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputTensorInfo, const armnn::SoftmaxDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("SOFTMAX", tfLiteContext, IsSoftmaxSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateLogSoftmaxOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputTensorInfo, const armnn::LogSoftmaxDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("LOG_SOFTMAX", tfLiteContext, IsLogSoftmaxSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitSoftmaxOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t softmaxOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in node #%d: ", nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { switch(softmaxOperatorCode) { case kTfLiteBuiltinSoftmax: { armnn::SoftmaxDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_Beta = params->beta; return ValidateSoftmaxOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, descriptor); } case kTfLiteBuiltinLogSoftmax: { armnn::LogSoftmaxDescriptor descriptor; return ValidateLogSoftmaxOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, descriptor); } default: return kTfLiteError; } } auto layerName = GetLayerName(armnn::LayerType::Softmax, nodeIndex); armnn::IConnectableLayer* softmaxLayer = nullptr; switch(softmaxOperatorCode) { case kTfLiteBuiltinSoftmax: { armnn::SoftmaxDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_Beta = params->beta; softmaxLayer = delegateData.m_Network->AddSoftmaxLayer(descriptor, layerName.c_str()); break; } case kTfLiteBuiltinLogSoftmax: { armnn::LogSoftmaxDescriptor descriptor; softmaxLayer = delegateData.m_Network->AddLogSoftmaxLayer(descriptor, layerName.c_str()); break; } default: return kTfLiteError; } ARMNN_ASSERT(softmaxLayer != nullptr); armnn::IOutputSlot& outputSlot = softmaxLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(softmaxLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(softmaxLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/SpaceDepth.hpp000066400000000000000000000135321446772241200213710ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitSpaceToDepthOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::SpaceToDepthDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_BlockSize = params->block_size; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("SPACE_TO_DEPTH", tfLiteContext, IsSpaceToDepthSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a SpaceToDepth layer auto layerName = GetLayerName(armnn::LayerType::SpaceToDepth, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSpaceToDepthLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(layer, tfLiteNode, delegateData); } TfLiteStatus VisitDepthToSpaceOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::DepthToSpaceDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); descriptor.m_BlockSize = params->block_size; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("DEPTH_TO_SPACE", tfLiteContext, IsDepthToSpaceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a DepthToSpace layer auto layerName = GetLayerName(armnn::LayerType::DepthToSpace, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddDepthToSpaceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Split.hpp000066400000000000000000000321321446772241200204410ustar00rootroot00000000000000// // Copyright © 2020,2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { constexpr unsigned int MaxNumOfTensorDimensions = 5U; TfLiteStatus VisitSplitOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteSplitOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); auto* splitParameters = reinterpret_cast(tfLiteNode->builtin_data); const unsigned int numSplits = NonNegative(splitParameters->num_splits, nodeIndex); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, numSplits, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteAxisTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); if (GetTensorInfoForTfLiteTensor(tfLiteAxisTensor).GetNumElements() != 1) { return kTfLiteError; } auto* axisTensorDataPtr = tflite::GetTensorData(&tfLiteAxisTensor); std::vector axisTensorData(axisTensorDataPtr, axisTensorDataPtr + 1); int32_t axis = axisTensorData[0]; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { // Square bracket denotes inclusive n while parenthesis denotes exclusive n // E.g. Rank 4 tensor can have axis in range [-4, 3) // -1 == 3, -2 == 2, -3 == 1, -4 == 0 TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Operation has invalid axis: #%d. Axis must be in range [-n, n) in node #%d:", axis, nodeIndex); } const unsigned int splitDim = ComputeWrappedIndex(axis, inputTensorInfo.GetNumDimensions()); std::vector outputs; for (unsigned int i = 0; i < numSplits; ++i) { const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[i]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); auto inputDimSize = inputTensorInfo.GetNumDimensions(); if (inputDimSize > MaxNumOfTensorDimensions) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The number of dimensions: #%d for input tensors of the split op cannot be greater " "than #%d in node #%d: ", inputDimSize, MaxNumOfTensorDimensions, nodeIndex); return kTfLiteError; } std::vector splitterDimSizes(inputDimSize); // Add current input shape to splitterDimSizes for (unsigned int i = 0; i < inputDimSize; ++i) { splitterDimSizes[i] = inputTensorInfo.GetShape()[i]; } if (splitterDimSizes[splitDim] % numSplits != 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Number of splits #%d must evenly divide the dimension #%d in node #%d: ", numSplits, splitterDimSizes[splitDim], nodeIndex); return kTfLiteError; } splitterDimSizes[splitDim] /= numSplits; armnn::SplitterDescriptor splitDescriptor(numSplits, inputDimSize); for (unsigned int j = 0; j < numSplits; ++j) { // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < splitterDimSizes.size(); ++dimIdx) { splitDescriptor.SetViewSize(j, dimIdx, splitterDimSizes[dimIdx]); } splitDescriptor.SetViewOriginCoord(j, splitDim, splitterDimSizes[splitDim] * j); } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("SPLIT", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfos, splitDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Splitter, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSplitterLayer(splitDescriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); for (unsigned int k = 0; k < layer->GetNumOutputSlots(); ++k) { layer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // Connect the input slots delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[1]]->Connect(layer->GetInputSlot(0)); // Prepare output slots for (unsigned int outputIndex = 0; outputIndex < layer->GetNumOutputSlots(); ++outputIndex) { armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(outputIndex); delegateData.m_OutputSlotForNode[ static_cast(tfLiteNode->outputs->data[outputIndex])] = &outputSlot; } return kTfLiteOk; } TfLiteStatus VisitSplitVOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfLiteSplitVOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteSplitsTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (!IsValid(tfLiteContext, tfLiteSplitsTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[2]]; if (!IsValid(tfLiteContext, tfLiteAxisTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& splitsTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteSplitsTensor); if (splitsTensorInfo.GetNumDimensions() != 1) { return kTfLiteError; } if (GetTensorInfoForTfLiteTensor(tfLiteAxisTensor).GetNumElements() != 1) { return kTfLiteError; } auto* axisTensorDataPtr = tflite::GetTensorData(&tfLiteAxisTensor); std::vector axisTensorData(axisTensorDataPtr, axisTensorDataPtr + 1); int32_t axis = axisTensorData[0]; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Operation has invalid axis: #%d. Axis must be in range [-n, n) in node #%d:", axis, nodeIndex); } const unsigned int splitDim = ComputeWrappedIndex(axisTensorData[0], inputTensorInfo.GetNumDimensions()); auto* splitVParameters = reinterpret_cast(tfLiteNode->builtin_data); unsigned int numSplits = 0; if (splitVParameters) { numSplits = NonNegative(splitVParameters->num_splits, nodeIndex); } else { numSplits = splitsTensorInfo.GetNumElements(); } if (numSplits <= 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid number of splits %d in node #%d", numSplits, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, numSplits, nodeIndex)); std::vector outputs; for (unsigned int i = 0; i < numSplits; ++i) { const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[i]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); auto inputDimSize = inputTensorInfo.GetNumDimensions(); if (inputDimSize > MaxNumOfTensorDimensions) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The number of dimensions: #%d for input tensors of the split op cannot be greater " "than #%d in node #%d: ", inputDimSize, MaxNumOfTensorDimensions, nodeIndex); return kTfLiteError; } std::vector splitsTensorData(numSplits); std::memcpy(splitsTensorData.data(), tfLiteSplitsTensor.data.data, splitsTensorInfo.GetNumBytes()); unsigned int index = 0; unsigned int inferredIndex = 0; int numberOfInferred = 0; int splitSum = 0; for (auto splitData : splitsTensorData) { if (splitData < 0) { ++numberOfInferred; inferredIndex = index; } else { splitSum += splitData; } ++index; } // Check for inferred axis if (numberOfInferred == 0) { if (splitSum != armnn::numeric_cast(inputTensorInfo.GetShape()[splitDim])) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: SplitV split_sizes does not sum to the dimension of value along" " split_dim in node #%d", nodeIndex); return kTfLiteError; } } else if (numberOfInferred == 1) { splitsTensorData[inferredIndex] = armnn::numeric_cast(inputTensorInfo.GetShape()[splitDim]) - splitSum; } else { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: SplitV cannot infer split size for more than one split in node #%d", nodeIndex); return kTfLiteError; } armnn::SplitterDescriptor splitDescriptor(numSplits, inputDimSize); unsigned int accumSplit = 0; for (unsigned int j = 0; j < numSplits; ++j) { unsigned int splitSize = armnn::numeric_cast(splitsTensorData[j]); // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < inputTensorInfo.GetNumDimensions(); ++dimIdx) { unsigned int dimSize = inputTensorInfo.GetShape()[dimIdx]; if (dimIdx == splitDim) { dimSize = splitSize; } splitDescriptor.SetViewSize(j, dimIdx, dimSize); } splitDescriptor.SetViewOriginCoord(j, splitDim, accumSplit); accumSplit += splitSize; } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("SPLIT", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfos, splitDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } armnn::IConnectableLayer* layer = delegateData.m_Network->AddSplitterLayer(splitDescriptor); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); for (unsigned int k = 0; k < layer->GetNumOutputSlots(); ++k) { layer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/StridedSlice.hpp000066400000000000000000000142211446772241200217230ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitStridedSliceOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t sliceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 4, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Read inputs [input, begin, end, strides] int numInputs = tfLiteNode->inputs->size; std::vector tfLiteInputs; tfLiteInputs.reserve(numInputs); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; for (int i = 0; i < numInputs; i++) { const TfLiteTensor* inputTensor = &tfLiteTensors[tfLiteNode->inputs->data[i]]; tfLiteInputs.push_back(inputTensor); if (!IsValid(tfLiteContext, *inputTensor, sliceOperatorCode, nodeIndex)) { return kTfLiteError; } } // We save the begin, end and strides tensors in our descriptor. Therefore we have to read those values from inputs int inputRank = tfLiteInputs[0]->dims->size; auto ReadInt32Input = [&](int inputIndex, std::vector& outputData) -> TfLiteStatus { if (tfLiteInputs[inputIndex]->type != kTfLiteInt32) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Begin-, End- and Stride-Tensors of the StridedSlice operation need to " "be of type int32. Operator: #%d node #%d: ", sliceOperatorCode, nodeIndex); return kTfLiteError; } int rank = tfLiteInputs[inputIndex]->dims->size; if (rank != 1) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Begin-, End- and Stride-Tensors of the StridedSlice operation need to " "be a 1D-Tensor. Operator: #%d node #%d: ", sliceOperatorCode, nodeIndex); return kTfLiteError; } int numValues = tfLiteInputs[inputIndex]->dims->data[0]; if (numValues != inputRank) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The number of values in the Begin-, End- and Stride-Tensors of the " "StridedSlice operation need to be equal to the rank of the Input-Tensor. Operator: #%d node #%d: ", sliceOperatorCode, nodeIndex); return kTfLiteError; } // return tensor data auto* tensorDataPtr = tflite::GetTensorData(tfLiteInputs[inputIndex]); outputData.assign(tensorDataPtr, tensorDataPtr+numValues); return kTfLiteOk; }; std::vector beginData; if (ReadInt32Input(1, beginData) != kTfLiteOk) return kTfLiteError; std::vector endData; if (ReadInt32Input(2, endData) != kTfLiteOk) return kTfLiteError; std::vector strideData; if (ReadInt32Input(3, strideData) != kTfLiteOk) return kTfLiteError; // parse built in options auto* stridedSliceParams = reinterpret_cast(tfLiteNode->builtin_data); // Write all data to the descriptor armnn::StridedSliceDescriptor descriptor; descriptor.m_Begin = std::move(beginData); descriptor.m_End = std::move(endData); descriptor.m_Stride = std::move(strideData); descriptor.m_BeginMask = stridedSliceParams->begin_mask; descriptor.m_EllipsisMask = stridedSliceParams->ellipsis_mask; descriptor.m_EndMask = stridedSliceParams->end_mask; descriptor.m_NewAxisMask = stridedSliceParams->new_axis_mask; descriptor.m_ShrinkAxisMask = stridedSliceParams->shrink_axis_mask; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Validate output const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, sliceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(*tfLiteInputs[0]); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("STRIDED_SLICE", tfLiteContext, IsStridedSliceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a StridedSlice layer auto layerName = GetLayerName(armnn::LayerType::StridedSlice, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddStridedSliceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/Tile.hpp000066400000000000000000000147611446772241200202530ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus ValidateTileOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, const armnn::TileDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("TILE", tfLiteContext, IsTileSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitTileOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tileOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; // The input contains the data that should be tiled const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // The multiples tensor contains the number of copies for each axis const TfLiteTensor& tfLiteMultiplesTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteMultiplesTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // The output tensor const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& multiplesTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteMultiplesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); // Multiples length must be the same as the number of dimension in input tensor if (multiplesTensorInfo.GetNumElements() != inputTensorInfo.GetNumDimensions()) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Multiples length must be the same as the number of dimension in input tensor", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // Get the Multiples data: In armnn, the values of the multiples input tensor is saved in the operator descriptor // We have to read it from the input tensor and write it the descriptor auto* multiplesTensorDataPtr = tflite::GetTensorData(&tfLiteMultiplesTensor); auto multiplesTensorNum = tfLiteMultiplesTensor.dims->data[0]; std::vector multiplesIntData(multiplesTensorDataPtr, multiplesTensorDataPtr + multiplesTensorNum); // The multiples must be positive for (auto multiple : multiplesIntData) { if (multiple < 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The Multiples must be positive values", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } } // The original input from TFLite is int32, and we have to make it as uint32 for our descriptor std::vector multiplesUintData; std::transform(multiplesIntData.begin(), multiplesIntData.end(), std::back_inserter(multiplesUintData), [] (const int value) { return static_cast(value); }); armnn::TileDescriptor tileDescriptor; tileDescriptor.m_Multiples = multiplesUintData; // Check output dimensions if (inputTensorInfo.GetNumDimensions() != outputTensorInfo.GetNumDimensions()) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Input tensor dimension and output tensor dimension differ", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateTileOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, tileDescriptor); } auto layerName = GetLayerName(armnn::LayerType::Tile, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddTileLayer(tileDescriptor, layerName.c_str()); if (layer == nullptr) { return kTfLiteError; } layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(layer, tfLiteNode, delegateData); } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/Transpose.hpp000066400000000000000000000112341446772241200213240ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitTransposeOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t tfliteTransposeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor *tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor0 = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (IsDynamicTensor(tfLiteInputTensor0)) { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in " "operator #%d node #%d: ", tfliteTransposeOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteInputTensor1 = tfLiteTensors[tfLiteNode->inputs->data[1]]; if (IsDynamicTensor(tfLiteInputTensor1)) { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Dynamic input tensors are not supported in " "operator #%d node #%d: ", tfliteTransposeOperatorCode, nodeIndex); return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_MAYBE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Dynamic output tensors are not supported in " "operator #%d node #%d: ", tfliteTransposeOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* permTensorDataPtr = tflite::GetTensorData(&tfLiteInputTensor1); unsigned int numEl = tfLiteInputTensor1.dims->data[0]; if (numEl > static_cast(armnn::MaxNumOfTensorDimensions)) { return kTfLiteError; } if (tfLiteInputTensor1.dims->size != 1) { return kTfLiteError; } armnn::TransposeDescriptor descriptor(armnn::PermutationVector( reinterpret_cast (permTensorDataPtr), static_cast(numEl))); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("TRANSPOSE", tfLiteContext, IsTransposeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::Transpose, nodeIndex); armnn::IConnectableLayer* transposeLayer = delegateData.m_Network->AddTransposeLayer(descriptor, layerName.c_str()); transposeLayer->SetBackendId(setBackend); ARMNN_ASSERT(transposeLayer != nullptr); // permutation vector given to descriptor object if (transposeLayer->GetNumInputSlots() != 1) { return kTfLiteError; } armnn::IOutputSlot& outputSlot = transposeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(transposeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(transposeLayer, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/UnidirectionalSequenceLstm.hpp000066400000000000000000000334311446772241200246530ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitUnidirectionalSequenceLstmOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = tfLiteNode->inputs->size; if (numInputs < 2) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } const auto nodeParams = reinterpret_cast(tfLiteNode->builtin_data); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Set the params structure for the AddUnidirectionalSequenceLstmLayer call // Please refer to each operand at // https://www.tensorflow.org/mlir/tfl_ops#tflunidirectional_sequence_lstm_tflunidirectionalsequencelstmop armnn::LstmInputParams params; if (IsOptionalOperandPresent(tfLiteNode, 1)) { params.m_InputToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 1); } params.m_InputToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 2); params.m_InputToCellWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 3); params.m_InputToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 4); // Recurrent weight tensors of size {n_cell, n_output} if (IsOptionalOperandPresent(tfLiteNode, 5)) { params.m_RecurrentToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 5); } params.m_RecurrentToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 6); params.m_RecurrentToCellWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 7); params.m_RecurrentToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 8); // Peephole weights tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 9)) { params.m_CellToInputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 9); } if (IsOptionalOperandPresent(tfLiteNode, 10)) { params.m_CellToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 10); } if (IsOptionalOperandPresent(tfLiteNode, 11)) { params.m_CellToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 11); } // Gates bias tensors of size {n_cell} if (IsOptionalOperandPresent(tfLiteNode, 12)) { params.m_InputGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 12); } params.m_ForgetGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 13); params.m_CellBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 14); params.m_OutputGateBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 15); // Projection weight tensor of size {n_output, n_cell} if (IsOptionalOperandPresent(tfLiteNode, 16)) { params.m_ProjectionWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 16); } // Projection bias tensor of size {n_output} if (IsOptionalOperandPresent(tfLiteNode, 17)) { params.m_ProjectionBias = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 17); } // These state tensors are defined as variable tensors, and will be modified by this op. armnn::TensorInfo outputStateInInfo = GetTensorInfoForTfLiteTensor(tfLiteTensors[tfLiteNode->inputs->data[18]]); armnn::TensorInfo cellStateInInfo = GetTensorInfoForTfLiteTensor(tfLiteTensors[tfLiteNode->inputs->data[19]]); // Layer norm coefficient tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 20)) { params.m_InputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 20); } if (IsOptionalOperandPresent(tfLiteNode, 21)) { params.m_ForgetLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 21); } if (IsOptionalOperandPresent(tfLiteNode, 22)) { params.m_CellLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 22); } if (IsOptionalOperandPresent(tfLiteNode, 23)) { params.m_OutputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteTensors, tfLiteNode, 23); } // set the layer descriptor armnn::UnidirectionalSequenceLstmDescriptor desc; desc.m_ActivationFunc = NonNegative(nodeParams->activation, nodeIndex); desc.m_ClippingThresCell = nodeParams->cell_clip; desc.m_ClippingThresProj = nodeParams->proj_clip; desc.m_CifgEnabled = (params.m_InputToInputWeights == nullptr || params.m_RecurrentToInputWeights == nullptr || params.m_InputGateBias == nullptr); desc.m_PeepholeEnabled = (params.m_CellToForgetWeights != nullptr || params.m_CellToOutputWeights != nullptr); desc.m_ProjectionEnabled = (params.m_ProjectionWeights != nullptr); desc.m_LayerNormEnabled = (params.m_InputLayerNormWeights != nullptr || params.m_ForgetLayerNormWeights != nullptr || params.m_CellLayerNormWeights != nullptr || params.m_OutputLayerNormWeights != nullptr); desc.m_TimeMajor = nodeParams->time_major; if (tfLiteNode->intermediates->size > 3 && desc.m_LayerNormEnabled) { auto inputIntermediateTensorInfo = GetTensorInfoForTfLiteTensor( tfLiteTensors[tfLiteNode->intermediates->data[0]]); auto forgetIntermediateTensorInfo = GetTensorInfoForTfLiteTensor( tfLiteTensors[tfLiteNode->intermediates->data[1]]); auto cellIntermediateTensorInfo = GetTensorInfoForTfLiteTensor( tfLiteTensors[tfLiteNode->intermediates->data[2]]); auto outputIntermediateTensorInfo = GetTensorInfoForTfLiteTensor( tfLiteTensors[tfLiteNode->intermediates->data[3]]); desc.m_InputIntermediateScale = inputIntermediateTensorInfo.GetQuantizationScale(); desc.m_ForgetIntermediateScale = forgetIntermediateTensorInfo.GetQuantizationScale(); desc.m_CellIntermediateScale = cellIntermediateTensorInfo.GetQuantizationScale(); desc.m_OutputIntermediateScale = outputIntermediateTensorInfo.GetQuantizationScale(); } else { float defaultIntermediate = std::pow(2, -12); desc.m_InputIntermediateScale = defaultIntermediate; desc.m_ForgetIntermediateScale = defaultIntermediate; desc.m_CellIntermediateScale = defaultIntermediate; desc.m_OutputIntermediateScale = defaultIntermediate; } if (tfLiteNode->intermediates->size > 4) { auto hiddentensorInfo = GetTensorInfoForTfLiteTensor(tfLiteTensors[tfLiteNode->intermediates->data[4]]); desc.m_HiddenStateScale = hiddentensorInfo.GetQuantizationScale(); desc.m_HiddenStateZeroPoint = hiddentensorInfo.GetQuantizationOffset(); } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[2]; unsigned int numUnits = cellStateInInfo.GetShape()[1]; armnn::DataType dataType = inputTensorInfo.GetDataType(); float qScale = inputTensorInfo.GetQuantizationScale(); float qOffset = inputTensorInfo.GetQuantizationOffset(); armnn::TensorInfo scratchBufferTensorInfo({batchSize, numUnits * 3}, dataType, qScale, qOffset); if (!desc.m_CifgEnabled) { scratchBufferTensorInfo = armnn::TensorInfo({batchSize, numUnits * 4}, dataType, qScale, qOffset); } armnn::TensorInfo cellStateOutTensorInfo({batchSize, numUnits}, cellStateInInfo.GetDataType(), cellStateInInfo.GetQuantizationScale(), cellStateInInfo.GetQuantizationOffset()); armnn::TensorInfo outputStateOutTensorInfo({batchSize, outputSize}, dataType, qScale, qOffset); armnn::LstmInputParamsInfo paramsInfo; paramsInfo.m_InputToForgetWeights = &(params.m_InputToForgetWeights->GetInfo()); paramsInfo.m_InputToCellWeights = &(params.m_InputToCellWeights->GetInfo()); paramsInfo.m_InputToOutputWeights = &(params.m_InputToOutputWeights->GetInfo()); paramsInfo.m_RecurrentToForgetWeights = &(params.m_RecurrentToForgetWeights->GetInfo()); paramsInfo.m_RecurrentToCellWeights = &(params.m_RecurrentToCellWeights->GetInfo()); paramsInfo.m_RecurrentToOutputWeights = &(params.m_RecurrentToOutputWeights->GetInfo()); paramsInfo.m_ForgetGateBias = &(params.m_ForgetGateBias->GetInfo()); paramsInfo.m_CellBias = &(params.m_CellBias->GetInfo()); paramsInfo.m_OutputGateBias = &(params.m_OutputGateBias->GetInfo()); if (!desc.m_CifgEnabled) { paramsInfo.m_InputToInputWeights = &(params.m_InputToInputWeights->GetInfo()); paramsInfo.m_RecurrentToInputWeights = &(params.m_RecurrentToInputWeights->GetInfo()); if (params.m_CellToInputWeights != nullptr) { paramsInfo.m_CellToInputWeights = &(params.m_CellToInputWeights->GetInfo()); } paramsInfo.m_InputGateBias = &(params.m_InputGateBias->GetInfo()); } if (desc.m_ProjectionEnabled) { paramsInfo.m_ProjectionWeights = &(params.m_ProjectionWeights->GetInfo()); if (params.m_ProjectionBias != nullptr) { paramsInfo.m_ProjectionBias = &(params.m_ProjectionBias->GetInfo()); } } if (desc.m_PeepholeEnabled) { paramsInfo.m_CellToForgetWeights = &(params.m_CellToForgetWeights->GetInfo()); paramsInfo.m_CellToOutputWeights = &(params.m_CellToOutputWeights->GetInfo()); } if (desc.m_LayerNormEnabled) { if(!desc.m_CifgEnabled) { paramsInfo.m_InputLayerNormWeights = &(params.m_InputLayerNormWeights->GetInfo()); } paramsInfo.m_ForgetLayerNormWeights = &(params.m_ForgetLayerNormWeights->GetInfo()); paramsInfo.m_CellLayerNormWeights = &(params.m_CellLayerNormWeights->GetInfo()); paramsInfo.m_OutputLayerNormWeights = &(params.m_OutputLayerNormWeights->GetInfo()); } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_SUPPORT_FUNC("UNIDIRECTIONAL_SEQUENCE_LSTM", tfLiteContext, IsUnidirectionalSequenceLstmSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputStateInInfo, cellStateInInfo, outputStateOutTensorInfo, cellStateOutTensorInfo, outputInfo, desc, paramsInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetLayerName(armnn::LayerType::UnidirectionalSequenceLstm, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddUnidirectionalSequenceLstmLayer(desc, params, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputStateOutTensorInfo); layer->GetOutputSlot(1).SetTensorInfo(cellStateOutTensorInfo); layer->GetOutputSlot(2).SetTensorInfo(outputTensorInfo); // Connect the inputs // input_layer delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[0]]->Connect(layer->GetInputSlot(0)); // cellStateIn delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[18]]->Connect(layer->GetInputSlot(1)); //outputStateIn delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[19]]->Connect(layer->GetInputSlot(2)); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(2); delegateData.m_OutputSlotForNode[static_cast(tfLiteNode->outputs->data[0])] = &outputSlot; return kTfLiteOk; } } // namespace armnnDelegatearmnn-23.08/delegate/classic/src/Unpack.hpp000066400000000000000000000210441446772241200205670ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include namespace armnnDelegate { TfLiteStatus VisitUnpackOperator(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Get Unpack Axis const auto params = reinterpret_cast(tfLiteNode->builtin_data); const unsigned int unpackAxis = NonNegative(params->axis, nodeIndex); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); if (unpackAxis >= inputTensorInfo.GetNumDimensions()) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: The unpack axis #%d cannot be greater than or equal to " "the number of input dimensions #%d in operator #%d node #%d", unpackAxis, inputTensorInfo.GetNumDimensions(), operatorCode, nodeIndex); return kTfLiteError; } // Get Unpack Num unsigned int unpackNum = NonNegative(params->num, nodeIndex); // If num is not defined, automatically infer from the length of the dimension axis. if(unpackNum == 0) { unpackNum = inputTensorInfo.GetShape()[unpackAxis]; } // If unpack number cannot be inferred and is still zero, return kTfLiteError. if(unpackNum == 0) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Number to unpack must greater than zero in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } // Check outputs TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, unpackNum, nodeIndex)); auto inputDimSize = inputTensorInfo.GetNumDimensions(); std::vector unpackDimSizes(inputDimSize); // Add current input shape to unpackDimSizes for (unsigned int i = 0; i < inputDimSize; ++i) { unpackDimSizes[i] = inputTensorInfo.GetShape()[i]; } if (unpackDimSizes[unpackAxis] != unpackNum) { TF_LITE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Number to unpack must be the same as length " "of the dimension to unpack along in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } unpackDimSizes[unpackAxis] /= unpackNum; armnn::SplitterDescriptor splitDesc(unpackNum, static_cast(unpackDimSizes.size())); for (unsigned int j = 0; j < unpackNum; ++j) { // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < unpackDimSizes.size(); ++dimIdx) { splitDesc.SetViewSize(j, dimIdx, unpackDimSizes[dimIdx]); } splitDesc.SetViewOriginCoord(j, unpackAxis, unpackDimSizes[unpackAxis] * j); } std::vector outputs; for (unsigned int i = 0; i < unpackNum; ++i) { const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[i]]; if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); // Determine the shape of the Splitter layer outputs for validation armnn::TensorShape splitOutShape = armnn::TensorShape(static_cast(unpackDimSizes.size()), unpackDimSizes.data()); std::vector splitterOutputs; for (unsigned int outputIndex = 0; outputIndex < outputTensorInfos.size(); ++outputIndex) { splitterOutputs.push_back(armnn::TensorInfo(splitOutShape, outputTensorInfos[outputIndex].get().GetDataType(), outputTensorInfos[outputIndex].get().GetQuantizationScale(), outputTensorInfos[outputIndex].get().GetQuantizationOffset())); } std::vector> splitterOutputTensorInfos(splitterOutputs.begin(), splitterOutputs.end()); armnn::BackendId setBackendSplit; if (!delegateData.m_Network) { // Check if splitter is supported bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("UNPACK", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackendSplit, inputTensorInfo, splitterOutputTensorInfos, splitDesc); return isSupported ? kTfLiteOk : kTfLiteError; } // Create Reshape descriptor from the first outputTensorInfo to validate a single Reshape layer // Use this descriptor later when creating every ReshapeLayer as all Reshape Layers should be the same armnn::ReshapeDescriptor reshapeDescriptor; reshapeDescriptor.m_TargetShape = outputTensorInfos[0].get().GetShape(); armnn::BackendId setBackendReshape; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackendReshape, splitterOutputTensorInfos[0], outputTensorInfos[0], reshapeDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; }; auto layerName = GetLayerName(armnn::LayerType::Splitter, nodeIndex, "Unpack"); armnn::IConnectableLayer* splitterLayer = delegateData.m_Network->AddSplitterLayer(splitDesc, layerName.c_str()); splitterLayer->SetBackendId(setBackendSplit); ARMNN_ASSERT(splitterLayer != nullptr); for (unsigned int k = 0; k < splitterLayer->GetNumOutputSlots(); ++k) { splitterLayer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // Connect the input slots delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[0]]->Connect(splitterLayer->GetInputSlot(0)); // Create reshape to remove the unpacked dimension for unpack operator of each output from Splitter. for (unsigned int outputIndex = 0; outputIndex < splitterLayer->GetNumOutputSlots(); ++outputIndex) { auto reshapeName = GetLayerName(armnn::LayerType::Reshape, nodeIndex, "Unpack"); armnn::IConnectableLayer* reshapeLayer = delegateData.m_Network->AddReshapeLayer(reshapeDescriptor, reshapeName.c_str()); reshapeLayer->SetBackendId(setBackendReshape); ARMNN_ASSERT(reshapeLayer != nullptr); splitterLayer->GetOutputSlot(outputIndex).SetTensorInfo(splitterOutputTensorInfos[outputIndex]); splitterLayer->GetOutputSlot(outputIndex).Connect(reshapeLayer->GetInputSlot(0)); armnn::TensorInfo outputTensorInfo = outputTensorInfos[outputIndex]; reshapeLayer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); armnn::IOutputSlot& slot = reshapeLayer->GetOutputSlot(0); delegateData.m_OutputSlotForNode[ static_cast(tfLiteNode->outputs->data[outputIndex])] = &slot; } return kTfLiteOk; } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/armnn_delegate.cpp000066400000000000000000001435441446772241200223200ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include "Version.hpp" #include "Activation.hpp" #include "ArgMinMax.hpp" #include "BatchMatMul.hpp" #include "BatchSpace.hpp" #include "Comparison.hpp" #include "Convolution.hpp" #include "Control.hpp" #include "ElementwiseBinary.hpp" #include "ElementwiseUnary.hpp" #include "Fill.hpp" #include "FullyConnected.hpp" #include "Gather.hpp" #include "GatherNd.hpp" #include "LogicalBinary.hpp" #include "Lstm.hpp" #include "Normalization.hpp" #include "Pack.hpp" #include "Pad.hpp" #include "Pooling.hpp" #include "Prelu.hpp" #include "Quantization.hpp" #include "Redefine.hpp" #include "Reduce.hpp" #include "Resize.hpp" #include "ReverseV2.hpp" #include "Round.hpp" #include "Shape.hpp" #include "Slice.hpp" #include "StridedSlice.hpp" #include "Softmax.hpp" #include "SpaceDepth.hpp" #include "Split.hpp" #include "Tile.hpp" #include "Transpose.hpp" #include "UnidirectionalSequenceLstm.hpp" #include "Unpack.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { DelegateOptions TfLiteArmnnDelegateOptionsDefault() { DelegateOptions options(armnn::Compute::CpuRef); return options; } TfLiteDelegate* TfLiteArmnnDelegateCreate(armnnDelegate::DelegateOptions options) { auto* armnnDelegate = new ::armnnDelegate::Delegate(options); return armnnDelegate->GetDelegate(); } void TfLiteArmnnDelegateDelete(TfLiteDelegate* tfLiteDelegate) { if (tfLiteDelegate != nullptr) { delete static_cast<::armnnDelegate::Delegate*>(tfLiteDelegate->data_); } } TfLiteStatus DoPrepare(TfLiteContext* tfLiteContext, TfLiteDelegate* tfLiteDelegate) { TfLiteIntArray* supportedOperators = static_cast<::armnnDelegate::Delegate*>(tfLiteDelegate->data_)->IdentifyOperatorsToDelegate(tfLiteContext); // ArmNN Delegate Registration static const TfLiteRegistration kArmnnSubgraphRegistration = { // ArmnnSubgraph Init .init = [](TfLiteContext* tfLiteContext, const char* buffer, size_t length) -> void* { armnn::IgnoreUnused(length); const TfLiteDelegateParams* parameters = reinterpret_cast(buffer); return static_cast(ArmnnSubgraph::Create( tfLiteContext, parameters, static_cast<::armnnDelegate::Delegate*>(parameters->delegate->data_))); }, // ArmnnSubgraph Free .free = [](TfLiteContext* tfLiteContext, void* buffer) -> void { armnn::IgnoreUnused(tfLiteContext); if (buffer != nullptr) { delete static_cast(buffer); } }, // ArmnnSubgraph Prepare .prepare = [](TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode) -> TfLiteStatus { if (tfLiteNode->user_data == nullptr) { return kTfLiteError; } return static_cast(tfLiteNode->user_data)->Prepare(tfLiteContext); }, // ArmnnSubgraph Invoke .invoke = [](TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode) -> TfLiteStatus { if (tfLiteNode->user_data == nullptr) { return kTfLiteError; } return static_cast(tfLiteNode->user_data)->Invoke(tfLiteContext, tfLiteNode); }, .profiling_string = nullptr, .builtin_code = kTfLiteBuiltinDelegate, .custom_name = "TfLiteArmNnDelegate", .version = 1, .registration_external = nullptr, }; const TfLiteStatus status = tfLiteContext->ReplaceNodeSubsetsWithDelegateKernels( tfLiteContext, kArmnnSubgraphRegistration, supportedOperators, tfLiteDelegate); TfLiteIntArrayFree(supportedOperators); return status; } Delegate::Delegate(armnnDelegate::DelegateOptions options) : m_Options(std::move(options)) { // Configures logging for ARMNN if (m_Options.IsLoggingEnabled()) { armnn::ConfigureLogging(true, true, m_Options.GetLoggingSeverity()); } // Create/Get the static ArmNN Runtime. Note that the m_Runtime will be shared by all armnn_delegate // instances so the RuntimeOptions cannot be altered for different armnn_delegate instances. m_Runtime = GetRuntime(m_Options.GetRuntimeOptions()); std::vector backends; if (m_Runtime) { const armnn::BackendIdSet supportedDevices = m_Runtime->GetDeviceSpec().GetSupportedBackends(); for (auto& backend : m_Options.GetBackends()) { if (std::find(supportedDevices.cbegin(), supportedDevices.cend(), backend) == supportedDevices.cend()) { TFLITE_LOG_PROD(tflite::TFLITE_LOG_INFO, "TfLiteArmnnDelegate: Requested unknown backend %s", backend.Get().c_str()); } else { backends.push_back(backend); } } } if (backends.empty()) { // No known backend specified throw armnn::InvalidArgumentException("TfLiteArmnnDelegate: No known backend specified."); } m_Options.SetBackends(backends); TFLITE_LOG_PROD_ONCE(tflite::TFLITE_LOG_INFO, "TfLiteArmnnDelegate: Created TfLite ArmNN delegate."); } TfLiteIntArray* Delegate::IdentifyOperatorsToDelegate(TfLiteContext* tfLiteContext) { TfLiteIntArray* executionPlan = nullptr; if (tfLiteContext->GetExecutionPlan(tfLiteContext, &executionPlan) != kTfLiteOk) { TF_LITE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Unable to get graph execution plan."); return nullptr; } // Delegate data with null network DelegateData delegateData(m_Options.GetBackends()); TfLiteIntArray* nodesToDelegate = TfLiteIntArrayCreate(executionPlan->size); nodesToDelegate->size = 0; std::set unsupportedOperators; for (int i = 0; i < executionPlan->size; ++i) { const int nodeIndex = executionPlan->data[i]; // If TfLite nodes can be delegated to ArmNN TfLiteNode* tfLiteNode = nullptr; TfLiteRegistration* tfLiteRegistration = nullptr; if (tfLiteContext->GetNodeAndRegistration( tfLiteContext, nodeIndex, &tfLiteNode, &tfLiteRegistration) != kTfLiteOk) { TF_LITE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnDelegate: Unable to get node and registration for node %d.", nodeIndex); continue; } TfLiteStatus visitStatus; try { visitStatus = ArmnnSubgraph::VisitNode( delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex); } catch(std::exception& ex) { ARMNN_LOG(error) << "ArmNN Failed to visit node with error: " << ex.what(); visitStatus = kTfLiteError; } if ( visitStatus != kTfLiteOk) { // node is not supported by ArmNN unsupportedOperators.insert(tfLiteRegistration->builtin_code); continue; } nodesToDelegate->data[nodesToDelegate->size++] = nodeIndex; } for (std::set::iterator it=unsupportedOperators.begin(); it!=unsupportedOperators.end(); ++it) { TF_LITE_KERNEL_LOG(tfLiteContext, "Operator %s [%d] is not supported by armnn_delegate.", tflite::EnumNameBuiltinOperator(tflite::BuiltinOperator(*it)), *it); } if (!unsupportedOperators.empty() && m_Options.TfLiteRuntimeFallbackDisabled()) { std::stringstream exMessage; exMessage << "TfLiteArmnnDelegate: There are unsupported operators in the model. "; exMessage << "Not falling back to TfLite Runtime as fallback is disabled. "; exMessage << "This should only be disabled under test conditions."; throw armnn::Exception(exMessage.str()); } if (nodesToDelegate->size == 0) { ARMNN_LOG(info) << "No operators in this model are supported by the Arm NN TfLite delegate." << " The model will be executed entirely by TfLite runtime."; } std::sort(&nodesToDelegate->data[0], &nodesToDelegate->data[nodesToDelegate->size]); return nodesToDelegate; } TfLiteDelegate* Delegate::GetDelegate() { return &m_Delegate; } const std::string Delegate::GetVersion() { return DELEGATE_VERSION; } TfLiteStatus ArmnnSubgraph::AddInputLayer(DelegateData& delegateData, TfLiteContext* tfLiteContext, const TfLiteIntArray* inputs, std::vector& inputBindings) { const size_t numInputs = static_cast(inputs->size); for (unsigned int i = 0; i < numInputs; ++i) { const int32_t tensorId = inputs->data[i]; const TfLiteTensor tensor = tfLiteContext->tensors[tensorId]; // Do not create bindings for constant inputs if (tensor.allocation_type == kTfLiteMmapRo) { continue; } auto bindingId = static_cast((tensorId)); armnn::IConnectableLayer* layer = delegateData.m_Network->AddInputLayer(bindingId); auto tensorInfo = GetTensorInfoForTfLiteTensor(tensor); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(tensorInfo); // Store for creating connections delegateData.m_OutputSlotForNode[static_cast(tensorId)] = &outputSlot; inputBindings.push_back(std::make_pair(bindingId, tensorInfo)); } return kTfLiteOk; } TfLiteStatus ArmnnSubgraph::AddOutputLayer(DelegateData& delegateData, TfLiteContext* tfLiteContext, const TfLiteIntArray* outputs, std::vector& outputBindings) { const size_t numOutputs = static_cast(outputs->size); for (unsigned int i = 0; i < numOutputs; ++i) { const int32_t tensorId = outputs->data[i]; const TfLiteTensor tensor = tfLiteContext->tensors[tensorId]; auto bindingId = static_cast((tensorId)); armnn::IConnectableLayer* layer = delegateData.m_Network->AddOutputLayer(bindingId); auto tensorInfo = GetTensorInfoForTfLiteTensor(tensor); if (delegateData.m_OutputSlotForNode[static_cast(tensorId)] == nullptr) { return kTfLiteError; } delegateData.m_OutputSlotForNode[static_cast(tensorId)]->Connect(layer->GetInputSlot(0)); outputBindings.push_back(std::make_pair(bindingId, tensorInfo)); } return kTfLiteOk; } ArmnnSubgraph* ArmnnSubgraph::Create(TfLiteContext* tfLiteContext, const TfLiteDelegateParams* parameters, const Delegate* delegate) { const auto startTime = armnn::GetTimeNow(); ARMNN_LOG(info) << "ArmnnSubgraph creation"; TfLiteIntArray* executionPlan; if (tfLiteContext->GetExecutionPlan(tfLiteContext, &executionPlan) != kTfLiteOk) { return nullptr; } // Initialize DelegateData holds network and output slots information DelegateData delegateData(delegate->m_Options.GetBackends()); // Build ArmNN Network armnn::NetworkOptions networkOptions = delegate->m_Options.GetOptimizerOptions().GetModelOptions(); armnn::NetworkId networkId; delegateData.m_Network = armnn::INetwork::Create(networkOptions); delegateData.m_OutputSlotForNode = std::vector(tfLiteContext->tensors_size, nullptr); std::vector inputBindings; std::vector outputBindings; // Add input layer auto status = AddInputLayer(delegateData, tfLiteContext, parameters->input_tensors, inputBindings); if (status != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnDelegate: Unable to add Inputs to the network!"); } // Parse TfLite delegate nodes to ArmNN const auto parseStartTime = armnn::GetTimeNow(); for (int i = 0; i < parameters->nodes_to_replace->size; ++i) { const int nodeIndex = parameters->nodes_to_replace->data[i]; TfLiteNode* tfLiteNode = nullptr; TfLiteRegistration* tfLiteRegistration = nullptr; if (tfLiteContext->GetNodeAndRegistration( tfLiteContext, nodeIndex, &tfLiteNode, &tfLiteRegistration) != kTfLiteOk) { throw armnn::Exception(&"TfLiteArmnnDelegate: Unable to get node registration: " [ nodeIndex]); } if (VisitNode(delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex) != kTfLiteOk) { throw armnn::Exception(&"TfLiteArmnnDelegate: Unable to parse node: " [ nodeIndex]); } } ARMNN_LOG(info) << "Parse nodes to ArmNN time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(parseStartTime).count() << " ms"; // Add Output layer status = AddOutputLayer(delegateData, tfLiteContext, parameters->output_tensors, outputBindings); if (status != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnDelegate: Unable to add Outputs to the network!"); } // Optimize ArmNN network armnn::IOptimizedNetworkPtr optNet(nullptr, nullptr); try { const auto optimizeStartTime = armnn::GetTimeNow(); optNet = armnn::Optimize(*(delegateData.m_Network.get()), delegate->m_Options.GetBackends(), delegate->m_Runtime->GetDeviceSpec(), delegate->m_Options.GetOptimizerOptions()); ARMNN_LOG(info) << "Optimize ArmnnSubgraph time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(optimizeStartTime).count() << " ms"; } catch (std::exception& ex) { std::stringstream exMessage; exMessage << "TfLiteArmnnDelegate: Exception (" << ex.what() << ") caught from optimize."; throw armnn::Exception(exMessage.str()); } if (!optNet) { // Optimize failed throw armnn::Exception("TfLiteArmnnDelegate: Unable to optimize the network!"); } // If set, we will serialize the optimized model into a dot file. const std::string serializeToDotFile = delegate->m_Options.GetSerializeToDot(); if (!serializeToDotFile.empty()) { ARMNN_LOG(info) << "Writing graph to dot file: " << serializeToDotFile; fs::path filename = serializeToDotFile; std::fstream file(filename.c_str(), std::ios_base::out); optNet->SerializeToDot(file); } try { const auto loadStartTime = armnn::GetTimeNow(); // Load graph into runtime std::string errorMessage; armnn::Status loadingStatus; armnn::MemorySource inputSource = armnn::MemorySource::Undefined; armnn::MemorySource outputSource = armnn::MemorySource::Undefined; // There's a bit of an assumption here that the delegate will only support Malloc memory source. if (delegate->m_Options.GetOptimizerOptions().GetImportEnabled()) { inputSource = armnn::MemorySource::Malloc; } if (delegate->m_Options.GetOptimizerOptions().GetExportEnabled()) { outputSource = armnn::MemorySource::Malloc; } armnn::INetworkProperties networkProperties(false, inputSource, outputSource, delegate->m_Options.GetInternalProfilingState(), delegate->m_Options.GetInternalProfilingDetail()); loadingStatus = delegate->m_Runtime->LoadNetwork(networkId, std::move(optNet), errorMessage, networkProperties); if (loadingStatus != armnn::Status::Success) { // Network load failed. throw armnn::Exception("TfLiteArmnnDelegate: Network could not be loaded: " + errorMessage); } ARMNN_LOG(info) << "Load ArmnnSubgraph time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(loadStartTime).count() << " ms"; } catch (std::exception& ex) { std::stringstream exMessage; exMessage << "TfLiteArmnnDelegate: Exception (" << ex.what() << ") caught from LoadNetwork."; throw armnn::Exception(exMessage.str()); } // Register debug callback function if (delegate->m_Options.GetDebugCallbackFunction().has_value()) { delegate->m_Runtime->RegisterDebugCallback(networkId, delegate->m_Options.GetDebugCallbackFunction().value()); } ARMNN_LOG(info) << "Overall ArmnnSubgraph creation time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(startTime).count() << " ms\n"; // Create a new SubGraph with networkId and runtime return new ArmnnSubgraph(networkId, delegate->m_Runtime, inputBindings, outputBindings); } TfLiteStatus ArmnnSubgraph::Prepare(TfLiteContext* tfLiteContext) { armnn::IgnoreUnused(tfLiteContext); return kTfLiteOk; } TfLiteStatus ArmnnSubgraph::Invoke(TfLiteContext* tfLiteContext, TfLiteNode* tfLiteNode) { // Prepare inputs armnn::InputTensors inputTensors; size_t inputIndex = 0; for (auto inputIdx : tflite::TfLiteIntArrayView(tfLiteNode->inputs)) { TfLiteTensor* tensor = &tfLiteContext->tensors[inputIdx]; if (tensor->allocation_type != kTfLiteMmapRo) { const armnn::BindingPointInfo& inputBinding = m_InputBindings[inputIndex]; armnn::TensorInfo inputTensorInfo = inputBinding.second; inputTensorInfo.SetConstant(true); const armnn::ConstTensor inputTensor(inputTensorInfo, tensor->data.data); inputTensors.emplace_back(inputIdx, inputTensor); ++inputIndex; } } // Prepare outputs armnn::OutputTensors outputTensors; size_t outputIndex = 0; for (auto outputIdx : tflite::TfLiteIntArrayView(tfLiteNode->outputs)) { const armnn::BindingPointInfo& outputBinding = m_OutputBindings[outputIndex]; TfLiteTensor* tensor = &tfLiteContext->tensors[outputIdx]; const armnn::Tensor outputTensor(outputBinding.second, tensor->data.data); outputTensors.emplace_back(outputIdx, outputTensor); ++outputIndex; } // Run graph auto status = m_Runtime->EnqueueWorkload(m_NetworkId, inputTensors, outputTensors); // The delegate holds its own Arm NN runtime so this is our last chance to print internal profiling data. std::shared_ptr profiler = m_Runtime->GetProfiler(m_NetworkId); if (profiler && profiler->IsProfilingEnabled()) { profiler->Print(std::cout); } return (status == armnn::Status::Success) ? kTfLiteOk : kTfLiteError; } TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, TfLiteContext* tfLiteContext, TfLiteRegistration* tfLiteRegistration, TfLiteNode* tfLiteNode, int nodeIndex) { switch (tfLiteRegistration->builtin_code) { case kTfLiteBuiltinCustom: { #if defined(ARMNN_POST_TFLITE_2_5) // Custom operators are defined by the name rather than the builtin code. // Parse the custom_name param in the registration to point to the correct visitor function. std::string customOperatorName = tfLiteRegistration->custom_name; if ( customOperatorName == "AveragePool3D" ) { return VisitPooling3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, customOperatorName); } else if (customOperatorName == "MaxPool3D") { return VisitPooling3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, customOperatorName); } #endif // Invalid or unsupported custom operator return kTfLiteError; } case kTfLiteBuiltinAbs: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Abs); case kTfLiteBuiltinAdd: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinAdd); case kTfLiteBuiltinArgMax: return VisitArgMinMaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinArgMax); case kTfLiteBuiltinArgMin: return VisitArgMinMaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinArgMin); case kTfLiteBuiltinAveragePool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinAveragePool2d); case kTfLiteBuiltinBatchMatmul: return VisitBatchMatMulOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinBatchMatmul); case kTfLiteBuiltinBatchToSpaceNd: return VisitBatchToSpaceNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinBatchToSpaceNd); case kTfLiteBuiltinCast: return VisitCastOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinCast); case kTfLiteBuiltinCeil: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Ceil); case kTfLiteBuiltinConcatenation: return VisitControlOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConcatenation); case kTfLiteBuiltinConv2d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConv2d); // Conv3d is only correctly supported for external delegates from TF Lite v2.6, as there was a breaking bug in v2.5. #if defined(ARMNN_POST_TFLITE_2_5) case kTfLiteBuiltinConv3d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConv3d); #endif case kTfLiteBuiltinDepthToSpace: return VisitDepthToSpaceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDepthToSpace); case kTfLiteBuiltinDepthwiseConv2d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDepthwiseConv2d); case kTfLiteBuiltinDequantize: return VisitDequantizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDequantize); case kTfLiteBuiltinDiv: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDiv); case kTfLiteBuiltinElu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinElu); case kTfLiteBuiltinEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinEqual); case kTfLiteBuiltinExp: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Exp); case kTfLiteBuiltinExpandDims: return VisitExpandDimsOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinExpandDims); case kTfLiteBuiltinFill: return VisitFillOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFill); case kTfLiteBuiltinFloor: return VisitFloorOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFloor); case kTfLiteBuiltinFloorDiv: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFloorDiv); case kTfLiteBuiltinFullyConnected: return VisitFullyConnectedOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFullyConnected); case kTfLiteBuiltinGather: return VisitGatherOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGather); case kTfLiteBuiltinGatherNd: return VisitGatherNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGatherNd); case kTfLiteBuiltinGreater: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGreater); case kTfLiteBuiltinGreaterEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGreaterEqual); case kTfLiteBuiltinHardSwish: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinHardSwish); case kTfLiteBuiltinL2Normalization: return VisitL2NormalizationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinL2Normalization); case kTfLiteBuiltinL2Pool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinL2Pool2d); case kTfLiteBuiltinLeakyRelu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLeakyRelu); case kTfLiteBuiltinLess: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLess); case kTfLiteBuiltinLessEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLessEqual); case kTfLiteBuiltinLocalResponseNormalization: return VisitLocalResponseNormalizationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLocalResponseNormalization); case kTfLiteBuiltinLog: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Log); case kTfLiteBuiltinLogicalAnd: return VisitLogicalBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogicalAnd, armnn::LogicalBinaryOperation::LogicalAnd); case kTfLiteBuiltinLogicalNot: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::LogicalNot); case kTfLiteBuiltinLogicalOr: return VisitLogicalBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogicalOr, armnn::LogicalBinaryOperation::LogicalOr); case kTfLiteBuiltinLogistic: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogistic); case kTfLiteBuiltinLogSoftmax: return VisitSoftmaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogSoftmax); case kTfLiteBuiltinLstm: return VisitLstmOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLstm); case kTfLiteBuiltinMaxPool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMaxPool2d); case kTfLiteBuiltinMaximum: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMaximum); case kTfLiteBuiltinMean: return VisitControlOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMean); case kTfLiteBuiltinMinimum: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMinimum); case kTfLiteBuiltinMirrorPad: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMirrorPad); case kTfLiteBuiltinMul: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMul); case kTfLiteBuiltinNeg: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Neg); case kTfLiteBuiltinNotEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinNotEqual); case kTfLiteBuiltinPack: return VisitPackOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPack); case kTfLiteBuiltinPad: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPad); case kTfLiteBuiltinPadv2: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPadv2); case kTfLiteBuiltinPow: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPow); case kTfLiteBuiltinPrelu: return VisitPreluOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPrelu); case kTfLiteBuiltinQuantize: return VisitQuantizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinQuantize); case kTfLiteBuiltinRank: return VisitControlOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRank); case kTfLiteBuiltinReduceMax: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceMax); case kTfLiteBuiltinReduceMin: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceMin); case kTfLiteBuiltinReduceProd: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceProd); case kTfLiteBuiltinRelu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRelu); case kTfLiteBuiltinReluN1To1: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReluN1To1); case kTfLiteBuiltinRelu6: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRelu6); case kTfLiteBuiltinReshape: return VisitReshapeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReshape); case kTfLiteBuiltinResizeBilinear: return VisitResizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinResizeBilinear); case kTfLiteBuiltinResizeNearestNeighbor: return VisitResizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinResizeNearestNeighbor); case kTfLiteBuiltinReverseV2: return VisitReverseV2Operator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReverseV2); case kTfLiteBuiltinRsqrt: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Rsqrt); case kTfLiteBuiltinShape: return VisitShapeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinShape); case kTfLiteBuiltinSin: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Sin); case kTfLiteBuiltinSplit: return VisitSplitOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSplit); case kTfLiteBuiltinSplitV: return VisitSplitVOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSplitV); case kTfLiteBuiltinSqrt: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, armnn::UnaryOperation::Sqrt); case kTfLiteBuiltinSquaredDifference: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSquaredDifference); case kTfLiteBuiltinSqueeze: return VisitSqueezeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSqueeze); case kTfLiteBuiltinSlice: return VisitSliceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSlice); case kTfLiteBuiltinStridedSlice: return VisitStridedSliceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinStridedSlice); case kTfLiteBuiltinSum: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSum); case kTfLiteBuiltinTranspose: return VisitTransposeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTranspose); case kTfLiteBuiltinTransposeConv: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTransposeConv); case kTfLiteBuiltinSoftmax: return VisitSoftmaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSoftmax); case kTfLiteBuiltinSpaceToBatchNd: return VisitSpaceToBatchNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSpaceToBatchNd); case kTfLiteBuiltinSpaceToDepth: return VisitSpaceToDepthOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSpaceToDepth); case kTfLiteBuiltinSub: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSub); case kTfLiteBuiltinTanh: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTanh); case kTfLiteBuiltinTile: return VisitTileOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTile); case kTfLiteBuiltinUnidirectionalSequenceLstm: return VisitUnidirectionalSequenceLstmOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinUnidirectionalSequenceLstm); case kTfLiteBuiltinUnpack: return VisitUnpackOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinUnpack); default: return kTfLiteError; } } } // armnnDelegate namespacearmnn-23.08/delegate/classic/src/armnn_external_delegate.cpp000066400000000000000000000043061446772241200242120ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "armnn_delegate.hpp" #include #include #include #include namespace tflite { /** * This file defines two symbols that need to be exported to use the TFLite external delegate provider. This is a plugin * that can be used for fast integration of delegates into benchmark tests and other tools. It allows loading of * a dynamic delegate library at runtime. * * The external delegate also has Tensorflow Lite Python bindings. Therefore the dynamic external delegate * can be directly used with Tensorflow Lite Python APIs. * * See tensorflow/lite/delegates/external for details or visit the tensorflow guide * [here](https://www.tensorflow.org/lite/performance/implementing_delegate#option_2_leverage_external_delegate) */ extern "C" { /** * Implementation of the TfLite external delegate plugin * * For details about what options_keys and option_values are supported please see: * armnnDelegate::DelegateOptions::DelegateOptions(char const* const*, char const* const*,size_t,void (*)(const char*)) */ TfLiteDelegate* tflite_plugin_create_delegate(char** options_keys, char** options_values, size_t num_options, void (*report_error)(const char*)) { // Returning null indicates an error during delegate creation, we initialize with that TfLiteDelegate* delegate = nullptr; try { armnnDelegate::DelegateOptions options (options_keys, options_values, num_options, (*report_error)); delegate = TfLiteArmnnDelegateCreate(options); } catch (const std::exception& ex) { if(report_error) { report_error(ex.what()); } } return delegate; } /** Destroy a given delegate plugin * * @param[in] delegate Delegate to destruct */ void tflite_plugin_destroy_delegate(TfLiteDelegate* delegate) { armnnDelegate::TfLiteArmnnDelegateDelete(delegate); } } // extern "C" } // namespace tflitearmnn-23.08/delegate/classic/src/test/000077500000000000000000000000001446772241200176135ustar00rootroot00000000000000armnn-23.08/delegate/classic/src/test/ArmnnClassicDelegateTest.cpp000066400000000000000000000102001446772241200251600ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #define DOCTEST_CONFIG_IMPLEMENT_WITH_MAIN #include #include #include #include #include namespace armnnDelegate { TEST_SUITE("ArmnnDelegate") { TEST_CASE ("ArmnnDelegate Registered") { using namespace tflite; auto tfLiteInterpreter = std::make_unique(); tfLiteInterpreter->AddTensors(3); tfLiteInterpreter->SetInputs({0, 1}); tfLiteInterpreter->SetOutputs({2}); tfLiteInterpreter->SetTensorParametersReadWrite(0, kTfLiteFloat32, "input1", {1,2,2,1}, TfLiteQuantization()); tfLiteInterpreter->SetTensorParametersReadWrite(1, kTfLiteFloat32, "input2", {1,2,2,1}, TfLiteQuantization()); tfLiteInterpreter->SetTensorParametersReadWrite(2, kTfLiteFloat32, "output", {1,2,2,1}, TfLiteQuantization()); tflite::ops::builtin::BuiltinOpResolver opResolver; const TfLiteRegistration* opRegister = opResolver.FindOp(BuiltinOperator_ADD, 1); tfLiteInterpreter->AddNodeWithParameters({0, 1}, {2}, "", 0, nullptr, opRegister); // Create the Armnn Delegate std::vector backends = { armnn::Compute::CpuRef }; std::vector backendOptions; backendOptions.emplace_back( armnn::BackendOptions{ "BackendName", { { "Option1", 42 }, { "Option2", true } }} ); armnnDelegate::DelegateOptions delegateOptions(backends, backendOptions); std::unique_ptr theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), armnnDelegate::TfLiteArmnnDelegateDelete); auto status = tfLiteInterpreter->ModifyGraphWithDelegate(std::move(theArmnnDelegate)); CHECK(status == kTfLiteOk); CHECK(tfLiteInterpreter != nullptr); } TEST_CASE ("ArmnnDelegateOptimizerOptionsRegistered") { using namespace tflite; auto tfLiteInterpreter = std::make_unique(); tfLiteInterpreter->AddTensors(3); tfLiteInterpreter->SetInputs({0, 1}); tfLiteInterpreter->SetOutputs({2}); tfLiteInterpreter->SetTensorParametersReadWrite(0, kTfLiteFloat32, "input1", {1,2,2,1}, TfLiteQuantization()); tfLiteInterpreter->SetTensorParametersReadWrite(1, kTfLiteFloat32, "input2", {1,2,2,1}, TfLiteQuantization()); tfLiteInterpreter->SetTensorParametersReadWrite(2, kTfLiteFloat32, "output", {1,2,2,1}, TfLiteQuantization()); tflite::ops::builtin::BuiltinOpResolver opResolver; const TfLiteRegistration* opRegister = opResolver.FindOp(BuiltinOperator_ADD, 1); tfLiteInterpreter->AddNodeWithParameters({0, 1}, {2}, "", 0, nullptr, opRegister); // Create the Armnn Delegate std::vector backends = { armnn::Compute::CpuRef }; armnn::OptimizerOptionsOpaque optimizerOptions(true, true, false, true); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); std::unique_ptr theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), armnnDelegate::TfLiteArmnnDelegateDelete); auto status = tfLiteInterpreter->ModifyGraphWithDelegate(std::move(theArmnnDelegate)); CHECK(status == kTfLiteOk); CHECK(tfLiteInterpreter != nullptr); } TEST_CASE ("DelegateOptions_ClassicDelegateDefault") { // Check default options can be created auto options = TfLiteArmnnDelegateOptionsDefault(); // Check Classic delegate created auto classicDelegate = armnnDelegate::TfLiteArmnnDelegateCreate(options); CHECK(classicDelegate); // Check Classic Delegate can be deleted CHECK(classicDelegate->data_); armnnDelegate::TfLiteArmnnDelegateDelete(classicDelegate); } } } // namespace armnnDelegate armnn-23.08/delegate/classic/src/test/DelegateTestInterpreter.cpp000066400000000000000000000053161446772241200251220ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include namespace delegateTestInterpreter { DelegateTestInterpreter::DelegateTestInterpreter(std::vector& modelBuffer, const std::vector& backends, const std::string& customOp, bool disableFallback) { TfLiteModel* tfLiteModel = delegateTestInterpreter::CreateTfLiteModel(modelBuffer); TfLiteInterpreterOptions* options = delegateTestInterpreter::CreateTfLiteInterpreterOptions(); if (!customOp.empty()) { options->mutable_op_resolver = delegateTestInterpreter::GenerateCustomOpResolver(customOp); } // Disable fallback by default for unit tests unless specified. armnnDelegate::DelegateOptions delegateOptions(backends); delegateOptions.DisableTfLiteRuntimeFallback(disableFallback); auto armnnDelegate = armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions); TfLiteInterpreterOptionsAddDelegate(options, armnnDelegate); m_TfLiteDelegate = armnnDelegate; m_TfLiteInterpreter = TfLiteInterpreterCreate(tfLiteModel, options); // The options and model can be deleted after the interpreter is created. TfLiteInterpreterOptionsDelete(options); TfLiteModelDelete(tfLiteModel); } DelegateTestInterpreter::DelegateTestInterpreter(std::vector& modelBuffer, const armnnDelegate::DelegateOptions& delegateOptions, const std::string& customOp) { TfLiteModel* tfLiteModel = delegateTestInterpreter::CreateTfLiteModel(modelBuffer); TfLiteInterpreterOptions* options = delegateTestInterpreter::CreateTfLiteInterpreterOptions(); if (!customOp.empty()) { options->mutable_op_resolver = delegateTestInterpreter::GenerateCustomOpResolver(customOp); } auto armnnDelegate = armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions); TfLiteInterpreterOptionsAddDelegate(options, armnnDelegate); m_TfLiteDelegate = armnnDelegate; m_TfLiteInterpreter = TfLiteInterpreterCreate(tfLiteModel, options); // The options and model can be deleted after the interpreter is created. TfLiteInterpreterOptionsDelete(options); TfLiteModelDelete(tfLiteModel); } void DelegateTestInterpreter::Cleanup() { TfLiteInterpreterDelete(m_TfLiteInterpreter); if (m_TfLiteDelegate) { armnnDelegate::TfLiteArmnnDelegateDelete(static_cast(m_TfLiteDelegate)); } } } // anonymous namespacearmnn-23.08/delegate/cmake/000077500000000000000000000000001446772241200155045ustar00rootroot00000000000000armnn-23.08/delegate/cmake/Modules/000077500000000000000000000000001446772241200171145ustar00rootroot00000000000000armnn-23.08/delegate/cmake/Modules/ArmnnDelegateConfig.cmake.in000066400000000000000000000014501446772241200243570ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # get_filename_component(ARMNN_DELEGATE_CMAKE_DIR "${CMAKE_CURRENT_LIST_FILE}" DIRECTORY) set(ARMNN_DELEGATE_CONFIG_FILE ${CMAKE_CURRENT_LIST_FILE}) MESSAGE(STATUS "Found ArmnnDelegate: ${ARMNN_DELEGATE_CONFIG_FILE}") include(CMakeFindDependencyMacro) list(APPEND CMAKE_MODULE_PATH ${ARMNN_DELEGATE_CMAKE_DIR}) @PACKAGE_INIT@ set_and_check(Armnn_DIR "@Armnn_DIR@") find_dependency(Armnn REQUIRED CONFIG HINTS ${Armnn_DIR}) if(NOT TARGET ArmnnDelegate::ArmnnDelegate) MESSAGE(STATUS "ArmnnDelegate Import: ${ARMNN_DELEGATE_CMAKE_DIR}/ArmnnDelegateTargets.cmake") include("${ARMNN_DELEGATE_CMAKE_DIR}/ArmnnDelegateTargets.cmake") endif() set(ARMNN_DELEGATE_LIBRARIES ArmnnDelegate::ArmnnDelegate)armnn-23.08/delegate/cmake/Modules/FindFlatbuffers.cmake000066400000000000000000000015301446772241200231610ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # include(FindPackageHandleStandardArgs) unset(FLATBUFFERS_FOUND) find_path(Flatbuffers_INCLUDE_DIR flatbuffers/flatbuffers.h HINTS ${FLATBUFFERS_ROOT}/include /usr/local/include /usr/include) find_library(Flatbuffers_LIB NAMES libflatbuffers.a flatbuffers HINTS ${FLATBUFFERS_ROOT}/lib /usr/local/lib /usr/lib) ## Set FLATBUFFERS_FOUND find_package_handle_standard_args(Flatbuffers DEFAULT_MSG Flatbuffers_INCLUDE_DIR Flatbuffers_LIB) ## Set external variables for usage in CMakeLists.txt if(FLATBUFFERS_FOUND) set(Flatbuffers_LIB ${Flatbuffers_LIB}) set(Flatbuffers_INCLUDE_DIR ${Flatbuffers_INCLUDE_DIR}) endif()armnn-23.08/delegate/cmake/Modules/FindTfLite.cmake000066400000000000000000000227201446772241200221110ustar00rootroot00000000000000# # Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # include(FindPackageHandleStandardArgs) unset(TFLITE_FOUND) # # NOTE: this module is used to find the tensorflow lite binary libraries only # the FindTfLiteSrc.cmake module is used to find the tensorflow lite include directory. # This is to allow components like the Tensorflow lite parser that have a source dependency # on tensorflow lite headers but no need to link to the binary libraries to use only the sources # and not have an artificial dependency on the libraries. # # First look for the static version of tensorflow lite find_library(TfLite_LIB NAMES "libtensorflow-lite.a" HINTS ${TFLITE_LIB_ROOT} ${TFLITE_LIB_ROOT}/tensorflow/lite) # If not found then, look for the dynamic library of tensorflow lite find_library(TfLite_LIB NAMES "libtensorflow_lite_all.so" "libtensorflowlite.so" HINTS ${TFLITE_LIB_ROOT} ${TFLITE_LIB_ROOT}/tensorflow/lite) # If the static library was found, gather all of its dependencies if (TfLite_LIB MATCHES .a$) message("-- Static tensorflow lite library found, using for ArmNN build") find_library(TfLite_abseilstrings_LIB "libabsl_strings.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/strings) find_library(TfLite_abseil_synchronization_LIB "libabsl_synchronization.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/synchronization) find_library(TfLite_farmhash_LIB "libfarmhash.a" PATH ${TFLITE_LIB_ROOT}/_deps/farmhash-build) find_library(TfLite_fftsg_LIB "libfft2d_fftsg.a" PATH ${TFLITE_LIB_ROOT}/_deps/fft2d-build) find_library(TfLite_fftsg2d_LIB "libfft2d_fftsg2d.a" PATH ${TFLITE_LIB_ROOT}/_deps/fft2d-build) find_library(TfLite_flatbuffers_LIB "libflatbuffers.a" PATH ${TFLITE_LIB_ROOT}/_deps/flatbuffers-build) find_library(TfLite_cpuinfo_LIB "libcpuinfo.a" PATH ${TFLITE_LIB_ROOT}/_deps/cpuinfo-build) # All remaining libraries are part of libruy. find_library(TfLite_ruy_allocator_LIB "libruy_allocator.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_apply_multiplier_LIB "libruy_apply_multiplier.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_blocking_counter_LIB "libruy_blocking_counter.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_block_map_LIB "libruy_block_map.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_context_LIB "libruy_context.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_context_get_ctx_LIB "libruy_context_get_ctx.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_cpuinfo_LIB "libruy_cpuinfo.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_ctx_LIB "libruy_ctx.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_denormal_LIB "libruy_denormal.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_frontend_LIB "libruy_frontend.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_have_built_path_for_avx2_fma_LIB "libruy_have_built_path_for_avx2_fma.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_have_built_path_for_avx512_LIB "libruy_have_built_path_for_avx512.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_have_built_path_for_avx_LIB "libruy_have_built_path_for_avx.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_kernel_arm_LIB "libruy_kernel_arm.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_kernel_avx2_fma_LIB "libruy_kernel_avx2_fma.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_kernel_avx512_LIB "libruy_kernel_avx512.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_kernel_avx_LIB "libruy_kernel_avx.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_pack_arm_LIB "libruy_pack_arm.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_pack_avx2_fma_LIB "libruy_pack_avx2_fma.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_pack_avx512_LIB "libruy_pack_avx512.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_pack_avx_LIB "libruy_pack_avx.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_prepacked_cache_LIB "libruy_prepacked_cache.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_prepare_packed_matrices_LIB "libruy_prepare_packed_matrices.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_system_aligned_alloc_LIB "libruy_system_aligned_alloc.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_threadpool_LIB "libruy_thread_pool.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_trmul_LIB "libruy_trmul.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_tune_LIB "libruy_tune.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_wait_LIB "libruy_wait.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy) find_library(TfLite_ruy_profiler_LIB "libruy_profiler_instrumentation.a" PATH ${TFLITE_LIB_ROOT}/_deps/ruy-build/ruy/profiler) find_library(TfLite_pthread_pool_LIB "libpthreadpool.a" PATH ${TFLITE_LIB_ROOT}/pthreadpool) ## Set TFLITE_FOUND if all libraries are satisfied for static lib find_package_handle_standard_args(TfLite DEFAULT_MSG TfLite_LIB TfLite_abseilstrings_LIB TfLite_farmhash_LIB TfLite_fftsg_LIB TfLite_fftsg2d_LIB TfLite_flatbuffers_LIB TfLite_ruy_allocator_LIB TfLite_ruy_apply_multiplier_LIB TfLite_ruy_blocking_counter_LIB TfLite_ruy_block_map_LIB TfLite_ruy_context_LIB TfLite_ruy_context_get_ctx_LIB TfLite_ruy_cpuinfo_LIB TfLite_ruy_ctx_LIB TfLite_ruy_denormal_LIB TfLite_ruy_frontend_LIB TfLite_ruy_have_built_path_for_avx2_fma_LIB TfLite_ruy_have_built_path_for_avx512_LIB TfLite_ruy_have_built_path_for_avx_LIB TfLite_ruy_kernel_arm_LIB TfLite_ruy_kernel_avx2_fma_LIB TfLite_ruy_kernel_avx512_LIB TfLite_ruy_kernel_avx_LIB TfLite_ruy_pack_arm_LIB TfLite_ruy_pack_avx2_fma_LIB TfLite_ruy_pack_avx512_LIB TfLite_ruy_pack_avx_LIB TfLite_ruy_prepacked_cache_LIB TfLite_ruy_prepare_packed_matrices_LIB TfLite_ruy_system_aligned_alloc_LIB TfLite_ruy_threadpool_LIB TfLite_ruy_trmul_LIB TfLite_ruy_tune_LIB TfLite_ruy_wait_LIB TfLite_ruy_profiler_LIB TfLite_cpuinfo_LIB TfLite_abseil_synchronization_LIB TfLite_pthread_pool_LIB) # Set external variables for usage in CMakeLists.txt if (TFLITE_FOUND) # WARNING! The order of these libraries is critical. Moving them # around will result in linker errors in DelegateUnitTests. set(TfLite_LIB ${TfLite_LIB} ${TfLite_abseilstrings_LIB} ${TfLite_farmhash_LIB} ${TfLite_fftsg_LIB} ${TfLite_fftsg2d_LIB} ${TfLite_flatbuffers_LIB} ${TfLite_ruy_allocator_LIB} ${TfLite_ruy_apply_multiplier_LIB} ${TfLite_ruy_frontend_LIB} ${TfLite_ruy_trmul_LIB} ${TfLite_ruy_threadpool_LIB} ${TfLite_ruy_blocking_counter_LIB} ${TfLite_ruy_block_map_LIB} ${TfLite_ruy_context_LIB} ${TfLite_ruy_context_get_ctx_LIB} ${TfLite_ruy_cpuinfo_LIB} ${TfLite_ruy_ctx_LIB} ${TfLite_ruy_denormal_LIB} ${TfLite_ruy_have_built_path_for_avx2_fma_LIB} ${TfLite_ruy_have_built_path_for_avx512_LIB} ${TfLite_ruy_have_built_path_for_avx_LIB} ${TfLite_ruy_kernel_arm_LIB} ${TfLite_ruy_kernel_avx2_fma_LIB} ${TfLite_ruy_kernel_avx512_LIB} ${TfLite_ruy_kernel_avx_LIB} ${TfLite_ruy_pack_arm_LIB} ${TfLite_ruy_pack_avx2_fma_LIB} ${TfLite_ruy_pack_avx512_LIB} ${TfLite_ruy_pack_avx_LIB} ${TfLite_ruy_prepacked_cache_LIB} ${TfLite_ruy_prepare_packed_matrices_LIB} ${TfLite_ruy_system_aligned_alloc_LIB} ${TfLite_ruy_tune_LIB} ${TfLite_ruy_wait_LIB} ${TfLite_ruy_profiler_LIB} ${TfLite_cpuinfo_LIB} ${TfLite_abseil_synchronization_LIB} ${TfLite_pthread_pool_LIB}) endif () elseif (TfLite_LIB MATCHES .so$) message("-- Dynamic tensorflow lite library found, using for ArmNN build") find_package_handle_standard_args(TfLite DEFAULT_MSG TfLite_LIB) ## Set external variables for usage in CMakeLists.txt if (TFLITE_FOUND) set(TfLite_LIB ${TfLite_LIB}) endif () else() message(FATAL_ERROR "Could not find a tensorflow lite library to use") endif() armnn-23.08/delegate/cmake/Modules/FindTfLiteAbsl.cmake000066400000000000000000000071571446772241200227220ustar00rootroot00000000000000# # Copyright © 2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # include(FindPackageHandleStandardArgs) unset(TFLITEABSL_FOUND) find_path(TfLite_ABSL_SYNC_HEADERS NAMES absl HINTS ${TFLITE_LIB_ROOT}/abseil-cpp) # First look for the static version of tensorflow lite find_library(TfLite_LIB NAMES "libtensorflow-lite.a" HINTS ${TFLITE_LIB_ROOT} ${TFLITE_LIB_ROOT}/tensorflow/lite) # If the static library was found, gather extra absl libraries for opaque delegate if (TfLite_LIB MATCHES .a$) find_library(TfLite_abseil_base_LIB "libabsl_base.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/base) find_library(TfLite_abseil_log_severity_LIB "libabsl_log_severity.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/base) find_library(TfLite_abseil_spinlock_wait_LIB "libabsl_spinlock_wait.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/base) find_library(TfLite_abseil_malloc_internal_LIB "libabsl_malloc_internal.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/base) find_library(TfLite_abseil_raw_logging_internal_LIB "libabsl_raw_logging_internal.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/base) find_library(TfLite_abseil_stacktrace_LIB "libabsl_stacktrace.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/debugging) find_library(TfLite_abseil_debugging_internal_LIB "libabsl_debugging_internal.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/debugging) find_library(TfLite_abseil_symbolize_LIB "libabsl_symbolize.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/debugging) find_library(TfLite_abseil_demangle_internal_LIB "libabsl_demangle_internal.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/debugging) find_library(TfLite_abseil_time_LIB "libabsl_time.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/time) find_library(TfLite_abseil_time_zone_LIB "libabsl_time_zone.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/time) find_library(TfLite_abseil_int128_LIB "libabsl_int128.a" PATH ${TFLITE_LIB_ROOT}/_deps/abseil-cpp-build/absl/numeric) ## Set TFLITEABSL_FOUND find_package_handle_standard_args(TfLiteAbsl DEFAULT_MSG TfLite_ABSL_SYNC_HEADERS TfLite_abseil_base_LIB TfLite_abseil_int128_LIB TfLite_abseil_spinlock_wait_LIB TfLite_abseil_raw_logging_internal_LIB TfLite_abseil_malloc_internal_LIB TfLite_abseil_symbolize_LIB TfLite_abseil_stacktrace_LIB TfLite_abseil_demangle_internal_LIB TfLite_abseil_debugging_internal_LIB TfLite_abseil_time_LIB TfLite_abseil_time_zone_LIB) ## Set external variables for usage in CMakeLists.txt if(TFLITEABSL_FOUND) set(TfLite_ABSL_SYNC_HEADERS ${TfLite_ABSL_SYNC_HEADERS}) set(TfLite_Extra_Absl_LIB ${TfLite_abseil_base_LIB} ${TfLite_abseil_int128_LIB} ${TfLite_abseil_spinlock_wait_LIB} ${TfLite_abseil_raw_logging_internal_LIB} ${TfLite_abseil_malloc_internal_LIB} ${TfLite_abseil_symbolize_LIB} ${TfLite_abseil_stacktrace_LIB} ${TfLite_abseil_demangle_internal_LIB} ${TfLite_abseil_debugging_internal_LIB} ${TfLite_abseil_time_LIB} ${TfLite_abseil_time_zone_LIB}) endif() endif() armnn-23.08/delegate/cmake/Modules/FindTfLiteSrc.cmake000066400000000000000000000014021446772241200225530ustar00rootroot00000000000000# # Copyright © 2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # include(FindPackageHandleStandardArgs) unset(TFLITE_SRC_FOUND) find_path(TfLite_INCLUDE_DIR NAMES tensorflow/lite third_party HINTS ${TENSORFLOW_ROOT}) find_path(TfLite_Schema_INCLUDE_PATH schema_generated.h HINTS ${TENSORFLOW_ROOT}/tensorflow/lite/schema) ## Set TFLITE_FOUND find_package_handle_standard_args(TfLiteSrc DEFAULT_MSG TfLite_INCLUDE_DIR TfLite_Schema_INCLUDE_PATH) ## Set external variables for usage in CMakeLists.txt if(TFLITE_SRC_FOUND) set(TfLite_INCLUDE_DIR ${TfLite_INCLUDE_DIR}) set(TfLite_Schema_INCLUDE_PATH ${TfLite_Schema_INCLUDE_PATH}) endif() armnn-23.08/delegate/common/000077500000000000000000000000001446772241200157145ustar00rootroot00000000000000armnn-23.08/delegate/common/include/000077500000000000000000000000001446772241200173375ustar00rootroot00000000000000armnn-23.08/delegate/common/include/DelegateOptions.hpp000066400000000000000000000255301446772241200231430ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include namespace armnnDelegate { struct DelegateOptionsImpl; class DelegateOptions { public: ~DelegateOptions(); DelegateOptions(); DelegateOptions(const DelegateOptions& other); DelegateOptions(armnn::Compute computeDevice, const std::vector& backendOptions = {}, armnn::Optional logSeverityLevel = armnn::EmptyOptional()); DelegateOptions(const std::vector& backends, const std::vector& backendOptions = {}, armnn::Optional logSeverityLevel = armnn::EmptyOptional()); DelegateOptions(armnn::Compute computeDevice, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel = armnn::EmptyOptional(), const armnn::Optional& func = armnn::EmptyOptional()); DelegateOptions(const std::vector& backends, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel = armnn::EmptyOptional(), const armnn::Optional& func = armnn::EmptyOptional()); /** * This constructor processes delegate options in form of command line arguments. * It works in conjunction with the TfLite external delegate plugin. * * Available options: * * Option key: "backends" \n * Possible values: ["EthosNPU"/"GpuAcc"/"CpuAcc"/"CpuRef"] \n * Descriptions: A comma separated list without whitespaces of * backends which should be used for execution. Falls * back to next backend in list if previous doesn't * provide support for operation. e.g. "GpuAcc,CpuAcc" * * Option key: "dynamic-backends-path" \n * Possible values: [filenameString] \n * Descriptions: This is the directory that will be searched for any dynamic backends. * * Option key: "logging-severity" \n * Possible values: ["trace"/"debug"/"info"/"warning"/"error"/"fatal"] \n * Description: Sets the logging severity level for ArmNN. Logging * is turned off if this option is not provided. * * Option key: "gpu-tuning-level" \n * Possible values: ["0"/"1"/"2"/"3"] \n * Description: 0=UseOnly(default), 1=RapidTuning, 2=NormalTuning, * 3=ExhaustiveTuning. Requires option gpu-tuning-file. * 1,2 and 3 will create a tuning-file, 0 will apply the * tunings from an existing file * * Option key: "gpu-mlgo-tuning-file" \n * Possible values: [filenameString] \n * Description: File name for the MLGO tuning file * * Option key: "gpu-tuning-file" \n * Possible values: [filenameString] \n * Description: File name for the tuning file. * * Option key: "gpu-enable-profiling" \n * Possible values: ["true"/"false"] \n * Description: Enables GPU profiling * * Option key: "gpu-kernel-profiling-enabled" \n * Possible values: ["true"/"false"] \n * Description: Enables GPU kernel profiling * * Option key: "save-cached-network" \n * Possible values: ["true"/"false"] \n * Description: Enables saving of the cached network to a file, * specified with the cached-network-filepath option * * Option key: "cached-network-filepath" \n * Possible values: [filenameString] \n * Description: If non-empty, the given file will be used to load/save the cached network. * If save-cached-network is given then the cached network will be saved to the given file. * To save the cached network a file must already exist. * If save-cached-network is not given then the cached network will be loaded from the given file. * This will remove initial compilation time of kernels and speed up the first execution. * * Option key: "enable-fast-math" \n * Possible values: ["true"/"false"] \n * Description: Enables fast_math options in backends that support it * * Option key: "number-of-threads" \n * Possible values: ["1"-"64"] \n * Description: Assign the number of threads used by the CpuAcc backend. * Default is set to 0 (Backend will decide number of threads to use). * * Option key: "reduce-fp32-to-fp16" \n * Possible values: ["true"/"false"] \n * Description: Reduce Fp32 data to Fp16 for faster processing * * Option key: "reduce-fp32-to-bf16" \n * Possible values: ["true"/"false"] \n * Description: This option is currently ignored. Please enable Fast Math in the CpuAcc or GpuAcc backends. * * Option key: "debug-data" \n * Possible values: ["true"/"false"] \n * Description: Add debug data for easier troubleshooting * * Option key: "memory-import" \n * Possible values: ["true"/"false"] \n * Description: Enable memory import * * Option key: "enable-internal-profiling" \n * Possible values: ["true"/"false"] \n * Description: Enable the internal profiling feature. * * Option key: "internal-profiling-detail" \n * Possible values: [1/2] \n * Description: Set the detail on the internal profiling. 1 = DetailsWithEvents, 2 = DetailsOnly. * * Option key: "enable-external-profiling" \n * Possible values: ["true"/"false"] \n * Description: Enable the external profiling feature. * * Option key: "timeline-profiling" \n * Possible values: ["true"/"false"] \n * Description: Indicates whether external timeline profiling is enabled or not. * * Option key: "outgoing-capture-file" \n * Possible values: [filenameString] \n * Description: Path to a file in which outgoing timeline profiling messages will be stored. * * Option key: "incoming-capture-file" \n * Possible values: [filenameString] \n * Description: Path to a file in which incoming timeline profiling messages will be stored. * * Option key: "file-only-external-profiling" \n * Possible values: ["true"/"false"] \n * Description: Enable profiling output to file only. * * Option key: "counter-capture-period" \n * Possible values: Integer, Default is 10000u * Description: Value in microseconds of the profiling capture period. \n * * Option key: "profiling-file-format" \n * Possible values: String of ["binary"] \n * Description: The format of the file used for outputting profiling data. Currently on "binary" is supported. * * Option key: "serialize-to-dot" \n * Possible values: [filenameString] \n * Description: Serialize the optimized network to the file specified in "dot" format. * * Option key: "infer-output-shape" \n * Possible values: ["true"/"false"] \n * Description: Infers output tensor shape from input tensor shape and validate where applicable. * * Option key: "allow-expanded-dims" \n * Possible values: ["true"/"false"] \n * Description: If true will disregard dimensions with a size of 1 when validating tensor shapes but tensor * sizes must still match. \n * This is an Experimental parameter that is incompatible with "infer-output-shape". \n * This parameter may be removed in a later update. * * Option key: "disable-tflite-runtime-fallback" \n * Possible values: ["true"/"false"] \n * Description: Disable TfLite Runtime fallback in the Arm NN TfLite delegate. * An exception will be thrown if unsupported operators are encountered. * This option is only for testing purposes. * * @param[in] option_keys Delegate option names * @param[in] options_values Delegate option values * @param[in] num_options Number of delegate options * @param[in,out] report_error Error callback function * */ DelegateOptions(char const* const* options_keys, char const* const* options_values, size_t num_options, void (*report_error)(const char*)); const std::vector& GetBackends() const; void SetBackends(const std::vector& backends); void SetDynamicBackendsPath(const std::string& dynamicBackendsPath); const std::string& GetDynamicBackendsPath() const; void SetGpuProfilingState(bool gpuProfilingState); bool GetGpuProfilingState(); const std::vector& GetBackendOptions() const; /// Appends a backend option to the list of backend options void AddBackendOption(const armnn::BackendOptions& option); /// Sets the severity level for logging within ArmNN that will be used on creation of the delegate void SetLoggingSeverity(const armnn::LogSeverity& level); void SetLoggingSeverity(const std::string& level); /// Returns the severity level for logging within ArmNN armnn::LogSeverity GetLoggingSeverity(); bool IsLoggingEnabled(); const armnn::OptimizerOptionsOpaque& GetOptimizerOptions() const; void SetOptimizerOptions(const armnn::OptimizerOptionsOpaque& optimizerOptions); const armnn::Optional& GetDebugCallbackFunction() const; void SetInternalProfilingParams(bool internalProfilingState, const armnn::ProfilingDetailsMethod& internalProfilingDetail); bool GetInternalProfilingState() const; const armnn::ProfilingDetailsMethod& GetInternalProfilingDetail() const; void SetSerializeToDot(const std::string& serializeToDotFile); const std::string& GetSerializeToDot() const; /// @Note: This might overwrite options that were set with other setter functions of DelegateOptions void SetRuntimeOptions(const armnn::IRuntime::CreationOptions& runtimeOptions); const armnn::IRuntime::CreationOptions& GetRuntimeOptions(); void DisableTfLiteRuntimeFallback(bool fallbackState); bool TfLiteRuntimeFallbackDisabled(); private: std::unique_ptr p_DelegateOptionsImpl; }; } // namespace armnnDelegate armnn-23.08/delegate/common/src/000077500000000000000000000000001446772241200165035ustar00rootroot00000000000000armnn-23.08/delegate/common/src/DelegateOptions.cpp000066400000000000000000000471211446772241200223020ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include namespace armnnDelegate { struct DelegateOptionsImpl { ~DelegateOptionsImpl() = default; DelegateOptionsImpl() = default; explicit DelegateOptionsImpl(armnn::Compute computeDevice, const std::vector& backendOptions, const armnn::Optional logSeverityLevel) : m_Backends({computeDevice}), m_RuntimeOptions(), m_LoggingSeverity(logSeverityLevel) { m_RuntimeOptions.m_BackendOptions = backendOptions; } explicit DelegateOptionsImpl(const std::vector& backends, const std::vector& backendOptions, const armnn::Optional logSeverityLevel) : m_Backends(backends), m_RuntimeOptions(), m_LoggingSeverity(logSeverityLevel) { m_RuntimeOptions.m_BackendOptions = backendOptions; } explicit DelegateOptionsImpl(armnn::Compute computeDevice, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel, const armnn::Optional& func) : m_Backends({computeDevice}), m_RuntimeOptions(), m_OptimizerOptions(optimizerOptions), m_LoggingSeverity(logSeverityLevel), m_DebugCallbackFunc(func) { } explicit DelegateOptionsImpl(const std::vector& backends, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel, const armnn::Optional& func) : m_Backends(backends), m_RuntimeOptions(), m_OptimizerOptions(optimizerOptions), m_LoggingSeverity(logSeverityLevel), m_DebugCallbackFunc(func) { } /// Which backend to run Delegate on. /// Examples of possible values are: CpuRef, CpuAcc, GpuAcc. /// CpuRef as default. std::vector m_Backends = {armnn::Compute::CpuRef }; /// Creation options for the ArmNN runtime /// Contains options for global settings that are valid for the whole lifetime of ArmNN /// i.e. BackendOptions, DynamicBackendPath, ExternalProfilingOptions and more armnn::IRuntime::CreationOptions m_RuntimeOptions; /// Options for the optimization step for the network armnn::OptimizerOptionsOpaque m_OptimizerOptions; /// Internal profiling options. Written to INetworkProperties during model load. /// Indicates whether internal profiling is enabled or not. bool m_InternalProfilingEnabled = false; /// Sets the level of detail output by the profiling. Options are DetailsWithEvents = 1 and DetailsOnly = 2 armnn::ProfilingDetailsMethod m_InternalProfilingDetail = armnn::ProfilingDetailsMethod::DetailsWithEvents; /// Severity level for logging within ArmNN that will be used on creation of the delegate armnn::Optional m_LoggingSeverity; /// A callback function to debug layers performing custom computations on intermediate tensors. /// If a function is not registered, and debug is enabled in OptimizerOptions, /// debug will print information of the intermediate tensors. armnn::Optional m_DebugCallbackFunc; /// If not empty then the optimized model will be serialized to a file with this file name in "dot" format. std::string m_SerializeToDot = ""; /// Option to disable TfLite Runtime fallback for unsupported operators. bool m_DisableTfLiteRuntimeFallback = false; }; DelegateOptions::~DelegateOptions() = default; DelegateOptions::DelegateOptions() : p_DelegateOptionsImpl(std::make_unique()) { } DelegateOptions::DelegateOptions(DelegateOptions const &other) : p_DelegateOptionsImpl(std::make_unique(*other.p_DelegateOptionsImpl)) { } DelegateOptions::DelegateOptions(armnn::Compute computeDevice, const std::vector& backendOptions, const armnn::Optional logSeverityLevel) : p_DelegateOptionsImpl(std::make_unique(computeDevice, backendOptions, logSeverityLevel)) { } DelegateOptions::DelegateOptions(const std::vector& backends, const std::vector& backendOptions, const armnn::Optional logSeverityLevel) : p_DelegateOptionsImpl(std::make_unique(backends, backendOptions, logSeverityLevel)) { } DelegateOptions::DelegateOptions(armnn::Compute computeDevice, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel, const armnn::Optional& func) : p_DelegateOptionsImpl(std::make_unique(computeDevice, optimizerOptions, logSeverityLevel, func)) { } DelegateOptions::DelegateOptions(const std::vector& backends, const armnn::OptimizerOptionsOpaque& optimizerOptions, const armnn::Optional& logSeverityLevel, const armnn::Optional& func) : p_DelegateOptionsImpl(std::make_unique(backends, optimizerOptions, logSeverityLevel, func)) { } DelegateOptions::DelegateOptions(char const* const* options_keys, char const* const* options_values, size_t num_options, void (*report_error)(const char*)) : p_DelegateOptionsImpl(std::make_unique()) { armnn::IRuntime::CreationOptions runtimeOptions; armnn::OptimizerOptionsOpaque optimizerOptions; bool internalProfilingState = false; armnn::ProfilingDetailsMethod internalProfilingDetail = armnn::ProfilingDetailsMethod::DetailsWithEvents; for (size_t i = 0; i < num_options; ++i) { // Process backends if (std::string(options_keys[i]) == std::string("backends")) { // The backend option is a comma separated string of backendIDs that needs to be split std::vector backends; char* dup = strdup(options_values[i]); char* pch = std::strtok(dup, ","); while (pch != NULL) { backends.push_back(pch); pch = strtok (NULL, ","); } SetBackends(backends); } // Process dynamic-backends-path else if (std::string(options_keys[i]) == std::string("dynamic-backends-path")) { runtimeOptions.m_DynamicBackendsPath = std::string(options_values[i]); } // Process logging level else if (std::string(options_keys[i]) == std::string("logging-severity")) { SetLoggingSeverity(options_values[i]); } // Process GPU backend options else if (std::string(options_keys[i]) == std::string("gpu-tuning-level")) { armnn::BackendOptions option("GpuAcc", {{"TuningLevel", atoi(options_values[i])}}); runtimeOptions.m_BackendOptions.push_back(option); } else if (std::string(options_keys[i]) == std::string("gpu-mlgo-tuning-file")) { armnn::BackendOptions option("GpuAcc", {{"MLGOTuningFilePath", std::string(options_values[i])}}); optimizerOptions.AddModelOption(option); } else if (std::string(options_keys[i]) == std::string("gpu-tuning-file")) { armnn::BackendOptions option("GpuAcc", {{"TuningFile", std::string(options_values[i])}}); runtimeOptions.m_BackendOptions.push_back(option); } else if (std::string(options_keys[i]) == std::string("gpu-enable-profiling")) { runtimeOptions.m_EnableGpuProfiling = (*options_values[i] != '0'); } else if (std::string(options_keys[i]) == std::string("gpu-kernel-profiling-enabled")) { armnn::BackendOptions option("GpuAcc", {{"KernelProfilingEnabled", armnn::stringUtils::StringToBool(options_values[i])}}); runtimeOptions.m_BackendOptions.push_back(option); } else if (std::string(options_keys[i]) == std::string("save-cached-network")) { armnn::BackendOptions option("GpuAcc", {{"SaveCachedNetwork", armnn::stringUtils::StringToBool(options_values[i])}}); optimizerOptions.AddModelOption(option); } else if (std::string(options_keys[i]) == std::string("cached-network-filepath")) { armnn::BackendOptions option("GpuAcc", {{"CachedNetworkFilePath", std::string(options_values[i])}}); optimizerOptions.AddModelOption(option); } // Process GPU & CPU backend options else if (std::string(options_keys[i]) == std::string("enable-fast-math")) { armnn::BackendOptions modelOptionGpu("GpuAcc", {{"FastMathEnabled", armnn::stringUtils::StringToBool(options_values[i])}}); optimizerOptions.AddModelOption(modelOptionGpu); armnn::BackendOptions modelOptionCpu("CpuAcc", {{"FastMathEnabled", armnn::stringUtils::StringToBool(options_values[i])}}); optimizerOptions.AddModelOption(modelOptionCpu); } // Process CPU backend options else if (std::string(options_keys[i]) == std::string("number-of-threads")) { unsigned int numberOfThreads = armnn::numeric_cast(atoi(options_values[i])); armnn::BackendOptions modelOption("CpuAcc", {{"NumberOfThreads", numberOfThreads}}); optimizerOptions.AddModelOption(modelOption); } // Process reduce-fp32-to-fp16 option else if (std::string(options_keys[i]) == std::string("reduce-fp32-to-fp16")) { optimizerOptions.SetReduceFp32ToFp16(armnn::stringUtils::StringToBool(options_values[i])); } // Process debug-data else if (std::string(options_keys[i]) == std::string("debug-data")) { optimizerOptions.SetDebugEnabled(armnn::stringUtils::StringToBool(options_values[i])); } // Infer output-shape else if (std::string(options_keys[i]) == std::string("infer-output-shape")) { armnn::BackendOptions backendOption("ShapeInferenceMethod", { { "InferAndValidate", armnn::stringUtils::StringToBool(options_values[i]) } }); optimizerOptions.AddModelOption(backendOption); } // Allow expanded dims else if (std::string(options_keys[i]) == std::string("allow-expanded-dims")) { armnn::BackendOptions backendOption("AllowExpandedDims", { { "AllowExpandedDims", armnn::stringUtils::StringToBool(options_values[i]) } }); optimizerOptions.AddModelOption(backendOption); } // Process memory-import else if (std::string(options_keys[i]) == std::string("memory-import")) { optimizerOptions.SetImportEnabled(armnn::stringUtils::StringToBool(options_values[i])); } // Process enable-internal-profiling else if (std::string(options_keys[i]) == std::string("enable-internal-profiling")) { internalProfilingState = *options_values[i] != '0'; optimizerOptions.SetProfilingEnabled(internalProfilingState); } // Process internal-profiling-detail else if (std::string(options_keys[i]) == std::string("internal-profiling-detail")) { uint32_t detailLevel = static_cast(std::stoul(options_values[i])); switch (detailLevel) { case 1: internalProfilingDetail = armnn::ProfilingDetailsMethod::DetailsWithEvents; break; case 2: internalProfilingDetail = armnn::ProfilingDetailsMethod::DetailsOnly; break; default: internalProfilingDetail = armnn::ProfilingDetailsMethod::Undefined; break; } } // Process enable-external-profiling else if (std::string(options_keys[i]) == std::string("enable-external-profiling")) { runtimeOptions.m_ProfilingOptions.m_EnableProfiling = armnn::stringUtils::StringToBool(options_values[i]); } // Process timeline-profiling else if (std::string(options_keys[i]) == std::string("timeline-profiling")) { runtimeOptions.m_ProfilingOptions.m_TimelineEnabled = armnn::stringUtils::StringToBool(options_values[i]); } // Process outgoing-capture-file else if (std::string(options_keys[i]) == std::string("outgoing-capture-file")) { runtimeOptions.m_ProfilingOptions.m_OutgoingCaptureFile = options_values[i]; } // Process incoming-capture-file else if (std::string(options_keys[i]) == std::string("incoming-capture-file")) { runtimeOptions.m_ProfilingOptions.m_IncomingCaptureFile = options_values[i]; } // Process file-only-external-profiling else if (std::string(options_keys[i]) == std::string("file-only-external-profiling")) { runtimeOptions.m_ProfilingOptions.m_FileOnly = armnn::stringUtils::StringToBool(options_values[i]); } // Process counter-capture-period else if (std::string(options_keys[i]) == std::string("counter-capture-period")) { runtimeOptions.m_ProfilingOptions.m_CapturePeriod = static_cast(std::stoul(options_values[i])); } // Process profiling-file-format else if (std::string(options_keys[i]) == std::string("profiling-file-format")) { runtimeOptions.m_ProfilingOptions.m_FileFormat = options_values[i]; } // Process serialize-to-dot else if (std::string(options_keys[i]) == std::string("serialize-to-dot")) { SetSerializeToDot(options_values[i]); } // Process disable-tflite-runtime-fallback else if (std::string(options_keys[i]) == std::string("disable-tflite-runtime-fallback")) { this->DisableTfLiteRuntimeFallback(armnn::stringUtils::StringToBool(options_values[i])); } else { throw armnn::Exception("Unknown option for the ArmNN Delegate given: " + std::string(options_keys[i])); } } SetRuntimeOptions(runtimeOptions); SetOptimizerOptions(optimizerOptions); SetInternalProfilingParams(internalProfilingState, internalProfilingDetail); } const std::vector& DelegateOptions::GetBackends() const { return p_DelegateOptionsImpl->m_Backends; } void DelegateOptions::SetBackends(const std::vector& backends) { p_DelegateOptionsImpl->m_Backends = backends; } void DelegateOptions::SetDynamicBackendsPath(const std::string& dynamicBackendsPath) { p_DelegateOptionsImpl->m_RuntimeOptions.m_DynamicBackendsPath = dynamicBackendsPath; } const std::string& DelegateOptions::GetDynamicBackendsPath() const { return p_DelegateOptionsImpl->m_RuntimeOptions.m_DynamicBackendsPath; } void DelegateOptions::SetGpuProfilingState(bool gpuProfilingState) { p_DelegateOptionsImpl->m_RuntimeOptions.m_EnableGpuProfiling = gpuProfilingState; } bool DelegateOptions::GetGpuProfilingState() { return p_DelegateOptionsImpl->m_RuntimeOptions.m_EnableGpuProfiling; } const std::vector& DelegateOptions::GetBackendOptions() const { return p_DelegateOptionsImpl->m_RuntimeOptions.m_BackendOptions; } void DelegateOptions::AddBackendOption(const armnn::BackendOptions& option) { p_DelegateOptionsImpl->m_RuntimeOptions.m_BackendOptions.push_back(option); } void DelegateOptions::SetLoggingSeverity(const armnn::LogSeverity& level) { p_DelegateOptionsImpl->m_LoggingSeverity = level; } void DelegateOptions::SetLoggingSeverity(const std::string& level) { p_DelegateOptionsImpl->m_LoggingSeverity = armnn::StringToLogLevel(level); } armnn::LogSeverity DelegateOptions::GetLoggingSeverity() { return p_DelegateOptionsImpl->m_LoggingSeverity.value(); } bool DelegateOptions::IsLoggingEnabled() { return p_DelegateOptionsImpl->m_LoggingSeverity.has_value(); } const armnn::OptimizerOptionsOpaque& DelegateOptions::GetOptimizerOptions() const { return p_DelegateOptionsImpl->m_OptimizerOptions; } void DelegateOptions::SetOptimizerOptions(const armnn::OptimizerOptionsOpaque& optimizerOptions) { p_DelegateOptionsImpl->m_OptimizerOptions = optimizerOptions; } const armnn::Optional& DelegateOptions::GetDebugCallbackFunction() const { return p_DelegateOptionsImpl->m_DebugCallbackFunc; } void DelegateOptions::SetInternalProfilingParams(bool internalProfilingState, const armnn::ProfilingDetailsMethod& internalProfilingDetail) { p_DelegateOptionsImpl->m_InternalProfilingEnabled = internalProfilingState; p_DelegateOptionsImpl->m_InternalProfilingDetail = internalProfilingDetail; } bool DelegateOptions::GetInternalProfilingState() const { return p_DelegateOptionsImpl->m_InternalProfilingEnabled; } const armnn::ProfilingDetailsMethod& DelegateOptions::GetInternalProfilingDetail() const { return p_DelegateOptionsImpl->m_InternalProfilingDetail; } void DelegateOptions::SetSerializeToDot(const std::string& serializeToDotFile) { p_DelegateOptionsImpl->m_SerializeToDot = serializeToDotFile; } const std::string& DelegateOptions::GetSerializeToDot() const { return p_DelegateOptionsImpl->m_SerializeToDot; } void DelegateOptions::SetRuntimeOptions(const armnn::IRuntime::CreationOptions& runtimeOptions) { p_DelegateOptionsImpl->m_RuntimeOptions = runtimeOptions; } const armnn::IRuntime::CreationOptions& DelegateOptions::GetRuntimeOptions() { return p_DelegateOptionsImpl->m_RuntimeOptions; } void DelegateOptions::DisableTfLiteRuntimeFallback(bool fallbackState) { p_DelegateOptionsImpl->m_DisableTfLiteRuntimeFallback = fallbackState; } bool DelegateOptions::TfLiteRuntimeFallbackDisabled() { return p_DelegateOptionsImpl->m_DisableTfLiteRuntimeFallback; } } // namespace armnnDelegate armnn-23.08/delegate/common/src/DelegateUtils.hpp000066400000000000000000000206721446772241200217560ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include #include #include #include #include #include namespace { uint32_t NonNegative(int32_t value, int nodeIndex) { if (value < 0) { throw armnn::Exception( "TfLiteArmnnDelegate: Non-negative value in node " + std::to_string(static_cast(nodeIndex))); } else { return static_cast(value); } } void ExpandTensorRankToEqual(armnn::TensorInfo& inputInfo0, armnn::TensorInfo& inputInfo1) { unsigned int inputDimensions0 = inputInfo0.GetNumDimensions(); unsigned int inputDimensions1 = inputInfo1.GetNumDimensions(); if (inputDimensions0 == inputDimensions1) { return; } unsigned int biggerInputDimensions = std::max(inputDimensions0, inputDimensions1); bool input0IsSmaller = inputDimensions0 < inputDimensions1; armnn::TensorInfo& smallInfo = input0IsSmaller ? inputInfo0 : inputInfo1; const armnn::TensorShape& newShape = armnnUtils::ExpandDimsToRank(smallInfo.GetShape(), biggerInputDimensions); smallInfo.SetShape(newShape); } void CalcPadding(uint32_t inputSize, uint32_t filterSize, uint32_t stride, uint32_t dilation, uint32_t& paddingFront, uint32_t& paddingBack, TfLitePadding padding) { paddingFront = 0; paddingBack = 0; if (padding == kTfLitePaddingSame) { uint32_t outputSize = (inputSize + stride - 1) / stride; uint32_t dilatedSize = filterSize + (dilation - 1) * (filterSize - 1); uint32_t temp = (outputSize - 1) * stride + dilatedSize; if (temp > inputSize) { paddingFront = (temp - inputSize) / 2; paddingBack = (temp - inputSize) - paddingFront; } } } // Function that calculates explicit padding when the output shape is known. // At the moment the output is only given as an input parameter in Transpose Convolution, // not in Convolution and Depthwise Convolution void CalcPadding(uint32_t inputSize, uint32_t filterSize, uint32_t stride, uint32_t dilation, uint32_t& paddingFront, uint32_t& paddingBack, TfLitePadding padding, uint32_t outputSize) { armnn::IgnoreUnused(dilation); paddingFront = 0; paddingBack = 0; if (padding == kTfLitePaddingSame) { uint32_t totalPadding = (inputSize - 1) * stride + filterSize - outputSize; paddingFront = totalPadding / 2; paddingBack = totalPadding - paddingFront; } } unsigned int ComputeWrappedIndex(int index, unsigned int numDimensions) { int numDims = armnn::numeric_cast(numDimensions); int wrappedIndex = index < 0 ? numDims + index : index; if (wrappedIndex < 0 || wrappedIndex >= numDims) { throw armnn::ParseException("Unable to compute wrapped index"); } return static_cast(wrappedIndex); }; bool AreAllSigned32(const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { return (armnn::DataType::Signed32 == inputInfo1.GetDataType()) && (armnn::DataType::Signed32 == inputInfo2.GetDataType()) && (armnn::DataType::Signed32 == outputInfo.GetDataType()); } void UpdateConstantTensorOutputs(const armnn::TensorInfo& inputInfo, armnn::TensorInfo& outputInfo) { // If input tensor info is constant and output tensor info shape is not specified // set the output shape from input shape if (inputInfo.IsConstant() && outputInfo.GetShape().GetDimensionality() == armnn::Dimensionality::NotSpecified) { outputInfo.SetShape(inputInfo.GetShape()); } } void SetupConcatViewOrigin(const armnn::TensorInfo& inputTensorInfo, armnn::OriginsDescriptor& concatDescriptor, const unsigned int concatAxis, unsigned int inputIndex, unsigned int& mergeDimOrigin) { const uint32_t inputRank = concatDescriptor.GetNumDimensions(); // double check dimensions of the tensors if (inputTensorInfo.GetNumDimensions() != inputRank) { throw armnn::ParseException("The number of dimensions for input tensors " "of the concatenation operator should be: " + std::to_string(inputRank)); } for (unsigned int j = 0; j < concatAxis; ++j) { concatDescriptor.SetViewOriginCoord(inputIndex, j, 0); } concatDescriptor.SetViewOriginCoord(inputIndex, concatAxis, mergeDimOrigin); mergeDimOrigin += inputTensorInfo.GetShape()[concatAxis]; for (unsigned int j = concatAxis + 1; j < inputRank; ++j) { concatDescriptor.SetViewOriginCoord(inputIndex, j, 0); } } TfLiteStatus CreateOutputTensorShape(const armnn::TensorInfo& inputTensorInfo, const std::vector& targetShape, armnn::ReshapeDescriptor& reshapeDesc) { std::vector outputDims(targetShape.begin(), targetShape.end()); const auto stretchDim = std::find(targetShape.begin(), targetShape.end(), -1); if (stretchDim != targetShape.end()) { if (std::find(std::next(stretchDim), targetShape.end(), -1) != targetShape.end()) { // Return kTfLiteError and log the error after returning return kTfLiteError; } auto targetNumElements = armnn::numeric_cast( std::accumulate(targetShape.begin(), targetShape.end(), -1, std::multiplies())); auto stretchIndex = static_cast(std::distance(targetShape.begin(), stretchDim)); outputDims[stretchIndex] = inputTensorInfo.GetNumElements() / targetNumElements; } armnn::TensorShape outputShape = armnn::TensorShape(static_cast(outputDims.size()), outputDims.data()); reshapeDesc.m_TargetShape = outputShape; return kTfLiteOk; } armnn::TensorInfo OutputShapeOfSqueeze(std::vector squeezeDims, const armnn::TensorInfo& inputTensorInfo) { static const uint32_t dimensionSequence[] = { 0, 1, 2, 3 }; if (inputTensorInfo.GetNumDimensions() > 4) { std::stringstream ss; ss << "Input tensor has unexpected number of dimensions:" << inputTensorInfo.GetNumDimensions() << " shape:" << inputTensorInfo.GetShape() << " " << CHECK_LOCATION().AsString(); throw armnn::ParseException(ss.str()); } if (squeezeDims.empty()) { squeezeDims.assign(dimensionSequence, dimensionSequence + inputTensorInfo.GetNumDimensions()); } std::vector outputDims; for(unsigned int i = 0; i < inputTensorInfo.GetNumDimensions(); i++) { bool skipSqueeze = (std::find(squeezeDims.begin(), squeezeDims.end(), i) == squeezeDims.end()); auto currentDimension = inputTensorInfo.GetShape()[i]; if (skipSqueeze || currentDimension != 1) { outputDims.push_back(currentDimension); } } if (outputDims.size() > 4) { std::stringstream ss; ss << "Output tensor has unexpected number of dimensions:" << inputTensorInfo.GetNumDimensions() << " shape:" << inputTensorInfo.GetShape() << " " << CHECK_LOCATION().AsString(); throw armnn::ParseException(ss.str()); } armnn::TensorShape outShape = armnn::TensorShape(static_cast(outputDims.size()), outputDims.data()); // We need to preserve the tensor type and the quantization data as well armnn::TensorInfo outTensorInfo = inputTensorInfo; outTensorInfo.SetShape(outShape); return outTensorInfo; } } // namespace anonymous armnn-23.08/delegate/common/src/MultiLayerFacade.hpp000066400000000000000000000113601446772241200223700ustar00rootroot00000000000000// // Copyright © 2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once // NOTE: the MultiLayerFacade class is a utility class which makes a chain // of operators look like a single IConnectableLayer with the first // layer in the chain supplying the input slots and the last supplying // the output slots. It enables us, for example, to simulate a // Tensorflow Lite FloorDiv operator by chaining a Div layer followed // by a Floor layer and pass them as a single unit to the code that // connects up the graph as the delegate proceeds to build up the // Arm NN subgraphs. // #include #include namespace armnnDelegate { class MultiLayerFacade : public armnn::IConnectableLayer { public: MultiLayerFacade() : m_FirstLayer(nullptr), m_LastLayer(nullptr) {} MultiLayerFacade(armnn::IConnectableLayer* firstLayer, armnn::IConnectableLayer* lastLayer) : m_FirstLayer(firstLayer), m_LastLayer(lastLayer) {} MultiLayerFacade(const MultiLayerFacade& obj) : m_FirstLayer(obj.m_FirstLayer), m_LastLayer(obj.m_LastLayer) {} ~MultiLayerFacade() {} // we don't own the pointers MultiLayerFacade& operator=(const MultiLayerFacade& obj) { m_FirstLayer = obj.m_FirstLayer; m_LastLayer = obj.m_LastLayer; return *this; } void AssignValues(armnn::IConnectableLayer* firstLayer, armnn::IConnectableLayer* lastLayer) { m_FirstLayer = firstLayer; m_LastLayer = lastLayer; } virtual const char* GetName() const override { return m_FirstLayer->GetName(); } virtual unsigned int GetNumInputSlots() const override { return m_FirstLayer->GetNumInputSlots(); } virtual unsigned int GetNumOutputSlots() const override { return m_LastLayer->GetNumOutputSlots(); } virtual const armnn::IInputSlot& GetInputSlot(unsigned int index) const override { return m_FirstLayer->GetInputSlot(index); } virtual armnn::IInputSlot& GetInputSlot(unsigned int index) override { return m_FirstLayer->GetInputSlot(index); } virtual const armnn::IOutputSlot& GetOutputSlot(unsigned int index) const override { return m_LastLayer->GetOutputSlot(index); } virtual armnn::IOutputSlot& GetOutputSlot(unsigned int index) override { return m_LastLayer->GetOutputSlot(index); } virtual std::vector InferOutputShapes( const std::vector& inputShapes) const override { // NOTE: do not expect this function to be used. Likely that if it is it might need to be overridden // for particular sequences of operators. return m_FirstLayer->InferOutputShapes(inputShapes); } virtual LayerGuid GetGuid() const override { return m_FirstLayer->GetGuid(); } virtual void ExecuteStrategy(armnn::IStrategy& strategy) const override { // Do not expect this function to be used so not providing an implementation // if an implementation is required and the chain contains more than two operators // would have to provide a way to record the intermediate layers so they could be // visited... the same applies to the BackendSelectionHint // below. } virtual void BackendSelectionHint(armnn::Optional backend) override { // Do not expect this function to be used so not providing an implementation } virtual armnn::LayerType GetType() const override { return m_FirstLayer->GetType(); } virtual const armnn::BaseDescriptor& GetParameters() const override { return m_NullDescriptor; } void SetBackendId(const armnn::BackendId& id) override {} protected: /// Retrieve the handles to the constant values stored by the layer. /// @return A vector of the constant tensors stored by this layer. ConstantTensors GetConstantTensorsByRef() override { return {}; } ImmutableConstantTensors GetConstantTensorsByRef() const override { return {}; } private: armnn::IConnectableLayer* m_FirstLayer; armnn::IConnectableLayer* m_LastLayer; // to satisfy the GetParameters method need to hand back a NullDescriptor armnn::NullDescriptor m_NullDescriptor; }; } // namespace armnnDelegate armnn-23.08/delegate/common/src/test/000077500000000000000000000000001446772241200174625ustar00rootroot00000000000000armnn-23.08/delegate/common/src/test/DelegateTestInterpreter.hpp000066400000000000000000000145151446772241200247770ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include #include namespace delegateTestInterpreter { class DelegateTestInterpreter { public: /// Create TfLite Interpreter only DelegateTestInterpreter(std::vector& modelBuffer, const std::string& customOp = "") { TfLiteModel* model = delegateTestInterpreter::CreateTfLiteModel(modelBuffer); TfLiteInterpreterOptions* options = delegateTestInterpreter::CreateTfLiteInterpreterOptions(); if (!customOp.empty()) { options->mutable_op_resolver = delegateTestInterpreter::GenerateCustomOpResolver(customOp); } m_TfLiteInterpreter = TfLiteInterpreterCreate(model, options); m_TfLiteDelegate = nullptr; // The options and model can be deleted after the interpreter is created. TfLiteInterpreterOptionsDelete(options); TfLiteModelDelete(model); } /// Create Interpreter with default Arm NN Classic/Opaque Delegate applied DelegateTestInterpreter(std::vector& model, const std::vector& backends, const std::string& customOp = "", bool disableFallback = true); /// Create Interpreter with Arm NN Classic/Opaque Delegate applied and DelegateOptions DelegateTestInterpreter(std::vector& model, const armnnDelegate::DelegateOptions& delegateOptions, const std::string& customOp = ""); /// Allocate the TfLiteTensors within the graph. /// This must be called before FillInputTensor(values, index) and Invoke(). TfLiteStatus AllocateTensors() { return TfLiteInterpreterAllocateTensors(m_TfLiteInterpreter); } /// Copy a buffer of values into an input tensor at a given index. template TfLiteStatus FillInputTensor(std::vector& inputValues, int index) { TfLiteTensor* inputTensor = delegateTestInterpreter::GetInputTensorFromInterpreter(m_TfLiteInterpreter, index); return delegateTestInterpreter::CopyFromBufferToTensor(inputTensor, inputValues); } /// Copy a boolean buffer of values into an input tensor at a given index. /// Boolean types get converted to a bit representation in a vector. /// vector.data() returns a void pointer instead of a pointer to bool, so the tensor needs to be accessed directly. TfLiteStatus FillInputTensor(std::vector& inputValues, int index) { TfLiteTensor* inputTensor = delegateTestInterpreter::GetInputTensorFromInterpreter(m_TfLiteInterpreter, index); if(inputTensor->type != kTfLiteBool) { throw armnn::Exception("Input tensor at the given index is not of bool type: " + std::to_string(index)); } // Make sure there is enough bytes allocated to copy into. if(inputTensor->bytes < inputValues.size() * sizeof(bool)) { throw armnn::Exception("Input tensor has not been allocated to match number of input values."); } for (unsigned int i = 0; i < inputValues.size(); ++i) { inputTensor->data.b[i] = inputValues[i]; } return kTfLiteOk; } /// Run the interpreter either on TFLite Runtime or Arm NN Delegate. /// AllocateTensors() must be called before Invoke(). TfLiteStatus Invoke() { return TfLiteInterpreterInvoke(m_TfLiteInterpreter); } /// Return a buffer of values from the output tensor at a given index. /// This must be called after Invoke(). template std::vector GetOutputResult(int index) { const TfLiteTensor* outputTensor = delegateTestInterpreter::GetOutputTensorFromInterpreter(m_TfLiteInterpreter, index); int64_t n = tflite::NumElements(outputTensor); std::vector output; output.resize(n); TfLiteStatus status = TfLiteTensorCopyToBuffer(outputTensor, output.data(), output.size() * sizeof(T)); if(status != kTfLiteOk) { throw armnn::Exception("An error occurred when copying output buffer."); } return output; } /// Return a buffer of values from the output tensor at a given index. This must be called after Invoke(). /// Boolean types get converted to a bit representation in a vector. /// vector.data() returns a void pointer instead of a pointer to bool, so the tensor needs to be accessed directly. std::vector GetOutputResult(int index) { const TfLiteTensor* outputTensor = delegateTestInterpreter::GetOutputTensorFromInterpreter(m_TfLiteInterpreter, index); if(outputTensor->type != kTfLiteBool) { throw armnn::Exception("Output tensor at the given index is not of bool type: " + std::to_string(index)); } int64_t n = tflite::NumElements(outputTensor); std::vector output(n, false); output.reserve(n); for (unsigned int i = 0; i < output.size(); ++i) { output[i] = outputTensor->data.b[i]; } return output; } /// Return a buffer of dimensions from the output tensor at a given index. std::vector GetOutputShape(int index) { const TfLiteTensor* outputTensor = delegateTestInterpreter::GetOutputTensorFromInterpreter(m_TfLiteInterpreter, index); int32_t numDims = TfLiteTensorNumDims(outputTensor); std::vector dims; dims.reserve(numDims); for (int32_t i = 0; i < numDims; ++i) { dims.push_back(TfLiteTensorDim(outputTensor, i)); } return dims; } /// Delete TfLiteInterpreter and the TfLiteDelegate/TfLiteOpaqueDelegate void Cleanup(); private: TfLiteInterpreter* m_TfLiteInterpreter; /// m_TfLiteDelegate can be TfLiteDelegate or TfLiteOpaqueDelegate void* m_TfLiteDelegate; }; } // anonymous namespacearmnn-23.08/delegate/common/src/test/DelegateTestInterpreterUtils.hpp000066400000000000000000000065141446772241200260200ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace delegateTestInterpreter { inline TfLiteTensor* GetInputTensorFromInterpreter(TfLiteInterpreter* interpreter, int index) { TfLiteTensor* inputTensor = TfLiteInterpreterGetInputTensor(interpreter, index); if(inputTensor == nullptr) { throw armnn::Exception("Input tensor was not found at the given index: " + std::to_string(index)); } return inputTensor; } inline const TfLiteTensor* GetOutputTensorFromInterpreter(TfLiteInterpreter* interpreter, int index) { const TfLiteTensor* outputTensor = TfLiteInterpreterGetOutputTensor(interpreter, index); if(outputTensor == nullptr) { throw armnn::Exception("Output tensor was not found at the given index: " + std::to_string(index)); } return outputTensor; } inline TfLiteModel* CreateTfLiteModel(std::vector& data) { TfLiteModel* tfLiteModel = TfLiteModelCreate(data.data(), data.size()); if(tfLiteModel == nullptr) { throw armnn::Exception("An error has occurred when creating the TfLiteModel."); } return tfLiteModel; } inline TfLiteInterpreterOptions* CreateTfLiteInterpreterOptions() { TfLiteInterpreterOptions* options = TfLiteInterpreterOptionsCreate(); if(options == nullptr) { throw armnn::Exception("An error has occurred when creating the TfLiteInterpreterOptions."); } return options; } inline tflite::ops::builtin::BuiltinOpResolver GenerateCustomOpResolver(const std::string& opName) { tflite::ops::builtin::BuiltinOpResolver opResolver; if (opName == "MaxPool3D") { opResolver.AddCustom("MaxPool3D", tflite::ops::custom::Register_MAX_POOL_3D()); } else if (opName == "AveragePool3D") { opResolver.AddCustom("AveragePool3D", tflite::ops::custom::Register_AVG_POOL_3D()); } else { throw armnn::Exception("The custom op isn't supported by the DelegateTestInterpreter."); } return opResolver; } template inline TfLiteStatus CopyFromBufferToTensor(TfLiteTensor* tensor, std::vector& values) { // Make sure there is enough bytes allocated to copy into for uint8_t and int16_t case. if(tensor->bytes < values.size() * sizeof(T)) { throw armnn::Exception("Tensor has not been allocated to match number of values."); } // Requires uint8_t and int16_t specific case as the number of bytes is larger than values passed when creating // TFLite tensors of these types. Otherwise, use generic TfLiteTensorCopyFromBuffer function. TfLiteStatus status = kTfLiteOk; if (std::is_same::value) { for (unsigned int i = 0; i < values.size(); ++i) { tensor->data.uint8[i] = values[i]; } } else if (std::is_same::value) { for (unsigned int i = 0; i < values.size(); ++i) { tensor->data.i16[i] = values[i]; } } else { status = TfLiteTensorCopyFromBuffer(tensor, values.data(), values.size() * sizeof(T)); } return status; } } // anonymous namespacearmnn-23.08/delegate/include/000077500000000000000000000000001446772241200160475ustar00rootroot00000000000000armnn-23.08/delegate/include/DelegateOptions.hpp000066400000000000000000000006061446772241200216500ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #pragma message("armnn/delegate/include/DelegateOptions.hpp has been deprecated, it is due for removal in"\ " 24.02 release. Please include armnn/delegate/common/include/DelegateOptions.hpp instead.") armnn-23.08/delegate/include/Version.hpp000066400000000000000000000005601446772241200202060ustar00rootroot00000000000000// // Copyright © 2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #pragma message("armnn/delegate/include/Version.hpp has been deprecated, it is due for removal in"\ " 24.02 release. Please include armnn/delegate/classic/include/Version.hpp instead.") armnn-23.08/delegate/include/armnn_delegate.hpp000066400000000000000000000006051446772241200215260ustar00rootroot00000000000000// // Copyright © 2020-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #pragma message("armnn/delegate/include/armnn_delegate.hpp has been deprecated, it is due for removal in"\ " 24.02 release. Please include armnn/delegate/classic/include/armnn_delegate.hpp instead.") armnn-23.08/delegate/opaque/000077500000000000000000000000001446772241200157165ustar00rootroot00000000000000armnn-23.08/delegate/opaque/CMakeLists.txt000066400000000000000000000072101446772241200204560ustar00rootroot00000000000000# # Copyright © 2023 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # set(armnnOpaqueDelegateObject_sources) list(APPEND armnnOpaqueDelegateObject_sources include/armnn_delegate.hpp include/Version.hpp src/Activation.hpp src/ArgMinMax.hpp src/armnn_delegate.cpp src/armnn_external_delegate.cpp src/BatchMatMul.hpp src/BatchSpace.hpp src/Comparison.hpp src/Control.hpp src/Convolution.hpp src/ElementwiseBinary.hpp src/ElementwiseUnary.hpp src/FullyConnected.hpp src/Gather.hpp src/GatherNd.hpp src/LogicalBinary.hpp src/Lstm.hpp src/Normalization.hpp src/Pad.hpp src/Pooling.hpp src/Pack.hpp src/Prelu.hpp src/Redefine.hpp src/Reduce.hpp src/Resize.hpp src/ReverseV2.hpp src/Round.hpp src/Shape.hpp src/SharedFunctions.cpp src/SharedFunctions.hpp src/Slice.hpp src/Softmax.hpp src/SpaceDepth.hpp src/Split.hpp src/StridedSlice.hpp src/Tile.hpp src/Transpose.hpp src/UnidirectionalSequenceLstm.hpp src/Unpack.hpp) add_library(armnnOpaqueDelegateObject OBJECT ${armnnOpaqueDelegateObject_sources}) target_include_directories(armnnOpaqueDelegateObject PUBLIC $ $ $ PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src ${PROJECT_SOURCE_DIR}/common/src) ## Add Tflite dependency if(NOT TfLite_INCLUDE_DIR OR NOT TfLite_Schema_INCLUDE_PATH) find_package(TfLiteSrc REQUIRED MODULE) endif() # Various tflite header files are not warning clean # We can't change compilation flags on header files directly, so we need to add them to an interface library first add_library(tflite_headers_opaque INTERFACE) target_include_directories(tflite_headers_opaque INTERFACE $ $) target_compile_options(tflite_headers_opaque INTERFACE -Wno-conversion -Wno-sign-conversion -Wno-unused-parameter -Wno-unused-function) target_link_libraries(armnnOpaqueDelegateObject PUBLIC tflite_headers_opaque) ## Add Flatbuffers dependency find_package(Flatbuffers REQUIRED MODULE) target_link_libraries(armnnOpaqueDelegateObject PRIVATE ${Flatbuffers_LIB}) # include/flatbuffers/flatbuffers.h is not warning clean # We can't change compilation flags on header files directly, so we need to add them to an interface library first add_library(flatbuffer_headers_opaque INTERFACE) target_include_directories(flatbuffer_headers_opaque INTERFACE $ $) target_compile_options(flatbuffer_headers_opaque INTERFACE -Wno-sign-conversion) target_link_libraries(armnnOpaqueDelegateObject PUBLIC flatbuffer_headers_opaque) # Additional Absl Sync for Opaque Delegate find_package(TfLiteAbsl REQUIRED MODULE) target_include_directories(armnnOpaqueDelegateObject PUBLIC ${TfLite_ABSL_SYNC_HEADERS}) target_link_libraries(armnnOpaqueDelegateObject PUBLIC ${TfLite_Extra_Absl_LIB}) #################################################### ## Export targets install(TARGETS armnnOpaqueDelegateObject LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) armnn-23.08/delegate/opaque/include/000077500000000000000000000000001446772241200173415ustar00rootroot00000000000000armnn-23.08/delegate/opaque/include/Version.hpp000066400000000000000000000014601446772241200215000ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once namespace armnnOpaqueDelegate { /// Macro utils #define STRINGIFY_VALUE(s) STRINGIFY_MACRO(s) #define STRINGIFY_MACRO(s) #s // ArmNN Delegate version components #define OPAQUE_DELEGATE_MAJOR_VERSION 1 #define OPAQUE_DELEGATE_MINOR_VERSION 0 #define OPAQUE_DELEGATE_PATCH_VERSION 0 /// DELEGATE_VERSION: "X.Y.Z" /// where: /// X = Major version number /// Y = Minor version number /// Z = Patch version number #define OPAQUE_DELEGATE_VERSION STRINGIFY_VALUE(OPAQUE_DELEGATE_MAJOR_VERSION) "." \ STRINGIFY_VALUE(OPAQUE_DELEGATE_MINOR_VERSION) "." \ STRINGIFY_VALUE(OPAQUE_DELEGATE_PATCH_VERSION) } //namespace armnnDelegatearmnn-23.08/delegate/opaque/include/armnn_delegate.hpp000066400000000000000000000134271446772241200230260ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #if TF_MAJOR_VERSION > 2 || (TF_MAJOR_VERSION == 2 && TF_MINOR_VERSION > 5) #define ARMNN_POST_TFLITE_2_5 #endif namespace armnnOpaqueDelegate { struct DelegateData { DelegateData(const std::vector& backends) : m_Backends(backends) , m_Network(nullptr, nullptr) {} const std::vector m_Backends; armnn::INetworkPtr m_Network; std::vector m_OutputSlotForNode; }; /// Forward declaration for functions initializing the ArmNN Delegate ::armnnDelegate::DelegateOptions TfLiteArmnnDelegateOptionsDefault(); TfLiteOpaqueDelegate* TfLiteArmnnOpaqueDelegateCreate(const void* settings); void TfLiteArmnnOpaqueDelegateDelete(TfLiteOpaqueDelegate* tfLiteDelegate); TfLiteStatus DoPrepare(TfLiteOpaqueContext* context, TfLiteOpaqueDelegate* delegate, void* data); /// ArmNN Opaque Delegate class ArmnnOpaqueDelegate { friend class ArmnnSubgraph; public: explicit ArmnnOpaqueDelegate(armnnDelegate::DelegateOptions options); TfLiteIntArray* IdentifyOperatorsToDelegate(TfLiteOpaqueContext* context); TfLiteOpaqueDelegateBuilder* GetDelegateBuilder() { return &m_Builder; } /// Retrieve version in X.Y.Z form static const std::string GetVersion(); private: /** * Returns a pointer to the armnn::IRuntime* this will be shared by all armnn_delegates. */ armnn::IRuntime* GetRuntime(const armnn::IRuntime::CreationOptions& options) { static armnn::IRuntimePtr instance = armnn::IRuntime::Create(options); /// Instantiated on first use. return instance.get(); } TfLiteOpaqueDelegateBuilder m_Builder = { reinterpret_cast(this), // .data_ DoPrepare, // .Prepare nullptr, // .CopyFromBufferHandle nullptr, // .CopyToBufferHandle nullptr, // .FreeBufferHandle kTfLiteDelegateFlagsNone, // .flags }; /// ArmNN Runtime pointer armnn::IRuntime* m_Runtime; /// ArmNN Delegate Options armnnDelegate::DelegateOptions m_Options; }; static int TfLiteArmnnOpaqueDelegateErrno(TfLiteOpaqueDelegate* delegate) { return 0; } /// In order for the delegate to be loaded by TfLite const TfLiteOpaqueDelegatePlugin* GetArmnnDelegatePluginApi(); using tflite::delegates::DelegatePluginInterface; using TfLiteOpaqueDelegatePtr = tflite::delegates::TfLiteDelegatePtr; class ArmnnDelegatePlugin : public DelegatePluginInterface { public: static std::unique_ptr New(const tflite::TFLiteSettings& tflite_settings) { return std::make_unique(tflite_settings); } tflite::delegates::TfLiteDelegatePtr Create() override { // Use default settings until options have been enabled. return tflite::delegates::TfLiteDelegatePtr( TfLiteArmnnOpaqueDelegateCreate(nullptr), TfLiteArmnnOpaqueDelegateDelete); } int GetDelegateErrno(TfLiteOpaqueDelegate* from_delegate) override { return 0; } explicit ArmnnDelegatePlugin(const tflite::TFLiteSettings& tfliteSettings) { // Use default settings until options have been enabled. } }; /// ArmnnSubgraph class where parsing the nodes to ArmNN format and creating the ArmNN Graph class ArmnnSubgraph { public: static ArmnnSubgraph* Create(TfLiteOpaqueContext* tfLiteContext, const TfLiteOpaqueDelegateParams* parameters, const ArmnnOpaqueDelegate* delegate); TfLiteStatus Prepare(TfLiteOpaqueContext* tfLiteContext); TfLiteStatus Invoke(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode); static TfLiteStatus VisitNode(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteRegistrationExternal* tfLiteRegistration, TfLiteOpaqueNode* tfLiteNode, int nodeIndex); private: ArmnnSubgraph(armnn::NetworkId networkId, armnn::IRuntime* runtime, std::vector& inputBindings, std::vector& outputBindings) : m_NetworkId(networkId) , m_Runtime(runtime) , m_InputBindings(inputBindings) , m_OutputBindings(outputBindings) {} static TfLiteStatus AddInputLayer(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const TfLiteIntArray* inputs, std::vector& inputBindings); static TfLiteStatus AddOutputLayer(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const TfLiteIntArray* outputs, std::vector& outputBindings); /// The Network Id armnn::NetworkId m_NetworkId; /// ArmNN Runtime armnn::IRuntime* m_Runtime; /// Binding information for inputs and outputs std::vector m_InputBindings; std::vector m_OutputBindings; }; } // armnnOpaqueDelegate namespacearmnn-23.08/delegate/opaque/src/000077500000000000000000000000001446772241200165055ustar00rootroot00000000000000armnn-23.08/delegate/opaque/src/Activation.hpp000066400000000000000000000167721446772241200213340ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { std::string GetLayerName(armnn::ActivationFunction activationFunction) { std::string layerName = "ACTIVATION"; switch (activationFunction) { case armnn::ActivationFunction::Abs: layerName += " ABS"; break; case armnn::ActivationFunction::BoundedReLu: layerName += " BOUNDED_RELU"; break; case armnn::ActivationFunction::Elu: layerName += " ELU"; break; case armnn::ActivationFunction::HardSwish: layerName += " HARD_SWISH"; break; case armnn::ActivationFunction::LeakyReLu: layerName += " LEAKY_RELU"; break; case armnn::ActivationFunction::Linear: layerName += " LINEAR"; break; case armnn::ActivationFunction::ReLu: layerName += " RELU"; break; case armnn::ActivationFunction::Sigmoid: layerName += " SIGMOID"; break; case armnn::ActivationFunction::SoftReLu: layerName += " SOFT_RELU"; break; case armnn::ActivationFunction::Square: layerName += " SQUARE"; break; case armnn::ActivationFunction::Sqrt: layerName += " SQRT"; break; case armnn::ActivationFunction::TanH: layerName += " TANH"; break; default: layerName += " UNKNOWN"; } return layerName; } TfLiteStatus ValidateActivationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, armnn::ActivationDescriptor& activationDesc) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported, std::string layerName) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC(layerName.c_str(), tfLiteContext, IsActivationSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, activationDesc); }; validateFunc(outputInfo, isSupported, GetLayerName(activationDesc.m_Function)); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitActivationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::ActivationDescriptor activationDesc; switch(operatorCode) { case kTfLiteBuiltinRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } case kTfLiteBuiltinRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; break; } case kTfLiteBuiltinLogistic: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteBuiltinTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } case kTfLiteBuiltinElu: { activationDesc.m_Function = armnn::ActivationFunction::Elu; activationDesc.m_A = 1.0f; break; } case kTfLiteBuiltinHardSwish: { activationDesc.m_Function = armnn::ActivationFunction::HardSwish; break; } case kTfLiteBuiltinLeakyRelu: { // Get alpha param from builtin data auto* leakyReluParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); activationDesc.m_Function = armnn::ActivationFunction::LeakyReLu; activationDesc.m_A = leakyReluParameters->alpha; break; } default: { return kTfLiteError; } } if (!delegateData.m_Network) { return ValidateActivationOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, activationDesc); } auto layerName = GetName(activationDesc.m_Function, nodeIndex); armnn::IConnectableLayer* activationLayer = delegateData.m_Network->AddActivationLayer(activationDesc, layerName.c_str()); ARMNN_ASSERT(activationLayer != nullptr); armnn::IOutputSlot& outputSlot = activationLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(activationLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(activationLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/opaque/src/ArgMinMax.hpp000066400000000000000000000146751446772241200210560ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitArgMinMaxOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t argMinMaxOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get filter tensor. const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if(!IsValid(tfLiteAxisTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Invalid filter tensor in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. if (!IsValid(tfLiteContext, tfLiteAxisTensor, argMinMaxOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::ArgMinMaxDescriptor desc; auto* axisData = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); // Get the axis value from the input tensor switch (TfLiteOpaqueTensorType(tfLiteAxisTensor)) { case kTfLiteInt32: case kTfLiteInt64: desc.m_Axis = axisData[0]; break; default: TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Axis value data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } // If output_type is int32 then set Signed32 else Signed64. Default type is Signed64. if (argMinMaxOperatorCode == kTfLiteBuiltinArgMax) { desc.m_Function = armnn::ArgMinMaxFunction::Max; auto* argMaxParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); if (argMaxParameters->output_type != kTfLiteInt32 && argMaxParameters->output_type != kTfLiteInt64) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: output_type data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } } else { desc.m_Function = armnn::ArgMinMaxFunction::Min; auto* argMinParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); if (argMinParameters->output_type != kTfLiteInt32 && argMinParameters->output_type != kTfLiteInt64) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: output_type data type is not supported in operator #%d node #%d: ", argMinMaxOperatorCode, nodeIndex); return kTfLiteError; } } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("ARGMINMAX", tfLiteContext, IsArgMinMaxSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add an ArgMinMax layer auto layerName = GetName(desc.m_Function, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddArgMinMaxLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } }armnn-23.08/delegate/opaque/src/BatchMatMul.hpp000066400000000000000000000115041446772241200213600ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitBatchMatMulOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* kTfLiteLHSInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); const TfLiteOpaqueTensor* kTfLiteRHSInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, kTfLiteLHSInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } if (!IsValid(tfLiteContext, kTfLiteRHSInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* kTfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (IsDynamicTensor(kTfLiteOutputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& armnnLHSInputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(kTfLiteLHSInputTensor); const armnn::TensorInfo& armnnRHSInputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(kTfLiteRHSInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(kTfLiteOutputTensor, true); armnn::BatchMatMulDescriptor descriptor; auto* params = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); // Tensorflow params are called adjoint, however they are actually just transposes behind the scene. They do // not perform ajoint. descriptor.m_TransposeX = params->adj_x; descriptor.m_TransposeY = params->adj_y; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("BATCH_MATMUL", tfLiteContext, IsBatchMatMulSupported, delegateData.m_Backends, isSupported, setBackend, armnnLHSInputTensorInfo, armnnRHSInputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::BatchMatMul, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddBatchMatMulLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/BatchSpace.hpp000066400000000000000000000265641446772241200212300ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitBatchToSpaceNdOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numInputs = 3; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteBlockShapeTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteBlockShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteCropsTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteCropsTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& cropsTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteCropsTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Copy memory into block and crops std::vector blockShape(blockShapeTensorInfo.GetNumElements()); ::memcpy(blockShape.data(), TfLiteOpaqueTensorData(tfLiteBlockShapeTensor), blockShapeTensorInfo.GetNumBytes()); std::vector cropsVector(cropsTensorInfo.GetNumElements()); std::memcpy(cropsVector.data(), TfLiteOpaqueTensorData(tfLiteCropsTensor), cropsTensorInfo.GetNumBytes()); size_t step = 2; std::vector> crops; for (unsigned int i = 0; i < cropsTensorInfo.GetNumElements() / step; ++i) { crops.emplace_back(cropsVector[i * step], cropsVector[i * step + 1]); } // Make a descriptor armnn::BatchToSpaceNdDescriptor descriptor; descriptor.m_BlockShape = blockShape; descriptor.m_Crops = crops; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("BATCH_TO_SPACE_ND", tfLiteContext, IsBatchToSpaceNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitBatchToSpaceNdOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a BatchToSpace layer auto layerName = GetName(armnn::LayerType::BatchToSpaceNd, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddBatchToSpaceNdLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitSpaceToBatchNdOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numInputs = 3; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext,inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteBlockShapeTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteBlockShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLitePadListTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLitePadListTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& padListTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLitePadListTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); std::vector blockShape(blockShapeTensorInfo.GetNumElements()); std::memcpy(blockShape.data(), TfLiteOpaqueTensorData(tfLiteBlockShapeTensor), blockShapeTensorInfo.GetNumBytes()); std::vector padListVector(padListTensorInfo.GetNumElements()); std::memcpy(padListVector.data(), TfLiteOpaqueTensorData(tfLitePadListTensor), padListTensorInfo.GetNumBytes()); size_t step = 2; std::vector> padList; for (unsigned int i = 0; i < padListTensorInfo.GetNumElements() / step; ++i) { padList.emplace_back(padListVector[i * step], padListVector[i * step + 1]); } armnn::SpaceToBatchNdDescriptor descriptor; descriptor.m_BlockShape = blockShape; descriptor.m_PadList = padList; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SPACE_TO_BATCH_ND", tfLiteContext, IsSpaceToBatchNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitSpaceToBatchNdOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a SpaceToBatch layer auto layerName = GetName(armnn::LayerType::SpaceToBatchNd, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSpaceToBatchNdLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespacearmnn-23.08/delegate/opaque/src/Comparison.hpp000066400000000000000000000133621446772241200213350ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { std::string GetOperationName(armnn::ComparisonOperation comparisonOperation) { std::string layerName = "COMPARISON"; switch (comparisonOperation) { case armnn::ComparisonOperation::NotEqual: layerName += " NOT_EQUAL"; break; case armnn::ComparisonOperation::Equal: layerName += " EQUAL"; break; case armnn::ComparisonOperation::Greater: layerName += " GREATER"; break; case armnn::ComparisonOperation::GreaterOrEqual: layerName += " GREATER_OR_EQUAL"; break; case armnn::ComparisonOperation::Less: layerName += " LESS"; break; case armnn::ComparisonOperation::LessOrEqual: layerName += " LESS_OR_EQUAL"; break; default: layerName += " UNKNOWN"; } return layerName; } TfLiteStatus VisitComparisonOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteComparisonOperatorCode, armnn::ComparisonOperation comparisonOperation) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensors. const TfLiteOpaqueTensor* tfLiteInputTensor0 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor0, tfLiteComparisonOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor1 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteInputTensor1, tfLiteComparisonOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use output indices to get output tensor. const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteComparisonOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of the input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } armnn::ComparisonDescriptor descriptor(comparisonOperation); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported, std::string layerName) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC(layerName.c_str(), tfLiteContext, IsComparisonSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, inputTensorInfo1, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported, GetOperationName(comparisonOperation)); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(descriptor.m_Operation, nodeIndex); armnn::IConnectableLayer* comparisonLayer = delegateData.m_Network->AddComparisonLayer(descriptor, layerName.c_str()); comparisonLayer->SetBackendId(setBackend); ARMNN_ASSERT(comparisonLayer != nullptr); armnn::IOutputSlot& outputSlot = comparisonLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(comparisonLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(comparisonLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Control.hpp000066400000000000000000000310301446772241200206330ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitConcatenationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteConcatOperatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } std::vector inputTensorInfos; for (int i = 0; i < numInputs; ++i) { const TfLiteOpaqueTensor* inputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[i]); if (!IsValid(tfLiteContext, inputTensor, tfLiteConcatOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(inputTensor); inputTensorInfos.emplace_back(inputTensorInfo); } // Convert input tensors to const armnn::TensorInfo* type for FORWARD_LAYER_SUPPORT_FUNC. std::vector inputConstTensorInfos; std::transform(inputTensorInfos.begin(), inputTensorInfos.end(), std::back_inserter(inputConstTensorInfos), [](armnn::TensorInfo& t)->const armnn::TensorInfo*{ return &t; }); // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteConcatOperatorCode, nodeIndex)) { return kTfLiteError; } // Setup OriginsDescriptor, axis and view origin auto numConcatView = static_cast(numInputs); uint32_t inputRank = TfLiteOpaqueTensorNumDims(TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0])); auto* concatenationParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); if(!concatenationParameters) { throw armnn::Exception(&"TfLiteArmnnOpaqueDelegate: Concat parameters are null in: " [ nodeIndex ]); } const auto concatDimInput = static_cast( (static_cast(inputRank) + concatenationParameters->axis) % static_cast(inputRank)); armnn::OriginsDescriptor concatDescriptor(static_cast(numConcatView), inputRank); concatDescriptor.SetConcatAxis(concatDimInput); unsigned int mergeDimOrigin = 0; for (unsigned int viewIndex = 0; viewIndex < numConcatView; ++viewIndex) { armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[viewIndex])); // Sets up concatDescriptor view origin SetupConcatViewOrigin(inputTensorInfo, concatDescriptor, concatDimInput, viewIndex, mergeDimOrigin); } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Verify we support the fused activation before attempting to create a layer TfLiteFusedActivation activationType = concatenationParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("CONCATENATION", tfLiteContext, IsConcatSupported, delegateData.m_Backends, isSupported, setBackend, inputConstTensorInfos, outputTensorInfo, concatDescriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Setup layer and connect. auto layerName = GetName(armnn::LayerType::Concat, nodeIndex); armnn::IConnectableLayer* concatenationLayer = delegateData.m_Network->AddConcatLayer(concatDescriptor, layerName.c_str()); concatenationLayer->SetBackendId(setBackend); ARMNN_ASSERT(concatenationLayer != nullptr); // Connect the Constant Inputs auto inputsTensorsProcess = ProcessInputs(concatenationLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } armnn::IOutputSlot& outputSlot = concatenationLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(concatenationLayer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (activationType == kTfLiteActNone) { // No Activation return kTfLiteOk; } // Check and Create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, concatenationLayer, 0, delegateData, nodeIndex); } TfLiteStatus VisitMeanOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteMeanOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteMeanOperatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get axis tensor. const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteAxisTensor, tfLiteMeanOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteMeanOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteAxisTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* axisTensorData = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); std::vector axis; // Add axis data to vector to be converter to unsigned int and assigned to descriptor axis. for (unsigned int i = 0; i < axisTensorInfo.GetNumElements(); ++i) { axis.emplace_back(axisTensorData[i]); } // Convert the axis to unsigned int and remove duplicates. unsigned int rank = inputTensorInfo.GetNumDimensions(); std::set uniqueAxis; std::transform(axis.begin(), axis.end(), std::inserter(uniqueAxis, uniqueAxis.begin()), [rank](int i)->unsigned int{ return (i + rank) % rank; }); // Setup MeanDescriptor and assign axis and keepDims armnn::MeanDescriptor desc; desc.m_Axis.assign(uniqueAxis.begin(), uniqueAxis.end()); desc.m_KeepDims = inputTensorInfo.GetNumDimensions() == outputTensorInfo.GetNumDimensions() ? true : false; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("MEAN", tfLiteContext, IsMeanSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Setup layer and connect. auto layerName = GetName(armnn::LayerType::Mean, nodeIndex); armnn::IConnectableLayer* meanLayer = delegateData.m_Network->AddMeanLayer(desc, layerName.c_str()); meanLayer->SetBackendId(setBackend); ARMNN_ASSERT(meanLayer != nullptr); armnn::IOutputSlot& outputSlot = meanLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(meanLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(meanLayer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitControlOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { switch(operatorCode) { case kTfLiteBuiltinConcatenation: return VisitConcatenationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinMean: return VisitMeanOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); default: return kTfLiteError; } } } // namespace armnnDelegate armnn-23.08/delegate/opaque/src/Convolution.hpp000066400000000000000000001115431446772241200215420ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include #include #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitConv2dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get filter tensor. const TfLiteOpaqueTensor* tfLiteFilterTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteFilterTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } armnn::TensorInfo biasTensorInfo; const TfLiteOpaqueTensor* tfLiteBiasTensor = nullptr; bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); if(biasEnabled) { // Use input indices to get bias tensor. tfLiteBiasTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::Optional optionalBiasInfo(biasTensorInfo); armnn::Convolution2dDescriptor descriptor; descriptor.m_BiasEnabled = biasEnabled; descriptor.m_StrideX = NonNegative(tfLiteNodeParameters->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(tfLiteNodeParameters->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_DilationX = NonNegative(tfLiteNodeParameters->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(tfLiteNodeParameters->dilation_height_factor, nodeIndex); // TfLite uses NHWC tensors const unsigned int inputHeight = inputTensorInfo.GetShape()[1]; const unsigned int inputWidth = inputTensorInfo.GetShape()[2]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, tfLiteNodeParameters->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, tfLiteNodeParameters->padding); armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("CONV2D", tfLiteContext, IsConvolution2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, optionalBiasInfo); return isSupported ? kTfLiteOk : kTfLiteError; } // Set up filter and biases auto layerName = GetName(armnn::LayerType::Convolution2d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddConvolution2dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); if(filterTensorInfo.IsConstant()) { auto filter = CreateConstTensor(tfLiteFilterTensor, filterTensorInfo); auto filterName = GetName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if (biasEnabled) { if (biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(tfLiteBiasTensor, biasTensorInfo); auto biasName = GetName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if (inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); auto inputName = GetName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if (Connect(layer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get filter tensor. const TfLiteOpaqueTensor* tfLiteFilterTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteFilterTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } armnn::TensorInfo biasTensorInfo; const TfLiteOpaqueTensor* tfLiteBiasTensor = nullptr; bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); if(biasEnabled) { // Use input indices to get bias tensor. tfLiteBiasTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::DepthwiseConvolution2dDescriptor descriptor; descriptor.m_BiasEnabled = biasEnabled; descriptor.m_StrideX = NonNegative(tfLiteNodeParameters->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(tfLiteNodeParameters->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_DilationX = NonNegative(tfLiteNodeParameters->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(tfLiteNodeParameters->dilation_height_factor, nodeIndex); // Assuming input is NHWC unsigned int inputHeight = inputTensorInfo.GetShape()[1]; unsigned int inputWidth = inputTensorInfo.GetShape()[2]; // TensorflowLite weights come in the format [1, H, W, I * M] unsigned int filterHeight = filterTensorInfo.GetShape()[1]; unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, tfLiteNodeParameters->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, tfLiteNodeParameters->padding); armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("DEPTHWISE_CONV2D", tfLiteContext, IsDepthwiseConvolutionSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, armnn::Optional(biasTensorInfo)); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::DepthwiseConvolution2d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddDepthwiseConvolution2dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); if(filterTensorInfo.IsConstant()) { // For depthwise the weights layout is the same as for tflite [1, H, W, I*M]. No permutation required. auto filter = CreateConstTensor(tfLiteFilterTensor, filterTensorInfo); auto filterName = GetName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if (biasEnabled) { if(biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(tfLiteBiasTensor, biasTensorInfo); auto biasName = GetName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); auto inputName = GetName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if(Connect(layer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } TfLiteStatus VisitConv3dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); armnn::Convolution3dDescriptor descriptor; auto* params = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_DataLayout = armnn::DataLayout::NDHWC; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(params->stride_height, nodeIndex); descriptor.m_StrideZ = NonNegative(params->stride_depth, nodeIndex); descriptor.m_DilationX = NonNegative(params->dilation_width_factor, nodeIndex); descriptor.m_DilationY = NonNegative(params->dilation_height_factor, nodeIndex); descriptor.m_DilationZ = NonNegative(params->dilation_depth_factor, nodeIndex); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get filter tensor. const TfLiteOpaqueTensor* tfLiteFilterTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType=kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteFilterTensor); armnn::TensorInfo biasTensorInfo; const TfLiteOpaqueTensor* tfLiteBiasTensor = nullptr; if (biasEnabled) { // Use input indices to get bias tensor. tfLiteBiasTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::Optional optionalBiasInfo(biasTensorInfo); // TfLite uses NDHWC tensors const unsigned int inputDepth = inputTensorInfo.GetShape()[1]; const unsigned int inputHeight = inputTensorInfo.GetShape()[2]; const unsigned int inputWidth = inputTensorInfo.GetShape()[3]; // Assuming the filter is DHWIO : Depth, Height, Width, OutputChannels, InputChannels const unsigned int filterDepth = filterTensorInfo.GetShape()[0]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // Calculate padding CalcPadding(inputDepth, filterDepth, descriptor.m_StrideZ, descriptor.m_DilationZ, descriptor.m_PadFront, descriptor.m_PadBack, params->padding); CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, descriptor.m_DilationY, descriptor.m_PadTop, descriptor.m_PadBottom, params->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, descriptor.m_DilationX, descriptor.m_PadLeft, descriptor.m_PadRight, params->padding); // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitConvolutionOperator will be called again to add the layer to the network as seen below. armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("CONV3D", tfLiteContext, IsConvolution3dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, optionalBiasInfo); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Convolution3d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddConvolution3dLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Add a constant layer for weights and biases if inputs are constant, // which are connected to the Convolution3d layer as inputs. if (filterTensorInfo.IsConstant()) { auto filter = CreateConstTensor(tfLiteFilterTensor, filterTensorInfo); auto filterName = GetName(armnn::LayerType::Constant, nodeIndex, "Filter"); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter, filterName.c_str()); ARMNN_ASSERT(weightsLayer != nullptr); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); } if (biasEnabled) { if (biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(tfLiteBiasTensor, biasTensorInfo); auto biasName = GetName(armnn::LayerType::Constant, nodeIndex, "Bias"); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor, biasName.c_str()); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if (inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); auto inputName = GetName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); if (Connect(layer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } TfLiteStatus VisitTransposeConv2dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); armnn::TransposeConvolution2dDescriptor descriptor; auto* parameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_BiasEnabled = false; descriptor.m_StrideX = NonNegative(parameters->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(parameters->stride_height, nodeIndex); descriptor.m_DataLayout = armnn::DataLayout::NHWC; auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputShapeTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputShapeTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteFilterTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteFilterTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); const armnn::TensorInfo& filterTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteFilterTensor); // TfLite uses NHWC tensors const unsigned int inputHeight = inputTensorInfo.GetShape()[1]; const unsigned int inputWidth = inputTensorInfo.GetShape()[2]; const unsigned int filterHeight = filterTensorInfo.GetShape()[1]; const unsigned int filterWidth = filterTensorInfo.GetShape()[2]; // This block determines the output shape of the transpose convolution. // If the output shape tensor is a constant, we can access the data at load time and set the shape of the layer. // If this is not constant, we do not have access to the shape data, so we have to use infer output shape. if (IsConstantTensor(tfLiteOutputShapeTensor)) { const armnn::TensorInfo outputShapeTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputShapeTensor); std::vector outputShape(outputShapeTensorInfo.GetNumElements()); if (outputShapeTensorInfo.GetDataType() == armnn::DataType::Signed32) { for(unsigned int i=0; i < outputShapeTensorInfo.GetNumElements(); ++i) { outputShape[i] = static_cast(TfLiteOpaqueTensorData(tfLiteOutputShapeTensor))[i]; } } if (outputShapeTensorInfo.GetDataType() == armnn::DataType::QAsymmU8) { for(unsigned int i=0; i < outputShapeTensorInfo.GetNumElements(); ++i) { outputShape[i] = static_cast(TfLiteOpaqueTensorData(tfLiteOutputShapeTensor))[i]; } } // Change from signed to unsigned int to store in TransposeConvolution2dDescriptor. for (int dimension : outputShape) { descriptor.m_OutputShape.push_back(static_cast(dimension)); } descriptor.m_OutputShapeEnabled = true; // TfLite uses NHWC tensors const unsigned int outputHeight = descriptor.m_OutputShape[1]; const unsigned int outputWidth = descriptor.m_OutputShape[2]; CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, 1, // DilationY descriptor.m_PadTop, descriptor.m_PadBottom, parameters->padding, outputHeight); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, 1, // DilationX descriptor.m_PadLeft, descriptor.m_PadRight, parameters->padding, outputWidth); } else { CalcPadding(inputHeight, filterHeight, descriptor.m_StrideY, 1, // DilationY descriptor.m_PadTop, descriptor.m_PadBottom, parameters->padding); CalcPadding(inputWidth, filterWidth, descriptor.m_StrideX, 1, // DilationX descriptor.m_PadLeft, descriptor.m_PadRight, parameters->padding); } // Set up filter auto filterTensor = CreateConstTensor(tfLiteFilterTensor, filterTensorInfo); armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("TRANSPOSE_CONV2D", tfLiteContext, IsTransposeConvolution2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor, filterTensorInfo, armnn::EmptyOptional()); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::TransposeConvolution2d, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddTransposeConvolution2dLayer(descriptor, filterTensor, armnn::EmptyOptional(), layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // The data input can be constant, so we must check that this is allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); auto inputName = GetName(armnn::LayerType::Constant, nodeIndex, "Input"); armnn::IConnectableLayer *inputLayer = delegateData.m_Network->AddConstantLayer(input, inputName.c_str()); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect if (delegateData.m_OutputSlotForNode[static_cast(inputTensors[2])] != nullptr) { delegateData.m_OutputSlotForNode[static_cast(inputTensors[2])]-> Connect(layer->GetInputSlot(0)); } if (Connect(layer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } return kTfLiteOk; } TfLiteStatus VisitConvolutionOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { switch(operatorCode) { case kTfLiteBuiltinConv2d: return VisitConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinConv3d: return VisitConv3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinDepthwiseConv2d: return VisitDepthwiseConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); case kTfLiteBuiltinTransposeConv: return VisitTransposeConv2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, operatorCode); default: return kTfLiteError; } } }armnn-23.08/delegate/opaque/src/ElementwiseBinary.hpp000066400000000000000000000567371446772241200226660ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateAddOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { std::vector infos { inputInfo1, inputInfo2, outputInfo }; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("ADD", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputInfo, armnn::BinaryOperation::Add); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateDivOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("DIV", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Div); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateFloorDivOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { // need first to validate that the div operator is supported // then that the floor operator is supported TfLiteStatus status = ValidateDivOperator(delegateData, tfLiteContext, inputInfo1, inputInfo2, outputInfo); if (status != kTfLiteOk) { return status; } // if the inputs and output of the div are all Signed32 we don't need to add the floor operator afterward. if (AreAllSigned32(inputInfo1, inputInfo2, outputInfo)) { return status; } // in case broadcasting is being done from one of the inputs to the div // choose the full sized input tensor to pass to the floor validation routine armnn::TensorInfo floorInputInfo = inputInfo1; if (inputInfo1.GetNumDimensions() < inputInfo2.GetNumDimensions()) { floorInputInfo = inputInfo2; } status = ValidateFloorOperator(delegateData, tfLiteContext, floorInputInfo, outputInfo); return status; } TfLiteStatus ValidateMaximumOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("MAXIMUM", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Maximum); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateMinimumOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("MINIMUM", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Minimum); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateMulOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("MUL", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Mul); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidatePowerOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("POWER", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Power); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateSquaredDifferenceOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SQUAREDDIFFERENCE", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::SqDiff); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateSubOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& inputInfo2, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SUB", tfLiteContext, IsElementwiseBinarySupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo1, inputInfo2, outputTensorInfo, armnn::BinaryOperation::Sub); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } std::pair AddFloorDivLayer( DelegateData& delegateData, const armnn::TensorInfo& outputTensorInfo, int nodeIndex) { auto layerName = GetName(armnn::BinaryOperation::Div, nodeIndex); armnn::IConnectableLayer* divisionLayer = delegateData.m_Network->AddElementwiseBinaryLayer( armnn::BinaryOperation::Div, layerName.c_str()); // if the output of the div is Signed32 the Floor layer is not required if (armnn::DataType::Signed32 == outputTensorInfo.GetDataType()) { return std::make_pair(divisionLayer, divisionLayer); } armnn::IOutputSlot& outputSlot = divisionLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto floorName = GetName(armnn::LayerType::Floor, nodeIndex); armnn::IConnectableLayer* floorLayer = delegateData.m_Network->AddFloorLayer(floorName.c_str()); outputSlot.Connect(floorLayer->GetInputSlot(0)); return std::make_pair(divisionLayer, floorLayer); } TfLiteStatus VisitElementwiseBinaryOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t elementwiseBinaryOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get Input Tensors auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor0 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor0, elementwiseBinaryOperatorCode, nodeIndex)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Invalid input tensor in operator #%d node #%d: ", elementwiseBinaryOperatorCode, nodeIndex); return kTfLiteError; } // Use input indices to get filter tensor. const TfLiteOpaqueTensor* tfLiteInputTensor1 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if(!IsValid(tfLiteInputTensor1)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Invalid input tensor in operator #%d node #%d: ", elementwiseBinaryOperatorCode, nodeIndex); return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, elementwiseBinaryOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of the input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } if (!delegateData.m_Network) { switch(elementwiseBinaryOperatorCode) { case kTfLiteBuiltinAdd: return ValidateAddOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinDiv: return ValidateDivOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinFloorDiv: return ValidateFloorDivOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMaximum: return ValidateMaximumOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMinimum: return ValidateMinimumOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinMul: return ValidateMulOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinPow: return ValidatePowerOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinSquaredDifference: return ValidateSquaredDifferenceOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); case kTfLiteBuiltinSub: return ValidateSubOperator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); default: return kTfLiteError; } } armnn::IConnectableLayer* elementwiseBinaryLayer = nullptr; armnnDelegate::MultiLayerFacade multiLayer; std::string layerName; switch(elementwiseBinaryOperatorCode) { case kTfLiteBuiltinAdd: layerName = GetName(armnn::BinaryOperation::Add, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Add, layerName.c_str()); break; case kTfLiteBuiltinDiv: layerName = GetName(armnn::BinaryOperation::Div, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Div, layerName.c_str()); break; case kTfLiteBuiltinFloorDiv: { auto layers = AddFloorDivLayer(delegateData, outputTensorInfo, nodeIndex); multiLayer.AssignValues(layers.first, layers.second); elementwiseBinaryLayer = &multiLayer; } break; case kTfLiteBuiltinMaximum: layerName = GetName(armnn::BinaryOperation::Maximum, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Maximum, layerName.c_str()); break; case kTfLiteBuiltinMinimum: layerName = GetName(armnn::BinaryOperation::Minimum, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Minimum, layerName.c_str()); break; case kTfLiteBuiltinMul: layerName = GetName(armnn::BinaryOperation::Mul, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Mul, layerName.c_str()); break; case kTfLiteBuiltinPow: layerName = GetName(armnn::BinaryOperation::Power, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Power, layerName.c_str()); break; case kTfLiteBuiltinSquaredDifference: layerName = GetName(armnn::BinaryOperation::SqDiff, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::SqDiff, layerName.c_str()); break; case kTfLiteBuiltinSub: layerName = GetName(armnn::BinaryOperation::Sub, nodeIndex); elementwiseBinaryLayer = delegateData.m_Network->AddElementwiseBinaryLayer(armnn::BinaryOperation::Sub, layerName.c_str()); break; default: return kTfLiteError; } ARMNN_ASSERT(elementwiseBinaryLayer != nullptr); armnn::IOutputSlot& outputSlot = elementwiseBinaryLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(elementwiseBinaryLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } if(Connect(elementwiseBinaryLayer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create Activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, elementwiseBinaryLayer, 0, delegateData, nodeIndex); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/ElementwiseUnary.hpp000066400000000000000000000122361446772241200225220ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "OpaqueDelegateUtils.hpp" namespace armnnOpaqueDelegate { std::string GetLayerName(armnn::UnaryOperation unaryOperation) { std::string layerName = "ELEMENTWISE_UNARY"; switch (unaryOperation) { case armnn::UnaryOperation::Abs: layerName += " ABS"; break; case armnn::UnaryOperation::Ceil: layerName += " CEIL"; break; case armnn::UnaryOperation::Exp: layerName += " EXP"; break; case armnn::UnaryOperation::Log: layerName += " LOG"; break; case armnn::UnaryOperation::LogicalNot: layerName += " LOGICALNOT"; break; case armnn::UnaryOperation::Neg: layerName += " NEG"; break; case armnn::UnaryOperation::Rsqrt: layerName += " RSQRT"; break; case armnn::UnaryOperation::Sin: layerName += " SIN"; break; case armnn::UnaryOperation::Sqrt: layerName += " SQRT"; break; default: layerName += " UNKNOWN"; } return layerName; } TfLiteStatus VisitElementwiseUnaryOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteElementWiseUnaryOperatorCode, armnn::UnaryOperation unaryOperation) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensor. const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteElementWiseUnaryOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensor. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use output indices to get output tensor. const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteElementWiseUnaryOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::ElementwiseUnaryDescriptor descriptor(unaryOperation); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported, std::string layerName) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC(layerName.c_str(), tfLiteContext, IsElementwiseUnarySupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported, GetLayerName(unaryOperation)); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(descriptor.m_Operation, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddElementwiseUnaryLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Fill.hpp000066400000000000000000000126421446772241200201110ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitFillOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteFillOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); switch(tfLiteFillOperatorCode) { case kTfLiteBuiltinFill: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); break; default: return kTfLiteError; } // Inputs int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteFillTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteFillTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteFillOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::FillDescriptor descriptor; switch (TfLiteOpaqueTensorType(tfLiteFillTensor)) { case kTfLiteFloat32: descriptor.m_Value = *static_cast(TfLiteOpaqueTensorData(tfLiteFillTensor)); break; case kTfLiteInt32: descriptor.m_Value = *static_cast(TfLiteOpaqueTensorData(tfLiteFillTensor)); break; default: TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: FILL value data type is not supported in operator #%d node #%d: ", tfLiteFillOperatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("FILL", tfLiteContext, IsFillSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Fill, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFillLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnDelegate armnn-23.08/delegate/opaque/src/FullyConnected.hpp000066400000000000000000000271711446772241200221440ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitFullyConnectedOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteWeightsTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteWeightsTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& weightsTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteWeightsTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Check that we support fused activation before we attempt to create a layer auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType=kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } // Fully Connected Layer accepts two dimensional weights input int32_t weightsDimension = static_cast(weightsTensorInfo.GetNumDimensions()); if (weightsDimension != 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dimension #$d for Fully Connected weights is not supported by Armnn" " in operator #%d node #%d: ", weightsDimension, operatorCode, nodeIndex); return kTfLiteError; } armnn::TensorInfo biasTensorInfo; const TfLiteOpaqueTensor* tfLiteBiasTensor = nullptr; bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); if (biasEnabled) { // Use input indices to get bias tensor. tfLiteBiasTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteBiasTensor, operatorCode, nodeIndex)) { return kTfLiteError; } biasTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteBiasTensor); } else { biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } armnn::TensorInfo reshapedTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); if (inputTensorInfo.GetNumDimensions() > 2) { // Calculate reshape to flatten to 2D [batch_size, input_size] std::vector reshapedDimensions(2); reshapedDimensions[1] = weightsTensorInfo.GetShape()[1]; reshapedDimensions[0] = inputTensorInfo.GetNumElements() / reshapedDimensions[1]; if (inputTensorInfo.GetNumElements() % reshapedDimensions[1] != 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Failed to deduce input tensor shape from filter size #%d #%d node #%d: ", reshapedDimensions[1], operatorCode, nodeIndex); return kTfLiteError; } reshapedTensorInfo.SetShape(armnn::TensorShape{ 2, reshapedDimensions.data() }); } armnn::TensorInfo reshapedOutputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor); if (outputTensorInfo.GetNumDimensions() > 2) { // Calculate reshape to flatten to 2D [batch_size, input_size] std::vector reshapedDimensions(2); reshapedDimensions[1] = weightsTensorInfo.GetShape()[0]; reshapedDimensions[0] = outputTensorInfo.GetNumElements() / reshapedDimensions[1]; if (outputTensorInfo.GetNumElements() % reshapedDimensions[1] != 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Failed to deduce output tensor shape from filter size #%d #%d node #%d: ", reshapedDimensions[1], operatorCode, nodeIndex); return kTfLiteError; } reshapedOutputTensorInfo.SetShape(armnn::TensorShape{ 2, reshapedDimensions.data() }); } armnn::FullyConnectedDescriptor descriptor; descriptor.m_TransposeWeightMatrix = true; descriptor.m_BiasEnabled = biasEnabled; descriptor.m_ConstantWeights = weightsTensorInfo.IsConstant(); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("FULLY_CONNECTED", tfLiteContext, IsFullyConnectedSupported, delegateData.m_Backends, isSupported, setBackend, reshapedTensorInfo, outputTensorInfo, weightsTensorInfo, biasTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(reshapedOutputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::FullyConnected, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFullyConnectedLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Add a constant layer for weights and biases if inputs are constant. if (weightsTensorInfo.IsConstant()) { auto weightsTensor = CreateConstTensor(tfLiteWeightsTensor, weightsTensorInfo); armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(weightsTensor); weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); weightsLayer->GetOutputSlot(0).SetTensorInfo(weightsTensorInfo); } if (biasEnabled) { if(biasTensorInfo.IsConstant()) { auto biasTensor = CreateConstTensor(tfLiteBiasTensor, biasTensorInfo); armnn::IConnectableLayer* biasLayer = delegateData.m_Network->AddConstantLayer(biasTensor); ARMNN_ASSERT(biasLayer != nullptr); biasLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(2u)); biasLayer->GetOutputSlot(0).SetTensorInfo(biasTensorInfo); } } // The data input can also be constant, so we must check that this is also allocated to an input slot if(inputTensorInfo.IsConstant()) { auto input = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); armnn::IConnectableLayer* inputLayer = delegateData.m_Network->AddConstantLayer(input); inputLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0u)); inputLayer->GetOutputSlot(0).SetTensorInfo(inputTensorInfo); } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); armnn::IConnectableLayer* reshapeLayer = nullptr; if (inputTensorInfo.GetNumDimensions() > 2) { // Add reshape to flatten to 2D [batch_size, input_size] armnn::ReshapeDescriptor reshapeDescriptor; reshapeDescriptor.m_TargetShape = reshapedTensorInfo.GetShape(); reshapeLayer = delegateData.m_Network->AddReshapeLayer(reshapeDescriptor); ARMNN_ASSERT(reshapeLayer != nullptr); reshapeLayer->GetOutputSlot(0).SetTensorInfo(reshapedTensorInfo); // Connect delegateData.m_OutputSlotForNode[inputTensors[0]]->Connect(reshapeLayer->GetInputSlot(0)); reshapeLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(0)); if (!descriptor.m_ConstantWeights) { delegateData.m_OutputSlotForNode[inputTensors[1]]->Connect(layer->GetInputSlot(1)); } if (biasEnabled && !biasTensorInfo.IsConstant()) { delegateData.m_OutputSlotForNode[inputTensors[2]]->Connect(layer->GetInputSlot(2)); } delegateData.m_OutputSlotForNode[outputTensors[0]] = &outputSlot; } if (reshapeLayer == nullptr) { if(Connect(layer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } } if (outputTensorInfo.GetNumDimensions() > 2) { layer = AddReshapeLayer(tfLiteContext, tfLiteNode, layer, reshapedOutputTensorInfo, outputTensorInfo, delegateData, nodeIndex); if (!layer) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Failed to add reshape for FullyConnected #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } } if (!tfLiteNodeParameters) { // No Activation return kTfLiteOk; } // Check and Create Activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, layer, 0, delegateData, nodeIndex); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Gather.hpp000066400000000000000000000127131446772241200204340ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitGatherOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteIndicesTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteIndicesTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); auto axis = tfLiteNodeParameters->axis; const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteIndicesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::GatherDescriptor gatherDescriptor; gatherDescriptor.m_Axis = axis; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); auto indicesDimensions = indicesTensorInfo.GetNumDimensions(); auto outputDimensions = outputTensorInfo.GetNumDimensions(); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Operation has invalid axis: %d. It is out of bounds [-%d, %d))", axis, inputDimensions, inputDimensions); return kTfLiteError; } if (outputDimensions != static_cast(inputDimensions) + indicesDimensions - 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Operation has invalid output dimensions: %d. " "Output must be an (%d + %d - 1)-D tensor", outputDimensions, inputDimensions, indicesDimensions); return kTfLiteError; } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("GATHER", tfLiteContext, IsGatherSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, indicesTensorInfo, outputTensorInfo, gatherDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Gather, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddGatherLayer(gatherDescriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/GatherNd.hpp000066400000000000000000000102351446772241200207130ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitGatherNdOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteIndicesTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteIndicesTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteIndicesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("GATHER_ND", tfLiteContext, IsGatherNdSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, indicesTensorInfo, outputTensorInfo); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::GatherNd, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddGatherNdLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/LogicalBinary.hpp000066400000000000000000000131311446772241200217340ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { std::string GetLayerName(armnn::LogicalBinaryOperation logicalBinaryOperation) { std::string layerName = "LOGICAL_BINARY"; switch (logicalBinaryOperation) { case armnn::LogicalBinaryOperation::LogicalAnd: layerName += " LOGICAL_AND"; break; case armnn::LogicalBinaryOperation::LogicalOr: layerName += " LOGICAL_OR"; break; default: layerName += " UNKNOWN"; } return layerName; } TfLiteStatus VisitLogicalBinaryOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t logicalOperatorCode, armnn::LogicalBinaryOperation binaryOperation) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensors. const TfLiteOpaqueTensor* tfLiteInputTensor0 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor0, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor1 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteInputTensor1, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use output indices to get output tensor. const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, logicalOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor1); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Check if we need to expand the dims of any input tensor infos. // This is required for a few of the backends. if(inputTensorInfo0.GetNumDimensions() != inputTensorInfo1.GetNumDimensions()) { ExpandTensorRankToEqual(inputTensorInfo0, inputTensorInfo1); } // Setup descriptor and assign operation armnn::LogicalBinaryDescriptor desc; desc.m_Operation = binaryOperation; // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported, std::string layerName) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC(layerName.c_str(), tfLiteContext, IsLogicalBinarySupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, inputTensorInfo1, outputTensorInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported, GetLayerName(binaryOperation)); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(desc.m_Operation, nodeIndex); armnn::IConnectableLayer* logicalBinaryLayer = delegateData.m_Network->AddLogicalBinaryLayer(desc, layerName.c_str()); logicalBinaryLayer->SetBackendId(setBackend); ARMNN_ASSERT(logicalBinaryLayer != nullptr); armnn::IOutputSlot& outputSlot = logicalBinaryLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(logicalBinaryLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(logicalBinaryLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Lstm.hpp000066400000000000000000000311251446772241200201370ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitLstmOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Set the params structure for the AddLstmLayer call armnn::LstmInputParams params; if (IsOptionalOperandPresent(tfLiteNode, 1)) { params.m_InputToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 1); } params.m_InputToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 2); params.m_InputToCellWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 3); params.m_InputToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 4); // Recurrent weight tensors of size {n_cell, n_output} if (IsOptionalOperandPresent(tfLiteNode, 5)) { params.m_RecurrentToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 5); } params.m_RecurrentToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 6); params.m_RecurrentToCellWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 7); params.m_RecurrentToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 8); // Peephole weights tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 9)) { params.m_CellToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 9); } if (IsOptionalOperandPresent(tfLiteNode, 10)) { params.m_CellToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 10); } if (IsOptionalOperandPresent(tfLiteNode, 11)) { params.m_CellToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 11); } // Gates bias tensors of size {n_cell} if (IsOptionalOperandPresent(tfLiteNode, 12)) { params.m_InputGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 12); } params.m_ForgetGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 13); params.m_CellBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 14); params.m_OutputGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 15); // Projection weight tensor of size {n_output, n_cell} if (IsOptionalOperandPresent(tfLiteNode, 16)) { params.m_ProjectionWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 16); } // Projection bias tensor of size {n_output} if (IsOptionalOperandPresent(tfLiteNode, 17)) { params.m_ProjectionBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 17); } // These state tensors are defined as variable tensors, and will be modified by this op. const TfLiteOpaqueTensor* tfLiteOutputStateIn = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[18]); if (!IsValid(tfLiteContext, tfLiteOutputStateIn, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* cellStateIn = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[19]); if (!IsValid(tfLiteContext, cellStateIn, operatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo outputStateInInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputStateIn); armnn::TensorInfo cellStateInInfo = GetTensorInfoForTfLiteOpaqueTensor(cellStateIn); // Layer norm coefficient tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 20)) { params.m_InputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 20); } if (IsOptionalOperandPresent(tfLiteNode, 21)) { params.m_ForgetLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 21); } if (IsOptionalOperandPresent(tfLiteNode, 22)) { params.m_CellLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 22); } if (IsOptionalOperandPresent(tfLiteNode, 23)) { params.m_OutputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 23); } const auto nodeParams = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); // set the layer descriptor armnn::LstmDescriptor desc; desc.m_ActivationFunc = NonNegative(nodeParams->activation, nodeIndex); desc.m_ClippingThresCell = nodeParams->cell_clip; desc.m_ClippingThresProj = nodeParams->proj_clip; desc.m_CifgEnabled = (params.m_InputToInputWeights == nullptr || params.m_RecurrentToInputWeights == nullptr || params.m_InputGateBias == nullptr); desc.m_PeepholeEnabled = (params.m_CellToForgetWeights != nullptr || params.m_CellToOutputWeights != nullptr); desc.m_ProjectionEnabled = (params.m_ProjectionWeights != nullptr); desc.m_LayerNormEnabled = (params.m_InputLayerNormWeights != nullptr || params.m_ForgetLayerNormWeights != nullptr || params.m_CellLayerNormWeights != nullptr || params.m_OutputLayerNormWeights != nullptr); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[1]; unsigned int numUnits = cellStateInInfo.GetShape()[1]; armnn::DataType dataType = inputTensorInfo.GetDataType(); float qScale = inputTensorInfo.GetQuantizationScale(); float qOffset = inputTensorInfo.GetQuantizationOffset(); armnn::TensorInfo scratchBufferTensorInfo({batchSize, numUnits * 3}, dataType, qScale, qOffset); if (!desc.m_CifgEnabled) { scratchBufferTensorInfo = armnn::TensorInfo({batchSize, numUnits * 4}, dataType, qScale, qOffset); } armnn::TensorInfo cellStateOutTensorInfo({batchSize, numUnits}, dataType, qScale, qOffset); armnn::TensorInfo outputStateOutTensorInfo({batchSize, outputSize}, dataType, qScale, qOffset); armnn::LstmInputParamsInfo paramsInfo; paramsInfo.m_InputToForgetWeights = &(params.m_InputToForgetWeights->GetInfo()); paramsInfo.m_InputToCellWeights = &(params.m_InputToCellWeights->GetInfo()); paramsInfo.m_InputToOutputWeights = &(params.m_InputToOutputWeights->GetInfo()); paramsInfo.m_RecurrentToForgetWeights = &(params.m_RecurrentToForgetWeights->GetInfo()); paramsInfo.m_RecurrentToCellWeights = &(params.m_RecurrentToCellWeights->GetInfo()); paramsInfo.m_RecurrentToOutputWeights = &(params.m_RecurrentToOutputWeights->GetInfo()); paramsInfo.m_ForgetGateBias = &(params.m_ForgetGateBias->GetInfo()); paramsInfo.m_CellBias = &(params.m_CellBias->GetInfo()); paramsInfo.m_OutputGateBias = &(params.m_OutputGateBias->GetInfo()); if (!desc.m_CifgEnabled) { paramsInfo.m_InputToInputWeights = &(params.m_InputToInputWeights->GetInfo()); paramsInfo.m_RecurrentToInputWeights = &(params.m_RecurrentToInputWeights->GetInfo()); if (params.m_CellToInputWeights != nullptr) { paramsInfo.m_CellToInputWeights = &(params.m_CellToInputWeights->GetInfo()); } paramsInfo.m_InputGateBias = &(params.m_InputGateBias->GetInfo()); } if (desc.m_ProjectionEnabled) { paramsInfo.m_ProjectionWeights = &(params.m_ProjectionWeights->GetInfo()); if (params.m_ProjectionBias != nullptr) { paramsInfo.m_ProjectionBias = &(params.m_ProjectionBias->GetInfo()); } } if (desc.m_PeepholeEnabled) { paramsInfo.m_CellToForgetWeights = &(params.m_CellToForgetWeights->GetInfo()); paramsInfo.m_CellToOutputWeights = &(params.m_CellToOutputWeights->GetInfo()); } if (desc.m_LayerNormEnabled) { if(!desc.m_CifgEnabled) { paramsInfo.m_InputLayerNormWeights = &(params.m_InputLayerNormWeights->GetInfo()); } paramsInfo.m_ForgetLayerNormWeights = &(params.m_ForgetLayerNormWeights->GetInfo()); paramsInfo.m_CellLayerNormWeights = &(params.m_CellLayerNormWeights->GetInfo()); paramsInfo.m_OutputLayerNormWeights = &(params.m_OutputLayerNormWeights->GetInfo()); } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("LSTM", tfLiteContext, IsLstmSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputStateInInfo, cellStateInInfo, scratchBufferTensorInfo, outputStateOutTensorInfo, cellStateOutTensorInfo, outputInfo, desc, paramsInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Lstm, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddLstmLayer(desc, params, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(scratchBufferTensorInfo); layer->GetOutputSlot(1).SetTensorInfo(outputStateOutTensorInfo); layer->GetOutputSlot(2).SetTensorInfo(cellStateOutTensorInfo); layer->GetOutputSlot(3).SetTensorInfo(outputTensorInfo); // Connect the inputs // input_layer delegateData.m_OutputSlotForNode[inputTensors[0]]->Connect(layer->GetInputSlot(0)); // cellStateIn delegateData.m_OutputSlotForNode[inputTensors[18]]->Connect(layer->GetInputSlot(1)); //outputStateIn delegateData.m_OutputSlotForNode[inputTensors[19]]->Connect(layer->GetInputSlot(2)); // In the test_model there is only 1 Output armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(1); delegateData.m_OutputSlotForNode[static_cast(outputTensors[0])] = &outputSlot; return kTfLiteOk; } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Normalization.hpp000066400000000000000000000207071446772241200220520ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitL2NormalizationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteL2NormalizationOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensor. const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteL2NormalizationOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensor. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use output indices to get output tensor. const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteL2NormalizationOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::L2NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("L2_NORMALIZATION", tfLiteContext, IsL2NormalizationSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a L2Normalization layer auto layerName = GetName(armnn::LayerType::L2Normalization, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddL2NormalizationLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitLocalResponseNormalizationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteNormalizationOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensor. const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteNormalizationOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensor. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use output indices to get output tensor. const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteNormalizationOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; descriptor.m_NormChannelType = armnn::NormalizationAlgorithmChannel::Across; descriptor.m_NormMethodType = armnn::NormalizationAlgorithmMethod::LocalBrightness; auto* nodeParams = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_NormSize = nodeParams->radius; descriptor.m_K = nodeParams->bias; descriptor.m_Alpha = nodeParams->alpha; descriptor.m_Beta = nodeParams->beta; // ArmNN expects normSize to be the full size of the normalization window descriptor.m_NormSize = 1 + (2 * descriptor.m_NormSize); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("NORMALIZATION", tfLiteContext, IsNormalizationSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Normalization layer auto layerName = GetName(armnn::LayerType::Normalization, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddNormalizationLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/OpaqueDelegateUtils.hpp000066400000000000000000000614351446772241200231350ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include namespace { std::string GetName(armnn::ActivationFunction function, int nodeIndex) { return fmt::format("{}:{}", GetActivationFunctionAsCString(function), nodeIndex); } std::string GetName(armnn::ArgMinMaxFunction function, int nodeIndex) { return fmt::format("{}:{}", GetArgMinMaxFunctionAsCString(function), nodeIndex); } std::string GetName(armnn::BinaryOperation opType, int nodeIndex) { return fmt::format("{}:{}", GetBinaryOperationAsCString(opType), nodeIndex); } std::string GetName(armnn::ComparisonOperation layerType, int nodeIndex) { return fmt::format("{}:{}", GetComparisonOperationAsCString(layerType), nodeIndex); } std::string GetName(armnn::LogicalBinaryOperation operation, int nodeIndex) { return fmt::format("{}:{}", GetLogicalBinaryOperationAsCString(operation), nodeIndex); } std::string GetName(armnn::UnaryOperation opType, int nodeIndex) { return fmt::format("{}:{}", GetUnaryOperationAsCString(opType), nodeIndex); } std::string GetName(armnn::LayerType layerType, int nodeIndex, std::string subname = "") { return fmt::format("{}{}:{}", GetLayerTypeAsCString(layerType), subname, nodeIndex); } // Macro to call an IsSupported function and log caller name together with reason for lack of support #define FORWARD_LAYER_OPAQUE_SUPPORT_FUNC(opName, tfLiteContext, func, backends, supported, setBackend, ...) \ try \ { \ for (auto&& backendId : backends) \ { \ auto layerSupportObject = armnn::GetILayerSupportByBackendId(backendId); \ if (layerSupportObject.IsBackendRegistered()) \ { \ std::string reasonIfUnsupported; \ supported = \ layerSupportObject.func(__VA_ARGS__, armnn::Optional(reasonIfUnsupported)); \ if (supported) \ { \ setBackend = backendId; \ break; \ } \ else \ { \ if (reasonIfUnsupported.size() > 0) \ { \ TFLITE_LOG_PROD(tflite::TFLITE_LOG_WARNING, \ "%s: not supported by armnn: %s", opName, reasonIfUnsupported.c_str()); \ } \ else \ { \ TFLITE_LOG_PROD(tflite::TFLITE_LOG_WARNING, \ "%s: not supported by armnn", opName); \ } \ } \ } \ else \ { \ TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "%s: backend not registered: %s", \ opName, backendId.Get().c_str()); \ } \ } \ if (!supported) \ { \ TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "%s: not supported by any specified backend", opName); \ } \ } \ catch (const armnn::InvalidArgumentException &e) \ { \ throw armnn::InvalidArgumentException(e, "Failed to check layer support", CHECK_LOCATION()); \ } TfLiteStatus ValidateNumInputs(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, const unsigned int expectedSize, int nodeIndex) { int numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (static_cast(numInputs) != expectedSize) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unexpected number of inputs (%d != %d) in node #%d", numInputs, expectedSize, nodeIndex); return kTfLiteError; } return kTfLiteOk; } TfLiteStatus ValidateNumOutputs(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, const unsigned int expectedSize, int nodeIndex) { auto numOutputs = TfLiteOpaqueNodeNumberOfOutputs(tfLiteNode); if (static_cast(numOutputs) != expectedSize) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unexpected number of outputs (%d != %d) in node #%d", numOutputs, expectedSize, nodeIndex); return kTfLiteError; } return kTfLiteOk; } bool IsConstantTensor(const TfLiteOpaqueTensor* tfLiteTensor) { auto tensorAllocationType = TfLiteOpaqueTensorGetAllocationType(tfLiteTensor); if (tensorAllocationType == kTfLiteMmapRo) { return true; } return false; } bool IsDynamicTensor(const TfLiteOpaqueTensor* tfLiteTensor) { auto tensorAllocationType = TfLiteOpaqueTensorGetAllocationType(tfLiteTensor); if (tensorAllocationType == kTfLiteDynamic) { return true; } return false; } bool IsValid(const TfLiteOpaqueTensor* tfLiteTensor) { return tfLiteTensor == nullptr ? false : true; } bool IsValid(TfLiteOpaqueContext* tfLiteContext, const TfLiteOpaqueTensor* tfLiteTensor, int32_t operatorCode, int32_t nodeIndex) { if(!IsValid(tfLiteTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Invalid TfLite tensor in operator #%d node #%d: ", operatorCode, nodeIndex); return false; } if (IsDynamicTensor(tfLiteTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic tensors are not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return false; } return true; } bool IsAffineQuantization(const TfLiteOpaqueTensor& tfLiteTensor) { auto quantizationInfo = TfLiteOpaqueTensorGetQuantization(&tfLiteTensor); if (quantizationInfo.type == kTfLiteAffineQuantization) { return true; } return false; } // Connects the layer to the graph TfLiteStatus Connect(armnn::IConnectableLayer* layer, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, armnnOpaqueDelegate::DelegateData& data) { // Get array of input indices, inputIndexArray is set from the TfLiteOpaqueNodeInputs function // This function turns inputIndexArray into an int array of indices. These indices point to the index of the // tensors for each input slot in the node. const int* inputIndexArray; int numInputs; if(TfLiteOpaqueNodeInputs(tfLiteNode, &inputIndexArray, &numInputs) != kTfLiteOk) { return kTfLiteError; } // We can't validate the number of inputs vs the layer->GetNumOutputSlots() as some operators differ. // An example is Mean where the number of TFLite inputs is 2, but number of Arm NN inputs is 1, // as we store the axis within the descriptor. // Connect the input slots. // For each input slot, get the index of the opaque tensor that was allocated for it. for (unsigned int inputIndex = 0; inputIndex < layer->GetNumInputSlots(); ++inputIndex) { if (data.m_OutputSlotForNode[inputIndexArray[inputIndex]] != nullptr) { data.m_OutputSlotForNode[inputIndexArray[inputIndex]]->Connect(layer->GetInputSlot(inputIndex)); } } // Get array of output indices, outputIndexArray is set from the TfLiteOpaqueNodeOutputs function // This function turns outputIndexArray into an int array of indices. These indices point to the tensors for // each output slot in the node. const int* outputIndexArray; int numOutputs; if(TfLiteOpaqueNodeOutputs(tfLiteNode, &outputIndexArray, &numOutputs) != kTfLiteOk) { return kTfLiteError; } // numOutputs is set from TfLiteOpaqueNodeOutputs. if(numOutputs != static_cast(layer->GetNumOutputSlots())) { ARMNN_LOG(error) << "Layer: " << layer->GetName() << ": Expected number of output slots does not match actual " "number of output slots."; return kTfLiteError; } // Prepare output slots for (unsigned int outputIndex = 0; outputIndex < layer->GetNumOutputSlots(); ++outputIndex) { armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast(outputIndexArray[outputIndex])] = &outputSlot; } return kTfLiteOk; } TfLiteStatus FusedActivation(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, TfLiteFusedActivation activationType, armnn::IConnectableLayer* prevLayer, unsigned int outputSlotIndex, armnnOpaqueDelegate::DelegateData& data, int nodeIndex) { const armnn::TensorInfo& activationOutputInfo = prevLayer->GetOutputSlot(outputSlotIndex).GetTensorInfo(); armnn::ActivationDescriptor activationDesc; switch (activationType) { case kTfLiteActNone: { // No Activation return kTfLiteOk; } case kTfLiteActRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } case kTfLiteActReluN1To1: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 1.0f; activationDesc.m_B = -1.0f; break; } case kTfLiteActRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; activationDesc.m_B = 0.0f; break; } case kTfLiteActSigmoid: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteActTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } default: return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("ACTIVATION", tfLiteContext, IsActivationSupported, data.m_Backends, isSupported, setBackend, activationOutputInfo, activationOutputInfo, activationDesc); if (!isSupported) { return kTfLiteError; } auto layerName = GetName(activationDesc.m_Function, nodeIndex); armnn::IConnectableLayer* activationLayer = data.m_Network->AddActivationLayer(activationDesc, layerName.c_str()); activationLayer->SetBackendId(setBackend); ARMNN_ASSERT(activationLayer != nullptr); activationLayer->GetOutputSlot(0).SetTensorInfo(activationOutputInfo); // Get array of output indices, outputIndexArray is set from the TfLiteOpaqueNodeOutputs function // This function turns outputIndexArray into an int array of indices. These indices point to the tensors for // each output slot in the node. const int* outputIndexArray; int numOutputs; TfLiteStatus outputStatus = TfLiteOpaqueNodeOutputs(tfLiteNode, &outputIndexArray, &numOutputs); if(outputStatus != kTfLiteOk) { return kTfLiteError; } // Connect and prepare output slots for (unsigned int outputIndex = 0; outputIndex < activationLayer->GetNumOutputSlots(); ++outputIndex) { data.m_OutputSlotForNode[static_cast( outputIndexArray[outputIndex])]->Connect(activationLayer->GetInputSlot(0)); armnn::IOutputSlot& outputSlot = activationLayer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast(outputIndexArray[outputIndex])] = &outputSlot; } return kTfLiteOk; } armnn::IConnectableLayer* AddReshapeLayer(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, armnn::IConnectableLayer* prevLayer, armnn::TensorInfo reshapedOutputTensorInfo, armnn::TensorInfo outputTensorInfo, armnnOpaqueDelegate::DelegateData& data, int nodeIndex) { armnn::ReshapeDescriptor desc; desc.m_TargetShape = outputTensorInfo.GetShape(); bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, data.m_Backends, isSupported, setBackend, reshapedOutputTensorInfo, outputTensorInfo, desc); if (!isSupported) { return nullptr; } auto layerName = GetName(armnn::LayerType::Reshape, nodeIndex); armnn::IConnectableLayer* reshapeLayer = data.m_Network->AddReshapeLayer(desc, layerName.c_str()); reshapeLayer->SetBackendId(setBackend); ARMNN_ASSERT(reshapeLayer != nullptr); prevLayer->GetOutputSlot(0).SetTensorInfo(reshapedOutputTensorInfo); reshapeLayer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); // Gather array of indices and it's length, replaces node->outputs->data[i] const int* outputIndices = nullptr; int numOutputs = 0; TfLiteStatus status = TfLiteOpaqueNodeOutputs(tfLiteNode, &outputIndices, &numOutputs); if(status != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to gather output information from node."); } if (static_cast(numOutputs) != reshapeLayer->GetNumOutputSlots()) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unexpected number of outputs (" + std::to_string(numOutputs) + "!= " + std::to_string(reshapeLayer->GetNumOutputSlots()) + ") in node."); } // Connect and prepare output slots for (unsigned int outputIndex = 0; outputIndex < reshapeLayer->GetNumOutputSlots(); ++outputIndex) { data.m_OutputSlotForNode[static_cast( outputIndices[outputIndex])]->Connect(reshapeLayer->GetInputSlot(0)); armnn::IOutputSlot& outputSlot = reshapeLayer->GetOutputSlot(outputIndex); data.m_OutputSlotForNode[static_cast(outputIndices[outputIndex])] = &outputSlot; } return reshapeLayer; } armnn::DataType GetDataType(const TfLiteOpaqueTensor* tfLiteTensor) { switch (TfLiteOpaqueTensorType(tfLiteTensor)) { case kTfLiteBool: return armnn::DataType::Boolean; case kTfLiteFloat32: return armnn::DataType::Float32; case kTfLiteFloat16: return armnn::DataType::Float16; case kTfLiteUInt8: return armnn::DataType::QAsymmU8; case kTfLiteInt8: { auto quantizationInfo = TfLiteOpaqueTensorGetQuantization(tfLiteTensor); if (quantizationInfo.type == kTfLiteAffineQuantization) { auto* quantization = reinterpret_cast(quantizationInfo.params); if (quantization->zero_point != nullptr && quantization->zero_point->size == 1) { return armnn::DataType::QAsymmS8; } else { return armnn::DataType::QSymmS8; } } else { return armnn::DataType::QAsymmS8; } } case kTfLiteInt16: return armnn::DataType::QSymmS16; case kTfLiteInt32: return armnn::DataType::Signed32; case kTfLiteInt64: return armnn::DataType::Signed64; default: throw armnn::Exception( &"TfLiteArmnnOpaqueDelegate: Unsupported data type: " [ TfLiteOpaqueTensorType(tfLiteTensor) ]); } } armnn::TensorInfo GetTensorInfoForTfLiteOpaqueTensor(const TfLiteOpaqueTensor* tfLiteTensor, bool isOutput = false) { armnn::DataType type = GetDataType(tfLiteTensor); armnn::TensorInfo ret; auto tensorDimensionSize = TfLiteOpaqueTensorNumDims(tfLiteTensor); if (tensorDimensionSize == 0) { // If input tensor does not have a shape // assuming that it has 1D tensor if (!isOutput) { std::vector safeShape = { 1 }; bool dimensionsSpecificity[1] = { true }; armnn::TensorShape tensorShape(safeShape.size(), safeShape.data(), dimensionsSpecificity); ret = armnn::TensorInfo(tensorShape, type); if(IsConstantTensor(tfLiteTensor)) { ret.SetConstant(true); } } else { armnn::TensorShape tensorShape(armnn::Dimensionality::NotSpecified); ret = armnn::TensorInfo(tensorShape, type); } } else { std::vector tensorDims(tensorDimensionSize); std::vector dimensionsSpecificity(tensorDimensionSize, true); for (int32_t i = 0; i < tensorDimensionSize; ++i) { int32_t dim = TfLiteOpaqueTensorDim(tfLiteTensor, i); if (dim <= 0) { dimensionsSpecificity[i] = false; } tensorDims[i] = static_cast(dim); } armnn::TensorShape tensorShape(tensorDimensionSize, tensorDims.data(), reinterpret_cast(dimensionsSpecificity.data())); if (IsConstantTensor(tfLiteTensor)) { ret = armnn::TensorInfo(tensorShape, type); ret.SetConstant(true); } else { ret = armnn::TensorInfo(tensorShape, type); } } auto quantizationInfo = TfLiteOpaqueTensorGetQuantization(tfLiteTensor); if (quantizationInfo.type == kTfLiteAffineQuantization) { // get per-channel quantization parameters const auto* affineQuantization = reinterpret_cast(quantizationInfo.params); if (affineQuantization->scale->size > 1) { std::vector quantizationScales; for (unsigned int i = 0; i < static_cast(affineQuantization->scale->size); ++i) { quantizationScales.push_back(affineQuantization->scale->data[i]); } ret.SetQuantizationScales(quantizationScales); ret.SetQuantizationDim(armnn::numeric_cast(affineQuantization->quantized_dimension)); } else { ret.SetQuantizationScale(affineQuantization->scale->data[0]); ret.SetQuantizationOffset(affineQuantization->zero_point->data[0]); } } else { auto quantizationParameters = TfLiteOpaqueTensorGetQuantizationParams(tfLiteTensor); ret.SetQuantizationScale(quantizationParameters.scale); ret.SetQuantizationOffset(quantizationParameters.zero_point); } return ret; } armnn::ConstTensor CreateConstTensor(const TfLiteOpaqueTensor* tfLiteTensor, const armnn::TensorInfo& tensorInfo) { auto allocType = TfLiteOpaqueTensorGetAllocationType(tfLiteTensor); if (allocType != kTfLiteMmapRo) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Not constant allocation type: " + std::to_string(allocType)); } return armnn::ConstTensor(tensorInfo, TfLiteOpaqueTensorData(tfLiteTensor)); } armnn::ConstTensor* GetConstTensorForTfLiteTensor(const TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int index) { const TfLiteOpaqueTensor* tfLiteTensor = TfLiteOpaqueNodeGetInput(tfLiteContext, tfLiteNode, index); armnn::TensorInfo tensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteTensor); return new armnn::ConstTensor(tensorInfo, TfLiteOpaqueTensorData(tfLiteTensor)); } bool IsOptionalOperandPresent(TfLiteOpaqueNode* tfLiteNode, const int operandIndex) { // Get array of input indices, inputIndexArray is set from the TfLiteOpaqueNodeInputs function // This function turns inputIndexArray into an int array of indices. These indices point to the index of the // tensors for each input slot in the node. const int* inputIndexArray; int numInputs = 0; TfLiteStatus status = TfLiteOpaqueNodeInputs(tfLiteNode, &inputIndexArray, &numInputs); if(status != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to gather input information from node."); } // If the inputs array has fewer than operandIndex entries or if the entry at operandIndex has a value of -1 or // less then the input is not present. if (numInputs > operandIndex && inputIndexArray[operandIndex] >= 0) { return true; } return false; } TfLiteStatus ProcessInputs(armnn::IConnectableLayer* layer, armnnOpaqueDelegate::DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex) { // Get array of input indices, inputIndexArray is set from the TfLiteOpaqueNodeInputs function // This function turns inputIndexArray into an int array of indices. These indices point to the index of the // tensors for each input slot in the node. const int* inputIndexArray; int numInputs = 0; TfLiteStatus status = TfLiteOpaqueNodeInputs(tfLiteNode, &inputIndexArray, &numInputs); if(status != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to gather input information from node."); } // Process input tensors // If input tensor is a Constant tensor create a constant layer and connect it to the network for (int32_t inputIndex = 0; inputIndex < static_cast(layer->GetNumInputSlots()); ++inputIndex) { const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueNodeGetInput(tfLiteContext, tfLiteNode, inputIndex); if (IsConstantTensor(tfLiteInputTensor)) { armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); bool isSupported = false; armnn::BackendId setBackend; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("CONSTANT", tfLiteContext, IsConstantSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo); if (!isSupported) { return kTfLiteError; } auto constantInput = CreateConstTensor(tfLiteInputTensor, inputTensorInfo); auto layerName = GetName(armnn::LayerType::Constant, nodeIndex); armnn::IConnectableLayer* constantLayer = delegateData.m_Network->AddConstantLayer(constantInput, layerName.c_str()); constantLayer->SetBackendId(setBackend); armnn::IOutputSlot& outputSlot = constantLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(inputTensorInfo); delegateData.m_OutputSlotForNode[inputIndexArray[inputIndex]] = &outputSlot; } } return kTfLiteOk; } } // namespace anonymous armnn-23.08/delegate/opaque/src/Pack.hpp000066400000000000000000000132341446772241200200770ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitPackOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLitePackOperatorCode) { // Check Inputs auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Must have at least one input in (%d != %d) in node #%d", 1, numInputs, nodeIndex); return kTfLiteError; } // Gather input indices and use to get input tensors. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Validate all inputs and get TensorInfo std::vector inputTensorInfos; for (int i = 0; i < numInputs; ++i) { const TfLiteOpaqueTensor* inputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[i]); if (!IsValid(tfLiteContext, inputTensor, tfLitePackOperatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(inputTensor); inputTensorInfos.emplace_back(inputTensorInfo); } // Convert inputTensorInfos to const armnn::TensorInfo* type for FORWARD_LAYER_OPAQUE_SUPPORT_FUNC. std::vector inputConstTensorInfos; std::transform(inputTensorInfos.begin(), inputTensorInfos.end(), std::back_inserter(inputConstTensorInfos), [](armnn::TensorInfo& t)->const armnn::TensorInfo*{ return &t; }); // Check outputs TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather output indices and use to get output tensor. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Validate the output and get TensorInfo const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLitePackOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::StackDescriptor desc; desc.m_NumInputs = static_cast(numInputs); // Get axis from TfLite parameters auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); auto axis = tfLiteNodeParameters->axis; desc.m_Axis = NonNegative(axis, nodeIndex); // Use the tensor shape of the first input as the "correct" input shape in the descriptor desc.m_InputShape = inputTensorInfos[0].GetShape(); // Check if supported bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("STACK", tfLiteContext, IsStackSupported, delegateData.m_Backends, isSupported, setBackend, inputConstTensorInfos, outputTensorInfo, desc); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitPackOperator will be called again to add the layer to the network as seen below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // The TfLite Pack operator is equivalent to the ArmNN Stack operator auto layerName = GetName(armnn::LayerType::Stack, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddStackLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // Connect the Constant Inputs auto inputsTensorsProcess = ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Pad.hpp000066400000000000000000000176741446772241200177410ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitPadOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLitePadOperatorCode) { switch(tfLitePadOperatorCode) { case kTfLiteBuiltinMirrorPad: case kTfLiteBuiltinPad: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); break; case kTfLiteBuiltinPadv2: TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); break; default: return kTfLiteError; } // Inputs int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLitePadOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLitePaddingTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLitePaddingTensor, tfLitePadOperatorCode, nodeIndex)) { return kTfLiteError; } // Output TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLitePadOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& paddingTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLitePaddingTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Get the padding data from the input tensor auto* paddingData = static_cast(TfLiteOpaqueTensorData(tfLitePaddingTensor)); size_t step = 2; armnn::PadDescriptor descriptor; for (unsigned int i = 0; i < paddingTensorInfo.GetNumElements() / step; ++i) { descriptor.m_PadList.emplace_back(paddingData[i * step], paddingData[i * step + 1]); } if (tfLitePadOperatorCode == kTfLiteBuiltinPad && inputTensorInfo.IsQuantized()) { descriptor.m_PadValue = inputTensorInfo.GetQuantizationOffset(); } else if (tfLitePadOperatorCode == kTfLiteBuiltinPadv2) { const TfLiteOpaqueTensor* tfLitepaddingValue = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); armnn::TensorInfo paddingValueTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLitepaddingValue); if (paddingValueTensorInfo.GetNumElements() != 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Multiple padding value are not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } // Get the padding value from the input tensor switch (TfLiteOpaqueTensorType(tfLitepaddingValue)) { case kTfLiteFloat32: descriptor.m_PadValue = static_cast(TfLiteOpaqueTensorData(tfLitepaddingValue))[0]; break; case kTfLiteUInt8: descriptor.m_PadValue = static_cast(TfLiteOpaqueTensorData(tfLitepaddingValue))[0]; break; case kTfLiteInt8: descriptor.m_PadValue = static_cast(TfLiteOpaqueTensorData(tfLitepaddingValue))[0]; break; default: TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Padding value datatype is not supported in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); return kTfLiteError; } } else if (tfLitePadOperatorCode == kTfLiteBuiltinMirrorPad) { auto* options = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); if (options->mode == TfLiteMirrorPaddingMode::kTfLiteMirrorPaddingReflect) { descriptor.m_PaddingMode = armnn::PaddingMode::Reflect; } else if (options->mode == TfLiteMirrorPaddingMode::kTfLiteMirrorPaddingSymmetric) { descriptor.m_PaddingMode = armnn::PaddingMode::Symmetric; } else { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: PaddingMode must be either REFLECT or SYMMETRIC " "in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); } // If padding mode is Reflect then both paddings must be no greater than inputShape(i) - 1. // If padding mode is Symmetric then both paddings must be no greater than inputShape(i). auto inputShape = inputTensorInfo.GetShape(); auto padList = descriptor.m_PadList; const auto isReflect = static_cast(descriptor.m_PaddingMode == armnn::PaddingMode::Reflect); for(unsigned int i = 0; i < padList.size(); ++i) { if(padList.at(i).first > (inputShape[i] - isReflect) || padList.at(i).second > (inputShape[i] - isReflect)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Padding values must be less (Reflect) or " "equal (Symmetric) to the dimension size in operator #%d node #%d: ", tfLitePadOperatorCode, nodeIndex); } } } armnn::BackendId setBackend; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("PAD", tfLiteContext, IsPadSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Pad, nodeIndex); armnn::IConnectableLayer* padLayer = delegateData.m_Network->AddPadLayer(descriptor, layerName.c_str()); padLayer->SetBackendId(setBackend); ARMNN_ASSERT(padLayer != nullptr); armnn::IOutputSlot& outputSlot = padLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); return Connect(padLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Pooling.hpp000066400000000000000000000351231446772241200206310ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitPooling2dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLitePoolingOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensors. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLitePoolingOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLitePoolingOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); TfLiteFusedActivation activationType = kTfLiteActNone; if (tfLiteNodeParameters) { activationType = tfLiteNodeParameters->activation; TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } } armnn::PoolingAlgorithm poolingAlgorithm; switch(tfLitePoolingOperatorCode) { case kTfLiteBuiltinAveragePool2d: poolingAlgorithm = armnn::PoolingAlgorithm::Average; break; case kTfLiteBuiltinL2Pool2d: poolingAlgorithm = armnn::PoolingAlgorithm::L2; break; case kTfLiteBuiltinMaxPool2d: poolingAlgorithm = armnn::PoolingAlgorithm::Max; break; default: return kTfLiteError; } armnn::Pooling2dDescriptor descriptor; descriptor.m_PoolType = poolingAlgorithm; descriptor.m_PoolWidth = tfLiteNodeParameters->filter_width; descriptor.m_PoolHeight = tfLiteNodeParameters->filter_height; descriptor.m_StrideX = tfLiteNodeParameters->stride_width; descriptor.m_StrideY = tfLiteNodeParameters->stride_height; descriptor.m_DataLayout = armnn::DataLayout::NHWC; unsigned int inputHeight = inputTensorInfo.GetShape()[1]; unsigned int inputWidth = inputTensorInfo.GetShape()[2]; CalcPadding(inputHeight, descriptor.m_PoolHeight, descriptor.m_StrideY, 1u, descriptor.m_PadTop, descriptor.m_PadBottom, tfLiteNodeParameters->padding); CalcPadding(inputWidth, descriptor.m_PoolWidth, descriptor.m_StrideX, 1u, descriptor.m_PadLeft, descriptor.m_PadRight, tfLiteNodeParameters->padding); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("POOLING_2D", tfLiteContext, IsPooling2dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Pooling2d, nodeIndex); armnn::IConnectableLayer* poolingLayer = delegateData.m_Network->AddPooling2dLayer(descriptor, layerName.c_str()); poolingLayer->SetBackendId(setBackend); ARMNN_ASSERT(poolingLayer != nullptr); armnn::IOutputSlot& outputSlot = poolingLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(poolingLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } if (Connect(poolingLayer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } // Check and create activation return FusedActivation(tfLiteContext, tfLiteNode, activationType, poolingLayer, 0, delegateData, nodeIndex); } TfLiteStatus VisitPooling3dOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, std::string customOperatorName) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensors. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, kTfLiteBuiltinCustom, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, kTfLiteBuiltinCustom, nodeIndex)) { return kTfLiteError; } // Set the input and output info const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Custom Operators are defined by the name string associated to the operator. Use this to determine // which pooling algorithm to create the armnn operator with. L2 Pooling3D is unsupported in TfLite. armnn::PoolingAlgorithm poolingAlgorithm; if (customOperatorName == "MaxPool3D") { poolingAlgorithm = armnn::PoolingAlgorithm::Max; } else if (customOperatorName == "AveragePool3D") { poolingAlgorithm = armnn::PoolingAlgorithm::Average; } else { return kTfLiteError; } // Create the armnn pool3d descriptor and set the algorithm parsed above. armnn::Pooling3dDescriptor descriptor; descriptor.m_PoolType = poolingAlgorithm; // custom_initial_data and custom_initial_data_size are void* variables defined in the tflite registration // used to access the custom option buffer for the operator. const void* customData = nullptr; int customDataSize = 0; if (TfLiteOpaqueNodeGetCustomInitialData(tfLiteNode, &customData, &customDataSize) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to initialise initial custom data from node #%d: ", nodeIndex); return kTfLiteError; } // Reinterpret the void* to a byte buffer to access the options data in the flexbuffers map. const flexbuffers::Map& m = flexbuffers::GetRoot(reinterpret_cast(customData), customDataSize).AsMap(); // poolDims is a vector of [ 1, Depth, Height, Width, 1 ] const auto poolDims = m["ksize"].AsTypedVector(); descriptor.m_PoolWidth = poolDims[3].AsInt32(); descriptor.m_PoolHeight = poolDims[2].AsInt32(); descriptor.m_PoolDepth = poolDims[1].AsInt32(); // strideDimes is a vector of [ 1, Z, Y, X, 1] const auto strideDims = m["strides"].AsTypedVector(); descriptor.m_StrideX = strideDims[3].AsInt32(); descriptor.m_StrideY = strideDims[2].AsInt32(); descriptor.m_StrideZ = strideDims[1].AsInt32(); descriptor.m_DataLayout = armnn::DataLayout::NDHWC; unsigned int inputDepth = inputTensorInfo.GetShape()[1]; unsigned int inputHeight = inputTensorInfo.GetShape()[2]; unsigned int inputWidth = inputTensorInfo.GetShape()[3]; // CalcPadding expects a TfLitePadding type. Parse flexbuffers to extract padding string and create TfLitePadding. std::string paddingStr = m["padding"].AsString().str(); TfLitePadding padding; if (paddingStr == "VALID") { padding = kTfLitePaddingValid; } else if (paddingStr == "SAME") { padding = kTfLitePaddingSame; } else { padding = kTfLitePaddingUnknown; } // Calculates padding for each pooling dimension separately CalcPadding(inputHeight, descriptor.m_PoolHeight, descriptor.m_StrideY, 1u, descriptor.m_PadTop, descriptor.m_PadBottom, padding); CalcPadding(inputWidth, descriptor.m_PoolWidth, descriptor.m_StrideX, 1u, descriptor.m_PadLeft, descriptor.m_PadRight, padding); CalcPadding(inputDepth, descriptor.m_PoolDepth, descriptor.m_StrideZ, 1u, descriptor.m_PadFront, descriptor.m_PadBack, padding); // Check activation by parsing the string from the flexbuffer map std::string activationTypeStr = m["activation"].AsString().str(); TfLiteFusedActivation activationType = kTfLiteActNone; if (activationTypeStr == "kTfLiteActRelu") { activationType = kTfLiteActRelu; } else if (activationTypeStr == "kTfLiteActReluN1To1") { activationType = kTfLiteActReluN1To1; } else if (activationTypeStr == "kTfLiteActRelu6") { activationType = kTfLiteActRelu6; } else if (activationTypeStr == "kTfLiteActTanh") { activationType = kTfLiteActTanh; } else if (activationTypeStr == "kTfLiteActSignBit") { activationType = kTfLiteActSignBit; } else if (activationTypeStr == "kTfLiteActSigmoid") { activationType = kTfLiteActSigmoid; } else { activationType = kTfLiteActNone; } TfLiteStatus activationStatus = ValidateFusedActivationOperator(delegateData, tfLiteContext, outputTensorInfo, outputTensorInfo, activationType); if(activationStatus != kTfLiteOk) { return kTfLiteError; } // Validate the output info. bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("POOLING_3D", tfLiteContext, IsPooling3dSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Create the Layer auto layerName = GetName(armnn::LayerType::Pooling3d, nodeIndex); armnn::IConnectableLayer* poolingLayer = delegateData.m_Network->AddPooling3dLayer(descriptor, layerName.c_str()); poolingLayer->SetBackendId(setBackend); ARMNN_ASSERT(poolingLayer != nullptr); // Create and set output slots armnn::IOutputSlot& outputSlot = poolingLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(poolingLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } if (Connect(poolingLayer, tfLiteContext, tfLiteNode, delegateData) != kTfLiteOk) { return kTfLiteError; } return FusedActivation(tfLiteContext, tfLiteNode, activationType, poolingLayer, 0, delegateData, nodeIndex); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Prelu.hpp000066400000000000000000000120561446772241200203110ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus ValidatePreluOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& alphaInfo, const armnn::TensorInfo& outputInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("PRELU", tfLiteContext, IsPreluSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, alphaInfo, outputInfo); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitPreluOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteAlphaTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteAlphaTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& alphaTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteAlphaTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { return ValidatePreluOperator(delegateData, tfLiteContext, inputTensorInfo, alphaTensorInfo, outputTensorInfo); } auto layerName = GetName(armnn::LayerType::Prelu, nodeIndex); armnn::IConnectableLayer* preluLayer = delegateData.m_Network->AddPreluLayer(layerName.c_str()); ARMNN_ASSERT(preluLayer != nullptr); bool isConstantAlpha = IsConstantTensor(tfLiteAlphaTensor); // Add constant layer for constant alpha if (isConstantAlpha) { auto constAlphaTensor = armnn::ConstTensor(alphaTensorInfo, TfLiteOpaqueTensorData(tfLiteAlphaTensor)); auto alphaName = GetName(armnn::LayerType::Constant, nodeIndex, "Alpha"); armnn::IConnectableLayer* constLayer = delegateData.m_Network->AddConstantLayer(constAlphaTensor, alphaName.c_str()); ARMNN_ASSERT(constLayer != nullptr); constLayer->GetOutputSlot(0).SetTensorInfo(alphaTensorInfo); constLayer->GetOutputSlot(0).Connect(preluLayer->GetInputSlot(1)); } armnn::IOutputSlot& outputSlot = preluLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(preluLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Quantization.hpp000066400000000000000000000174631446772241200217170ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitDequantizeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); armnn::TensorInfo outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); UpdateConstantTensorOutputs(inputTensorInfo, outputTensorInfo); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("DEQUANTIZE", tfLiteContext, IsDequantizeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Dequantize, nodeIndex); armnn::IConnectableLayer* dequantizeLayer = delegateData.m_Network->AddDequantizeLayer(layerName.c_str()); dequantizeLayer->SetBackendId(setBackend); ARMNN_ASSERT(dequantizeLayer != nullptr); armnn::IOutputSlot& outputSlot = dequantizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); auto inputsTensorsProcess = ProcessInputs(dequantizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex); if (inputsTensorsProcess == kTfLiteError) { return inputsTensorsProcess; } return Connect(dequantizeLayer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitQuantizeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Only affine per-layer quantization is supported. if (!IsAffineQuantization(*tfLiteOutputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Only affine per-layer quantization is supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("QUANTIZE", tfLiteContext, IsQuantizeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Quantize, nodeIndex); armnn::IConnectableLayer* quantizeLayer = delegateData.m_Network->AddQuantizeLayer(layerName.c_str()); quantizeLayer->SetBackendId(setBackend); ARMNN_ASSERT(quantizeLayer != nullptr); armnn::IOutputSlot& outputSlot = quantizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(quantizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(quantizeLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Redefine.hpp000066400000000000000000000466171446772241200207550ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitCastOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { return kTfLiteError; } // This layer only has 1 input, so we can directly assign tensor[0] to a new opaque tensor const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[numInputs-1]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { return kTfLiteError; } // This layer only has 1 output, so we can directly assign tensor[0] to a new opaque tensor const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[numOutputs-1]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("CAST", tfLiteContext, IsCastSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitCastOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Cast layer auto layerName = GetName(armnn::LayerType::Cast, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddCastLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitReshapeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs == 2) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); } else { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::ReshapeDescriptor reshapeDesc; std::vector targetShape; auto* reshapeOptions = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); // The new shape can be defined by either a second input tensor or by a builtin option, we need to check for both. // Options might be set without valid data. we need to check the dimensions are in a valid range. if (reshapeOptions && reshapeOptions->num_dimensions > 0 && reshapeOptions->num_dimensions <= 8) { for (int i = 0; i < reshapeOptions->num_dimensions; ++i) { targetShape.push_back(reshapeOptions->shape[i]); } } else if (numInputs == 2) { // Get shape from the second input tensor const TfLiteOpaqueTensor* tfLiteShapeInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteShapeInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } int32_t numDims = TfLiteOpaqueTensorNumDims(tfLiteShapeInputTensor); if (numDims != 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Target 'shape' input is not a 1D tensor in " "operator #%d node #%d: Falling back to TfLiteOptions.", operatorCode, nodeIndex); } else { // Get the shape data out of the input tensor auto* shapeTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteShapeInputTensor)); int32_t shapeTensorNumValues = TfLiteOpaqueTensorDim(tfLiteShapeInputTensor, 0); for (int32_t i = 0; i < shapeTensorNumValues; ++i) { targetShape.push_back(shapeTensorDataPtr[i]); } } } else { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Target shape not defined in reshape parameters or input tensor. " "At least one method required in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } // Use the data to create the required tensor shape. if (CreateOutputTensorShape(inputTensorInfo0, targetShape, reshapeDesc) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: At most one component of shape can be -1 in: " "operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } if (reshapeDesc.m_TargetShape.GetNumElements() != inputTensorInfo0.GetNumElements()) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Reshape, number of elements in output shape does not match input " "operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Reshape, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitSqueezeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } auto* options = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); std::vector squeezeDim; // A single negative dim index is interpreted as a negative index in python // Meaning the index will be the shape size plus the negative index value if (options->num_squeeze_dims == 1 && options->squeeze_dims[0] < 0) { int32_t dim = static_cast(inputTensorInfo.GetShape().GetNumDimensions()) + options->squeeze_dims[0]; squeezeDim.push_back(static_cast(dim)); } else { for (int32_t i = 0; i < options->num_squeeze_dims; ++i) { squeezeDim.push_back(static_cast(options->squeeze_dims[i])); } } armnn::TensorInfo outputTensorInfo = OutputShapeOfSqueeze(squeezeDim, inputTensorInfo); armnn::ReshapeDescriptor reshapeDesc; reshapeDesc.m_TargetShape = outputTensorInfo.GetShape(); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SQUEEZE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Reshape, nodeIndex, "Squeeze"); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitExpandDimsOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteAxisTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); armnn::TensorInfo outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor); auto* axisTensorData = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); int32_t axis = axisTensorData[0]; int32_t inputDimSize = static_cast(inputTensorInfo.GetShape().GetNumDimensions()); if (axis > inputDimSize || axis < 0 - (inputDimSize + 1)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Axis must be in range " "[0 - (inputDimSize + 1), inputDimSize] inclusive."); return kTfLiteError; } if(axis < 0) { axis = inputDimSize + axis + 1; } std::vector shape(static_cast(inputDimSize) + 1); unsigned int inputShapeIndex = 0; for (unsigned int i = 0; i < static_cast(inputDimSize + 1); ++i) { if (i == static_cast(axis)) { shape[i] = 1; } else { shape[i] = inputTensorInfo.GetShape()[inputShapeIndex]; ++inputShapeIndex; } } armnn::ReshapeDescriptor reshapeDesc; reshapeDesc.m_TargetShape = armnn::TensorShape(static_cast(inputDimSize + 1), shape.data()); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("EXPAND_DIMS", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, reshapeDesc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Reshape, nodeIndex, "ExpandDims"); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReshapeLayer(reshapeDesc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputTensorInfo.SetShape(reshapeDesc.m_TargetShape); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } armnn-23.08/delegate/opaque/src/Reduce.hpp000066400000000000000000000141451446772241200204320ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitReduceOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t reduceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteAxisTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, reduceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteAxisTensor); auto* axisTensorData = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); std::vector axis; // Add axis data to vector to be converter to unsigned int and assigned to descriptor axis. if (axisTensorData != nullptr) { for (unsigned int i = 0; i < axisTensorInfo.GetNumElements(); ++i) { axis.emplace_back(axisTensorData[i]); } } else { for (unsigned int i = 0; i < inputTensorInfo.GetNumDimensions(); ++i) { axis.push_back(i); } } // Convert the axis to unsigned int and remove duplicates. unsigned int rank = inputTensorInfo.GetNumDimensions(); std::set uniqueAxis; std::transform(axis.begin(), axis.end(), std::inserter(uniqueAxis, uniqueAxis.begin()), [rank](int i)->unsigned int{ return (i + rank) % rank; }); armnn::ReduceDescriptor desc; desc.m_vAxis.assign(uniqueAxis.begin(), uniqueAxis.end()); auto* reducerParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); desc.m_KeepDims = reducerParameters->keep_dims; if (reduceOperatorCode == kTfLiteBuiltinReduceMax) { desc.m_ReduceOperation = armnn::ReduceOperation::Max; } else if (reduceOperatorCode == kTfLiteBuiltinReduceMin) { desc.m_ReduceOperation = armnn::ReduceOperation::Min; } else if (reduceOperatorCode == kTfLiteBuiltinSum) { desc.m_ReduceOperation = armnn::ReduceOperation::Sum; } else if (reduceOperatorCode == kTfLiteBuiltinReduceProd) { desc.m_ReduceOperation = armnn::ReduceOperation::Prod; } else { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unsupported Reduction Operator #%d node #%d: ", reduceOperatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("REDUCE", tfLiteContext, IsReduceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, desc); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add an Reduce layer auto layerName = GetName(armnn::LayerType::Reduce, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddReduceLayer(desc, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Resize.hpp000066400000000000000000000220231446772241200204560ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateResizeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, const armnn::ResizeDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("RESIZE", tfLiteContext, IsResizeSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitResizeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t resizeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // The first input contains the data of the image that should be resized [batch, height, width, channels] const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // The second input contains a size tensor. The size tensor contains two integer values // that describe the new height and width of the image [new_height, new_width] const TfLiteOpaqueTensor* tfLiteSizeTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (IsDynamicTensor(tfLiteSizeTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // The output tensor should have the shape [batch, new_height, new_width, channels] const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); std::string layerName("Resize"); // Fill descriptor armnn::ResizeDescriptor desc; switch (resizeOperatorCode) { case kTfLiteBuiltinResizeBilinear: { desc.m_Method = armnn::ResizeMethod::Bilinear; layerName += "Bilinear:" + std::to_string(nodeIndex); TfLiteResizeBilinearParams* bilinearOptions = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); desc.m_AlignCorners = bilinearOptions->align_corners; desc.m_HalfPixelCenters = bilinearOptions->half_pixel_centers; break; } case kTfLiteBuiltinResizeNearestNeighbor: { desc.m_Method = armnn::ResizeMethod::NearestNeighbor; layerName += "NearestNeighbor:" + std::to_string(nodeIndex); TfLiteResizeNearestNeighborParams* nearestNeighborOptions = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); desc.m_AlignCorners = nearestNeighborOptions->align_corners; desc.m_HalfPixelCenters = nearestNeighborOptions->half_pixel_centers; break; } default: { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unknown TfLite built in operation for Resize. " "Given operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } } // In Arm NN the values of the size input tensor [new_height, new_width] is saved in the operator // descriptor. We have to read it from the input tensor and write it to the descriptor. auto* sizeTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteSizeTensor)); auto sizeTensorNumDimensions = TfLiteOpaqueTensorNumDims(tfLiteSizeTensor); // The size tensor is only a 1D tensor -> [new_height, new width] if (sizeTensorNumDimensions != 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The Size-Input-Tensor of the Resize operation is not allowed to be a " "dynamic tensor. Operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } // Get number of values in the size tensor auto sizeTensorNumValues = TfLiteOpaqueTensorDim(tfLiteSizeTensor,0); if (sizeTensorNumValues == 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The Size-Input-Tensor of the Resize operation is not allowed to be a " "dynamic tensor. Operator: #%d node #%d: ", resizeOperatorCode, nodeIndex); return kTfLiteError; } else if (sizeTensorNumValues != 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The Size-Input-Tensor of the Resize operation requires to " "have a dimension of 2 [new_height, new width] but a tensor with a dimension of #%d was given. " "Operator: #%d node #%d: ", sizeTensorNumValues, resizeOperatorCode, nodeIndex); return kTfLiteError; } // get size tensor data std::vector sizeTensorData(sizeTensorDataPtr, sizeTensorDataPtr+sizeTensorNumValues); desc.m_TargetHeight = static_cast (sizeTensorData[0]); desc.m_TargetWidth = static_cast (sizeTensorData[1]); desc.m_DataLayout = armnn::DataLayout::NHWC; // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateResizeOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, desc); } armnn::IConnectableLayer* resizeLayer = nullptr; layerName += ":"; layerName += nodeIndex; resizeLayer = delegateData.m_Network->AddResizeLayer(desc, layerName.c_str()); armnn::IOutputSlot& outputSlot = resizeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(resizeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } ARMNN_ASSERT(resizeLayer != nullptr); return Connect(resizeLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/ReverseV2.hpp000066400000000000000000000153451446772241200210510ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateReverseV2Operator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo0, const armnn::TensorInfo& inputInfo1, const armnn::TensorInfo& outputInfo) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("REVERSEV2", tfLiteContext, IsReverseV2Supported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo0, inputInfo1, outputInfo); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitReverseV2Operator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t reverseV2OperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // The first input contains the data to be reversed const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // The second input contains the axis tensor const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (IsDynamicTensor(tfLiteAxisTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Get the output tensor const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& inputTensorInfo1 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteAxisTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); if (inputTensorInfo0.GetNumDimensions() != outputTensorInfo.GetNumDimensions()) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: input tensor dimension and output tensor dimension differ #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } for (unsigned i=0; i < inputTensorInfo0.GetNumDimensions(); i++) { if (inputTensorInfo0.GetShape()[i] != outputTensorInfo.GetShape()[i]) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: input tensor dimension and output tensor differ #%d node #%d: ", reverseV2OperatorCode, nodeIndex); return kTfLiteError; } } // Get axis tensor data auto axisTensorNumValues = static_cast(TfLiteOpaqueTensorDim(tfLiteAxisTensor,0)); const auto maxDimension = 4; if (axisTensorNumValues > maxDimension) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The Axis-Input-Tensor of the ReverseV2 operation requires a " "dimension of <= %d but a tensor with a dimension of %d was given. " "Operator: #%d node #%d: ", maxDimension, axisTensorNumValues, reverseV2OperatorCode, nodeIndex); return kTfLiteError; } // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateReverseV2Operator(delegateData, tfLiteContext, inputTensorInfo0, inputTensorInfo1, outputTensorInfo); } auto layerName = GetName(armnn::LayerType::ReverseV2, nodeIndex); armnn::IConnectableLayer* reverseV2Layer = delegateData.m_Network->AddReverseV2Layer(layerName.c_str()); armnn::IOutputSlot& outputSlot = reverseV2Layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(reverseV2Layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } ARMNN_ASSERT(reverseV2Layer != nullptr); return Connect(reverseV2Layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Round.hpp000066400000000000000000000070231446772241200203070ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include namespace armnnOpaqueDelegate { TfLiteStatus VisitFloorOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. int numInputs = 0; const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Use input indices to get input tensors. const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); // NOTE: looks like the outputTensorInfo is the only thing that is required for the case // where we are adding the floor layer so maybe move the other stuff inside the // if !delegateData block for efficiency. const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitFloorOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { return ValidateFloorOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo); } // Add a Floor layer auto layerName = GetName(armnn::LayerType::Floor, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddFloorLayer(layerName.c_str()); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Shape.hpp000066400000000000000000000105651446772241200202650ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitShapeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* shapeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); if (shapeParameters->out_type != kTfLiteInt32 && shapeParameters->out_type != kTfLiteInt64) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: output_type data type is not supported in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SHAPE", tfLiteContext, IsShapeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo); }; // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator // If supported, VisitShapeOperator will be called again to add the layer to the network as seen further below if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Shape layer auto layerName = GetName(armnn::LayerType::Shape, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddShapeLayer(layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/SharedFunctions.cpp000066400000000000000000000070451446772241200223160ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SharedFunctions.hpp" #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateFloorOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputTensorInfo, const armnn::TensorInfo& outputTensorInfo) { bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("FLOOR", tfLiteContext, IsFloorSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputTensorInfo, outInfo); }; validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateFusedActivationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, TfLiteFusedActivation activationType) { armnn::ActivationDescriptor activationDesc; switch (activationType) { case kTfLiteActNone: { // No Activation return kTfLiteOk; } case kTfLiteActRelu: { activationDesc.m_Function = armnn::ActivationFunction::ReLu; break; } case kTfLiteActReluN1To1: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 1.0f; activationDesc.m_B = -1.0f; break; } case kTfLiteActRelu6: { activationDesc.m_Function = armnn::ActivationFunction::BoundedReLu; activationDesc.m_A = 6.0f; activationDesc.m_B = 0.0f; break; } case kTfLiteActSigmoid: { activationDesc.m_Function = armnn::ActivationFunction::Sigmoid; break; } case kTfLiteActTanh: { activationDesc.m_Function = armnn::ActivationFunction::TanH; activationDesc.m_A = 1.0f; activationDesc.m_B = 1.0f; break; } default: return kTfLiteError; } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("ACTIVATION", tfLiteContext, IsActivationSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, activationDesc); }; validateFunc(outputInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } } // namespace armnnDelegate armnn-23.08/delegate/opaque/src/SharedFunctions.hpp000066400000000000000000000017021446772241200223150ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateFloorOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputTensorInfo, const armnn::TensorInfo& outputTensorInfo); TfLiteStatus ValidateFusedActivationOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, TfLiteFusedActivation activationType); } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Slice.hpp000066400000000000000000000164631446772241200202670ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitSliceOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteSliceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Read inputs [input, begin, size] // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } std::vector tfLiteInputTensors; tfLiteInputTensors.reserve(numInputs); for (int i = 0; i < numInputs; i++) { const TfLiteOpaqueTensor* inputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[i]); tfLiteInputTensors.push_back(inputTensor); if (!IsValid(tfLiteContext, inputTensor, tfLiteSliceOperatorCode, nodeIndex)) { return kTfLiteError; } } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensors[0]); // We save the begin and size tensors in our descriptor. Therefore we have to read those values from inputs unsigned int inputRank = inputTensorInfo.GetNumDimensions(); auto ReadInt32Input = [&](int inputIndex, std::vector& outputData, const char* name) -> TfLiteStatus { if (TfLiteOpaqueTensorType(tfLiteInputTensors[inputIndex]) != kTfLiteInt32) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The %s Tensor of the Slice operation needs to " "be of type int32. Operator: #%d node #%d: ", name, tfLiteSliceOperatorCode, nodeIndex); return kTfLiteError; } uint32_t rank = TfLiteOpaqueTensorNumDims(tfLiteInputTensors[inputIndex]); if (rank != 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The %s Tensor of the Slice operation needs to " "be a 1D-Tensor. Operator: #%d node #%d: ", name, tfLiteSliceOperatorCode, nodeIndex); return kTfLiteError; } uint32_t numValues = TfLiteOpaqueTensorDim(tfLiteInputTensors[inputIndex], 0); if (numValues != inputRank) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The number of values in the %s Tensor of the " "Slice operation needs to be equal to the rank of the Input Tensor. Operator: #%d node #%d: ", name, tfLiteSliceOperatorCode, nodeIndex); return kTfLiteError; } // return tensor data auto* tensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteInputTensors[inputIndex])); outputData.assign(tensorDataPtr, tensorDataPtr + numValues); return kTfLiteOk; }; std::vector signedBegin; if (ReadInt32Input(1, signedBegin, "Begin") != kTfLiteOk) { return kTfLiteError; } std::vector signedSize; if (ReadInt32Input(2, signedSize, "Size") != kTfLiteOk) { return kTfLiteError; } std::vector begin({ signedBegin.begin(), signedBegin.end() }); std::vector size(signedSize.size()); for (unsigned int i = 0; i < signedSize.size(); ++i) { int signedValue = signedSize[i]; if (signedValue < -1 || signedValue > TfLiteOpaqueTensorDim(tfLiteInputTensors[0], i) - signedBegin[i]) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnDelegate: Invalid value for Size. Size must be in range [-1, inputDimSize - begin] " "[-1, %d] inclusive but was %d Operator: #%d node #%d: ", TfLiteOpaqueTensorDim(tfLiteInputTensors[0], i) - signedBegin[i], signedValue, tfLiteSliceOperatorCode, nodeIndex); return kTfLiteError; } if (signedValue == -1) { size[i] = TfLiteOpaqueTensorDim(tfLiteInputTensors[0], i) - signedBegin[i]; } else { size[i] = static_cast(signedValue); } } // Write all data to the descriptor armnn::SliceDescriptor descriptor(begin, size); // Validate output // Gather output indices and use to get output tensor. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSliceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SLICE", tfLiteContext, IsSliceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a Slice layer auto layerName = GetName(armnn::LayerType::Slice, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSliceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Softmax.hpp000066400000000000000000000151451446772241200206450ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateSoftmaxOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputTensorInfo, const armnn::SoftmaxDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SOFTMAX", tfLiteContext, IsSoftmaxSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus ValidateLogSoftmaxOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputTensorInfo, const armnn::LogSoftmaxDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("LOG_SOFTMAX", tfLiteContext, IsLogSoftmaxSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputTensorInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitSoftmaxOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfliteSoftmaxOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfliteSoftmaxOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensor. const int* outputTensors; int numOutputs = 0; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfliteSoftmaxOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { switch(tfliteSoftmaxOperatorCode) { case kTfLiteBuiltinSoftmax: { armnn::SoftmaxDescriptor descriptor; auto* nodeParams = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_Beta = nodeParams->beta; return ValidateSoftmaxOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, descriptor); } case kTfLiteBuiltinLogSoftmax: { armnn::LogSoftmaxDescriptor descriptor; return ValidateLogSoftmaxOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, descriptor); } default: return kTfLiteError; } } armnn::IConnectableLayer* softmaxLayer = nullptr; auto layerName = GetName(armnn::LayerType::Softmax, nodeIndex); switch(tfliteSoftmaxOperatorCode) { case kTfLiteBuiltinSoftmax: { armnn::SoftmaxDescriptor descriptor; auto* nodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_Beta = nodeParameters->beta; softmaxLayer = delegateData.m_Network->AddSoftmaxLayer(descriptor, layerName.c_str()); break; } case kTfLiteBuiltinLogSoftmax: { armnn::LogSoftmaxDescriptor descriptor; softmaxLayer = delegateData.m_Network->AddLogSoftmaxLayer(descriptor, layerName.c_str()); break; } default: return kTfLiteError; } ARMNN_ASSERT(softmaxLayer != nullptr); armnn::IOutputSlot& outputSlot = softmaxLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(softmaxLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(softmaxLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/SpaceDepth.hpp000066400000000000000000000174031446772241200212430ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitSpaceToDepthOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteSpaceDepthOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteSpaceDepthOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSpaceDepthOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::SpaceToDepthDescriptor descriptor; auto* nodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_BlockSize = nodeParameters->block_size; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SPACE_TO_DEPTH", tfLiteContext, IsSpaceToDepthSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a SpaceToDepth layer auto layerName = GetName(armnn::LayerType::SpaceToDepth, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSpaceToDepthLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } TfLiteStatus VisitDepthToSpaceOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteDepthSpaceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteDepthSpaceOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteDepthSpaceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); armnn::DepthToSpaceDescriptor descriptor; auto* nodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); descriptor.m_BlockSize = nodeParameters->block_size; bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("DEPTH_TO_SPACE", tfLiteContext, IsDepthToSpaceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a DepthToSpace layer auto layerName = GetName(armnn::LayerType::DepthToSpace, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddDepthToSpaceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Split.hpp000066400000000000000000000376211446772241200203220ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include #include namespace armnnOpaqueDelegate { constexpr unsigned int MaxNumOfTensorDimensions = 5U; TfLiteStatus VisitSplitOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteSplitOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); auto* splitParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); int numSplits = NonNegative(splitParameters->num_splits, nodeIndex); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, numSplits, nodeIndex)); // Gather input indices and use to get Axis tensor. const int* inputTensors; auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteAxisTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } // Use input indices to get input tensor. const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numSplits) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); if (GetTensorInfoForTfLiteOpaqueTensor(tfLiteAxisTensor).GetNumElements() != 1) { return kTfLiteError; } auto* axisTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); std::vector axisTensorData(axisTensorDataPtr, axisTensorDataPtr + 1); int32_t axis = axisTensorData[0]; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { // Square bracket denotes inclusive n while parenthesis denotes exclusive n // E.g. Rank 4 tensor can have axis in range [-4, 3) // -1 == 3, -2 == 2, -3 == 1, -4 == 0 TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: Operation has invalid axis: #%d. " "Axis must be in range [-n, n) in node #%d:", axis, nodeIndex); } const unsigned int splitDim = ComputeWrappedIndex(axis, inputTensorInfo.GetNumDimensions()); std::vector outputs; for (int i = 0; i < numSplits; ++i) { const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[i]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSplitOperatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); auto inputDimSize = inputTensorInfo.GetNumDimensions(); if (inputDimSize > MaxNumOfTensorDimensions) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: The number of dimensions: #%d for input tensors of the split op cannot be " "greater than #%d in node #%d: ", inputDimSize, MaxNumOfTensorDimensions, nodeIndex); return kTfLiteError; } std::vector splitterDimSizes(inputDimSize); // Add current input shape to splitterDimSizes for (unsigned int i = 0; i < inputDimSize; ++i) { splitterDimSizes[i] = inputTensorInfo.GetShape()[i]; } if (splitterDimSizes[splitDim] % numSplits != 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: Number of splits #%d must evenly divide the dimension #%d in node #%d: ", numSplits, splitterDimSizes[splitDim], nodeIndex); return kTfLiteError; } splitterDimSizes[splitDim] /= numSplits; armnn::SplitterDescriptor splitDescriptor(numSplits, inputDimSize); for (int j = 0; j < numSplits; ++j) { // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < splitterDimSizes.size(); ++dimIdx) { splitDescriptor.SetViewSize(j, dimIdx, splitterDimSizes[dimIdx]); } splitDescriptor.SetViewOriginCoord(j, splitDim, splitterDimSizes[splitDim] * j); } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SPLIT", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfos, splitDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Splitter, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSplitterLayer(splitDescriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); for (unsigned int k = 0; k < layer->GetNumOutputSlots(); ++k) { layer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // Connect the input slots delegateData.m_OutputSlotForNode[inputTensors[1]]->Connect(layer->GetInputSlot(0)); if(numSplits != static_cast(layer->GetNumOutputSlots())) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: Expected number of splits #%d does not " "match the number of output slots #%d in node #%d: ", numSplits, layer->GetNumOutputSlots(), nodeIndex); return kTfLiteError; } // Prepare output slots for (unsigned int outputIndex = 0; outputIndex < layer->GetNumOutputSlots(); ++outputIndex) { armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(outputIndex); delegateData.m_OutputSlotForNode[ static_cast(outputTensors[outputIndex])] = &outputSlot; } return kTfLiteOk; } TfLiteStatus VisitSplitVOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteSplitVOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 3, nodeIndex)); const int* inputTensors; auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteSplitsTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteSplitsTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteAxisTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[2]); if (!IsValid(tfLiteContext, tfLiteAxisTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& splitsTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteSplitsTensor); if (splitsTensorInfo.GetNumDimensions() != 1) { return kTfLiteError; } if (GetTensorInfoForTfLiteOpaqueTensor(tfLiteAxisTensor).GetNumElements() != 1) { return kTfLiteError; } auto* axisTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteAxisTensor)); std::vector axisTensorData(axisTensorDataPtr, axisTensorDataPtr + 1); int32_t axis = axisTensorData[0]; auto inputDimensions = static_cast(inputTensorInfo.GetNumDimensions()); if (((axis < -inputDimensions) && (axis < 0)) || ((axis >= inputDimensions) && (axis > 0))) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: Operation has invalid axis: #%d. " "Axis must be in range [-n, n) in node #%d:", axis, nodeIndex); } const unsigned int splitDim = ComputeWrappedIndex(axisTensorData[0], inputTensorInfo.GetNumDimensions()); auto* splitVParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); int numSplits = 0; if (splitVParameters) { numSplits = NonNegative(splitVParameters->num_splits, nodeIndex); } else { numSplits = splitsTensorInfo.GetNumElements(); } if (numSplits <= 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: Invalid number of splits %d in node #%d", numSplits, nodeIndex); return kTfLiteError; } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, numSplits, nodeIndex)); // Gather output indices and use to get output tensors. const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numSplits) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } std::vector outputs; for (int i = 0; i < numSplits; ++i) { const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[i]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteSplitVOperatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); auto inputDimSize = inputTensorInfo.GetNumDimensions(); if (inputDimSize > MaxNumOfTensorDimensions) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: The number of dimensions: #%d for input tensors of the split op cannot be " "greater than #%d in node #%d: ", inputDimSize, MaxNumOfTensorDimensions, nodeIndex); return kTfLiteError; } std::vector splitsTensorData(numSplits); std::memcpy(splitsTensorData.data(), TfLiteOpaqueTensorData(tfLiteSplitsTensor), splitsTensorInfo.GetNumBytes()); unsigned int index = 0; unsigned int inferredIndex = 0; int numberOfInferred = 0; int splitSum = 0; for (auto splitData : splitsTensorData) { if (splitData < 0) { ++numberOfInferred; inferredIndex = index; } else { splitSum += splitData; } ++index; } // Check for inferred axis if (numberOfInferred == 0) { if (splitSum != armnn::numeric_cast(inputTensorInfo.GetShape()[splitDim])) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: SplitV split_sizes does not sum to the dimension " "of value along split_dim in node #%d", nodeIndex); return kTfLiteError; } } else if (numberOfInferred == 1) { splitsTensorData[inferredIndex] = armnn::numeric_cast(inputTensorInfo.GetShape()[splitDim]) - splitSum; } else { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteOpaqueArmnnDelegate: SplitV cannot infer split size for " "more than one split in node #%d", nodeIndex); return kTfLiteError; } armnn::SplitterDescriptor splitDescriptor(numSplits, inputDimSize); unsigned int accumSplit = 0; for (int j = 0; j < numSplits; ++j) { unsigned int splitSize = armnn::numeric_cast(splitsTensorData[j]); // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < inputTensorInfo.GetNumDimensions(); ++dimIdx) { unsigned int dimSize = inputTensorInfo.GetShape()[dimIdx]; if (dimIdx == splitDim) { dimSize = splitSize; } splitDescriptor.SetViewSize(j, dimIdx, dimSize); } splitDescriptor.SetViewOriginCoord(j, splitDim, accumSplit); accumSplit += splitSize; } armnn::BackendId setBackend; if (!delegateData.m_Network) { // Check if supported bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("SPLITV", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputTensorInfos, splitDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Splitter, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddSplitterLayer(splitDescriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); for (unsigned int k = 0; k < layer->GetNumOutputSlots(); ++k) { layer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/StridedSlice.hpp000066400000000000000000000162411446772241200216000ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitStridedSliceOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfLiteStridedSliceOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 4, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Read inputs [input, begin, end, strides] // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } std::vector tfLiteInputTensors; tfLiteInputTensors.reserve(numInputs); for (int i = 0; i < numInputs; i++) { const TfLiteOpaqueTensor* inputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[i]); tfLiteInputTensors.push_back(inputTensor); if (!IsValid(tfLiteContext, inputTensor, tfLiteStridedSliceOperatorCode, nodeIndex)) { return kTfLiteError; } } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensors[0]); // We save the begin, end and strides tensors in our descriptor. Therefore we have to read those values from inputs unsigned int inputRank = inputTensorInfo.GetNumDimensions(); auto ReadInt32Input = [&](int inputIndex, std::vector& outputData) -> TfLiteStatus { if (TfLiteOpaqueTensorType(tfLiteInputTensors[inputIndex]) != kTfLiteInt32) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLitearmnnOpaqueDelegate: The Begin-, End- and Stride-Tensors of the StridedSlice operation need" " to be of type int32. Operator: #%d node #%d: ", tfLiteStridedSliceOperatorCode, nodeIndex); return kTfLiteError; } uint32_t rank = TfLiteOpaqueTensorNumDims(tfLiteInputTensors[inputIndex]); if (rank != 1) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLitearmnnOpaqueDelegate: The Begin-, End- and Stride-Tensors of the StridedSlice operation need" " to be a 1D-Tensor. Operator: #%d node #%d: ", tfLiteStridedSliceOperatorCode, nodeIndex); return kTfLiteError; } uint32_t numValues = TfLiteOpaqueTensorDim(tfLiteInputTensors[inputIndex], 0); if (numValues != inputRank) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLitearmnnOpaqueDelegate: The number of values in the Begin-, End- and Stride-Tensors of the " "StridedSlice operation need to be equal to the rank of the Input-Tensor. Operator: #%d node #%d: ", tfLiteStridedSliceOperatorCode, nodeIndex); return kTfLiteError; } // return tensor data auto* tensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteInputTensors[inputIndex])); outputData.assign(tensorDataPtr, tensorDataPtr + numValues); return kTfLiteOk; }; std::vector beginData; if (ReadInt32Input(1, beginData) != kTfLiteOk) return kTfLiteError; std::vector endData; if (ReadInt32Input(2, endData) != kTfLiteOk) return kTfLiteError; std::vector strideData; if (ReadInt32Input(3, strideData) != kTfLiteOk) return kTfLiteError; // parse built in options auto* nodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); // Write all data to the descriptor armnn::StridedSliceDescriptor descriptor; descriptor.m_Begin = std::move(beginData); descriptor.m_End = std::move(endData); descriptor.m_Stride = std::move(strideData); descriptor.m_BeginMask = nodeParameters->begin_mask; descriptor.m_EllipsisMask = nodeParameters->ellipsis_mask; descriptor.m_EndMask = nodeParameters->end_mask; descriptor.m_NewAxisMask = nodeParameters->new_axis_mask; descriptor.m_ShrinkAxisMask = nodeParameters->shrink_axis_mask; descriptor.m_DataLayout = armnn::DataLayout::NHWC; // Validate output // Gather output indices and use to get output tensor. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfLiteStridedSliceOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("STRIDED_SLICE", tfLiteContext, IsStridedSliceSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } // Add a StridedSlice layer auto layerName = GetName(armnn::LayerType::StridedSlice, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddStridedSliceLayer(descriptor, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } // Connect return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/Tile.hpp000066400000000000000000000165251446772241200201240ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus ValidateTileOperator(DelegateData& delegateData, TfLiteOpaqueContext *tfLiteContext, const armnn::TensorInfo& inputInfo, const armnn::TensorInfo& outputInfo, const armnn::TileDescriptor& descriptor) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("TILE", tfLiteContext, IsTileSupported, delegateData.m_Backends, isSupported, armnn::BackendId(), inputInfo, outputInfo, descriptor); return isSupported ? kTfLiteOk : kTfLiteError; } TfLiteStatus VisitTileOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tileOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input tensors auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Gather output tensors int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // The input contains the data that should be tiled const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (IsDynamicTensor(tfLiteInputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // The multiples tensor contains the number of copies for each axis const TfLiteOpaqueTensor* tfLiteMultiplesTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]);; if (IsDynamicTensor(tfLiteMultiplesTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic input tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // The output tensor const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (IsDynamicTensor(tfLiteOutputTensor)) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Dynamic output tensors are not supported in operator #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& multiplesTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteMultiplesTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); // Multiples length must be the same as the number of dimension in input tensor if (multiplesTensorInfo.GetNumElements() != inputTensorInfo.GetNumDimensions()) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate:", "The Multiples length must be the same as the number of dimension in input tensor", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // Get the Multiples data: In armnn, the values of the multiples input tensor is saved in the operator descriptor // We have to read it from the input tensor and write it the descriptor auto* multiplesTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteMultiplesTensor)); auto multiplesTensorNum = TfLiteOpaqueTensorDim(tfLiteMultiplesTensor, 0); std::vector multiplesIntData(multiplesTensorDataPtr, multiplesTensorDataPtr + multiplesTensorNum); // The multiples must be positive for (auto multiple : multiplesIntData) { if (multiple < 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The Multiples must be positive values", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } } // The original input from TFLite is int32, and we have to make it as uint32 for our descriptor std::vector multiplesUintData; std::transform(multiplesIntData.begin(), multiplesIntData.end(), std::back_inserter(multiplesUintData), [] (const int value) { return static_cast(value); }); armnn::TileDescriptor tileDescriptor; tileDescriptor.m_Multiples = multiplesUintData; // Check output dimensions if (inputTensorInfo.GetNumDimensions() != outputTensorInfo.GetNumDimensions()) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Input tensor dimension and output tensor dimension differ", "Operator: #%d node #%d: ", tileOperatorCode, nodeIndex); return kTfLiteError; } // No network pointer indicates that only support for this operator should be checked if (!delegateData.m_Network) { return ValidateTileOperator(delegateData, tfLiteContext, inputTensorInfo, outputTensorInfo, tileDescriptor); } auto layerName = GetName(armnn::LayerType::Tile, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddTileLayer(tileDescriptor, layerName.c_str()); if (layer == nullptr) { return kTfLiteError; } layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); if (ProcessInputs(layer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(layer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Transpose.hpp000066400000000000000000000115061446772241200211770ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitTransposeOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t tfliteTransposeOperatorCode) { TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); // Gather input indices and use to get input tensor. const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor0 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor0, tfliteTransposeOperatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor1 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); if (!IsValid(tfLiteContext, tfLiteInputTensor1, tfliteTransposeOperatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfliteTransposeOperatorCode, nodeIndex)) { return kTfLiteError; } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor0); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); auto* permTensorDataPtr = static_cast(TfLiteOpaqueTensorData(tfLiteInputTensor1)); unsigned int numEl = TfLiteOpaqueTensorDim(tfLiteInputTensor1, 0); if ( numEl > static_cast(armnn::MaxNumOfTensorDimensions) ) { return kTfLiteError; } // Ensure only single dimension to the permutation tensor if ( TfLiteOpaqueTensorNumDims(tfLiteInputTensor1) != 1 ) { return kTfLiteError; } armnn::TransposeDescriptor descriptor(armnn::PermutationVector( reinterpret_cast (permTensorDataPtr), static_cast(numEl))); bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("TRANSPOSE", tfLiteContext, IsTransposeSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo0, outputTensorInfo, descriptor); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::Transpose, nodeIndex); armnn::IConnectableLayer* transposeLayer = delegateData.m_Network->AddTransposeLayer(descriptor, layerName.c_str()); transposeLayer->SetBackendId(setBackend); ARMNN_ASSERT(transposeLayer != nullptr); // Permutation vector given to descriptor object if (transposeLayer->GetNumInputSlots() != 1) { return kTfLiteError; } armnn::IOutputSlot& outputSlot = transposeLayer->GetOutputSlot(0); outputSlot.SetTensorInfo(outputTensorInfo); // try to connect the Constant Inputs if there are any if (ProcessInputs(transposeLayer, delegateData, tfLiteContext, tfLiteNode, nodeIndex) != kTfLiteOk) { return kTfLiteError; } return Connect(transposeLayer, tfLiteContext, tfLiteNode, delegateData); } } // namespace armnnOpaqueDelegate armnn-23.08/delegate/opaque/src/UnidirectionalSequenceLstm.hpp000066400000000000000000000375141446772241200245320ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitUnidirectionalSequenceLstmOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { auto numInputs = TfLiteOpaqueNodeNumberOfInputs(tfLiteNode); if (numInputs < 2) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Minimum number of inputs (%d != %d) in node #%d", 2, numInputs, nodeIndex); return kTfLiteError; } // Gather input indices and use to get input tensor. const int* inputTensors; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Gather output indices and use to get output tensors. int numOutputs = 0; const int* outputTensors; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } // Set the params structure for the AddUnidirectionalSequenceLstmLayer call // Please refer to each operand at // https://www.tensorflow.org/mlir/tfl_ops#tflunidirectional_sequence_lstm_tflunidirectionalsequencelstmop armnn::LstmInputParams params; if (IsOptionalOperandPresent(tfLiteNode, 1)) { params.m_InputToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 1); } params.m_InputToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 2); params.m_InputToCellWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 3); params.m_InputToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 4); // Recurrent weight tensors of size {n_cell, n_output} if (IsOptionalOperandPresent(tfLiteNode, 5)) { params.m_RecurrentToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 5); } params.m_RecurrentToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 6); params.m_RecurrentToCellWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 7); params.m_RecurrentToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 8); // Peephole weights tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 9)) { params.m_CellToInputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 9); } if (IsOptionalOperandPresent(tfLiteNode, 10)) { params.m_CellToForgetWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 10); } if (IsOptionalOperandPresent(tfLiteNode, 11)) { params.m_CellToOutputWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 11); } // Gates bias tensors of size {n_cell} if (IsOptionalOperandPresent(tfLiteNode, 12)) { params.m_InputGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 12); } params.m_ForgetGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 13); params.m_CellBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 14); params.m_OutputGateBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 15); // Projection weight tensor of size {n_output, n_cell} if (IsOptionalOperandPresent(tfLiteNode, 16)) { params.m_ProjectionWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 16); } // Projection bias tensor of size {n_output} if (IsOptionalOperandPresent(tfLiteNode, 17)) { params.m_ProjectionBias = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 17); } // These state tensors are defined as variable tensors, and will be modified by this op. const TfLiteOpaqueTensor* tfLiteOutputStateIn = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[18]); if (!IsValid(tfLiteContext, tfLiteOutputStateIn, operatorCode, nodeIndex)) { return kTfLiteError; } const TfLiteOpaqueTensor* cellStateIn = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[19]); if (!IsValid(tfLiteContext, cellStateIn, operatorCode, nodeIndex)) { return kTfLiteError; } armnn::TensorInfo outputStateInInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputStateIn); armnn::TensorInfo cellStateInInfo = GetTensorInfoForTfLiteOpaqueTensor(cellStateIn); // Layer norm coefficient tensors of size {n_cell}, representing a diagonal matrix. if (IsOptionalOperandPresent(tfLiteNode, 20)) { params.m_InputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 20); } if (IsOptionalOperandPresent(tfLiteNode, 21)) { params.m_ForgetLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 21); } if (IsOptionalOperandPresent(tfLiteNode, 22)) { params.m_CellLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 22); } if (IsOptionalOperandPresent(tfLiteNode, 23)) { params.m_OutputLayerNormWeights = GetConstTensorForTfLiteTensor(tfLiteContext, tfLiteNode, 23); } const auto nodeParams = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); // set the layer descriptor armnn::UnidirectionalSequenceLstmDescriptor desc; desc.m_ActivationFunc = NonNegative(nodeParams->activation, nodeIndex); desc.m_ClippingThresCell = nodeParams->cell_clip; desc.m_ClippingThresProj = nodeParams->proj_clip; desc.m_CifgEnabled = (params.m_InputToInputWeights == nullptr || params.m_RecurrentToInputWeights == nullptr || params.m_InputGateBias == nullptr); desc.m_PeepholeEnabled = (params.m_CellToForgetWeights != nullptr || params.m_CellToOutputWeights != nullptr); desc.m_ProjectionEnabled = (params.m_ProjectionWeights != nullptr); desc.m_LayerNormEnabled = (params.m_InputLayerNormWeights != nullptr || params.m_ForgetLayerNormWeights != nullptr || params.m_CellLayerNormWeights != nullptr || params.m_OutputLayerNormWeights != nullptr); desc.m_TimeMajor = nodeParams->time_major; // Intermediates tensors aren't accessible through the new Opaque Interface yet, so we have to cast it for now. // This should be changed to use the accessor functions once added. auto* classicTfliteNode = reinterpret_cast(tfLiteNode); if (classicTfliteNode->intermediates->size > 3 && desc.m_LayerNormEnabled) { auto inputIntermediateTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, classicTfliteNode->intermediates->data[0])); auto forgetIntermediateTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, classicTfliteNode->intermediates->data[1])); auto cellIntermediateTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, classicTfliteNode->intermediates->data[2])); auto outputIntermediateTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, classicTfliteNode->intermediates->data[3])); desc.m_InputIntermediateScale = inputIntermediateTensorInfo.GetQuantizationScale(); desc.m_ForgetIntermediateScale = forgetIntermediateTensorInfo.GetQuantizationScale(); desc.m_CellIntermediateScale = cellIntermediateTensorInfo.GetQuantizationScale(); desc.m_OutputIntermediateScale = outputIntermediateTensorInfo.GetQuantizationScale(); } else { float defaultIntermediate = std::pow(2, -12); desc.m_InputIntermediateScale = defaultIntermediate; desc.m_ForgetIntermediateScale = defaultIntermediate; desc.m_CellIntermediateScale = defaultIntermediate; desc.m_OutputIntermediateScale = defaultIntermediate; } if (classicTfliteNode->intermediates->size > 4) { auto hiddenTensorInfo = GetTensorInfoForTfLiteOpaqueTensor( TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, classicTfliteNode->intermediates->data[4])); desc.m_HiddenStateScale = hiddenTensorInfo.GetQuantizationScale(); desc.m_HiddenStateZeroPoint = hiddenTensorInfo.GetQuantizationOffset(); } float defaultIntermediate = std::pow(2, -12); desc.m_InputIntermediateScale = defaultIntermediate; desc.m_ForgetIntermediateScale = defaultIntermediate; desc.m_CellIntermediateScale = defaultIntermediate; desc.m_OutputIntermediateScale = defaultIntermediate; const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[2]; unsigned int numUnits = cellStateInInfo.GetShape()[1]; armnn::DataType dataType = inputTensorInfo.GetDataType(); float qScale = inputTensorInfo.GetQuantizationScale(); float qOffset = inputTensorInfo.GetQuantizationOffset(); armnn::TensorInfo scratchBufferTensorInfo({batchSize, numUnits * 3}, dataType, qScale, qOffset); if (!desc.m_CifgEnabled) { scratchBufferTensorInfo = armnn::TensorInfo({batchSize, numUnits * 4}, dataType, qScale, qOffset); } armnn::TensorInfo cellStateOutTensorInfo({batchSize, numUnits}, cellStateInInfo.GetDataType(), cellStateInInfo.GetQuantizationScale(), cellStateInInfo.GetQuantizationOffset()); armnn::TensorInfo outputStateOutTensorInfo({batchSize, outputSize}, dataType, qScale, qOffset); armnn::LstmInputParamsInfo paramsInfo; paramsInfo.m_InputToForgetWeights = &(params.m_InputToForgetWeights->GetInfo()); paramsInfo.m_InputToCellWeights = &(params.m_InputToCellWeights->GetInfo()); paramsInfo.m_InputToOutputWeights = &(params.m_InputToOutputWeights->GetInfo()); paramsInfo.m_RecurrentToForgetWeights = &(params.m_RecurrentToForgetWeights->GetInfo()); paramsInfo.m_RecurrentToCellWeights = &(params.m_RecurrentToCellWeights->GetInfo()); paramsInfo.m_RecurrentToOutputWeights = &(params.m_RecurrentToOutputWeights->GetInfo()); paramsInfo.m_ForgetGateBias = &(params.m_ForgetGateBias->GetInfo()); paramsInfo.m_CellBias = &(params.m_CellBias->GetInfo()); paramsInfo.m_OutputGateBias = &(params.m_OutputGateBias->GetInfo()); if (!desc.m_CifgEnabled) { paramsInfo.m_InputToInputWeights = &(params.m_InputToInputWeights->GetInfo()); paramsInfo.m_RecurrentToInputWeights = &(params.m_RecurrentToInputWeights->GetInfo()); if (params.m_CellToInputWeights != nullptr) { paramsInfo.m_CellToInputWeights = &(params.m_CellToInputWeights->GetInfo()); } paramsInfo.m_InputGateBias = &(params.m_InputGateBias->GetInfo()); } if (desc.m_ProjectionEnabled) { paramsInfo.m_ProjectionWeights = &(params.m_ProjectionWeights->GetInfo()); if (params.m_ProjectionBias != nullptr) { paramsInfo.m_ProjectionBias = &(params.m_ProjectionBias->GetInfo()); } } if (desc.m_PeepholeEnabled) { paramsInfo.m_CellToForgetWeights = &(params.m_CellToForgetWeights->GetInfo()); paramsInfo.m_CellToOutputWeights = &(params.m_CellToOutputWeights->GetInfo()); } if (desc.m_LayerNormEnabled) { if(!desc.m_CifgEnabled) { paramsInfo.m_InputLayerNormWeights = &(params.m_InputLayerNormWeights->GetInfo()); } paramsInfo.m_ForgetLayerNormWeights = &(params.m_ForgetLayerNormWeights->GetInfo()); paramsInfo.m_CellLayerNormWeights = &(params.m_CellLayerNormWeights->GetInfo()); paramsInfo.m_OutputLayerNormWeights = &(params.m_OutputLayerNormWeights->GetInfo()); } bool isSupported = false; armnn::BackendId setBackend; auto validateFunc = [&](const armnn::TensorInfo& outputInfo, bool& isSupported) { FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("UNIDIRECTIONAL_SEQUENCE_LSTM", tfLiteContext, IsUnidirectionalSequenceLstmSupported, delegateData.m_Backends, isSupported, setBackend, inputTensorInfo, outputStateInInfo, cellStateInInfo, outputStateOutTensorInfo, cellStateOutTensorInfo, outputInfo, desc, paramsInfo); }; if (!delegateData.m_Network) { validateFunc(outputTensorInfo, isSupported); return isSupported ? kTfLiteOk : kTfLiteError; } auto layerName = GetName(armnn::LayerType::UnidirectionalSequenceLstm, nodeIndex); armnn::IConnectableLayer* layer = delegateData.m_Network->AddUnidirectionalSequenceLstmLayer(desc, params, layerName.c_str()); layer->SetBackendId(setBackend); ARMNN_ASSERT(layer != nullptr); layer->GetOutputSlot(0).SetTensorInfo(outputStateOutTensorInfo); layer->GetOutputSlot(1).SetTensorInfo(cellStateOutTensorInfo); layer->GetOutputSlot(2).SetTensorInfo(outputTensorInfo); // Connect the inputs // input_layer delegateData.m_OutputSlotForNode[inputTensors[0]]->Connect(layer->GetInputSlot(0)); // cellStateIn delegateData.m_OutputSlotForNode[inputTensors[18]]->Connect(layer->GetInputSlot(1)); //outputStateIn delegateData.m_OutputSlotForNode[inputTensors[19]]->Connect(layer->GetInputSlot(2)); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(2); delegateData.m_OutputSlotForNode[static_cast(outputTensors[0])] = &outputSlot; return kTfLiteOk; } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/Unpack.hpp000066400000000000000000000234241446772241200204440ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include namespace armnnOpaqueDelegate { TfLiteStatus VisitUnpackOperator(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode, int nodeIndex, int32_t operatorCode) { // Check inputs TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); const int* inputTensors; int numInputs; if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } const TfLiteOpaqueTensor* tfLiteInputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } auto* tfLiteNodeParameters = reinterpret_cast(TfLiteOpaqueNodeGetBuiltinData(tfLiteNode)); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor); // Get Unpack Axis const unsigned int unpackAxis = NonNegative(tfLiteNodeParameters->axis, nodeIndex); if (unpackAxis >= inputTensorInfo.GetNumDimensions()) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: The unpack axis #%d cannot be greater than or equal to " "the number of input dimensions #%d in operator #%d node #%d", unpackAxis, inputTensorInfo.GetNumDimensions(), operatorCode, nodeIndex); return kTfLiteError; } // Get Unpack Num unsigned int unpackNum = NonNegative(tfLiteNodeParameters->num, nodeIndex); // If num is not defined, automatically infer from the length of the dimension axis. if(unpackNum == 0) { unpackNum = inputTensorInfo.GetShape()[unpackAxis]; } // If unpack number cannot be inferred and is still zero, return kTfLiteError. if(unpackNum == 0) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Number to unpack must greater than zero in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } // Check outputs TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, unpackNum, nodeIndex)); auto inputDimSize = inputTensorInfo.GetNumDimensions(); std::vector unpackDimSizes(inputDimSize); // Add current input shape to unpackDimSizes for (unsigned int i = 0; i < inputDimSize; ++i) { unpackDimSizes[i] = inputTensorInfo.GetShape()[i]; } if (unpackDimSizes[unpackAxis] != unpackNum) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Number to unpack must be the same as length " "of the dimension to unpack along in operator #%d node #%d: ", operatorCode, nodeIndex); return kTfLiteError; } unpackDimSizes[unpackAxis] /= unpackNum; armnn::SplitterDescriptor splitDesc(unpackNum, static_cast(unpackDimSizes.size())); for (unsigned int j = 0; j < unpackNum; ++j) { // Set the size of the views. for (unsigned int dimIdx = 0; dimIdx < unpackDimSizes.size(); ++dimIdx) { splitDesc.SetViewSize(j, dimIdx, unpackDimSizes[dimIdx]); } splitDesc.SetViewOriginCoord(j, unpackAxis, unpackDimSizes[unpackAxis] * j); } // Gather output indices and use to get output tensors. const int* outputTensors; int numOutputs; if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) { TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", nodeIndex); return kTfLiteError; } // Validate all outputs and get TensorInfo std::vector outputs; for (unsigned int i = 0; i < unpackNum; ++i) { const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[i]); if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) { return kTfLiteError; } outputs.push_back(GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); // Determine the shape of the Splitter layer outputs for validation armnn::TensorShape splitOutShape = armnn::TensorShape(static_cast(unpackDimSizes.size()), unpackDimSizes.data()); std::vector splitterOutputs; for (unsigned int outputIndex = 0; outputIndex < outputTensorInfos.size(); ++outputIndex) { splitterOutputs.push_back(armnn::TensorInfo(splitOutShape, outputTensorInfos[outputIndex].get().GetDataType(), outputTensorInfos[outputIndex].get().GetQuantizationScale(), outputTensorInfos[outputIndex].get().GetQuantizationOffset())); } std::vector> splitterOutputTensorInfos(splitterOutputs.begin(), splitterOutputs.end()); armnn::BackendId setBackendSplit; if (!delegateData.m_Network) { // Check if splitter is supported bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("UNPACK", tfLiteContext, IsSplitterSupported, delegateData.m_Backends, isSupported, setBackendSplit, inputTensorInfo, splitterOutputTensorInfos, splitDesc); return isSupported ? kTfLiteOk : kTfLiteError; } // Create Reshape descriptor from the first outputTensorInfo to validate a single Reshape layer // Use this descriptor later when creating every ReshapeLayer as all Reshape Layers should be the same armnn::ReshapeDescriptor reshapeDescriptor; reshapeDescriptor.m_TargetShape = outputTensorInfos[0].get().GetShape(); armnn::BackendId setBackendReshape; if (!delegateData.m_Network) { bool isSupported = false; FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("RESHAPE", tfLiteContext, IsReshapeSupported, delegateData.m_Backends, isSupported, setBackendReshape, splitterOutputTensorInfos[0], outputTensorInfos[0], reshapeDescriptor); return isSupported ? kTfLiteOk : kTfLiteError; }; auto layerName = GetName(armnn::LayerType::Splitter, nodeIndex, "Unpack"); armnn::IConnectableLayer* splitterLayer = delegateData.m_Network->AddSplitterLayer(splitDesc, layerName.c_str()); splitterLayer->SetBackendId(setBackendSplit); ARMNN_ASSERT(splitterLayer != nullptr); for (unsigned int k = 0; k < splitterLayer->GetNumOutputSlots(); ++k) { splitterLayer->GetOutputSlot(k).SetTensorInfo(outputs[k]); } // Connect the input slots auto inputIndex = static_cast(inputTensors[0]); delegateData.m_OutputSlotForNode[inputIndex]->Connect(splitterLayer->GetInputSlot(0)); // Create reshape to remove the unpacked dimension for unpack operator of each output from Splitter. for (unsigned int outputIndex = 0; outputIndex < splitterLayer->GetNumOutputSlots(); ++outputIndex) { auto reshapeLayerName = GetName(armnn::LayerType::Reshape, nodeIndex, "Unpack"); armnn::IConnectableLayer* reshapeLayer = delegateData.m_Network->AddReshapeLayer(reshapeDescriptor, reshapeLayerName.c_str()); reshapeLayer->SetBackendId(setBackendReshape); ARMNN_ASSERT(reshapeLayer != nullptr); splitterLayer->GetOutputSlot(outputIndex).SetTensorInfo(splitterOutputTensorInfos[outputIndex]); splitterLayer->GetOutputSlot(outputIndex).Connect(reshapeLayer->GetInputSlot(0)); armnn::TensorInfo outputTensorInfo = outputTensorInfos[outputIndex]; reshapeLayer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); armnn::IOutputSlot& slot = reshapeLayer->GetOutputSlot(0); delegateData.m_OutputSlotForNode[ static_cast(static_cast(outputTensors[outputIndex]))] = &slot; } return kTfLiteOk; } } // namespace armnnOpaqueDelegatearmnn-23.08/delegate/opaque/src/armnn_delegate.cpp000066400000000000000000001553631446772241200221730ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include "Activation.hpp" #include "ArgMinMax.hpp" #include "BatchMatMul.hpp" #include "BatchSpace.hpp" #include "Comparison.hpp" #include "Convolution.hpp" #include "Control.hpp" #include "ElementwiseBinary.hpp" #include "ElementwiseUnary.hpp" #include "Fill.hpp" #include "FullyConnected.hpp" #include "Gather.hpp" #include "GatherNd.hpp" #include "LogicalBinary.hpp" #include "Lstm.hpp" #include "Normalization.hpp" #include "Pack.hpp" #include "Pad.hpp" #include "Pooling.hpp" #include "Prelu.hpp" #include "Quantization.hpp" #include "Redefine.hpp" #include "Reduce.hpp" #include "Resize.hpp" #include "ReverseV2.hpp" #include "Round.hpp" #include "Shape.hpp" #include "Slice.hpp" #include "StridedSlice.hpp" #include "Softmax.hpp" #include "SpaceDepth.hpp" #include "Split.hpp" #include "Tile.hpp" #include "Transpose.hpp" #include "UnidirectionalSequenceLstm.hpp" #include "Unpack.hpp" #include #include #include #include #include #include #include #include #include #include namespace armnnOpaqueDelegate { static auto* g_delegate_plugin_ArmnnDelegatePlugin_ = new tflite::delegates::DelegatePluginRegistry::Register("armnn_delegate", ArmnnDelegatePlugin::New); ArmnnOpaqueDelegate::ArmnnOpaqueDelegate(armnnDelegate::DelegateOptions options) : m_Options(std::move(options)) { // Configures logging for ARMNN if (m_Options.IsLoggingEnabled()) { armnn::ConfigureLogging(true, true, m_Options.GetLoggingSeverity()); } // Create/Get the static ArmNN Runtime. Note that the m_Runtime will be shared by all armnn_delegate // instances so the RuntimeOptions cannot be altered for different armnn_delegate instances. m_Runtime = GetRuntime(m_Options.GetRuntimeOptions()); std::vector backends; if (m_Runtime) { const armnn::BackendIdSet supportedDevices = m_Runtime->GetDeviceSpec().GetSupportedBackends(); for (auto& backend : m_Options.GetBackends()) { if (std::find(supportedDevices.cbegin(), supportedDevices.cend(), backend) == supportedDevices.cend()) { TFLITE_LOG_PROD(tflite::TFLITE_LOG_INFO, "TfLiteArmnnOpaqueDelegate: Requested unknown backend %s", backend.Get().c_str()); } else { backends.push_back(backend); } } } if (backends.empty()) { // No known backend specified throw armnn::InvalidArgumentException("TfLiteArmnnOpaqueDelegate: No known backend specified."); } m_Options.SetBackends(backends); TFLITE_LOG_PROD_ONCE(tflite::TFLITE_LOG_INFO, "TfLiteArmnnOpaqueDelegate: Created TfLite ArmNN delegate."); } TfLiteStatus DoPrepare(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueDelegate* tfLiteDelegate, void* data) { // We are required to have the void* data parameter in the function signature, but we don't actually use it. armnn::IgnoreUnused(data); TfLiteIntArray* supportedOperators = static_cast<::armnnOpaqueDelegate::ArmnnOpaqueDelegate*> (TfLiteOpaqueDelegateGetData(tfLiteDelegate))->IdentifyOperatorsToDelegate(tfLiteContext); if(supportedOperators == nullptr) { return kTfLiteError; } // ArmNN Opaque Delegate Registration TfLiteRegistrationExternal* kernelRegistration = TfLiteRegistrationExternalCreate(kTfLiteBuiltinDelegate, "armnn_delegate", /*version=*/OPAQUE_DELEGATE_MAJOR_VERSION); if(kernelRegistration == nullptr) { return kTfLiteError; } TfLiteRegistrationExternalSetInit( kernelRegistration, [](TfLiteOpaqueContext* tfLiteContext, const char* buffer, size_t length) -> void* { armnn::IgnoreUnused(length); const TfLiteOpaqueDelegateParams* parameters = reinterpret_cast(buffer); if(parameters == nullptr) { TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to get parameters."); return nullptr; } return static_cast( ArmnnSubgraph::Create(tfLiteContext, parameters, static_cast<::armnnOpaqueDelegate::ArmnnOpaqueDelegate*>( parameters->delegate->opaque_delegate_builder->data))); } ); TfLiteRegistrationExternalSetFree( kernelRegistration, [](TfLiteOpaqueContext* tfLiteContext, void* buffer) -> void { armnn::IgnoreUnused(tfLiteContext); if (buffer != nullptr) { delete static_cast(buffer); } } ); TfLiteRegistrationExternalSetPrepare( kernelRegistration, [](TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode) -> TfLiteStatus { void* userData = TfLiteOpaqueNodeGetUserData(tfLiteNode); if (userData == nullptr) { return kTfLiteError; } return static_cast(userData)->Prepare(tfLiteContext); } ); TfLiteRegistrationExternalSetInvoke( kernelRegistration, [](TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode) -> TfLiteStatus { void* userData = TfLiteOpaqueNodeGetUserData(tfLiteNode); if (userData == nullptr) { return kTfLiteError; } return static_cast(userData)->Invoke(tfLiteContext, tfLiteNode); } ); const TfLiteStatus status = TfLiteOpaqueContextReplaceNodeSubsetsWithDelegateKernels( tfLiteContext, kernelRegistration, supportedOperators, tfLiteDelegate); TfLiteIntArrayFree(supportedOperators); return status; } TfLiteOpaqueDelegate* TfLiteArmnnOpaqueDelegateCreate(const void* settings) { // This method will always create Opaque Delegate with default settings until // we have a DelegateOptions Constructor which can parse the void* settings armnn::IgnoreUnused(settings); auto options = TfLiteArmnnDelegateOptionsDefault(); auto* armnnDelegate = new ::armnnOpaqueDelegate::ArmnnOpaqueDelegate(options); return TfLiteOpaqueDelegateCreate(armnnDelegate->GetDelegateBuilder()); } ::armnnDelegate::DelegateOptions TfLiteArmnnDelegateOptionsDefault() { ::armnnDelegate::DelegateOptions options(armnn::Compute::CpuRef); return options; } void TfLiteArmnnOpaqueDelegateDelete(TfLiteOpaqueDelegate* tfLiteDelegate) { if (tfLiteDelegate != nullptr) { delete static_cast<::armnnOpaqueDelegate::ArmnnOpaqueDelegate*>(TfLiteOpaqueDelegateGetData(tfLiteDelegate)); TfLiteOpaqueDelegateDelete(tfLiteDelegate); } } const std::string ArmnnOpaqueDelegate::GetVersion() { return OPAQUE_DELEGATE_VERSION; } TfLiteIntArray* ArmnnOpaqueDelegate::IdentifyOperatorsToDelegate(TfLiteOpaqueContext* tfLiteContext) { TfLiteIntArray* executionPlan = nullptr; if (TfLiteOpaqueContextGetExecutionPlan(tfLiteContext, &executionPlan) != kTfLiteOk) { TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to get graph execution plan."); return nullptr; } // Delegate data with null network DelegateData delegateData(m_Options.GetBackends()); TfLiteIntArray* nodesToDelegate = TfLiteIntArrayCreate(executionPlan->size); if (nodesToDelegate == nullptr) { TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to create int array from execution plan."); return nullptr; } nodesToDelegate->size = 0; std::set unsupportedOperators; for (int i = 0; i < executionPlan->size; ++i) { const int nodeIndex = executionPlan->data[i]; // If TfLiteOpaqueNodes can be delegated to ArmNN TfLiteOpaqueNode* tfLiteNode = nullptr; TfLiteRegistrationExternal* tfLiteRegistration = nullptr; if (TfLiteOpaqueContextGetNodeAndRegistration( tfLiteContext, nodeIndex, &tfLiteNode, &tfLiteRegistration) != kTfLiteOk) { TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "TfLiteArmnnOpaqueDelegate: Unable to get node and registration for node %d.", nodeIndex); continue; } TfLiteStatus visitStatus; try { visitStatus = ArmnnSubgraph::VisitNode( delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex); } catch(std::exception& ex) { ARMNN_LOG(error) << "ArmNN Failed to visit node with error: " << ex.what(); visitStatus = kTfLiteError; } if (visitStatus != kTfLiteOk) { // node is not supported by ArmNN unsupportedOperators.insert(TfLiteRegistrationExternalGetBuiltInCode(tfLiteRegistration)); continue; } nodesToDelegate->data[nodesToDelegate->size++] = nodeIndex; } for (std::set::iterator it=unsupportedOperators.begin(); it!=unsupportedOperators.end(); ++it) { TF_LITE_OPAQUE_KERNEL_LOG(tfLiteContext, "Operator %s [%d] is not supported by armnn_opaque_delegate.", tflite::EnumNameBuiltinOperator(tflite::BuiltinOperator(*it)), *it); } if (!unsupportedOperators.empty() && m_Options.TfLiteRuntimeFallbackDisabled()) { std::stringstream exMessage; exMessage << "TfLiteArmnnOpaqueDelegate: There are unsupported operators in the model. "; exMessage << "Not falling back to TfLite Runtime as fallback is disabled. "; exMessage << "This should only be disabled under test conditions."; throw armnn::Exception(exMessage.str()); } if (nodesToDelegate->size == 0) { ARMNN_LOG(info) << "No operators in this model are supported by the Arm NN TfLite delegate." << " The model will be executed entirely by TfLite runtime."; } std::sort(&nodesToDelegate->data[0], &nodesToDelegate->data[nodesToDelegate->size]); return nodesToDelegate; } TfLiteStatus ArmnnSubgraph::AddInputLayer(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const TfLiteIntArray* inputs, std::vector& inputBindings) { const size_t numInputs = static_cast(inputs->size); for (unsigned int i = 0; i < numInputs; ++i) { const int32_t tensorId = inputs->data[i]; const TfLiteOpaqueTensor* tensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, tensorId); if(!tensor) { return kTfLiteError; } // Do not create bindings for constant inputs if (TfLiteOpaqueTensorGetAllocationType(tensor) == kTfLiteMmapRo) { continue; } auto bindingId = static_cast((tensorId)); armnn::IConnectableLayer* layer = delegateData.m_Network->AddInputLayer(bindingId); auto tensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tensor); armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); outputSlot.SetTensorInfo(tensorInfo); // Store for creating connections delegateData.m_OutputSlotForNode[static_cast(tensorId)] = &outputSlot; inputBindings.push_back(std::make_pair(bindingId, tensorInfo)); } return kTfLiteOk; } TfLiteStatus ArmnnSubgraph::AddOutputLayer(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, const TfLiteIntArray* outputs, std::vector& outputBindings) { const size_t numOutputs = static_cast(outputs->size); for (unsigned int i = 0; i < numOutputs; ++i) { const int32_t tensorId = outputs->data[i]; const TfLiteOpaqueTensor* tensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, tensorId); if(!IsValid(tensor)) { return kTfLiteError; } auto bindingId = static_cast((tensorId)); armnn::IConnectableLayer* layer = delegateData.m_Network->AddOutputLayer(bindingId); auto tensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tensor); if (delegateData.m_OutputSlotForNode[static_cast(tensorId)] == nullptr) { return kTfLiteError; } delegateData.m_OutputSlotForNode[static_cast(tensorId)]->Connect(layer->GetInputSlot(0)); outputBindings.push_back(std::make_pair(bindingId, tensorInfo)); } return kTfLiteOk; } ArmnnSubgraph* ArmnnSubgraph::Create(TfLiteOpaqueContext* tfLiteContext, const TfLiteOpaqueDelegateParams* parameters, const ArmnnOpaqueDelegate* delegate) { const auto startTime = armnn::GetTimeNow(); ARMNN_LOG(info) << "ArmnnSubgraph creation"; TfLiteIntArray* executionPlan; if (TfLiteOpaqueContextGetExecutionPlan(tfLiteContext, &executionPlan) != kTfLiteOk) { return nullptr; } // Initialize DelegateData holds network and output slots information DelegateData delegateData(delegate->m_Options.GetBackends()); // Build ArmNN Network armnn::NetworkOptions networkOptions = delegate->m_Options.GetOptimizerOptions().GetModelOptions(); armnn::NetworkId networkId; delegateData.m_Network = armnn::INetwork::Create(networkOptions); delegateData.m_OutputSlotForNode = std::vector( TfLiteOpaqueContextGetNumTensors(tfLiteContext), nullptr); std::vector inputBindings; std::vector outputBindings; // Add input layer if (AddInputLayer(delegateData, tfLiteContext, parameters->input_tensors, inputBindings) != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to add Inputs to the network!"); } // Parse TfLite delegate nodes to ArmNN const auto parseStartTime = armnn::GetTimeNow(); for (int i = 0; i < parameters->nodes_to_replace->size; ++i) { const int nodeIndex = parameters->nodes_to_replace->data[i]; TfLiteOpaqueNode* tfLiteNode = nullptr; TfLiteRegistrationExternal* tfLiteRegistration = nullptr; if (TfLiteOpaqueContextGetNodeAndRegistration( tfLiteContext, nodeIndex, &tfLiteNode, &tfLiteRegistration) != kTfLiteOk) { throw armnn::Exception(&"TfLiteArmnnOpaqueDelegate: Unable to get node registration: " [ nodeIndex]); } if (VisitNode(delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex) != kTfLiteOk) { throw armnn::Exception(&"TfLiteArmnnOpaqueDelegate: Unable to parse node: " [ nodeIndex]); } } ARMNN_LOG(info) << "Parse nodes to ArmNN time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(parseStartTime).count() << " ms"; // Add Output layer if (AddOutputLayer(delegateData, tfLiteContext, parameters->output_tensors, outputBindings) != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to add Outputs to the network!"); } // Optimize ArmNN network armnn::IOptimizedNetworkPtr optNet(nullptr, nullptr); try { const auto optimizeStartTime = armnn::GetTimeNow(); optNet = armnn::Optimize(*(delegateData.m_Network.get()), delegate->m_Options.GetBackends(), delegate->m_Runtime->GetDeviceSpec(), delegate->m_Options.GetOptimizerOptions()); ARMNN_LOG(info) << "Optimize ArmnnSubgraph time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(optimizeStartTime).count() << " ms"; } catch (std::exception& ex) { std::stringstream exMessage; exMessage << "TfLiteArmnnOpaqueDelegate: Exception (" << ex.what() << ") caught from optimize."; throw armnn::Exception(exMessage.str()); } if (!optNet) { // Optimize failed throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to optimize the network!"); } // If set, we will serialize the optimized model into a dot file. const std::string serializeToDotFile = delegate->m_Options.GetSerializeToDot(); if (!serializeToDotFile.empty()) { ARMNN_LOG(info) << "Writing graph to dot file: " << serializeToDotFile; fs::path filename = serializeToDotFile; std::fstream file(filename.c_str(), std::ios_base::out); optNet->SerializeToDot(file); } try { const auto loadStartTime = armnn::GetTimeNow(); // Load graph into runtime std::string errorMessage; armnn::Status loadingStatus; armnn::MemorySource inputSource = armnn::MemorySource::Undefined; armnn::MemorySource outputSource = armnn::MemorySource::Undefined; // There's a bit of an assumption here that the delegate will only support Malloc memory source. if (delegate->m_Options.GetOptimizerOptions().GetImportEnabled()) { inputSource = armnn::MemorySource::Malloc; } if (delegate->m_Options.GetOptimizerOptions().GetExportEnabled()) { outputSource = armnn::MemorySource::Malloc; } armnn::INetworkProperties networkProperties(false, inputSource, outputSource, delegate->m_Options.GetInternalProfilingState(), delegate->m_Options.GetInternalProfilingDetail()); loadingStatus = delegate->m_Runtime->LoadNetwork(networkId, std::move(optNet), errorMessage, networkProperties); if (loadingStatus != armnn::Status::Success) { // Network load failed. throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Network could not be loaded: " + errorMessage); } ARMNN_LOG(info) << "Load ArmnnSubgraph time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(loadStartTime).count() << " ms"; } catch (std::exception& ex) { std::stringstream exMessage; exMessage << "TfLiteArmnnOpaqueDelegate: Exception (" << ex.what() << ") caught from LoadNetwork."; throw armnn::Exception(exMessage.str()); } // Register debug callback function if (delegate->m_Options.GetDebugCallbackFunction().has_value()) { delegate->m_Runtime->RegisterDebugCallback(networkId, delegate->m_Options.GetDebugCallbackFunction().value()); } ARMNN_LOG(info) << "Overall ArmnnSubgraph creation time: " << std::setprecision(2) << std::fixed << armnn::GetTimeDuration(startTime).count() << " ms\n"; // Create a new SubGraph with networkId and runtime return new ArmnnSubgraph(networkId, delegate->m_Runtime, inputBindings, outputBindings); } TfLiteStatus ArmnnSubgraph::Prepare(TfLiteOpaqueContext* tfLiteContext) { armnn::IgnoreUnused(tfLiteContext); return kTfLiteOk; } TfLiteStatus ArmnnSubgraph::Invoke(TfLiteOpaqueContext* tfLiteContext, TfLiteOpaqueNode* tfLiteNode) { // Get array of input indices, inputIndexArray is set from the TfLiteOpaqueNodeInputs function // This function turns inputIndexArray into an int array of indices. These indices point to the tensors for // each input slot in the node. const int* inputIndexArray; int numInputs; if(TfLiteOpaqueNodeInputs(tfLiteNode, &inputIndexArray, &numInputs) != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to load subgraph inputs!"); } // Prepare inputs armnn::InputTensors inputTensors; size_t inputIndex = 0; for (int inputIdx = 0; inputIdx < numInputs; inputIdx++) { TfLiteOpaqueTensor* tensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputIndexArray[inputIdx]); if(!IsValid(tensor)) { return kTfLiteError; } // If tensor is not read only if (TfLiteOpaqueTensorGetAllocationType(tensor) != kTfLiteMmapRo) { const armnn::BindingPointInfo& inputBinding = m_InputBindings[inputIndex]; armnn::TensorInfo inputTensorInfo = inputBinding.second; inputTensorInfo.SetConstant(true); const armnn::ConstTensor inputTensor(inputTensorInfo, TfLiteOpaqueTensorData(tensor)); inputTensors.emplace_back(inputIndexArray[inputIdx], inputTensor); ++inputIndex; } } // Get array of output indices, outputIndexArray is set from the TfLiteOpaqueNodeOutputs function // This function turns outputIndexArray into an int array of indices. These indices point to the tensors for // each output slot in the node. const int* outputIndexArray; int numOutputs; if(TfLiteOpaqueNodeOutputs(tfLiteNode, &outputIndexArray, &numOutputs) != kTfLiteOk) { throw armnn::Exception("TfLiteArmnnOpaqueDelegate: Unable to load subgraph outputs!"); } // Assign the tensors from the outputIndexArray to the armnn BindingPointInfo armnn::OutputTensors outputTensors; for (int outputIdx = 0; outputIdx < numOutputs; outputIdx++) { const armnn::BindingPointInfo& outputBinding = m_OutputBindings[outputIdx]; TfLiteOpaqueTensor* tensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputIndexArray[outputIdx]); if(!IsValid(tensor)) { return kTfLiteError; } const armnn::Tensor outputTensor(outputBinding.second, reinterpret_cast(tensor)->data .data); outputTensors.emplace_back(outputIndexArray[outputIdx], outputTensor); } // Run graph auto status = m_Runtime->EnqueueWorkload(m_NetworkId, inputTensors, outputTensors); // The delegate holds its own Arm NN runtime so this is our last chance to print internal profiling data. std::shared_ptr profiler = m_Runtime->GetProfiler(m_NetworkId); if (profiler && profiler->IsProfilingEnabled()) { profiler->Print(std::cout); } return (status == armnn::Status::Success) ? kTfLiteOk : kTfLiteError; } TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, TfLiteOpaqueContext* tfLiteContext, TfLiteRegistrationExternal* tfLiteRegistration, TfLiteOpaqueNode* tfLiteNode, int nodeIndex) { switch (TfLiteRegistrationExternalGetBuiltInCode(tfLiteRegistration)) { case kTfLiteBuiltinAbs: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinAbs, armnn::UnaryOperation::Abs); case kTfLiteBuiltinAdd: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinAdd); case kTfLiteBuiltinArgMax: return VisitArgMinMaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinArgMax); case kTfLiteBuiltinArgMin: return VisitArgMinMaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinArgMin); case kTfLiteBuiltinAveragePool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinAveragePool2d); case kTfLiteBuiltinBatchMatmul: return VisitBatchMatMulOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinBatchMatmul); case kTfLiteBuiltinBatchToSpaceNd: return VisitBatchToSpaceNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinBatchToSpaceNd); case kTfLiteBuiltinCast: return VisitCastOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinCast); case kTfLiteBuiltinCeil: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinCeil, armnn::UnaryOperation::Ceil); case kTfLiteBuiltinConcatenation: return VisitControlOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConcatenation); case kTfLiteBuiltinConv2d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConv2d); case kTfLiteBuiltinConv3d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinConv3d); case kTfLiteBuiltinCustom: { // Custom operators are defined by the name rather than the builtin code. // Parse the custom_name param in the registration to point to the correct visitor function. std::string customOperatorName = TfLiteRegistrationExternalGetCustomName(tfLiteRegistration); if ( customOperatorName == "AveragePool3D" ) { return VisitPooling3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, customOperatorName); } else if (customOperatorName == "MaxPool3D") { return VisitPooling3dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, customOperatorName); } // Invalid or unsupported custom operator return kTfLiteError; } case kTfLiteBuiltinDepthwiseConv2d: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDepthwiseConv2d); case kTfLiteBuiltinDequantize: return VisitDequantizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDequantize); case kTfLiteBuiltinDiv: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDiv); case kTfLiteBuiltinEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinEqual, armnn::ComparisonOperation::Equal); case kTfLiteBuiltinDepthToSpace: return VisitDepthToSpaceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinDepthToSpace); case kTfLiteBuiltinElu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinElu); case kTfLiteBuiltinExp: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinExp, armnn::UnaryOperation::Exp); case kTfLiteBuiltinExpandDims: return VisitExpandDimsOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinExpandDims); case kTfLiteBuiltinFill: return VisitFillOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFill); case kTfLiteBuiltinFloor: return VisitFloorOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFloor); case kTfLiteBuiltinFloorDiv: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFloorDiv); case kTfLiteBuiltinFullyConnected: return VisitFullyConnectedOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinFullyConnected); case kTfLiteBuiltinGather: return VisitGatherOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGather); case kTfLiteBuiltinGatherNd: return VisitGatherNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGatherNd); case kTfLiteBuiltinGreater: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGreater, armnn::ComparisonOperation::Greater); case kTfLiteBuiltinGreaterEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinGreaterEqual, armnn::ComparisonOperation::GreaterOrEqual); case kTfLiteBuiltinHardSwish: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinHardSwish); case kTfLiteBuiltinL2Normalization: return VisitL2NormalizationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinL2Normalization); case kTfLiteBuiltinL2Pool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinL2Pool2d); case kTfLiteBuiltinLeakyRelu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLeakyRelu); case kTfLiteBuiltinLess: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLess, armnn::ComparisonOperation::Less); case kTfLiteBuiltinLessEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLessEqual, armnn::ComparisonOperation::LessOrEqual); case kTfLiteBuiltinLogistic: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogistic); case kTfLiteBuiltinLocalResponseNormalization: return VisitLocalResponseNormalizationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLocalResponseNormalization); case kTfLiteBuiltinLog: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLog, armnn::UnaryOperation::Log); case kTfLiteBuiltinLogicalAnd: return VisitLogicalBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogicalAnd, armnn::LogicalBinaryOperation::LogicalAnd); case kTfLiteBuiltinLogicalNot: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogicalNot, armnn::UnaryOperation::LogicalNot); case kTfLiteBuiltinLogicalOr: return VisitLogicalBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogicalOr, armnn::LogicalBinaryOperation::LogicalOr); case kTfLiteBuiltinLogSoftmax: return VisitSoftmaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLogSoftmax); case kTfLiteBuiltinLstm: return VisitLstmOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinLstm); case kTfLiteBuiltinMaxPool2d: return VisitPooling2dOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMaxPool2d); case kTfLiteBuiltinMaximum: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMaximum); case kTfLiteBuiltinMean: return VisitControlOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMean); case kTfLiteBuiltinMinimum: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMinimum); case kTfLiteBuiltinMirrorPad: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMirrorPad); case kTfLiteBuiltinMul: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinMul); case kTfLiteBuiltinNeg: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinNeg, armnn::UnaryOperation::Neg); case kTfLiteBuiltinNotEqual: return VisitComparisonOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinNotEqual, armnn::ComparisonOperation::NotEqual); case kTfLiteBuiltinPack: return VisitPackOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPack); case kTfLiteBuiltinPad: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPad); case kTfLiteBuiltinPadv2: return VisitPadOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPadv2); case kTfLiteBuiltinPow: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPow); case kTfLiteBuiltinPrelu: return VisitPreluOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinPrelu); case kTfLiteBuiltinQuantize: return VisitQuantizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinQuantize); case kTfLiteBuiltinReduceMax: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceMax); case kTfLiteBuiltinReduceMin: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceMin); case kTfLiteBuiltinReduceProd: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReduceProd); case kTfLiteBuiltinRelu: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRelu); case kTfLiteBuiltinReluN1To1: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReluN1To1); case kTfLiteBuiltinRelu6: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRelu6); case kTfLiteBuiltinReshape: return VisitReshapeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReshape); case kTfLiteBuiltinResizeNearestNeighbor: return VisitResizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinResizeNearestNeighbor); case kTfLiteBuiltinResizeBilinear: return VisitResizeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinResizeBilinear); case kTfLiteBuiltinReverseV2: return VisitReverseV2Operator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinReverseV2); case kTfLiteBuiltinRsqrt: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinRsqrt, armnn::UnaryOperation::Rsqrt); case kTfLiteBuiltinShape: return VisitShapeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinShape); case kTfLiteBuiltinSin: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSin, armnn::UnaryOperation::Sin); case kTfLiteBuiltinSlice: return VisitSliceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSlice); case kTfLiteBuiltinSoftmax: return VisitSoftmaxOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSoftmax); case kTfLiteBuiltinSpaceToBatchNd: return VisitSpaceToBatchNdOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSpaceToBatchNd); case kTfLiteBuiltinSpaceToDepth: return VisitSpaceToDepthOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSpaceToDepth); case kTfLiteBuiltinSplit: return VisitSplitOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSplit); case kTfLiteBuiltinSplitV: return VisitSplitVOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSplitV); case kTfLiteBuiltinSquaredDifference: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSquaredDifference); case kTfLiteBuiltinSub: return VisitElementwiseBinaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSub); case kTfLiteBuiltinSqrt: return VisitElementwiseUnaryOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSqrt, armnn::UnaryOperation::Sqrt); case kTfLiteBuiltinSqueeze: return VisitSqueezeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSqueeze); case kTfLiteBuiltinStridedSlice: return VisitStridedSliceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinStridedSlice); case kTfLiteBuiltinSum: return VisitReduceOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinSum); case kTfLiteBuiltinTanh: return VisitActivationOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTanh); case kTfLiteBuiltinTile: return VisitTileOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTile); case kTfLiteBuiltinTranspose: return VisitTransposeOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTranspose); case kTfLiteBuiltinTransposeConv: return VisitConvolutionOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinTransposeConv); case kTfLiteBuiltinUnidirectionalSequenceLstm: return VisitUnidirectionalSequenceLstmOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinUnidirectionalSequenceLstm); case kTfLiteBuiltinUnpack: return VisitUnpackOperator(delegateData, tfLiteContext, tfLiteNode, nodeIndex, kTfLiteBuiltinUnpack); default: return kTfLiteError; } } } // armnnOpaqueDelegate namespace armnn-23.08/delegate/opaque/src/armnn_external_delegate.cpp000066400000000000000000000023671446772241200240700ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include namespace { TfLiteOpaqueDelegate* ArmNNDelegateCreateFunc(const void* tflite_settings) { auto delegate = armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateCreate(tflite_settings); return delegate; } void ArmNNDelegateDestroyFunc(TfLiteOpaqueDelegate* armnnDelegate) { armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateDelete( armnnDelegate); } int ArmNNDelegateErrnoFunc(TfLiteOpaqueDelegate* sample_stable_delegate) { return 0; } const TfLiteOpaqueDelegatePlugin armnn_delegate_plugin = { ArmNNDelegateCreateFunc, ArmNNDelegateDestroyFunc, ArmNNDelegateErrnoFunc}; const TfLiteStableDelegate armnn_delegate = { /*delegate_abi_version=*/ TFL_STABLE_DELEGATE_ABI_VERSION, /*delegate_name=*/ "armnn_delegate", /*delegate_version=*/ OPAQUE_DELEGATE_VERSION, /*delegate_plugin=*/ &armnn_delegate_plugin }; } // namespace /** * The ArmNN delegate to be loaded dynamically */ extern "C" const TfLiteStableDelegate TFL_TheStableDelegate = armnn_delegate;armnn-23.08/delegate/opaque/src/test/000077500000000000000000000000001446772241200174645ustar00rootroot00000000000000armnn-23.08/delegate/opaque/src/test/ArmnnOpaqueDelegateTest.cpp000066400000000000000000000043661446772241200247220ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #define DOCTEST_CONFIG_IMPLEMENT_WITH_MAIN #include #include #include #include #include namespace armnnOpaqueDelegate { TEST_SUITE("ArmnnOpaqueDelegate") { TEST_CASE ("DelegateOptions_OpaqueDelegateDefault") { // Check default options can be created auto options = armnnOpaqueDelegate::TfLiteArmnnDelegateOptionsDefault(); armnnOpaqueDelegate::ArmnnOpaqueDelegate delegate(options); // Check version returns correctly auto version = delegate.GetVersion(); CHECK_EQ(version, OPAQUE_DELEGATE_VERSION); auto* builder = delegate.GetDelegateBuilder(); CHECK(builder); // Check Opaque delegate created auto opaqueDelegate = armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateCreate(&options); CHECK(opaqueDelegate); // Check Opaque Delegate can be deleted CHECK(opaqueDelegate->opaque_delegate_builder->data); armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateDelete(opaqueDelegate); } TEST_CASE ("DelegatePluginTest") { // Use default settings until options have been enabled. flatbuffers::FlatBufferBuilder flatBufferBuilder; tflite::TFLiteSettingsBuilder tfliteSettingsBuilder(flatBufferBuilder); flatbuffers::Offset tfliteSettings = tfliteSettingsBuilder.Finish(); flatBufferBuilder.Finish(tfliteSettings); const tflite::TFLiteSettings* settings = flatbuffers::GetRoot( flatBufferBuilder.GetBufferPointer()); std::unique_ptr delegatePlugin = tflite::delegates::DelegatePluginRegistry::CreateByName("armnn_delegate", *settings); // Plugin is created correctly using armnn_delegate name. CHECK((delegatePlugin != nullptr)); tflite::delegates::TfLiteDelegatePtr armnnDelegate = delegatePlugin->Create(); // Armnn Opaque Delegate is created correctly. CHECK((armnnDelegate != nullptr)); CHECK((armnnDelegate->opaque_delegate_builder != nullptr)); } } } // namespace armnnDelegate armnn-23.08/delegate/opaque/src/test/DelegateTestInterpreter.cpp000066400000000000000000000055001446772241200247660ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include #include #include namespace delegateTestInterpreter { DelegateTestInterpreter::DelegateTestInterpreter(std::vector& modelBuffer, const std::vector& backends, const std::string& customOp, bool disableFallback) { armnn::IgnoreUnused(backends); armnn::IgnoreUnused(disableFallback); TfLiteModel* tfLiteModel = delegateTestInterpreter::CreateTfLiteModel(modelBuffer); TfLiteInterpreterOptions* options = delegateTestInterpreter::CreateTfLiteInterpreterOptions(); if (!customOp.empty()) { options->mutable_op_resolver = delegateTestInterpreter::GenerateCustomOpResolver(customOp); } // Use default settings until options have been enabled. auto armnnDelegate = armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateCreate(nullptr); TfLiteInterpreterOptionsAddDelegate(options, armnnDelegate); m_TfLiteDelegate = armnnDelegate; m_TfLiteInterpreter = TfLiteInterpreterCreate(tfLiteModel, options); // The options and model can be deleted after the interpreter is created. TfLiteInterpreterOptionsDelete(options); TfLiteModelDelete(tfLiteModel); } DelegateTestInterpreter::DelegateTestInterpreter(std::vector& modelBuffer, const armnnDelegate::DelegateOptions& delegateOptions, const std::string& customOp) { armnn::IgnoreUnused(delegateOptions); TfLiteModel* tfLiteModel = delegateTestInterpreter::CreateTfLiteModel(modelBuffer); TfLiteInterpreterOptions* options = delegateTestInterpreter::CreateTfLiteInterpreterOptions(); if (!customOp.empty()) { options->mutable_op_resolver = delegateTestInterpreter::GenerateCustomOpResolver(customOp); } // Use default settings until options have been enabled. auto armnnDelegate = armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateCreate(nullptr); TfLiteInterpreterOptionsAddDelegate(options, armnnDelegate); m_TfLiteDelegate = armnnDelegate; m_TfLiteInterpreter = TfLiteInterpreterCreate(tfLiteModel, options); // The options and model can be deleted after the interpreter is created. TfLiteInterpreterOptionsDelete(options); TfLiteModelDelete(tfLiteModel); } void DelegateTestInterpreter::Cleanup() { TfLiteInterpreterDelete(m_TfLiteInterpreter); if (m_TfLiteDelegate) { armnnOpaqueDelegate::TfLiteArmnnOpaqueDelegateDelete(static_cast(m_TfLiteDelegate)); } } } // anonymous namespacearmnn-23.08/delegate/python/000077500000000000000000000000001446772241200157455ustar00rootroot00000000000000armnn-23.08/delegate/python/test/000077500000000000000000000000001446772241200167245ustar00rootroot00000000000000armnn-23.08/delegate/python/test/conftest.py000066400000000000000000000016211446772241200211230ustar00rootroot00000000000000# Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT import pytest import os @pytest.fixture(scope="module") def test_data_folder(request): """ This fixture returns path to the folder with the shared test resources """ return str(os.path.join(request.fspath.dirname, "test_data")) def pytest_addoption(parser): """ Adds the program option 'delegate-dir' to pytest """ parser.addoption("--delegate-dir", action="append", help="Directory of the armnn tflite delegate library", required=True) def pytest_generate_tests(metafunc): """ Makes the program option 'delegate-dir' available to all tests as a function fixture """ if "delegate_dir" in metafunc.fixturenames: metafunc.parametrize("delegate_dir", metafunc.config.getoption("delegate_dir"))armnn-23.08/delegate/python/test/pytest.ini000066400000000000000000000005041446772241200207540ustar00rootroot00000000000000# Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT [pytest] addopts = --strict-markers markers = CpuRefTest: marks tests that require the CpuRef backend CpuAccTest: marks tests that require the CpuAcc backend GpuAccTest: marks tests that require the GpuAcc backendarmnn-23.08/delegate/python/test/test_data/000077500000000000000000000000001446772241200206745ustar00rootroot00000000000000armnn-23.08/delegate/python/test/test_data/conv2d.tflite000066400000000000000000000013301446772241200232750ustar00rootroot00000000000000TFL3 8$`L8+ArmnnDelegate: Convolution2d Operator Model    ,0,x  (  f outputbias dfilter  tinput ? @   ?@$@@@@@@?armnn-23.08/delegate/python/test/test_data/conv2d.tflite.license000066400000000000000000000001461446772241200247220ustar00rootroot00000000000000# # Copyright © 2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/python/test/test_data/fallback_model.tflite000066400000000000000000000013001446772241200250160ustar00rootroot00000000000000TFL3 8(\l*)ArmnnDelegate: Add and Div Operator Model   $04LT  P   2  outputf add input_2 tinput_1  0input_0   ?armnn-23.08/delegate/python/test/test_data/fallback_model.tflite.license000066400000000000000000000001461446772241200264460ustar00rootroot00000000000000# # Copyright © 2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/python/test/test_data/fp32_model.tflite000066400000000000000000000012601446772241200240360ustar00rootroot00000000000000TFL3 8(\X*)ArmnnDelegate: Add and Div Operator Model   $04@ T  P   B outputr add input_2 pinput_1  0input_0   ?armnn-23.08/delegate/python/test/test_data/fp32_model.tflite.license000066400000000000000000000001461446772241200254610ustar00rootroot00000000000000# # Copyright © 2021 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/python/test/test_data/mock_model.tflite000066400000000000000000001120701446772241200242170ustar00rootroot00000000000000 TFL3 , TOCO Converted.th\TLD<4( nhnnnnnnnnnnno, o0-oQoR"o\n1.5.0 min_runtime_version 8  (+XPD+ddQp4 max_pooling2d_1/MaxPool0$<@Fq( conv2d/Relu , XD;C?q$ dense/BiasAdd|, IW=<AS*r L ,conv2d/weights_quant/FakeQuantWithMinMaxVars0$sC:|>|M Q.WtկݮlD3lw:w9K3ҼqFAVC͆ث!wbm nymil\J6"ղ䆲 +uz)<$AKo[4_= Z<2~vdvÔYL~XglHO_lV#Acѫ#Uķ,Vc?gi!W>ь7bf'hc'hR<! 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$  ?(  vh$RH,  0   0    ,H armnn-23.08/delegate/python/test/test_data/mock_model.tflite.license000066400000000000000000000001461446772241200256400ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/delegate/python/test/test_external_delegate.py000066400000000000000000000213151446772241200240130ustar00rootroot00000000000000# Copyright © 2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT import numpy as np import pytest import tflite_runtime.interpreter as tflite import os from utils import run_mock_model, run_inference, compare_outputs def test_external_delegate_unknown_options(delegate_dir): print(delegate_dir) with pytest.raises(ValueError): tflite.load_delegate( delegate_dir, options={"wrong": "wrong"}) def test_external_delegate_options_multiple_backends(delegate_dir): tflite.load_delegate( delegate_dir, options={"backends": "GpuAcc,CpuAcc,CpuRef,Unknown"}) @pytest.mark.GpuAccTest def test_external_delegate_options_gpu_tuning(delegate_dir, test_data_folder, tmp_path): tuning_file = os.path.join(str(tmp_path), "test_gpu.tuning") # cleanup previous test run if necessary if os.path.exists(tuning_file): os.remove(tuning_file) # with tuning level 2 a tuning file should be created armnn_delegate = tflite.load_delegate( delegate_dir, options={ "backends": "GpuAcc", "gpu-tuning-level": "2", "gpu-tuning-file": tuning_file, "logging-severity": "info"}) run_mock_model(armnn_delegate, test_data_folder) # destroy delegate, otherwise tuning file won't be written to file armnn_delegate.__del__() assert (os.path.exists(tuning_file)) # if no tuning level is provided it defaults to 0 which means it will use the tuning parameters from a tuning # file if one is provided armnn_delegate2 = tflite.load_delegate( delegate_dir, options={ "backends": "GpuAcc", "gpu-tuning-file": tuning_file, "logging-severity": "info"}) run_mock_model(armnn_delegate2, test_data_folder) # cleanup os.remove(tuning_file) @pytest.mark.GpuAccTest def test_external_delegate_options_gpu_cached_network(delegate_dir, test_data_folder, tmp_path): binary_file = os.path.join(str(tmp_path), "test_binary.bin") # cleanup previous test run if necessary if os.path.exists(binary_file): os.remove(binary_file) # Create blank binary file to write to. open(binary_file, "a").close() assert (os.path.exists(binary_file)) assert (os.stat(binary_file).st_size == 0) # Run inference to save cached network. armnn_delegate = tflite.load_delegate( delegate_dir, options={ "backends": "GpuAcc", "save-cached-network": "1", "cached-network-filepath": binary_file, "logging-severity": "info"}) run_mock_model(armnn_delegate, test_data_folder) # destroy delegate and check if file has been saved. armnn_delegate.__del__() assert (os.stat(binary_file).st_size != 0) # Create second delegate to load in binary file created. armnn_delegate2 = tflite.load_delegate( delegate_dir, options={ "backends": "GpuAcc", "cached-network-filepath": binary_file, "logging-severity": "info"}) run_mock_model(armnn_delegate2, test_data_folder) # cleanup os.remove(binary_file) @pytest.mark.GpuAccTest def test_external_delegate_gpu_fastmath(delegate_dir, test_data_folder): # create armnn delegate with enable-fast-math # fast-math is only enabled on Conv2d layer, so use conv2d model. armnn_delegate = tflite.load_delegate(delegate_dir, options = {"backends": "GpuAcc", "enable-fast-math": "1", "logging-severity": "info"}) model_file_name = "conv2d.tflite" inputShape = [ 1, 5, 5, 1 ] outputShape = [ 1, 3, 3, 1 ] inputValues = [ 1, 5, 2, 3, 5, 8, 7, 3, 6, 3, 3, 3, 9, 1, 9, 4, 1, 8, 1, 3, 6, 8, 1, 9, 2 ] expectedResult = [ 28, 38, 29, 96, 104, 53, 31, 55, 24 ] input = np.array(inputValues, dtype=np.float32).reshape(inputShape) expected_output = np.array(expectedResult, dtype=np.float32).reshape(outputShape) # run the inference armnn_outputs = run_inference(test_data_folder, model_file_name, [input], [armnn_delegate]) # check results compare_outputs(armnn_outputs, [expected_output]) @pytest.mark.CpuAccTest def test_external_delegate_cpu_options(delegate_dir, test_data_folder): # create armnn delegate with enable-fast-math and number-of-threads options # fast-math is only enabled on Conv2d layer, so use conv2d model. armnn_delegate = tflite.load_delegate(delegate_dir, options = {"backends": "CpuAcc", "enable-fast-math": "1", "number-of-threads": "4", "logging-severity": "info"}) model_file_name = "conv2d.tflite" inputShape = [ 1, 5, 5, 1 ] outputShape = [ 1, 3, 3, 1 ] inputValues = [ 1, 5, 2, 3, 5, 8, 7, 3, 6, 3, 3, 3, 9, 1, 9, 4, 1, 8, 1, 3, 6, 8, 1, 9, 2 ] expectedResult = [ 28, 38, 29, 96, 104, 53, 31, 55, 24 ] input = np.array(inputValues, dtype=np.float32).reshape(inputShape) expected_output = np.array(expectedResult, dtype=np.float32).reshape(outputShape) # run the inference armnn_outputs = run_inference(test_data_folder, model_file_name, [input], [armnn_delegate]) # check results compare_outputs(armnn_outputs, [expected_output]) def test_external_delegate_options_wrong_logging_level(delegate_dir): with pytest.raises(ValueError): tflite.load_delegate( delegate_dir, options={"logging-severity": "wrong"}) def test_external_delegate_options_debug(capfd, delegate_dir, test_data_folder): # create armnn delegate with debug option armnn_delegate = tflite.load_delegate(delegate_dir, options = {"backends": "CpuRef", "debug-data": "1"}) model_file_name = "fp32_model.tflite" tensor_shape = [1, 2, 2, 1] input0 = np.array([1, 2, 3, 4], dtype=np.float32).reshape(tensor_shape) input1 = np.array([2, 2, 3, 4], dtype=np.float32).reshape(tensor_shape) inputs = [input0, input0, input1] expected_output = np.array([1, 2, 2, 2], dtype=np.float32).reshape(tensor_shape) # run the inference armnn_outputs = run_inference(test_data_folder, model_file_name, inputs, [armnn_delegate]) # check results compare_outputs(armnn_outputs, [expected_output]) captured = capfd.readouterr() assert "layerGuid" in captured.out def test_external_delegate_options_fp32_to_fp16(capfd, delegate_dir, test_data_folder): # create armnn delegate with reduce-fp32-to-fp16 option armnn_delegate = tflite.load_delegate(delegate_dir, options = {"backends": "CpuRef", "debug-data": "1", "reduce-fp32-to-fp16": "1"}) model_file_name = "fp32_model.tflite" tensor_shape = [1, 2, 2, 1] input0 = np.array([1, 2, 3, 4], dtype=np.float32).reshape(tensor_shape) input1 = np.array([2, 2, 3, 4], dtype=np.float32).reshape(tensor_shape) inputs = [input0, input0, input1] expected_output = np.array([1, 2, 2, 2], dtype=np.float32).reshape(tensor_shape) # run the inference armnn_outputs = run_inference(test_data_folder, model_file_name, inputs, [armnn_delegate]) # check results compare_outputs(armnn_outputs, [expected_output]) captured = capfd.readouterr() assert "convert_fp32_to_fp16" in captured.out assert "convert_fp16_to_fp32" in captured.out def test_external_delegate_options_memory_import(delegate_dir, test_data_folder): # create armnn delegate with memory-import option armnn_delegate = tflite.load_delegate(delegate_dir, options = {"backends": "CpuAcc,CpuRef", "memory-import": "1"}) model_file_name = "fallback_model.tflite" tensor_shape = [1, 2, 2, 1] input0 = np.array([1, 2, 3, 4], dtype=np.uint8).reshape(tensor_shape) input1 = np.array([2, 2, 3, 4], dtype=np.uint8).reshape(tensor_shape) inputs = [input0, input0, input1] expected_output = np.array([1, 2, 2, 2], dtype=np.uint8).reshape(tensor_shape) # run the inference armnn_outputs = run_inference(test_data_folder, model_file_name, inputs, [armnn_delegate]) # check results compare_outputs(armnn_outputs, [expected_output])armnn-23.08/delegate/python/test/utils.py000066400000000000000000000040731446772241200204420ustar00rootroot00000000000000# Copyright © 2020 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT import tflite_runtime.interpreter as tflite import numpy as np import os def run_mock_model(delegate, test_data_folder): model_path = os.path.join(test_data_folder, 'mock_model.tflite') interpreter = tflite.Interpreter(model_path=model_path, experimental_delegates=[delegate]) interpreter.allocate_tensors() # Get input and output tensors. input_details = interpreter.get_input_details() output_details = interpreter.get_output_details() # Test model on random input data. input_shape = input_details[0]['shape'] input_data = np.array(np.random.random_sample(input_shape), dtype=np.uint8) interpreter.set_tensor(input_details[0]['index'], input_data) interpreter.invoke() def run_inference(test_data_folder, model_filename, inputs, delegates=None): model_path = os.path.join(test_data_folder, model_filename) interpreter = tflite.Interpreter(model_path=model_path, experimental_delegates=delegates) interpreter.allocate_tensors() # Get input and output tensors. input_details = interpreter.get_input_details() output_details = interpreter.get_output_details() # Set inputs to tensors. for i in range(len(inputs)): interpreter.set_tensor(input_details[i]['index'], inputs[i]) interpreter.invoke() results = [] for output in output_details: results.append(interpreter.get_tensor(output['index'])) return results def compare_outputs(outputs, expected_outputs): assert len(outputs) == len(expected_outputs), 'Incorrect number of outputs' for i in range(len(expected_outputs)): assert outputs[i].shape == expected_outputs[i].shape, 'Incorrect output shape on output#{}'.format(i) assert outputs[i].dtype == expected_outputs[i].dtype, 'Incorrect output data type on output#{}'.format(i) assert outputs[i].all() == expected_outputs[i].all(), 'Incorrect output value on output#{}'.format(i)armnn-23.08/delegate/test/000077500000000000000000000000001446772241200154035ustar00rootroot00000000000000armnn-23.08/delegate/test/ActivationTest.cpp000066400000000000000000000221421446772241200210510ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ActivationTestHelper.hpp" #include #include #include #include #include namespace armnnDelegate { void ActivationReLuTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; // Calculate output values for input. auto f = [](float value) { return std::fmax(0.0f, value); }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_RELU, backends, inputData, outputExpectedData); } void ActivationBoundedReluTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; const float a = 6.0f; const float b = 0.0f; // Calculate output values for input. auto f = [a, b](float value) { return std::min(a, std::max(b, value)); }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_RELU6, backends, inputData, outputExpectedData); } void ActivationSigmoidTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; // Calculate output values for input. auto f = [](float value) { return 1.0f / (1.0f + std::exp(-value)); }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_LOGISTIC, backends, inputData, outputExpectedData); } void ActivationTanHTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; // Calculate output values for input. auto f = [](float value) { return tanhf(value); }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_TANH, backends, inputData, outputExpectedData); } void ActivationEluTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; // Calculate output values for input. auto f = [](float value) { if (value < 0) { // alpha * (exp(x) - 1) return 1 * (std::exp(value) - 1); } return value; }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_ELU, backends, inputData, outputExpectedData); } void ActivationHardSwishTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; // Calculate output values for input. auto f = [](float x) { // Break down the calculation to help with verification. // hard_swish(x) = x * relu6(x+3) / 6 // relu6(x) = min(max(x,0),6) float reLu6_step1 = std::max((x + 3),0.0f); float reLu6Complete = std::min(reLu6_step1, 6.0f); float hardSwish_step1 = x * reLu6Complete; float result = hardSwish_step1 / 6; return result; }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_HARD_SWISH, backends, inputData, outputExpectedData); } void ActivationLeakyReLuTest(std::vector& backends) { std::vector inputData = { -0.1f, -0.2f, -0.3f, -0.4f, 0.1f, 0.2f, 0.3f, 0.4f, -1.0f, -2.0f, -3.0f, -4.0f, 1.0f, 2.0f, 3.0f, 4.0f }; float alpha = 0.3f; // Calculate output values for input. auto f = [alpha](float value) { return value > 0 ? value : value * alpha; }; std::vector outputExpectedData(inputData.size()); std::transform(inputData.begin(), inputData.end(), outputExpectedData.begin(), f); ActivationTest(tflite::BuiltinOperator_LEAKY_RELU, backends, inputData, outputExpectedData, alpha); } TEST_SUITE("Activation_CpuRefTests") { TEST_CASE ("Activation_ReLu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationReLuTest(backends); } TEST_CASE ("Activation_Bounded_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationBoundedReluTest(backends); } TEST_CASE ("Activation_Sigmoid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationSigmoidTest(backends); } TEST_CASE ("Activation_TanH_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationTanHTest(backends); } TEST_CASE ("Activation_Elu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationEluTest(backends); } TEST_CASE ("Activation_HardSwish_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationHardSwishTest(backends); } TEST_CASE ("Activation_LeakyRelu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ActivationLeakyReLuTest(backends); } } TEST_SUITE("Activation_CpuAccTests") { TEST_CASE ("Activation_ReLu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationReLuTest(backends); } TEST_CASE ("Activation_Bounded_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationBoundedReluTest(backends); } TEST_CASE ("Activation_Sigmoid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationSigmoidTest(backends); } TEST_CASE ("Activation_TanH_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationTanHTest(backends); } TEST_CASE ("Activation_Elu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationEluTest(backends); } TEST_CASE ("Activation_HardSwish_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationHardSwishTest(backends); } TEST_CASE ("Activation_LeakyRelu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ActivationLeakyReLuTest(backends); } } TEST_SUITE("Activation_GpuAccTests") { TEST_CASE ("Activation_ReLu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationReLuTest(backends); } TEST_CASE ("Activation_Bounded_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationBoundedReluTest(backends); } TEST_CASE ("Activation_Sigmoid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationSigmoidTest(backends); } TEST_CASE ("Activation_TanH_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationTanHTest(backends); } TEST_CASE ("Activation_Elu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationEluTest(backends); } TEST_CASE ("Activation_HardSwish_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationHardSwishTest(backends); } TEST_CASE ("Activation_LeakyRelu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ActivationLeakyReLuTest(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/ActivationTestHelper.hpp000066400000000000000000000133071446772241200222210ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateActivationTfLiteModel(tflite::BuiltinOperator activationOperatorCode, tflite::TensorType tensorType, const std::vector & tensorShape, float alpha = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 1> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType); // create operator const std::vector operatorInputs{0}; const std::vector operatorOutputs{1}; // builtin options tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOption = 0; if (activationOperatorCode == tflite::BuiltinOperator_LEAKY_RELU) { operatorBuiltinOptionsType = tflite::BuiltinOptions_LeakyReluOptions; operatorBuiltinOption = CreateLeakyReluOptions(flatBufferBuilder, alpha).Union(); } flatbuffers::Offset unaryOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOption); const std::vector subgraphInputs{0}; const std::vector subgraphOutputs{1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&unaryOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Activation Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, activationOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void ActivationTest(tflite::BuiltinOperator activationOperatorCode, std::vector& backends, std::vector& inputValues, std::vector& expectedOutputValues, float alpha = 0) { using namespace delegateTestInterpreter; std::vector inputShape { { 4, 1, 4} }; std::vector modelBuffer = CreateActivationTfLiteModel(activationOperatorCode, ::tflite::TensorType_FLOAT32, inputShape, alpha); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, inputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ArgMinMaxTest.cpp000066400000000000000000000127561446772241200206050ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ArgMinMaxTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void ArgMaxFP32Test(std::vector& backends, int axisValue) { // Set input data std::vector inputShape { 1, 3, 2, 4 }; std::vector outputShape { 1, 3, 4 }; std::vector axisShape { 1 }; std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 10.0f, 20.0f, 30.0f, 40.0f, 50.0f, 60.0f, 70.0f, 80.0f, 100.0f, 200.0f, 300.0f, 400.0f, 500.0f, 600.0f, 700.0f, 800.0f }; std::vector expectedOutputValues = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ArgMinMaxTest(tflite::BuiltinOperator_ARG_MAX, ::tflite::TensorType_FLOAT32, backends, inputShape, axisShape, outputShape, inputValues, expectedOutputValues, axisValue, ::tflite::TensorType_INT32); } void ArgMinFP32Test(std::vector& backends, int axisValue) { // Set input data std::vector inputShape { 1, 3, 2, 4 }; std::vector outputShape { 1, 3, 2 }; std::vector axisShape { 1 }; std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 10.0f, 20.0f, 30.0f, 40.0f, 50.0f, 60.0f, 70.0f, 80.0f, 100.0f, 200.0f, 300.0f, 400.0f, 500.0f, 600.0f, 700.0f, 800.0f }; std::vector expectedOutputValues = { 0, 0, 0, 0, 0, 0 }; ArgMinMaxTest(tflite::BuiltinOperator_ARG_MIN, ::tflite::TensorType_FLOAT32, backends, inputShape, axisShape, outputShape, inputValues, expectedOutputValues, axisValue, ::tflite::TensorType_INT32); } void ArgMaxUint8Test(std::vector& backends, int axisValue) { // Set input data std::vector inputShape { 1, 1, 1, 5 }; std::vector outputShape { 1, 1, 1 }; std::vector axisShape { 1 }; std::vector inputValues = { 5, 2, 8, 10, 9 }; std::vector expectedOutputValues = { 3 }; ArgMinMaxTest(tflite::BuiltinOperator_ARG_MAX, ::tflite::TensorType_UINT8, backends, inputShape, axisShape, outputShape, inputValues, expectedOutputValues, axisValue, ::tflite::TensorType_INT32); } TEST_SUITE("ArgMinMax_CpuRefTests") { TEST_CASE ("ArgMaxFP32Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ArgMaxFP32Test(backends, 2); } TEST_CASE ("ArgMinFP32Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ArgMinFP32Test(backends, 3); } TEST_CASE ("ArgMaxUint8Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ArgMaxUint8Test(backends, -1); } } // TEST_SUITE("ArgMinMax_CpuRefTests") TEST_SUITE("ArgMinMax_CpuAccTests") { TEST_CASE ("ArgMaxFP32Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ArgMaxFP32Test(backends, 2); } TEST_CASE ("ArgMinFP32Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ArgMinFP32Test(backends, 3); } TEST_CASE ("ArgMaxUint8Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ArgMaxUint8Test(backends, -1); } } // TEST_SUITE("ArgMinMax_CpuAccTests") TEST_SUITE("ArgMinMax_GpuAccTests") { TEST_CASE ("ArgMaxFP32Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ArgMaxFP32Test(backends, 2); } TEST_CASE ("ArgMinFP32Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ArgMinFP32Test(backends, 3); } TEST_CASE ("ArgMaxUint8Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ArgMaxUint8Test(backends, -1); } } // TEST_SUITE("ArgMinMax_GpuAccTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/ArgMinMaxTestHelper.hpp000066400000000000000000000215261446772241200217450ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreateArgMinMaxTfLiteModel(tflite::BuiltinOperator argMinMaxOperatorCode, tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& axisTensorShape, const std::vector& outputTensorShape, const std::vector axisValue, tflite::TensorType outputType, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); auto axisTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(axisTensorShape.data(), axisTensorShape.size()), tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("axis")); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), outputType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); std::vector> tensors = { inputTensor, axisTensor, outputTensor }; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(axisValue.data()), sizeof(OutputT)))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::vector operatorInputs = {{ 0, 1 }}; std::vector subgraphInputs = {{ 0, 1 }}; tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_ArgMaxOptions; flatbuffers::Offset operatorBuiltinOptions = CreateArgMaxOptions(flatBufferBuilder, outputType).Union(); if (argMinMaxOperatorCode == tflite::BuiltinOperator_ARG_MIN) { operatorBuiltinOptionsType = BuiltinOptions_ArgMinOptions; operatorBuiltinOptions = CreateArgMinOptions(flatBufferBuilder, outputType).Union(); } // create operator const std::vector operatorOutputs{ 2 }; flatbuffers::Offset argMinMaxOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&argMinMaxOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: ArgMinMax Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, argMinMaxOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ArgMinMaxTest(tflite::BuiltinOperator argMinMaxOperatorCode, tflite::TensorType tensorType, const std::vector& backends, const std::vector& inputShape, const std::vector& axisShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, OutputT axisValue, tflite::TensorType outputType, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateArgMinMaxTfLiteModel(argMinMaxOperatorCode, tensorType, inputShape, axisShape, outputShape, {axisValue}, outputType, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/BatchMatMulTest.cpp000066400000000000000000000702641446772241200211210ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "BatchMatMulTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void BatchMatMul2DFp32SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2, 2 }; std::vector RHSInputShape { 2, 2 }; std::vector outputShape { 2, 2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul2DInt8SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2, 2 }; std::vector RHSInputShape { 2, 2 }; std::vector outputShape { 2, 2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DFp32SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,2,2 }; std::vector RHSInputShape { 1,2,2 }; std::vector outputShape { 1,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DInt8SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,2,2 }; std::vector RHSInputShape { 1,2,2 }; std::vector outputShape { 1,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul4DFp32SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,1,2,2 }; std::vector RHSInputShape { 1,1,2,2 }; std::vector outputShape { 1,1,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul4DInt8SimpleTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,1,2,2}; std::vector RHSInputShape { 1,1,2,2 }; std::vector outputShape { 1,1,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4 }; std::vector RHSInputValues = { 5, 6, 7, 8 }; std::vector expectedOutputValues = { 19, 22, 43, 50 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DFp32BatchTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 5, 6, 7, 8, 13, 14, 15, 16 }; std::vector expectedOutputValues = { 19, 22, 43, 50, 267, 286, 323, 346 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DInt8BatchTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 5, 6, 7, 8, 1, 2, 3, 4 }; std::vector expectedOutputValues = { 19, 22, 43, 50, 39, 58, 47, 70 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DFp32BroadcastTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 13, 14, 15, 16 }; std::vector expectedOutputValues = { 43, 46, 99, 106, 267, 286, 323, 346 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3DInt8BroadcastTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 7, 10, 15, 22, 39, 58, 47, 70 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3D2DFp32BroadcastTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 13, 14, 15, 16 }; std::vector expectedOutputValues = { 43, 46, 99, 106, 267, 286, 323, 346 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul3D2DInt8BroadcastTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,2,2 }; std::vector RHSInputShape { 2,2 }; std::vector outputShape { 2,2,2 }; std::vector LHSInputValues = { 1, 2, 3, 4, 9, 10, 11, 12 }; std::vector RHSInputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 7, 10, 15, 22, 39, 58, 47, 70 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul2DFp32TinyTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,1 }; std::vector RHSInputShape { 1,1 }; std::vector outputShape { 1,1 }; std::vector LHSInputValues = { 3 }; std::vector RHSInputValues = { 5 }; std::vector expectedOutputValues = { 15 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul2DInt8TinyTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 1,1 }; std::vector RHSInputShape { 1,1 }; std::vector outputShape { 1,1 }; std::vector LHSInputValues = { 3 }; std::vector RHSInputValues = { 5 }; std::vector expectedOutputValues = { 15 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMulNonSquareFp32Test(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,5,3 }; std::vector RHSInputShape { 2,3,4 }; std::vector outputShape { 2,5,4 }; std::vector LHSInputValues = { 8, 8, 4, 6, 1, 3, 8, 8, 3, 8, 9, 8, 5, 4, 4, 1, 8, 5, 7, 1, 1, 8, 7, 9, 3, 2, 7, 8, 5, 3 }; std::vector RHSInputValues = { 6, 2, 3, 2, 6, 2, 2, 8, 3, 7, 8, 1, 7, 2, 9, 5, 2, 3, 1, 3, 2, 7, 7, 5 }; std::vector expectedOutputValues = { 108, 60, 72, 84, 51, 35, 44, 23, 105, 53, 64, 83, 126, 90, 106, 96, 66, 46, 55, 46, 33, 61, 52, 54, 53, 24, 71, 43, 88, 100, 142, 106, 39, 61, 78, 56, 72, 52, 98, 70 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMulNonSquareInt8Test(std::vector& backends) { // Set input data std::vector LHSInputShape { 2,5,3 }; std::vector RHSInputShape { 2,3,4 }; std::vector outputShape { 2,5,4 }; std::vector LHSInputValues = { 8, 8, 4, 6, 1, 3, 8, 8, 3, 8, 9, 8, 5, 4, 4, 1, 8, 5, 7, 1, 1, 8, 7, 9, 3, 2, 7, 8, 5, 3 }; std::vector RHSInputValues = { 6, 2, 3, 2, 6, 2, 2, 8, 3, 7, 8, 1, 7, 2, 3, 5, 2, 3, 1, 3, 2, 7, 7, 5 }; std::vector expectedOutputValues = { 108, 60, 72, 84, 51, 35, 44, 23, 105, 53, 64, 83, 126, 90, 106, 96, 66, 46, 55, 46, 33, 61, 46, 54, 53, 24, 29, 43, 88, 100, 94, 106, 39, 61, 60, 56, 72, 52, 50, 70 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, false, false); } void BatchMatMul2DFp32SimpleAdjointTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 3,3 }; std::vector RHSInputShape { 3,3 }; std::vector outputShape { 3,3 }; std::vector LHSInputValues = { 3, 1, 1, 1, 3, -1, 2, 4, 1 }; std::vector RHSInputValues = { 1, 0, 0, 0, 1, 0, 0, 0, 1 }; std::vector expectedOutputValues = { 3, 1, 2, 1, 3, 4, 1, -1, 1 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_FLOAT32, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, true, false); } void BatchMatMul2DInt8SimpleAdjointTest(std::vector& backends) { // Set input data std::vector LHSInputShape { 3,3 }; std::vector RHSInputShape { 3,3 }; std::vector outputShape { 3,3 }; std::vector LHSInputValues = { 3, 1, 1, 1, 3, -1, 2, 4, 1 }; std::vector RHSInputValues = { 1, 0, 0, 0, 1, 0, 0, 0, 1 }; std::vector expectedOutputValues = { 3, 1, 2, 1, 3, 4, 1, -1, 1 }; BatchMatMulTest(tflite::BuiltinOperator_BATCH_MATMUL, ::tflite::TensorType_INT8, backends, LHSInputShape, RHSInputShape, outputShape, LHSInputValues, RHSInputValues, expectedOutputValues, true, false); } TEST_SUITE("BATCH_MATMUL_CpuRefTests") { TEST_CASE("BATCH_MATMUL_Fp32_CpuRefTests") { std::vector backends = {armnn::Compute::CpuRef}; BatchMatMul2DFp32SimpleTest (backends); BatchMatMul3DFp32SimpleTest (backends); BatchMatMul4DFp32SimpleTest (backends); BatchMatMul3DFp32BatchTest (backends); BatchMatMul3DFp32BroadcastTest (backends); BatchMatMul3D2DFp32BroadcastTest (backends); BatchMatMul2DFp32TinyTest (backends); BatchMatMulNonSquareFp32Test (backends); BatchMatMul2DFp32SimpleAdjointTest(backends); } TEST_CASE("BATCH_MATMUL_Int8_CpuRefTests") { std::vector backends = {armnn::Compute::CpuRef}; BatchMatMul2DInt8SimpleTest (backends); BatchMatMul3DInt8SimpleTest (backends); BatchMatMul4DInt8SimpleTest (backends); BatchMatMul3DInt8BatchTest (backends); BatchMatMul3DInt8BroadcastTest (backends); BatchMatMul3D2DInt8BroadcastTest (backends); BatchMatMul2DInt8TinyTest (backends); BatchMatMulNonSquareInt8Test (backends); BatchMatMul2DInt8SimpleAdjointTest(backends); } } TEST_SUITE("BATCH_MATMUL_CpuAccTests") { TEST_CASE("BATCH_MATMUL_Fp32_CpuAccTests") { std::vector backends = {armnn::Compute::CpuAcc}; BatchMatMul2DFp32SimpleTest (backends); BatchMatMul3DFp32SimpleTest (backends); BatchMatMul4DFp32SimpleTest (backends); BatchMatMul3DFp32BatchTest (backends); BatchMatMul2DFp32TinyTest (backends); BatchMatMulNonSquareFp32Test (backends); BatchMatMul2DFp32SimpleAdjointTest(backends); } TEST_CASE("BATCH_MATMUL_Int8_CpuAccTests") { std::vector backends = {armnn::Compute::CpuAcc}; BatchMatMul2DInt8SimpleTest (backends); BatchMatMul3DInt8SimpleTest (backends); BatchMatMul4DInt8SimpleTest (backends); BatchMatMul3DInt8BatchTest (backends); BatchMatMul2DInt8TinyTest (backends); BatchMatMulNonSquareInt8Test (backends); BatchMatMul2DInt8SimpleAdjointTest(backends); } } TEST_SUITE("BATCH_MATMUL_GpuAccTests") { TEST_CASE("BATCH_MATMUL_Fp32_GpuAccTests") { std::vector backends = {armnn::Compute::GpuAcc}; BatchMatMul2DFp32SimpleTest (backends); BatchMatMul3DFp32SimpleTest (backends); BatchMatMul4DFp32SimpleTest (backends); BatchMatMul3DFp32BatchTest (backends); BatchMatMul2DFp32TinyTest (backends); BatchMatMulNonSquareFp32Test (backends); BatchMatMul2DFp32SimpleAdjointTest(backends); } TEST_CASE("BATCH_MATMUL_Int8_GpuAccTests") { std::vector backends = {armnn::Compute::GpuAcc}; BatchMatMul2DInt8SimpleTest (backends); BatchMatMul3DInt8SimpleTest (backends); BatchMatMul3DInt8BatchTest (backends); BatchMatMul2DInt8TinyTest (backends); BatchMatMulNonSquareInt8Test (backends); BatchMatMul2DInt8SimpleAdjointTest(backends); } } } armnn-23.08/delegate/test/BatchMatMulTestHelper.hpp000066400000000000000000000204101446772241200222520ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateBatchMatMulTfLiteModel( tflite::BuiltinOperator bmmOperatorCode, tflite::TensorType tensorType, const std::vector & LHSInputTensorShape, const std::vector & RHSInputTensorShape, const std::vector & outputTensorShape, bool adjX = false, bool adjY = false, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(LHSInputTensorShape.data(), LHSInputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("LHSInput"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(RHSInputTensorShape.data(), RHSInputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("RHSInput"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_BatchMatMulOptions; flatbuffers::Offset operatorBuiltinOptions = CreateBatchMatMulOptions(flatBufferBuilder, adjX, adjY).Union(); const std::vector operatorInputs{{0, 1}}; const std::vector operatorOutputs{2}; flatbuffers::Offset bmmOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{{0, 1}}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&bmmOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: BatchMatMul Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, bmmOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void BatchMatMulTest(tflite::BuiltinOperator bmmOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& LHSInputShape, std::vector& RHSInputShape, std::vector& outputShape, std::vector& LHSInputValues, std::vector& RHSInputValues, std::vector& expectedOutputValues, bool adjX = false, bool adjY = false, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateBatchMatMulTfLiteModel(bmmOperatorCode, tensorType, LHSInputShape, RHSInputShape, outputShape, adjX, adjY, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(LHSInputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(RHSInputValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(LHSInputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(RHSInputValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/BatchSpaceTest.cpp000066400000000000000000000222441446772241200207500ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "BatchSpaceTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // BatchToSpaceND Operator void BatchToSpaceNDFp32Test(std::vector& backends) { std::vector inputShape { 4, 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector expectedOutputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector blockShape({2, 2}); std::vector> crops = {{0, 0}, {0, 0}}; BatchSpaceTest(tflite::BuiltinOperator_BATCH_TO_SPACE_ND, ::tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, blockShape, crops, expectedOutputValues); } void BatchToSpaceNDFp32BatchOneTest(std::vector& backends) { std::vector inputShape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector expectedOutputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector blockShape({1, 1}); std::vector> crops = {{0, 0}, {0, 0}}; BatchSpaceTest(tflite::BuiltinOperator_BATCH_TO_SPACE_ND, ::tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, blockShape, crops, expectedOutputValues); } void BatchToSpaceNDUint8Test(std::vector& backends) { std::vector inputShape { 4, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector inputValues { 1, 2, 3, 4, 5, 6, 7 }; std::vector expectedOutputValues { 1, 2, 3, 4, 5, 6, 7 }; std::vector blockShape({2, 2}); std::vector> crops = {{0, 0}, {0, 0}}; BatchSpaceTest(tflite::BuiltinOperator_BATCH_TO_SPACE_ND, ::tflite::TensorType_UINT8, backends, inputShape, expectedOutputShape, inputValues, blockShape, crops, expectedOutputValues); } // SpaceToBatchND Operator void SpaceToBatchNDFp32Test(std::vector& backends) { std::vector inputShape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 4, 1, 1, 1 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector expectedOutputValues { 1.0f, 2.0f, 3.0f, 4.0f }; std::vector blockShape({2, 2}); std::vector> padding = {{0, 0}, {0, 0}}; BatchSpaceTest(tflite::BuiltinOperator_SPACE_TO_BATCH_ND, ::tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, blockShape, padding, expectedOutputValues); } void SpaceToBatchNDFp32PaddingTest(std::vector& backends) { std::vector inputShape { 2, 2, 4, 1 }; std::vector expectedOutputShape { 8, 1, 3, 1 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f }; std::vector expectedOutputValues { 0.0f, 1.0f, 3.0f, 0.0f, 9.0f, 11.0f, 0.0f, 2.0f, 4.0f, 0.0f, 10.0f, 12.0f, 0.0f, 5.0f, 7.0f, 0.0f, 13.0f, 15.0f, 0.0f, 6.0f, 8.0f, 0.0f, 14.0f, 16.0f }; std::vector blockShape({2, 2}); std::vector> padding = {{0, 0}, {2, 0}}; BatchSpaceTest(tflite::BuiltinOperator_SPACE_TO_BATCH_ND, ::tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, blockShape, padding, expectedOutputValues); } void SpaceToBatchNDUint8Test(std::vector& backends) { std::vector inputShape { 1, 2, 2, 3 }; std::vector expectedOutputShape { 4, 1, 1, 3 }; std::vector inputValues { 1, 2, 3, 4, 5, 6, 7 }; std::vector expectedOutputValues { 1, 2, 3, 4, 5, 6, 7 }; std::vector blockShape({2, 2}); std::vector> padding = {{0, 0}, {0, 0}}; BatchSpaceTest(tflite::BuiltinOperator_SPACE_TO_BATCH_ND, ::tflite::TensorType_UINT8, backends, inputShape, expectedOutputShape, inputValues, blockShape, padding, expectedOutputValues); } // BatchToSpaceND Tests TEST_SUITE("BatchToSpaceND_CpuAccTests") { TEST_CASE ("BatchToSpaceND_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; BatchToSpaceNDFp32Test(backends); } TEST_CASE ("BatchToSpaceND_Fp32_BatchOne_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; BatchToSpaceNDFp32BatchOneTest(backends); } TEST_CASE ("BatchToSpaceND_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; BatchToSpaceNDUint8Test(backends); } } TEST_SUITE("BatchToSpaceND_GpuAccTests") { TEST_CASE ("BatchToSpaceND_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; BatchToSpaceNDFp32Test(backends); } TEST_CASE ("BatchToSpaceND_Fp32_BatchOne_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; BatchToSpaceNDFp32BatchOneTest(backends); } TEST_CASE ("BatchToSpaceND_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; BatchToSpaceNDUint8Test(backends); } } TEST_SUITE("BatchToSpaceND_CpuRefTests") { TEST_CASE ("BatchToSpaceND_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; BatchToSpaceNDFp32Test(backends); } TEST_CASE ("BatchToSpaceND_Fp32_BatchOne_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; BatchToSpaceNDFp32BatchOneTest(backends); } TEST_CASE ("BatchToSpaceND_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; BatchToSpaceNDUint8Test(backends); } } // SpaceToBatchND Tests TEST_SUITE("SpaceToBatchND_CpuAccTests") { TEST_CASE ("SpaceToBatchND_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SpaceToBatchNDFp32Test(backends); } TEST_CASE ("SpaceToBatchND_Fp32_Padding_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SpaceToBatchNDFp32PaddingTest(backends); } TEST_CASE ("SpaceToBatchND_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SpaceToBatchNDUint8Test(backends); } } TEST_SUITE("SpaceToBatchND_GpuAccTests") { TEST_CASE ("SpaceToBatchND_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SpaceToBatchNDFp32Test(backends); } TEST_CASE ("SpaceToBatchND_Fp32_Padding_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SpaceToBatchNDFp32PaddingTest(backends); } TEST_CASE ("SpaceToBatchND_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SpaceToBatchNDUint8Test(backends); } } TEST_SUITE("SpaceToBatchND_CpuRefTests") { TEST_CASE ("SpaceToBatchND_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SpaceToBatchNDFp32Test(backends); } TEST_CASE ("SpaceToBatchND_Fp32_Padding_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SpaceToBatchNDFp32PaddingTest(backends); } TEST_CASE ("SpaceToBatchND_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SpaceToBatchNDUint8Test(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/BatchSpaceTestHelper.hpp000066400000000000000000000233521446772241200221160ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateBatchSpaceTfLiteModel(tflite::BuiltinOperator batchSpaceOperatorCode, tflite::TensorType tensorType, std::vector& inputTensorShape, std::vector & outputTensorShape, std::vector& blockData, std::vector>& cropsPadData, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 5> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder); buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(blockData.data()), sizeof(int32_t) * blockData.size())); buffers[3] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cropsPadData.data()), sizeof(int64_t) * cropsPadData.size())); buffers[4] = CreateBuffer(flatBufferBuilder); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::string cropsOrPadding = batchSpaceOperatorCode == tflite::BuiltinOperator_BATCH_TO_SPACE_ND ? "crops" : "padding"; std::vector blockShape { 2 }; std::vector cropsOrPaddingShape { 2, 2 }; std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(blockShape.data(), blockShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("block"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(cropsOrPaddingShape.data(), cropsOrPaddingShape.size()), ::tflite::TensorType_INT32, 3, flatBufferBuilder.CreateString(cropsOrPadding), quantizationParameters); // Create output tensor tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 4, flatBufferBuilder.CreateString("output"), quantizationParameters); // Create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOptions = 0; switch (batchSpaceOperatorCode) { case tflite::BuiltinOperator_BATCH_TO_SPACE_ND: { operatorBuiltinOptionsType = tflite::BuiltinOptions_BatchToSpaceNDOptions; operatorBuiltinOptions = CreateBatchToSpaceNDOptions(flatBufferBuilder).Union(); break; } case tflite::BuiltinOperator_SPACE_TO_BATCH_ND: { operatorBuiltinOptionsType = tflite::BuiltinOptions_SpaceToBatchNDOptions; operatorBuiltinOptions = CreateSpaceToBatchNDOptions(flatBufferBuilder).Union(); break; } default: break; } const std::vector operatorInputs{ {0, 1, 2} }; const std::vector operatorOutputs{ 3 }; flatbuffers::Offset batchSpaceOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1, 2} }; const std::vector subgraphOutputs{ 3 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&batchSpaceOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: BatchSpace Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, batchSpaceOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void BatchSpaceTest(tflite::BuiltinOperator controlOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& expectedOutputShape, std::vector& inputValues, std::vector& blockShapeValues, std::vector>& cropsPaddingValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateBatchSpaceTfLiteModel(controlOperatorCode, tensorType, inputShape, expectedOutputShape, blockShapeValues, cropsPaddingValues, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/CastTest.cpp000066400000000000000000000051031446772241200176400ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "CastTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void CastUint8ToFp32Test(std::vector& backends) { std::vector inputShape {1, 3, 2, 3}; std::vector inputValues { 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 2, 1, 3, 1, 3 }; std::vector expectedOutputValues { 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 2.0f, 1.0f, 3.0f, 1.0f, 3.0f }; CastTest(::tflite::TensorType_UINT8, ::tflite::TensorType_FLOAT32, backends, inputShape, inputValues, expectedOutputValues); } void CastInt32ToFp32Test(std::vector& backends) { std::vector inputShape {1, 3, 2, 3}; std::vector inputValues { -1, -3, -1, -3, -1, -3, -1, -3, 1, 3, 1, 3, 1, 2, 1, 3, 1, 3 }; std::vector expectedOutputValues { -1.0f, -3.0f, -1.0f, -3.0f, -1.0f, -3.0f, -1.0f, -3.0f, 1.0f, 3.0f, 1.0f, 3.0f, 1.0f, 2.0f, 1.0f, 3.0f, 1.0f, 3.0f }; CastTest(::tflite::TensorType_INT32, ::tflite::TensorType_FLOAT32, backends, inputShape, inputValues, expectedOutputValues); } // CAST Test Suite TEST_SUITE("CAST_CpuRefTests") { TEST_CASE ("CAST_UINT8_TO_FP32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; CastUint8ToFp32Test(backends); } TEST_CASE ("CAST_INT32_TO_FP32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; CastInt32ToFp32Test(backends); } } TEST_SUITE("CAST_CpuAccTests") { TEST_CASE ("CAST_INT32_TO_FP32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; CastInt32ToFp32Test(backends); } } TEST_SUITE("CAST_GpuAccTests") { TEST_CASE ("CAST_INT32_TO_FP32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; CastInt32ToFp32Test(backends); } } // End of CAST Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/CastTestHelper.hpp000066400000000000000000000145261446772241200210160ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateCastTfLiteModel(tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, const std::vector & tensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), outputTensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); const std::vector operatorInputs({0}); const std::vector operatorOutputs({1}); flatbuffers::Offset castOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_CastOptions, CreateCastOptions(flatBufferBuilder).Union()); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: CAST Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_CAST); const std::vector subgraphInputs({0}); const std::vector subgraphOutputs({1}); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&castOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void CastTest(tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, std::vector& backends, std::vector& shape, std::vector& inputValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateCastTfLiteModel(inputTensorType, outputTensorType, shape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, shape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/ComparisonTest.cpp000066400000000000000000000617101446772241200210660ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ComparisonTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void EqualFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1.f, 1.f, 1.f, 1.f, 5.f, 5.f, 5.f, 5.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f }; std::vector input1Values = { 1.f, 1.f, 1.f, 1.f, 3.f, 3.f, 3.f, 3.f, 5.f, 5.f, 5.f, 5.f, 4.f, 4.f, 4.f, 4.f }; std::vector expectedOutputValues = { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1 }; ComparisonTest(tflite::BuiltinOperator_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void EqualBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; // Set output data std::vector expectedOutputValues { 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 }; ComparisonTest(tflite::BuiltinOperator_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void EqualInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 4 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { 1, 0, 0, 1 }; ComparisonTest(tflite::BuiltinOperator_EQUAL, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void NotEqualFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1.f, 1.f, 1.f, 1.f, 5.f, 5.f, 5.f, 5.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f }; std::vector input1Values = { 1.f, 1.f, 1.f, 1.f, 3.f, 3.f, 3.f, 3.f, 5.f, 5.f, 5.f, 5.f, 4.f, 4.f, 4.f, 4.f }; std::vector expectedOutputValues = { 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 }; ComparisonTest(tflite::BuiltinOperator_NOT_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void NotEqualBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; // Set output data std::vector expectedOutputValues { 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1 }; ComparisonTest(tflite::BuiltinOperator_NOT_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void NotEqualInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 4 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { 0, 1, 1, 0 }; ComparisonTest(tflite::BuiltinOperator_NOT_EQUAL, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterFP32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 4 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { 0, 1, 0, 0 }; ComparisonTest(tflite::BuiltinOperator_GREATER, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; std::vector expectedOutputValues { 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 }; ComparisonTest(tflite::BuiltinOperator_GREATER, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 4 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { 0, 1, 0, 0 }; ComparisonTest(tflite::BuiltinOperator_GREATER, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterEqualFP32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1.f, 5.f, 6.f, 4.f }; std::vector input1Values = { 1.f, 3.f, 9.f, 4.f }; std::vector expectedOutputValues = { true, true, false, true }; ComparisonTest(tflite::BuiltinOperator_GREATER_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterEqualBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; // Set output data std::vector expectedOutputValues { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; ComparisonTest(tflite::BuiltinOperator_GREATER_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void GreaterEqualInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 3 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { 1, 1, 0, 0 }; ComparisonTest(tflite::BuiltinOperator_GREATER_EQUAL, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessFP32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1.f, 5.f, 6.f, 4.f }; std::vector input1Values = { 1.f, 3.f, 9.f, 4.f }; std::vector expectedOutputValues = { false, false, true, false }; ComparisonTest(tflite::BuiltinOperator_LESS, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; std::vector expectedOutputValues { true, true, true, false, false, false, false, false, false, false, false, false }; ComparisonTest(tflite::BuiltinOperator_LESS, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 3 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { false, false, true, true }; ComparisonTest(tflite::BuiltinOperator_LESS, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessEqualFP32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1.f, 5.f, 6.f, 4.f }; std::vector input1Values = { 1.f, 3.f, 9.f, 4.f }; std::vector expectedOutputValues = { true, false, true, true }; ComparisonTest(tflite::BuiltinOperator_LESS_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessEqualBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f }; std::vector input1Values { 4.f, 5.f, 6.f }; std::vector expectedOutputValues { true, true, true, true, true, true, false, false, false, false, false, false }; ComparisonTest(tflite::BuiltinOperator_LESS_EQUAL, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LessEqualInt32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values = { 1, 5, 6, 3 }; std::vector input1Values = { 1, 3, 9, 4 }; std::vector expectedOutputValues = { true, false, true, true }; ComparisonTest(tflite::BuiltinOperator_LESS_EQUAL, ::tflite::TensorType_INT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } TEST_SUITE("Comparison_CpuRefTests") { TEST_CASE ("EQUAL_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; EqualFP32Test(backends); } TEST_CASE ("EQUAL_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; EqualBroadcastTest(backends); } TEST_CASE ("EQUAL_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; EqualInt32Test(backends); } TEST_CASE ("NOT_EQUAL_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; NotEqualFP32Test(backends); } TEST_CASE ("NOT_EQUAL_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; NotEqualBroadcastTest(backends); } TEST_CASE ("NOT_EQUAL_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; NotEqualInt32Test(backends); } TEST_CASE ("GREATER_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterFP32Test(backends); } TEST_CASE ("GREATER_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterBroadcastTest(backends); } TEST_CASE ("GREATER_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterInt32Test(backends); } TEST_CASE ("GREATER_EQUAL_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterEqualFP32Test(backends); } TEST_CASE ("GREATER_EQUAL_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterEqualBroadcastTest(backends); } TEST_CASE ("GREATER_EQUAL_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; GreaterEqualInt32Test(backends); } TEST_CASE ("LESS_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessFP32Test(backends); } TEST_CASE ("LESS_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessBroadcastTest(backends); } TEST_CASE ("LESS_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessInt32Test(backends); } TEST_CASE ("LESS_EQUAL_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessEqualFP32Test(backends); } TEST_CASE ("LESS_EQUAL_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessEqualBroadcastTest(backends); } TEST_CASE ("LESS_EQUAL_INT32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LessEqualInt32Test(backends); } } // End TEST_SUITE("Comparison_CpuRefTests") TEST_SUITE("Comparison_GpuAccTests") { TEST_CASE ("EQUAL_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; EqualFP32Test(backends); } TEST_CASE ("EQUAL_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; EqualBroadcastTest(backends); } TEST_CASE ("EQUAL_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; EqualInt32Test(backends); } TEST_CASE ("NOT_EQUAL_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; NotEqualFP32Test(backends); } TEST_CASE ("NOT_EQUAL_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; NotEqualBroadcastTest(backends); } TEST_CASE ("NOT_EQUAL_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; NotEqualInt32Test(backends); } TEST_CASE ("GREATER_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc, armnn::Compute::CpuRef }; GreaterFP32Test(backends); } TEST_CASE ("GREATER_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc, armnn::Compute::CpuRef }; GreaterBroadcastTest(backends); } TEST_CASE ("GREATER_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc, armnn::Compute::CpuRef }; GreaterInt32Test(backends); } TEST_CASE ("GREATER_EQUAL_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; GreaterEqualFP32Test(backends); } TEST_CASE ("GREATER_EQUAL_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; GreaterEqualBroadcastTest(backends); } TEST_CASE ("GREATER_EQUAL_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; GreaterEqualInt32Test(backends); } TEST_CASE ("LESS_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessFP32Test(backends); } TEST_CASE ("LESS_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessBroadcastTest(backends); } TEST_CASE ("LESS_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessInt32Test(backends); } TEST_CASE ("LESS_EQUAL_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessEqualFP32Test(backends); } TEST_CASE ("LESS_EQUAL_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessEqualBroadcastTest(backends); } TEST_CASE ("LESS_EQUAL_INT32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LessEqualInt32Test(backends); } } // End TEST_SUITE("Comparison_GpuAccTests") TEST_SUITE("Comparison_CpuAccTests") { TEST_CASE ("EQUAL_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; EqualFP32Test(backends); } TEST_CASE ("EQUAL_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; EqualBroadcastTest(backends); } TEST_CASE ("EQUAL_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; EqualInt32Test(backends); } TEST_CASE ("NOT_EQUAL_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; NotEqualFP32Test(backends); } TEST_CASE ("NOT_EQUAL_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; NotEqualBroadcastTest(backends); } TEST_CASE ("NOT_EQUAL_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; NotEqualInt32Test(backends); } TEST_CASE ("GREATER_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterFP32Test(backends); } TEST_CASE ("GREATER_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterBroadcastTest(backends); } TEST_CASE ("GREATER_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterInt32Test(backends); } TEST_CASE ("GREATER_EQUAL_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterEqualFP32Test(backends); } TEST_CASE ("GREATER_EQUAL_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterEqualBroadcastTest(backends); } TEST_CASE ("GREATER_EQUAL_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; GreaterEqualInt32Test(backends); } TEST_CASE ("LESS_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessFP32Test(backends); } TEST_CASE ("LESS_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessBroadcastTest(backends); } TEST_CASE ("LESS_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessInt32Test(backends); } TEST_CASE ("LESS_EQUAL_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessEqualFP32Test(backends); } TEST_CASE ("LESS_EQUAL_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessEqualBroadcastTest(backends); } TEST_CASE ("LESS_EQUAL_INT32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LessEqualInt32Test(backends); } } // End TEST_SUITE("Comparison_CpuAccTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/ComparisonTestHelper.hpp000066400000000000000000000225641446772241200222370ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateComparisonTfLiteModel(tflite::BuiltinOperator comparisonOperatorCode, tflite::TensorType tensorType, const std::vector & input0TensorShape, const std::vector & input1TensorShape, const std::vector & outputTensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input1TensorShape.data(), input1TensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("input_1"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), ::tflite::TensorType_BOOL, 3); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_EqualOptions;; flatbuffers::Offset operatorBuiltinOptions = CreateEqualOptions(flatBufferBuilder).Union(); switch (comparisonOperatorCode) { case BuiltinOperator_EQUAL: { operatorBuiltinOptionsType = BuiltinOptions_EqualOptions; operatorBuiltinOptions = CreateEqualOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_NOT_EQUAL: { operatorBuiltinOptionsType = BuiltinOptions_NotEqualOptions; operatorBuiltinOptions = CreateNotEqualOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_GREATER: { operatorBuiltinOptionsType = BuiltinOptions_GreaterOptions; operatorBuiltinOptions = CreateGreaterOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_GREATER_EQUAL: { operatorBuiltinOptionsType = BuiltinOptions_GreaterEqualOptions; operatorBuiltinOptions = CreateGreaterEqualOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_LESS: { operatorBuiltinOptionsType = BuiltinOptions_LessOptions; operatorBuiltinOptions = CreateLessOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_LESS_EQUAL: { operatorBuiltinOptionsType = BuiltinOptions_LessEqualOptions; operatorBuiltinOptions = CreateLessEqualOptions(flatBufferBuilder).Union(); break; } default: break; } const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset comparisonOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&comparisonOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Comparison Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, comparisonOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ComparisonTest(tflite::BuiltinOperator comparisonOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& input0Shape, std::vector& input1Shape, std::vector& outputShape, std::vector& input0Values, std::vector& input1Values, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateComparisonTfLiteModel(comparisonOperatorCode, tensorType, input0Shape, input1Shape, outputShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareData(expectedOutputValues, armnnOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(expectedOutputValues, tfLiteOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues.size()); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ControlTest.cpp000066400000000000000000000305401446772241200203710ustar00rootroot00000000000000// // Copyright © 2020,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ControlTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // CONCATENATION Operator void ConcatUint8TwoInputsTest(std::vector& backends) { std::vector inputShape { 2, 2 }; std::vector expectedOutputShape { 4, 2 }; // Set input and output data std::vector> inputValues; std::vector inputValue1 { 0, 1, 2, 3 }; // Lower bounds std::vector inputValue2 { 252, 253, 254, 255 }; // Upper bounds inputValues.push_back(inputValue1); inputValues.push_back(inputValue2); std::vector expectedOutputValues { 0, 1, 2, 3, 252, 253, 254, 255 }; ConcatenationTest(tflite::BuiltinOperator_CONCATENATION, ::tflite::TensorType_UINT8, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues); } void ConcatInt16TwoInputsTest(std::vector& backends) { std::vector inputShape { 2, 2 }; std::vector expectedOutputShape { 4, 2 }; std::vector> inputValues; std::vector inputValue1 { -32768, -16384, -1, 0 }; std::vector inputValue2 { 1, 2, 16384, 32767 }; inputValues.push_back(inputValue1); inputValues.push_back(inputValue2); std::vector expectedOutputValues { -32768, -16384, -1, 0, 1, 2, 16384, 32767}; ConcatenationTest(tflite::BuiltinOperator_CONCATENATION, ::tflite::TensorType_INT16, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues); } void ConcatFloat32TwoInputsTest(std::vector& backends) { std::vector inputShape { 2, 2 }; std::vector expectedOutputShape { 4, 2 }; std::vector> inputValues; std::vector inputValue1 { -127.f, -126.f, -1.f, 0.f }; std::vector inputValue2 { 1.f, 2.f, 126.f, 127.f }; inputValues.push_back(inputValue1); inputValues.push_back(inputValue2); std::vector expectedOutputValues { -127.f, -126.f, -1.f, 0.f, 1.f, 2.f, 126.f, 127.f }; ConcatenationTest(tflite::BuiltinOperator_CONCATENATION, ::tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues); } void ConcatThreeInputsTest(std::vector& backends) { std::vector inputShape { 2, 2 }; std::vector expectedOutputShape { 6, 2 }; std::vector> inputValues; std::vector inputValue1 { 0, 1, 2, 3 }; std::vector inputValue2 { 125, 126, 127, 128 }; std::vector inputValue3 { 252, 253, 254, 255 }; inputValues.push_back(inputValue1); inputValues.push_back(inputValue2); inputValues.push_back(inputValue3); std::vector expectedOutputValues { 0, 1, 2, 3, 125, 126, 127, 128, 252, 253, 254, 255 }; ConcatenationTest(tflite::BuiltinOperator_CONCATENATION, ::tflite::TensorType_UINT8, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues); } void ConcatAxisTest(std::vector& backends) { std::vector inputShape { 1, 2, 2 }; std::vector expectedOutputShape { 1, 2, 4 }; std::vector> inputValues; std::vector inputValue1 { 0, 1, 2, 3 }; std::vector inputValue3 { 252, 253, 254, 255 }; inputValues.push_back(inputValue1); inputValues.push_back(inputValue3); std::vector expectedOutputValues { 0, 1, 252, 253, 2, 3, 254, 255 }; ConcatenationTest(tflite::BuiltinOperator_CONCATENATION, ::tflite::TensorType_UINT8, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 2); } // MEAN Operator void MeanUint8KeepDimsTest(std::vector& backends) { std::vector input0Shape { 1, 3 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1 }; std::vector input0Values { 5, 10, 15 }; // Inputs std::vector input1Values { 1 }; // Axis std::vector expectedOutputValues { 10 }; MeanTest(tflite::BuiltinOperator_MEAN, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, true); } void MeanUint8Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 2, 2 }; std::vector input0Values { 5, 10, 15, 20 }; // Inputs std::vector input1Values { 0 }; // Axis std::vector expectedOutputValues { 5, 10, 15, 20 }; MeanTest(tflite::BuiltinOperator_MEAN, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, false); } void MeanFp32KeepDimsTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1, 2 }; std::vector input0Values { 1.0f, 1.5f, 2.0f, 2.5f }; // Inputs std::vector input1Values { 1 }; // Axis std::vector expectedOutputValues { 1.5f, 2.0f }; MeanTest(tflite::BuiltinOperator_MEAN, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, true); } void MeanFp32Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 2, 1 }; std::vector input0Values { 1.0f, 1.5f, 2.0f, 2.5f }; // Inputs std::vector input1Values { 2 }; // Axis std::vector expectedOutputValues { 1.25f, 2.25f }; MeanTest(tflite::BuiltinOperator_MEAN, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, false); } // CONCATENATION Tests. TEST_SUITE("Concatenation_CpuAccTests") { TEST_CASE ("Concatenation_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; ConcatUint8TwoInputsTest(backends); } TEST_CASE ("Concatenation_Int16_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; ConcatInt16TwoInputsTest(backends); } TEST_CASE ("Concatenation_Float32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; ConcatFloat32TwoInputsTest(backends); } TEST_CASE ("Concatenation_Three_Inputs_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; ConcatThreeInputsTest(backends); } TEST_CASE ("Concatenation_Axis_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; ConcatAxisTest(backends); } } TEST_SUITE("Concatenation_GpuAccTests") { TEST_CASE ("Concatenation_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; ConcatUint8TwoInputsTest(backends); } TEST_CASE ("Concatenation_Int16_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; ConcatInt16TwoInputsTest(backends); } TEST_CASE ("Concatenation_Float32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; ConcatFloat32TwoInputsTest(backends); } TEST_CASE ("Concatenation_Three_Inputs_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; ConcatThreeInputsTest(backends); } TEST_CASE ("Concatenation_Axis_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; ConcatAxisTest(backends); } } TEST_SUITE("Concatenation_CpuRefTests") { TEST_CASE ("Concatenation_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; ConcatUint8TwoInputsTest(backends); } TEST_CASE ("Concatenation_Int16_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; ConcatInt16TwoInputsTest(backends); } TEST_CASE ("Concatenation_Float32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; ConcatFloat32TwoInputsTest(backends); } TEST_CASE ("Concatenation_Three_Inputs_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; ConcatThreeInputsTest(backends); } TEST_CASE ("Concatenation_Axis_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; ConcatAxisTest(backends); } } // MEAN Tests TEST_SUITE("Mean_CpuAccTests") { TEST_CASE ("Mean_Uint8_KeepDims_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; MeanUint8KeepDimsTest(backends); } TEST_CASE ("Mean_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; MeanUint8Test(backends); } TEST_CASE ("Mean_Fp32_KeepDims_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; MeanFp32KeepDimsTest(backends); } TEST_CASE ("Mean_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; MeanFp32Test(backends); } } TEST_SUITE("Mean_GpuAccTests") { TEST_CASE ("Mean_Uint8_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; MeanUint8KeepDimsTest(backends); } TEST_CASE ("Mean_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; MeanUint8Test(backends); } TEST_CASE ("Mean_Fp32_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; MeanFp32KeepDimsTest(backends); } TEST_CASE ("Mean_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; MeanFp32Test(backends); } } TEST_SUITE("Mean_CpuRefTests") { TEST_CASE ("Mean_Uint8_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; MeanUint8KeepDimsTest(backends); } TEST_CASE ("Mean_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; MeanUint8Test(backends); } TEST_CASE ("Mean_Fp32_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; MeanFp32KeepDimsTest(backends); } TEST_CASE ("Mean_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; MeanFp32Test(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/ControlTestHelper.hpp000066400000000000000000000364761446772241200215540ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateConcatTfLiteModel(tflite::BuiltinOperator controlOperatorCode, tflite::TensorType tensorType, std::vector& inputTensorShape, const std::vector & outputTensorShape, const int32_t inputTensorNum, int32_t axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::vector operatorInputs{}; const std::vector operatorOutputs{inputTensorNum}; std::vector subgraphInputs{}; const std::vector subgraphOutputs{inputTensorNum}; std::vector> tensors(inputTensorNum + 1); for (int i = 0; i < inputTensorNum; ++i) { tensors[i] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input" + std::to_string(i)), quantizationParameters); // Add number of inputs to vector. operatorInputs.push_back(i); subgraphInputs.push_back(i); } // Create output tensor tensors[inputTensorNum] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_ConcatenationOptions; flatbuffers::Offset operatorBuiltinOptions = CreateConcatenationOptions(flatBufferBuilder, axis).Union(); flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Concatenation Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, controlOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } std::vector CreateMeanTfLiteModel(tflite::BuiltinOperator controlOperatorCode, tflite::TensorType tensorType, std::vector& input0TensorShape, std::vector& input1TensorShape, const std::vector & outputTensorShape, std::vector& axisData, const bool keepDims, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 2> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(axisData.data()), sizeof(int32_t) * axisData.size())); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input1TensorShape.data(), input1TensorShape.size()), ::tflite::TensorType_INT32, 1, flatBufferBuilder.CreateString("axis"), quantizationParameters); // Create output tensor tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator. Mean uses ReducerOptions. tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_ReducerOptions; flatbuffers::Offset operatorBuiltinOptions = CreateReducerOptions(flatBufferBuilder, keepDims).Union(); const std::vector operatorInputs{ {0, 1} }; const std::vector operatorOutputs{ 2 }; flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1} }; const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Mean Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, controlOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ConcatenationTest(tflite::BuiltinOperator controlOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShapes, std::vector& expectedOutputShape, std::vector>& inputValues, std::vector& expectedOutputValues, int32_t axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateConcatTfLiteModel(controlOperatorCode, tensorType, inputShapes, expectedOutputShape, inputValues.size(), axis, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); for (unsigned int i = 0; i < inputValues.size(); ++i) { CHECK(tfLiteInterpreter.FillInputTensor(inputValues[i], i) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues[i], i) == kTfLiteOk); } CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } template void MeanTest(tflite::BuiltinOperator controlOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& input0Shape, std::vector& input1Shape, std::vector& expectedOutputShape, std::vector& input0Values, std::vector& input1Values, std::vector& expectedOutputValues, const bool keepDims, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateMeanTfLiteModel(controlOperatorCode, tensorType, input0Shape, input1Shape, expectedOutputShape, input1Values, keepDims, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/Convolution2dTest.cpp000066400000000000000000000323161446772241200215210ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ConvolutionTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void Conv2DWithBiasesFp32Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 5, 5, 1 }; std::vector filterShape { 1, 3, 3, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 3, 3, 1 }; static std::vector inputValues = { 1, 5, 2, 3, 5, 8, 7, 3, 6, 3, 3, 3, 9, 1, 9, 4, 1, 8, 1, 3, 6, 8, 1, 9, 2 }; std::vector filterValues = { 4, 5, 6, 0, 0, 0, 3, 2, 1 }; std::vector biasValues = { 0 }; std::vector expectedOutputValues = { 23, 33, 24, 91, 99, 48, 26, 50, 19 }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_CONV_2D, ::tflite::TensorType_FLOAT32, 2, // strideX 2, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv2DWithBiasesInt8Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector filterShape { 1, 2, 2, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 2, 2, 1 }; static std::vector inputValues = { 1, 2, 3, 4 }; std::vector filterValues = { 2, 1, 0, 6 }; std::vector biasValues = { 10 }; std::vector expectedOutputValues = { (1 * 2 + 2 * 1 + 3 * 0 + 4 * 6 + 10) / 2, // 19 (2 * 2 + 0 * 1 + 4 * 0 + 0 * 6 + 10) / 2, // 7 (3 * 2 + 4 * 1 + 0 * 0 + 0 * 6 + 10) / 2, // 10 (4 * 2 + 0 * 1 + 0 * 0 + 0 * 6 + 10) / 2, // 9 }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_CONV_2D, ::tflite::TensorType_INT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv2DWithBiasesReluUint8Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector filterShape { 1, 2, 2, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 2, 2, 1 }; static std::vector inputValues = { 1, 2, 4, 8 }; std::vector filterValues = { 2, 1, 0, 6 }; std::vector biasValues = { 16 }; // factors to consider: // - the filter zero point is non zero, hence the (x-fz) // - the output scale is 2 hence the /2 // - output zero point is non zero, hence the +outZero // - RELU cuts negative values and then we add the output zero point uint8_t bias = 16; uint8_t outZero = 20; uint8_t fz = 4; // filter zero point std::vector expectedOutputValues = { std::max(outZero, static_cast((1*(2-fz) + 2*(1-fz) + 4*(0-fz) + 8*(6-fz) + bias)/2 + outZero)), std::max(outZero, static_cast((2*(2-fz) + 0*(1-fz) + 8*(0-fz) + 0*(6-fz) + bias)/2 + outZero)), std::max(outZero, static_cast((4*(2-fz) + 8*(1-fz) + 0*(0-fz) + 0*(6-fz) + bias)/2 + outZero)), std::max(outZero, static_cast((8*(2-fz) + 0*(1-fz) + 0*(0-fz) + 0*(6-fz) + bias)/2 + outZero)) }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_CONV_2D, ::tflite::TensorType_UINT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_RELU, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues, {1.0f}, // biasScale {0}, // biasOffset {1.0f}, // filterScale {4}, // filterOffsets 2, // output scale 20); // output offset } void Conv2DWithBiasesRelu6Uint8Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector filterShape { 1, 2, 2, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 2, 2, 1 }; static std::vector inputValues = { 1, 2, 4, 1 }; std::vector filterValues = { 2, 1, 0, 6 }; std::vector biasValues = { 0 }; // factors to consider: // - the output scale is 2 hence the /2 // - RELU6 cuts output values at +6 uint8_t relu6Min = 6 / 2; // divide by output scale std::vector expectedOutputValues = { std::min(relu6Min, static_cast((1 * 2 + 2 * 1 + 4 * 0 + 1 * 6) / 2)), std::min(relu6Min, static_cast((2 * 2 + 0 * 1 + 1 * 0 + 0 * 6) / 2)), std::min(relu6Min, static_cast((4 * 2 + 1 * 1 + 0 * 0 + 0 * 6) / 2)), std::min(relu6Min, static_cast((1 * 2 + 0 * 1 + 0 * 0 + 0 * 6) / 2)) }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_CONV_2D, ::tflite::TensorType_UINT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_RELU6, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv2DPerChannelInt8Test(std::vector& backends) { // Set input data std::vector inputShape { 1,4,4,2 }; std::vector filterShape { 4,2,2,2 }; std::vector biasShape { 4 }; std::vector outputShape { 1,4,4,4 }; static std::vector inputValues = { -11, 40,-26, 11,-28, 8, 0, -8, -10, 34, 47, 0,-33,-14, 28, 35, 6,-28,-26, 8, 13, 33,-31,-41, 31,-20,-31,-16, 8,-18,-44, 0 }; std::vector filterScales = { 1.858268, 2.0, 1.992126, 1.905512 }; int32_t filterQuantizationDim = 0; std::vector filterValues = { 13,-44, 5,-14, 21,-45, 36,-25, -42, -2, 24,-30,-31, 35, 43,-30, -20, -5, 25, 17, 18, 20, 4,-46, -49, 9, -3,-20, 46, 5, 7,-15 }; std::vector biasValues = { 0,0,0,0 }; std::vector biasScales = { 0.721445, 0.7764700055, 0.773414, 0.739787 }; std::vector expectedOutputValues = { -1, 9, 3, 5, 1, -1, 5, 9, 2, 7, -1, 2, 2, 4, 5, 6, 1, 1, 4, 4, 2, 0, -4, -3, 0, 6, 12, 6, 3, 0, -1, -2, 7, -4, 4, 4, 3, 6, 6, 2, 0, -3, -1, 4, 4, 8, 3, 1, 5, 0, 0, 1, 4, 7, 4, 6, 4, 0, 1, 2, 2, 7, 5, 7 }; float outputQuantScale = 401.960785f; int outputQuantOffset = 3; float inputQuantScale = 0.388235f; int inputQuantOffset = 1; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_CONV_2D, ::tflite::TensorType_INT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues, biasScales, {0,0,0,0}, filterScales, {0,0,0,0}, outputQuantScale, outputQuantOffset, inputQuantScale, inputQuantOffset, 1, // depth_multiplier is ignored for conv2d value doesn't matter filterQuantizationDim); } TEST_SUITE("Convolution2dTest_CpuRefTests") { TEST_CASE ("Conv2DWithBiases_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv2DWithBiasesFp32Test(backends); } TEST_CASE ("Conv2DWithBiases_Int8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv2DWithBiasesInt8Test(backends); } TEST_CASE ("Conv2DPerChannel_Int8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv2DPerChannelInt8Test(backends); } } //End of TEST_SUITE("Convolution2dTest_CpuRef") TEST_SUITE("Convolution2dTest_CpuAccTests") { TEST_CASE ("Conv2DWithBiases_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv2DWithBiasesFp32Test(backends); } TEST_CASE ("Conv2DWithBiases_Int8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv2DWithBiasesInt8Test(backends); } TEST_CASE ("Conv2DPerChannel_Int8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv2DPerChannelInt8Test(backends); } } //End of TEST_SUITE("Convolution2dTest_CpuAcc") TEST_SUITE("Convolution2dTest_GpuAccTests") { TEST_CASE ("Conv2DWithBiases_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv2DWithBiasesFp32Test(backends); } TEST_CASE ("Conv2DWithBiases_Int8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv2DWithBiasesInt8Test(backends); } TEST_CASE ("Conv2DPerChannel_Int8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv2DPerChannelInt8Test(backends); } } //End of TEST_SUITE("Convolution2dTest_GpuAcc") } // namespace armnnDelegatearmnn-23.08/delegate/test/Convolution3dTest.cpp000066400000000000000000000240561446772241200215240ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ConvolutionTestHelper.hpp" #include #include #include #include #include #include #include namespace armnnDelegate { // Conv3d is currently only supports Float32 inputs, filter, bias and outputs in TFLite. // Conv3d is only correctly supported for external delegates from TF Lite v2.6, as there was a breaking bug in v2.5. #if defined(ARMNN_POST_TFLITE_2_5) // Create a vector from 0 to size divided to create smaller floating point values. template std::vector CreateFloatData(int32_t size, float divisor) { std::vector data; for (int32_t i = 0; i < size; ++i) { float value = static_cast(i); data.push_back(value/divisor); } return data; } void Conv3DWithBiasesSimpleWithPaddingFp32Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 2, 1 }; std::vector filterShape { 2, 2, 2, 1, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 2, 2, 2, 1 }; static std::vector inputValues = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f }; std::vector filterValues = { 2.f,1.f, 1.f,0.f, 0.f,1.f, 1.f,1.f }; std::vector biasValues = { 5.f }; std::vector expectedOutputValues = { 33.f, 21.f, 23.f, 13.f, 28.f, 25.f, 27.f, 21.f }; Convolution3dTest(tflite::BuiltinOperator_CONV_3D, ::tflite::TensorType_FLOAT32, { 1, 1, 1 }, // strideX, strideY, strideZ { 1, 1, 1 }, // dilationX, dilationY, dilationZ tflite::Padding_SAME, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv3DWithBiasesStridesFp32Test(std::vector& backends) { std::vector inputShape { 1, 3, 10, 10, 1 }; std::vector filterShape { 3, 5, 5, 1, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 1, 3, 3, 1 }; std::vector inputValues = CreateFloatData(300, 1.0f); std::vector filterValues = { 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 1.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f, 2.f }; std::vector biasValues = { 10.f }; std::vector expectedOutputValues = { 11660.f, 11810.f, 11960.f, 13160.f, 13310.f, 13460.f, 14660.f, 14810.f, 14960.f }; Convolution3dTest(tflite::BuiltinOperator_CONV_3D, ::tflite::TensorType_FLOAT32, { 2, 2, 2 }, // strideX, strideY, strideZ { 1, 1, 1 }, // dilationX, dilationY, dilationZ tflite::Padding_VALID, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv3DWithBiasesDilationFp32Test(std::vector& backends) { std::vector inputShape { 1, 5, 5, 5, 2 }; std::vector filterShape { 2, 2, 2, 2, 2 }; std::vector biasShape { 2 }; std::vector outputShape { 1, 2, 2, 2, 2 }; std::vector inputValues = CreateFloatData(250, 1.0f); std::vector filterValues = { -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, -1.f, 1.f, 1.f, 1.f, -1.f, -1.f, 1.f, 1.f, -1.f, 1.f, -1.f, 1.f, -1.f, 1.f, -1.f, -1.f, -1.f, 1.f, -1.f, 1.f, -1.f, 1.f, }; std::vector biasValues = { 0.f, 2.f }; // Since the dilation rate is 3 this will dilate the kernel to be 4x4, // therefore the output will be 2x2 std::vector expectedOutputValues = { -1124.f, 976.f, -1148.f, 980.f, -1244.f, 996.f, -1268.f, 1000.f, -1724.f, 1076.f, -1748.f, 1080.f, -1844.f, 1096.f, -1868.f, 1100.f }; Convolution3dTest(tflite::BuiltinOperator_CONV_3D, ::tflite::TensorType_FLOAT32, { 1, 1, 1 }, // strideX, strideY, strideZ { 3, 3, 3 }, // dilationX, dilationY, dilationZ tflite::Padding_VALID, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void Conv3DFp32SmallTest(std::vector& backends) { std::vector inputShape { 1, 3, 10, 10, 1 }; std::vector filterShape { 3, 3, 3, 1, 1 }; std::vector biasShape { 1 }; std::vector outputShape { 1, 1, 4, 4, 1 }; std::vector inputValues = CreateFloatData(300, 100.0f); std::vector filterValues = { 0.125977f, 0.150391f, 0.101562f, 0.0585938f, 0.0864258f, 0.043457f, 0.034668f, 0.0322266f, 0.0385742f, 0.125977f, 0.150391f, -0.101562f, -0.0585938f,-0.0864258f,-0.043457f, -0.0104630f, 0.0154114f, 0.0013768f, 0.0344238f, 0.035644f, 0.0495605f, 0.0683594f, 0.099121f, -0.0461426f, -0.0996094f,-0.126953f, -0.043457f, }; std::vector biasValues = { 0 }; std::vector expectedOutputValues = { -0.08156067f, -0.06891209f, -0.05589598f, -0.04310101f, 0.04584253f, 0.05855697f, 0.07129729f, 0.08325434f, 0.17304349f, 0.18521416f, 0.19818866f, 0.21096253f, 0.29965734f, 0.312698f, 0.32547557f, 0.33818722f }; Convolution3dTest(tflite::BuiltinOperator_CONV_3D, ::tflite::TensorType_FLOAT32, { 2, 2, 2 }, // strideX, strideY, strideZ { 1, 1, 1 }, // dilationX, dilationY, dilationZ tflite::Padding_VALID, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } TEST_SUITE("Convolution3dTest_CpuRefTests") { TEST_CASE ("Conv3DWithBiasesSimpleWithPadding_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv3DWithBiasesSimpleWithPaddingFp32Test(backends); } TEST_CASE ("Conv3DWithBiasesStrides_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv3DWithBiasesStridesFp32Test(backends); } TEST_CASE ("Conv3DWithBiasesDilation_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv3DWithBiasesDilationFp32Test(backends); } TEST_CASE ("Conv3DFp32Small_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; Conv3DFp32SmallTest(backends); } } //End of TEST_SUITE("Convolution3dTest_CpuRefTests") TEST_SUITE("Convolution3dTest_CpuAccTests") { TEST_CASE ("Conv3DWithBiasesSimpleWithPadding_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv3DWithBiasesSimpleWithPaddingFp32Test(backends); } TEST_CASE ("Conv3DWithBiasesStrides_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv3DWithBiasesStridesFp32Test(backends); } TEST_CASE ("Conv3DFp32Small_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; Conv3DFp32SmallTest(backends); } } //End of TEST_SUITE("Convolution3dTest_CpuAccTests") TEST_SUITE("Convolution3dTest_GpuAccTests") { TEST_CASE ("Conv3DWithBiasesSimpleWithPadding_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv3DWithBiasesSimpleWithPaddingFp32Test(backends); } TEST_CASE ("Conv3DWithBiasesStrides_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv3DWithBiasesStridesFp32Test(backends); } TEST_CASE ("Conv3DFp32Small_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; Conv3DFp32SmallTest(backends); } } //End of TEST_SUITE("Convolution3dTest_GpuAccTests") #endif } // namespace armnnDelegatearmnn-23.08/delegate/test/ConvolutionTestHelper.hpp000066400000000000000000001144161446772241200224420ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include #include #include namespace { template std::vector CreateConv2dTfLiteModel(tflite::BuiltinOperator convolutionOperatorCode, tflite::TensorType tensorType, uint32_t strideX, uint32_t strideY, uint32_t dilationX, uint32_t dilationY, tflite::Padding padding, tflite::ActivationFunctionType fused_activation_function, const std::vector & inputTensorShape, const std::vector & filterTensorShape, const std::vector & biasTensorShape, const std::vector & outputTensorShape, const std::vector & filterData, const std::vector & biasData, const std::vector biasScales = {1.0f}, const std::vector biasOffsets = {0}, const std::vector filterScales = {1.0f}, const std::vector filterOffsets = {0}, float outputQuantScale = 2.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0, int32_t depth_multiplier = 1, int32_t filterQuantizationDim = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 5> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder); buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(filterData.data()), sizeof(T) * filterData.size())); buffers[3] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(biasData.data()), sizeof(B) * biasData.size())); buffers[4] = CreateBuffer(flatBufferBuilder); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto outputQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ outputQuantScale }), flatBufferBuilder.CreateVector({ outputQuantOffset })); auto filterQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector(filterScales), flatBufferBuilder.CreateVector(filterOffsets), tflite::QuantizationDetails_NONE, 0, filterQuantizationDim); auto biasQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector(biasScales), flatBufferBuilder.CreateVector(biasOffsets)); std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(filterTensorShape.data(), filterTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("filter"), filterQuantizationParameters); auto biasTensorType = ::tflite::TensorType_FLOAT32; if (tensorType == ::tflite::TensorType_INT8 || tensorType == ::tflite::TensorType_UINT8) { biasTensorType = ::tflite::TensorType_INT32; } tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(biasTensorShape.data(), biasTensorShape.size()), biasTensorType, 3, flatBufferBuilder.CreateString("bias"), biasQuantizationParameters); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 4, flatBufferBuilder.CreateString("output"), outputQuantizationParameters); flatbuffers::Offset operatorBuiltinOptions; tflite::BuiltinOptions operatorBuiltinOptionsType; if(convolutionOperatorCode == tflite::BuiltinOperator_DEPTHWISE_CONV_2D) { operatorBuiltinOptionsType = tflite::BuiltinOptions_DepthwiseConv2DOptions; operatorBuiltinOptions = CreateDepthwiseConv2DOptions(flatBufferBuilder, padding, strideX, strideY, depth_multiplier, fused_activation_function, dilationX, dilationY).Union(); } if(convolutionOperatorCode == tflite::BuiltinOperator_CONV_2D) { operatorBuiltinOptionsType = tflite::BuiltinOptions_Conv2DOptions; operatorBuiltinOptions = CreateConv2DOptions(flatBufferBuilder, padding, strideX, strideY, fused_activation_function, dilationX, dilationY).Union(); } // create operator const std::vector operatorInputs{0, 1, 2}; const std::vector operatorOutputs{3}; flatbuffers::Offset convolutionOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1, 2}; const std::vector subgraphOutputs{3}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&convolutionOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Convolution2d Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, convolutionOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ConvolutionTest(tflite::BuiltinOperator convolutionOperatorCode, tflite::TensorType tensorType, uint32_t strideX, uint32_t strideY, uint32_t dilationX, uint32_t dilationY, tflite::Padding padding, tflite::ActivationFunctionType fused_activation_function, std::vector& backends, std::vector& inputShape, std::vector& filterShape, std::vector& outputShape, std::vector& inputValues, std::vector& filterValues, std::vector& expectedOutputValues, const std::vector& biasShape = {}, const std::vector& biasValues = {}, const std::vector biasScales = {1.0f}, const std::vector biasOffsets = {0}, const std::vector filterScales = {1.0f}, const std::vector filterOffsets = {0}, float outputQuantScale = 2.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0, int32_t depth_multiplier = 1, int32_t filterQuantizationDim = 3) { using namespace delegateTestInterpreter; std::vector modelBuffer; modelBuffer = CreateConv2dTfLiteModel(convolutionOperatorCode, tensorType, strideX, strideY, dilationX, dilationY, padding, fused_activation_function, inputShape, filterShape, biasShape, outputShape, filterValues, biasValues, biasScales, biasOffsets, filterScales, filterOffsets, outputQuantScale, outputQuantOffset, quantScale, quantOffset, depth_multiplier, filterQuantizationDim); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // Conv3d is only correctly supported for external delegates from TF Lite v2.6, as there was a breaking bug in v2.5. #if defined(ARMNN_POST_TFLITE_2_5) template std::vector CreateConv3dTfLiteModel(tflite::BuiltinOperator convolutionOperatorCode, tflite::TensorType tensorType, std::vector strides, std::vector dilation, tflite::Padding padding, tflite::ActivationFunctionType fused_activation_function, const std::vector& inputTensorShape, const std::vector& filterTensorShape, const std::vector& biasTensorShape, const std::vector& outputTensorShape, const std::vector& filterData, const std::vector& biasData, const std::vector biasScales = {1.0f}, const std::vector biasOffsets = {0}, const std::vector filterScales = {1.0f}, const std::vector filterOffsets = {0}, float outputQuantScale = 2.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0, int32_t depth_multiplier = 1, int32_t filterQuantizationDim = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 3> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(filterData.data()), sizeof(T) * filterData.size())); buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(biasData.data()), sizeof(B) * biasData.size())); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto outputQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ outputQuantScale }), flatBufferBuilder.CreateVector({ outputQuantOffset })); auto filterQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector(filterScales), flatBufferBuilder.CreateVector(filterOffsets), tflite::QuantizationDetails_NONE, 0, filterQuantizationDim); auto biasQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector(biasScales), flatBufferBuilder.CreateVector(biasOffsets)); std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(filterTensorShape.data(), filterTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("filter"), filterQuantizationParameters); auto biasTensorType = ::tflite::TensorType_FLOAT32; if (tensorType == ::tflite::TensorType_INT8 || tensorType == ::tflite::TensorType_UINT8) { biasTensorType = ::tflite::TensorType_INT32; } tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(biasTensorShape.data(), biasTensorShape.size()), biasTensorType, 2, flatBufferBuilder.CreateString("bias"), biasQuantizationParameters); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), outputQuantizationParameters); tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_Conv3DOptions; flatbuffers::Offset operatorBuiltinOptions = CreateConv3DOptions(flatBufferBuilder, padding, strides[2], // Depth strides[0], // Width strides[1], // Height fused_activation_function, dilation[2], dilation[0], dilation[1]).Union(); // Create operator const std::vector operatorInputs{0, 1, 2}; const std::vector operatorOutputs{3}; flatbuffers::Offset convolutionOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1, 2}; const std::vector subgraphOutputs{3}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&convolutionOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Convolution 3d Operator Model"); // If using an operator with a code greater than 127 then the enum value should be passed as the fifth // parameter rather than the second like in other tests. flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, 0, 0, 1, tflite::BuiltinOperator_CONV_3D); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void Convolution3dTest(tflite::BuiltinOperator convolutionOperatorCode, tflite::TensorType tensorType, std::vector strides, std::vector dilation, tflite::Padding padding, tflite::ActivationFunctionType fused_activation_function, std::vector& backends, std::vector& inputShape, std::vector& filterShape, std::vector& outputShape, std::vector& inputValues, std::vector& filterValues, std::vector& expectedOutputValues, const std::vector& biasShape = {}, const std::vector& biasValues = {}, const std::vector biasScales = {1.0f}, const std::vector biasOffsets = {0}, const std::vector filterScales = {1.0f}, const std::vector filterOffsets = {0}, float outputQuantScale = 2.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0, int32_t depth_multiplier = 1, int32_t filterQuantizationDim = 3) { using namespace delegateTestInterpreter; std::vector modelBuffer; modelBuffer = CreateConv3dTfLiteModel(convolutionOperatorCode, tensorType, strides, dilation, padding, fused_activation_function, inputShape, filterShape, biasShape, outputShape, filterValues, biasValues, biasScales, biasOffsets, filterScales, filterOffsets, outputQuantScale, outputQuantOffset, quantScale, quantOffset, depth_multiplier, filterQuantizationDim); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); armnnDelegate::CompareData(expectedOutputValues.data(), armnnOutputValues.data(), expectedOutputValues.size(), 1); armnnDelegate::CompareData(expectedOutputValues.data(), tfLiteOutputValues.data(), expectedOutputValues.size(), 1); armnnDelegate::CompareData(tfLiteOutputValues.data(), armnnOutputValues.data(), expectedOutputValues.size(), 1); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } #endif template std::vector CreateTransposeConvTfLiteModel(tflite::TensorType tensorType, uint32_t strideX, uint32_t strideY, tflite::Padding padding, const std::vector & transposeTensorShape, const std::vector & filterTensorShape, const std::vector & inputTensorShape, const std::vector & outputTensorShape, const std::vector & transposeData, const std::vector & filterData, float filterScale = 1.0f, int filterOffset = 0, float outputQuantScale = 2.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 3> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(transposeData.data()), sizeof(int32_t) * transposeData.size())); buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(filterData.data()), sizeof(T) * filterData.size())); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto outputQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ outputQuantScale }), flatBufferBuilder.CreateVector({ outputQuantOffset })); auto filterQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ filterScale }), flatBufferBuilder.CreateVector({ filterOffset })); std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(transposeTensorShape.data(), transposeTensorShape.size()), tflite::TensorType_INT32, 1); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(filterTensorShape.data(), filterTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("filter"), filterQuantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), outputQuantizationParameters); tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_TransposeConvOptions; flatbuffers::Offset operatorBuiltinOptions = CreateTransposeConvOptions(flatBufferBuilder, padding, strideX, strideY).Union(); // create operator const std::vector operatorInputs{0, 1, 2}; const std::vector operatorOutputs{3}; flatbuffers::Offset convolutionOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1, 2}; const std::vector subgraphOutputs{3}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&convolutionOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: TransposeConv Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_TRANSPOSE_CONV); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void TransposeConvTest(std::vector& backends, tflite::TensorType tensorType, uint32_t strideX, uint32_t strideY, tflite::Padding padding, const std::vector & transposeTensorShape, const std::vector & filterTensorShape, const std::vector & inputTensorShape, const std::vector & outputTensorShape, const std::vector & transposeData, const std::vector & filterData, std::vector& inputValues, std::vector& expectedOutputValues, float filterScale = 1.0f, int filterOffset = 0, float outputQuantScale = 1.0f, int outputQuantOffset = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer; modelBuffer = CreateTransposeConvTfLiteModel(tensorType, strideX, strideY, padding, transposeTensorShape, filterTensorShape, inputTensorShape, outputTensorShape, transposeData, filterData, filterScale, filterOffset, outputQuantScale, outputQuantOffset, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 2) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 2) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/DelegateOptionsTest.cpp000066400000000000000000000363541446772241200220500ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "DelegateOptionsTestHelper.hpp" #include #include namespace armnnDelegate { TEST_SUITE("DelegateOptions") { TEST_CASE ("ArmnnDelegateOptimizerOptionsReduceFp32ToFp16") { std::stringstream ss; { StreamRedirector redirect(std::cout, ss.rdbuf()); std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; // Enable ReduceFp32ToFp16 armnn::OptimizerOptionsOpaque optimizerOptions(true, true, false, false); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); DelegateOptionTest(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } // ReduceFp32ToFp16 option is enabled CHECK(ss.str().find("convert_fp32_to_fp16") != std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") != std::string::npos); } TEST_CASE ("ArmnnDelegateOptimizerOptionsDebug") { std::stringstream ss; { StreamRedirector redirect(std::cout, ss.rdbuf()); std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; // Enable Debug armnn::OptimizerOptionsOpaque optimizerOptions(false, true, false, false); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); DelegateOptionTest(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } // Debug option triggered. CHECK(ss.str().find("layerGuid") != std::string::npos); CHECK(ss.str().find("layerName") != std::string::npos); CHECK(ss.str().find("outputSlot") != std::string::npos); CHECK(ss.str().find("shape") != std::string::npos); CHECK(ss.str().find("data") != std::string::npos); } TEST_CASE ("ArmnnDelegateOptimizerOptionsDebugFunction") { std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; // Enable debug with debug callback function armnn::OptimizerOptionsOpaque optimizerOptions(false, true, false, false); bool callback = false; auto mockCallback = [&](LayerGuid guid, unsigned int slotIndex, armnn::ITensorHandle* tensor) { armnn::IgnoreUnused(guid); armnn::IgnoreUnused(slotIndex); armnn::IgnoreUnused(tensor); callback = true; }; armnn::INetworkProperties networkProperties(false, armnn::MemorySource::Undefined, armnn::MemorySource::Undefined); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions, armnn::EmptyOptional(), armnn::Optional(mockCallback)); CHECK(!callback); DelegateOptionTest(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); // Check that the debug callback function was called. CHECK(callback); } TEST_CASE ("ArmnnDelegateOptimizerOptionsImport") { std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; armnn::OptimizerOptionsOpaque optimizerOptions(false, false, false, true); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); DelegateOptionTest(::tflite::TensorType_UINT8, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } TEST_CASE ("ArmnnDelegateStringParsingOptionDisableTfLiteRuntimeFallback") { std::stringstream stringStream; std::vector keys { "backends", "debug-data", "disable-tflite-runtime-fallback"}; std::vector values { "CpuRef", "1", "1"}; std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 0.1f, -2.1f, 3.0f, -4.6f }; std::vector expectedResult = { 1.0f, -2.0f, 3.0f, -4.0f }; // Create options_keys and options_values char array size_t num_options = keys.size(); std::unique_ptr options_keys = std::unique_ptr(new const char*[num_options + 1]); std::unique_ptr options_values = std::unique_ptr(new const char*[num_options + 1]); for (size_t i=0; i(::tflite::TensorType_FLOAT32, tensorShape, inputData, expectedResult, delegateOptions); CHECK(stringStream.str().find("TfLiteArmnnDelegate: There are unsupported operators in the model") != std::string::npos); } TEST_CASE ("ArmnnDelegateStringParsingOptionEnableTfLiteRuntimeFallback") { std::stringstream stringStream; std::vector keys { "backends", "debug-data", "disable-tflite-runtime-fallback"}; std::vector values { "CpuRef", "1", "0"}; std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 0.1f, -2.1f, 3.0f, -4.6f }; std::vector expectedResult = { 0.995004177f, -0.504846036f, -0.989992499f, -0.112152621f }; // Create options_keys and options_values char array size_t num_options = keys.size(); std::unique_ptr options_keys = std::unique_ptr(new const char*[num_options + 1]); std::unique_ptr options_values = std::unique_ptr(new const char*[num_options + 1]); for (size_t i=0; i(::tflite::TensorType_FLOAT32, tensorShape, inputData, expectedResult, delegateOptions); CHECK(stringStream.str().find("TfLiteArmnnDelegate: There are unsupported operators in the model") == std::string::npos); } } TEST_SUITE("DelegateOptions_CpuAccTests") { TEST_CASE ("ArmnnDelegateModelOptions_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; unsigned int numberOfThreads = 2; armnn::ModelOptions modelOptions; armnn::BackendOptions cpuAcc("CpuAcc", { { "FastMathEnabled", true }, { "NumberOfThreads", numberOfThreads } }); modelOptions.push_back(cpuAcc); armnn::OptimizerOptionsOpaque optimizerOptions(false, false, false, false, modelOptions, false); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); DelegateOptionTest(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } TEST_CASE ("ArmnnDelegateSerializeToDot") { const fs::path filename(fs::temp_directory_path() / "ArmnnDelegateSerializeToDot.dot"); if ( fs::exists(filename) ) { fs::remove(filename); } std::stringstream ss; { StreamRedirector redirect(std::cout, ss.rdbuf()); std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; armnn::OptimizerOptionsOpaque optimizerOptions(false, false, false, false); armnnDelegate::DelegateOptions delegateOptions(backends, optimizerOptions); // Enable serialize to dot by specifying the target file name. delegateOptions.SetSerializeToDot(filename); DelegateOptionTest(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } CHECK(fs::exists(filename)); // The file should have a size greater than 0 bytes. CHECK(fs::file_size(filename) > 0); // Clean up. fs::remove(filename); } void CreateFp16StringParsingTestRun(std::vector& keys, std::vector& values, std::stringstream& ss) { StreamRedirector redirect(std::cout, ss.rdbuf()); std::vector backends = { armnn::Compute::CpuRef }; std::vector tensorShape { 1, 2, 2, 1 }; std::vector inputData = { 1, 2, 3, 4 }; std::vector divData = { 2, 2, 3, 4 }; std::vector expectedResult = { 1, 2, 2, 2 }; // Create options_keys and options_values char array size_t num_options = keys.size(); std::unique_ptr options_keys = std::unique_ptr(new const char*[num_options + 1]); std::unique_ptr options_values = std::unique_ptr(new const char*[num_options + 1]); for (size_t i=0; i(::tflite::TensorType_FLOAT32, tensorShape, inputData, inputData, divData, expectedResult, delegateOptions); } TEST_CASE ("ArmnnDelegateStringParsingOptionReduceFp32ToFp16") { SUBCASE("Fp16=1") { std::stringstream ss; std::vector keys { "backends", "debug-data", "reduce-fp32-to-fp16", "logging-severity"}; std::vector values { "CpuRef", "1", "1", "info"}; CreateFp16StringParsingTestRun(keys, values, ss); CHECK(ss.str().find("convert_fp32_to_fp16") != std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") != std::string::npos); } SUBCASE("Fp16=true") { std::stringstream ss; std::vector keys { "backends", "debug-data", "reduce-fp32-to-fp16"}; std::vector values { "CpuRef", "TRUE", "true"}; CreateFp16StringParsingTestRun(keys, values, ss); CHECK(ss.str().find("convert_fp32_to_fp16") != std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") != std::string::npos); } SUBCASE("Fp16=True") { std::stringstream ss; std::vector keys { "backends", "debug-data", "reduce-fp32-to-fp16"}; std::vector values { "CpuRef", "true", "True"}; CreateFp16StringParsingTestRun(keys, values, ss); CHECK(ss.str().find("convert_fp32_to_fp16") != std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") != std::string::npos); } SUBCASE("Fp16=0") { std::stringstream ss; std::vector keys { "backends", "debug-data", "reduce-fp32-to-fp16"}; std::vector values { "CpuRef", "true", "0"}; CreateFp16StringParsingTestRun(keys, values, ss); CHECK(ss.str().find("convert_fp32_to_fp16") == std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") == std::string::npos); } SUBCASE("Fp16=false") { std::stringstream ss; std::vector keys { "backends", "debug-data", "reduce-fp32-to-fp16"}; std::vector values { "CpuRef", "1", "false"}; CreateFp16StringParsingTestRun(keys, values, ss); CHECK(ss.str().find("convert_fp32_to_fp16") == std::string::npos); CHECK(ss.str().find("convert_fp16_to_fp32") == std::string::npos); } } } } // namespace armnnDelegate armnn-23.08/delegate/test/DelegateOptionsTestHelper.hpp000066400000000000000000000364401446772241200232110ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { struct StreamRedirector { public: StreamRedirector(std::ostream &stream, std::streambuf *newStreamBuffer) : m_Stream(stream), m_BackupBuffer(m_Stream.rdbuf(newStreamBuffer)) {} ~StreamRedirector() { m_Stream.rdbuf(m_BackupBuffer); } private: std::ostream &m_Stream; std::streambuf *m_BackupBuffer; }; std::vector CreateAddDivTfLiteModel(tflite::TensorType tensorType, const std::vector& tensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 5> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("input_1"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("input_2"), quantizationParameters); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 4, flatBufferBuilder.CreateString("add"), quantizationParameters); tensors[4] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 5, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions addBuiltinOptionsType = tflite::BuiltinOptions_AddOptions; flatbuffers::Offset addBuiltinOptions = CreateAddOptions(flatBufferBuilder, ActivationFunctionType_NONE).Union(); tflite::BuiltinOptions divBuiltinOptionsType = tflite::BuiltinOptions_DivOptions; flatbuffers::Offset divBuiltinOptions = CreateAddOptions(flatBufferBuilder, ActivationFunctionType_NONE).Union(); std::array, 2> operators; const std::vector addInputs{0, 1}; const std::vector addOutputs{3}; operators[0] = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(addInputs.data(), addInputs.size()), flatBufferBuilder.CreateVector(addOutputs.data(), addOutputs.size()), addBuiltinOptionsType, addBuiltinOptions); const std::vector divInputs{3, 2}; const std::vector divOutputs{4}; operators[1] = CreateOperator(flatBufferBuilder, 1, flatBufferBuilder.CreateVector(divInputs.data(), divInputs.size()), flatBufferBuilder.CreateVector(divOutputs.data(), divOutputs.size()), divBuiltinOptionsType, divBuiltinOptions); const std::vector subgraphInputs{0, 1, 2}; const std::vector subgraphOutputs{4}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(operators.data(), operators.size())); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Add and Div Operator Model"); std::array, 2> codes; codes[0] = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_ADD); codes[1] = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_DIV); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(codes.data(), codes.size()), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } std::vector CreateCosTfLiteModel(tflite::TensorType tensorType, const std::vector & tensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), quantizationParameters); const std::vector operatorInputs({0}); const std::vector operatorOutputs({1}); flatbuffers::Offset ceilOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_NONE); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: CEIL Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_COS); const std::vector subgraphInputs({0}); const std::vector subgraphOutputs({1}); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&ceilOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void DelegateOptionTest(tflite::TensorType tensorType, std::vector& tensorShape, std::vector& input0Values, std::vector& input1Values, std::vector& input2Values, std::vector& expectedOutputValues, const armnnDelegate::DelegateOptions& delegateOptions, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateAddDivTfLiteModel(tensorType, tensorShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input2Values, 2) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, delegateOptions); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input2Values, 2) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, tensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } template void DelegateOptionNoFallbackTest(tflite::TensorType tensorType, std::vector& tensorShape, std::vector& inputValues, std::vector& expectedOutputValues, const armnnDelegate::DelegateOptions& delegateOptions, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateCosTfLiteModel(tensorType, tensorShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); tfLiteInterpreter.Cleanup(); try { auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, delegateOptions); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnInterpreter.Cleanup(); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, tensorShape); } catch (const armnn::Exception& e) { // Forward the exception message to std::cout std::cout << e.what() << std::endl; } } } // anonymous namespacearmnn-23.08/delegate/test/DepthwiseConvolution2dTest.cpp000066400000000000000000000242611446772241200233760ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ConvolutionTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void DepthwiseConv2dValidReluFp32Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 2, 2 }; std::vector filterShape { 1, 2, 2, 4 }; std::vector biasShape { 4 }; std::vector outputShape { 1, 2, 1, 4 }; static std::vector inputValues = { 1, 2, 7, 8, 3, 4, 9, 10, 5, 6, 11, 12 }; std::vector filterValues = { 1, 2, 3, 4, -9, 10, -11, 12, 5, 6, 7, 8, 13, -14, 15, -16 }; std::vector biasValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 71, 0, 99, 0, 91, 0, 127, 0 }; tflite::Padding padding = tflite::Padding_VALID; int32_t depth_multiplier = 2; ConvolutionTest(tflite::BuiltinOperator_DEPTHWISE_CONV_2D, ::tflite::TensorType_FLOAT32, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_RELU, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues, {1.0f}, // biasScale {0}, // biasOffset {1.0f}, // filterScale {0}, // filterOffsets 2.0f, // outputQuantScale 0, // outputQuantOffset 1.0f, // quantScale 0, // quantOffset depth_multiplier); } void DepthwiseConv2dSameUint8Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 3, 1 }; std::vector filterShape { 1, 3, 3, 1 }; std::vector biasShape { 1 } ; std::vector outputShape { 1, 3, 3, 1 }; static std::vector inputValues = { 0, 1, 2, 3, 4, 5, 6, 7, 8 }; std::vector filterValues = { 9, 8, 7, 6, 5, 4, 3, 2, 1 }; std::vector biasValues = { 10 }; std::vector expectedOutputValues = { 12, 23, 24, // ( 14+10)/2, ( 35+10)/2, ( 38+10)/2, 34, 65, 61, // ( 57+10)/2, (120+10)/2, (111+10)/2, 60, 104, 84 // (110+10)/2, (197+10)/2, (158+10)/2 }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_DEPTHWISE_CONV_2D, ::tflite::TensorType_UINT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues); } void DepthwiseConv2dSameInt8PerChannelTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 4, 4, 4 }; std::vector filterShape { 1, 2, 2, 16 }; std::vector biasShape {16} ; std::vector outputShape { 1, 4, 4, 16 }; static std::vector inputValues = { 3,3,3,4, 4,4,0,0, 0,3,4,3, 0,2,2,3, 3,0,3,0, 0,3,2,1, 4,1,2,2, 0,0,0,4, 3,2,2,2, 2,1,0,4, 4,3,2,4, 3,2,0,0, 4,1,4,4, 1,0,4,3, 3,2,0,3, 1,1,0,2 }; std::vector filterValues = { 12,20,10, 3, 2,24, 9,10, 5,16,30,12, 3,10, 4,32, 8, 0,30, 3, 0,16,12,15,20,12, 0, 3, 9,20, 8, 8, 12,15,20, 0, 0, 0, 3,15,15, 8,40,12, 9, 5, 2,24, 4, 0, 0, 6, 6, 0, 3, 5,20, 8,20, 3, 6,15, 4, 0 }; std::vector filterScales = { 0.25, 0.2, 0.1, 0.3333333333, 0.5, 0.125, 0.33333333, 0.2, 0.2, 0.25, 0.1, 0.333333333, 0.3333333333, 0.2, 0.5, 0.125 }; int32_t filterQuantizationDim = 3; int32_t depth_multiplier = 4; std::vector biasValues = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; float inputScale = 1.0f; std::vector biasScales {}; std::vector biasOffsets {}; std::vector filterOffsets {}; for (const auto& filterScale: filterScales) { biasScales.push_back(inputScale * filterScale); // filter and bias offset always needs to be zero for per channel. We don't support anything else biasOffsets.push_back(0); filterOffsets.push_back(0); } std::vector expectedOutputValues = { 26,21,21, 7,12,17,28,21,20,22,25,26, 6,11,10,16, 16,16, 4,12, 7,18,28,27,30,20,12,14,16,19,17, 6, 12,12, 8, 0, 3,13,18,15,18,26,20,26,26,32,28,21, 0, 0, 0, 0, 2, 6, 6, 4, 2, 8, 6, 8,15,10,10,24, 20,21, 9, 7, 3, 6,15,16,17,22,17,22,17,18,14, 7, 18, 6,16,12,12,11,17,15,18,18,10,12,27,26,22,18, 27,28,12,10, 7, 3, 8,13, 8,12,14,16,26,24,24,24, 9, 9, 6, 0, 0, 0, 2, 6, 0, 0, 0, 0, 4, 8, 8,16, 26,24,17, 7, 2, 8,11,10,30,24,30,28,32,33,30,24, 20,11,16,12, 7, 9,17,13,20,14,16,18,31,36,33,29, 28,25,19, 9, 6,13,20,19, 2, 8, 6, 8,17,17,15,25, 12,15, 5, 3, 2, 6, 7, 7, 0, 0, 0, 0, 6, 2, 2, 6, 14,16, 7, 5, 1, 3, 3, 2,20,28,12,20,13,20,20,19, 9, 4,10, 4, 0, 4, 8, 6, 4,16,12,16,12,18,18,15, 11,12, 6, 4, 2, 8,10, 7, 0, 0, 0, 0, 9,14,14,14, 3, 4, 1, 1, 1, 3, 3, 2, 0, 0, 0, 0, 2, 4, 4, 8 }; tflite::Padding padding = tflite::Padding_SAME; ConvolutionTest(tflite::BuiltinOperator_DEPTHWISE_CONV_2D, ::tflite::TensorType_INT8, 1, // strideX 1, // strideY 1, // dilationX 1, // dilationY padding, tflite::ActivationFunctionType_NONE, backends, inputShape, filterShape, outputShape, inputValues, filterValues, expectedOutputValues, biasShape, biasValues, biasScales, biasOffsets, filterScales, filterOffsets, 1.0f, 0, inputScale, 0, depth_multiplier, filterQuantizationDim); } TEST_SUITE("DepthwiseConv2d_CpuRef_Tests") { TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; DepthwiseConv2dValidReluFp32Test(backends); } TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; DepthwiseConv2dSameUint8Test(backends); } TEST_CASE ("DepthwiseConv2d_Same_Int8_PerChannelQuantization_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; DepthwiseConv2dSameInt8PerChannelTest(backends); } }//End of TEST_SUITE("DepthwiseConv2d_CpuRef_Tests") TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests") { TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; DepthwiseConv2dValidReluFp32Test(backends); } TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; DepthwiseConv2dSameUint8Test(backends); } }//End of TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests") TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests") { TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; DepthwiseConv2dValidReluFp32Test(backends); } TEST_CASE ("DepthwiseConv2d_Same_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; DepthwiseConv2dSameUint8Test(backends); } }//End of TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests") } // namespace armnnDelegatearmnn-23.08/delegate/test/ElementwiseBinaryTest.cpp000066400000000000000000001077431446772241200224110ustar00rootroot00000000000000// // Copyright © 2020-2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ElementwiseBinaryTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void AddFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 3 }; std::vector input1Shape { 2, 2, 2, 3 }; std::vector expectedOutputShape { 2, 2, 2, 3 }; std::vector input0Values = { 0.0f, 2.0f, 1.0f, 0.2f, 1.0f, 2.0f, 1.0f, 2.0f, 1.0f, 0.2f, 1.0f, 2.0f, 0.0f, 2.0f, 1.0f, 4.2f, 1.0f, 2.0f, 0.0f, 0.0f, 1.0f, 0.2f, 1.0f, 2.0f, }; std::vector input1Values = { 1.0f, 2.0f, 1.0f, 0.0f, 1.0f, 2.0f, 1.0f, 2.0f, -2.0f, 0.2f, 1.0f, 2.0f, 0.0f, 2.0f, 1.0f, 4.2f, 0.0f, -3.0f, 0.0f, 0.0f, 1.0f, 0.7f, 1.0f, 5.0f, }; std::vector expectedOutputValues = { 1.0f, 4.0f, 2.0f, 0.2f, 2.0f, 4.0f, 2.0f, 4.0f, -1.0f, 0.4f, 2.0f, 4.0f, 0.0f, 4.0f, 2.0f, 8.4f, 1.0f, -1.0f, 0.0f, 0.0f, 2.0f, 0.9f, 2.0f, 7.0f, }; ElementwiseBinaryTest(tflite::BuiltinOperator_ADD, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void AddBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 3, 2, 1 }; std::vector input1Shape { 1, 1, 2, 3 }; std::vector expectedOutputShape { 1, 3, 2, 3 }; std::vector input0Values { 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, }; std::vector input1Values { 0.5f, 1.5f, 2.5f, 3.5f, 4.5f, 5.5f, }; // Set output data std::vector expectedOutputValues { 0.5f, 1.5f, 2.5f, 4.5f, 5.5f, 6.5f, 2.5f, 3.5f, 4.5f, 6.5f, 7.5f, 8.5f, 4.5f, 5.5f, 6.5f, 8.5f, 9.5f, 10.5f, }; ElementwiseBinaryTest(tflite::BuiltinOperator_ADD, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void AddConstInputTest(std::vector& backends) { std::vector input0Shape { 1, 3, 2, 1 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 3, 2, 1 }; std::vector input0Values { 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, }; std::vector input1Values { 0.5f }; // Set output data std::vector expectedOutputValues { 0.5f, 1.5f, 2.5f, 3.5f, 4.5f, 5.5f, }; ElementwiseBinaryTest(tflite::BuiltinOperator_ADD, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 1.0f, 0, true); } void AddActivationTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values { 4.0f, 0.8f, 0.7f, -0.8f }; std::vector input1Values { 0.7f, -1.2f, 0.8f, 0.5f }; std::vector expectedOutputValues { 4.7f, 0.0f, 1.5f, 0.0f }; ElementwiseBinaryTest(tflite::BuiltinOperator_ADD, tflite::ActivationFunctionType_RELU, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void AddUint8Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 2, 2, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values = { 63, 35, 77, 70, 56, 112, 203, 28, 252, 168, 245, 91 }; std::vector input1Values = { 21, 7, 175, 231, 175, 210, 126, 161, 63, 21, 105, 126 }; std::vector expectedOutputValues = { 81, 39, 249, 255, 228, 255, 255, 186, 255, 186, 255, 214, }; ElementwiseBinaryTest(tflite::BuiltinOperator_ADD, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 7.0f, 3); } void DivFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 2.f, 2.f, 2.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f, 5.f, 5.f, 5.f, 5.f }; std::vector input1Values = { 1.f, 1.f, 1.f, 1.f, 2.f, 2.f, 2.f, 2.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f }; std::vector expectedOutputValues = { 2.f, 2.f, 2.f, 2.f, 1.50f, 1.50f, 1.50f, 1.50f, 1.f, 1.f, 1.f, 1.f, 1.25f, 1.25f, 1.25f, 1.25f }; ElementwiseBinaryTest(tflite::BuiltinOperator_DIV, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void DivBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2, 2 }; std::vector input0Values = { 2, 4, 6, 8, 10, 12, 14, 16 }; std::vector input1Values = { 2 }; std::vector expectedOutputValues = { 1, 2, 3, 4, 5, 6, 7, 8 }; ElementwiseBinaryTest(tflite::BuiltinOperator_DIV, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void DivUint8Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5 }; std::vector input1Values = { 1, 1, 1, 1, 2, 2, 2, 2, 4, 4, 4, 4, 4, 4, 4, 4 }; std::vector expectedOutputValues = { 8, 8, 8, 8, 6, 6, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 }; ElementwiseBinaryTest(tflite::BuiltinOperator_DIV, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 0.25f, 0); } void FloorDivFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { -37.5f, -15.2f, -8.76f, -2.0f, -2.6f, -1.0f, -0.8f, 0.0f, 4.0f, 1.6f, 2.0f, 5.2f, 6.0f, 35.04f, 60.8f, 150.0f }; std::vector input1Values = { 1.f, 1.f, 1.f, 1.f, 2.f, 2.f, 2.f, 2.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f, 4.f }; std::vector expectedOutputValues = { -38.0f, -16.0f, -9.0f, -2.0f, -2.0f, -1.0f, -1.0f, 0.0f, 1.0f, 0.0f, 0.0f, 1.0f, 1.0f, 8.0f, 15.0f, 37.0f }; ElementwiseBinaryTest(tflite::BuiltinOperator_FLOOR_DIV, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MaxFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1.f, 1.f, 5.f, 1.f, 2.f, 2.f, 7.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f }; std::vector input1Values = { 2.f, 2.f, 2.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f, 5.f, 5.f, 5.f, 5.f }; std::vector expectedOutputValues = { 2.f, 2.f, 5.f, 2.f, 3.f, 3.f, 7.f, 3.f, 4.f, 4.f, 4.f, 4.f, 5.f, 5.f, 5.f, 5.f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MAXIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MaxBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2, 2 }; std::vector input0Values = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f }; std::vector input1Values = { 4.f }; std::vector expectedOutputValues = { 4.f, 4.f, 4.f, 4.f, 5.f, 6.f, 7.f, 8.f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MAXIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MaxUint8Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1, 1, 1, 1, 7, 8, 9, 9, 3, 3, 3, 3, 4, 4, 4, 4 }; std::vector input1Values = { 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5 }; std::vector expectedOutputValues = { 2, 2, 2, 2, 7, 8, 9, 9, 4, 4, 4, 4, 5, 5, 5, 5 }; ElementwiseBinaryTest(tflite::BuiltinOperator_MAXIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 1.0f, 0); } void MinFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1.f, 1.f, 5.f, 1.f, 2.f, 2.f, 7.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f }; std::vector input1Values = { 2.f, 2.f, 2.f, 2.f, 3.f, 3.f, 3.f, 3.f, 1.f, 1.f, 1.f, 1.f, 5.f, 5.f, 5.f, 5.f }; std::vector expectedOutputValues = { 1.f, 1.f, 2.f, 1.f, 2.f, 2.f, 3.f, 2.f, 1.f, 1.f, 1.f, 1.f, 4.f, 4.f, 4.f, 4.f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MINIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MinBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2, 2 }; std::vector input0Values = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f }; std::vector input1Values = { 4.f }; std::vector expectedOutputValues = { 1.f, 2.f, 3.f, 4.f, 4.f, 4.f, 4.f, 4.f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MINIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MinUint8Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1, 1, 1, 1, 7, 8, 9, 9, 3, 3, 3, 3, 4, 4, 4, 4 }; std::vector input1Values = { 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5 }; std::vector expectedOutputValues = { 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4 }; ElementwiseBinaryTest(tflite::BuiltinOperator_MINIMUM, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 1.0f, 0); } void MulFP32Test(std::vector& backends) { std::vector input0Shape { 2, 2, 2, 2 }; std::vector input1Shape { 2, 2, 2, 2 }; std::vector expectedOutputShape { 2, 2, 2, 2 }; std::vector input0Values = { 1.f, 1.f, 1.f, 1.f, 2.f, 2.f, 2.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f }; std::vector input1Values = { 2.f, 2.f, 2.f, 2.f, 3.f, 3.f, 3.f, 3.f, 4.f, 4.f, 4.f, 4.f, 5.f, 5.f, 5.f, 5.f }; std::vector expectedOutputValues = { 2.f, 2.f, 2.f, 2.f, 6.f, 6.f, 6.f, 6.f, 12.f, 12.f, 12.f, 12.f, 20.f, 20.f, 20.f, 20.f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MUL, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MulBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2, 2 }; std::vector input0Values = { 2, 4, 6, 8, 10, 12, 14, 16 }; std::vector input1Values = { 2 }; std::vector expectedOutputValues = { 4, 8, 12, 16, 20, 24, 28, 32 }; ElementwiseBinaryTest(tflite::BuiltinOperator_MUL, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void MulUint8Test(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 3 }; std::vector input1Shape { 1, 1, 1, 3 }; std::vector expectedOutputShape { 1, 2, 2, 3 }; std::vector input0Values = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }; std::vector input1Values = { 1, 2, 3 }; std::vector expectedOutputValues = { 1, 4, 9, 4, 10, 18, 7, 16, 27, 10, 22, 36 }; ElementwiseBinaryTest(tflite::BuiltinOperator_MUL, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 1.0f, 0); } void MulActivationTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2, 1 }; std::vector input1Shape { 1, 2, 2, 1 }; std::vector expectedOutputShape { 1, 2, 2, 1 }; std::vector input0Values { 4.0f, 0.0f, 1.0f, 0.5f }; std::vector input1Values { -2.0f, -1.2f, 2.5f, 2.0f }; std::vector expectedOutputValues { 0.0f, 0.0f, 2.5f, 1.0f }; ElementwiseBinaryTest(tflite::BuiltinOperator_MUL, tflite::ActivationFunctionType_RELU, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void SubFP32Test(std::vector& backends) { std::vector input0Shape { 1, 1, 2, 2 }; std::vector input1Shape { 1, 1, 2, 2 }; std::vector expectedOutputShape { 1, 1, 2, 2 }; std::vector input0Values = { 1, 3, 3, -7 }; std::vector input1Values = { 1, -1, 0, -2 }; std::vector expectedOutputValues = { 0, 4, 3, -5 }; ElementwiseBinaryTest(tflite::BuiltinOperator_SUB, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void PowerFP32Test(std::vector& backends) { std::vector input0Shape { 1, 1, 2, 2 }; std::vector input1Shape { 1, 1, 2, 2 }; std::vector expectedOutputShape { 1, 1, 2, 2 }; std::vector input0Values = { 1, 3, 3, -7 }; std::vector input1Values = { 1, 1, 0, 2 }; std::vector expectedOutputValues = { 1, 3, 1, 49 }; ElementwiseBinaryTest(tflite::BuiltinOperator_POW, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void SqDiffFP32Test(std::vector& backends) { std::vector input0Shape { 1, 1, 2, 2 }; std::vector input1Shape { 1, 1, 2, 2 }; std::vector expectedOutputShape { 1, 1, 2, 2 }; std::vector input0Values = { 1, 3, 3, -7 }; std::vector input1Values = { 1, -1, 0, -2 }; std::vector expectedOutputValues = { 0, 16, 9, 25 }; ElementwiseBinaryTest(tflite::BuiltinOperator_SQUARED_DIFFERENCE, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void SubBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 1, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 1, 2, 2 }; std::vector input0Values = { 2, 3, 4, 5}; std::vector input1Values = { 10 }; std::vector expectedOutputValues = { -8, -7, -6, -5 }; ElementwiseBinaryTest(tflite::BuiltinOperator_SUB, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void SubUint8Test(std::vector& backends) { std::vector input0Shape { 1, 1, 2, 2 }; std::vector input1Shape { 1, 1, 1, 1 }; std::vector expectedOutputShape { 1, 1, 2, 2 }; std::vector input0Values = { 10, 12, 14, 16 }; std::vector input1Values = { 2 }; std::vector expectedOutputValues = { 8, 10, 12, 14 }; ElementwiseBinaryTest(tflite::BuiltinOperator_SUB, tflite::ActivationFunctionType_NONE, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, 1.0f, 0); } TEST_SUITE("ElementwiseBinary_GpuAccTests") { TEST_CASE ("ADD_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AddFP32Test(backends); } TEST_CASE ("ADD_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AddBroadcastTest(backends); } TEST_CASE ("ADD_Activation_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AddActivationTest(backends); } TEST_CASE ("ADD_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AddUint8Test(backends); } TEST_CASE ("DIV_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DivFP32Test(backends); } TEST_CASE ("DIV_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DivBroadcastTest(backends); } TEST_CASE ("FLOORDIV_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; FloorDivFP32Test(backends); } TEST_CASE ("MAX_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxFP32Test(backends); } TEST_CASE ("MAX_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxBroadcastTest(backends); } TEST_CASE ("MAX_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxUint8Test(backends); } TEST_CASE ("MIN_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MinFP32Test(backends); } TEST_CASE ("MIN_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MinBroadcastTest(backends); } TEST_CASE ("MIN_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MinUint8Test(backends); } TEST_CASE ("MUL_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MulFP32Test(backends); } TEST_CASE ("MUL_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MulBroadcastTest(backends); } TEST_CASE ("MUL_Activation_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MulActivationTest(backends); } TEST_CASE ("MUL_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MulUint8Test(backends); } TEST_CASE ("SUB_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SubFP32Test(backends); } TEST_CASE ("SUB_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SubBroadcastTest(backends); } TEST_CASE ("SUB_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SubUint8Test(backends); } } //TEST_SUITE("ElementwiseBinary_GpuAccTests") TEST_SUITE("ElementwiseBinary_CpuAccTests") { TEST_CASE ("ADD_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AddFP32Test(backends); } TEST_CASE ("ADD_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AddBroadcastTest(backends); } TEST_CASE ("ADD_Activation_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AddActivationTest(backends); } TEST_CASE ("ADD_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AddUint8Test(backends); } TEST_CASE ("DIV_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DivFP32Test(backends); } TEST_CASE ("DIV_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DivBroadcastTest(backends); } TEST_CASE ("FLOORDIV_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; FloorDivFP32Test(backends); } TEST_CASE ("MAX_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxFP32Test(backends); } TEST_CASE ("MAX_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxBroadcastTest(backends); } TEST_CASE ("MAX_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxUint8Test(backends); } TEST_CASE ("MIN_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MinFP32Test(backends); } TEST_CASE ("MIN_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MinBroadcastTest(backends); } TEST_CASE ("MIN_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MinUint8Test(backends); } TEST_CASE ("MUL_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MulFP32Test(backends); } TEST_CASE ("MUL_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MulBroadcastTest(backends); } TEST_CASE ("MUL_Actiation_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MulActivationTest(backends); } TEST_CASE ("MUL_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MulUint8Test(backends); } TEST_CASE ("SUB_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SubFP32Test(backends); } TEST_CASE ("SUB_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SubBroadcastTest(backends); } TEST_CASE ("SUB_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SubUint8Test(backends); } } // TEST_SUITE("ElementwiseBinary_CpuAccTests") TEST_SUITE("ElementwiseBinary_CpuRefTests") { TEST_CASE ("ADD_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AddFP32Test(backends); } TEST_CASE ("ADD_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AddBroadcastTest(backends); } TEST_CASE ("ADD_Constant_Input_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AddConstInputTest(backends); } TEST_CASE ("ADD_Activation_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AddActivationTest(backends); } TEST_CASE ("ADD_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AddUint8Test(backends); } TEST_CASE ("DIV_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DivFP32Test(backends); } TEST_CASE ("DIV_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DivBroadcastTest(backends); } TEST_CASE ("FLOORDIV_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FloorDivFP32Test(backends); } TEST_CASE ("DIV_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DivUint8Test(backends); } TEST_CASE ("MAX_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxFP32Test(backends); } TEST_CASE ("MAX_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxBroadcastTest(backends); } TEST_CASE ("MAX_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxUint8Test(backends); } TEST_CASE ("MIN_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MinFP32Test(backends); } TEST_CASE ("MIN_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MinBroadcastTest(backends); } TEST_CASE ("MIN_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MinUint8Test(backends); } TEST_CASE ("MUL_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MulFP32Test(backends); } TEST_CASE ("MUL_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MulBroadcastTest(backends); } TEST_CASE ("MUL_Actiation_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MulActivationTest(backends); } TEST_CASE ("MUL_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MulUint8Test(backends); } TEST_CASE ("SUB_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SubFP32Test(backends); } TEST_CASE ("SUB_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SubBroadcastTest(backends); } TEST_CASE ("SUB_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SubUint8Test(backends); } TEST_CASE ("SqDiffFP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SqDiffFP32Test(backends); } TEST_CASE ("PowerFP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PowerFP32Test(backends); } } // TEST_SUITE("ElementwiseBinary_CpuRefTests") } // namespace armnnDelegate armnn-23.08/delegate/test/ElementwiseBinaryTestHelper.hpp000066400000000000000000000262671446772241200235570ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreateElementwiseBinaryTfLiteModel(tflite::BuiltinOperator binaryOperatorCode, tflite::ActivationFunctionType activationType, tflite::TensorType tensorType, const std::vector & input0TensorShape, const std::vector & input1TensorShape, const std::vector & outputTensorShape, std::vector& input1Values, bool constantInput = false, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); if (constantInput) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(input1Values.data()), sizeof(T) * input1Values.size()))); } else { buffers.push_back(CreateBuffer(flatBufferBuilder)); } buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input1TensorShape.data(), input1TensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("input_1"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOptions = 0; switch (binaryOperatorCode) { case BuiltinOperator_ADD: { operatorBuiltinOptionsType = BuiltinOptions_AddOptions; operatorBuiltinOptions = CreateAddOptions(flatBufferBuilder, activationType).Union(); break; } case BuiltinOperator_DIV: { operatorBuiltinOptionsType = BuiltinOptions_DivOptions; operatorBuiltinOptions = CreateDivOptions(flatBufferBuilder, activationType).Union(); break; } case BuiltinOperator_MAXIMUM: { operatorBuiltinOptionsType = BuiltinOptions_MaximumMinimumOptions; operatorBuiltinOptions = CreateMaximumMinimumOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_MINIMUM: { operatorBuiltinOptionsType = BuiltinOptions_MaximumMinimumOptions; operatorBuiltinOptions = CreateMaximumMinimumOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_MUL: { operatorBuiltinOptionsType = BuiltinOptions_MulOptions; operatorBuiltinOptions = CreateMulOptions(flatBufferBuilder, activationType).Union(); break; } case BuiltinOperator_SUB: { operatorBuiltinOptionsType = BuiltinOptions_SubOptions; operatorBuiltinOptions = CreateSubOptions(flatBufferBuilder, activationType).Union(); break; } case BuiltinOperator_POW: { operatorBuiltinOptionsType = BuiltinOptions_PowOptions; operatorBuiltinOptions = CreatePowOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_SQUARED_DIFFERENCE: { operatorBuiltinOptionsType = BuiltinOptions_SquaredDifferenceOptions; operatorBuiltinOptions = CreateSquaredDifferenceOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_FLOOR_DIV: { operatorBuiltinOptionsType = tflite::BuiltinOptions_FloorDivOptions; operatorBuiltinOptions = CreateSubOptions(flatBufferBuilder, activationType).Union(); break; } default: break; } const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset elementwiseBinaryOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&elementwiseBinaryOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Elementwise Binary Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, binaryOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ElementwiseBinaryTest(tflite::BuiltinOperator binaryOperatorCode, tflite::ActivationFunctionType activationType, tflite::TensorType tensorType, std::vector& backends, std::vector& input0Shape, std::vector& input1Shape, std::vector& outputShape, std::vector& input0Values, std::vector& input1Values, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0, bool constantInput = false) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateElementwiseBinaryTfLiteModel(binaryOperatorCode, activationType, tensorType, input0Shape, input1Shape, outputShape, input1Values, constantInput, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ElementwiseUnaryTest.cpp000066400000000000000000000271511446772241200222550ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ElementwiseUnaryTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { TEST_SUITE("ElementwiseUnary_GpuAccTests") { TEST_CASE ("Abs_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { -0.1f, -0.2f, -0.3f, 0.1f, 0.2f, 0.3f }; // Calculate output data std::vector expectedOutputValues(inputValues.size()); for (unsigned int i = 0; i < inputValues.size(); ++i) { expectedOutputValues[i] = std::abs(inputValues[i]); } ElementwiseUnaryFP32Test(tflite::BuiltinOperator_ABS, backends, inputValues, expectedOutputValues); } TEST_CASE ("Exp_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { 5.0f, 4.0f, 3.0f, 2.0f, 1.0f, 1.1f }; // Set output data std::vector expectedOutputValues { 148.413159102577f, 54.598150033144f, 20.085536923188f, 7.389056098931f, 2.718281828459f, 3.004166023946f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } TEST_CASE ("Log_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { 1.0f, 1.0f, 2.0f, 3.0f, 4.0f, 2.71828f }; // Set output data std::vector expectedOutputValues { 0.f, 0.f, 0.69314718056f, 1.09861228867f, 1.38629436112f, 0.99999932734f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Neg_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { 1.f, 0.f, 3.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { -1.f, 0.f, -3.f, -25.f, -64.f, -100.f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_NEG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Rsqrt_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { 1.f, 4.f, 16.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { 1.f, 0.5f, 0.25f, 0.2f, 0.125f, 0.1f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_RSQRT, backends, inputValues, expectedOutputValues); } TEST_CASE ("Sin_Float32_GpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::GpuAcc }; // Set input data std::vector inputValues { 0.0f, 1.0f, 16.0f, 0.5f, 36.0f, -1.f }; // Set output data std::vector expectedOutputValues { 0.0f, 0.8414709848f, -0.28790331666f, 0.4794255386f, -0.99177885344f, -0.8414709848f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); } } // TEST_SUITE("ElementwiseUnary_GpuAccTests") TEST_SUITE("ElementwiseUnary_CpuAccTests") { TEST_CASE ("Abs_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { -0.1f, -0.2f, -0.3f, 0.1f, 0.2f, 0.3f }; // Calculate output data std::vector expectedOutputValues(inputValues.size()); for (unsigned int i = 0; i < inputValues.size(); ++i) { expectedOutputValues[i] = std::abs(inputValues[i]); } ElementwiseUnaryFP32Test(tflite::BuiltinOperator_ABS, backends, inputValues, expectedOutputValues); } TEST_CASE ("Exp_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { 5.0f, 4.0f, 3.0f, 2.0f, 1.0f, 1.1f }; // Set output data std::vector expectedOutputValues { 148.413159102577f, 54.598150033144f, 20.085536923188f, 7.389056098931f, 2.718281828459f, 3.004166023946f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } TEST_CASE ("Log_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { 1.0f, 1.0f, 2.0f, 3.0f, 4.0f, 2.71828f }; // Set output data std::vector expectedOutputValues { 0.f, 0.f, 0.69314718056f, 1.09861228867f, 1.38629436112f, 0.99999932734f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Neg_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { 1.f, 0.f, 3.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { -1.f, 0.f, -3.f, -25.f, -64.f, -100.f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_NEG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Rsqrt_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { 1.f, 4.f, 16.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { 1.f, 0.5f, 0.25f, 0.2f, 0.125f, 0.1f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_RSQRT, backends, inputValues, expectedOutputValues); } TEST_CASE ("Sin_Float32_CpuAcc_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuAcc }; // Set input data std::vector inputValues { 0.0f, 1.0f, 16.0f, 0.5f, 36.0f, -1.f }; // Set output data std::vector expectedOutputValues { 0.0f, 0.8414709848f, -0.28790331666f, 0.4794255386f, -0.99177885344f, -0.8414709848f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); } } // TEST_SUITE("ElementwiseUnary_CpuAccTests") TEST_SUITE("ElementwiseUnary_CpuRefTests") { TEST_CASE ("Abs_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { -0.1f, -0.2f, -0.3f, 0.1f, 0.2f, 0.3f }; // Calculate output data std::vector expectedOutputValues(inputValues.size()); for (unsigned int i = 0; i < inputValues.size(); ++i) { expectedOutputValues[i] = std::abs(inputValues[i]); } ElementwiseUnaryFP32Test(tflite::BuiltinOperator_ABS, backends, inputValues, expectedOutputValues); } TEST_CASE ("Ceil_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 0.0f, 1.1f, -16.1f, 0.5f, -0.5f, -1.3f }; // Set output data std::vector expectedOutputValues { 0.0f, 2.0f, -16.0f, 1.0f, 0.0f, -1.0f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_CEIL, backends, inputValues, expectedOutputValues); } TEST_CASE ("Exp_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 5.0f, 4.0f, 3.0f, 2.0f, 1.0f, 1.1f }; // Set output data std::vector expectedOutputValues { 148.413159102577f, 54.598150033144f, 20.085536923188f, 7.389056098931f, 2.718281828459f, 3.004166023946f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } TEST_CASE ("Log_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 1.0f, 1.0f, 2.0f, 3.0f, 4.0f, 2.71828f }; // Set output data std::vector expectedOutputValues { 0.f, 0.f, 0.69314718056f, 1.09861228867f, 1.38629436112f, 0.99999932734f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Neg_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 1.f, 0.f, 3.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { -1.f, 0.f, -3.f, -25.f, -64.f, -100.f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_NEG, backends, inputValues, expectedOutputValues); } TEST_CASE ("Rsqrt_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 1.f, 4.f, 16.f, 25.f, 64.f, 100.f }; // Set output data std::vector expectedOutputValues { 1.f, 0.5f, 0.25f, 0.2f, 0.125f, 0.1f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_RSQRT, backends, inputValues, expectedOutputValues); } TEST_CASE ("Sqrt_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 9.0f, 4.25f, 81.9f, 0.1f, 0.9f, 169.0f }; // Calculate output data std::vector expectedOutputValues(inputValues.size()); for (unsigned int i = 0; i < inputValues.size(); ++i) { expectedOutputValues[i] = std::sqrt(inputValues[i]); } ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SQRT, backends, inputValues, expectedOutputValues); } TEST_CASE ("Sin_Float32_CpuRef_Test") { // Create the ArmNN Delegate std::vector backends = { armnn::Compute::CpuRef }; // Set input data std::vector inputValues { 0.0f, 1.0f, 16.0f, 0.5f, 36.0f, -1.f }; // Set output data std::vector expectedOutputValues { 0.0f, 0.8414709848f, -0.28790331666f, 0.4794255386f, -0.99177885344f, -0.8414709848f }; ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); } } // TEST_SUITE("ElementwiseUnary_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/ElementwiseUnaryTestHelper.hpp000066400000000000000000000161701446772241200234210ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateElementwiseUnaryTfLiteModel(tflite::BuiltinOperator unaryOperatorCode, tflite::TensorType tensorType, const std::vector & tensorShape) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 1> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType); // create operator const std::vector operatorInputs{0}; const std::vector operatorOutputs{1}; flatbuffers::Offset unaryOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size())); const std::vector subgraphInputs{0}; const std::vector subgraphOutputs{1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&unaryOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Elementwise Unary Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, unaryOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void ElementwiseUnaryFP32Test(tflite::BuiltinOperator unaryOperatorCode, std::vector& backends, std::vector& inputValues, std::vector& expectedOutputValues) { using namespace delegateTestInterpreter; std::vector inputShape { { 3, 1, 2} }; std::vector modelBuffer = CreateElementwiseUnaryTfLiteModel(unaryOperatorCode, ::tflite::TensorType_FLOAT32, inputShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, inputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } void ElementwiseUnaryBoolTest(tflite::BuiltinOperator unaryOperatorCode, std::vector& backends, std::vector& inputShape, std::vector& inputValues, std::vector& expectedOutputValues) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateElementwiseUnaryTfLiteModel(unaryOperatorCode, ::tflite::TensorType_BOOL, inputShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareData(expectedOutputValues, armnnOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(expectedOutputValues, tfLiteOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues.size()); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, inputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/ExpandDimsTest.cpp000066400000000000000000000054351446772241200210120ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "RedefineTestHelper.hpp" namespace armnnDelegate { void ExpandDimsSimpleTest(std::vector& backends) { // Set input data std::vector inputShape { 2, 2, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector axis { 0 }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_EXPAND_DIMS, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, axis); } void ExpandDimsWithNegativeAxisTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector axis { -1 }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_EXPAND_DIMS, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, axis); } TEST_SUITE("ExpandDims_GpuAccTests") { TEST_CASE ("ExpandDims_Simple_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ExpandDimsSimpleTest(backends); } TEST_CASE ("ExpandDims_With_Negative_Axis_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ExpandDimsWithNegativeAxisTest(backends); } } // TEST_SUITE("ExpandDims_GpuAccTests") TEST_SUITE("ExpandDims_CpuAccTests") { TEST_CASE ("ExpandDims_Simple_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ExpandDimsSimpleTest(backends); } TEST_CASE ("ExpandDims_With_Negative_Axis_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ExpandDimsWithNegativeAxisTest(backends); } } // TEST_SUITE("ExpandDims_CpuAccTests") TEST_SUITE("ExpandDims_CpuRefTests") { TEST_CASE ("ExpandDims_Simple_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ExpandDimsSimpleTest(backends); } TEST_CASE ("ExpandDims_With_Negative_Axis_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ExpandDimsWithNegativeAxisTest(backends); } } // TEST_SUITE("ExpandDims_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/FillTest.cpp000066400000000000000000000150001446772241200176310ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "FillTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void Fill2dTest(std::vector& backends, tflite::BuiltinOperator fillOperatorCode = tflite::BuiltinOperator_FILL, float fill = 2.0f ) { std::vector inputShape { 2 }; std::vector tensorShape { 2, 2 }; std::vector expectedOutputValues = { fill, fill, fill, fill }; FillTest(fillOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, tensorShape, expectedOutputValues, fill); } void Fill3dTest(std::vector& backends, tflite::BuiltinOperator fillOperatorCode = tflite::BuiltinOperator_FILL, float fill = 5.0f ) { std::vector inputShape { 3 }; std::vector tensorShape { 3, 3, 3 }; std::vector expectedOutputValues = { fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill }; FillTest(fillOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, tensorShape, expectedOutputValues, fill); } void Fill4dTest(std::vector& backends, tflite::BuiltinOperator fillOperatorCode = tflite::BuiltinOperator_FILL, float fill = 3.0f ) { std::vector inputShape { 4 }; std::vector tensorShape { 2, 2, 4, 4 }; std::vector expectedOutputValues = { fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill, fill }; FillTest(fillOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, tensorShape, expectedOutputValues, fill); } void FillInt32Test(std::vector& backends, tflite::BuiltinOperator fillOperatorCode = tflite::BuiltinOperator_FILL, int32_t fill = 2 ) { std::vector inputShape { 2 }; std::vector tensorShape { 2, 2 }; std::vector expectedOutputValues = { fill, fill, fill, fill }; FillTest(fillOperatorCode, ::tflite::TensorType_INT32, backends, inputShape, tensorShape, expectedOutputValues, fill); } TEST_SUITE("Fill_CpuRefTests") { TEST_CASE ("Fill2d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Fill2dTest(backends); } TEST_CASE ("Fill3d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Fill3dTest(backends); } TEST_CASE ("Fill3d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Fill3dTest(backends); } TEST_CASE ("Fill4d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Fill4dTest(backends); } TEST_CASE ("FillInt32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FillInt32Test(backends); } } TEST_SUITE("Fill_CpuAccTests") { TEST_CASE ("Fill2d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Fill2dTest(backends); } TEST_CASE ("Fill3d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Fill3dTest(backends); } TEST_CASE ("Fill3d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Fill3dTest(backends); } TEST_CASE ("Fill4d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Fill4dTest(backends); } TEST_CASE ("FillInt32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; FillInt32Test(backends); } } TEST_SUITE("Fill_GpuAccTests") { TEST_CASE ("Fill2d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Fill2dTest(backends); } TEST_CASE ("Fill3d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Fill3dTest(backends); } TEST_CASE ("Fill3d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Fill3dTest(backends); } TEST_CASE ("Fill4d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Fill4dTest(backends); } TEST_CASE ("FillInt32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; FillInt32Test(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/FillTestHelper.hpp000066400000000000000000000155461446772241200210150ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreateFillTfLiteModel(tflite::BuiltinOperator fillOperatorCode, tflite::TensorType tensorType, const std::vector& inputShape, const std::vector & tensorShape, const std::vector fillValue) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(tensorShape.data()), sizeof(int32_t) * tensorShape.size()))); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(fillValue.data()), sizeof(T) * fillValue.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputShape.data(), inputShape.size()), tflite::TensorType_INT32, 1, flatBufferBuilder.CreateString("dims")); std::vector fillShape = {}; tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(fillShape.data(), fillShape.size()), tensorType, 2, flatBufferBuilder.CreateString("value")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output")); tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_FillOptions; flatbuffers::Offset operatorBuiltinOptions = CreateFillOptions(flatBufferBuilder).Union(); // create operator const std::vector operatorInputs{ {0, 1} }; const std::vector operatorOutputs{ 2 }; flatbuffers::Offset fillOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1} }; const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&fillOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Fill Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, fillOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void FillTest(tflite::BuiltinOperator fillOperatorCode, tflite::TensorType tensorType, const std::vector& backends, std::vector& inputShape, std::vector& tensorShape, std::vector& expectedOutputValues, T fillValue) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateFillTfLiteModel(fillOperatorCode, tensorType, inputShape, tensorShape, {fillValue}); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, tensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/FullyConnectedTest.cpp000066400000000000000000000137221446772241200216720ustar00rootroot00000000000000// // Copyright © 2020-2021,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "FullyConnectedTestHelper.hpp" namespace { void FullyConnectedFp32Test(std::vector& backends, bool constantWeights = true) { std::vector inputTensorShape { 1, 4, 1, 1 }; std::vector weightsTensorShape { 1, 4 }; std::vector biasTensorShape { 1 }; std::vector outputTensorShape { 1, 1 }; std::vector inputValues = { 10, 20, 30, 40 }; std::vector weightsData = { 2, 3, 4, 5 }; std::vector expectedOutputValues = { (400 + 10) }; // bias is set std::vector biasData = { 10 } in the model FullyConnectedTest(backends, ::tflite::TensorType_FLOAT32, tflite::ActivationFunctionType_NONE, inputTensorShape, weightsTensorShape, biasTensorShape, outputTensorShape, inputValues, expectedOutputValues, weightsData, constantWeights); } void FullyConnectedActivationTest(std::vector& backends, bool constantWeights = true) { std::vector inputTensorShape { 1, 4, 1, 1 }; std::vector weightsTensorShape { 1, 4 }; std::vector biasTensorShape { 1 }; std::vector outputTensorShape { 1, 1 }; std::vector inputValues = { -10, 20, 30, 40 }; std::vector weightsData = { 2, 3, 4, -5 }; std::vector expectedOutputValues = { 0 }; // bias is set std::vector biasData = { 10 } in the model FullyConnectedTest(backends, ::tflite::TensorType_FLOAT32, tflite::ActivationFunctionType_RELU, inputTensorShape, weightsTensorShape, biasTensorShape, outputTensorShape, inputValues, expectedOutputValues, weightsData, constantWeights); } void FullyConnectedInt8Test(std::vector& backends, bool constantWeights = true) { std::vector inputTensorShape { 1, 4, 2, 1 }; std::vector weightsTensorShape { 1, 4 }; std::vector biasTensorShape { 1 }; std::vector outputTensorShape { 2, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 10, 15, 20 }; std::vector weightsData = { 2, 3, 4, 5 }; std::vector expectedOutputValues = { 25, 105 }; // (40 + 10) / 2, (200 + 10) / 2 // bias is set std::vector biasData = { 10 } in the model // input and weights quantization scale 1.0f and offset 0 in the model // output quantization scale 2.0f and offset 0 in the model FullyConnectedTest(backends, ::tflite::TensorType_INT8, tflite::ActivationFunctionType_NONE, inputTensorShape, weightsTensorShape, biasTensorShape, outputTensorShape, inputValues, expectedOutputValues, weightsData, constantWeights); } TEST_SUITE("FullyConnected_GpuAccTests") { TEST_CASE ("FullyConnected_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; FullyConnectedFp32Test(backends); } TEST_CASE ("FullyConnected_Int8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; FullyConnectedInt8Test(backends); } TEST_CASE ("FullyConnected_Activation_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; FullyConnectedActivationTest(backends); } } // End of TEST_SUITE("FullyConnected_GpuAccTests") TEST_SUITE("FullyConnected_CpuAccTests") { TEST_CASE ("FullyConnected_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; FullyConnectedFp32Test(backends); } TEST_CASE ("FullyConnected_Int8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; FullyConnectedInt8Test(backends); } TEST_CASE ("FullyConnected_Activation_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; FullyConnectedActivationTest(backends); } } // End of TEST_SUITE("FullyConnected_CpuAccTests") TEST_SUITE("FullyConnected_CpuRefTests") { TEST_CASE ("FullyConnected_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedFp32Test(backends); } TEST_CASE ("FullyConnected_Int8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedInt8Test(backends); } TEST_CASE ("FullyConnected_Activation_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedActivationTest(backends); } TEST_CASE ("FullyConnected_Weights_As_Inputs_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedFp32Test(backends, false); } TEST_CASE ("FullyConnected_Weights_As_Inputs_Int8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedInt8Test(backends, false); } TEST_CASE ("FullyConnected_Weights_As_Inputs_Activation_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; FullyConnectedActivationTest(backends, false); } } // End of TEST_SUITE("FullyConnected_CpuRefTests") } // anonymous namespacearmnn-23.08/delegate/test/FullyConnectedTestHelper.hpp000066400000000000000000000271731446772241200230440ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreateFullyConnectedTfLiteModel(tflite::TensorType tensorType, tflite::ActivationFunctionType activationType, const std::vector & inputTensorShape, const std::vector & weightsTensorShape, const std::vector & biasTensorShape, std::vector & outputTensorShape, std::vector & weightsData, bool constantWeights = true, float quantScale = 1.0f, int quantOffset = 0, float outputQuantScale = 2.0f, int outputQuantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 5> buffers; buffers[0] = CreateBuffer(flatBufferBuilder); buffers[1] = CreateBuffer(flatBufferBuilder); auto biasTensorType = ::tflite::TensorType_FLOAT32; if (tensorType == ::tflite::TensorType_INT8) { biasTensorType = ::tflite::TensorType_INT32; } if (constantWeights) { buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(weightsData.data()), sizeof(T) * weightsData.size())); if (tensorType == ::tflite::TensorType_INT8) { std::vector biasData = { 10 }; buffers[3] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(biasData.data()), sizeof(int32_t) * biasData.size())); } else { std::vector biasData = { 10 }; buffers[3] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(biasData.data()), sizeof(float) * biasData.size())); } } else { buffers[2] = CreateBuffer(flatBufferBuilder); buffers[3] = CreateBuffer(flatBufferBuilder); } buffers[4] = CreateBuffer(flatBufferBuilder); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto outputQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ outputQuantScale }), flatBufferBuilder.CreateVector({ outputQuantOffset })); std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(weightsTensorShape.data(), weightsTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("weights"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(biasTensorShape.data(), biasTensorShape.size()), biasTensorType, 3, flatBufferBuilder.CreateString("bias"), quantizationParameters); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 4, flatBufferBuilder.CreateString("output"), outputQuantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_FullyConnectedOptions; flatbuffers::Offset operatorBuiltinOptions = CreateFullyConnectedOptions(flatBufferBuilder, activationType, FullyConnectedOptionsWeightsFormat_DEFAULT, false).Union(); const std::vector operatorInputs{0, 1, 2}; const std::vector operatorOutputs{3}; flatbuffers::Offset fullyConnectedOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0, 1, 2}; const std::vector subgraphOutputs{3}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&fullyConnectedOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: FullyConnected Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_FULLY_CONNECTED); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void FullyConnectedTest(std::vector& backends, tflite::TensorType tensorType, tflite::ActivationFunctionType activationType, const std::vector & inputTensorShape, const std::vector & weightsTensorShape, const std::vector & biasTensorShape, std::vector & outputTensorShape, std::vector & inputValues, std::vector & expectedOutputValues, std::vector & weightsData, bool constantWeights = true, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateFullyConnectedTfLiteModel(tensorType, activationType, inputTensorShape, weightsTensorShape, biasTensorShape, outputTensorShape, weightsData, constantWeights, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); if (!constantWeights) { CHECK(tfLiteInterpreter.FillInputTensor(weightsData, 1) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(weightsData, 1) == kTfLiteOk); if (tensorType == ::tflite::TensorType_INT8) { std::vector biasData = {10}; CHECK(tfLiteInterpreter.FillInputTensor(biasData, 2) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(biasData, 2) == kTfLiteOk); } else { std::vector biasData = {10}; CHECK(tfLiteInterpreter.FillInputTensor(biasData, 2) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(biasData, 2) == kTfLiteOk); } } CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/GatherNdTest.cpp000066400000000000000000000056441446772241200204540ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "GatherNdTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // GATHER_ND Operator void GatherNdUint8Test(std::vector& backends) { std::vector paramsShape{ 5, 2 }; std::vector indicesShape{ 3, 1 }; std::vector expectedOutputShape{ 3, 2 }; std::vector paramsValues{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; std::vector indicesValues{ 1, 0, 4 }; std::vector expectedOutputValues{ 3, 4, 1, 2, 9, 10 }; GatherNdTest(::tflite::TensorType_UINT8, backends, paramsShape, indicesShape, expectedOutputShape, paramsValues, indicesValues, expectedOutputValues); } void GatherNdFp32Test(std::vector& backends) { std::vector paramsShape{ 5, 2 }; std::vector indicesShape{ 3, 1 }; std::vector expectedOutputShape{ 3, 2 }; std::vector paramsValues{ 1.1f, 2.2f, 3.3f, 4.4f, 5.5f, 6.6f, 7.7f, 8.8f, 9.9f, 10.10f }; std::vector indicesValues{ 1, 0, 4 }; std::vector expectedOutputValues{ 3.3f, 4.4f, 1.1f, 2.2f, 9.9f, 10.10f }; GatherNdTest(::tflite::TensorType_FLOAT32, backends, paramsShape, indicesShape, expectedOutputShape, paramsValues, indicesValues, expectedOutputValues); } // GATHER_ND Test Suite TEST_SUITE("GATHER_ND_CpuRefTests") { TEST_CASE ("GATHER_ND_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; GatherNdUint8Test(backends); } TEST_CASE ("GATHER_ND_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; GatherNdFp32Test(backends); } } TEST_SUITE("GATHER_ND_CpuAccTests") { TEST_CASE ("GATHER_ND_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; GatherNdUint8Test(backends); } TEST_CASE ("GATHER_ND_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; GatherNdFp32Test(backends); } } TEST_SUITE("GATHER_ND_GpuAccTests") { TEST_CASE ("GATHER_ND_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; GatherNdUint8Test(backends); } TEST_CASE ("GATHER_ND_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; GatherNdFp32Test(backends); } } // End of GATHER_ND Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/GatherNdTestHelper.hpp000066400000000000000000000210541446772241200216120ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateGatherNdTfLiteModel(tflite::TensorType tensorType, std::vector& paramsShape, std::vector& indicesShape, const std::vector& expectedOutputShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(paramsShape.data(), paramsShape.size()), tensorType, 1, flatBufferBuilder.CreateString("params"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(indicesShape.data(), indicesShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("indices"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(expectedOutputShape.data(), expectedOutputShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_GatherNdOptions; flatbuffers::Offset operatorBuiltinOptions = CreateGatherNdOptions(flatBufferBuilder).Union(); const std::vector operatorInputs{{0, 1}}; const std::vector operatorOutputs{2}; flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{{0, 1}}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: GATHER_ND Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_GATHER_ND); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void GatherNdTest(tflite::TensorType tensorType, std::vector& backends, std::vector& paramsShape, std::vector& indicesShape, std::vector& expectedOutputShape, std::vector& paramsValues, std::vector& indicesValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateGatherNdTfLiteModel(tensorType, paramsShape, indicesShape, expectedOutputShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(paramsValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(indicesValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(paramsValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(indicesValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/GatherTest.cpp000066400000000000000000000055621446772241200201710ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "GatherTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // GATHER Operator void GatherUint8Test(std::vector& backends) { std::vector paramsShape{8}; std::vector indicesShape{3}; std::vector expectedOutputShape{3}; int32_t axis = 0; std::vector paramsValues{1, 2, 3, 4, 5, 6, 7, 8}; std::vector indicesValues{7, 6, 5}; std::vector expectedOutputValues{8, 7, 6}; GatherTest(::tflite::TensorType_UINT8, backends, paramsShape, indicesShape, expectedOutputShape, axis, paramsValues, indicesValues, expectedOutputValues); } void GatherFp32Test(std::vector& backends) { std::vector paramsShape{8}; std::vector indicesShape{3}; std::vector expectedOutputShape{3}; int32_t axis = 0; std::vector paramsValues{1.1f, 2.2f, 3.3f, 4.4f, 5.5f, 6.6f, 7.7f, 8.8f}; std::vector indicesValues{7, 6, 5}; std::vector expectedOutputValues{8.8f, 7.7f, 6.6f}; GatherTest(::tflite::TensorType_FLOAT32, backends, paramsShape, indicesShape, expectedOutputShape, axis, paramsValues, indicesValues, expectedOutputValues); } // GATHER Test Suite TEST_SUITE("GATHER_CpuRefTests") { TEST_CASE ("GATHER_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; GatherUint8Test(backends); } TEST_CASE ("GATHER_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; GatherFp32Test(backends); } } TEST_SUITE("GATHER_CpuAccTests") { TEST_CASE ("GATHER_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; GatherUint8Test(backends); } TEST_CASE ("GATHER_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; GatherFp32Test(backends); } } TEST_SUITE("GATHER_GpuAccTests") { TEST_CASE ("GATHER_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; GatherUint8Test(backends); } TEST_CASE ("GATHER_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; GatherFp32Test(backends); } } // End of GATHER Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/GatherTestHelper.hpp000066400000000000000000000212711446772241200213310ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateGatherTfLiteModel(tflite::TensorType tensorType, std::vector& paramsShape, std::vector& indicesShape, const std::vector& expectedOutputShape, int32_t axis, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(paramsShape.data(), paramsShape.size()), tensorType, 1, flatBufferBuilder.CreateString("params"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(indicesShape.data(), indicesShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("indices"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(expectedOutputShape.data(), expectedOutputShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_GatherOptions; flatbuffers::Offset operatorBuiltinOptions = CreateGatherOptions(flatBufferBuilder).Union(); const std::vector operatorInputs{{0, 1}}; const std::vector operatorOutputs{2}; flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{{0, 1}}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: GATHER Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_GATHER); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void GatherTest(tflite::TensorType tensorType, std::vector& backends, std::vector& paramsShape, std::vector& indicesShape, std::vector& expectedOutputShape, int32_t axis, std::vector& paramsValues, std::vector& indicesValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateGatherTfLiteModel(tensorType, paramsShape, indicesShape, expectedOutputShape, axis, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(paramsValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(indicesValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(paramsValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(indicesValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/LogicalTest.cpp000066400000000000000000000151001446772241200203160ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ElementwiseUnaryTestHelper.hpp" #include "LogicalTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void LogicalBinaryAndBoolTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1, 2, 2 }; std::vector expectedOutputShape { 1, 2, 2 }; // Set input and output values std::vector input0Values { 0, 0, 1, 1 }; std::vector input1Values { 0, 1, 0, 1 }; std::vector expectedOutputValues { 0, 0, 0, 1 }; LogicalBinaryTest(tflite::BuiltinOperator_LOGICAL_AND, ::tflite::TensorType_BOOL, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LogicalBinaryAndBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2 }; std::vector input0Values { 0, 1, 0, 1 }; std::vector input1Values { 1 }; std::vector expectedOutputValues { 0, 1, 0, 1 }; LogicalBinaryTest(tflite::BuiltinOperator_LOGICAL_AND, ::tflite::TensorType_BOOL, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LogicalBinaryOrBoolTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1, 2, 2 }; std::vector expectedOutputShape { 1, 2, 2 }; std::vector input0Values { 0, 0, 1, 1 }; std::vector input1Values { 0, 1, 0, 1 }; std::vector expectedOutputValues { 0, 1, 1, 1 }; LogicalBinaryTest(tflite::BuiltinOperator_LOGICAL_OR, ::tflite::TensorType_BOOL, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } void LogicalBinaryOrBroadcastTest(std::vector& backends) { std::vector input0Shape { 1, 2, 2 }; std::vector input1Shape { 1, 1, 1 }; std::vector expectedOutputShape { 1, 2, 2 }; std::vector input0Values { 0, 1, 0, 1 }; std::vector input1Values { 1 }; std::vector expectedOutputValues { 1, 1, 1, 1 }; LogicalBinaryTest(tflite::BuiltinOperator_LOGICAL_OR, ::tflite::TensorType_BOOL, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues); } // LogicalNot operator uses ElementwiseUnary unary layer and descriptor but is still classed as logical operator. void LogicalNotBoolTest(std::vector& backends) { std::vector inputShape { 1, 2, 2 }; std::vector inputValues { 0, 1, 0, 1 }; std::vector expectedOutputValues { 1, 0, 1, 0 }; ElementwiseUnaryBoolTest(tflite::BuiltinOperator_LOGICAL_NOT, backends, inputShape, inputValues, expectedOutputValues); } TEST_SUITE("LogicalBinaryTests_GpuAccTests") { TEST_CASE ("LogicalBinary_AND_Bool_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LogicalBinaryAndBoolTest(backends); } TEST_CASE ("LogicalBinary_AND_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LogicalBinaryAndBroadcastTest(backends); } TEST_CASE ("Logical_NOT_Bool_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LogicalNotBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Bool_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LogicalBinaryOrBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Broadcast_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LogicalBinaryOrBroadcastTest(backends); } } TEST_SUITE("LogicalBinaryTests_CpuAccTests") { TEST_CASE ("LogicalBinary_AND_Bool_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LogicalBinaryAndBoolTest(backends); } TEST_CASE ("LogicalBinary_AND_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LogicalBinaryAndBroadcastTest(backends); } TEST_CASE ("Logical_NOT_Bool_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LogicalNotBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Bool_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LogicalBinaryOrBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Broadcast_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LogicalBinaryOrBroadcastTest(backends); } } TEST_SUITE("LogicalBinaryTests_CpuRefTests") { TEST_CASE ("LogicalBinary_AND_Bool_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LogicalBinaryAndBoolTest(backends); } TEST_CASE ("LogicalBinary_AND_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LogicalBinaryAndBroadcastTest(backends); } TEST_CASE ("Logical_NOT_Bool_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LogicalNotBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Bool_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LogicalBinaryOrBoolTest(backends); } TEST_CASE ("LogicalBinary_OR_Broadcast_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LogicalBinaryOrBroadcastTest(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/LogicalTestHelper.hpp000066400000000000000000000211361446772241200214710ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateLogicalBinaryTfLiteModel(tflite::BuiltinOperator logicalOperatorCode, tflite::TensorType tensorType, const std::vector & input0TensorShape, const std::vector & input1TensorShape, const std::vector & outputTensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input1TensorShape.data(), input1TensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("input_1"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOptions = 0; switch (logicalOperatorCode) { case BuiltinOperator_LOGICAL_AND: { operatorBuiltinOptionsType = BuiltinOptions_LogicalAndOptions; operatorBuiltinOptions = CreateLogicalAndOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_LOGICAL_OR: { operatorBuiltinOptionsType = BuiltinOptions_LogicalOrOptions; operatorBuiltinOptions = CreateLogicalOrOptions(flatBufferBuilder).Union(); break; } default: break; } const std::vector operatorInputs{ {0, 1} }; const std::vector operatorOutputs{ 2 }; flatbuffers::Offset logicalBinaryOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1} }; const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&logicalBinaryOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Logical Binary Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, logicalOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void LogicalBinaryTest(tflite::BuiltinOperator logicalOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& input0Shape, std::vector& input1Shape, std::vector& expectedOutputShape, std::vector& input0Values, std::vector& input1Values, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateLogicalBinaryTfLiteModel(logicalOperatorCode, tensorType, input0Shape, input1Shape, expectedOutputShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input1Values, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); armnnDelegate::CompareData(expectedOutputValues, armnnOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(expectedOutputValues, tfLiteOutputValues, expectedOutputValues.size()); armnnDelegate::CompareData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues.size()); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/LstmTest.cpp000066400000000000000000000200321446772241200176630ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "LstmTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void LstmTest(std::vector& backends) { int32_t batchSize = 2; int32_t inputSize = 2; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; std::vector inputShape {batchSize , inputSize}; std::vector cellStateInTensorInfo {batchSize , numUnits}; std::vector outputStateInTensorInfo {batchSize , outputSize}; std::vector scratchBufferTensorInfo {batchSize, numUnits * 4}; std::vector cellStateOutTensorInfo {batchSize, numUnits}; std::vector outputStateOutTensorInfo {batchSize, outputSize}; std::vector outputTensorInfo {batchSize, outputSize}; std::vector tensorInfo4 {numUnits}; std::vector tensorInfo8 {numUnits, 2}; std::vector tensorInfo16 {numUnits, 4}; //tensorInfo8, bool hasInputToInputWeights = true; std::vector inputToInputWeights {-0.45018822f, -0.02338299f, -0.0870589f, -0.34550029f, 0.04266912f, -0.15680569f, -0.34856534f, 0.43890524f}; std::vector inputToForgetWeights {0.09701663f, 0.20334584f, -0.50592935f, -0.31343272f, -0.40032279f, 0.44781327f, 0.01387155f, -0.35593212f}; std::vector inputToCellWeights {-0.50013041f, 0.1370284f, 0.11810488f, 0.2013163f, -0.20583314f, 0.44344562f, 0.22077113f, -0.29909778f}; std::vector inputToOutputWeights {-0.25065863f, -0.28290087f, 0.04613829f, 0.40525138f, 0.44272184f, 0.03897077f, -0.1556896f, 0.19487578f}; //tensorInfo16, bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights {-0.0063535f, -0.2042388f, 0.31454784f, -0.35746509f, 0.28902304f, 0.08183324f, -0.16555229f, 0.02286911f, -0.13566875f, 0.03034258f, 0.48091322f, -0.12528998f, 0.24077177f, -0.51332325f, -0.33502164f, 0.10629296f}; std::vector recurrentToForgetWeights {-0.48684245f, -0.06655136f, 0.42224967f, 0.2112639f, 0.27654213f, 0.20864892f, -0.07646349f, 0.45877004f, 0.00141793f, -0.14609534f, 0.36447752f, 0.09196436f, 0.28053468f, 0.01560611f, -0.20127171f, -0.01140004f}; std::vector recurrentToCellWeights {-0.3407414f, 0.24443203f, -0.2078532f, 0.26320225f, 0.05695659f, -0.00123841f, -0.4744786f, -0.35869038f, -0.06418842f, -0.13502428f, -0.501764f, 0.22830659f, -0.46367589f, 0.26016325f, -0.03894562f, -0.16368064f}; std::vector recurrentToOutputWeights {0.43385774f, -0.17194885f, 0.2718237f, 0.09215671f, 0.24107647f, -0.39835793f, 0.18212086f, 0.01301402f, 0.48572797f, -0.50656658f, 0.20047462f, -0.20607421f, -0.51818722f, -0.15390486f, 0.0468148f, 0.39922136f}; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights {}; bool hasCellToForgetWeights = false; std::vector cellToForgetWeights {}; bool hasCellToOutputWeights = false; std::vector cellToOutputWeights {}; bool hasInputGateBias = true; std::vector inputGateBias {0., 0., 0., 0.}; std::vector forgetGateBias {1., 1., 1., 1.}; std::vector cellBias {0., 0., 0., 0.}; std::vector outputGateBias {0., 0., 0., 0.}; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues {2., 3., 3., 4.}; std::vector expectedOutputValues {-0.02973187f, 0.1229473f, 0.20885126f, -0.15358765f, -0.0185422f, 0.11281417f, 0.24466537f, -0.1826292f}; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 0.f; float clippingThresProj = 0.f; LstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj); } TEST_SUITE("LstmTest_CpuRefTests") { TEST_CASE ("LstmTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; LstmTest(backends); } } //End of TEST_SUITE("Convolution2dTest_CpuRef") TEST_SUITE("LstmTest_CpuAccTests") { TEST_CASE ("LstmTest_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; LstmTest(backends); } } //End of TEST_SUITE("Convolution2dTest_CpuAcc") } // namespace armnnDelegatearmnn-23.08/delegate/test/LstmTestHelper.hpp000066400000000000000000001072621446772241200210430ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreateLstmTfLiteModel(tflite::TensorType tensorType, int32_t batchSize, int32_t inputSize, int32_t outputSize, int32_t numUnits, bool hasInputToInputWeights, const std::vector& inputToInputWeights, const std::vector& inputToForgetWeights, const std::vector& inputToCellWeights, const std::vector& inputToOutputWeights, bool hasRecurrentToInputWeights, const std::vector& recurrentToInputWeights, const std::vector& recurrentToForgetWeights, const std::vector& recurrentToCellWeights, const std::vector& recurrentToOutputWeights, bool hasCellToInputWeights, const std::vector& cellToInputWeights, bool hasCellToForgetWeights, const std::vector& cellToForgetWeights, bool hasCellToOutputWeights, const std::vector& cellToOutputWeights, bool hasInputGateBias, const std::vector& inputGateBias, const std::vector& forgetGateBias, const std::vector& cellBias, const std::vector& outputGateBias, bool hasProjectionWeights, const std::vector& projectionWeights, bool hasProjectionBias, const std::vector& projectionBias, bool hasInputLayerNormWeights, const std::vector& inputLayerNormWeights, bool hasForgetLayerNormWeights, const std::vector& forgetLayerNormWeights, bool hasCellLayerNormWeights, const std::vector& cellLayerNormWeights, bool hasOutputLayerNormWeights, const std::vector& outputLayerNormWeights, tflite::ActivationFunctionType activationFunction, float clippingThresCell, float clippingThresProj, float quantScale = 1.0f, int quantOffset = 0, float outputQuantScale = 2.0f, int outputQuantOffset = 0) { std::vector tensorInfo0 {}; std::vector tensorInfo4 {numUnits}; std::vector tensorInfo8 {numUnits, static_cast(2)}; std::vector tensorInfo16 {numUnits, static_cast(4)}; std::vector inputShape {batchSize , inputSize}; std::vector outputShape {batchSize , outputSize}; std::vector outputStateInDimensions{batchSize, outputSize}; std::vector cellStateInDimensions{batchSize, numUnits}; std::vector operatorInputs; using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; std::vector> tensors; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto outputQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ outputQuantScale }), flatBufferBuilder.CreateVector({ outputQuantOffset })); buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputShape.data(), inputShape.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("input_0"), quantizationParameters)); operatorInputs.push_back(buffers.size() - 1); if (hasInputToInputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputToInputWeights.data()), sizeof(T) * inputToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo8.data(), tensorInfo8.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToInputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputToForgetWeights.data()), sizeof(T) * inputToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo8.data(), tensorInfo8.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToForgetWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputToCellWeights.data()), sizeof(T) * inputToCellWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo8.data(), tensorInfo8.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToCellWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputToOutputWeights.data()), sizeof(T) * inputToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo8.data(), tensorInfo8.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToOutputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); if (hasRecurrentToInputWeights) { buffers.push_back(CreateBuffer( flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(recurrentToInputWeights.data()), sizeof(T) * recurrentToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo16.data(), tensorInfo16.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToInputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(recurrentToForgetWeights.data()), sizeof(T) * recurrentToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo16.data(), tensorInfo16.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToForgetWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(recurrentToCellWeights.data()), sizeof(T) * recurrentToCellWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo16.data(), tensorInfo16.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToCellWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(recurrentToOutputWeights.data()), sizeof(T) * recurrentToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo16.data(), tensorInfo16.size()), tensorType, buffers.size() - 1 , flatBufferBuilder.CreateString("recurrentToOutputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); if (hasCellToInputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellToInputWeights.data()), sizeof(T) * cellToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToInputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellToForgetWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellToForgetWeights.data()), sizeof(T) * cellToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToForgetWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellToOutputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellToOutputWeights.data()), sizeof(T) * cellToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToOutputWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasInputGateBias) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputGateBias.data()), sizeof(T) * inputGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputGateBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(forgetGateBias.data()), sizeof(T) * forgetGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("forgetGateBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellBias.data()), sizeof(T) * cellBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(outputGateBias.data()), sizeof(T) * outputGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("outputGateBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); if (hasProjectionWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(projectionWeights.data()), sizeof(T) * projectionWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("outputGateBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasProjectionBias) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(projectionBias.data()), sizeof(T) * projectionBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("projectionBias"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputStateInDimensions.data(), outputStateInDimensions.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("outputStateInInfo"), outputQuantizationParameters, true)); operatorInputs.push_back(buffers.size() - 1); buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(cellStateInDimensions.data(), cellStateInDimensions.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellStateInInfo"), outputQuantizationParameters, true)); operatorInputs.push_back(buffers.size() - 1); if (hasInputLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputLayerNormWeights.data()), sizeof(T) * inputLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputLayerNormWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasForgetLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(forgetLayerNormWeights.data()), sizeof(T) * forgetLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("forgetLayerNormWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellLayerNormWeights.data()), sizeof(T) * cellLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellLayerNormWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasOutputLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(outputLayerNormWeights.data()), sizeof(T) * outputLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfo4.data(), tensorInfo4.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("outputLayerNormWeights"), outputQuantizationParameters)); operatorInputs.push_back(buffers.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } int outputBufferId = buffers.size(); buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputShape.data(), outputShape.size()), tensorType, outputBufferId, flatBufferBuilder.CreateString("output"), outputQuantizationParameters)); std::vector operatorOutputs; operatorOutputs.push_back(buffers.size() - 1); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_LSTMOptions; flatbuffers::Offset operatorBuiltinOptions = CreateLSTMOptions(flatBufferBuilder, activationFunction, clippingThresCell, clippingThresProj).Union(); flatbuffers::Offset lstmOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), flatBufferBuilder.CreateVector(&lstmOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: LSTM Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_LSTM); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void LstmTestImpl(std::vector& backends, tflite::TensorType tensorType, int32_t batchSize, int32_t inputSize, int32_t outputSize, int32_t numUnits, bool hasInputToInputWeights, const std::vector& inputToInputWeights, const std::vector& inputToForgetWeights, const std::vector& inputToCellWeights, const std::vector& inputToOutputWeights, bool hasRecurrentToInputWeights, const std::vector& recurrentToInputWeights, const std::vector& recurrentToForgetWeights, const std::vector& recurrentToCellWeights, const std::vector& recurrentToOutputWeights, bool hasCellToInputWeights, const std::vector& cellToInputWeights, bool hasCellToForgetWeights, const std::vector& cellToForgetWeights, bool hasCellToOutputWeights, const std::vector& cellToOutputWeights, bool hasInputGateBias, const std::vector& inputGateBias, const std::vector& forgetGateBias, const std::vector& cellBias, const std::vector& outputGateBias, bool hasProjectionWeights, const std::vector& projectionWeights, bool hasProjectionBias, const std::vector& projectionBias, bool hasInputLayerNormWeights, const std::vector& inputLayerNormWeights, bool hasForgetLayerNormWeights, const std::vector& forgetLayerNormWeights, bool hasCellLayerNormWeights, const std::vector& cellLayerNormWeights, bool hasOutputLayerNormWeights, const std::vector& outputLayerNormWeights, std::vector& inputValues, std::vector& expectedOutputValues, tflite::ActivationFunctionType activationFunction, float clippingThresCell, float clippingThresProj) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateLstmTfLiteModel(tensorType, batchSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, activationFunction, clippingThresCell, clippingThresProj); std::vector expectedOutputShape {batchSize , outputSize}; // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/MirrorPadTest.cpp000066400000000000000000000226741446772241200206610ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "PadTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void MirrorPadSymmetric2dTest(std::vector& backends) { // Set input data std::vector inputShape { 3, 3 }; std::vector outputShape { 7, 7 }; std::vector paddingShape { 2, 2 }; std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f }; std::vector expectedOutputValues = { 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f, 2.0f, 1.0f, 1.0f, 2.0f, 3.0f, 3.0f, 2.0f, 2.0f, 1.0f, 1.0f, 2.0f, 3.0f, 3.0f, 2.0f, 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f, 8.0f, 7.0f, 7.0f, 8.0f, 9.0f, 9.0f, 8.0f, 8.0f, 7.0f, 7.0f, 8.0f, 9.0f, 9.0f, 8.0f, 5.0f, 4.0f, 4.0f, 5.0f, 6.0f, 6.0f, 5.0f }; std::vector paddingDim = { 2, 2, 2, 2 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 0, // Offset tflite::MirrorPadMode_SYMMETRIC); } void MirrorPadReflect2dTest(std::vector& backends) { // Set input data std::vector inputShape { 3, 3 }; std::vector outputShape { 7, 7 }; std::vector paddingShape { 2, 2 }; std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f }; std::vector expectedOutputValues = { 9.0f, 8.0f, 7.0f, 8.0f, 9.0f, 8.0f, 7.0f, 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 3.0f, 2.0f, 1.0f, 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f, 9.0f, 8.0f, 7.0f, 8.0f, 9.0f, 8.0f, 7.0f, 6.0f, 5.0f, 4.0f, 5.0f, 6.0f, 5.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 3.0f, 2.0f, 1.0f }; std::vector paddingDim = { 2, 2, 2, 2 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 0, // Offset tflite::MirrorPadMode_REFLECT); } void MirrorPadSymmetric3dTest(std::vector& backends) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 4, 4, 4 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { // Channel 0, Height (2) x Width (2) 1.0f, 2.0f, 3.0f, 4.0f, // Channel 1, Height (2) x Width (2) 5.0f, 6.0f, 7.0f, 8.0f }; std::vector expectedOutputValues = { 1.0f, 1.0f, 2.0f, 2.0f, 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f, 4.0f, 4.0f, 3.0f, 3.0f, 4.0f, 4.0f, 1.0f, 1.0f, 2.0f, 2.0f, 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f, 4.0f, 4.0f, 3.0f, 3.0f, 4.0f, 4.0f, 5.0f, 5.0f, 6.0f, 6.0f, 5.0f, 5.0f, 6.0f, 6.0f, 7.0f, 7.0f, 8.0f, 8.0f, 7.0f, 7.0f, 8.0f, 8.0f, 5.0f, 5.0f, 6.0f, 6.0f, 5.0f, 5.0f, 6.0f, 6.0f, 7.0f, 7.0f, 8.0f, 8.0f, 7.0f, 7.0f, 8.0f, 8.0f }; std::vector paddingDim = { 1, 1, 1, 1, 1, 1 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 0, // Offset tflite::MirrorPadMode_SYMMETRIC); } void MirrorPadReflect3dTest(std::vector& backends) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 4, 4, 4 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { // Channel 0, Height (2) x Width (2) 1.0f, 2.0f, 3.0f, 4.0f, // Channel 1, Height (2) x Width (2) 5.0f, 6.0f, 7.0f, 8.0f }; std::vector expectedOutputValues = { 8.0f, 7.0f, 8.0f, 7.0f, 6.0f, 5.0f, 6.0f, 5.0f, 8.0f, 7.0f, 8.0f, 7.0f, 6.0f, 5.0f, 6.0f, 5.0f, 4.0f, 3.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 1.0f, 4.0f, 3.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 1.0f, 8.0f, 7.0f, 8.0f, 7.0f, 6.0f, 5.0f, 6.0f, 5.0f, 8.0f, 7.0f, 8.0f, 7.0f, 6.0f, 5.0f, 6.0f, 5.0f, 4.0f, 3.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 1.0f, 4.0f, 3.0f, 4.0f, 3.0f, 2.0f, 1.0f, 2.0f, 1.0f }; std::vector paddingDim = { 1, 1, 1, 1, 1, 1 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 0, // Offset tflite::MirrorPadMode_REFLECT); } void MirrorPadSymmetricUint8Test(std::vector& backends) { // Set input data std::vector inputShape { 3, 3 }; std::vector outputShape { 5, 7 }; std::vector paddingShape { 2, 2 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 7, 8, 9 }; std::vector expectedOutputValues = { 2, 1, 1, 2, 3, 3, 2, 2, 1, 1, 2, 3, 3, 2, 5, 4, 4, 5, 6, 6, 5, 8, 7, 7, 8, 9, 9, 8, 8, 7, 7, 8, 9, 9, 8, }; std::vector paddingDim = { 1, 1, 2, 2 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_UINT8, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 1, // Offset tflite::MirrorPadMode_SYMMETRIC); } void MirrorPadReflectInt8Test(std::vector& backends) { // Set input data std::vector inputShape { 3, 3 }; std::vector outputShape { 7, 5 }; std::vector paddingShape { 2, 2 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 7, 8, 9 }; std::vector expectedOutputValues = { 8, 7, 8, 9, 8, 5, 4, 5, 6, 5, 2, 1, 2, 3, 2, 5, 4, 5, 6, 5, 8, 7, 8, 9, 8, 5, 4, 5, 6, 5, 2, 1, 2, 3, 2 }; std::vector paddingDim = { 2, 2, 1, 1 }; PadTest(tflite::BuiltinOperator_MIRROR_PAD, ::tflite::TensorType_INT8, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, 0, // Padding value - Not used in these tests. 1.0f, // Scale 1, // Offset tflite::MirrorPadMode_REFLECT); } TEST_SUITE("MirrorPad_CpuRefTests") { TEST_CASE ("MirrorPadSymmetric2d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadSymmetric2dTest(backends); } TEST_CASE ("MirrorPadReflect2d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadReflect2dTest(backends); } TEST_CASE ("MirrorPadSymmetric3d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadSymmetric3dTest(backends); } TEST_CASE ("MirrorPadReflect3d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadReflect3dTest(backends); } TEST_CASE ("MirrorPadSymmetricUint8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadSymmetricUint8Test(backends); } TEST_CASE ("MirrorPadSymmetricInt8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MirrorPadReflectInt8Test(backends); } } // TEST_SUITE("MirrorPad_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/NeonDelegateTests_NDK_Issue.cpp000066400000000000000000000042031446772241200233270ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "NormalizationTestHelper.hpp" #include "SoftmaxTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // There's a known Android NDK bug which causes this subset of Neon Tests to // fail. We'll exclude these tests in if we're doing // a debug build and NDK is less than r21. // The exclusion takes place in test/CMakeLists.txt // https://github.com/android/ndk/issues/1135 TEST_SUITE ("Softmax_CpuAccTests") { TEST_CASE ("Softmax_Standard_Beta_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; std::vector expectedOutput = {0.00994190481, 0.0445565246, 0.0734612942, 0.329230666, 0.542809606, 0.710742831, 0.158588171, 0.0961885825, 0.0214625746, 0.0130177103}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 1, expectedOutput); } TEST_CASE ("Softmax_Different_Beta_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; std::vector expectedOutput = { 0.0946234912, 0.148399189, 0.172415257, 0.270400971, 0.314161092, 0.352414012, 0.224709094, 0.193408906, 0.123322964, 0.106145054}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 0.3, expectedOutput); } TEST_CASE ("Log_Softmax_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; std::vector expectedOutput = {-4.61099672, -3.11099672, -2.61099672, -1.11099672, -0.610996664, -0.341444582, -1.84144461, -2.34144449, -3.84144449, -4.34144449}; SoftmaxTestCase(tflite::BuiltinOperator_LOG_SOFTMAX, backends, 0, expectedOutput); } } // TEST_SUITE ("Softmax_CpuAccTests") TEST_SUITE("L2Normalization_CpuAccTests") { TEST_CASE ("L2NormalizationFp32Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; L2NormalizationTest(backends); } } // TEST_SUITE("L2NormalizationFp32Test_CpuAcc_Test") }armnn-23.08/delegate/test/NormalizationTest.cpp000066400000000000000000000033411446772241200215760ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "NormalizationTestHelper.hpp" #include #include #include namespace armnnDelegate { TEST_SUITE("L2Normalization_CpuRefTests") { TEST_CASE ("L2NormalizationFp32Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; L2NormalizationTest(backends); } } // TEST_SUITE("L2Normalization_CpuRefTests") TEST_SUITE("L2Normalization_GpuAccTests") { TEST_CASE ("L2NormalizationFp32Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; L2NormalizationTest(backends); } } // TEST_SUITE("L2Normalization_GpuAccTests") TEST_SUITE("LocalResponseNormalization_CpuRefTests") { TEST_CASE ("LocalResponseNormalizationTest_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; LocalResponseNormalizationTest(backends, 3, 1.f, 1.f, 1.f); } } // TEST_SUITE("LocalResponseNormalization_CpuRefTests") TEST_SUITE("LocalResponseNormalization_CpuAccTests") { TEST_CASE ("LocalResponseNormalizationTest_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; LocalResponseNormalizationTest(backends, 3, 1.f, 1.f, 1.f); } } // TEST_SUITE("LocalResponseNormalization_CpuAccTests") TEST_SUITE("LocalResponseNormalization_GpuAccTests") { TEST_CASE ("LocalResponseNormalizationTest_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; LocalResponseNormalizationTest(backends, 3, 1.f, 1.f, 1.f); } } // TEST_SUITE("LocalResponseNormalization_GpuAccTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/NormalizationTestHelper.hpp000066400000000000000000000251741446772241200227530ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateNormalizationTfLiteModel(tflite::BuiltinOperator normalizationOperatorCode, tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& outputTensorShape, int32_t radius, float bias, float alpha, float beta, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); std::vector> tensors = { inputTensor, outputTensor }; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::vector operatorInputs = { 0 }; std::vector subgraphInputs = { 0 }; tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_L2NormOptions; flatbuffers::Offset operatorBuiltinOptions = CreateL2NormOptions(flatBufferBuilder, tflite::ActivationFunctionType_NONE).Union(); if (normalizationOperatorCode == tflite::BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION) { operatorBuiltinOptionsType = BuiltinOptions_LocalResponseNormalizationOptions; operatorBuiltinOptions = CreateLocalResponseNormalizationOptions(flatBufferBuilder, radius, bias, alpha, beta).Union(); } // create operator const std::vector operatorOutputs{ 1 }; flatbuffers::Offset normalizationOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphOutputs{ 1 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&normalizationOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Normalization Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, normalizationOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void NormalizationTest(tflite::BuiltinOperator normalizationOperatorCode, tflite::TensorType tensorType, const std::vector& backends, const std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, int32_t radius = 0, float bias = 0.f, float alpha = 0.f, float beta = 0.f, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateNormalizationTfLiteModel(normalizationOperatorCode, tensorType, inputShape, outputShape, radius, bias, alpha, beta, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } void L2NormalizationTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 1, 1, 10 }; std::vector outputShape { 1, 1, 1, 10 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f }; const float approxInvL2Norm = 0.050964719f; std::vector expectedOutputValues { 1.0f * approxInvL2Norm, 2.0f * approxInvL2Norm, 3.0f * approxInvL2Norm, 4.0f * approxInvL2Norm, 5.0f * approxInvL2Norm, 6.0f * approxInvL2Norm, 7.0f * approxInvL2Norm, 8.0f * approxInvL2Norm, 9.0f * approxInvL2Norm, 10.0f * approxInvL2Norm }; NormalizationTest(tflite::BuiltinOperator_L2_NORMALIZATION, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void LocalResponseNormalizationTest(std::vector& backends, int32_t radius, float bias, float alpha, float beta) { // Set input data std::vector inputShape { 2, 2, 2, 1 }; std::vector outputShape { 2, 2, 2, 1 }; std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f }; std::vector expectedOutputValues { 0.5f, 0.400000006f, 0.300000012f, 0.235294119f, 0.192307696f, 0.16216217f, 0.140000001f, 0.123076923f }; NormalizationTest(tflite::BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, radius, bias, alpha, beta); } } // anonymous namespacearmnn-23.08/delegate/test/PackTest.cpp000066400000000000000000000257501446772241200176360ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "PackTestHelper.hpp" #include #include #include #include namespace armnnDelegate { template void PackFp32Axis0Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector expectedOutputShape { 2, 3, 2, 3 }; std::vector> inputValues; inputValues.push_back( { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }); inputValues.push_back( { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }); std::vector expectedOutputValues = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }; PackTest(tflite::BuiltinOperator_PACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 0); } template void PackFp32Axis1Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector expectedOutputShape { 3, 2, 2, 3 }; std::vector> inputValues; inputValues.push_back( { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }); inputValues.push_back( { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }); std::vector expectedOutputValues = { 1, 2, 3, 4, 5, 6, 19, 20, 21, 22, 23, 24, 7, 8, 9, 10, 11, 12, 25, 26, 27, 28, 29, 30, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 35, 36 }; PackTest(tflite::BuiltinOperator_PACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 1); } template void PackFp32Axis2Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector expectedOutputShape { 3, 2, 2, 3 }; std::vector> inputValues; inputValues.push_back( { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }); inputValues.push_back( { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }); std::vector expectedOutputValues = { 1, 2, 3, 19, 20, 21, 4, 5, 6, 22, 23, 24, 7, 8, 9, 25, 26, 27, 10, 11, 12, 28, 29, 30, 13, 14, 15, 31, 32, 33, 16, 17, 18, 34, 35, 36 }; PackTest(tflite::BuiltinOperator_PACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 2); } template void PackFp32Axis3Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector expectedOutputShape { 3, 2, 3, 2 }; std::vector> inputValues; inputValues.push_back( { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 }); inputValues.push_back( { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 }); std::vector expectedOutputValues = { 1, 19, 2, 20, 3, 21, 4, 22, 5, 23, 6, 24, 7, 25, 8, 26, 9, 27, 10, 28, 11, 29, 12, 30, 13, 31, 14, 32, 15, 33, 16, 34, 17, 35, 18, 36 }; PackTest(tflite::BuiltinOperator_PACK, tflite::TensorType_FLOAT32, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 3); } template void PackFp32Inputs3Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 3, 3 }; std::vector expectedOutputShape { 3, 3, 3 }; std::vector> inputValues; inputValues.push_back( { 1, 2, 3, 4, 5, 6, 7, 8, 9 }); inputValues.push_back( { 10, 11, 12, 13, 14, 15, 16, 17, 18 }); inputValues.push_back( { 19, 20, 21, 22, 23, 24, 25, 26, 27 }); std::vector expectedOutputValues = { 1, 2, 3, 10, 11, 12, 19, 20, 21, 4, 5, 6, 13, 14, 15, 22, 23, 24, 7, 8, 9, 16, 17, 18, 25, 26, 27 }; PackTest(tflite::BuiltinOperator_PACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 1); } TEST_SUITE("Pack_CpuAccTests") { // Fp32 TEST_CASE ("Pack_Fp32_Axis0_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis0Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis1_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis1Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis2_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis2Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis3_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis3Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Inputs3_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Inputs3Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Pack_Uint8_Axis0_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis0Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Pack_Uint8_Inputs3_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Inputs3Test(tflite::TensorType_UINT8, backends); } // Uint8 TEST_CASE ("Pack_Int8_Axis0_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Axis0Test(tflite::TensorType_INT8, backends); } TEST_CASE ("Pack_Int8_Inputs3_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; PackFp32Inputs3Test(tflite::TensorType_INT8, backends); } } TEST_SUITE("Pack_GpuAccTests") { // Fp32 TEST_CASE ("Pack_Fp32_Axis0_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis0Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis1_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis1Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis2_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis2Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis3_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis3Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Inputs3_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Inputs3Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Pack_Uint8_Axis0_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis0Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Pack_Uint8_Inputs3_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Inputs3Test(tflite::TensorType_UINT8, backends); } // Int8 TEST_CASE ("Pack_Int8_Axis0_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Axis0Test(tflite::TensorType_INT8, backends); } TEST_CASE ("Pack_Int8_Inputs3_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; PackFp32Inputs3Test(tflite::TensorType_INT8, backends); } } TEST_SUITE("Pack_CpuRefTests") { // Fp32 TEST_CASE ("Pack_Fp32_Axis0_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis0Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis1_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis1Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis2_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis2Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Axis3_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis3Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Pack_Fp32_Inputs3_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Inputs3Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Pack_Uint8_Axis0_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis0Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Pack_Uint8_Inputs3_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Inputs3Test(tflite::TensorType_UINT8, backends); } // Int8 TEST_CASE ("Pack_Int8_Axis0_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Axis0Test(tflite::TensorType_INT8, backends); } TEST_CASE ("Pack_Int8_Inputs3_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; PackFp32Inputs3Test(tflite::TensorType_INT8, backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/PackTestHelper.hpp000066400000000000000000000171371446772241200210030ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreatePackTfLiteModel(tflite::BuiltinOperator packOperatorCode, tflite::TensorType tensorType, std::vector& inputTensorShape, const std::vector & outputTensorShape, const int32_t inputTensorNum, unsigned int axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::vector operatorInputs{}; const std::vector operatorOutputs{inputTensorNum}; std::vector subgraphInputs{}; const std::vector subgraphOutputs{inputTensorNum}; std::vector> tensors(inputTensorNum + 1); for (int i = 0; i < inputTensorNum; ++i) { tensors[i] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input" + std::to_string(i)), quantizationParameters); // Add number of inputs to vector. operatorInputs.push_back(i); subgraphInputs.push_back(i); } // Create output tensor tensors[inputTensorNum] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_PackOptions; flatbuffers::Offset operatorBuiltinOptions = CreatePackOptions(flatBufferBuilder, inputTensorNum, axis).Union(); flatbuffers::Offset packOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&packOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Pack Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, packOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void PackTest(tflite::BuiltinOperator packOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& expectedOutputShape, std::vector>& inputValues, std::vector& expectedOutputValues, unsigned int axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreatePackTfLiteModel(packOperatorCode, tensorType, inputShape, expectedOutputShape, inputValues.size(), axis, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); // Set input data for all input tensors. for (unsigned int i = 0; i < inputValues.size(); ++i) { auto inputTensorValues = inputValues[i]; CHECK(tfLiteInterpreter.FillInputTensor(inputTensorValues, i) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputTensorValues, i) == kTfLiteOk); } CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/PadTest.cpp000066400000000000000000000605461446772241200174660ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "PadTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void Pad2dTest(std::vector& backends, tflite::BuiltinOperator padOperatorCode = tflite::BuiltinOperator_PAD, float pad = 0.0f) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 3, 5, 6 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { 0.0f, 4.0f, 2.0f, -5.0f, 6.0f, 1.0f, 5.0f, -2.0f }; std::vector expectedOutputValues = { pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 0.0f, 4.0f, pad, pad, pad, pad, 2.0f, -5.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 6.0f, 1.0f, pad, pad, pad, pad, 5.0f, -2.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad }; std::vector paddingDim = { 0, 1, 2, 1, 2, 2 }; PadTest(padOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, pad); } void Pad3dTest(std::vector& backends, tflite::BuiltinOperator padOperatorCode = tflite::BuiltinOperator_PAD, float pad = 0.0f) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 3, 5, 6 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { 0.0f, 4.0f, 2.0f, 5.0f, 6.0f, 1.0f, 5.0f, 2.0f }; std::vector expectedOutputValues = { pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 0.0f, 4.0f, pad, pad, pad, pad, 2.0f, 5.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 6.0f, 1.0f, pad, pad, pad, pad, 5.0f, 2.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad }; std::vector paddingDim = { 0, 1, 2, 1, 2, 2 }; PadTest(padOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, pad); } void Pad4dTest(std::vector& backends, tflite::BuiltinOperator padOperatorCode = tflite::BuiltinOperator_PAD, float pad = 0.0f) { // Set input data std::vector inputShape { 2, 2, 3, 2 }; std::vector outputShape { 4, 5, 7, 4 }; std::vector paddingShape { 4, 2 }; std::vector inputValues = { 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, 20.0f, 21.0f, 22.0f, 23.0f }; std::vector expectedOutputValues = { pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 0.0f, 1.0f, pad, pad, 2.0f, 3.0f, pad, pad, 4.0f, 5.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 6.0f, 7.0f, pad, pad, 8.0f, 9.0f, pad, pad, 10.0f, 11.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 12.0f, 13.0f, pad, pad, 14.0f, 15.0f, pad, pad, 16.0f, 17.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, 18.0f, 19.0f, pad, pad, 20.0f, 21.0f, pad, pad, 22.0f, 23.0f, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad, pad }; std::vector paddingDim = { 1, 1, 2, 1, 3, 1, 1, 1 }; PadTest(padOperatorCode, ::tflite::TensorType_FLOAT32, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, pad); } void PadInt8Test(std::vector& backends, tflite::BuiltinOperator padOperatorCode = tflite::BuiltinOperator_PAD, int8_t paddingValue = 0, int8_t p = 3, float quantizationScale = -2.0f, int32_t quantizationOffset = 3) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 3, 5, 6 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { 0, 4, 2, -5, 6, 1, 5, -2 }; std::vector expectedOutputValues = { p, p, p, p, p, p, p, p, p, p, p, p, p, p, 0, 4, p, p, p, p, 2, -5, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, 6, 1, p, p, p, p, 5, -2, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p }; std::vector paddingDim = { 0, 1, 2, 1, 2, 2 }; PadTest(padOperatorCode, ::tflite::TensorType_INT8, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, paddingValue, quantizationScale, quantizationOffset); } void PadUint8Test(std::vector& backends, tflite::BuiltinOperator padOperatorCode = tflite::BuiltinOperator_PAD, uint8_t paddingValue = 0, uint8_t p = 3, float quantizationScale = -2.0f, int32_t quantizationOffset = 3) { // Set input data std::vector inputShape { 2, 2, 2 }; std::vector outputShape { 3, 5, 6 }; std::vector paddingShape { 3, 2 }; std::vector inputValues = { 0, 4, 2, 5, 6, 1, 5, 2 }; std::vector expectedOutputValues = { p, p, p, p, p, p, p, p, p, p, p, p, p, p, 0, 4, p, p, p, p, 2, 5, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, 6, 1, p, p, p, p, 5, 2, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p, p }; std::vector paddingDim = { 0, 1, 2, 1, 2, 2 }; PadTest(padOperatorCode, ::tflite::TensorType_UINT8, backends, inputShape, paddingShape, outputShape, inputValues, paddingDim, expectedOutputValues, paddingValue, quantizationScale, quantizationOffset); } TEST_SUITE("Pad_CpuRefTests") { TEST_CASE ("Pad2d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad2dTest(backends); } TEST_CASE ("Pad3d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad3dTest(backends); } TEST_CASE ("Pad4d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad4dTest(backends); } TEST_CASE ("Pad_Int8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PadInt8Test(backends); } TEST_CASE ("Pad_Uint8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PadUint8Test(backends); } TEST_CASE ("PadV22d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad2dTest(backends, tflite::BuiltinOperator_PADV2, -2.5); } TEST_CASE ("PadV23d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad3dTest(backends, tflite::BuiltinOperator_PADV2, 2.0); } TEST_CASE ("PadV24d_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; Pad4dTest(backends, tflite::BuiltinOperator_PADV2, -1.33); } TEST_CASE ("PadV2_Int8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PadInt8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } TEST_CASE ("PadV2_Uint8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PadUint8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } } // TEST_SUITE("Pad_CpuRefTests") TEST_SUITE("Pad_CpuAccTests") { TEST_CASE ("Pad2d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad2dTest(backends); } TEST_CASE ("Pad3d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad3dTest(backends); } TEST_CASE ("Pad4d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad4dTest(backends); } TEST_CASE ("Pad_Int8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PadInt8Test(backends); } TEST_CASE ("Pad_Uint8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PadUint8Test(backends); } TEST_CASE ("PadV22d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad2dTest(backends, tflite::BuiltinOperator_PADV2, -2.5); } TEST_CASE ("PadV23d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad3dTest(backends, tflite::BuiltinOperator_PADV2, 2.0); } TEST_CASE ("PadV24d_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; Pad4dTest(backends, tflite::BuiltinOperator_PADV2, -1.33); } TEST_CASE ("PadV2_Int8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PadInt8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } TEST_CASE ("PadV2_Uint8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PadUint8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } } // TEST_SUITE("Pad_CpuAccTests") TEST_SUITE("Pad_GpuAccTests") { TEST_CASE ("Pad2d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad2dTest(backends); } TEST_CASE ("Pad3d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad3dTest(backends); } TEST_CASE ("Pad4d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad4dTest(backends); } TEST_CASE ("Pad_Int8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PadInt8Test(backends); } TEST_CASE ("Pad_Uint8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PadUint8Test(backends); } TEST_CASE ("PadV22d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad2dTest(backends, tflite::BuiltinOperator_PADV2, -2.5); } TEST_CASE ("PadV23d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad3dTest(backends, tflite::BuiltinOperator_PADV2, 2.0); } TEST_CASE ("PadV24d_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; Pad4dTest(backends, tflite::BuiltinOperator_PADV2, -1.33); } TEST_CASE ("PadV2_Int8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PadInt8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } TEST_CASE ("PadV2_Uint8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PadUint8Test(backends, tflite::BuiltinOperator_PADV2, -1, -1); } } // TEST_SUITE("Pad_GpuAccTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/PadTestHelper.hpp000066400000000000000000000233151446772241200206240ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { template std::vector CreatePadTfLiteModel( tflite::BuiltinOperator padOperatorCode, tflite::TensorType tensorType, tflite::MirrorPadMode paddingMode, const std::vector& inputTensorShape, const std::vector& paddingTensorShape, const std::vector& outputTensorShape, const std::vector& paddingDim, const std::vector paddingValue, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); auto paddingTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(paddingTensorShape.data(), paddingTensorShape.size()), tflite::TensorType_INT32, 1, flatBufferBuilder.CreateString("padding")); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); std::vector> tensors = { inputTensor, paddingTensor, outputTensor}; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(paddingDim.data()), sizeof(int32_t) * paddingDim.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::vector operatorInputs; std::vector subgraphInputs; tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_PadOptions; flatbuffers::Offset operatorBuiltinOptions; if (padOperatorCode == tflite::BuiltinOperator_PAD) { operatorInputs = {{ 0, 1 }}; subgraphInputs = {{ 0, 1 }}; operatorBuiltinOptions = CreatePadOptions(flatBufferBuilder).Union(); } else if(padOperatorCode == tflite::BuiltinOperator_MIRROR_PAD) { operatorInputs = {{ 0, 1 }}; subgraphInputs = {{ 0, 1 }}; operatorBuiltinOptionsType = BuiltinOptions_MirrorPadOptions; operatorBuiltinOptions = CreateMirrorPadOptions(flatBufferBuilder, paddingMode).Union(); } else if (padOperatorCode == tflite::BuiltinOperator_PADV2) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(paddingValue.data()), sizeof(T)))); const std::vector shape = { 1 }; auto padValueTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(shape.data(), shape.size()), tensorType, 3, flatBufferBuilder.CreateString("paddingValue"), quantizationParameters); tensors.push_back(padValueTensor); operatorInputs = {{ 0, 1, 3 }}; subgraphInputs = {{ 0, 1, 3 }}; operatorBuiltinOptionsType = BuiltinOptions_PadV2Options; operatorBuiltinOptions = CreatePadV2Options(flatBufferBuilder).Union(); } // create operator const std::vector operatorOutputs{ 2 }; flatbuffers::Offset paddingOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&paddingOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Pad Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, padOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void PadTest(tflite::BuiltinOperator padOperatorCode, tflite::TensorType tensorType, const std::vector& backends, const std::vector& inputShape, const std::vector& paddingShape, std::vector& outputShape, std::vector& inputValues, std::vector& paddingDim, std::vector& expectedOutputValues, T paddingValue, float quantScale = 1.0f, int quantOffset = 0, tflite::MirrorPadMode paddingMode = tflite::MirrorPadMode_SYMMETRIC) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreatePadTfLiteModel(padOperatorCode, tensorType, paddingMode, inputShape, paddingShape, outputShape, paddingDim, {paddingValue}, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/Pooling2dTest.cpp000066400000000000000000001240321446772241200206060ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "Pooling2dTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void MaxPool2dFP32PaddingValidTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 1, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 12.0f, 7.0f }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 2, 2, 2, 2); } void MaxPool2dInt8PaddingValidTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 1, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 12, 7 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void MaxPool2dFP32PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 12.0f, 7.0f, 3.0f, -1.0f }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2); } void MaxPool2dInt8PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 12, 7, 3, -1 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void MaxPool2dFP32ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5.0f, -8.0f, -10.0f, 7.0f, -8.0f, -12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 0.0f, 0.0f, 7.0f, 3.0f, 0.0f, 2.0f }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU); } void MaxPool2dInt8ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5, -8, -10, 7, -8, -12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 1, 1, 7, 3, 1, 2 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.0f, 1); } void MaxPool2dFP32Relu6Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, -8.0f, -10.0f, 7.0f, -8.0f, -12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 0.0f, 0.0f, 3.0f, 0.0f }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 1, 1, ::tflite::ActivationFunctionType_RELU6); } void MaxPool2dInt8Relu6Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, -8, -10, 7, -8, -12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 1, 1, 3, 1 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 1, 1, ::tflite::ActivationFunctionType_RELU6, 2.0f, 1); } void MaxPool2dUint8PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { 5, 8, 10, 7, 8, 12, 15, 2, 3, 4, 1, 11 }; std::vector expectedOutputValues = { 12, 15, 4, 11 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void MaxPool2dUint8ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { 12, 8, 10, 15, 8, 5, 7, 2, 3, 4, 1, 11 }; std::vector expectedOutputValues = { 12, 10, 15, 8, 7, 11 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.0f, 1); } void MaxPool2dInt16PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 12, 7, 3, -1 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 0); } void MaxPool2dInt16ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5, -8, -10, 7, -8, -12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 0, 0, 7, 3, 0, 2 }; Pooling2dTest(tflite::BuiltinOperator_MAX_POOL_2D, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.0f, 0); } void AveragePool2dFP32PaddingValidTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 1, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 5.75f, -4.0f }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 2, 2, 2, 2); } void AveragePool2dInt8PaddingValidTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 1, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 6, -4 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void AveragePool2dFP32PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 5.75f, -4.0f, -0.5f, -6.0f }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2); } void AveragePool2dInt8PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 6, -4, -1, -6 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void AveragePool2dFP32ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, -8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, 11.0f }; std::vector expectedOutputValues = { 1.75f, 0.0f, 0.0f, 0.75f, 0.0f, 0.0f }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU); } void AveragePool2dInt8ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5, 8, -10, 7, -8, 12, -15, 2, 3, -4, -1, 11 }; std::vector expectedOutputValues = { 2, 1, 1, 1, 1, 1 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.5f, 1); } void AveragePool2dFP32Relu6Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, -8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, 11.0f }; std::vector expectedOutputValues = { 0.0f, 0.0f, 3.0f, 0.0f }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 1, 1, ::tflite::ActivationFunctionType_RELU6); } void AveragePool2dInt8Relu6Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, -8, 12, -15, 2, 3, -4, -1, 11 }; std::vector expectedOutputValues = { 1, 1, 3, 1 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 1, 1, ::tflite::ActivationFunctionType_RELU6, 2.5f, 1); } void AveragePool2dUint8PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { 5, 8, 10, 7, 8, 12, 15, 2, 3, 4, 1, 11 }; std::vector expectedOutputValues = { 8, 9, 4, 6 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 1); } void AveragePool2dUint8ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { 12, 8, 10, 15, 8, 5, 7, 2, 3, 4, 1, 11 }; std::vector expectedOutputValues = { 8, 8, 9, 5, 4, 5 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.0f, 1); } void AveragePool2dInt16PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { 6, -4, -1, -6 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2, tflite::ActivationFunctionType_NONE, 2.5f, 0); } void AveragePool2dInt16ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5, 8, -10, 7, -8, 12, -15, 2, 3, -4, -1, 11 }; std::vector expectedOutputValues = { 2, 0, 0, 1, 0, 0 }; Pooling2dTest(tflite::BuiltinOperator_AVERAGE_POOL_2D, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU, 2.5f, 0); } void L2Pool2dFP32PaddingValidTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 1, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 8.616844f, 9.721111f }; Pooling2dTest(tflite::BuiltinOperator_L2_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 2, 2, 2, 2); } void L2Pool2dFP32PaddingSameTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { 8.616844f, 9.721111f, 3.535534f, 7.81025f }; Pooling2dTest(tflite::BuiltinOperator_L2_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 2, 2); } void L2Pool2dFP32ReluTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, -8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, 11.0f }; std::vector expectedOutputValues = { 8.616844f, 11.543396f, 9.721111f, 7.632169f, 9.8234415f, 9.367497f }; Pooling2dTest(tflite::BuiltinOperator_L2_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_VALID, 1, 1, 2, 2, ::tflite::ActivationFunctionType_RELU); } void L2Pool2dFP32Relu6Test(std::vector& backends) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 2, 2, 1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, -8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, 11.0f }; std::vector expectedOutputValues = { 5.0f, 6.0f, 3.0f, 1.0f }; Pooling2dTest(tflite::BuiltinOperator_L2_POOL_2D, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, ::tflite::Padding_SAME, 2, 2, 1, 1, ::tflite::ActivationFunctionType_RELU6); } TEST_SUITE("Pooling2d_GpuAccTests") { TEST_CASE ("MaxPooling2d_FP32_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dInt8PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_FP32_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dInt8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dFP32ReluTest(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dInt8ReluTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dFP32Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dInt8Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Uint8_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dUint8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Uint8_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool2dUint8ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dInt8PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dInt8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dFP32ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dFP32Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dInt8ReluTest(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dInt8Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Uint8_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dUint8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Uint8_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool2dUint8ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; L2Pool2dFP32PaddingValidTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; L2Pool2dFP32PaddingSameTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; L2Pool2dFP32ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu6_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; L2Pool2dFP32Relu6Test(backends); } } // TEST_SUITE("Pooling2d_GpuAccTests") TEST_SUITE("Pooling2d_CpuAccTests") { TEST_CASE ("MaxPooling2d_FP32_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dInt8PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_FP32_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dInt8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dFP32ReluTest(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dInt8ReluTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dFP32Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dInt8Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Uint8_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dUint8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Uint8_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool2dUint8ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dInt8PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dInt8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dFP32ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dFP32Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dInt8ReluTest(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dInt8Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Uint8_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dUint8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Uint8_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool2dUint8ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; L2Pool2dFP32PaddingValidTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; L2Pool2dFP32PaddingSameTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; L2Pool2dFP32ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu6_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; L2Pool2dFP32Relu6Test(backends); } } // TEST_SUITE("Pooling2d_CpuAccTests") TEST_SUITE("Pooling2d_CpuRefTests") { TEST_CASE ("MaxPooling2d_FP32_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt8PaddingValidTest(backends); } TEST_CASE ("MaxPooling2d_FP32_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Int8_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dFP32ReluTest(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt8ReluTest(backends); } TEST_CASE ("MaxPooling2d_FP32_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dFP32Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Int8_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt8Relu6Test(backends); } TEST_CASE ("MaxPooling2d_Uint8_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dUint8PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Uint8_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dUint8ReluTest(backends); } TEST_CASE ("MaxPooling2d_Int16_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt16PaddingSameTest(backends); } TEST_CASE ("MaxPooling2d_Int16_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool2dInt16ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt8PaddingValidTest(backends); } TEST_CASE ("AveragePooling2d_FP32_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Int8_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dFP32ReluTest(backends); } TEST_CASE ("AveragePooling2d_FP32_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dFP32Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt8ReluTest(backends); } TEST_CASE ("AveragePooling2d_Int8_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt8Relu6Test(backends); } TEST_CASE ("AveragePooling2d_Uint8_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dUint8PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Uint8_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dUint8ReluTest(backends); } TEST_CASE ("AveragePooling2d_Int16_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt16PaddingSameTest(backends); } TEST_CASE ("AveragePooling2d_Int16_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool2dInt16ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; L2Pool2dFP32PaddingValidTest(backends); } TEST_CASE ("L2Pooling2d_FP32_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; L2Pool2dFP32PaddingSameTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; L2Pool2dFP32ReluTest(backends); } TEST_CASE ("L2Pooling2d_FP32_Relu6_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; L2Pool2dFP32Relu6Test(backends); } } // TEST_SUITE("Pooling2d_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/Pooling2dTestHelper.hpp000066400000000000000000000176201446772241200217570ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreatePooling2dTfLiteModel( tflite::BuiltinOperator poolingOperatorCode, tflite::TensorType tensorType, const std::vector & inputTensorShape, const std::vector & outputTensorShape, tflite::Padding padding = tflite::Padding_SAME, int32_t strideWidth = 0, int32_t strideHeight = 0, int32_t filterWidth = 0, int32_t filterHeight = 0, tflite::ActivationFunctionType fusedActivation = tflite::ActivationFunctionType_NONE, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; flatbuffers::Offset buffers[3] = {CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder)}; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); flatbuffers::Offset tensors[2] { CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters), CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters) }; // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_Pool2DOptions; flatbuffers::Offset operatorBuiltinOptions = CreatePool2DOptions(flatBufferBuilder, padding, strideWidth, strideHeight, filterWidth, filterHeight, fusedActivation).Union(); const std::vector operatorInputs{0}; const std::vector operatorOutputs{1}; flatbuffers::Offset poolingOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs), flatBufferBuilder.CreateVector(operatorOutputs), operatorBuiltinOptionsType, operatorBuiltinOptions); const int subgraphInputs[1] = {0}; const int subgraphOutputs[1] = {1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors, 2), flatBufferBuilder.CreateVector(subgraphInputs, 1), flatBufferBuilder.CreateVector(subgraphOutputs, 1), flatBufferBuilder.CreateVector(&poolingOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Pooling2d Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, poolingOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers, 3)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void Pooling2dTest(tflite::BuiltinOperator poolingOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, tflite::Padding padding = tflite::Padding_SAME, int32_t strideWidth = 0, int32_t strideHeight = 0, int32_t filterWidth = 0, int32_t filterHeight = 0, tflite::ActivationFunctionType fusedActivation = tflite::ActivationFunctionType_NONE, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreatePooling2dTfLiteModel(poolingOperatorCode, tensorType, inputShape, outputShape, padding, strideWidth, strideHeight, filterWidth, filterHeight, fusedActivation, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/Pooling3dTest.cpp000066400000000000000000000342451446772241200206150ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "Pooling3dTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { // Pool3D custom op was only added in tflite r2.6. #if defined(ARMNN_POST_TFLITE_2_5) void MaxPool3dFP32PaddingValidTest(std::vector& backends) { // Set input and expected output data std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 1, 2, 3, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 6, 6, 4 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kMax"; TfLitePadding padding = kTfLitePaddingValid; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 2, 2); } void MaxPool3dFP32PaddingSameTest(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 2, 3, 4, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 6, 6, 4, 4, 6, 6, 6, 6, 4, 5, 6, 6, 6, 6, 4, 4 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kMax"; TfLitePadding padding = kTfLitePaddingSame; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 2, 2); } void MaxPool3dFP32H1Test(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 1, 3, 3, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 2, 3 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kMax"; TfLitePadding padding = kTfLitePaddingValid; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 1, 2); } void MaxPool3dFP32Test(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 2, 3, 4, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 6, 6 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kMax"; TfLitePadding padding = kTfLitePaddingUnknown; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 2, 2); } void AveragePool3dFP32PaddingValidTest(std::vector& backends) { // Set input data and expected output data. std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 1, 2, 3, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 3.5, 3, 2.5 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kAverage"; TfLitePadding padding = kTfLitePaddingValid; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 2, 2); } void AveragePool3dFP32PaddingSameTest(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 4, 2, 3, 1, 1 }; std::vector outputShape = { 4, 2, 3, 1, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 3, 4, 4.5, 4.5, 5.5, 6, 3, 4, 4.5, 4.5, 5.5, 6, 3, 4, 4.5, 4.5 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kAverage"; TfLitePadding padding = kTfLitePaddingSame; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 1, 1, 1, 2, 2, 2); } void AveragePool3dFP32H1Test(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 1, 2, 3, 4, 1 }; std::vector outputShape = { 1, 1, 2, 2, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 1.5, 3.5 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kAverage"; TfLitePadding padding = kTfLitePaddingUnknown; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 2, 2, 2, 2, 1, 2); } void AveragePool3dFP32Test(std::vector& backends) { // Set input data and expected output data std::vector inputShape = { 4, 3, 2, 1, 1 }; std::vector outputShape = { 1, 2, 2, 4, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues = { 3.125, 4.25 }; // poolType string required to create the correct pooling operator // Padding type required to create the padding in custom options std::string poolType = "kMax"; TfLitePadding padding = kTfLitePaddingUnknown; Pooling3dTest(poolType, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, padding, 2, 2, 2, 2, 2, 2); } TEST_SUITE("Pooling3d_GpuAccTests") { TEST_CASE ("MaxPooling3d_FP32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool3dFP32Test(backends); } TEST_CASE ("MaxPooling3d_FP32_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool3dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling3d_FP32_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool3dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling3d_FP32_H1_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; MaxPool3dFP32H1Test(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingValid_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool3dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingSame_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool3dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling3d_FP32_H1_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; AveragePool3dFP32H1Test(backends); } } // TEST_SUITE("Pooling3d_GpuAccTests") TEST_SUITE("Pooling3d_CpuAccTests") { TEST_CASE ("MaxPooling3d_FP32_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool3dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling3d_FP32_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool3dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling3d_FP32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool3dFP32Test(backends); } TEST_CASE ("MaxPooling3d_FP32_H1_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; MaxPool3dFP32H1Test(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingValid_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool3dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingSame_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool3dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling3d_FP32_H1_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; AveragePool3dFP32H1Test(backends); } } // TEST_SUITE("Pooling3d_CpuAccTests") TEST_SUITE("Pooling3d_CpuRefTests") { TEST_CASE ("MaxPooling3d_FP32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool3dFP32Test(backends); } TEST_CASE ("MaxPooling3d_FP32_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool3dFP32PaddingValidTest(backends); } TEST_CASE ("MaxPooling3d_FP32_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool3dFP32PaddingSameTest(backends); } TEST_CASE ("MaxPooling3d_FP32_H1_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; MaxPool3dFP32H1Test(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingValid_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool3dFP32PaddingValidTest(backends); } TEST_CASE ("AveragePooling3d_FP32_PaddingSame_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool3dFP32PaddingSameTest(backends); } TEST_CASE ("AveragePooling3d_FP32_H1_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; AveragePool3dFP32H1Test(backends); } } // TEST_SUITE("Pooling3d_CpuRefTests") #endif }armnn-23.08/delegate/test/Pooling3dTestHelper.hpp000066400000000000000000000260271446772241200217610ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include #include #include namespace { #if defined(ARMNN_POST_TFLITE_2_5) std::vector CreateCustomOptions(int, int, int, int, int, int, TfLitePadding); std::vector CreatePooling3dTfLiteModel( std::string poolType, tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& outputTensorShape, TfLitePadding padding = kTfLitePaddingSame, int32_t strideWidth = 0, int32_t strideHeight = 0, int32_t strideDepth = 0, int32_t filterWidth = 0, int32_t filterHeight = 0, int32_t filterDepth = 0, tflite::ActivationFunctionType fusedActivation = tflite::ActivationFunctionType_NONE, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); // Create the input and output tensors std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("output"), quantizationParameters); // Create the custom options from the function below std::vector customOperatorOptions = CreateCustomOptions(strideHeight, strideWidth, strideDepth, filterHeight, filterWidth, filterDepth, padding); // opCodeIndex is created as a uint8_t to avoid map lookup uint8_t opCodeIndex = 0; // Set the operator name based on the PoolType passed in from the test case std::string opName = ""; if (poolType == "kMax") { opName = "MaxPool3D"; } else { opName = "AveragePool3D"; } // To create a custom operator code you pass in the builtin code for custom operators and the name of the custom op flatbuffers::Offset operatorCode = CreateOperatorCodeDirect(flatBufferBuilder, tflite::BuiltinOperator_CUSTOM, opName.c_str()); // Create the Operator using the opCodeIndex and custom options. Also sets builtin options to none. const std::vector operatorInputs{ 0 }; const std::vector operatorOutputs{ 1 }; flatbuffers::Offset poolingOperator = CreateOperator(flatBufferBuilder, opCodeIndex, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), tflite::BuiltinOptions_NONE, 0, flatBufferBuilder.CreateVector(customOperatorOptions), tflite::CustomOptionsFormat_FLEXBUFFERS); // Create the subgraph using the operator created above. const std::vector subgraphInputs{ 0 }; const std::vector subgraphOutputs{ 1 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&poolingOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Pooling3d Operator Model"); // Create the model using operatorCode and the subgraph. flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void Pooling3dTest(std::string poolType, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, TfLitePadding padding = kTfLitePaddingSame, int32_t strideWidth = 0, int32_t strideHeight = 0, int32_t strideDepth = 0, int32_t filterWidth = 0, int32_t filterHeight = 0, int32_t filterDepth = 0, tflite::ActivationFunctionType fusedActivation = tflite::ActivationFunctionType_NONE, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; // Create the single op model buffer std::vector modelBuffer = CreatePooling3dTfLiteModel(poolType, tensorType, inputShape, outputShape, padding, strideWidth, strideHeight, strideDepth, filterWidth, filterHeight, filterDepth, fusedActivation, quantScale, quantOffset); std::string opType = ""; if (poolType == "kMax") { opType = "MaxPool3D"; } else { opType = "AveragePool3D"; } // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer, opType); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends, opType); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // Function to create the flexbuffer custom options for the custom pooling3d operator. std::vector CreateCustomOptions(int strideHeight, int strideWidth, int strideDepth, int filterHeight, int filterWidth, int filterDepth, TfLitePadding padding) { auto flex_builder = std::make_unique(); size_t map_start = flex_builder->StartMap(); flex_builder->String("data_format", "NDHWC"); // Padding is created as a key and padding type. Only VALID and SAME supported if (padding == kTfLitePaddingValid) { flex_builder->String("padding", "VALID"); } else { flex_builder->String("padding", "SAME"); } // Vector of filter dimensions in order ( 1, Depth, Height, Width, 1 ) auto start = flex_builder->StartVector("ksize"); flex_builder->Add(1); flex_builder->Add(filterDepth); flex_builder->Add(filterHeight); flex_builder->Add(filterWidth); flex_builder->Add(1); // EndVector( start, bool typed, bool fixed) flex_builder->EndVector(start, true, false); // Vector of stride dimensions in order ( 1, Depth, Height, Width, 1 ) auto stridesStart = flex_builder->StartVector("strides"); flex_builder->Add(1); flex_builder->Add(strideDepth); flex_builder->Add(strideHeight); flex_builder->Add(strideWidth); flex_builder->Add(1); // EndVector( stridesStart, bool typed, bool fixed) flex_builder->EndVector(stridesStart, true, false); flex_builder->EndMap(map_start); flex_builder->Finish(); return flex_builder->GetBuffer(); } #endif } // anonymous namespace armnn-23.08/delegate/test/PreluTest.cpp000066400000000000000000000070401446772241200200370ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "PreluTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void PreluFloatSimpleTest(std::vector & backends, bool isAlphaConst, bool isDynamicOutput = false) { std::vector inputShape { 1, 2, 3 }; std::vector alphaShape { 1 }; std::vector outputShape { 1, 2, 3 }; if (isDynamicOutput) { outputShape.clear(); } std::vector inputData = { -14.f, 2.f, 0.f, 1.f, -5.f, 14.f }; std::vector alphaData = { 0.5f }; std::vector expectedOutput = { -7.f, 2.f, 0.f, 1.f, -2.5f, 14.f }; PreluTest(tflite::BuiltinOperator_PRELU, ::tflite::TensorType_FLOAT32, backends, inputShape, alphaShape, outputShape, inputData, alphaData, expectedOutput, isAlphaConst); } TEST_SUITE("Prelu_CpuRefTests") { TEST_CASE ("PreluFp32SimpleConstTest_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PreluFloatSimpleTest(backends, true); } TEST_CASE ("PreluFp32SimpleTest_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PreluFloatSimpleTest(backends, false); } TEST_CASE ("PreluFp32SimpleConstDynamicTest_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PreluFloatSimpleTest(backends, true, true); } TEST_CASE ("PreluFp32SimpleDynamicTest_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; PreluFloatSimpleTest(backends, false, true); } } // TEST_SUITE("Prelu_CpuRefTests") TEST_SUITE("Prelu_CpuAccTests") { TEST_CASE ("PreluFp32SimpleConstTest_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PreluFloatSimpleTest(backends, true); } TEST_CASE ("PreluFp32SimpleTest_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PreluFloatSimpleTest(backends, false); } TEST_CASE ("PreluFp32SimpleConstDynamicTest_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PreluFloatSimpleTest(backends, true, true); } TEST_CASE ("PreluFp32SimpleDynamicTest_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; PreluFloatSimpleTest(backends, false, true); } } // TEST_SUITE("Prelu_CpuAccTests") TEST_SUITE("Prelu_GpuAccTests") { TEST_CASE ("PreluFp32SimpleConstTest_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PreluFloatSimpleTest(backends, true); } TEST_CASE ("PreluFp32SimpleTest_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PreluFloatSimpleTest(backends, false); } TEST_CASE ("PreluFp32SimpleConstDynamicTest_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PreluFloatSimpleTest(backends, true, true); } TEST_CASE ("PreluFp32SimpleDynamicTest_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; PreluFloatSimpleTest(backends, false, true); } } // TEST_SUITE("Prelu_GpuAccTests") }armnn-23.08/delegate/test/PreluTestHelper.hpp000066400000000000000000000174621446772241200212150ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreatePreluTfLiteModel(tflite::BuiltinOperator preluOperatorCode, tflite::TensorType tensorType, const std::vector& inputShape, const std::vector& alphaShape, const std::vector& outputShape, std::vector& alphaData, bool alphaIsConstant) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(alphaData.data()), sizeof(float) * alphaData.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ 1.0f }), flatBufferBuilder.CreateVector({ 0 })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputShape.data(), inputShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); auto alphaTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(alphaShape.data(), alphaShape.size()), tensorType, 2, flatBufferBuilder.CreateString("alpha"), quantizationParameters); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputShape.data(), outputShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); std::vector> tensors = { inputTensor, alphaTensor, outputTensor }; const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset preluOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size())); std::vector subgraphInputs{0}; if (!alphaIsConstant) { subgraphInputs.push_back(1); } const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&preluOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Prelu Operator Model"); flatbuffers::Offset opCode = CreateOperatorCode(flatBufferBuilder, preluOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&opCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void PreluTest(tflite::BuiltinOperator preluOperatorCode, tflite::TensorType tensorType, const std::vector& backends, const std::vector& inputShape, const std::vector& alphaShape, std::vector& outputShape, std::vector& inputData, std::vector& alphaData, std::vector& expectedOutput, bool alphaIsConstant) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreatePreluTfLiteModel(preluOperatorCode, tensorType, inputShape, alphaShape, outputShape, alphaData, alphaIsConstant); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputData, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputData, 0) == kTfLiteOk); // Set alpha data if not constant if (!alphaIsConstant) { CHECK(tfLiteInterpreter.FillInputTensor(alphaData, 1) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(alphaData, 1) == kTfLiteOk); } CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutput); // Don't compare shapes on dynamic output tests, as output shape gets cleared. if(!outputShape.empty()) { std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); } tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/QuantizationTest.cpp000066400000000000000000000315451446772241200214450ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "QuantizationTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // Dequantize operator test functions. void DequantizeUint8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; // Set input and output data std::vector inputValues { 0, 1, 2, 3, // Lower bounds 252, 253, 254, 255 // Upper bounds }; std::vector expectedOutputValues { 0.f, 1.f, 2.f, 3.f, 252.f, 253.f, 254.f, 255.f }; QuantizationTest(tflite::BuiltinOperator_DEQUANTIZE, ::tflite::TensorType_UINT8, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void DequantizeInt8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1, 0, 1, 2, -128, -127, 126, 127 }; std::vector expectedOutputValues { -1.f, 0.f, 1.f, 2.f, -128.f, -127.f, 126.f, 127.f }; QuantizationTest(tflite::BuiltinOperator_DEQUANTIZE, ::tflite::TensorType_INT8, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void DequantizeInt16Test(std::vector& backends) { std::vector inputShape { 2, 5 }; std::vector outputShape { 2, 5 }; std::vector inputValues { -1, 0, 1, 2, -32768, -16384, 16384, 32767 }; std::vector expectedOutputValues { -1.f, 0.f, 1.f, 2.f, -32768.f, -16384.f, 16384.f, 32767.f }; QuantizationTest(tflite::BuiltinOperator_DEQUANTIZE, ::tflite::TensorType_INT16, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues); } // Quantize operator test functions. void QuantizeFloat32Uint8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; // Set input and output data std::vector inputValues { -1.f, 0.f, 1.f, 2.f, // Lower bounds 252.f, 253.f, 255.f, 256.f // Upper bounds }; std::vector expectedOutputValues { 0, 0, 1, 2, 252, 253, 255, 255 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_FLOAT32, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeFloat32Int8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1.f, 0.f, 1.f, 2.f, -128.5f, -127.f, 126.f, 127.5f }; std::vector expectedOutputValues { -1, 0, 1, 2, -128, -127, 126, 127 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_FLOAT32, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeFloat32Int16Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1.f, 0.f, 1.f, 2.f, -32768.5f, -16384.f, 16384.f, 32767.5f }; std::vector expectedOutputValues { -1, 0, 1, 2, -32768, -16384, 16384, 32767 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_FLOAT32, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeInt16Int16Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1, 0, 1, 2, -32768, -16384, 16384, 32767 }; std::vector expectedOutputValues { -1, 0, 1, 2, -32768, -16384, 16384, 32767 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_INT16, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeInt16Int8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1, 0, 1, 2, -32768, -16384, 16384, 32767 }; std::vector expectedOutputValues { -1, 0, 1, 2, -128, -128, 127, 127 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_INT16, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeInt8Uint8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { -1, 0, 1, 2, -128, -127, 126, 127 }; std::vector expectedOutputValues { 0, 0, 1, 2, 0, 0, 126, 127 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_INT8, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues); } void QuantizeUint8Int8Test(std::vector& backends) { std::vector inputShape { 2, 4 }; std::vector outputShape { 2, 4 }; std::vector inputValues { 0, 1, 2, 3, 126, 127, 254, 255 }; std::vector expectedOutputValues { 0, 1, 2, 3, 126, 127, 127, 127 }; QuantizationTest(tflite::BuiltinOperator_QUANTIZE, ::tflite::TensorType_UINT8, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues); } TEST_SUITE("CpuRef_QuantizationTests") { TEST_CASE ("DEQUANTIZE_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DequantizeUint8Test(backends); } TEST_CASE ("DEQUANTIZE_INT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DequantizeInt8Test(backends); } TEST_CASE ("DEQUANTIZE_INT16_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DequantizeInt16Test(backends); } TEST_CASE ("QUANTIZE_FLOAT32_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeFloat32Uint8Test(backends); } TEST_CASE ("QUANTIZE_FLOAT32_INT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeFloat32Int8Test(backends); } TEST_CASE ("QUANTIZE_FLOAT32_INT16_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeFloat32Int16Test(backends); } TEST_CASE ("QUANTIZE_INT16_INT16_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeInt16Int16Test(backends); } TEST_CASE ("QUANTIZE_INT16_INT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeInt16Int8Test(backends); } TEST_CASE ("QUANTIZE_INT8_UINT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeInt8Uint8Test(backends); } TEST_CASE ("QUANTIZE_UINT8_INT8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; QuantizeUint8Int8Test(backends); } } TEST_SUITE("CpuAcc_QuantizationTests") { // Dequantize Operator Tests TEST_CASE ("DEQUANTIZE_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DequantizeUint8Test(backends); } TEST_CASE ("DEQUANTIZE_INT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DequantizeInt8Test(backends); } TEST_CASE ("DEQUANTIZE_INT16_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DequantizeInt16Test(backends); } // Quantize Operator Tests TEST_CASE ("QUANTIZE_FLOAT32_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; QuantizeFloat32Uint8Test(backends); } TEST_CASE ("QUANTIZE_FLOAT32_INT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; QuantizeFloat32Int8Test(backends); } TEST_CASE ("QUANTIZE_INT8_UINT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; QuantizeInt8Uint8Test(backends); } TEST_CASE ("QUANTIZE_UINT8_INT8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; QuantizeUint8Int8Test(backends); } } TEST_SUITE("GpuAcc_QuantizationTests") { // Dequantize Operator Tests TEST_CASE ("DEQUANTIZE_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DequantizeUint8Test(backends); } TEST_CASE ("DEQUANTIZE_INT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DequantizeInt8Test(backends); } TEST_CASE ("DEQUANTIZE_INT16_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DequantizeInt16Test(backends); } // Quantize Operator Tests TEST_CASE ("QUANTIZE_FLOAT32_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; QuantizeFloat32Uint8Test(backends); } TEST_CASE ("QUANTIZE_FLOAT32_INT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; QuantizeFloat32Int8Test(backends); } TEST_CASE ("QUANTIZE_INT8_UINT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; QuantizeInt8Uint8Test(backends); } TEST_CASE ("QUANTIZE_UINT8_INT8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; QuantizeUint8Int8Test(backends); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/QuantizationTestHelper.hpp000066400000000000000000000176311446772241200226120ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateQuantizationTfLiteModel(tflite::BuiltinOperator quantizationOperatorCode, tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, const std::vector & inputTensorShape, const std::vector & outputTensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset }), QuantizationDetails_CustomQuantization); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), outputTensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOptions = 0; switch (quantizationOperatorCode) { case BuiltinOperator_QUANTIZE: { operatorBuiltinOptionsType = BuiltinOptions_QuantizeOptions; operatorBuiltinOptions = CreateQuantizeOptions(flatBufferBuilder).Union(); break; } case BuiltinOperator_DEQUANTIZE: { operatorBuiltinOptionsType = BuiltinOptions_DequantizeOptions; operatorBuiltinOptions = CreateDequantizeOptions(flatBufferBuilder).Union(); break; } default: break; } const std::vector operatorInputs{0}; const std::vector operatorOutputs{1}; flatbuffers::Offset quantizationOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{0}; const std::vector subgraphOutputs{1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&quantizationOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Quantization Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, quantizationOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void QuantizationTest(tflite::BuiltinOperator quantizeOperatorCode, tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, std::vector& backends, std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateQuantizationTfLiteModel(quantizeOperatorCode, inputTensorType, outputTensorType, inputShape, outputShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/RedefineTestHelper.hpp000066400000000000000000000406301446772241200216400ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateReshapeTfLiteModel( tflite::BuiltinOperator redefineOperatorCode, tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& outputTensorShape, const std::vector& targetShape, bool useOption = true, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); std::vector> tensors; std::vector operatorInputs; std::vector subgraphInputs; flatbuffers::Offset operatorBuiltinOptions; if (useOption) { buffers.push_back(CreateBuffer(flatBufferBuilder)); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); tensors = { inputTensor, outputTensor}; operatorInputs = {0}; subgraphInputs = {0}; operatorBuiltinOptions = CreateReshapeOptions( flatBufferBuilder, flatBufferBuilder.CreateVector(targetShape.data(), targetShape.size())).Union(); } else { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(targetShape.data()), sizeof(int32_t) * targetShape.size()))); int32_t size = static_cast(targetShape.size()); auto shapeTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector( { size } ), tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("shape")); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); tensors = { inputTensor, outputTensor, shapeTensor }; operatorInputs = {0, 2}; subgraphInputs = {0, 2}; operatorBuiltinOptions = CreateReshapeOptions(flatBufferBuilder).Union(); } // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_ReshapeOptions; const std::vector operatorOutputs{1}; flatbuffers::Offset redefineOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphOutputs{1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&redefineOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Reshape Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, redefineOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } std::vector CreateRedefineTfLiteModel( tflite::BuiltinOperator redefineOperatorCode, tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& outputTensorShape, const std::vector& squeezeOrAxisData, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); auto inputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); std::vector> tensors; std::vector operatorInputs; std::vector subgraphInputs; flatbuffers::Offset operatorBuiltinOptions; tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_SqueezeOptions; if (redefineOperatorCode == tflite::BuiltinOperator_SQUEEZE) { buffers.push_back(CreateBuffer(flatBufferBuilder)); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); tensors = { inputTensor, outputTensor}; operatorInputs = {0}; subgraphInputs = {0}; operatorBuiltinOptions = CreateSqueezeOptions(flatBufferBuilder, flatBufferBuilder.CreateVector(squeezeOrAxisData.data(), squeezeOrAxisData.size())).Union(); operatorBuiltinOptionsType = BuiltinOptions_SqueezeOptions; } else if (redefineOperatorCode == tflite::BuiltinOperator_EXPAND_DIMS) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(squeezeOrAxisData.data()), sizeof(int32_t) * squeezeOrAxisData.size()))); auto shapeTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector( { 1 } ), tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("axis")); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto outputTensor = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); tensors = { inputTensor, outputTensor, shapeTensor }; operatorInputs = {0, 2}; subgraphInputs = {0, 2}; operatorBuiltinOptions = CreateExpandDimsOptions(flatBufferBuilder).Union(); operatorBuiltinOptionsType = BuiltinOptions_ExpandDimsOptions; } const std::vector operatorOutputs{1}; flatbuffers::Offset redefineOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphOutputs{1}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&redefineOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Redefine Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, redefineOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void RedefineTest(tflite::BuiltinOperator redefineOperatorCode, tflite::TensorType tensorType, const std::vector& backends, const std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, std::vector& additionalData, bool useOption = true, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer; if (redefineOperatorCode == tflite::BuiltinOperator_EXPAND_DIMS) { modelBuffer = CreateRedefineTfLiteModel(redefineOperatorCode, tensorType, inputShape, outputShape, additionalData, quantScale, quantOffset); } else if (redefineOperatorCode == tflite::BuiltinOperator_RESHAPE) { modelBuffer = CreateReshapeTfLiteModel(redefineOperatorCode, tensorType, inputShape, outputShape, additionalData, useOption, quantScale, quantOffset); } else if (redefineOperatorCode == tflite::BuiltinOperator_SQUEEZE) { modelBuffer = CreateRedefineTfLiteModel(redefineOperatorCode, tensorType, inputShape, outputShape, additionalData, quantScale, quantOffset); } // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ReduceTest.cpp000066400000000000000000000326461446772241200201710ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ReduceTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void ReduceUint8KeepDimsTest(tflite::BuiltinOperator reduceOperatorCode, std::vector& backends, std::vector& expectedOutputValues) { std::vector input0Shape { 1, 1, 2, 3 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1, 1, 3 }; std::vector input0Values { 1, 2, 3, 4, 3, 1 }; // Inputs std::vector input1Values { 2 }; // Axis ReduceTest(reduceOperatorCode, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, true); } void ReduceUint8Test(tflite::BuiltinOperator reduceOperatorCode, std::vector& backends, std::vector& expectedOutputValues) { std::vector input0Shape { 1, 1, 2, 3 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1, 3 }; std::vector input0Values { 1, 2, 3, 4, 3, 1 }; // Inputs std::vector input1Values { 2 }; // Axis ReduceTest(reduceOperatorCode, ::tflite::TensorType_UINT8, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, false); } void ReduceFp32KeepDimsTest(tflite::BuiltinOperator reduceOperatorCode, std::vector& backends, std::vector& expectedOutputValues) { std::vector input0Shape { 1, 1, 2, 3 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1, 1, 3 }; std::vector input0Values { 1001.0f, 11.0f, 1003.0f, 10.0f, 1002.0f, 12.0f }; // Inputs std::vector input1Values { 2 }; // Axis ReduceTest(reduceOperatorCode, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, true); } void ReduceFp32Test(tflite::BuiltinOperator reduceOperatorCode, std::vector& backends, std::vector& expectedOutputValues) { std::vector input0Shape { 1, 1, 2, 3 }; std::vector input1Shape { 1 }; std::vector expectedOutputShape { 1, 1, 3 }; std::vector input0Values { 1001.0f, 11.0f, 1003.0f, 10.0f, 1002.0f, 12.0f }; // Inputs std::vector input1Values { 2 }; // Axis ReduceTest(reduceOperatorCode, ::tflite::TensorType_FLOAT32, backends, input0Shape, input1Shape, expectedOutputShape, input0Values, input1Values, expectedOutputValues, false); } // REDUCE_MAX Tests TEST_SUITE("ReduceMax_CpuRefTests") { TEST_CASE ("ReduceMax_Uint8_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } } // End of ReduceMax_CpuRefTests TEST_SUITE("ReduceMax_CpuAccTests") { TEST_CASE ("ReduceMax_Uint8_KeepDims_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_KeepDims_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } } // End of ReduceMax_CpuAccTests TEST_SUITE("ReduceMax_GpuAccTests") { TEST_CASE ("ReduceMax_Uint8_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 4, 3, 3 }; ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } TEST_CASE ("ReduceMax_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, backends, expectedOutputValues); } } // End of ReduceMax_GpuAccTests // REDUCE_MIN Tests TEST_SUITE("ReduceMin_CpuRefTests") { TEST_CASE ("ReduceMin_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, backends, expectedOutputValues); } } // End of ReduceMin_CpuRefTests TEST_SUITE("ReduceMin_CpuAccTests") { TEST_CASE ("ReduceMin_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, backends, expectedOutputValues); } } // End of ReduceMin_CpuAccTests TEST_SUITE("ReduceMin_GpuAccTests") { TEST_CASE ("ReduceMin_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, backends, expectedOutputValues); } } // End of ReduceMin_GpuAccTests // SUM Tests TEST_SUITE("Sum_CpuRefTests") { TEST_CASE ("Sum_Uint8_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 5, 5, 4 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } TEST_CASE ("Sum_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; ReduceFp32Test(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } } // End of Sum_CpuRefTests TEST_SUITE("Sum_CpuAccTests") { TEST_CASE ("Sum_Uint8_KeepDims_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 5, 5, 4 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } TEST_CASE ("Sum_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; ReduceFp32Test(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } } // End of Sum_CpuAccTests TEST_SUITE("Sum_GpuAccTests") { TEST_CASE ("Sum_Uint8_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 5, 5, 4 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } TEST_CASE ("Sum_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; ReduceFp32Test(tflite::BuiltinOperator_SUM, backends, expectedOutputValues); } } // End of Sum_GpuAccTests // PROD Tests TEST_SUITE("Prod_CpuRefTests") { TEST_CASE ("Prod_Uint8_KeepDims_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 4, 6, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } TEST_CASE ("Prod_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; std::vector expectedOutputValues { 10010.0f, 11022.0f, 12036.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } } // End of Prod_CpuRefTests TEST_SUITE("Prod_CpuAccTests") { TEST_CASE ("Prod_Uint8_KeepDims_CpuAcc_Test" ) { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 4, 6, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } TEST_CASE ("Prod_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; std::vector expectedOutputValues { 10010.0f, 11022.0f, 12036.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } } // End of Prod_CpuAccTests TEST_SUITE("Prod_GpuAccTests") { TEST_CASE ("Prod_Uint8_KeepDims_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 4, 6, 3 }; ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } TEST_CASE ("Prod_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; std::vector expectedOutputValues { 10010.0f, 11022.0f, 12036.0f }; ReduceFp32Test(tflite::BuiltinOperator_REDUCE_PROD, backends, expectedOutputValues); } } // End of Prod_GpuAccTests } // namespace armnnDelegatearmnn-23.08/delegate/test/ReduceTestHelper.hpp000066400000000000000000000241171446772241200213300ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateReduceTfLiteModel(tflite::BuiltinOperator reduceOperatorCode, tflite::TensorType tensorType, std::vector& input0TensorShape, std::vector& input1TensorShape, const std::vector & outputTensorShape, std::vector& axisData, const bool keepDims, float quantScale = 1.0f, int quantOffset = 0, bool kTfLiteNoQuantizationForQuantized = false) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; flatbuffers::Offset buffers[4] = { CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(axisData.data()), sizeof(int32_t) * axisData.size())), CreateBuffer(flatBufferBuilder) }; flatbuffers::Offset quantizationParametersAxis = CreateQuantizationParameters(flatBufferBuilder); flatbuffers::Offset quantizationParameters; if (kTfLiteNoQuantizationForQuantized) { if ((quantScale == 1 || quantScale == 0) && quantOffset == 0) { // Creates quantization parameter with quantization.type = kTfLiteNoQuantization quantizationParameters = CreateQuantizationParameters(flatBufferBuilder); } else { // Creates quantization parameter with quantization.type != kTfLiteNoQuantization quantizationParameters = CreateQuantizationParameters( flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); } } else { quantizationParameters = CreateQuantizationParameters( flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); } std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input1TensorShape.data(), input1TensorShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("axis"), quantizationParametersAxis); // Create output tensor tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 3, flatBufferBuilder.CreateString("output"), quantizationParameters); // Create operator. Reduce operations MIN, MAX, SUM, MEAN, PROD uses ReducerOptions. tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_ReducerOptions; flatbuffers::Offset operatorBuiltinOptions = CreateReducerOptions(flatBufferBuilder, keepDims).Union(); const std::vector operatorInputs{ {0, 1} }; const std::vector operatorOutputs{ 2 }; flatbuffers::Offset reduceOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1} }; const std::vector subgraphOutputs{ 2 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&reduceOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Reduce Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, reduceOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers, 4)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ReduceTest(tflite::BuiltinOperator reduceOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& input0Shape, std::vector& input1Shape, std::vector& expectedOutputShape, std::vector& input0Values, std::vector& input1Values, std::vector& expectedOutputValues, const bool keepDims, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBufferArmNN = CreateReduceTfLiteModel(reduceOperatorCode, tensorType, input0Shape, input1Shape, expectedOutputShape, input1Values, keepDims, quantScale, quantOffset, false); std::vector modelBufferTFLite = CreateReduceTfLiteModel(reduceOperatorCode, tensorType, input0Shape, input1Shape, expectedOutputShape, input1Values, keepDims, quantScale, quantOffset, true); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBufferTFLite); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBufferArmNN, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input0Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ReshapeTest.cpp000066400000000000000000000401501446772241200203360ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "RedefineTestHelper.hpp" #include #include #include #include #include using Half = half_float::half; namespace armnnDelegate { void ReshapeSimpleTest(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 3, 2, 2 }; std::vector targetShape { 1, 3, 2, 2 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption); } using namespace half_float::literal; void ReshapeSimpleFloat16Test(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 3, 2, 2 }; std::vector targetShape { 1, 3, 2, 2 }; std::vector inputValues = { 5._h, -8._h, -10._h, 7._h, 8._h, 12._h, -15._h, 2._h, 3._h, -4._h, -1._h, -11._h }; std::vector expectedOutputValues = { 5._h, -8._h, -10._h, 7._h, 8._h, 12._h, -15._h, 2._h, 3._h, -4._h, -1._h, -11._h }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_FLOAT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption); } void ReshapeReduceDimTest(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 1, 4, 3 }; std::vector targetShape { 1, 4, 3 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption); } void ReshapeFlattenTest(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 6, 2 }; std::vector targetShape { -1, 2 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption); } void ReshapeFlattenAllTest(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 12 }; std::vector targetShape { -1 }; std::vector inputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; std::vector expectedOutputValues = { -5.0f, 8.0f, -10.0f, 7.0f, 8.0f, 12.0f, -15.0f, 2.0f, 3.0f, -4.0f, -1.0f, -11.0f }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption); } void ReshapeInt8Test(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 6, 2 }; std::vector targetShape { -1, 2 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_INT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption, 2.5f, 1); } void ReshapeUint8Test(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 6, 2 }; std::vector targetShape { -1, 2 }; std::vector inputValues = { 5, 8, 10, 7, 8, 12, 15, 2, 3, 4, 1, 11 }; std::vector expectedOutputValues = { 5, 8, 10, 7, 8, 12, 15, 2, 3, 4, 1, 11 }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption, 2.5f, 1); } void ReshapeInt16Test(std::vector& backends, bool useOption = true) { // Set input data std::vector inputShape { 1, 3, 4, 1 }; std::vector outputShape { 6, 2 }; std::vector targetShape { -1, 2 }; std::vector inputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; std::vector expectedOutputValues = { -5, 8, -10, 7, 8, 12, -15, 2, 3, -4, -1, -11 }; RedefineTest(tflite::BuiltinOperator_RESHAPE, ::tflite::TensorType_INT16, backends, inputShape, outputShape, inputValues, expectedOutputValues, targetShape, useOption, 2.5f, 0); } TEST_SUITE("Reshape_GpuAccTests") { TEST_CASE ("Reshape_Simple_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeSimpleTest(backends); } TEST_CASE ("Reshape_ReduceDimension_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeReduceDimTest(backends); } TEST_CASE ("Reshape_Flatten_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeFlattenTest(backends); } TEST_CASE ("Reshape_FlattenAll_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeFlattenAllTest(backends); } TEST_CASE ("Reshape_Int8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeInt8Test(backends); } TEST_CASE ("Reshape_Uint8_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeUint8Test(backends); } TEST_CASE ("Reshape_Float16_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeSimpleFloat16Test(backends); } TEST_CASE ("Reshape_Simple_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeSimpleTest(backends, false); } TEST_CASE ("Reshape_ReduceDimension_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeReduceDimTest(backends, false); } TEST_CASE ("Reshape_Flatten_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeFlattenTest(backends, false); } TEST_CASE ("Reshape_FlattenAll_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeFlattenAllTest(backends, false); } TEST_CASE ("Reshape_Int8_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeInt8Test(backends, false); } TEST_CASE ("Reshape_Uint8_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeUint8Test(backends, false); } TEST_CASE ("Reshape_Float16_ShapeTensor_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReshapeSimpleFloat16Test(backends, false); } } // TEST_SUITE("Reshape_GpuAccTests") TEST_SUITE("Reshape_CpuAccTests") { TEST_CASE ("Reshape_Simple_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeSimpleTest(backends); } TEST_CASE ("Reshape_ReduceDimension_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeReduceDimTest(backends); } TEST_CASE ("Reshape_Flatten_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeFlattenTest(backends); } TEST_CASE ("Reshape_FlattenAll_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeFlattenAllTest(backends); } TEST_CASE ("Reshape_Int8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeInt8Test(backends); } TEST_CASE ("Reshape_Uint8_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeUint8Test(backends); } TEST_CASE ("Reshape_Float16_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeSimpleFloat16Test(backends); } TEST_CASE ("Reshape_Simple_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeSimpleTest(backends, false); } TEST_CASE ("Reshape_ReduceDimension_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeReduceDimTest(backends, false); } TEST_CASE ("Reshape_Flatten_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeFlattenTest(backends, false); } TEST_CASE ("Reshape_FlattenAll_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeFlattenAllTest(backends, false); } TEST_CASE ("Reshape_Int8_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeInt8Test(backends, false); } TEST_CASE ("Reshape_Uint8_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeUint8Test(backends, false); } TEST_CASE ("Reshape_Float16_ShapeTensor_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReshapeSimpleFloat16Test(backends, false); } } // TEST_SUITE("Reshape_CpuAccTests") TEST_SUITE("Reshape_CpuRefTests") { TEST_CASE ("Reshape_Simple_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeSimpleTest(backends); } TEST_CASE ("Reshape_ReduceDimension_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeReduceDimTest(backends); } TEST_CASE ("Reshape_Flatten_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeFlattenTest(backends); } TEST_CASE ("Reshape_FlattenAll_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeFlattenAllTest(backends); } TEST_CASE ("Reshape_Int8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeInt8Test(backends); } TEST_CASE ("Reshape_Uint8_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeUint8Test(backends); } TEST_CASE ("Reshape_Int16_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeInt16Test(backends); } TEST_CASE ("Reshape_Float16_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeSimpleFloat16Test(backends); } TEST_CASE ("Reshape_Simple_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeSimpleTest(backends, false); } TEST_CASE ("Reshape_ReduceDimension_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeReduceDimTest(backends, false); } TEST_CASE ("Reshape_Flatten_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeFlattenTest(backends, false); } TEST_CASE ("Reshape_FlattenAll_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeFlattenAllTest(backends, false); } TEST_CASE ("Reshape_Int8_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeInt8Test(backends, false); } TEST_CASE ("Reshape_Uint8_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeUint8Test(backends, false); } TEST_CASE ("Reshape_Int16_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeInt16Test(backends, false); } TEST_CASE ("Reshape_Float16_ShapeTensor_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReshapeSimpleFloat16Test(backends, false); } } // TEST_SUITE("Reshape_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/ResizeTest.cpp000066400000000000000000000072711446772241200202170ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ResizeTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void ResizeBiliniarFloat32Test(std::vector& backends) { // Set input data std::vector input1Values { 0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f }; const std::vector input2NewShape { 5, 5 }; // Calculate output data std::vector expectedOutputValues { 0.0f, 0.6f, 1.2f, 1.8f, 2.0f, 1.8f, 2.4f, 3.0f, 3.6f, 3.8f, 3.6f, 4.2f, 4.8f, 5.4f, 5.6f, 5.4f, 6.0f, 6.6f, 7.2f, 7.4f, 6.0f, 6.6f, 7.2f, 7.8f, 8.0f }; const std::vector input1Shape { 1, 3, 3, 1 }; const std::vector input2Shape { 2 }; const std::vector expectedOutputShape = { 1, 5, 5, 1 }; ResizeFP32TestImpl(tflite::BuiltinOperator_RESIZE_BILINEAR, backends, input1Values, input1Shape, input2NewShape, input2Shape, expectedOutputValues, expectedOutputShape); } void ResizeNearestNeighbourFloat32Test(std::vector& backends) { // Set input data std::vector input1Values { 1.0f, 2.0f, 3.0f, 4.0f } ; const std::vector input2NewShape { 1, 1 }; // Calculate output data std::vector expectedOutputValues { 1.0f }; const std::vector input1Shape { 1, 2, 2, 1 }; const std::vector input2Shape { 2 }; const std::vector expectedOutputShape = { 1, 1, 1, 1 }; ResizeFP32TestImpl(tflite::BuiltinOperator_RESIZE_NEAREST_NEIGHBOR, backends, input1Values, input1Shape, input2NewShape, input2Shape, expectedOutputValues, expectedOutputShape); } TEST_SUITE("ResizeTests_GpuAccTests") { TEST_CASE ("Resize_Biliniar_Float32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ResizeBiliniarFloat32Test(backends); } TEST_CASE ("Resize_NearestNeighbour_Float32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ResizeNearestNeighbourFloat32Test(backends); } } // TEST_SUITE("ResizeTests_GpuAccTests") TEST_SUITE("ResizeTests_CpuAccTests") { TEST_CASE ("Resize_Biliniar_Float32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ResizeBiliniarFloat32Test(backends); } TEST_CASE ("Resize_NearestNeighbour_Float32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ResizeNearestNeighbourFloat32Test(backends); } } // TEST_SUITE("ResizeTests_CpuAccTests") TEST_SUITE("ResizeTests_CpuRefTests") { TEST_CASE ("Resize_Biliniar_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ResizeBiliniarFloat32Test(backends); } TEST_CASE ("Resize_NearestNeighbour_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ResizeNearestNeighbourFloat32Test(backends); } } // TEST_SUITE("ResizeTests_CpuRefTests") } // namespace armnnDelegate armnn-23.08/delegate/test/ResizeTestHelper.hpp000066400000000000000000000175321446772241200213650ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateResizeTfLiteModel(tflite::BuiltinOperator operatorCode, tflite::TensorType inputTensorType, const std::vector & inputTensorShape, const std::vector & sizeTensorData, const std::vector & sizeTensorShape, const std::vector & outputTensorShape) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(sizeTensorData.data()), sizeof(int32_t) * sizeTensorData.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input_tensor")); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(sizeTensorShape.data(), sizeTensorShape.size()), TensorType_INT32, 2, flatBufferBuilder.CreateString("size_input_tensor")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), inputTensorType, 3, flatBufferBuilder.CreateString("output_tensor")); // Create Operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOption = 0; switch (operatorCode) { case BuiltinOperator_RESIZE_BILINEAR: { operatorBuiltinOption = CreateResizeBilinearOptions(flatBufferBuilder, false, false).Union(); operatorBuiltinOptionsType = tflite::BuiltinOptions_ResizeBilinearOptions; break; } case BuiltinOperator_RESIZE_NEAREST_NEIGHBOR: { operatorBuiltinOption = CreateResizeNearestNeighborOptions(flatBufferBuilder, false, false).Union(); operatorBuiltinOptionsType = tflite::BuiltinOptions_ResizeNearestNeighborOptions; break; } default: break; } const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset resizeOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOption); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&resizeOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Resize Biliniar Operator Model"); flatbuffers::Offset opCode = CreateOperatorCode(flatBufferBuilder, operatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&opCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void ResizeFP32TestImpl(tflite::BuiltinOperator operatorCode, std::vector& backends, std::vector& input1Values, std::vector input1Shape, std::vector input2NewShape, std::vector input2Shape, std::vector& expectedOutputValues, std::vector expectedOutputShape) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateResizeTfLiteModel(operatorCode, ::tflite::TensorType_FLOAT32, input1Shape, input2NewShape, input2Shape, expectedOutputShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input1Values, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(input2NewShape, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input1Values, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(input2NewShape, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/ReverseV2Test.cpp000066400000000000000000000121021446772241200205660ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ReverseV2TestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void ReverseV2Float32Test(std::vector& backends) { // Set input data std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, 21.0f, 22.0f, 23.0f, 24.0f, 25.0f, 26.0f, 27.0f, 28.0f, 29.0f }; // The output data std::vector expectedOutputValues = { 3.0f, 2.0f, 1.0f, 6.0f, 5.0f, 4.0f, 9.0f, 8.0f, 7.0f, 13.0f, 12.0f, 11.0f, 16.0f, 15.0f, 14.0f, 19.0f, 18.0f, 17.0f, 23.0f, 22.0f, 21.0f, 26.0f, 25.0f, 24.0f, 29.0f, 28.0f, 27.0f }; // The axis to reverse const std::vector axisValues = {2}; // Shapes const std::vector inputShape = {3, 3, 3}; const std::vector axisShapeDims = {1}; const std::vector expectedOutputShape = {3, 3, 3}; ReverseV2FP32TestImpl(tflite::BuiltinOperator_REVERSE_V2, backends, inputValues, inputShape, axisValues, axisShapeDims, expectedOutputValues, expectedOutputShape); } void ReverseV2NegativeAxisFloat32Test(std::vector& backends) { // Set input data std::vector inputValues = { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, 21.0f, 22.0f, 23.0f, 24.0f, 25.0f, 26.0f, 27.0f, 28.0f, 29.0f }; // The output data std::vector expectedOutputValues = { 7.0f, 8.0f, 9.0f, 4.0f, 5.0f, 6.0f, 1.0f, 2.0f, 3.0f, 17.0f, 18.0f, 19.0f, 14.0f, 15.0f, 16.0f, 11.0f, 12.0f, 13.0f, 27.0f, 28.0f, 29.0f, 24.0f, 25.0f, 26.0f, 21.0f, 22.0f, 23.0f }; // The axis to reverse const std::vector axisValues = {-2}; // Shapes const std::vector inputShape = {3, 3, 3}; const std::vector axisShapeDims = {1}; const std::vector expectedOutputShape = {3, 3, 3}; ReverseV2FP32TestImpl(tflite::BuiltinOperator_REVERSE_V2, backends, inputValues, inputShape, axisValues, axisShapeDims, expectedOutputValues, expectedOutputShape); } #if defined(REVERSEV2_GPUACC) TEST_SUITE("ReverseV2Tests_GpuAccTests") { TEST_CASE ("ReverseV2_Float32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReverseV2Float32Test(backends); } TEST_CASE ("ReverseV2_NegativeAxis_Float32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; ReverseV2NegativeAxisFloat32Test(backends); } } // TEST_SUITE("ReverseV2Tests_GpuAccTests") #endif #if defined(REVERSEV2_CPUACC) TEST_SUITE("ReverseV2Tests_CpuAccTests") { TEST_CASE ("ReverseV2_Float32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReverseV2Float32Test(backends); } TEST_CASE ("ReverseV2_NegativeAxis_Float32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; ReverseV2NegativeAxisFloat32Test(backends); } } // TEST_SUITE("ReverseV2Tests_CpuAccTests") #endif TEST_SUITE("ReverseV2Tests_CpuRefTests") { TEST_CASE ("ReverseV2_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReverseV2Float32Test(backends); } TEST_CASE ("ReverseV2_NegativeAxis_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ReverseV2NegativeAxisFloat32Test(backends); } } // TEST_SUITE("ReverseV2Tests_CpuRefTests") } // namespace armnnDelegate armnn-23.08/delegate/test/ReverseV2TestHelper.hpp000066400000000000000000000174551446772241200217530ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateReverseV2TfLiteModel(tflite::BuiltinOperator operatorCode, tflite::TensorType inputTensorType, const std::vector & inputTensorShape, const std::vector & axisTensorData, const std::vector & axisTensorShape, const std::vector & outputTensorShape) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(axisTensorData.data()), sizeof(int32_t) * axisTensorData.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input_tensor")); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(axisTensorShape.data(), axisTensorShape.size()), TensorType_INT32, 2, flatBufferBuilder.CreateString("axis_input_tensor")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), inputTensorType, 3, flatBufferBuilder.CreateString("output_tensor")); // Create Operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOption = 0; const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset reverseV2Operator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOption); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&reverseV2Operator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: ReverseV2 Operator Model"); flatbuffers::Offset opCode = CreateOperatorCode(flatBufferBuilder, operatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&opCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void ReverseV2FP32TestImpl(tflite::BuiltinOperator operatorCode, std::vector& backends, std::vector& inputValues, std::vector inputShape, std::vector axisValues, std::vector axisShapeDims, std::vector& expectedOutputValues, std::vector expectedOutputShape) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateReverseV2TfLiteModel(operatorCode, ::tflite::TensorType_FLOAT32, inputShape, axisValues, axisShapeDims, expectedOutputShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(axisValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(axisValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/RoundTest.cpp000066400000000000000000000033171446772241200200420ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "RoundTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void FloorFp32Test(std::vector& backends) { std::vector inputShape {1, 3, 2, 3}; std::vector outputShape {1, 3, 2, 3}; std::vector inputValues { -37.5f, -15.2f, -8.76f, -2.0f, -1.5f, -1.3f, -0.5f, -0.4f, 0.0f, 1.0f, 0.4f, 0.5f, 1.3f, 1.5f, 2.0f, 8.76f, 15.2f, 37.5f }; std::vector expectedOutputValues { -38.0f, -16.0f, -9.0f, -2.0f, -2.0f, -2.0f, -1.0f, -1.0f, 0.0f, 1.0f, 0.0f, 0.0f, 1.0f, 1.0f, 2.0f, 8.0f, 15.0f, 37.0f }; RoundTest(tflite::BuiltinOperator_FLOOR, ::tflite::TensorType_FLOAT32, backends, inputShape, inputValues, expectedOutputValues); } // FLOOR Test Suite TEST_SUITE("FLOOR_CpuRefTests") { TEST_CASE ("FLOOR_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; FloorFp32Test(backends); } } TEST_SUITE("FLOOR_CpuAccTests") { TEST_CASE ("FLOOR_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; FloorFp32Test(backends); } } TEST_SUITE("FLOOR_GpuAccTests") { TEST_CASE ("FLOOR_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; FloorFp32Test(backends); } } // End of FLOOR Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/RoundTestHelper.hpp000066400000000000000000000147001446772241200212050ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateRoundTfLiteModel(tflite::BuiltinOperator roundOperatorCode, tflite::TensorType tensorType, const std::vector & tensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); const std::vector operatorInputs({0}); const std::vector operatorOutputs({1}); flatbuffers::Offset roundOperator; flatbuffers::Offset modelDescription; flatbuffers::Offset operatorCode; switch (roundOperatorCode) { case tflite::BuiltinOperator_FLOOR: default: roundOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size())); modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Floor Operator Model"); operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_FLOOR); break; } const std::vector subgraphInputs({0}); const std::vector subgraphOutputs({1}); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&roundOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void RoundTest(tflite::BuiltinOperator roundOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& shape, std::vector& inputValues, std::vector& expectedOutputValues, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateRoundTfLiteModel(roundOperatorCode, tensorType, shape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, shape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/ShapeTest.cpp000066400000000000000000000022351446772241200200110ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ShapeTestHelper.hpp" #include namespace armnnDelegate { void ShapeSimpleTest(std::vector& backends) { std::vector inputShape{ 1, 3, 2, 3 }; std::vector inputValues{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; std::vector expectedOutputShape{ 4 }; std::vector expectedOutputValues{ 1, 3, 2, 3 }; ShapeTest(::tflite::TensorType_INT32, ::tflite::TensorType_INT32, backends, inputShape, inputValues, expectedOutputValues, expectedOutputShape); } // SHAPE Test Suite TEST_SUITE("SHAPE_CpuRefTests") { TEST_CASE("SHAPE_Simple_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; ShapeSimpleTest(backends); } } // End of SHAPE Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/ShapeTestHelper.hpp000066400000000000000000000160231446772241200211560ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateShapeTfLiteModel(tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, const std::vector& inputTensorShape, const std::vector& outputTensorShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), outputTensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); const std::vector operatorInputs({ 0 }); const std::vector operatorOutputs({ 1 }); flatbuffers::Offset shapeOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_ShapeOptions, CreateShapeOptions(flatBufferBuilder, outputTensorType).Union()); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: SHAPE Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_SHAPE); const std::vector subgraphInputs({ 0 }); const std::vector subgraphOutputs({ 1 }); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&shapeOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void ShapeTest(tflite::TensorType inputTensorType, tflite::TensorType outputTensorType, std::vector& backends, std::vector& inputShape, std::vector& inputValues, std::vector& expectedOutputValues, std::vector& expectedOutputShape, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateShapeTfLiteModel(inputTensorType, outputTensorType, inputShape, expectedOutputShape, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/SliceTest.cpp000066400000000000000000000062371446772241200200160ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SliceTestHelper.hpp" #include #include #include namespace armnnDelegate { void SliceFixtureSimpleTest(std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector outputShape { 2, 1, 3 }; std::vector beginShape { 3 }; std::vector sizeShape { 3 }; std::vector beginData { 1, 0, 0 }; std::vector sizeData { 2, 1, 3 }; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 3.0f, 3.0f, 3.0f, 5.0f, 5.0f, 5.0f }; SliceTestImpl( backends, inputData, outputData, beginData, sizeData, inputShape, beginShape, sizeShape, outputShape); } void SliceFixtureSizeTest(std::vector& backends) { std::vector inputShape { 3, 2, 3 }; std::vector outputShape { 2, 1, 3 }; std::vector beginShape { 3 }; std::vector sizeShape { 3 }; std::vector beginData { 1, 0, 0 }; std::vector sizeData { 2, 1, -1 }; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 3.0f, 3.0f, 3.0f, 5.0f, 5.0f, 5.0f }; SliceTestImpl( backends, inputData, outputData, beginData, sizeData, inputShape, beginShape, sizeShape, outputShape); } TEST_SUITE("Slice_CpuRefTests") { TEST_CASE ("Slice_Simple_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SliceFixtureSimpleTest(backends); } TEST_CASE ("Slice_Size_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SliceFixtureSizeTest(backends); } } // Slice_CpuRefTests TestSuite TEST_SUITE("Slice_CpuAccTests") { TEST_CASE ("Slice_Simple_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SliceFixtureSimpleTest(backends); } TEST_CASE ("Slice_Size_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SliceFixtureSizeTest(backends); } } // Slice_CpuAccTests TestSuite TEST_SUITE("StridedSlice_GpuAccTests") { TEST_CASE ("Slice_Simple_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SliceFixtureSimpleTest(backends); } TEST_CASE ("Slice_Size_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SliceFixtureSizeTest(backends); } } // Slice_GpuAccTests TestSuite } // namespace armnnDelegatearmnn-23.08/delegate/test/SliceTestHelper.hpp000066400000000000000000000171061446772241200211600ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateSliceTfLiteModel(tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& beginTensorData, const std::vector& sizeTensorData, const std::vector& beginTensorShape, const std::vector& sizeTensorShape, const std::vector& outputTensorShape) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; flatbuffers::Offset buffers[5] = { CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(beginTensorData.data()), sizeof(int32_t) * beginTensorData.size())), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(sizeTensorData.data()), sizeof(int32_t) * sizeTensorData.size())), CreateBuffer(flatBufferBuilder) }; std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input")); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(beginTensorShape.data(), beginTensorShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("begin_tensor")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(sizeTensorShape.data(), sizeTensorShape.size()), ::tflite::TensorType_INT32, 3, flatBufferBuilder.CreateString("size_tensor")); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 4, flatBufferBuilder.CreateString("output")); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_SliceOptions; flatbuffers::Offset operatorBuiltinOptions = CreateSliceOptions(flatBufferBuilder).Union(); const std::vector operatorInputs{ 0, 1, 2 }; const std::vector operatorOutputs{ 3 }; flatbuffers::Offset sliceOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ 0, 1, 2 }; const std::vector subgraphOutputs{ 3 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&sliceOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Slice Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_SLICE); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers, 5)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void SliceTestImpl(std::vector& backends, std::vector& inputValues, std::vector& expectedOutputValues, std::vector& beginTensorData, std::vector& sizeTensorData, std::vector& inputTensorShape, std::vector& beginTensorShape, std::vector& sizeTensorShape, std::vector& outputTensorShape) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateSliceTfLiteModel( ::tflite::TensorType_FLOAT32, inputTensorShape, beginTensorData, sizeTensorData, beginTensorShape, sizeTensorShape, outputTensorShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // End of Slice Test } // anonymous namespacearmnn-23.08/delegate/test/SoftmaxTest.cpp000066400000000000000000000055711446772241200204000ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SoftmaxTestHelper.hpp" #include #include #include #include namespace armnnDelegate { TEST_SUITE ("Softmax_GpuAccTests") { TEST_CASE ("Softmax_Standard_Beta_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; std::vector expectedOutput = {0.00994190481, 0.0445565246, 0.0734612942, 0.329230666, 0.542809606, 0.710742831, 0.158588171, 0.0961885825, 0.0214625746, 0.0130177103}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 1, expectedOutput); } TEST_CASE ("Softmax_Different_Beta_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; std::vector expectedOutput = {0.0946234912, 0.148399189, 0.172415257, 0.270400971, 0.314161092, 0.352414012, 0.224709094, 0.193408906, 0.123322964, 0.106145054}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 0.3, expectedOutput); } TEST_CASE ("Log_Softmax_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; std::vector expectedOutput = {-4.61099672, -3.11099672, -2.61099672, -1.11099672, -0.610996664, -0.341444582, -1.84144461, -2.34144449, -3.84144449, -4.34144449}; SoftmaxTestCase(tflite::BuiltinOperator_LOG_SOFTMAX, backends, 0, expectedOutput); } } // TEST_SUITE ("Softmax_GpuAccTests") TEST_SUITE ("Softmax_CpuRefTests") { TEST_CASE ("Softmax_Standard_Beta_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; std::vector expectedOutput = { 0.00994190481, 0.0445565246, 0.0734612942, 0.329230666, 0.542809606, 0.710742831, 0.158588171, 0.0961885825, 0.0214625746, 0.0130177103}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 1, expectedOutput); } TEST_CASE ("Softmax_Different_Beta_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; std::vector expectedOutput = { 0.0946234912, 0.148399189, 0.172415257, 0.270400971, 0.314161092, 0.352414012, 0.224709094, 0.193408906, 0.123322964, 0.106145054}; SoftmaxTestCase(tflite::BuiltinOperator_SOFTMAX, backends, 0.3, expectedOutput); } TEST_CASE ("Log_Softmax_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; std::vector expectedOutput = {-4.61099672, -3.11099672, -2.61099672, -1.11099672, -0.610996664, -0.341444582, -1.84144461, -2.34144449, -3.84144449, -4.34144449}; SoftmaxTestCase(tflite::BuiltinOperator_LOG_SOFTMAX, backends, 0, expectedOutput); } } // TEST_SUITE ("Softmax_CpuRefTests") } // namespace armnnDelegate armnn-23.08/delegate/test/SoftmaxTestHelper.hpp000066400000000000000000000171241446772241200215420ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include #include namespace { std::vector CreateSoftmaxTfLiteModel(tflite::BuiltinOperator softmaxOperatorCode, tflite::TensorType tensorType, const std::vector & tensorShape, float beta) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 1); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorShape.data(), tensorShape.size()), tensorType, 2); const std::vector operatorInputs({0}); const std::vector operatorOutputs({1}); flatbuffers::Offset softmaxOperator; flatbuffers::Offset modelDescription; flatbuffers::Offset operatorCode; switch (softmaxOperatorCode) { case tflite::BuiltinOperator_SOFTMAX: softmaxOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_SoftmaxOptions, CreateSoftmaxOptions(flatBufferBuilder, beta).Union()); modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Softmax Operator Model"); operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_SOFTMAX); break; case tflite::BuiltinOperator_LOG_SOFTMAX: softmaxOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_LogSoftmaxOptions, CreateLogSoftmaxOptions(flatBufferBuilder).Union()); flatBufferBuilder.CreateString("ArmnnDelegate: Log-Softmax Operator Model"); operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_LOG_SOFTMAX); break; default: break; } const std::vector subgraphInputs({0}); const std::vector subgraphOutputs({1}); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&softmaxOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void SoftmaxTest(tflite::BuiltinOperator softmaxOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& shape, std::vector& inputValues, std::vector& expectedOutputValues, float beta = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateSoftmaxTfLiteModel(softmaxOperatorCode, tensorType, shape, beta); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, shape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } /// Convenience function to run softmax and log-softmax test cases /// \param operatorCode tflite::BuiltinOperator_SOFTMAX or tflite::BuiltinOperator_LOG_SOFTMAX /// \param backends armnn backends to target /// \param beta multiplicative parameter to the softmax function /// \param expectedOutput to be checked against transformed input void SoftmaxTestCase(tflite::BuiltinOperator operatorCode, std::vector backends, float beta, std::vector expectedOutput) { std::vector input = { 1.0, 2.5, 3.0, 4.5, 5.0, -1.0, -2.5, -3.0, -4.5, -5.0}; std::vector shape = {2, 5}; SoftmaxTest(operatorCode, tflite::TensorType_FLOAT32, backends, shape, input, expectedOutput, beta); } } // anonymous namespace armnn-23.08/delegate/test/SpaceDepthTest.cpp000066400000000000000000000142041446772241200207700ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SpaceDepthTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void DepthToSpaceFp32Test(std::vector& backends, int blockSize) { // Set input data std::vector inputShape { 1, 2, 2, 4 }; std::vector outputShape { 1, 4, 4, 1 }; std::vector inputValues = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f, 9.f, 10.f, 11.f, 12.f, 13.f, 14.f, 15.f, 16.f }; std::vector expectedOutputValues = { 1.f, 2.f, 5.f, 6.f, 3.f, 4.f, 7.f, 8.f, 9.f, 10.f, 13.f, 14.f, 11.f, 12.f, 15.f, 16.f }; SpaceDepthTest(tflite::BuiltinOperator_DEPTH_TO_SPACE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, blockSize); } void DepthToSpaceUint8Test(std::vector& backends, int blockSize) { // Set input data std::vector inputShape { 2, 1, 1, 4 }; std::vector outputShape { 2, 2, 2, 1 }; std::vector inputValues = { 1, 2, 3, 4, 5, 6, 7, 8 }; std::vector expectedOutputValues = { 1, 2, 3, 4, 5, 6, 7, 8 }; SpaceDepthTest(tflite::BuiltinOperator_DEPTH_TO_SPACE, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, blockSize); } void SpaceToDepthFp32Test(std::vector& backends, int blockSize) { // Set input data std::vector inputShape { 1, 2, 2, 2 }; std::vector outputShape { 1, 1, 1, 8 }; std::vector inputValues = { 1.4f, 2.3f, 3.2f, 4.1f, 5.4f, 6.3f, 7.2f, 8.1f }; std::vector expectedOutputValues = { 1.4f, 2.3f, 3.2f, 4.1f, 5.4f, 6.3f, 7.2f, 8.1f }; SpaceDepthTest(tflite::BuiltinOperator_SPACE_TO_DEPTH, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, blockSize); } void SpaceToDepthUint8Test(std::vector& backends, int blockSize) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 1, 1, 1, 4 }; std::vector inputValues = { 1, 2, 3, 2 }; std::vector expectedOutputValues = { 1, 2, 3, 2 }; SpaceDepthTest(tflite::BuiltinOperator_SPACE_TO_DEPTH, ::tflite::TensorType_UINT8, backends, inputShape, outputShape, inputValues, expectedOutputValues, blockSize); } TEST_SUITE("DepthToSpace_CpuRefTests") { TEST_CASE ("DepthToSpaceFp32Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DepthToSpaceFp32Test(backends, 2); } TEST_CASE ("DepthToSpaceUint8Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; DepthToSpaceUint8Test(backends, 2); } } // TEST_SUITE("DepthToSpace_CpuRefTests") TEST_SUITE("DepthToSpace_CpuAccTests") { TEST_CASE ("DepthToSpaceFp32Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DepthToSpaceFp32Test(backends, 2); } TEST_CASE ("DepthToSpaceUint8Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; DepthToSpaceUint8Test(backends, 2); } } // TEST_SUITE("DepthToSpace_CpuAccTests") TEST_SUITE("DepthToSpace_GpuAccTests") { TEST_CASE ("DepthToSpaceFp32Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DepthToSpaceFp32Test(backends, 2); } TEST_CASE ("DepthToSpaceUint8Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; DepthToSpaceUint8Test(backends, 2); } } // TEST_SUITE("DepthToSpace_GpuAccTests") TEST_SUITE("SpaceToDepth_CpuRefTests") { TEST_CASE ("SpaceToDepthFp32Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SpaceToDepthFp32Test(backends, 2); } TEST_CASE ("SpaceToDepthUint8Test_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SpaceToDepthUint8Test(backends, 2); } } // TEST_SUITE("SpaceToDepth_CpuRefTests") TEST_SUITE("SpaceToDepth_CpuAccTests") { TEST_CASE ("SpaceToDepthFp32Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SpaceToDepthFp32Test(backends, 2); } TEST_CASE ("SpaceToDepthUint8Test_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SpaceToDepthUint8Test(backends, 2); } } // TEST_SUITE("SpaceToDepth_CpuAccTests") TEST_SUITE("SpaceToDepth_GpuAccTests") { TEST_CASE ("SpaceToDepthFp32Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SpaceToDepthFp32Test(backends, 2); } TEST_CASE ("SpaceToDepthUint8Test_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SpaceToDepthUint8Test(backends, 2); } } // TEST_SUITE("SpaceToDepth_GpuAccTests") } // namespace armnnDelegate armnn-23.08/delegate/test/SpaceDepthTestHelper.hpp000066400000000000000000000172651446772241200221470ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateSpaceDepthTfLiteModel(tflite::BuiltinOperator spaceDepthOperatorCode, tflite::TensorType tensorType, const std::vector & inputTensorShape, const std::vector & outputTensorShape, int32_t blockSize) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ 1.0f }), flatBufferBuilder.CreateVector({ 0 })); std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 2> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 2, flatBufferBuilder.CreateString("output"), quantizationParameters); const std::vector operatorInputs({0}); const std::vector operatorOutputs({1}); flatbuffers::Offset spaceDepthOperator; flatbuffers::Offset modelDescription; flatbuffers::Offset operatorCode; switch (spaceDepthOperatorCode) { case tflite::BuiltinOperator_SPACE_TO_DEPTH: spaceDepthOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_SpaceToDepthOptions, CreateSpaceToDepthOptions(flatBufferBuilder, blockSize).Union()); modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: SPACE_TO_DEPTH Operator Model"); operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_SPACE_TO_DEPTH); break; case tflite::BuiltinOperator_DEPTH_TO_SPACE: spaceDepthOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_DepthToSpaceOptions, CreateDepthToSpaceOptions(flatBufferBuilder, blockSize).Union()); flatBufferBuilder.CreateString("ArmnnDelegate: DEPTH_TO_SPACE Operator Model"); operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_DEPTH_TO_SPACE); break; default: break; } const std::vector subgraphInputs({0}); const std::vector subgraphOutputs({1}); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&spaceDepthOperator, 1)); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void SpaceDepthTest(tflite::BuiltinOperator spaceDepthOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& outputShape, std::vector& inputValues, std::vector& expectedOutputValues, int32_t blockSize = 2) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateSpaceDepthTfLiteModel(spaceDepthOperatorCode, tensorType, inputShape, outputShape, blockSize); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespace armnn-23.08/delegate/test/SplitTest.cpp000066400000000000000000000202361446772241200200450ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "SplitTestHelper.hpp" #include #include #include #include namespace armnnDelegate { // SPLIT Operator void SplitUint8Test(std::vector& backends) { std::vector axisShape { 1 }; std::vector inputShape { 2, 2, 2, 2} ; std::vector outputShape0 { 2, 2, 2, 1 }; std::vector outputShape1 { 2, 2, 2, 1 }; std::vector> outputShapes{ outputShape0, outputShape1 }; std::vector axisData { 3 }; // Axis std::vector inputValues { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; // Input std::vector expectedOutputValues0 { 1, 3, 5, 7, 9, 11, 13, 15 }; std::vector expectedOutputValues1 { 2, 4, 6, 8, 10, 12, 14, 16 }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1 }; int32_t numSplits = 2; SplitTest(::tflite::TensorType_UINT8, backends, axisShape, inputShape, outputShapes, axisData, inputValues, expectedOutputValues, numSplits); } void SplitFp32Test(std::vector& backends) { std::vector axisShape { 1 }; std::vector inputShape { 2, 2, 2, 2 }; std::vector outputShape0 { 2, 1, 2, 2 }; std::vector outputShape1 { 2, 1, 2, 2 }; std::vector> outputShapes{ outputShape0, outputShape1 }; std::vector axisData { 1 }; // Axis std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f }; // Input std::vector expectedOutputValues0 { 1.0f, 2.0f, 3.0f, 4.0f, 9.0f, 10.0f, 11.0f, 12.0f }; std::vector expectedOutputValues1 { 5.0f, 6.0f, 7.0f, 8.0f, 13.0f, 14.0f, 15.0f, 16.0f }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1 }; int32_t numSplits = 2; SplitTest(::tflite::TensorType_FLOAT32, backends, axisShape, inputShape, outputShapes, axisData, inputValues, expectedOutputValues, numSplits); } // SPLIT Test Suite TEST_SUITE("SPLIT_CpuRefTests") { TEST_CASE ("SPLIT_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SplitUint8Test(backends); } TEST_CASE ("SPLIT_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SplitFp32Test(backends); } } TEST_SUITE("SPLIT_CpuAccTests") { TEST_CASE ("SPLIT_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SplitUint8Test(backends); } TEST_CASE ("SPLIT_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SplitFp32Test(backends); } } TEST_SUITE("SPLIT_GpuAccTests") { TEST_CASE ("SPLIT_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SplitUint8Test(backends); } TEST_CASE ("SPLIT_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SplitFp32Test(backends); } } // End of SPLIT Test Suite // SPLIT_V Operator void SplitVUint8Test(std::vector& backends) { std::vector axisShape { 1 }; std::vector inputShape { 2, 4, 2, 2 }; std::vector splitsShape { 2 }; std::vector outputShape0 { 2, 3, 2, 2 }; std::vector outputShape1 { 2, 1, 2, 2 }; std::vector> outputShapes{ outputShape0, outputShape1 }; std::vector axisData { 1 }; // Axis std::vector splitsData { 3, 1 }; // Splits std::vector inputValues { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }; // Input std::vector expectedOutputValues0 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 }; std::vector expectedOutputValues1 { 13, 14, 15, 16, 29, 30, 31, 32 }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1 }; int32_t numSplits = 2; SplitVTest(::tflite::TensorType_UINT8, backends, inputShape, splitsShape, axisShape, outputShapes, inputValues, splitsData, axisData, expectedOutputValues, numSplits); } void SplitVFp32Test(std::vector& backends) { std::vector axisShape { 1 }; std::vector inputShape { 2, 4, 2, 2 }; std::vector splitsShape { 2 }; std::vector outputShape0 { 2, 3, 2, 2 }; std::vector outputShape1 { 2, 1, 2, 2 }; std::vector> outputShapes{ outputShape0, outputShape1 }; std::vector axisData { 1 }; // Axis std::vector splitsData { 3, 1 }; // Splits std::vector inputValues { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, 20.0f, 21.0f, 22.0f, 23.0f, 24.0f, 25.0f, 26.0f, 27.0f, 28.0f, 29.0f, 30.0f, 31.0f, 32.0f }; // Input std::vector expectedOutputValues0 { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, 11.0f, 12.0f, 17.0f, 18.0f, 19.0f, 20.0f, 21.0f, 22.0f, 23.0f, 24.0f, 25.0f, 26.0f, 27.0f, 28.0f }; std::vector expectedOutputValues1 { 13.0f, 14.0f, 15.0f, 16.0f, 29.0f, 30.0f, 31.0f, 32.0f }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1 }; int32_t numSplits = 2; SplitVTest(::tflite::TensorType_FLOAT32, backends, inputShape, splitsShape, axisShape, outputShapes, inputValues, splitsData, axisData, expectedOutputValues, numSplits); } // SPLIT_V Test Suite TEST_SUITE("SPLIT_V_CpuRefTests") { TEST_CASE ("SPLIT_V_Uint8_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SplitVUint8Test(backends); } TEST_CASE ("SPLIT_V_Fp32_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; SplitVFp32Test(backends); } } TEST_SUITE("SPLIT_V_CpuAccTests") { TEST_CASE ("SPLIT_V_Uint8_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SplitVUint8Test(backends); } TEST_CASE ("SPLIT_V_Fp32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; SplitVFp32Test(backends); } } TEST_SUITE("SPLIT_V_GpuAccTests") { TEST_CASE ("SPLIT_V_Uint8_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SplitVUint8Test(backends); } TEST_CASE ("SPLIT_V_Fp32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; SplitVFp32Test(backends); } } // End of SPLIT_V Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/SplitTestHelper.hpp000066400000000000000000000424701446772241200212160ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateSplitTfLiteModel(tflite::TensorType tensorType, std::vector& axisTensorShape, std::vector& inputTensorShape, const std::vector>& outputTensorShapes, std::vector& axisData, const int32_t numSplits, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(axisData.data()), sizeof(int32_t) * axisData.size()))); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 4> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(axisTensorShape.data(), axisTensorShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("axis"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); // Create output tensor for (unsigned int i = 0; i < outputTensorShapes.size(); ++i) { buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors[i + 2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShapes[i].data(), outputTensorShapes[i].size()), tensorType, (i+3), flatBufferBuilder.CreateString("output"), quantizationParameters); } // create operator. Mean uses ReducerOptions. tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_SplitOptions; flatbuffers::Offset operatorBuiltinOptions = CreateSplitOptions(flatBufferBuilder, numSplits).Union(); const std::vector operatorInputs{ {0, 1} }; const std::vector operatorOutputs{ {2, 3} }; flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1} }; const std::vector subgraphOutputs{ {2, 3} }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: SPLIT Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_SPLIT); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void SplitTest(tflite::TensorType tensorType, std::vector& backends, std::vector& axisTensorShape, std::vector& inputTensorShape, std::vector>& outputTensorShapes, std::vector& axisData, std::vector& inputValues, std::vector>& expectedOutputValues, const int32_t numSplits, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateSplitTfLiteModel(tensorType, axisTensorShape, inputTensorShape, outputTensorShapes, axisData, numSplits, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); // Compare output data for (unsigned int i = 0; i < expectedOutputValues.size(); ++i) { std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(i); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(i); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(i); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(i); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues[i]); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShapes[i]); } tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // End of SPLIT Test std::vector CreateSplitVTfLiteModel(tflite::TensorType tensorType, std::vector& inputTensorShape, std::vector& splitsTensorShape, std::vector& axisTensorShape, const std::vector>& outputTensorShapes, std::vector& splitsData, std::vector& axisData, const int32_t numSplits, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::array, 3> buffers; buffers[0] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector({})); buffers[1] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(splitsData.data()), sizeof(int32_t) * splitsData.size())); buffers[2] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(axisData.data()), sizeof(int32_t) * axisData.size())); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); std::array, 5> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 0, flatBufferBuilder.CreateString("input"), quantizationParameters); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(splitsTensorShape.data(), splitsTensorShape.size()), ::tflite::TensorType_INT32, 1, flatBufferBuilder.CreateString("splits"), quantizationParameters); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(axisTensorShape.data(), axisTensorShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("axis"), quantizationParameters); // Create output tensor for (unsigned int i = 0; i < outputTensorShapes.size(); ++i) { tensors[i + 3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShapes[i].data(), outputTensorShapes[i].size()), tensorType, 0, flatBufferBuilder.CreateString("output"), quantizationParameters); } // create operator. Mean uses ReducerOptions. tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_SplitVOptions; flatbuffers::Offset operatorBuiltinOptions = CreateSplitVOptions(flatBufferBuilder, numSplits).Union(); const std::vector operatorInputs{ {0, 1, 2} }; const std::vector operatorOutputs{ {3, 4} }; flatbuffers::Offset controlOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ {0, 1, 2} }; const std::vector subgraphOutputs{ {3, 4} }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&controlOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: SPLIT_V Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_SPLIT_V); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void SplitVTest(tflite::TensorType tensorType, std::vector& backends, std::vector& inputTensorShape, std::vector& splitsTensorShape, std::vector& axisTensorShape, std::vector>& outputTensorShapes, std::vector& inputValues, std::vector& splitsData, std::vector& axisData, std::vector>& expectedOutputValues, const int32_t numSplits, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateSplitVTfLiteModel(tensorType, inputTensorShape, splitsTensorShape, axisTensorShape, outputTensorShapes, splitsData, axisData, numSplits, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); // Compare output data for (unsigned int i = 0; i < expectedOutputValues.size(); ++i) { std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(i); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(i); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(i); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(i); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues[i]); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShapes[i]); } tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // End of SPLIT_V Test } // anonymous namespacearmnn-23.08/delegate/test/SqueezeTest.cpp000066400000000000000000000052651446772241200204000ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "RedefineTestHelper.hpp" namespace armnnDelegate { void SqueezeSimpleTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 2, 2 }; std::vector squeezeDims { }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_SQUEEZE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, squeezeDims); } void SqueezeWithDimsTest(std::vector& backends) { // Set input data std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 1, 2, 2 }; std::vector squeezeDims { -1 }; std::vector inputValues = { 1, 2, 3, 4 }; std::vector expectedOutputValues = { 1, 2, 3, 4 }; RedefineTest(tflite::BuiltinOperator_SQUEEZE, ::tflite::TensorType_FLOAT32, backends, inputShape, outputShape, inputValues, expectedOutputValues, squeezeDims); } TEST_SUITE("Squeeze_GpuAccTests") { TEST_CASE ("Squeeze_Simple_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_GpuAccTests") TEST_SUITE("Squeeze_CpuAccTests") { TEST_CASE ("Squeeze_Simple_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_CpuAccTests") TEST_SUITE("Squeeze_CpuRefTests") { TEST_CASE ("Squeeze_Simple_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SqueezeSimpleTest(backends); } TEST_CASE ("Squeeze_With_Dims_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; SqueezeWithDimsTest(backends); } } // TEST_SUITE("Squeeze_CpuRefTests") } // namespace armnnDelegatearmnn-23.08/delegate/test/StridedSliceTest.cpp000066400000000000000000000156761446772241200213440ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "StridedSliceTestHelper.hpp" #include #include #include namespace armnnDelegate { void StridedSlice4DTest(std::vector& backends) { std::vector inputShape { 3, 2, 3, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector beginShape { 4 }; std::vector endShape { 4 }; std::vector strideShape { 4 }; std::vector beginData { 1, 0, 0, 0 }; std::vector endData { 2, 2, 3, 1 }; std::vector strideData { 1, 1, 1, 1 }; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f }; StridedSliceTestImpl( backends, inputData, outputData, beginData, endData, strideData, inputShape, beginShape, endShape, strideShape, outputShape ); } void StridedSlice4DReverseTest(std::vector& backends) { std::vector inputShape { 3, 2, 3, 1 }; std::vector outputShape { 1, 2, 3, 1 }; std::vector beginShape { 4 }; std::vector endShape { 4 }; std::vector strideShape { 4 }; std::vector beginData { 1, -1, 0, 0 }; std::vector endData { 2, -3, 3, 1 }; std::vector strideData { 1, -1, 1, 1 }; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 4.0f, 4.0f, 4.0f, 3.0f, 3.0f, 3.0f }; StridedSliceTestImpl( backends, inputData, outputData, beginData, endData, strideData, inputShape, beginShape, endShape, strideShape, outputShape ); } void StridedSliceSimpleStrideTest(std::vector& backends) { std::vector inputShape { 3, 2, 3, 1 }; std::vector outputShape { 2, 1, 2, 1 }; std::vector beginShape { 4 }; std::vector endShape { 4 }; std::vector strideShape { 4 }; std::vector beginData { 0, 0, 0, 0 }; std::vector endData { 3, 2, 3, 1 }; std::vector strideData { 2, 2, 2, 1 }; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 1.0f, 1.0f, 5.0f, 5.0f }; StridedSliceTestImpl( backends, inputData, outputData, beginData, endData, strideData, inputShape, beginShape, endShape, strideShape, outputShape ); } void StridedSliceSimpleRangeMaskTest(std::vector& backends) { std::vector inputShape { 3, 2, 3, 1 }; std::vector outputShape { 3, 2, 3, 1 }; std::vector beginShape { 4 }; std::vector endShape { 4 }; std::vector strideShape { 4 }; std::vector beginData { 1, 1, 1, 1 }; std::vector endData { 1, 1, 1, 1 }; std::vector strideData { 1, 1, 1, 1 }; int beginMask = -1; int endMask = -1; std::vector inputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; std::vector outputData { 1.0f, 1.0f, 1.0f, 2.0f, 2.0f, 2.0f, 3.0f, 3.0f, 3.0f, 4.0f, 4.0f, 4.0f, 5.0f, 5.0f, 5.0f, 6.0f, 6.0f, 6.0f }; StridedSliceTestImpl( backends, inputData, outputData, beginData, endData, strideData, inputShape, beginShape, endShape, strideShape, outputShape, beginMask, endMask ); } TEST_SUITE("StridedSlice_CpuRefTests") { TEST_CASE ("StridedSlice_4D_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; StridedSlice4DTest(backends); } TEST_CASE ("StridedSlice_4D_Reverse_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; StridedSlice4DReverseTest(backends); } TEST_CASE ("StridedSlice_SimpleStride_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; StridedSliceSimpleStrideTest(backends); } TEST_CASE ("StridedSlice_SimpleRange_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; StridedSliceSimpleRangeMaskTest(backends); } } // StridedSlice_CpuRefTests TestSuite TEST_SUITE("StridedSlice_CpuAccTests") { TEST_CASE ("StridedSlice_4D_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; StridedSlice4DTest(backends); } TEST_CASE ("StridedSlice_4D_Reverse_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; StridedSlice4DReverseTest(backends); } TEST_CASE ("StridedSlice_SimpleStride_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; StridedSliceSimpleStrideTest(backends); } TEST_CASE ("StridedSlice_SimpleRange_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; StridedSliceSimpleRangeMaskTest(backends); } } // StridedSlice_CpuAccTests TestSuite TEST_SUITE("StridedSlice_GpuAccTests") { TEST_CASE ("StridedSlice_4D_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; StridedSlice4DTest(backends); } TEST_CASE ("StridedSlice_4D_Reverse_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; StridedSlice4DReverseTest(backends); } TEST_CASE ("StridedSlice_SimpleStride_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; StridedSliceSimpleStrideTest(backends); } TEST_CASE ("StridedSlice_SimpleRange_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; StridedSliceSimpleRangeMaskTest(backends); } } // StridedSlice_GpuAccTests TestSuite } // namespace armnnDelegatearmnn-23.08/delegate/test/StridedSliceTestHelper.hpp000066400000000000000000000245671446772241200225100ustar00rootroot00000000000000// // Copyright © 2022-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateStridedSliceTfLiteModel(tflite::TensorType tensorType, const std::vector& inputTensorShape, const std::vector& beginTensorData, const std::vector& endTensorData, const std::vector& strideTensorData, const std::vector& beginTensorShape, const std::vector& endTensorShape, const std::vector& strideTensorShape, const std::vector& outputTensorShape, const int32_t beginMask, const int32_t endMask, const int32_t ellipsisMask, const int32_t newAxisMask, const int32_t ShrinkAxisMask, const armnn::DataLayout& dataLayout) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; flatbuffers::Offset buffers[6] = { CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(beginTensorData.data()), sizeof(int32_t) * beginTensorData.size())), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(endTensorData.data()), sizeof(int32_t) * endTensorData.size())), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(strideTensorData.data()), sizeof(int32_t) * strideTensorData.size())), CreateBuffer(flatBufferBuilder) }; std::array, 5> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input")); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(beginTensorShape.data(), beginTensorShape.size()), ::tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("begin_tensor")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(endTensorShape.data(), endTensorShape.size()), ::tflite::TensorType_INT32, 3, flatBufferBuilder.CreateString("end_tensor")); tensors[3] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(strideTensorShape.data(), strideTensorShape.size()), ::tflite::TensorType_INT32, 4, flatBufferBuilder.CreateString("stride_tensor")); tensors[4] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, 5, flatBufferBuilder.CreateString("output")); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_StridedSliceOptions; flatbuffers::Offset operatorBuiltinOptions = CreateStridedSliceOptions(flatBufferBuilder, beginMask, endMask, ellipsisMask, newAxisMask, ShrinkAxisMask).Union(); const std::vector operatorInputs{ 0, 1, 2, 3 }; const std::vector operatorOutputs{ 4 }; flatbuffers::Offset sliceOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); const std::vector subgraphInputs{ 0, 1, 2, 3 }; const std::vector subgraphOutputs{ 4 }; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&sliceOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: StridedSlice Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, BuiltinOperator_STRIDED_SLICE); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers, 6)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void StridedSliceTestImpl(std::vector& backends, std::vector& inputValues, std::vector& expectedOutputValues, std::vector& beginTensorData, std::vector& endTensorData, std::vector& strideTensorData, std::vector& inputTensorShape, std::vector& beginTensorShape, std::vector& endTensorShape, std::vector& strideTensorShape, std::vector& outputTensorShape, const int32_t beginMask = 0, const int32_t endMask = 0, const int32_t ellipsisMask = 0, const int32_t newAxisMask = 0, const int32_t ShrinkAxisMask = 0, const armnn::DataLayout& dataLayout = armnn::DataLayout::NHWC) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateStridedSliceTfLiteModel( ::tflite::TensorType_FLOAT32, inputTensorShape, beginTensorData, endTensorData, strideTensorData, beginTensorShape, endTensorShape, strideTensorShape, outputTensorShape, beginMask, endMask, ellipsisMask, newAxisMask, ShrinkAxisMask, dataLayout); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputTensorShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } // End of StridedSlice Test } // anonymous namespacearmnn-23.08/delegate/test/TestUtils.cpp000066400000000000000000000075201446772241200200530ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "TestUtils.hpp" namespace armnnDelegate { void CompareData(bool tensor1[], bool tensor2[], size_t tensorSize) { auto compareBool = [](auto a, auto b) {return (((a == 0) && (b == 0)) || ((a != 0) && (b != 0)));}; for (size_t i = 0; i < tensorSize; i++) { CHECK(compareBool(tensor1[i], tensor2[i])); } } void CompareData(std::vector& tensor1, std::vector& tensor2, size_t tensorSize) { auto compareBool = [](auto a, auto b) {return (((a == 0) && (b == 0)) || ((a != 0) && (b != 0)));}; for (size_t i = 0; i < tensorSize; i++) { CHECK(compareBool(tensor1[i], tensor2[i])); } } void CompareData(float tensor1[], float tensor2[], size_t tensorSize) { for (size_t i = 0; i < tensorSize; i++) { CHECK(tensor1[i] == doctest::Approx( tensor2[i] )); } } void CompareData(float tensor1[], float tensor2[], size_t tensorSize, float percentTolerance) { for (size_t i = 0; i < tensorSize; i++) { CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= std::abs(tensor1[i]*percentTolerance/100)); } } void CompareData(uint8_t tensor1[], uint8_t tensor2[], size_t tensorSize) { uint8_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance); } } void CompareData(int16_t tensor1[], int16_t tensor2[], size_t tensorSize) { int16_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance); } } void CompareData(int32_t tensor1[], int32_t tensor2[], size_t tensorSize) { int32_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance); } } void CompareData(int8_t tensor1[], int8_t tensor2[], size_t tensorSize) { int8_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { CHECK(std::max(tensor1[i], tensor2[i]) - std::min(tensor1[i], tensor2[i]) <= tolerance); } } void CompareData(Half tensor1[], Half tensor2[], size_t tensorSize) { for (size_t i = 0; i < tensorSize; i++) { CHECK(tensor1[i] == doctest::Approx( tensor2[i] )); } } void CompareData(TfLiteFloat16 tensor1[], TfLiteFloat16 tensor2[], size_t tensorSize) { uint16_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { uint16_t tensor1Data = tensor1[i].data; uint16_t tensor2Data = tensor2[i].data; CHECK(std::max(tensor1Data, tensor2Data) - std::min(tensor1Data, tensor2Data) <= tolerance); } } void CompareData(TfLiteFloat16 tensor1[], Half tensor2[], size_t tensorSize) { uint16_t tolerance = 1; for (size_t i = 0; i < tensorSize; i++) { uint16_t tensor1Data = tensor1[i].data; uint16_t tensor2Data = half_float::detail::float2half(tensor2[i]); CHECK(std::max(tensor1Data, tensor2Data) - std::min(tensor1Data, tensor2Data) <= tolerance); } } void CompareOutputShape(const std::vector& tfLiteDelegateShape, const std::vector& armnnDelegateShape, const std::vector& expectedOutputShape) { CHECK(expectedOutputShape.size() == tfLiteDelegateShape.size()); CHECK(expectedOutputShape.size() == armnnDelegateShape.size()); for (size_t i = 0; i < expectedOutputShape.size(); i++) { CHECK(expectedOutputShape[i] == armnnDelegateShape[i]); CHECK(tfLiteDelegateShape[i] == expectedOutputShape[i]); CHECK(tfLiteDelegateShape[i] == armnnDelegateShape[i]); } } } // namespace armnnDelegatearmnn-23.08/delegate/test/TestUtils.hpp000066400000000000000000000065321446772241200200620ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include #include #include #include using Half = half_float::half; namespace armnnDelegate { constexpr const char* FILE_IDENTIFIER = "TFL3"; /// Can be used to compare bool data coming from a tflite interpreter /// Boolean types get converted to a bit representation in a vector. vector.data() returns a void pointer /// instead of a pointer to bool. Therefore a special function to compare to vector of bool is required void CompareData(std::vector& tensor1, std::vector& tensor2, size_t tensorSize); void CompareData(bool tensor1[], bool tensor2[], size_t tensorSize); /// Can be used to compare float data coming from a tflite interpreter with a tolerance of limit_of_float*100 void CompareData(float tensor1[], float tensor2[], size_t tensorSize); /// Can be used to compare float data coming from a tflite interpreter with a given percentage tolerance void CompareData(float tensor1[], float tensor2[], size_t tensorSize, float percentTolerance); /// Can be used to compare int8_t data coming from a tflite interpreter with a tolerance of 1 void CompareData(int8_t tensor1[], int8_t tensor2[], size_t tensorSize); /// Can be used to compare uint8_t data coming from a tflite interpreter with a tolerance of 1 void CompareData(uint8_t tensor1[], uint8_t tensor2[], size_t tensorSize); /// Can be used to compare int16_t data coming from a tflite interpreter with a tolerance of 1 void CompareData(int16_t tensor1[], int16_t tensor2[], size_t tensorSize); /// Can be used to compare int32_t data coming from a tflite interpreter with a tolerance of 1 void CompareData(int32_t tensor1[], int32_t tensor2[], size_t tensorSize); /// Can be used to compare Half (Float16) data with a tolerance of limit_of_float*100 void CompareData(Half tensor1[], Half tensor2[], size_t tensorSize); /// Can be used to compare TfLiteFloat16 data coming from a tflite interpreter void CompareData(TfLiteFloat16 tensor1[], TfLiteFloat16 tensor2[], size_t tensorSize); /// Can be used to compare Half (Float16) data and TfLiteFloat16 data coming from a tflite interpreter void CompareData(TfLiteFloat16 tensor1[], Half tensor2[], size_t tensorSize); /// Can be used to compare the output tensor shape /// Example usage can be found in ControlTestHelper.hpp void CompareOutputShape(const std::vector& tfLiteDelegateShape, const std::vector& armnnDelegateShape, const std::vector& expectedOutputShape); /// Can be used to compare the output tensor values /// Example usage can be found in ControlTestHelper.hpp template void CompareOutputData(std::vector& tfLiteDelegateOutputs, std::vector& armnnDelegateOutputs, std::vector& expectedOutputValues) { armnnDelegate::CompareData(expectedOutputValues.data(), armnnDelegateOutputs.data(), expectedOutputValues.size()); armnnDelegate::CompareData(tfLiteDelegateOutputs.data(), expectedOutputValues.data(), expectedOutputValues.size()); armnnDelegate::CompareData(tfLiteDelegateOutputs.data(), armnnDelegateOutputs.data(), expectedOutputValues.size()); } } // namespace armnnDelegate armnn-23.08/delegate/test/TileTest.cpp000066400000000000000000000042741446772241200176530ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "TileTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void TileFloat32Test(std::vector& backends) { // Set input data std::vector inputValues = { 0.f, 1.f, 2.f, 3.f, 4.f, 5.f }; // Set output data std::vector expectedOutputValues = { 0.f, 1.f, 2.f, 0.f, 1.f, 2.f, 3.f, 4.f, 5.f, 3.f, 4.f, 5.f, 0.f, 1.f, 2.f, 0.f, 1.f, 2.f, 3.f, 4.f, 5.f, 3.f, 4.f, 5.f }; // The multiples const std::vector multiplesValues = { 2, 2 }; // Set shapes const std::vector inputShape = { 2, 3 }; const std::vector multiplesShape = { 2 }; const std::vector expectedOutputShape = { 4, 6 }; TileFP32TestImpl(tflite::BuiltinOperator_TILE, backends, inputValues, inputShape, multiplesValues, multiplesShape, expectedOutputValues, expectedOutputShape); } TEST_SUITE("TileTests_GpuAccTests") { TEST_CASE ("Tile_Float32_GpuAcc_Test") { std::vector backends = { armnn::Compute::GpuAcc }; TileFloat32Test(backends); } } // TEST_SUITE("Tile_Float32_GpuAcc_Test") TEST_SUITE("TileTests_CpuAccTests") { TEST_CASE ("Tile_Float32_CpuAcc_Test") { std::vector backends = { armnn::Compute::CpuAcc }; TileFloat32Test(backends); } } // TEST_SUITE("Tile_Float32_CpuAcc_Test") TEST_SUITE("TileTests_CpuRefTests") { TEST_CASE ("Tile_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; TileFloat32Test(backends); } } // TEST_SUITE("Tile_Float32_CpuRef_Test") } // namespace armnnDelegatearmnn-23.08/delegate/test/TileTestHelper.hpp000066400000000000000000000165151446772241200210210ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateTileTfLiteModel(tflite::BuiltinOperator operatorCode, tflite::TensorType inputTensorType, const std::vector& inputTensorShape, const std::vector& multiplesTensorData, const std::vector& multiplesTensorShape, const std::vector& outputTensorShape) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(multiplesTensorData.data()), sizeof(int32_t) * multiplesTensorData.size()))); buffers.push_back(CreateBuffer(flatBufferBuilder)); std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), inputTensorType, 1, flatBufferBuilder.CreateString("input_tensor")); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(multiplesTensorShape.data(), multiplesTensorShape.size()), TensorType_INT32, 2, flatBufferBuilder.CreateString("axis_input_tensor")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), inputTensorType, 3, flatBufferBuilder.CreateString("output_tensor")); // Create Operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_NONE; flatbuffers::Offset operatorBuiltinOption = 0; const std::vector operatorInputs {0, 1}; const std::vector operatorOutputs {2}; flatbuffers::Offset tileOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOption); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&tileOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Tile Operator Model"); flatbuffers::Offset opCode = CreateOperatorCode(flatBufferBuilder, operatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&opCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } void TileFP32TestImpl(tflite::BuiltinOperator operatorCode, std::vector& backends, std::vector& inputValues, std::vector inputShape, std::vector multiplesValues, std::vector multiplesShapes, std::vector& expectedOutputValues, std::vector expectedOutputShape) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateTileTfLiteModel(operatorCode, ::tflite::TensorType::TensorType_FLOAT32, inputShape, multiplesValues, multiplesShapes, expectedOutputShape); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(multiplesValues, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(multiplesValues, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/TransposeConvolution2dTest.cpp000066400000000000000000000101601446772241200234110ustar00rootroot00000000000000// // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "ConvolutionTestHelper.hpp" #include #include #include #include #include #include #include #include namespace armnnDelegate { void TransposeConvInt8Test(std::vector& backends) { // Set input data std::vector transposeTensorShape { 4 }; std::vector filterShape { 1, 2, 2, 1 }; std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 1, 3, 3, 1 }; std::vector transposeData = { 1, 3, 3, 1 }; static std::vector inputValues = { 1, 2, 3, 4 }; std::vector filterValues = { 0, 1, 2, 4 }; std::vector expectedOutputValues = { 0, 1, 2, 2, 11, 12, 6, 20, 16 }; tflite::Padding padding = tflite::Padding_VALID; TransposeConvTest(backends, ::tflite::TensorType_INT8, 1, // strideX 1, // strideY padding, transposeTensorShape, filterShape, inputShape, outputShape, transposeData, filterValues, inputValues, expectedOutputValues); } void TransposeConvFp32Test(std::vector& backends) { std::vector transposeTensorShape { 4 }; std::vector filterShape { 1, 2, 2, 1 }; std::vector inputShape { 1, 2, 2, 1 }; std::vector outputShape { 1, 3, 3, 1 }; std::vector transposeData = { 1, 3, 3, 1 }; static std::vector inputValues = { 1, 2, 3, 4 }; std::vector filterValues = { 0, 1, 2, 4 }; std::vector expectedOutputValues = { 0, 1, 2, 2, 11, 12, 6, 20, 16 }; tflite::Padding padding = tflite::Padding_VALID; TransposeConvTest(backends, ::tflite::TensorType_FLOAT32, 1, // strideX 1, // strideY padding, transposeTensorShape, filterShape, inputShape, outputShape, transposeData, filterValues, inputValues, expectedOutputValues); } TEST_SUITE("TransposeConv_CpuRef_Test") { TEST_CASE ("TransposeConv_CpuRef_Fp32_Test") { std::vector backends = {armnn::Compute::CpuRef}; TransposeConvFp32Test(backends); } TEST_CASE ("TransposeConv_CpuRef_Int8_Test") { std::vector backends = {armnn::Compute::CpuRef}; TransposeConvInt8Test(backends); } } // End of TEST_SUITE(TransposeConv_CpuRef_Test) TEST_SUITE("TransposeConv_CpuAcc_Test") { TEST_CASE ("TransposeConv_CpuAcc_Fp32_Test") { std::vector backends = {armnn::Compute::CpuAcc}; TransposeConvFp32Test(backends); } TEST_CASE ("TransposeConv_CpuAcc_Int8_Test") { std::vector backends = {armnn::Compute::CpuAcc}; TransposeConvInt8Test(backends); } } // End of TEST_SUITE(TransposeConv_CpuAcc_Test) TEST_SUITE("TransposeConv_GpuAcc_Test") { TEST_CASE ("TransposeConv_GpuAcc_Fp32_Test") { std::vector backends = {armnn::Compute::GpuAcc}; TransposeConvFp32Test(backends); } TEST_CASE ("TransposeConv_GpuAcc_Int8_Test") { std::vector backends = {armnn::Compute::GpuAcc}; TransposeConvInt8Test(backends); } } // End of TEST_SUITE(TransposeConv_GpuAcc_Test) } // namespace armnnDelegatearmnn-23.08/delegate/test/TransposeTest.cpp000066400000000000000000000034371446772241200207340ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "TransposeTestHelper.hpp" #include #include #include namespace armnnDelegate { void TransposeFP32Test(std::vector& backends) { // set test input data std::vector input0Shape {4, 2, 3}; std::vector inputPermVecShape {3}; std::vector outputShape {3, 4, 2}; std::vector input0Values = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23}; std::vector inputPermVec = {2, 0, 1}; std::vector expectedOutputValues = {0, 3, 6, 9, 12, 15, 18, 21, 1, 4, 7, 10, 13, 16, 19, 22, 2, 5, 8, 11, 14, 17, 20, 23}; TransposeTest(backends, input0Shape, inputPermVecShape, outputShape, input0Values, inputPermVec, expectedOutputValues); } TEST_SUITE ("Transpose_GpuAccTests") { TEST_CASE ("Transpose_Float32_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; TransposeFP32Test(backends); } } TEST_SUITE ("Transpose_CpuAccTests") { TEST_CASE ("Transpose_Float32_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; TransposeFP32Test(backends); } } TEST_SUITE ("Transpose_CpuRefTests") { TEST_CASE ("Transpose_Float32_CpuRef_Test") { std::vector backends = { armnn::Compute::CpuRef }; TransposeFP32Test(backends); } } } // namespace armnnDelegate armnn-23.08/delegate/test/TransposeTestHelper.hpp000066400000000000000000000153321446772241200220760ustar00rootroot00000000000000// // Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateTransposeTfLiteModel(tflite::TensorType tensorType, const std::vector & input0TensorShape, const std::vector & inputPermVecShape, const std::vector & outputTensorShape, const std::vector& inputPermVec) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; flatbuffers::Offset buffers[4]{ CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder), CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputPermVec.data()), sizeof(int32_t) * inputPermVec.size())), CreateBuffer(flatBufferBuilder) }; std::array, 3> tensors; tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(input0TensorShape.data(), input0TensorShape.size()), tensorType, 1); tensors[1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputPermVecShape.data(), inputPermVecShape.size()), tflite::TensorType_INT32, 2, flatBufferBuilder.CreateString("permutation_vector")); tensors[2] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType,3); const std::vector operatorInputs{0, 1}; const std::vector operatorOutputs{2}; flatbuffers::Offset transposeOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), BuiltinOptions_TransposeOptions, CreateTransposeOptions(flatBufferBuilder).Union()); const std::vector subgraphInputs{0, 1}; const std::vector subgraphOutputs{2}; flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&transposeOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Transpose Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_TRANSPOSE); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers, 4)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void TransposeTest(std::vector& backends, std::vector& inputShape, std::vector& inputPermVecShape, std::vector& outputShape, std::vector& inputValues, std::vector& inputPermVec, std::vector& expectedOutputValues) { using namespace delegateTestInterpreter; // Create model std::vector modelBuffer = CreateTransposeTfLiteModel(::tflite::TensorType_FLOAT32, inputShape, inputPermVecShape, outputShape, inputPermVec); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputPermVec, 1) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputPermVec, 1) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } armnn-23.08/delegate/test/UnidirectionalSequenceLstmTest.cpp000066400000000000000000002503531446772241200242610ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "UnidirectionalSequenceLstmTestHelper.hpp" #include #include #include #include namespace armnnDelegate { void UnidirectionalSequenceLstmTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; //tensorInfo12, bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -0.49536117f, -0.0556083915f, -0.102400711f, -0.117484632f, 0.3298470976f, -0.1179017122f, 0.214305695f, 0.42135173085f, 0.003878414626f, -0.348303917f, -0.1881275477f, 0.0343011027f }; std::vector inputToForgetWeights = { 0.2415594226f, 0.15400093799f, 0.4566498398f, -0.3810434485f, 0.268383264f, -0.009807467424f, -0.3522925403f, -0.24275735512f, -0.28344226125f, 0.13512269116f, -0.4932442977f, -0.10039821991f }; std::vector inputToCellWeights = { -0.2504855627f, 0.184490025045f, -0.2480507493f, 0.386399507f, -0.259465157985f, -0.16545993089f, -0.4230232555f, 0.341664791103f, -0.18127849691f, -0.2277662414f, -0.55275535589f, 0.34184026718f }; std::vector inputToOutputWeights = { 0.2303854227f, 0.5218806862f, -0.4865379333f, 0.53969591851f, 0.23393625035f, -0.27140527306f, 0.50009280443f, 0.07511717046f, 0.3998299249f, -0.51717478049f, 0.1889653282f, -0.367323637f }; //tensorInfo16, bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -0.128009796112f, 0.1995525098f, -0.07745539397f, 0.1558421701f, -0.265254765766f, -0.38837709614f, -0.05636804124f, 0.4259087456f, 0.17628988623f, 0.3877420127f, 0.53300309181f, -0.0959980934f, 0.00302857416f, 0.3266998827f, -0.142509296562f, -0.04433270756f }; std::vector recurrentToForgetWeights = { -0.09499983487f, -0.08814888417f, -0.04834804721f, 0.1516668247f, -0.3967529535f, -0.06463699788f, 0.4952811002f, 0.003274492938f, -0.0968840941f, 0.17928104102f, 0.0031281141592f, -0.3387276584f, -0.3587934076f, 0.06705895066f, 0.22463923692f, 0.1961955726f }; std::vector recurrentToCellWeights = { -0.21938985582f, -0.3023648226f, -0.1170005202f, -0.3509177422f, -0.4286288613f, 0.2726137042f, 0.09216640889f, -0.06551410215f, 0.20453298098f, 0.2393476665f, 0.11846517771f, 0.2630801796f, 0.3954237699f, -0.19407111404f, 0.30412107706f, -0.27342408554f }; std::vector recurrentToOutputWeights = { -0.32921677827f, 0.32624614238f, -0.1388191282f, -0.17879831790f, -0.15185534954f, -0.16918526583f, -0.10087361183f, -0.5436913968f, 0.016758225858f, 0.30454617738f, -0.41493862867f, -0.005565764375f, -0.12584099173f, -0.12319286912f, 0.2407919466f, -0.08879069983f }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = false; std::vector cellToForgetWeights; bool hasCellToOutputWeights = false; std::vector cellToOutputWeights; bool hasInputGateBias = true; std::vector inputGateBias = {0., 0., 0., 0.}; std::vector forgetGateBias = {1., 1., 1., 1.}; std::vector cellBias = {0., 0., 0., 0.}; std::vector outputGateBias = {0., 0., 0., 0.}; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2. }; std::vector expectedOutputValues = { -0.0714901f, -0.162117f, -0.175168f, -0.0232934f, -0.168107f, -0.414129f, -0.549875f, -0.00803579f, -0.0668735f, 0.204078f, -0.42765f, -0.0312321f, -0.120003f, -0.0941918f, -0.456391f, -0.0287019f, -0.0342921f, 0.20824f, -0.656989f, -0.00415265f, -0.10493f, 0.14211f, -0.583478f, -0.0329754f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor); } void UnidirectionalSequenceLstmTimeMajorTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; std::vector inputShape = {timeSize, batchSize, inputSize}; std::vector cellStateInTensorInfo = {batchSize, numUnits}; std::vector outputStateInTensorInfo = {batchSize, outputSize}; std::vector outputTensorInfo = {timeSize, batchSize, outputSize}; //tensorInfo12 bool hasInputToInputWeights = true; std::vector inputToInputWeights = { 0.27277296781539917f, 0.3813590407371521f, -0.394489049911499f, 0.2782636880874634f, -0.3793870210647583f, -0.018918335437774658f, 0.2724653482437134f, -0.19314253330230713f, -0.2947450876235962f, -0.30253493785858154f, 0.4241350293159485f, -0.22560018301010132f }; std::vector inputToForgetWeights = { -0.2667974531650543f, -0.05505800247192383f, -0.20932340621948242f, -0.14345619082450867f, 0.09666192531585693f, -0.2604355812072754f, -0.2681812047958374f, -0.3314584493637085f, 0.4485899806022644f, -0.23467743396759033f, 0.5072842240333557f, -0.4192768931388855f }; std::vector inputToCellWeights = { -0.15782442688941956f, -0.027530014514923096f, 0.4789854884147644f, 0.23227906227111816f, 0.28259342908859253f, -0.030095696449279785f, 0.10071521997451782f, -0.08535495400428772f, 0.18563997745513916f, -0.3049069046974182f, -0.478048175573349f, 0.025234103202819824f }; std::vector inputToOutputWeights = { -0.04584759473800659f, -0.2716066539287567f, 0.012970447540283203f, -0.4729190170764923f, -0.37422770261764526f, 0.49352723360061646f, 0.3163864016532898f, -0.436781644821167f, -0.33074596524238586f, -0.32885751128196716f, -0.40959352254867554f, -0.2124689817428589f }; //tensorInfo16 bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { 0.23788475990f, -0.24948765337f, 0.50044941902f, 0.14431896805f, -0.115940228137f, -0.717082679f, -0.17208620906f, 0.17850610617f, -0.16702319684f, -0.11384502053f, -0.309785276245f, -0.3316611672f, 0.52380162477f, -0.06839632987f, -0.391478359627f, -0.10756178963f }; std::vector recurrentToForgetWeights = { 0.11383482068f, 0.1676601767f, -0.08550968004f, 0.03399394089f, 0.08042152225f, -0.2133381964f, 0.05182432704f, 0.38161808255f, -0.5018365979f, -0.08043262364f, 0.07894329014f, -0.07547105155f, 0.12047368288f, 0.2986997961f, 0.0485043078f, -0.13372567296f }; std::vector recurrentToCellWeights = { 0.0433832928545f, 0.07587072294f, -0.120520234107f, 0.604576051f, -0.434353142986f, 0.009314475068f, 0.005085289478f, 0.08488202038f, -0.00025437487886f, 0.15245915082f, -0.1936587542f, 0.004754020f, -0.1582719236f, 0.3307867646f, 0.0236605107784f, 0.307716339826f }; std::vector recurrentToOutputWeights = { -0.079031050201f, 0.041414566286f, -0.583727357285f, 0.1025384515f, -0.172372072937f, 0.09214124082f, 0.178184121827f, -0.2439443916f, 0.104485116899f, 0.2600405514f, 0.064414866268f, 0.24141204357f, 0.281875759363f, -0.14234502664f, 0.15126448862f, -0.24421440064f }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = false; std::vector cellToForgetWeights; bool hasCellToOutputWeights = false; std::vector cellToOutputWeights; bool hasInputGateBias = true; std::vector inputGateBias = {0., 0., 0., 0.}; std::vector forgetGateBias = {1., 1., 1., 1.}; std::vector cellBias = {0., 0., 0., 0.}; std::vector outputGateBias = {0., 0., 0., 0.}; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2. }; std::vector expectedOutputValues = { 0.135658f, 0.124673f, 0.021209f, -0.0530204f, 0.106138f, 0.0404792f, 0.0151644f, -0.00675166f, -0.0128514f, 0.0644884f, 0.0709072f, -0.0454045f, 0.162886f, 0.166494f, 0.0277046f, -0.0369807f, 0.111716f, 0.043119f, 0.0762981f, -0.0122854f, 0.104397f, 0.2144f, 0.119192f, -0.0839058f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = true; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor); } void UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionTest(std::vector& backends) { int32_t batchSize = 2; int32_t timeSize = 3; int32_t inputSize = 4; int32_t outputSize = 5; int32_t numUnits = 6; std::vector inputShape = {batchSize, timeSize, inputSize}; std::vector cellStateInTensorInfo = {batchSize, numUnits}; std::vector outputStateInTensorInfo = {batchSize, outputSize}; std::vector outputTensorInfo = {batchSize, timeSize, outputSize}; //tensorInfoInputSize, bool hasInputToInputWeights = true; std::vector inputToInputWeights = { 0.021393683f, 0.06124551f, 0.046905167f, -0.014657677f, -0.03149463f, 0.09171803f, 0.14647801f, 0.10797193f, -0.0057968358f, 0.0019193048f, -0.2726754f, 0.10154029f, -0.018539885f, 0.080349885f, -0.10262385f, -0.022599787f, -0.09121155f, -0.008675967f, -0.045206103f, -0.0821282f, -0.008045952f, 0.015478081f, 0.055217247f, 0.038719587f }; std::vector inputToForgetWeights = { -0.0018401089f, -0.004852237f, 0.03698424f, 0.014181704f, 0.028273236f, -0.016726194f, -0.05249759f, -0.10204261f, 0.00861066f, -0.040979505f, -0.009899187f, 0.01923892f, -0.028177269f, -0.08535103f, -0.14585495f, 0.10662567f, -0.01909731f, -0.017883534f, -0.0047269356f, -0.045103323f, 0.0030784295f, 0.076784775f, 0.07463696f, 0.094531395f}; std::vector inputToCellWeights = { -0.04580283f, -0.09549462f, -0.032418985f, -0.06454633f, -0.043528453f, 0.043018587f, -0.049152344f, -0.12418144f, -0.078985475f, -0.07596889f, 0.019484362f, -0.11434962f, -0.0074034138f, -0.06314844f, -0.092981495f, 0.0062155537f, -0.025034338f, -0.0028890965f, 0.048929527f, 0.06235075f, 0.10665918f, -0.032036792f, -0.08505916f, -0.10843358f }; std::vector inputToOutputWeights = { -0.0998932f, -0.07201956f, -0.052803773f, -0.15629593f, -0.15001918f, -0.07650751f, 0.02359855f, -0.075155355f, -0.08037709f, -0.15093534f, 0.029517552f, -0.04751393f, 0.010350531f, -0.02664851f, -0.016839722f, -0.023121163f, 0.0077019283f, 0.012851257f, -0.05040649f, -0.0129761f, -0.021737747f, -0.038305793f, -0.06870586f, -0.01481247f }; //tensorInfoOutputSize, bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -0.001374326f, -0.078856036f, 0.10672688f, 0.029162422f, -0.11585556f, 0.02557986f, -0.13446963f, -0.035785314f, -0.01244275f, 0.025961924f, -0.02337298f, -0.044228926f, -0.055839065f, -0.046598054f, -0.010546039f, -0.06900766f, 0.027239809f, 0.022582639f, -0.013296484f, -0.05459212f, 0.08981f, -0.045407712f, 0.08682226f, -0.06867011f, -0.14390695f, -0.02916037f, 0.000996957f, 0.091420636f, 0.14283475f, -0.07390571f }; std::vector recurrentToForgetWeights = { -0.057784554f, -0.026057621f, -0.068447545f, -0.022581743f, 0.14811787f, 0.10826372f, 0.09471067f, 0.03987225f, -0.0039523416f, 0.00030638507f, 0.053185795f, 0.10572994f, 0.08414449f, -0.022036452f, -0.00066928595f, -0.09203576f, 0.032950465f, -0.10985798f, -0.023809856f, 0.0021431844f, -0.02196096f, -0.00326074f, 0.00058621005f, -0.074678116f, -0.06193199f, 0.055729095f, 0.03736828f, 0.020123724f, 0.061878487f, -0.04729229f }; std::vector recurrentToCellWeights = { -0.037322544f, 0.018592842f, 0.0056175636f, -0.06253426f, 0.055647098f, -0.05713207f, -0.05626563f, 0.005559383f, 0.03375411f, -0.025757805f, -0.088049285f, 0.06017052f, -0.06570978f, 0.007384076f, 0.035123326f, -0.07920549f, 0.053676967f, 0.044480428f, -0.07663568f, 0.0071805613f, 0.08089997f, 0.05143358f, 0.038261272f, 0.03339287f, -0.027673481f, 0.044746667f, 0.028349208f, 0.020090483f, -0.019443132f, -0.030755889f }; std::vector recurrentToOutputWeights = { 0.025825322f, -0.05813119f, 0.09495884f, -0.045984812f,-0.01255415f, -0.0026479573f, -0.08196161f, -0.054914974f, -0.0046604523f, -0.029587349f, -0.044576716f, -0.07480124f, -0.082868785f, 0.023254942f, 0.027502948f, -0.0039728214f, -0.08683098f, -0.08116779f, -0.014675607f, -0.037924774f, -0.023314456f, -0.007401714f, -0.09255757f, 0.029460307f, -0.08829125f, -0.005139627f, -0.08989442f, -0.0555066f, 0.13596267f, 0.025062224f }; // tensorInfoNumUnits bool hasCellToInputWeights = true; std::vector cellToInputWeights = { 0.040369894f, 0.030746894f, 0.24704495f, 0.018586371f, -0.037586458f, -0.15312155f }; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = { -0.01998659f, -0.15568835f, -0.24248174f, -0.012770197f, 0.041331276f, -0.072311886f }; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = { 0.08286371f, -0.08261836f, -0.51210177f, 0.002913762f, 0.17764764f, -0.5495371f }; bool hasInputGateBias = true; std::vector inputGateBias = { 0.02234832f, 0.14757581f, 0.18176508f, 0.10380666f, 0.053110216f, -0.06928846f }; std::vector forgetGateBias = { 0.035185695f, -0.042891346f, -0.03032477f, 0.23027696f, 0.11098921f, 0.08989442f }; std::vector cellBias = { -0.024379363f, 0.0055531194f, 0.23377132f, 0.033463873f, -0.1483596f, 0.029460307f }; std::vector outputGateBias = { 0.046159424f, -0.0012809046f, 0.03563469f, 0.12648113f, 0.027195795f, 0.35373217f }; bool hasProjectionWeights = true; std::vector projectionWeights = { -0.009802181f, 0.09401916f, 0.0717386f, -0.13895074f, 0.09641832f, 0.060420845f, 0.08539281f, 0.054285463f, 0.061395317f, 0.034448683f, -0.042991187f, 0.019801661f, -0.16840284f, -0.015726732f, -0.23041931f, -0.024478018f, -0.10959692f, -0.013875541f, 0.18600968f, -0.061274476f, 0.0138165f, -0.08160894f, -0.07661644f, 0.032372914f, 0.16169067f, 0.22465782f, -0.03993472f, -0.004017731f, 0.08633481f, -0.28869787f }; bool hasProjectionBias = true; std::vector projectionBias(outputSize, 0.f); bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 1., 2., 3., 4., 5., 4.}; std::vector expectedOutputValues = { -0.0135612f, -0.0263441f, 0.0314008f, -0.00883455f, 0.00763052f, -0.00126877f, -0.0292959f, 0.0449957f, -0.00976195f, -0.00492338f, -0.0175702f, -0.0431753f, 0.0597117f, -0.0169154f, 0.0142087f, 0.00472515f, -0.0196355f, 0.0342524f, -0.00407936f, -0.0253189f, -0.00512944f, -0.0293754f, 0.0512771f, -0.0151874f, -0.0246433f, -0.00744986f, -0.0345103f, 0.0450666f, -0.00944991f, 0.0126895f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor); } void UnidirectionalSequenceLstmWithCifgWithPeepholeNoProjectionTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; //tensorInfo12 bool hasInputToInputWeights = false; std::vector inputToInputWeights{}; std::vector inputToForgetWeights = { 0.2415594226f, 0.15400093799f, 0.4566498398f, -0.3810434485f, 0.268383264f, -0.009807467424f, -0.3522925403f, -0.24275735512f, -0.28344226125f, 0.13512269116f, -0.4932442977f, -0.10039821991f }; std::vector inputToCellWeights = { -0.2504855627f, 0.184490025045f, -0.2480507493f, 0.386399507f, -0.259465157985f, -0.16545993089f, -0.4230232555f, 0.341664791103f, -0.18127849691f, -0.2277662414f, -0.55275535589f, 0.34184026718f }; std::vector inputToOutputWeights = { 0.2303854227f, 0.5218806862f, -0.4865379333f, 0.53969591851f, 0.23393625035f, -0.27140527306f, 0.50009280443f, 0.07511717046f, 0.3998299249f, -0.51717478049f, 0.1889653282f, -0.367323637f }; //tensorInfo16 bool hasRecurrentToInputWeights = false; std::vector recurrentToInputWeights{}; std::vector recurrentToForgetWeights = { -0.09499983487f, -0.08814888417f, -0.04834804721f, 0.1516668247f, -0.3967529535f, -0.06463699788f, 0.4952811002f, 0.003274492938f, -0.0968840941f, 0.17928104102f, 0.0031281141592f, -0.3387276584f, -0.3587934076f, 0.06705895066f, 0.22463923692f, 0.1961955726f }; std::vector recurrentToCellWeights = { -0.21938985582f, -0.3023648226f, -0.1170005202f, -0.3509177422f, -0.4286288613f, 0.2726137042f, 0.09216640889f, -0.06551410215f, 0.20453298098f, 0.2393476665f, 0.11846517771f, 0.2630801796f, 0.3954237699f, -0.19407111404f, 0.30412107706f, -0.27342408554f }; std::vector recurrentToOutputWeights = { -0.32921677827f, 0.32624614238f, -0.1388191282f, -0.17879831790f, -0.15185534954f, -0.16918526583f, -0.10087361183f, -0.5436913968f, 0.016758225858f, 0.30454617738f, -0.41493862867f, -0.005565764375f, -0.12584099173f, -0.12319286912f, 0.2407919466f, -0.08879069983f }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = {0.47485286f, -0.51955009f, -0.24458408f, 0.31544167f}; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = {-0.17135078f, 0.82760304f, 0.85573703f, -0.77109635f}; bool hasInputGateBias = false; std::vector inputGateBias; std::vector forgetGateBias = {1., 1., 1., 1.}; std::vector cellBias = {0., 0., 0., 0.}; std::vector outputGateBias = {0., 0., 0., 0.}; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2. }; std::vector expectedOutputValues = { -0.0129257f, -0.070531f, -0.153508f, -0.0392391f, -0.0300169f, -0.195717f, -0.528679f, -0.0818106f, -0.0332748f, 0.155429f, -0.353966f, -0.0801505f, -0.032312f, -0.0407911f, -0.435053f, -0.0932317f, -0.0108233f, 0.165584f, -0.640424f, -0.0447535f, -0.031675f, 0.125987f, -0.526695f, -0.110093f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor); } void UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionWithLayerNormTest( std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; int32_t numUnits = 5; //tensorInfo15 bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -0.49536117f, -0.0556083915f, -0.102400711f, -0.117484632f, 0.3298470976f, -0.1179017122f, 0.214305695f, 0.42135173085f, 0.003878414626f, -0.348303917f, -0.1881275477f, 0.0343011027f, -0.38837709614f, -0.05636804124f, 0.4259087456f}; std::vector inputToForgetWeights = { 0.2415594226f, 0.15400093799f, 0.4566498398f, -0.3810434485f, 0.268383264f, -0.009807467424f, -0.3522925403f, -0.24275735512f, -0.28344226125f, 0.13512269116f, -0.4932442977f, -0.10039821991f, 0.2726137042f, 0.09216640889f, -0.06551410215f}; std::vector inputToCellWeights = { -0.2504855627f, 0.184490025045f, -0.2480507493f, 0.386399507f, -0.259465157985f, -0.16545993089f, -0.4230232555f, 0.341664791103f, -0.18127849691f, -0.2277662414f, -0.55275535589f, 0.34184026718f, 0.3954237699f, -0.19407111404f, 0.30412107706f}; std::vector inputToOutputWeights = { 0.2303854227f, 0.5218806862f, -0.4865379333f, 0.53969591851f, 0.23393625035f, -0.27140527306f, 0.50009280443f, 0.07511717046f, 0.3998299249f, -0.51717478049f, 0.1889653282f, -0.367323637f, -0.12584099173f, -0.12319286912f, 0.2407919466f}; //tensorInfo20 bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -0.128009796112f, 0.1995525098f, -0.07745539397f, 0.1558421701f, -0.265254765766f, -0.38837709614f, -0.05636804124f, 0.4259087456f, 0.17628988623f, 0.3877420127f, 0.53300309181f, -0.0959980934f, 0.00302857416f, 0.3266998827f, -0.142509296562f, -0.04433270756f, 0.54066205f, -0.32668582f, -0.43562764f, -0.56094903f }; std::vector recurrentToForgetWeights = { -0.09499983487f, -0.08814888417f, -0.04834804721f, 0.1516668247f, -0.3967529535f, -0.06463699788f, 0.4952811002f, 0.003274492938f, -0.0968840941f, 0.17928104102f, 0.0031281141592f, -0.3387276584f, -0.3587934076f, 0.06705895066f, 0.22463923692f, 0.1961955726f, 0.01841056f, -0.32764608f, -0.33027974f, -0.10826075f }; std::vector recurrentToCellWeights = { -0.21938985582f, -0.3023648226f, -0.1170005202f, -0.3509177422f, -0.4286288613f, 0.2726137042f, 0.09216640889f, -0.06551410215f, 0.20453298098f, 0.2393476665f, 0.11846517771f, 0.2630801796f, 0.3954237699f, -0.19407111404f, 0.30412107706f, -0.27342408554f, 0.19069612f, -0.03026325f, -0.54532051f, 0.33003211f }; std::vector recurrentToOutputWeights = { -0.32921677827f, 0.32624614238f, -0.1388191282f, -0.17879831790f, -0.15185534954f, -0.16918526583f, -0.10087361183f, -0.5436913968f, 0.016758225858f, 0.30454617738f, -0.41493862867f, -0.005565764375f, -0.12584099173f, -0.12319286912f, 0.2407919466f, -0.08879069983f, 0.11178309f, 0.09481031f, -0.26424935f, 0.46261835f }; // tensorInfo5 bool hasCellToInputWeights = true; std::vector cellToInputWeights = { 0.05f, 0.1f, 0.25f, 0.15f, -0.02f }; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = { -0.02f, -0.15f, -0.25f, -0.03f, 0.15f }; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = { 0.1f, -0.1f, -0.5f, 0.05f, 0.01f }; bool hasInputGateBias = true; std::vector inputGateBias = { 0.03f, 0.15f, 0.22f, 0.38f, 0.05f }; std::vector forgetGateBias = { 0.1f, -0.3f, -0.2f, 0.1f, 0.4f }; std::vector cellBias = { -0.05f, 0.72f, 0.25f, 0.08f, 0.1f }; std::vector outputGateBias = { 0.05f, -0.01f, 0.2f, 0.1f, -0.2f }; bool hasProjectionWeights = true; std::vector projectionWeights = { -0.1f, 0.2f, 0.01f, -0.2f, 0.1f, 0.5f, 0.3f, 0.08f, 0.07f, 0.2f, -0.4f, 0.2f, 0.5f, -0.4f, 0.3f, -0.2f, 0.3f, 0.08f, -0.07f, 0.2f}; //{outputSize, numUnits} bool hasProjectionBias = true; std::vector projectionBias(outputSize, 0.f);; bool hasInputLayerNormWeights = true; std::vector inputLayerNormWeights = { 0.1f, 0.2f, 0.3f, 0.5f, 0.8f }; bool hasForgetLayerNormWeights = true; std::vector forgetLayerNormWeights = { 0.1f, 0.2f, 0.3f, 0.5f, 0.2f }; bool hasCellLayerNormWeights = true; std::vector cellLayerNormWeights = { 0.7f, 0.2f, 0.3f, 0.8f, 0.5f }; bool hasOutputLayerNormWeights = true; std::vector outputLayerNormWeights = { 0.6f, 0.2f, 0.2f, 0.5f, 0.1f }; std::vector inputValues = { 1., 2., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2. }; std::vector expectedOutputValues = { 0.0642256f, 0.0343966f, 0.184122f, 0.114717f, 0.11458f, 0.0407109f, 0.300327f, 0.174301f, 0.0864761f, 0.0362912f, 0.178635f, 0.115689f, 0.108008f, 0.0386623f, 0.273471f, 0.167115f, 0.0859545f, 0.0331481f, 0.186051f, 0.11888f, 0.106649f, 0.0276847f, 0.229863f, 0.166958f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_FLOAT32, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor); } void UnidirectionalSequenceLstmInt8Test(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; //tensorInfo12 bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -4, -1, -1, -2, 3, -2, 2, 4, 1, -4, -2, 3 }; std::vector inputToForgetWeights = { 2, 1, 4, -4, 3, -1, -3, -2, -3, 1, -4, -1 }; std::vector inputToCellWeights = { -2, 1, -2, 4, -3, -2, -4, 3, -2, -2, -6, 3 }; std::vector inputToOutputWeights = { 2, 5, -4, 5, 2, -3, 5, 7, 3, -5, 1, -4 }; //tensorInfo16 bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -1, -1 }; std::vector recurrentToForgetWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -2, -1 }; std::vector recurrentToCellWeights = { -2, -3, -1, -3, -4, 2, 1, -1, 2, 2, 1, 2, 3, -2, 3, -3 }; std::vector recurrentToOutputWeights = { -3, 3, -1, -2, -2, -2, -1, -5, 1, 3, -4, -1, -1, -1, 2, -1 }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = false; std::vector cellToForgetWeights; bool hasCellToOutputWeights = false; std::vector cellToOutputWeights; bool hasInputGateBias = true; std::vector inputGateBias = { 0., 0., 0., 0. }; std::vector forgetGateBias = { 1., 1., 1., 1. }; std::vector cellBias = { 0., 0., 0., 0. }; std::vector outputGateBias = { 0., 0., 0., 0. }; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f }; std::vector expectedOutputValues = { -0.0142517f, -0.0198845f, -0.0120569f, -0.0116868f, -0.0350714f, -0.0343202f, -0.047504f, -0.0569789f, -0.0146346f, 0.0106663f, -0.0247238f, -0.0319502f, -0.0294759f, -0.0129935f, -0.0444175f, -0.0444354f, -0.0280855f, 0.00545101f, -0.051422f, -0.0463838f, -0.0310702f, 0.00915739f, -0.0625207f, -0.0482648f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_INT8, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, 0.1f); } void UnidirectionalSequenceLstmInt8TimeMajorTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; //tensorInfo12 bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -4, -1, -1, -2, 3, -2, 2, 4, 1, -4, -2, 3 }; std::vector inputToForgetWeights = { 2, 1, 4, -4, 3, -1, -3, -2, -3, 1, -4, -1 }; std::vector inputToCellWeights = { -2, 1, -2, 4, -3, -2, -4, 3, -2, -2, -6, 3 }; std::vector inputToOutputWeights = { 2, 5, -4, 5, 2, -3, 5, 7, 3, -5, 1, -4 }; //tensorInfo16 bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -1, -1 }; std::vector recurrentToForgetWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -2, -1 }; std::vector recurrentToCellWeights = { -2, -3, -1, -3, -4, 2, 1, -1, 2, 2, 1, 2, 3, -2, 3, -3 }; std::vector recurrentToOutputWeights = { -3, 3, -1, -2, -2, -2, -1, -5, 1, 3, -4, -1, -1, -1, 2, -1 }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = false; std::vector cellToForgetWeights; bool hasCellToOutputWeights = false; std::vector cellToOutputWeights; bool hasInputGateBias = true; std::vector inputGateBias = { 0., 0., 0., 0. }; std::vector forgetGateBias = { 1., 1., 1., 1. }; std::vector cellBias = { 0., 0., 0., 0. }; std::vector outputGateBias = { 0., 0., 0., 0. }; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f }; std::vector expectedOutputValues = { -0.0142517f, -0.0198845f, -0.0120122f, -0.0116868f, -0.0261295f, -0.0188487f, -0.0345463f, -0.049733f, -0.0146346f, 0.0106663f, -0.0247238f, -0.0319502f, -0.0291863f, -0.0369402f, -0.0354071f, -0.0296529f, -0.0419539f, -0.00617731f, -0.0814796f, -0.0804005f, -0.0244737f, 0.0119905f, -0.0457527f, -0.0331862f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = true; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_INT8, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, 0.1); } void UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; int32_t numUnits = 4; bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -4, -1, -1, -2, 3, -2, 2, 4, 1, -4, -2, 3 }; std::vector inputToForgetWeights = { 2, 1, 4, -4, 3, -1, -3, -2, -3, 1, -4, -1 }; std::vector inputToCellWeights = { -2, 1, -2, 4, -3, -2, -4, 3, -2, -2, -6, 3 }; std::vector inputToOutputWeights = { 2, 5, -4, 5, 2, -3, 5, 7, 3, -5, 1, -4 }; //tensorInfo16 bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -1, -1 }; std::vector recurrentToForgetWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -2, -1 }; std::vector recurrentToCellWeights = { -2, -3, -1, -3, -4, 2, 1, -1, 2, 2, 1, 2, 3, -2, 3, -3 }; std::vector recurrentToOutputWeights = { -3, 3, -1, -2, -2, -2, -1, -5, 1, 3, -4, -1, -1, -1, 2, -1 }; // tensorInfo4 bool hasCellToInputWeights = true; std::vector cellToInputWeights = { 5, 10, 25, 15 }; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = { -5, 15, 25, 3 }; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = { 10, -10, -5, 50 }; bool hasInputGateBias = true; std::vector inputGateBias = { 0.02234832f, 0.14757581f, 0.18176508f, 0.10380666f}; std::vector forgetGateBias = { 0.035185695f, -0.042891346f, -0.3032477f, 0.23027696f}; std::vector cellBias = { -0.124379363f, 0.55531194f, 0.23377132f, 0.033463873f }; std::vector outputGateBias = { 0.046159424f, -0.12809046f, 0.03563469f, 0.12648113f }; bool hasProjectionWeights = true; std::vector projectionWeights = { -25, 51, 3, -5, 25, 127, 77, 20, 18, 51, -10, 51, -25, 88, 77, -13 }; bool hasProjectionBias = true; std::vector projectionBias(outputSize, 0.f); bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f }; std::vector expectedOutputValues = { 0.612103f, 1.56788f, 0.31966f, 1.42956f, 0.909718f, 3.07916f, -0.560586f, 3.8907f, 0.753671f, 1.77485f, 0.365122f, 1.60077f, 0.812644f, 2.79092f, -0.605396f, 3.61742f, 0.791857f, 1.64353f, 0.316588f, 1.55192f, 0.807265f, 2.47012f, -0.539598f, 3.25654f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_INT8, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, 0.1f); } void UnidirectionalSequenceLstmInt8WithCifgWithPeepholeNoProjectionTest(std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; // cellSize and outputSize have the same size when there is no projection. int32_t numUnits = outputSize; //tensorInfo12, bool hasInputToInputWeights = false; std::vector inputToInputWeights; std::vector inputToForgetWeights = { 2, 1, 4, -4, 3, -1, -3, -2, -3, 1, -4, -1 }; std::vector inputToCellWeights = { -2, 1, -2, 4, -3, -2, -4, 3, -2, -2, -6, 3 }; std::vector inputToOutputWeights = { 2, 5, -4, 5, 2, -3, 5, 7, 3, -5, 1, -4 }; //tensorInfo16, bool hasRecurrentToInputWeights = false; std::vector recurrentToInputWeights; std::vector recurrentToForgetWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -2, -1 }; std::vector recurrentToCellWeights = { -2, -3, -1, -3, -4, 2, 1, -1, 2, 2, 1, 2, 3, -2, 3, -3 }; std::vector recurrentToOutputWeights = { -3, 3, -1, -2, -2, -2, -1, -5, 1, 3, -4, -1, -1, -1, 2, -1 }; // tensorInfo4 bool hasCellToInputWeights = false; std::vector cellToInputWeights; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = { 47, -52, -24, 31 }; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = { -17, 82, 85, -77 }; bool hasInputGateBias = false; std::vector inputGateBias; std::vector forgetGateBias = { 1., 1., 1., 1. }; std::vector cellBias = { 0., 0., 0., 0. }; std::vector outputGateBias = { 0., 0., 0., 0. }; bool hasProjectionWeights = false; std::vector projectionWeights; bool hasProjectionBias = false; std::vector projectionBias; bool hasInputLayerNormWeights = false; std::vector inputLayerNormWeights; bool hasForgetLayerNormWeights = false; std::vector forgetLayerNormWeights; bool hasCellLayerNormWeights = false; std::vector cellLayerNormWeights; bool hasOutputLayerNormWeights = false; std::vector outputLayerNormWeights; std::vector inputValues = { 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f, 0.3f, 0.4f, 0.5f, 0.4f, 0.3f, 0.2f, 0.1f, 0.2f }; std::vector expectedOutputValues = { -0.0072104f, -0.00991171f, -0.00650478f, -0.00713055f, -0.0191782f, -0.0161269f, -0.0233683f, -0.054299f, -0.00783725f, 0.00635271f, -0.0126718f, -0.022613f, -0.0161351f, -0.00775868f, -0.021054f, -0.0339778f, -0.0146392f, 0.00330261f, -0.0258733f, -0.0407797f, -0.0174297f, 0.0050105f, -0.0266275f, -0.0362564f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_INT8, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, 0.1); } void UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionWithLayerNormTest( std::vector& backends) { int32_t batchSize = 3; int32_t timeSize = 2; int32_t inputSize = 3; int32_t outputSize = 4; int32_t numUnits = 5; bool hasInputToInputWeights = true; std::vector inputToInputWeights = { -4, -1, -1, -2, 3, -2, 2, 4, 1, -4, -2, 3, 2, 2, -4 }; std::vector inputToForgetWeights = { 2, 1, 4, -4, 3, -1, -3, -2, -3, 1, -4, -1, -3, -2, -4 }; std::vector inputToCellWeights = { -2, 1, -2, 4, -3, -2, -4, 3, -2, -2, -6, 3, 2, 5, -4 }; std::vector inputToOutputWeights = { 2, 5, -4, 5, 2, -3, 5, 7, 3, -5, 1, -4, -4, -1, -1 }; bool hasRecurrentToInputWeights = true; std::vector recurrentToInputWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -1, -1, -1, 4, 2, 3 }; std::vector recurrentToForgetWeights = { -1, 1, -1, 1, -3, -4, -1, 4, 2, 3, 5, -1, 1, 3, -2, -1, -1, 2, 2, 1 }; std::vector recurrentToCellWeights = { -2, -3, -1, -3, -4, 2, 1, -1, 2, 2, 1, 2, 3, -2, 3, -3, -1, -5, 1, 3 }; std::vector recurrentToOutputWeights = { -3, 3, -1, -2, -2, -2, -1, -5, 1, 3, -4, -1, -1, -1, 2, -1, 5, 1, -3, -4 }; // tensorInfo5 bool hasCellToInputWeights = true; std::vector cellToInputWeights = { 5, 3, 8, -5, 2 }; bool hasCellToForgetWeights = true; std::vector cellToForgetWeights = { -2, -7, 5, -3, 4 }; bool hasCellToOutputWeights = true; std::vector cellToOutputWeights = { 9, -10 , -5, 5, 1 }; bool hasInputGateBias = true; std::vector inputGateBias = { 0.03f, 0.15f, 0.22f, 0.38f, 0.05f }; std::vector forgetGateBias = { 0.1f, -0.3f, -0.2f, 0.1f, 0.4f }; std::vector cellBias = { -0.05f, 0.72f, 0.25f, 0.08f, 0.1f }; std::vector outputGateBias = { 0.05f, -0.01f, 0.2f, 0.1f, -0.2f }; bool hasProjectionWeights = true; std::vector projectionWeights = { -1, 2, 1, -2, 1, 5, 3, 8, 7, 2, -4, 2, 5, -4, 3, -2, 3, 8, -7, 2 }; bool hasProjectionBias = true; std::vector projectionBias(outputSize, 0.f); bool hasInputLayerNormWeights = true; std::vector inputLayerNormWeights = { 0.1f, 0.2f, -0.3f, -0.1f, 0.5f }; bool hasForgetLayerNormWeights = true; std::vector forgetLayerNormWeights = { -0.1f, 0.2f, 0.3f, 0.5f, 0.2f }; bool hasCellLayerNormWeights = true; std::vector cellLayerNormWeights = { 0.5f, 0.2f, 0.3f, 0.4f, -0.5f }; bool hasOutputLayerNormWeights = true; std::vector outputLayerNormWeights = { 0.6f, -0.2f, -0.2f, 0.5f, 0.1f }; std::vector inputValues = { 1., 8., 3., 4., 5., 4., 3., 2., 1., 2., 3., 4., 5., 4., 3., 2., 1., 2. }; std::vector expectedOutputValues = { 0.0471276f, 0.0168155f, 0.0789885f, 0.16550f, 0.0643133f, -0.0400722f, 0.100593f, 0.197722f, 0.0465562f, -0.0600682f, 0.0622087f, 0.115053f, 0.056287f, -0.0566218f, 0.0856832f, 0.148484f, 0.0457859f, -0.0588112f, 0.0623636f, 0.114333f, 0.0509271f, -0.0754262f, 0.058600f, 0.0801288f }; tflite::ActivationFunctionType activationFunction = tflite::ActivationFunctionType_TANH; float clippingThresCell = 10.f; float clippingThresProj = 0.f; bool isTimeMajor = false; UnidirectionalSequenceLstmTestImpl(backends, ::tflite::TensorType_INT8, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, inputValues, expectedOutputValues, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, 0.1); } TEST_SUITE("UnidirectionalSequenceLstmTest_CpuRefTests") { TEST_CASE ("UnidirectionalSequenceLstmTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmTimeMajorTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmTimeMajorTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmWithCifgWithPeepholeNoProjectionTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmWithCifgWithPeepholeNoProjectionTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionWithLayerNormTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmNoCifgWithPeepholeWithProjectionWithLayerNormTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmInt8Test_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmInt8Test(backends); } TEST_CASE ("UnidirectionalSequenceLstmTimeInt8TimeMajorTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmInt8TimeMajorTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmInt8WithCifgWithPeepholeNoProjectionTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmInt8WithCifgWithPeepholeNoProjectionTest(backends); } TEST_CASE ("UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionWithLayerNormTest_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnidirectionalSequenceLstmInt8NoCifgWithPeepholeWithProjectionWithLayerNormTest(backends); } } //End of TEST_SUITE("UnidirectionalSequenceLstmTest_CpuRef") } // namespace armnnDelegatearmnn-23.08/delegate/test/UnidirectionalSequenceLstmTestHelper.hpp000066400000000000000000001234101446772241200254170ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include #include #include #include #include #include #include #include namespace { template std::vector CreateUnidirectionalSequenceLstmTfLiteModel(tflite::TensorType tensorType, int32_t batchSize, int32_t timeSize, int32_t inputSize, int32_t outputSize, int32_t numUnits, bool hasInputToInputWeights, const std::vector& inputToInputWeights, const std::vector& inputToForgetWeights, const std::vector& inputToCellWeights, const std::vector& inputToOutputWeights, bool hasRecurrentToInputWeights, const std::vector& recurrentToInputWeights, const std::vector& recurrentToForgetWeights, const std::vector& recurrentToCellWeights, const std::vector& recurrentToOutputWeights, bool hasCellToInputWeights, const std::vector& cellToInputWeights, bool hasCellToForgetWeights, const std::vector& cellToForgetWeights, bool hasCellToOutputWeights, const std::vector& cellToOutputWeights, bool hasInputGateBias, const std::vector& inputGateBias, const std::vector& forgetGateBias, const std::vector& cellBias, const std::vector& outputGateBias, bool hasProjectionWeights, const std::vector& projectionWeights, bool hasProjectionBias, const std::vector& projectionBias, bool hasInputLayerNormWeights, const std::vector& inputLayerNormWeights, bool hasForgetLayerNormWeights, const std::vector& forgetLayerNormWeights, bool hasCellLayerNormWeights, const std::vector& cellLayerNormWeights, bool hasOutputLayerNormWeights, const std::vector& outputLayerNormWeights, tflite::ActivationFunctionType activationFunction, float clippingThresCell, float clippingThresProj, bool isTimeMajor, float quantScale, int quantOffset = 0) { std::vector tensorInfo0{}; std::vector tensorInfoNumUnits{numUnits}; std::vector tensorInfoInputSize{numUnits, inputSize}; std::vector tensorInfoOutputSize{numUnits, outputSize}; std::vector inputShape; std::vector outputShape; if (isTimeMajor) { inputShape = {timeSize, batchSize, inputSize}; outputShape = {timeSize, batchSize, outputSize}; } else { inputShape = {batchSize, timeSize, inputSize}; outputShape = {batchSize, timeSize, outputSize}; } std::vector outputStateInDimensions{batchSize, outputSize}; std::vector cellStateInDimensions{batchSize, numUnits}; std::vector projectionWeightDimensions{outputSize, numUnits}; std::vector projectionBiasDimensions{outputSize}; std::vector operatorInputs; using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; std::vector> tensors; auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({1.0f}), flatBufferBuilder.CreateVector({0})); auto weightQuantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({quantScale}), flatBufferBuilder.CreateVector({quantOffset})); buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputShape.data(), inputShape.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("input_0"))); operatorInputs.push_back(tensors.size() - 1); if (hasInputToInputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputToInputWeights.data()), sizeof(T) * inputToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoInputSize.data(), tensorInfoInputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToInputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputToForgetWeights.data()), sizeof(T) * inputToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoInputSize.data(), tensorInfoInputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToForgetWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputToCellWeights.data()), sizeof(T) * inputToCellWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoInputSize.data(), tensorInfoInputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToCellWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputToOutputWeights.data()), sizeof(T) * inputToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoInputSize.data(), tensorInfoInputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("inputToOutputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); if (hasRecurrentToInputWeights) { buffers.push_back(CreateBuffer( flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(recurrentToInputWeights.data()), sizeof(T) * recurrentToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoOutputSize.data(), tensorInfoOutputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToInputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( recurrentToForgetWeights.data()), sizeof(T) * recurrentToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoOutputSize.data(), tensorInfoOutputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToForgetWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( recurrentToCellWeights.data()), sizeof(T) * recurrentToCellWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoOutputSize.data(), tensorInfoOutputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToCellWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( recurrentToOutputWeights.data()), sizeof(T) * recurrentToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoOutputSize.data(), tensorInfoOutputSize.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("recurrentToOutputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); if (hasCellToInputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( cellToInputWeights.data()), sizeof(T) * cellToInputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToInputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellToForgetWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( cellToForgetWeights.data()), sizeof(T) * cellToForgetWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToForgetWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellToOutputWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( cellToOutputWeights.data()), sizeof(T) * cellToOutputWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("cellToOutputWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasInputGateBias) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(inputGateBias.data()), sizeof(float) * inputGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("inputGateBias"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(forgetGateBias.data()), sizeof(float) * forgetGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("forgetGateBias"))); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(cellBias.data()), sizeof(float) * cellBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("cellBias"))); operatorInputs.push_back(tensors.size() - 1); buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast(outputGateBias.data()), sizeof(float) * outputGateBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("outputGateBias"))); operatorInputs.push_back(tensors.size() - 1); if (hasProjectionWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(projectionWeights.data()), sizeof(T) * projectionWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(projectionWeightDimensions.data(), projectionWeightDimensions.size()), tensorType, buffers.size() - 1, flatBufferBuilder.CreateString("projectionWeights"), weightQuantizationParameters)); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasProjectionBias) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(projectionBias.data()), sizeof(float) * projectionBias.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(projectionBiasDimensions.data(), projectionBiasDimensions.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("projectionBias"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputStateInDimensions.data(), outputStateInDimensions.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("outputStateInInfo"), quantizationParameters, true)); operatorInputs.push_back(tensors.size() - 1); buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(cellStateInDimensions.data(), cellStateInDimensions.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("cellStateInInfo"), quantizationParameters, true)); operatorInputs.push_back(tensors.size() - 1); if (hasInputLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(inputLayerNormWeights.data()), sizeof(float) * inputLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("inputLayerNormWeights"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasForgetLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(forgetLayerNormWeights.data()), sizeof(float) * forgetLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("forgetLayerNormWeights"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasCellLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector(reinterpret_cast( cellLayerNormWeights.data()), sizeof(float) * cellLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("cellLayerNormWeights"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } if (hasOutputLayerNormWeights) { buffers.push_back( CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector( reinterpret_cast(outputLayerNormWeights.data()), sizeof(float) * outputLayerNormWeights.size()))); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(tensorInfoNumUnits.data(), tensorInfoNumUnits.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("outputLayerNormWeights"))); operatorInputs.push_back(tensors.size() - 1); } else { operatorInputs.push_back(kTfLiteOptionalTensor); } buffers.push_back(CreateBuffer(flatBufferBuilder)); tensors.push_back(CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputShape.data(), outputShape.size()), ::tflite::TensorType_FLOAT32, buffers.size() - 1, flatBufferBuilder.CreateString("output"))); std::vector operatorOutputs; operatorOutputs.push_back(tensors.size() - 1); // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = BuiltinOptions_UnidirectionalSequenceLSTMOptions; flatbuffers::Offset operatorBuiltinOptions = CreateUnidirectionalSequenceLSTMOptions(flatBufferBuilder, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor).Union(); flatbuffers::Offset lstmOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), flatBufferBuilder.CreateVector(&lstmOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString( "ArmnnDelegate: UnidirectionalSequenceLSTM Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, tflite::BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void UnidirectionalSequenceLstmTestImpl(std::vector& backends, tflite::TensorType tensorType, int32_t batchSize, int32_t timeSize, int32_t inputSize, int32_t outputSize, int32_t numUnits, bool hasInputToInputWeights, const std::vector& inputToInputWeights, const std::vector& inputToForgetWeights, const std::vector& inputToCellWeights, const std::vector& inputToOutputWeights, bool hasRecurrentToInputWeights, const std::vector& recurrentToInputWeights, const std::vector& recurrentToForgetWeights, const std::vector& recurrentToCellWeights, const std::vector& recurrentToOutputWeights, bool hasCellToInputWeights, const std::vector& cellToInputWeights, bool hasCellToForgetWeights, const std::vector& cellToForgetWeights, bool hasCellToOutputWeights, const std::vector& cellToOutputWeights, bool hasInputGateBias, const std::vector& inputGateBias, const std::vector& forgetGateBias, const std::vector& cellBias, const std::vector& outputGateBias, bool hasProjectionWeights, const std::vector& projectionWeights, bool hasProjectionBias, const std::vector& projectionBias, bool hasInputLayerNormWeights, const std::vector& inputLayerNormWeights, bool hasForgetLayerNormWeights, const std::vector& forgetLayerNormWeights, bool hasCellLayerNormWeights, const std::vector& cellLayerNormWeights, bool hasOutputLayerNormWeights, const std::vector& outputLayerNormWeights, std::vector& inputValues, std::vector& expectedOutputValues, tflite::ActivationFunctionType activationFunction, float clippingThresCell, float clippingThresProj, bool isTimeMajor, float quantScale = 0.1f) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateUnidirectionalSequenceLstmTfLiteModel(tensorType, batchSize, timeSize, inputSize, outputSize, numUnits, hasInputToInputWeights, inputToInputWeights, inputToForgetWeights, inputToCellWeights, inputToOutputWeights, hasRecurrentToInputWeights, recurrentToInputWeights, recurrentToForgetWeights, recurrentToCellWeights, recurrentToOutputWeights, hasCellToInputWeights, cellToInputWeights, hasCellToForgetWeights, cellToForgetWeights, hasCellToOutputWeights, cellToOutputWeights, hasInputGateBias, inputGateBias, forgetGateBias, cellBias, outputGateBias, hasProjectionWeights, projectionWeights, hasProjectionBias, projectionBias, hasInputLayerNormWeights, inputLayerNormWeights, hasForgetLayerNormWeights, forgetLayerNormWeights, hasCellLayerNormWeights, cellLayerNormWeights, hasOutputLayerNormWeights, outputLayerNormWeights, activationFunction, clippingThresCell, clippingThresProj, isTimeMajor, quantScale); std::vector outputShape; if (isTimeMajor) { outputShape = {timeSize, batchSize, outputSize}; } else { outputShape = {batchSize, timeSize, outputSize}; } // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(0); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(0); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(0); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(0); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, outputShape); if (tensorType == ::tflite::TensorType_INT8) { // Allow 2% tolerance for Quantized weights armnnDelegate::CompareData(expectedOutputValues.data(), armnnOutputValues.data(), expectedOutputValues.size(), 2); armnnDelegate::CompareData(expectedOutputValues.data(), tfLiteOutputValues.data(), expectedOutputValues.size(), 2); armnnDelegate::CompareData(tfLiteOutputValues.data(), armnnOutputValues.data(), expectedOutputValues.size(), 2); } else { armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues); } tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/delegate/test/UnpackTest.cpp000066400000000000000000000131131446772241200201670ustar00rootroot00000000000000// // Copyright © 2021,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "UnpackTestHelper.hpp" #include #include #include #include namespace armnnDelegate { template void UnpackAxis0Num4Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 4, 1, 6 }; std::vector expectedOutputShape { 1, 6 }; std::vector inputValues { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 }; std::vector expectedOutputValues0 { 1, 2, 3, 4, 5, 6 }; std::vector expectedOutputValues1 { 7, 8, 9, 10, 11, 12 }; std::vector expectedOutputValues2 { 13, 14, 15, 16, 17, 18 }; std::vector expectedOutputValues3 { 19, 20, 21, 22, 23, 24 }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1, expectedOutputValues2, expectedOutputValues3 }; UnpackTest(tflite::BuiltinOperator_UNPACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 0); } template void UnpackAxis2Num6Test(tflite::TensorType tensorType, std::vector& backends) { std::vector inputShape { 4, 1, 6 }; std::vector expectedOutputShape { 4, 1 }; std::vector inputValues { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 }; std::vector expectedOutputValues0 { 1, 7, 13, 19 }; std::vector expectedOutputValues1 { 2, 8, 14, 20 }; std::vector expectedOutputValues2 { 3, 9, 15, 21 }; std::vector expectedOutputValues3 { 4, 10, 16, 22 }; std::vector expectedOutputValues4 { 5, 11, 17, 23 }; std::vector expectedOutputValues5 { 6, 12, 18, 24 }; std::vector> expectedOutputValues{ expectedOutputValues0, expectedOutputValues1, expectedOutputValues2, expectedOutputValues3, expectedOutputValues4, expectedOutputValues5 }; UnpackTest(tflite::BuiltinOperator_UNPACK, tensorType, backends, inputShape, expectedOutputShape, inputValues, expectedOutputValues, 2); } TEST_SUITE("Unpack_CpuRefTests") { // Fp32 TEST_CASE ("Unpack_Fp32_Axis0_Num4_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Unpack_Fp32_Axis2_Num6_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Unpack_Uint8_Axis0_Num4_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Unpack_Uint8_Axis2_Num6_CpuRef_Test") { std::vector backends = {armnn::Compute::CpuRef}; UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); } } // End of Unpack_CpuRefTests TEST_SUITE("Unpack_CpuAccTests") { // Fp32 TEST_CASE ("Unpack_Fp32_Axis0_Num4_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Unpack_Fp32_Axis2_Num6_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Unpack_Uint8_Axis0_Num4_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Unpack_Uint8_Axis2_Num6_CpuAcc_Test") { std::vector backends = {armnn::Compute::CpuAcc}; UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); } } // End of Unpack_CpuAccTests TEST_SUITE("Unpack_GpuAccTests") { // Fp32 TEST_CASE ("Unpack_Fp32_Axis0_Num4_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); } TEST_CASE ("Unpack_Fp32_Axis2_Num6_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); } // Uint8 TEST_CASE ("Unpack_Uint8_Axis0_Num4_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); } TEST_CASE ("Unpack_Uint8_Axis2_Num6_GpuAcc_Test") { std::vector backends = {armnn::Compute::GpuAcc}; UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); } } // End of Unpack_GpuAccTests // End of Unpack Test Suite } // namespace armnnDelegatearmnn-23.08/delegate/test/UnpackTestHelper.hpp000066400000000000000000000172341446772241200213440ustar00rootroot00000000000000// // Copyright © 2021, 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "TestUtils.hpp" #include #include #include #include #include #include #include namespace { std::vector CreateUnpackTfLiteModel(tflite::BuiltinOperator unpackOperatorCode, tflite::TensorType tensorType, std::vector& inputTensorShape, const std::vector & outputTensorShape, const int32_t outputTensorNum, unsigned int axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace tflite; flatbuffers::FlatBufferBuilder flatBufferBuilder; std::vector> buffers; buffers.push_back(CreateBuffer(flatBufferBuilder)); buffers.push_back(CreateBuffer(flatBufferBuilder)); auto quantizationParameters = CreateQuantizationParameters(flatBufferBuilder, 0, 0, flatBufferBuilder.CreateVector({ quantScale }), flatBufferBuilder.CreateVector({ quantOffset })); const std::vector operatorInputs{ 0 }; std::vector operatorOutputs{}; const std::vector subgraphInputs{ 0 }; std::vector subgraphOutputs{}; std::vector> tensors(outputTensorNum + 1); // Create input tensor tensors[0] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(inputTensorShape.data(), inputTensorShape.size()), tensorType, 1, flatBufferBuilder.CreateString("input"), quantizationParameters); for (int i = 0; i < outputTensorNum; ++i) { tensors[i + 1] = CreateTensor(flatBufferBuilder, flatBufferBuilder.CreateVector(outputTensorShape.data(), outputTensorShape.size()), tensorType, (i + 2), flatBufferBuilder.CreateString("output" + std::to_string(i)), quantizationParameters); buffers.push_back(CreateBuffer(flatBufferBuilder)); operatorOutputs.push_back(i + 1); subgraphOutputs.push_back(i + 1); } // create operator tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_UnpackOptions; flatbuffers::Offset operatorBuiltinOptions = CreateUnpackOptions(flatBufferBuilder, outputTensorNum, axis).Union(); flatbuffers::Offset unpackOperator = CreateOperator(flatBufferBuilder, 0, flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), operatorBuiltinOptionsType, operatorBuiltinOptions); flatbuffers::Offset subgraph = CreateSubGraph(flatBufferBuilder, flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), flatBufferBuilder.CreateVector(&unpackOperator, 1)); flatbuffers::Offset modelDescription = flatBufferBuilder.CreateString("ArmnnDelegate: Unpack Operator Model"); flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, unpackOperatorCode); flatbuffers::Offset flatbufferModel = CreateModel(flatBufferBuilder, TFLITE_SCHEMA_VERSION, flatBufferBuilder.CreateVector(&operatorCode, 1), flatBufferBuilder.CreateVector(&subgraph, 1), modelDescription, flatBufferBuilder.CreateVector(buffers)); flatBufferBuilder.Finish(flatbufferModel, armnnDelegate::FILE_IDENTIFIER); return std::vector(flatBufferBuilder.GetBufferPointer(), flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); } template void UnpackTest(tflite::BuiltinOperator unpackOperatorCode, tflite::TensorType tensorType, std::vector& backends, std::vector& inputShape, std::vector& expectedOutputShape, std::vector& inputValues, std::vector>& expectedOutputValues, unsigned int axis = 0, float quantScale = 1.0f, int quantOffset = 0) { using namespace delegateTestInterpreter; std::vector modelBuffer = CreateUnpackTfLiteModel(unpackOperatorCode, tensorType, inputShape, expectedOutputShape, expectedOutputValues.size(), axis, quantScale, quantOffset); // Setup interpreter with just TFLite Runtime. auto tfLiteInterpreter = DelegateTestInterpreter(modelBuffer); CHECK(tfLiteInterpreter.AllocateTensors() == kTfLiteOk); CHECK(tfLiteInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(tfLiteInterpreter.Invoke() == kTfLiteOk); // Setup interpreter with Arm NN Delegate applied. auto armnnInterpreter = DelegateTestInterpreter(modelBuffer, backends); CHECK(armnnInterpreter.AllocateTensors() == kTfLiteOk); CHECK(armnnInterpreter.FillInputTensor(inputValues, 0) == kTfLiteOk); CHECK(armnnInterpreter.Invoke() == kTfLiteOk); // Compare output data for (unsigned int i = 0; i < expectedOutputValues.size(); ++i) { std::vector tfLiteOutputValues = tfLiteInterpreter.GetOutputResult(i); std::vector tfLiteOutputShape = tfLiteInterpreter.GetOutputShape(i); std::vector armnnOutputValues = armnnInterpreter.GetOutputResult(i); std::vector armnnOutputShape = armnnInterpreter.GetOutputShape(i); armnnDelegate::CompareOutputData(tfLiteOutputValues, armnnOutputValues, expectedOutputValues[i]); armnnDelegate::CompareOutputShape(tfLiteOutputShape, armnnOutputShape, expectedOutputShape); } tfLiteInterpreter.Cleanup(); armnnInterpreter.Cleanup(); } } // anonymous namespacearmnn-23.08/docker/000077500000000000000000000000001446772241200141215ustar00rootroot00000000000000armnn-23.08/docker/README.md000066400000000000000000000005631446772241200154040ustar00rootroot00000000000000# ARMNN Docker Files A productized Arm NN Docker solution has been released as part of our new Arm NN Build Tool which can be found at this link on our GitHub website: https://github.com/ARM-software/armnn/tree/HEAD/build-tool The above link automatically points to the latest release version of the Arm NN Build Tool and will be live when Arm NN 22.08 is released. armnn-23.08/docker/README.md.license000066400000000000000000000001531446772241200170200ustar00rootroot00000000000000# # Copyright © 2021-2022 Arm Ltd and Contributors. All rights reserved. # SPDX-License-Identifier: MIT # armnn-23.08/docs/000077500000000000000000000000001446772241200136025ustar00rootroot00000000000000armnn-23.08/docs/01_00_quick_start.dox000066400000000000000000000011761446772241200174530ustar00rootroot00000000000000/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page quickstart Quick Start Guide On this page you can find guides which allow you to get setup and ready to run models with Arm NN quickly. These guides rely on using the apt packages or prebuilt binaries from our release notes. We only have added a quick start guide that uses TfLite-Delegate. More guides will be added in the future. - @subpage md_delegate_DelegateQuickStartGuide **/ } namespace armnn { /** @page md_delegate_DelegateQuickStartGuide TfLite Delegate Quick Start Guide **/ } armnn-23.08/docs/02_operator_list.dox000066400000000000000000001725451446772241200175230ustar00rootroot00000000000000/// Copyright (c) 2021, 2023 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page operator_list Arm NN Operators @section S5_1_operator_list Arm NN Operators Arm NN supports operators that are listed in below table. Arm NN supports a wide list of data-types. The main data-types that the Machine Learning functions support are the following:
  • BFLOAT16: 16-bit non-standard brain floating point
  • QASYMMU8: 8-bit unsigned asymmetric quantized
  • QASYMMS8: 8-bit signed asymmetric quantized
  • QUANTIZEDSYMM8PERAXIS: 8-bit signed symmetric quantized
  • QSYMMS8: 8-bit signed symmetric quantized
  • QSYMMS16: 16-bit signed symmetric quantized
  • FLOAT32: 32-bit single precision floating point
  • FLOAT16: 16-bit half precision floating point
  • SIGNED32: 32-bit signed integer
  • BOOLEAN: 8-bit unsigned char
  • All: Agnostic to any specific data type
Arm NN supports the following data layouts (fast changing dimension from right to left):
  • NHWC: Layout where channels are in the fastest changing dimension
  • NCHW: Layout where width is in the fastest changing dimension
  • All: Agnostic to any specific data layout
where N = batches, C = channels, H = height, W = width
Operator Description Equivalent Android NNAPI Operator Backends Data Layouts Data Types
AbsLayer Layer to perform absolute operation.
  • ANEURALNETWORKS_ABS
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
FLOAT16
FLOAT32
SIGNED32
GpuAcc
  • All
FLOAT16
FLOAT32
ActivationLayer Layer to simulate an activation layer with the specified activation function.
  • ANEURALNETWORKS_ABS
  • ANEURALNETWORKS_ELU
  • ANEURALNETWORKS_HARD_SWISH
  • ANEURALNETWORKS_LOGISTIC
  • ANEURALNETWORKS_PRELU
  • ANEURALNETWORKS_RELU
  • ANEURALNETWORKS_RELU1
  • ANEURALNETWORKS_RELU6
  • ANEURALNETWORKS_SQRT
  • ANEURALNETWORKS_TANH
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
FLOAT16
FLOAT32
AdditionLayer Layer to add 2 tensors.
  • ANEURALNETWORKS_ADD
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
ArgMinMaxLayer Layer to calculate the index of the minimum or maximum values in a tensor based on an axis.
  • ANEURALNETWORKS_ARGMAX
  • ANEURALNETWORKS_ARGMIN
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
SIGNED64
CpuAcc
  • All
QASYMMU8
QASYMMS8
SIGNED32
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
SIGNED32
FLOAT16
FLOAT32
BatchMatMulLayer Layer to perform batch matrix multiplication.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
FLOAT32
QASYMMS8
GpuAcc
  • All
FLOAT32
QASYMMS8
BatchNormalizationLayer Layer to perform batch normalization.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
FLOAT32
FLOAT16
GpuAcc
  • NHWC
  • NCHW
FLOAT32
FLOAT16
BatchToSpaceNdLayer Layer to perform a batch to space transformation.
  • ANEURALNETWORKS_BATCH_TO_SPACE_ND
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
CastLayer Layer to cast a tensor to a type.
  • ANEURALNETWORKS_CAST
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QSYMMS8
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMS8
QASYMMU8
FLOAT16
SIGNED32
FLOAT32
GpuAcc
  • All
QASYMMS8
QASYMMU8
SIGNED32
FLOAT16
FLOAT32
ChannelShuffleLayer Layer to reorganize the channels of a tensor.
  • ANEURALNETWORKS_CHANNEL_SHUFFLE
CpuRef
  • All
FLOAT16
FLOAT32
QSYMMS8
QASYMMS8
QASYMMU8
CpuAcc
  • All
QASYMMS8
QASYMMU8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMS8
QASYMMU8
FLOAT16
FLOAT32
ComparisonLayer Layer to compare 2 tensors.
  • ANEURALNETWORKS_EQUAL
  • ANEURALNETWORKS_GREATER
  • ANEURALNETWORKS_GREATER_EQUAL
  • ANEURALNETWORKS_LESS
  • ANEURALNETWORKS_LESS_EQUAL
  • ANEURALNETWORKS_NOT_EQUAL
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
BOOLEAN
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
All
GpuAcc
  • All
All
ConcatLayer Layer to concatenate tensors along a given axis.
  • ANEURALNETWORKS_CONCATENATION
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
ConstantLayer Layer to provide a constant tensor.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
SIGNED32
CpuAcc
  • All
All
GpuAcc
  • All
All
ConvertFp16ToFp32Layer Layer to convert Float16 tensor to Float32 tensor.
  • N/A
CpuRef
  • All
FLOAT16
FLOAT32
CpuAcc
  • All
FLOAT16
FLOAT32
GpuAcc
  • All
FLOAT16
FLOAT32
ConvertFp32ToFp16Layer Layer to convert Float32 tensor to Float16 tensor.
  • N/A
CpuRef
  • All
FLOAT16
FLOAT32
CpuAcc
  • All
FLOAT16
FLOAT32
GpuAcc
  • All
FLOAT16
FLOAT32
Convolution2dLayer Layer to compute a convolution operation.
  • ANEURALNETWORKS_CONV_2D
  • ANEURALNETWORKS_GROUPED_CONV_2D
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
GpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
Convolution3dLayer Layer to compute a 3D convolution operation.
  • N/A
CpuRef
  • NDHWC
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • N/A
  • N/A
GpuAcc
  • N/A
  • N/A
DebugLayer Layer to print out inter layer tensor information.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
SIGNED32
DepthToSpaceLayer Layer to perform Depth to Space transformation.
  • ANEURALNETWORKS_DEPTH_TO_SPACE
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
DepthwiseConvolution2dLayer Layer to compute a deconvolution or transpose convolution.
  • ANEURALNETWORKS_DEPTHWISE_CONV_2D
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
SIGNED32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
GpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
SIGNED32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
DequantizeLayer Layer to dequantize the values in a tensor.
  • ANEURALNETWORKS_DEQUANTIZE
CpuRef
  • All
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • All
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
QSYMMS8
QSYMMS16
GpuAcc
  • All
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
QSYMMS8
QSYMMS16
DetectionPostProcessLayer Layer to generate the detection output based on center size encoded boxes, class prediction and anchors by doing non maximum suppression (NMS).
  • ANEURALNETWORKS_DETECTION_POSTPROCESSING
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT32
DivisionLayer Layer to divide 2 tensors.
  • ANEURALNETWORKS_DIV
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
FLOAT16
FLOAT32
GpuAcc
  • All
FLOAT16
FLOAT32
ElementwiseBaseLayer Layer to perform Add - Div - Max - Min - Mul operations.
  • ANEURALNETWORKS_ADD
  • ANEURALNETWORKS_DIV
  • ANEURALNETWORKS_MAXIMUM
  • ANEURALNETWORKS_MINIMUM
  • ANEURALNETWORKS_MUL
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
ElementwiseBinaryLayer Layer to perform Power and Square Difference operations.
  • ANEURALNETWORKS_POW
CpuRef
  • All
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
FLOAT16
FLOAT32
GpuAcc
  • All
FLOAT16
FLOAT32
ElementwiseUnaryLayer Layer to perform Rsqrt - Exp - Neg - Log - Abs - Sin - Sqrt - Ceil operations.
  • ANEURALNETWORKS_ABS
  • ANEURALNETWORKS_EXP
  • ANEURALNETWORKS_LOG
  • ANEURALNETWORKS_NEG
  • ANEURALNETWORKS_RSQRT
  • ANEURALNETWORKS_SIN
  • ANEURALNETWORKS_SQRT
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
FLOAT16
FLOAT32
SIGNED32
GpuAcc
  • All
FLOAT16
FLOAT32
FakeQuantizationLayer Layer to quantize float values and dequantize afterwards. The current implementation does not dequantize the values.
  • N/A
CpuRef
  • All
FLOAT32
FillLayer Layer to set the values of a tensor with a given value.
  • ANEURALNETWORKS_FILL
CpuRef
  • All
FLOAT16
FLOAT32
SIGNED32
CpuAcc
  • All
All
GpuAcc
  • All
All
FloorLayer Layer to round the value to the lowest whole number.
  • ANEURALNETWORKS_FLOOR
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
CpuAcc
  • All
FLOAT32
FLOAT16
GpuAcc
  • All
FLOAT32
FLOAT16
FullyConnectedLayer Layer to perform a fully connected / dense operation.
  • ANEURALNETWORKS_FULLY_CONNECTED
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
GpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
GatherLayer Layer to perform the gather operation along the chosen axis.
  • ANEURALNETWORKS_GATHER
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
All
GpuAcc
  • All
All
GatherNdLayer Layer to perform the gatherNd operation.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
GpuAcc
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
InputLayer Special layer used to provide input data to the computational network.
  • N/A
All
  • All
All
InstanceNormalizationLayer Layer to perform an instance normalization on a given axis.
  • ANEURALNETWORKS_INSTANCE_NORMALIZATION
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
CpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
GpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
L2NormalizationLayer Layer to perform an L2 normalization on a given axis.
  • ANEURALNETWORKS_L2_NORMALIZATION
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
GpuAcc
  • NHWC
  • NCHW
FLOAT16
FLOAT32
LogSoftmaxLayer Layer to perform the log softmax activations given logits.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
LogicalBinaryLayer Layer to perform Logical AND - Logical NOT - Logical OR operations.
  • ANEURALNETWORKS_LOGICAL_AND
  • ANEURALNETWORKS_LOGICAL_NOT
  • ANEURALNETWORKS_LOGICAL_OR
CpuRef
  • All
BOOLEAN
CpuAcc
  • All
BOOLEAN
GpuAcc
  • All
BOOLEAN
LstmLayer Layer to perform a single time step in a Long Short-Term Memory (LSTM) operation.
  • ANEURALNETWORKS_LSTM
CpuRef
  • All
BFLOAT16
FLOAT16
QSYMMS16
CpuAcc
  • All
FLOAT16
FLOAT32
GpuAcc
  • All
FLOAT16
FLOAT32
MapLayer Layer to perform map operation on tensor.
  • N/A
CpuRef
  • All
All
CpuAcc
  • All
All
GpuAcc
  • All
All
MaximumLayer Layer to perform an elementwise maximum of two tensors.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
SIGNED32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
FLOAT16
FLOAT32
SIGNED32
MeanLayer Layer to perform reduce mean operation.
  • ANEURALNETWORKS_MEAN
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
MemCopyLayer Layer to perform memory copy operation.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
BOOLEAN
CpuAcc
  • All
All
GpuAcc
  • All
All
MemImportLayer Layer to perform memory import operation.
  • N/A
CpuRef
  • All
All
CpuAcc
  • All
All
GpuAcc
  • All
All
MergeLayer Layer to concatenate tensors along a given axis.
  • ANEURALNETWORKS_CONCATENATION
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
MinimumLayer Layer to perform an elementwise minimum of two tensors.
  • ANEURALNETWORKS_MINIMUM
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
FLOAT16
FLOAT32
SIGNED32
MultiplicationLayer Layer to perform an elementwise multiplication of two tensors.
  • ANEURALNETWORKS_MUL
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
SIGNED32
NormalizationLayer Layer to compute normalization operation.
  • ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
FLOAT32
FLOAT16
GpuAcc
  • NHWC
  • NCHW
FLOAT32
FLOAT16
OutputLayer A special layer providing access to a user supplied buffer into which the output of a network can be written.
  • N/A
All
  • All
All
PadLayer Layer to pad a tensor.
  • ANEURALNETWORKS_PAD
  • ANEURALNETWORKS_PAD_V2
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
PermuteLayer Layer to transpose an ND tensor.
  • ANEURALNETWORKS_TRANSPOSE
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
Pooling2dLayer Layer to perform 2D pooling with the specified pooling operation.
  • ANEURALNETWORKS_AVERAGE_POOL_2D
  • ANEURALNETWORKS_L2_POOL_2D
  • ANEURALNETWORKS_MAX_POOL_2D
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • NHWC
  • NCHW
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
Pooling3dLayer Layer to perform 3D pooling with the specified pooling operation.
  • ANEURALNETWORKS_AVERAGE_POOL_3D
  • ANEURALNETWORKS_L2_POOL_3D
  • ANEURALNETWORKS_MAX_POOL_3D
CpuRef
  • NDHWC
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NA
GpuAcc
  • NDHWC
PreCompiledLayer Opaque layer provided by a backend which provides an executable representation of a subgraph from the original network.
  • N/A
N/A N/A N/A
PreluLayer Layer to compute the activation layer with the PRELU activation function.
  • ANEURALNETWORKS_PRELU
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
QLstmLayer Layer to perform quantized LSTM (Long Short-Term Memory) operation.
  • ANEURALNETWORKS_QUANTIZED_LSTM
  • ANEURALNETWORKS_QUANTIZED_16BIT_LSTM
CpuRef
  • All
All
CpuAcc
  • All
QASYMMS8
QASYMMU8
SIGNED32
QSYMMS16
GpuAcc
  • All
QASYMMS8
QASYMMU8
SIGNED32
QSYMMS16
QuantizeLayer Layer to perform quantization operation.
  • ANEURALNETWORKS_QUANTIZE
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
QASYMM16
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QASYMM16
FLOAT16
FLOAT32
QuantizedLstmLayer Layer to perform quantized LSTM (Long Short-Term Memory) operation.
  • ANEURALNETWORKS_QUANTIZED_LSTM
  • ANEURALNETWORKS_QUANTIZED_16BIT_LSTM
CpuRef
  • All
All
CpuAcc
  • All
SIGNED32
QASYMMU8
QSYMMS16
GpuAcc
  • All
SIGNED32
QASYMMU8
QSYMMS16
RankLayer Layer to perform a rank operation.
  • ANEURALNETWORKS_RANK
CpuRef
  • All
All
CpuAcc
  • All
All
GpuAcc
  • All
All
ReduceLayer Layer to perform reduce with the following operations - ARG_IDX_MAX: Index of the max value - ARG_IDX_MIN: Index of the min value - MEAN_SUM: Mean of sum - PROD: Product - SUM_SQUARE: Sum of squares - SUM: Sum - MIN: Min - MAX: Max
  • ANEURALNETWORKS_REDUCE_MAX
  • ANEURALNETWORKS_REDUCE_MIN
  • ANEURALNETWORKS_REDUCE_SUM
  • ANEURALNETWORKS_REDUCE_PROD
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
SIGNED32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
SIGNED32
ReshapeLayer Layer to reshape a tensor.
  • ANEURALNETWORKS_RESHAPE
  • ANEURALNETWORKS_SQUEEZE
  • ANEURALNETWORKS_EXPAND_DIMS
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
BOOLEAN
CpuAcc
  • All
All
GpuAcc
  • All
All
ResizeLayer Layer to perform resize of a tensor using one of the interpolation methods: - Bilinear - Nearest Neighbor.
  • ANEURALNETWORKS_RESIZE_BILINEAR
  • ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • NHWC
  • NCHW
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
ReverseV2Layer Layer to perform reverse of a tensor.
  • NA
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
RsqrtLayer Layer to perform Rsqrt operation.
  • ANEURALNETWORKS_RSQRT
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
FLOAT16
FLOAT32
SIGNED32
GpuAcc
  • All
FLOAT16
FLOAT32
ShapeLayer Layer to return the shape of the input tensor.
  • N/A
CpuRef
  • All
All
CpuAcc
  • All
All
GpuAcc
  • All
All
SliceLayer Layer to perform tensor slicing.
  • ANEURALNETWORKS_SLICE
CpuRef
  • All
BFLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
SoftmaxLayer Layer to perform softmax, log-softmax operation over the specified axis.
  • ANEURALNETWORKS_LOG_SOFTMAX
  • ANEURALNETWORKS_SOFTMAX
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
FLOAT16
FLOAT32
SpaceToBatchNdLayer Layer to divide spatial dimensions of the tensor into a grid of blocks and interleaves these blocks with the batch dimension.
  • ANEURALNETWORKS_SPACE_TO_BATCH_ND
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
SpaceToDepthLayer Layer to rearrange blocks of spatial data into depth.
  • ANEURALNETWORKS_SPACE_TO_DEPTH
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
SplitterLayer Layer to split a tensor along a given axis.
  • ANEURALNETWORKS_SPLIT
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
StackLayer Layer to stack tensors along an axis.
  • N/A
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
StandInLayer A layer to represent "unknown" or "unsupported" operations in the input graph. It has a configurable number of input and output slots and an optional name.
  • N/A
N/A N/A N/A
StridedSliceLayer Layer to extract a strided slice of a tensor.
  • ANEURALNETWORKS_STRIDED_SLICE
CpuRef
  • All
BFLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
SubtractionLayer Layer to perform an elementwise subtract of 2 tensors.
  • ANEURALNETWORKS_SUB
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
SIGNED32
CpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
GpuAcc
  • All
QASYMMU8
QASYMMS8
QSYMMS16
SIGNED32
FLOAT16
FLOAT32
TileLayer Layer to construct a tensor by repeating in tiles a given tensor.
  • ANEURALNETWORKS_TILE
CpuRef
  • All
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
SIGNED32
CpuAcc
  • All
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QASYMM8
QSYMMS16
SIGNED32
GpuAcc
  • All
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
SIGNED32
TransposeConvolution2dLayer Layer to perform 2D transpose convolution (deconvolution) operation.
  • ANEURALNETWORKS_TRANSPOSE_CONV_2D
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS8
QSYMMS16
CpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
GpuAcc
  • NHWC
  • NCHW
SIGNED32
FLOAT16
FLOAT32
QASYMMU8
QASYMMS8
QUANTIZEDSYMM8PERAXIS
TransposeLayer Layer to transpose a tensor.
  • ANEURALNETWORKS_TRANSPOSE
CpuRef
  • All
BFLOAT16
FLOAT16
FLOAT32
QASYMMS8
QASYMMU8
QSYMMS16
CpuAcc
  • All
All
GpuAcc
  • All
All
UnidirectionalSquenceLstmLayer Layer to perform unidirectional sequence LSTM operation.
  • ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_LSTM
CpuRef
  • All
Input Types
FLOAT32
Weight Types
FLOAT32
QASYMMS8
CpuAcc
  • All
Input Types
FLOAT32
Weight Types
FLOAT32
GpuAcc
  • All
Input Types
FLOAT32
Weight Types
FLOAT32
UnmapLayer Layer to perform unmap operation on tensor.
  • N/A
CpuRef
  • All
All
CpuAcc
  • NHWC
  • NCHW
All
GpuAcc
  • NHWC
  • NCHW
All
*/ } // namespace armnn-23.08/docs/03_build_guides.dox000066400000000000000000000017211446772241200172600ustar00rootroot00000000000000/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page buildguides Build Guides This page links all guides to build and/or install Arm NN tools hosted in our repository. You can find additional tutorials on https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides Arm NN is written using portable C++14 and the build system uses [CMake](https://cmake.org/), therefore it is possible to build for a wide variety of target platforms, from a wide variety of host environments. Arm NN is managed by a single CMake project. That allows you to build multiple tools at once by combining the CMake options from different build guides. ## Installation via APT Repository - @subpage md_InstallationViaAptRepository ## TfLite Delegate build guide - @subpage md_delegate_BuildGuideNative ## Android NDK and Arm NN - @subpage md_BuildGuideAndroidNDK **/ }armnn-23.08/docs/04_contributor.dox000066400000000000000000000020141446772241200171700ustar00rootroot00000000000000/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page contribguides Contribution Guides This is a collection of guides that should help you contribute code to Arm NN. Before you get started, please take a look into our /ref md_Contributor_Guide section. - @subpage md_src_backends_README \n This guide explains how to add your own backend to Arm NN. This might be useful if you would like to accelerate neural networks on hardware that Arm NN currently doesn't support. - @subpage md_src_dynamic_README \n Arm NN allows you to load a backend dynamically on runtime. To find out how that can be done take a look at this guide. **/ } /// Create pages for each tool so they appear nicely in the doxygen tree-view. Subpages are not listed there. /// Also we can overwrite the page name this way. namespace armnn { /** @page md_src_backends_README Backend Developer Guide @page md_src_dynamic_README Dynamically loadable Backend **/ } armnn-23.08/docs/05_00_software_components.dox000066400000000000000000000016351446772241200212250ustar00rootroot00000000000000/// Copyright (c) 2022 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page swtools Software Components On this page you can find all software components contained in the Arm NN repository. You will find links to how-to guides and other helpful information in each section. - @subpage md_src_armnnConverter_README - @subpage deserializer - @subpage supportlibrary - @subpage parsers - @subpage md_python_pyarmnn_README - @subpage runtimeoptions - @subpage serializer - @subpage delegate **/ } /// Create pages for each tool so they appear nicely in the doxygen tree-view. Subpages are not listed there. /// /// Note: The parser, serializer and deserializer pages are created in 01_parsers.dox or 02_deserializer_serializer.dox namespace armnn { /** @page md_python_pyarmnn_README PyArmNN @page md_src_armnnConverter_README Converter **/ } armnn-23.08/docs/05_01_parsers.dox000066400000000000000000000165751446772241200166170ustar00rootroot00000000000000/// Copyright (c) 2022-2023 Arm Ltd and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page parsers Parsers Execute models from different machine learning platforms efficiently with our parsers. Simply choose a parser according to the model you want to run e.g. If you've got a model in onnx format (.onnx) use our onnx-parser. If you would like to run a Tensorflow Lite (TfLite) model you probably also want to take a look at our @ref delegate. All parsers are written in C++ but it is also possible to use them in python. For more information on our python bindings take a look into the @ref md_python_pyarmnn_README section.

@section S5_onnx_parser Arm NN Onnx Parser `armnnOnnxParser` is a library for loading neural networks defined in ONNX protobuf files into the Arm NN runtime. ## ONNX operators that the Arm NN SDK supports This reference guide provides a list of ONNX operators the Arm NN SDK currently supports. The Arm NN SDK ONNX parser currently only supports fp32 operators. ### Fully supported - Add - See the ONNX [Add documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Add) for more information - AveragePool - See the ONNX [AveragePool documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#AveragePool) for more information. - Concat - See the ONNX [Concat documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Concat) for more information. - Constant - See the ONNX [Constant documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Constant) for more information. - Clip - See the ONNX [Clip documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Clip) for more information. - Flatten - See the ONNX [Flatten documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Flatten) for more information. - Gather - See the ONNX [Gather documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Gather) for more information. - GlobalAveragePool - See the ONNX [GlobalAveragePool documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#GlobalAveragePool) for more information. - LeakyRelu - See the ONNX [LeakyRelu documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#LeakyRelu) for more information. - MaxPool - See the ONNX [max_pool documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#MaxPool) for more information. - Relu - See the ONNX [Relu documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Relu) for more information. - Reshape - See the ONNX [Reshape documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Reshape) for more information. - Shape - See the ONNX [Shape documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Shape) for more information. - Sigmoid - See the ONNX [Sigmoid documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Sigmoid) for more information. - Tanh - See the ONNX [Tanh documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Tanh) for more information. - Unsqueeze - See the ONNX [Unsqueeze documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Unsqueeze) for more information. ### Partially supported - Conv - The parser only supports 2D convolutions with a group = 1 or group = #Nb_of_channel (depthwise convolution) - BatchNormalization - The parser does not support training mode. See the ONNX [BatchNormalization documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#BatchNormalization) for more information. - Gemm - The parser only supports constant bias or non-constant bias where bias dimension = 1. See the ONNX [Gemm documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#Gemm) for more information. - MatMul - The parser only supports constant weights in a fully connected layer. See the ONNX [MatMul documentation](https://github.com/onnx/onnx/blob/master/docs/Operators.md#MatMul) for more information. ## Tested networks Arm tested these operators with the following ONNX fp32 neural networks: - Mobilenet_v2. See the ONNX [MobileNet documentation](https://github.com/onnx/models/tree/master/vision/classification/mobilenet) for more information. - Simple MNIST. This is no longer directly documented by ONNX. The model and test data may be downloaded [from the ONNX model zoo](https://onnxzoo.blob.core.windows.net/models/opset_8/mnist/mnist.tar.gz). More machine learning operators will be supported in future releases.



@section S6_tf_lite_parser Arm NN Tf Lite Parser `armnnTfLiteParser` is a library for loading neural networks defined by TensorFlow Lite FlatBuffers files into the Arm NN runtime. ## TensorFlow Lite operators that the Arm NN SDK supports This reference guide provides a list of TensorFlow Lite operators the Arm NN SDK currently supports. ### Fully supported The Arm NN SDK TensorFlow Lite parser currently supports the following operators: - ABS - ADD - ARG_MAX - ARG_MIN - AVERAGE_POOL_2D, Supported Fused Activation: RELU , RELU6 , TANH, NONE - BATCH_TO_SPACE - CAST - CEIL - CONCATENATION, Supported Fused Activation: RELU , RELU6 , TANH, NONE - CONV_2D, Supported Fused Activation: RELU , RELU6 , TANH, NONE - CONV_3D, Supported Fused Activation: RELU , RELU6 , TANH, NONE - DEPTH_TO_SPACE - DEPTHWISE_CONV_2D, Supported Fused Activation: RELU , RELU6 , TANH, NONE - DEQUANTIZE - DIV - ELU - EQUAL - EXP - EXPAND_DIMS - FLOOR_DIV - FULLY_CONNECTED, Supported Fused Activation: RELU , RELU6 , TANH, NONE - GATHER - GATHER_ND - GREATER - GREATER_EQUAL - HARD_SWISH - LEAKY_RELU - LESS - LESS_EQUAL - LOG - LOGICAL_NOT - LOGISTIC - LOG_SOFTMAX - L2_NORMALIZATION - MAX_POOL_2D, Supported Fused Activation: RELU , RELU6 , TANH, NONE - MAXIMUM - MEAN - MINIMUM - MIRROR_PAD - MUL - NEG - NOT_EQUAL - PACK - PAD - PADV2 - POW - PRELU - QUANTIZE - RELU - RELU6 - REDUCE_MAX - REDUCE_MIN - REDUCE_PROD - RESHAPE - RESIZE_BILINEAR - RESIZE_NEAREST_NEIGHBOR - REVERSE_V2 - RSQRT - SHAPE - SIN - SLICE - SOFTMAX - SPACE_TO_BATCH - SPACE_TO_DEPTH - SPLIT - SPLIT_V - SQUEEZE - SQRT - SQUARE - SQUARE_DIFFERENCE - STRIDED_SLICE - SUB - SUM - TANH - TILE - TRANSPOSE - TRANSPOSE_CONV - UNIDIRECTIONAL_SEQUENCE_LSTM - UNPACK ### Custom Operator - TFLite_Detection_PostProcess ## Tested networks Arm tested these operators with the following TensorFlow Lite neural network: - [Quantized MobileNet](http://download.tensorflow.org/models/mobilenet_v1_2018_02_22/mobilenet_v1_1.0_224_quant.tgz) - [Quantized SSD MobileNet](http://download.tensorflow.org/models/object_detection/ssd_mobilenet_v1_quantized_300x300_coco14_sync_2018_07_18.tar.gz) - DeepSpeech v1 converted from [TensorFlow model](https://github.com/mozilla/DeepSpeech/releases/tag/v0.4.1) - DeepSpeaker - [DeepLab v3+](https://www.tensorflow.org/lite/models/segmentation/overview) - FSRCNN - EfficientNet-lite - RDN converted from [TensorFlow model](https://github.com/hengchuan/RDN-TensorFlow) - Quantized RDN (CpuRef) - [Quantized Inception v3](http://download.tensorflow.org/models/tflite_11_05_08/inception_v3_quant.tgz) - [Quantized Inception v4](http://download.tensorflow.org/models/inception_v4_299_quant_20181026.tgz) (CpuRef) - Quantized ResNet v2 50 (CpuRef) - Quantized Yolo v3 (CpuRef) More machine learning operators will be supported in future releases. **/ } armnn-23.08/docs/05_02_serializer.dox000066400000000000000000000036571446772241200173070ustar00rootroot00000000000000/// Copyright (c) 2021-2023 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page serializer Serializer The `armnnSerializer` is a library for serializing an Arm NN network to a stream. @section serializersupport Supported Layers This reference guide provides a list of layers which can be serialized by the Arm NN SDK. The Arm NN SDK Serializer currently supports the following layers: - Activation - Addition - ArgMinMax - BatchMatMul - BatchToSpaceNd - BatchNormalization - Cast - ChannelShuffle - Comparison - Concat - Constant - Convolution2d - Convolution3d - DepthToSpace - DepthwiseConvolution2d - Dequantize - DetectionPostProcess - Division - ElementwiseUnary - Fill - Floor - FullyConnected - Gather - GatherNd - Input - InstanceNormalization - L2Normalization - Logical - LogSoftmax - Lstm - Maximum - Mean - Merge - Minimum - Multiplication - Normalization - Output - Pad (Constant, Symmetric, Reflect) - Permute - Pooling2d - Pooling3d - Prelu - QLstm - Quantize - QuantizedLstm - Rank - Reduce - Reshape - Resize - ReverseV2 - Shape - Slice - Softmax - SpaceToBatchNd - SpaceToDepth - Splitter - Stack - StandIn - StridedSlice - Subtraction - Switch - Transpose - TransposeConvolution2d - UnidirectionalSequenceLstm More machine learning layers will be supported in future releases. @section serializersupportdeprecated Deprecated layers Some layers have been deprecated and replaced by others layers. In order to maintain backward compatibility, serializations of these deprecated layers will deserialize to the layers that have replaced them, as follows: - Abs will deserialize as ElementwiseUnary - Equal will deserialize as Comparison - Greater will deserialize as Comparison - Merger will deserialize as Concat - ResizeBilinear will deserialize as Resize - Rsqrt will deserialize as ElementwiseUnary **/ } armnn-23.08/docs/05_03_delegate.dox000066400000000000000000000103551446772241200167020ustar00rootroot00000000000000/// Copyright (c) 2022-2023 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page delegate TfLite Delegate @section delegateintro About the delegate 'armnnDelegate' is a library for accelerating certain TensorFlow Lite (TfLite) operators on Arm hardware. It can be integrated in TfLite using its delegation mechanism. TfLite will then delegate the execution of operators supported by Arm NN to Arm NN. The main difference to our @ref S6_tf_lite_parser is the amount of operators you can run with it. If none of the active backends support an operation in your model you won't be able to execute it with our parser. In contrast to that, TfLite only delegates operations to the armnnDelegate if it does support them and otherwise executes them itself. In other words, every TfLite model can be executed and every operation in your model that we can accelerate will be accelerated. That is the reason why the armnnDelegate is our recommended way to accelerate TfLite models. If you need help building the armnnDelegate, please take a look at our [build guide](delegate/BuildGuideNative.md). @section delegatesupport Supported Operators This reference guide provides a list of TensorFlow Lite operators the Arm NN SDK currently supports. @section delegatefullysupported Fully supported The Arm NN SDK TensorFlow Lite delegate currently supports the following operators: - ABS - ADD - ARG_MAX - ARG_MIN - AVERAGE_POOL_2D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - AVERAGE_POOL_3D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, SIGN_BIT, TANH, NONE - BATCH_MATMUL - BATCH_TO_SPACE_ND - CAST - CEIL - CONCATENATION, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - CONV_2D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - CONV_3D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - DEPTH_TO_SPACE - DEPTHWISE_CONV_2D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - DEQUANTIZE - DIV - EQUAL - ELU - EXP - EXPAND_DIMS - FILL - FLOOR - FLOOR_DIV - FULLY_CONNECTED, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - GATHER - GATHER_ND - GREATER - GREATER_EQUAL - HARD_SWISH - L2_NORMALIZATION - L2_POOL_2D - LESS - LESS_EQUAL - LOCAL_RESPONSE_NORMALIZATION - LOG - LOGICAL_AND - LOGICAL_NOT - LOGICAL_OR - LOGISTIC - LOG_SOFTMAX - LSTM - MAXIMUM - MAX_POOL_2D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, TANH, NONE - MAX_POOL_3D, Supported Fused Activation: RELU, RELU6, RELU_N1_TO_1, SIGMOID, SIGN_BIT, TANH, NONE - MEAN - MINIMUM - MIRROR_PAD - MUL - NEG - NOT_EQUAL - PACK - PAD - PADV2 - POW - PRELU - QUANTIZE - RANK - REDUCE_MAX - REDUCE_MIN - REDUCE_PROD - RELU - RELU6 - RELU_N1_TO_1 - RESHAPE - RESIZE_BILINEAR - RESIZE_NEAREST_NEIGHBOR - REVERSEV2 - RSQRT - SHAPE - SIN - SOFTMAX - SPACE_TO_BATCH_ND - SPACE_TO_DEPTH - SPLIT - SPLIT_V - SQRT - SQUARE_DIFFERENCE - SQUEEZE - SLICE - STRIDED_SLICE - SUB - SUM - TANH - TILE - TRANSPOSE - TRANSPOSE_CONV - UNIDIRECTIONAL_SEQUENCE_LSTM - UNPACK More machine learning operators will be supported in future releases. @section delegateoptions Delegate Options The general list of runtime options are described in @subpage runtimeoptions @subsection opaquedelegateoptions Opaque Delegate Options In Opaque Delegate, delegate options are passed via ArmNNSettings which is a FlatBuffer of tflite::TFLiteSettings. Arm NN Settings | Possible Values | Description :--------------- ------------- | :----- | :---------- backends | ["GpuAcc"/"CpuAcc"] | A comma separated list without whitespaces of backends which should be used for execution. Falls back to next backend in list if previous does not provide support for operation. fastmath | [true/false] | Allows the use of optimisation techniques e.g. Winograd that will reduce execution time with the possibility of a drop in accuracy. additional_parameters | JSON string of additional Arm NN delegate options | JSON string of additional Arm NN delegate options. The general list of runtime options are described in [Runtime options](\ref runtimeoptions). **/ }armnn-23.08/docs/05_04_supportlibrary.dox000066400000000000000000000031451446772241200202310ustar00rootroot00000000000000/// Copyright (c) 2022 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page supportlibrary NNAPI Support Library @section supportlibraryintro About the NNAPI Support Library If you need help building the Arm NN NNAPI Support Library, please take a look at our [build guide](shim/BuildGuideShimSupportLibrary.md). @section sloptions Support Library Options The general list of runtime options are described in @subpage runtimeoptions @section slfullysupported Supported Operators The NNAPI Support Library currently supports the following operators: - ABS - ADD - ARGMAX - ARGMIN - AVERAGE_POOL_2D - BATCH_MATMUL - BATCH_TO_SPACE_ND - CAST - CONCATENATION - CONV_2D - DEPTH_TO_SPACE - DEPTHWISE_CONV_2D - DEQUANTIZE - DIV - ELU - EQUAL - EXP - EXPAND_DIMS - FILL - FLOOR - FULLY_CONNECTED - GATHER - GREATER - GREATER_EQUAL - GROUPED_CONV_2D - HARD_SWISH - INSTANCE_NORMALIZATION - L2_NORMALIZATION - L2_POOL_2D - LESS - LESS_EQUAL - LOCAL_RESPONSE_NORMALIZATION - LOG - LOGICAL_AND - LOGICAL_NOT - LOGICAL_OR - LOGISTIC - LOG_SOFTMAX - LSTM - MAX_POOL_2D - MAXIMUM - MEAN - MINIMUM - MUL - NEG - NOT_EQUAL - PAD - PADV2 - PRELU - POW - QUANTIZE - QUANTIZED_LSTM - QUANTIZED_16BIT_LSTM - RANK - REDUCE_MAX - REDUCE_MIN - REDUCE_PROD - REDUCE_SUM - RELU - RELU1 - RELU6 - RESHAPE - RESIZE_BILINEAR - RESIZE_NEAREST_NEIGHBOR - REVERSE - RSQRT - SIN - SOFTMAX - SPACE_TO_BATCH_ND - SPACE_TO_DEPTH - SQRT - SQUEEZE - STRIDED_SLICE - SUB - TILE - TRANSPOSE - TRANSPOSE_CONV_2D - TANH **/ }armnn-23.08/docs/05_05_runtimeoptions.dox000066400000000000000000000273561446772241200202420ustar00rootroot00000000000000/// Copyright (c) 2022 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page runtimeoptions Runtime options for Arm NN Across all software interfaces to Arm NN there are a set of common configuration parameters. These parameters control how a model is loaded or how the inference is executed. The widest set of options are available at the lowest, Arm NN C++ interface. They reduce as you move outward to the TfLite delegate and NNAPI Support Library. The tables below describe the arguments and in which interface they are available. @subsection deviceselection Compute device selection The compute device selected is required to be specified across all interfaces. The device selection will dictate the availability of some parameters and whether some sub graphs are supported. Interface | Device selection :-------- | :---------- Arm NN | The parameter "const std::vector& backendPreferences" to armnn::Optimize provides a vector of backendId's. If multiple devices are specifed the order of the vector dictates the order in which execution will be attempted. If all or part of the model is not supported by a backend, the next in order will be tried. TfLite delegate | armnnDelegate::DelegateOptions Compute device or backend ids: This tells Arm NN which devices will be used to process the inference. A single device can be specified using the armnn::Compute enum. Multiple devices can be specified using a vector of armnn::BackendId. If multiple devices are specifed the order of the vector dictates the order in which execution will be attempted. If all or part of the model is not supported by a backend the next in order will be tried. Valid backend ids are: [EthosNAcc/GpuAcc/CpuAcc/CpuRef] Support Library | armnn_driver::DriverOptions Compute device or backend ids: This tells Arm NN which devices will be used to process the inference. A single device can be specified using the armnn::Compute enum. Multiple devices can be specified using a vector of armnn::BackendId. If multiple devices are specifed the order of the vector dictates the order in which execution will be attempted. If all or part of the model is not supported by a backend the next in order will be tried. Valid backend ids are: [EthosNAcc/GpuAcc/CpuAcc/CpuRef] @subsection runtimeoptions Runtime options There a several levels at which Arm NN accepts runtime parameters. Some of these are specific to an Arm NN instance, some to a loaded network and some to the backend on which a network inference is to execute. Each of the external interfaces handles these options in different ways. @subsection instanceoptions Arm NN Instance level options In the Arm NN C++ interface these options are set by passing an armnn::CreationOptions struct to IRuntime. Not all available options are described here. Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :----- | :---------- m_DynamicBackendsPath | dynamic-backends-path | (Not Available) | String file path | A path in which Arm NN will search for dynamic backends to load. m_ProtectedMode | (Not Available) | (Not Available) | ["true"/"false"] | Setting this flag will allow the user to create the Runtime in protected mode. It will run all the inferences on protected memory and will make sure that INetworkProperties::m_ImportEnabled set to true with MemorySource::DmaBufProtected option. This requires that the backend supports Protected Memory and has an allocator capable of allocating Protected Memory associated with it. m_CustomAllocatorMap | (Not Available) | (Not Available) | std::map> | A map of Custom Allocator used for allocation of working memory in the backends. Required for Protected Mode in order to correctly allocate Protected Memory m_MemoryOptimizerStrategyMap | (Not Available) | (Not Available) | std::map> | A map to define a custom memory optimizer strategy for specific backend Ids. m_GpuAccTunedParameters | gpu-tuning-level | cl-tuning-level | ["0"/"1"/"2"/"3"] | 0=UseOnly(default), 1=RapidTuning, 2=NormalTuning, 3=ExhaustiveTuning. Requires option gpu-tuning-file. 1,2 and 3 will create a tuning-file, 0 will apply the tunings from an existing file (Not Available) | disable-tflite-runtime-fallback | (Not Available) | ["true"/"false"] | Disable TfLite Runtime fallback in the Arm NN TfLite delegate. An exception will be thrown if unsupported operators are encountered. This option is only for testing purposes. armnn::ConfigureLogging | logging-severity | verbose-logging | [Trace/Debug/Info/Warning/Error/Fatal | Set the level of logging information output by Arm NN. armnn::IOptimizedNetworkPtr->SerializeToDot | serialize-to-dot | (Not Available) | String file path | Serialize the optimized network to the file specified in "dot" format. A specific sub-struct of parameters exists to configure external profiling. This is held as a member, m_ProfilingOptions, of CreationOptions Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :----- | :---------- m_ProfilingOptions.m_EnableProfiling | enable-external-profiling | (Not Available) | ["true"/"false"] | Enable external profiling. m_ProfilingOptions.m_TimelineEnabled | timeline-profiling | (Not Available) | ["true"/"false"] | Enable Arm Development studio Timeline events. m_ProfilingOptions.m_OutgoingCaptureFile | outgoing-capture-file | (Not Available) | String file path | Path to a file in which outgoing timeline profiling messages will be stored. m_ProfilingOptions.m_IncomingCaptureFile | incoming-capture-file | (Not Available) | String file path | Path to a file in which incoming timeline profiling messages will be stored. m_ProfilingOptions.m_FileOnly | file-only-external-profiling | (Not Available) | ["true"/"false"] | Enable profiling output to file only. m_ProfilingOptions.m_CapturePeriod | counter-capture-period | (Not Available) | Integer (default : 10000) | Value in microseconds of the profiling capture period. m_ProfilingOptions.m_FileFormat | profiling-file-format | (Not Available) | String of ["binary"] | The format of the file used for outputting profiling data. Currently on "binary" is supported. @subsection networkoptions NetworkOptions During Network creation you can specify several optional parameters via armnn::NetworkOptions. Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :----- | :---------- ShapeInferenceMethod | infer-output-shape | (Not Available) | ["true"/"false"] | Infers output tensor shape from input tensor shape and validate where applicable. AllowExpandedDims | allow-expanded-dims | (Not Available) | ["true"/"false"] | If true will disregard dimensions with a size of 1 when validating tensor shapes. Tensor sizes must still match. This is an Experimental parameter that is incompatible with infer-output-shape. profilingEnabled | enable-internal-profiling | enable-internal-profiling | ["true"/"false"] | Enable json profiling in CpuAcc and GpuAcc backends. detailsMethod | internal-profiling-detail | (Not Available) | ProfilingDetailsMethod | Set the detail of internale porfiling. Options are DetailsWithEvents and DetailsOnly. @subsection optimizeroptions OptimizerOptions OptimizerOptions are a set of parameters specifically targeting the Arm NN optimizer. This executes when a model is being loaded and these parameters are used to tune its operation. Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :----- | :---------- reduceFp32ToFp16 | reduce-fp32-to-fp16 | (Not available) | ["true"/"false"] | Note This feature works best if all operators of the model are in Fp32. ArmNN will add conversion layers between layers that weren't in Fp32 in the first place or if the operator is not supported in Fp16. The overhead of these conversions can lead to a slower overall performance if too many conversions are required. reduceFp32ToBf16 | reduce-fp32-to-bf16 | (Not available) | ["true"/"false"] | This feature has been replaced by enabling Fast Math in compute library backend options. This is currently a placeholder option debug | debug-data | (Not available) | ["true"/"false"] | If the debug flag is set a DebugLayer is inserted after each layer. The action of each debug layer is backend specific. importEnabled | memory-import | (Not available) | ["true"/"false"] | Instructs the optimizer that this model will be importing it's input tensors. This value must match the MemorySource set for input in INetworkProperties. exportEnabled | (Not available) | (Not available) | ["true"/"false"] | Instructs the optimizer that this model will be exporting it's output tensors. This value must match the MemorySource set for output in INetworkProperties. @subsection modeloptions OptimizerOptions::ModelOptions Model options is a vector of name value pairs contained inside OptimizerOptions. The options specifically target backends. @subsection gpuaccmodeloptions GpuAcc backend model options Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :----- | :---------- FastMathEnabled | enable-fast-math | enable-fast-math | ["true"/"false"] | Enables fast_math options in backends that support it. SaveCachedNetwork| save-cached-network |save-cached-network | ["true"/"false"] | Enables saving the cached network to the file given with cached-network-file option. CachedNetworkFilePath| cached-network-filepath |cached-network-file | String file path | If non-empty, the given file will be used to load/save cached network. If save-cached-network option is given will save the cached network to given file. If save-cached-network option is not given will load the cached network from given file. MLGOTuningFilePath |gpu-mlgo-tuning-file | mlgo-cl-tuned-parameters-file | String file path | If non-empty, the given file will be used to load/save MLGO CL tuned parameters. KernelProfilingEnabled | gpu-kernel-profiling-enabled | (Not available) | ["true"/"false"] | Enables GPU kernel profiling @subsection cpuaccmodeloptions CpuAcc backend model options Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :--- | :---------- FastMathEnabled | enable-fast-math | enable-fast-math | ["true"/"false"] | Enables fast_math options in backends that support it. NumberOfThreads | number-of-threads | number-of-threads | Integer [1-64] | Assign the number of threads used by the CpuAcc backend. Input value must be between 1 and 64. Default is set to 0 (Backend will decide number of threads to use). @subsection ethosnmodeloptions EthosNAcc backend model options Arm NN Parameter | Delegate | Support library | Values | Description :--------------- | :-------- | :-------------- | :--- | :---------- DisableWinograd | (Not available) | (Not available) | ["true"/"false"] | Disables Winograd fast convolution. StrictPrecision | (Not available) | (Not available) | ["true"/"false"] | When enabled the network is more precise as the Re-quantize operations aren't fused, but it is slower to compile as there will be additional operations. This is currently only supported for the Concat operation. SaveCachedNetwork| save-cached-network |save-cached-network | ["true"/"false"] | Enables saving the cached network to the file given with cached-network-file option. CachedNetworkFilePath| cached-network-filepath |cached-network-file | String file path | If non-empty, the given file will be used to load/save cached network. If save-cached-network option is given will save the cached network to given file. If save-cached-network option is not given will load the cached network from given file. **/ }armnn-23.08/docs/05_06_deserializer.dox000066400000000000000000000034301446772241200176110ustar00rootroot00000000000000/// Copyright (c) 2021-2023 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// namespace armnn { /** @page deserializer Deserializer The `armnnDeserializer` is a library for loading neural networks defined by Arm NN FlatBuffers files into the Arm NN runtime. @section deserializersupport Supported Layers The Arm NN SDK Deserialize parser currently supports the following layers: - Abs - Activation - Addition - ArgMinMax - BatchMatMul - BatchToSpaceNd - BatchNormalization - Cast - ChannelShuffle - Concat - Comparison - Constant - Convolution2d - DepthToSpace - DepthwiseConvolution2d - Dequantize - DetectionPostProcess - Division - ElementwiseUnary - Fill - Floor - FullyConnected - Gather - GatherNd - Input - InstanceNormalization - L2Normalization - Logical - LogSoftmax - Lstm - Maximum - Mean - Merge - Minimum - Multiplication - Normalization - Output - Pad - Permute - Pooling2d - Pooling3d - Prelu - Quantize - QLstm - QuantizedLstm - Rank - Reduce - Reshape - Resize - ResizeBilinear - ReverseV2 - Slice - Softmax - SpaceToBatchNd - SpaceToDepth - Splitter - Stack - StandIn - StridedSlice - Subtraction - Switch - Transpose - TransposeConvolution2d - UnidirectionalSequenceLstm More machine learning layers will be supported in future releases. @section deserializersupportdeprecated Deprecated layers Some layers have been deprecated and replaced by others layers. In order to maintain backward compatibility, serializations of these deprecated layers will deserialize to the layers that have replaced them, as follows: - Equal will deserialize as Comparison - Merger will deserialize as Concat - Greater will deserialize as Comparison - ResizeBilinear will deserialize as Resize **/ } armnn-23.08/docs/Arm_NN_horizontal_blue.png000066400000000000000000000402341446772241200207050ustar00rootroot00000000000000PNG  IHDRwTd+ pHYsgRYiTXtXML:com.adobe.xmp v*9IDATxg!B1%mZQ_C =Zh C 5PL ^ Qbzz `lm~82^ֻ+)=ϝ{Gw==6050L^u$,xk5X y9\gj+R} Q50p4I`,pUe;"s \SJ)TzFrG$tlj`4qB̎$uG%x2pXTJ)T y|`f LIitykV\ |J)j@&w? 8Єٞun\iksORJ)TZ/ـ+-GW -[:7ļO\ļǧHw#+#-ɢZxPRJ)Ո|=QLnDNҪl`ш|XΏ!(<"468T`fJ)jP~;Y{ X8G=p 8Y25 $Z۵ǁ]qW 沁ˈy [qJ)2n;Hs.[f82u F^ r+ags*Ray>Ps1g:GJ\gH6v0b\gȽr]kiRٟl:f(RJ>;ϟXp=@j4.&Qi1Ǒ-1O5SJ)RN6kbE] ;,܍3=:-]G9OʵǺJ)JI^ ?1]Ed$il/p Y>`Ҹ[ o#J)Tnykcu]qtmi?++Z68RJ)&wK\,~Jq֏3;~Z)ܨRC)R@;Tf11g:tuz' "_*R)crz+ Z3ڴ[mkRJ:yLf۽8M+kK-5IoSB)RLLʏ?q|JtuZ,(AӟRJ) /V& ifx}ҵ+KC FĭRJ)CK׮K)M -(5X/80RJ)53z=<N>x]{@i84nRJkr&!Iwpw;^_M[ճ7?O$RJ)krVQC>`Q%2w^>6sIH|?k\DWJ)TܹǘLm {n_g8sWyc G5RJ)gr'0h<H3z㘗W^J)2:%!6<o7<=ޭqWUFS6_qMͯRJ)Z%BfF; U<췛t):f0RJ)iN;MArX 9יĹRJ)Յ~YPo "͟ ڄjF\&̩RJ)y[ %N]p5Ł9k> i_;Q%O1jrHo݅AH: iIQ\dVJ)T g8s`q\g|1Mw-b8/RJ,wϝ/l7udN[p3)ĢRJ7Ӏ $>pz'sD7*_ ajVRJ)|&wvFVeqo8fD+}r x(jBt@Xʪ`}K)K%N=d8\gbpd`i\Db.45 |BDy0`C5s;u%\ l=%ledHFfvWWpϛfd0ҹgA` L<<|؄xK 0<0i%ru LK=r-'sP,4BXZ)y,z`h`ωQM\XX9Un_ {mLjxς<9_uLi9P,MVGfH  E: Y{dOi?U >>Bbpu1ΞeiuJxq-4׮io?OBWA Œiɵ60m[cD$#v.uM4_:'(M79X`͸;)K?83.KZ<,J5btfE)4@_]I$&un|QQ L~1F)|bѲde\wH `i^<un< ip ?QhObHly7QpUX$@Z+ RO;mr0/&֮mHOAtTsX7PX?sZM/d<7^+K3?Vy#?h41뼄yG3kGeMS)JlԳ!PA7bƽѾJt@Bjց=_>wKd_>Fa }9u1j 'b^Qq"#mWOh6Z@\(V:BtlAĕF6Cj͂xxי~Z?ܘP\K<$2q9q1oMs֮ xRSLC΅fG0~|xꭿFjʩKP]Z _y @4I֩VѻJYUNM$^K)^[6dvI1SG?Vߘ##ZFK@>gz&.: 6,B>Z=ުN/KV+ $hɝ/00)(3u |qr)x@pɞaֆlq }}?ςZ8 |JcId*ҭ if :oWm* 7/4^A܈t/TVG&q"3ҷk ʪB]R9@L4IwNYTr>_v@ryYʷ Jl s!#BJuxI :!<adu &:ow{lѩFͣ.^:?W %z6K9ӳq)ub{ϿdV[1)cڐ"ǛW+廳Q#YH|PuP-kA<%v-T¿=np>ppM\=\ dkQ7:M\k\矸ΊHw!bnO`]{3YMs$3>\GLwi # _J,I1իiS25O<dB5rq<(^ʯ hn~? ¼F ;IX6~ljƓ̇:[F :7:IJX`H_]g*3?/i%\H~ 1Oqo޼k5ee$3;y՝b)m1C 9hfS#nOZ{#p3A͡$`c\Ǵfc}3  lA \e&ta;3-\["aؽ]r@,&pU+2zZb?CZߥR<'w.=x\ۗ/rjF`ŬC:N័GY?Y:sgsvcs97]뜕u)> |}{4{%q*yDHERr[M9=t\:ٯhRfN<( / UVKyr R/7g/a)ۑu%ۦQ9akeЦ̕/zg=}ΣI^ȽđVf LZ)_ *K{<߃77G@_@]As7b#oY3880: ܄Zf9Nw":C'pVdt&y6ω-S~̘`By-{M?Ij|u.P,m1ij:Cӏ\D*N:#⼖Y<meakl .0HNgvY,M²7vI$x0O&&|$ܒt9~DHYRgWZwn⪕k&[BلNHqQR~P,mC'Hrվ;|٨VC LuF ̞a>NY9h(:g7 u^u@GϳUfwA2m':$v3lTZ=8Dlsa|HJ!_j{So$ \gb"Rܸr`>zN)KLU+N =/5)t`}\=3h Zx⑽O;Dy> cHuVɝϗ(EXVWdmcw?;khݚJ=h<1wzA riJV\q&$uJy.?P,rHVA+)c桤n'q?[:񾹺9HiS&aK̗߯Fm):Wğ>C [pŠmk*NÑC y,WnJ"9_:}~x7(fViJT" |n^\(K9\VʷXVeiCVLܟP !mL$QfׇrWhNQ{bsk=$]wb, Θ Y6JʐwSY]W"}SWDV=5i./Ky횉ZFZn\e׆I<7IW[FQm8o~hX`fs3}ĶLWۺf[_""MLqqI%q3|dqO} j޿Huҏ*4Vww;`LV5ېr&F'Ԓfy 9)j"Fs`v"e>h{{CwLKiº Ҩa")đ]ܲ:ix!*RlK3JY~)'R'!ឭsiBdYߣT+3i@& Ӑ}difu386B 5gp}{} z<lk pᨼ;zMvnYl:~^7Yj%<6~ݿ݅biʯj| \)Չj4{,4poXߗ&xΥӬo>CO&5$(¸ޟh3c'&BϷY>V]8(PJVʏ"IKR9+ lGOJy"҂^MYGf=ۤRD3kxbxSB`i[?ap/E.8%ӟoD+M$d+rZ)?୊$-U>j44@qv!ڀ' xCz_Dc1[Z OcPMqgif@ŭS\A$̤еR*G_ nmB4 V3Dc5Mf`~Iy( U+sF~r8VeKBB¸l+0r ?abA؏ 9mDlqlD x,ȿTRkC ӎ'ϪSӔFjf`SVxC"M--jAGU%=R25}p#. \@s/C2qlRȡ;2 H|n`Ok%VR#p7{ߊdypd{ƝR=~lHѝ j|v!SR Ҧg{w.W.K׊#:/)P,rHVGLsQJt|Dx>(0d]Gu]x$-"+ny7UA4DhcFyyRMWPm9mH @f^ \1/3ows&6y`MV9wqlGrbTasjAzƵ%߼DKY݀lPJoc~lCVO?V4pvE <:X(4_\g!}dۗO8N=n鱭 h|ڞLkfuܪx_Wݝ>י_#^ieGa#O:x0ComMAV@"z? #!O_u&n6oo"l%q ¥h0cGb[%ŐH"-B. yBy?i駔R-Z)W R Izzbi#iIÒۀ/-^3H_SS|ZSN=>(ItF7/pP20Ykqxۺvs'dRJVO֒Y'Ϫj@qi=$u1t1o>A9}lA ᨩ_o>IamE)LU+Gܫ =kLFa ۊ~׶Kfgo6wV= ٯZ~ )ʝj|A; kr%i۪~G!{MD} ,j8f#Z}# y'Jv\=iW${E+:VʗdG+V#?:MzmEyI` 9 9jUrV7dJ'uzJTªhJMdo{ #w&[R#w%WH4Dy`M,3u8*)VʧHYER)57MQ[zmt8=Hg}UZRaީߵJ\R} X9%RQ$Y=HR~Igu/jRe)c)8dbQӹ۸Uio:O6q^Tq pqAjJ$Wĸ pT>j[a^4lk ? t(1uePE:#oyi|)srPwMշI84}'%H'ޣa}Bׯg?U+ibiov [j`XZ-^Gik{b[Qn 970o| u|qaπű)Sxjfno* \>?ϟ;?:/QJϟ iaV@YHy:\513uR)KRJirW_XD^RsAxXp5֟n55*}?\R(KU+mabi&we_ G ,m5`<a1?#ƶM+RJ)Dz.܏ԣ+TpXǥ"&0ۚ#pykTĶ>@V+XQTJ)Tca20{`gl+[eNJݸ u%QkY_)Rkra[o'ñHب hel롄cOiԬj ǠRJvܙ:/K<-ox9G _.4\q(RgyMF\eQ^ow\&%b&"5p|RJ^']4DJti0P*Qtnakƶ&mbRJ)e(nx}zM\ȷ#H+NNilN?_RJcrgG6ӟ]AE13$)?\RJ)δIɂI]jQ$a3MMikRJ:yL1>=\A8;0`iq<.MZADPJ)T>1[Z)@"TG׮Th \f0$nRJ_r'L6BΛR4^Z*QtUk&^H)u܉qvI<  `8$^4~# G78RJ)&w^Ah7s\!F1taL.p cM'фcPJ)T;=% 87كp)HQ$6cG_dkׂpn_󧱭K(RZ>;zxpvၱy[#= zՀc G^{nRJu+ɝ"˜3 C" #ݕN^y/lÑN)J]O"; hTn< ,aN2-m=<5'#FFN9>0N)Rҩ}Y;-e+] R@`|2)* ydql.IżtSV=nRJ^/ݬHybd$ GYb{l''jZ{ uYXga[żRJ) KYх'ձ2B>OD5 Kb[vL)j<U7'v*atb*&vJ)T?OdD;?;c[oelBJmibRZ#ŶbHӮYQsuzA(RMk$w%P¼j¶8I9kBcPJ)z(<_Mלt6ُ`^RJъPp"phf jKF4a/{0RJ)КtA0JWFLFǷ \'V\<49RJ)ՀN`*_+NnDλ[ l , c S)R1~r7$y; mE˻X_V`t I:NA9ҲrlSJ)TzNr^FC , ]0K*v!l륦ǚi*6,ҎmX$}55RJ)Հ·mH vIENDB`armnn-23.08/docs/Arm_NN_horizontal_blue.png.license000066400000000000000000000001461446772241200223240ustar00rootroot00000000000000# # Copyright © 2020 Arm Ltd and Contributors. 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Doxygen will then generate output that is tailored for VHDL. # The default value is: NO. OPTIMIZE_OUTPUT_VHDL = NO # Doxygen selects the parser to use depending on the extension of the files it # parses. With this tag you can assign which parser to use for a given # extension. Doxygen has a built-in mapping, but you can override or extend it # using this tag. The format is ext=language, where ext is a file extension, and # language is one of the parsers supported by doxygen: IDL, Java, Javascript, # C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: # FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: # Fortran. In the later case the parser tries to guess whether the code is fixed # or free formatted code, this is the default for Fortran type files), VHDL. For # instance to make doxygen treat .inc files as Fortran files (default is PHP), # and .f files as C (default is Fortran), use: inc=Fortran f=C. # # Note: For files without extension you can use no_extension as a placeholder. # # Note that for custom extensions you also need to set FILE_PATTERNS otherwise # the files are not read by doxygen. EXTENSION_MAPPING = # If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments # according to the Markdown format, which allows for more readable # documentation. See http://daringfireball.net/projects/markdown/ for details. # The output of markdown processing is further processed by doxygen, so you can # mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in # case of backward compatibilities issues. # The default value is: YES. MARKDOWN_SUPPORT = YES # When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up # to that level are automatically included in the table of contents, even if # they do not have an id attribute. # Note: This feature currently applies only to Markdown headings. # Minimum value: 0, maximum value: 99, default value: 0. # This tag requires that the tag MARKDOWN_SUPPORT is set to YES. TOC_INCLUDE_HEADINGS = 0 # When enabled doxygen tries to link words that correspond to documented # classes, or namespaces to their corresponding documentation. Such a link can # be prevented in individual cases by putting a % sign in front of the word or # globally by setting AUTOLINK_SUPPORT to NO. # The default value is: YES. AUTOLINK_SUPPORT = YES # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should set this # tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); # versus func(std::string) {}). This also make the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. # The default value is: NO. BUILTIN_STL_SUPPORT = NO # If you use Microsoft's C++/CLI language, you should set this option to YES to # enable parsing support. # The default value is: NO. CPP_CLI_SUPPORT = NO # Set the SIP_SUPPORT tag to YES if your project consists of sip (see: # http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen # will parse them like normal C++ but will assume all classes use public instead # of private inheritance when no explicit protection keyword is present. # The default value is: NO. SIP_SUPPORT = NO # For Microsoft's IDL there are propget and propput attributes to indicate # getter and setter methods for a property. Setting this option to YES will make # doxygen to replace the get and set methods by a property in the documentation. # This will only work if the methods are indeed getting or setting a simple # type. If this is not the case, or you want to show the methods anyway, you # should set this option to NO. # The default value is: YES. IDL_PROPERTY_SUPPORT = YES # If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC # tag is set to YES then doxygen will reuse the documentation of the first # member in the group (if any) for the other members of the group. By default # all members of a group must be documented explicitly. # The default value is: NO. DISTRIBUTE_GROUP_DOC = NO # If one adds a struct or class to a group and this option is enabled, then also # any nested class or struct is added to the same group. By default this option # is disabled and one has to add nested compounds explicitly via \ingroup. # The default value is: NO. GROUP_NESTED_COMPOUNDS = NO # Set the SUBGROUPING tag to YES to allow class member groups of the same type # (for instance a group of public functions) to be put as a subgroup of that # type (e.g. under the Public Functions section). Set it to NO to prevent # subgrouping. Alternatively, this can be done per class using the # \nosubgrouping command. # The default value is: YES. SUBGROUPING = YES # When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions # are shown inside the group in which they are included (e.g. using \ingroup) # instead of on a separate page (for HTML and Man pages) or section (for LaTeX # and RTF). # # Note that this feature does not work in combination with # SEPARATE_MEMBER_PAGES. # The default value is: NO. INLINE_GROUPED_CLASSES = NO # When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions # with only public data fields or simple typedef fields will be shown inline in # the documentation of the scope in which they are defined (i.e. file, # namespace, or group documentation), provided this scope is documented. If set # to NO, structs, classes, and unions are shown on a separate page (for HTML and # Man pages) or section (for LaTeX and RTF). # The default value is: NO. INLINE_SIMPLE_STRUCTS = NO # When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or # enum is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct # with name TypeT. When disabled the typedef will appear as a member of a file, # namespace, or class. And the struct will be named TypeS. This can typically be # useful for C code in case the coding convention dictates that all compound # types are typedef'ed and only the typedef is referenced, never the tag name. # The default value is: NO. TYPEDEF_HIDES_STRUCT = NO # The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This # cache is used to resolve symbols given their name and scope. Since this can be # an expensive process and often the same symbol appears multiple times in the # code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small # doxygen will become slower. If the cache is too large, memory is wasted. The # cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range # is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 # symbols. At the end of a run doxygen will report the cache usage and suggest # the optimal cache size from a speed point of view. # Minimum value: 0, maximum value: 9, default value: 0. LOOKUP_CACHE_SIZE = 0 #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- # If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in # documentation are documented, even if no documentation was available. Private # class members and static file members will be hidden unless the # EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. # Note: This will also disable the warnings about undocumented members that are # normally produced when WARNINGS is set to YES. # The default value is: NO. EXTRACT_ALL = YES # If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will # be included in the documentation. # The default value is: NO. EXTRACT_PRIVATE = NO # If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal # scope will be included in the documentation. # The default value is: NO. EXTRACT_PACKAGE = NO # If the EXTRACT_STATIC tag is set to YES, all static members of a file will be # included in the documentation. # The default value is: NO. EXTRACT_STATIC = NO # If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined # locally in source files will be included in the documentation. If set to NO, # only classes defined in header files are included. Does not have any effect # for Java sources. # The default value is: YES. EXTRACT_LOCAL_CLASSES = NO # This flag is only useful for Objective-C code. If set to YES, local methods, # which are defined in the implementation section but not in the interface are # included in the documentation. If set to NO, only methods in the interface are # included. # The default value is: NO. EXTRACT_LOCAL_METHODS = YES # If this flag is set to YES, the members of anonymous namespaces will be # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base name of # the file that contains the anonymous namespace. By default anonymous namespace # are hidden. # The default value is: NO. EXTRACT_ANON_NSPACES = NO # If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all # undocumented members inside documented classes or files. If set to NO these # members will be included in the various overviews, but no documentation # section is generated. This option has no effect if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_MEMBERS = NO # If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. If set # to NO, these classes will be included in the various overviews. This option # has no effect if EXTRACT_ALL is enabled. # The default value is: NO. HIDE_UNDOC_CLASSES = NO # If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend # (class|struct|union) declarations. If set to NO, these declarations will be # included in the documentation. # The default value is: NO. HIDE_FRIEND_COMPOUNDS = NO # If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any # documentation blocks found inside the body of a function. If set to NO, these # blocks will be appended to the function's detailed documentation block. # The default value is: NO. HIDE_IN_BODY_DOCS = NO # The INTERNAL_DOCS tag determines if documentation that is typed after a # \internal command is included. If the tag is set to NO then the documentation # will be excluded. Set it to YES to include the internal documentation. # The default value is: NO. INTERNAL_DOCS = NO # If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file # names in lower-case letters. If set to YES, upper-case letters are also # allowed. This is useful if you have classes or files whose names only differ # in case and if your file system supports case sensitive file names. Windows # and Mac users are advised to set this option to NO. # The default value is: system dependent. CASE_SENSE_NAMES = NO # If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with # their full class and namespace scopes in the documentation. If set to YES, the # scope will be hidden. # The default value is: NO. HIDE_SCOPE_NAMES = YES # If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will # append additional text to a page's title, such as Class Reference. If set to # YES the compound reference will be hidden. # The default value is: NO. #HIDE_COMPOUND_REFERENCE= NO # If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of # the files that are included by a file in the documentation of that file. # The default value is: YES. SHOW_INCLUDE_FILES = YES # If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each # grouped member an include statement to the documentation, telling the reader # which file to include in order to use the member. # The default value is: NO. #SHOW_GROUPED_MEMB_INC = NO # If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include # files with double quotes in the documentation rather than with sharp brackets. # The default value is: NO. FORCE_LOCAL_INCLUDES = NO # If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the # documentation for inline members. # The default value is: YES. INLINE_INFO = YES # If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the # (detailed) documentation of file and class members alphabetically by member # name. If set to NO, the members will appear in declaration order. # The default value is: YES. SORT_MEMBER_DOCS = YES # If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief # descriptions of file, namespace and class members alphabetically by member # name. If set to NO, the members will appear in declaration order. Note that # this will also influence the order of the classes in the class list. # The default value is: NO. SORT_BRIEF_DOCS = NO # If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the # (brief and detailed) documentation of class members so that constructors and # destructors are listed first. If set to NO the constructors will appear in the # respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. # Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief # member documentation. # Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting # detailed member documentation. # The default value is: NO. SORT_MEMBERS_CTORS_1ST = NO # If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy # of group names into alphabetical order. If set to NO the group names will # appear in their defined order. # The default value is: NO. SORT_GROUP_NAMES = NO # If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by # fully-qualified names, including namespaces. If set to NO, the class list will # be sorted only by class name, not including the namespace part. # Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. # Note: This option applies only to the class list, not to the alphabetical # list. # The default value is: NO. SORT_BY_SCOPE_NAME = NO # If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper # type resolution of all parameters of a function it will reject a match between # the prototype and the implementation of a member function even if there is # only one candidate or it is obvious which candidate to choose by doing a # simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still # accept a match between prototype and implementation in such cases. # The default value is: NO. STRICT_PROTO_MATCHING = NO # The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo # list. This list is created by putting \todo commands in the documentation. # The default value is: YES. GENERATE_TODOLIST = YES # The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test # list. This list is created by putting \test commands in the documentation. # The default value is: YES. GENERATE_TESTLIST = YES # The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug # list. This list is created by putting \bug commands in the documentation. # The default value is: YES. GENERATE_BUGLIST = YES # The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) # the deprecated list. This list is created by putting \deprecated commands in # the documentation. # The default value is: YES. GENERATE_DEPRECATEDLIST= YES # The ENABLED_SECTIONS tag can be used to enable conditional documentation # sections, marked by \if ... \endif and \cond # ... \endcond blocks. ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the # initial value of a variable or macro / define can have for it to appear in the # documentation. If the initializer consists of more lines than specified here # it will be hidden. Use a value of 0 to hide initializers completely. The # appearance of the value of individual variables and macros / defines can be # controlled using \showinitializer or \hideinitializer command in the # documentation regardless of this setting. # Minimum value: 0, maximum value: 10000, default value: 30. MAX_INITIALIZER_LINES = 30 # Set the SHOW_USED_FILES tag to NO to disable the list of files generated at # the bottom of the documentation of classes and structs. If set to YES, the # list will mention the files that were used to generate the documentation. # The default value is: YES. SHOW_USED_FILES = YES # Set the SHOW_FILES tag to NO to disable the generation of the Files page. This # will remove the Files entry from the Quick Index and from the Folder Tree View # (if specified). # The default value is: YES. SHOW_FILES = YES # Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces # page. This will remove the Namespaces entry from the Quick Index and from the # Folder Tree View (if specified). # The default value is: YES. SHOW_NAMESPACES = YES # The FILE_VERSION_FILTER tag can be used to specify a program or script that # doxygen should invoke to get the current version for each file (typically from # the version control system). Doxygen will invoke the program by executing (via # popen()) the command command input-file, where command is the value of the # FILE_VERSION_FILTER tag, and input-file is the name of an input file provided # by doxygen. Whatever the program writes to standard output is used as the file # version. For an example see the documentation. FILE_VERSION_FILTER = # The LAYOUT_FILE tag can be used to specify a layout file which will be parsed # by doxygen. The layout file controls the global structure of the generated # output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. You can # optionally specify a file name after the option, if omitted DoxygenLayout.xml # will be used as the name of the layout file. # # Note that if you run doxygen from a directory containing a file called # DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE # tag is left empty. LAYOUT_FILE = # The CITE_BIB_FILES tag can be used to specify one or more bib files containing # the reference definitions. This must be a list of .bib files. The .bib # extension is automatically appended if omitted. This requires the bibtex tool # to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. # For LaTeX the style of the bibliography can be controlled using # LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the # search path. See also \cite for info how to create references. CITE_BIB_FILES = #--------------------------------------------------------------------------- # Configuration options related to warning and progress messages #--------------------------------------------------------------------------- # The QUIET tag can be used to turn on/off the messages that are generated to # standard output by doxygen. If QUIET is set to YES this implies that the # messages are off. # The default value is: NO. QUIET = NO # The WARNINGS tag can be used to turn on/off the warning messages that are # generated to standard error (stderr) by doxygen. If WARNINGS is set to YES # this implies that the warnings are on. # # Tip: Turn warnings on while writing the documentation. # The default value is: YES. WARNINGS = YES # If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate # warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag # will automatically be disabled. # The default value is: YES. WARN_IF_UNDOCUMENTED = YES # If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for # potential errors in the documentation, such as not documenting some parameters # in a documented function, or documenting parameters that don't exist or using # markup commands wrongly. # The default value is: YES. WARN_IF_DOC_ERROR = YES # This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that # are documented, but have no documentation for their parameters or return # value. If set to NO, doxygen will only warn about wrong or incomplete # parameter documentation, but not about the absence of documentation. # The default value is: NO. WARN_NO_PARAMDOC = YES # If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when # a warning is encountered. # The default value is: NO. WARN_AS_ERROR = NO # The WARN_FORMAT tag determines the format of the warning messages that doxygen # can produce. The string should contain the $file, $line, and $text tags, which # will be replaced by the file and line number from which the warning originated # and the warning text. Optionally the format may contain $version, which will # be replaced by the version of the file (if it could be obtained via # FILE_VERSION_FILTER) # The default value is: $file:$line: $text. WARN_FORMAT = "$file:$line:[DOXY_WARN] $text" # The WARN_LOGFILE tag can be used to specify a file to which warning and error # messages should be written. If left blank the output is written to standard # error (stderr). WARN_LOGFILE = #--------------------------------------------------------------------------- # Configuration options related to the input files #--------------------------------------------------------------------------- # The INPUT tag is used to specify the files and/or directories that contain # documented source files. You may enter file names like myfile.cpp or # directories like /usr/src/myproject. Separate the files or directories with # spaces. See also FILE_PATTERNS and EXTENSION_MAPPING # Note: If this tag is empty the current directory is searched. INPUT = ./docs/01_00_quick_start.dox \ ./docs/02_operator_list.dox \ ./docs/03_build_guides.dox \ ./docs/04_contributor.dox \ ./docs/05_00_software_components.dox \ ./docs/05_01_parsers.dox \ ./docs/05_02_serializer.dox \ ./docs/05_03_delegate.dox \ ./docs/05_04_supportlibrary.dox \ ./docs/05_05_runtimeoptions.dox \ ./docs/05_06_deserializer.dox \ ./docs/FAQ.md \ ./tests/ImageCSVFileGenerator/README.md \ ./tests/ImageTensorGenerator/README.md \ ./tests/ModelAccuracyTool-Armnn/README.md \ ./python/pyarmnn/README.md \ ./include/ \ ./src/ \ ./src/armnnConverter/README.md \ ./src/backends/README.md \ ./src/dynamic/README.md \ ./delegate/classic/include \ ./delegate/opaque/include \ ./delegate/classic/src/armnn_external_delegate.cpp \ ./delegate/opaque/src/armnn_external_delegate.cpp \ ./delegate/BuildGuideNative.md \ ./delegate/DelegateQuickStartGuide.md \ ./shim/ \ ./shim/BuildGuideShimSupportLibrary.md \ ./shim/sl/ \ ./shim/sl/canonical/ \ ./README.md \ ./InstallationViaAptRepository.md \ ./CONTRIBUTING.md \ ./BuildGuideAndroidNDK.md \ ./samples/examples.dox # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses # libiconv (or the iconv built into libc) for the transcoding. See the libiconv # documentation (see: http://www.gnu.org/software/libiconv) for the list of # possible encodings. # The default value is: UTF-8. INPUT_ENCODING = UTF-8 # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and # *.h) to filter out the source-files in the directories. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # read by doxygen. # # If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, # *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, # *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, # *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, # *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf. FILE_PATTERNS = *.cpp \ *.inl \ *.h \ *.hpp \ *.md \ *.dox \ *.py # The RECURSIVE tag can be used to specify whether or not subdirectories should # be searched for input files as well. # The default value is: NO. RECURSIVE = YES # The EXCLUDE tag can be used to specify files and/or directories that should be # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. # # Note that relative paths are relative to the directory from which doxygen is # run. EXCLUDE = ./include/armnnTestUtils \ ./tests/ # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded # from the input. # The default value is: NO. EXCLUDE_SYMLINKS = NO # If the value of the INPUT tag contains directories, you can use the # EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude # certain files from those directories. # # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories for example use the pattern */test/* EXCLUDE_PATTERNS = *.md EXCLUDE_PATTERNS += */test/* # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, # AClass::ANamespace, ANamespace::*Test # # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories use the pattern */test/* EXCLUDE_SYMBOLS = caffe tensorflow cl armcomputetensorutils # The EXAMPLE_PATH tag can be used to specify one or more files or directories # that contain example code fragments that are included (see the \include # command). EXAMPLE_PATH = ./samples/ # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and # *.h) to filter out the source-files in the directories. If left blank all # files are included. EXAMPLE_PATTERNS = * # If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be # searched for input files to be used with the \include or \dontinclude commands # irrespective of the value of the RECURSIVE tag. # The default value is: NO. EXAMPLE_RECURSIVE = NO # The IMAGE_PATH tag can be used to specify one or more files or directories # that contain images that are to be included in the documentation (see the # \image command). IMAGE_PATH = ./docs/ # The INPUT_FILTER tag can be used to specify a program that doxygen should # invoke to filter for each input file. Doxygen will invoke the filter program # by executing (via popen()) the command: # # # # where is the value of the INPUT_FILTER tag, and is the # name of an input file. Doxygen will then use the output that the filter # program writes to standard output. If FILTER_PATTERNS is specified, this tag # will be ignored. # # Note that the filter must not add or remove lines; it is applied before the # code is scanned, but not when the output code is generated. If lines are added # or removed, the anchors will not be placed correctly. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. INPUT_FILTER = # The FILTER_PATTERNS tag can be used to specify filters on a per file pattern # basis. Doxygen will compare the file name with each pattern and apply the # filter if there is a match. The filters are a list of the form: pattern=filter # (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how # filters are used. If the FILTER_PATTERNS tag is empty or if none of the # patterns match the file name, INPUT_FILTER is applied. # # Note that for custom extensions or not directly supported extensions you also # need to set EXTENSION_MAPPING for the extension otherwise the files are not # properly processed by doxygen. FILTER_PATTERNS = # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will also be used to filter the input files that are used for # producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). # The default value is: NO. FILTER_SOURCE_FILES = NO # The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file # pattern. A pattern will override the setting for FILTER_PATTERN (if any) and # it is also possible to disable source filtering for a specific pattern using # *.ext= (so without naming a filter). # This tag requires that the tag FILTER_SOURCE_FILES is set to YES. FILTER_SOURCE_PATTERNS = # If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that # is part of the input, its contents will be placed on the main page # (index.html). This can be useful if you have a project on for instance GitHub # and want to reuse the introduction page also for the doxygen output. USE_MDFILE_AS_MAINPAGE = ./README.md #--------------------------------------------------------------------------- # Configuration options related to source browsing #--------------------------------------------------------------------------- # If the SOURCE_BROWSER tag is set to YES then a list of source files will be # generated. Documented entities will be cross-referenced with these sources. # # Note: To get rid of all source code in the generated output, make sure that # also VERBATIM_HEADERS is set to NO. # The default value is: NO. SOURCE_BROWSER = YES # Setting the INLINE_SOURCES tag to YES will include the body of functions, # classes and enums directly into the documentation. # The default value is: NO. INLINE_SOURCES = YES # Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any # special comment blocks from generated source code fragments. Normal C, C++ and # Fortran comments will always remain visible. # The default value is: YES. STRIP_CODE_COMMENTS = NO # If the REFERENCED_BY_RELATION tag is set to YES then for each documented # function all documented functions referencing it will be listed. # The default value is: NO. REFERENCED_BY_RELATION = YES # If the REFERENCES_RELATION tag is set to YES then for each documented function # all documented entities called/used by that function will be listed. # The default value is: NO. REFERENCES_RELATION = YES # If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set # to YES then the hyperlinks from functions in REFERENCES_RELATION and # REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will # link to the documentation. # The default value is: YES. REFERENCES_LINK_SOURCE = YES # If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the # source code will show a tooltip with additional information such as prototype, # brief description and links to the definition and documentation. Since this # will make the HTML file larger and loading of large files a bit slower, you # can opt to disable this feature. # The default value is: YES. # This tag requires that the tag SOURCE_BROWSER is set to YES. SOURCE_TOOLTIPS = YES # If the USE_HTAGS tag is set to YES then the references to source code will # point to the HTML generated by the htags(1) tool instead of doxygen built-in # source browser. The htags tool is part of GNU's global source tagging system # (see http://www.gnu.org/software/global/global.html). You will need version # 4.8.6 or higher. # # To use it do the following: # - Install the latest version of global # - Enable SOURCE_BROWSER and USE_HTAGS in the config file # - Make sure the INPUT points to the root of the source tree # - Run doxygen as normal # # Doxygen will invoke htags (and that will in turn invoke gtags), so these # tools must be available from the command line (i.e. in the search path). # # The result: instead of the source browser generated by doxygen, the links to # source code will now point to the output of htags. # The default value is: NO. # This tag requires that the tag SOURCE_BROWSER is set to YES. USE_HTAGS = NO # If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a # verbatim copy of the header file for each class for which an include is # specified. Set to NO to disable this. # See also: Section \class. # The default value is: YES. VERBATIM_HEADERS = YES # If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the # clang parser (see: http://clang.llvm.org/) for more accurate parsing at the # cost of reduced performance. This can be particularly helpful with template # rich C++ code for which doxygen's built-in parser lacks the necessary type # information. # Note: The availability of this option depends on whether or not doxygen was # generated with the -Duse-libclang=ON option for CMake. # The default value is: NO. CLANG_ASSISTED_PARSING = NO # If clang assisted parsing is enabled you can provide the compiler with command # line options that you would normally use when invoking the compiler. Note that # the include paths will already be set by doxygen for the files and directories # specified with INPUT and INCLUDE_PATH. # This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. CLANG_OPTIONS = -std=c++11 #--------------------------------------------------------------------------- # Configuration options related to the alphabetical class index #--------------------------------------------------------------------------- # If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all # compounds will be generated. Enable this if the project contains a lot of # classes, structs, unions or interfaces. # The default value is: YES. ALPHABETICAL_INDEX = YES # The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in # which the alphabetical index list will be split. # Minimum value: 1, maximum value: 20, default value: 5. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. COLS_IN_ALPHA_INDEX = 5 # In case all classes in a project start with a common prefix, all classes will # be put under the same header in the alphabetical index. The IGNORE_PREFIX tag # can be used to specify a prefix (or a list of prefixes) that should be ignored # while generating the index headers. # This tag requires that the tag ALPHABETICAL_INDEX is set to YES. IGNORE_PREFIX = #--------------------------------------------------------------------------- # Configuration options related to the HTML output #--------------------------------------------------------------------------- # If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output # The default value is: YES. GENERATE_HTML = YES # The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a # relative path is entered the value of OUTPUT_DIRECTORY will be put in front of # it. # The default directory is: html. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_OUTPUT = html # The HTML_FILE_EXTENSION tag can be used to specify the file extension for each # generated HTML page (for example: .htm, .php, .asp). # The default value is: .html. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a user-defined HTML header file for # each generated HTML page. If the tag is left blank doxygen will generate a # standard header. # # To get valid HTML the header file that includes any scripts and style sheets # that doxygen needs, which is dependent on the configuration options used (e.g. # the setting GENERATE_TREEVIEW). It is highly recommended to start with a # default header using # doxygen -w html new_header.html new_footer.html new_stylesheet.css # YourConfigFile # and then modify the file new_header.html. See also section "Doxygen usage" # for information on how to generate the default header that doxygen normally # uses. # Note: The header is subject to change so you typically have to regenerate the # default header when upgrading to a newer version of doxygen. For a description # of the possible markers and block names see the documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_HEADER = ./docs/header.html # The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each # generated HTML page. If the tag is left blank doxygen will generate a standard # footer. See HTML_HEADER for more information on how to generate a default # footer and what special commands can be used inside the footer. See also # section "Doxygen usage" for information on how to generate the default footer # that doxygen normally uses. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading style # sheet that is used by each HTML page. It can be used to fine-tune the look of # the HTML output. If left blank doxygen will generate a default style sheet. # See also section "Doxygen usage" for information on how to generate the style # sheet that doxygen normally uses. # Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as # it is more robust and this tag (HTML_STYLESHEET) will in the future become # obsolete. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_STYLESHEET = # The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined # cascading style sheets that are included after the standard style sheets # created by doxygen. Using this option one can overrule certain style aspects. # This is preferred over using HTML_STYLESHEET since it does not replace the # standard style sheet and is therefore more robust against future updates. # Doxygen will copy the style sheet files to the output directory. # Note: The order of the extra style sheet files is of importance (e.g. the last # style sheet in the list overrules the setting of the previous ones in the # list). For an example see the documentation. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_STYLESHEET = ./docs/customdoxygen.css # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or # other source files which should be copied to the HTML output directory. Note # that these files will be copied to the base HTML output directory. Use the # $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these # files. In the HTML_STYLESHEET file, use the file name only. Also note that the # files will be copied as-is; there are no commands or markers available. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_EXTRA_FILES = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen # will adjust the colors in the style sheet and background images according to # this color. Hue is specified as an angle on a colorwheel, see # http://en.wikipedia.org/wiki/Hue for more information. For instance the value # 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 # purple, and 360 is red again. # Minimum value: 0, maximum value: 359, default value: 220. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_HUE = 220 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors # in the HTML output. For a value of 0 the output will use grayscales only. A # value of 255 will produce the most vivid colors. # Minimum value: 0, maximum value: 255, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_SAT = 100 # The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the # luminance component of the colors in the HTML output. Values below 100 # gradually make the output lighter, whereas values above 100 make the output # darker. The value divided by 100 is the actual gamma applied, so 80 represents # a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not # change the gamma. # Minimum value: 40, maximum value: 240, default value: 80. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_COLORSTYLE_GAMMA = 80 # If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML # page will contain the date and time when the page was generated. Setting this # to YES can help to show when doxygen was last run and thus if the # documentation is up to date. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_TIMESTAMP = YES # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the # page has loaded. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_DYNAMIC_SECTIONS = NO # With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries # shown in the various tree structured indices initially; the user can expand # and collapse entries dynamically later on. Doxygen will expand the tree to # such a level that at most the specified number of entries are visible (unless # a fully collapsed tree already exceeds this amount). So setting the number of # entries 1 will produce a full collapsed tree by default. 0 is a special value # representing an infinite number of entries and will result in a full expanded # tree by default. # Minimum value: 0, maximum value: 9999, default value: 100. # This tag requires that the tag GENERATE_HTML is set to YES. HTML_INDEX_NUM_ENTRIES = 100 # If the GENERATE_DOCSET tag is set to YES, additional index files will be # generated that can be used as input for Apple's Xcode 3 integrated development # environment (see: http://developer.apple.com/tools/xcode/), introduced with # OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a # Makefile in the HTML output directory. Running make will produce the docset in # that directory and running make install will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at # startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html # for more information. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_DOCSET = NO # This tag determines the name of the docset feed. A documentation feed provides # an umbrella under which multiple documentation sets from a single provider # (such as a company or product suite) can be grouped. # The default value is: Doxygen generated docs. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_FEEDNAME = "Doxygen generated docs" # This tag specifies a string that should uniquely identify the documentation # set bundle. This should be a reverse domain-name style string, e.g. # com.mycompany.MyDocSet. Doxygen will append .docset to the name. # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_BUNDLE_ID = org.doxygen.Project # The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify # the documentation publisher. This should be a reverse domain-name style # string, e.g. com.mycompany.MyDocSet.documentation. # The default value is: org.doxygen.Publisher. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_PUBLISHER_ID = org.doxygen.Publisher # The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. # The default value is: Publisher. # This tag requires that the tag GENERATE_DOCSET is set to YES. DOCSET_PUBLISHER_NAME = Publisher # If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three # additional HTML index files: index.hhp, index.hhc, and index.hhk. The # index.hhp is a project file that can be read by Microsoft's HTML Help Workshop # (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on # Windows. # # The HTML Help Workshop contains a compiler that can convert all HTML output # generated by doxygen into a single compiled HTML file (.chm). Compiled HTML # files are now used as the Windows 98 help format, and will replace the old # Windows help format (.hlp) on all Windows platforms in the future. Compressed # HTML files also contain an index, a table of contents, and you can search for # words in the documentation. The HTML workshop also contains a viewer for # compressed HTML files. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_HTMLHELP = NO # The CHM_FILE tag can be used to specify the file name of the resulting .chm # file. You can add a path in front of the file if the result should not be # written to the html output directory. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. CHM_FILE = # The HHC_LOCATION tag can be used to specify the location (absolute path # including file name) of the HTML help compiler (hhc.exe). If non-empty, # doxygen will try to run the HTML help compiler on the generated index.hhp. # The file has to be specified with full path. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. HHC_LOCATION = # The GENERATE_CHI flag controls if a separate .chi index file is generated # (YES) or that it should be included in the master .chm file (NO). # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. GENERATE_CHI = NO # The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) # and project file content. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. CHM_INDEX_ENCODING = # The BINARY_TOC flag controls whether a binary table of contents is generated # (YES) or a normal table of contents (NO) in the .chm file. Furthermore it # enables the Previous and Next buttons. # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. BINARY_TOC = NO # The TOC_EXPAND flag can be set to YES to add extra items for group members to # the table of contents of the HTML help documentation and to the tree view. # The default value is: NO. # This tag requires that the tag GENERATE_HTMLHELP is set to YES. TOC_EXPAND = NO # If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and # QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that # can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help # (.qch) of the generated HTML documentation. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_QHP = NO # If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify # the file name of the resulting .qch file. The path specified is relative to # the HTML output folder. # This tag requires that the tag GENERATE_QHP is set to YES. QCH_FILE = # The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help # Project output. For more information please see Qt Help Project / Namespace # (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_QHP is set to YES. QHP_NAMESPACE = org.doxygen.Project # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt # Help Project output. For more information please see Qt Help Project / Virtual # Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- # folders). # The default value is: doc. # This tag requires that the tag GENERATE_QHP is set to YES. QHP_VIRTUAL_FOLDER = doc # If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom # filter to add. For more information please see Qt Help Project / Custom # Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- # filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_NAME = # The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the # custom filter to add. For more information please see Qt Help Project / Custom # Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- # filters). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_CUST_FILTER_ATTRS = # The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this # project's filter section matches. Qt Help Project / Filter Attributes (see: # http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). # This tag requires that the tag GENERATE_QHP is set to YES. QHP_SECT_FILTER_ATTRS = # The QHG_LOCATION tag can be used to specify the location of Qt's # qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the # generated .qhp file. # This tag requires that the tag GENERATE_QHP is set to YES. QHG_LOCATION = # If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be # generated, together with the HTML files, they form an Eclipse help plugin. To # install this plugin and make it available under the help contents menu in # Eclipse, the contents of the directory containing the HTML and XML files needs # to be copied into the plugins directory of eclipse. The name of the directory # within the plugins directory should be the same as the ECLIPSE_DOC_ID value. # After copying Eclipse needs to be restarted before the help appears. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_ECLIPSEHELP = NO # A unique identifier for the Eclipse help plugin. When installing the plugin # the directory name containing the HTML and XML files should also have this # name. Each documentation set should have its own identifier. # The default value is: org.doxygen.Project. # This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. ECLIPSE_DOC_ID = org.doxygen.Project # If you want full control over the layout of the generated HTML pages it might # be necessary to disable the index and replace it with your own. The # DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top # of each HTML page. A value of NO enables the index and the value YES disables # it. Since the tabs in the index contain the same information as the navigation # tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. DISABLE_INDEX = NO # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. If the tag # value is set to YES, a side panel will be generated containing a tree-like # index structure (just like the one that is generated for HTML Help). For this # to work a browser that supports JavaScript, DHTML, CSS and frames is required # (i.e. any modern browser). Windows users are probably better off using the # HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can # further fine-tune the look of the index. As an example, the default style # sheet generated by doxygen has an example that shows how to put an image at # the root of the tree instead of the PROJECT_NAME. Since the tree basically has # the same information as the tab index, you could consider setting # DISABLE_INDEX to YES when enabling this option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. GENERATE_TREEVIEW = YES # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that # doxygen will group on one line in the generated HTML documentation. # # Note that a value of 0 will completely suppress the enum values from appearing # in the overview section. # Minimum value: 0, maximum value: 20, default value: 4. # This tag requires that the tag GENERATE_HTML is set to YES. ENUM_VALUES_PER_LINE = 4 # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used # to set the initial width (in pixels) of the frame in which the tree is shown. # Minimum value: 0, maximum value: 1500, default value: 250. # This tag requires that the tag GENERATE_HTML is set to YES. TREEVIEW_WIDTH = 250 # If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to # external symbols imported via tag files in a separate window. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. EXT_LINKS_IN_WINDOW = NO # Use this tag to change the font size of LaTeX formulas included as images in # the HTML documentation. When you change the font size after a successful # doxygen run you need to manually remove any form_*.png images from the HTML # output directory to force them to be regenerated. # Minimum value: 8, maximum value: 50, default value: 10. # This tag requires that the tag GENERATE_HTML is set to YES. FORMULA_FONTSIZE = 10 # Use the FORMULA_TRANPARENT tag to determine whether or not the images # generated for formulas are transparent PNGs. Transparent PNGs are not # supported properly for IE 6.0, but are supported on all modern browsers. # # Note that when changing this option you need to delete any form_*.png files in # the HTML output directory before the changes have effect. # The default value is: YES. # This tag requires that the tag GENERATE_HTML is set to YES. FORMULA_TRANSPARENT = YES # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see # http://www.mathjax.org) which uses client side Javascript for the rendering # instead of using pre-rendered bitmaps. Use this if you do not have LaTeX # installed or if you want to formulas look prettier in the HTML output. When # enabled you may also need to install MathJax separately and configure the path # to it using the MATHJAX_RELPATH option. # The default value is: NO. # This tag requires that the tag GENERATE_HTML is set to YES. USE_MATHJAX = YES # When MathJax is enabled you can set the default output format to be used for # the MathJax output. See the MathJax site (see: # http://docs.mathjax.org/en/latest/output.html) for more details. # Possible values are: HTML-CSS (which is slower, but has the best # compatibility), NativeMML (i.e. MathML) and SVG. # The default value is: HTML-CSS. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_FORMAT = HTML-CSS # When MathJax is enabled you need to specify the location relative to the HTML # output directory using the MATHJAX_RELPATH option. The destination directory # should contain the MathJax.js script. For instance, if the mathjax directory # is located at the same level as the HTML output directory, then # MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax # Content Delivery Network so you can quickly see the result without installing # MathJax. However, it is strongly recommended to install a local copy of # MathJax from http://www.mathjax.org before deployment. # The default value is: http://cdn.mathjax.org/mathjax/latest. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest # The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax # extension names that should be enabled during MathJax rendering. For example # MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_EXTENSIONS = # The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces # of code that will be used on startup of the MathJax code. See the MathJax site # (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an # example see the documentation. # This tag requires that the tag USE_MATHJAX is set to YES. MATHJAX_CODEFILE = # When the SEARCHENGINE tag is enabled doxygen will generate a search box for # the HTML output. The underlying search engine uses javascript and DHTML and # should work on any modern browser. Note that when using HTML help # (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) # there is already a search function so this one should typically be disabled. # For large projects the javascript based search engine can be slow, then # enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to # search using the keyboard; to jump to the search box use + S # (what the is depends on the OS and browser, but it is typically # , /