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If the Library as you received it specifies that a proxy can decide whether future versions of the GNU Lesser General Public License shall apply, that proxy's public statement of acceptance of any version is permanent authorization for you to choose that version for the Library. amdgpu-sysfs-0.19.3/README.md000064400000000000000000000013551046102023000136230ustar 00000000000000# amdgpu-syfs-rs [![Crates.io](https://img.shields.io/crates/v/amdgpu-sysfs)](https://crates.io/crates/amdgpu-sysfs) [![Docs.rs](https://docs.rs/amdgpu-sysfs/badge.svg)](https://docs.rs/amdgpu-sysfs/) This library allows you to interact with the Linux Kernel SysFS interface for GPUs (mainly targeted at the AMDGPU driver). Basic usage: ```rust,no_run use amdgpu_sysfs::gpu_handle::GpuHandle; # use std::path::PathBuf; let sysfs_path = PathBuf::from("/sys/class/drm/card0/device"); let gpu_handle = GpuHandle::new_from_path(sysfs_path).unwrap(); let gpu_usage = gpu_handle.get_busy_percent().unwrap(); let total_vram = gpu_handle.get_total_vram().unwrap(); ``` See the [documentation](https://docs.rs/amdgpu-sysfs/) for more info. amdgpu-sysfs-0.19.3/src/error/context.rs000064400000000000000000000013571046102023000163200ustar 00000000000000use super::Error; use std::fmt::Display; pub trait ErrorContext { fn context(self, msg: D) -> Result; fn with_context D>(self, f: F) -> Result; } impl ErrorContext for Result where Error: From, { fn context(self, msg: D) -> Result { self.map_err(|err| { let mut err = Error::from(err); err.context = Some(msg.to_string()); err }) } fn with_context D>(self, f: F) -> Result { self.map_err(|err| { let mut err = Error::from(err); err.context = Some(f().to_string()); err }) } } amdgpu-sysfs-0.19.3/src/error/mod.rs000064400000000000000000000062011046102023000154040ustar 00000000000000//! SysFS errors mod context; pub(crate) use context::ErrorContext; use std::{ fmt::Display, num::{ParseFloatError, ParseIntError}, }; #[derive(Debug, PartialEq)] /// An error that can happen when working with the SysFs pub struct Error { context: Option, /// The error kind pub kind: ErrorKind, } /// Possible types of errors #[derive(Debug)] pub enum ErrorKind { /// It is not allowed to perform the given action NotAllowed(String), /// Something is potentially unsupported by this library Unsupported(String), /// The given path is not a valid SysFs InvalidSysFS, /// An error that happens during parsing ParseError { /// What went wrong during parsing msg: String, /// The line where the error occured line: usize, }, /// An IO error IoError(std::io::Error), } impl Error { pub(crate) fn unexpected_eol(expected_item: T, line: usize) -> Self { ErrorKind::ParseError { msg: format!("Unexpected EOL, expected {expected_item}"), line, } .into() } pub(crate) fn basic_parse_error(msg: impl Into) -> Self { ErrorKind::ParseError { msg: msg.into(), line: 1, } .into() } pub(crate) fn not_allowed(msg: String) -> Self { ErrorKind::NotAllowed(msg).into() } /// If the error means that the file doesn't exist pub fn is_not_found(&self) -> bool { matches!(&self.kind, ErrorKind::IoError(io_err) if io_err.kind() == std::io::ErrorKind::NotFound) } } impl Display for Error { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { match &self.kind { ErrorKind::NotAllowed(info) => write!(f, "not allowed: {info}")?, ErrorKind::InvalidSysFS => write!(f, "invalid SysFS")?, ErrorKind::ParseError { msg, line } => write!(f, "parse error: {msg} at line {line}")?, ErrorKind::IoError(error) => write!(f, "io error: {error}")?, ErrorKind::Unsupported(err) => write!(f, "unsupported: {err}")?, } if let Some(ctx) = &self.context { write!(f, "\n{ctx}")?; } Ok(()) } } impl std::error::Error for Error {} impl From for Error { fn from(kind: ErrorKind) -> Self { Self { context: None, kind, } } } impl From for Error { fn from(err: std::io::Error) -> Self { Self { context: None, kind: ErrorKind::IoError(err), } } } impl From for Error { fn from(err: ParseIntError) -> Self { Self::basic_parse_error(err.to_string()) } } impl From for Error { fn from(err: ParseFloatError) -> Self { Self::basic_parse_error(err.to_string()) } } impl PartialEq for ErrorKind { fn eq(&self, other: &Self) -> bool { match (self, other) { (Self::IoError(l0), Self::IoError(r0)) => l0.kind() == r0.kind(), _ => core::mem::discriminant(self) == core::mem::discriminant(other), } } } amdgpu-sysfs-0.19.3/src/gpu_handle/fan_control.rs000064400000000000000000000116611046102023000201140ustar 00000000000000//! Types for working with the dedicated fan control interface. //! Only for Navi 3x (RDNA 3) and newer. Older GPUs have to use the HwMon interface. use crate::{ error::{Error, ErrorKind}, Result, }; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{collections::HashMap, fmt::Write, ops::RangeInclusive}; /// Information about fan characteristics. #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub struct FanInfo { /// Current value pub current: u32, /// Minimum and maximum allowed values. /// This is empty if changes to the value are not supported. pub allowed_range: Option<(u32, u32)>, } /// Custom fan curve #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[derive(Debug, Clone, PartialEq, Eq)] pub struct FanCurve { /// Fan curve points in the (temperature, speed) format /// This is a boxed slice as the number of curve points cannot be modified, only their values can be. pub points: Box<[(i32, u8)]>, /// Allowed value ranges. /// Empty when changes to the fan curve are not supported. pub allowed_ranges: Option, } /// Range of values allowed to be used within fan curve points #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[derive(Debug, Clone, PartialEq, Eq)] pub struct FanCurveRanges { /// Temperature range allowed in curve points pub temperature_range: RangeInclusive, /// Fan speed range allowed in curve points pub speed_range: RangeInclusive, } #[derive(PartialEq, Eq, Debug)] pub(crate) struct FanCtrlContents { pub contents: String, pub od_range: HashMap, } impl FanCtrlContents { pub(crate) fn parse(data: &str, expected_section_name: &str) -> Result { let mut lines = data.lines().enumerate(); let (_, section_line) = lines .next() .ok_or_else(|| Error::unexpected_eol("Section name", 1))?; let section_name = section_line.strip_suffix(':').ok_or_else(|| { Error::basic_parse_error(format!("Section \"{section_line}\" should end with \":\"")) })?; if section_name != expected_section_name { return Err(Error::basic_parse_error(format!( "Found section {section_name}, expected {expected_section_name}" ))); } let mut contents = String::new(); for (_, line) in &mut lines { if line == "OD_RANGE:" { break; } writeln!(contents, "{line}").unwrap(); } contents.pop(); // Remove newline symbol let mut od_range = HashMap::new(); for (i, range_line) in lines { let (name, value) = range_line .split_once(": ") .ok_or_else(|| ErrorKind::ParseError { msg: format!("Range line \"{range_line}\" does not have a separator"), line: i + 1, })?; let (min, max) = value.split_once(' ').ok_or_else(|| ErrorKind::ParseError { msg: format!( "Range line \"{range_line}\" does not have a separator between the values" ), line: i + 1, })?; od_range.insert(name.to_owned(), (min.to_owned(), max.to_owned())); } Ok(Self { contents, od_range }) } } #[cfg(test)] mod tests { use super::FanCtrlContents; use pretty_assertions::assert_eq; #[test] fn parse_od_acoustic_limit() { let data = "\ OD_ACOUSTIC_LIMIT: 2450 OD_RANGE: ACOUSTIC_LIMIT: 500 3100"; let contents = FanCtrlContents::parse(data, "OD_ACOUSTIC_LIMIT").unwrap(); let expected_contents = FanCtrlContents { contents: "2450".to_owned(), od_range: [( "ACOUSTIC_LIMIT".to_owned(), ("500".to_owned(), "3100".to_owned()), )] .into_iter() .collect(), }; assert_eq!(expected_contents, contents); } #[test] fn parse_fan_curve() { let data = "\ OD_FAN_CURVE: 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0% OD_RANGE: FAN_CURVE(hotspot temp): 25C 100C FAN_CURVE(fan speed): 20% 100%"; let contents = FanCtrlContents::parse(data, "OD_FAN_CURVE").unwrap(); let expected_contents = FanCtrlContents { contents: "\ 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0%" .to_owned(), od_range: [ ( "FAN_CURVE(hotspot temp)".to_owned(), ("25C".to_owned(), "100C".to_owned()), ), ( "FAN_CURVE(fan speed)".to_owned(), ("20%".to_owned(), "100%".to_owned()), ), ] .into_iter() .collect(), }; assert_eq!(expected_contents, contents); } } amdgpu-sysfs-0.19.3/src/gpu_handle/mod.rs000064400000000000000000000673341046102023000163770ustar 00000000000000//! Handle on a GPU #[cfg(feature = "overdrive")] pub mod overdrive; #[macro_use] mod power_levels; pub mod fan_control; pub mod power_profile_mode; pub use power_levels::{PowerLevelKind, PowerLevels}; use self::fan_control::{FanCurve, FanCurveRanges, FanInfo}; use crate::{ error::{Error, ErrorContext, ErrorKind}, gpu_handle::fan_control::FanCtrlContents, hw_mon::HwMon, sysfs::SysFS, Result, }; use power_profile_mode::PowerProfileModesTable; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{ collections::HashMap, fmt::{self, Display, Write as _}, fs, io::Write, path::{Path, PathBuf}, str::FromStr, }; #[cfg(feature = "overdrive")] use { self::overdrive::{ClocksTable, ClocksTableGen}, std::fs::File, }; /// A `GpuHandle` represents a handle over a single GPU device, as exposed in the Linux SysFS. #[derive(Clone, Debug)] pub struct GpuHandle { sysfs_path: PathBuf, /// A collection of all [HwMon](../hw_mon/struct.HwMon.html)s bound to this GPU. They are used to expose real-time data. pub hw_monitors: Vec, uevent: HashMap, } impl GpuHandle { /// Initializes a new `GpuHandle` from a given SysFS device path. /// /// Normally, the path should look akin to `/sys/class/drm/card0/device`, /// and it needs to at least contain a `uevent` file. pub fn new_from_path(sysfs_path: PathBuf) -> Result { let mut hw_monitors = Vec::new(); if let Ok(hw_mons_iter) = fs::read_dir(sysfs_path.join("hwmon")) { for hw_mon_dir in hw_mons_iter.flatten() { if let Ok(hw_mon) = HwMon::new_from_path(hw_mon_dir.path()) { hw_monitors.push(hw_mon); } } } let uevent_raw = fs::read_to_string(sysfs_path.join("uevent"))?.replace(char::from(0), ""); let mut uevent = HashMap::new(); for (i, line) in uevent_raw.trim().lines().enumerate() { let (key, value) = line .split_once('=') .ok_or_else(|| Error::unexpected_eol("=", i))?; uevent.insert(key.to_owned(), value.to_owned()); } match uevent.get("DRIVER") { Some(_) => Ok(Self { sysfs_path, hw_monitors, uevent, }), None => Err(ErrorKind::InvalidSysFS.into()), } } /// Gets the kernel driver used. pub fn get_driver(&self) -> &str { self.uevent.get("DRIVER").unwrap() } /// Gets the **GPU's** PCI vendor and ID. This is the ID of your GPU chip, e.g. AMD Radeon RX 580. pub fn get_pci_id(&self) -> Option<(&str, &str)> { match self.uevent.get("PCI_ID") { Some(pci_str) => pci_str.split_once(':'), None => None, } } /// Gets the **Card's** PCI vendor and ID. This is the ID of your card model, e.g. Sapphire RX 580 Pulse. pub fn get_pci_subsys_id(&self) -> Option<(&str, &str)> { match self.uevent.get("PCI_SUBSYS_ID") { Some(pci_str) => pci_str.split_once(':'), None => None, } } /// Gets the pci slot name of the card. pub fn get_pci_slot_name(&self) -> Option<&str> { self.uevent.get("PCI_SLOT_NAME").map(|s| s.as_str()) } fn get_link(&self, file_name: &str) -> Result { // Despite being labled NAVI10, newer generations use the same port device ids const NAVI10_UPSTREAM_PORT: &str = "0x1478\n"; const NAVI10_DOWNSTREAM_PORT: &str = "0x1479\n"; let mut sysfs_path = std::fs::canonicalize(self.get_path())?.join("../"); // pcie port for _ in 0..2 { let Ok(did) = std::fs::read_to_string(sysfs_path.join("device")) else { break; }; if did == NAVI10_UPSTREAM_PORT || did == NAVI10_DOWNSTREAM_PORT { sysfs_path.push("../"); } else { break; } } sysfs_path.pop(); Self { sysfs_path, hw_monitors: Vec::new(), uevent: HashMap::new(), } .read_file(file_name) } /// Gets the current PCIe link speed. pub fn get_current_link_speed(&self) -> Result { self.get_link("current_link_speed") } /// Gets the current PCIe link width. pub fn get_current_link_width(&self) -> Result { self.get_link("current_link_width") } /// Gets the maximum possible PCIe link speed. pub fn get_max_link_speed(&self) -> Result { self.get_link("max_link_speed") } /// Gets the maximum possible PCIe link width. pub fn get_max_link_width(&self) -> Result { self.get_link("max_link_width") } fn read_vram_file(&self, file: &str) -> Result { let raw_vram = self.read_file(file)?; Ok(raw_vram.parse()?) } /// Gets total VRAM size in bytes. May not be reported on some devices, such as integrated GPUs. pub fn get_total_vram(&self) -> Result { self.read_vram_file("mem_info_vram_total") } /// Gets how much VRAM is currently used, in bytes. May not be reported on some devices, such as integrated GPUs. pub fn get_used_vram(&self) -> Result { self.read_vram_file("mem_info_vram_used") } /// Returns the GPU busy percentage. pub fn get_busy_percent(&self) -> Result { let raw_busy = self.read_file("gpu_busy_percent")?; Ok(raw_busy.parse()?) } /// Returns the GPU VBIOS version. pub fn get_vbios_version(&self) -> Result { self.read_file("vbios_version") } /// Returns the VRAM vendor pub fn get_vram_vendor(&self) -> Result { self.read_file("mem_info_vram_vendor") } /// Returns the currently forced performance level. pub fn get_power_force_performance_level(&self) -> Result { let raw_level = self.read_file("power_dpm_force_performance_level")?; PerformanceLevel::from_str(&raw_level) } /// Forces a given performance level. pub fn set_power_force_performance_level(&self, level: PerformanceLevel) -> Result<()> { self.write_file("power_dpm_force_performance_level", level.to_string()) } /// Retuns the list of power levels and index of the currently active level for a given kind of power state. /// `T` is the type that values should be deserialized into. pub fn get_clock_levels(&self, kind: PowerLevelKind) -> Result> where T: FromStr, ::Err: Display, { self.read_file(kind.filename()).and_then(|content| { let mut levels = Vec::new(); let mut active = None; let mut invalid_active = false; for mut line in content.trim().split('\n') { if let Some(stripped) = line.strip_suffix('*') { line = stripped; if let Some(identifier) = stripped.split(':').next() { if !invalid_active { if active.is_some() { active = None; invalid_active = true; } else { let idx = identifier .trim() .parse() .context("Unexpected power level identifier")?; active = Some(idx); } } } } if let Some(s) = line.split(':').next_back() { let parse_result = if let Some(suffix) = kind.value_suffix() { let raw_value = s.trim().to_lowercase(); let value = raw_value.strip_suffix(suffix).ok_or_else(|| { ErrorKind::ParseError { msg: format!("Level did not have the expected suffix {suffix}"), line: levels.len() + 1, } })?; T::from_str(value) } else { let value = s.trim(); T::from_str(value) }; let parsed_value = parse_result.map_err(|err| ErrorKind::ParseError { msg: format!("Could not deserialize power level value: {err}"), line: levels.len() + 1, })?; levels.push(parsed_value); } } Ok(PowerLevels { levels, active }) }) } impl_get_clocks_levels!(get_core_clock_levels, PowerLevelKind::CoreClock, u64); impl_get_clocks_levels!(get_memory_clock_levels, PowerLevelKind::MemoryClock, u64); impl_get_clocks_levels!(get_pcie_clock_levels, PowerLevelKind::PcieSpeed, String); /// Sets the enabled power levels for a power state kind to a given list of levels. This means that only the given power levels will be allowed. /// /// Can only be used if `power_force_performance_level` is set to `manual`. pub fn set_enabled_power_levels(&self, kind: PowerLevelKind, levels: &[u8]) -> Result<()> { match self.get_power_force_performance_level()? { PerformanceLevel::Manual => { let mut s = String::new(); for l in levels { s.push(char::from_digit((*l).into(), 10).unwrap()); s.push(' '); } Ok(self.write_file(kind.filename(), s)?) } _ => Err(ErrorKind::NotAllowed( "power_force_performance level needs to be set to 'manual' to adjust power levels" .to_string(), ) .into()), } } /// Reads the clocks table from `pp_od_clk_voltage`. #[cfg(feature = "overdrive")] pub fn get_clocks_table(&self) -> Result { self.read_file_parsed("pp_od_clk_voltage") } /// Writes and commits the given clocks table to `pp_od_clk_voltage`. #[cfg(feature = "overdrive")] pub fn set_clocks_table(&self, new_table: &ClocksTableGen) -> Result { let old_table = self.get_clocks_table()?; let path = self.sysfs_path.join("pp_od_clk_voltage"); let mut file = File::create(&path)?; new_table.write_commands(&mut file, &old_table)?; Ok(CommitHandle::new(path)) } /// Resets the clocks table to the default configuration. #[cfg(feature = "overdrive")] pub fn reset_clocks_table(&self) -> Result<()> { let path = self.sysfs_path.join("pp_od_clk_voltage"); let mut file = File::create(path)?; file.write_all(b"r\n")?; Ok(()) } /// Reads the list of predefined power profiles and the relevant heuristics settings for them from `pp_power_profile_mode` /// /// https://kernel.org/doc/html/latest/gpu/amdgpu/thermal.html#pp-power-profile-mode pub fn get_power_profile_modes(&self) -> Result { let contents = self.read_file("pp_power_profile_mode")?; PowerProfileModesTable::parse(&contents) } /// Sets the current power profile mode. You can get the available modes with [`get_power_profile_modes`]. /// Requires the performance level to be set to "manual" first using [`set_power_force_performance_level`] pub fn set_active_power_profile_mode(&self, i: u16) -> Result<()> { self.write_file("pp_power_profile_mode", format!("{i}\n")) } /// Sets a custom power profile mode. You can get the available modes, and the list of heuristic names with [`get_power_profile_modes`]. /// Requires the performance level to be set to "manual" first using [`set_power_force_performance_level`] pub fn set_custom_power_profile_mode_heuristics( &self, components: &[Vec>], ) -> Result<()> { let table = self.get_power_profile_modes()?; let (index, current_custom_profile) = table .modes .iter() .find(|(_, profile)| profile.is_custom()) .ok_or_else(|| { ErrorKind::NotAllowed("Could not find a custom power profile".to_owned()) })?; if current_custom_profile.components.len() != components.len() { return Err(ErrorKind::NotAllowed(format!( "Expected {} power profile components, got {}", current_custom_profile.components.len(), components.len() )) .into()); } if current_custom_profile.components.len() == 1 { let mut values_command = format!("{index}"); for heuristic in &components[0] { match heuristic { Some(value) => write!(values_command, " {value}").unwrap(), None => write!(values_command, " -").unwrap(), } } values_command.push('\n'); self.write_file("pp_power_profile_mode", values_command) } else { for (component_index, heuristics) in components.iter().enumerate() { let mut values_command = format!("{index} {component_index}"); for heuristic in heuristics { match heuristic { Some(value) => write!(values_command, " {value}").unwrap(), None => write!(values_command, " -").unwrap(), } } values_command.push('\n'); self.write_file("pp_power_profile_mode", values_command)?; } Ok(()) } } fn read_fan_info(&self, file: &str, section_name: &str, range_name: &str) -> Result { let file_path = Path::new("gpu_od/fan_ctrl").join(file); let data = self.read_file(file_path)?; let contents = FanCtrlContents::parse(&data, section_name)?; let current = contents.contents.parse()?; let allowed_range = match contents.od_range.get(range_name) { Some((raw_min, raw_max)) => { let min = raw_min.parse()?; let max = raw_max.parse()?; Some((min, max)) } None => None, }; Ok(FanInfo { current, allowed_range, }) } /// Gets the fan acoustic limit. Values are in RPM. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn get_fan_acoustic_limit(&self) -> Result { self.read_fan_info( "acoustic_limit_rpm_threshold", "OD_ACOUSTIC_LIMIT", "ACOUSTIC_LIMIT", ) } /// Gets the fan acoustic target. Values are in RPM. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn get_fan_acoustic_target(&self) -> Result { self.read_fan_info( "acoustic_target_rpm_threshold", "OD_ACOUSTIC_TARGET", "ACOUSTIC_TARGET", ) } /// Gets the fan temperature target. Values are in degrees. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn get_fan_target_temperature(&self) -> Result { self.read_fan_info( "fan_target_temperature", "FAN_TARGET_TEMPERATURE", "TARGET_TEMPERATURE", ) } /// Gets the fan minimum PWM. Values are in percentages. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn get_fan_minimum_pwm(&self) -> Result { self.read_fan_info("fan_minimum_pwm", "FAN_MINIMUM_PWM", "MINIMUM_PWM") } /// Gets the current fan zero RPM mode. /// /// Only available on Navi3x (RDNA 3) or newer. pub fn get_fan_zero_rpm_enable(&self) -> Result { self.read_fan_info( "fan_zero_rpm_enable", "FAN_ZERO_RPM_ENABLE", "ZERO_RPM_ENABLE", ) .map(|info| info.current == 1) } /// Gets the current fan zero RPM stop temperature. /// /// Only available on Navi3x (RDNA 3) or newer. pub fn get_fan_zero_rpm_stop_temperature(&self) -> Result { self.read_fan_info( "fan_zero_rpm_stop_temperature", "FAN_ZERO_RPM_STOP_TEMPERATURE", "ZERO_RPM_STOP_TEMPERATURE", ) } fn set_fan_value( &self, file: &str, value: u32, section_name: &str, range_name: &str, ) -> Result { let info = self.read_fan_info(file, section_name, range_name)?; match info.allowed_range { Some((min, max)) => { if !(min..=max).contains(&value) { return Err(Error::not_allowed(format!( "Value {value} is out of range, should be between {min} and {max}" ))); } let file_path = self.sysfs_path.join("gpu_od/fan_ctrl").join(file); std::fs::write(&file_path, format!("{value}\n"))?; Ok(CommitHandle::new(file_path)) } None => Err(Error::not_allowed(format!( "Changes to {range_name} are not allowed" ))), } } /// Sets the fan acoustic limit. Value is in RPM. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn set_fan_acoustic_limit(&self, value: u32) -> Result { self.set_fan_value( "acoustic_limit_rpm_threshold", value, "OD_ACOUSTIC_LIMIT", "ACOUSTIC_LIMIT", ) } /// Sets the fan acoustic target. Value is in RPM. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn set_fan_acoustic_target(&self, value: u32) -> Result { self.set_fan_value( "acoustic_target_rpm_threshold", value, "OD_ACOUSTIC_TARGET", "ACOUSTIC_TARGET", ) } /// Sets the fan temperature target. Value is in degrees. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn set_fan_target_temperature(&self, value: u32) -> Result { self.set_fan_value( "fan_target_temperature", value, "FAN_TARGET_TEMPERATURE", "TARGET_TEMPERATURE", ) } /// Sets the fan minimum PWM. Value is a percentage. /// /// Only available on Navi3x (RDNA 3) or newer. pub fn set_fan_minimum_pwm(&self, value: u32) -> Result { self.set_fan_value("fan_minimum_pwm", value, "FAN_MINIMUM_PWM", "MINIMUM_PWM") } /// Sets the current fan zero RPM mode. /// /// Only available on Navi3x (RDNA 3) or newer. pub fn set_fan_zero_rpm_enable(&self, enabled: bool) -> Result { self.set_fan_value( "fan_zero_rpm_enable", enabled as u32, "FAN_ZERO_RPM_ENABLE", "ZERO_RPM_ENABLE", ) } /// Sets the fan zero RPM stop temperature. /// /// Only available on Navi3x (RDNA 3) or newer. pub fn set_fan_zero_rpm_stop_temperature(&self, value: u32) -> Result { self.set_fan_value( "fan_zero_rpm_stop_temperature", value, "FAN_ZERO_RPM_STOP_TEMPERATURE", "ZERO_RPM_STOP_TEMPERATURE", ) } fn reset_fan_value(&self, file: &str) -> Result<()> { let file_path = self.sysfs_path.join("gpu_od/fan_ctrl").join(file); let mut file = File::create(file_path)?; writeln!(file, "r")?; Ok(()) } /// Resets the fan acoustic limit. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn reset_fan_acoustic_limit(&self) -> Result<()> { self.reset_fan_value("acoustic_limit_rpm_threshold") } /// Resets the fan acoustic target. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn reset_fan_acoustic_target(&self) -> Result<()> { self.reset_fan_value("acoustic_target_rpm_threshold") } /// Resets the fan target temperature. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn reset_fan_target_temperature(&self) -> Result<()> { self.reset_fan_value("fan_target_temperature") } /// Resets the fan minimum pwm. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn reset_fan_minimum_pwm(&self) -> Result<()> { self.reset_fan_value("fan_minimum_pwm") } /// Gets the PMFW (power management firmware) fan curve. /// Note: if no custom curve is used, all of the curve points may be set to 0. /// /// Only available on Navi3x (RDNA 3) or newer. /// Older GPUs do not have a configurable fan curve in firmware, they need custom logic. pub fn get_fan_curve(&self) -> Result { let data = self.read_file("gpu_od/fan_ctrl/fan_curve")?; let contents = FanCtrlContents::parse(&data, "OD_FAN_CURVE")?; let points = contents .contents .lines() .enumerate() .map(|(i, line)| { let mut split = line.split(' '); split.next(); // Discard index let raw_temp = split .next() .ok_or_else(|| Error::unexpected_eol("Temperature value", i))?; let temp = raw_temp.trim_end_matches('C').parse()?; let raw_speed = split .next() .ok_or_else(|| Error::unexpected_eol("Speed value", i))?; let speed = raw_speed.trim_end_matches('%').parse()?; Ok((temp, speed)) }) .collect::>()?; let temp_range = contents.od_range.get("FAN_CURVE(hotspot temp)"); let speed_range = contents.od_range.get("FAN_CURVE(fan speed)"); let allowed_ranges = if let Some(((min_temp, max_temp), (min_speed, max_speed))) = (temp_range).zip(speed_range) { let min_temp: i32 = min_temp.trim_end_matches('C').parse()?; let max_temp: i32 = max_temp.trim_end_matches('C').parse()?; let min_speed: u8 = min_speed.trim_end_matches('%').parse()?; let max_speed: u8 = max_speed.trim_end_matches('%').parse()?; Some(FanCurveRanges { temperature_range: min_temp..=max_temp, speed_range: min_speed..=max_speed, }) } else { None }; Ok(FanCurve { points, allowed_ranges, }) } /// Sets and applies the PMFW fan curve. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn set_fan_curve(&self, new_curve: &FanCurve) -> Result { let current_curve = self.get_fan_curve()?; let allowed_ranges = current_curve.allowed_ranges.ok_or_else(|| { Error::not_allowed("Changes to the fan curve are not supported".to_owned()) })?; let file_path = self.sysfs_path.join("gpu_od/fan_ctrl/fan_curve"); for (i, (temperature, speed)) in new_curve.points.iter().enumerate() { if !allowed_ranges.temperature_range.contains(temperature) { Err(Error::not_allowed(format!( "Temperature value {temperature} is outside of the allowed range {:?}", allowed_ranges.temperature_range )))?; } if !allowed_ranges.speed_range.contains(speed) { Err(Error::not_allowed(format!( "Speed value {speed} is outside of the allowed range {:?}", allowed_ranges.speed_range )))?; } std::fs::write(&file_path, format!("{i} {temperature} {speed}\n"))?; } Ok(CommitHandle::new(file_path)) } /// Resets the PMFW fan curve. /// /// Only available on Navi3x (RDNA 3) or newer. /// pub fn reset_fan_curve(&self) -> Result<()> { self.reset_fan_value("fan_curve") } } impl SysFS for GpuHandle { fn get_path(&self) -> &std::path::Path { &self.sysfs_path } } /// Performance level to be used by the GPU. /// /// #[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[cfg_attr(feature = "serde", serde(rename_all = "lowercase"))] pub enum PerformanceLevel { /// When auto is selected, the driver will attempt to dynamically select the optimal power profile for current conditions in the driver. #[default] Auto, /// When low is selected, the clocks are forced to the lowest power state. Low, /// When high is selected, the clocks are forced to the highest power state. High, /// When manual is selected, power states can be manually adjusted via `pp_dpm_*` files ([`GpuHandle::set_enabled_power_levels`]) and `pp_od_clk_voltage` ([`GpuHandle::set_clocks_table`]). Manual, } impl FromStr for PerformanceLevel { type Err = Error; fn from_str(s: &str) -> Result { match s { "auto" | "Automatic" => Ok(PerformanceLevel::Auto), "high" | "Highest Clocks" => Ok(PerformanceLevel::High), "low" | "Lowest Clocks" => Ok(PerformanceLevel::Low), "manual" | "Manual" => Ok(PerformanceLevel::Manual), _ => Err(ErrorKind::ParseError { msg: "unrecognized GPU power profile".to_string(), line: 1, } .into()), } } } impl fmt::Display for PerformanceLevel { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { write!( f, "{}", match self { PerformanceLevel::Auto => "auto", PerformanceLevel::High => "high", PerformanceLevel::Low => "low", PerformanceLevel::Manual => "manual", } ) } } /// For some reason files sometimes have random null bytes around lines fn trim_sysfs_line(line: &str) -> &str { line.trim_matches(char::from(0)).trim() } /// Handle for committing values which were previusly written #[must_use] #[derive(Debug)] pub struct CommitHandle { file_path: PathBuf, } impl CommitHandle { pub(crate) fn new(file_path: PathBuf) -> Self { Self { file_path } } /// Commit the previously written values pub fn commit(self) -> Result<()> { std::fs::write(&self.file_path, "c\n").with_context(|| { format!( "Could not commit values to {:?}", self.file_path.file_name().unwrap() ) }) } } amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/gcn.rs000064400000000000000000000317011046102023000203610ustar 00000000000000//! The format used by Vega10 and older GPUs. use super::{parse_range_line, push_level_line, ClocksLevel, ClocksTable, ClocksTableGen, Range}; use crate::{ error::{Error, ErrorKind::ParseError}, Result, }; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{cmp, io::Write, str::FromStr}; /// Vega10 clocks table. #[derive(Debug, Clone)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct Table { /// List of core clock levels. pub sclk_levels: Vec, /// List of memory clock levels. pub mclk_levels: Vec, /// The allowed ranges for clockspeeds and voltages. pub od_range: OdRange, } impl ClocksTable for Table { fn write_commands( &self, writer: &mut W, _previous_table: &ClocksTableGen, ) -> Result<()> { for (i, level) in self.sclk_levels.iter().enumerate() { let command = level_command(*level, i, 's'); writer.write_all(command.as_bytes())?; } for (i, level) in self.mclk_levels.iter().enumerate() { let command = level_command(*level, i, 'm'); writer.write_all(command.as_bytes())?; } Ok(()) } fn get_max_sclk_range(&self) -> Option { Some(self.od_range.sclk) } fn get_min_sclk_range(&self) -> Option { Some(self.od_range.sclk) } fn get_max_mclk_range(&self) -> Option { self.od_range.mclk } fn get_min_mclk_range(&self) -> Option { self.od_range.mclk } fn get_max_voltage_range(&self) -> Option { self.od_range.vddc } fn get_min_voltage_range(&self) -> Option { self.od_range.vddc } fn get_current_voltage_range(&self) -> Option { let min = self.sclk_levels.first().map(|level| level.voltage); let max = self.sclk_levels.last().map(|level| level.voltage); Some(Range { min, max }) } fn get_current_sclk_range(&self) -> Range { let min = self.sclk_levels.first().map(|level| level.clockspeed); let max = self.sclk_levels.last().map(|level| level.clockspeed); Range { min, max } } fn get_current_mclk_range(&self) -> Range { let min = self.mclk_levels.first().map(|level| level.clockspeed); let max = self.mclk_levels.last().map(|level| level.clockspeed); Range { min, max } } fn set_max_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { let len = self.sclk_levels.len(); if len == 0 { return Ok(()); } self.sclk_levels[len - 1].clockspeed = clockspeed; for clock_level in &mut self.sclk_levels[0..len - 1] { clock_level.clockspeed = cmp::min(clock_level.clockspeed, clockspeed); } Ok(()) } fn set_min_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { let len = self.sclk_levels.len(); if len == 0 { return Ok(()); } self.sclk_levels[0].clockspeed = clockspeed; for clock_level in &mut self.sclk_levels[1..len] { clock_level.clockspeed = cmp::max(clock_level.clockspeed, clockspeed); } Ok(()) } fn set_max_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { let len = self.mclk_levels.len(); if len == 0 { return Ok(()); } self.mclk_levels[len - 1].clockspeed = clockspeed; for clock_level in &mut self.mclk_levels[0..len - 1] { clock_level.clockspeed = cmp::min(clock_level.clockspeed, clockspeed); } Ok(()) } fn set_min_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { let len = self.mclk_levels.len(); if len == 0 { return Ok(()); } self.mclk_levels[0].clockspeed = clockspeed; for clock_level in &mut self.mclk_levels[1..len] { clock_level.clockspeed = cmp::max(clock_level.clockspeed, clockspeed); } Ok(()) } fn set_max_voltage_unchecked(&mut self, voltage: i32) -> Result<()> { let len = self.sclk_levels.len(); if len == 0 { return Ok(()); } self.sclk_levels[len - 1].voltage = voltage; for clock_level in &mut self.sclk_levels[0..len - 1] { clock_level.voltage = cmp::min(clock_level.voltage, voltage); } Ok(()) } fn set_min_voltage_unchecked(&mut self, voltage: i32) -> Result<()> { let len = self.sclk_levels.len(); if len == 0 { return Ok(()); } self.sclk_levels[0].voltage = voltage; for clock_level in &mut self.sclk_levels[1..len - 1] { clock_level.voltage = cmp::max(clock_level.voltage, voltage); } Ok(()) } fn get_max_sclk_voltage(&self) -> Option { self.sclk_levels.last().map(|level| level.voltage) } } /// The ranges for overclocking values which the GPU allows to be used. #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct OdRange { /// Clocks range for sclk (in MHz). Should be present on all GPUs. pub sclk: Range, /// Clocks range for mclk (in MHz). Present on discrete GPUs only. pub mclk: Option, /// Voltage range (in mV). Present on Vega10 and older GPUs only. pub vddc: Option, } impl FromStr for Table { type Err = Error; fn from_str(s: &str) -> Result { let mut sclk_levels = Vec::with_capacity(7); let mut mclk_levels = Vec::with_capacity(2); let mut sclk_range = None; let mut mclk_range = None; let mut vddc_range = None; let mut current_section = None; let mut i = 1; for line in s.lines().map(str::trim).filter(|line| !line.is_empty()) { match line { "OD_SCLK:" => current_section = Some(Section::Sclk), "OD_MCLK:" => current_section = Some(Section::Mclk), "OD_RANGE:" => current_section = Some(Section::Range), line => match current_section { Some(Section::Sclk) => { push_level_line(line, &mut sclk_levels, i)?; } Some(Section::Mclk) => { push_level_line(line, &mut mclk_levels, i)?; } Some(Section::Range) => { let (range, name) = parse_range_line(line, i)?; match name { "SCLK" => sclk_range = Some(range), "MCLK" => mclk_range = Some(range), "VDDC" => vddc_range = Some(range), other => { return Err(ParseError { msg: format!("Unexpected range item: {other}"), line: i, } .into()) } } } None => { return Err(ParseError { msg: "Could not find section".to_owned(), line: i, } .into()) } }, } i += 1; } sclk_levels.shrink_to_fit(); mclk_levels.shrink_to_fit(); let od_range = OdRange { sclk: sclk_range.ok_or_else(|| ParseError { msg: "No sclk range found".to_owned(), line: i, })?, mclk: mclk_range, vddc: vddc_range, }; Ok(Self { sclk_levels, mclk_levels, od_range, }) } } fn level_command(level: ClocksLevel, i: usize, symbol: char) -> String { let ClocksLevel { clockspeed, voltage, } = level; format!("{symbol} {i} {clockspeed} {voltage}\n") } #[derive(PartialEq)] enum Section { Sclk, Mclk, Range, } #[cfg(test)] mod tests { use super::{ClocksLevel, Table}; use crate::{ gpu_handle::overdrive::{arr_commands, gcn::OdRange, ClocksTable, Range}, include_table, }; use pretty_assertions::assert_eq; use std::str::FromStr; const TABLE_RX580: &str = include_table!("rx580"); #[test] fn parse_full_table() { let table = Table::from_str(TABLE_RX580).unwrap(); let sclk_levels = [ (300, 750), (600, 769), (900, 912), (1145, 1125), (1215, 1150), (1257, 1150), (1300, 1150), (1366, 1150), ] .map(|(clockspeed, voltage)| ClocksLevel { clockspeed, voltage, }); let mclk_levels = [(300, 750), (1000, 825), (1750, 975)].map(|(clockspeed, voltage)| ClocksLevel { clockspeed, voltage, }); let ranges = OdRange { sclk: Range::full(300, 2000), mclk: Some(Range::full(300, 2250)), vddc: Some(Range::full(750, 1200)), }; assert_eq!(table.sclk_levels, sclk_levels); assert_eq!(table.mclk_levels, mclk_levels); assert_eq!(table.od_range, ranges); } #[test] fn table_into_commands() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_max_sclk(1500).unwrap(); table.set_max_mclk(2250).unwrap(); table.set_min_sclk(350).unwrap(); table.set_min_mclk(360).unwrap(); table.set_min_voltage(800).unwrap(); table.set_max_voltage(1200).unwrap(); let mut buf = Vec::new(); table .write_commands(&mut buf, &table.clone().into()) .unwrap(); let commands = String::from_utf8(buf).unwrap(); let expected_commands = arr_commands([ "s 0 350 800", "s 1 600 800", "s 2 900 912", "s 3 1145 1125", "s 4 1215 1150", "s 5 1257 1150", "s 6 1300 1150", "s 7 1500 1200", "m 0 360 750", "m 1 1000 825", "m 2 2250 975", ]); assert_eq!(expected_commands, commands); } #[test] fn generic_actions() { let mut table = Table::from_str(TABLE_RX580).unwrap(); let sclk = table.get_max_sclk().unwrap(); assert_eq!(sclk, 1366); let mclk = table.get_max_mclk().unwrap(); assert_eq!(mclk, 1750); let voltage = table.get_max_sclk_voltage().unwrap(); assert_eq!(voltage, 1150); table.set_max_sclk(1400).unwrap(); let sclk = table.get_max_sclk().unwrap(); assert_eq!(sclk, 1400); assert_eq!(table.sclk_levels[7].clockspeed, 1400); table.set_max_mclk(1800).unwrap(); let mclk = table.get_max_mclk().unwrap(); assert_eq!(mclk, 1800); assert_eq!(table.mclk_levels[2].clockspeed, 1800); let sclk_range = table.get_max_sclk_range(); let mclk_range = table.get_max_mclk_range(); let voltage_range = table.get_max_voltage_range(); assert_eq!(sclk_range, Some(Range::full(300, 2000))); assert_eq!(mclk_range, Some(Range::full(300, 2250))); assert_eq!(voltage_range, Some(Range::full(750, 1200))); } #[test] fn undervolt_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_max_voltage(1100).unwrap(); assert!(table.sclk_levels.iter().all(|level| level.voltage <= 1100)); } #[test] fn underclock_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_max_sclk(1200).unwrap(); assert!(table .sclk_levels .iter() .all(|level| level.clockspeed <= 1200)); } #[test] fn underclock_memory_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_max_mclk(900).unwrap(); assert!(table .mclk_levels .iter() .all(|level| level.clockspeed <= 900)); } #[test] fn min_voltage_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_min_voltage(800).unwrap(); assert!(table.sclk_levels.iter().all(|level| level.voltage >= 800)); } #[test] fn min_clockspeed_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_min_sclk(750).unwrap(); assert!(table .sclk_levels .iter() .all(|level| level.clockspeed >= 750)); } #[test] fn min_memory_clockspeed_normalize() { let mut table = Table::from_str(TABLE_RX580).unwrap(); table.set_min_mclk(1100).unwrap(); assert!(table .mclk_levels .iter() .all(|level| level.clockspeed >= 1100)); } } amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/mod.rs000064400000000000000000000322711046102023000203740ustar 00000000000000//! GPU overdrive (overclocking) //! //! pub mod gcn; pub mod rdna; use crate::{ error::{Error, ErrorKind}, Result, }; use enum_dispatch::enum_dispatch; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{ convert::TryFrom, io::Write, str::{FromStr, SplitWhitespace}, }; /// Shared functionality across all table formats. #[enum_dispatch] pub trait ClocksTable: FromStr { /// Writes commands needed to apply the state that is in the table struct on the GPU. fn write_commands( &self, writer: &mut W, previous_table: &ClocksTableGen, ) -> Result<()>; /// Gets the list of commands that will apply the current state of the clocks table. /// `write_commands` should generally be preferred instead. fn get_commands(&self, previous_table: &ClocksTableGen) -> Result> { let mut buf = Vec::new(); self.write_commands(&mut buf, previous_table)?; let raw_commands = String::from_utf8(buf).map_err(|_| { ErrorKind::Unsupported("Generated clocks table commands are not valid UTF-8".into()) })?; Ok(raw_commands.lines().map(str::to_owned).collect()) } /// Gets the core clock range usable at the highest power level. fn get_max_sclk_range(&self) -> Option; /// Gets the core clock range usable at the lowest power level. fn get_min_sclk_range(&self) -> Option; /// Gets the memory clock range usable at the highest power level. fn get_max_mclk_range(&self) -> Option; /// Gets the memory clock range usable at the lowest power level. fn get_min_mclk_range(&self) -> Option; /// Gets the voltage range usable at the highest power level. fn get_max_voltage_range(&self) -> Option; /// Gets the voltage range usable at the lowest power level. fn get_min_voltage_range(&self) -> Option; /// Gets the current voltage range. fn get_current_voltage_range(&self) -> Option; /// Gets the current maximum core clock. fn get_max_sclk(&self) -> Option { self.get_current_sclk_range().max } /// Gets the current range of values for core clocks. fn get_current_sclk_range(&self) -> Range; /// Gets the current range of values for memory clocks. fn get_current_mclk_range(&self) -> Range; /// Sets the maximum core clock. fn set_max_sclk(&mut self, clockspeed: i32) -> Result<()> { let range = self.get_max_sclk_range(); check_clockspeed_in_range(range, clockspeed)?; self.set_max_sclk_unchecked(clockspeed) } /// Sets the maximum core clock (without checking if it's in the allowed range). fn set_max_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()>; /// Sets the minimum core clock. fn set_min_sclk(&mut self, clockspeed: i32) -> Result<()> { let range = self.get_min_sclk_range(); check_clockspeed_in_range(range, clockspeed)?; self.set_min_sclk_unchecked(clockspeed) } /// Sets the minimum core clock (without checking if it's in the allowed range). fn set_min_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()>; /// Gets the current maximum memory clock. fn get_max_mclk(&self) -> Option { self.get_current_mclk_range().max } /// Sets the maximum memory clock. fn set_max_mclk(&mut self, clockspeed: i32) -> Result<()> { let range = self.get_max_mclk_range(); check_clockspeed_in_range(range, clockspeed)?; self.set_max_mclk_unchecked(clockspeed) } /// Sets the maximum memory clock (without checking if it's in the allowed range). fn set_max_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()>; /// Sets the minimum memory clock. fn set_min_mclk(&mut self, clockspeed: i32) -> Result<()> { let range = self.get_min_mclk_range(); check_clockspeed_in_range(range, clockspeed)?; self.set_min_mclk_unchecked(clockspeed) } /// Sets the minimum memory clock (without checking if it's in the allowed range). fn set_min_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()>; /// Sets the voltage to be used at the maximum clockspeed. fn set_max_voltage(&mut self, voltage: i32) -> Result<()> { let range = self.get_max_voltage_range(); check_clockspeed_in_range(range, voltage)?; self.set_max_voltage_unchecked(voltage) } /// Sets the voltage to be used at the maximum clockspeed (without checking if it's in the allowed range). fn set_max_voltage_unchecked(&mut self, voltage: i32) -> Result<()>; /// Sets the voltage to be used at the minimum clockspeed. fn set_min_voltage(&mut self, voltage: i32) -> Result<()> { let range = self.get_min_voltage_range(); check_clockspeed_in_range(range, voltage)?; self.set_min_voltage_unchecked(voltage) } /// Sets the voltage to be used at the minimum clockspeed (without checking if it's in the allowed range). fn set_min_voltage_unchecked(&mut self, voltage: i32) -> Result<()>; /// Gets the current maximum voltage (used on maximum clockspeed). fn get_max_sclk_voltage(&self) -> Option; } fn check_clockspeed_in_range(range: Option, clockspeed: i32) -> Result<()> { if let (Some(min), Some(max)) = range.map_or((None, None), |range| (range.min, range.max)) { if (min..=max).contains(&clockspeed) { Ok(()) } else { Err(Error::not_allowed(format!( "Given clockspeed {clockspeed} is out of the allowed OD range {min} to {max}" ))) } } else { Err(Error::not_allowed( "GPU does not report allowed OD ranges".to_owned(), )) } } /// Representation of clocks and voltage table (`pp_od_clk_voltage`). /// /// NOTE: the variant names are not 100% accurate, they roughly represent what generations of GPUs use each format. /// For example, Radeon VII (Vega20) uses the new "RDNA" format. #[derive(Debug, Clone)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[cfg_attr( feature = "serde", serde(tag = "kind", content = "data", rename_all = "snake_case") )] #[enum_dispatch(ClocksTable)] pub enum ClocksTableGen { /// Vega10 (and older) format Gcn(gcn::Table), /// Vega20 (and newer) format Rdna(rdna::Table), } impl FromStr for ClocksTableGen { type Err = Error; fn from_str(s: &str) -> Result { if s.contains("VDDC_CURVE") || s.contains("OD_VDDGFX_OFFSET") || { let mut lines = s.lines(); lines.next() == Some("OD_SCLK:") && lines.next().is_some_and(|sclk_line| { let sclk_line = sclk_line.to_ascii_lowercase(); sclk_line.contains("mhz") && !sclk_line.contains("mv") }) } { rdna::Table::from_str(s).map(Self::Rdna) } else { gcn::Table::from_str(s).map(Self::Gcn) } } } fn parse_range_line(line: &str, i: usize) -> Result<(Range, &str)> { let mut split = line.split_whitespace(); let name = split .next() .ok_or_else(|| Error::unexpected_eol("range name", i))? .trim_end_matches(':'); let min = parse_line_item(&mut split, i, "range minimum", &["mhz", "mv"])?; let max = parse_line_item(&mut split, i, "range maximum", &["mhz", "mv"])?; Ok((Range::full(min, max), name)) } /// Takes the next item from a split, strips the given suffixes, an parses it to a type fn parse_line_item( split: &mut SplitWhitespace, i: usize, item: &str, suffixes: &[&str], ) -> Result where T: FromStr, ::Err: std::fmt::Display, { let text = split .next() .ok_or_else(|| Error::unexpected_eol(item, i))? .to_lowercase(); let mut trimmed_text = text.as_str(); for suffix in suffixes { if cfg!(test) && suffix.chars().any(|ch| ch.is_uppercase()) { panic!("Suffixes must be all lowercase"); } trimmed_text = trimmed_text.trim_end_matches(suffix); } trimmed_text.parse().map_err(|err| { ErrorKind::ParseError { msg: format!("Could not parse {item} with value {trimmed_text}: {err}"), line: i, } .into() }) } /// A range. #[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct Range { /// The lower value of a range. pub min: Option, /// The higher value of a range. pub max: Option, } impl Range { /// Creates a range with both a minimum and a maximum value. pub fn full(min: i32, max: i32) -> Self { Self { min: Some(min), max: Some(max), } } /// Creates a rage with a minimum value only. pub fn min(min: i32) -> Self { Self { min: Some(min), max: None, } } /// Creates a rage with a maximum value only. pub fn max(max: i32) -> Self { Self { min: None, max: Some(max), } } /// Creates an empty range. pub const fn empty() -> Self { Self { min: None, max: None, } } /// Tries to convert the current range into a (min, max) pair. pub fn into_full(self) -> Option<(i32, i32)> { self.min.zip(self.max) } } impl TryFrom for (i32, i32) { type Error = (); fn try_from(value: Range) -> std::result::Result { if let (Some(min), Some(max)) = (value.min, value.max) { Ok((min, max)) } else { Err(()) } } } /// Represents a combination of a clockspeed and voltage. May be used in different context based on the table format. #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct ClocksLevel { /// Clockspeed (in MHz) pub clockspeed: i32, /// Voltage (in mV) pub voltage: i32, } impl ClocksLevel { /// Create a new clocks level. pub fn new(clockspeed: i32, voltage: i32) -> Self { Self { clockspeed, voltage, } } } fn parse_level_line(line: &str, i: usize) -> Result<(ClocksLevel, usize)> { let mut split = line.split_whitespace(); let num = parse_line_item(&mut split, i, "level number", &[":"])?; let clockspeed = parse_line_item(&mut split, i, "clockspeed", &["mhz"])?; let voltage = parse_line_item(&mut split, i, "voltage", &["mv"])?; Ok((ClocksLevel::new(clockspeed, voltage), num)) } fn push_level_line(line: &str, levels: &mut Vec, i: usize) -> Result<()> { let (level, num) = parse_level_line(line, i)?; let len = levels.len(); if num != len { return Err(ErrorKind::ParseError { msg: format!("Unexpected level num: expected {len}, got {num}"), line: i, } .into()); } levels.push(level); Ok(()) } #[cfg(test)] fn arr_commands(commands: [&str; N]) -> String { let mut output = commands.join("\n"); output.push('\n'); output } #[cfg(test)] mod tests { use std::str::FromStr; use insta::assert_yaml_snapshot; use crate::gpu_handle::overdrive::ClocksTableGen; use super::{check_clockspeed_in_range, parse_level_line, parse_range_line, Range}; #[macro_export] macro_rules! include_table { ($name:literal) => { include_test_data!(concat!($name, "/pp_od_clk_voltage")) }; } pub const TABLE_PHOENIX: &str = include_table!("internal-7840u"); pub const TABLE_VEGA56: &str = include_table!("vega56"); #[test] fn parse_range_line_sclk() { let line = "SCLK: 300MHz 2000MHz"; let (level, name) = parse_range_line(line, 50).unwrap(); assert_eq!(name, "SCLK"); assert_eq!(level.min, Some(300)); assert_eq!(level.max, Some(2000)); } #[test] fn parse_level_line_basic() { let line = "0: 300MHz 750mV"; let (level, i) = parse_level_line(line, 50).unwrap(); assert_eq!(i, 0); assert_eq!(level.clockspeed, 300); assert_eq!(level.voltage, 750); } #[test] fn allowed_ranges() { let range = Some(Range::full(300, 1000)); check_clockspeed_in_range(range, 300).unwrap(); check_clockspeed_in_range(range, 750).unwrap(); check_clockspeed_in_range(range, 1000).unwrap(); check_clockspeed_in_range(range, 1001).unwrap_err(); check_clockspeed_in_range(range, 250).unwrap_err(); } #[test] fn parse_range_line_voltage_point() { let line = "VDDC_CURVE_SCLK[2]: 800Mhz 2150Mhz"; let (range, name) = parse_range_line(line, 0).unwrap(); assert_eq!(range, Range::full(800, 2150)); assert_eq!(name, "VDDC_CURVE_SCLK[2]"); } #[test] fn detect_type_phoenix() { let table = ClocksTableGen::from_str(TABLE_PHOENIX).unwrap(); assert_yaml_snapshot!(table); } #[test] fn detect_type_vega10() { let table = ClocksTableGen::from_str(TABLE_VEGA56).unwrap(); assert_yaml_snapshot!(table); } } amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/rdna.rs000064400000000000000000000654151046102023000205470ustar 00000000000000//! The format used by Vega20 and newer GPUs. use super::{ parse_line_item, parse_range_line, push_level_line, ClocksLevel, ClocksTable, ClocksTableGen, Range, }; use crate::{ error::{Error, ErrorContext, ErrorKind::ParseError}, gpu_handle::trim_sysfs_line, Result, }; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{cmp, io::Write, str::FromStr}; /// Vega20 clocks table. #[derive(Debug, Clone)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct Table { /// The current core clock range. pub current_sclk_range: Range, /// The current core clock offset (RDNA4+) pub sclk_offset: Option, /// The current memory clock range. Empty on iGPUs. pub current_mclk_range: Range, /// The current voltage curve. May be empty if the GPU does not support it. pub vddc_curve: Vec, /// Voltage offset(in mV) applied on target voltage calculation. /// This is available for Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. /// /// Note: editing this value directly does not check if it's in the allowed range! pub voltage_offset: Option, /// The allowed ranges for clockspeeds and voltages. pub od_range: OdRange, } impl ClocksTable for Table { fn write_commands( &self, writer: &mut W, previous_table: &ClocksTableGen, ) -> Result<()> { let ClocksTableGen::Rdna(previous_table) = previous_table else { return Err(Error::not_allowed( "Mismatched clocks table format".to_owned(), )); }; let mut clocks_commands = Vec::with_capacity(4); // If the new minimum clockspeed is higher than the previous maximum clockspeed, // we need to first write the new maximum value to avoid an error on RDNA3 if let (Some(current_sclk_min), Some(old_sclk_max)) = ( self.current_sclk_range.min, previous_table.current_sclk_range.max, ) { if current_sclk_min > old_sclk_max { clocks_commands.push((self.current_sclk_range.max, 's', 1)); } } clocks_commands.extend([ (self.current_sclk_range.min, 's', 0), (self.current_sclk_range.max, 's', 1), ]); if let (Some(current_mclk_min), Some(old_mclk_max)) = ( self.current_mclk_range.min, previous_table.current_mclk_range.max, ) { if current_mclk_min > old_mclk_max { clocks_commands.push((self.current_mclk_range.max, 'm', 1)); } } clocks_commands.extend([ (self.current_mclk_range.min, 'm', 0), (self.current_mclk_range.max, 'm', 1), ]); if let Some(sclk_offset) = self.sclk_offset { let line = format!("s {sclk_offset}\n"); writer .write_all(line.as_bytes()) .context("Could not write sclk offset")?; } for (maybe_clockspeed, symbol, index) in clocks_commands { if let Some(clockspeed) = maybe_clockspeed { let line = clockspeed_line(symbol, index, clockspeed); writer .write_all(line.as_bytes()) .with_context(|| format!("Error when writing clockspeed line `{line}`"))?; } } for (i, level) in self.vddc_curve.iter().enumerate() { let line = vddc_curve_line(i, level.clockspeed, level.voltage); writer .write_all(line.as_bytes()) .with_context(|| format!("Error when writing VDDC line `{line}`"))?; } if let Some(offset) = self.voltage_offset { let line = voltage_offset_line(offset); writer .write_all(line.as_bytes()) .with_context(|| format!("Error when writing voltage offset `{line}`"))?; } Ok(()) } fn get_max_sclk_range(&self) -> Option { self.od_range .curve_sclk_points .last() .copied() .or(self.od_range.sclk) } fn get_min_sclk_range(&self) -> Option { self.od_range .curve_sclk_points .first() .copied() .or(self.od_range.sclk) } fn get_max_mclk_range(&self) -> Option { self.od_range.mclk } fn get_min_mclk_range(&self) -> Option { self.od_range.mclk } fn get_max_voltage_range(&self) -> Option { self.od_range.curve_voltage_points.last().copied() } fn get_min_voltage_range(&self) -> Option { self.od_range.curve_voltage_points.first().copied() } fn get_current_voltage_range(&self) -> Option { let min = self.vddc_curve.first().map(|level| level.voltage)?; let max = self.vddc_curve.last().map(|level| level.voltage)?; Some(Range::full(min, max)) } fn get_current_sclk_range(&self) -> Range { self.current_sclk_range } fn get_current_mclk_range(&self) -> Range { self.current_mclk_range } fn set_max_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { self.current_sclk_range.max = Some(clockspeed); if let Some(point) = self.vddc_curve.last_mut() { point.clockspeed = clockspeed; } Ok(()) } fn set_min_sclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { self.current_sclk_range.min = Some(clockspeed); if let Some(point) = self.vddc_curve.first_mut() { point.clockspeed = clockspeed; } Ok(()) } fn set_max_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { self.current_mclk_range.max = Some(clockspeed); Ok(()) } fn set_min_mclk_unchecked(&mut self, clockspeed: i32) -> Result<()> { self.current_mclk_range.min = Some(clockspeed); Ok(()) } fn set_max_voltage_unchecked(&mut self, voltage: i32) -> Result<()> { self.vddc_curve .last_mut() .ok_or_else(|| { Error::not_allowed("The GPU did not report any voltage curve points".to_owned()) })? .voltage = voltage; Ok(()) } fn set_min_voltage_unchecked(&mut self, voltage: i32) -> Result<()> { self.vddc_curve .first_mut() .ok_or_else(|| { Error::not_allowed("The GPU did not report any voltage curve points".to_owned()) })? .voltage = voltage; Ok(()) } fn get_max_sclk_voltage(&self) -> Option { self.vddc_curve.last().map(|level| level.voltage) } } impl Table { /// Sets the voltage offset, checking if it's in range if the GPU provided one /// /// Note: RDNA2 GPUs use a voltage offset but do not provide a range pub fn set_voltage_offset(&mut self, offset: i32) -> Result<()> { if let Some(offset_range) = self.od_range.voltage_offset { if let Some((min, max)) = offset_range.into_full() { if !(min..=max).contains(&offset) { return Err(Error::not_allowed(format!("Provided voltage offset {offset} is out of range, should be between {min} and {max}"))); } } } self.voltage_offset = Some(offset); Ok(()) } } impl FromStr for Table { type Err = Error; fn from_str(s: &str) -> Result { let mut current_section = None; let mut current_sclk_range = None; let mut current_mclk_range = None; let mut allowed_sclk_range = None; let mut allowed_sclk_offset_range = None; let mut allowed_mclk_range = None; let mut vddc_curve = Vec::with_capacity(3); let mut curve_sclk_points = Vec::with_capacity(3); let mut curve_voltage_points = Vec::with_capacity(3); let mut sclk_offset = None; let mut voltage_offset = None; let mut voltage_offset_range = None; let mut lines = s .lines() .map(trim_sysfs_line) .filter(|line| !line.is_empty()); let mut i = 1; while let Some(line) = lines.next() { match line { "OD_SCLK:" => current_section = Some(Section::Sclk), "OD_SCLK_OFFSET:" => current_section = Some(Section::SclkOffset), "OD_MCLK:" => current_section = Some(Section::Mclk), "OD_RANGE:" => current_section = Some(Section::Range), "OD_VDDC_CURVE:" => current_section = Some(Section::VddcCurve), "OD_VDDGFX_OFFSET:" => current_section = Some(Section::VddGfxOffset), line => match current_section { // Voltage points will overwrite maximum clock info, with the last one taking priority Some(Section::Range) if line.starts_with("VDDC_CURVE_SCLK") => { let (range, _) = parse_range_line(line, i)?; curve_sclk_points.push(range); } Some(Section::Range) if line.starts_with("VDDC_CURVE_VOLT") || (line.starts_with("VDDC_CURVE:") && line.contains("mv")) => { let (range, _) = parse_range_line(line, i)?; curve_voltage_points.push(range); } Some(Section::Range) if line.starts_with("CCLK_RANGE") => { lines.next(); lines.next(); } Some(Section::Range) => { let (range, name) = parse_range_line(line, i)?; match name { "SCLK" => allowed_sclk_range = Some(range), "SCLK_OFFSET" => allowed_sclk_offset_range = Some(range), "MCLK" => allowed_mclk_range = Some(range), "VDDGFX_OFFSET" => voltage_offset_range = Some(range), "CCLK" => (), // Ignore Van Gogh CPU clocks other => { return Err(ParseError { msg: format!("Unexpected range item: {other}"), line: i, } .into()) } } } Some(Section::Sclk) => parse_min_max_line(line, i, &mut current_sclk_range)?, Some(Section::SclkOffset) => { let line = line.to_ascii_lowercase(); let raw_value = line.trim_end_matches("mhz"); let value = raw_value .parse() .context("Could not parse sclk offset value")?; sclk_offset = Some(value); } Some(Section::Mclk) => parse_min_max_line(line, i, &mut current_mclk_range)?, Some(Section::VddcCurve) => { let _ = push_level_line(line, &mut vddc_curve, i); } Some(Section::VddGfxOffset) => { let offset = parse_voltage_offset_line(line, i)?; voltage_offset = Some(offset); } None => { return Err(ParseError { msg: "Unexpected line without section".to_owned(), line: i, } .into()) } }, } i += 1; } let od_range = OdRange { sclk: allowed_sclk_range, sclk_offset: allowed_sclk_offset_range, mclk: allowed_mclk_range, curve_sclk_points, curve_voltage_points, voltage_offset: voltage_offset_range, }; Ok(Self { current_sclk_range: current_sclk_range.unwrap_or_default(), sclk_offset, current_mclk_range: current_mclk_range.unwrap_or_default(), vddc_curve, od_range, voltage_offset, }) } } impl Table { /// Clears the table of all "applicable" values. /// /// This removes all values except the allowed range and voltage curve. /// You can use it to avoid overwriting the table with already present values, as it can be problematic on some cards. /// It is intended to be used before calling `set_*` functions and generating commands/writing the table. pub fn clear(&mut self) { self.current_sclk_range = Range::empty(); self.current_mclk_range = Range::empty(); self.sclk_offset = None; self.voltage_offset = None; } /// Normalizes the VDDC curve making sure all of the values are within the allowed range. /// This is needed as some GPUs have default values outside of the allowed range. pub fn normalize_vddc_curve(&mut self) { for (i, point) in self.vddc_curve.iter_mut().enumerate() { if let Some(sclk_range) = self.od_range.curve_sclk_points.get(i) { let normalized_clockspeed = normalize_value(point.clockspeed, *sclk_range); point.clockspeed = normalized_clockspeed; } if let Some(voltage_range) = self.od_range.curve_voltage_points.get(i) { let normalized_voltage = normalize_value(point.voltage, *voltage_range); point.voltage = normalized_voltage; } } } } fn normalize_value(mut value: i32, range: Range) -> i32 { if let Some(min_allowed) = range.min { value = cmp::max(min_allowed, value); } if let Some(max_allowed) = range.max { value = cmp::min(max_allowed, value); } value } /// The ranges for overclocking values which the GPU allows to be used. #[derive(Debug, Clone, PartialEq, Eq)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct OdRange { /// Clocks range for sclk (in MHz). Present on RDNA1-3. pub sclk: Option, /// Clocks offset range for sclk (in MHz). Present on at least RDNA4. pub sclk_offset: Option, /// Clocks range for mclk (in MHz). Present on discrete GPUs only. pub mclk: Option, /// Frequencies available at specific levels. pub curve_sclk_points: Vec, /// Ranges available at specific levels. pub curve_voltage_points: Vec, /// Allowed voltage offset range. Present on RDNA3+. pub voltage_offset: Option, } #[derive(Debug)] enum Section { Sclk, SclkOffset, Mclk, VddcCurve, Range, VddGfxOffset, } fn parse_clockspeed_line(line: &str, i: usize) -> Result<(i32, usize)> { let mut split = line.split_whitespace(); let num = parse_line_item(&mut split, i, "level number", &[":"])?; let clockspeed = parse_line_item(&mut split, i, "clockspeed", &["mhz"])?; Ok((clockspeed, num)) } fn parse_min_max_line(line: &str, i: usize, range: &mut Option) -> Result<()> { let (clockspeed, num) = parse_clockspeed_line(line, i)?; match num { 0 => { *range = Some(Range::min(clockspeed)); Ok(()) } 1 => { if let Some(range) = range { range.max = Some(clockspeed); } else { *range = Some(Range::max(clockspeed)); } Ok(()) } _ => Err(ParseError { msg: format!("Unexpected range number {num}"), line: i, } .into()), } } fn parse_voltage_offset_line(line: &str, i: usize) -> Result { match line.to_lowercase().strip_suffix("mv") { Some(raw_value) => Ok(raw_value.parse()?), None => Err(ParseError { msg: format!("Could not find expected `mV` suffix in offset line {line}"), line: i, } .into()), } } fn clockspeed_line(symbol: char, index: usize, clockspeed: i32) -> String { format!("{symbol} {index} {clockspeed}\n") } fn vddc_curve_line(index: usize, clockspeed: i32, voltage: i32) -> String { format!("vc {index} {clockspeed} {voltage}\n") } fn voltage_offset_line(offset: i32) -> String { format!("vo {offset}\n") } #[cfg(test)] mod tests { use super::{OdRange, Table}; use crate::{ gpu_handle::overdrive::{ arr_commands, tests::TABLE_PHOENIX, ClocksLevel, ClocksTable, Range, }, include_table, }; use insta::assert_yaml_snapshot; use pretty_assertions::assert_eq; use std::str::FromStr; const TABLE_5500XT: &str = include_table!("rx5500xt"); const TABLE_5700XT: &str = include_table!("rx5700xt"); const TABLE_6900XT: &str = include_table!("rx6900xt"); const TABLE_6700XT: &str = include_table!("rx6700xt"); const TABLE_6800: &str = include_table!("rx6800"); const TABLE_7900XTX: &str = include_table!("rx7900xtx"); const TABLE_7900XT: &str = include_table!("rx7900xt"); const TABLE_7800XT: &str = include_table!("rx7800xt"); const TABLE_9070XT: &str = include_table!("rx9070xt"); const TABLE_VANGOGH: &str = include_table!("vangogh"); #[test] fn parse_5700xt_full() { let table = Table::from_str(TABLE_5700XT).unwrap(); assert_eq!(table.current_sclk_range, Range::full(800, 2100)); assert_eq!(table.current_mclk_range, Range::max(875)); let vddc_curve = [(800, 711), (1450, 801), (2100, 1191)] .map(|(clockspeed, voltage)| ClocksLevel::new(clockspeed, voltage)); assert_eq!(table.vddc_curve, vddc_curve); let curve_sclk_points = vec![ Range::full(800, 2150), Range::full(800, 2150), Range::full(800, 2150), ]; let curve_voltage_points = vec![ Range::full(750, 1200), Range::full(750, 1200), Range::full(750, 1200), ]; let od_range = OdRange { sclk: Some(Range::full(800, 2150)), mclk: Some(Range::full(625, 950)), curve_sclk_points, curve_voltage_points, sclk_offset: None, voltage_offset: None, }; assert_eq!(table.od_range, od_range); } #[test] fn generic_actions_5700xt() { let mut table = Table::from_str(TABLE_5700XT).unwrap(); assert_eq!(table.get_max_sclk(), Some(2100)); assert_eq!(table.get_max_mclk(), Some(875)); assert_eq!(table.get_max_sclk_voltage(), Some(1191)); table.set_max_sclk(2050).unwrap(); assert_eq!(table.get_max_sclk(), Some(2050)); assert_eq!(table.current_sclk_range.max, Some(2050)); table.set_max_mclk(950).unwrap(); assert_eq!(table.get_max_mclk(), Some(950)); assert_eq!(table.current_mclk_range.max, Some(950)); table.set_max_voltage(1150).unwrap(); assert_eq!(table.vddc_curve[2].voltage, 1150); let sclk_range = table.get_max_sclk_range(); let mclk_range = table.get_max_mclk_range(); let voltage_range = table.get_max_voltage_range(); assert_eq!(sclk_range, Some(Range::full(800, 2150))); assert_eq!(mclk_range, Some(Range::full(625, 950))); assert_eq!(voltage_range, Some(Range::full(750, 1200))); } #[test] fn write_commands_5700xt() { let mut table = Table::from_str(TABLE_5700XT).unwrap(); table.set_max_sclk(2150).unwrap(); table.set_min_sclk(850).unwrap(); table.set_max_mclk(950).unwrap(); table.set_max_voltage(1200).unwrap(); let mut buf = Vec::new(); table .write_commands(&mut buf, &table.clone().into()) .unwrap(); let commands = String::from_utf8(buf).unwrap(); let expected_commands = arr_commands([ "s 0 850", "s 1 2150", "m 1 950", "vc 0 850 711", "vc 1 1450 801", "vc 2 2150 1200", ]); assert_eq!(expected_commands, commands); } #[test] fn normalize_vddc_curve_5700xt() { let mut table = Table::from_str(TABLE_5700XT).unwrap(); let voltage_range = table.od_range.curve_voltage_points[0]; // The table has points outside of the allowed range by default assert!(table.vddc_curve.iter().any(|level| { level.voltage < voltage_range.min.unwrap() || level.voltage > voltage_range.max.unwrap() })); table.normalize_vddc_curve(); // The table does not have any points outside of the allowed range after normalization assert!(!table.vddc_curve.iter().any(|level| { level.voltage < voltage_range.min.unwrap() || level.voltage > voltage_range.max.unwrap() })); assert_eq!(750, table.vddc_curve[0].voltage); } #[test] fn write_commands_5500xt() { let mut table = Table::from_str(TABLE_5500XT).unwrap(); table.clear(); table.set_max_sclk(1900).unwrap(); table.set_max_voltage(1140).unwrap(); let commands = table.get_commands(&table.clone().into()).unwrap(); let expected_commands = vec![ "s 1 1900", "vc 0 500 710", "vc 1 1162 794", "vc 2 1900 1140", ]; assert_eq!(expected_commands, commands); } #[test] fn write_commands_custom_5700xt() { let table = Table { current_sclk_range: Range::empty(), current_mclk_range: Range::full(500, 1000), sclk_offset: None, vddc_curve: vec![ClocksLevel::new(300, 600), ClocksLevel::new(1000, 1000)], voltage_offset: None, od_range: OdRange { sclk: None, sclk_offset: None, mclk: None, curve_sclk_points: Vec::new(), curve_voltage_points: Vec::new(), voltage_offset: None, }, }; let mut buf = Vec::new(); table .write_commands(&mut buf, &table.clone().into()) .unwrap(); let commands = String::from_utf8(buf).unwrap(); let expected_commands = arr_commands(["m 0 500", "m 1 1000", "vc 0 300 600", "vc 1 1000 1000"]); assert_eq!(expected_commands, commands); } #[test] fn parse_6900xt_full() { let table = Table::from_str(TABLE_6900XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn write_commands_6900xt_default() { let table = Table::from_str(TABLE_6900XT).unwrap(); let commands = table.get_commands(&table.clone().into()).unwrap(); assert_yaml_snapshot!(commands); } #[test] fn write_commands_6900xt_custom() { let mut table = Table::from_str(TABLE_6900XT).unwrap(); table.clear(); table.set_min_sclk(800).unwrap(); table.set_max_sclk(2400).unwrap(); table.set_max_mclk(900).unwrap(); assert!(table.set_min_voltage(1000).is_err()); let commands = table.get_commands(&table.clone().into()).unwrap(); assert_yaml_snapshot!(commands); } #[test] fn parse_6700xt_full() { let table = Table::from_str(TABLE_6700XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn generic_actions_6700xt() { let table = Table::from_str(TABLE_6700XT).unwrap(); let max_sclk = table.get_max_sclk().unwrap(); assert_eq!(max_sclk, 2725); let sclk_range = table.get_max_sclk_range().unwrap(); assert_eq!(sclk_range, Range::full(500, 2800)); let max_mclk = table.get_max_mclk().unwrap(); assert_eq!(max_mclk, 1000); let mclk_range = table.get_max_mclk_range().unwrap(); assert_eq!(mclk_range, Range::full(674, 1075)); assert!(table.get_max_sclk_voltage().is_none()); let current_sclk_range = table.get_current_sclk_range(); assert_eq!(current_sclk_range, Range::full(500, 2725)); let current_mclk_range = table.get_current_mclk_range(); assert_eq!(current_mclk_range, Range::full(97, 1000)); } #[test] fn write_only_max_values_6700xt() { let mut table = Table::from_str(TABLE_6700XT).unwrap(); table.clear(); table.set_max_sclk(2800).unwrap(); table.set_max_mclk(1075).unwrap(); let commands = table.get_commands(&table.clone().into()).unwrap(); assert_yaml_snapshot!(commands); } #[test] fn write_new_min_over_old_max_7900xt() { let original_table = Table::from_str(TABLE_7900XT).unwrap(); let mut new_table = original_table.clone(); new_table.clear(); new_table.set_min_mclk(1350).unwrap(); new_table.set_max_mclk(1350).unwrap(); new_table.set_min_sclk(3000).unwrap(); new_table.set_max_sclk(3000).unwrap(); let commands = new_table.get_commands(&original_table.into()).unwrap(); assert_yaml_snapshot!(commands); } #[test] fn parse_6800_full() { let table = Table::from_str(TABLE_6800).unwrap(); assert_yaml_snapshot!(table); } #[test] fn set_max_values_6800() { let mut table = Table::from_str(TABLE_6800).unwrap(); table.clear(); table.set_max_sclk(2400).unwrap(); assert!(table.set_max_sclk(2700).is_err()); table.set_max_mclk(1050).unwrap(); table.voltage_offset = Some(10); assert_yaml_snapshot!(table.get_commands(&table.clone().into()).unwrap()); } #[test] fn parse_7900xtx_full() { let table = Table::from_str(TABLE_7900XTX).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_7900xt_full() { let table = Table::from_str(TABLE_7900XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_7800xt_full() { let table = Table::from_str(TABLE_7800XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_9070xt_full() { let table = Table::from_str(TABLE_9070XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn set_clock_offset_9070xt() { let mut table = Table::from_str(TABLE_9070XT).unwrap(); table.clear(); table.sclk_offset = Some(200); table.voltage_offset = Some(-50); assert_yaml_snapshot!(table.get_commands(&table.clone().into()).unwrap()); } #[test] fn set_7800xt_voltage() { let mut table = Table::from_str(TABLE_7800XT).unwrap(); table.set_voltage_offset(-300).unwrap(); table.set_voltage_offset(100).unwrap_err(); } #[test] fn parse_phoenix_full() { let table = Table::from_str(TABLE_PHOENIX).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_vangogh_full() { let table = Table::from_str(TABLE_VANGOGH).unwrap(); assert_yaml_snapshot!(table); } } ././@LongLink00006440000000000000000000000200000000000000007763Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6700xt_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000005601046102023000324570ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 2725 sclk_offset: ~ current_mclk_range: min: 97 max: 1000 vddc_curve: [] voltage_offset: 0 od_range: sclk: min: 500 max: 2800 sclk_offset: ~ mclk: min: 674 max: 1075 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000176000000000000007777Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6800_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000005601046102023000324570ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 2314 sclk_offset: ~ current_mclk_range: min: 97 max: 1000 vddc_curve: [] voltage_offset: 0 od_range: sclk: min: 500 max: 2600 sclk_offset: ~ mclk: min: 674 max: 1075 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000200000000000000007763Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6900xt_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000005621046102023000324610ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 2499 sclk_offset: ~ current_mclk_range: min: 97 max: 1000 vddc_curve: [] voltage_offset: -10 od_range: sclk: min: 500 max: 3000 sclk_offset: ~ mclk: min: 674 max: 1075 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000200000000000000007763Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_7800xt_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000006061046102023000324600ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 2660 sclk_offset: ~ current_mclk_range: min: 97 max: 1219 vddc_curve: [] voltage_offset: 0 od_range: sclk: min: 500 max: 5000 sclk_offset: ~ mclk: min: 97 max: 1500 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: min: -450 max: 0 ././@LongLink00006440000000000000000000000200000000000000007763Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_7900xt_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000006061046102023000324600ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 2735 sclk_offset: ~ current_mclk_range: min: 97 max: 1250 vddc_curve: [] voltage_offset: 0 od_range: sclk: min: 500 max: 5000 sclk_offset: ~ mclk: min: 97 max: 1500 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: min: -450 max: 0 ././@LongLink00006440000000000000000000000201000000000000007764Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_7900xtx_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000006111046102023000324540ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 500 max: 3005 sclk_offset: ~ current_mclk_range: min: 97 max: 1250 vddc_curve: [] voltage_offset: ~ od_range: sclk: min: 500 max: 5000 sclk_offset: ~ mclk: min: 97 max: 1500 curve_sclk_points: [] curve_voltage_points: - min: -450 max: 0 voltage_offset: ~ ././@LongLink00006440000000000000000000000200000000000000007763Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_9070xt_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000006021046102023000324540ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: ~ max: ~ sclk_offset: 0 current_mclk_range: min: 97 max: 1259 vddc_curve: [] voltage_offset: 0 od_range: sclk: ~ sclk_offset: min: -500 max: 1000 mclk: min: 97 max: 1500 curve_sclk_points: [] curve_voltage_points: [] voltage_offset: min: -200 max: 0 ././@LongLink00006440000000000000000000000201000000000000007764Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_phoenix_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000005231046102023000324560ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 800 max: 2700 sclk_offset: ~ current_mclk_range: min: ~ max: ~ vddc_curve: [] voltage_offset: ~ od_range: sclk: min: 800 max: 2700 sclk_offset: ~ mclk: ~ curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000201000000000000007764Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_vangogh_full.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000005241046102023000324570ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table --- current_sclk_range: min: 1600 max: 1600 sclk_offset: ~ current_mclk_range: min: ~ max: ~ vddc_curve: [] voltage_offset: ~ od_range: sclk: min: 200 max: 1600 sclk_offset: ~ mclk: ~ curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000206000000000000007771Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__set_clock_offset_9070xt.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000002011046102023000324470ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table.get_commands(&table.clone().into()).unwrap() --- - s 200 - vo -50 ././@LongLink00006440000000000000000000000202000000000000007765Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__set_max_values_6800.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000002161046102023000324550ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: table.get_commands(&table.clone().into()).unwrap() --- - s 1 2400 - m 1 1050 - vo 10 ././@LongLink00006440000000000000000000000213000000000000007767Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__write_commands_6900xt_custom.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000001451046102023000324560ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: commands --- - s 0 800 - s 1 2400 - m 1 900 ././@LongLink00006440000000000000000000000214000000000000007770Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__write_commands_6900xt_default.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000001701046102023000324540ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: commands --- - s 0 500 - s 1 2499 - m 0 97 - m 1 1000 - vo -10 ././@LongLink00006440000000000000000000000220000000000000007765Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__write_new_min_over_old_max_7900xt.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000002101046102023000324470ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: commands --- - s 1 3000 - s 0 3000 - s 1 3000 - m 1 1350 - m 0 1350 - m 1 1350 ././@LongLink00006440000000000000000000000213000000000000007767Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__write_only_max_values_6700xt.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__te000064400000000000000000000001341046102023000324540ustar 00000000000000--- source: src/gpu_handle/overdrive/rdna.rs expression: commands --- - s 1 2800 - m 1 1075 ././@LongLink00006440000000000000000000000174000000000000007775Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__tests__detect_type_phoenix.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__tests__d000064400000000000000000000006071046102023000325120ustar 00000000000000--- source: src/gpu_handle/overdrive/mod.rs expression: table --- kind: rdna data: current_sclk_range: min: 800 max: 2700 sclk_offset: ~ current_mclk_range: min: ~ max: ~ vddc_curve: [] voltage_offset: ~ od_range: sclk: min: 800 max: 2700 sclk_offset: ~ mclk: ~ curve_sclk_points: [] curve_voltage_points: [] voltage_offset: ~ ././@LongLink00006440000000000000000000000173000000000000007774Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__tests__detect_type_vega10.snapamdgpu-sysfs-0.19.3/src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__tests__d000064400000000000000000000013561046102023000325140ustar 00000000000000--- source: src/gpu_handle/overdrive/mod.rs expression: table --- kind: gcn data: sclk_levels: - clockspeed: 852 voltage: 800 - clockspeed: 991 voltage: 900 - clockspeed: 1138 voltage: 950 - clockspeed: 1269 voltage: 1000 - clockspeed: 1312 voltage: 1050 - clockspeed: 1474 voltage: 1100 - clockspeed: 1538 voltage: 1150 - clockspeed: 1590 voltage: 1200 mclk_levels: - clockspeed: 167 voltage: 800 - clockspeed: 500 voltage: 800 - clockspeed: 700 voltage: 900 - clockspeed: 920 voltage: 950 od_range: sclk: min: 852 max: 2400 mclk: min: 167 max: 1500 vddc: min: 800 max: 1200 amdgpu-sysfs-0.19.3/src/gpu_handle/power_levels.rs000064400000000000000000000034641046102023000203200ustar 00000000000000#[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; /// List of power levels. #[derive(Debug, Clone, PartialEq, Eq, Default)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct PowerLevels { /// List of possible levels. pub levels: Vec, /// The currently active level. pub active: Option, } impl PowerLevels { /// Gets the currently active level value. pub fn active_level(&self) -> Option<&T> { self.active.and_then(|active| self.levels.get(active)) } } macro_rules! impl_get_clocks_levels { ($name:ident, $level:expr, $out:ty) => { /// Gets clocks levels. pub fn $name(&self) -> Result> { self.get_clock_levels($level) } }; } /// Type of a power level. #[allow(missing_docs)] #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[cfg_attr(feature = "serde", serde(rename_all = "snake_case"))] pub enum PowerLevelKind { CoreClock, MemoryClock, SOCClock, FabricClock, DCEFClock, PcieSpeed, } impl PowerLevelKind { /// Gets the filename of a given power level kind. pub fn filename(&self) -> &str { use PowerLevelKind::*; match self { CoreClock => "pp_dpm_sclk", MemoryClock => "pp_dpm_mclk", SOCClock => "pp_dpm_socclk", FabricClock => "pp_dpm_fclk", DCEFClock => "pp_dpm_dcefclk", PcieSpeed => "pp_dpm_pcie", } } /// Suffix of the power level value pub fn value_suffix(&self) -> Option<&str> { use PowerLevelKind::*; match self { CoreClock | MemoryClock | SOCClock | FabricClock | DCEFClock => Some("mhz"), PcieSpeed => None, } } } amdgpu-sysfs-0.19.3/src/gpu_handle/power_profile_mode.rs000064400000000000000000000364611046102023000214750ustar 00000000000000//! `pp-power-profile-mode` #![allow(missing_docs)] // temp use crate::{ error::{Error, ErrorKind}, Result, }; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::collections::BTreeMap; /// Table of predefined power profile modes /// https://kernel.org/doc/html/latest/gpu/amdgpu/thermal.html#pp-power-profile-mode #[derive(Debug)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct PowerProfileModesTable { /// List of available modes pub modes: BTreeMap, /// Names for the values in [`PowerProfile`] pub value_names: Vec, /// The currently active mode pub active: u16, } #[derive(Debug)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct PowerProfile { pub name: String, /// On RDNA and newer, each profile has multiple components for different clock types. /// Older generations have only one set of values. pub components: Vec, } #[derive(Debug)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize, Default, Clone))] pub struct PowerProfileComponent { /// Filled on RDNA and newer pub clock_type: Option, pub values: Vec>, } impl PowerProfileModesTable { /// Parse the table from a given string pub fn parse(s: &str) -> Result { let mut lines = s.lines().map(|line| line.split_whitespace()); let mut split = lines .next() .ok_or_else(|| Error::unexpected_eol("Power profile line", 1))?; let start = split .next() .ok_or_else(|| Error::unexpected_eol("Value description", 1))?; match start { "NUM" => Self::parse_flat(s), "PROFILE_INDEX(NAME)" => Self::parse_nested(s), _ if start.parse::().is_ok() => { if lines .next() .and_then(|mut line| line.next()) .is_some_and(|term| term.parse::().is_ok()) { Self::parse_basic(s) } else { Self::parse_rotated(s) } } _ => Err(Error::basic_parse_error( "Could not determine the type of power profile mode table", )), } } /// Parse the format used by pre-RDNA GPUs fn parse_flat(s: &str) -> Result { let mut modes = BTreeMap::new(); let mut active = None; let mut lines = s.lines(); let header_line = lines .next() .ok_or_else(|| Error::unexpected_eol("Info header", 1))?; let mut header_split = header_line.split_whitespace(); if header_split.next() != Some("NUM") { return Err( ErrorKind::Unsupported("Expected header to start with 'NUM'".to_owned()).into(), ); } if header_split.next() != Some("MODE_NAME") { return Err(ErrorKind::Unsupported( "Expected header to contain 'MODE_NAME'".to_owned(), ) .into()); } let value_names: Vec = header_split.map(str::to_owned).collect(); for (line, row) in s.lines().map(str::trim).enumerate() { let mut split = row.split_whitespace().peekable(); if let Some(num) = split.next().and_then(|part| part.parse::().ok()) { let name_part = split .next() .ok_or_else(|| Error::unexpected_eol("Mode name", line + 1))? .trim_end_matches(':'); // Handle space within the mode name: // `3D_FULL_SCREEN *:` if let Some(next) = split.peek() { if next.ends_with(':') { if next.starts_with('*') { active = Some(num); } split.next(); } } let name = if let Some(name) = name_part.strip_suffix('*') { active = Some(num); name.trim() } else { name_part }; let values = split .map(|value| { if value == "-" { Ok(None) } else { let parsed = value.parse().map_err(|_| { Error::from(ErrorKind::ParseError { msg: format!("Expected an integer, got '{value}'"), line: line + 1, }) })?; Ok(Some(parsed)) } }) .collect::>()?; let power_profile = PowerProfile { name: name.to_owned(), components: vec![PowerProfileComponent { clock_type: None, values, }], }; modes.insert(num, power_profile); } } Ok(Self { modes, value_names, active: active.ok_or_else(|| Error::basic_parse_error("No active level found"))?, }) } /// Parse the format used by RDNA and higher fn parse_nested(s: &str) -> Result { let mut modes = BTreeMap::new(); let mut active = None; let mut lines = s.lines(); let header_line = lines .next() .ok_or_else(|| Error::unexpected_eol("Info header", 1))?; let mut header_split = header_line.split_whitespace(); if header_split.next() != Some("PROFILE_INDEX(NAME)") { return Err(ErrorKind::Unsupported( "Expected header to start with 'PROFILE_INDEX(NAME)'".to_owned(), ) .into()); } if header_split.next() != Some("CLOCK_TYPE(NAME)") { return Err(ErrorKind::Unsupported( "Expected header to contain 'CLOCK_TYPE(NAME)'".to_owned(), ) .into()); } let value_names: Vec = header_split.map(str::to_owned).collect(); let mut lines = lines.map(str::trim).enumerate().peekable(); while let Some((line, row)) = lines.next() { if row.contains('(') { return Err(ErrorKind::ParseError { msg: format!("Unexpected mode heuristics line '{row}'"), line: line + 1, } .into()); } let mut split = row.split_whitespace(); if let Some(num) = split.next().and_then(|part| part.parse::().ok()) { let name_part = split .next() .ok_or_else(|| Error::unexpected_eol("No name after mode number", line + 1))? .trim_end_matches(':'); let name = if let Some(name) = name_part.strip_suffix('*') { active = Some(num); name.trim() } else { name_part }; let mut components = Vec::new(); while lines .peek() .is_some_and(|(_, row)| row.contains(['(', ')'])) { let (line, clock_type_line) = lines.next().unwrap(); let name_start = clock_type_line .char_indices() .position(|(_, c)| c == '(') .ok_or_else(|| Error::unexpected_eol('(', line + 1))?; let name_end = clock_type_line .char_indices() .position(|(_, c)| c == ')') .ok_or_else(|| Error::unexpected_eol(')', line + 1))?; let clock_type = clock_type_line[name_start + 1..name_end].trim(); let clock_type_values = clock_type_line[name_end + 1..] .split_whitespace() .map(str::trim) .map(|value| { if value == "-" { Ok(None) } else { let parsed = value.parse().map_err(|_| { Error::from(ErrorKind::ParseError { msg: format!("Expected an integer, got '{value}'"), line: line + 1, }) })?; Ok(Some(parsed)) } }) .collect::>>>()?; components.push(PowerProfileComponent { clock_type: Some(clock_type.to_owned()), values: clock_type_values, }) } let power_profile = PowerProfile { name: name.to_owned(), components, }; modes.insert(num, power_profile); } } Ok(Self { modes, value_names, active: active.ok_or_else(|| Error::basic_parse_error("No active level found"))?, }) } /// Parse "rotated" format (with columns as profiles, and rows as values). /// Used at least by RDNA3 laptop GPUs (example data: 7700s) fn parse_rotated(s: &str) -> Result { let mut modes = BTreeMap::new(); let mut active = None; let mut lines = s.lines().map(str::trim).enumerate(); let mut header_split = lines .next() .ok_or_else(|| Error::basic_parse_error("Missing header"))? .1 .split_whitespace() .peekable(); while let Some(raw_index) = header_split.next() { let index: u16 = raw_index.parse().map_err(|_| { Error::basic_parse_error(format!("Invalid mode index '{raw_index}'")) })?; let mut name = header_split .next() .ok_or_else(|| Error::unexpected_eol("Missing section name", 1))?; if let Some(stripped) = name.strip_suffix("*") { name = stripped; active = Some(index); } if let Some(&"*") = header_split.peek() { active = Some(index); header_split.next(); } modes.insert( index, PowerProfile { name: name.to_owned(), components: vec![], }, ); } let mut value_names = vec![]; for (i, line) in lines { let mut split = line.split_whitespace(); let value_name = split .next() .ok_or_else(|| Error::unexpected_eol("Value name", i + 1))?; value_names.push(value_name.to_owned()); for (profile_i, raw_value) in split.enumerate() { let value = raw_value.parse().map_err(|_| { Error::basic_parse_error(format!("Invalid mode value '{raw_value}'")) })?; let profile = modes.get_mut(&(profile_i as u16)).ok_or_else(|| { Error::basic_parse_error("Could not get profile from header by index") })?; match profile.components.first_mut() { Some(component) => { component.values.push(Some(value)); } None => { let component = PowerProfileComponent { clock_type: None, values: vec![Some(value)], }; profile.components.push(component); } } } } Ok(Self { modes, value_names, active: active.ok_or_else(|| Error::basic_parse_error("No active level found"))?, }) } /// Parse the format used by integrated GPUs fn parse_basic(s: &str) -> Result { let mut modes = BTreeMap::new(); let mut active = None; for (line, row) in s.lines().map(str::trim).enumerate() { let mut split = row.split_whitespace(); if let Some(num) = split.next().and_then(|part| part.parse::().ok()) { let name_part = split .next() .ok_or_else(|| Error::unexpected_eol("No name after mode number", line + 1))?; let name = if let Some(name) = name_part.strip_suffix('*') { active = Some(num); name } else { name_part }; modes.insert( num, PowerProfile { name: name.to_owned(), components: vec![], }, ); } } Ok(Self { modes, value_names: vec![], active: active.ok_or_else(|| Error::basic_parse_error("No active level found"))?, }) } } impl PowerProfile { /// If this is the custom profile (checked by name) pub fn is_custom(&self) -> bool { self.name.eq_ignore_ascii_case("CUSTOM") } } #[cfg(test)] mod tests { use super::PowerProfileModesTable; use insta::assert_yaml_snapshot; const TABLE_VEGA56: &str = include_test_data!("vega56/pp_power_profile_mode"); const TABLE_RX580: &str = include_test_data!("rx580/pp_power_profile_mode"); const TABLE_4800H: &str = include_test_data!("internal-4800h/pp_power_profile_mode"); const TABLE_RX6900XT: &str = include_test_data!("rx6900xt/pp_power_profile_mode"); const TABLE_RX7600S: &str = include_test_data!("rx7600s/pp_power_profile_mode"); const TABLE_RX7700S: &str = include_test_data!("rx7700s/pp_power_profile_mode"); const TABLE_RX7800XT: &str = include_test_data!("rx7800xt/pp_power_profile_mode"); #[test] fn parse_full_vega56() { let table = PowerProfileModesTable::parse(TABLE_VEGA56).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_rx580() { let table = PowerProfileModesTable::parse(TABLE_RX580).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_internal_4800h() { let table = PowerProfileModesTable::parse(TABLE_4800H).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_rx6900xt() { let table = PowerProfileModesTable::parse(TABLE_RX6900XT).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_rx7600s() { let table = PowerProfileModesTable::parse(TABLE_RX7600S).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_rx7700s() { let table = PowerProfileModesTable::parse(TABLE_RX7700S).unwrap(); assert_yaml_snapshot!(table); } #[test] fn parse_full_rx7800xt() { let table = PowerProfileModesTable::parse(TABLE_RX7800XT).unwrap(); assert_yaml_snapshot!(table); } } ././@LongLink00006440000000000000000000000201000000000000007764Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_internal_4800h.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000004711046102023000325340ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 1: name: 3D_FULL_SCREEN components: [] 3: name: VIDEO components: [] 4: name: VR components: [] 5: name: COMPUTE components: [] 6: name: CUSTOM components: [] value_names: [] active: 3 ././@LongLink00006440000000000000000000000170000000000000007771Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_rx580.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000025341046102023000325360ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: ~ values: - ~ - ~ - ~ - ~ - ~ - ~ 1: name: 3D_FULL_SCREEN components: - clock_type: ~ values: - 0 - 100 - 30 - 10 - 60 - 25 2: name: POWER_SAVING components: - clock_type: ~ values: - 10 - 0 - 30 - ~ - ~ - ~ 3: name: VIDEO components: - clock_type: ~ values: - ~ - ~ - ~ - 10 - 16 - 31 4: name: VR components: - clock_type: ~ values: - 0 - 11 - 50 - 0 - 100 - 10 5: name: COMPUTE components: - clock_type: ~ values: - 0 - 5 - 30 - ~ - ~ - ~ 6: name: CUSTOM components: - clock_type: ~ values: - ~ - ~ - ~ - ~ - ~ - ~ value_names: - SCLK_UP_HYST - SCLK_DOWN_HYST - SCLK_ACTIVE_LEVEL - MCLK_UP_HYST - MCLK_DOWN_HYST - MCLK_ACTIVE_LEVEL active: 1 ././@LongLink00006440000000000000000000000173000000000000007774Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_rx6900xt.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000104301046102023000325300ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: GFXCLK values: - 0 - 5 - 1 - 0 - 4 - 800 - 4587520 - -65536 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 3276800 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 1 - 0 - 4 - 800 - 327680 - -65536 - 0 1: name: 3D_FULL_SCREEN components: - clock_type: GFXCLK values: - 0 - 5 - 0 - 1600 - 4 - 650 - 5242880 - -3276 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 655360 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 4 - 850 - 4 - 800 - 327680 - -65536 - 0 2: name: POWER_SAVING components: - clock_type: GFXCLK values: - 0 - 5 - 1 - 0 - 3 - 0 - 5898240 - -65536 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 3407872 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 1 - 0 - 3 - 0 - 1966080 - -65536 - 0 3: name: VIDEO components: - clock_type: GFXCLK values: - 0 - 5 - 1 - 0 - 4 - 500 - 4587520 - -65536 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 3473408 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 1 - 0 - 4 - 500 - 1966080 - -65536 - 0 4: name: VR components: - clock_type: GFXCLK values: - 0 - 5 - 4 - 1000 - 1 - 0 - 3276800 - 0 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 655360 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 1 - 0 - 4 - 800 - 327680 - -65536 - 0 5: name: COMPUTE components: - clock_type: GFXCLK values: - 0 - 5 - 4 - 1000 - 1 - 0 - 3932160 - 0 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 655360 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 4 - 850 - 3 - 0 - 327680 - -65536 - -32768 6: name: CUSTOM components: - clock_type: GFXCLK values: - 0 - 5 - 1 - 0 - 4 - 800 - 4587520 - -65536 - 0 - clock_type: SOCCLK values: - 0 - 5 - 1 - 0 - 1 - 0 - 3276800 - -65536 - -6553 - clock_type: MEMLK values: - 0 - 5 - 1 - 0 - 4 - 800 - 327680 - -65536 - 0 value_names: - FPS - MinFreqType - MinActiveFreqType - MinActiveFreq - BoosterFreqType - BoosterFreq - PD_Data_limit_c - PD_Data_error_coeff - PD_Data_error_rate_coeff active: 0 ././@LongLink00006440000000000000000000000172000000000000007773Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_rx7600s.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000050731046102023000325370ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 800 - 0 - 0 - 0 - 3 - 1 - 0 - 0 1: name: 3D_FULL_SCREEN components: - clock_type: ~ values: - 0 - 2 - 0 - 1 - 4 - 0 - 650 - 0 - 0 - 0 - 1 - 1 - 0 - 0 2: name: POWER_SAVING components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 3 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 3: name: VIDEO components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 4: name: VR components: - clock_type: ~ values: - 0 - 1 - 0 - 4 - 1 - 1000 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 5: name: COMPUTE components: - clock_type: ~ values: - 0 - 1 - 0 - 4 - 1 - 1000 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 6: name: CUSTOM components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 800 - 0 - 0 - 0 - 3 - 1 - 0 - 0 7: name: WINDOW_3D components: - clock_type: ~ values: - 0 - 2 - 0 - 1 - 4 - 0 - 650 - 0 - 0 - 0 - 3 - 1 - 0 - 0 value_names: - Gfx_ActiveHystLimit - Gfx_IdleHystLimit - Gfx_FPS - Gfx_MinActiveFreqType - Gfx_BoosterFreqType - Gfx_MinActiveFreq - Gfx_BoosterFreq - Fclk_ActiveHystLimit - Fclk_IdleHystLimit - Fclk_FPS - Fclk_MinActiveFreqType - Fclk_BoosterFreqType - Fclk_MinActiveFreq - Fclk_BoosterFreq active: 4 ././@LongLink00006440000000000000000000000172000000000000007773Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_rx7700s.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000050731046102023000325370ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 800 - 0 - 0 - 0 - 3 - 1 - 0 - 0 1: name: 3D_FULL_SCREEN components: - clock_type: ~ values: - 0 - 2 - 0 - 1 - 4 - 0 - 650 - 0 - 0 - 0 - 1 - 1 - 0 - 0 2: name: POWER_SAVING components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 3 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 3: name: VIDEO components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 4: name: VR components: - clock_type: ~ values: - 0 - 1 - 0 - 4 - 1 - 1000 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 5: name: COMPUTE components: - clock_type: ~ values: - 0 - 1 - 0 - 4 - 1 - 1000 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 6: name: CUSTOM components: - clock_type: ~ values: - 0 - 0 - 0 - 1 - 4 - 0 - 800 - 0 - 0 - 0 - 3 - 1 - 0 - 0 7: name: WINDOW_3D components: - clock_type: ~ values: - 0 - 2 - 0 - 1 - 4 - 0 - 650 - 0 - 0 - 0 - 3 - 1 - 0 - 0 value_names: - Gfx_ActiveHystLimit - Gfx_IdleHystLimit - Gfx_FPS - Gfx_MinActiveFreqType - Gfx_BoosterFreqType - Gfx_MinActiveFreq - Gfx_BoosterFreq - Fclk_ActiveHystLimit - Fclk_IdleHystLimit - Fclk_FPS - Fclk_MinActiveFreqType - Fclk_BoosterFreqType - Fclk_MinActiveFreq - Fclk_BoosterFreq active: 0 ././@LongLink00006440000000000000000000000173000000000000007774Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_rx7800xt.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000063121046102023000325340ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: GFXCLK values: - 0 - 1 - 0 - 4 - 800 - 4587520 - -65536 - 0 - clock_type: FCLK values: - 0 - 3 - 0 - 1 - 0 - 3276800 - -65536 - -6553 1: name: 3D_FULL_SCREEN components: - clock_type: GFXCLK values: - 0 - 0 - 1200 - 4 - 650 - 3932160 - -3276 - -65536 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 1310720 - -6553 - -6553 2: name: POWER_SAVING components: - clock_type: GFXCLK values: - 0 - 1 - 0 - 3 - 0 - 5898240 - -65536 - 0 - clock_type: FCLK values: - 0 - 1 - 0 - 1 - 0 - 3407872 - -65536 - -6553 3: name: VIDEO components: - clock_type: GFXCLK values: - 0 - 1 - 0 - 4 - 500 - 4587520 - -65536 - 0 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 3473408 - -65536 - -6553 4: name: VR components: - clock_type: GFXCLK values: - 0 - 2 - 1000 - 1 - 0 - 3276800 - 0 - 0 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 1310720 - -6553 - -6553 5: name: COMPUTE components: - clock_type: GFXCLK values: - 0 - 2 - 1000 - 1 - 0 - 3932160 - 0 - 0 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 1310720 - -6553 - -6553 6: name: CUSTOM components: - clock_type: GFXCLK values: - 0 - 0 - 1200 - 4 - 0 - 655360 - -3276 - -65536 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 1310720 - -6553 - -6553 7: name: WINDOW_3D components: - clock_type: GFXCLK values: - 0 - 0 - 1200 - 4 - 650 - 3932160 - -3276 - -65536 - clock_type: FCLK values: - 0 - 3 - 0 - 3 - 0 - 1310720 - -6553 - -6553 value_names: - FPS - MinActiveFreqType - MinActiveFreq - BoosterFreqType - BoosterFreq - PD_Data_limit_c - PD_Data_error_coeff - PD_Data_error_rate_coeff active: 0 ././@LongLink00006440000000000000000000000171000000000000007772Lustar amdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__parse_full_vega56.snapamdgpu-sysfs-0.19.3/src/gpu_handle/snapshots/amdgpu_sysfs__gpu_handle__power_profile_mode__tests__pa000064400000000000000000000021401046102023000325270ustar 00000000000000--- source: src/gpu_handle/power_profile_mode.rs expression: table --- modes: 0: name: BOOTUP_DEFAULT components: - clock_type: ~ values: - 70 - 60 - 0 - 0 1: name: 3D_FULL_SCREEN components: - clock_type: ~ values: - 70 - 60 - 1 - 3 2: name: POWER_SAVING components: - clock_type: ~ values: - 90 - 60 - 0 - 0 3: name: VIDEO components: - clock_type: ~ values: - 70 - 60 - 0 - 0 4: name: VR components: - clock_type: ~ values: - 70 - 90 - 0 - 0 5: name: COMPUTE components: - clock_type: ~ values: - 30 - 60 - 0 - 6 6: name: CUSTOM components: - clock_type: ~ values: - 0 - 0 - 0 - 0 value_names: - BUSY_SET_POINT - FPS - USE_RLC_BUSY - MIN_ACTIVE_LEVEL active: 0 amdgpu-sysfs-0.19.3/src/hw_mon.rs000064400000000000000000000200661046102023000147700ustar 00000000000000//! Hardware monitoring use crate::{ error::{ErrorContext, ErrorKind}, sysfs::SysFS, Result, }; #[cfg(feature = "serde")] use serde::{Deserialize, Serialize}; use std::{ collections::HashMap, path::{Path, PathBuf}, }; /// Represents a hardware monitor. /// Hardware monitors are used to report real-time information about the device, such as temperatures and power usage. #[derive(Clone, Debug)] pub struct HwMon { path: PathBuf, } impl HwMon { /// Most of the time you may want to access `HwMon`s through the /// [GpuHandle](../gpu_handle/struct.GpuHandle.html) they're bound to. pub fn new_from_path(path: PathBuf) -> Result { let hw_mon = Self { path }; hw_mon.read_file("name")?; Ok(hw_mon) } fn read_temp(&self, file: &str) -> Result { let temp_str = self.read_file(file)?; Ok(temp_str .trim() .parse::() .context("Invalid temperature value (driver bug?)")? / 1000.0) } /// Returns a HashMap of temperatures(in degress celsius), indexed by the labels (example: "edge"). pub fn get_temps(&self) -> HashMap { let mut temps = HashMap::new(); let mut i = 1; while let Ok(current) = self.read_temp(&format!("temp{i}_input")) { let temperature = Temperature { current: Some(current), crit: self.read_temp(&format!("temp{i}_crit")).ok(), crit_hyst: self.read_temp(&format!("temp{i}_crit_hyst")).ok(), }; match self.read_file(format!("temp{i}_label")) { Ok(label) => { temps.insert(label, temperature); } Err(_) => { temps.insert(i.to_string(), temperature); break; } } i += 1; } temps } fn read_clockspeed(&self, file: &str) -> Result { let raw_clockspeed = self.read_file(file)?; Ok(raw_clockspeed .parse::() .context("Unexpected GPU clockspeed (driver bug?)")? / 1000000) } /// Gets the current GFX/compute clockspeed in MHz. pub fn get_gpu_clockspeed(&self) -> Result { self.read_clockspeed("freq1_input") } /// Gets the current memory clockspeed in MHz. pub fn get_vram_clockspeed(&self) -> Result { self.read_clockspeed("freq2_input") } fn read_power(&self, file: &str) -> Result { let raw_power = self.read_file(file)?; Ok(raw_power .parse::() .context("Unexpected power value (driver bug?)")? / 1000000.0) } /// Gets the average power (currently) used by the GPU in watts. pub fn get_power_average(&self) -> Result { self.read_power("power1_average") } /// Gets the instantaneous power (currently) used by the GPU in watts. pub fn get_power_input(&self) -> Result { self.read_power("power1_input") } /// Gets the current power cap of the GPU in watts. pub fn get_power_cap(&self) -> Result { self.read_power("power1_cap") } /// Sets the current power cap of the GPU in watts. pub fn set_power_cap(&self, cap: f64) -> Result<()> { let value = (cap * 1000000.0).round() as i64; self.write_file("power1_cap", value.to_string()) } /// Gets the maximum possible power cap for the GPU in watts. If overclocking is disabled, this is probably the same as the default cap. pub fn get_power_cap_max(&self) -> Result { self.read_power("power1_cap_max") } /// Gets the minimum possible power cap for the GPU in watts. pub fn get_power_cap_min(&self) -> Result { self.read_power("power1_cap_min") } /// Gets the default power cap for the GPU in watts. pub fn get_power_cap_default(&self) -> Result { self.read_power("power1_cap_default") } /// Gets the pulse width modulation fan level. pub fn get_fan_pwm(&self) -> Result { let pwm = self.read_file("pwm1")?; pwm.parse().context("Unexpected PWM (driver bug?)") } /// Gets the minimum pulse width modulation fan level. pub fn get_fan_min_pwm(&self) -> Result { let pwm = self.read_file("pwm1_min")?; pwm.parse().context("Unexpected PWM (driver bug?)") } /// Gets the maximum pulse width modulation fan level. pub fn get_fan_max_pwm(&self) -> Result { let pwm = self.read_file("pwm1_max")?; pwm.parse().context("Unexpected PWM (driver bug?)") } /// Sets the pulse width modulation fan level. pub fn set_fan_pwm(&self, pwm: u8) -> Result<()> { self.write_file("pwm1", pwm.to_string()) } /// Gets the current fan speed in RPM. pub fn get_fan_current(&self) -> Result { let s = self.read_file("fan1_input")?; s.parse().context("Unexpected fan1_input (driver bug?)") } /// Gets the maximum possible fan speed in RPM. pub fn get_fan_max(&self) -> Result { let s = self.read_file("fan1_max")?; s.parse().context("Unexpected fan1_max (driver bug?)") } /// Gets the minimum possible fan speed in RPM. pub fn get_fan_min(&self) -> Result { let s = self.read_file("fan1_min")?; s.parse().context("Unexpected fan1_min (driver bug?)") } /// Gets the currently desired fan speed in RPM. pub fn get_fan_target(&self) -> Result { self.read_file("fan1_target") .map(|s| s.parse().expect("Unexpected fan1_target (driver bug?)")) } /// Sets the desired fan speed in RPM. pub fn set_fan_target(&self, target: u32) -> Result<()> { self.write_file("fan1_target", target.to_string())?; Ok(()) } /// Gets the pulse width modulation control method. pub fn get_fan_control_method(&self) -> Result { self.read_file("pwm1_enable").and_then(|pwm1_enable| { let repr = pwm1_enable .parse() .context("Unexpected pwm1_enable (driver bug?)")?; FanControlMethod::from_repr(repr).ok_or_else(|| { ErrorKind::Unsupported( "Unexpected pwm1_enable (driver bug or unsupported?)".to_owned(), ) .into() }) }) } /// Sets the fan control method (`pwm1_enable`). pub fn set_fan_control_method(&self, method: FanControlMethod) -> Result<()> { let repr = method as u32; self.write_file("pwm1_enable", repr.to_string()) } /// Gets the GPU voltage in millivolts. pub fn get_gpu_voltage(&self) -> Result { self.read_file_parsed("in0_input") } /// Gets the north bridge voltage in millivolts. pub fn get_northbridge_voltage(&self) -> Result { self.read_file_parsed("in1_input") } } impl SysFS for HwMon { fn get_path(&self) -> &Path { &self.path } } /// Temperature reported by the GPU. #[derive(Debug, Clone, Copy, PartialEq)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct Temperature { /// The current temperature. pub current: Option, /// The maximum allowed temperature. pub crit: Option, /// The minimum allowed temperature. pub crit_hyst: Option, } /// The way the fan speed is controlled. #[derive(Debug, Clone, Copy)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] #[cfg_attr(feature = "serde", serde(rename_all = "lowercase"))] pub enum FanControlMethod { /// No fan speed control. None = 0, /// Manual fan speed control via the PWM interface. Manual = 1, /// Automatic fan speed control (by the kernel). Auto = 2, } impl FanControlMethod { /// Create [FanControlMethod] from a digit in the SysFS. pub fn from_repr(repr: u32) -> Option { match repr { 0 => Some(Self::None), 1 => Some(Self::Manual), 2 => Some(Self::Auto), _ => None, } } } amdgpu-sysfs-0.19.3/src/lib.rs000064400000000000000000000003641046102023000142460ustar 00000000000000#![doc = include_str!("../README.md")] #![warn(missing_docs)] #![deny(unsafe_code)] #[cfg(test)] #[macro_use] mod tests; pub mod error; pub mod gpu_handle; pub mod hw_mon; pub mod sysfs; type Result = std::result::Result; amdgpu-sysfs-0.19.3/src/sysfs.rs000064400000000000000000000024421046102023000146460ustar 00000000000000//! Utilities for working with SysFS. use crate::{ error::{Error, ErrorContext}, Result, }; use std::{fmt::Debug, fs, path::Path, str::FromStr}; /// General functionality of a SysFS. pub trait SysFS { /// Gets the path of the current SysFS. fn get_path(&self) -> &Path; /// Reads the content of a file in the `SysFS`. fn read_file(&self, file: impl AsRef + Debug) -> Result { let path = file.as_ref(); Ok(fs::read_to_string(self.get_path().join(path)) .with_context(|| format!("Could not read file {file:?}"))? .replace(char::from(0), "") // Workaround for random null bytes in SysFS entries .trim() .to_owned()) } /// Reads the content of a file and then parses it fn read_file_parsed, E: ToString>(&self, file: &str) -> Result { fs::read_to_string(self.get_path().join(file)) .with_context(|| format!("Could not read file {file}"))? .trim() .parse() .map_err(|err: E| Error::basic_parse_error(err.to_string())) } /// Write to a file in the `SysFS`. fn write_file + Send>(&self, file: &str, contents: C) -> Result<()> { Ok(fs::write(self.get_path().join(file), contents)?) } } amdgpu-sysfs-0.19.3/src/tests.rs000064400000000000000000000002661046102023000146430ustar 00000000000000macro_rules! include_test_data { ($e:expr) => { include_str!(concat!( env!("CARGO_MANIFEST_DIR"), concat!("/tests/data/", $e) )) }; } amdgpu-sysfs-0.19.3/tests/data/internal-4800h/pp_power_profile_mode000064400000000000000000000001371046102023000232730ustar 00000000000000 1 3D_FULL_SCREEN 3 VIDEO* 4 VR 5 COMPUTE 6 CUSTOM amdgpu-sysfs-0.19.3/tests/data/internal-7840u/pp_od_clk_voltage000064400000000000000000000000751046102023000224140ustar 00000000000000OD_SCLK: 0: 800Mhz 1: 2700Mhz OD_RANGE: SCLK: 800MHz 2700Mhz amdgpu-sysfs-0.19.3/tests/data/rx5500xt/pp_od_clk_voltage000064400000000000000000000007051046102023000213320ustar 00000000000000OD_SCLK: 0: 500Mhz 1: 1825Mhz OD_MCLK: 1: 900MHz OD_VDDC_CURVE: 0: 500MHz 710mV 1: 1162MHz 794mV 2: 1825MHz 1115mV OD_RANGE: SCLK: 800Mhz 2200Mhz MCLK: 625Mhz 930Mhz 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2.5GT/s, x1 310Mhz 1: 16.0GT/s, x16 619Mhz * amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_dpm_sclk000064400000000000000000000100001046102023000201440ustar 000000000000000: 500Mhz * 1: 2660Mhz amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_dpm_socclk000064400000000000000000000100001046102023000204660ustar 000000000000000: 480Mhz 1: 800Mhz * 2: 1200Mhz amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_dpm_vclk000064400000000000000000000100001046102023000201470ustar 000000000000000: 0Mhz * 1: 0Mhz * amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_features000064400000000000000000000100001046102023000201660ustar 00000000000000features high: 0x00003763 low: 0xa37ffdff No. Feature Bit : State 00. DPM_PREFETCHER ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_GPO ( 2) : enabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_MP0CLK ( 6) : enabled 07. DPM_LINK ( 7) : enabled 08. DPM_DCEFCLK ( 8) : enabled 09. DPM_XGMI ( 9) : disabled 10. MEM_VDDCI_SCALING (10) : enabled 11. MEM_MVDD_SCALING (11) : enabled 12. DS_GFXCLK (12) : enabled 13. DS_SOCCLK (13) : enabled 14. DS_FCLK (14) : enabled 15. DS_LCLK (15) : enabled 16. DS_DCEFCLK (16) : enabled 17. DS_UCLK (17) : enabled 18. GFX_ULV (18) : enabled 19. FW_DSTATE (19) : enabled 20. GFXOFF (20) : enabled 21. BACO (21) : enabled 22. MM_DPM_PG (22) : enabled 23. PPT (24) : enabled 24. TDC (25) : enabled 25. APCC_PLUS (26) : disabled 26. GTHR (27) : disabled 27. ACDC (28) : disabled 28. VR0HOT (29) : enabled 29. VR1HOT (30) : disabled 30. FW_CTF (31) : enabled 31. FAN_CONTROL (32) : enabled 32. THERMAL (33) : enabled 33. GFX_DCS (34) : disabled 34. RM (35) : disabled 35. LED_DISPLAY (36) : disabled 36. GFX_SS (37) : enabled 37. OUT_OF_BAND_MONITOR (38) : enabled 38. TEMP_DEPENDENT_VMIN (39) : disabled 39. MMHUB_PG (40) : enabled 40. ATHUB_PG (41) : enabled 41. APCC_DFLL (42) : enabled 42. RSMU_SMN_CG (44) : enabled amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_force_state000064400000000000000000000100001046102023000206460ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_mclk_od000064400000000000000000000100001046102023000177600ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_num_states000064400000000000000000000100001046102023000205320ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_od_clk_voltage000064400000000000000000000002071046102023000213340ustar 00000000000000OD_SCLK: 0: 500Mhz 1: 2499Mhz OD_MCLK: 0: 97Mhz 1: 1000MHz OD_VDDGFX_OFFSET: -10mV OD_RANGE: SCLK: 500Mhz 3000Mhz MCLK: 674Mhz 1075Mhz amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_power_profile_mode000064400000000000000000000100001046102023000222300ustar 00000000000000PROFILE_INDEX(NAME) CLOCK_TYPE(NAME) FPS MinFreqType MinActiveFreqType MinActiveFreq BoosterFreqType BoosterFreq PD_Data_limit_c PD_Data_error_coeff PD_Data_error_rate_coeff 0 BOOTUP_DEFAULT*: 0( GFXCLK) 0 5 1 0 4 800 4587520 -65536 0 1( SOCCLK) 0 5 1 0 1 0 3276800 -65536 -6553 2( MEMLK) 0 5 1 0 4 800 327680 -65536 0 1 3D_FULL_SCREEN : 0( GFXCLK) 0 5 0 1600 4 650 5242880 -3276 0 1( SOCCLK) 0 5 1 0 1 0 655360 -65536 -6553 2( MEMLK) 0 5 4 850 4 800 327680 -65536 0 2 POWER_SAVING : 0( GFXCLK) 0 5 1 0 3 0 5898240 -65536 0 1( SOCCLK) 0 5 1 0 1 0 3407872 -65536 -6553 2( MEMLK) 0 5 1 0 3 0 1966080 -65536 0 3 VIDEO : 0( GFXCLK) 0 5 1 0 4 500 4587520 -65536 0 1( SOCCLK) 0 5 1 0 1 0 3473408 -65536 -6553 2( MEMLK) 0 5 1 0 4 500 1966080 -65536 0 4 VR : 0( GFXCLK) 0 5 4 1000 1 0 3276800 0 0 1( SOCCLK) 0 5 1 0 1 0 655360 -65536 -6553 2( MEMLK) 0 5 1 0 4 800 327680 -65536 0 5 COMPUTE : 0( GFXCLK) 0 5 4 1000 1 0 3932160 0 0 1( SOCCLK) 0 5 1 0 1 0 655360 -65536 -6553 2( MEMLK) 0 5 4 850 3 0 327680 -65536 -32768 6 CUSTOM : 0( GFXCLK) 0 5 1 0 4 800 4587520 -65536 0 1( SOCCLK) 0 5 1 0 1 0 3276800 -65536 -6553 2( MEMLK) 0 5 1 0 4 800 327680 -65536 0 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_sclk_od000064400000000000000000000100001046102023000177660ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/pp_table000064400000000000000000000100001046102023000174370ustar 00000000000000¦ "¯ w@€v d °è”òÅòÅ°ÁÁ*Áôàa&=k=k¢çç,ç¸ ¸ ¸ 33H H dnddddddddddôôô¢¢ úè2     [Y_WªrÖÄ Œ ÊT ÿý£c7!ÿ@7dndssss þ8sdd € ä ä \ø@2<€ € € € €?µ7¸>ïg¿O@§?‹î|?¦›„>D4š>C­ ¾=6?ñÍ̬?㥛½oä>ʦ̾!I?À€?rÄz>L‰„¾ÜºC? Š¯?)\½…Îë>ÌÁ¾G F?›jÞ‰?¸>Žu‘>(IW¾ä,ÌÁ¾G F?›jÞ‰?¸>Žu‘>(IW¾ä,wª>îwh¾És.e>Rí¾×/8?Cj¼t?®Ga>s.e>Rí¾×/8?C-?š™Ù>'ƒ£=(í¼çã2?¶j¼t?®Ga>s.e>Rí¾×/8?Côd kÅ=òà°aɢ袰çÁçÁ,*çÁ&”d °è”òÅòÅ°ÁÁ*ÁxLúð € Œ € H H ˆô ô]*ׄ0ÝŠ6ã=é–±Ìç6k2<r¾ H [ô T†=¼Ò½€>š™™>À?33@ @ffF@ ×#=Ý$†=¢E¶=9´È=ÇK·>u“˜=/Ý„¾£’z>åa!½VŽ>År+¾ÀÀÀÀ; E4€7;Ÿ«Í>í >amdgpu-sysfs-0.19.3/tests/data/rx6900xt/product_name000064400000000000000000000100001046102023000203310ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/product_number000064400000000000000000000100001046102023000207010ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/reset_method000064400000000000000000000100001046102023000203330ustar 00000000000000bus amdgpu-sysfs-0.19.3/tests/data/rx6900xt/resource000064400000000000000000000100001046102023000175000ustar 000000000000000x000000f800000000 0x000000fbffffffff 0x000000000014220c 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x000000fc00000000 0x000000fc0fffffff 0x000000000014220c 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x000000000000e000 0x000000000000e0ff 0x0000000000040101 0x00000000fcb00000 0x00000000fcbfffff 0x0000000000040200 0x00000000fcc00000 0x00000000fcc1ffff 0x0000000000046200 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/resource0_resize000064400000000000000000000100001046102023000211410ustar 000000000000000000000000007f00 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/resource2_resize000064400000000000000000000100001046102023000211430ustar 0000000000000000000000000001fe amdgpu-sysfs-0.19.3/tests/data/rx6900xt/revision000064400000000000000000000100001046102023000175070ustar 000000000000000xc0 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/subsystem_device000064400000000000000000000100001046102023000212260ustar 000000000000000x440e amdgpu-sysfs-0.19.3/tests/data/rx6900xt/subsystem_vendor000064400000000000000000000100001046102023000212640ustar 000000000000000x1da2 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/thermal_throttling_logging000064400000000000000000000100001046102023000232710ustar 000000000000000000:0c:00.0: thermal throttling logging enabled, with interval 60 seconds amdgpu-sysfs-0.19.3/tests/data/rx6900xt/uevent000064400000000000000000000100001046102023000171570ustar 00000000000000DRIVER=amdgpu PCI_CLASS=30000 PCI_ID=1002:73BF PCI_SUBSYS_ID=1DA2:440E PCI_SLOT_NAME=0000:0c:00.0 MODALIAS=pci:v00001002d000073BFsv00001DA2sd0000440Ebc03sc00i00 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/unique_id000064400000000000000000000100001046102023000176330ustar 00000000000000946d7e1ef9b172dd amdgpu-sysfs-0.19.3/tests/data/rx6900xt/usbc_pd_fw000064400000000000000000000100001046102023000177640ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/vbios_version000064400000000000000000000100001046102023000205400ustar 00000000000000113-D4121EXT-CO1 amdgpu-sysfs-0.19.3/tests/data/rx6900xt/vendor000064400000000000000000000100001046102023000171460ustar 000000000000000x1002 amdgpu-sysfs-0.19.3/tests/data/rx6950xt/pp_dpm_sclk000064400000000000000000000000231046102023000201550ustar 000000000000000: 0Mhz * 1: 0Mhz *amdgpu-sysfs-0.19.3/tests/data/rx6950xt/uevent000064400000000000000000000000151046102023000171710ustar 00000000000000DRIVER=amdgpuamdgpu-sysfs-0.19.3/tests/data/rx7600s/current_link_speed000064400000000000000000000000171046102023000213440ustar 0000000000000016.0 GT/s PCIe amdgpu-sysfs-0.19.3/tests/data/rx7600s/current_link_width000064400000000000000000000000021046102023000213550ustar 000000000000008 amdgpu-sysfs-0.19.3/tests/data/rx7600s/gpu_busy_percent000064400000000000000000000000021046102023000210340ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/gpu_metrics000064400000000000000000000001701046102023000200060ustar 00000000000000x56<½Uû1€ÿÿ5°Ç` ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿׯÿÿamdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/fan1_enable000064400000000000000000000000021046102023000221570ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/fan1_input000064400000000000000000000000021046102023000220700ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/fan1_max000064400000000000000000000000051046102023000215210ustar 000000000000004900 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/fan1_min000064400000000000000000000000021046102023000215140ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/fan1_target000064400000000000000000000000021046102023000222170ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/freq1_input000064400000000000000000000000021046102023000222610ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/freq1_label000064400000000000000000000000051046102023000222040ustar 00000000000000sclk amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/freq2_input000064400000000000000000000000111046102023000222620ustar 0000000000000096000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/freq2_label000064400000000000000000000000051046102023000222050ustar 00000000000000mclk amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/in0_input000064400000000000000000000000021046102023000217310ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/in0_label000064400000000000000000000000071046102023000216560ustar 00000000000000vddgfx amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/name000064400000000000000000000000071046102023000207510ustar 00000000000000amdgpu amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power/control000064400000000000000000000000051046102023000226430ustar 00000000000000auto amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power/runtime_active_time000064400000000000000000000000021046102023000252140ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power/runtime_status000064400000000000000000000000141046102023000242510ustar 00000000000000unsupported amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power/runtime_suspended_time000064400000000000000000000000021046102023000257330ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_average000064400000000000000000000000101046102023000227320ustar 000000000000001000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_cap000064400000000000000000000000111046102023000220640ustar 0000000000000095000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_cap_default000064400000000000000000000000111046102023000235700ustar 0000000000000095000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_cap_max000064400000000000000000000000111046102023000227310ustar 0000000000000095000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_cap_min000064400000000000000000000000111046102023000227270ustar 0000000000000095000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/power1_label000064400000000000000000000000041046102023000224020ustar 00000000000000PPT amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/pwm1000064400000000000000000000000031046102023000207110ustar 0000000000000076 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/pwm1_enable000064400000000000000000000000021046102023000222160ustar 000000000000002 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/pwm1_max000064400000000000000000000000041046102023000215570ustar 00000000000000255 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/pwm1_min000064400000000000000000000000021046102023000215530ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp1_crit000064400000000000000000000000071046102023000221000ustar 00000000000000100000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp1_crit_hyst000064400000000000000000000000101046102023000231410ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp1_emergency000064400000000000000000000000071046102023000231150ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp1_input000064400000000000000000000000061046102023000222750ustar 0000000000000053000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp1_label000064400000000000000000000000051046102023000222140ustar 00000000000000edge amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp2_crit000064400000000000000000000000071046102023000221010ustar 00000000000000100000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp2_crit_hyst000064400000000000000000000000101046102023000231420ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp2_emergency000064400000000000000000000000071046102023000231160ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp2_input000064400000000000000000000000061046102023000222760ustar 0000000000000054000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp2_label000064400000000000000000000000111046102023000222120ustar 00000000000000junction amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp3_crit000064400000000000000000000000071046102023000221020ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp3_crit_hyst000064400000000000000000000000101046102023000231430ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp3_emergency000064400000000000000000000000071046102023000231170ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp3_input000064400000000000000000000000061046102023000222770ustar 0000000000000060000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/temp3_label000064400000000000000000000000041046102023000222150ustar 00000000000000mem amdgpu-sysfs-0.19.3/tests/data/rx7600s/hwmon/hwmon5/uevent000064400000000000000000000000001046102023000213300ustar 00000000000000amdgpu-sysfs-0.19.3/tests/data/rx7600s/mem_info_vram_vendor000064400000000000000000000000101046102023000216510ustar 00000000000000samsung amdgpu-sysfs-0.19.3/tests/data/rx7600s/power_dpm_force_performance_level000064400000000000000000000000071046102023000244060ustar 00000000000000manual amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_cur_state000064400000000000000000000000021046102023000201470ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_dpm_mclk000064400000000000000000000000551046102023000177540ustar 000000000000000: 96Mhz * 1: 456Mhz 2: 772Mhz 3: 1000Mhz amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_dpm_pcie000064400000000000000000000001101046102023000177360ustar 000000000000000: 2.5GT/s, x1 81Mhz 1: 16.0GT/s, x8 306Mhz * 2: 16.0GT/s, x8 306Mhz * amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_dpm_sclk000064400000000000000000000000371046102023000177620ustar 000000000000000: 255Mhz 1: 0Mhz * 2: 1841Mhz amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_dpm_socclk000064400000000000000000000000411046102023000202770ustar 000000000000000: 417Mhz 1: 711Mhz * 2: 1280Mhz amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_features000064400000000000000000000040611046102023000200050ustar 00000000000000features high: 0x0001a33d low: 0xfbffffff No. Feature Bit : State 00. FW_DATA_READ ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_POWER_OPTIMIZER ( 2) : enabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_MP0CLK ( 6) : enabled 07. DPM_LINK ( 7) : enabled 08. DPM_DCN ( 8) : enabled 09. VMEMP_SCALING ( 9) : enabled 10. VDDIO_MEM_SCALING (10) : enabled 11. DS_GFXCLK (11) : enabled 12. DS_SOCCLK (12) : enabled 13. DS_FCLK (13) : enabled 14. DS_LCLK (14) : enabled 15. DS_DCFCLK (15) : enabled 16. DS_UCLK (16) : enabled 17. GFX_ULV (17) : enabled 18. FW_DSTATE (18) : enabled 19. GFXOFF (19) : enabled 20. BACO (20) : enabled 21. MM_DPM (21) : enabled 22. SOC_MPCLK_DS (22) : enabled 23. BACO_MPCLK_DS (23) : enabled 24. THROTTLERS (24) : enabled 25. SMARTSHIFT (25) : enabled 26. GTHR (26) : disabled 27. ACDC (27) : enabled 28. VR0HOT (28) : enabled 29. FW_CTF (29) : enabled 30. FAN_CONTROL (30) : enabled 31. GFX_DCS (31) : enabled 32. GFX_READ_MARGIN (32) : enabled 33. LED_DISPLAY (33) : disabled 34. GFXCLK_SPREAD_SPECTRUM (34) : enabled 35. OUT_OF_BAND_MONITOR (35) : enabled 36. OPTIMIZED_VMIN (36) : enabled 37. GFX_IMU (37) : enabled 38. BOOT_TIME_CAL (38) : disabled 39. GFX_PCC_DFLL (39) : disabled 40. SOC_CG (40) : enabled 41. DF_CSTATE (41) : enabled 42. GFX_EDC (42) : disabled 43. BOOT_POWER_OPT (43) : disabled 44. CLOCK_POWER_DOWN_BYPASS (44) : disabled 45. DS_VCN (45) : enabled 46. BACO_CG (46) : disabled 47. MEM_TEMP_READ (47) : enabled 48. ATHUB_MMHUB_PG (48) : enabled 49. SOC_PCC (49) : disabled amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_force_state000064400000000000000000000000011046102023000204530ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_num_states000064400000000000000000000000241046102023000203440ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx7600s/pp_power_profile_mode000064400000000000000000000051011046102023000220430ustar 00000000000000 0 BOOTUP_DEFAULT 1 3D_FULL_SCREEN 2 POWER_SAVING 3 VIDEO 4 VR * 5 COMPUTE 6 CUSTOM 7 WINDOW_3D Gfx_ActiveHystLimit 0 0 0 0 0 0 0 0 Gfx_IdleHystLimit 0 2 0 0 1 1 0 2 Gfx_FPS 0 0 0 0 0 0 0 0 Gfx_MinActiveFreqType 1 1 1 1 4 4 1 1 Gfx_BoosterFreqType 4 4 3 4 1 1 4 4 Gfx_MinActiveFreq 0 0 0 0 1000 1000 0 0 Gfx_BoosterFreq 800 650 0 0 0 0 800 650 Fclk_ActiveHystLimit 0 0 0 0 0 0 0 0 Fclk_IdleHystLimit 0 0 0 0 0 0 0 0 Fclk_FPS 0 0 0 0 0 0 0 0 Fclk_MinActiveFreqType 3 1 1 1 1 1 3 3 Fclk_BoosterFreqType 1 1 1 1 1 1 1 1 Fclk_MinActiveFreq 0 0 0 0 0 0 0 0 Fclk_BoosterFreq 0 0 0 0 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amdgpu-sysfs-0.19.3/tests/data/rx7600s/vbios_version000064400000000000000000000000221046102023000203500ustar 00000000000000113-BRT112125.001 amdgpu-sysfs-0.19.3/tests/data/rx7600s/vendor000064400000000000000000000000071046102023000167610ustar 000000000000000x1002 amdgpu-sysfs-0.19.3/tests/data/rx7700s/current_link_speed000064400000000000000000000000171046102023000213450ustar 0000000000000016.0 GT/s PCIe amdgpu-sysfs-0.19.3/tests/data/rx7700s/current_link_width000064400000000000000000000000021046102023000213560ustar 000000000000008 amdgpu-sysfs-0.19.3/tests/data/rx7700s/gpu_busy_percent000064400000000000000000000000021046102023000210350ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/fan1_enable000064400000000000000000000000021046102023000221640ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/fan1_input000064400000000000000000000000021046102023000220750ustar 000000000000000 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amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/in0_input000064400000000000000000000000031046102023000217370ustar 0000000000000018 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/in0_label000064400000000000000000000000071046102023000216630ustar 00000000000000vddgfx amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/name000064400000000000000000000000071046102023000207560ustar 00000000000000amdgpu amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_average000064400000000000000000000000101046102023000227370ustar 000000000000001000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_cap000064400000000000000000000000121046102023000220720ustar 00000000000000100000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_cap_default000064400000000000000000000000121046102023000235760ustar 00000000000000100000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_cap_max000064400000000000000000000000121046102023000227370ustar 00000000000000120000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_cap_min000064400000000000000000000000121046102023000227350ustar 00000000000000100000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/power1_label000064400000000000000000000000041046102023000224070ustar 00000000000000PPT amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/pwm1000064400000000000000000000000031046102023000207160ustar 0000000000000076 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/pwm1_enable000064400000000000000000000000021046102023000222230ustar 000000000000002 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/pwm1_max000064400000000000000000000000041046102023000215640ustar 00000000000000255 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/pwm1_min000064400000000000000000000000021046102023000215600ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp1_crit000064400000000000000000000000071046102023000221050ustar 00000000000000100000 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amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp2_input000064400000000000000000000000061046102023000223030ustar 0000000000000034000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp2_label000064400000000000000000000000111046102023000222170ustar 00000000000000junction amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp3_crit000064400000000000000000000000071046102023000221070ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp3_crit_hyst000064400000000000000000000000101046102023000231500ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp3_emergency000064400000000000000000000000071046102023000231240ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp3_input000064400000000000000000000000061046102023000223040ustar 0000000000000042000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/hwmon/hwmon9/temp3_label000064400000000000000000000000041046102023000222220ustar 00000000000000mem amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_cur_state000064400000000000000000000000021046102023000201500ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_dpm_mclk000064400000000000000000000000551046102023000177550ustar 000000000000000: 96Mhz * 1: 456Mhz 2: 772Mhz 3: 1124Mhz amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_dpm_pcie000064400000000000000000000001061046102023000177440ustar 000000000000000: 2.5GT/s, x1 81Mhz 1: 16.0GT/s, x8 306Mhz 2: 16.0GT/s, x8 306Mhz amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_dpm_sclk000064400000000000000000000000371046102023000177630ustar 000000000000000: 255Mhz 1: 0Mhz * 2: 2208Mhz amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_dpm_socclk000064400000000000000000000000411046102023000203000ustar 000000000000000: 417Mhz 1: 492Mhz * 2: 1280Mhz amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_features000064400000000000000000000040611046102023000200060ustar 00000000000000features high: 0x0001a33d low: 0xfbffffff No. Feature Bit : State 00. FW_DATA_READ ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_POWER_OPTIMIZER ( 2) : enabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_MP0CLK ( 6) : enabled 07. DPM_LINK ( 7) : enabled 08. DPM_DCN ( 8) : enabled 09. VMEMP_SCALING ( 9) : enabled 10. VDDIO_MEM_SCALING (10) : enabled 11. DS_GFXCLK (11) : enabled 12. DS_SOCCLK (12) : enabled 13. DS_FCLK (13) : enabled 14. DS_LCLK (14) : enabled 15. DS_DCFCLK (15) : enabled 16. DS_UCLK (16) : enabled 17. GFX_ULV (17) : enabled 18. FW_DSTATE (18) : enabled 19. GFXOFF (19) : enabled 20. BACO (20) : enabled 21. MM_DPM (21) : enabled 22. SOC_MPCLK_DS (22) : enabled 23. BACO_MPCLK_DS (23) : enabled 24. THROTTLERS (24) : enabled 25. SMARTSHIFT (25) : enabled 26. GTHR (26) : disabled 27. ACDC (27) : enabled 28. VR0HOT (28) : enabled 29. FW_CTF (29) : enabled 30. FAN_CONTROL (30) : enabled 31. GFX_DCS (31) : enabled 32. GFX_READ_MARGIN (32) : enabled 33. LED_DISPLAY (33) : disabled 34. GFXCLK_SPREAD_SPECTRUM (34) : enabled 35. OUT_OF_BAND_MONITOR (35) : enabled 36. OPTIMIZED_VMIN (36) : enabled 37. GFX_IMU (37) : enabled 38. BOOT_TIME_CAL (38) : disabled 39. GFX_PCC_DFLL (39) : disabled 40. SOC_CG (40) : enabled 41. DF_CSTATE (41) : enabled 42. GFX_EDC (42) : disabled 43. BOOT_POWER_OPT (43) : disabled 44. CLOCK_POWER_DOWN_BYPASS (44) : disabled 45. DS_VCN (45) : enabled 46. BACO_CG (46) : disabled 47. MEM_TEMP_READ (47) : enabled 48. ATHUB_MMHUB_PG (48) : enabled 49. SOC_PCC (49) : disabled amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_force_state000064400000000000000000000000011046102023000204540ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_num_states000064400000000000000000000000241046102023000203450ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx7700s/pp_power_profile_mode000064400000000000000000000051011046102023000220440ustar 00000000000000 0 BOOTUP_DEFAULT* 1 3D_FULL_SCREEN 2 POWER_SAVING 3 VIDEO 4 VR 5 COMPUTE 6 CUSTOM 7 WINDOW_3D Gfx_ActiveHystLimit 0 0 0 0 0 0 0 0 Gfx_IdleHystLimit 0 2 0 0 1 1 0 2 Gfx_FPS 0 0 0 0 0 0 0 0 Gfx_MinActiveFreqType 1 1 1 1 4 4 1 1 Gfx_BoosterFreqType 4 4 3 4 1 1 4 4 Gfx_MinActiveFreq 0 0 0 0 1000 1000 0 0 Gfx_BoosterFreq 800 650 0 0 0 0 800 650 Fclk_ActiveHystLimit 0 0 0 0 0 0 0 0 Fclk_IdleHystLimit 0 0 0 0 0 0 0 0 Fclk_FPS 0 0 0 0 0 0 0 0 Fclk_MinActiveFreqType 3 1 1 1 1 1 3 3 Fclk_BoosterFreqType 1 1 1 1 1 1 1 1 Fclk_MinActiveFreq 0 0 0 0 0 0 0 0 Fclk_BoosterFreq 0 0 0 0 0 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amdgpu-sysfs-0.19.3/tests/data/rx7800xt/gpu_od/fan_ctrl/fan_zero_rpm_enable000064400000000000000000000000661046102023000247200ustar 00000000000000FAN_ZERO_RPM_ENABLE: 0 OD_RANGE: ZERO_RPM_ENABLE: 0 1 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/fan1_enable000064400000000000000000000000021046102023000223510ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/fan1_input000064400000000000000000000000021046102023000222620ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/fan1_max000064400000000000000000000000051046102023000217130ustar 000000000000003100 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/fan1_min000064400000000000000000000000021046102023000217060ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/fan1_target000064400000000000000000000000021046102023000224110ustar 000000000000000 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amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/pwm1_max000064400000000000000000000000041046102023000217510ustar 00000000000000255 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/pwm1_min000064400000000000000000000000021046102023000217450ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp1_crit000064400000000000000000000000071046102023000222720ustar 00000000000000100000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp1_crit_hyst000064400000000000000000000000101046102023000233330ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp1_emergency000064400000000000000000000000071046102023000233070ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp1_input000064400000000000000000000000061046102023000224670ustar 0000000000000037000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp1_label000064400000000000000000000000051046102023000224060ustar 00000000000000edge amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp2_crit000064400000000000000000000000071046102023000222730ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp2_crit_hyst000064400000000000000000000000101046102023000233340ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp2_emergency000064400000000000000000000000071046102023000233100ustar 00000000000000115000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp2_input000064400000000000000000000000061046102023000224700ustar 0000000000000043000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp2_label000064400000000000000000000000111046102023000224040ustar 00000000000000junction amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp3_crit000064400000000000000000000000071046102023000222740ustar 00000000000000108000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp3_crit_hyst000064400000000000000000000000101046102023000233350ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp3_emergency000064400000000000000000000000071046102023000233110ustar 00000000000000113000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp3_input000064400000000000000000000000061046102023000224710ustar 0000000000000056000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/hwmon/hwmon4/temp3_label000064400000000000000000000000041046102023000224070ustar 00000000000000mem amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_cur_state000064400000000000000000000000021046102023000203420ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_dpm_mclk000064400000000000000000000000551046102023000201470ustar 000000000000000: 96Mhz * 1: 456Mhz 2: 772Mhz 3: 1218Mhz amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_dpm_pcie000064400000000000000000000001071046102023000201370ustar 000000000000000: 2.5GT/s, x1 78Mhz 1: 5.0GT/s, x4 156Mhz 2: 16.0GT/s, x16 623Mhz * amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_dpm_sclk000064400000000000000000000000371046102023000201550ustar 000000000000000: 500Mhz 1: 0Mhz * 2: 2124Mhz amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_dpm_socclk000064400000000000000000000000411046102023000204720ustar 000000000000000: 300Mhz 1: 750Mhz * 2: 1500Mhz amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_features000064400000000000000000000040611046102023000202000ustar 00000000000000features high: 0x0003ebbc low: 0x71ffffff No. Feature Bit : State 00. FW_DATA_READ ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_POWER_OPTIMIZER ( 2) : enabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_MP0CLK ( 6) : enabled 07. DPM_LINK ( 7) : enabled 08. DPM_DCN ( 8) : enabled 09. VMEMP_SCALING ( 9) : enabled 10. VDDIO_MEM_SCALING (10) : enabled 11. DS_GFXCLK (11) : enabled 12. DS_SOCCLK (12) : enabled 13. DS_FCLK (13) : enabled 14. DS_LCLK (14) : enabled 15. DS_DCFCLK (15) : enabled 16. DS_UCLK (16) : enabled 17. GFX_ULV (17) : enabled 18. FW_DSTATE (18) : enabled 19. GFXOFF (19) : enabled 20. BACO (20) : enabled 21. MM_DPM (21) : enabled 22. SOC_MPCLK_DS (22) : enabled 23. BACO_MPCLK_DS (23) : enabled 24. THROTTLERS (24) : enabled 25. SMARTSHIFT (25) : disabled 26. GTHR (26) : disabled 27. ACDC (27) : disabled 28. VR0HOT (28) : enabled 29. FW_CTF (29) : enabled 30. FAN_CONTROL (30) : enabled 31. GFX_DCS (31) : disabled 32. GFX_READ_MARGIN (32) : disabled 33. LED_DISPLAY (33) : disabled 34. GFXCLK_SPREAD_SPECTRUM (34) : enabled 35. OUT_OF_BAND_MONITOR (35) : enabled 36. OPTIMIZED_VMIN (36) : enabled 37. GFX_IMU (37) : enabled 38. BOOT_TIME_CAL (38) : disabled 39. GFX_PCC_DFLL (39) : enabled 40. SOC_CG (40) : enabled 41. DF_CSTATE (41) : enabled 42. GFX_EDC (42) : disabled 43. BOOT_POWER_OPT (43) : enabled 44. CLOCK_POWER_DOWN_BYPASS (44) : disabled 45. DS_VCN (45) : enabled 46. BACO_CG (46) : enabled 47. MEM_TEMP_READ (47) : enabled 48. ATHUB_MMHUB_PG (48) : enabled 49. SOC_PCC (49) : enabled amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_force_state000064400000000000000000000000011046102023000206460ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_num_states000064400000000000000000000000241046102023000205370ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_od_clk_voltage000064400000000000000000000033041046102023000213350ustar 00000000000000OD_SCLK: 0: 500Mhz 1: 2660Mhz OD_MCLK: 0: 97Mhz 1: 1219MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK: 500Mhz 5000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -450mv 0mv amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_power_profile_mode000064400000000000000000000036221046102023000222440ustar 00000000000000PROFILE_INDEX(NAME) CLOCK_TYPE(NAME) FPS MinActiveFreqType MinActiveFreq BoosterFreqType BoosterFreq PD_Data_limit_c PD_Data_error_coeff PD_Data_error_rate_coeff 0 BOOTUP_DEFAULT*: 0( GFXCLK) 0 1 0 4 800 4587520 -65536 0 1( FCLK) 0 3 0 1 0 3276800 -65536 -6553 1 3D_FULL_SCREEN : 0( GFXCLK) 0 0 1200 4 650 3932160 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 2 POWER_SAVING : 0( GFXCLK) 0 1 0 3 0 5898240 -65536 0 1( FCLK) 0 1 0 1 0 3407872 -65536 -6553 3 VIDEO : 0( GFXCLK) 0 1 0 4 500 4587520 -65536 0 1( FCLK) 0 3 0 3 0 3473408 -65536 -6553 4 VR : 0( GFXCLK) 0 2 1000 1 0 3276800 0 0 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 5 COMPUTE : 0( GFXCLK) 0 2 1000 1 0 3932160 0 0 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 6 CUSTOM : 0( GFXCLK) 0 0 1200 4 0 655360 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 7 WINDOW_3D : 0( GFXCLK) 0 0 1200 4 650 3932160 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/pp_table000064400000000000000000000077771046102023000174720ustar 000000000000000@·«U…vƒ)ˆˆÜÜ  nnddddddddddôôaa ôô2 i_¤ü,ÿÿÿq¼ëÔ°0]#0]#dnnnlsssssxòãCÿÿ›ddddøÀøÀ77ð ð ð ð ð ð ð ð d ö—ݾö(Ü=iop>€?ôb¨?ð§F>ªñÂ?¦ Æ=€?üxœ‚? ¯>Pg?·Ñ@¾xœ‚? ¯>Pg?·Ñ@¾þÔH?Ûù>?þÔH?Ûù>?˜n¢?ƒ@>òÒ?{?˜n¢?ƒ@>ôÐôs v ˜,ÜaÉ­èaÉÔf”fÍÍ””Xè°@ž˜üs ÜÃü˜v ˜v ffÍô¼ð €  ú`ê€?fff?kdd/„áz”?š™¹?33³?×£p?d¶Û£ ð Œ ð ¸ € ˆ¸ ¸ ¸ ¸ ¸ ¸ H H `  À x`"ð#Nœo777A77777FFFKFFFFF$˜’   ôò___Zddddd}vvvq}}}}}èÈ- dìÿúUàð àð àð àð àð  1›X‹>>>>>ÿÿàð àð àð àð àð  1›X‹>>>>>ÿÿ¼¼¼¼¼¼¼¼ªªªª ¸ F F F F F  ¸ F F F F F ffæ?ÍÌ,@@@`@w‹>w‹>TÆï>TÆï>TÆï>d#°¾d#°¾Ô‚W¿Ô‚W¿Ô‚W¿X¼L°U,ð 8J^=9—b<õ>è0_=b¾¼ºñ?Àì=v7¾™ž>U,ð 8J^=9—b<õ>è0_=b¾¼ºñ?Àì=v7¾™ž>U,ð 8J^=9—b<õ>è0_=b¾¼ºñ?Àì=v7¾™ž>l²> =ú$¾l²> =ú$¾l²> =ú$¾˜˜ @˜˜€? A°,ÐôôèÍ– ýo°¼è”Ì h€ H L~ ô°0]#dnnnlsssssÿdôˆôˆ^ddÔÍ>þôôaaöÿöÿôô2͈ˆÜÜddd  ndn°XÐôôè¼h¼îç¿ië>@¼š™*AͤÃCüo=IÁ²¥D´amdgpu-sysfs-0.19.3/tests/data/rx7800xt/uevent000064400000000000000000000002411046102023000171650ustar 00000000000000DRIVER=amdgpu PCI_CLASS=30000 PCI_ID=1002:747E PCI_SUBSYS_ID=1002:0E37 PCI_SLOT_NAME=0000:2f:00.0 MODALIAS=pci:v00001002d0000747Esv00001002sd00000E37bc03sc00i00 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/vbios_version000064400000000000000000000000211046102023000205420ustar 00000000000000113-D7120200-100 amdgpu-sysfs-0.19.3/tests/data/rx7800xt/vendor000064400000000000000000000000071046102023000171540ustar 000000000000000x1002 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/current_link_speed000064400000000000000000000000171046102023000215400ustar 0000000000000016.0 GT/s PCIe amdgpu-sysfs-0.19.3/tests/data/rx7900xt/current_link_width000064400000000000000000000000031046102023000215520ustar 0000000000000016 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_busy_percent000064400000000000000000000000021046102023000212300ustar 000000000000003 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_od/fan_ctrl/acoustic_limit_rpm_threshold000064400000000000000000000000731046102023000266720ustar 00000000000000OD_ACOUSTIC_LIMIT: 3200 OD_RANGE: ACOUSTIC_LIMIT: 500 3200 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_od/fan_ctrl/acoustic_target_rpm_threshold000064400000000000000000000000751046102023000270440ustar 00000000000000OD_ACOUSTIC_TARGET: 1450 OD_RANGE: ACOUSTIC_TARGET: 500 3200 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_od/fan_ctrl/fan_curve000064400000000000000000000002061046102023000226760ustar 00000000000000OD_FAN_CURVE: 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0% OD_RANGE: FAN_CURVE(hotspot temp): 25C 100C FAN_CURVE(fan speed): 15% 100% amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_od/fan_ctrl/fan_minimum_pwm000064400000000000000000000000621046102023000241100ustar 00000000000000FAN_MINIMUM_PWM: 15 OD_RANGE: MINIMUM_PWM: 15 100 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/gpu_od/fan_ctrl/fan_target_temperature000064400000000000000000000001001046102023000254460ustar 00000000000000FAN_TARGET_TEMPERATURE: 83 OD_RANGE: TARGET_TEMPERATURE: 25 105 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/fan1_enable000064400000000000000000000000021046102023000223560ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/fan1_input000064400000000000000000000000021046102023000222670ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/fan1_max000064400000000000000000000000051046102023000217200ustar 000000000000003200 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/fan1_min000064400000000000000000000000021046102023000217130ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/fan1_target000064400000000000000000000000021046102023000224160ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/freq1_input000064400000000000000000000000111046102023000224600ustar 0000000000000031000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/freq1_label000064400000000000000000000000051046102023000224030ustar 00000000000000sclk amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/freq2_input000064400000000000000000000000131046102023000224630ustar 000000000000001249000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/freq2_label000064400000000000000000000000051046102023000224040ustar 00000000000000mclk amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/in0_input000064400000000000000000000000041046102023000221320ustar 00000000000000686 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/in0_label000064400000000000000000000000071046102023000220550ustar 00000000000000vddgfx amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_average000064400000000000000000000000111046102023000231320ustar 0000000000000068000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_cap000064400000000000000000000000121046102023000222640ustar 00000000000000290000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_cap_default000064400000000000000000000000121046102023000237700ustar 00000000000000290000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_cap_max000064400000000000000000000000121046102023000231310ustar 00000000000000333000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_cap_min000064400000000000000000000000121046102023000231270ustar 00000000000000261000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/power1_label000064400000000000000000000000041046102023000226010ustar 00000000000000PPT amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/pwm1000064400000000000000000000000021046102023000211070ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/pwm1_enable000064400000000000000000000000021046102023000224150ustar 000000000000002 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/pwm1_max000064400000000000000000000000041046102023000217560ustar 00000000000000255 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/pwm1_min000064400000000000000000000000021046102023000217520ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp1_crit000064400000000000000000000000071046102023000222770ustar 00000000000000100000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp1_crit_hyst000064400000000000000000000000101046102023000233400ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp1_emergency000064400000000000000000000000071046102023000233140ustar 00000000000000105000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp1_input000064400000000000000000000000061046102023000224740ustar 0000000000000053000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp1_label000064400000000000000000000000051046102023000224130ustar 00000000000000edge amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp2_crit000064400000000000000000000000071046102023000223000ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp2_crit_hyst000064400000000000000000000000101046102023000233410ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp2_emergency000064400000000000000000000000071046102023000233150ustar 00000000000000115000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp2_input000064400000000000000000000000061046102023000224750ustar 0000000000000061000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp2_label000064400000000000000000000000111046102023000224110ustar 00000000000000junction amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp3_crit000064400000000000000000000000071046102023000223010ustar 00000000000000108000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp3_crit_hyst000064400000000000000000000000101046102023000233420ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp3_emergency000064400000000000000000000000071046102023000233160ustar 00000000000000113000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp3_input000064400000000000000000000000061046102023000224760ustar 0000000000000068000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/hwmon/hwmon8/temp3_label000064400000000000000000000000041046102023000224140ustar 00000000000000mem amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_cur_state000064400000000000000000000000021046102023000203430ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_dpm_mclk000064400000000000000000000000551046102023000201500ustar 000000000000000: 96Mhz 1: 456Mhz 2: 772Mhz 3: 1249Mhz * amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_dpm_pcie000064400000000000000000000001151046102023000201370ustar 000000000000000: 16.0GT/s, x16 78Mhz * 1: 16.0GT/s, x16 156Mhz * 2: 16.0GT/s, x16 623Mhz * amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_dpm_sclk000064400000000000000000000000401046102023000201500ustar 000000000000000: 500Mhz 1: 31Mhz * 2: 2219Mhz amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_dpm_socclk000064400000000000000000000000301046102023000204710ustar 000000000000000: 500Mhz 1: 1500Mhz * amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_features000064400000000000000000000040621046102023000202020ustar 00000000000000features high: 0x0003ebb8 low: 0x71ffffff No. Feature Bit : State 00. FW_DATA_READ ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_POWER_OPTIMIZER ( 2) : enabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_MP0CLK ( 6) : enabled 07. DPM_LINK ( 7) : enabled 08. DPM_DCN ( 8) : enabled 09. VMEMP_SCALING ( 9) : enabled 10. VDDIO_MEM_SCALING (10) : enabled 11. DS_GFXCLK (11) : enabled 12. DS_SOCCLK (12) : enabled 13. DS_FCLK (13) : enabled 14. DS_LCLK (14) : enabled 15. DS_DCFCLK (15) : enabled 16. DS_UCLK (16) : enabled 17. GFX_ULV (17) : enabled 18. FW_DSTATE (18) : enabled 19. GFXOFF (19) : enabled 20. BACO (20) : enabled 21. MM_DPM (21) : enabled 22. SOC_MPCLK_DS (22) : enabled 23. BACO_MPCLK_DS (23) : enabled 24. THROTTLERS (24) : enabled 25. SMARTSHIFT (25) : disabled 26. GTHR (26) : disabled 27. ACDC (27) : disabled 28. VR0HOT (28) : enabled 29. FW_CTF (29) : enabled 30. FAN_CONTROL (30) : enabled 31. GFX_DCS (31) : disabled 32. GFX_READ_MARGIN (32) : disabled 33. LED_DISPLAY (33) : disabled 34. GFXCLK_SPREAD_SPECTRUM (34) : disabled 35. OUT_OF_BAND_MONITOR (35) : enabled 36. OPTIMIZED_VMIN (36) : enabled 37. GFX_IMU (37) : enabled 38. BOOT_TIME_CAL (38) : disabled 39. GFX_PCC_DFLL (39) : enabled 40. SOC_CG (40) : enabled 41. DF_CSTATE (41) : enabled 42. GFX_EDC (42) : disabled 43. BOOT_POWER_OPT (43) : enabled 44. CLOCK_POWER_DOWN_BYPASS (44) : disabled 45. DS_VCN (45) : enabled 46. BACO_CG (46) : enabled 47. MEM_TEMP_READ (47) : enabled 48. ATHUB_MMHUB_PG (48) : enabled 49. SOC_PCC (49) : enabled amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_force_state000064400000000000000000000000011046102023000206470ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_num_states000064400000000000000000000000241046102023000205400ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_od_clk_voltage000064400000000000000000000033041046102023000213360ustar 00000000000000OD_SCLK: 0: 500Mhz 1: 2735Mhz OD_MCLK: 0: 97Mhz 1: 1250MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK: 500Mhz 5000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -450mv 0mv amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_power_profile_mode000064400000000000000000000036221046102023000222450ustar 00000000000000PROFILE_INDEX(NAME) CLOCK_TYPE(NAME) FPS MinActiveFreqType MinActiveFreq BoosterFreqType BoosterFreq PD_Data_limit_c PD_Data_error_coeff PD_Data_error_rate_coeff 0 BOOTUP_DEFAULT*: 0( GFXCLK) 0 1 0 4 800 4587520 -65536 0 1( FCLK) 0 3 0 1 0 3276800 -65536 -6553 1 3D_FULL_SCREEN : 0( GFXCLK) 0 0 1200 4 650 3932160 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 2 POWER_SAVING : 0( GFXCLK) 0 1 0 3 0 5898240 -65536 0 1( FCLK) 0 1 0 1 0 3407872 -65536 -6553 3 VIDEO : 0( GFXCLK) 0 1 0 4 500 4587520 -65536 0 1( FCLK) 0 3 0 3 0 3473408 -65536 -6553 4 VR : 0( GFXCLK) 0 2 1000 1 0 3276800 0 0 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 5 COMPUTE : 0( GFXCLK) 0 2 1000 1 0 3932160 0 0 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 6 CUSTOM : 0( GFXCLK) 0 0 1200 4 0 655360 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 7 WINDOW_3D : 0( GFXCLK) 0 0 1200 4 650 3932160 -3276 -65536 1( FCLK) 0 3 0 3 0 1310720 -6553 -6553 amdgpu-sysfs-0.19.3/tests/data/rx7900xt/pp_table000064400000000000000000000077771046102023000174730ustar 000000000000000@6¬R…vƒ'ˆˆÜÜ€ € inddddddddddôôaa ôô2 i_KxÖ¸ @и 'ÿÿÿq¸ë"°RVÀRVdnnnlsssssxòãÿÿ›dddd0À0À77ð ð ð ð ð ð ð ð d š™™= ×#¼€?ôb¨?ð§F>ªñÂ?¦ Æ=€?üxœ‚? ¯>Pg?·Ñ@¾xœ‚? ¯>Pg?·Ñ@¾þÔH?Ûù>?þÔH?Ûù>?˜n¢?ƒ@>òÒ?{?˜n¢?ƒ@>ôÐô3 v ˜ôÜaÉ­èaÉâ”f”fÍÍ””Xè°@ИÊü3 Üâü˜v ˜v ffÍô¼ð € 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amdgpu-sysfs-0.19.3/tests/data/rx7900xt/vendor000064400000000000000000000000071046102023000171550ustar 000000000000000x1002 amdgpu-sysfs-0.19.3/tests/data/rx7900xtx/pp_od_clk_voltage000064400000000000000000000002751046102023000215320ustar 00000000000000OD_SCLK: 0: 500Mhz 1: 3005Mhz OD_MCLK: 0: 97Mhz 1: 1250MHz OD_VDDC_CURVE: 0: 0mv 1: 0mv 2: 0mv 3: 0mv 4: 0mv 5: 0mv OD_RANGE: SCLK: 500Mhz 5000Mhz MCLK: 97Mhz 1500Mhz VDDC_CURVE: -450mv 0mvamdgpu-sysfs-0.19.3/tests/data/rx9070xt/current_link_speed000064400000000000000000000000171046102023000215400ustar 0000000000000032.0 GT/s PCIe amdgpu-sysfs-0.19.3/tests/data/rx9070xt/current_link_width000064400000000000000000000000031046102023000215520ustar 0000000000000016 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_busy_percent000064400000000000000000000000021046102023000212300ustar 000000000000009 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_od/fan_ctrl/acoustic_limit_rpm_threshold000064400000000000000000000000731046102023000266720ustar 00000000000000OD_ACOUSTIC_LIMIT: 3300 OD_RANGE: ACOUSTIC_LIMIT: 500 3650 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_od/fan_ctrl/acoustic_target_rpm_threshold000064400000000000000000000000751046102023000270440ustar 00000000000000OD_ACOUSTIC_TARGET: 1300 OD_RANGE: ACOUSTIC_TARGET: 500 3650 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_od/fan_ctrl/fan_curve000064400000000000000000000002061046102023000226760ustar 00000000000000OD_FAN_CURVE: 0: 0C 0% 1: 0C 0% 2: 0C 0% 3: 0C 0% 4: 0C 0% OD_RANGE: FAN_CURVE(hotspot temp): 25C 100C FAN_CURVE(fan speed): 30% 100% amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_od/fan_ctrl/fan_minimum_pwm000064400000000000000000000000621046102023000241100ustar 00000000000000FAN_MINIMUM_PWM: 30 OD_RANGE: MINIMUM_PWM: 30 100 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/gpu_od/fan_ctrl/fan_target_temperature000064400000000000000000000001001046102023000254460ustar 00000000000000FAN_TARGET_TEMPERATURE: 90 OD_RANGE: TARGET_TEMPERATURE: 25 105 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/freq1_input000064400000000000000000000000111046102023000224530ustar 0000000000000059000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/freq1_label000064400000000000000000000000051046102023000223760ustar 00000000000000sclk amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/freq2_input000064400000000000000000000000111046102023000224540ustar 0000000000000096000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/freq2_label000064400000000000000000000000051046102023000223770ustar 00000000000000mclk amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/in0_input000064400000000000000000000000041046102023000221250ustar 00000000000000696 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/in0_label000064400000000000000000000000071046102023000220500ustar 00000000000000vddgfx amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/name000064400000000000000000000000071046102023000211430ustar 00000000000000amdgpu amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power/control000064400000000000000000000000051046102023000230350ustar 00000000000000auto amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power/runtime_active_time000064400000000000000000000000021046102023000254060ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power/runtime_status000064400000000000000000000000141046102023000244430ustar 00000000000000unsupported amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power/runtime_suspended_time000064400000000000000000000000021046102023000261250ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_average000064400000000000000000000000111046102023000231250ustar 0000000000000019000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_cap000064400000000000000000000000121046102023000222570ustar 00000000000000330000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_cap_default000064400000000000000000000000121046102023000237630ustar 00000000000000330000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_cap_max000064400000000000000000000000121046102023000231240ustar 00000000000000340000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_cap_min000064400000000000000000000000021046102023000231210ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/power1_label000064400000000000000000000000041046102023000225740ustar 00000000000000PPT amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp1_crit000064400000000000000000000000071046102023000222720ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp1_crit_hyst000064400000000000000000000000101046102023000233330ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp1_emergency000064400000000000000000000000071046102023000233070ustar 00000000000000115000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp1_input000064400000000000000000000000061046102023000224670ustar 0000000000000039000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp1_label000064400000000000000000000000051046102023000224060ustar 00000000000000edge amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp2_crit000064400000000000000000000000071046102023000222730ustar 00000000000000110000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp2_crit_hyst000064400000000000000000000000101046102023000233340ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp2_emergency000064400000000000000000000000071046102023000233100ustar 00000000000000115000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp2_input000064400000000000000000000000061046102023000224700ustar 0000000000000042000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp2_label000064400000000000000000000000111046102023000224040ustar 00000000000000junction amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp3_crit000064400000000000000000000000071046102023000222740ustar 00000000000000108000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp3_crit_hyst000064400000000000000000000000101046102023000233350ustar 00000000000000-273150 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp3_emergency000064400000000000000000000000071046102023000233110ustar 00000000000000113000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp3_input000064400000000000000000000000061046102023000224710ustar 0000000000000062000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/temp3_label000064400000000000000000000000041046102023000224070ustar 00000000000000mem amdgpu-sysfs-0.19.3/tests/data/rx9070xt/hwmon/hwmon3/uevent000064400000000000000000000000001046102023000215220ustar 00000000000000amdgpu-sysfs-0.19.3/tests/data/rx9070xt/power_dpm_force_performance_level000064400000000000000000000000051046102023000246000ustar 00000000000000auto amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_cur_state000064400000000000000000000000021046102023000203430ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_dpm_mclk000064400000000000000000000001041046102023000201430ustar 000000000000000: 96Mhz * 1: 456Mhz 2: 772Mhz 3: 875Mhz 4: 1124Mhz 5: 1258Mhz amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_dpm_pcie000064400000000000000000000000611046102023000201370ustar 000000000000000: 2.5GT/s, x16 250Mhz 1: 8.0GT/s, x16 1143Mhz amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_dpm_sclk000064400000000000000000000000371046102023000201560ustar 000000000000000: 500Mhz 1: 0Mhz * 2: 2520Mhz amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_dpm_socclk000064400000000000000000000000301046102023000204710ustar 000000000000000: 417Mhz * 1: 1476Mhz amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_features000064400000000000000000000043321046102023000202020ustar 00000000000000features high: 0x048cf19e low: 0x38fffcfb No. Feature Bit : State 00. FW_DATA_READ ( 0) : enabled 01. DPM_GFXCLK ( 1) : enabled 02. DPM_GFX_POWER_OPTIMIZER ( 2) : disabled 03. DPM_UCLK ( 3) : enabled 04. DPM_FCLK ( 4) : enabled 05. DPM_SOCCLK ( 5) : enabled 06. DPM_LINK ( 6) : enabled 07. DPM_DCN ( 7) : enabled 08. VMEMP_SCALING ( 8) : disabled 09. VDDIO_MEM_SCALING ( 9) : disabled 10. DS_GFXCLK (10) : enabled 11. DS_SOCCLK (11) : enabled 12. DS_FCLK (12) : enabled 13. DS_LCLK (13) : enabled 14. DS_DCFCLK (14) : enabled 15. DS_UCLK (15) : enabled 16. GFX_ULV (16) : enabled 17. FW_DSTATE (17) : enabled 18. GFXOFF (18) : enabled 19. BACO (19) : enabled 20. MM_DPM (20) : enabled 21. SOC_MPCLK_DS (21) : enabled 22. BACO_MPCLK_DS (22) : enabled 23. THROTTLERS (23) : enabled 24. SMARTSHIFT (24) : disabled 25. GTHR (25) : disabled 26. ACDC (26) : disabled 27. VR0HOT (27) : enabled 28. FW_CTF (28) : enabled 29. FAN_CONTROL (29) : enabled 30. GFX_DCS (30) : disabled 31. GFX_READ_MARGIN (31) : disabled 32. LED_DISPLAY (32) : disabled 33. GFXCLK_SPREAD_SPECTRUM (33) : enabled 34. OUT_OF_BAND_MONITOR (34) : enabled 35. OPTIMIZED_VMIN (35) : enabled 36. GFX_IMU (36) : enabled 37. BOOT_TIME_CAL (37) : disabled 38. GFX_PCC_DFLL (38) : disabled 39. SOC_CG (39) : enabled 40. DF_CSTATE (40) : enabled 41. GFX_EDC (41) : disabled 42. BOOT_POWER_OPT (42) : disabled 43. CLOCK_POWER_DOWN_BYPASS (43) : disabled 44. DS_VCN (44) : enabled 45. BACO_CG (45) : enabled 46. MEM_TEMP_READ (46) : enabled 47. ATHUB_MMHUB_PG (47) : enabled 48. SOC_PCC (48) : disabled 49. EDC_PWRBRK (49) : disabled 50. SOC_EDC_XVMIN (50) : enabled 51. GFX_PSM_DIDT (51) : enabled 52. APT_ALL_ENABLE (52) : disabled 53. APT_SQ_THROTTLE (53) : disabled amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_force_state000064400000000000000000000000011046102023000206470ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_num_states000064400000000000000000000000241046102023000205400ustar 00000000000000states: 1 0 default amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_od_clk_voltage000064400000000000000000000002751046102023000213420ustar 00000000000000OD_SCLK_OFFSET: 0Mhz OD_MCLK: 0: 97Mhz 1: 1259MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK_OFFSET: -500Mhz 1000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -200mv 0mv amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_power_profile_mode000064400000000000000000000036221046102023000222450ustar 00000000000000PROFILE_INDEX(NAME) CLOCK_TYPE(NAME) FPS MinActiveFreqType MinActiveFreq BoosterFreqType BoosterFreq PD_Data_limit_c PD_Data_error_coeff PD_Data_error_rate_coeff 0 BOOTUP_DEFAULT : 0( GFXCLK) 0 1 0 4 800 4587520 -65536 0 1( FCLK) 0 3 0 1 0 5898240 -6553 -6553 1 3D_FULL_SCREEN*: 0( GFXCLK) 0 1 0 1 0 5570560 -655 -6553 1( FCLK) 0 1 0 1 0 5898240 -6553 -6553 2 POWER_SAVING : 0( GFXCLK) 0 1 0 3 0 5898240 -65536 0 1( FCLK) 0 1 0 1 0 5898240 -65536 -6553 3 VIDEO : 0( GFXCLK) 0 1 0 4 500 4587520 -65536 0 1( FCLK) 0 1 0 1 0 5898240 -6553 -6553 4 VR : 0( GFXCLK) 0 4 600 1 0 4587520 -16384 0 1( FCLK) 0 1 0 1 0 5898240 -6553 -6553 5 COMPUTE : 0( GFXCLK) 0 4 600 1 0 4587520 -16384 0 1( FCLK) 0 1 0 1 0 5898240 -6553 -6553 6 CUSTOM : 0( GFXCLK) 0 1 0 4 800 4587520 -65536 0 1( FCLK) 0 3 0 1 0 5898240 -6553 -6553 7 WINDOW_3D : 0( GFXCLK) 0 1 0 1 0 5570560 -655 -6553 1( FCLK) 0 3 0 1 0 5898240 -6553 -6553 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/pp_table000064400000000000000000000077771046102023000174730ustar 00000000000000´@t\à ¤<hÂ:\ˆ vûÿZZZä ä ä ìÿôôôôôôûÿiiippppppûüÿ:žñŒÿÿPxiòñdddÀøÀø77ð ä ð ä ð ä ð ä ð ð ‡=o¼°°¨5?ŸåÙ>°°ž?ÓÇKŸ?¸å>¸?Í€?€?ž^y?zí>‡?Ç7P?ÜK>]?}x ”?f½X>Ž?åx ”?f½X>Ž?åä¥?Wx7>? ä¥?Wx7>? ä¥?Wx7>?ôz ôè v ˜ ˜¢Ü »aÉkeëf³ÛJ-£”Ðèeâf³”Ð-£”dДd”ÐД”d3` ”dz ÜÉ` ˜v ÐÐаè°úÈ'°ô°ú š™¹?33³?×£p?d(dúCÂBd  Œ ð ¸ ¸ H H ˆˆˆˆÉˆÉˆúhw€€€€€±Ú1ýX‹&&&&&ÿÿÀü¨0DÀü¨0DÀü¨0DÀü¨0DÀü¨0DÆ7 1 X… ‹€€€€€ÿÿRèÍÌL?ÍÌL?ÍÌL?¼¼¼¼¼¼¼¼¼¼¼¼¼¼¼¼ ¸ ôôôôô ö ÎÎÎÎ΀?ffæ?ÍÌ,@@@fff@’–Š=’–Š=’–Š=’–Š=’–Š=S?o=S?o=S?o=S?o=S?o=èÞC½èÞC½èÞC½èÞC½èÞC½€?333@ìQ8@ÍÌL@fff@XV?XV?XV?ÛÜÈ>ÛÜÈ>öÑ<öÑ<öÑ<™ÓE>™ÓE>Î6—¾M¡“¾¹ˆ¾{ƒ'¿{ƒ'¿ŠŽä=0*i¾»'??ÍÌ >Õ ˆ¾jÞA?õ¹>‚⇾/nC?ΈҼPü?X¢ôôXXÐÐÐèôww¸ôè°ôÀ” Ð    ä ˆð  ð ˆð Ø ô z TT°°JTnnlssssÿnôpôpP(Z9amdgpu-sysfs-0.19.3/tests/data/rx9070xt/uevent000064400000000000000000000002411046102023000171660ustar 00000000000000DRIVER=amdgpu PCI_CLASS=30000 PCI_ID=1002:7550 PCI_SUBSYS_ID=148C:2435 PCI_SLOT_NAME=0000:09:00.0 MODALIAS=pci:v00001002d00007550sv0000148Csd00002435bc03sc00i00 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/vbios_version000064400000000000000000000000221046102023000205440ustar 00000000000000113-EXT108779-100 amdgpu-sysfs-0.19.3/tests/data/rx9070xt/vendor000064400000000000000000000000071046102023000171550ustar 000000000000000x1002 amdgpu-sysfs-0.19.3/tests/data/vangogh/pp_od_clk_voltage000064400000000000000000000002511046102023000214400ustar 00000000000000OD_SCLK: 0: 1600Mhz 1: 1600Mhz OD_RANGE: SCLK: 200Mhz 1600Mhz CCLK: 1400Mhz 3500Mhz CCLK_RANGE in Core0: 0: 1400Mhz 1: 3500Mhzamdgpu-sysfs-0.19.3/tests/data/vega56/aer_dev_correctable000064400000000000000000000001461046102023000214060ustar 00000000000000RxErr 0 BadTLP 0 BadDLLP 0 Rollover 0 Timeout 0 NonFatalErr 0 CorrIntErr 0 HeaderOF 0 TOTAL_ERR_COR 0 amdgpu-sysfs-0.19.3/tests/data/vega56/aer_dev_fatal000064400000000000000000000003261046102023000202100ustar 00000000000000Undefined 0 DLP 0 SDES 0 TLP 0 FCP 0 CmpltTO 0 CmpltAbrt 0 UnxCmplt 0 RxOF 0 MalfTLP 0 ECRC 0 UnsupReq 0 ACSViol 0 UncorrIntErr 0 BlockedTLP 0 AtomicOpBlocked 0 TLPBlockedErr 0 PoisonTLPBlocked 0 TOTAL_ERR_FATAL 0 amdgpu-sysfs-0.19.3/tests/data/vega56/aer_dev_nonfatal000064400000000000000000000003311046102023000207170ustar 00000000000000Undefined 0 DLP 0 SDES 0 TLP 0 FCP 0 CmpltTO 0 CmpltAbrt 0 UnxCmplt 0 RxOF 0 MalfTLP 0 ECRC 0 UnsupReq 0 ACSViol 0 UncorrIntErr 0 BlockedTLP 0 AtomicOpBlocked 0 TLPBlockedErr 0 PoisonTLPBlocked 0 TOTAL_ERR_NONFATAL 0 amdgpu-sysfs-0.19.3/tests/data/vega56/ari_enabled000064400000000000000000000000021046102023000176500ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/vega56/boot_vga000064400000000000000000000000021046102023000172230ustar 000000000000001 amdgpu-sysfs-0.19.3/tests/data/vega56/broken_parity_status000064400000000000000000000000021046102023000216760ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/vega56/class000064400000000000000000000000111046102023000165300ustar 000000000000000x030000 amdgpu-sysfs-0.19.3/tests/data/vega56/consistent_dma_mask_bits000064400000000000000000000000031046102023000224720ustar 0000000000000044 amdgpu-sysfs-0.19.3/tests/data/vega56/current_link_speed000064400000000000000000000000161046102023000213070ustar 000000000000008.0 GT/s PCIe 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amdgpu-sysfs-0.19.3/tests/data/vega56/power_dpm_force_performance_level000064400000000000000000000000051046102023000243500ustar 00000000000000auto amdgpu-sysfs-0.19.3/tests/data/vega56/power_dpm_state000064400000000000000000000000141046102023000206220ustar 00000000000000performance amdgpu-sysfs-0.19.3/tests/data/vega56/power_state000064400000000000000000000000031046102023000177600ustar 00000000000000D0 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_cur_state000064400000000000000000000000021046102023000201130ustar 000000000000001 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_dpm_dcefclk000064400000000000000000000000551046102023000203650ustar 000000000000000: 600Mhz * 1: 720Mhz 2: 847Mhz 3: 900Mhz amdgpu-sysfs-0.19.3/tests/data/vega56/pp_dpm_mclk000064400000000000000000000000551046102023000177200ustar 000000000000000: 167Mhz * 1: 500Mhz 2: 700Mhz 3: 920Mhz amdgpu-sysfs-0.19.3/tests/data/vega56/pp_dpm_pcie000064400000000000000000000000441046102023000177100ustar 000000000000000: 8.0GT/s, x16 * 1: 8.0GT/s, x16 * amdgpu-sysfs-0.19.3/tests/data/vega56/pp_dpm_sclk000064400000000000000000000001371046102023000177270ustar 000000000000000: 852Mhz * 1: 991Mhz 2: 1138Mhz 3: 1269Mhz 4: 1312Mhz 5: 1474Mhz 6: 1538Mhz 7: 1590Mhz amdgpu-sysfs-0.19.3/tests/data/vega56/pp_dpm_socclk000064400000000000000000000001051046102023000202440ustar 000000000000000: 600Mhz * 1: 720Mhz 2: 847Mhz 3: 960Mhz 4: 1028Mhz 5: 1107Mhz amdgpu-sysfs-0.19.3/tests/data/vega56/pp_features000064400000000000000000000027011046102023000177500ustar 00000000000000Current ppfeatures: 0x000000001ba1ff4f FEATURES BITMASK ENABLEMENT DPM_PREFETCHER 0x0000000000000001 Y GFXCLK_DPM 0x0000000000000002 Y UCLK_DPM 0x0000000000000004 Y SOCCLK_DPM 0x0000000000000008 Y UVD_DPM 0x0000000000000010 N VCE_DPM 0x0000000000000020 N ULV 0x0000000000000040 Y MP0CLK_DPM 0x0000000000000080 N LINK_DPM 0x0000000000000100 Y DCEFCLK_DPM 0x0000000000000200 Y AVFS 0x0000000000000400 Y GFXCLK_DS 0x0000000000000800 Y SOCCLK_DS 0x0000000000001000 Y LCLK_DS 0x0000000000002000 Y PPT 0x0000000000004000 Y TDC 0x0000000000008000 Y THERMAL 0x0000000000010000 Y GFX_PER_CU_CG 0x0000000000020000 N RM 0x0000000000040000 N DCEFCLK_DS 0x0000000000080000 N ACDC 0x0000000000100000 N VR0HOT 0x0000000000200000 Y VR1HOT 0x0000000000400000 N FW_CTF 0x0000000000800000 Y LED_DISPLAY 0x0000000001000000 Y FAN_CONTROL 0x0000000002000000 Y FAST_PPT 0x0000000004000000 N DIDT 0x0000000008000000 Y ACG 0x0000000010000000 Y PCC_LIMIT 0x0000000020000000 N amdgpu-sysfs-0.19.3/tests/data/vega56/pp_force_state000064400000000000000000000000011046102023000204170ustar 00000000000000 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_mclk_od000064400000000000000000000000031046102023000175330ustar 0000000000000015 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_num_states000064400000000000000000000000371046102023000203140ustar 00000000000000states: 2 0 boot 1 performance amdgpu-sysfs-0.19.3/tests/data/vega56/pp_od_clk_voltage000064400000000000000000000007401046102023000211070ustar 00000000000000OD_SCLK: 0: 852Mhz 800mV 1: 991Mhz 900mV 2: 1138Mhz 950mV 3: 1269Mhz 1000mV 4: 1312Mhz 1050mV 5: 1474Mhz 1100mV 6: 1538Mhz 1150mV 7: 1590Mhz 1200mV OD_MCLK: 0: 167Mhz 800mV 1: 500Mhz 800mV 2: 700Mhz 900mV 3: 920Mhz 950mV OD_RANGE: SCLK: 852MHz 2400MHz MCLK: 167MHz 1500MHz VDDC: 800mV 1200mV amdgpu-sysfs-0.19.3/tests/data/vega56/pp_power_profile_mode000064400000000000000000000010241046102023000220070ustar 00000000000000NUM MODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL 0 BOOTUP_DEFAULT*: 70 60 0 0 1 3D_FULL_SCREEN : 70 60 1 3 2 POWER_SAVING : 90 60 0 0 3 VIDEO : 70 60 0 0 4 VR : 70 90 0 0 5 COMPUTE : 30 60 0 6 6 CUSTOM : 0 0 0 0 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_sclk_od000064400000000000000000000000021046102023000175400ustar 000000000000000 amdgpu-sysfs-0.19.3/tests/data/vega56/pp_table000064400000000000000000000012471046102023000172250ustar 00000000000000§\ï,H€©ðI2\@7”´zŒ­c™^4ˆh6q „¶èL~°â„`ê@ÜJw‘l°ÐL€ƒˆ¼´ï€È?ÈXm`ê@ÜJ_(n,Éø €8_ô‘аÀÔl9$^ü…¬¼4Ðhn—ì£h< { GpuHandle::get_pci_id, Some(("1002", "67DF")), GpuHandle::get_pci_subsys_id, Some(("1DA2", "E387")), }, driver => { GpuHandle::get_driver, "amdgpu" }, busy_percent => { GpuHandle::get_busy_percent, Ok(11) }, vram => { GpuHandle::get_total_vram, Ok(4096 * 1024 * 1024), GpuHandle::get_used_vram, Ok(512 * 1024 * 1024), }, vbios => { GpuHandle::get_vbios_version, Ok("113-1E3871U-O4C".to_owned()) }, performance_level => { GpuHandle::get_power_force_performance_level, Ok(PerformanceLevel::Auto), }, link => { GpuHandle::get_current_link_speed, Ok("8.0 GT/s PCIe".to_owned()), GpuHandle::get_current_link_width, Ok("16".to_owned()), GpuHandle::get_max_link_speed, Ok("8.0 GT/s PCIe".to_owned()), GpuHandle::get_max_link_width, Ok("16".to_owned()), }, pp_dpm_sclk => { GpuHandle::get_core_clock_levels, Ok(PowerLevels { levels: vec![ 300, 600, 900, 1145, 1215, 1257, 1300, 1366 ], active: Some(2) }) }, pp_dpm_mclk => { GpuHandle::get_memory_clock_levels, Ok(PowerLevels { levels: vec![ 300, 1000, 1750, ], active: Some(2) }) }, pp_dpm_pcie => { GpuHandle::get_pcie_clock_levels, Ok(PowerLevels { levels: [ "2.5GT/s, x8", "8.0GT/s, x16" ].map(str::to_owned).to_vec(), active: Some(1) }) } } test_with_hw_mon! { "rx580", fan_info => { HwMon::get_fan_pwm, Ok(35), HwMon::get_fan_current, Ok(595), HwMon::get_fan_target, Ok(595), HwMon::get_fan_min, Ok(0), HwMon::get_fan_max, Ok(3200), }, temperatures => { HwMon::get_temps, HashMap::from([( "edge".to_owned(), Temperature { current: Some(44.0), crit: Some(94.0), crit_hyst: Some(-273.15) } )]) }, gpu_voltage => { HwMon::get_gpu_voltage, Ok(975) }, } amdgpu-sysfs-0.19.3/tests/rx6900xt.rs000064400000000000000000000005041046102023000153730ustar 00000000000000use amdgpu_sysfs::gpu_handle::{GpuHandle, PowerLevels}; mod sysfs; test_with_handle! { "rx6900xt", pp_dpm_sclk => { GpuHandle::get_core_clock_levels, Ok(PowerLevels { levels: vec![ 500, 2660 ], active: Some(0) }) }, } amdgpu-sysfs-0.19.3/tests/rx6950xt.rs000064400000000000000000000004621046102023000154030ustar 00000000000000mod sysfs; use amdgpu_sysfs::gpu_handle::{GpuHandle, PowerLevels}; test_with_handle! { "rx6950xt", invalid_dpm_sclk => { GpuHandle::get_core_clock_levels, Ok(PowerLevels { levels: vec![ 0, 0 ], active: None, }) }, } amdgpu-sysfs-0.19.3/tests/rx7800xt.rs000064400000000000000000000021011046102023000153660ustar 00000000000000mod sysfs; use amdgpu_sysfs::gpu_handle::{ fan_control::{FanCurve, FanCurveRanges, FanInfo}, GpuHandle, }; test_with_handle! { "rx7800xt", get_fan_acoustic_limit => { GpuHandle::get_fan_acoustic_limit, Ok(FanInfo { current: 2450, allowed_range: Some((500, 3100)) }) }, get_fan_acoustic_target => { GpuHandle::get_fan_acoustic_target, Ok(FanInfo { current: 2200, allowed_range: Some((500, 3100)) }) }, get_fan_target_temperature => { GpuHandle::get_fan_target_temperature, Ok(FanInfo { current: 95, allowed_range: Some((25, 110)) }) }, get_fan_minimum_pwm => { GpuHandle::get_fan_minimum_pwm, Ok(FanInfo { current: 97, allowed_range: Some((20, 100)) }) }, get_fan_curve => { GpuHandle::get_fan_curve, Ok(FanCurve { points: vec![(0, 0); 5].into_boxed_slice(), allowed_ranges: Some(FanCurveRanges {temperature_range: 25..=100, speed_range: 20..=100 })}) }, get_fan_zero_rpm => { GpuHandle::get_fan_zero_rpm_enable, Ok(false), } } amdgpu-sysfs-0.19.3/tests/rx7900xt.rs000064400000000000000000000035051046102023000154000ustar 00000000000000#![allow(clippy::redundant_closure_call)] mod sysfs; use amdgpu_sysfs::gpu_handle::{ fan_control::{FanCurve, FanCurveRanges, FanInfo}, GpuHandle, }; test_with_handle! { "rx7900xt", get_fan_acoustic_limit => { GpuHandle::get_fan_acoustic_limit, Ok(FanInfo { current: 3200, allowed_range: Some((500, 3200)) }) }, get_fan_acoustic_target => { GpuHandle::get_fan_acoustic_target, Ok(FanInfo { current: 1450, allowed_range: Some((500, 3200)) }) }, get_fan_target_temperature => { GpuHandle::get_fan_target_temperature, Ok(FanInfo { current: 83, allowed_range: Some((25, 105)) }) }, get_fan_minimum_pwm => { GpuHandle::get_fan_minimum_pwm, Ok(FanInfo { current: 15, allowed_range: Some((15, 100)) }) }, get_fan_curve => { GpuHandle::get_fan_curve, Ok(FanCurve { points: vec![(0, 0); 5].into_boxed_slice(), allowed_ranges: Some(FanCurveRanges {temperature_range: 25..=100, speed_range: 15..=100 })}) }, set_invalid_fan_curve => { |gpu_handle: &GpuHandle| { let mut curve = gpu_handle.get_fan_curve().unwrap(); curve.points[0].0 = 5; curve.points[0].1 = 0; gpu_handle.set_fan_curve(&curve).unwrap_err().to_string() }, "not allowed: Temperature value 5 is outside of the allowed range 25..=100", }, set_valid_fan_curve => { |gpu_handle: &GpuHandle| { let mut curve = gpu_handle.get_fan_curve().unwrap(); curve.points[0] = (25, 15); curve.points[1] = (40, 30); curve.points[2] = (60, 65); curve.points[3] = (70, 80); curve.points[4] = (85, 100); let handle = gpu_handle.set_fan_curve(&curve)?; handle.commit() }, Ok(()) } } amdgpu-sysfs-0.19.3/tests/sysfs/mod.rs000064400000000000000000000047761046102023000160140ustar 00000000000000use amdgpu_sysfs::{gpu_handle::GpuHandle, sysfs::SysFS}; use rust_embed::RustEmbed; use std::fs; use tempfile::{tempdir, TempDir}; #[derive(RustEmbed)] #[folder = "tests/data/"] struct Asset; pub struct MockSysFs { temp_dir: TempDir, } impl MockSysFs { pub fn new(name: &str) -> Self { let temp_dir = tempdir().expect("Failed to create temp dir"); let path = temp_dir.path(); let path_prefix = format!("{name}/"); for file_name in Asset::iter() { if let Some(stripped_name) = file_name.strip_prefix(&path_prefix) { let target_path = path.join(stripped_name); if let Some(parent) = target_path.parent() { fs::create_dir_all(parent).expect("Could not create parent dir in temp dir"); } let contents = Asset::get(&file_name) .expect("Could not read file from embedded fs") .data; fs::write(target_path, contents).expect("Could not write contents to temp dir"); } } Self { temp_dir } } } impl SysFS for MockSysFs { fn get_path(&self) -> &std::path::Path { self.temp_dir.path() } } pub fn create_mock_gpu_handle(name: &str) -> (GpuHandle, MockSysFs) { let mockfs = MockSysFs::new(name); ( GpuHandle::new_from_path(mockfs.get_path().to_path_buf()) .expect("Failed to create GPU handle"), mockfs, ) } #[macro_export] macro_rules! test_with_handle { ($sysfs_name:expr, $($test_name:ident => {$($code:expr, $expected:expr),* $(,)?}),* $(,)?) => { $( #[test] fn $test_name() { let (handle, _mockfs) = $crate::sysfs::create_mock_gpu_handle($sysfs_name); $( let value = $code(&handle); pretty_assertions::assert_eq!(value, $expected); )* } )* }; } #[macro_export] macro_rules! test_with_hw_mon { ($sysfs_name:expr, $($test_name:ident => {$($code:expr, $expected:expr),* $(,)?}),* $(,)?) => { $( #[test] fn $test_name() { let (handle, _mockfs) = $crate::sysfs::create_mock_gpu_handle($sysfs_name); let hw_mon = handle.hw_monitors.first().expect("Handle has no hw monitor"); $( let value = $code(&hw_mon); pretty_assertions::assert_eq!(value, $expected); )* } )* }; } amdgpu-sysfs-0.19.3/tests/vega56.rs000064400000000000000000000060101046102023000151420ustar 00000000000000mod sysfs; use amdgpu_sysfs::{ gpu_handle::{GpuHandle, PerformanceLevel, PowerLevels}, hw_mon::{HwMon, Temperature}, }; use std::collections::HashMap; test_with_handle! { "vega56", pci_ids => { GpuHandle::get_pci_id, Some(("1002", "687F")), GpuHandle::get_pci_subsys_id, Some(("1043", "0555")), }, driver => { GpuHandle::get_driver, "amdgpu" }, busy_percent => { GpuHandle::get_busy_percent, Ok(0) }, vram => { GpuHandle::get_total_vram, Ok(8176 * 1024 * 1024), GpuHandle::get_used_vram, Ok(16224 * 1024), }, vbios => { GpuHandle::get_vbios_version, Ok("115-D050PIL-100".to_owned()) }, performance_level => { GpuHandle::get_power_force_performance_level, Ok(PerformanceLevel::Auto), }, link => { GpuHandle::get_current_link_speed, Ok("8.0 GT/s PCIe".to_owned()), GpuHandle::get_current_link_width, Ok("16".to_owned()), GpuHandle::get_max_link_speed, Ok("8.0 GT/s PCIe".to_owned()), GpuHandle::get_max_link_width, Ok("16".to_owned()), }, vram_vendor => { GpuHandle::get_vram_vendor, Ok("hynix".to_owned()), }, pp_dpm_sclk => { GpuHandle::get_core_clock_levels, Ok(PowerLevels { levels: vec![ 852, 991, 1138, 1269, 1312, 1474, 1538, 1590 ], active: Some(0) }) }, pp_dpm_mclk => { GpuHandle::get_memory_clock_levels, Ok(PowerLevels { levels: vec![ 167, 500, 700, 920, ], active: Some(0) }) }, pp_dpm_pcie => { GpuHandle::get_pcie_clock_levels, Ok(PowerLevels { levels: [ "8.0GT/s, x16", "8.0GT/s, x16" ].map(str::to_owned).to_vec(), active: None }) } } test_with_hw_mon! { "vega56", fan_info => { HwMon::get_fan_pwm, Ok(0), HwMon::get_fan_current, Ok(5), HwMon::get_fan_target, Ok(5), HwMon::get_fan_min, Ok(0), HwMon::get_fan_max, Ok(3500), }, temperatures => { HwMon::get_temps, HashMap::from([ ( "edge".to_owned(), Temperature { current: Some(38.0), crit: Some(85.0), crit_hyst: Some(-273.15) } ), ( "junction".to_owned(), Temperature { current: Some(38.0), crit: Some(105.0), crit_hyst: Some(-273.15) } ), ( "mem".to_owned(), Temperature { current: Some(39.0), crit: Some(95.0), crit_hyst: Some(-273.15) } ) ]) }, gpu_voltage => { HwMon::get_gpu_voltage, Ok(762) }, }