pax_global_header00006660000000000000000000000064145713306120014514gustar00rootroot0000000000000052 comment=ab37c5a8d43978057b85f02d0d271a08dd6291e8 libudis86-0+20221013/000077500000000000000000000000001457133061200137145ustar00rootroot00000000000000libudis86-0+20221013/BUILD-WINDOWS000066400000000000000000000052451457133061200156340ustar00rootroot00000000000000Build Instructions for Visual Studio ************************************ Note: it is important to perform the build at least once before attempting to open the solution in Visual Studio so that the build process can generate the itab.c/itab.h files from the itab.py Python script. Prerequisites ============= The buildVS2010.bat and build.proj MSBuild project have the following prerequisites: 1. Visual Studio 2010 with VC++ (full edition is required to compile for x64). A later compiler can be used however the build batch file will need to be changed to run the correct vcvarsall.bat. 2. Python 2.7 - although a later version should work, the build script has been configured to expect "python.exe" to be installed in "c:\python27\". How to Build ============ Ensure all prerequisites are in place and then run "buildVS2010.bat". MSBuild will run the "Clean" target for the "udis86.sln" solution and then build the following targets for "build.proj" MSBuild project: 1. Clean - (remove the "./Build" directory) 2. BuildRelease_x86 - build the release configuration for x86 3. BuildRelease_x64 - build the release configuration for x64 4. PostBuild - copy license and headers to build directory If a debug version is required, the batch file can be modified to also build the BuildDebug_x86 and BuildDebug_x64 targets. If Visual Studio Express is being used you will need to comment out the x64 target(s). Build Output ============ The Build directory has the following structure (if building all Release and Debug targets): . +-- Bin ¦   +-- Debug ¦   ¦   +-- x64 ¦   ¦   ¦   +-- libudis86.dll ¦   ¦   ¦   +-- libudis86.ilk ¦   ¦   ¦   +-- libudis86.pdb ¦   ¦   ¦   +-- udcli.exe ¦   ¦   ¦   +-- udcli.ilk ¦   ¦   ¦   +-- udcli.pdb ¦   ¦   +-- x86 ¦   ¦   +-- libudis86.dll ¦   ¦   +-- libudis86.ilk ¦   ¦   +-- libudis86.pdb ¦   ¦   +-- udcli.exe ¦   ¦   +-- udcli.ilk ¦   ¦   +-- udcli.pdb ¦   +-- x64 ¦   ¦   +-- libudis86.dll ¦   ¦   +-- libudis86.pdb ¦   ¦   +-- udcli.exe ¦   ¦   +-- udcli.pdb ¦   +-- x86 ¦   +-- libudis86.dll ¦   +-- libudis86.pdb ¦   +-- udcli.exe ¦   +-- udcli.pdb +-- Include ¦   +-- libudis86 ¦   ¦   +-- itab.h ¦   ¦   +-- types.h ¦   +-- udis86.h +-- Lib ¦   +-- Debug ¦   ¦   +-- x64 ¦   ¦   ¦   +-- libudis86.lib ¦   ¦   +-- x86 ¦   ¦   +-- libudis86.lib ¦   +-- x64 ¦   ¦   +-- libudis86.lib ¦   +-- x86 ¦   +-- libudis86.lib +-- LICENSE +-- README libudis86-0+20221013/BuildVS2010/000077500000000000000000000000001457133061200155275ustar00rootroot00000000000000libudis86-0+20221013/BuildVS2010/README.txt000066400000000000000000000006601457133061200172270ustar00rootroot00000000000000Build notes for Windows: - If you don't have python installed at C:\Python27, edit build.proj accordingly - Execute buildVS2010.bat - If you got VS2012, this will fail. - Edit/Copy the build script, so that it finds vcvars32.bat (just needed to replace 10.0 with 11.0). - Open the solution and update the toolset. - Compile with the build script and ignore an error regarding ./Win32 not deletable. - Be done with it :)libudis86-0+20221013/BuildVS2010/build.proj000066400000000000000000000050751457133061200175310ustar00rootroot00000000000000 .\Deploy .\Build libudis86-0+20221013/BuildVS2010/buildVS2010.bat000066400000000000000000000004771457133061200201020ustar00rootroot00000000000000echo off call "C:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\vcvarsall.bat" x86_amd64 msbuild.exe udis86.sln /t:Clean msbuild.exe build.proj /t:Clean,BuildRelease_x86,BuildRelease_x64,PostBuild REM msbuild.exe build.proj /t:Clean,BuildRelease_x86,BuildRelease_x64,BuildDebug_x86,BuildDebug_x64,PostBuild pauselibudis86-0+20221013/BuildVS2010/libudis86.vcxproj000066400000000000000000000344211457133061200207610ustar00rootroot00000000000000 Debug-DLL Win32 Debug-DLL x64 Debug Win32 Debug x64 Release-DLL Win32 Release-DLL x64 Release Win32 Release x64 {D5C34A21-7218-4A08-9578-1EBB35280A42} Win32Proj libudis86 StaticLibrary true Unicode DynamicLibrary true Unicode StaticLibrary true Unicode DynamicLibrary true Unicode StaticLibrary false true Unicode DynamicLibrary false true Unicode StaticLibrary false true Unicode DynamicLibrary false true Unicode true $(SolutionDir)Build\Lib\Debug\x86\ $(Platform)\$(Configuration)\ true $(SolutionDir)Build\Bin\Debug\x86\ $(Platform)\$(Configuration)\ true $(SolutionDir)Build\Lib\Debug\x64\ true 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Level3 MaxSpeed true true WIN32;NDEBUG;_WINDOWS;_USRDLL;LIBUDIS86_EXPORTS;%(PreprocessorDefinitions) Windows true true true Level3 MaxSpeed true true WIN32;NDEBUG;_WINDOWS;_USRDLL;LIBUDIS86_EXPORTS;%(PreprocessorDefinitions) Windows true true true libudis86-0+20221013/BuildVS2010/libudis86.vcxproj.filters000066400000000000000000000045161457133061200224320ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hpp;hxx;hm;inl;inc;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms {67a7943a-ad63-4da1-be6b-daf8a3fef1d6} {a0eee912-4b82-493a-8c43-3b712061afb1} Source Files Source Files Source Files Source Files Source Files Source Files\Generated Header Files Header Files Header Files Header Files Header Files Header Files\Generated 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libudis86.lib;%(AdditionalDependencies) Level3 MaxSpeed true true WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) Console true true true libudis86-0+20221013/BuildVS2010/udcli.vcxproj.filters000066400000000000000000000020331457133061200217110ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hpp;hxx;hm;inl;inc;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files Header Files libudis86-0+20221013/BuildVS2010/udis86.sln000066400000000000000000000060421457133061200173710ustar00rootroot00000000000000 Microsoft Visual Studio Solution File, Format Version 11.00 # Visual Studio 2010 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "libudis86", "libudis86.vcxproj", "{D5C34A21-7218-4A08-9578-1EBB35280A42}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "udcli", "udcli.vcxproj", "{620E885C-DA4A-4296-AFEB-AFB0077EFA14}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 Debug|x64 = Debug|x64 Debug-DLL|Win32 = Debug-DLL|Win32 Debug-DLL|x64 = Debug-DLL|x64 Release|Win32 = Release|Win32 Release|x64 = Release|x64 Release-DLL|Win32 = Release-DLL|Win32 Release-DLL|x64 = Release-DLL|x64 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug|Win32.ActiveCfg = Debug|Win32 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug|Win32.Build.0 = Debug|Win32 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug|x64.ActiveCfg = Debug|x64 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug|x64.Build.0 = Debug|x64 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug-DLL|Win32.ActiveCfg = Debug-DLL|Win32 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug-DLL|Win32.Build.0 = Debug-DLL|Win32 {D5C34A21-7218-4A08-9578-1EBB35280A42}.Debug-DLL|x64.ActiveCfg = Debug-DLL|x64 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Debug|x64 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Debug-DLL|Win32.ActiveCfg = Debug-DLL|Win32 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Debug-DLL|x64.ActiveCfg = Debug-DLL|x64 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release|Win32.ActiveCfg = Release|Win32 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release|Win32.Build.0 = Release|Win32 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release|x64.ActiveCfg = Release|x64 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release|x64.Build.0 = Release|x64 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release-DLL|Win32.ActiveCfg = Release-DLL|Win32 {620E885C-DA4A-4296-AFEB-AFB0077EFA14}.Release-DLL|x64.ActiveCfg = Release-DLL|x64 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE EndGlobalSection EndGlobal libudis86-0+20221013/CHANGES000066400000000000000000000030751457133061200147140ustar00rootroot00000000000000v1.7.2 * Clean up input handling, removing unnecessary caching of input, which should speed up things. * Add the missing ud_insn_mnemonic api function. * Rename ud_opr_isgpr to ud_opr_is_gpr. * Fix decoding of relative jumps. * Fix build with automake-1.14 * Minor fix to AT&T syntax (missing "$" prefix for immedaites) * Add a new api checker (tests/libcheck.c). * Add a standalone script for diff-testing (tests/difftest.sh) * Refinements to the documentation. Acknowledgements: Brendan Long (https://github.com/brendanlong) radare (https://github.com/radare) Sergey Basalaev (https://github.com/SBasalaev) ebfe (https://github.com/ebfe) v1.7.1 * Full support for SSSE3, SSE4.1, SSE4.2, SMX, AES. * New Sphinx-doc/RST based documentation. * New api for client size symbol resolver. * Visual Studio 2010 Build Support. * Added an operand tester. * Python 3.0 compatibility changes. * Minor fixes to AT&T syntax. * Fix install directory for data files. * Many bug fixes, and optable updates. * Add Texinfo document (make install-info). Acknowledgements: L Peter Deutsch (https://github.com/ghghost) Bjoern Doebel (https://github.com/bjoernd) Justin Stenning (http://github.com/spazzarama) Jamie Iles (https://github.com/jamieiles) Stephen Fewer (https://github.com/stephenfewer) Piotr Gaczkowski (https://github.com/DoomHammer) Evan Pheonix mbarbu (https://github.com/mbarbu) Please see the commit logs for change information for older releases libudis86-0+20221013/CMakeLists.txt000066400000000000000000000004661457133061200164620ustar00rootroot00000000000000cmake_minimum_required(VERSION 3.12) project(udis86 LANGUAGES C) include_directories("${PROJECT_SOURCE_DIR}") add_subdirectory(libudis86) add_subdirectory(udcli) add_library(udis86 INTERFACE) target_include_directories(udis86 INTERFACE ${CMAKE_SOURCE_DIR}) target_link_libraries(udis86 INTERFACE libudis86) libudis86-0+20221013/INSTALL000066400000000000000000000223101457133061200147430ustar00rootroot00000000000000Installation Instructions ************************* Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc. This file is free documentation; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Basic Installation ================== Briefly, the shell commands `./configure; make; make install' should configure, build, and install this package. The following more-detailed instructions are generic; see the `README' file for instructions specific to this package. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses those values to create a `Makefile' in each directory of the package. It may also create one or more `.h' files containing system-dependent definitions. Finally, it creates a shell script `config.status' that you can run in the future to recreate the current configuration, and a file `config.log' containing compiler output (useful mainly for debugging `configure'). It can also use an optional file (typically called `config.cache' and enabled with `--cache-file=config.cache' or simply `-C') that saves the results of its tests to speed up reconfiguring. Caching is disabled by default to prevent problems with accidental use of stale cache files. If you need to do unusual things to compile the package, please try to figure out how `configure' could check whether to do them, and mail diffs or instructions to the address given in the `README' so they can be considered for the next release. If you are using the cache, and at some point `config.cache' contains results you don't want to keep, you may remove or edit it. The file `configure.ac' (or `configure.in') is used to create `configure' by a program called `autoconf'. You need `configure.ac' if you want to change it or regenerate `configure' using a newer version of `autoconf'. The simplest way to compile this package is: 1. `cd' to the directory containing the package's source code and type `./configure' to configure the package for your system. Running `configure' might take a while. While running, it prints some messages telling which features it is checking for. 2. Type `make' to compile the package. 3. Optionally, type `make check' to run any self-tests that come with the package. 4. Type `make install' to install the programs and any data files and documentation. 5. You can remove the program binaries and object files from the source code directory by typing `make clean'. To also remove the files that `configure' created (so you can compile the package for a different kind of computer), type `make distclean'. There is also a `make maintainer-clean' target, but that is intended mainly for the package's developers. If you use it, you may have to get all sorts of other programs in order to regenerate files that came with the distribution. Compilers and Options ===================== Some systems require unusual options for compilation or linking that the `configure' script does not know about. Run `./configure --help' for details on some of the pertinent environment variables. You can give `configure' initial values for configuration parameters by setting variables in the command line or in the environment. Here is an example: ./configure CC=c99 CFLAGS=-g LIBS=-lposix *Note Defining Variables::, for more details. Compiling For Multiple Architectures ==================================== You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you can use GNU `make'. `cd' to the directory where you want the object files and executables to go and run the `configure' script. `configure' automatically checks for the source code in the directory that `configure' is in and in `..'. With a non-GNU `make', it is safer to compile the package for one architecture at a time in the source code directory. After you have installed the package for one architecture, use `make distclean' before reconfiguring for another architecture. Installation Names ================== By default, `make install' installs the package's commands under `/usr/local/bin', include files under `/usr/local/include', etc. You can specify an installation prefix other than `/usr/local' by giving `configure' the option `--prefix=PREFIX'. You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you pass the option `--exec-prefix=PREFIX' to `configure', the package uses PREFIX as the prefix for installing programs and libraries. Documentation and other data files still use the regular prefix. In addition, if you use an unusual directory layout you can give options like `--bindir=DIR' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. If the package supports it, you can cause programs to be installed with an extra prefix or suffix on their names by giving `configure' the option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. Optional Features ================= Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The `README' should mention any `--enable-' and `--with-' options that the package recognizes. For packages that use the X Window System, `configure' can usually find the X include and library files automatically, but if it doesn't, you can use the `configure' options `--x-includes=DIR' and `--x-libraries=DIR' to specify their locations. Specifying the System Type ========================== There may be some features `configure' cannot figure out automatically, but needs to determine by the type of machine the package will run on. Usually, assuming the package is built to be run on the _same_ architectures, `configure' can figure that out, but if it prints a message saying it cannot guess the machine type, give it the `--build=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name which has the form: CPU-COMPANY-SYSTEM where SYSTEM can have one of these forms: OS KERNEL-OS See the file `config.sub' for the possible values of each field. If `config.sub' isn't included in this package, then this package doesn't need to know the machine type. If you are _building_ compiler tools for cross-compiling, you should use the option `--target=TYPE' to select the type of system they will produce code for. If you want to _use_ a cross compiler, that generates code for a platform different from the build platform, you should specify the "host" platform (i.e., that on which the generated programs will eventually be run) with `--host=TYPE'. Sharing Defaults ================ If you want to set default values for `configure' scripts to share, you can create a site shell script called `config.site' that gives default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. A warning: not all `configure' scripts look for a site script. Defining Variables ================== Variables not defined in a site shell script can be set in the environment passed to `configure'. However, some packages may run configure again during the build, and the customized values of these variables may be lost. In order to avoid this problem, you should set them in the `configure' command line, using `VAR=value'. For example: ./configure CC=/usr/local2/bin/gcc causes the specified `gcc' to be used as the C compiler (unless it is overridden in the site shell script). Unfortunately, this technique does not work for `CONFIG_SHELL' due to an Autoconf bug. Until the bug is fixed you can use this workaround: CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash `configure' Invocation ====================== `configure' recognizes the following options to control how it operates. `--help' `-h' Print a summary of the options to `configure', and exit. `--version' `-V' Print the version of Autoconf used to generate the `configure' script, and exit. `--cache-file=FILE' Enable the cache: use and save the results of the tests in FILE, traditionally `config.cache'. FILE defaults to `/dev/null' to disable caching. `--config-cache' `-C' Alias for `--cache-file=config.cache'. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `configure' also accepts some other, not widely useful, options. Run `configure --help' for more details. libudis86-0+20221013/LICENSE000066400000000000000000000024711457133061200147250ustar00rootroot00000000000000Copyright (c) 2002-2012, Vivek Thampi All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. libudis86-0+20221013/Makefile.am000066400000000000000000000013171457133061200157520ustar00rootroot00000000000000ACLOCAL_AMFLAGS = -I build/m4 SUBDIRS = scripts libudis86 udcli docs tests MAINTAINERCLEANFILES = \ Makefile.in \ configure \ config.h.in \ config.h.in~ \ missing \ aclocal.m4 \ build/config.guess \ build/config.sub \ build/compile \ build/config.guess \ build/config.sub \ build/depcomp \ build/install-sh \ build/ltmain.sh \ build/missing pcfiles = udis86.pc all-local: $(pcfiles) pkgconfigdir = $(libdir)/pkgconfig pkgconfig_DATA = $(pcfiles) include_ladir = ${includedir} include_la_HEADERS = udis86.h .PHONY: libudis86 udcli tests docs libudis86: $(MAKE) -C $@ udcli: libudis86 $(MAKE) -C $@ tests: check maintainer-clean-local: -rm -rf build/m4 -rm -rf build -rm -rf autom4te.cache libudis86-0+20221013/README.md000066400000000000000000000060061457133061200151750ustar00rootroot00000000000000# Udis86 Udis86 is a disassembler for the x86 and x86-64 class of instruction set architectures. It consists of a C library called `libudis86` which provides a clean and simple interface to decode and inspect a stream of raw binary data as disassembled instructions in a structured manner, and a command line tool called `udcli` that incorporates the library. ## libudis86 - Supports all x86 and x86-64 (AMD64) General purpose and System instructions. - Supported ISA extensions: - MMX, FPU (x87), AMD 3DNow - SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a - AMD-V, INTEL-VMX, SMX, AVX, BMI, FMA4, FMA, F16C - ADX, MPX, SGX, RTM, AES, SHA, CET - Instructions are defined in an XML document, with opcode tables generated for performance. - Supports output in both INTEL (NASM) as well as AT&T (GNU as) style assembly language syntax. - Supports a variety of input methods: Files, Memory Buffers, and Function Callback hooks. - Re-entrant, no dynamic memory allocation. - Fully documented API ### usage example ```c ud_t u; ud_init(&u); ud_set_input_file(&u, stdin); ud_set_mode(&u, 64); ud_set_syntax(&u, UD_SYN_INTEL); while (ud_disassemble(&u)) { printf("\t%s\n", ud_insn_asm(&u)); } ``` ## udcli udcli is a small command-line tool for your quick disassembly needs. ### usage example ```shell echo "65 67 89 87 76 65 54 56 78 89 09 00 90" | udcli -32 -x ``` will result in output such as this: ``` 0000000080000800 656789877665 mov [gs:bx+0x6576], eax 0000000080000806 54 push esp 0000000080000807 56 push esi 0000000080000808 7889 js 0x80000793 000000008000080a 0900 or [eax], eax 000000008000080c 90 nop ``` ## Documentation The libudis86 api is fully documented. The package distribution contains a Texinfo file which can be installed by invoking "make install-info". You can also find an online html version of the documentation available at http://udis86.sourceforge.net/. ## Building You need autotools if building from sources cloned from version control system, or if you need to regenerate the build system. The wrapper script 'autogen.sh' is provided that'll generate the build system. Alternatively you can use cmake to build the library. ## License Udis86 is distributed under the terms of the 2-clause "Simplified BSD License". A copy of the license is included with the source in LICENSE. ## Author and contributors Udis86 was originally written by [Vivek Thampi](https://github.com/vmt/). Further fixes and additions have been merged from these forks: - https://github.com/relyze-ltd/udis86 - https://github.com/matthewfl/udis86 - https://github.com/jwilk-forks/udis86 - https://github.com/TuileriesMac/Udis86 - https://github.com/falconkirtaran/udis86 - https://github.com/Fonger/udis86 - https://github.com/hasherezade/udis86 - https://github.com/bSr43/udis86 - https://github.com/frida/udis86 - https://github.com/el2ro/udis86 - https://github.com/radare/udis86 libudis86-0+20221013/autogen.sh000077500000000000000000000002251457133061200157140ustar00rootroot00000000000000#!/bin/bash # if [ ! -e build/m4 ]; then mkdir -p build/m4; fi autoreconf --force -v --install || ( echo "autogen: autoreconf -i failed." && false ) libudis86-0+20221013/configure.ac000066400000000000000000000036421457133061200162070ustar00rootroot00000000000000# # udis86 autoconf # AC_PREREQ(2.60) AC_INIT([udis86], [1.7.2], [vivek.mt@gmail.com]) AC_CONFIG_HEADERS(config.h) AC_CONFIG_AUX_DIR(build) AC_CONFIG_MACRO_DIR([build/m4]) m4_include([m4/ax_compare_version.m4]) m4_include([m4/ax_prog_sphinx_version.m4]) m4_include([m4/ax_prog_yasm_version.m4]) m4_include([m4/ax_with_prog.m4]) m4_include([m4/ax_with_python.m4]) # Make sure $ACLOCAL_FLAGS are used during a rebuild. AC_SUBST([ACLOCAL_AMFLAGS], ["-I $ac_macro_dir \${ACLOCAL_FLAGS}"]) # # Determine the build host; we notify automake of Windows # builds, so it can pass proper parameters for building # DLLs to the linker. # AC_CANONICAL_HOST case "$host_os" in mingw32* ) TARGET_OS=windows AC_LIBTOOL_WIN32_DLL ;; esac # Initialize the automake subsystem. AM_INIT_AUTOMAKE([1.11 -Wall -Wno-portability -Wno-extra-portability -Werror foreign]) # # In case we have a Windows build, we pass a # TARGET_WINDOWS conditional to automake. # AM_CONDITIONAL(TARGET_WINDOWS, test "$TARGET_OS" = windows) AC_PROG_CC AC_DISABLE_STATIC AC_PROG_LIBTOOL AM_PROG_CC_C_O # If this is a gnu compiler, pass -Wall if test "$ac_cv_c_compiler_gnu" = "yes"; then CFLAGS="$CFLAGS -Wall" fi # Look for python AX_WITH_PYTHON if test "x$PYTHON" = "x"; then AC_MSG_ERROR([Python not found. Use --with-python to specify path to python binary]) fi # Yasm (>= 1.2.0) for testing AX_WITH_PROG(YASM,yasm) AX_PROG_YASM_VERSION([1.2.0],[ac_have_yasm_version=1],[]) AM_CONDITIONAL(HAVE_YASM, [test -n "$ac_have_yasm_version"]) # Sphinx (>= 1.1.3) for documentation AX_WITH_PROG(SPHINX_BUILD,sphinx-build) AX_PROG_SPHINX([1.1.3],[ac_have_sphinx_version=1],[]) AM_CONDITIONAL(HAVE_SPHINX_DOC, [test -n "$ac_have_sphinx_version"]) AC_CHECK_HEADERS([assert.h stdio.h]) AC_CONFIG_FILES([ udis86.pc Makefile scripts/Makefile libudis86/Makefile udcli/Makefile tests/Makefile docs/Makefile docs/manual/Makefile docs/x86/Makefile tests/difftest.sh ]) AC_OUTPUT libudis86-0+20221013/docs/000077500000000000000000000000001457133061200146445ustar00rootroot00000000000000libudis86-0+20221013/docs/Makefile.am000066400000000000000000000000701457133061200166750ustar00rootroot00000000000000SUBDIRS = x86 manual MAINTAINERCLEANFILES = Makefile.in libudis86-0+20221013/docs/manual/000077500000000000000000000000001457133061200161215ustar00rootroot00000000000000libudis86-0+20221013/docs/manual/Makefile.am000066400000000000000000000023701457133061200201570ustar00rootroot00000000000000manualdir = ${docdir}/manual rst_sources = \ index.rst \ getstarted.rst \ libudis86.rst # # The official distribution only contains the rst files. So users # may generate documentation using Sphinx if they wish to. # EXTRA_DIST = \ $(rst_sources) \ udis86.info \ conf.py \ static MAINTAINERCLEANFILES = \ Makefile.in \ udis86.info if HAVE_SPHINX_DOC html-local: $(SPHINX_BUILD) -c $(srcdir) -b html $(srcdir) $(builddir)/html udis86.info: $(rst_sources) $(SPHINX_BUILD) -E -c $(srcdir) -b texinfo $(srcdir) $(builddir)/texinfo $(MAKEINFO) --no-split $(builddir)/texinfo/udis86.texi check-local: html-local else udis86.info: $(rst_sources) html-local udis86.info: @echo "" @echo "------------------------------------------------------------------" @echo "" @echo " Please make sure you have Sphinx (sphinx-doc.org) version 1.1.3" @echo " or above, to be able to build documentation." @echo "" @echo " You can also find documentation at http://udis86.sourceforge.net/" @echo "" @echo "------------------------------------------------------------------" @echo "" @exit 1 endif install-info-local: udis86.info install-info --info-dir=$(infodir) $< clean-local: -rm -rf $(builddir)/html -rm -rf $(builddir)/texinfo $(builddir)/udis86.info libudis86-0+20221013/docs/manual/conf.py000066400000000000000000000015471457133061200174270ustar00rootroot00000000000000# -*- coding: utf-8 -*- import sys, os source_suffix = '.rst' master_doc = 'index' project = u'udis86' copyright = u'2013, Vivek Thampi' version = '1.7' release = '1.7.2' # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. exclude_patterns = ['_build'] pygments_style = 'sphinx' html_theme = 'pyramid' html_theme_options = { "nosidebar" : True } html_static_path = ['static'] html_style = "udis86.css" htmlhelp_basename = 'udis86doc' latex_documents = [ ('index', 'udis86.tex', u'udis86 Documentation', u'Vivek Thampi', 'manual'), ] man_pages = [ ('index', 'udis86', u'udis86 Documentation', [u'Vivek Thampi'], 1) ] texinfo_documents = [ ('index', 'udis86', u'udis86 Documentation', u'Vivek Thampi', 'udis86', 'Disassembler library for x86.', 'Miscellaneous', True), ] libudis86-0+20221013/docs/manual/getstarted.rst000066400000000000000000000025441457133061200210260ustar00rootroot00000000000000Getting Started =============== Building and Installing udis86 ------------------------------ udis86 is developed for unix-like environments, and like most software, the basic steps towards building and installing it are as follows. .. code:: $ ./configure $ make $ make install Depending on your choice of install location, you may need to have root privileges to do an install. The install scripts copy the necessary header and library files to appropriate locations in your system. Interfacing with libudis86: A Quick Example ------------------------------------------- The following is an example of a program that interfaces with libudis86 and uses the API to generate assembly language output for 64-bit code, input from STDIN. .. code-block:: c #include #include int main() { ud_t ud_obj; ud_init(&ud_obj); ud_set_input_file(&ud_obj, stdin); ud_set_mode(&ud_obj, 64); ud_set_syntax(&ud_obj, UD_SYN_INTEL); while (ud_disassemble(&ud_obj)) { printf("\t%s\n", ud_insn_asm(&ud_obj)); } return 0; } To compile the program (using gcc): .. code:: $ gcc -ludis86 example.c -o example This example should give you an idea of how this library can be used. The following sections describe, in detail, the complete API of libudis86. libudis86-0+20221013/docs/manual/index.rst000066400000000000000000000013051457133061200177610ustar00rootroot00000000000000.. udis86 documentation master file Welcome to udis86's documentation! ================================== Udis86 is a disassembler engine that decodes a stream of binary machine code bytes as opcodes defined in the x86 and x86-64 class of Instruction Set Architectures. The core component of this project is libudis86 which provides a clean and simple interface to disassemble binary code, and to inspect the disassembly to various degrees of detail. The library is designed to aid software projects that entail analysis and manipulation of all flavors of x86 binary code. .. toctree:: :maxdepth: 3 getstarted libudis86 Indices and tables ================== * :ref:`genindex` * :ref:`search` libudis86-0+20221013/docs/manual/libudis86.rst000066400000000000000000000416431457133061200204740ustar00rootroot00000000000000libudis86 ========= libudis86 is a disassembler library for the x86 architecture, including support for the newer 64bit variants (IA32e, amd64, etc.) It provides you the ability to decode a stream of bytes as x86 instructions, inspect various bits of information about those instructions and even translate to human readable assembly language format. .. default-domain:: c .. contents:: ud_t: udis86 object ------------------- libudis86 is reentrant, and to maintain that property it does not use static data. All data related to the disassembly are stored in a single object, called the udis86 object :type:`ud_t`. .. c:type:: ud_t A structure encapsulating udis86 disassembler state. To use libudis86 you must create an instance of this object, .. code-block:: c ud_t ud_obj; and initialize it, .. code-block:: c ud_init(&ud_obj); You can create multiple such objects and use with the library, each one an independent disassembler. Setup Machine State ------------------- The decode semantics of a sequence of bytes depends on the target machine state for which they are being disassembled. In x86, this means the current effective processor mode (16, 32 or 64bits), the current program counter (ip/eip/rip), and sometimes, the processor vendor. By default, libudis86 is initialized to be in 32 bit disassembly mode, program counter at 0, and vendor being :code:`UD_VENDOR_ANY`. The following functions allow you to override these default to suit your needs. .. c:function:: void ud_set_mode(ud_t*, uint8_t mode_bits) Sets the mode of disassembly. Possible values are 16, 32, and 64. By default, the library works in 32bit mode. .. c:function:: void ud_set_pc(ud_t*, uint64_t pc) Sets the program counter (IP/EIP/RIP). This changes the offset of the assembly output generated, with direct effect on branch instructions. .. c:function:: void ud_set_vendor(ud_t*, unsigned vendor) Sets the vendor of whose instruction to choose from. This is only useful for selecting the VMX or SVM instruction sets at which point INTEL and AMD have diverged significantly. At a later stage, support for a more granular selection of instruction sets maybe added. * :code:`UD_VENDOR_INTEL` - for INTEL instruction set. * :code:`UD_VENDOR_ATT` - for AMD instruction set. * :code:`UD_VENDOR_ANY` - for any valid instruction in either INTEL or AMD. Setup Input ----------- libudis86 provides three ways in which you can input binary data: as a fixed sized memory buffer, a standard library FILE object, or as a callback function. By default, a :type:`ud_t` object is initialized to read input from :code:`STDIN`. .. c:function:: void ud_set_input_buffer(ud_t*, unsigned char* buffer, size_t size) Sets the input source for the library to a `buffer` of `size` bytes. .. c:function:: void ud_set_input_file(ud_t*, FILE* filep) Sets the input source to a file pointed to by a given standard library :code:`FILE` pointer. Note that libudis86 does not perform any checks, and assumes that the file pointer is properly initialized and open for reading. .. c:function:: void ud_set_input_hook(ud_t* ud_obj, int (*hook)(ud_t *ud_obj)) Sets a pointer to a function, to callback for input. The callback is invoked each time libudis86 needs the next byte in the input stream. To single end-of-input, this callback must return the constant :code:`UD_EOI`. .. seealso:: :func:`ud_set_user_opaque_data`, :func:`ud_set_user_opaque_data` .. c:function:: void ud_input_skip(ud_t*, size_t n); Skips ahead `n` number of bytes in the input stream. .. c:function:: int ud_input_end(const ud_t*); Test for end of input. You can use this function to test if udis86 has exhausted the input. At the end of input, udis86 stops disassembly. If you want to restart or reset the source of input, you must again invoke one of the above functions. Sometimes you may want to associate custom data with a udis86 object, that you can use with the input callback function, or even in different parts of your own project as you pass the object around. You can use the following two functions to achieve this. .. c:function:: void ud_set_user_opaque_data(ud_t* ud_obj, void* opaque) Associates a pointer with the udis86 object to be retrieved and used in client functions, such as the input hook callback function. .. c:function:: void* ud_get_user_opaque_data(const ud_t* ud_obj) Returns any pointer associated with the udis86 object, using the :func:`ud_set_user_opaque_data` function. Setup Translation ----------------- libudis86 can translate the decoded instruction into one of two assembly language dialects: the INTEL syntax (such as those found in NASM and YASM) and the other which resembles GNU Assembler (AT&T style) syntax. By default, this is set to INTEL like syntax. You can override the default or specify your own translator using the following function. .. c:function:: void ud_set_syntax(ud_t*, void (*translator)(ud_t*)) Sets the function that translates the intermediate decode information to a human readable form. There are two inbuilt translators, - :code:`UD_SYN_INTEL` for INTEL (NASM-like) syntax. (default) - :code:`UD_SYN_ATT` for AT&T (GAS-like) syntax. If you do not want libudis86 to translate, you can pass :code:`NULL` to the function, with no more translations thereafter. This is useful when you only want to identify chunks of code and then create the assembly output if needed, or when you are only interested in examining the instructions and do not want to waste cycles generating the assembly language output. If you want to create your own translator, you can specify a pointer to your own function. This function must accept a single parameter, the udis86 object :type:`ud_t`, and it will be invoked every time an instruction is decoded. Disassemble ----------- With target state and input source set up, you can now disassemble. At the core of libudis86 api is the function :c:func:`ud_disassemble` which does this. libudis86 exposes decoded instructions in an intermediate form meant to be useful for programs that want to examine them. This intermediate form is available using functions and fields of :type:`ud_t` as described below. .. c:function:: unsigned int ud_disassemble(ud_t*) Disassembles the next instruction in the input stream. :returns: the number of bytes disassembled. A 0 indicates end of input. Note, to restart disassembly after the end of input, you must call one of the input setting functions with a new source of input. A common use-case pattern for this function is in a loop:: while (ud_disassemble(&ud_obj)) { /* * use or print decode info. */ } For each successful invocation of :c:func:`ud_disassemble`, you can use the following functions to get information about the disassembled instruction. .. c:function:: unsigned int ud_insn_len(const ud_t* u) Returns the number of bytes disassembled. .. c:function:: uint64_t ud_insn_off(const ud_t*) Returns the offset of the disassembled instruction in terms of the program counter value specified initially. .. seealso:: :func:`ud_set_pc` .. c:function:: const char* ud_insn_hex(ud_t*) Returns pointer to a character string holding the hexadecimal representation of the disassembled bytes. .. c:function:: const uint8_t* ud_insn_ptr(const ud_t* u) Returns pointer to the buffer holding the instruction bytes. Use :func:`ud_insn_len` to determine the size of this buffer. .. c:function:: const char* ud_insn_asm(const ud_t* u) If the syntax is specified, returns pointer to the character string holding assembly language representation of the disassembled instruction. .. c:function:: const ud_operand_t* ud_insn_opr(const ud_t* u, unsigned int n) Returns a reference (:type:`ud_operand_t`) to the nth (starting with 0) operand of the instruction. If the instruction does not have such an operand, the function returns :code:`NULL`. .. c:function:: enum ud_mnemonic_code ud_insn_mnemonic(const ud_t *u) .. versionadded:: 1.7.2 Returns the instruction mnemonic in the form of an enumerated constant (:code:`enum ud_mnemonic_code`). As a convention all mnemonic constants are composed by prefixing standard instruction mnemonics with :code:`UD_I`. For example, the enumerations for :code:`mov`, :code:`xor` and :code:`jmp` are :code:`UD_Imov`, :code:`UD_Ixor`, and :code:`UD_Ijmp`, respectively.:: ud_disassemble(&ud_obj); switch (ud_insn_mnemonic(ud_obj)) { case UD_Imov: printf("mov!"); break; case UD_Ixor: printf("xor!"); break; case UD_Ijmp: printf("jmp!"); break; /*...*/ } Prior to version 1.7.2, the way to access the mnemonic was by a field of :code:`ud_t`, :c:member:`ud_t.mnemonc`. This field is now deprecated and may not be supported in the future. .. seealso:: :func:`ud_lookup_mnemonic` .. c:function:: const char* ud_const lookup_mnemonic(enum ud_mnemonic_code) Returns a pointer to a character string corresponding to the given mnemonic code. Returns a :code:`NULL` if the code is invalid. Inspect Operands ---------------- An intermediate representation of instruction operands is available in the form of :type:`ud_operand_t`. You can retrieve the nth operand of a disassembled instruction using the function :func:`ud_insn_opr`. .. c:type:: ud_operand_t The operand type, represents a single operand of an instruction. It contains the following fields. - :c:member:`size ` - :c:member:`type ` - :c:member:`base ` - :c:member:`index ` - :c:member:`scale ` - :c:member:`offset ` - :c:member:`lval ` .. c:member:: unsigned ud_operand_t.size Size of the operand in number of bits. .. c:member:: enum ud_operand_type ud_operand_t.type Type of the operand. Possible values are, .. c:var:: UD_OP_MEM A memory operand. The intermediate form normalizes all memory address equations to the scale-index-base form. The address equation is available in, - :member:`base ` - base register as an enumerated constant of type :type:`enum ud_type`. Maybe :code:`UD_NONE`, in which case the memory addressing form does not include a base register. - :member:`index ` - index register as an enumerated constant of type :type:`enum ud_type`. Maybe :code:`UD_NONE`, in which case the memory addressing form does not include an index register. - :member:`scale ` - an integer value by which the index register must be scaled. Maybe 0, denoting the absence of a scale component in the address. - :member:`offset ` - An integer value, which if non-zero represents the size of the displacement offset, and is one of 8, 16, 32, and 64. The value is available in :member:`lval `. .. c:var:: UD_OP_PTR A segment:offset pointer operand. The :member:`size ` field can have two values, 32 (for 16:16 seg:off) and 48 (for 16:32 seg:off). The pointer value is available in :member:`lval ` (as :member:`lval.ptr.seg` and :member:`lval.ptr.off`) .. c:var:: UD_OP_IMM An Immediate operand. Value available in :member:`lval `. .. c:var:: UD_OP_JIMM An Immediate operand to a branch instruction (relative offsets). Value available in :member:`lval `. .. c:var:: UD_OP_CONST Implicit constant operand. Value available in :member:`lval `. .. c:var:: UD_OP_REG A register operand. The specific register is available in the :member:`base ` field as an enumerated constant of type :type:`enum ud_type`. .. c:member:: enum ud_register ud_operand_t.base Contains an enumerated constant of type :type:`enum ud_type` representing a :data:`register ` operand or the base of a :data:`memory ` operand. .. c:member:: enum ud_register ud_operand_t.index Contains an enumerated constant of type :type:`enum ud_type` representing the index register of a :data:`memory ` operand. .. c:member:: unsigned ud_operand_t.scale Contains the scale component of a :data:`memory ` address operand. .. c:member:: unsigned ud_operand_t.offset Contains the size of the displacement component of a :data:`memory ` address operand. The displacement itself is given by :member:`lval `. .. c:member:: ud_lval_t ud_operand_t.lval A union data structure that aggregates integer fields of different sizes, storing values depending on the :member:`type ` and :member:`size ` of the operand. .. c:member:: lval.sbyte Signed Byte .. c:member:: lval.ubyte Unsigned Byte .. c:member:: lval.sword Signed Word .. c:member:: lval.uword Unsigned Word .. c:member:: lval.sdword Signed Double Word .. c:member:: lval.udword Unsigned Double Word .. c:member:: lval.sqword Signed Quad Word .. c:member:: lval.uqword Unsigned Quad Word .. c:member:: lval.ptr.seg Pointer Segment in Segment:Offset .. c:member:: lval.ptr.off Pointer Offset in Segment:Offset .. c:type:: enum ud_type Instruction Pointer .. code-block:: c UD_R_RIP 8-Bit Registers .. code-block:: c UD_NONE, UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL, UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH, UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL, UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B, UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B, 16-Bit General Purporse Registers .. code-block:: c UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX, UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI, UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W, UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W, 32-Bit General Purporse Registers: .. code-block:: c UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX, UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI, UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D, UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D, 64-Bit General Purporse Registers: .. code-block:: c UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX, UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI, UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11, UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15, Segment Registers: .. code-block:: c UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS, UD_R_FS, UD_R_GS, Control Registers: .. code-block:: c UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3, UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7, UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11, UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15, Debug Registers: .. code-block:: c UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3, UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7, UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11, UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15, MMX Registers: .. code-block:: c UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3, UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7, FPU Registers: .. code-block:: c UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3, UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7, SSE Registers: .. code-block:: c UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3, UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7, UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11, UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15, Inspect Prefixes ---------------- Prefix bytes that affect the disassembly of the instruction are available in the following fields, each of which corresponds to a particular type or class of prefixes. .. c:member:: uint8_t ud_t.pfx_rex 64-bit mode REX prefix .. c:member:: uint8_t ud_t.pfx_seg Segment register prefix .. c:member:: uint8_t ud_t.pfx_opr Operand-size prefix (66h) .. c:member:: uint8_t ud_t.pfx_adr Address-size prefix (67h) .. c:member:: uint8_t ud_t.pfx_lock Lock prefix .. c:member:: uint8_t ud_t.pfx_str String prefix .. c:member:: uint8_t ud_t.pfx_rep Rep prefix .. c:member:: uint8_t ud_t.pfx_repe Repe prefix .. c:member:: uint8_t ud_t.pfx_repne Repne prefix These fields default to :code:`UD_NONE` if the respective prefixes were not found. libudis86-0+20221013/docs/manual/static/000077500000000000000000000000001457133061200174105ustar00rootroot00000000000000libudis86-0+20221013/docs/manual/static/udis86.css000066400000000000000000000032641457133061200212510ustar00rootroot00000000000000/* override pyramid */ @import url("pyramid.css"); body { background-color: #eee; background-color: #e8ecef; } pre { background-color: #e8ecef; border: 1px solid #bbb; border-radius: 5px; -moz-border-radius: 5px; } div.body { border: 1px solid #bbb; border-radius: 5px; -moz-border-radius: 5px; color: black; } div.related, div.document { width: 840px; margin-left: auto; margin-right: auto; } div.related ul { padding-left: 8px; } div.footer a, div.footer { color: #000; font-weight: bold; } div.footer { margin-top: 40px; background-color: #ddd; } /* div.body { margin-left: auto; margin-right: auto; width: 720px; }*/ body, div.body, div.body h1, div.body h2, div.body h3, div.body h4, div.body h5, div.body h6 { font-family: Arial, "Helvetica Neue", Arial, Helvetica, "sans-serif"; } div.body h1, div.body h2, div.body h3, div.body h4, div.body h5, div.body h6 { font-weight: bold; } code, .function dt, .member dt, .type dt, .var dt, .function tt.descname, .member tt.descname, .var tt.descname, .type tt.descname, pre { font-family: 'Consolas', 'Deja Vu Sans Mono', 'Bitstream Vera Sans Mono', monospace; font-size: 1em; padding-bottom: 6px; } .function dt { font-size: 1em; padding-bottom: 6px; } .function tt.descname { font-size: 1em; } a .pre, div.related a, a { text-decoration: none; color: #444; border-bottom: 1px solid #eee; } a .pre { font-weight: bold; } a:hover .pre, a:hover, div.toctree-wrapper a:hover, .indextable a:hover, #indices-and-tables a:hover { text-decoration: none; color: #111; border-bottom: 1px solid #111; } libudis86-0+20221013/docs/x86/000077500000000000000000000000001457133061200152715ustar00rootroot00000000000000libudis86-0+20221013/docs/x86/Makefile.am000066400000000000000000000001431457133061200173230ustar00rootroot00000000000000x86dir = ${docdir}/x86 dist_x86_DATA = optable.xml optable.xsl MAINTAINERCLEANFILES = Makefile.in libudis86-0+20221013/docs/x86/README000066400000000000000000000121221457133061200161470ustar00rootroot00000000000000x86 optable reference --------------------- (incomplete) P - modrm (reg mmx) PR - modrm (rm mmx, mod must be 11b) Q - modrm (rm mmx if mod=11b else mem) V - modrm (reg - xmm) VR - modrm (rm xmm, mod must be 11b) W - modrm (rm xmm if mod=11b else mem) MU - modrm (rm xmm if mod=11b else mem) lets us specify different sizes for reg and for mem. B - modrm (reg bounds) BM - modrm (rm bounds) K - modrm (reg opmask) KM - modrm (rm opmask if mod=11b else mem) KH - vex.vvvv (opmask) H - vex.vvvv xmm HR - vex.vvvv gpr L - xmm reg encoded in immediate byte XS - mem with base GPR and index XMM and a scale. (XSd, XSq) index will be xmm or ymm depending on vexl XSX - index will always be XMM XSY - index will always be YMM G - modrm (reg - gpr) S - modrm (reg - seg) VR - modrm (rm gpr, mod must be 11b) E - modrm (rm gpr if mod=11b else mem) M - modrm (mem), mod!=11b I - immediate J - relative immediate O - memory offset C - control reg D - debug reg opc <> /n - modrm reg field extends opcode /Mnn - disassembly mode extends opcode /Onn - operand mode extends opcode /mod=!11 - modrm mod field extends opcode libudis86-0+20221013/docs/x86/avx.xml000066400000000000000000002315571457133061200166260ustar00rootroot00000000000000 vaddpd W vex.L vex.660f 58 V H W avx vaddps W vex.L vex.0f 58 V H W avx vaddsd W vex.f20f 58 V H W avx vaddss W vex.f30f 58 V H W avx vandpd W vex.L vex.660f 54 V H W avx vandps W vex.L vex.0f 54 V H W avx vandnpd W vex.L vex.660f 55 V H W avx vandnps W vex.L vex.0f 55 V H W avx vcmppd W vex.L vex.660f c2 V W Ib avx vcmpps W vex.L vex.0f c2 V W Ib avx vcmpsd W vex.f20f c2 V W Ib avx vcmpss W vex.f30f c2 V W Ib avx vcomisd vex.660f 2f V H W avx vcomiss vex.0f 2f V H W avx vcvtdq2pd W vex.L vex.f30f e6 V H W avx vcvtdq2ps W vex.L vex.0f 5b V H W avx vcvtpd2dq W vex.L vex.f20f e6 V H W avx vcvtpd2pi W vex.L vex.660f 2d P W avx vcvtpd2ps W vex.L vex.660f 5a V H W avx vcvtpi2ps W vex.L vex.0f 2a V Q avx vcvtpi2pd W vex.L vex.660f 2a V Q avx vcvtps2dq W vex.L vex.660f 5b V H W avx vcvtps2pi W vex.L vex.0f 2d P W avx vcvtps2pd W vex.L vex.0f 5a V H W avx vcvtsd2si W vex.W vex.L vex.f20f 2d Gy W avx vcvtsd2ss W vex.f20f 5a V H W avx vcvtsi2ss W aso vex.f30f 2a V Ey avx vcvtss2si W vex.W vex.L vex.f30f 2d Gy W avx vcvtss2sd W vex.f30f 5a V H W avx vcvttpd2pi W vex.L vex.660f 2c P W avx vcvttpd2dq W vex.L vex.660f e6 V H W avx vcvttps2dq W vex.L vex.f30f 5b V H W avx vcvttps2pi W vex.L vex.0f 2c P W avx vcvttsd2si W vex.W vex.L vex.f20f 2c Gy W avx vcvtsi2sd W aso vex.f20f 2a V Ey avx vcvttss2si W vex.W vex.L vex.f30f 2c Gy W avx vdivpd W vex.L vex.660f 5e V H W avx vdivps W vex.L vex.0f 5e V H W avx vdivsd W vex.f20f 5e V H W avx vdivss W vex.f30f 5e V H W avx vmaskmovq vex.L vex.0f f7 V U avx vmaxpd W vex.L vex.660f 5f V H W avx vmaxps W vex.L vex.0f 5f V H W avx vmaxsd W vex.f20f 5f V H W avx vmaxss W vex.f30f 5f V H W avx vminpd W vex.L vex.660f 5d V H W avx vminps W vex.L vex.0f 5d V H W avx vminsd W vex.f20f 5d V H W avx vminss W vex.f30f 5d V H W avx vmovapd W vex.L vex.660f 28 V H W avx vmovapd W vex.L vex.660f 29 W H V avx vmovaps W vex.L vex.0f 28 V H W avx vmovaps W vex.L vex.0f 29 W H V avx vmovd W aso vex.L vex.660f 6e V Ey avx vmovd W aso vex.L vex.0f 6e P Ey avx vmovd W aso vex.L vex.660f 7e Ey V avx vmovd W aso vex.L vex.0f 7e Ey P avx vmovhpd W aso vex.L vex.660f 16 /mod=!11 V M avx vmovhpd W aso vex.L vex.660f 17 M V avx vmovhps W aso vex.L vex.0f 16 /mod=!11 V M avx vmovhps W aso vex.L vex.0f 17 M V avx vmovlhps W vex.L vex.0f 16 /mod=11 V U avx vmovlpd W aso vex.L vex.660f 12 /mod=!11 V M avx vmovlpd W aso vex.L vex.660f 13 M V avx vmovlps W aso vex.L vex.0f 12 /mod=!11 V M avx vmovlps W aso vex.L vex.0f 13 M V avx vmovhlps W vex.L vex.0f 12 /mod=11 V U avx vmovmskpd W vex.W vex.L vex.660f 50 Gd U avx vmovmskps W vex.W vex.L vex.0f 50 Gd U avx vmovntdq W aso vex.L vex.660f e7 M V avx vmovnti W aso vex.W vex.L vex.0f c3 M Gy avx vmovntpd W aso vex.L vex.660f 2b M V avx vmovntps W aso vex.L vex.0f 2b M V avx vmovntq W aso vex.L vex.0f e7 M V avx vmovq W vex.L vex.0f 6f V W avx vmovq W vex.L vex.660f d6 W H V avx vmovq W vex.L vex.f30f 7e V H W avx vmovq W vex.L vex.0f 7f W V avx vmovsd W vex.f20f 10 V H W avx vmovsd W vex.f20f 11 W H V avx vmovss W vex.f30f 10 V H W avx vmovss W vex.f30f 11 W H V avx vmovsx W aso vex.W vex.L vex.0f be Gv Eb avx vmovsx W aso vex.W vex.L vex.0f bf Gy Ew avx vmovupd W vex.L vex.660f 10 V H W avx vmovupd W vex.L vex.660f 11 W H V avx vmovups W vex.L vex.0f 10 V H W avx vmovups W vex.L vex.0f 11 W H V avx vmovzx W aso vex.W vex.L vex.0f b6 Gv Eb avx vmovzx W aso vex.W vex.L vex.0f b7 Gy Ew avx vmulpd W vex.L vex.660f 59 V H W avx vmulps W vex.L vex.0f 59 V H W avx vmulsd W vex.f20f 59 V H W avx vmulss W vex.f30f 59 V H W avx vorps W vex.L vex.0f 56 V H W avx vpacksswb W vex.L vex.660f 63 V H W avx vpacksswb W vex.L vex.0f 63 V W avx vpackssdw W vex.L vex.660f 6b V H W avx vpackssdw W vex.L vex.0f 6b V W avx vpackuswb W vex.L vex.660f 67 V H W avx vpackuswb W vex.L vex.0f 67 V W avx vpaddb W vex.L vex.660f fc V H W avx vpaddb W vex.L vex.0f fc V W avx vpaddw W vex.L vex.0f fd V W avx vpaddw W vex.L vex.660f fd V H W avx vpaddd W vex.L vex.0f fe V W avx vpaddd W vex.L vex.660f fe V H W avx vpaddsb W vex.L vex.0f ec V W avx vpaddsb W vex.L vex.660f ec V H W avx vpaddsw W vex.L vex.0f ed V W avx vpaddsw W vex.L vex.660f ed V H W avx vpaddusb W vex.L vex.0f dc V W avx vpaddusb W vex.L vex.660f dc V H W avx vpaddusw W vex.L vex.0f dd V W avx vpaddusw W vex.L vex.660f dd V H W avx vpand W vex.L vex.660f db V H W avx vpand W vex.L vex.0f db V W avx vpandn W vex.L vex.660f df V H W avx vpandn W vex.L vex.0f df V W avx vpavgb W vex.L vex.660f e0 V H W avx vpavgb W vex.L vex.0f e0 V W avx vpavgw W vex.L vex.660f e3 V H W avx vpavgw W vex.L vex.0f e3 V W avx vpcmpeqb W vex.L vex.0f 74 V W avx vpcmpeqb W vex.L vex.660f 74 V H W avx vpcmpeqw W vex.L vex.0f 75 V W avx vpcmpeqw W vex.L vex.660f 75 V H W avx vpcmpeqd W vex.L vex.0f 76 V W avx vpcmpeqd W vex.L vex.660f 76 V H W avx vpcmpgtb W vex.L vex.660f 64 V H W avx vpcmpgtb W vex.L vex.0f 64 V W avx vpcmpgtw W vex.L vex.660f 65 V H W avx vpcmpgtw W vex.L vex.0f 65 V W avx vpcmpgtd W vex.L vex.660f 66 V H W avx vpcmpgtd W vex.L vex.0f 66 V W avx vpextrb W aso vex.W vex.L vex.660f3a 14 MbRv V Ib avx vpextrd W aso vex.L vex.660f3a 16 /o=16 Ed V Ib avx vpextrd W aso vex.L vex.660f3a 16 /o=32 Ed V Ib avx vpextrq W aso vex.L vex.660f3a 16 /o=64 Eq V Ib avx vpextrw W vex.W vex.L vex.660f c5 Gd U Ib avx vpextrw W vex.W vex.L vex.0f c5 Gd N Ib avx vpinsrb W aso vex.W vex.L vex.660f3a 20 V MbRd Ib avx vpinsrw W aso vex.W vex.L vex.0f c4 P MwRy Ib avx vpinsrw W aso vex.W vex.L vex.660f c4 V MwRy Ib avx vpinsrd W aso vex.L vex.660f3a 22 /o=16 V Ed Ib avx vpinsrd W aso vex.L vex.660f3a 22 /o=32 V Ed Ib avx vpinsrq W aso vex.L vex.660f3a 22 /o=64 V Eq Ib avx vpmaddwd W vex.L vex.0f f5 V W avx vpmaddwd W vex.L vex.660f f5 V H W avx vpmaxsw W vex.L vex.660f ee V H W avx vpmaxsw W vex.L vex.0f ee V W avx vpmaxub W vex.L vex.0f de V W avx vpmaxub W vex.L vex.660f de V H W avx vpminsw W vex.L vex.660f ea V H W avx vpminsw W vex.L vex.0f ea V W avx vpminub W vex.L vex.660f da V H W avx vpminub W vex.L vex.0f da V W avx vpmovmskb W vex.W vex.L vex.660f d7 Gd U avx vpmovmskb W vex.W vex.L vex.0f d7 Gd N avx vpmulhuw W vex.L vex.0f e4 V W avx vpmulhuw W vex.L vex.660f e4 V H W avx vpmulhw W vex.L vex.660f e5 V H W avx vpmulhw W vex.L vex.0f e5 V W avx vpmullw W vex.L vex.0f d5 V W avx vpmullw W vex.L vex.660f d5 V H W avx vpop W vex.W vex.L vex.0f a9 GS avx vpop W vex.L vex.0f a1 FS avx vpor W vex.L vex.660f eb V H W avx vpor W vex.L vex.0f eb V W avx vprefetch aso vex.L vex.0f 0d /reg=0 M avx vprefetch aso vex.L vex.0f 0d /reg=1 M avx vprefetch aso vex.L vex.0f 0d /reg=2 M avx vprefetch aso vex.L vex.0f 0d /reg=3 M avx vprefetch aso vex.L vex.0f 0d /reg=4 M avx vprefetch aso vex.L vex.0f 0d /reg=5 M avx vprefetch aso vex.L vex.0f 0d /reg=6 M avx vprefetch aso vex.L vex.0f 0d /reg=7 M avx vprefetchnta aso vex.L vex.0f 18 /reg=0 M avx vprefetcht0 aso vex.L vex.0f 18 /reg=1 M avx vprefetcht1 aso vex.L vex.0f 18 /reg=2 M avx vprefetcht2 aso vex.L vex.0f 18 /reg=3 M avx vpsadbw W vex.L vex.660f f6 V H W avx vpsadbw W vex.L vex.0f f6 V W avx vpshufw W vex.L vex.0f 70 P Q Ib avx vpsllw W vex.L vex.660f f1 V H W avx vpsllw W vex.L vex.0f f1 V W avx vpsllw W vex.L vex.660f 71 /reg=6 U Ib avx vpsllw W vex.L vex.0f 71 /reg=6 N Ib avx vpslld W vex.L vex.660f f2 V H W avx vpslld W vex.L vex.0f f2 V W avx vpslld W vex.L vex.660f 72 /reg=6 U Ib avx vpslld W vex.L vex.0f 72 /reg=6 N Ib avx vpsllq W vex.L vex.660f f3 V H W avx vpsllq W vex.L vex.0f f3 V W avx vpsllq W vex.L vex.660f 73 /reg=6 U Ib avx vpsllq W vex.L vex.0f 73 /reg=6 N Ib avx vpsraw W vex.L vex.0f e1 V W avx vpsraw W vex.L vex.660f e1 V H W avx vpsraw W vex.L vex.660f 71 /reg=4 U Ib avx vpsraw W vex.L vex.0f 71 /reg=4 N Ib avx vpsrad W vex.L vex.0f 72 /reg=4 N Ib avx vpsrad W vex.L vex.660f e2 V H W avx vpsrad W vex.L vex.0f e2 V W avx vpsrad W vex.L vex.660f 72 /reg=4 U Ib avx vpsrlw W vex.L vex.0f 71 /reg=2 N Ib avx vpsrlw W vex.L vex.0f d1 V W avx vpsrlw W vex.L vex.660f d1 V H W avx vpsrlw W vex.L vex.660f 71 /reg=2 U Ib avx vpsrld W vex.L vex.0f 72 /reg=2 N Ib avx vpsrld W vex.L vex.0f d2 V W avx vpsrld W vex.L vex.660f d2 V H W avx vpsrld W vex.L vex.660f 72 /reg=2 U Ib avx vpsrlq W vex.L vex.0f 73 /reg=2 N Ib avx vpsrlq W vex.L vex.0f d3 V W avx vpsrlq W vex.L vex.660f d3 V H W avx vpsrlq W vex.L vex.660f 73 /reg=2 U Ib avx vpsubb W vex.L vex.660f f8 V H W avx vpsubb W vex.L vex.0f f8 V W avx vpsubw W vex.L vex.660f f9 V H W avx vpsubw W vex.L vex.0f f9 V W avx vpsubd W vex.L vex.0f fa V W avx vpsubd W vex.L vex.660f fa V H W avx vpsubsb W vex.L vex.0f e8 V W avx vpsubsb W vex.L vex.660f e8 V H W avx vpsubsw W vex.L vex.0f e9 V W avx vpsubsw W vex.L vex.660f e9 V H W avx vpsubusb W vex.L vex.0f d8 V W avx vpsubusb W vex.L vex.660f d8 V H W avx vpsubusw W vex.L vex.0f d9 V W avx vpsubusw W vex.L vex.660f d9 V H W avx vpunpckhbw W vex.L vex.660f 68 V H W avx vpunpckhbw W vex.L vex.0f 68 V W avx vpunpckhwd W vex.L vex.660f 69 V H W avx vpunpckhwd W vex.L vex.0f 69 V W avx vpunpckhdq W vex.L vex.660f 6a V H W avx vpunpckhdq W vex.L vex.0f 6a V W avx vpunpcklbw W vex.L vex.660f 60 V H W avx vpunpcklbw W vex.L vex.0f 60 V W avx vpunpcklwd W vex.L vex.660f 61 V H W avx vpunpcklwd W vex.L vex.0f 61 V W avx vpunpckldq W vex.L vex.660f 62 V H W avx vpunpckldq W vex.L vex.0f 62 V W avx vpush vex.W vex.L vex.0f a8 GS avx vpush vex.L vex.0f a0 FS avx vpxor W vex.L vex.660f ef V H W avx vpxor W vex.L vex.0f ef V W avx vrcpps W vex.L vex.0f 53 V H W avx vrcpss W vex.f30f 53 V H W avx vrsqrtps W vex.L vex.0f 52 V H W avx vrsqrtss W vex.f30f 52 V H W avx vshufpd W vex.L vex.660f c6 V W Ib avx vshufps W vex.L vex.0f c6 V W Ib avx vsqrtps W vex.L vex.0f 51 V H W avx vsqrtpd W vex.L vex.660f 51 V H W avx vsqrtsd W vex.f20f 51 V H W avx vsqrtss W vex.f30f 51 V H W avx vsubpd W vex.L vex.660f 5c V H W avx vsubps W vex.L vex.0f 5c V H W avx vsubsd W vex.f20f 5c V H W avx vsubss W vex.f30f 5c V H W avx vucomisd vex.660f 2e V H W avx vucomiss vex.0f 2e V H W avx vunpckhpd W vex.L vex.660f 15 V H W avx vunpckhps W vex.L vex.0f 15 V H W avx vunpcklps W vex.L vex.0f 14 V H W avx vunpcklpd W vex.L vex.660f 14 V H W avx vxorpd W vex.L vex.660f 57 V H W avx vxorps W vex.L vex.0f 57 V H W avx vmovdqa W vex.L vex.660f 7f W H V avx vmovdqa W vex.L vex.660f 6f V H W avx vmovdq2q W vex.L vex.f20f d6 P U avx vmovdqu W vex.L vex.f30f 6f V H W avx vmovdqu W vex.L vex.f30f 7f W H V avx vmovq2dq W vex.L vex.f30f d6 V N avx vpaddq W vex.L vex.0f d4 V W avx vpaddq W vex.L vex.660f d4 V H W avx vpsubq W vex.L vex.660f fb V H W avx vpsubq W vex.L vex.0f fb V W avx vpmuludq W vex.L vex.0f f4 V W avx vpmuludq W vex.L vex.660f f4 V H W avx vpshufhw W vex.L vex.f30f 70 V W Ib avx vpshuflw W vex.L vex.f20f 70 V W Ib avx vpshufd W vex.L vex.660f 70 V W Ib avx vpslldq W vex.L vex.660f 73 /reg=7 U Ib avx vpsrldq W vex.L vex.660f 73 /reg=3 U Ib avx vpunpckhqdq W vex.L vex.660f 6d V H W avx vpunpcklqdq W vex.L vex.660f 6c V H W avx vaddsubpd W vex.L vex.660f d0 V H W avx vaddsubps W vex.L vex.f20f d0 V H W avx vhaddpd W vex.L vex.660f 7c V H W avx vhaddps W vex.L vex.f20f 7c V H W avx vhsubpd W vex.L vex.660f 7d V H W avx vhsubps W vex.L vex.f20f 7d V H W avx vmovddup W vex.L vex.f20f 12 /mod=11 V H W avx vmovddup W vex.L vex.f20f 12 /mod=!11 V H W avx vmovshdup W vex.L vex.f30f 16 /mod=11 V H W avx vmovshdup W vex.L vex.f30f 16 /mod=!11 V H W avx vmovsldup W vex.L vex.f30f 12 /mod=11 V H W avx vmovsldup W vex.L vex.f30f 12 /mod=!11 V H W avx vpabsb W vex.L vex.0f38 1c V W avx vpabsb W vex.L vex.660f38 1c V H W avx vpabsw W vex.L vex.0f38 1d V W avx vpabsw W vex.L vex.660f38 1d V H W avx vpabsd W vex.0f38 1e V W avx vpabsd W vex.660f38 1e V H W avx vpsignb W vex.L vex.0f38 00 V W avx vpsignb W vex.L vex.660f38 00 V H W avx vphaddw W vex.L vex.0f38 01 V W avx vphaddw W vex.L vex.660f38 01 V H W avx vphaddd W vex.L vex.0f38 02 V W avx vphaddd W vex.L vex.660f38 02 V H W avx vphaddsw W vex.L vex.0f38 03 V W avx vphaddsw W vex.L vex.660f38 03 V H W avx vpmaddubsw W vex.L vex.0f38 04 V W avx vpmaddubsw W vex.L vex.660f38 04 V H W avx vphsubw W vex.L vex.0f38 05 V W avx vphsubw W vex.L vex.660f38 05 V H W avx vphsubd W vex.L vex.0f38 06 V W avx vphsubd W vex.L vex.660f38 06 V H W avx vphsubsw W vex.L vex.0f38 07 V W avx vphsubsw W vex.L vex.660f38 07 V H W avx vpsignb W vex.L vex.0f38 08 V W avx vpsignb W vex.L vex.660f38 08 V H W avx vpsignd W vex.L vex.0f38 0a V W avx vpsignd W vex.L vex.660f38 0a V H W avx vpsignw W vex.L vex.0f38 09 V W avx vpsignw W vex.L vex.660f38 09 V H W avx vpmulhrsw W vex.L vex.0f38 0b V W avx vpmulhrsw W vex.L vex.660f38 0b V H W avx vpalignr W vex.L vex.0f3a 0f P Q Ib avx vpalignr W vex.L vex.660f3a 0f V W Ib avx vpblendvb W vex.L vex.660f38 10 V H W avx vpmuldq W vex.L vex.660f38 28 V H W avx vpminsb W vex.L vex.660f38 38 V H W avx vpminsd W vex.660f38 39 V H W avx vpminuw W vex.L vex.660f38 3a V H W avx vpminud W vex.L vex.660f38 3b V H W avx vpmaxsb W vex.L vex.660f38 3c V H W avx vpmaxsd W vex.660f38 3d V H W avx vpmaxud W vex.L vex.660f38 3f V H W avx vpmaxuw W vex.L vex.660f38 3e V H W avx vpmulld W vex.L vex.660f38 40 V H W avx vphminposuw W vex.L vex.660f38 41 V H W avx vroundps W vex.L vex.660f3a 08 V W Ib avx vroundpd W vex.L vex.660f3a 09 V W Ib avx vroundss W vex.660f3a 0a V W Ib avx vroundsd W vex.660f3a 0b V W Ib avx vblendpd W vex.L vex.660f3a 0d V W Ib avx vpblendw W vex.L vex.660f3a 0e V W Ib avx vblendps W vex.L vex.660f3a 0c V W Ib avx vblendvpd W vex.L vex.660f38 15 V H W avx vblendvps W vex.L vex.660f38 14 V H W avx vdpps W vex.L vex.660f3a 40 V W Ib avx vdppd W vex.L vex.660f3a 41 V W Ib avx vmpsadbw W vex.L vex.660f3a 42 V W Ib avx vextractps W aso vex.W vex.L vex.660f3a 17 MdRy V Ib avx vinsertps W aso vex.L vex.660f3a 21 V Md Ib avx vmovntdqa W aso vex.L vex.660f38 2a V Mo avx vpackusdw W vex.L vex.660f38 2b V H W avx vpmovsxbw W aso vex.L vex.660f38 20 V MqU avx vpmovsxbd W aso vex.L vex.660f38 21 V MdU avx vpmovsxbq W aso vex.L vex.660f38 22 V MwU avx vpmovsxwd W aso vex.L vex.660f38 23 V MqU avx vpmovsxwq W aso vex.L vex.660f38 24 V MdU avx vpmovsxdq W aso vex.L vex.660f38 25 V MqU avx vpmovzxbw W aso vex.L vex.660f38 30 V MqU avx vpmovzxbd W aso vex.L vex.660f38 31 V MdU avx vpmovzxbq W aso vex.L vex.660f38 32 V MwU avx vpmovzxwd W aso vex.L vex.660f38 33 V MqU avx vpmovzxwq W aso vex.L vex.660f38 34 V MdU avx vpmovzxdq W aso vex.L vex.660f38 35 V MqU avx vpcmpeqq W vex.L vex.660f38 29 V H W avx vptest vex.L vex.660f38 17 V H W avx vpcmpestri W vex.L vex.660f3a 61 V W Ib avx vpcmpestrm W vex.L vex.660f3a 60 V W Ib avx vpcmpgtq W vex.L vex.660f38 37 V H W avx vpcmpistri W vex.L vex.660f3a 63 V W Ib avx vpcmpistrm W vex.L vex.660f3a 62 V W Ib avx libudis86-0+20221013/docs/x86/optable.xml000066400000000000000000016653331457133061200174620ustar00rootroot00000000000000 pop xop avx aso oso rexw rexr rexx rexb /vex=10 /reg=0 Ev W def64 aaa UUUMUM______ al al 37 /m=!64 aad ax ax UMMUMU______ d5 /m=!64 Ib aam ax ax UMMUMU______ d4 /m=!64 Ib aas al al UUUMUM______ 3f /m=!64 adc RW MMMMMM______ aso rexr rexx rexb 10 Eb Gb RW R aso oso rexw rexr rexx rexb 11 Ev Gv RW R aso rexr rexx rexb 12 Gb Eb RW R aso oso rexw rexr rexx rexb 13 Gv Ev RW R 14 AL Ib RW N oso rexw 15 rAX sIz RW N aso rexr rexx rexb 80 /reg=2 Eb Ib RW N aso rexr rexx rexb 82 /reg=2 /m=!64 Eb Ib RW N inv64 aso oso rexw rexr rexx rexb 81 /reg=2 Ev sIz RW N aso oso rexw rexr rexx rexb 83 /reg=2 Ev sIb RW N add RW MMMMMM______ aso rexr rexx rexb 00 Eb Gb RW R aso oso rexw rexr rexx rexb 01 Ev Gv RW R aso rexr rexx rexb 02 Gb Eb RW R aso oso rexw rexr rexx rexb 03 Gv Ev RW R 04 AL Ib RW N oso rexw 05 rAX sIz RW N aso rexr rexx rexb 80 /reg=0 Eb Ib RW N aso rexr rexx rexb 82 /reg=0 /m=!64 Eb Ib RW N inv64 aso oso rexw rexr rexx rexb 81 /reg=0 Ev sIz RW N aso oso rexw rexr rexx rexb 83 /reg=0 Ev sIb RW N addpd RW ____________ aso rexr rexx rexb vexl /sse=66 0f 58 V H W W R R sse2 avx addps RW ____________ aso rexr rexx rexb vexl 0f 58 V H W W R R sse avx addsd RW ____________ aso rexr rexx rexb /sse=f2 0f 58 V H MqU W R R sse2 avx addss RW ____________ aso rexr rexx rexb /sse=f3 0f 58 V H MdU W R R sse avx addsubpd RW ____________ aso vexl rexr rexx rexb /sse=66 0f d0 V H W W R R sse3 avx addsubps RW ____________ aso vexl rexr rexx rexb /sse=f2 0f d0 V H W W R R sse3 avx aesdec RW ____________ aso rexr rexx rexb /sse=66 0f 38 de V H W W R R aesni avx aesdeclast RW ____________ aso rexr rexx rexb /sse=66 0f 38 df V H W W R R aesni avx aesenc RW ____________ aesni aso rexr rexx rexb /sse=66 0f 38 dc V H W W R R aesni avx aesenclast RW ____________ aesni avx aso rexr rexx rexb /sse=66 0f 38 dd V H W W R R aesni avx aesimc W ____________ aso rexr rexx rexb /sse=66 0f 38 db V W W R aesni avx aeskeygenassist W ____________ aso rexr rexx rexb /sse=66 0f 3a df V W Ib W R N aesni avx and RW RMMUMR______ aso rexr rexx rexb 20 Eb Gb RW R aso oso rexw rexr rexx rexb 21 Ev Gv RW R aso rexr rexx rexb 22 Gb Eb RW R aso oso rexw rexr rexx rexb 23 Gv Ev RW R 24 AL Ib RW N oso rexw 25 rAX sIz RW N aso rexw rexr rexx rexb 80 /reg=4 Eb Ib RW N aso rexr rexx rexb 82 /reg=4 /m=!64 Eb Ib RW N inv64 aso oso rexw rexr rexx rexb 81 /reg=4 Ev sIz RW N aso oso rexw rexr rexx rexb 83 /reg=4 Ev sIb RW N andpd RW ____________ aso rexr rexx rexb vexl /sse=66 0f 54 V H W W R R sse2 avx andps RW ____________ aso vexl rexr rexx rexb 0f 54 V H W W R R sse avx andnpd RW ____________ aso vexl rexr rexx rexb /sse=66 0f 55 V H W W R R sse2 avx andnps RW ____________ aso vexl rexr rexx rexb 0f 55 V H W W R R sse2 avx arpl W __M_________ aso 63 /m=!64 Ew Gw W R movsxd W ____________ aso oso rexw rexx rexr rexb 63 /m=64 Gq Ed W R call rsp rsp rip ____________ aso oso rexw rexr rexx rexb ff /reg=2 /m=!64 Ev R aso oso rexw rexr rexx rexb ff /reg=2 /m=64 Eq R def64 aso oso rexw rexr rexx rexb ff /reg=3 Fv R oso e8 Jz R def64 oso 9a /m=!64 Av N cbw al ax ____________ oso rexw 98 /o=16 cwde ax eax ____________ oso rexw 98 /o=32 cdqe eax rax ____________ oso rexw 98 /o=64 clac ___________R 0f 01 /reg=1 /mod=11 /rm=2 smap clc _____R______ f8 cld ________R___ fc clflush W ____________ aso rexw rexr rexx rexb 0f ae /reg=7 /mod=!11 Mb W clgi amd 0f 01 /reg=3 /mod=11 /rm=5 cli _______R____ fa clts cr0 cr0 ____________ 0f 06 cmc _____M______ f5 cmovo W T___________ aso oso rexw rexr rexx rexb 0f 40 Gv Ev RW R cmovno W T___________ aso oso rexw rexr rexx rexb 0f 41 Gv Ev RW R cmovb W _____T______ aso oso rexw rexr rexx rexb 0f 42 Gv Ev RW R cmovae W _____T______ aso oso rexw rexr rexx rexb 0f 43 Gv Ev RW R cmove W __T_________ aso oso rexw rexr rexx rexb 0f 44 Gv Ev RW R cmovne W __T_________ aso oso rexw rexr rexx rexb 0f 45 Gv Ev RW R cmovbe W __T__T______ aso oso rexw rexr rexx rexb 0f 46 Gv Ev RW R cmova W __T__T______ aso oso rexw rexr rexx rexb 0f 47 Gv Ev RW R cmovs W _T__________ aso oso rexw rexr rexx rexb 0f 48 Gv Ev RW R cmovns W _T__________ aso oso rexw rexr rexx rexb 0f 49 Gv Ev RW R cmovp W ____T_______ aso oso rexw rexr rexx rexb 0f 4a Gv Ev RW R cmovnp W ____T_______ aso oso rexw rexr rexx rexb 0f 4b Gv Ev RW R cmovl W TT__________ aso oso rexw rexr rexx rexb 0f 4c Gv Ev RW R cmovge W TT__________ aso oso rexw rexr rexx rexb 0f 4d Gv Ev RW R cmovle W TTT_________ aso oso rexw rexr rexx rexb 0f 4e Gv Ev RW R cmovg W TTT_________ aso oso rexw rexr rexx rexb 0f 4f Gv Ev RW R cmp MMMMMM______ aso rexr rexx rexb 38 Eb Gb R R aso oso rexw rexr rexx rexb 39 Ev Gv R R aso rexr rexx rexb 3a Gb Eb R R aso oso rexw rexr rexx rexb 3b Gv Ev R R 3c AL Ib R N oso rexw 3d rAX sIz R N aso rexr rexx rexb 80 /reg=7 Eb Ib R N aso rexr rexx rexb 82 /reg=7 /m=!64 Eb Ib R N inv64 aso oso rexw rexr rexx rexb 81 /reg=7 Ev sIz R N aso oso rexw rexr rexx rexb 83 /reg=7 Ev sIb R N cmppd RW MMMMMM______ aso rexr rexx rexb vexl /sse=66 0f c2 V H W Ib W R R N sse2 avx cmpeqpd cmpltpd cmplepd cmpunordpd cmpneqpd cmpnltpd cmpnlepd cmpordpd vcmpeqpd vcmpltpd vcmplepd vcmpunordpd vcmpneqpd vcmpnltpd vcmpnlepd vcmpordpd vcmpeq_uqpd vcmpngepd vcmpngtpd vcmpfalsepd vcmpneq_oqpd vcmpgepd vcmpgtpd vcmptruepd vcmpeq_ospd vcmplt_oqpd vcmple_oqpd vcmpunord_spd vcmpneq_uspd vcmpnlt_uqpd vcmpnle_uqpd vcmpord_spd vcmpeq_uspd vcmpnge_uqpd vcmpngt_uqpd vcmpfalse_ospd vcmpneq_ospd vcmpge_oqpd vcmpgt_oqpd vcmptrue_uspd cmpps RW ____________ aso rexr rexx rexb vexl 0f c2 V H W Ib W R R N sse2 avx cmpeqps cmpltps cmpleps cmpunordps cmpneqps cmpnltps cmpnleps cmpordps vcmpeqps vcmpltps vcmpleps vcmpunordps vcmpneqps vcmpnltps vcmpnleps vcmpordps vcmpeq_uqps vcmpngeps vcmpngtps vcmpfalseps vcmpneq_oqps vcmpgeps vcmpgtps vcmptrueps vcmpeq_osps vcmplt_oqps vcmple_oqps vcmpunord_sps vcmpneq_usps vcmpnlt_uqps vcmpnle_uqps vcmpord_sps vcmpeq_usps vcmpnge_uqps vcmpngt_uqps vcmpfalse_osps vcmpneq_osps vcmpge_oqps vcmpgt_oqps vcmptrue_usps cmpsb rsi rdi rsi rdi MMMMMM__T___ repz seg a6 cmpsw rsi rdi rsi rdi MMMMMM__T___ repz oso rexw seg a7 /o=16 cmpsd MMMMMM__T___ rsi rdi rsi rdi repz oso rexw seg a7 /o=32 RW aso rexr rexx rexb /sse=f2 0f c2 V H MqU Ib W R R N sse2 avx cmpeqsd cmpltsd cmplesd cmpunordsd cmpneqsd cmpnltsd cmpnlesd cmpordsd vcmpeqsd vcmpltsd vcmplesd vcmpunordsd vcmpneqsd vcmpnltsd vcmpnlesd vcmpordsd vcmpeq_uqsd vcmpngesd vcmpngtsd vcmpfalsesd vcmpneq_oqsd vcmpgesd vcmpgtsd vcmptruesd vcmpeq_ossd vcmplt_oqsd vcmple_oqsd vcmpunord_ssd vcmpneq_ussd vcmpnlt_uqsd vcmpnle_uqsd vcmpord_ssd vcmpeq_ussd vcmpnge_uqsd vcmpngt_uqsd vcmpfalse_ossd vcmpneq_ossd vcmpge_oqsd vcmpgt_oqsd vcmptrue_ussd cmpsq rsi rdi rsi rdi MMMMMM__T___ repz oso rexw seg a7 /o=64 cmpss RW ____________ aso rexr rexx rexb /sse=f3 0f c2 V H MdU Ib W R R N sse2 avx cmpeqss cmpltss cmpless cmpunordss cmpneqss cmpnltss cmpnless cmpordss vcmpeqss vcmpltss vcmpless vcmpunordss vcmpneqss vcmpnltss vcmpnless vcmpordss vcmpeq_uqss vcmpngess vcmpngtss vcmpfalsess vcmpneq_oqss vcmpgess vcmpgtss vcmptruess vcmpeq_osss vcmplt_oqss vcmple_oqss vcmpunord_sss vcmpneq_usss vcmpnlt_uqss vcmpnle_uqss vcmpord_sss vcmpeq_usss vcmpnge_uqss vcmpngt_uqss vcmpfalse_osss vcmpneq_osss vcmpge_oqss vcmpgt_oqss vcmptrue_usss cmpxchg rax rax RW MMMMMM______ aso rexr rexx rexb 0f b0 Eb Gb RW R aso oso rexw rexr rexx rexb 0f b1 Ev Gv RW R cmpxchg8b rax rdx rax rdx RW __M_________ aso rexr rexx rexb 0f c7 /mod=!11 /reg=1 /o=16 Mq RW aso rexr rexx rexb 0f c7 /mod=!11 /reg=1 /o=32 Mq RW cmpxchg16b rax rdx rax rdx RW __M_________ aso rexr rexx rexb 0f c7 /mod=!11 /reg=1 /o=64 Mdq RW comisd RRMRMM______ aso rexr rexx rexb /sse=66 0f 2f Vsd Wsd R R sse2 avx comiss RRMRMM______ aso rexr rexx rexb 0f 2f V MdU R R sse2 avx cpuid eax eax ebx ecx edx ____________ 0f a2 cvtdq2pd W ____________ aso rexr rexx rexb /sse=f3 0f e6 V MqU W R sse2 vcvtdq2pd ____________ aso rexr rexx rexb vexl /vex=f3_0f /vexl=0 e6 V MqU W R avx aso rexr rexx rexb vexl /vex=f3_0f /vexl=1 e6 V MdqU W R avx cvtdq2ps W aso rexr rexx rexb vexl 0f 5b V W W R sse2 avx cvtpd2dq W aso rexr rexx rexb vexl /sse=f2 0f e6 Vdq W W R sse2 avx cvtpd2pi W aso rexr rexx rexb /sse=66 0f 2d P W W R cvtpd2ps W aso rexr rexx rexb vexl /sse=66 0f 5a Vdq W W R sse2 avx cvtpi2ps W aso rexr rexx rexb 0f 2a V Q W R cvtpi2pd W aso rexr rexx rexb /sse=66 0f 2a V Q W R cvtps2dq W aso rexr rexx rexb vexl /sse=66 0f 5b V W W R sse2 avx cvtps2pd W aso rexr rexx rexb 0f 5a V MqU W R sse2 vcvtps2pd aso rexr rexx rexb vexl /vex=0f 5a /vexl=0 V MqU W R avx aso rexr rexx rexb vexl /vex=0f 5a /vexl=1 V MdqU W R avx cvtps2pi W aso rexr rexx rexb 0f 2d P MqU W R cvtsd2si W aso rexw rexr rexx rexb /sse=f2 0f 2d Gy MqU W R sse2 avx cvtsd2ss W aso rexr rexx rexb /sse=f2 0f 5a V H MqU W R R sse2 avx cvtsi2sd W aso rexw rexr rexx rexb /sse=f2 0f 2a V H Ey W R R sse2 avx cvtsi2ss W aso rexw rexr rexx rexb /sse=f3 0f 2a V H Ey W R R sse avx cvtss2sd W aso rexr rexx rexb /sse=f3 0f 5a V H MdU W R R sse2 avx cvtss2si W aso rexw rexr rexx rexb /sse=f3 0f 2d Gy MdU W R sse avx cvttpd2dq W aso rexr rexx rexb vexl /sse=66 0f e6 Vdq W W R sse2 avx cvttpd2pi W aso rexr rexx rexb /sse=66 0f 2c P W W R cvttps2dq W aso rexr rexx rexb vexl /sse=f3 0f 5b V W W R sse2 avx cvttps2pi W aso rexr rexx rexb 0f 2c P MqU W R cvttsd2si W aso rexw rexr rexx rexb /sse=f2 0f 2c Gy MqU W R sse2 avx cvttss2si W aso rexw rexr rexx rexb /sse=f3 0f 2c Gy MdU W R sse2 avx cwd ax ax dx ____________ oso rexw 99 /o=16 cdq eax eax edx ____________ oso rexw 99 /o=32 cqo rax rax rdx ____________ oso rexw 99 /o=64 daa al al UMMMMM______ 27 /m=!64 inv64 das al al UMMMMM______ 2f /m=!64 inv64 dec RW MMMMM_______ oso 48 R0z RW oso 49 R1z RW oso 4a R2z RW oso 4b R3z RW oso 4c R4z RW oso 4d R5z RW oso 4e R6z RW oso 4f R7z RW aso rexw rexr rexx rexb fe /reg=1 Eb RW aso oso rexw rexr rexx rexb ff /reg=1 Ev RW div R UUUUUU______ ax dx ax dx aso oso rexw rexr rexx rexb f7 /reg=6 Ev R ax ax aso rexw rexr rexx rexb f6 /reg=6 Eb R divpd RW ____________ aso rexr rexx rexb vexl /sse=66 0f 5e V H W W R R sse2 avx divps RW ____________ aso vexl rexr rexx rexb 0f 5e V H W W R R sse avx divsd RW ____________ aso rexr rexx rexb /sse=f2 0f 5e V H MqU W R R sse2 avx divss RW ____________ aso rexr rexx rexb /sse=f3 0f 5e V H MdU W R R sse avx dppd RW ____________ aso rexr rexx rexb /sse=66 0f 3a 41 V H W Ib W R R N sse4.1 avx dpps RW aso rexr rexx rexb vexl /sse=66 0f 3a 40 V H W Ib W R R N sse4.1 avx emms ____________ 0f 77 enter ____________ c8 Iw Ib N N def64 extractps W ____________ aso rexr rexw rexx rexb /sse=66 0f 3a 17 MdRy V Ib W R N sse4.1 avx f2xm1 st0 st0 X87 d9 /mod=11 /x87=30 fabs st0 st0 X87 d9 /mod=11 /x87=21 fadd X87 aso rexr rexx rexb dc /mod=!11 /reg=0 Mq aso rexr rexx rexb d8 /mod=!11 /reg=0 Md dc /mod=11 /x87=00 ST0 ST0 dc /mod=11 /x87=01 ST1 ST0 dc /mod=11 /x87=02 ST2 ST0 dc /mod=11 /x87=03 ST3 ST0 dc /mod=11 /x87=04 ST4 ST0 dc /mod=11 /x87=05 ST5 ST0 dc /mod=11 /x87=06 ST6 ST0 dc /mod=11 /x87=07 ST7 ST0 d8 /mod=11 /x87=00 ST0 ST0 d8 /mod=11 /x87=01 ST0 ST1 d8 /mod=11 /x87=02 ST0 ST2 d8 /mod=11 /x87=03 ST0 ST3 d8 /mod=11 /x87=04 ST0 ST4 d8 /mod=11 /x87=05 ST0 ST5 d8 /mod=11 /x87=06 ST0 ST6 d8 /mod=11 /x87=07 ST0 ST7 faddp X87 de /mod=11 /x87=00 ST0 ST0 de /mod=11 /x87=01 ST1 ST0 de /mod=11 /x87=02 ST2 ST0 de /mod=11 /x87=03 ST3 ST0 de /mod=11 /x87=04 ST4 ST0 de /mod=11 /x87=05 ST5 ST0 de /mod=11 /x87=06 ST6 ST0 de /mod=11 /x87=07 ST7 ST0 fbld X87 aso rexr rexx rexb df /mod=!11 /reg=4 Mt fbstp X87 aso rexr rexx rexb df /mod=!11 /reg=6 Mt fchs X87 d9 /mod=11 /x87=20 fnclex X87 db /mod=11 /x87=22 fcmovb _____T______ X87 da /mod=11 /x87=00 ST0 ST0 da /mod=11 /x87=01 ST0 ST1 da /mod=11 /x87=02 ST0 ST2 da /mod=11 /x87=03 ST0 ST3 da /mod=11 /x87=04 ST0 ST4 da /mod=11 /x87=05 ST0 ST5 da /mod=11 /x87=06 ST0 ST6 da /mod=11 /x87=07 ST0 ST7 fcmove __T_________ X87 da /mod=11 /x87=08 ST0 ST0 da /mod=11 /x87=09 ST0 ST1 da /mod=11 /x87=0a ST0 ST2 da /mod=11 /x87=0b ST0 ST3 da /mod=11 /x87=0c ST0 ST4 da /mod=11 /x87=0d ST0 ST5 da /mod=11 /x87=0e ST0 ST6 da /mod=11 /x87=0f ST0 ST7 fcmovbe __T__T______ X87 da /mod=11 /x87=10 ST0 ST0 da /mod=11 /x87=11 ST0 ST1 da /mod=11 /x87=12 ST0 ST2 da /mod=11 /x87=13 ST0 ST3 da /mod=11 /x87=14 ST0 ST4 da /mod=11 /x87=15 ST0 ST5 da /mod=11 /x87=16 ST0 ST6 da /mod=11 /x87=17 ST0 ST7 fcmovu ____T_______ X87 da /mod=11 /x87=18 ST0 ST0 da /mod=11 /x87=19 ST0 ST1 da /mod=11 /x87=1a ST0 ST2 da /mod=11 /x87=1b ST0 ST3 da /mod=11 /x87=1c ST0 ST4 da /mod=11 /x87=1d ST0 ST5 da /mod=11 /x87=1e ST0 ST6 da /mod=11 /x87=1f ST0 ST7 fcmovnb _____T______ X87 db /mod=11 /x87=00 ST0 ST0 db /mod=11 /x87=01 ST0 ST1 db /mod=11 /x87=02 ST0 ST2 db /mod=11 /x87=03 ST0 ST3 db /mod=11 /x87=04 ST0 ST4 db /mod=11 /x87=05 ST0 ST5 db /mod=11 /x87=06 ST0 ST6 db /mod=11 /x87=07 ST0 ST7 fcmovne __T_________ X87 db /mod=11 /x87=08 ST0 ST0 db /mod=11 /x87=09 ST0 ST1 db /mod=11 /x87=0a ST0 ST2 db /mod=11 /x87=0b ST0 ST3 db /mod=11 /x87=0c ST0 ST4 db /mod=11 /x87=0d ST0 ST5 db /mod=11 /x87=0e ST0 ST6 db /mod=11 /x87=0f ST0 ST7 fcmovnbe __T__T______ X87 db /mod=11 /x87=10 ST0 ST0 db /mod=11 /x87=11 ST0 ST1 db /mod=11 /x87=12 ST0 ST2 db /mod=11 /x87=13 ST0 ST3 db /mod=11 /x87=14 ST0 ST4 db /mod=11 /x87=15 ST0 ST5 db /mod=11 /x87=16 ST0 ST6 db /mod=11 /x87=17 ST0 ST7 fcmovnu ____T_______ X87 db /mod=11 /x87=18 ST0 ST0 db /mod=11 /x87=19 ST0 ST1 db /mod=11 /x87=1a ST0 ST2 db /mod=11 /x87=1b ST0 ST3 db /mod=11 /x87=1c ST0 ST4 db /mod=11 /x87=1d ST0 ST5 db /mod=11 /x87=1e ST0 ST6 db /mod=11 /x87=1f ST0 ST7 fucomi __M_MM______ X87 db /mod=11 /x87=28 ST0 ST0 db /mod=11 /x87=29 ST0 ST1 db /mod=11 /x87=2a ST0 ST2 db /mod=11 /x87=2b ST0 ST3 db /mod=11 /x87=2c ST0 ST4 db /mod=11 /x87=2d ST0 ST5 db /mod=11 /x87=2e ST0 ST6 db /mod=11 /x87=2f ST0 ST7 fcom ___________ X87 aso rexr rexx rexb d8 /mod=!11 /reg=2 Md aso rexr rexx rexb dc /mod=!11 /reg=2 Mq d8 /mod=11 /x87=10 ST0 ST0 d8 /mod=11 /x87=11 ST0 ST1 d8 /mod=11 /x87=12 ST0 ST2 d8 /mod=11 /x87=13 ST0 ST3 d8 /mod=11 /x87=14 ST0 ST4 d8 /mod=11 /x87=15 ST0 ST5 d8 /mod=11 /x87=16 ST0 ST6 d8 /mod=11 /x87=17 ST0 ST7 fcom2 ____________ X87 UNDOC dc /mod=11 /x87=10 ST0 dc /mod=11 /x87=11 ST1 dc /mod=11 /x87=12 ST2 dc /mod=11 /x87=13 ST3 dc /mod=11 /x87=14 ST4 dc /mod=11 /x87=15 ST5 dc /mod=11 /x87=16 ST6 dc /mod=11 /x87=17 ST7 fcomp3 ____________ X87 UNDOC dc /mod=11 /x87=18 ST0 dc /mod=11 /x87=19 ST1 dc /mod=11 /x87=1a ST2 dc /mod=11 /x87=1b ST3 dc /mod=11 /x87=1c ST4 dc /mod=11 /x87=1d ST5 dc /mod=11 /x87=1e ST6 dc /mod=11 /x87=1f ST7 fcomi RRMRMM______ X87 db /mod=11 /x87=30 ST0 ST0 db /mod=11 /x87=31 ST0 ST1 db /mod=11 /x87=32 ST0 ST2 db /mod=11 /x87=33 ST0 ST3 db /mod=11 /x87=34 ST0 ST4 db /mod=11 /x87=35 ST0 ST5 db /mod=11 /x87=36 ST0 ST6 db /mod=11 /x87=37 ST0 ST7 fucomip RRMRMM______ X87 df /mod=11 /x87=28 ST0 ST0 df /mod=11 /x87=29 ST0 ST1 df /mod=11 /x87=2a ST0 ST2 df /mod=11 /x87=2b ST0 ST3 df /mod=11 /x87=2c ST0 ST4 df /mod=11 /x87=2d ST0 ST5 df /mod=11 /x87=2e ST0 ST6 df /mod=11 /x87=2f ST0 ST7 fcomip RRMRMM______ X87 df /mod=11 /x87=30 ST0 ST0 df /mod=11 /x87=31 ST0 ST1 df /mod=11 /x87=32 ST0 ST2 df /mod=11 /x87=33 ST0 ST3 df /mod=11 /x87=34 ST0 ST4 df /mod=11 /x87=35 ST0 ST5 df /mod=11 /x87=36 ST0 ST6 df /mod=11 /x87=37 ST0 ST7 fcomp ____________ X87 aso rexr rexx rexb d8 /mod=!11 /reg=3 Md aso rexr rexx rexb dc /mod=!11 /reg=3 Mq d8 /mod=11 /x87=18 ST0 ST0 d8 /mod=11 /x87=19 ST0 ST1 d8 /mod=11 /x87=1a ST0 ST2 d8 /mod=11 /x87=1b ST0 ST3 d8 /mod=11 /x87=1c ST0 ST4 d8 /mod=11 /x87=1d ST0 ST5 d8 /mod=11 /x87=1e ST0 ST6 d8 /mod=11 /x87=1f ST0 ST7 fcomp5 ____________ X87 UNDOC de /mod=11 /x87=10 ST0 de /mod=11 /x87=11 ST1 de /mod=11 /x87=12 ST2 de /mod=11 /x87=13 ST3 de /mod=11 /x87=14 ST4 de /mod=11 /x87=15 ST5 de /mod=11 /x87=16 ST6 de /mod=11 /x87=17 ST7 fcompp ____________ X87 de /mod=11 /x87=19 fcos X87 d9 /mod=11 /x87=3f fdecstp X87 d9 /mod=11 /x87=36 fdiv X87 aso rexr rexx rexb dc /mod=!11 /reg=6 Mq dc /mod=11 /x87=38 ST0 ST0 dc /mod=11 /x87=39 ST1 ST0 dc /mod=11 /x87=3a ST2 ST0 dc /mod=11 /x87=3b ST3 ST0 dc /mod=11 /x87=3c ST4 ST0 dc /mod=11 /x87=3d ST5 ST0 dc /mod=11 /x87=3e ST6 ST0 dc /mod=11 /x87=3f ST7 ST0 aso rexr rexx rexb d8 /mod=!11 /reg=6 Md d8 /mod=11 /x87=30 ST0 ST0 d8 /mod=11 /x87=31 ST0 ST1 d8 /mod=11 /x87=32 ST0 ST2 d8 /mod=11 /x87=33 ST0 ST3 d8 /mod=11 /x87=34 ST0 ST4 d8 /mod=11 /x87=35 ST0 ST5 d8 /mod=11 /x87=36 ST0 ST6 d8 /mod=11 /x87=37 ST0 ST7 fdivp X87 de /mod=11 /x87=38 ST0 ST0 de /mod=11 /x87=39 ST1 ST0 de /mod=11 /x87=3a ST2 ST0 de /mod=11 /x87=3b ST3 ST0 de /mod=11 /x87=3c ST4 ST0 de /mod=11 /x87=3d ST5 ST0 de /mod=11 /x87=3e ST6 ST0 de /mod=11 /x87=3f ST7 ST0 fdivr X87 aso rexr rexx rexb dc /mod=!11 /reg=7 Mq dc /mod=11 /x87=30 ST0 ST0 dc /mod=11 /x87=31 ST1 ST0 dc /mod=11 /x87=32 ST2 ST0 dc /mod=11 /x87=33 ST3 ST0 dc /mod=11 /x87=34 ST4 ST0 dc /mod=11 /x87=35 ST5 ST0 dc /mod=11 /x87=36 ST6 ST0 dc /mod=11 /x87=37 ST7 ST0 aso rexr rexx rexb d8 /mod=!11 /reg=7 Md d8 /mod=11 /x87=38 ST0 ST0 d8 /mod=11 /x87=39 ST0 ST1 d8 /mod=11 /x87=3a ST0 ST2 d8 /mod=11 /x87=3b ST0 ST3 d8 /mod=11 /x87=3c ST0 ST4 d8 /mod=11 /x87=3d ST0 ST5 d8 /mod=11 /x87=3e ST0 ST6 d8 /mod=11 /x87=3f ST0 ST7 fdivrp X87 de /mod=11 /x87=30 ST0 ST0 de /mod=11 /x87=31 ST1 ST0 de /mod=11 /x87=32 ST2 ST0 de /mod=11 /x87=33 ST3 ST0 de /mod=11 /x87=34 ST4 ST0 de /mod=11 /x87=35 ST5 ST0 de /mod=11 /x87=36 ST6 ST0 de /mod=11 /x87=37 ST7 ST0 femms 0f 0e ffree X87 dd /mod=11 /x87=00 ST0 dd /mod=11 /x87=01 ST1 dd /mod=11 /x87=02 ST2 dd /mod=11 /x87=03 ST3 dd /mod=11 /x87=04 ST4 dd /mod=11 /x87=05 ST5 dd /mod=11 /x87=06 ST6 dd /mod=11 /x87=07 ST7 ffreep X87 df /mod=11 /x87=00 ST0 df /mod=11 /x87=01 ST1 df /mod=11 /x87=02 ST2 df /mod=11 /x87=03 ST3 df /mod=11 /x87=04 ST4 df /mod=11 /x87=05 ST5 df /mod=11 /x87=06 ST6 df /mod=11 /x87=07 ST7 ficom X87 aso rexr rexx rexb de /mod=!11 /reg=2 Mw aso rexr rexx rexb da /mod=!11 /reg=2 Md ficomp X87 aso rexr rexx rexb de /mod=!11 /reg=3 Mw aso rexr rexx rexb da /mod=!11 /reg=3 Md fild X87 aso rexr rexx rexb df /mod=!11 /reg=0 Mw aso rexr rexx rexb df /mod=!11 /reg=5 Mq aso rexr rexx rexb db /mod=!11 /reg=0 Md fincstp X87 d9 /mod=11 /x87=37 fninit X87 db /mod=11 /x87=23 fiadd X87 aso rexr rexx rexb da /mod=!11 /reg=0 Md aso rexr rexx rexb de /mod=!11 /reg=0 Mw fidivr X87 aso rexr rexx rexb da /mod=!11 /reg=7 Md aso rexr rexx rexb de /mod=!11 /reg=7 Mw fidiv X87 aso rexr rexx rexb da /mod=!11 /reg=6 Md aso rexr rexx rexb de /mod=!11 /reg=6 Mw fisub X87 aso rexr rexx rexb da /mod=!11 /reg=4 Md aso rexr rexx rexb de /mod=!11 /reg=4 Mw fisubr X87 aso rexr rexx rexb da /mod=!11 /reg=5 Md aso rexr rexx rexb de /mod=!11 /reg=5 Mw fist X87 aso rexr rexx rexb df /mod=!11 /reg=2 Mw aso rexr rexx rexb db /mod=!11 /reg=2 Md fistp X87 aso rexr rexx rexb df /mod=!11 /reg=3 Mw aso rexr rexx rexb df /mod=!11 /reg=7 Mq aso rexr rexx rexb db /mod=!11 /reg=3 Md fisttp X87 aso rexr rexx rexb db /mod=!11 /reg=1 Md aso rexr rexx rexb dd /mod=!11 /reg=1 Mq aso rexr rexx rexb df /mod=!11 /reg=1 Mw fld X87 aso rexr rexx rexb db /mod=!11 /reg=5 Mt aso rexr rexx rexb dd /mod=!11 /reg=0 Mq aso rexr rexx rexb d9 /mod=!11 /reg=0 Md d9 /mod=11 /x87=00 ST0 d9 /mod=11 /x87=01 ST1 d9 /mod=11 /x87=02 ST2 d9 /mod=11 /x87=03 ST3 d9 /mod=11 /x87=04 ST4 d9 /mod=11 /x87=05 ST5 d9 /mod=11 /x87=06 ST6 d9 /mod=11 /x87=07 ST7 fld1 X87 d9 /mod=11 /x87=28 fldl2t X87 d9 /mod=11 /x87=29 fldl2e X87 d9 /mod=11 /x87=2a fldpi X87 d9 /mod=11 /x87=2b fldlg2 X87 d9 /mod=11 /x87=2c fldln2 X87 d9 /mod=11 /x87=2d fldz X87 d9 /mod=11 /x87=2e fldcw X87 aso rexr rexx rexb d9 /mod=!11 /reg=5 Mw fldenv X87 aso rexr rexx rexb d9 /mod=!11 /reg=4 M fmul X87 aso rexr rexx rexb dc /mod=!11 /reg=1 Mq dc /mod=11 /x87=08 ST0 ST0 dc /mod=11 /x87=09 ST1 ST0 dc /mod=11 /x87=0a ST2 ST0 dc /mod=11 /x87=0b ST3 ST0 dc /mod=11 /x87=0c ST4 ST0 dc /mod=11 /x87=0d ST5 ST0 dc /mod=11 /x87=0e ST6 ST0 dc /mod=11 /x87=0f ST7 ST0 aso rexr rexx rexb d8 /mod=!11 /reg=1 Md d8 /mod=11 /x87=08 ST0 ST0 d8 /mod=11 /x87=09 ST0 ST1 d8 /mod=11 /x87=0a ST0 ST2 d8 /mod=11 /x87=0b ST0 ST3 d8 /mod=11 /x87=0c ST0 ST4 d8 /mod=11 /x87=0d ST0 ST5 d8 /mod=11 /x87=0e ST0 ST6 d8 /mod=11 /x87=0f ST0 ST7 fmulp X87 de /mod=11 /x87=08 ST0 ST0 de /mod=11 /x87=09 ST1 ST0 de /mod=11 /x87=0a ST2 ST0 de /mod=11 /x87=0b ST3 ST0 de /mod=11 /x87=0c ST4 ST0 de /mod=11 /x87=0d ST5 ST0 de /mod=11 /x87=0e ST6 ST0 de /mod=11 /x87=0f ST7 ST0 fimul X87 aso rexr rexx rexb da /mod=!11 /reg=1 Md aso rexr rexx rexb de /mod=!11 /reg=1 Mw fnop X87 d9 /mod=11 /x87=10 fndisi X87 db /mod=11 /x87=21 fneni X87 db /mod=11 /x87=20 fnsetpm X87 db /mod=11 /x87=24 fpatan X87 d9 /mod=11 /x87=33 fprem X87 d9 /mod=11 /x87=38 fprem1 X87 d9 /mod=11 /x87=35 fptan X87 d9 /mod=11 /x87=32 frndint X87 d9 /mod=11 /x87=3c frstor X87 aso rexr rexx rexb dd /mod=!11 /reg=4 M frstpm X87 db /mod=11 /x87=25 fnsave X87 aso rexr rexx rexb dd /mod=!11 /reg=6 M fscale X87 d9 /mod=11 /x87=3d fsin X87 d9 /mod=11 /x87=3e fsincos X87 d9 /mod=11 /x87=3b fsqrt X87 d9 /mod=11 /x87=3a fstp X87 aso rexr rexx rexb db /mod=!11 /reg=7 Mt aso rexr rexx rexb dd /mod=!11 /reg=3 Mq aso rexr rexx rexb d9 /mod=!11 /reg=3 Md dd /mod=11 /x87=18 ST0 dd /mod=11 /x87=19 ST1 dd /mod=11 /x87=1a ST2 dd /mod=11 /x87=1b ST3 dd /mod=11 /x87=1c ST4 dd /mod=11 /x87=1d ST5 dd /mod=11 /x87=1e ST6 dd /mod=11 /x87=1f ST7 fstp1 d9 /mod=11 /x87=18 ST0 d9 /mod=11 /x87=19 ST1 d9 /mod=11 /x87=1a ST2 d9 /mod=11 /x87=1b ST3 d9 /mod=11 /x87=1c ST4 d9 /mod=11 /x87=1d ST5 d9 /mod=11 /x87=1e ST6 d9 /mod=11 /x87=1f ST7 fstp8 df /mod=11 /x87=10 ST0 df /mod=11 /x87=11 ST1 df /mod=11 /x87=12 ST2 df /mod=11 /x87=13 ST3 df /mod=11 /x87=14 ST4 df /mod=11 /x87=15 ST5 df /mod=11 /x87=16 ST6 df /mod=11 /x87=17 ST7 fstp9 df /mod=11 /x87=18 ST0 df /mod=11 /x87=19 ST1 df /mod=11 /x87=1a ST2 df /mod=11 /x87=1b ST3 df /mod=11 /x87=1c ST4 df /mod=11 /x87=1d ST5 df /mod=11 /x87=1e ST6 df /mod=11 /x87=1f ST7 fst X87 aso rexr rexx rexb d9 /mod=!11 /reg=2 Md aso rexr rexx rexb dd /mod=!11 /reg=2 Mq dd /mod=11 /x87=10 ST0 dd /mod=11 /x87=11 ST1 dd /mod=11 /x87=12 ST2 dd /mod=11 /x87=13 ST3 dd /mod=11 /x87=14 ST4 dd /mod=11 /x87=15 ST5 dd /mod=11 /x87=16 ST6 dd /mod=11 /x87=17 ST7 fnstcw X87 aso rexr rexx rexb d9 /mod=!11 /reg=7 Mw W fnstenv X87 aso rexr rexx rexb d9 /mod=!11 /reg=6 M W fnstsw X87 aso rexr rexx rexb dd /mod=!11 /reg=7 Mw W df /mod=11 /x87=20 AX W fsub X87 aso rexr rexx rexb d8 /mod=!11 /reg=4 Md aso rexr rexx rexb dc /mod=!11 /reg=4 Mq d8 /mod=11 /x87=20 ST0 ST0 d8 /mod=11 /x87=21 ST0 ST1 d8 /mod=11 /x87=22 ST0 ST2 d8 /mod=11 /x87=23 ST0 ST3 d8 /mod=11 /x87=24 ST0 ST4 d8 /mod=11 /x87=25 ST0 ST5 d8 /mod=11 /x87=26 ST0 ST6 d8 /mod=11 /x87=27 ST0 ST7 dc /mod=11 /x87=28 ST0 ST0 dc /mod=11 /x87=29 ST1 ST0 dc /mod=11 /x87=2a ST2 ST0 dc /mod=11 /x87=2b ST3 ST0 dc /mod=11 /x87=2c ST4 ST0 dc /mod=11 /x87=2d ST5 ST0 dc /mod=11 /x87=2e ST6 ST0 dc /mod=11 /x87=2f ST7 ST0 fsubp X87 de /mod=11 /x87=28 ST0 ST0 de /mod=11 /x87=29 ST1 ST0 de /mod=11 /x87=2a ST2 ST0 de /mod=11 /x87=2b ST3 ST0 de /mod=11 /x87=2c ST4 ST0 de /mod=11 /x87=2d ST5 ST0 de /mod=11 /x87=2e ST6 ST0 de /mod=11 /x87=2f ST7 ST0 fsubr X87 aso rexr rexx rexb dc /mod=!11 /reg=5 Mq d8 /mod=11 /x87=28 ST0 ST0 d8 /mod=11 /x87=29 ST0 ST1 d8 /mod=11 /x87=2a ST0 ST2 d8 /mod=11 /x87=2b ST0 ST3 d8 /mod=11 /x87=2c ST0 ST4 d8 /mod=11 /x87=2d ST0 ST5 d8 /mod=11 /x87=2e ST0 ST6 d8 /mod=11 /x87=2f ST0 ST7 dc /mod=11 /x87=20 ST0 ST0 dc /mod=11 /x87=21 ST1 ST0 dc /mod=11 /x87=22 ST2 ST0 dc /mod=11 /x87=23 ST3 ST0 dc /mod=11 /x87=24 ST4 ST0 dc /mod=11 /x87=25 ST5 ST0 dc /mod=11 /x87=26 ST6 ST0 dc /mod=11 /x87=27 ST7 ST0 aso rexr rexx rexb d8 /mod=!11 /reg=5 Md fsubrp X87 de /mod=11 /x87=20 ST0 ST0 de /mod=11 /x87=21 ST1 ST0 de /mod=11 /x87=22 ST2 ST0 de /mod=11 /x87=23 ST3 ST0 de /mod=11 /x87=24 ST4 ST0 de /mod=11 /x87=25 ST5 ST0 de /mod=11 /x87=26 ST6 ST0 de /mod=11 /x87=27 ST7 ST0 ftst X87 d9 /mod=11 /x87=24 fucom X87 dd /mod=11 /x87=20 ST0 dd /mod=11 /x87=21 ST1 dd /mod=11 /x87=22 ST2 dd /mod=11 /x87=23 ST3 dd /mod=11 /x87=24 ST4 dd /mod=11 /x87=25 ST5 dd /mod=11 /x87=26 ST6 dd /mod=11 /x87=27 ST7 fucomp X87 dd /mod=11 /x87=28 ST0 dd /mod=11 /x87=29 ST1 dd /mod=11 /x87=2a ST2 dd /mod=11 /x87=2b ST3 dd /mod=11 /x87=2c ST4 dd /mod=11 /x87=2d ST5 dd /mod=11 /x87=2e ST6 dd /mod=11 /x87=2f ST7 fucompp X87 da /mod=11 /x87=29 fxam X87 d9 /mod=11 /x87=25 fxch X87 d9 /mod=11 /x87=08 ST0 ST0 d9 /mod=11 /x87=09 ST0 ST1 d9 /mod=11 /x87=0a ST0 ST2 d9 /mod=11 /x87=0b ST0 ST3 d9 /mod=11 /x87=0c ST0 ST4 d9 /mod=11 /x87=0d ST0 ST5 d9 /mod=11 /x87=0e ST0 ST6 d9 /mod=11 /x87=0f ST0 ST7 fxch4 X87 dd /mod=11 /x87=08 ST0 dd /mod=11 /x87=09 ST1 dd /mod=11 /x87=0a ST2 dd /mod=11 /x87=0b ST3 dd /mod=11 /x87=0c ST4 dd /mod=11 /x87=0d ST5 dd /mod=11 /x87=0e ST6 dd /mod=11 /x87=0f ST7 fxch7 X87 df /mod=11 /x87=08 ST0 df /mod=11 /x87=09 ST1 df /mod=11 /x87=0a ST2 df /mod=11 /x87=0b ST3 df /mod=11 /x87=0c ST4 df /mod=11 /x87=0d ST5 df /mod=11 /x87=0e ST6 df /mod=11 /x87=0f ST7 fxrstor aso rexw rexr rexx rexb 0f ae /mod=!11 /reg=1 M R fxrstor64 fxsave aso rexw rexr rexx rexb 0f ae /mod=!11 /reg=0 M W fxsave64 fxtract X87 d9 /mod=11 /x87=34 fyl2x X87 d9 /mod=11 /x87=31 fyl2xp1 X87 d9 /mod=11 /x87=39 hlt ____________ f4 idiv UUUUUU______ rax rdx rax rdx aso oso rexw rexr rexx rexb f7 /reg=7 Ev R rax rax aso rexw rexr rexx rexb f6 /reg=7 Eb R in W ____________ e4 AL Ib oso e5 eAX Ib ec AL DX oso ed eAX DX imul RW MUUUUM______ aso oso rexw rexr rexx rexb 0f af Gv Ev RW R al ax aso rexw rexr rexx rexb f6 /reg=5 Eb RW rax rax rdx aso oso rexw rexr rexx rexb f7 /reg=5 Ev RW aso oso rexw rexr rexx rexb 69 Gv Ev Iz RW R N aso oso rexw rexr rexx rexb 6b Gv Ev sIb RW R N inc RW MMMMM_______ oso 40 R0z RW oso 41 R1z RW oso 42 R2z RW oso 43 R3z RW oso 44 R4z RW oso 45 R5z RW oso 46 R6z RW oso 47 R7z RW aso oso rexw rexr rexx rexb ff /reg=0 Ev RW aso rexw rexr rexx rexb fe /reg=0 Eb RW insb dx rdi rdi ________T___ rep seg 6c insw dx rdi rdi ________T___ rep oso seg 6d /o=16 insd dx rdi rdi ________T___ rep oso seg 6d /o=32 int1 ______R__R__ f1 int3 ______R__R__ cc int ______R__R__ cd Ib N into T_____R__R__ ce /m=!64 inv64 invd ____________ 0f 08 invept intel aso rexw rexr rexx rexb /sse=66 0f 38 80 /m=32 Gd Mo R R aso rexw rexr rexx rexb /sse=66 0f 38 80 /m=64 Gq Mo R R invlpg ____________ aso rexr rexx rexb 0f 01 /reg=7 /mod=!11 Mb R invlpga amd 0f 01 /reg=3 /mod=11 /rm=7 invvpid intel /sse=66 0f 38 81 /m=32 Gd Mo R R /sse=66 0f 38 81 /m=64 Gq Mo R R iretw PPPPPPPPPT__ oso rexw cf /o=16 iretd PPPPPPPPPT__ oso rexw cf /o=32 iretq PPPPPPPPPT__ oso rexw cf /o=64 jo rip T___________ 70 Jb N def64 oso 0f 80 Jz N def64 jno rip T___________ 71 Jb N def64 oso 0f 81 Jz N def64 jb rip _____T______ 72 Jb N def64 oso 0f 82 Jz N def64 jae rip _____T______ 73 Jb def64 oso 0f 83 Jz def64 je jne jz rip __T_________ 74 Jb N def64 oso 0f 84 Jz N def64 jnz rip __T_________ 75 Jb N def64 oso 0f 85 Jz N def64 jbe rip __T__T______ 76 Jb N def64 oso 0f 86 Jz N def64 ja rip __T__T______ 77 Jb def64 oso 0f 87 Jz def64 js rip _T__________ 78 Jb N def64 oso 0f 88 Jz N def64 jns rip _T__________ 79 Jb N def64 oso 0f 89 Jz N def64 jp rip ____T_______ 7a Jb N def64 oso 0f 8a Jz N def64 jnp rip ____T_______ 7b Jb N def64 oso 0f 8b Jz N def64 jl rip TT__________ 7c Jb N def64 oso 0f 8c Jz N def64 jge rip TT__________ 7d Jb N def64 oso 0f 8d Jz N def64 jle rip TTT_________ 7e Jb N def64 oso 0f 8e Jz N def64 jg rip TTT_________ 7f Jb N def64 oso 0f 8f Jz N def64 jcxz rip ____________ aso e3 /a=16 Jb N def64 jecxz rip ____________ aso e3 /a=32 Jb N def64 jrcxz rip ____________ aso e3 /a=64 Jb N def64 jmp rip ____________ aso oso rexw rexr rexx rexb ff /reg=4 Ev R def64 aso oso rexw rexr rexx rexb ff /reg=5 Fv R oso e9 Jz R def64 oso ea /m=!64 Av R eb Jb R def64 lahf ah _TTTTT______ 9f lar W __M_________ aso oso rexw rexr rexx rexb 0f 02 Gv Ew W R ldmxcsr ____________ aso rexw rexr rexx rexb 0f ae /reg=2 /mod=!11 Md R sse avx lds W ____________ aso oso c5 /vex=none /m=!64 Gv M W R lea W ____________ aso oso rexw rexr rexx rexb 8d Gv M W N les W es ____________ aso oso c4 /m=!64 Gv M W R lfs W fs ____________ aso oso rexw rexr rexx rexb 0f b4 Gz M W R lgs W fs ____________ aso oso rexw rexr rexx rexb 0f b5 Gz M W R lidt ____________ aso rexr rexx rexb 0f 01 /reg=3 /mod=!11 M R lss W ss ____________ aso oso rexw rexr rexx rexb 0f b2 Gv M W R leave rbp rbp rsp ____________ c9 lfence ____________ 0f ae /mod=11 /reg=5 lgdt ____________ aso rexr rexx rexb 0f 01 /reg=2 /mod=!11 M R lldt ____________ aso rexr rexx rexb 0f 00 /reg=2 Ew R lmsw cr0 ____________ aso rexr rexx rexb 0f 01 /reg=6 /mod=!11 Ew R aso rexr rexx rexb 0f 01 /reg=6 /mod=11 Ew R lock ____________ f0 lodsb rsi al rsi ________T___ rep seg ac lodsw rsi ax rsi ________T___ rep seg oso rexw ad /o=16 lodsd rsi eax rsi ________T___ rep seg oso rexw ad /o=32 lodsq rsi rax rsi ________T___ rep seg oso rexw ad /o=64 loopne __T_________ e0 Jb N loope __T_________ e1 Jb N loop ____________ e2 Jb N lsl W __M_________ aso oso rexw rexr rexx rexb 0f 03 Gv Ew W R ltr ____________ aso rexr rexx rexb 0f 00 /reg=3 Ew R maskmovq rdi ____________ aso rexr rexx rexb 0f f7 /mod=11 P N R R maxpd RW aso rexr rexx rexb vexl /sse=66 0f 5f V H W W R R sse2 avx maxps RW aso rexr rexx rexb vexl 0f 5f V H W W R R sse avx maxsd RW aso rexr rexx rexb /sse=f2 0f 5f V H MqU W R R sse2 avx maxss RW aso rexr rexx rexb /sse=f3 0f 5f V H MdU W R R sse avx mfence 0f ae /mod=11 /reg=6 minpd RW aso rexr rexx rexb vexl /sse=66 0f 5d V H W W R R sse2 avx minps RW aso rexr rexx rexb vexl 0f 5d V H W W R R sse2 avx minsd RW aso rexr rexx rexb /sse=f2 0f 5d V H MqU W R R sse2 avx minss RW aso rexr rexx rexb /sse=f3 0f 5d V H MdU W R R sse avx monitor rax rdx ____________ 0f 01 /reg=1 /mod=11 /rm=0 montmul 0f a6 /mod=11 /rm=0 /reg=0 mov W ___________ ____________ aso rexw rexr rexx rexb c6 /mod=11 /reg=0 Eb Ib W N aso rexw rexr rexx rexb c6 /mod=!11 /reg=0 Eb Ib W N aso oso rexw rexr rexx rexb c7 /mod=11 /reg=0 Ev sIz W N aso oso rexw rexr rexx rexb c7 /mod=!11 /reg=0 Ev sIz W N aso rexr rexx rexb 88 Eb Gb W R aso oso rexw rexr rexx rexb 89 Ev Gv W R aso rexr rexx rexb 8a Gb Eb W R aso oso rexw rexr rexx rexb 8b Gv Ev W R aso oso rexw rexr rexx rexb 8c MwRv S W R aso oso rexw rexr rexx rexb 8e S MwRv W R a0 AL Ob W R aso oso rexw a1 rAX Ov W R a2 Ob AL W R aso oso rexw a3 Ov rAX W R rexb b0 R0b Ib W N rexb b1 R1b Ib W N rexb b2 R2b Ib W N rexb b3 R3b Ib W N rexb b4 R4b Ib W N rexb b5 R5b Ib W N rexb b6 R6b Ib W N rexb b7 R7b Ib W N oso rexw rexb b8 R0v Iv W N oso rexw rexb b9 R1v Iv W N oso rexw rexb ba R2v Iv W N oso rexw rexb bb R3v Iv W N oso rexw rexb bc R4v Iv W N oso rexw rexb bd R5v Iv W N oso rexw rexb be R6v Iv W N oso rexw rexb bf R7v Iv W N UUUUUU______ rexr rexw rexb 0f 20 R C W R UUUUUU______ rexr rexw rexb 0f 21 R D W R UUUUUU______ rexr rexw rexb 0f 22 C R W R UUUUUU______ rexr rexw rexb 0f 23 D R W R movapd W aso rexr rexx rexb vexl /sse=66 0f 28 V W W R sse2 avx aso rexr rexx rexb vexl /sse=66 0f 29 W V W R sse2 avx movaps W aso rexr rexx rexb vexl 0f 28 V W W R sse avx aso rexr rexx rexb vexl 0f 29 W V W R sse avx movd W aso rexw rexr rexx rexb 0f 6e /o=16 P Ey W R mmx aso rexw rexr rexx rexb 0f 6e /o=32 P Ey W R mmx aso rexw rexr rexx rexb /sse=66 0f 6e /o=16 V Ey W R sse2 avx aso rexw rexr rexx rexb /sse=66 0f 6e /o=32 V Ey W R sse2 avx aso rexw rexr rexx rexb 0f 7e /o=16 Ey P W R mmx aso rexw rexr rexx rexb 0f 7e /o=32 Ey P W R mmx aso rexw rexr rexx rexb /sse=66 0f 7e /o=16 Ey V W R sse2 avx aso rexw rexr rexx rexb /sse=66 0f 7e /o=32 Ey V W R sse2 avx movhpd W aso rexr rexx rexb /sse=66 0f 16 /mod=!11 V H Mq W R R sse2 avx aso rexr rexx rexb /sse=66 0f 17 Mq V W R sse2 avx movhps W aso rexr rexx rexb 0f 16 /mod=!11 V H Mq W R R sse avx aso rexr rexx rexb 0f 17 Mq V W R sse avx movlhps W aso rexr rexx rexb 0f 16 /mod=11 V H U W R R sse avx movlpd W aso rexr rexx rexb /sse=66 0f 12 /mod=!11 V H MqU W R aso rexr rexx rexb /sse=66 0f 13 Mq V W R sse2 avx movlps W aso rexr rexx rexb 0f 12 /mod=!11 V H MqU W R aso rexr rexx rexb 0f 13 Mq V W R sse avx movhlps W aso rexr rexx rexb 0f 12 /mod=11 V H U W R R sse avx movmskpd W oso rexr rexb vexl /sse=66 0f 50 Gd U W R sse2 avx movmskps W oso rexr rexb vexl 0f 50 Gd U W R sse2 avx movntdq W aso rexr rexx rexb vexl /sse=66 0f e7 Mx V W R sse2 avx movnti W aso rexw rexr rexx rexb 0f c3 Mv Gy W R movntpd W aso rexr rexx rexb vexl /sse=66 0f 2b M V W R sse2 avx movntps W aso rexr rexx rexb vexl 0f 2b M V W R sse2 avx movntq W aso rexr rexx rexb 0f e7 Mq P W R movq W aso rexw rexr rexx rexb 0f 6e /o=64 P Eq W R mmx aso rexw rexr rexx rexb /sse=66 0f 6e /o=64 V Eq W R sse2 avx aso rexw rexr rexx rexb 0f 7e /o=64 Eq P W R mmx aso rexw rexr rexx rexb /sse=66 0f 7e /o=64 Eq V W R sse2 avx aso rexw rexr rexx rexb /sse=f3 0f 7e V MqU W R sse2 avx aso rexw rexr rexx rexb /sse=66 0f d6 MqU V W R sse2 avx aso rexw rexr rexx rexb 0f 6f P Q W R mmx aso rexw rexr rexx rexb 0f 7f Q P W R mmx movsb W rsi rsi rdi rdi ________T___ rep seg a4 movsw W rsi rsi rdi rdi ________T___ rep seg oso rexw a5 /o=16 movsd W ________T___ rsi rsi rdi rdi rep seg oso rexw a5 /o=32 aso rexr rexx rexb /sse=f2 0f 10 V MqU W R sse2 aso rexr rexx rexb /sse=f2 0f 11 MqU V W R sse2 movsq W rsi rsi rdi rdi ________T___ rep seg oso rexw a5 /o=64 movss W ________T___ aso rexr rexx rexb /sse=f3 0f 10 V MdU W R sse aso rexr rexx rexb /sse=f3 0f 11 MdU V W R sse movsx W ____________ aso oso rexw rexr rexx rexb 0f be Gv Eb W R aso oso rexw rexr rexx rexb 0f bf Gy Ew W R movupd W aso rexr rexx rexb vexl /sse=66 0f 10 V W W R sse2 avx aso rexr rexx rexb vexl /sse=66 0f 11 W V W R sse2 avx movups W aso rexr rexx rexb vexl 0f 10 V W W R sse2 avx aso rexr rexx rexb vexl 0f 11 W V W R sse2 avx movzx W ____________ aso oso rexw rexr rexx rexb 0f b6 Gv Eb W R aso oso rexw rexr rexx rexb 0f b7 Gy Ew W R mul MUUUUM______ al ax aso rexw rexr rexx rexb f6 /reg=4 Eb R rax rax rdx aso oso rexw rexr rexx rexb f7 /reg=4 Ev R mulpd RW aso rexr rexx rexb vexl /sse=66 0f 59 V H W W R R sse2 avx mulps RW aso rexr rexx rexb vexl 0f 59 V H W W R R sse2 avx mulsd RW aso rexr rexx rexb /sse=f2 0f 59 V H MqU W R R sse2 avx mulss RW aso rexr rexx rexb /sse=f3 0f 59 V H MdU W R R sse avx mwait ____________ 0f 01 /reg=1 /mod=11 /rm=1 neg RW MMMMMM______ aso rexw rexr rexx rexb f6 /reg=3 Eb RW aso oso rexw rexr rexx rexb f7 /reg=3 Ev RW nop ____________ aso rexr rexx rexb 0f 19 M R aso rexr rexx rexb 0f 1c M R aso rexr rexx rexb 0f 1d M R aso rexr rexx rexb 0f 1e /mod=!11 M R aso rexr rexx rexb 0f 1f M R not RW ____________ aso rexw rexr rexx rexb f6 /reg=2 Eb RW aso oso rexw rexr rexx rexb f7 /reg=2 Ev RW or RW RMMUMR______ aso rexr rexx rexb 08 Eb Gb RW R aso oso rexw rexr rexx rexb 09 Ev Gv RW R aso rexr rexx rexb 0a Gb Eb RW R aso oso rexw rexr rexx rexb 0b Gv Ev RW R 0c AL Ib RW N oso rexw 0d rAX sIz RW N aso rexr rexx rexb 80 /reg=1 Eb Ib RW N aso oso rexw rexr rexx rexb 81 /reg=1 Ev sIz RW N aso rexr rexx rexb 82 /reg=1 /m=!64 Eb Ib RW N aso oso rexw rexr rexx rexb 83 /reg=1 Ev sIb RW N orpd RW aso rexr rexx rexb vexl /sse=66 0f 56 V H W W R R sse2 avx orps aso rexr rexx rexb vexl 0f 56 V H W W R R sse avx out ____________ e6 Ib AL N R oso e7 Ib eAX N R ee DX AL R R oso ef DX eAX R R outsb rsi rsi ________T___ rep seg 6e outsw rsi rsi ________T___ rep oso seg 6f /o=16 outsd rsi rsi ________T___ rep oso seg 6f /o=32 packsswb RW aso rexr rexx rexb vexl /sse=66 0f 63 V H W W R R sse2 avx aso rexr rexx rexb 0f 63 P Q RW R mmx packssdw RW aso rexr rexx rexb vexl /sse=66 0f 6b V H W W R R sse2 avx aso rexr rexx rexb 0f 6b P Q RW R mmx packuswb RW aso rexr rexx rexb vexl /sse=66 0f 67 V H W W R R sse2 avx aso rexr rexx rexb 0f 67 P Q RW R mmx paddb RW aso rexr rexx rexb vexl /sse=66 0f fc V H W W R R sse2 avx aso rexr rexx rexb 0f fc P Q RW R mmx paddw RW aso rexr rexx rexb 0f fd P Q RW R mmx aso rexr rexx rexb vexl /sse=66 0f fd V H W W R R sse2 avx paddd RW aso rexr rexx rexb 0f fe P Q RW R mmx aso rexr rexx rexb vexl /sse=66 0f fe V H W W R R sse2 avx paddsb RW aso rexr rexx rexb 0f ec P Q RW R aso rexr rexx rexb vexl /sse=66 0f ec V H W W R R sse2 avx paddsw RW aso rexr rexx rexb 0f ed P Q RW R aso rexr rexx rexb vexl /sse=66 0f ed V H W W R R sse2 avx paddusb RW aso rexr rexx rexb 0f dc P Q RW R aso rexr rexx rexb vexl /sse=66 0f dc V H W W R R sse2 avx paddusw RW aso rexr rexx rexb 0f dd P Q RW R aso rexr rexx rexb vexl /sse=66 0f dd V H W W R R sse2 avx pand RW aso rexr rexx rexb vexl /sse=66 0f db V H W W R R sse2 avx aso rexr rexx rexb 0f db P Q RW R pandn RW aso rexr rexx rexb vexl /sse=66 0f df V H W W R R sse2 avx aso rexr rexx rexb 0f df P Q RW R pavgb RW aso rexr rexx rexb vexl /sse=66 0f e0 V H W W R R sse2 avx aso rexr rexx rexb 0f e0 P Q RW R pavgw RW aso rexr rexx rexb vexl /sse=66 0f e3 V H W W R R sse2 avx aso rexr rexx rexb 0f e3 P Q RW R pcmpeqb RW aso rexr rexx rexb 0f 74 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 74 V H W W R R sse2 avx pcmpeqw RW aso rexr rexx rexb 0f 75 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 75 V H W W R R sse2 avx pcmpeqd RW aso rexr rexx rexb 0f 76 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 76 V H W W R R sse2 avx pcmpgtb RW aso rexr rexx rexb vexl /sse=66 0f 64 V H W W R R sse2 avx aso rexr rexx rexb 0f 64 P Q RW R pcmpgtw RW aso rexr rexx rexb vexl /sse=66 0f 65 V H W W R R sse2 avx aso rexr rexx rexb 0f 65 P Q RW R pcmpgtd RW aso rexr rexx rexb vexl /sse=66 0f 66 V H W W R R sse2 avx aso rexr rexx rexb 0f 66 P Q RW R pextrb W aso rexx rexr rexb /sse=66 0f 3a 14 /vexw=0 MbRd V Ib W R N def64 sse4.1 avx pextrd W aso rexr rexx rexw rexb /sse=66 0f 3a 16 /o=16 /vexw=0 Ed V Ib W R N sse4.1 avx aso rexr rexx rexw rexb /sse=66 0f 3a 16 /o=32 /vexw=0 Ed V Ib W R N sse4.1 avx pextrq W aso rexr rexw rexb /sse=66 0f 3a 16 /o=64 /vexw=1 Eq V Ib W R N def64 sse4.1 avx pextrw W aso rexw rexr rexb /sse=66 0f c5 Gd U Ib W R N sse avx aso rexw rexr rexx rexb 0f c5 Gd N Ib W R N aso rexw rexx rexr rexb /sse=66 0f 3a 15 MwRd V Ib W R N sse4.1 avx pinsrb W aso rexw rexr rexx rexb /sse=66 0f 3a 20 V MbRd Ib W R N sse4.1 pinsrw W aso rexw rexr rexx rexb 0f c4 P MwRd Ib W R N def64 aso rexw rexr rexx rexb /sse=66 0f c4 V H MwRd Ib def64 sse2 avx pinsrd W aso rexw rexr rexx rexb /sse=66 0f 3a 22 /o=16 V Ed Ib W R N sse4.1 aso rexw rexr rexx rexb /sse=66 0f 3a 22 /o=32 V Ed Ib W R N sse4.1 pinsrq W aso oso rexw rexr rexx rexb /sse=66 0f 3a 22 /o=64 V Eq Ib W R N sse4.1 vpinsrb W aso rexw rexr rexx rexb /vex=66_0f3a 20 /vexw=0 /vexl=0 V H MbRd Ib W R R N avx vpinsrd W aso oso rexw rexr rexx rexb /vex=66_0f3a 22 /m=!64 /vexw=0 /vexl=0 V H Ed Ib W R R N avx aso oso rexw rexr rexx rexb /vex=66_0f3a 22 /m=64 /vexw=0 /vexl=0 V H Ed Ib W R R N avx vpinsrq W aso oso rexw rexr rexx rexb /vex=66_0f3a 22 /m=64 /vexw=1 /vexl=0 V H Eq Ib W R R N avx pmaddwd RW aso rexr rexx rexb 0f f5 P Q RW R aso rexr rexx rexb vexl /sse=66 0f f5 V H W W R R sse4.1 avx pmaxsw RW aso rexr rexx rexb vexl /sse=66 0f ee V H W W R R sse4.1 avx aso rexr rexx rexb 0f ee P Q RW R pmaxub RW aso rexr rexx rexb 0f de P Q RW R aso rexr rexx rexb vexl /sse=66 0f de V H W W R R sse2 avx pminsw RW aso rexr rexx rexb vexl /sse=66 0f ea V H W W R R sse2 avx aso rexr rexx rexb 0f ea P Q RW R pminub RW aso rexr rexx rexb vexl /sse=66 0f da V H W W R R sse2 avx aso rexr rexx rexb 0f da P Q RW R pmovmskb W oso rexr rexw rexb vexl /sse=66 0f d7 Gd U W R sse2 avx oso rexr rexw rexb vexl 0f d7 Gd N W R pmulhuw RW aso rexr rexx rexb 0f e4 P Q RW R aso rexr rexx rexb vexl /sse=66 0f e4 V H W W R R sse2 avx pmulhw RW aso rexr rexx rexb vexl /sse=66 0f e5 V H W W R R sse2 avx aso rexr rexx rexb 0f e5 P Q RW R pmullw RW aso rexr rexx rexb 0f d5 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d5 V H W W R R sse2 avx pop W rsp rsp ____________ 07 /m=!64 ES W inv64 17 /m=!64 SS W inv64 1f /m=!64 DS W inv64 0f a9 GS W 0f a1 FS W oso rexb 58 R0v W def64 oso rexb 59 R1v W def64 oso rexb 5a R2v W def64 oso rexb 5b R3v W def64 oso rexb 5c R4v W def64 oso rexb 5d R5v W def64 oso rexb 5e R6v W def64 oso rexb 5f R7v W def64 popa rsp di si bp bx dx cx ax rbp ____________ oso 61 /o=16 /m=!64 inv64 popad rsp edi esi ebp ebx edx ecx eax rbp ____________ oso 61 /o=32 /m=!64 inv64 popfw rsp rsp PPPPPPPPPP__ oso 9d /m=!64 /o=16 oso rexw 9d /m=64 /o=16 def64 popfd rsp rsp PPPPPPPPPP__ oso 9d /m=!64 /o=32 popfq rsp rsp PPPPPPPPPP__ oso 9d /m=64 /o=32 def64 oso 9d /m=64 /o=64 def64 por RW aso rexr rexx rexb vexl /sse=66 0f eb V H W W R R sse2 avx aso rexr rexx rexb 0f eb P Q RW R prefetch aso rexw rexr rexx rexb 0f 0d /reg=0 Mb R aso rexw rexr rexx rexb 0f 0d /reg=3 Mb R aso rexw rexr rexx rexb 0f 0d /reg=4 Mb R aso rexw rexr rexx rexb 0f 0d /reg=5 Mb R aso rexw rexr rexx rexb 0f 0d /reg=6 Mb R aso rexw rexr rexx rexb 0f 0d /reg=7 Mb R prefetchnta aso rexw rexr rexx rexb 0f 18 /reg=0 Mb R prefetcht0 aso rexw rexr rexx rexb 0f 18 /reg=1 Mb R prefetcht1 aso rexw rexr rexx rexb 0f 18 /reg=2 Mb R prefetcht2 aso rexw rexr rexx rexb 0f 18 /reg=3 Mb R prefetchw aso rexw rexr rexx rexb 0f 0d /reg=1 Mb R prfchw prefetchwt1 aso rexw rexr rexx rexb 0f 0d /reg=2 Mb R prefetchwt1 psadbw RW aso rexr rexx rexb /sse=66 0f f6 V H W W R R sse2 avx aso rexr rexx rexb 0f f6 P Q RW R pshufw W aso rexr rexx rexb 0f 70 P Q Ib W R N psllw RW aso rexr rexx rexb /sse=66 0f f1 V W RW R sse2 aso rexr rexx rexb 0f f1 P Q RW R rexb /sse=66 0f 71 /reg=6 U Ib RW N sse2 0f 71 /reg=6 N Ib RW N pslld RW aso rexr rexx rexb /sse=66 0f f2 V W RW R sse2 aso rexr rexx rexb 0f f2 P Q RW R rexb /sse=66 0f 72 /reg=6 U Ib RW N sse2 0f 72 /reg=6 N Ib RW N psllq RW aso rexr rexx rexb /sse=66 0f f3 V W RW R sse2 aso rexr rexx rexb 0f f3 P Q RW R rexb /sse=66 0f 73 /reg=6 U Ib RW N sse2 0f 73 /reg=6 N Ib RW N psraw RW aso rexr rexx rexb 0f e1 P Q RW R aso rexr rexx rexb vexl /sse=66 0f e1 V H MdqU W R R sse2 avx rexb vexl /sse=66 0f 71 /reg=4 H U Ib W R N sse2 avx 0f 71 /reg=4 N Ib RW N psrad RW 0f 72 /reg=4 N Ib RW N aso rexr rexx rexb vexl /sse=66 0f e2 V H Wdq W R R sse2 avx aso rexr rexx rexb 0f e2 P Q RW R rexb vexl /sse=66 0f 72 /reg=4 H U Ib W R N sse2 avx psrlw RW 0f 71 /reg=2 N Ib RW N aso rexr rexx rexb 0f d1 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d1 V H MdqU W R R sse2 avx rexb vexl /sse=66 0f 71 /reg=2 H U Ib W R N sse2 avx psrld RW 0f 72 /reg=2 N Ib RW N aso rexr rexx rexb 0f d2 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d2 V H MdqU W R R sse2 avx rexb vexl /sse=66 0f 72 /reg=2 H U Ib W R N sse2 avx psrlq RW 0f 73 /reg=2 N Ib RW N aso rexr rexx rexb 0f d3 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d3 V H MdqU W R R sse2 avx rexb vexl /sse=66 0f 73 /reg=2 H U Ib W R N sse2 avx psubb RW aso rexr rexx rexb vexl /sse=66 0f f8 V H W W R R sse2 avx aso rexr rexx rexb 0f f8 P Q RW R psubw RW aso rexr rexx rexb vexl /sse=66 0f f9 V H W W R R sse2 avx aso rexr rexx rexb 0f f9 P Q RW R psubd RW aso rexr rexx rexb 0f fa P Q RW R aso rexr rexx rexb vexl /sse=66 0f fa V H W W R R sse2 avx psubsb RW aso rexr rexx rexb 0f e8 P Q RW R aso rexr rexx rexb vexl /sse=66 0f e8 V H W W R R sse2 avx psubsw RW aso rexr rexx rexb 0f e9 P Q RW R aso rexr rexx rexb vexl /sse=66 0f e9 V H W W R R sse2 avx psubusb RW aso rexr rexx rexb 0f d8 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d8 V H W W R R sse2 avx psubusw RW aso rexr rexx rexb 0f d9 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d9 V H W W R R sse2 avx punpckhbw RW aso rexr rexx rexb vexl /sse=66 0f 68 V H W W R R sse2 avx aso rexr rexx rexb 0f 68 P Q RW R punpckhwd RW aso rexr rexx rexb vexl /sse=66 0f 69 V H W W R R sse2 avx aso rexr rexx rexb 0f 69 P Q RW R punpckhdq RW aso rexr rexx rexb vexl /sse=66 0f 6a V H W W R R sse2 avx aso rexr rexx rexb 0f 6a P Q RW R punpcklbw RW aso rexr rexx rexb vexl /sse=66 0f 60 V H W W R R sse2 avx aso rexr rexx rexb 0f 60 P MdU RW R punpcklwd RW aso rexr rexx rexb vexl /sse=66 0f 61 V H W W R R sse2 avx aso rexr rexx rexb 0f 61 P MdU RW R punpckldq RW aso rexr rexx rexb vexl /sse=66 0f 62 V H W W R R sse2 avx aso rexr rexx rexb 0f 62 P MdU RW R pi2fw W aso rexr rexx rexb 0f 0f /3dnow=0c P Q pi2fd W aso rexr rexx rexb 0f 0f /3dnow=0d P Q pf2iw W aso rexr rexx rexb 0f 0f /3dnow=1c P Q pf2id W aso rexr rexx rexb 0f 0f /3dnow=1d P Q pfnacc RW aso rexr rexx rexb 0f 0f /3dnow=8a P Q pfpnacc RW aso rexr rexx rexb 0f 0f /3dnow=8e P Q pfcmpge RW aso rexr rexx rexb 0f 0f /3dnow=90 P Q pfmin RW aso rexr rexx rexb 0f 0f /3dnow=94 P Q pfrcp W aso rexr rexx rexb 0f 0f /3dnow=96 P Q pfrsqrt W aso rexr rexx rexb 0f 0f /3dnow=97 P Q pfsub RW aso rexr rexx rexb 0f 0f /3dnow=9a P Q pfadd RW aso rexr rexx rexb 0f 0f /3dnow=9e P Q pfcmpgt RW aso rexr rexx rexb 0f 0f /3dnow=a0 P Q pfmax RW aso rexr rexx rexb 0f 0f /3dnow=a4 P Q pfrcpit1 W aso rexr rexx rexb 0f 0f /3dnow=a6 P Q pfrsqit1 W aso rexr rexx rexb 0f 0f /3dnow=a7 P Q pfsubr RW aso rexr rexx rexb 0f 0f /3dnow=aa P Q pfacc RW aso rexr rexx rexb 0f 0f /3dnow=ae P Q pfcmpeq RW aso rexr rexx rexb 0f 0f /3dnow=b0 P Q pfmul RW aso rexr rexx rexb 0f 0f /3dnow=b4 P Q pfrcpit2 W aso rexr rexx rexb 0f 0f /3dnow=b6 P Q pmulhrw RW aso rexr rexx rexb 0f 0f /3dnow=b7 P Q pswapd W aso rexr rexx rexb 0f 0f /3dnow=bb P Q pavgusb RW aso rexr rexx rexb 0f 0f /3dnow=bf P Q push rsp rsp ____________ 06 /m=!64 ES R inv64 0e /m=!64 CS R inv64 16 /m=!64 SS R inv64 1e /m=!64 DS R inv64 0f a8 GS R 0f a0 FS R oso rexb 50 R0v R def64 oso rexb 51 R1v R def64 oso rexb 52 R2v R def64 oso rexb 53 R3v R def64 oso rexb 54 R4v R def64 oso rexb 55 R5v R def64 oso rexb 56 R6v R def64 oso rexb 57 R7v R def64 oso 68 sIz N def64 aso oso rexw rexr rexx rexb ff /reg=6 Ev R def64 oso 6a sIb N def64 pusha ax cx dx bx bp si di rsp rsp ____________ oso 60 /o=16 /m=!64 inv64 pushad eax ecx edx ebx ebp esi edi rsp rsp ____________ oso 60 /o=32 /m=!64 inv64 pushfw rsp rsp TTTTTTTTTT__ oso 9c /m=!64 /o=16 oso rexw 9c /m=64 /o=16 def64 pushfd rsp rsp TTTTTTTTTT__ oso 9c /m=!64 /o=32 pushfq rsp rsp TTTTTTTTTT__ oso rexw 9c /m=64 /o=32 def64 oso rexw 9c /m=64 /o=64 def64 pxor RW aso rexr rexx rexb vexl /sse=66 0f ef V H W W R R sse2 avx aso rexr rexx rexb 0f ef P Q RW R rcl RW U____M______ aso rexw rexr rexx rexb c0 /reg=2 Eb Ib W N aso oso rexw rexr rexx rexb c1 /reg=2 Ev Ib W N M____M______ aso rexw rexr rexx rexb d0 /reg=2 Eb I1 W N aso rexw rexr rexx rexb d2 /reg=2 Eb CL W N aso oso rexw rexr rexx rexb d3 /reg=2 Ev CL W N M____M______ aso oso rexw rexr rexx rexb d1 /reg=2 Ev I1 W N rcr RW U____M______ M____M______ aso rexw rexr rexx rexb d0 /reg=3 Eb I1 W N aso oso rexw rexr rexx rexb c1 /reg=3 Ev Ib W N aso rexw rexr rexx rexb c0 /reg=3 Eb Ib W N M____M______ aso oso rexw rexr rexx rexb d1 /reg=3 Ev I1 W N aso rexw rexr rexx rexb d2 /reg=3 Eb CL W N aso oso rexw rexr rexx rexb d3 /reg=3 Ev CL W N rol RW U____M______ aso rexw rexr rexx rexb c0 /reg=0 Eb Ib W N M____M______ aso rexw rexr rexx rexb d0 /reg=0 Eb I1 W N M____M______ aso oso rexw rexr rexx rexb d1 /reg=0 Ev I1 W N aso rexw rexr rexx rexb d2 /reg=0 Eb CL W N aso oso rexw rexr rexx rexb d3 /reg=0 Ev CL W N aso oso rexw rexr rexx rexb c1 /reg=0 Ev Ib W N ror RW U____M______ M____M______ aso rexw rexr rexx rexb d0 /reg=1 Eb I1 W N aso rexw rexr rexx rexb c0 /reg=1 Eb Ib W N aso oso rexw rexr rexx rexb c1 /reg=1 Ev Ib W N M____M______ aso oso rexw rexr rexx rexb d1 /reg=1 Ev I1 W N aso rexw rexr rexx rexb d2 /reg=1 Eb CL W N aso oso rexw rexr rexx rexb d3 /reg=1 Ev CL W N rcpps W aso rexr rexx rexb vexl 0f 53 V W W R sse avx rcpss W aso rexr rexx rexb /sse=f3 0f 53 V H MdU W R R sse avx rdmsr ecx rdx rax ____________ 0f 32 rdpmc ecx rdx rax ____________ 0f 33 rdtsc rdx rax ____________ 0f 31 rdtscp ecx edx eax amd 0f 01 /reg=7 /mod=11 /rm=1 repne rcx rcx ____________ f2 rep rcx rcx ____________ f3 ret rsp rsp rip ____________ c2 Iw N c3 retf rsp rsp rip ca Iw cb rsm MMMMMMMMMMM_ 0f aa rsqrtps W aso rexr rexx rexb vexl 0f 52 V W W R sse avx rsqrtss W aso rexr rexx rexb /sse=f3 0f 52 V H MdU W R R sse avx sahf ah _PPPPP______ 9e sal RW MMMUMM______ salc RW _____T______ d6 /m=!64 inv64 sar RW UMMUMM______ MMMUMM______ aso oso rexw rexr rexx rexb d1 /reg=7 Ev I1 RW N aso rexw rexr rexx rexb c0 /reg=7 Eb Ib RW N MMMUMM______ aso rexw rexr rexx rexb d0 /reg=7 Eb I1 RW N aso oso rexw rexr rexx rexb c1 /reg=7 Ev Ib RW N aso rexw rexr rexx rexb d2 /reg=7 Eb CL RW N aso oso rexw rexr rexx rexb d3 /reg=7 Ev CL RW N shl RW UMMUMM______ aso rexw rexr rexx rexb c0 /reg=6 Eb Ib RW N aso oso rexw rexr rexx rexb c1 /reg=6 Ev Ib RW N MMMUMM______ aso rexw rexr rexx rexb d0 /reg=6 Eb I1 RW N aso rexw rexr rexx rexb d2 /reg=6 Eb CL RW N aso oso rexw rexr rexx rexb d3 /reg=6 Ev CL RW N aso oso rexw rexr rexx rexb c1 /reg=4 Ev Ib RW N aso rexr rexx rexb d2 /reg=4 Eb CL RW N MMMUMM______ aso oso rexw rexr rexx rexb d1 /reg=4 Ev I1 RW N MMMUMM______ aso rexw rexr rexx rexb d0 /reg=4 Eb I1 RW N aso rexw rexr rexx rexb c0 /reg=4 Eb Ib RW N aso oso rexw rexr rexx rexb d3 /reg=4 Ev CL RW N MMMUMM______ aso oso rexw rexr rexx rexb d1 /reg=6 Ev I1 RW N shr RW UMMUMM______ aso oso rexw rexr rexx rexb c1 /reg=5 Ev Ib RW N aso rexw rexr rexx rexb d2 /reg=5 Eb CL RW N MMMUMM______ aso oso rexw rexr rexx rexb d1 /reg=5 Ev I1 RW N MMMUMM______ aso rexw rexr rexx rexb d0 /reg=5 Eb I1 RW N aso rexw rexr rexx rexb c0 /reg=5 Eb Ib RW N aso oso rexw rexr rexx rexb d3 /reg=5 Ev CL RW N sbb W MMMMMM______ aso rexr rexx rexb 18 Eb Gb W R aso oso rexw rexr rexx rexb 19 Ev Gv W R aso rexr rexx rexb 1a Gb Eb W R aso oso rexw rexr rexx rexb 1b Gv Ev W R al al 1c AL Ib W N eax eax oso rexw 1d rAX sIz W N aso rexr rexx rexb 80 /reg=3 Eb Ib W N aso oso rexw rexr rexx rexb 81 /reg=3 Ev sIz W N aso rexr rexx rexb 82 /reg=3 /m=!64 Eb Ib W N inv64 aso oso rexw rexr rexx rexb 83 /reg=3 Ev sIb W N scasb al rdi rdi MMMMMM__T___ repz ae scasw ax rdi rdi MMMMMM__T___ repz oso rexw af /o=16 scasd eax rdi rdi MMMMMM__T___ repz oso rexw af /o=32 scasq rax rdi rdi MMMMMM__T___ repz oso rexw af /o=64 seto W T___________ aso rexr rexx rexb 0f 90 Eb W setno W T___________ aso rexr rexx rexb 0f 91 Eb W setb W _____T______ aso rexr rexx rexb 0f 92 Eb W setae W _____T______ aso rexr rexx rexb 0f 93 Eb W sete W __T_________ aso rexr rexx rexb 0f 94 Eb W setne W __T_________ aso rexr rexx rexb 0f 95 Eb W setbe W __T__T______ aso rexr rexx rexb 0f 96 Eb W seta W __T__T______ aso rexr rexx rexb 0f 97 Eb W sets W _T__________ aso rexr rexx rexb 0f 98 Eb W setns W _T__________ aso rexr rexx rexb 0f 99 Eb W setp W ____T_______ aso rexr rexx rexb 0f 9a Eb W setnp W ____T_______ aso rexr rexx rexb 0f 9b Eb W setl W TT__________ aso rexr rexx rexb 0f 9c Eb W setge W TT__________ aso rexr rexx rexb 0f 9d Eb W setle W TTT_________ aso rexr rexx rexb 0f 9e Eb W setg W TTT_________ aso rexr rexx rexb 0f 9f Eb W sfence 0f ae /reg=7 /mod=11 /rm=0 0f ae /reg=7 /mod=11 /rm=1 0f ae /reg=7 /mod=11 /rm=2 0f ae /reg=7 /mod=11 /rm=3 0f ae /reg=7 /mod=11 /rm=4 0f ae /reg=7 /mod=11 /rm=5 0f ae /reg=7 /mod=11 /rm=6 0f ae /reg=7 /mod=11 /rm=7 sgdt ____________ aso rexr rexx rexb 0f 01 /reg=0 /mod=!11 M W shld RW UMMUMM______ aso oso rexw rexr rexx rexb 0f a4 Ev Gv Ib W R N aso oso rexw rexr rexx rexb 0f a5 Ev Gv CL W R R shrd RW UMMUMM______ aso oso rexw rexr rexx rexb 0f ac Ev Gv Ib W R N aso oso rexw rexr rexx rexb 0f ad Ev Gv CL W R R shufpd RW aso rexr rexx rexb vexl /sse=66 0f c6 V H W Ib W R R N sse2 avx shufps RW aso rexr rexx rexb vexl 0f c6 V H W Ib W R R N sse2 avx sidt W ____________ aso rexr rexx rexb 0f 01 /reg=1 /mod=!11 M W sldt W ____________ aso oso rexr rexw rexx rexb 0f 00 /reg=0 MwRv W smsw W ____________ aso oso rexr rexw rexx rexb 0f 01 /reg=4 /mod=!11 MwRv W aso oso rexr rexw rexx rexb 0f 01 /reg=4 /mod=11 MwRv W sqrtps W aso rexr rexx rexb vexl 0f 51 V W W R sse avx sqrtpd W aso rexr rexx rexb vexl /sse=66 0f 51 V W W R sse2 avx sqrtsd W aso rexr rexx rexb /sse=f2 0f 51 V H MqU W R R sse2 avx sqrtss W aso rexr rexx rexb /sse=f3 0f 51 V H MdU W R R sse avx stac ___________S 0f 01 /reg=1 /mod=11 /rm=3 smap stc _____S______ f9 std ________S___ fd stgi amd 0f 01 /reg=3 /mod=11 /rm=4 sti _______S____ fb skinit rax rbx rcx rdx rsi rdi rbp rsp cr0 amd 0f 01 /reg=3 /mod=11 /rm=6 stmxcsr W aso rexw rexr rexx rexb 0f ae /mod=!11 /reg=3 Md W sse avx stosb al rdi rdi ________T___ rep seg aa stosw ax rdi rdi ________T___ rep seg oso rexw ab /o=16 stosd eax rdi rdi ________T___ rep seg oso rexw ab /o=32 stosq rax rdi rdi ________T___ rep seg oso rexw ab /o=64 str ____________ aso oso rexr rexw rexx rexb 0f 00 /reg=1 MwRv W sub RW MMMMMM______ aso rexr rexx rexb 28 Eb Gb RW R aso oso rexw rexr rexx rexb 29 Ev Gv RW R aso rexr rexx rexb 2a Gb Eb RW R aso oso rexw rexr rexx rexb 2b Gv Ev RW R 2c AL Ib RW N oso rexw 2d rAX sIz RW N aso rexr rexx rexb 80 /reg=5 Eb Ib RW N aso oso rexw rexr rexx rexb 81 /reg=5 Ev sIz RW N aso rexr rexx rexb 82 /reg=5 /m=!64 Eb Ib RW N inv64 aso oso rexw rexr rexx rexb 83 /reg=5 Ev sIb RW N subpd RW aso rexr rexx rexb vexl /sse=66 0f 5c V H W W R R sse2 avx subps RW aso rexr rexx rexb vexl 0f 5c V H W W R R sse avx subsd RW aso rexr rexx rexb /sse=f2 0f 5c V H MqU W R R sse2 avx subss RW aso rexr rexx rexb /sse=f3 0f 5c V H MdU W R R sse avx swapgs gs 0f 01 /reg=7 /mod=11 /rm=0 syscall rip rcx r11 rip MMMMMMMMMMM_ 0f 05 sysenter rsp rip MMMMMMMMMMM_ 0f 34 /m=!64 0f 34 /m=64 intel sysexit rsp rip MMMMMMMMMMM_ 0f 35 /m=!64 0f 35 /m=64 intel sysret rcx rip MMMMMMMMMMM_ 0f 07 test RMMUMR______ aso rexw rexr rexx rexb f6 /reg=0 Eb Ib R N aso rexr rexx rexb 84 Eb Gb R R aso oso rexw rexr rexx rexb 85 Ev Gv R R a8 AL Ib R N oso rexw a9 rAX sIz R N aso rexw rexr rexx rexb f6 /reg=1 Eb Ib R N aso oso rexw rexr rexx rexb f7 /reg=0 Ev sIz R N aso oso rexw rexr rexx rexb f7 /reg=1 Ev Iz R N ucomisd RRMRMM______ aso rexr rexx rexb /sse=66 0f 2e V MqU R R sse2 avx ucomiss RRMRMM______ aso rexr rexx rexb 0f 2e V MdU R R sse avx ud1 0f b9 ud2 ____________ 0f 0b unpckhpd RW aso rexr rexx rexb vexl /sse=66 0f 15 V H W W R R sse2 avx unpckhps RW aso rexr rexx rexb vexl 0f 15 V H W W R R sse avx unpcklps RW aso rexr rexx rexb vexl 0f 14 V H W W R R sse avx unpcklpd RW aso rexr rexx rexb vexl /sse=66 0f 14 V H W W R R sse2 avx verr __M_________ aso rexr rexx rexb 0f 00 /reg=4 Ew R verw __M_________ aso rexr rexx rexb 0f 00 /reg=5 Ew R vmcall intel 0f 01 /reg=0 /mod=11 /rm=1 rdrand W oso rexr rexw rexx rexb 0f c7 /mod=11 /reg=6 Rv W rdrand rdseed RRRRRM______ oso rexr rexw rexx rexb 0F C7 /mod=11 /reg=7 Ev W rdseed vmclear intel aso rexr rexx rexb /sse=66 0f c7 /mod=!11 /reg=6 Mq R vmxon intel aso rexr rexx rexb /sse=f3 0f c7 /mod=!11 /reg=6 Mq R vmptrld intel aso rexr rexx rexb 0f c7 /mod=!11 /reg=6 Mq R vmptrst intel aso rexr rexx rexb 0f c7 /mod=!11 /reg=7 Mq W vmlaunch intel 0f 01 /reg=0 /mod=11 /rm=2 vmresume intel 0f 01 /reg=0 /mod=11 /rm=3 vmxoff intel 0f 01 /reg=0 /mod=11 /rm=4 vmread intel aso rexr rexx rexb 0f 78 Ey Gy W R def64 vmwrite intel aso rexr rexx rexb 0f 79 Gy Ey W R def64 vmrun amd 0f 01 /reg=3 /mod=11 /rm=0 vmmcall amd 0f 01 /reg=3 /mod=11 /rm=1 vmload amd 0f 01 /reg=3 /mod=11 /rm=2 vmsave amd 0f 01 /reg=3 /mod=11 /rm=3 wait ____________ 9b wbinvd ____________ 0f 09 wrmsr edx eax ____________ 0f 30 xadd RW W MMMMMM______ aso oso rexr rexx rexb 0f c0 Eb Gb RW W aso oso rexw rexr rexx rexb 0f c1 Ev Gv RW W xchg RW RW ____________ aso rexr rexx rexb 86 Eb Gb RW RW aso oso rexw rexr rexx rexb 87 Ev Gv RW RW oso rexw rexb 90 R0v rAX RW RW oso rexw rexb 91 R1v rAX RW RW oso rexw rexb 92 R2v rAX RW RW oso rexw rexb 93 R3v rAX RW RW oso rexw rexb 94 R4v rAX RW RW oso rexw rexb 95 R5v rAX RW RW oso rexw rexb 96 R6v rAX RW RW oso rexw rexb 97 R7v rAX RW RW xgetbv ecx edx eax 0f 01 /mod=11 /reg=2 /rm=0 xlatb al ebx al ____________ rexw seg d7 xor RW RMMUMR______ aso rexr rexx rexb 30 Eb Gb RW R aso oso rexw rexr rexx rexb 31 Ev Gv RW R aso rexr rexx rexb 32 Gb Eb RW R aso oso rexw rexr rexx rexb 33 Gv Ev RW R 34 AL Ib RW N oso rexw 35 rAX sIz RW N aso rexr rexx rexb 80 /reg=6 Eb Ib RW N aso oso rexw rexr rexx rexb 81 /reg=6 Ev sIz RW N aso rexr rexx rexb 82 /reg=6 /m=!64 Eb Ib RW N inv64 aso oso rexw rexr rexx rexb 83 /reg=6 Ev sIb RW N xorpd RW aso rexr rexx rexb vexl /sse=66 0f 57 V H W W R R sse2 avx xorps RW aso rexr rexx rexb vexl 0f 57 V H W W R R sse2 avx xcryptecb eax edx ebx rsi rdi rsi rdi 0f a7 /mod=11 /rm=0 /reg=1 xcryptcbc eax edx ebx rsi rdi rsi rdi 0f a7 /mod=11 /rm=0 /reg=2 xcryptctr eax edx ebx rsi rdi rsi rdi 0f a7 /mod=11 /rm=0 /reg=3 xcryptcfb eax edx ebx rsi rdi rsi rdi 0f a7 /mod=11 /rm=0 /reg=4 xcryptofb eax edx ebx rsi rdi rsi rdi 0f a7 /mod=11 /rm=0 /reg=5 xrstor edx eax aso rexw rexr rexx rexb 0f ae /reg=5 /mod=!11 M R xsave xsave edx eax aso rexw rexr rexx rexb 0f ae /reg=4 /mod=!11 M W xsave xsaveopt ____________ aso rexw rexr rexx rexb 0f ae /reg=6 /mod=!11 M W xsave xsetbv edx eax 0f 01 /mod=11 /reg=2 /rm=1 xsha1 eax esi edi eax esi edi 0f a6 /mod=11 /rm=0 /reg=1 xsha256 eax esi edi eax esi edi 0f a6 /mod=11 /rm=0 /reg=2 xstore edx edi eax edi 0f a7 /mod=11 /rm=0 /reg=0 pclmulqdq RW aso rexr rexx rexb /sse=66 0f 3a 44 V H W Ib W R R N aesni avx getsec smx 0f 37 movdqa W aso rexr rexx rexb vexl /sse=66 0f 7f W V W R aso rexr rexx rexb vexl /sse=66 0f 6f V W W R sse2 avx maskmovdqu rdi aso rexr rexx rexb /sse=66 0f f7 /mod=11 V U R R sse2 avx movdq2q W aso rexb /sse=f2 0f d6 P U W R movdqu W aso rexr rexx rexb vexl /sse=f3 0f 6f V W W R aso rexr rexx rexb vexl /sse=f3 0f 7f W V W R sse2 avx movq2dq W aso rexr /sse=f3 0f d6 V N W R paddq RW aso rexr rexx rexb 0f d4 P Q RW R aso rexr rexx rexb vexl /sse=66 0f d4 V H W W R R sse2 avx psubq RW aso rexr rexx rexb vexl /sse=66 0f fb V H W W R R sse2 avx aso rexr rexx rexb 0f fb P Q RW R pmuludq RW aso rexr rexx rexb 0f f4 P Q RW R aso rexr rexx rexb vexl /sse=66 0f f4 V H W W R R sse2 avx pshufhw W aso rexr rexx rexb vexl /sse=f3 0f 70 V W Ib W R N sse2 avx pshuflw W aso rexr rexx rexb vexl /sse=f2 0f 70 V W Ib W R N sse2 avx pshufd W aso rexr rexx rexb vexl /sse=66 0f 70 V W Ib W R N sse2 avx pslldq RW rexb vexl /sse=66 0f 73 /reg=7 H U Ib W R N sse2 avx psrldq RW rexb vexl /sse=66 0f 73 /reg=3 H U Ib W R N sse2 avx punpckhqdq RW aso rexr rexx rexb vexl /sse=66 0f 6d V H W W R R sse2 avx punpcklqdq RW aso rexr rexx rexb vexl /sse=66 0f 6c V H W W R R sse2 avx haddpd RW aso rexr rexx rexb vexl /sse=66 0f 7c V H W W R R sse3 avx haddps RW aso rexr rexx rexb vexl /sse=f2 0f 7c V H W W R R sse3 avx hsubpd RW aso rexr rexx rexb vexl /sse=66 0f 7d V H W W R R sse3 avx hsubps RW aso rexr rexx rexb vexl /sse=f2 0f 7d V H W W R R sse3 avx insertps W aso rexr rexw rexx rexb /sse=66 0f 3a 21 V H MdU Ib W R R N sse4.1 avx lddqu W aso oso rexr rexx rexb vexl /sse=f2 0f f0 V M W R sse3 avx movddup W aso oso rexr rexx rexb /sse=f2 0f 12 /mod=!11 V W W R sse3 vmovddup aso rexr rexx rexb vexl /vex=f2_0f 12 /vexl=0 V MqU W R aso rexr rexx rexb vexl /vex=f2_0f 12 /vexl=1 V W W R avx movshdup W aso rexr rexx rexb vexl /sse=f3 0f 16 /mod=11 V W W R sse3 avx aso rexr rexx rexb vexl /sse=f3 0f 16 /mod=!11 V W W R sse3 avx movsldup W aso rexr rexx rexb vexl /sse=f3 0f 12 /mod=11 V W W R sse3 avx aso rexr rexx rexb vexl /sse=f3 0f 12 /mod=!11 V W W R sse3 avx pabsb W aso rexr rexx rexb 0f 38 1c P Q W R ssse3 aso rexr rexx rexb vexl /sse=66 0f 38 1c V W W R ssse3 avx pabsw W aso rexr rexx rexb 0f 38 1d P Q W R ssse3 aso rexr rexx rexb vexl /sse=66 0f 38 1d V W W R ssse3 avx pabsd W aso rexr rexx rexb 0f 38 1e P Q W R ssse3 aso rexr rexx rexb vexl /sse=66 0f 38 1e V W W R ssse3 avx pshufb RW aso rexr rexx rexb 0f 38 00 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 00 V H W W R R ssse3 avx phaddw RW aso rexr rexx rexb 0f 38 01 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 01 V H W W R R ssse3 avx phaddd RW aso rexr rexx rexb 0f 38 02 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 02 V H W W R R ssse3 avx phaddsw RW aso rexr rexx rexb 0f 38 03 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 03 V H W W R R ssse3 avx pmaddubsw RW aso rexr rexx rexb 0f 38 04 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 04 V H W W R R ssse3 avx phsubw RW aso rexr rexx rexb 0f 38 05 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 05 V H W RW R R ssse3 avx phsubd RW aso rexr rexx rexb 0f 38 06 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 06 V H W RW R R ssse3 avx phsubsw RW aso rexr rexx rexb 0f 38 07 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 07 V H W RW R R ssse3 avx psignb RW aso rexr rexx rexb 0f 38 08 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 08 V H W W R R ssse3 avx psignd RW aso rexr rexx rexb 0f 38 0a P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 0a V H W W R R ssse3 avx psignw RW aso rexr rexx rexb 0f 38 09 P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 09 V H W W R R ssse3 avx pmulhrsw RW aso rexr rexx rexb 0f 38 0b P Q RW R aso rexr rexx rexb vexl /sse=66 0f 38 0b V H W W R R ssse3 avx palignr RW aso rexr rexx rexb 0f 3a 0f P Q Ib RW R N aso rexr rexx rexb vexl /sse=66 0f 3a 0f V H W Ib W R R N ssse3 avx pblendvb RW aso rexr rexx rexb /sse=66 0f 38 10 V W IMP_XMM0 RW R R sse4.1 avx pmuldq RW aso rexr rexx rexb vexl /sse=66 0f 38 28 V H W W R R sse4.1 avx pminsb RW aso rexr rexx rexb vexl /sse=66 0f 38 38 V H W W R R sse4.1 avx pminsd RW aso rexr rexx rexb vexl /sse=66 0f 38 39 V H W W R R sse4.1 avx pminuw RW aso rexr rexx rexb vexl /sse=66 0f 38 3a V H W W R R sse4.1 avx pminud RW aso rexr rexx rexb vexl /sse=66 0f 38 3b V H W W R R sse4.1 avx pmaxsb RW aso rexr rexx rexb vexl /sse=66 0f 38 3c V H W W R R sse4.1 avx pmaxsd RW aso rexr rexx rexb vexl /sse=66 0f 38 3d V H W W R R sse4.1 avx pmaxud RW aso rexr rexx rexb vexl /sse=66 0f 38 3f V H W W R R sse4.1 avx pmaxuw RW aso rexr rexx rexb vexl /sse=66 0f 38 3e V H W W R R sse4.1 avx pmulld RW aso rexr rexx rexb vexl /sse=66 0f 38 40 V H W W R R sse4.1 avx phminposuw W aso rexr rexx rexb /sse=66 0f 38 41 V W W R sse4.1 avx roundps W aso rexr rexx rexb vexl /sse=66 0f 3a 08 V W Ib W R N sse avx roundpd W aso rexr rexx rexb vexl /sse=66 0f 3a 09 V W Ib W R N sse4.1 avx roundss W aso rexr rexx rexb /sse=66 0f 3a 0a V H MdU Ib W R R N sse4.1 avx roundsd W aso rexr rexx rexb /sse=66 0f 3a 0b V H MqU Ib W R R N sse4.1 avx blendpd RW aso rexr rexx rexb vexl /sse=66 0f 3a 0d V H W Ib W R R N sse4.1 avx blendps RW aso rexr rexx rexb vexl /sse=66 0f 3a 0c V H W Ib W R R N sse4.1 avx blendvpd RW aso rexr rexx rexb /sse=66 0f 38 15 V W IMP_XMM0 RW R R sse4.1 blendvps RW aso rexr rexx rexb /sse=66 0f 38 14 V W IMP_XMM0 RW R R sse4.1 bound ____________ aso oso 62 /m=!64 Gv M R R bsf W UUMUUU______ aso oso rexw rexr rexx rexb 0f bc Gv Ev W R bsr W UUMUUU______ aso oso rexw rexr rexx rexb 0f bd Gv Ev W R bswap RW ____________ oso rexw rexb 0f c8 R0y RW oso rexw rexb 0f c9 R1y RW oso rexw rexb 0f ca R2y RW oso rexw rexb 0f cb R3y RW oso rexw rexb 0f cc R4y RW oso rexw rexb 0f cd R5y RW oso rexw rexb 0f ce R6y RW oso rexw rexb 0f cf R7y RW bt UU_UUM______ aso oso rexw rexr rexx rexb 0f ba /reg=4 Ev Ib R N aso oso rexw rexr rexx rexb 0f a3 Ev Gv R R btc RW UU_UUM______ aso oso rexw rexr rexx rexb 0f bb Ev Gv RW R aso oso rexw rexr rexx rexb 0f ba /reg=7 Ev Ib RW N btr RW UU_UUM______ aso oso rexw rexr rexx rexb 0f b3 Ev Gv RW R aso oso rexw rexr rexx rexb 0f ba /reg=6 Ev Ib RW N bts RW UU_UUM______ aso oso rexw rexr rexx rexb 0f ab Ev Gv RW R aso oso rexw rexr rexx rexb 0f ba /reg=5 Ev Ib RW N pblendw RW aso rexr rexx rexb vexl /sse=66 0f 3a 0e V H W Ib W R R N sse4.1 avx mpsadbw RW aso rexr rexx rexb vexl /sse=66 0f 3a 42 V H W Ib W R R N sse4.1 avx movntdqa W aso rexr rexw rexx rexb vexl /sse=66 0f 38 2a V Mx W R sse4.1 avx packusdw RW aso rexr rexw rexx rexb vexl /sse=66 0f 38 2b V H W W R R sse2 avx pmovsxbw W aso rexr rexw rexx rexb /sse=66 0f 38 20 V MqU W R sse4.1 vpmovsxbw aso rexr rexw rexx rexb vexl /vex=66_0f38 20 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 20 /vexl=1 V MdqU W R avx pmovsxbd W aso rexr rexw rexx rexb /sse=66 0f 38 21 V MdU W R sse4.1 vpmovsxbd aso rexr rexw rexx rexb vexl /vex=66_0f38 21 /vexl=0 V MdU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 21 /vexl=1 V MqU W R avx pmovsxbq W aso rexr rexw rexx rexb /sse=66 0f 38 22 V MwU W R sse4.1 vpmovsxbq W aso rexr rexw rexx rexb vexl /vex=66_0f38 22 /vexl=0 V MwU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 22 /vexl=1 V MdU W R avx pmovsxwd W aso rexr rexw rexx rexb /sse=66 0f 38 23 V MqU W R sse4.1 vpmovsxwd W aso rexr rexw rexx rexb vexl /vex=66_0f38 23 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 23 /vexl=1 V MdqU W R avx pmovsxwq W aso rexr rexw rexx rexb /sse=66 0f 38 24 V MdU W R sse4.1 vpmovsxwq W aso rexr rexw rexx rexb vexl /vex=66_0f38 24 /vexl=0 V MdU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 24 /vexl=1 V MqU W R avx pmovsxdq W aso rexr rexw rexx rexb /sse=66 0f 38 25 V MqU W R sse4.1 vpmovsxdq W aso rexr rexw rexx rexb vexl /vex=66_0f38 25 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 25 /vexl=1 V MdqU W R avx pmovzxbw W aso rexr rexw rexx rexb /sse=66 0f 38 30 V MqU W R sse4.1 vpmovzxbw W aso rexr rexw rexx rexb vexl /vex=66_0f38 30 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 30 /vexl=1 V MdqU W R avx pmovzxbd W aso rexr rexw rexx rexb /sse=66 0f 38 31 V MdU W R sse4.1 vpmovzxbd W aso rexr rexw rexx rexb vexl /vex=66_0f38 31 /vexl=0 V MdU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 31 /vexl=1 V MqU W R avx pmovzxbq W aso rexr rexw rexx rexb /sse=66 0f 38 32 V MwU W R sse4.1 vpmovzxbq W aso rexr rexw rexx rexb vexl /vex=66_0f38 32 /vexl=0 V MwU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 32 /vexl=1 V MdU W R avx pmovzxwd W aso rexr rexw rexx rexb /sse=66 0f 38 33 V MqU W R sse4.1 vpmovzxwd W aso rexr rexw rexx rexb vexl /vex=66_0f38 33 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 33 /vexl=1 V MdqU W R avx pmovzxwq W aso rexr rexw rexx rexb /sse=66 0f 38 34 V MdU W R sse4.1 vpmovzxwq W aso rexr rexw rexx rexb vexl /vex=66_0f38 34 /vexl=0 V MdU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 34 /vexl=1 V MqU W R avx pmovzxdq W aso rexr rexw rexx rexb /sse=66 0f 38 35 V MqU W R sse4.1 vpmovzxdq W aso rexr rexw rexx rexb vexl /vex=66_0f38 35 /vexl=0 V MqU W R avx aso rexr rexw rexx rexb vexl /vex=66_0f38 35 /vexl=1 V MdqU W R avx pcmpeqq aso rexr rexw rexx rexb vexl /sse=66 0f 38 29 V H W W R R sse4.1 avx popcnt W RRMRRR______ aso oso rexr rexw rexx rexb /sse=f3 0f b8 Gv Ev W R sse4.2 ptest aso rexr rexw rexx rexb vexl /sse=66 0f 38 17 V W R R sse4.1 avx pcmpestri aso rexr rexw rexx rexb /sse=66 0f 3a 61 V W Ib R R N sse4.2 avx pcmpestrm aso rexr rexw rexx rexb /sse=66 0f 3a 60 V W Ib R R N sse4.2 avx pcmpgtq aso rexr rexw rexx rexb vexl /sse=66 0f 38 37 V H W W R R sse4.2 avx pcmpistri aso rexr rexw rexx rexb /sse=66 0f 3a 63 V W Ib R R N sse4.2 avx pcmpistrm aso rexr rexw rexx rexb /sse=66 0f 3a 62 V W Ib R R N sse4.2 avx movbe W aso oso rexr rexw rexx rexb 0f 38 f0 Gv Mv W R sse3 atom aso oso rexr rexw rexx rexb 0f 38 f1 Mv Gv W R sse3 atom crc32 RW aso oso rexr rexw rexx rexb /sse=f2 0f 38 f0 Gy Eb RW R sse4.2 aso oso rexr rexw rexx rexb /sse=f2 0f 38 f1 Gy Ev RW R sse4.2 invalid vbroadcastss W aso rexr rexx rexb vexl /vex=66_0f38 18 /vexw=0 V MdU W R avx vbroadcastsd W aso rexr rexx rexb vexl /vex=66_0f38 19 /vexw=0 /vexl=1 Vqq MqU W R avx vpmaskmovq aso rexr rexx rexb vexl /vex=66_0f38 8c /vexw=1 V H M W R R avx aso rexr rexx rexb vexl /vex=66_0f38 8e /vexw=1 M H V W R R avx vextractf128 W aso rexr rexx rexb vexl /vex=66_0f3a 19 /vexw=0 /vexl=1 Wdq Vqq Ib W R N avx vinsertf128 W aso rexr rexx rexb vexl /vex=66_0f3a 18 /vexw=0 /vexl=1 Vqq Hqq Wdq Ib W R R N avx vmaskmovps W aso rexr rexx rexb vexl /vex=66_0f38 2c /vexw=0 V H M W R R avx aso rexr rexx rexb vexl /vex=66_0f38 2e /vexw=0 M H V W R R avx vmaskmovpd W avx aso oso vexl rexw rexr rexx rexb /vex=66_0f38 2d /vexw=0 Vx Hx Mx W R R aso oso vexl rexw rexr rexx rexb /vex=66_0f38 2f /vexw=0 Mx Hx Vx W R R vbroadcastf128 aso rexr rexx rexb vexl /vex=66_0f38 1a /vexw=0 /vexl=1 Vqq Mdq W R avx vpblendd aso rexr rexx rexb vexl /vex=66_0f3a 02 /vexw=0 V H W Ib W R R N avx vpermilpd W aso rexr rexx rexb vexl /vex=66_0f38 0d /vexw=0 Vx Hx Wx W R R avx aso rexr rexx rexb vexl /vex=66_0f3a 05 /vexw=0 V W Ib W R N avx vpmaskmovd aso rexr rexx rexb vexl /vex=66_0f38 8c /vexw=0 V H M W R R avx aso rexr rexx rexb vexl /vex=66_0f38 8e /vexw=0 M H V W R R avx vpermilps W aso rexr rexx rexb vexl /vex=66_0f38 0c /vexw=0 Vx Hx Wx W R R avx aso rexr rexx rexb vexl /vex=66_0f3a 04 /vexw=0 Vx Wx Ib W R N avx vperm2f128 W aso rexr rexx rexb vexl /vex=66_0f3a 06 /vexl=1 /vexw=0 Vqq Hqq Wqq Ib W R R N avx vtestps aso rexr rexx rexb vexl /vex=66_0f38 0e /vexw=0 Vx Wx R R avx vtestpd aso rexr rexx rexb vexl /vex=66_0f38 0f /vexw=0 Vx Wx R R avx vextracti128 aso rexr rexx rexb vexl /vex=66_0f3a 39 /vexl=1 /vexw=0 MdqU Vqq Ib W R N avx vinserti128 aso rexr rexx rexb vexl /vex=66_0f3a 38 /vexl=1 /vexw=0 Vqq H MdqU Ib W R R N avx vzeroupper ymm0 ymm1 ymm2 ymm3 ymm4 ymm5 ymm6 ymm7 ymm8 ymm9 ymm10 ymm11 ymm12 ymm13 ymm14 ymm15 /vex=0f 77 /vexl=0 avx vzeroall ymm0 ymm1 ymm2 ymm3 ymm4 ymm5 ymm6 ymm7 ymm8 ymm9 ymm10 ymm11 ymm12 ymm13 ymm14 ymm15 /vex=0f 77 /vexl=1 avx vperm2i128 aso rexr rexx rexb vexl /vex=66_0f3a 46 /vexl=1 /vexw=0 Vqq H Wqq Ib W R R N avx vpsrlvd aso rexr rexx rexb vexl /vex=66_0f38 45 /vexw=0 V H W W R R avx vpsrlvq aso rexr rexx rexb vexl /vex=66_0f38 45 /vexw=1 V H W W R R avx vpsravd aso rexr rexx rexb vexl /vex=66_0f38 46 /vexw=0 V H W W R R avx vpsllvd aso rexr rexx rexb vexl /vex=66_0f38 47 /vexw=0 V H W W R R avx vpsllvq aso rexr rexx rexb vexl /vex=66_0f38 47 /vexw=1 V H W W R R avx vpermpd aso rexr rexx rexb vexl /vex=66_0f3a 01 /vexl=1 /vexw=1 V W Ib W R N avx vpermps aso rexr rexx rexb vexl /vex=66_0f38 16 /vexl=1 /vexw=0 V H W W R R avx vpermd aso rexr rexx rexb vexl /vex=66_0f38 36 /vexl=1 /vexw=0 V H W W R R avx vpermq aso rexr rexx rexb vexl /vex=66_0f3a 00 /vexl=1 /vexw=1 V W Ib W R N avx vgatherdpd rexr rexx rexb vexl /vex=66_0f38 92 /vexw=1 V XSXq H RW R RW avx vgatherqpd rexr rexx rexb vexl /vex=66_0f38 93 /vexw=1 V XSq H RW R RW avx vgatherdps rexr rexx rexb vexl /vex=66_0f38 92 /vexw=0 V XSd H RW R RW avx vgatherqps rexr rexx rexb vexl /vex=66_0f38 93 /vexw=0 Vdq XSd Hdq RW R RW avx vpgatherdd rexr rexx rexb vexl /vex=66_0f38 90 /vexw=0 V XSd H RW R RW avx vpgatherqd rexr rexx rexb vexl /vex=66_0f38 91 /vexw=0 Vdq XSd Hdq RW R RW avx vpgatherdq rexr rexx rexb vexl /vex=66_0f38 90 /vexw=1 V XSXq H RW R RW avx vpgatherqq rexr rexx rexb vexl /vex=66_0f38 91 /vexw=1 V XSq H RW R RW avx vblendvpd W aso rexr rexx rexb vexl /vex=66_0f3a 4b /vexw=0 Vx Hx Wx Lx W R R R avx vblendvps W aso rexr rexx rexb vexl /vex=66_0f3a 4a /vexw=0 Vx Hx Wx Lx W R R R avx vmovsd W aso rexr rexx rexb /vex=f2_0f 10 /mod=11 V H U W R R avx aso rexr rexx rexb /vex=f2_0f 10 /mod=!11 V Mq W R avx aso rexr rexx rexb /vex=f2_0f 11 /mod=11 U H V W R R avx aso rexr rexx rexb /vex=f2_0f 11 /mod=!11 Mq V W R avx vmovss W aso rexr rexx rexb /vex=f3_0f 10 /mod=11 V H U W R R avx aso rexr rexx rexb /vex=f3_0f 10 /mod=!11 V Md W R avx aso rexr rexx rexb /vex=f3_0f 11 /mod=11 U H V W R R avx aso rexr rexx rexb /vex=f3_0f 11 /mod=!11 Md V W R avx vpblendvb W aso rexr rexx rexb vexl /vex=66_0f3a 4c /vexw=0 V H W Lx W R R R avx vpbroadcastb aso rexr rexx rexb vexl /vex=66_0f38 78 /vexw=0 V MbU W R avx vpbroadcastw aso rexr rexx rexb vexl /vex=66_0f38 79 /vexw=0 V MwU W R avx vpbroadcastd aso rexr rexx rexb vexl /vex=66_0f38 58 /vexw=0 V MdU W R avx vpbroadcastq aso rexr rexx rexb vexl /vex=66_0f38 59 /vexw=0 V MqU W R avx vbroadcasti128 aso rexr rexx rexb vexl /vex=66_0f38 5A /vexl=1 /vexw=0 V Mdq W R avx vpsllw W aso rexr rexx rexb vexl /vex=66_0f f1 V H MdqU W R R avx aso rexr rexx rexb vexl /vex=66_0f 71 /reg=6 H W Ib W R R avx vpslld W aso rexr rexx rexb vexl /vex=66_0f f2 V H MdqU W R R avx aso rexr rexx rexb vexl /vex=66_0f 72 /reg=6 H W Ib W R N avx vpsllq W aso rexr rexx rexb vexl /vex=66_0f f3 V H MdqU W R R avx aso rexr rexx rexb vexl /vex=66_0f 73 /reg=6 H W Ib W R R avx adox M___________ aso oso rexr rexw rexx rexb /sse=f3 0F 38 F6 Gv Ev RW R adx adcx _____M______ aso oso rexr rexw rexx rexb /sse=66 0F 38 F6 Gv Ev RW R adx lzcnt UUMUUM______ aso oso rexw rexr rexx rexb /sse=F3 0F BD Gv Ev W R lzcnt andn RMMUUR______ avx bmi1 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F2 Gd HRd Ed aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F2 Gq HRq Eq bextr RUMUURRRRRR_ avx bmi1 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F7 Gd Ed HRd W R R aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F7 Gq Eq HRq W R R blsi RMMUUM______ avx bmi1 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F3 /reg=3 HRd Ed aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F3 /reg=3 HRq Eq blsmsk RMRUUM______ avx bmi1 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F3 /reg=2 HRd Ed aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F3 /reg=2 HRq Eq blsr RMRUUM______ avx bmi1 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F3 /reg=1 HRd Ed aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F3 /reg=1 HRq Eq tzcnt UUMUUM______ aso oso rexw rexr rexx rexb /sse=F3 0F BC Gv Ev W R bmi1 bzhi RMMUUM______ avx bmi2 aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=0 F5 Gd Ed HRd W R R aso oso rexw rexr rexx rexb /vex=0f38 /vexl=0 /vexw=1 F5 Gq Eq HRq W R R mulx ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=0 F6 Gd HRd Ed W W R aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=1 F6 Gq HRq Eq W W R pdep ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=0 F5 Gd HRd Ed aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=1 F5 Gq HRq Eq pext ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f3_0f38 /vexl=0 /vexw=0 F5 Gd HRd Ed aso oso rexw rexr rexx rexb /vex=f3_0f38 /vexl=0 /vexw=1 F5 Gq HRq Eq rorx ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f2_0f3a /vexl=0 /vexw=0 F0 Gd Ed Ib aso oso rexw rexr rexx rexb /vex=f2_0f3a /vexl=0 /vexw=1 F0 Gq Eq Ib sarx ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f3_0f38 /vexl=0 /vexw=0 F7 Gd Ed HRd W R R aso oso rexw rexr rexx rexb /vex=f3_0f38 /vexl=0 /vexw=1 F7 Gq Eq HRq W R R shlx ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=66_0f38 /vexl=0 /vexw=0 F7 Gd Ed HRd W R R aso oso rexw rexr rexx rexb /vex=66_0f38 /vexl=0 /vexw=1 F7 Gq Eq HRq W R R shrx ____________ avx bmi2 aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=0 F7 Gd Ed HRd W R R aso oso rexw rexr rexx rexb /vex=f2_0f38 /vexl=0 /vexw=1 F7 Gq Eq HRq W R R vcvtph2ps avx f16c aso oso rexw rexr rexx rexb /vex=66_0f38 /vexl=1 /vexw=0 13 Vqq Wx W R aso oso rexw rexr rexx rexb /vex=66_0f38 /vexl=0 /vexw=0 13 Vx MqU W R vcvtps2ph avx f16c aso oso rexw rexr rexx rexb /vex=66_0f3a /vexl=1 /vexw=0 1d Wx Vqq Ib W R N aso oso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=0 1d MqU Vx Ib W R N xsave64 xsavec ____________ aso rexw rexr rexx rexb 0F C7 /mod=!11 /reg=4 M W xsave xsavec64 xsaveopt64 xsaves aso rexw rexr rexx rexb 0F C7 /mod=!11 /reg=5 M W xsave xsaves64 xrstor64 xrstors aso rexw rexr rexx rexb 0F C7 /mod=!11 /reg=3 M R xsave xrstors64 rdfsbase oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=0 Ev W fsgsbase rdgsbase oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=1 Ev W fsgsbase wrfsbase oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=2 Ev R fsgsbase wrgsbase oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=3 Ev R fsgsbase xabort c6 /mod=11 /reg=7 /rm=0 Ib N rtm xbegin aso c7 /mod=11 /reg=7 /rm=0 Jz N rtm xend 0f 01 /mod=11 /reg=2 /rm=5 rtm xtest 0f 01 /mod=11 /reg=2 /rm=6 rtm invpcid invpcid /sse=66 0F 38 82 /m=!64 Gv W R R /sse=66 0F 38 82 /m=64 Gq W R R def64 vmfunc intel 0f 01 /mod=11 /reg=2 /rm=4 vmx encls intel 0f 01 /mod=11 /reg=1 /rm=7 sgx1 enclu intel 0f 01 /mod=11 /reg=2 /rm=7 sgx1 sha1rnds4 intel oso aso rexw rexr rexx rexb 0f 3a cc V W Ib RW R N sha sha1nexte intel oso aso rexw rexr rexx rexb 0f 38 c8 V W RW R sha sha1msg1 intel oso aso rexw rexr rexx rexb 0f 38 c9 V W RW R sha sha1msg2 intel oso aso rexw rexr rexx rexb 0f 38 ca V W RW R sha sha256rnds2 intel oso aso rexw rexr rexx rexb 0f 38 cb V W RW R sha sha256msg1 intel oso aso rexw rexr rexx rexb 0f 38 cc V W RW R sha sha256msg2 intel oso aso rexw rexr rexx rexb 0f 38 cd V W RW R sha clflushopt intel rexw rexr rexx rexb /sse=66 0f ae /mod=!11 /reg=7 Mb R clflushopt pcommit intel /sse=66 0f ae /mod=11 /reg=7 /rm=0 pcommit pclmullqlqdq pclmulhqlqdq pclmullqhqdq pclmulhqhqdq vpclmullqlqdq vpclmulhqlqdq vpclmullqhqdq vpclmulhqhqdq vfmadd132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 98 Vx Hx Wx RW R R vfmadd213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 a8 Vx Hx Wx RW R R vfmadd231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 b8 Vx Hx Wx RW R R vfmadd132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 98 Vx Hx Wx RW R R vfmadd213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 a8 Vx Hx Wx RW R R vfmadd231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 b8 Vx Hx Wx RW R R vfmadd132sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 99 Vx Hx MqU RW R R vfmadd213sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 a9 Vx Hx MqU RW R R vfmadd231sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 b9 Vx Hx MqU RW R R vfmadd132ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 99 Vx Hx MdU RW R R vfmadd213ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 a9 Vx Hx MdU RW R R vfmadd231ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 b9 Vx Hx MdU RW R R vfmaddsub132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 96 Vx Hx Wx RW R R vfmaddsub213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 a6 Vx Hx Wx RW R R vfmaddsub231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 b6 Vx Hx Wx RW R R vfmaddsub132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 96 Vx Hx Wx RW R R vfmaddsub213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 a6 Vx Hx Wx RW R R vfmaddsub231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 b6 Vx Hx Wx RW R R vfmsub132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9a Vx Hx Wx RW R R vfmsub213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 aa Vx Hx Wx RW R R vfmsub231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 ba Vx Hx Wx RW R R vfmsub132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9a Vx Hx Wx RW R R vfmsub213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 aa Vx Hx Wx RW R R vfmsub231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 ba Vx Hx Wx RW R R vfmsub132sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9b Vx Hx MqU RW R R vfmsub213sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 ab Vx Hx MqU RW R R vfmsub231sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 bb Vx Hx MqU RW R R vfmsubadd132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 97 Vx Hx Wx RW R R vfmsubadd213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 a7 Vx Hx Wx RW R R vfmsubadd231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 b7 Vx Hx Wx RW R R vfmsubadd132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 97 Vx Hx Wx RW R R vfmsubadd213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 a7 Vx Hx Wx RW R R vfmsubadd231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 b7 Vx Hx Wx RW R R vfnmadd132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9c Vx Hx Wx RW R R vfnmadd213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 ac Vx Hx Wx RW R R vfnmadd231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 bc Vx Hx Wx RW R R vfnmadd132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9c Vx Hx Wx RW R R vfnmadd213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 ac Vx Hx Wx RW R R vfnmadd231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 bc Vx Hx Wx RW R R vfnmadd132sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9d Vx Hx MqU RW R R vfnmadd213sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 ad Vx Hx MqU RW R R vfnmadd231sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 bd Vx Hx MqU RW R R vfnmadd132ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9d Vx Hx MdU RW R R vfnmadd213ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 ad Vx Hx MdU RW R R vfnmadd231ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 bd Vx Hx MdU RW R R vfnmsub132pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9e Vx Hx Wx RW R R vfnmsub213pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 ae Vx Hx Wx RW R R vfnmsub231pd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 be Vx Hx Wx RW R R vfnmsub132ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9e Vx Hx Wx RW R R vfnmsub213ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 ae Vx Hx Wx RW R R vfnmsub231ps avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 be Vx Hx Wx RW R R vfnmsub132sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 9f Vx Hx MqU RW R R vfnmsub213sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 af Vx Hx MqU RW R R vfnmsub231sd avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=1 bf Vx Hx MqU RW R R vfnmsub132ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9f Vx Hx MdU RW R R vfnmsub213ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 af Vx Hx MdU RW R R vfnmsub231ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 bf Vx Hx MdU RW R R vfmsub132ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 9b Vx Hx MdU RW R R vfmsub213ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 ab Vx Hx MdU RW R R vfmsub231ss avx fma aso oso vexl rexw rexr rexx rexb /vex=66_0f38 /vexw=0 bb Vx Hx MdU RW R R vfmaddpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 69 Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 69 Vx Hx Lx Wx vfmaddps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 68 Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 68 Vx Hx Lx Wx vfmaddsd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6b Vx Hx MqU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6b Vx Hx Lx MqU vfmaddsubpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 5d Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 5d Vx Hx Lx Wx vfmaddsubps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 5c Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 5c Vx Hx Lx Wx vfmsubaddpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 5f Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 5f Vx Hx Lx Wx vfmsubaddps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 5e Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 5e Vx Hx Lx Wx vfmsubpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6d Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6d Vx Hx Lx Wx vfmsubps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6c Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6c Vx Hx Lx Wx vfmsubsd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6f Vx Hx MqU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6f Vx Hx Lx MqU vfmsubss avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6e Vx Hx MdU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6e Vx Hx Lx MdU vfmaddss avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 6a Vx Hx MdU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 6a Vx Hx Lx MdU vfnmsubsd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7f Vx Hx MqU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7f Vx Hx Lx MqU vfnmsubss avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7e Vx Hx MdU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7e Vx Hx Lx MdU vfnmaddss avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7a Vx Hx MdU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7a Vx Hx Lx MdU vfnmaddsd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7b Vx Hx MqU Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7b Vx Hx Lx MqU vfnmaddpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 79 Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 79 Vx Hx Lx Wx vfnmaddps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 78 Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 78 Vx Hx Lx Wx vfnmsubps avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7c Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7c Vx Hx Lx Wx vfnmsubpd avx fma4 aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=0 7d Vx Hx Wx Lx aso oso vexl rexw rexr rexx rexb /vex=66_0f3a /vexw=1 7d Vx Hx Lx Wx movntss amd aso oso rexr rexx rexb /sse=f3 0f 2b Md V sse4a movntsd amd aso oso rexr rexx rexb /sse=f2 0f 2b Mq V sse4a extrq amd aso oso rexr rexx rexb /sse=66 0f 78 W Ib Ib sse4a aso oso rexr rexx rexb /sse=66 0f 79 V W sse4a insertq amd aso oso rexr rexx rexb /sse=f2 0f 78 V W Ib Ib sse4a rexr rexx rexb /sse=f2 0f 79 V W sse4a bndmk intel mpx rexr rexx rexb /sse=f3 0f 1b B Mrdq W R bndcl intel mpx rexw rexr rexx rexb /sse=f3 0f 1a B Erdq W R bndcu intel mpx rexr rexx rexb /sse=f2 0f 1a B Erdq W R bndcn intel mpx rexr rexx rexb /sse=f2 0f 1b B Erdq W R bndmov intel mpx rexr rexx rexb /sse=66 0f 1a /m=32 B BMqR W R rexr rexx rexb /sse=66 0f 1a /m=64 B BMdqR W R rexr rexx rexb /sse=66 0f 1b /m=32 BMqR B W R rexr rexx rexb /sse=66 0f 1b /m=64 BMdqR B W R bndldx intel mpx oso aso rexr rexx rexb 0f 1a B M W R bndstx intel mpx oso aso rexr rexx rexb 0f 1b M B R R vfrczpd amd xop avx oso aso vexl rexr rexx rexb /vex=09 /vexw=0 81 Vx Wx W R vfrczps amd xop avx oso aso vexl rexr rexx rexb /vex=09 /vexw=0 80 Vx Wx W R vfrczsd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 83 Vx MqU W R vfrczss amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 82 Vx MdU W R vpcmov amd xop avx oso aso vexl rexr rexx rexb /vex=08 /vexw=0 a2 Vx Hx Wx Lx W R R R oso aso vexl rexr rexx rexb /vex=08 /vexw=1 a2 Vx Hx Lx Wx W R R R vpcomb amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 cc Vx Hx Wx Ib W R R R vpcomltb vpcomleb vpcomgtb vpcomgeb vpcomeqb vpcomneqb vpcomfalseb vpcomtrueb vpcomd amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 ce Vx Hx Wx Ib W R R R vpcomltd vpcomled vpcomgtd vpcomged vpcomeqd vpcomneqd vpcomfalsed vpcomtrued vpcomq amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 cf Vx Hx Wx Ib W R R R vpcomltq vpcomleq vpcomgtq vpcomgeq vpcomeqq vpcomneqq vpcomfalseq vpcomtrueq vpcomub amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 ec Vx Hx Wx Ib W R R R vpcomltub vpcomleub vpcomgtub vpcomgeub vpcomequb vpcomnequb vpcomfalseub vpcomtrueub vpcomud amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 ee Vx Hx Wx Ib W R R R vpcomltud vpcomleud vpcomgtud vpcomgeud vpcomequd vpcomnequd vpcomfalseud vpcomtrueud vpcomuq amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 ef Vx Hx Wx Ib W R R R vpcomltuq vpcomleuq vpcomgtuq vpcomgeuq vpcomequq vpcomnequq vpcomfalseuq vpcomtrueuq vpcomuw amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 ed Vx Hx Wx Ib W R R R vpcomltuw vpcomleuw vpcomgtuw vpcomgeuw vpcomequw vpcomnequw vpcomfalseuw vpcomtrueuw vpcomw amd xop avx oso aso rexr rexx rexb /vex=08 /vexl=0 /vexw=0 cd Vx Hx Wx Ib W R R R vpcomltw vpcomlew vpcomgtw vpcomgew vpcomeqw vpcomneqw vpcomfalsew vpcomtruew vphaddbd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 C2 Vx Wx W R vphaddbq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 C3 Vx Wx W R vphaddbw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 C1 Vx Wx W R vphadddq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 cb Vx Wx W R vphaddubd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 d2 Vx Wx W R vphaddubq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 d3 Vx Wx W R vphaddubw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 d1 Vx Wx W R vphaddudq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 db Vx Wx W R vphadduwd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 d6 Vx Wx W R vphadduwq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 d7 Vx Wx W R vphaddwd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 c6 Vx Wx W R vphaddwq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 c7 Vx Wx W R vphsubbw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 e1 Vx Wx W R vphsubdq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 e3 Vx Wx W R vphsubwd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 e2 Vx Wx W R vpmacsdd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 9e Vx Hx Wx Lx W R R R vpmacsdqh amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 9f Vx Hx Wx Lx W R R R vpmacsdql amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 97 Vx Hx Wx Lx W R R R vpmacssdd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 8e Vx Hx Wx Lx W R R R vpmacssdqh amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 8f Vx Hx Wx Lx W R R R vpmacssdql amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 87 Vx Hx Wx Lx W R R R vpmacsswd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 86 Vx Hx Wx Lx W R R R vpmacssww amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 85 Vx Hx Wx Lx W R R R vpmacswd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 96 Vx Hx Wx Lx W R R R vpmacsww amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 95 Vx Hx Wx Lx W R R R vpmadcsswd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 a6 Vx Hx Wx Lx W R R R vpmadcswd amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 b6 Vx Hx Wx Lx W R R R vpperm amd xop avx oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 a3 Vx Hx Wx Lx W R R R oso aso rexr rexx rexb /vex=08 /vexw=1 /vexl=0 a3 Vx Hx Lx Wx W R R R vprotb amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 90 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 90 Vx Hx Wx W R R oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 c0 Vx Wx Ib W R R vprotd amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 92 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 92 Vx Hx Wx W R R oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 c2 Vx Wx Ib W R R vprotq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 93 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 93 Vx Hx Wx W R R oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 c3 Vx Wx Ib W R R vprotw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 91 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 91 Vx Hx Wx W R R oso aso rexr rexx rexb /vex=08 /vexw=0 /vexl=0 c1 Vx Wx Ib W R R vpshab amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 98 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 98 Vx Hx Wx W R R vpshad amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 9a Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 9a Vx Hx Wx W R R vpshaq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 9b Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 9b Vx Hx Wx W R R vpshaw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 99 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 99 Vx Hx Wx W R R vpshlb amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 94 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 94 Vx Hx Wx W R R vpshld amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 96 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 96 Vx Hx Wx W R R vpshlq amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 97 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 97 Vx Hx Wx W R R vpshlw amd xop avx oso aso rexr rexx rexb /vex=09 /vexw=0 /vexl=0 95 Vx Wx Hx W R R oso aso rexr rexx rexb /vex=09 /vexw=1 /vexl=0 95 Vx Hx Wx W R R bextr RUMUURRRRRR_ amd xop avx bmi1 aso oso rexw rexr rexx rexb /vex=0a /vexl=0 /vexw=0 10 Gd Ed Id W R R aso oso rexw rexr rexx rexb /vex=0a /vexl=0 /vexw=1 10 Gq Eq Id W R R blcfill amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=1 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=1 HRq Eq W R blci amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 02 /reg=6 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 02 /reg=6 HRq Eq W R blcic amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=5 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=5 HRq Eq W R blcmsk amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 02 /reg=1 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 02 /reg=1 HRq Eq W R blcs amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=3 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=3 HRq Eq W R blsfill amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=2 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=2 HRq Eq W R blsic amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=6 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=6 HRq Eq W R t1mskc amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=7 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=7 HRq Eq W R tzmsk amd RMMUUM______ xop avx oso aso rexw rexr rexx rexb /vex=09 /vexw=0 /vexl=0 01 /reg=4 HRd Ed W R oso aso rexw rexr rexx rexb /vex=09 /vexw=1 /vexl=0 01 /reg=4 HRq Eq W R kaddw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 4a Kw KHw KMw W R R kaddb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 4a Kb KHb KMb W R R kaddq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 4a Kq KHq KMq W R R kaddd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 4a Kd KHd KMd W R R kandw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 41 Kw KHw KMw W R R kandb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 41 Kb KHb KMb W R R kandq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 41 Kq KHq KMq W R R kandd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 41 Kd KHd KMd W R R kandnw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 42 Kw KHw KMw W R R kandnb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 42 Kb KHb KMb W R R kandnq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 42 Kq KHq KMq W R R kandnd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 42 Kd KHd KMd W R R kmovw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 90 Kw KMw W R oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 91 /mod=!11 KMw Kw W R oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 92 /mod=11 Kw Ed W R oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 93 /mod=11 Gd KMw W R kmovb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 90 Kb KMb W R oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 91 /mod=!11 KMb Kb W R oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 92 /mod=11 Kb Ed W R oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 93 /mod=11 Gd KMb W R kmovq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=1 90 Kq KMq W R oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=1 91 /mod=!11 KMq Kq W R oso aso rexw rexr rexx rexb /vex=f2_0f /vexl=0 /vexw=1 92 /mod=11 Kq Eq W R oso aso rexw rexr rexx rexb /vex=f2_0f /vexl=0 /vexw=1 93 /mod=11 Gq KMq W R kmovd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=1 90 Kd KMd W R oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=1 91 /mod=!11 KMd Kd W R oso aso rexw rexr rexx rexb /vex=f2_0f /vexl=0 /vexw=0 92 /mod=11 Kd Ed W R oso aso rexw rexr rexx rexb /vex=f2_0f /vexl=0 /vexw=0 93 /mod=11 Gd KMd W R kunpckbw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 4b /mod=11 Kb KHb KMb W R R kunpckwd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 4b /mod=11 Kw KHw KMw W R R kunpckdq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 4b /mod=11 Kd KHd KMd W R R knotw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 44 /mod=11 Kw KMw W R knotb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 44 /mod=11 Kb KMb W R knotq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=1 44 /mod=11 Kq KMq W R knotd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=1 44 /mod=11 Kd KMd W R korw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 45 /mod=11 Kw KHw KMw W R R korb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 45 /mod=11 Kb KHb KMb W R R korq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 45 /mod=11 Kq KHq KMq W R R kord intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 45 /mod=11 Kd KHd KMd W R R kortestw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 98 /mod=11 Kw KMw W R kortestb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 98 /mod=11 Kb KMb W R kortestq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=1 98 /mod=11 Kq KMq W R kortestd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=1 98 /mod=11 Kd KMd W R kshiftlw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=1 32 /mod=11 Kw KMw Ib W R R kshiftlb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=0 32 /mod=11 Kb KMb Ib W R R kshiftlq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=1 33 /mod=11 Kq KMq Ib W R R kshiftld intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=0 33 /mod=11 Kd KMd Ib W R R kshiftrw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=1 30 /mod=11 Kw KMw Ib W R R kshiftrb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=0 30 /mod=11 Kb KMb Ib W R R kshiftrq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=1 31 /mod=11 Kq KMq Ib W R R kshiftrd intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f3a /vexl=0 /vexw=0 31 /mod=11 Kd KMd Ib W R R kxnorw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 46 /mod=11 Kw KHw KMw W R R kxnorb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 46 /mod=11 Kb KHb KMb W R R kxnorq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 46 /mod=11 Kq KHq KMq W R R kxnord intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 46 /mod=11 Kd KHd KMd W R R ktestw intel RRMRRM______ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=0 99 /mod=11 Kw KMw R R ktestb intel RRMRRM______ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=0 99 /mod=11 Kb KMb R R ktestq intel RRMRRM______ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=0 /vexw=1 99 /mod=11 Kq KMq R R ktestd intel RRMRRM______ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=0 /vexw=1 99 /mod=11 Kd KMd R R kxorw intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=0 47 /mod=11 Kw KHw KMw W R R kxorb intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=0 47 /mod=11 Kb KHb KMb W R R kxorq intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=0f /vexl=1 /vexw=1 47 /mod=11 Kq KHq KMq W R R kxord intel ____________ avx avx512 oso aso rexw rexr rexx rexb /vex=66_0f /vexl=1 /vexw=1 47 /mod=11 Kd KHd KMd W R R incsspd intel cet aso oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=5 /o=32 Ev R incsspq intel cet aso oso rexw rexr rexx rexb /sse=F3 0F AE /mod=11 /reg=5 /o=64 Ev R rdsspd intel cet aso oso rexw rexr rexx rexb /sse=F3 0F 1E /mod=11 /reg=1 /o=32 Ev R rdsspq intel cet aso oso rexw rexr rexx rexb /sse=F3 0F 1E /mod=11 /reg=1 /o=64 Ev R saveprevssp intel cet /sse=F3 0F 01 /mod=11 /reg=5 /rm=2 rstorssp intel cet aso oso rexw rexr rexx rexb /sse=F3 0F 01 /mod=!11 /reg=5 M W wrssd intel cet aso oso rexr rexw rexx rexb 0f 38 f6 /o=32 Mv Gv W R wrssq intel cet aso oso rexr rexw rexx rexb 0f 38 f6 /o=64 Mv Gv W R wrussd intel cet aso oso rexr rexw rexx rexb /sse=66 0f 38 f5 /o=32 Mv Gv W R wrussq intel cet aso oso rexr rexw rexx rexb /sse=66 0f 38 f5 /o=64 Mv Gv W R setssbsy intel cet /sse=f3 0f 01 /mod=11 /reg=5 /rm=0 clrssbsy intel cet aso oso rexw rexr rexx rexb /sse=f3 0f ae /mod=11 /reg=6 /m=64 M RW endbr64 intel cet /sse=f3 0f 1e /mod=11 /reg=7 /rm=2 endbr32 intel cet /sse=f3 0f 1e /mod=11 /reg=7 /rm=3 libudis86-0+20221013/docs/x86/optable.xsl000066400000000000000000000044431457133061200174540ustar00rootroot00000000000000 x86 opcode table

x86/optable.xml

udis86.sourceforge.net

Mnemonic Opcodes Vendor
; ;

Copyright (c) 2008, Vivek Thampi

libudis86-0+20221013/libudis86/000077500000000000000000000000001457133061200155255ustar00rootroot00000000000000libudis86-0+20221013/libudis86/CMakeLists.txt000066400000000000000000000013231457133061200202640ustar00rootroot00000000000000cmake_minimum_required(VERSION 3.12) project(libudis86 LANGUAGES C) set(CMAKE_C_STANDARD 99) if(NOT EXISTS ${PROJECT_SOURCE_DIR}/itab.c OR NOT EXISTS ${PROJECT_SOURCE_DIR}/itab.h) find_package(Python3 COMPONENTS Interpreter) set(OPTABLE ${PROJECT_SOURCE_DIR}/../docs/x86/optable.xml) message("Building itab.c/itab.h...") execute_process( COMMAND ${Python3_EXECUTABLE} ${PROJECT_SOURCE_DIR}/../scripts/ud_itab.py ${OPTABLE} . WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} ) endif() set(FILES decode.c decode.h extern.h itab.c itab.h syn-att.c syn-intel.c syn.c syn.h types.h udint.h udis86.c) add_library(libudis86 STATIC ${FILES}) target_include_directories(libudis86 PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})libudis86-0+20221013/libudis86/Makefile.am000066400000000000000000000015351457133061200175650ustar00rootroot00000000000000# # -- udis86/libudis86 # PYTHON = @PYTHON@ OPTABLE = @top_srcdir@/docs/x86/optable.xml MAINTAINERCLEANFILES = Makefile.in lib_LTLIBRARIES = libudis86.la libudis86_la_SOURCES = \ itab.c \ decode.c \ syn.c \ syn-intel.c \ syn-att.c \ udis86.c \ udint.h \ syn.h \ decode.h include_ladir = ${includedir}/libudis86 include_la_HEADERS = \ types.h \ extern.h \ itab.h BUILT_SOURCES = \ itab.c \ itab.h # # DLLs may not contain undefined symbol references. # We have the linker check this explicitly. # if TARGET_WINDOWS libudis86_la_LDFLAGS = -no-undefined -version-info 0:0:0 endif itab.c itab.h: $(OPTABLE) \ $(top_srcdir)/scripts/ud_itab.py \ $(top_srcdir)/scripts/ud_opcode.py $(PYTHON) $(top_srcdir)/scripts/ud_itab.py $(OPTABLE) $(srcdir) clean-local: rm -rf $(BUILT_SOURCES) maintainer-clean-local: libudis86-0+20221013/libudis86/decode.c000066400000000000000000002043631457133061200171240ustar00rootroot00000000000000/* udis86 - libudis86/decode.c * * Copyright (c) 2002-2009 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "udint.h" #include "types.h" #include "extern.h" #include "decode.h" #ifndef __UD_STANDALONE__ # include #endif /* __UD_STANDALONE__ */ /* The max number of prefixes to an instruction */ #define MAX_PREFIXES 15 /* rex prefix bits */ #define REX_W(r) ( ( 0xF & ( r ) ) >> 3 ) #define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 ) #define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 ) #define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 ) #define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \ ( P_REXR(n) << 2 ) | \ ( P_REXX(n) << 1 ) | \ ( P_REXB(n) << 0 ) ) /* scable-index-base bits */ #define SIB_S(b) ( ( b ) >> 6 ) #define SIB_I(b) ( ( ( b ) >> 3 ) & 7 ) #define SIB_B(b) ( ( b ) & 7 ) /* modrm bits */ #define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 ) #define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 ) #define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 ) #define MODRM_RM(b) ( ( b ) & 7 ) static int decode_ext(struct ud *u, uint16_t ptr); static int decode_opcode(struct ud *u); enum reg_class { /* register classes */ REGCLASS_GPR, REGCLASS_MMX, REGCLASS_CR, REGCLASS_DB, REGCLASS_SEG, REGCLASS_XMM, REGCLASS_BOUNDS, REGCLASS_OPMASK }; /* * inp_start * Should be called before each de-code operation. */ static void inp_start(struct ud *u) { u->inp_ctr = 0; } static uint8_t inp_peek(struct ud *u) { if (u->inp_end == 0) { if (u->inp_buf != NULL) { if (u->inp_buf_index < u->inp_buf_size) { return u->inp_buf[u->inp_buf_index]; } } else if (u->inp_peek != UD_EOI) { return u->inp_peek; } else { int c; if ((c = u->inp_hook(u)) != UD_EOI) { u->inp_peek = c; return u->inp_peek; } } } u->inp_end = 1; UDERR(u, "byte expected, eoi received\n"); return 0; } static uint8_t inp_next(struct ud *u) { if (u->inp_end == 0) { if (u->inp_buf != NULL) { if (u->inp_buf_index < u->inp_buf_size) { u->inp_ctr++; return (u->inp_curr = u->inp_buf[u->inp_buf_index++]); } } else { int c = u->inp_peek; if (c != UD_EOI || (c = u->inp_hook(u)) != UD_EOI) { u->inp_peek = UD_EOI; u->inp_curr = c; u->inp_sess[u->inp_ctr++] = u->inp_curr; return u->inp_curr; } } } u->inp_end = 1; UDERR(u, "byte expected, eoi received\n"); return 0; } static uint8_t inp_curr(struct ud *u) { return u->inp_curr; } /* * inp_uint8 * int_uint16 * int_uint32 * int_uint64 * Load little-endian values from input */ static uint8_t inp_uint8(struct ud* u) { return inp_next(u); } static uint16_t inp_uint16(struct ud* u) { uint16_t r, ret; ret = inp_next(u); r = inp_next(u); return ret | (r << 8); } static uint32_t inp_uint32(struct ud* u) { uint32_t r, ret; ret = inp_next(u); r = inp_next(u); ret = ret | (r << 8); r = inp_next(u); ret = ret | (r << 16); r = inp_next(u); return ret | (r << 24); } static uint64_t inp_uint64(struct ud* u) { uint64_t r, ret; ret = inp_next(u); r = inp_next(u); ret = ret | (r << 8); r = inp_next(u); ret = ret | (r << 16); r = inp_next(u); ret = ret | (r << 24); r = inp_next(u); ret = ret | (r << 32); r = inp_next(u); ret = ret | (r << 40); r = inp_next(u); ret = ret | (r << 48); r = inp_next(u); return ret | (r << 56); } static UD_INLINE int eff_opr_mode(int dis_mode, int rex_w, int pfx_opr) { if (dis_mode == 64) { return rex_w ? 64 : (pfx_opr ? 16 : 32); } else if (dis_mode == 32) { return pfx_opr ? 16 : 32; } else { UD_ASSERT(dis_mode == 16); return pfx_opr ? 32 : 16; } } static UD_INLINE int eff_adr_mode(int dis_mode, int pfx_adr) { if (dis_mode == 64) { return pfx_adr ? 32 : 64; } else if (dis_mode == 32) { return pfx_adr ? 16 : 32; } else { UD_ASSERT(dis_mode == 16); return pfx_adr ? 32 : 16; } } /* * decode_prefixes * * Extracts instruction prefixes. */ int ud_decode_prefixes(struct ud *u) { int done = 0; uint8_t curr = 0, last = 0; UD_RETURN_ON_ERROR(u); do { last = curr; curr = inp_next(u); UD_RETURN_ON_ERROR(u); if (u->inp_ctr == MAX_INSN_LENGTH) { UD_RETURN_WITH_ERROR(u, "max instruction length"); } switch (curr) { case 0x2E: u->pfx_seg = UD_R_CS; break; case 0x36: u->pfx_seg = UD_R_SS; break; case 0x3E: u->pfx_seg = UD_R_DS; break; case 0x26: u->pfx_seg = UD_R_ES; break; case 0x64: u->pfx_seg = UD_R_FS; break; case 0x65: u->pfx_seg = UD_R_GS; break; case 0x67: /* adress-size override prefix */ u->pfx_adr = 0x67; break; case 0xF0: u->pfx_lock = 0xF0; break; case 0x66: u->pfx_opr = 0x66; break; case 0xF2: u->pfx_str = 0xf2; break; case 0xF3: u->pfx_str = 0xf3; break; default: /* consume if rex */ done = (u->dis_mode == 64 && (curr & 0xF0) == 0x40) ? 0 : 1; break; } } while (!done); /* rex prefixes in 64bit mode, must be the last prefix */ if (u->dis_mode == 64 && (last & 0xF0) == 0x40) { u->pfx_rex = last; } return 0; } /* * vex_l, vex_w * Return the vex.L and vex.W bits */ static UD_INLINE uint8_t vex_l(const struct ud *u) { UD_ASSERT(u->vex_op != 0); return ((u->vex_op != 0xc5 ? u->vex_b2 : u->vex_b1) >> 2) & 1; } static UD_INLINE uint8_t vex_w(const struct ud *u) { UD_ASSERT(u->vex_op != 0); return u->vex_op != 0xc5 ? ((u->vex_b2 >> 7) & 1) : 0; } static UD_INLINE uint8_t modrm(struct ud * u) { if ( !u->have_modrm ) { u->modrm = inp_next( u ); u->have_modrm = 1; } return u->modrm; } static unsigned int resolve_operand_size(const struct ud* u, ud_operand_size_t osize) { switch (osize) { case SZ_V: return u->opr_mode; case SZ_Z: return u->opr_mode == 16 ? 16 : 32; case SZ_Y: return u->opr_mode == 16 ? 32 : u->opr_mode; case SZ_RDQ: return u->dis_mode == 64 ? 64 : 32; case SZ_X: UD_ASSERT(u->vex_op != 0); return (P_VEXL(u->itab_entry->prefix) && vex_l(u)) ? SZ_QQ : SZ_DQ; default: return osize; } } static int resolve_mnemonic( struct ud* u ) { if( u->mnemonic == UD_I3dnow ) { // resolve 3dnow weirdness. uint8_t idx = inp_curr( u ); if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } u->mnemonic = ud_itab[ u->le->table[idx] ].mnemonic; } else if( u->mnemonic == UD_Iswapgs ) { if( u->dis_mode != 64 ) { UDERR(u, "swapgs invalid in 64bits mode\n"); return -1; } } else if( u->mnemonic == UD_Ixchg ) { if( (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_AX && u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_AX) || (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_EAX && u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_EAX) ) { u->operand[0].type = UD_NONE; u->operand[1].type = UD_NONE; u->mnemonic = UD_Inop; } } else if( u->mnemonic == UD_Inop ) { if( u->pfx_repe ) { u->pfx_repe = 0; u->mnemonic = UD_Ipause; } } else if( u->mnemonic == UD_Ixrstor ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixrstor64; } else if( u->mnemonic == UD_Ixrstors ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixrstors64; } else if( u->mnemonic == UD_Ixsave ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixsave64; } else if( u->mnemonic == UD_Ixsavec ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixsavec64; } else if( u->mnemonic == UD_Ixsaveopt ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixsaveopt64; } else if( u->mnemonic == UD_Ixsaves ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ixsaves64; } else if( u->mnemonic == UD_Ifxrstor ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ifxrstor64; } else if( u->mnemonic == UD_Ifxsave ) { if( u->pfx_rex != 0 && u->dis_mode == 64 && u->opr_mode == 64 ) u->mnemonic = UD_Ifxsave64; } else { // test the third/fourth operand for a immediate to see if we need to change the opcode. if( u->operand[2].type == UD_OP_IMM ) { if( u->mnemonic == UD_Ipclmulqdq ) { switch( u->operand[2].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ipclmullqlqdq; u->operand[2].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ipclmulhqlqdq; u->operand[2].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ipclmullqhqdq; u->operand[2].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ipclmulhqhqdq; u->operand[2].type = UD_NONE; break; } } else if( u->mnemonic == UD_Icmppd ) { switch( u->operand[2].lval.ubyte ) { case 0x00: u->mnemonic = UD_Icmpeqpd; u->operand[2].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Icmpltpd; u->operand[2].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Icmplepd; u->operand[2].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Icmpunordpd; u->operand[2].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Icmpneqpd; u->operand[2].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Icmpnltpd; u->operand[2].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Icmpnlepd; u->operand[2].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Icmpordpd; u->operand[2].type = UD_NONE; break; } } else if( u->mnemonic == UD_Icmpps ) { switch( u->operand[2].lval.ubyte ) { case 0x00: u->mnemonic = UD_Icmpeqps; u->operand[2].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Icmpltps; u->operand[2].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Icmpleps; u->operand[2].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Icmpunordps; u->operand[2].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Icmpneqps; u->operand[2].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Icmpnltps; u->operand[2].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Icmpnleps; u->operand[2].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Icmpordps; u->operand[2].type = UD_NONE; break; } } else if( u->mnemonic == UD_Icmpss ) { switch( u->operand[2].lval.ubyte ) { case 0x00: u->mnemonic = UD_Icmpeqss; u->operand[2].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Icmpltss; u->operand[2].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Icmpless; u->operand[2].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Icmpunordss; u->operand[2].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Icmpneqss; u->operand[2].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Icmpnltss; u->operand[2].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Icmpnless; u->operand[2].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Icmpordss; u->operand[2].type = UD_NONE; break; } } else if( u->mnemonic == UD_Icmpsd ) { switch( u->operand[2].lval.ubyte ) { case 0x00: u->mnemonic = UD_Icmpeqsd; u->operand[2].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Icmpltsd; u->operand[2].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Icmplesd; u->operand[2].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Icmpunordsd; u->operand[2].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Icmpneqsd; u->operand[2].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Icmpnltsd; u->operand[2].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Icmpnlesd; u->operand[2].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Icmpordsd; u->operand[2].type = UD_NONE; break; } } } else if( u->operand[3].type == UD_OP_IMM ) { if( u->mnemonic == UD_Ivpclmulqdq ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpclmullqlqdq; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpclmulhqlqdq; u->operand[3].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ivpclmullqhqdq; u->operand[3].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ivpclmulhqhqdq; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivcmppd ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivcmpeqpd; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivcmpltpd; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivcmplepd; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivcmpunordpd; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivcmpneqpd; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivcmpnltpd; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivcmpnlepd; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivcmpordpd; u->operand[3].type = UD_NONE; break; case 0x08: u->mnemonic = UD_Ivcmpeq_uqpd; u->operand[3].type = UD_NONE; break; case 0x09: u->mnemonic = UD_Ivcmpngepd; u->operand[3].type = UD_NONE; break; case 0x0A: u->mnemonic = UD_Ivcmpngtpd; u->operand[3].type = UD_NONE; break; case 0x0B: u->mnemonic = UD_Ivcmpfalsepd; u->operand[3].type = UD_NONE; break; case 0x0C: u->mnemonic = UD_Ivcmpneq_oqpd; u->operand[3].type = UD_NONE; break; case 0x0D: u->mnemonic = UD_Ivcmpgepd; u->operand[3].type = UD_NONE; break; case 0x0E: u->mnemonic = UD_Ivcmpgtpd; u->operand[3].type = UD_NONE; break; case 0x0F: u->mnemonic = UD_Ivcmptruepd; u->operand[3].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ivcmpeq_ospd; u->operand[3].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ivcmplt_oqpd; u->operand[3].type = UD_NONE; break; case 0x12: u->mnemonic = UD_Ivcmple_oqpd; u->operand[3].type = UD_NONE; break; case 0x13: u->mnemonic = UD_Ivcmpunord_spd; u->operand[3].type = UD_NONE; break; case 0x14: u->mnemonic = UD_Ivcmpneq_uspd; u->operand[3].type = UD_NONE; break; case 0x15: u->mnemonic = UD_Ivcmpnlt_uqpd; u->operand[3].type = UD_NONE; break; case 0x16: u->mnemonic = UD_Ivcmpnle_uqpd; u->operand[3].type = UD_NONE; break; case 0x17: u->mnemonic = UD_Ivcmpord_spd; u->operand[3].type = UD_NONE; break; case 0x18: u->mnemonic = UD_Ivcmpeq_uspd; u->operand[3].type = UD_NONE; break; case 0x19: u->mnemonic = UD_Ivcmpnge_uqpd; u->operand[3].type = UD_NONE; break; case 0x1A: u->mnemonic = UD_Ivcmpngt_uqpd; u->operand[3].type = UD_NONE; break; case 0x1B: u->mnemonic = UD_Ivcmpfalse_ospd; u->operand[3].type = UD_NONE; break; case 0x1C: u->mnemonic = UD_Ivcmpneq_ospd; u->operand[3].type = UD_NONE; break; case 0x1D: u->mnemonic = UD_Ivcmpge_oqpd; u->operand[3].type = UD_NONE; break; case 0x1E: u->mnemonic = UD_Ivcmpgt_oqpd; u->operand[3].type = UD_NONE; break; case 0x1F: u->mnemonic = UD_Ivcmptrue_uspd; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivcmpps ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivcmpeqps; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivcmpltps; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivcmpleps; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivcmpunordps; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivcmpneqps; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivcmpnltps; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivcmpnleps; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivcmpordps; u->operand[3].type = UD_NONE; break; case 0x08: u->mnemonic = UD_Ivcmpeq_uqps; u->operand[3].type = UD_NONE; break; case 0x09: u->mnemonic = UD_Ivcmpngeps; u->operand[3].type = UD_NONE; break; case 0x0A: u->mnemonic = UD_Ivcmpngtps; u->operand[3].type = UD_NONE; break; case 0x0B: u->mnemonic = UD_Ivcmpfalseps; u->operand[3].type = UD_NONE; break; case 0x0C: u->mnemonic = UD_Ivcmpneq_oqps; u->operand[3].type = UD_NONE; break; case 0x0D: u->mnemonic = UD_Ivcmpgeps; u->operand[3].type = UD_NONE; break; case 0x0E: u->mnemonic = UD_Ivcmpgtps; u->operand[3].type = UD_NONE; break; case 0x0F: u->mnemonic = UD_Ivcmptrueps; u->operand[3].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ivcmpeq_osps; u->operand[3].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ivcmplt_oqps; u->operand[3].type = UD_NONE; break; case 0x12: u->mnemonic = UD_Ivcmple_oqps; u->operand[3].type = UD_NONE; break; case 0x13: u->mnemonic = UD_Ivcmpunord_sps; u->operand[3].type = UD_NONE; break; case 0x14: u->mnemonic = UD_Ivcmpneq_usps; u->operand[3].type = UD_NONE; break; case 0x15: u->mnemonic = UD_Ivcmpnlt_uqps; u->operand[3].type = UD_NONE; break; case 0x16: u->mnemonic = UD_Ivcmpnle_uqps; u->operand[3].type = UD_NONE; break; case 0x17: u->mnemonic = UD_Ivcmpord_sps; u->operand[3].type = UD_NONE; break; case 0x18: u->mnemonic = UD_Ivcmpeq_usps; u->operand[3].type = UD_NONE; break; case 0x19: u->mnemonic = UD_Ivcmpnge_uqps; u->operand[3].type = UD_NONE; break; case 0x1A: u->mnemonic = UD_Ivcmpngt_uqps; u->operand[3].type = UD_NONE; break; case 0x1B: u->mnemonic = UD_Ivcmpfalse_osps; u->operand[3].type = UD_NONE; break; case 0x1C: u->mnemonic = UD_Ivcmpneq_osps; u->operand[3].type = UD_NONE; break; case 0x1D: u->mnemonic = UD_Ivcmpge_oqps; u->operand[3].type = UD_NONE; break; case 0x1E: u->mnemonic = UD_Ivcmpgt_oqps; u->operand[3].type = UD_NONE; break; case 0x1F: u->mnemonic = UD_Ivcmptrue_usps; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivcmpss ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivcmpeqss; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivcmpltss; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivcmpless; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivcmpunordss; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivcmpneqss; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivcmpnltss; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivcmpnless; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivcmpordss; u->operand[3].type = UD_NONE; break; case 0x08: u->mnemonic = UD_Ivcmpeq_uqss; u->operand[3].type = UD_NONE; break; case 0x09: u->mnemonic = UD_Ivcmpngess; u->operand[3].type = UD_NONE; break; case 0x0A: u->mnemonic = UD_Ivcmpngtss; u->operand[3].type = UD_NONE; break; case 0x0B: u->mnemonic = UD_Ivcmpfalsess; u->operand[3].type = UD_NONE; break; case 0x0C: u->mnemonic = UD_Ivcmpneq_oqss; u->operand[3].type = UD_NONE; break; case 0x0D: u->mnemonic = UD_Ivcmpgess; u->operand[3].type = UD_NONE; break; case 0x0E: u->mnemonic = UD_Ivcmpgtss; u->operand[3].type = UD_NONE; break; case 0x0F: u->mnemonic = UD_Ivcmptruess; u->operand[3].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ivcmpeq_osss; u->operand[3].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ivcmplt_oqss; u->operand[3].type = UD_NONE; break; case 0x12: u->mnemonic = UD_Ivcmple_oqss; u->operand[3].type = UD_NONE; break; case 0x13: u->mnemonic = UD_Ivcmpunord_sss; u->operand[3].type = UD_NONE; break; case 0x14: u->mnemonic = UD_Ivcmpneq_usss; u->operand[3].type = UD_NONE; break; case 0x15: u->mnemonic = UD_Ivcmpnlt_uqss; u->operand[3].type = UD_NONE; break; case 0x16: u->mnemonic = UD_Ivcmpnle_uqss; u->operand[3].type = UD_NONE; break; case 0x17: u->mnemonic = UD_Ivcmpord_sss; u->operand[3].type = UD_NONE; break; case 0x18: u->mnemonic = UD_Ivcmpeq_usss; u->operand[3].type = UD_NONE; break; case 0x19: u->mnemonic = UD_Ivcmpnge_uqss; u->operand[3].type = UD_NONE; break; case 0x1A: u->mnemonic = UD_Ivcmpngt_uqss; u->operand[3].type = UD_NONE; break; case 0x1B: u->mnemonic = UD_Ivcmpfalse_osss; u->operand[3].type = UD_NONE; break; case 0x1C: u->mnemonic = UD_Ivcmpneq_osss; u->operand[3].type = UD_NONE; break; case 0x1D: u->mnemonic = UD_Ivcmpge_oqss; u->operand[3].type = UD_NONE; break; case 0x1E: u->mnemonic = UD_Ivcmpgt_oqss; u->operand[3].type = UD_NONE; break; case 0x1F: u->mnemonic = UD_Ivcmptrue_usss; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivcmpsd ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivcmpeqsd; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivcmpltsd; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivcmplesd; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivcmpunordsd; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivcmpneqsd; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivcmpnltsd; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivcmpnlesd; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivcmpordsd; u->operand[3].type = UD_NONE; break; case 0x08: u->mnemonic = UD_Ivcmpeq_uqsd; u->operand[3].type = UD_NONE; break; case 0x09: u->mnemonic = UD_Ivcmpngesd; u->operand[3].type = UD_NONE; break; case 0x0A: u->mnemonic = UD_Ivcmpngtsd; u->operand[3].type = UD_NONE; break; case 0x0B: u->mnemonic = UD_Ivcmpfalsesd; u->operand[3].type = UD_NONE; break; case 0x0C: u->mnemonic = UD_Ivcmpneq_oqsd; u->operand[3].type = UD_NONE; break; case 0x0D: u->mnemonic = UD_Ivcmpgesd; u->operand[3].type = UD_NONE; break; case 0x0E: u->mnemonic = UD_Ivcmpgtsd; u->operand[3].type = UD_NONE; break; case 0x0F: u->mnemonic = UD_Ivcmptruesd; u->operand[3].type = UD_NONE; break; case 0x10: u->mnemonic = UD_Ivcmpeq_ossd; u->operand[3].type = UD_NONE; break; case 0x11: u->mnemonic = UD_Ivcmplt_oqsd; u->operand[3].type = UD_NONE; break; case 0x12: u->mnemonic = UD_Ivcmple_oqsd; u->operand[3].type = UD_NONE; break; case 0x13: u->mnemonic = UD_Ivcmpunord_ssd; u->operand[3].type = UD_NONE; break; case 0x14: u->mnemonic = UD_Ivcmpneq_ussd; u->operand[3].type = UD_NONE; break; case 0x15: u->mnemonic = UD_Ivcmpnlt_uqsd; u->operand[3].type = UD_NONE; break; case 0x16: u->mnemonic = UD_Ivcmpnle_uqsd; u->operand[3].type = UD_NONE; break; case 0x17: u->mnemonic = UD_Ivcmpord_ssd; u->operand[3].type = UD_NONE; break; case 0x18: u->mnemonic = UD_Ivcmpeq_ussd; u->operand[3].type = UD_NONE; break; case 0x19: u->mnemonic = UD_Ivcmpnge_uqsd; u->operand[3].type = UD_NONE; break; case 0x1A: u->mnemonic = UD_Ivcmpngt_uqsd; u->operand[3].type = UD_NONE; break; case 0x1B: u->mnemonic = UD_Ivcmpfalse_ossd; u->operand[3].type = UD_NONE; break; case 0x1C: u->mnemonic = UD_Ivcmpneq_ossd; u->operand[3].type = UD_NONE; break; case 0x1D: u->mnemonic = UD_Ivcmpge_oqsd; u->operand[3].type = UD_NONE; break; case 0x1E: u->mnemonic = UD_Ivcmpgt_oqsd; u->operand[3].type = UD_NONE; break; case 0x1F: u->mnemonic = UD_Ivcmptrue_ussd; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomb ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltb; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleb; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtb; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeb; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomeqb; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomneqb; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseb; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueb; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomd ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltd; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomled; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtd; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomged; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomeqd; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomneqd; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalsed; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrued; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomq ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltq; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleq; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtq; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeq; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomeqq; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomneqq; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseq; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueq; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomub ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltub; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleub; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtub; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeub; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomequb; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomnequb; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseub; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueub; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomud ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltud; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleud; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtud; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeud; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomequd; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomnequd; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseud; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueud; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomuq ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltuq; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleuq; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtuq; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeuq; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomequq; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomnequq; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseuq; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueuq; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomuw ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltuw; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomleuw; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtuw; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgeuw; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomequw; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomnequw; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalseuw; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtrueuw; u->operand[3].type = UD_NONE; break; } } else if( u->mnemonic == UD_Ivpcomw ) { switch( u->operand[3].lval.ubyte ) { case 0x00: u->mnemonic = UD_Ivpcomltw; u->operand[3].type = UD_NONE; break; case 0x01: u->mnemonic = UD_Ivpcomlew; u->operand[3].type = UD_NONE; break; case 0x02: u->mnemonic = UD_Ivpcomgtw; u->operand[3].type = UD_NONE; break; case 0x03: u->mnemonic = UD_Ivpcomgew; u->operand[3].type = UD_NONE; break; case 0x04: u->mnemonic = UD_Ivpcomeqw; u->operand[3].type = UD_NONE; break; case 0x05: u->mnemonic = UD_Ivpcomneqw; u->operand[3].type = UD_NONE; break; case 0x06: u->mnemonic = UD_Ivpcomfalsew; u->operand[3].type = UD_NONE; break; case 0x07: u->mnemonic = UD_Ivpcomtruew; u->operand[3].type = UD_NONE; break; } } } } return 0; } /* ----------------------------------------------------------------------------- * decode_a()- Decodes operands of the type seg:offset * ----------------------------------------------------------------------------- */ static void decode_a(struct ud* u, struct ud_operand *op) { if (u->opr_mode == 16) { /* seg16:off16 */ op->type = UD_OP_PTR; op->size = 32; op->lval.ptr.off = inp_uint16(u); op->lval.ptr.seg = inp_uint16(u); } else { /* seg16:off32 */ op->type = UD_OP_PTR; op->size = 48; op->lval.ptr.off = inp_uint32(u); op->lval.ptr.seg = inp_uint16(u); } } /* ----------------------------------------------------------------------------- * decode_gpr() - Returns decoded General Purpose Register * ----------------------------------------------------------------------------- */ static enum ud_type decode_gpr(register struct ud* u, unsigned int s, unsigned char rm) { switch (s) { case 64: return UD_R_RAX + rm; case 32: return UD_R_EAX + rm; case 16: return UD_R_AX + rm; case 8: if (u->dis_mode == 64 && u->pfx_rex) { if (rm >= 4) return UD_R_SPL + (rm-4); return UD_R_AL + rm; } else return UD_R_AL + rm; case 0: /* invalid size in case of a decode error */ UD_ASSERT(u->error); return UD_NONE; default: UD_ASSERT(!"invalid operand size"); return UD_NONE; } } static void decode_reg(struct ud *u, struct ud_operand *opr, int type, int num, int size) { int reg = -1; size = resolve_operand_size(u, size); switch (type) { case REGCLASS_GPR : reg = decode_gpr(u, size, num); break; case REGCLASS_MMX : reg = UD_R_MM0 + (num & 7); break; case REGCLASS_XMM : reg = num + (size == SZ_QQ ? UD_R_YMM0 : UD_R_XMM0); break; case REGCLASS_CR : reg = UD_R_CR0 + num; break; case REGCLASS_DB : reg = UD_R_DR0 + num; break; case REGCLASS_BOUNDS : reg = UD_R_BND0 + num; break; case REGCLASS_OPMASK : reg = UD_R_K0 + num; break; case REGCLASS_SEG : { /* * Only 6 segment registers, anything else is an error. */ if ((num & 7) > 5) { UDERR(u, "invalid segment register value\n"); return; } else { reg = UD_R_ES + (num & 7); } break; } default: UD_ASSERT(!"invalid register type"); return; } opr->type = UD_OP_REG; opr->base = reg; opr->size = size; } /* * decode_imm * * Decode Immediate values. */ static void decode_imm(struct ud* u, unsigned int size, struct ud_operand *op) { op->size = resolve_operand_size(u, size); op->type = UD_OP_IMM; switch (op->size) { case 8: op->lval.sbyte = inp_uint8(u); break; case 16: op->lval.uword = inp_uint16(u); break; case 32: op->lval.udword = inp_uint32(u); break; case 64: op->lval.uqword = inp_uint64(u); break; default: return; } } /* * decode_mem_disp * * Decode mem address displacement. */ static void decode_mem_disp(struct ud* u, unsigned int size, struct ud_operand *op) { switch (size) { case 8: op->offset = 8; op->lval.ubyte = inp_uint8(u); break; case 16: op->offset = 16; op->lval.uword = inp_uint16(u); break; case 32: op->offset = 32; op->lval.udword = inp_uint32(u); break; case 64: op->offset = 64; op->lval.uqword = inp_uint64(u); break; default: return; } } /* * decode_modrm_reg * * Decodes reg field of mod/rm byte * */ static UD_INLINE void decode_modrm_reg(struct ud *u, struct ud_operand *operand, unsigned int type, unsigned int size) { uint8_t reg = (REX_R(u->_rex) << 3) | MODRM_REG(modrm(u)); decode_reg(u, operand, type, reg, size); } /* * decode_modrm_rm * * Decodes rm field of mod/rm byte * */ static void decode_modrm_rm(struct ud *u, struct ud_operand *op, unsigned char type, /* register type */ unsigned int size) /* operand size */ { size_t offset = 0; unsigned char mod, rm; /* get mod, r/m and reg fields */ mod = MODRM_MOD(modrm(u)); rm = (REX_B(u->_rex) << 3) | MODRM_RM(modrm(u)); /* * If mod is 11b, then the modrm.rm specifies a register. * */ if (mod == 3) { decode_reg(u, op, type, rm, size); return; } /* * !11b => Memory Address */ op->type = UD_OP_MEM; op->size = resolve_operand_size(u, size); if (u->adr_mode == 64) { op->base = UD_R_RAX + rm; if (mod == 1) { offset = 8; } else if (mod == 2) { offset = 32; } else if (mod == 0 && (rm & 7) == 5) { op->base = UD_R_RIP; offset = 32; } else { offset = 0; } /* * Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { inp_next(u); op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->_rex) << 3)); op->index = UD_R_RAX + (SIB_I(inp_curr(u)) | (REX_X(u->_rex) << 3)); /* special conditions for base reference */ if (op->index == UD_R_RSP) { op->index = UD_NONE; op->scale = UD_NONE; } else { op->scale = (1 << SIB_S(inp_curr(u))) & ~1; } if (op->base == UD_R_RBP || op->base == UD_R_R13) { if (mod == 0) { op->base = UD_NONE; } if (mod == 1) { offset = 8; } else { offset = 32; } } } else { op->scale = UD_NONE; op->index = UD_NONE; } } else if (u->adr_mode == 32) { op->base = UD_R_EAX + rm; if (mod == 1) { offset = 8; } else if (mod == 2) { offset = 32; } else if (mod == 0 && rm == 5) { op->base = UD_NONE; offset = 32; } else { offset = 0; } /* Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { inp_next(u); op->scale = (1 << SIB_S(inp_curr(u))) & ~1; op->index = UD_R_EAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); if (op->index == UD_R_ESP) { op->index = UD_NONE; op->scale = UD_NONE; } /* special condition for base reference */ if (op->base == UD_R_EBP) { if (mod == 0) { op->base = UD_NONE; } if (mod == 1) { offset = 8; } else { offset = 32; } } } else { op->scale = UD_NONE; op->index = UD_NONE; } } else { const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP, UD_R_SI, UD_R_DI, UD_R_BP, UD_R_BX }; const unsigned int indices[] = { UD_R_SI, UD_R_DI, UD_R_SI, UD_R_DI, UD_NONE, UD_NONE, UD_NONE, UD_NONE }; op->base = bases[rm & 7]; op->index = indices[rm & 7]; op->scale = UD_NONE; if (mod == 0 && rm == 6) { offset = 16; op->base = UD_NONE; } else if (mod == 1) { offset = 8; } else if (mod == 2) { offset = 16; } } if (offset) { decode_mem_disp(u, (unsigned int) offset, op); } else { op->offset = 0; } } /* * decode_moffset * Decode offset-only memory operand */ static void decode_moffset(struct ud *u, unsigned int size, struct ud_operand *opr) { opr->type = UD_OP_MEM; opr->base = UD_NONE; opr->index = UD_NONE; opr->scale = UD_NONE; opr->size = resolve_operand_size(u, size); decode_mem_disp(u, u->adr_mode, opr); } static void decode_vex_vvvv(struct ud *u, struct ud_operand *opr, unsigned char type, unsigned size) { uint8_t vvvv; UD_ASSERT(u->vex_op != 0); vvvv = ((u->vex_op != 0xc5 ? u->vex_b2 : u->vex_b1) >> 3) & 0xf; decode_reg(u, opr, type, (0xf & ~vvvv), size); } /* * decode_vex_immreg * Decode source operand encoded in immediate byte [7:4] */ static int decode_vex_immreg(struct ud *u, struct ud_operand *opr, unsigned size) { uint8_t imm = inp_next(u); uint8_t mask = u->dis_mode == 64 ? 0xf : 0x7; UD_RETURN_ON_ERROR(u); UD_ASSERT(u->vex_op != 0); decode_reg(u, opr, REGCLASS_XMM, mask & (imm >> 4), size); return 0; } static void decode_vex_vsib( struct ud *u, struct ud_operand *op, unsigned size, enum ud_type index_base ) { size_t offset = 0; unsigned char mod, rm; mod = MODRM_MOD(modrm(u)); if (mod == 3) return; rm = (REX_B(u->_rex) << 3) | MODRM_RM(modrm(u)); op->type = UD_OP_MEM; op->size = resolve_operand_size(u, size); if (u->adr_mode == 64) { op->base = UD_R_RAX + rm; if (mod == 1) { offset = 8; } else if (mod == 2) { offset = 32; } else if (mod == 0 && (rm & 7) == 5) { op->base = UD_R_RIP; offset = 32; } else { offset = 0; } /* * Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { inp_next(u); op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->_rex) << 3)); op->index = index_base + (SIB_I(inp_curr(u)) | (REX_X(u->_rex) << 3)); /* special conditions for base reference */ if (op->index == UD_R_RSP) { op->index = UD_NONE; op->scale = UD_NONE; } else { op->scale = (1 << SIB_S(inp_curr(u))) & ~1; } if (op->base == UD_R_RBP || op->base == UD_R_R13) { if (mod == 0) { op->base = UD_NONE; } if (mod == 1) { offset = 8; } else { offset = 32; } } } else { op->scale = UD_NONE; op->index = UD_NONE; } } else if (u->adr_mode == 32) { op->base = UD_R_EAX + rm; if (mod == 1) { offset = 8; } else if (mod == 2) { offset = 32; } else if (mod == 0 && rm == 5) { op->base = UD_NONE; offset = 32; } else { offset = 0; } /* Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { inp_next(u); op->scale = (1 << SIB_S(inp_curr(u))) & ~1; op->index = index_base + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); if (op->index == UD_R_ESP) { op->index = UD_NONE; op->scale = UD_NONE; } /* special condition for base reference */ if (op->base == UD_R_EBP) { if (mod == 0) { op->base = UD_NONE; } if (mod == 1) { offset = 8; } else { offset = 32; } } } else { op->scale = UD_NONE; op->index = UD_NONE; } } if (offset) { decode_mem_disp(u, offset, op); } else { op->offset = 0; } return; } /* * decode_operand * * Decodes a single operand. * Returns the type of the operand (UD_NONE if none) */ static int decode_operand(struct ud *u, struct ud_operand *operand, enum ud_operand_code type, unsigned int size) { operand->type = UD_NONE; operand->_oprcode = type; switch (type) { case OP_A : decode_a(u, operand); break; case OP_MR: decode_modrm_rm(u, operand, REGCLASS_GPR, MODRM_MOD(modrm(u)) == 3 ? Mx_reg_size(size) : Mx_mem_size(size)); break; case OP_F: u->br_far = 1; /* intended fall through */ case OP_M: if (MODRM_MOD(modrm(u)) == 3) { UDERR(u, "expected modrm.mod != 3\n"); } /* intended fall through */ case OP_E: decode_modrm_rm(u, operand, REGCLASS_GPR, size); break; case OP_G: decode_modrm_reg(u, operand, REGCLASS_GPR, size); break; case OP_B: decode_modrm_reg(u, operand, REGCLASS_BOUNDS, size); break; case OP_BM: decode_modrm_rm(u, operand, REGCLASS_BOUNDS, size); break; case OP_BMR: decode_modrm_rm(u, operand, REGCLASS_BOUNDS, MODRM_MOD(modrm(u)) == 3 ? Mx_reg_size(size) : Mx_mem_size(size)); break; case OP_sI: case OP_I: decode_imm(u, size, operand); break; case OP_I1: operand->type = UD_OP_CONST; operand->lval.udword = 1; break; case OP_N: if (MODRM_MOD(modrm(u)) != 3) { UDERR(u, "expected modrm.mod == 3\n"); } /* intended fall through */ case OP_Q: decode_modrm_rm(u, operand, REGCLASS_MMX, size); break; case OP_P: decode_modrm_reg(u, operand, REGCLASS_MMX, size); break; case OP_U: if (MODRM_MOD(modrm(u)) != 3) { UDERR(u, "expected modrm.mod == 3\n"); } /* intended fall through */ case OP_W: decode_modrm_rm(u, operand, REGCLASS_XMM, size); break; case OP_V: decode_modrm_reg(u, operand, REGCLASS_XMM, size); break; case OP_H: decode_vex_vvvv(u, operand, REGCLASS_XMM, size); break; case OP_HR: decode_vex_vvvv(u, operand, REGCLASS_GPR, size); break; case OP_XS: decode_vex_vsib(u, operand, size, ((P_VEXL(u->itab_entry->prefix) && vex_l(u)) ? UD_R_YMM0 : UD_R_XMM0) ); break; case OP_XSX: decode_vex_vsib(u, operand, size, UD_R_XMM0 ); break; case OP_XSY: decode_vex_vsib(u, operand, size, UD_R_YMM0 ); break; case OP_K: decode_modrm_reg(u, operand, REGCLASS_OPMASK, size); break; case OP_KM: decode_modrm_rm(u, operand, REGCLASS_OPMASK, size); break; case OP_KH: decode_vex_vvvv(u, operand, REGCLASS_OPMASK, size); break; case OP_MU: decode_modrm_rm(u, operand, REGCLASS_XMM, MODRM_MOD(modrm(u)) == 3 ? Mx_reg_size(size) : Mx_mem_size(size)); break; case OP_S: decode_modrm_reg(u, operand, REGCLASS_SEG, size); break; case OP_O: decode_moffset(u, size, operand); break; case OP_R0: case OP_R1: case OP_R2: case OP_R3: case OP_R4: case OP_R5: case OP_R6: case OP_R7: decode_reg(u, operand, REGCLASS_GPR, (REX_B(u->_rex) << 3) | (type - OP_R0), size); break; case OP_AL: case OP_AX: case OP_eAX: case OP_rAX: decode_reg(u, operand, REGCLASS_GPR, 0, size); break; case OP_CL: case OP_CX: case OP_eCX: decode_reg(u, operand, REGCLASS_GPR, 1, size); break; case OP_DL: case OP_DX: case OP_eDX: decode_reg(u, operand, REGCLASS_GPR, 2, size); break; case OP_ES: case OP_CS: case OP_DS: case OP_SS: case OP_FS: case OP_GS: /* in 64bits mode, only fs and gs are allowed */ if (u->dis_mode == 64) { if (type != OP_FS && type != OP_GS) { UDERR(u, "invalid segment register in 64bits\n"); } } operand->type = UD_OP_REG; operand->base = (type - OP_ES) + UD_R_ES; operand->size = 16; break; case OP_J : decode_imm(u, size, operand); operand->type = UD_OP_JIMM; break ; case OP_R : if (MODRM_MOD(modrm(u)) != 3) { UDERR(u, "expected modrm.mod == 3\n"); } decode_modrm_rm(u, operand, REGCLASS_GPR, size); break; case OP_C: decode_modrm_reg(u, operand, REGCLASS_CR, size); break; case OP_D: decode_modrm_reg(u, operand, REGCLASS_DB, size); break; case OP_I3 : operand->type = UD_OP_CONST; operand->lval.sbyte = 3; break; case OP_ST0: case OP_ST1: case OP_ST2: case OP_ST3: case OP_ST4: case OP_ST5: case OP_ST6: case OP_ST7: operand->type = UD_OP_REG; operand->base = (type - OP_ST0) + UD_R_ST0; operand->size = 80; break; case OP_L: decode_vex_immreg(u, operand, size); break; case OP_IMP_XMM0: operand->type = UD_OP_REG; operand->base = UD_R_XMM0; operand->size = SZ_DQ; break; default : operand->type = UD_NONE; break; } return operand->type; } /* * decode_operands * * Disassemble upto 3 operands of the current instruction being * disassembled. By the end of the function, the operand fields * of the ud structure will have been filled. */ static int decode_operands(struct ud* u) { decode_operand( u, &u->operand[0], u->itab_entry->operand1.type, u->itab_entry->operand1.size ); u->operand[0].access = u->itab_entry->access1; if( u->operand[0].access == UD_ACCESS_NONE && u->operand[0].type == UD_OP_IMM ) u->operand[0].access = UD_ACCESS_READ; if( u->operand[0].type != UD_NONE ) { decode_operand( u, &u->operand[1], u->itab_entry->operand2.type, u->itab_entry->operand2.size ); u->operand[1].access = u->itab_entry->access2; if( u->operand[1].access == UD_ACCESS_NONE && u->operand[1].type == UD_OP_IMM ) u->operand[1].access = UD_ACCESS_READ; } if( u->operand[1].type != UD_NONE ) { decode_operand( u, &u->operand[2], u->itab_entry->operand3.type, u->itab_entry->operand3.size ); u->operand[2].access = u->itab_entry->access3; if( u->operand[2].access == UD_ACCESS_NONE && u->operand[2].type == UD_OP_IMM ) u->operand[2].access = UD_ACCESS_READ; } if( u->operand[2].type != UD_NONE ) { decode_operand( u, &u->operand[3], u->itab_entry->operand4.type, u->itab_entry->operand4.size ); u->operand[3].access = u->itab_entry->access4; if( u->operand[3].access == UD_ACCESS_NONE && u->operand[3].type == UD_OP_IMM ) u->operand[3].access = UD_ACCESS_READ; } return 0; } /* ----------------------------------------------------------------------------- * clear_insn() - clear instruction structure * ----------------------------------------------------------------------------- */ void ud_clear_insn(register struct ud* u) { u->error = 0; u->pfx_seg = 0; u->pfx_opr = 0; u->pfx_adr = 0; u->pfx_lock = 0; u->pfx_bnd = 0; u->pfx_xacquire = 0; u->pfx_xrelease = 0; u->pfx_repne = 0; u->pfx_rep = 0; u->pfx_repe = 0; u->pfx_rex = 0; u->pfx_str = 0; u->mnemonic = UD_Inone; u->itab_entry = NULL; u->have_modrm = 0; u->br_far = 0; u->vex_op = 0; u->_rex = 0; u->operand[0].type = UD_NONE; u->operand[1].type = UD_NONE; u->operand[2].type = UD_NONE; u->operand[3].type = UD_NONE; } static UD_INLINE int resolve_pfx_str( struct ud * u ) { if( u->pfx_str == 0xf3 ) { if( u->vendor == UD_VENDOR_AMD ) { u->pfx_repe = u->pfx_str; } else { if( u->pfx_lock == 0xf0 ) { if( u->operand[0].type == UD_OP_MEM ) { switch( u->mnemonic ) { case UD_Iadd: case UD_Iadc: case UD_Iand: case UD_Ibtc: case UD_Ibtr: case UD_Ibts: case UD_Icmpxchg: case UD_Icmpxchg8b: case UD_Idec: case UD_Iinc: case UD_Ineg: case UD_Inot: case UD_Ior: case UD_Isbb: case UD_Isub: case UD_Ixor: case UD_Ixadd: case UD_Ixchg: u->pfx_xrelease = u->pfx_str; break; default: break; } } } else if( u->mnemonic == UD_Ixchg ) { u->pfx_xrelease = u->pfx_str; } else if( u->mnemonic == UD_Imov && u->operand[0].type == UD_OP_MEM && (u->operand[1].type == UD_OP_REG || u->operand[1].type == UD_OP_IMM ) ) { u->pfx_xrelease = u->pfx_str; } if( u->pfx_xrelease != u->pfx_str ) { if( P_STR( u->itab_entry->prefix ) ) { u->pfx_rep = u->pfx_str; } else { u->pfx_repe = u->pfx_str; } } } } else if( u->pfx_str == 0xf2 ) { if( u->vendor == UD_VENDOR_AMD ) { u->pfx_repne = u->pfx_str; } else { if( u->pfx_lock == 0xf0 ) { if( u->operand[0].type == UD_OP_MEM ) { switch( u->mnemonic ) { case UD_Iadd: case UD_Iadc: case UD_Iand: case UD_Ibtc: case UD_Ibtr: case UD_Ibts: case UD_Icmpxchg: case UD_Icmpxchg8b: case UD_Idec: case UD_Iinc: case UD_Ineg: case UD_Inot: case UD_Ior: case UD_Isbb: case UD_Isub: case UD_Ixor: case UD_Ixadd: case UD_Ixchg: u->pfx_xacquire = u->pfx_str; break; default: break; } } } else if( u->mnemonic == UD_Ixchg ) { u->pfx_xacquire = u->pfx_str; } if( u->pfx_xacquire != u->pfx_str ) { switch( u->mnemonic ) { case UD_Icall: case UD_Iret: case UD_Ija: case UD_Ijae: case UD_Ijb: case UD_Ijbe: case UD_Ijcxz: case UD_Ijecxz: case UD_Ijg: case UD_Ijge: case UD_Ijl: case UD_Ijle: case UD_Ijmp: case UD_Ijno: case UD_Ijnp: case UD_Ijns: case UD_Ijnz: case UD_Ijo: case UD_Ijp: case UD_Ijrcxz: case UD_Ijs: case UD_Ijz: u->pfx_bnd = u->pfx_str; break; default: u->pfx_repne = u->pfx_str; break; } } } } return 0; } static int resolve_mode( struct ud* u ) { int default64; /* if in error state, bail out */ if ( u->error ) return -1; /* propagate prefix effects */ if ( u->dis_mode == 64 ) { /* set 64bit-mode flags */ /* Check validity of instruction m64 */ if ( P_INV64( u->itab_entry->prefix ) ) { UDERR(u, "instruction invalid in 64bits\n"); return -1; } /* compute effective rex based on, * - vex prefix (if any) * - rex prefix (if any, and not vex) * - allowed prefixes specified by the opcode map */ if (u->vex_op == 0xc4 || u->vex_op == 0x8f ) { /* vex has rex.rxb in 1's complement */ u->_rex = ((~(u->vex_b1 >> 5) & 0x7) /* rex.0rxb */ | ((u->vex_b2 >> 4) & 0x8) /* rex.w000 */); // patch back in pfx_rex so decode_mod_rm() works as expected under certain conditions. u->pfx_rex = u->_rex; } else if (u->vex_op == 0xc5) { /* vex has rex.r in 1's complement */ u->_rex = (~(u->vex_b1 >> 5)) & 4; // patch back in pfx_rex... u->pfx_rex = u->_rex; } else { UD_ASSERT(u->vex_op == 0); u->_rex = u->pfx_rex; } u->_rex &= REX_PFX_MASK(u->itab_entry->prefix); /* whether this instruction has a default operand size of * 64bit, also hardcoded into the opcode map. */ default64 = P_DEF64( u->itab_entry->prefix ); /* calculate effective operand size */ if (REX_W(u->_rex)) { u->opr_mode = 64; } else if ( u->pfx_opr ) { u->opr_mode = 16; } else { /* unless the default opr size of instruction is 64, * the effective operand size in the absence of rex.w * prefix is 32. */ u->opr_mode = default64 ? 64 : 32; } /* calculate effective address size */ u->adr_mode = (u->pfx_adr) ? 32 : 64; } else if ( u->dis_mode == 32 ) { /* set 32bit-mode flags */ u->opr_mode = ( u->pfx_opr ) ? 16 : 32; u->adr_mode = ( u->pfx_adr ) ? 16 : 32; } else if ( u->dis_mode == 16 ) { /* set 16bit-mode flags */ u->opr_mode = ( u->pfx_opr ) ? 32 : 16; u->adr_mode = ( u->pfx_adr ) ? 32 : 16; } return 0; } static UD_INLINE int decode_insn(struct ud *u, uint16_t ptr) { UD_ASSERT((ptr & 0x8000) == 0); u->itab_entry = &ud_itab[ ptr ]; u->mnemonic = u->itab_entry->mnemonic; return (resolve_mode(u) == 0 && decode_operands(u) == 0 && resolve_pfx_str(u) == 0 && resolve_mnemonic(u) == 0) ? 0 : -1; } /* * decode_3dnow() * * Decoding 3dnow is a little tricky because of its strange opcode * structure. The final opcode disambiguation depends on the last * byte that comes after the operands have been decoded. Fortunately, * all 3dnow instructions have the same set of operand types. So we * go ahead and decode the instruction by picking an arbitrarily chosen * valid entry in the table, decode the operands, and read the final * byte to resolve the menmonic. */ static UD_INLINE int decode_3dnow(struct ud* u) { uint8_t idx; uint16_t ptr; UD_ASSERT(u->le->type == UD_TAB__OPC_3DNOW); UD_ASSERT(u->le->table[0xc] != 0); if( 0xc > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } decode_insn(u, u->le->table[0xc]); inp_next(u); if (u->error) { return -1; } idx = inp_curr(u); if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } ptr = u->le->table[idx]; UD_ASSERT((ptr & 0x8000) == 0); u->mnemonic = ud_itab[ptr].mnemonic; return 0; } static int decode_ssepfx(struct ud *u) { uint8_t idx; uint8_t pfx; /* * String prefixes (f2, f3) take precedence over operand * size prefix (66). */ pfx = u->pfx_str; if (pfx == 0) { pfx = u->pfx_opr; } idx = ((pfx & 0xf) + 1) / 2; if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } if (u->le->table[idx] == 0) { idx = 0; } if (idx && u->le->table[idx] != 0) { /* * "Consume" the prefix as a part of the opcode, so it is no * longer exported as an instruction prefix. */ u->pfx_str = 0; if (pfx == 0x66) { /* * consume "66" only if it was used for decoding, leaving * it to be used as an operands size override for some * simd instructions. */ u->pfx_opr = 0; } } return decode_ext(u, u->le->table[idx]); } static int decode_vex(struct ud *u) { uint8_t idx; if (u->dis_mode != 64 && MODRM_MOD(inp_peek(u)) != 0x3) { idx = 0; } else { u->vex_op = inp_curr(u); u->vex_b1 = inp_next(u); if (u->vex_op == 0xc4 || u->vex_op == 0x8f) { uint8_t pp, m; /* 3-byte vex/xop */ u->vex_b2 = inp_next(u); UD_RETURN_ON_ERROR(u); m = u->vex_b1 & 0x1f; if (u->vex_op == 0x8f) { if( m != 8 && m != 9 && m != 10 ) UD_RETURN_WITH_ERROR(u, "reserved vex.m-mmmm value"); // see ud_opcode.py:93 pp = u->vex_b2 & 0x3; if( m == 8 ) idx = (pp << 2) | 0x10; else if( m == 9 ) idx = (pp << 2) | 0x14; else idx = (pp << 2) | 0x18; } else if (m == 0 || m > 3) { UD_RETURN_WITH_ERROR(u, "reserved vex.m-mmmm value"); } else { pp = u->vex_b2 & 0x3; idx = (pp << 2) | m; } } else { /* 2-byte vex */ UD_ASSERT(u->vex_op == 0xc5); idx = 0x1 | ((u->vex_b1 & 0x3) << 2); } } if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } return decode_ext(u, u->le->table[idx]); } /* * decode_ext() * * Decode opcode extensions (if any) */ static int decode_ext(struct ud *u, uint16_t ptr) { uint8_t idx = 0; if ((ptr & 0x8000) == 0) { return decode_insn(u, ptr); } u->le = &ud_lookup_table_list[(~0x8000 & ptr)]; if (u->le->type == UD_TAB__OPC_3DNOW) { return decode_3dnow(u); } switch (u->le->type) { case UD_TAB__OPC_MOD: /* !11 = 0, 11 = 1 */ idx = (MODRM_MOD(modrm(u)) + 1) / 4; break; /* disassembly mode/operand size/address size based tables. * 16 = 0,, 32 = 1, 64 = 2 */ case UD_TAB__OPC_MODE: idx = u->dis_mode != 64 ? 0 : 1; break; case UD_TAB__OPC_OSIZE: idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32; break; case UD_TAB__OPC_ASIZE: idx = eff_adr_mode(u->dis_mode, u->pfx_adr) / 32; break; case UD_TAB__OPC_X87: idx = modrm(u) - 0xC0; break; case UD_TAB__OPC_VENDOR: if (u->vendor == UD_VENDOR_ANY) { /* choose a valid entry */ if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } idx = (u->le->table[idx] != 0) ? 0 : 1; } else if (u->vendor == UD_VENDOR_AMD) { idx = 0; } else { idx = 1; } break; case UD_TAB__OPC_RM: idx = MODRM_RM(modrm(u)); break; case UD_TAB__OPC_REG: idx = MODRM_REG(modrm(u)); break; case UD_TAB__OPC_SSE: return decode_ssepfx(u); case UD_TAB__OPC_VEX: { // if we have an XOP inst, test the map is < 8 then this is a POP not an XOP instruction. if( (inp_curr( u ) == 0x8F) && (( inp_peek( u ) & 0x1f ) < 8) ) { // table 0 in the VEX tables is where we encoded the POP with // /vex=10 /reg=0 return decode_ext( u, u->le->table[0] ); } return decode_vex(u); } case UD_TAB__OPC_VEX_W: idx = vex_w(u); break; case UD_TAB__OPC_VEX_L: idx = vex_l(u); break; case UD_TAB__OPC_TABLE: inp_next(u); return decode_opcode(u); default: UD_ASSERT(!"not reached"); break; } if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } return decode_ext(u, u->le->table[idx]); } static int decode_opcode(struct ud *u) { uint16_t ptr; uint8_t idx; UD_ASSERT(u->le->type == UD_TAB__OPC_TABLE); UD_RETURN_ON_ERROR(u); idx = inp_curr(u); if( idx > u->le->limit ) { UDERR(u, "out of bounds table idx\n"); return -1; } ptr = u->le->table[idx]; return decode_ext(u, ptr); } /* ============================================================================= * ud_decode() - Instruction decoder. Returns the number of bytes decoded. * ============================================================================= */ unsigned int ud_decode(struct ud *u) { int i = 0; inp_start(u); ud_clear_insn(u); u->le = &ud_lookup_table_list[0]; u->error = ud_decode_prefixes(u) == -1 || decode_opcode(u) == -1 || u->error; /* Handle decode error. */ if (u->error) { /* clear out the decode data. */ ud_clear_insn(u); /* mark the sequence of bytes as invalid. */ u->itab_entry = &ud_itab[0]; /* entry 0 is invalid */ u->mnemonic = u->itab_entry->mnemonic; } /* maybe this stray segment override byte * should be spewed out? */ if ( !P_SEG( u->itab_entry->prefix ) && u->operand[0].type != UD_OP_MEM && u->operand[1].type != UD_OP_MEM ) u->pfx_seg = 0; /* Retrieve some information about operands. */ for (i=0; i<4; i++) { struct ud_operand *op = &u->operand[i]; switch (op->type) { case UD_OP_REG: op->signed_lval = 0; break; case UD_OP_MEM: op->signed_lval = 0; break; case UD_OP_IMM: op->signed_lval = (op->_oprcode == OP_sI ? 1 : 0); break; case UD_OP_JIMM: op->signed_lval = 1; break; case UD_OP_PTR: op->signed_lval = 0; break; case UD_OP_CONST: op->signed_lval = 0; break; default: break; } } u->operand[0].access = u->itab_entry->operand1_access; u->operand[1].access = u->itab_entry->operand2_access; u->operand[2].access = UD_OP_ACCESS_READ; u->operand[3].access = UD_OP_ACCESS_READ; u->insn_offset = u->pc; /* set offset of instruction */ u->asm_buf_fill = 0; /* set translation buffer index to 0 */ u->pc += u->inp_ctr; /* move program counter by bytes decoded */ /* return number of bytes disassembled. */ return (unsigned int) u->inp_ctr; } /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/decode.h000066400000000000000000000142471457133061200171310ustar00rootroot00000000000000/* udis86 - libudis86/decode.h * * Copyright (c) 2002-2009 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UD_DECODE_H #define UD_DECODE_H #include "types.h" #include "udint.h" #include "itab.h" #define MAX_INSN_LENGTH 15 /* itab prefix bits */ #define P_none ( 0 ) #define P_inv64 ( 1 << 0 ) #define P_INV64(n) ( ( n >> 0 ) & 1 ) #define P_def64 ( 1 << 1 ) #define P_DEF64(n) ( ( n >> 1 ) & 1 ) #define P_oso ( 1 << 2 ) #define P_OSO(n) ( ( n >> 2 ) & 1 ) #define P_aso ( 1 << 3 ) #define P_ASO(n) ( ( n >> 3 ) & 1 ) #define P_rexb ( 1 << 4 ) #define P_REXB(n) ( ( n >> 4 ) & 1 ) #define P_rexw ( 1 << 5 ) #define P_REXW(n) ( ( n >> 5 ) & 1 ) #define P_rexr ( 1 << 6 ) #define P_REXR(n) ( ( n >> 6 ) & 1 ) #define P_rexx ( 1 << 7 ) #define P_REXX(n) ( ( n >> 7 ) & 1 ) #define P_seg ( 1 << 8 ) #define P_SEG(n) ( ( n >> 8 ) & 1 ) #define P_vexl ( 1 << 9 ) #define P_VEXL(n) ( ( n >> 9 ) & 1 ) #define P_vexw ( 1 << 10 ) #define P_VEXW(n) ( ( n >> 10 ) & 1 ) #define P_str ( 1 << 11 ) #define P_STR(n) ( ( n >> 11 ) & 1 ) #define P_strz ( 1 << 12 ) #define P_STR_ZF(n) ( ( n >> 12 ) & 1 ) /* operand type constants -- order is important! */ enum ud_operand_code { OP_NONE, OP_A, OP_E, OP_M, OP_G, OP_I, OP_F, OP_R0, OP_R1, OP_R2, OP_R3, OP_R4, OP_R5, OP_R6, OP_R7, OP_AL, OP_CL, OP_DL, OP_AX, OP_CX, OP_DX, OP_eAX, OP_eCX, OP_eDX, OP_rAX, OP_rCX, OP_rDX, OP_ES, OP_CS, OP_SS, OP_DS, OP_FS, OP_GS, OP_ST0, OP_ST1, OP_ST2, OP_ST3, OP_ST4, OP_ST5, OP_ST6, OP_ST7, OP_J, OP_S, OP_O, OP_I1, OP_I3, OP_sI, OP_V, OP_W, OP_Q, OP_P, OP_U, OP_N, OP_MU, OP_H, OP_HR, OP_L, OP_XS, OP_XSX, OP_XSY, OP_R, OP_C, OP_D, OP_B, OP_BM, OP_BMR, OP_K, OP_KM, OP_KH, OP_MR, OP_IMP_XMM0 } UD_ATTR_PACKED; /* * Operand size constants * * Symbolic constants for various operand sizes. Some of these constants * are given a value equal to the width of the data (SZ_B == 8), such * that they maybe used interchangeably in the internals. Modifying them * will most certainly break things! */ typedef uint32_t ud_operand_size_t; #define SZ_NA 0 #define SZ_Z 1 #define SZ_V 2 #define SZ_Y 3 #define SZ_X 4 #define SZ_RDQ 7 #define SZ_B 8 #define SZ_W 16 #define SZ_D 32 #define SZ_Q 64 #define SZ_T 80 #define SZ_O 128 #define SZ_DQ 128 #define SZ_QQ 256 #define SZ_ZQ 512 /* * Complex size types; that encode sizes for operands of type MR (memory or * register); for internal use only. Id space above 256. */ #define SZ_BD ((SZ_B << 16) | SZ_D) #define SZ_BV ((SZ_B << 16) | SZ_V) #define SZ_WD ((SZ_W << 16) | SZ_D) #define SZ_WV ((SZ_W << 16) | SZ_V) #define SZ_WY ((SZ_W << 16) | SZ_Y) #define SZ_DY ((SZ_D << 16) | SZ_Y) #define SZ_BO ((SZ_B << 16) | SZ_O) #define SZ_WO ((SZ_W << 16) | SZ_O) #define SZ_DO ((SZ_D << 16) | SZ_O) #define SZ_QO ((SZ_Q << 16) | SZ_O) #define SZ_DQO ((SZ_DQ << 16) | SZ_O) #define SZ_QQO ((SZ_QQ << 16) | SZ_O) #define SZ_ZQO ((SZ_ZQ << 16) | SZ_O) /* resolve complex size type. */ static UD_INLINE ud_operand_size_t Mx_mem_size(ud_operand_size_t size) { return (size >> 16) & 0xffff; } static UD_INLINE ud_operand_size_t Mx_reg_size(ud_operand_size_t size) { return size & 0xffff; } /* A single operand of an entry in the instruction table. * (internal use only) */ struct ud_itab_entry_operand { enum ud_operand_code type; ud_operand_size_t size; }; /* A single entry in an instruction table. *(internal use only) */ struct ud_itab_entry { enum ud_mnemonic_code mnemonic; struct ud_itab_entry_operand operand1; struct ud_itab_entry_operand operand2; struct ud_itab_entry_operand operand3; struct ud_itab_entry_operand operand4; uint8_t operand1_access; uint8_t operand2_access; uint32_t prefix; struct ud_eflags eflags; enum ud_type implicit_register_uses[32]; enum ud_type implicit_register_defs[32]; uint8_t access1; uint8_t access2; uint8_t access3; uint8_t access4; }; struct ud_lookup_table_list_entry { const uint16_t *table; enum ud_table_type type; const char *meta; const uint8_t limit; }; extern struct ud_itab_entry ud_itab[]; extern struct ud_lookup_table_list_entry ud_lookup_table_list[]; #endif /* UD_DECODE_H */ /* vim:cindent * vim:expandtab * vim:ts=4 * vim:sw=4 */ libudis86-0+20221013/libudis86/extern.h000066400000000000000000000113341457133061200172050ustar00rootroot00000000000000/* udis86 - libudis86/extern.h * * Copyright (c) 2002-2009, 2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UD_EXTERN_H #define UD_EXTERN_H #ifdef __cplusplus extern "C" { #endif #include "types.h" #if defined(_MSC_VER) && defined(_USRDLL) # ifdef LIBUDIS86_EXPORTS # define LIBUDIS86_DLLEXTERN __declspec(dllexport) # else # define LIBUDIS86_DLLEXTERN __declspec(dllimport) # endif #else # define LIBUDIS86_DLLEXTERN #endif /* ============================= PUBLIC API ================================= */ extern LIBUDIS86_DLLEXTERN void ud_init(struct ud*); extern LIBUDIS86_DLLEXTERN void ud_set_mode(struct ud*, uint8_t); extern LIBUDIS86_DLLEXTERN void ud_set_pc(struct ud*, uint64_t); extern LIBUDIS86_DLLEXTERN void ud_set_input_hook(struct ud*, int (*)(struct ud*)); extern LIBUDIS86_DLLEXTERN void ud_set_input_buffer(struct ud*, const uint8_t*, size_t); #ifndef __UD_STANDALONE__ extern LIBUDIS86_DLLEXTERN void ud_set_input_file(struct ud*, FILE*); #endif /* __UD_STANDALONE__ */ extern LIBUDIS86_DLLEXTERN void ud_set_vendor(struct ud*, unsigned); extern LIBUDIS86_DLLEXTERN void ud_set_syntax(struct ud*, void (*)(struct ud*)); extern LIBUDIS86_DLLEXTERN void ud_input_skip(struct ud*, size_t); extern LIBUDIS86_DLLEXTERN int ud_input_end(const struct ud*); extern LIBUDIS86_DLLEXTERN unsigned int ud_decode(struct ud*); extern LIBUDIS86_DLLEXTERN unsigned int ud_disassemble(struct ud*); extern LIBUDIS86_DLLEXTERN void ud_translate_intel(struct ud*); extern LIBUDIS86_DLLEXTERN void ud_translate_att(struct ud*); extern LIBUDIS86_DLLEXTERN const char* ud_insn_asm(const struct ud* u); extern LIBUDIS86_DLLEXTERN const uint8_t* ud_insn_ptr(const struct ud* u); extern LIBUDIS86_DLLEXTERN uint64_t ud_insn_off(const struct ud*); extern LIBUDIS86_DLLEXTERN const char* ud_insn_hex(struct ud*); extern LIBUDIS86_DLLEXTERN unsigned int ud_insn_len(const struct ud* u); extern LIBUDIS86_DLLEXTERN const struct ud_operand* ud_insn_opr(const struct ud *u, unsigned int n); extern LIBUDIS86_DLLEXTERN int ud_opr_is_sreg(const struct ud_operand *opr); extern LIBUDIS86_DLLEXTERN int ud_opr_is_gpr(const struct ud_operand *opr); extern LIBUDIS86_DLLEXTERN enum ud_mnemonic_code ud_insn_mnemonic(const struct ud *u); extern LIBUDIS86_DLLEXTERN const char* ud_lookup_mnemonic(enum ud_mnemonic_code c); extern LIBUDIS86_DLLEXTERN const struct ud_eflags* ud_lookup_eflags(struct ud *u); extern LIBUDIS86_DLLEXTERN const enum ud_type* ud_lookup_implicit_reg_used_list(struct ud *u); extern LIBUDIS86_DLLEXTERN const enum ud_type* ud_lookup_implicit_reg_defined_list(struct ud *u); extern LIBUDIS86_DLLEXTERN void ud_set_user_opaque_data(struct ud*, void*); extern LIBUDIS86_DLLEXTERN void* ud_get_user_opaque_data(const struct ud*); extern LIBUDIS86_DLLEXTERN void ud_set_asm_buffer(struct ud *u, char *buf, size_t size); extern LIBUDIS86_DLLEXTERN void ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*, uint64_t addr, int64_t *offset)); extern LIBUDIS86_DLLEXTERN void ud_clear_insn(register struct ud* u); extern LIBUDIS86_DLLEXTERN int ud_decode_prefixes(struct ud *u); extern LIBUDIS86_DLLEXTERN const char *ud_type_to_value(enum ud_type x); /* ========================================================================== */ #ifdef __cplusplus } #endif #endif /* UD_EXTERN_H */ libudis86-0+20221013/libudis86/syn-att.c000066400000000000000000000141031457133061200172670ustar00rootroot00000000000000/* udis86 - libudis86/syn-att.c * * Copyright (c) 2002-2009 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "types.h" #include "extern.h" #include "decode.h" #include "itab.h" #include "syn.h" #include "udint.h" /* ----------------------------------------------------------------------------- * opr_cast() - Prints an operand cast. * ----------------------------------------------------------------------------- */ static void opr_cast(struct ud* u, struct ud_operand* op) { switch(op->size) { case 16 : case 32 : ud_asmprintf(u, "*"); break; default: break; } } /* ----------------------------------------------------------------------------- * gen_operand() - Generates assembly output for each operand. * ----------------------------------------------------------------------------- */ static void gen_operand(struct ud* u, struct ud_operand* op) { switch(op->type) { case UD_OP_CONST: ud_asmprintf(u, "$0x%x", op->lval.udword); break; case UD_OP_REG: ud_asmprintf(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]); break; case UD_OP_MEM: if (u->br_far) { opr_cast(u, op); } if (u->pfx_seg) { ud_asmprintf(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); } if (op->offset != 0) { ud_syn_print_mem_disp(u, op, 0); } if (op->base) { ud_asmprintf(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]); } if (op->index) { if (op->base) { ud_asmprintf(u, ","); } else { ud_asmprintf(u, "("); } ud_asmprintf(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]); } if (op->scale) { ud_asmprintf(u, ",%d", op->scale); } if (op->base || op->index) { ud_asmprintf(u, ")"); } break; case UD_OP_IMM: ud_asmprintf(u, "$"); ud_syn_print_imm(u, op); break; case UD_OP_JIMM: ud_syn_print_addr(u, ud_syn_rel_target(u, op)); break; case UD_OP_PTR: switch (op->size) { case 32: ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg, op->lval.ptr.off & 0xFFFF); break; case 48: ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg, op->lval.ptr.off); break; } break; default: return; } } /* ============================================================================= * translates to AT&T syntax * ============================================================================= */ extern void ud_translate_att(struct ud *u) { int size = 0; int star = 0; /* check if P_OSO prefix is used */ if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) { switch (u->dis_mode) { case 16: ud_asmprintf(u, "o32 "); break; case 32: case 64: ud_asmprintf(u, "o16 "); break; } } /* check if P_ASO prefix was used */ if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) { switch (u->dis_mode) { case 16: ud_asmprintf(u, "a32 "); break; case 32: ud_asmprintf(u, "a16 "); break; case 64: ud_asmprintf(u, "a32 "); break; } } if (u->pfx_xacquire) { ud_asmprintf(u, "xacquire "); } else if (u->pfx_xrelease) { ud_asmprintf(u, "xrelease "); } if (u->pfx_lock) ud_asmprintf(u, "lock "); if (u->pfx_bnd) ud_asmprintf(u, "bnd "); if (u->pfx_rep) { ud_asmprintf(u, "rep "); } else if (u->pfx_repe) { ud_asmprintf(u, "repe "); } else if (u->pfx_repne) { ud_asmprintf(u, "repne "); } /* special instructions */ switch (u->mnemonic) { case UD_Iretf: ud_asmprintf(u, "lret "); break; case UD_Idb: ud_asmprintf(u, ".byte 0x%x", u->operand[0].lval.ubyte); return; case UD_Ijmp: case UD_Icall: if (u->br_far) ud_asmprintf(u, "l"); if (u->operand[0].type == UD_OP_REG) { star = 1; } ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); break; case UD_Ibound: case UD_Ienter: if (u->operand[0].type != UD_NONE) gen_operand(u, &u->operand[0]); if (u->operand[1].type != UD_NONE) { ud_asmprintf(u, ","); gen_operand(u, &u->operand[1]); } return; default: ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); } if (size == 8) { ud_asmprintf(u, "b"); } else if (size == 16) { ud_asmprintf(u, "w"); } else if (size == 64) { ud_asmprintf(u, "q"); } if (star) { ud_asmprintf(u, " *"); } else { ud_asmprintf(u, " "); } if (u->operand[3].type != UD_NONE) { gen_operand(u, &u->operand[3]); ud_asmprintf(u, ", "); } if (u->operand[2].type != UD_NONE) { gen_operand(u, &u->operand[2]); ud_asmprintf(u, ", "); } if (u->operand[1].type != UD_NONE) { gen_operand(u, &u->operand[1]); ud_asmprintf(u, ", "); } if (u->operand[0].type != UD_NONE) { gen_operand(u, &u->operand[0]); } } /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/syn-intel.c000066400000000000000000000133011457133061200176110ustar00rootroot00000000000000/* udis86 - libudis86/syn-intel.c * * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "types.h" #include "extern.h" #include "decode.h" #include "itab.h" #include "syn.h" #include "udint.h" /* ----------------------------------------------------------------------------- * opr_cast() - Prints an operand cast. * ----------------------------------------------------------------------------- */ static void opr_cast(struct ud* u, struct ud_operand* op) { if (u->br_far) { ud_asmprintf(u, "far "); } // Note: lea instruction will have op size == 0. switch(op->size) { case 8: ud_asmprintf(u, "byte " ); break; case 16: ud_asmprintf(u, "word " ); break; case 32: ud_asmprintf(u, "dword "); break; case 64: ud_asmprintf(u, "qword "); break; case 80: ud_asmprintf(u, "xword "); break; case 128: ud_asmprintf(u, "xmmword "); break; case 256: ud_asmprintf(u, "ymmword "); break; case 512: ud_asmprintf(u, "zmmword "); break; default: break; } } /* ----------------------------------------------------------------------------- * gen_operand() - Generates assembly output for each operand. * ----------------------------------------------------------------------------- */ static void gen_operand(struct ud* u, struct ud_operand* op) { switch(op->type) { case UD_OP_REG: ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]); break; case UD_OP_MEM: opr_cast(u, op); if (u->pfx_seg) { ud_asmprintf(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); } ud_asmprintf(u, "["); if (op->base) { ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]); } if (op->index) { ud_asmprintf(u, "%s%s", op->base != UD_NONE? "+" : "", ud_reg_tab[op->index - UD_R_AL]); if (op->scale) { ud_asmprintf(u, "*%d", op->scale); } } if (op->offset != 0) { ud_syn_print_mem_disp(u, op, (op->base != UD_NONE || op->index != UD_NONE) ? 1 : 0); } ud_asmprintf(u, "]"); break; case UD_OP_IMM: ud_syn_print_imm(u, op); break; case UD_OP_JIMM: ud_syn_print_addr(u, ud_syn_rel_target(u, op)); break; case UD_OP_PTR: switch (op->size) { case 32: ud_asmprintf(u, "word 0x%x:0x%x", op->lval.ptr.seg, op->lval.ptr.off & 0xFFFF); break; case 48: ud_asmprintf(u, "dword 0x%x:0x%x", op->lval.ptr.seg, op->lval.ptr.off); break; } break; case UD_OP_CONST: ud_asmprintf(u, "%d", op->lval.udword); break; default: return; } } /* ============================================================================= * translates to intel syntax * ============================================================================= */ extern void ud_translate_intel(struct ud* u) { /* check if P_OSO prefix is used */ if (!P_OSO(u->itab_entry->prefix) && u->pfx_opr) { switch (u->dis_mode) { case 16: ud_asmprintf(u, "o32 "); break; case 32: case 64: ud_asmprintf(u, "o16 "); break; } } /* check if P_ASO prefix was used */ if (!P_ASO(u->itab_entry->prefix) && u->pfx_adr) { switch (u->dis_mode) { case 16: ud_asmprintf(u, "a32 "); break; case 32: ud_asmprintf(u, "a16 "); break; case 64: ud_asmprintf(u, "a32 "); break; } } if (u->pfx_seg && u->operand[0].type != UD_OP_MEM && u->operand[1].type != UD_OP_MEM ) { ud_asmprintf(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]); } if (u->pfx_xacquire) { ud_asmprintf(u, "xacquire "); } else if (u->pfx_xrelease) { ud_asmprintf(u, "xrelease "); } if (u->pfx_lock) { ud_asmprintf(u, "lock "); } if (u->pfx_bnd) { ud_asmprintf(u, "bnd "); } if (u->pfx_rep) { ud_asmprintf(u, "rep "); } else if (u->pfx_repe) { ud_asmprintf(u, "repe "); } else if (u->pfx_repne) { ud_asmprintf(u, "repne "); } /* print the instruction mnemonic */ ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); if (u->operand[0].type != UD_NONE) { ud_asmprintf(u, " "); gen_operand(u, &u->operand[0]); } if (u->operand[1].type != UD_NONE) { ud_asmprintf(u, ", "); gen_operand(u, &u->operand[1]); } if (u->operand[2].type != UD_NONE) { ud_asmprintf(u, ", "); gen_operand(u, &u->operand[2]); } if (u->operand[3].type != UD_NONE) { ud_asmprintf(u, ", "); gen_operand(u, &u->operand[3]); } } /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/syn.c000066400000000000000000000165061457133061200165120ustar00rootroot00000000000000/* udis86 - libudis86/syn.c * * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "types.h" #include "decode.h" #include "syn.h" #include "udint.h" /* * Register Table - Order Matters (types.h)! * */ const char* ud_reg_tab[] = { "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", "spl", "bpl", "sil", "dil", "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w", "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "es", "cs", "ss", "ds", "fs", "gs", "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", "dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15", "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", "bnd0", "bnd1", "bnd2", "bnd3", "rip" }; /* * Flag Table - Order Matters (types.h)! * */ const char* ud_flag_tab[] = { "of", "sf", "zf", "af", "pf", "cf", "tf", "if", "df", "nf", "rf", "ac" }; uint64_t ud_syn_rel_target(struct ud *u, struct ud_operand *opr) { uint64_t trunc_mask = 0xffffffffffffffffull; if (u->dis_mode != 64) { trunc_mask >>= (64 - u->dis_mode); } switch (opr->size) { case 8: { return (u->pc + opr->lval.sbyte) & trunc_mask; } case 16: { int delta = (opr->lval.sword & trunc_mask); if ((u->pc + delta) > 0xffff) { return (u->pc & 0xf0000) + ((u->pc + delta) & 0xffff); } return (u->pc + delta); } case 32: { return (u->pc + opr->lval.sdword) & trunc_mask; } default: { UD_ASSERT(!"invalid relative offset size."); return 0ull; } } } /* * asmprintf * Printf style function for printing translated assembly * output. Returns the number of characters written and * moves the buffer pointer forward. On an overflow, * returns a negative number and truncates the output. */ int ud_asmprintf(struct ud *u, const char *fmt, ...) { int ret; int avail; va_list ap; char* curr_buf = (u->asm_buf == NULL) ? u->asm_buf_int : u->asm_buf; size_t curr_buf_size = (curr_buf == u->asm_buf_int) ? sizeof(u->asm_buf_int) : u->asm_buf_size; va_start(ap, fmt); avail = (int) (curr_buf_size - u->asm_buf_fill - 1) /* nullchar */; ret = vsnprintf((char*) curr_buf + u->asm_buf_fill, avail, fmt, ap); if (ret < 0 || ret > avail) { u->asm_buf_fill = curr_buf_size - 1; } else { u->asm_buf_fill += ret; } va_end(ap); return ret; } void ud_syn_print_addr(struct ud *u, uint64_t addr) { const char *name = NULL; if (u->sym_resolver) { int64_t offset = 0; name = u->sym_resolver(u, addr, &offset); if (name) { if (offset) { ud_asmprintf(u, "%s%+" FMT64 "d", name, offset); } else { ud_asmprintf(u, "%s", name); } return; } } ud_asmprintf(u, "0x%" FMT64 "x", addr); } void ud_syn_print_imm(struct ud* u, const struct ud_operand *op) { uint64_t v; if (op->_oprcode == OP_sI && op->size != u->opr_mode) { if (op->size == 8) { v = (int64_t)op->lval.sbyte; } else { UD_ASSERT(op->size == 32); v = (int64_t)op->lval.sdword; } if (u->opr_mode < 64) { v = v & ((1ull << u->opr_mode) - 1ull); } } else { switch (op->size) { case 8 : v = op->lval.ubyte; break; case 16: v = op->lval.uword; break; case 32: v = op->lval.udword; break; case 64: v = op->lval.uqword; break; default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ } } ud_asmprintf(u, "0x%" FMT64 "x", v); } void ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *op, int sign) { UD_ASSERT(op->offset != 0); if (op->base == UD_NONE && op->index == UD_NONE) { uint64_t v; UD_ASSERT(op->scale == UD_NONE && op->offset != 8); /* unsigned mem-offset */ switch (op->offset) { case 16: v = op->lval.uword; break; case 32: v = op->lval.udword; break; case 64: v = op->lval.uqword; break; default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ } ud_asmprintf(u, "0x%" FMT64 "x", v); } else { int64_t v; UD_ASSERT(op->offset != 64); switch (op->offset) { case 8 : v = op->lval.sbyte; break; case 16: v = op->lval.sword; break; case 32: v = op->lval.sdword; break; default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ } if (v < 0) { ud_asmprintf(u, "-0x%" FMT64 "x", -v); } else if (v > 0) { ud_asmprintf(u, "%s0x%" FMT64 "x", sign? "+" : "", v); } } } /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/syn.h000066400000000000000000000041071457133061200165110ustar00rootroot00000000000000/* udis86 - libudis86/syn.h * * Copyright (c) 2002-2009 * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UD_SYN_H #define UD_SYN_H #include "types.h" #ifndef __UD_STANDALONE__ # include #endif /* __UD_STANDALONE__ */ extern const char* ud_reg_tab[]; extern const char* ud_flag_tab[]; uint64_t ud_syn_rel_target(struct ud*, struct ud_operand*); #ifdef __GNUC__ int ud_asmprintf(struct ud *u, const char *fmt, ...) __attribute__ ((format (printf, 2, 3))); #else int ud_asmprintf(struct ud *u, const char *fmt, ...); #endif void ud_syn_print_addr(struct ud *u, uint64_t addr); void ud_syn_print_imm(struct ud* u, const struct ud_operand *op); void ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *, int sign); #endif /* UD_SYN_H */ /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/types.h000066400000000000000000000233011457133061200170410ustar00rootroot00000000000000/* udis86 - libudis86/types.h * * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UD_TYPES_H #define UD_TYPES_H #ifdef KERNEL # include # include # include # ifndef __UD_STANDALONE__ # define __UD_STANDALONE__ 1 # endif #endif #ifdef __KERNEL__ /* * -D__KERNEL__ is automatically passed on the command line when * building something as part of the Linux kernel. Assume standalone * mode. */ # include # include # ifndef __UD_STANDALONE__ # define __UD_STANDALONE__ 1 # endif #endif /* __KERNEL__ */ #if !defined(__UD_STANDALONE__) # include # include #endif /* gcc specific extensions */ #ifdef __GNUC__ # define UD_ATTR_PACKED __attribute__((packed)) #else # define UD_ATTR_PACKED #endif /* UD_ATTR_PACKED */ /* ----------------------------------------------------------------------------- * All possible "types" of objects in udis86. Order is Important! * * NOTE: *** modify ud_type_to_value when adding new types here *** * * ----------------------------------------------------------------------------- */ enum ud_type { UD_NONE=0, // Note: UD_R_AL must be first register. /* 8 bit GPRs */ UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL, UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH, UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL, UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B, UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B, /* 16 bit GPRs */ UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX, UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI, UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W, UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W, /* 32 bit GPRs */ UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX, UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI, UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D, UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D, /* 64 bit GPRs */ UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX, UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI, UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11, UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15, /* segment registers */ UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS, UD_R_FS, UD_R_GS, /* control registers*/ UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3, UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7, UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11, UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15, /* debug registers */ UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3, UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7, UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11, UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15, /* mmx registers */ UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3, UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7, /* x87 registers */ UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3, UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7, /* extended multimedia registers */ UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3, UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7, UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11, UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15, UD_R_XMM16, UD_R_XMM17, UD_R_XMM18, UD_R_XMM19, UD_R_XMM20, UD_R_XMM21, UD_R_XMM22, UD_R_XMM23, UD_R_XMM24, UD_R_XMM25, UD_R_XMM26, UD_R_XMM27, UD_R_XMM28, UD_R_XMM29, UD_R_XMM30, UD_R_XMM31, /* 256B multimedia registers */ UD_R_YMM0, UD_R_YMM1, UD_R_YMM2, UD_R_YMM3, UD_R_YMM4, UD_R_YMM5, UD_R_YMM6, UD_R_YMM7, UD_R_YMM8, UD_R_YMM9, UD_R_YMM10, UD_R_YMM11, UD_R_YMM12, UD_R_YMM13, UD_R_YMM14, UD_R_YMM15, UD_R_YMM16, UD_R_YMM17, UD_R_YMM18, UD_R_YMM19, UD_R_YMM20, UD_R_YMM21, UD_R_YMM22, UD_R_YMM23, UD_R_YMM24, UD_R_YMM25, UD_R_YMM26, UD_R_YMM27, UD_R_YMM28, UD_R_YMM29, UD_R_YMM30, UD_R_YMM31, /* 512B multimedia registers */ UD_R_ZMM0, UD_R_ZMM1, UD_R_ZMM2, UD_R_ZMM3, UD_R_ZMM4, UD_R_ZMM5, UD_R_ZMM6, UD_R_ZMM7, UD_R_ZMM8, UD_R_ZMM9, UD_R_ZMM10, UD_R_ZMM11, UD_R_ZMM12, UD_R_ZMM13, UD_R_ZMM14, UD_R_ZMM15, UD_R_ZMM16, UD_R_ZMM17, UD_R_ZMM18, UD_R_ZMM19, UD_R_ZMM20, UD_R_ZMM21, UD_R_ZMM22, UD_R_ZMM23, UD_R_ZMM24, UD_R_ZMM25, UD_R_ZMM26, UD_R_ZMM27, UD_R_ZMM28, UD_R_ZMM29, UD_R_ZMM30, UD_R_ZMM31, /* AVX512 Opmask Registers */ UD_R_K0, UD_R_K1, UD_R_K2, UD_R_K3, UD_R_K4, UD_R_K5, UD_R_K6, UD_R_K7, /* Bounds Registers (Intel MPX)*/ UD_R_BND0, UD_R_BND1, UD_R_BND2, UD_R_BND3, // Note: must be last register UD_R_RIP, /* Operand Types */ UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM, UD_OP_JIMM, UD_OP_CONST }; enum ud_eflag_state { UD_FLAG_UNCHANGED, UD_FLAG_TESTED, UD_FLAG_MODIFIED, UD_FLAG_RESET, UD_FLAG_SET, UD_FLAG_UNDEFINED, UD_FLAG_PRIOR }; // TODO: seems to be duplicated with the enum below. #define UD_ACCESS_NONE 0 #define UD_ACCESS_READ (1 << 1) #define UD_ACCESS_WRITE (1 << 2) enum ud_operand_access { UD_OP_ACCESS_READ = 1, UD_OP_ACCESS_WRITE = 2 }; #define UD_FLAG_OF 0 #define UD_FLAG_SF 1 #define UD_FLAG_ZF 2 #define UD_FLAG_AF 3 #define UD_FLAG_PF 4 #define UD_FLAG_CF 5 #define UD_FLAG_TF 6 #define UD_FLAG_IF 7 #define UD_FLAG_DF 8 #define UD_FLAG_NF 9 #define UD_FLAG_RF 10 #define UD_FLAG_AC 11 #define UD_FLAG_MAX (UD_FLAG_AC+1) /* This structure describes the state of the EFLAGS register * once an instruction has been executed. */ struct ud_eflags { enum ud_eflag_state flag[UD_FLAG_MAX]; }; #include "itab.h" union ud_lval { int8_t sbyte; uint8_t ubyte; int16_t sword; uint16_t uword; int32_t sdword; uint32_t udword; int64_t sqword; uint64_t uqword; struct { uint16_t seg; uint32_t off; } ptr; }; /* ----------------------------------------------------------------------------- * struct ud_operand - Disassembled instruction Operand. * ----------------------------------------------------------------------------- */ struct ud_operand { union ud_lval lval; enum ud_type type; //enum ud_type opmask; // AVX512 opmask, ko-k7 enum ud_type base; enum ud_type index; uint16_t size; uint8_t scale; uint8_t offset; uint8_t signed_lval; uint8_t access; /* * internal use only */ uint8_t _oprcode; }; /* ----------------------------------------------------------------------------- * struct ud - The udis86 object. * ----------------------------------------------------------------------------- */ struct ud { /* * input buffering */ int (*inp_hook) (struct ud*); #ifndef __UD_STANDALONE__ FILE* inp_file; #endif const uint8_t* inp_buf; size_t inp_buf_size; size_t inp_buf_index; uint8_t inp_curr; size_t inp_ctr; uint8_t inp_sess[64]; int inp_end; int inp_peek; void (*translator)(struct ud*); uint64_t insn_offset; char insn_hexcode[64]; /* * Assembly output buffer */ char *asm_buf; size_t asm_buf_size; size_t asm_buf_fill; char asm_buf_int[128]; /* * Symbol resolver for use in the translation phase. */ const char* (*sym_resolver)(struct ud*, uint64_t addr, int64_t *offset); uint8_t dis_mode; uint64_t pc; uint8_t vendor; enum ud_mnemonic_code mnemonic; struct ud_operand operand[4]; uint8_t error; uint8_t _rex; uint8_t pfx_rex; uint8_t pfx_seg; uint8_t pfx_opr; uint8_t pfx_adr; uint8_t pfx_lock; uint8_t pfx_str; uint8_t pfx_bnd; uint8_t pfx_xacquire; uint8_t pfx_xrelease; uint8_t pfx_rep; uint8_t pfx_repe; uint8_t pfx_repne; uint8_t opr_mode; uint8_t adr_mode; uint8_t br_far; uint8_t br_near; uint8_t have_modrm; uint8_t modrm; uint8_t vex_op; uint8_t vex_b1; uint8_t vex_b2; void * user_opaque_data; struct ud_itab_entry * itab_entry; struct ud_lookup_table_list_entry *le; }; /* ----------------------------------------------------------------------------- * Type-definitions * ----------------------------------------------------------------------------- */ typedef enum ud_type ud_type_t; typedef enum ud_mnemonic_code ud_mnemonic_code_t; typedef struct ud ud_t; typedef struct ud_operand ud_operand_t; #define UD_SYN_INTEL ud_translate_intel #define UD_SYN_ATT ud_translate_att #define UD_EOI (-1) #define UD_INP_CACHE_SZ 32 #define UD_VENDOR_AMD 0 #define UD_VENDOR_INTEL 1 #define UD_VENDOR_ANY 2 #endif /* vim: set ts=2 sw=2 expandtab */ libudis86-0+20221013/libudis86/udint.h000066400000000000000000000055741457133061200170340ustar00rootroot00000000000000/* udis86 - libudis86/udint.h -- definitions for internal use only * * Copyright (c) 2002-2009 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _UDINT_H_ #define _UDINT_H_ #ifdef HAVE_CONFIG_H # include #endif /* HAVE_CONFIG_H */ #if defined(UD_DEBUG) && HAVE_ASSERT_H # include # define UD_ASSERT(_x) assert(_x) #else # define UD_ASSERT(_x) #endif /* !HAVE_ASSERT_H */ #if defined(UD_DEBUG) #define UDERR(u, msg) \ do { \ (u)->error = 1; \ fprintf(stderr, "decode-error: %s:%d: %s", \ __FILE__, __LINE__, (msg)); \ } while (0) #else #define UDERR(u, m) \ do { \ (u)->error = 1; \ } while (0) #endif /* !LOGERR */ #define UD_RETURN_ON_ERROR(u) \ do { \ if ((u)->error != 0) { \ return (u)->error; \ } \ } while (0) #define UD_RETURN_WITH_ERROR(u, m) \ do { \ UDERR(u, m); \ return (u)->error; \ } while (0) #ifndef __UD_STANDALONE__ # define UD_NON_STANDALONE(x) x #else # define UD_NON_STANDALONE(x) #endif /* printf formatting int64 specifier */ #ifdef FMT64 # undef FMT64 #endif #if defined(_MSC_VER) || defined(__BORLANDC__) # define FMT64 "I64" #else # if defined(__APPLE__) # define FMT64 "ll" # elif defined(__amd64__) || defined(__x86_64__) # define FMT64 "l" # else # define FMT64 "ll" # endif /* !x64 */ #endif /* define an inline macro */ #if defined(_MSC_VER) || defined(__BORLANDC__) # define UD_INLINE __inline /* MS Visual Studio requires __inline instead of inline for C code */ #else # define UD_INLINE inline #endif #endif /* _UDINT_H_ */ libudis86-0+20221013/libudis86/udis86.c000066400000000000000000000573101457133061200170210ustar00rootroot00000000000000/* udis86 - libudis86/udis86.c * * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "udint.h" #include "extern.h" #include "decode.h" #include #if HAVE_STRING_H # include #endif static void ud_inp_init(struct ud *u); /* ============================================================================= * ud_init * Initializes ud_t object. * ============================================================================= */ extern void ud_init(struct ud* u) { memset((void*)u, 0, sizeof(struct ud)); ud_set_mode(u, 16); u->mnemonic = UD_Iinvalid; ud_set_pc(u, 0); #ifndef __UD_STANDALONE__ ud_set_input_file(u, stdin); #endif /* __UD_STANDALONE__ */ u->asm_buf = NULL; u->asm_buf_size = 0; } /* ============================================================================= * ud_disassemble * Disassembles one instruction and returns the number of * bytes disassembled. A zero means end of disassembly. * ============================================================================= */ extern unsigned int ud_disassemble(struct ud* u) { int len; if (u->inp_end) { return 0; } if ((len = ud_decode(u)) > 0) { if (u->translator != NULL) { u->asm_buf_int[0] = '\0'; if (u->asm_buf && u->asm_buf_size > 0) { u->asm_buf[0] = '\0'; } u->translator(u); } } return len; } /* ============================================================================= * ud_set_mode() - Set Disassemly Mode. * ============================================================================= */ extern void ud_set_mode(struct ud* u, uint8_t m) { switch(m) { case 16: case 32: case 64: u->dis_mode = m ; return; default: u->dis_mode = 16; return; } } /* ============================================================================= * ud_set_vendor() - Set vendor. * ============================================================================= */ extern void ud_set_vendor(struct ud* u, unsigned v) { switch(v) { case UD_VENDOR_INTEL: u->vendor = v; break; case UD_VENDOR_ANY: u->vendor = v; break; default: u->vendor = UD_VENDOR_AMD; } } /* ============================================================================= * ud_set_pc() - Sets code origin. * ============================================================================= */ extern void ud_set_pc(struct ud* u, uint64_t o) { u->pc = o; } /* ============================================================================= * ud_set_syntax() - Sets the output syntax. * ============================================================================= */ extern void ud_set_syntax(struct ud* u, void (*t)(struct ud*)) { u->translator = t; } /* ============================================================================= * ud_insn() - returns the disassembled instruction * ============================================================================= */ const char* ud_insn_asm(const struct ud* u) { if (u->asm_buf != NULL) { return u->asm_buf; } return u->asm_buf_int; } /* ============================================================================= * ud_insn_offset() - Returns the offset. * ============================================================================= */ uint64_t ud_insn_off(const struct ud* u) { return u->insn_offset; } /* ============================================================================= * ud_insn_hex() - Returns hex form of disassembled instruction. * ============================================================================= */ const char* ud_insn_hex(struct ud* u) { u->insn_hexcode[0] = 0; if (!u->error) { unsigned int i; const unsigned char *src_ptr = ud_insn_ptr(u); char* src_hex; src_hex = (char*) u->insn_hexcode; /* for each byte used to decode instruction */ for (i = 0; i < ud_insn_len(u) && i < sizeof(u->insn_hexcode) / 2; ++i, ++src_ptr) { sprintf(src_hex, "%02x", *src_ptr & 0xFF); src_hex += 2; } } return u->insn_hexcode; } /* ============================================================================= * ud_insn_ptr * Returns a pointer to buffer containing the bytes that were * disassembled. * ============================================================================= */ extern const uint8_t* ud_insn_ptr(const struct ud* u) { return (u->inp_buf == NULL) ? u->inp_sess : u->inp_buf + (u->inp_buf_index - u->inp_ctr); } /* ============================================================================= * ud_insn_len * Returns the count of bytes disassembled. * ============================================================================= */ extern unsigned int ud_insn_len(const struct ud* u) { return (unsigned int) u->inp_ctr; } /* ============================================================================= * ud_insn_get_opr * Return the operand struct representing the nth operand of * the currently disassembled instruction. Returns NULL if * there's no such operand. * ============================================================================= */ const struct ud_operand* ud_insn_opr(const struct ud *u, unsigned int n) { if (n > 3 || u->operand[n].type == UD_NONE) { return NULL; } else { return &u->operand[n]; } } /* ============================================================================= * ud_opr_is_sreg * Returns non-zero if the given operand is of a segment register type. * ============================================================================= */ int ud_opr_is_sreg(const struct ud_operand *opr) { return opr->type == UD_OP_REG && opr->base >= UD_R_ES && opr->base <= UD_R_GS; } /* ============================================================================= * ud_opr_is_sreg * Returns non-zero if the given operand is of a general purpose * register type. * ============================================================================= */ int ud_opr_is_gpr(const struct ud_operand *opr) { return opr->type == UD_OP_REG && opr->base >= UD_R_AL && opr->base <= UD_R_R15; } /* ============================================================================= * ud_set_user_opaque_data * ud_get_user_opaque_data * Get/set user opaqute data pointer * ============================================================================= */ void ud_set_user_opaque_data(struct ud * u, void* opaque) { u->user_opaque_data = opaque; } void* ud_get_user_opaque_data(const struct ud *u) { return u->user_opaque_data; } /* ============================================================================= * ud_set_asm_buffer * Allow the user to set an assembler output buffer. If `buf` is NULL, * we switch back to the internal buffer. * ============================================================================= */ void ud_set_asm_buffer(struct ud *u, char *buf, size_t size) { if (buf == NULL) { ud_set_asm_buffer(u, u->asm_buf_int, sizeof(u->asm_buf_int)); } else { u->asm_buf = buf; u->asm_buf_size = size; } } /* ============================================================================= * ud_set_sym_resolver * Set symbol resolver for relative targets used in the translation * phase. * * The resolver is a function that takes a uint64_t address and returns a * symbolic name for the that address. The function also takes a second * argument pointing to an integer that the client can optionally set to a * non-zero value for offsetted targets. (symbol+offset) The function may * also return NULL, in which case the translator only prints the target * address. * * The function pointer maybe NULL which resets symbol resolution. * ============================================================================= */ void ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*, uint64_t addr, int64_t *offset)) { u->sym_resolver = resolver; } /* ============================================================================= * ud_insn_mnemonic * Return the current instruction mnemonic. * ============================================================================= */ enum ud_mnemonic_code ud_insn_mnemonic(const struct ud *u) { return u->mnemonic; } /* ============================================================================= * ud_lookup_mnemonic * Looks up mnemonic code in the mnemonic string table. * Returns NULL if the mnemonic code is invalid. * ============================================================================= */ const char* ud_lookup_mnemonic(enum ud_mnemonic_code c) { if (c < UD_MAX_MNEMONIC_CODE) { return ud_mnemonics_str[c]; } else { return NULL; } } /* ============================================================================= * ud_lookup_eflags * Looks up eflags information structure * Returns NULL if invalid. * ============================================================================= */ const struct ud_eflags* ud_lookup_eflags(struct ud *u) { if (u == NULL || u->itab_entry == NULL) { return NULL; } else { return &u->itab_entry->eflags; } } /* ============================================================================= * ud_lookup_implicit_reg_used_list * Returns the list of register implicitly used. * The list is terminated by UD_NONE. * Returns NULL if invalid. * ============================================================================= */ const enum ud_type* ud_lookup_implicit_reg_used_list(struct ud *u) { if (u == NULL || u->itab_entry == NULL) { return NULL; } else { return u->itab_entry->implicit_register_uses; } } /* ============================================================================= * ud_lookup_implicit_reg_used_list * Returns the list of register implicitly modified. * The list is terminated by UD_NONE. * Returns NULL if invalid. * ============================================================================= */ const enum ud_type* ud_lookup_implicit_reg_defined_list(struct ud *u) { if (u == NULL || u->itab_entry == NULL) { return NULL; } else { return u->itab_entry->implicit_register_defs; } } /* * ud_inp_init * Initializes the input system. */ static void ud_inp_init(struct ud *u) { u->inp_hook = NULL; u->inp_buf = NULL; u->inp_buf_size = 0; u->inp_buf_index = 0; u->inp_curr = 0; u->inp_ctr = 0; u->inp_end = 0; u->inp_peek = UD_EOI; UD_NON_STANDALONE(u->inp_file = NULL); } /* ============================================================================= * ud_inp_set_hook * Sets input hook. * ============================================================================= */ void ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*)) { ud_inp_init(u); u->inp_hook = hook; } /* ============================================================================= * ud_inp_set_buffer * Set buffer as input. * ============================================================================= */ void ud_set_input_buffer(register struct ud* u, const uint8_t* buf, size_t len) { ud_inp_init(u); u->inp_buf = buf; u->inp_buf_size = len; u->inp_buf_index = 0; } #ifndef __UD_STANDALONE__ /* ============================================================================= * ud_input_set_file * Set FILE as input. * ============================================================================= */ static int inp_file_hook(struct ud* u) { return fgetc(u->inp_file); } void ud_set_input_file(register struct ud* u, FILE* f) { ud_inp_init(u); u->inp_hook = inp_file_hook; u->inp_file = f; } #endif /* __UD_STANDALONE__ */ /* ============================================================================= * ud_input_skip * Skip n input bytes. * ============================================================================ */ void ud_input_skip(struct ud* u, size_t n) { if (u->inp_end) { return; } if (u->inp_buf == NULL) { while (n--) { int c = u->inp_hook(u); if (c == UD_EOI) { goto eoi; } } return; } else { if (n > u->inp_buf_size || u->inp_buf_index > u->inp_buf_size - n) { u->inp_buf_index = u->inp_buf_size; goto eoi; } u->inp_buf_index += n; return; } eoi: u->inp_end = 1; UDERR(u, "cannot skip, eoi received\b"); return; } /* ============================================================================= * ud_input_end * Returns non-zero on end-of-input. * ============================================================================= */ int ud_input_end(const struct ud *u) { return u->inp_end; } const char *ud_type_to_value(enum ud_type x) { if (x == UD_NONE) return "UD_NONE"; if (x == UD_R_AL) return "UD_R_AL"; if (x == UD_R_CL) return "UD_R_CL"; if (x == UD_R_DL) return "UD_R_DL"; if (x == UD_R_BL) return "UD_R_BL"; if (x == UD_R_AH) return "UD_R_AH"; if (x == UD_R_CH) return "UD_R_CH"; if (x == UD_R_DH) return "UD_R_DH"; if (x == UD_R_BH) return "UD_R_BH"; if (x == UD_R_SPL) return "UD_R_SPL"; if (x == UD_R_BPL) return "UD_R_BPL"; if (x == UD_R_SIL) return "UD_R_SIL"; if (x == UD_R_DIL) return "UD_R_DIL"; if (x == UD_R_R8B) return "UD_R_R8B"; if (x == UD_R_R9B) return "UD_R_R9B"; if (x == UD_R_R10B) return "UD_R_R10B"; if (x == UD_R_R11B) return "UD_R_R11B"; if (x == UD_R_R12B) return "UD_R_R12B"; if (x == UD_R_R13B) return "UD_R_R13B"; if (x == UD_R_R14B) return "UD_R_R14B"; if (x == UD_R_R15B) return "UD_R_R15B"; if (x == UD_R_AX) return "UD_R_AX"; if (x == UD_R_CX) return "UD_R_CX"; if (x == UD_R_DX) return "UD_R_DX"; if (x == UD_R_BX) return "UD_R_BX"; if (x == UD_R_SP) return "UD_R_SP"; if (x == UD_R_BP) return "UD_R_BP"; if (x == UD_R_SI) return "UD_R_SI"; if (x == UD_R_DI) return "UD_R_DI"; if (x == UD_R_R8W) return "UD_R_R8W"; if (x == UD_R_R9W) return "UD_R_R9W"; if (x == UD_R_R10W) return "UD_R_R10W"; if (x == UD_R_R11W) return "UD_R_R11W"; if (x == UD_R_R12W) return "UD_R_R12W"; if (x == UD_R_R13W) return "UD_R_R13W"; if (x == UD_R_R14W) return "UD_R_R14W"; if (x == UD_R_R15W) return "UD_R_R15W"; if (x == UD_R_EAX) return "UD_R_EAX"; if (x == UD_R_ECX) return "UD_R_ECX"; if (x == UD_R_EDX) return "UD_R_EDX"; if (x == UD_R_EBX) return "UD_R_EBX"; if (x == UD_R_ESP) return "UD_R_ESP"; if (x == UD_R_EBP) return "UD_R_EBP"; if (x == UD_R_ESI) return "UD_R_ESI"; if (x == UD_R_EDI) return "UD_R_EDI"; if (x == UD_R_R8D) return "UD_R_R8D"; if (x == UD_R_R9D) return "UD_R_R9D"; if (x == UD_R_R10D) return "UD_R_R10D"; if (x == UD_R_R11D) return "UD_R_R11D"; if (x == UD_R_R12D) return "UD_R_R12D"; if (x == UD_R_R13D) return "UD_R_R13D"; if (x == UD_R_R14D) return "UD_R_R14D"; if (x == UD_R_R15D) return "UD_R_R15D"; if (x == UD_R_RAX) return "UD_R_RAX"; if (x == UD_R_RCX) return "UD_R_RCX"; if (x == UD_R_RDX) return "UD_R_RDX"; if (x == UD_R_RBX) return "UD_R_RBX"; if (x == UD_R_RSP) return "UD_R_RSP"; if (x == UD_R_RBP) return "UD_R_RBP"; if (x == UD_R_RSI) return "UD_R_RSI"; if (x == UD_R_RDI) return "UD_R_RDI"; if (x == UD_R_R8) return "UD_R_R8"; if (x == UD_R_R9) return "UD_R_R9"; if (x == UD_R_R10) return "UD_R_R10"; if (x == UD_R_R11) return "UD_R_R11"; if (x == UD_R_R12) return "UD_R_R12"; if (x == UD_R_R13) return "UD_R_R13"; if (x == UD_R_R14) return "UD_R_R14"; if (x == UD_R_R15) return "UD_R_R15"; if (x == UD_R_ES) return "UD_R_ES"; if (x == UD_R_CS) return "UD_R_CS"; if (x == UD_R_SS) return "UD_R_SS"; if (x == UD_R_DS) return "UD_R_DS"; if (x == UD_R_FS) return "UD_R_FS"; if (x == UD_R_GS) return "UD_R_GS"; if (x == UD_R_CR0) return "UD_R_CR0"; if (x == UD_R_CR1) return "UD_R_CR1"; if (x == UD_R_CR2) return "UD_R_CR2"; if (x == UD_R_CR3) return "UD_R_CR3"; if (x == UD_R_CR4) return "UD_R_CR4"; if (x == UD_R_CR5) return "UD_R_CR5"; if (x == UD_R_CR6) return "UD_R_CR6"; if (x == UD_R_CR7) return "UD_R_CR7"; if (x == UD_R_CR8) return "UD_R_CR8"; if (x == UD_R_CR9) return "UD_R_CR9"; if (x == UD_R_CR10) return "UD_R_CR10"; if (x == UD_R_CR11) return "UD_R_CR11"; if (x == UD_R_CR12) return "UD_R_CR12"; if (x == UD_R_CR13) return "UD_R_CR13"; if (x == UD_R_CR14) return "UD_R_CR14"; if (x == UD_R_CR15) return "UD_R_CR15"; if (x == UD_R_DR0) return "UD_R_DR0"; if (x == UD_R_DR1) return "UD_R_DR1"; if (x == UD_R_DR2) return "UD_R_DR2"; if (x == UD_R_DR3) return "UD_R_DR3"; if (x == UD_R_DR4) return "UD_R_DR4"; if (x == UD_R_DR5) return "UD_R_DR5"; if (x == UD_R_DR6) return "UD_R_DR6"; if (x == UD_R_DR7) return "UD_R_DR7"; if (x == UD_R_DR8) return "UD_R_DR8"; if (x == UD_R_DR9) return "UD_R_DR9"; if (x == UD_R_DR10) return "UD_R_DR10"; if (x == UD_R_DR11) return "UD_R_DR11"; if (x == UD_R_DR12) return "UD_R_DR12"; if (x == UD_R_DR13) return "UD_R_DR13"; if (x == UD_R_DR14) return "UD_R_DR14"; if (x == UD_R_DR15) return "UD_R_DR15"; if (x == UD_R_MM0) return "UD_R_MM0"; if (x == UD_R_MM1) return "UD_R_MM1"; if (x == UD_R_MM2) return "UD_R_MM2"; if (x == UD_R_MM3) return "UD_R_MM3"; if (x == UD_R_MM4) return "UD_R_MM4"; if (x == UD_R_MM5) return "UD_R_MM5"; if (x == UD_R_MM6) return "UD_R_MM6"; if (x == UD_R_MM7) return "UD_R_MM7"; if (x == UD_R_ST0) return "UD_R_ST0"; if (x == UD_R_ST1) return "UD_R_ST1"; if (x == UD_R_ST2) return "UD_R_ST2"; if (x == UD_R_ST3) return "UD_R_ST3"; if (x == UD_R_ST4) return "UD_R_ST4"; if (x == UD_R_ST5) return "UD_R_ST5"; if (x == UD_R_ST6) return "UD_R_ST6"; if (x == UD_R_ST7) return "UD_R_ST7"; if (x == UD_R_XMM0) return "UD_R_XMM0"; if (x == UD_R_XMM1) return "UD_R_XMM1"; if (x == UD_R_XMM2) return "UD_R_XMM2"; if (x == UD_R_XMM3) return "UD_R_XMM3"; if (x == UD_R_XMM4) return "UD_R_XMM4"; if (x == UD_R_XMM5) return "UD_R_XMM5"; if (x == UD_R_XMM6) return "UD_R_XMM6"; if (x == UD_R_XMM7) return "UD_R_XMM7"; if (x == UD_R_XMM8) return "UD_R_XMM8"; if (x == UD_R_XMM9) return "UD_R_XMM9"; if (x == UD_R_XMM10) return "UD_R_XMM10"; if (x == UD_R_XMM11) return "UD_R_XMM11"; if (x == UD_R_XMM12) return "UD_R_XMM12"; if (x == UD_R_XMM13) return "UD_R_XMM13"; if (x == UD_R_XMM14) return "UD_R_XMM14"; if (x == UD_R_XMM15) return "UD_R_XMM15"; if (x == UD_R_XMM16) return "UD_R_XMM16"; if (x == UD_R_XMM17) return "UD_R_XMM17"; if (x == UD_R_XMM18) return "UD_R_XMM18"; if (x == UD_R_XMM19) return "UD_R_XMM19"; if (x == UD_R_XMM20) return "UD_R_XMM20"; if (x == UD_R_XMM21) return "UD_R_XMM21"; if (x == UD_R_XMM22) return "UD_R_XMM22"; if (x == UD_R_XMM23) return "UD_R_XMM23"; if (x == UD_R_XMM24) return "UD_R_XMM24"; if (x == UD_R_XMM25) return "UD_R_XMM25"; if (x == UD_R_XMM26) return "UD_R_XMM26"; if (x == UD_R_XMM27) return "UD_R_XMM27"; if (x == UD_R_XMM28) return "UD_R_XMM28"; if (x == UD_R_XMM29) return "UD_R_XMM29"; if (x == UD_R_XMM30) return "UD_R_XMM30"; if (x == UD_R_XMM31) return "UD_R_XMM31"; if (x == UD_R_YMM0) return "UD_R_YMM0"; if (x == UD_R_YMM1) return "UD_R_YMM1"; if (x == UD_R_YMM2) return "UD_R_YMM2"; if (x == UD_R_YMM3) return "UD_R_YMM3"; if (x == UD_R_YMM4) return "UD_R_YMM4"; if (x == UD_R_YMM5) return "UD_R_YMM5"; if (x == UD_R_YMM6) return "UD_R_YMM6"; if (x == UD_R_YMM7) return "UD_R_YMM7"; if (x == UD_R_YMM8) return "UD_R_YMM8"; if (x == UD_R_YMM9) return "UD_R_YMM9"; if (x == UD_R_YMM10) return "UD_R_YMM10"; if (x == UD_R_YMM11) return "UD_R_YMM11"; if (x == UD_R_YMM12) return "UD_R_YMM12"; if (x == UD_R_YMM13) return "UD_R_YMM13"; if (x == UD_R_YMM14) return "UD_R_YMM14"; if (x == UD_R_YMM15) return "UD_R_YMM15"; if (x == UD_R_YMM16) return "UD_R_YMM16"; if (x == UD_R_YMM17) return "UD_R_YMM17"; if (x == UD_R_YMM18) return "UD_R_YMM18"; if (x == UD_R_YMM19) return "UD_R_YMM19"; if (x == UD_R_YMM20) return "UD_R_YMM20"; if (x == UD_R_YMM21) return "UD_R_YMM21"; if (x == UD_R_YMM22) return "UD_R_YMM22"; if (x == UD_R_YMM23) return "UD_R_YMM23"; if (x == UD_R_YMM24) return "UD_R_YMM24"; if (x == UD_R_YMM25) return "UD_R_YMM25"; if (x == UD_R_YMM26) return "UD_R_YMM26"; if (x == UD_R_YMM27) return "UD_R_YMM27"; if (x == UD_R_YMM28) return "UD_R_YMM28"; if (x == UD_R_YMM29) return "UD_R_YMM29"; if (x == UD_R_YMM30) return "UD_R_YMM30"; if (x == UD_R_YMM31) return "UD_R_YMM31"; if (x == UD_R_ZMM0) return "UD_R_ZMM0"; if (x == UD_R_ZMM1) return "UD_R_ZMM1"; if (x == UD_R_ZMM2) return "UD_R_ZMM2"; if (x == UD_R_ZMM3) return "UD_R_ZMM3"; if (x == UD_R_ZMM4) return "UD_R_ZMM4"; if (x == UD_R_ZMM5) return "UD_R_ZMM5"; if (x == UD_R_ZMM6) return "UD_R_ZMM6"; if (x == UD_R_ZMM7) return "UD_R_ZMM7"; if (x == UD_R_ZMM8) return "UD_R_ZMM8"; if (x == UD_R_ZMM9) return "UD_R_ZMM9"; if (x == UD_R_ZMM10) return "UD_R_ZMM10"; if (x == UD_R_ZMM11) return "UD_R_ZMM11"; if (x == UD_R_ZMM12) return "UD_R_ZMM12"; if (x == UD_R_ZMM13) return "UD_R_ZMM13"; if (x == UD_R_ZMM14) return "UD_R_ZMM14"; if (x == UD_R_ZMM15) return "UD_R_ZMM15"; if (x == UD_R_ZMM16) return "UD_R_ZMM16"; if (x == UD_R_ZMM17) return "UD_R_ZMM17"; if (x == UD_R_ZMM18) return "UD_R_ZMM18"; if (x == UD_R_ZMM19) return "UD_R_ZMM19"; if (x == UD_R_ZMM20) return "UD_R_ZMM20"; if (x == UD_R_ZMM21) return "UD_R_ZMM21"; if (x == UD_R_ZMM22) return "UD_R_ZMM22"; if (x == UD_R_ZMM23) return "UD_R_ZMM23"; if (x == UD_R_ZMM24) return "UD_R_ZMM24"; if (x == UD_R_ZMM25) return "UD_R_ZMM25"; if (x == UD_R_ZMM26) return "UD_R_ZMM26"; if (x == UD_R_ZMM27) return "UD_R_ZMM27"; if (x == UD_R_ZMM28) return "UD_R_ZMM28"; if (x == UD_R_ZMM29) return "UD_R_ZMM29"; if (x == UD_R_ZMM30) return "UD_R_ZMM30"; if (x == UD_R_ZMM31) return "UD_R_ZMM31"; if (x == UD_R_K0) return "UD_R_K0"; if (x == UD_R_K1) return "UD_R_K1"; if (x == UD_R_K2) return "UD_R_K2"; if (x == UD_R_K3) return "UD_R_K3"; if (x == UD_R_K4) return "UD_R_K4"; if (x == UD_R_K5) return "UD_R_K5"; if (x == UD_R_K6) return "UD_R_K6"; if (x == UD_R_K7) return "UD_R_K7"; if (x == UD_R_BND0) return "UD_R_BND0"; if (x == UD_R_BND1) return "UD_R_BND1"; if (x == UD_R_BND2) return "UD_R_BND2"; if (x == UD_R_BND3) return "UD_R_BND3"; if (x == UD_R_RIP) return "UD_R_RIP"; if (x == UD_OP_REG) return "UD_OP_REG"; if (x == UD_OP_MEM) return "UD_OP_MEM"; if (x == UD_OP_PTR) return "UD_OP_PTR"; if (x == UD_OP_IMM) return "UD_OP_IMM"; if (x == UD_OP_JIMM) return "UD_OP_JIMM"; if (x == UD_OP_CONST) return "UD_OP_CONST"; return "???"; } /* vim:set ts=2 sw=2 expandtab */ libudis86-0+20221013/m4/000077500000000000000000000000001457133061200142345ustar00rootroot00000000000000libudis86-0+20221013/m4/ax_compare_version.m4000066400000000000000000000146521457133061200203710ustar00rootroot00000000000000# =========================================================================== # http://www.gnu.org/software/autoconf-archive/ax_compare_version.html # =========================================================================== # # SYNOPSIS # # AX_COMPARE_VERSION(VERSION_A, OP, VERSION_B, [ACTION-IF-TRUE], [ACTION-IF-FALSE]) # # DESCRIPTION # # This macro compares two version strings. Due to the various number of # minor-version numbers that can exist, and the fact that string # comparisons are not compatible with numeric comparisons, this is not # necessarily trivial to do in a autoconf script. This macro makes doing # these comparisons easy. # # The six basic comparisons are available, as well as checking equality # limited to a certain number of minor-version levels. # # The operator OP determines what type of comparison to do, and can be one # of: # # eq - equal (test A == B) # ne - not equal (test A != B) # le - less than or equal (test A <= B) # ge - greater than or equal (test A >= B) # lt - less than (test A < B) # gt - greater than (test A > B) # # Additionally, the eq and ne operator can have a number after it to limit # the test to that number of minor versions. # # eq0 - equal up to the length of the shorter version # ne0 - not equal up to the length of the shorter version # eqN - equal up to N sub-version levels # neN - not equal up to N sub-version levels # # When the condition is true, shell commands ACTION-IF-TRUE are run, # otherwise shell commands ACTION-IF-FALSE are run. The environment # variable 'ax_compare_version' is always set to either 'true' or 'false' # as well. # # Examples: # # AX_COMPARE_VERSION([3.15.7],[lt],[3.15.8]) # AX_COMPARE_VERSION([3.15],[lt],[3.15.8]) # # would both be true. # # AX_COMPARE_VERSION([3.15.7],[eq],[3.15.8]) # AX_COMPARE_VERSION([3.15],[gt],[3.15.8]) # # would both be false. # # AX_COMPARE_VERSION([3.15.7],[eq2],[3.15.8]) # # would be true because it is only comparing two minor versions. # # AX_COMPARE_VERSION([3.15.7],[eq0],[3.15]) # # would be true because it is only comparing the lesser number of minor # versions of the two values. # # Note: The characters that separate the version numbers do not matter. An # empty string is the same as version 0. OP is evaluated by autoconf, not # configure, so must be a string, not a variable. # # The author would like to acknowledge Guido Draheim whose advice about # the m4_case and m4_ifvaln functions make this macro only include the # portions necessary to perform the specific comparison specified by the # OP argument in the final configure script. # # LICENSE # # Copyright (c) 2008 Tim Toolan # # Copying and distribution of this file, with or without modification, are # permitted in any medium without royalty provided the copyright notice # and this notice are preserved. This file is offered as-is, without any # warranty. #serial 11 dnl ######################################################################### AC_DEFUN([AX_COMPARE_VERSION], [ AC_REQUIRE([AC_PROG_AWK]) # Used to indicate true or false condition ax_compare_version=false # Convert the two version strings to be compared into a format that # allows a simple string comparison. The end result is that a version # string of the form 1.12.5-r617 will be converted to the form # 0001001200050617. In other words, each number is zero padded to four # digits, and non digits are removed. AS_VAR_PUSHDEF([A],[ax_compare_version_A]) A=`echo "$1" | sed -e 's/\([[0-9]]*\)/Z\1Z/g' \ -e 's/Z\([[0-9]]\)Z/Z0\1Z/g' \ -e 's/Z\([[0-9]][[0-9]]\)Z/Z0\1Z/g' \ -e 's/Z\([[0-9]][[0-9]][[0-9]]\)Z/Z0\1Z/g' \ -e 's/[[^0-9]]//g'` AS_VAR_PUSHDEF([B],[ax_compare_version_B]) B=`echo "$3" | sed -e 's/\([[0-9]]*\)/Z\1Z/g' \ -e 's/Z\([[0-9]]\)Z/Z0\1Z/g' \ -e 's/Z\([[0-9]][[0-9]]\)Z/Z0\1Z/g' \ -e 's/Z\([[0-9]][[0-9]][[0-9]]\)Z/Z0\1Z/g' \ -e 's/[[^0-9]]//g'` dnl # In the case of le, ge, lt, and gt, the strings are sorted as necessary dnl # then the first line is used to determine if the condition is true. dnl # The sed right after the echo is to remove any indented white space. m4_case(m4_tolower($2), [lt],[ ax_compare_version=`echo "x$A x$B" | sed 's/^ *//' | sort -r | sed "s/x${A}/false/;s/x${B}/true/;1q"` ], [gt],[ ax_compare_version=`echo "x$A x$B" | sed 's/^ *//' | sort | sed "s/x${A}/false/;s/x${B}/true/;1q"` ], [le],[ ax_compare_version=`echo "x$A x$B" | sed 's/^ *//' | sort | sed "s/x${A}/true/;s/x${B}/false/;1q"` ], [ge],[ ax_compare_version=`echo "x$A x$B" | sed 's/^ *//' | sort -r | sed "s/x${A}/true/;s/x${B}/false/;1q"` ],[ dnl Split the operator from the subversion count if present. m4_bmatch(m4_substr($2,2), [0],[ # A count of zero means use the length of the shorter version. # Determine the number of characters in A and B. ax_compare_version_len_A=`echo "$A" | $AWK '{print(length)}'` ax_compare_version_len_B=`echo "$B" | $AWK '{print(length)}'` # Set A to no more than B's length and B to no more than A's length. A=`echo "$A" | sed "s/\(.\{$ax_compare_version_len_B\}\).*/\1/"` B=`echo "$B" | sed "s/\(.\{$ax_compare_version_len_A\}\).*/\1/"` ], [[0-9]+],[ # A count greater than zero means use only that many subversions A=`echo "$A" | sed "s/\(\([[0-9]]\{4\}\)\{m4_substr($2,2)\}\).*/\1/"` B=`echo "$B" | sed "s/\(\([[0-9]]\{4\}\)\{m4_substr($2,2)\}\).*/\1/"` ], [.+],[ AC_WARNING( [illegal OP numeric parameter: $2]) ],[]) # Pad zeros at end of numbers to make same length. ax_compare_version_tmp_A="$A`echo $B | sed 's/./0/g'`" B="$B`echo $A | sed 's/./0/g'`" A="$ax_compare_version_tmp_A" # Check for equality or inequality as necessary. m4_case(m4_tolower(m4_substr($2,0,2)), [eq],[ test "x$A" = "x$B" && ax_compare_version=true ], [ne],[ test "x$A" != "x$B" && ax_compare_version=true ],[ AC_WARNING([illegal OP parameter: $2]) ]) ]) AS_VAR_POPDEF([A])dnl AS_VAR_POPDEF([B])dnl dnl # Execute ACTION-IF-TRUE / ACTION-IF-FALSE. if test "$ax_compare_version" = "true" ; then m4_ifvaln([$4],[$4],[:])dnl m4_ifvaln([$5],[else $5])dnl fi ]) dnl AX_COMPARE_VERSION libudis86-0+20221013/m4/ax_prog_sphinx_version.m4000066400000000000000000000032261457133061200212760ustar00rootroot00000000000000# SYNOPSIS # # AX_PROG_SPHINX_VERSION([VERSION],[ACTION-IF-TRUE],[ACTION-IF-FALSE]) # # DESCRIPTION # # Makes sure that sphinx-build supports the version indicated. If true # the shell commands in ACTION-IF-TRUE are executed. If not the shell # commands in ACTION-IF-FALSE are run. Note if $SPHINX_BUILD is not set # (for example by running AX_WITH_PROG) the macro will fail. # # Example: # # AX_WITH_PROG(SPHINX_BUILD,sphinx-build) # AX_PROG_SPHINX([1.1.1],[ ... ],[ ... ]) # # LICENSE # # ax_prog_python_version.m4 # # Copyright (c) 2009 Francesco Salvestrini # # Copying and distribution of this file, with or without modification, are # permitted in any medium without royalty provided the copyright notice # and this notice are preserved. This file is offered as-is, without any # warranty. # # ax_prog_sphinx_version.m4 # # Copyright (c) 2013 Vivek Thampi AC_DEFUN([AX_PROG_SPHINX],[ AC_REQUIRE([AC_PROG_SED]) AC_REQUIRE([AC_PROG_GREP]) AS_IF([test -n "$SPHINX_BUILD"],[ ax_sphinx_version="$1" AC_MSG_CHECKING([for sphinx version]) changequote(<<,>>) sphinx_version=`$SPHINX_BUILD -h 2>&1 | $GREP "^Sphinx v" | $SED -e 's/^.* v\([0-9]*\.[0-9]*\.[0-9]*\)/\1/'` changequote([,]) AC_MSG_RESULT($sphinx_version) AC_SUBST([SPHINX_VERSION],[$sphinx_version]) AX_COMPARE_VERSION([$ax_sphinx_version],[le],[$sphinx_version],[ : $2 ],[ : $3 ]) ],[ AC_MSG_WARN([could not find the sphinx documentation tool]) $3 ]) ]) libudis86-0+20221013/m4/ax_prog_yasm_version.m4000066400000000000000000000031141457133061200207320ustar00rootroot00000000000000# SYNOPSIS # # AX_PROG_YASM_VERSION([VERSION],[ACTION-IF-TRUE],[ACTION-IF-FALSE]) # # DESCRIPTION # # Makes sure that yasm supports the version indicated. If true # the shell commands in ACTION-IF-TRUE are executed. If not the shell # commands in ACTION-IF-FALSE are run. Note if $YASM is not set # (for example by running AX_WITH_PROG) the macro will fail. # # Example: # # AX_WITH_PROG(YASM,yasm) # AX_PROG_YASM_VERSION([1.1.1],[ ... ],[ ... ]) # # LICENSE # # ax_prog_python_version.m4 # # Copyright (c) 2009 Francesco Salvestrini # # Copying and distribution of this file, with or without modification, are # permitted in any medium without royalty provided the copyright notice # and this notice are preserved. This file is offered as-is, without any # warranty. # # ax_prog_yasm_version.m4 # # Copyright (c) 2013 Vivek Thampi AC_DEFUN([AX_PROG_YASM_VERSION],[ AC_REQUIRE([AC_PROG_SED]) AC_REQUIRE([AC_PROG_GREP]) AS_IF([test -n "$YASM"],[ ax_yasm_version="$1" AC_MSG_CHECKING([for yasm version]) changequote(<<,>>) yasm_version=`$YASM --version 2>&1 | $GREP "^yasm " | $SED -e 's/^.* \([0-9]*\.[0-9]*\.[0-9]*\)/\1/'` changequote([,]) AC_MSG_RESULT($yasm_version) AC_SUBST([YASM_VERSION],[$yasm_version]) AX_COMPARE_VERSION([$ax_yasm_version],[le],[$yasm_version],[ : $2 ],[ : $3 ]) ],[ AC_MSG_WARN([could not find the yasm]) $3 ]) ]) libudis86-0+20221013/m4/ax_with_prog.m4000066400000000000000000000046051457133061200171750ustar00rootroot00000000000000# =========================================================================== # http://www.nongnu.org/autoconf-archive/ax_with_prog.html # =========================================================================== # # SYNOPSIS # # AX_WITH_PROG([VARIABLE],[program],[VALUE-IF-NOT-FOUND],[PATH]) # # DESCRIPTION # # Locates an installed program binary, placing the result in the precious # variable VARIABLE. Accepts a present VARIABLE, then --with-program, and # failing that searches for program in the given path (which defaults to # the system path). If program is found, VARIABLE is set to the full path # of the binary; if it is not found VARIABLE is set to VALUE-IF-NOT-FOUND # if provided, unchanged otherwise. # # A typical example could be the following one: # # AX_WITH_PROG(PERL,perl) # # NOTE: This macro is based upon the original AX_WITH_PYTHON macro from # Dustin J. Mitchell . # # LICENSE # # Copyright (c) 2008 Francesco Salvestrini # Copyright (c) 2008 Dustin J. Mitchell # # Copying and distribution of this file, with or without modification, are # permitted in any medium without royalty provided the copyright notice # and this notice are preserved. AC_DEFUN([AX_WITH_PROG],[ AC_PREREQ([2.61]) pushdef([VARIABLE],$1) pushdef([EXECUTABLE],$2) pushdef([VALUE_IF_NOT_FOUND],$3) pushdef([PATH_PROG],$4) AC_ARG_VAR(VARIABLE,Absolute path to EXECUTABLE executable) AS_IF(test -z "$VARIABLE",[ AC_MSG_CHECKING(whether EXECUTABLE executable path has been provided) AC_ARG_WITH(EXECUTABLE,AS_HELP_STRING([--with-EXECUTABLE=[[[[PATH]]]]],absolute path to EXECUTABLE executable), [ AS_IF([test "$withval" != yes -a "$withval" != no],[ VARIABLE="$withval" AC_MSG_RESULT($VARIABLE) ],[ VARIABLE="" AC_MSG_RESULT([no]) AS_IF([test "$withval" != no], [ AC_PATH_PROG([]VARIABLE[],[]EXECUTABLE[],[]VALUE_IF_NOT_FOUND[],[]PATH_PROG[]) ]) ]) ],[ AC_MSG_RESULT([no]) AC_PATH_PROG([]VARIABLE[],[]EXECUTABLE[],[]VALUE_IF_NOT_FOUND[],[]PATH_PROG[]) ]) ]) popdef([PATH_PROG]) popdef([VALUE_IF_NOT_FOUND]) popdef([EXECUTABLE]) popdef([VARIABLE]) ]) libudis86-0+20221013/m4/ax_with_python.m4000066400000000000000000000021671457133061200175500ustar00rootroot00000000000000# =========================================================================== # http://www.nongnu.org/autoconf-archive/ax_with_python.html # =========================================================================== # # SYNOPSIS # # AX_WITH_PYTHON([VALUE-IF-NOT-FOUND],[PATH]) # # DESCRIPTION # # Locates an installed Python binary, placing the result in the precious # variable $PYTHON. Accepts a present $PYTHON, then --with-python, and # failing that searches for python in the given path (which defaults to # the system path). If python is found, $PYTHON is set to the full path of # the binary; if it is not found $PYTHON is set to VALUE-IF-NOT-FOUND if # provided, unchanged otherwise. # # A typical use could be the following one: # # AX_WITH_PYTHON # # LICENSE # # Copyright (c) 2008 Francesco Salvestrini # # Copying and distribution of this file, with or without modification, are # permitted in any medium without royalty provided the copyright notice # and this notice are preserved. AC_DEFUN([AX_WITH_PYTHON],[ AX_WITH_PROG(PYTHON,python,$1,$2) ]) libudis86-0+20221013/scripts/000077500000000000000000000000001457133061200154035ustar00rootroot00000000000000libudis86-0+20221013/scripts/Makefile.am000066400000000000000000000001771457133061200174440ustar00rootroot00000000000000EXTRA_DIST = \ ud_opcode.py \ ud_itab.py MAINTAINERCLEANFILES = Makefile.in clean-local: -rm -f *.pyc -rm -f ud_asmtest* libudis86-0+20221013/scripts/asmtest.sh000077500000000000000000000013551457133061200174260ustar00rootroot00000000000000#!/usr/bin/env bash objdump="otool -tV" yasm=yasm asmfile="ud_yasmtest.asm" binfile="ud_yasmtest.bin" Sfile="ud_yasmtest.S" objfile="ud_yasmtest.o" echo "[bits $1]" > $asmfile echo $2 >> $asmfile $yasm -f bin -o $binfile $asmfile if [ ! $? -eq 0 ]; then echo "error: failed to assemble" exit 1 fi echo "-- hexdump --------------------------------------" hexdump $binfile echo echo "-- objdump --------------------------------------" hexdump -e '1/1 ".byte 0x%02x\n"' $binfile > $Sfile gcc -c $Sfile -o $objfile $objdump -d $objfile echo echo "-- udcli (intel) ---------------------------------" ../udcli/udcli -$1 $binfile echo echo "-- udcli (at&t) ----------------------------------" ../udcli/udcli -$1 -att $binfile echo exit 0 libudis86-0+20221013/scripts/ud_itab.py000066400000000000000000000403421457133061200173670ustar00rootroot00000000000000# udis86 - scripts/ud_itab.py # # Copyright (c) 2009, 2013 Vivek Thampi # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os import sys from typing import TextIO, List from ud_opcode import UdOpcodeTable, UdOpcodeTables, UdInsnDef class UdItabGenerator: OperandDict = { "Av": ["OP_A", "SZ_V"], "B": ["OP_B", "SZ_DQ"], "BM": ["OP_BM", "SZ_DQ"], "BMqR": ["OP_BMR", "SZ_QO"], "BMdqR": ["OP_BMR", "SZ_DQO"], "E": ["OP_E", "SZ_NA"], "Eb": ["OP_E", "SZ_B"], "Ew": ["OP_E", "SZ_W"], "Ev": ["OP_E", "SZ_V"], "Ed": ["OP_E", "SZ_D"], "Ey": ["OP_E", "SZ_Y"], "Eq": ["OP_E", "SZ_Q"], "Ez": ["OP_E", "SZ_Z"], "Erdq": ["OP_E", "SZ_RDQ"], "Fv": ["OP_F", "SZ_V"], "G": ["OP_G", "SZ_NA"], "Gb": ["OP_G", "SZ_B"], "Gw": ["OP_G", "SZ_W"], "Gv": ["OP_G", "SZ_V"], "Gy": ["OP_G", "SZ_Y"], "Gd": ["OP_G", "SZ_D"], "Gq": ["OP_G", "SZ_Q"], "Gz": ["OP_G", "SZ_Z"], "M": ["OP_M", "SZ_NA"], "Mb": ["OP_M", "SZ_B"], "Mw": ["OP_M", "SZ_W"], "Ms": ["OP_M", "SZ_W"], "Md": ["OP_M", "SZ_D"], "Mq": ["OP_M", "SZ_Q"], "Mdq": ["OP_M", "SZ_DQ"], "Mqq": ["OP_M", "SZ_QQ"], "Mrdq": ["OP_M", "SZ_RDQ"], "Mv": ["OP_M", "SZ_V"], "Mx": ["OP_M", "SZ_X"], "Mt": ["OP_M", "SZ_T"], "Mo": ["OP_M", "SZ_O"], "MbRd": ["OP_MR", "SZ_BD"], "MbRv": ["OP_MR", "SZ_BV"], "MwRv": ["OP_MR", "SZ_WV"], "MwRd": ["OP_MR", "SZ_WD"], "MwRy": ["OP_MR", "SZ_WY"], "MdRy": ["OP_MR", "SZ_DY"], "Kb": ["OP_K", "SZ_B"], "Kw": ["OP_K", "SZ_W"], "Kd": ["OP_K", "SZ_D"], "Kq": ["OP_K", "SZ_Q"], "KMb": ["OP_KM", "SZ_B"], "KMw": ["OP_KM", "SZ_W"], "KMd": ["OP_KM", "SZ_D"], "KMq": ["OP_KM", "SZ_Q"], "KHb": ["OP_KH", "SZ_B"], "KHw": ["OP_KH", "SZ_W"], "KHd": ["OP_KH", "SZ_D"], "KHq": ["OP_KH", "SZ_Q"], "I1": ["OP_I1", "SZ_NA"], "I3": ["OP_I3", "SZ_NA"], "Ib": ["OP_I", "SZ_B"], "Id": ["OP_I", "SZ_D"], "Iw": ["OP_I", "SZ_W"], "Iv": ["OP_I", "SZ_V"], "Iz": ["OP_I", "SZ_Z"], "sIb": ["OP_sI", "SZ_B"], "sIz": ["OP_sI", "SZ_Z"], "sIv": ["OP_sI", "SZ_V"], "Jv": ["OP_J", "SZ_V"], "Jz": ["OP_J", "SZ_Z"], "Jb": ["OP_J", "SZ_B"], "R": ["OP_R", "SZ_RDQ"], "Rv": ["OP_R", "SZ_V"], "C": ["OP_C", "SZ_NA"], "D": ["OP_D", "SZ_NA"], "S": ["OP_S", "SZ_W"], "Ob": ["OP_O", "SZ_B"], "Ow": ["OP_O", "SZ_W"], "Ov": ["OP_O", "SZ_V"], "U": ["OP_U", "SZ_O"], "Ux": ["OP_U", "SZ_X"], "V": ["OP_V", "SZ_DQ"], "Vdq": ["OP_V", "SZ_DQ"], "Vqq": ["OP_V", "SZ_QQ"], "Vsd": ["OP_V", "SZ_Q"], "Vx": ["OP_V", "SZ_X"], "HRv": ["OP_HR", "SZ_V"], "HRd": ["OP_HR", "SZ_D"], "HRq": ["OP_HR", "SZ_Q"], "H": ["OP_H", "SZ_X"], "Hx": ["OP_H", "SZ_X"], "Hdq": ["OP_H", "SZ_DQ"], "Hqq": ["OP_H", "SZ_QQ"], "W": ["OP_W", "SZ_DQ"], "Wdq": ["OP_W", "SZ_DQ"], "Wqq": ["OP_W", "SZ_QQ"], "Wsd": ["OP_W", "SZ_Q"], "Wx": ["OP_W", "SZ_X"], "L": ["OP_L", "SZ_O"], "Lx": ["OP_L", "SZ_X"], "Ldq": ["OP_L", "SZ_DQ"], "Lqq": ["OP_L", "SZ_QQ"], "MbU": ["OP_MU", "SZ_BO"], "MwU": ["OP_MU", "SZ_WO"], "MdU": ["OP_MU", "SZ_DO"], "MqU": ["OP_MU", "SZ_QO"], "MdqU": ["OP_MU", "SZ_DQO"], "MqqU": ["OP_MU", "SZ_QQO"], "XSd": ["OP_XS", "SZ_D"], "XSq": ["OP_XS", "SZ_Q"], "XSXd": ["OP_XSX", "SZ_D"], "XSXq": ["OP_XSX", "SZ_Q"], "XSYd": ["OP_XSY", "SZ_D"], "XSYq": ["OP_XSY", "SZ_Q"], "N": ["OP_N", "SZ_Q"], "P": ["OP_P", "SZ_Q"], "Q": ["OP_Q", "SZ_Q"], "AL": ["OP_AL", "SZ_B"], "AX": ["OP_AX", "SZ_W"], "eAX": ["OP_eAX", "SZ_Z"], "rAX": ["OP_rAX", "SZ_V"], "CL": ["OP_CL", "SZ_B"], "CX": ["OP_CX", "SZ_W"], "eCX": ["OP_eCX", "SZ_Z"], "rCX": ["OP_rCX", "SZ_V"], "DL": ["OP_DL", "SZ_B"], "DX": ["OP_DX", "SZ_W"], "eDX": ["OP_eDX", "SZ_Z"], "rDX": ["OP_rDX", "SZ_V"], "R0b": ["OP_R0", "SZ_B"], "R1b": ["OP_R1", "SZ_B"], "R2b": ["OP_R2", "SZ_B"], "R3b": ["OP_R3", "SZ_B"], "R4b": ["OP_R4", "SZ_B"], "R5b": ["OP_R5", "SZ_B"], "R6b": ["OP_R6", "SZ_B"], "R7b": ["OP_R7", "SZ_B"], "R0w": ["OP_R0", "SZ_W"], "R1w": ["OP_R1", "SZ_W"], "R2w": ["OP_R2", "SZ_W"], "R3w": ["OP_R3", "SZ_W"], "R4w": ["OP_R4", "SZ_W"], "R5w": ["OP_R5", "SZ_W"], "R6w": ["OP_R6", "SZ_W"], "R7w": ["OP_R7", "SZ_W"], "R0v": ["OP_R0", "SZ_V"], "R1v": ["OP_R1", "SZ_V"], "R2v": ["OP_R2", "SZ_V"], "R3v": ["OP_R3", "SZ_V"], "R4v": ["OP_R4", "SZ_V"], "R5v": ["OP_R5", "SZ_V"], "R6v": ["OP_R6", "SZ_V"], "R7v": ["OP_R7", "SZ_V"], "R0z": ["OP_R0", "SZ_Z"], "R1z": ["OP_R1", "SZ_Z"], "R2z": ["OP_R2", "SZ_Z"], "R3z": ["OP_R3", "SZ_Z"], "R4z": ["OP_R4", "SZ_Z"], "R5z": ["OP_R5", "SZ_Z"], "R6z": ["OP_R6", "SZ_Z"], "R7z": ["OP_R7", "SZ_Z"], "R0y": ["OP_R0", "SZ_Y"], "R1y": ["OP_R1", "SZ_Y"], "R2y": ["OP_R2", "SZ_Y"], "R3y": ["OP_R3", "SZ_Y"], "R4y": ["OP_R4", "SZ_Y"], "R5y": ["OP_R5", "SZ_Y"], "R6y": ["OP_R6", "SZ_Y"], "R7y": ["OP_R7", "SZ_Y"], "ES": ["OP_ES", "SZ_NA"], "CS": ["OP_CS", "SZ_NA"], "DS": ["OP_DS", "SZ_NA"], "SS": ["OP_SS", "SZ_NA"], "GS": ["OP_GS", "SZ_NA"], "FS": ["OP_FS", "SZ_NA"], "ST0": ["OP_ST0", "SZ_NA"], "ST1": ["OP_ST1", "SZ_NA"], "ST2": ["OP_ST2", "SZ_NA"], "ST3": ["OP_ST3", "SZ_NA"], "ST4": ["OP_ST4", "SZ_NA"], "ST5": ["OP_ST5", "SZ_NA"], "ST6": ["OP_ST6", "SZ_NA"], "ST7": ["OP_ST7", "SZ_NA"], "IMP_XMM0": ["OP_IMP_XMM0", "SZ_NA"], "NONE": ["OP_NONE", "SZ_NA"], } AccessDict = { "N": "UD_ACCESS_NONE", "R": "UD_ACCESS_READ", "W": "UD_ACCESS_WRITE", "RW": "UD_ACCESS_READ|UD_ACCESS_WRITE", "WR": "UD_ACCESS_READ|UD_ACCESS_WRITE", } # opcode prefix dictionary PrefixDict = { "rep": "P_str", "repz": "P_strz", "aso": "P_aso", "oso": "P_oso", "rexw": "P_rexw", "rexb": "P_rexb", "rexx": "P_rexx", "rexr": "P_rexr", "vexl": "P_vexl", "vexw": "P_vexw", "seg": "P_seg", "inv64": "P_inv64", "def64": "P_def64", "cast": "P_cast", } MnemonicAliases = ("invalid", "3dnow", "none", "db", "pause") def __init__(self, tables: UdOpcodeTables): self.tables = tables self._insnIndexMap, i = {}, 0 for insn in tables.get_instructions(): self._insnIndexMap[insn], i = i, i + 1 self._tableIndexMap, i = {}, 0 for table in tables.get_tables(): self._tableIndexMap[table], i = i, i + 1 def get_insn_index(self, insn: UdInsnDef) -> int: return self._insnIndexMap[insn] def get_table_index(self, table: UdOpcodeTable) -> int: return self._tableIndexMap[table] def get_table_name(self, table: UdOpcodeTable) -> str: return f"ud_itab__{self.get_table_index(table)}" def gen_opcode_table(self, table: UdOpcodeTable, fh: TextIO, is_global: bool = False): """ Emit Opcode Table in C. """ fh.write("\n") if not is_global: fh.write('static ') fh.write(f"const uint16_t {self.get_table_name(table)}[] = {{\n") limit = 0 for i in range(table.size()): if i > 0 and i % 4 == 0: fh.write("\n") if i % 4 == 0: fh.write(f" /* {i:2x} */") e = table.get_entry(i) if e is None: fh.write(f"{'INVALID':>12},") limit += 1 elif isinstance(e, UdOpcodeTable): fh.write(f"{f'GROUP({self.get_table_index(e)})':>12},") limit += 1 elif isinstance(e, UdInsnDef): fh.write(f"{self.get_insn_index(e):>12},") limit += 1 table.set_limit(limit - 1) fh.write("\n") fh.write("};\n") def gen_opcode_tables(self, fh: TextIO): tables = self.tables.get_tables() for table in tables: self.gen_opcode_table(table, fh, table is self.tables.root) def gen_opcode_tables_lookup_index(self, fh: TextIO): fh.write("\n\n") fh.write("struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n") for table in self.tables.get_tables(): if table.limit() > 255: print(f"error: invalid table limit: {table.limit()} \n") fh.write(f' /* {self.get_table_index(table):03d} */ ' f'{{ {self.get_table_name(table)}, {table.label()}, "{table.meta()}", {table.limit()} }},\n') fh.write("};") def gen_insn_table(self, fh: TextIO): fh.write("struct ud_itab_entry ud_itab[] = {\n") for insn in self.tables.get_instructions(): opr_c = ["O_NONE", "O_NONE", "O_NONE", "O_NONE"] acc_c = ["UD_ACCESS_NONE", "UD_ACCESS_NONE", "UD_ACCESS_NONE", "UD_ACCESS_NONE"] pfx_c = [] opr = insn.operands for i in range(len(opr)): if not (opr[i] in self.OperandDict.keys()): print("error: invalid operand declaration: %s\n" % opr[i]) opr_c[i] = "O_" + opr[i] opr = f"{opr_c[0]}, {opr_c[1]}, {opr_c[2]}, {opr_c[3]}" op1_access = "UD_OP_ACCESS_READ" op2_access = "UD_OP_ACCESS_READ" if insn.firstOpAccess == "W": op1_access = "UD_OP_ACCESS_WRITE" elif insn.firstOpAccess == "RW": op1_access = "UD_OP_ACCESS_READ | UD_OP_ACCESS_WRITE" if insn.secondOpAccess == "W": op2_access = "UD_OP_ACCESS_WRITE" elif insn.secondOpAccess == "RW": op2_access = "UD_OP_ACCESS_READ | UD_OP_ACCESS_WRITE" acc = insn.access for i in range(len(acc)): if not (acc[i] in self.AccessDict.keys()): print("error: invalid operand declaration: %s\n" % acc[i]) acc_c[i] = self.AccessDict[acc[i]] acc = f"{acc_c[0]}, {acc_c[1]}, {acc_c[2]}, {acc_c[3]}" for p in insn.prefixes: if p not in self.PrefixDict.keys(): print(f"error: invalid prefix specification: {p} \n") pfx_c.append(self.PrefixDict[p]) if len(insn.prefixes) == 0: pfx_c.append("P_none") pfx = "|".join(pfx_c) flag_map = { '_': 'UD_FLAG_UNCHANGED', 'T': 'UD_FLAG_TESTED', 'M': 'UD_FLAG_MODIFIED', 'R': 'UD_FLAG_RESET', 'S': 'UD_FLAG_SET', 'U': 'UD_FLAG_UNDEFINED', 'P': 'UD_FLAG_PRIOR' } eflags = ", ".join(map(lambda f: flag_map[f], [flag for flag in insn.eflags])) implicit_uses = ", ".join(map(lambda r: "UD_R_" + r.upper(), insn.implicitRegUse)) implicit_defs = ", ".join(map(lambda r: "UD_R_" + r.upper(), insn.implicitRegDef)) if len(implicit_uses) > 0: implicit_uses += ", " if len(implicit_defs) > 0: implicit_defs += ", " implicit_uses += "UD_NONE" implicit_defs += "UD_NONE" fh.write(" /* %04d */ { UD_I%s, %s, %s, %s, %s, { {%s} }, {%s}, {%s}, %s },\n" % ( self.get_insn_index(insn), insn.mnemonic, opr, op1_access, op2_access, pfx, eflags, implicit_uses, implicit_defs, acc )) fh.write("};\n") def get_mnemonics(self) -> List[str]: mnemonics = self.tables.get_mnemonics() mnemonics.extend(self.MnemonicAliases) return mnemonics def gen_mnemonics_list(self, fh: TextIO): fh.write("\n\n") fh.write("const char* ud_mnemonics_str[] = {\n ") fh.write(",\n ".join([f'"{m}"' for m in self.get_mnemonics()])) fh.write("\n};\n") def generate_itab_header(self, file_path: str): with open(file_path, "w") as fh: # Generate Table Type Enumeration fh.write("#ifndef UD_ITAB_H\n") fh.write("#define UD_ITAB_H\n\n") fh.write("/* itab.h -- generated by udis86:scripts/ud_itab.py, do no edit */\n\n") # table type enumeration fh.write("/* ud_table_type -- lookup table types (see decode.c) */\n") fh.write("enum ud_table_type {\n ") enum = UdOpcodeTable.get_labels() fh.write(",\n ".join(enum)) fh.write("\n};\n\n") # mnemonic enumeration fh.write("/* ud_mnemonic -- mnemonic constants */\n") enum = "enum ud_mnemonic_code {\n " enum += ",\n ".join([f"UD_I{m}" for m in self.get_mnemonics()]) enum += ",\n UD_MAX_MNEMONIC_CODE" enum += "\n} UD_ATTR_PACKED;\n" fh.write(enum) fh.write("\n") fh.write("extern const char * ud_mnemonics_str[];\n") fh.write("\n#endif /* UD_ITAB_H */\n") def generate_itab_source(self, file_path: str): with open(file_path, "w") as fh: fh.write("/* itab.c -- generated by udis86:scripts/ud_itab.py, do no edit */\n") fh.write("#include \"decode.h\"\n\n") fh.write("#define GROUP(n) (0x8000 | (n))\n") fh.write(f"#define INVALID {self.get_insn_index(self.tables.invalidInsn)}\n\n") self.gen_opcode_tables(fh) self.gen_opcode_tables_lookup_index(fh) # Macros defining short-names for operands fh.write("\n\n/* itab entry operand definitions (for readability) */\n") for o in sorted(self.OperandDict.keys()): fh.write(f"#define O_{o:<7} {{ {self.OperandDict[o][0] + ',':<12} {self.OperandDict[o][1]:<8} }}\n") fh.write("\n") self.gen_insn_table(fh) self.gen_mnemonics_list(fh) def generate_itab_files(self, location: str): self.generate_itab_source(os.path.join(location, "itab.c")) self.generate_itab_header(os.path.join(location, "itab.h")) def usage(): print("usage: ud_itab.py ") def main(): if len(sys.argv) != 3: usage() sys.exit(1) tables = UdOpcodeTables(xml=sys.argv[1]) itab = UdItabGenerator(tables) itab.generate_itab_files(sys.argv[2]) if __name__ == '__main__': main() libudis86-0+20221013/scripts/ud_opcode.py000066400000000000000000000666511457133061200177340ustar00rootroot00000000000000# udis86 - scripts/ud_opcode.py # # Copyright (c) 2009, 2013 Vivek Thampi # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os import copy from typing import Optional, ItemsView, Union, List, Dict XMLInstruction = Dict[str, Union[List[str], str]] EMPTY_EFLAGS = "____________" class TypeCollisionError(Exception): """ Class to signal a type collision error between instructions """ pass class CollisionError(Exception): def __init__(self, obj1, obj2): self.obj1, self.obj2 = obj1, obj2 class UdInsnDef: """ An x86 instruction definition """ def __init__(self, **ins_data): self.mnemonic = ins_data['mnemonic'] self.eflags = ins_data['eflags'] if 'eflags' in ins_data else EMPTY_EFLAGS self.firstOpAccess = ins_data['firstOpAccess'] self.secondOpAccess = ins_data['secondOpAccess'] self.access = ins_data['access'] self.implicitRegUse = ins_data['implicitRegUse'] self.implicitRegDef = ins_data['implicitRegDef'] self.prefixes = ins_data['prefixes'] self.opcodes = ins_data['opcodes'] self.operands = ins_data['operands'] self._cpuid = ins_data['cpuid'] self._opcexts = {} for opc in self.opcodes: if opc.startswith('/'): e, v = opc.split('=') self._opcexts[e] = v def has_prefix(self, pfx: str) -> bool: return pfx in self.prefixes @property def vendor(self) -> Optional[str]: return self._opcexts.get('/vendor', None) @property def mode(self) -> Optional[str]: return self._opcexts.get('/m', None) @property def o_size(self) -> Optional[str]: return self._opcexts.get('/o', None) def is_def_64(self) -> bool: return self.has_prefix('def64') def __str__(self) -> str: return f"{self.mnemonic} {', '.join(self.operands)} {' '.join(self.opcodes)}" UdOpcodeTableEntry = Union[UdInsnDef, "UdOpcodeTable"] class UdOpcodeTable: """ A single table of instruction definitions, indexed by a decode field. """ @classmethod def vendor2idx(cls, vendor: str) -> int: return 0 if vendor == 'amd' else (1 if vendor == 'intel' else 2) @classmethod def vex2idx(cls, vex: str) -> int: if vex.startswith("none_"): vex = vex[5:] vex_opc_ext_map = { 'none': 0x0, '0f': 0x1, '0f38': 0x2, '0f3a': 0x3, '66': 0x4, '66_0f': 0x5, '66_0f38': 0x6, '66_0f3a': 0x7, 'f3': 0x8, 'f3_0f': 0x9, 'f3_0f38': 0xa, 'f3_0f3a': 0xb, 'f2': 0xc, 'f2_0f': 0xd, 'f2_0f38': 0xe, 'f2_0f3a': 0xf, # XOP (3 byte VEX encoding)... '08': 0x10, '66_08': 0x11, 'f3_08': 0x12, 'f2_08': 0x13, '09': 0x14, '66_09': 0x15, 'f3_09': 0x16, 'f2_09': 0x17, '0a': 0x18, '66_0a': 0x19, 'f3_0a': 0x1a, 'f2_0a': 0x1b, '10': 0, } return vex_opc_ext_map[vex] # A mapping of opcode extensions to their representational values used in the opcode map. OpcExtMap = { '/rm': lambda v: int(v, 16), '/x87': lambda v: int(v, 16), '/3dnow': lambda v: int(v, 16), '/reg': lambda v: int(v, 16), # modrm.mod # (!11, 11) => (00b, 01b) '/mod': lambda v: 0 if v == '!11' else 1, # Mode extensions: # (16, 32, 64) => (00, 01, 02) '/o': lambda v: int(int(v) / 32), '/a': lambda v: int(int(v) / 32), # Disassembly mode # (!64, 64) => (00b, 01b) '/m': lambda v: 1 if v == '64' else 0, # SSE # none => 0 # f2 => 1 # f3 => 2 # 66 => 3 '/sse': lambda v: (0 if v == 'none' else int(((int(v, 16) & 0xf) + 1) / 2)), # AVX '/vex': lambda v: UdOpcodeTable.vex2idx(v), '/vexw': lambda v: 0 if v == '0' else 1, '/vexl': lambda v: 0 if v == '0' else 1, # Vendor '/vendor': lambda v: UdOpcodeTable.vendor2idx(v) } _TableInfo = { 'opctbl': {'label': 'UD_TAB__OPC_TABLE', 'size': 256}, '/sse': {'label': 'UD_TAB__OPC_SSE', 'size': 4}, '/reg': {'label': 'UD_TAB__OPC_REG', 'size': 8}, '/rm': {'label': 'UD_TAB__OPC_RM', 'size': 8}, '/mod': {'label': 'UD_TAB__OPC_MOD', 'size': 2}, '/m': {'label': 'UD_TAB__OPC_MODE', 'size': 2}, '/x87': {'label': 'UD_TAB__OPC_X87', 'size': 64}, '/a': {'label': 'UD_TAB__OPC_ASIZE', 'size': 3}, '/o': {'label': 'UD_TAB__OPC_OSIZE', 'size': 3}, '/3dnow': {'label': 'UD_TAB__OPC_3DNOW', 'size': 256}, '/vendor': {'label': 'UD_TAB__OPC_VENDOR', 'size': 3}, '/vex': {'label': 'UD_TAB__OPC_VEX', 'size': 28}, '/vexw': {'label': 'UD_TAB__OPC_VEX_W', 'size': 2}, '/vexl': {'label': 'UD_TAB__OPC_VEX_L', 'size': 2}, } def __init__(self, typ: str): assert typ in self._TableInfo self._typ = typ self._limit = 0 self._entries = {} def size(self) -> int: return self._TableInfo[self._typ]['size'] def entries(self) -> ItemsView: return self._entries.items() def num_entries(self) -> int: return len(self._entries.keys()) def set_limit(self, new_limit: int): self._limit = new_limit def limit(self) -> int: return self._limit def label(self) -> str: return self._TableInfo[self._typ]['label'] def typ(self) -> str: return self._typ def meta(self) -> str: return self._typ def __str__(self): return f"table-{self._typ}" def add(self, opc: str, obj: UdOpcodeTableEntry): typ = self.get_type_for_opcode(opc) idx = self.get_idx_for_opcode(opc) if self._typ != typ or idx in self._entries: raise TypeCollisionError(f"{self._typ} <-> {typ} ({opc}) 2") self._entries[idx] = obj def lookup(self, opc: str) -> Optional[UdOpcodeTableEntry]: typ = self.get_type_for_opcode(opc) idx = self.get_idx_for_opcode(opc) if self._typ != typ: raise TypeCollisionError(f"{self._typ} <-> {typ} ({opc})") return self._entries.get(idx, None) def get_entry(self, index: int) -> Optional[UdOpcodeTableEntry]: """ Returns the entry at a given index of the table, None if there is none. Raises an exception if the index is out of bounds. """ if index < self.size(): return self._entries.get(index, None) raise IndexError(f"index out of bounds: {index}") def set_entry(self, index: int, entry: UdOpcodeTableEntry): if index < self.size(): self._entries[index] = entry else: raise IndexError(f"index out of bounds: {index} (current size is {self.size()}") @classmethod def get_type_for_opcode(cls, opc: str) -> str: if opc.startswith('/'): return opc.split('=')[0] return 'opctbl' @classmethod def get_idx_for_opcode(cls, opc: str) -> int: if opc.startswith('/'): typ, v = opc.split('=') return cls.OpcExtMap[typ](v) # plain opctbl opcode return int(opc, 16) @classmethod def get_labels(cls) -> List[str]: """Returns a list of all labels""" return [v['label'] for v in cls._TableInfo.values()] class UdOpcodeTables(object): """ Collection of opcode tables """ def add_table_for_type(self, typ: str) -> UdOpcodeTable: """ Create a new opcode table of a give type `typ`. """ tbl = UdOpcodeTable(typ) self._tables.append(tbl) return tbl def build_opcode_tree(self, opcodes: List[str], obj: UdOpcodeTableEntry) -> UdOpcodeTable: """ Recursively construct a tree entry mapping a string of opcodes to an object. """ if len(opcodes) == 0: return obj opc = opcodes[0] tbl = self.add_table_for_type(UdOpcodeTable.get_type_for_opcode(opc)) tbl.add(opc, self.build_opcode_tree(opcodes[1:], obj)) return tbl def walk(self, tbl: UdOpcodeTable, opcodes: List[str]) -> Optional[UdOpcodeTableEntry]: """ Walk down the opcode tree, starting at a given opcode table, given a string of opcodes. Return None if unable to walk, the object at the leaf otherwise. """ opc = opcodes[0] e = tbl.lookup(opc) if e is None: return None elif isinstance(e, UdOpcodeTable) and len(opcodes[1:]): return self.walk(e, opcodes[1:]) return e def map(self, tbl: UdOpcodeTable, opcodes: List[str], obj: UdOpcodeTableEntry): """ Create a mapping from a given string of opcodes to an object in the opcode tree. Constructs tree branches as needed. """ opc = opcodes[0] e = tbl.lookup(opc) if e is None: tbl.add(opc, self.build_opcode_tree(opcodes[1:], obj)) else: if len(opcodes[1:]) == 0: raise CollisionError(e, obj) self.map(e, opcodes[1:], obj) def __init__(self, xml: str): self._tables = [] self._insns = [] self._mnemonics = {} # The root table is always a 256 entry opctbl, indexed by a plain opcode byte self.root = self.add_table_for_type('opctbl') if os.getenv("UD_OPCODE_DEBUG"): self._logFh = open("opcodeTables.log", "w") # add an invalid instruction entry without any mapping in the opcode tables. self.invalidInsn = UdInsnDef( mnemonic="invalid", eflags=EMPTY_EFLAGS, firstOpAccess="", secondOpAccess="", access=[], implicitRegUse=[], implicitRegDef=[], opcodes=[], cpuid=[], operands=[], prefixes=[]) self._insns.append(self.invalidInsn) # Construct UdOpcodeTables object from the given udis86 optable.xml for insn in self.parse_xml_optable(xml): self.add_instruction(insn) self.patch_avx_2byte() self.merge_sse_none_entries() self.print_statistics() def log(self, s: str): if os.getenv("UD_OPCODE_DEBUG"): self._logFh.write(s + "\n") def merge_sse_none_entries(self): """ Merge sse tables with only one entry for /sse=none """ for table in self._tables: for k, e in table.entries(): if isinstance(e, UdOpcodeTable) and e.typ() == '/sse': if e.num_entries() == 1: sse = e.lookup("/sse=none") if sse: table.set_entry(k, sse) unique_tables = {} def gen_table_list(tbl: UdOpcodeTable): if tbl not in unique_tables: self._tables.append(tbl) unique_tables[tbl] = 1 for _, entry in tbl.entries(): if isinstance(entry, UdOpcodeTable): gen_table_list(entry) self._tables = [] gen_table_list(self.root) def patch_avx_2byte(self): # create avx tables for pp in (None, 'f2', 'f3', '66'): for m in (None, '0f', '0f38', '0f3a'): if pp is None and m is None: continue if pp is None: vex = m elif m is None: vex = pp else: vex = pp + '_' + m table = self.walk(self.root, ['c4', f'/vex={vex}']) self.map(self.root, ['c5', f'/vex={vex}'], table) def _add_instruction(self, **ins_data): # Canonicalize opcode list opcexts = ins_data['opcexts'] opcodes = list(ins_data['opcodes']) # Re-order vex if '/vex' in opcexts: assert opcodes[0] in ('c4', 'c5', '8f') opcodes.insert(1, '/vex=' + opcexts['/vex']) # Add extensions. The order is important, and determines how well the opcode table is packed. Also note, # /sse must be before /o, because /sse may consume operand size prefix affect the outcome of /o. for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', '/o', '/a', '/m', '/vexw', '/vexl', '/3dnow', '/vendor'): if ext in opcexts: opcodes.append(f"{ext}={opcexts[ext]}") insn = UdInsnDef( mnemonic=ins_data['mnemonic'], eflags=ins_data['eflags'], firstOpAccess=ins_data['firstOpAccess'], secondOpAccess=ins_data['secondOpAccess'], implicitRegUse=ins_data['implicitRegUse'], implicitRegDef=ins_data['implicitRegDef'], prefixes=ins_data['prefixes'], operands=ins_data['operands'], access=ins_data['access'], opcodes=opcodes, cpuid=ins_data['cpuid']) try: self.map(self.root, opcodes, insn) except CollisionError as e: self.pretty_print() print(opcodes, insn, str(e.obj1), str(e.obj2)) raise except Exception: self.pretty_print() raise self._insns.append(insn) # add to lookup by mnemonic structure if insn.mnemonic not in self._mnemonics: self._mnemonics[insn.mnemonic] = [insn] else: self._mnemonics[insn.mnemonic].append(insn) def _add_sse2_avx_instruction(self, **ins_data): """ Add an instruction definition containing an avx cpuid bit, but declared in its legacy SSE form. The function splits the definition to create two new definitions, one for SSE and one promoted to an AVX form. """ # SSE sse_mnemonic = ins_data['mnemonic'] sse_eflags = ins_data['eflags'] sse_first_op_access = ins_data['firstOpAccess'] sse_second_op_access = ins_data['secondOpAccess'] sse_implicit_reg_use = ins_data['implicitRegUse'] sse_implicit_reg_def = ins_data['implicitRegDef'] sse_opcodes = ins_data['opcodes'] # remove vex opcode extensions sse_opcexts = {e: v for (e, v) in ins_data['opcexts'].items() if not e.startswith('/vex')} # strip out avx operands, preserving relative ordering of remaining operands sse_operands = [opr for opr in ins_data['operands'] if opr not in ('H', 'L')] sse_access = [] for idx in range(len(sse_operands)): if idx+1 > len(ins_data['access']): break sse_access.append(ins_data['access'][idx]) # strip out avx prefixes sse_prefixes = [pfx for pfx in ins_data['prefixes'] if not pfx.startswith('vex')] # strip out avx bits from cpuid sse_cpuid = [flag for flag in ins_data['cpuid'] if not flag.startswith('avx')] self._add_instruction( mnemonic=sse_mnemonic, eflags=sse_eflags, firstOpAccess=sse_first_op_access, secondOpAccess=sse_second_op_access, implicitRegUse=sse_implicit_reg_use, implicitRegDef=sse_implicit_reg_def, prefixes=sse_prefixes, opcodes=sse_opcodes, opcexts=sse_opcexts, operands=sse_operands, access=sse_access, cpuid=sse_cpuid) # AVX vex_mnemonic = 'v' + ins_data['mnemonic'] vex_eflags = ins_data['eflags'] vex_first_op_access = ins_data['firstOpAccess'] vex_second_op_access = ins_data['secondOpAccess'] vex_implicit_reg_use = ins_data['implicitRegUse'] vex_implicit_reg_def = ins_data['implicitRegDef'] vex_prefixes = ins_data['prefixes'] vex_opcodes = ['c4'] vex_opcexts = {e: ins_data['opcexts'][e] for e in ins_data['opcexts'] if e != '/sse'} vex_opcexts['/vex'] = ins_data['opcexts']['/sse'] + '_' + '0f' if ins_data['opcodes'][1] in ('38', '3a'): vex_opcexts['/vex'] += ins_data['opcodes'][1] vex_opcodes.extend(ins_data['opcodes'][2:]) else: vex_opcodes.extend(ins_data['opcodes'][1:]) vex_operands = [] for o in ins_data['operands']: # make the operand size explicit: x if o in ('V', 'W', 'H', 'U', 'M'): o = o + 'x' vex_operands.append(o) vex_access = ins_data['access'] vex_cpuid = [flag for flag in ins_data['cpuid'] if not flag.startswith('sse')] self._add_instruction( mnemonic=vex_mnemonic, eflags=vex_eflags, firstOpAccess=vex_first_op_access, secondOpAccess=vex_second_op_access, implicitRegUse=vex_implicit_reg_use, implicitRegDef=vex_implicit_reg_def, prefixes=vex_prefixes, opcodes=vex_opcodes, opcexts=vex_opcexts, operands=vex_operands, access=vex_access, cpuid=vex_cpuid) def add_instruction(self, instruction: XMLInstruction): opcodes = [] opcexts = {} if not instruction['opcodes']: self._mnemonics[instruction['mnemonic']] = [UdInsnDef( mnemonic=instruction['mnemonic'], flags=instruction['eflags'], firstOpAccess=instruction['firstOpAccess'], secondOpAccess=instruction['secondOpAccess'], implicitRegUse=instruction['implicitRegUse'], implicitRegDef=instruction['implicitRegDef'], opcodes=[], cpuid=[], operands=[], access=[], prefixes=[] )] return # pack plain opcodes first, and collect opcode extensions for opc in instruction['opcodes']: if not opc.startswith('/'): opcodes.append(opc) else: e, v = opc.split('=') opcexts[e] = v # treat vendor as an opcode extension if len(instruction['vendor']): opcexts['/vendor'] = instruction['vendor'][0] if instruction['mnemonic'] in ('lds', 'les'): # Massage lds and les, which share the same prefix as AVX instructions, to work well with the opcode tree. opcexts['/vex'] = 'none' elif '/vex' in opcexts: # A proper avx instruction definition; make sure there are no legacy opcode extensions assert '/sse' not in opcodes # make sure the opcode definitions don't already include the avx prefixes. if len(opcodes) > 0: assert opcodes[0] not in ('c4', 'c5') # An avx only instruction is defined by the /vex= opcode extension. They do not include the c4 (long form) # or c5 (short form) prefix. As part of opcode table generate, here we create the long form definition, # and then patch the table for c5 in a later stage. # Construct a long-form definition of the avx instruction if 'xop' in instruction['cpuid']: opcodes.insert(0, '8f') else: opcodes.insert(0, 'c4') elif opcodes[0] == '0f' and opcodes[1] != '0f' and '/sse' not in opcexts: # Make all 2-byte opcode form instructions play nice with sse opcode maps. opcexts['/sse'] = 'none' # legacy sse defs that get promoted to avx fn = self._add_instruction if 'avx' in instruction['cpuid']: if '/sse' in opcexts: fn = self._add_sse2_avx_instruction else: avx_operands = [] for o in instruction['operands']: # make the operand size explicit: x if o in ('V', 'W', 'H', 'U', 'M'): o = o + 'x' avx_operands.append(o) instruction['operands'] = avx_operands fn(mnemonic=instruction['mnemonic'], eflags=instruction['eflags'], firstOpAccess=instruction['firstOpAccess'], secondOpAccess=instruction['secondOpAccess'], implicitRegUse=instruction['implicitRegUse'], implicitRegDef=instruction['implicitRegDef'], prefixes=instruction['prefixes'], opcodes=opcodes, opcexts=opcexts, operands=instruction['operands'], access=instruction['access'], cpuid=instruction['cpuid']) def get_instructions(self) -> List[UdInsnDef]: """Returns a list of all instructions in the collection""" return self._insns def get_tables(self) -> List[UdOpcodeTable]: """Returns a list of all tables in the collection""" return self._tables def get_mnemonics(self) -> List[str]: """Returns a sorted list of mnemonics""" return sorted(self._mnemonics.keys()) def pretty_print(self): def print_walk(tbl, indent=""): for k, e in tbl.entries(): if isinstance(e, UdOpcodeTable): self.log("%s |-<%02x> %s" % (indent, k, e)) print_walk(e, indent + " |") elif isinstance(e, UdInsnDef): self.log("%s |-<%02x> %s" % (indent, k, e)) print_walk(self.root) def print_statistics(self): tables = self.get_tables() self.log("stats: ") self.log(f" Num tables = {len(tables)}") self.log(f" Num insnDefs = {len(self.get_instructions())}") self.log(f" Num insns = {len(self.get_mnemonics())}") total_size = 0 total_entries = 0 for table in tables: total_size += table.size() total_entries += table.num_entries() self.log(f" Packing Ratio = {(total_entries * 100) / total_size}%") self.log("--------------------") self.pretty_print() @staticmethod def parse_xml_optable(xml: str) -> List[XMLInstruction]: """ Parse udis86 optable.xml file and return list of instruction definitions. """ from xml.dom import minidom xml_doc = minidom.parse(xml) tl_node = xml_doc.firstChild insns = [] while tl_node and tl_node.localName != "x86optable": tl_node = tl_node.nextSibling for insn_node in tl_node.childNodes: if not insn_node.localName: continue if insn_node.localName != "instruction": raise Exception(f"warning: invalid insn node - {insn_node.localName}") mnemonic = insn_node.getElementsByTagName('mnemonic')[0].firstChild.data vendor = '' cpuid = [] global_eflags = EMPTY_EFLAGS global_first_op_access = "R" global_second_op_access = "R" global_implicit_reg_use = [] global_implicit_reg_def = [] for node in insn_node.childNodes: if node.localName == 'vendor': vendor = node.firstChild.data.split() elif node.localName == 'cpuid': cpuid = node.firstChild.data.split() elif node.localName == 'eflags': global_eflags = node.firstChild.data elif node.localName == 'first_operand_access': global_first_op_access = node.firstChild.data elif node.localName == 'second_operand_access': global_second_op_access = node.firstChild.data elif node.localName == 'implicit_register_use': global_implicit_reg_use.append(node.firstChild.data) elif node.localName == 'implicit_register_def': global_implicit_reg_def.append(node.firstChild.data) for node in insn_node.childNodes: if node.localName == 'def': eflags = copy.deepcopy(global_eflags) first_op_access = copy.deepcopy(global_first_op_access) second_op_access = copy.deepcopy(global_second_op_access) implicit_reg_use = copy.deepcopy(global_implicit_reg_use) implicit_reg_def = copy.deepcopy(global_implicit_reg_def) insn_def = {'pfx': []} for child_node in node.childNodes: if not child_node.localName: continue if child_node.localName in ('pfx', 'opc', 'opr', 'access', 'vendor', 'cpuid'): insn_def[child_node.localName] = child_node.firstChild.data.split() elif child_node.localName == 'eflags': eflags = child_node.firstChild.data elif child_node.localName == 'first_operand_access': first_op_access = child_node.firstChild.data elif child_node.localName == 'second_operand_access': second_op_access = child_node.firstChild.data elif child_node.localName == 'implicit_register_use': implicit_reg_use.append(child_node.firstChild.data) elif child_node.localName == 'implicit_register_def': implicit_reg_def.append(child_node.firstChild.data) elif child_node.localName == 'mode': insn_def['pfx'].extend(child_node.firstChild.data.split()) insns.append({ 'prefixes': insn_def.get('pfx', []), 'mnemonic': mnemonic, 'eflags': eflags, 'firstOpAccess': first_op_access, 'secondOpAccess': second_op_access, 'implicitRegUse': implicit_reg_use, 'implicitRegDef': implicit_reg_def, 'opcodes': insn_def.get('opc', []), 'operands': insn_def.get('opr', []), 'vendor': insn_def.get('vendor', vendor), 'access': insn_def.get('access', []), 'cpuid': insn_def.get('cpuid', cpuid) }) return insns libudis86-0+20221013/tests/000077500000000000000000000000001457133061200150565ustar00rootroot00000000000000libudis86-0+20221013/tests/Makefile.am000066400000000000000000000037431457133061200171210ustar00rootroot00000000000000# # Automake definitions for udis86 tests # check_PROGRAMS = \ symresolve \ libcheck symresolve_SOURCES = symresolve.c symresolve_LDADD = $(top_builddir)/libudis86/libudis86.la symresolve_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir) libcheck_SOURCES = libcheck.c libcheck_LDADD = $(top_builddir)/libudis86/libudis86.la libcheck_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir) MAINTAINERCLEANFILES = Makefile.in DISTCLEANFILES = difftest.sh YASM = @YASM@ PYTHON = @PYTHON@ TESTDIS = $(top_builddir)/udcli/udcli EXTRA_DIST = \ $(srcdir)/asm \ $(srcdir)/oprgen.py \ $(srcdir)/symresolve.ref \ $(srcdir)/installcheck.c \ $(srcdir)/libcheck.c if HAVE_YASM tests: difftest test-sym-resolver test-libcheck else tests: warn_no_yasm test-sym-resolver test-libcheck endif SEED = 1984 .PHONY: test-sym-resolver test-sym-resolver: symresolve @$(top_builddir)/tests/$< > $@.out @diff -w $(srcdir)/symresolve.ref $@.out && echo "$@: passed." .PHONY: test-libcheck test-libcheck: libcheck @./libcheck && echo "$@: passed" # # generate operand tests # oprtest_generate = \ outdir=$(builddir)/_results/asm/$(1) && \ mkdir -p $${outdir} && \ PYTHONPATH=$(top_srcdir)/scripts $(PYTHON) $(top_srcdir)/tests/oprgen.py \ $(top_srcdir)/docs/x86/optable.xml $(SEED) $(1) >$${outdir}/oprtest.asm .PHONY: oprtest oprtest: oprgen.py @echo "Generating operand tests." @$(call oprtest_generate,64) @$(call oprtest_generate,32) @$(call oprtest_generate,16) .PHONY: difftest difftest: oprtest $(builddir)/difftest.sh @bash $(builddir)/difftest.sh .PHONY: difftest-refup difftest-refup: $(builddir)/difftest.sh @bash $(builddir)/difftest.sh refup .PHONY: warn_no_yasm warn_no_yasm: @echo "*** YASM NOT FOUND: Poor Test Coverage ***" check-local: tests installcheck-local: @$(CC) $(srcdir)/installcheck.c -o installcheck.bin -I$(includedir) -L$(libdir) -ludis86 @echo "$@: passed" clean-local: rm -f $(builddir)/*.bin $(builddir)/*.out $(builddir)/*.pyc rm -rf $(builddir)/_results libudis86-0+20221013/tests/asm/000077500000000000000000000000001457133061200156365ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/16/000077500000000000000000000000001457133061200160645ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/16/disp.asm000066400000000000000000000002051457133061200175220ustar00rootroot00000000000000[bits 16] mov ax, [eax-0x10] add bx, [esi+0x10] add ax, [0xffff] add ax, [esi+edi*4-0x10] add ax, [bx+si-0x4877] libudis86-0+20221013/tests/asm/16/test16.asm000066400000000000000000000001371457133061200177150ustar00rootroot00000000000000[bits 16] movzx eax, word [bx] iretd dpps xmm2, xmm1, 0x10 blendvpd xmm1, xmm2 libudis86-0+20221013/tests/asm/32/000077500000000000000000000000001457133061200160625ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/32/att.asm000066400000000000000000000000641457133061200173540ustar00rootroot00000000000000[bits 32] mov eax, 0x1234 mov eax, [0x1234] libudis86-0+20221013/tests/asm/32/att.asm.Sref000066400000000000000000000001661457133061200202550ustar00rootroot000000000000000000000000000000 b834120000 mov $0x1234, %eax 0000000000000005 a134120000 mov 0x1234, %eax libudis86-0+20221013/tests/asm/32/att.asm.ref000066400000000000000000000001661457133061200201320ustar00rootroot000000000000000000000000000000 b834120000 mov eax, 0x1234 0000000000000005 a134120000 mov eax, [0x1234] libudis86-0+20221013/tests/asm/32/avx.asm000066400000000000000000000007761457133061200173740ustar00rootroot00000000000000[bits 32] vaddsd xmm1, xmm2, xmm4 vaddsd xmm2, xmm3, [eax] vaddps ymm1, ymm2, ymm3 vaddps ymm1, ymm7, [eax] vblendpd ymm1, ymm7, ymm4, 0x42 vcvtpd2ps xmm1, xmm2 vcvtpd2ps xmm1, ymm3 vcvtpd2ps xmm1, oword [eax] vcvtpd2ps xmm1, yword [eax] vcvtpd2dq xmm1, xmm2 vcvtpd2dq xmm1, ymm3 vcvtpd2dq xmm1, oword [eax] vcvtpd2dq xmm1, yword [eax] vcvttpd2dq xmm1, xmm2 vcvttpd2dq xmm1, ymm3 vcvttpd2dq xmm1, oword [eax] vcvttpd2dq xmm1, yword [eax] libudis86-0+20221013/tests/asm/32/avx.asm.Sref000066400000000000000000000020001457133061200202500ustar00rootroot000000000000000000000000000000 c5eb58cc vaddsd %xmm4, %xmm2, %xmm1 0000000000000004 c5e35810 vaddsd (%eax), %xmm3, %xmm2 0000000000000008 c5ec58cb vaddps %ymm3, %ymm2, %ymm1 000000000000000c c5c45808 vaddps (%eax), %ymm7, %ymm1 0000000000000010 c4e3450dcc42 vblendpd $0x42, %ymm4, %ymm7, %ymm1 0000000000000016 c5f95aca vcvtpd2ps %xmm2, %xmm1 000000000000001a c5fd5acb vcvtpd2ps %ymm3, %xmm1 000000000000001e c5f95a08 vcvtpd2ps (%eax), %xmm1 0000000000000022 c5fd5a08 vcvtpd2ps (%eax), %xmm1 0000000000000026 c5fbe6ca vcvtpd2dq %xmm2, %xmm1 000000000000002a c5ffe6cb vcvtpd2dq %ymm3, %xmm1 000000000000002e c5fbe608 vcvtpd2dq (%eax), %xmm1 0000000000000032 c5ffe608 vcvtpd2dq (%eax), %xmm1 0000000000000036 c5f9e6ca vcvttpd2dq %xmm2, %xmm1 000000000000003a c5fde6cb vcvttpd2dq %ymm3, %xmm1 000000000000003e c5f9e608 vcvttpd2dq (%eax), %xmm1 0000000000000042 c5fde608 vcvttpd2dq (%eax), %xmm1 libudis86-0+20221013/tests/asm/32/avx.asm.ref000066400000000000000000000017741457133061200201460ustar00rootroot000000000000000000000000000000 c5eb58cc vaddsd xmm1, xmm2, xmm4 0000000000000004 c5e35810 vaddsd xmm2, xmm3, [eax] 0000000000000008 c5ec58cb vaddps ymm1, ymm2, ymm3 000000000000000c c5c45808 vaddps ymm1, ymm7, [eax] 0000000000000010 c4e3450dcc42 vblendpd ymm1, ymm7, ymm4, 0x42 0000000000000016 c5f95aca vcvtpd2ps xmm1, xmm2 000000000000001a c5fd5acb vcvtpd2ps xmm1, ymm3 000000000000001e c5f95a08 vcvtpd2ps xmm1, [eax] 0000000000000022 c5fd5a08 vcvtpd2ps xmm1, yword [eax] 0000000000000026 c5fbe6ca vcvtpd2dq xmm1, xmm2 000000000000002a c5ffe6cb vcvtpd2dq xmm1, ymm3 000000000000002e c5fbe608 vcvtpd2dq xmm1, [eax] 0000000000000032 c5ffe608 vcvtpd2dq xmm1, yword [eax] 0000000000000036 c5f9e6ca vcvttpd2dq xmm1, xmm2 000000000000003a c5fde6cb vcvttpd2dq xmm1, ymm3 000000000000003e c5f9e608 vcvttpd2dq xmm1, [eax] 0000000000000042 c5fde608 vcvttpd2dq xmm1, yword [eax] libudis86-0+20221013/tests/asm/32/corner.asm000066400000000000000000000000621457133061200200520ustar00rootroot00000000000000[bits 32] lar eax, [bx+si] nop pause libudis86-0+20221013/tests/asm/32/corner.asm.ref000066400000000000000000000002611457133061200206260ustar00rootroot000000000000000000000000000000 670f0200 lar eax, word [bx+si] 0000000000000004 90 nop 0000000000000005 f390 pause libudis86-0+20221013/tests/asm/32/disp.asm000066400000000000000000000002101457133061200175140ustar00rootroot00000000000000[bits 32] mov eax, [eax-0x10] add eax, [esi+0x10] add eax, [0x10] add eax, [esi+edi*4+0x10] add eax, [bx+si-0x4877] libudis86-0+20221013/tests/asm/32/disp.asm.Sref000066400000000000000000000004541457133061200204240ustar00rootroot000000000000000000000000000000 8b40f0 mov -0x10(%eax), %eax 0000000000000003 034610 add 0x10(%esi), %eax 0000000000000006 030510000000 add 0x10, %eax 000000000000000c 0344be10 add 0x10(%esi,%edi,4), %eax 0000000000000010 67038089b7 add -0x4877(%bx,%si), %eax libudis86-0+20221013/tests/asm/32/invalid_seg.asm000066400000000000000000000000341457133061200210450ustar00rootroot00000000000000[bits 32] db 0x8C, 0x38 libudis86-0+20221013/tests/asm/32/invalid_seg.asm.ref000066400000000000000000000000731457133061200216230ustar00rootroot000000000000000000000000000000 8c38 invalid libudis86-0+20221013/tests/asm/32/obscure.asm000066400000000000000000000005011457133061200202220ustar00rootroot00000000000000 db 0xd1, 0xf6 ; shl Ev, 0x1 db 0xd0, 0xf6 ; shl Eb, 0x1 db 0xd9, 0xd9 ; fstp1 st1 db 0xdc, 0xd0 ; fcom2 db 0xdc, 0xd8 ; fcomp3 db 0xdd, 0xc8 ; fxch4 db 0xde, 0xd1 ; fcomp5 db 0xdf, 0xc3 ; fxch7 db 0xdf, 0xd0 ; fstp8 db 0xdf, 0xd8 ; fstp9 db 0x83, 0xe2, 0xdf ; and edx, 0xffffffdf (sign-extension) libudis86-0+20221013/tests/asm/32/obscure.asm.ref000066400000000000000000000012111457133061200207740ustar00rootroot000000000000000000000000000000 d1f6 shl esi, 1 0000000000000002 d0f6 shl dh, 1 0000000000000004 d9d9 fstp1 st1 0000000000000006 dcd0 fcom2 st0 0000000000000008 dcd8 fcomp3 st0 000000000000000a ddc8 fxch4 st0 000000000000000c ded1 fcomp5 st1 000000000000000e dfc3 ffreep st3 0000000000000010 dfd0 fstp8 st0 0000000000000012 dfd8 fstp9 st0 0000000000000014 83e2df and edx, 0xffffffdf libudis86-0+20221013/tests/asm/32/reljmp.asm000066400000000000000000000003051457133061200200530ustar00rootroot00000000000000[bits 32] [org 0x80000000] l1: nop nop nop nop nop jmp l1 nop jmp word l2 nop nop jmp dword l2 nop nop nop l2: nop nop jmp l1 libudis86-0+20221013/tests/asm/32/reljmp.asm.ref000066400000000000000000000017531457133061200206360ustar00rootroot000000000000000000000080000000 90 nop 0000000080000001 90 nop 0000000080000002 90 nop 0000000080000003 90 nop 0000000080000004 90 nop 0000000080000005 ebf9 jmp 0x80000000 0000000080000007 90 nop 0000000080000008 66e90a00 jmp 0x16 000000008000000c 90 nop 000000008000000d 90 nop 000000008000000e e903000000 jmp 0x80000016 0000000080000013 90 nop 0000000080000014 90 nop 0000000080000015 90 nop 0000000080000016 90 nop 0000000080000017 90 nop 0000000080000018 ebe6 jmp 0x80000000 libudis86-0+20221013/tests/asm/32/sext.asm000066400000000000000000000006201457133061200175450ustar00rootroot00000000000000[bits 32] ;; test sign extension adc ax, -100 and edx, -3 or dx, -1000 or dx, -1 add edx, -1000 imul dx, bx, -100 imul edx, ebx, -1 imul edx, ebx, -128 imul edx, ebx, -129 imul ax, bx, -129 sub dword [eax], -1 sub word [eax], -2000 test eax, 1 test eax, -1 push byte -1 push word -1 push dword -1000 push word -1000 libudis86-0+20221013/tests/asm/32/sext.asm.ref000066400000000000000000000020541457133061200203230ustar00rootroot000000000000000000000000000000 6683d09c adc ax, 0xff9c 0000000000000004 83e2fd and edx, 0xfffffffd 0000000000000007 6681ca18fc or dx, 0xfc18 000000000000000c 6683caff or dx, 0xffff 0000000000000010 81c218fcffff add edx, 0xfffffc18 0000000000000016 666bd39c imul dx, bx, 0xff9c 000000000000001a 6bd3ff imul edx, ebx, 0xffffffff 000000000000001d 6bd380 imul edx, ebx, 0xffffff80 0000000000000020 69d37fffffff imul edx, ebx, 0xffffff7f 0000000000000026 6669c37fff imul ax, bx, 0xff7f 000000000000002b 8328ff sub dword [eax], 0xffffffff 000000000000002e 66812830f8 sub word [eax], 0xf830 0000000000000033 a901000000 test eax, 0x1 0000000000000038 a9ffffffff test eax, 0xffffffff 000000000000003d 6aff push 0xffffffff 000000000000003f 666aff push 0xffff 0000000000000042 6818fcffff push 0xfffffc18 0000000000000047 666818fc push 0xfc18 libudis86-0+20221013/tests/asm/32/test32.asm000066400000000000000000000122141457133061200177100ustar00rootroot00000000000000[bits 32] mov [0x1000], bx mov [0x10], ax mov ax, [0x10] mov byte [bx+si], 0x10 mov byte [bx+si+0x10], 0x10 mov word [bp+0x10], 0x10 mov word [bp+di+0x10], 0x10 mov dword [si+0x10], 0x10 mov word [di+0x10], 0x10 mov dword [bx+0x10], 0x1000 mov word [bx+0x1000], 0x1000 mov dword [ebx+ecx*4], 0x100 mov [eax+eax*2], eax mov [edx+esi*8], ebp mov dword [ecx*4+0x490], 0x100 mov byte [cs:0x100000], 0x10 mov word [eax+0x10], 0x10 mov [eax+0x10], ax mov [eax+0x1000], ebx mov [ebp+eax+0x20], esi mov [ebp+edi+0x100000], esp mov byte [esp], 0x10 add al, 0x10 add eax, ebx push es pop es adc eax, 0x10000 and [eax], al daa inc ax inc edx push eax push ax pushad bound eax, [eax] bound ax, [ecx] bsr ax, ax bsf eax, [bx+si] bswap eax bt [eax], ax btr ax, 0x10 btc ebx, 0x10 bts word [ebx], 0x10 call ax call word [bx+si] call eax call dword [eax+ecx] call word 0x10:0x100 call dword 0x10:0x10000 call far word [eax] call far dword [bp+si] cbw cwd clc cld clflush [eax] cmp eax, ebx cmp ecx, [bx] cmpsb cmpsw cmpsd cmpxchg [eax], ax cmpxchg8b [ebx] cpuid das inc eax inc word [ecx] dec byte [si] in al, 0x10 in ax, 0x10 in eax, 0x10 insb insw insd int 0x10 into lahf lds ax, [eax] les eax, [ebx] lea ax, [eax] lea eax, [bx+si] leave lodsb lodsw lodsd test al, bl test [eax], bl test [eax], ebx test [eax], bx ret ret 0x10 aad 0x10 aam 0x10 salc hlt cmc lock xchg ebx, eax repne mov eax, ebx repe mov eax, 0x10 push cs outsd outsw mov ax, es mov bx, ds mov [eax], es mov [ebx+ecx], cs mov cs, [ebx+ecx] wait pushfw pushfd lodsw lodsd retf 0x10 int3 into iretw iretd lsl ax, [bx] syscall clts sysret movups xmm0, xmm1 mov dr0, eax ror word [ebx], cl wrmsr rdmsr rdtsc rdtscp rdpmc sysenter sysexit cmovo eax, [eax] cmovno eax, [bx] cmovb eax, [eax] cmovae eax, [bx] cmovo eax, [eax] cmovz eax, ebx cmovnz eax, [eax] cmovbe eax, [bx] cmova eax, [bx] movmskps eax, xmm0 movmskpd eax, xmm0 sqrtps xmm1, xmm0 rsqrtps xmm1, xmm0 rcpps xmm1, xmm0 andps xmm1, xmm0 orps xmm1, xmm0 xorps xmm1, xmm0 andnps xmm1, xmm0 sqrtss xmm1, xmm0 rsqrtss xmm1, xmm0 rcpss xmm1, xmm0 sqrtpd xmm1, xmm0 andpd xmm1, xmm0 andnpd xmm1, xmm0 orpd xmm1, xmm0 xorpd xmm1, xmm0 sqrtsd xmm1, xmm0 punpcklbw mm0, [eax] punpcklwd mm0, mm1 punpckldq mm0, mm1 packsswb mm0, mm1 packsswb mm0, mm1 pcmpgtb mm0, mm1 pcmpgtw mm0, mm1 pcmpgtd mm0, mm1 packuswb mm0, mm1 punpcklbw xmm0, [eax] punpcklwd xmm0, xmm1 punpckldq xmm0, xmm1 packsswb xmm0, xmm1 packsswb xmm0, xmm1 pcmpgtb xmm0, xmm1 pcmpgtw xmm0, xmm1 pcmpgtd xmm0, xmm1 packuswb xmm0, xmm1 pshufw mm0, mm1, 0x10 pcmpeqb mm0, mm1 pcmpeqw mm0, mm1 pcmpeqd mm0, mm1 pcmpeqb xmm0, xmm1 pcmpeqw xmm0, xmm1 pcmpeqd xmm0, xmm1 emms pshufhw xmm0, xmm1, 0x10 pshufd xmm0, xmm1, 0x10 pshuflw xmm0, xmm1, 0x10 seto byte [eax] setno byte [bx] setz byte [es:eax+ecx*2+0x100] push fs pop fs cpuid bt [eax], eax shld eax, ebx, 0x10 shld [eax], bx, cl cmpxchg [eax], eax lss eax, [eax] btr [eax], eax movnti [eax], eax psrlw mm0, 0x10 fadd dword [eax] imul eax, [eax], 0xf6 movd dword [eax], xmm0 movzx eax, word [eax] push word [0x10] insw insd fnstsw ax fucomip st0, st1 fcomip st0, st7 fucomp st4 fucom st5 fstp st3 fst st1 ffree st0 fdiv st7, st0 fdivr st2, st0 fsub st4, st0 fsubr st6, st0 fmul st0, st0 fadd st5, st0 ficom word [eax] fidivr word [eax] fimul word [ebx] fisub word [ecx] fld qword [bx+si] fisttp qword [edx+0x100] fnstsw word [eax] frstor [ebx] prefetch [bx+si] psrlq xmm0, 0x10 psrldq xmm0, 0x10 movsldup xmm0, [eax] add [0xffffffff], eax cvtsi2ss xmm1, dword [eax] pop dword [eax] out 0x0, al lldt word [0x100] lgdt [0x221] sldt word [0x233] sgdt [0x443] lidt [eax+0x333] lldt ax ltr bx verr cx verw dx sldt ax str bx str eax and esp, 0xfc psrlw xmm1, 0x10 psraw xmm7, 0x1 psllw xmm2, 0x23 fldenv [0x10] fldenv [0x123] fldcw word [0x100] fnstcw word [0x10] ficom word [eax+ebx+0x10] fstp tword [0x10] fadd qword [eax+ebx*2+0x1] frstor [0x100] fnstsw word [0x100] fiadd word [0x100] fild word [0x10] monitor mwait lfence mfence sfence vmrun vmmcall vmload vmsave stgi clgi skinit invlpga blendpd xmm1, xmm6, 0x8 psignw xmm4, [eax] blendpd xmm1, [eax], 0x9 libudis86-0+20221013/tests/asm/64/000077500000000000000000000000001457133061200160675ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/64/amd/000077500000000000000000000000001457133061200166305ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/64/amd/invalid.asm000066400000000000000000000002661457133061200207640ustar00rootroot00000000000000;; Test amd specific 64bit instructions [bits 64] ;; Invalid instructions in amd 64bit mode db 0x0f, 0x34 ; sysenter (invalid) db 0x0f, 0x35 ; sysexit (invalid) libudis86-0+20221013/tests/asm/64/amd/invalid.asm.ref000066400000000000000000000001661457133061200215360ustar00rootroot000000000000000000000000000000 0f34 invalid 0000000000000002 0f35 invalid libudis86-0+20221013/tests/asm/64/avx.asm000066400000000000000000000002161457133061200173660ustar00rootroot00000000000000[bits 64] vaddsd xmm12, xmm4, xmm1 vminsd xmm13, xmm15, qword [rbx+r8-0x10] vaddps ymm8, ymm3, ymm14 vaddps ymm8, ymm3, [rax] libudis86-0+20221013/tests/asm/64/avx.asm.ref000066400000000000000000000003741457133061200201460ustar00rootroot000000000000000000000000000000 c55b58e1 vaddsd xmm12, xmm4, xmm1 0000000000000004 c421035d6c03f0 vminsd xmm13, xmm15, qword [rbx+r8-0x10] 000000000000000b c4416458c6 vaddps ymm8, ymm3, ymm14 0000000000000010 c5645800 vaddps ymm8, ymm3, [rax] libudis86-0+20221013/tests/asm/64/branch.asm000066400000000000000000000004111457133061200200220ustar00rootroot00000000000000;; Test branching instructions ;; [bits 64] jnz near x jo near x jno word x jc near x jnc word x jae dword x jcxz x jecxz x jrcxz x jmp dword near x call dword near x jmp word x jmp dword x jmp word [eax] x: jmp qword [rax] jmp word x jmp dword x libudis86-0+20221013/tests/asm/64/branch.asm.ref000066400000000000000000000017531457133061200206070ustar00rootroot000000000000000000000000000000 0f853b000000 jnz 0x41 0000000000000006 0f8035000000 jo 0x41 000000000000000c 660f813000 jno 0x41 0000000000000011 0f822a000000 jb 0x41 0000000000000017 660f832500 jae 0x41 000000000000001c 0f831f000000 jae 0x41 0000000000000022 67e31c jecxz 0x41 0000000000000025 67e319 jecxz 0x41 0000000000000028 e317 jrcxz 0x41 000000000000002a e912000000 jmp 0x41 000000000000002f e80d000000 call 0x41 0000000000000034 66e90900 jmp 0x41 0000000000000038 e904000000 jmp 0x41 000000000000003d 6766ff20 jmp word [eax] 0000000000000041 ff20 jmp qword [rax] 0000000000000043 66e9faff jmp 0x41 0000000000000047 e9f5ffffff jmp 0x41 libudis86-0+20221013/tests/asm/64/disp.asm000066400000000000000000000002621457133061200175300ustar00rootroot00000000000000[bits 64] mov ax, [eax-0x10] add bx, [esi+0x10] add rax, [0xffff] add ax, [esi+edi*4-0x10] add r8, [rax+rbx*4-0x80000000] mov rax, [qword 0x800000000000] libudis86-0+20221013/tests/asm/64/disp.asm.Sref000066400000000000000000000006201457133061200204240ustar00rootroot000000000000000000000000000000 67668b40f0 mov -0x10(%eax), %ax 0000000000000005 6766035e10 add 0x10(%esi), %bx 000000000000000a 48030425ffff0000 add 0xffff, %rax 0000000000000012 67660344bef0 add -0x10(%esi,%edi,4), %ax 0000000000000018 4c03849800000080 add -0x80000000(%rax,%rbx,4), %r8 0000000000000020 48a1000000000080 mov 0x800000000000, %rax -0000 libudis86-0+20221013/tests/asm/64/disp.asm.ref000066400000000000000000000006131457133061200203030ustar00rootroot000000000000000000000000000000 67668b40f0 mov ax, [eax-0x10] 0000000000000005 6766035e10 add bx, [esi+0x10] 000000000000000a 48030425ffff0000 add rax, [0xffff] 0000000000000012 67660344bef0 add ax, [esi+edi*4-0x10] 0000000000000018 4c03849800000080 add r8, [rax+rbx*4-0x80000000] 0000000000000020 48a1000000000080 mov rax, [0x800000000000] -0000 libudis86-0+20221013/tests/asm/64/intel/000077500000000000000000000000001457133061200172025ustar00rootroot00000000000000libudis86-0+20221013/tests/asm/64/intel/invalid.asm000066400000000000000000000003171457133061200213330ustar00rootroot00000000000000;; Test intel specific instructions in 64bit mode [bits 64] ;; yasm doesn't seem to support a mode for intel ;; specific instructions db 0x0f, 0x34 ; sysenter db 0x0f, 0x35 ; sysexit libudis86-0+20221013/tests/asm/64/intel/invalid.asm.ref000066400000000000000000000001661457133061200221100ustar00rootroot000000000000000000000000000000 0f34 sysenter 0000000000000002 0f35 sysexit libudis86-0+20221013/tests/asm/64/reljmp.asm000066400000000000000000000003151457133061200200610ustar00rootroot00000000000000[bits 64] [org 0x8000000000000000] l1: nop nop nop nop nop jmp l1 nop jmp word l2 nop nop jmp dword l2 nop nop nop l2: nop nop jmp l1 libudis86-0+20221013/tests/asm/64/reljmp.asm.ref000066400000000000000000000017531457133061200206430ustar00rootroot000000000000008000000000000000 90 nop 8000000000000001 90 nop 8000000000000002 90 nop 8000000000000003 90 nop 8000000000000004 90 nop 8000000000000005 ebf9 jmp 0x8000000000000000 8000000000000007 90 nop 8000000000000008 66e90a00 jmp 0x16 800000000000000c 90 nop 800000000000000d 90 nop 800000000000000e e903000000 jmp 0x8000000000000016 8000000000000013 90 nop 8000000000000014 90 nop 8000000000000015 90 nop 8000000000000016 90 nop 8000000000000017 90 nop 8000000000000018 ebe6 jmp 0x8000000000000000 libudis86-0+20221013/tests/asm/64/sext.asm000066400000000000000000000005041457133061200175530ustar00rootroot00000000000000[bits 64] ;; test sign extension adc al, -100 adc ax, -100 adc eax, -100 adc rax, -100 imul dx, bx, -100 imul edx, ebx, -100 imul rdx, r11, -100 push byte -1 push word -1 push dword -1000 push word -1000 push -1 push byte -1 push dword -1 push word -1 libudis86-0+20221013/tests/asm/64/sext.asm.ref000066400000000000000000000016021457133061200203260ustar00rootroot000000000000000000000000000000 149c adc al, 0x9c 0000000000000002 6683d09c adc ax, 0xff9c 0000000000000006 83d09c adc eax, 0xffffff9c 0000000000000009 4883d09c adc rax, 0xffffffffffffff9c 000000000000000d 666bd39c imul dx, bx, 0xff9c 0000000000000011 6bd39c imul edx, ebx, 0xffffff9c 0000000000000014 496bd39c imul rdx, r11, 0xffffffffffffff9c 0000000000000018 6aff push 0xffffffffffffffff 000000000000001a 666aff push 0xffff 000000000000001d 6818fcffff push 0xfffffffffffffc18 0000000000000022 666818fc push 0xfc18 0000000000000026 6aff push 0xffffffffffffffff 0000000000000028 6aff push 0xffffffffffffffff 000000000000002a 6aff push 0xffffffffffffffff 000000000000002c 666aff push 0xffff libudis86-0+20221013/tests/asm/64/test64.asm000066400000000000000000000056211457133061200177260ustar00rootroot00000000000000[bits 64] mov rax, 0x102030405060708 mov [eax+0x10], ax mov [eax+0x1000], ebx mov [ebp+eax+0x40], esi mov qword [ebp+edi+0x1000], 0x10 mov byte [esp], 0x10 mov [eax], rax mov [r12], eax mov [r13+r12+0x200], eax mov [r8*4+0x670], sil inc rax dec rax mov [rip+0x200], rax mov rax, 0x10000 push rax push r12 call qword [r8] call qword [rax] call far word [r8] call far dword [rax] cbw cwde cdqe cwd cdq cqo cmovl rax, [rax] cmovge eax, [rax] clflush [r14] cmp [rax], rax cmp rbx, r12 cmp r12d, r8d cmpsb cmpsw cmpsd cmpsq cmpxchg [eax], r14 cmpxchg8b [ebx] inc r12d inc dword [rax] dec r11w hlt imul rax, [eax+ebx*8+0x100000], 0x10 idiv dword [r12] enter 0x100, 0x0 enter 0x100, 0x1 enter 0x100, 0x10 in al, 0x10 in ax, 0x10 in eax, 0x10 lfs eax, [eax] lgs eax, [ebx] lea eax, [rbx] lea r11, [eax] lodsb lodsq lodsd push rax push r11 xchg [eax], sil xchg [eax], ebx xchg [eax], bx xchg r8, rax xchg r9, rax xchg cx, ax movsd movsq mov al, r11b mov sil, al mov r11b, dil ret 0x10 pop rax pop r11 pop qword [eax] insd outsd mov [r14d], cs mov cs, [ebx+ecx] pushfq scasq lsl ax, [rbx] movups xmm0, [r12d] movupd xmm0, [r12d] movsldup xmm0, [r12d] movups xmm0, xmm1 movups xmm10, xmm12 movups xmm0, xmm12 movlps xmm0, [rax] movlps [rax], xmm0 unpcklps xmm4, xmm5 unpckhps xmm4, xmm5 movhps xmm3, [eax] movhps [rax], xmm3 movss xmm0, dword [eax] movss [eax], xmm0 movlpd [eax], xmm0 movlpd xmm0, [eax] unpcklpd xmm2, xmm4 unpckhpd xmm3, [eax+ebx*8-0x1243] movhpd xmm3, [rax] movhpd [rax], xmm2 movsd xmm3, xmm4 movddup xmm3, [rax] mov dr0, rax mov rax, dr1 movnti [eax], eax movnti [rax], rax movd dword [eax], xmm0 movd dword [eax], xmm0 movq xmm11, [eax] vmmcall vmrun clgi stgi mfence lfence sfence clflush [rax] mov cr8, rax push qword [eax] push word [eax] add bh, bh add dil, dil add sil, bpl add al, sil add rax, r12 add eax, r12d prefetcht0 [eax] prefetchnta [eax] prefetch [eax] add [r8], r9b mov [rax-0x1], eax inc rax jmp qword [eax] jmp rax mov [0x10], rax mov rax, [0x10] mov rax, 0x102030405060708 xchg r8, rax push ax push rax push r11 mov rax, [0x100] pmovmskb r12d, xmm14 movdq2q mm0, xmm13 psrlw xmm10, 0x10 psraw xmm7, 0x1 psllw xmm12, 0x23 swapgs fadd dword [rax+rbx] shl rsi, 1 cvtsi2ss xmm1, qword [eax] cvtss2si rax, dword [eax] cvttsd2si rax, [eax] call 0x64 mpsadbw xmm7, xmm6, 0x7 popfq libudis86-0+20221013/tests/difftest.sh.in000077500000000000000000000106651457133061200176420ustar00rootroot00000000000000# udis86 - tests/difftest.sh.in # # Copyright (c) 2013 Vivek Thampi # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. udcli=@top_builddir@/udcli/udcli srcdir=@srcdir@ builddir=@builddir@ yasm=@YASM@ function asm_org # (srcasm) { cat $1 | sed -n 's/\[org \(.*\)\]/\1/p' } function vendor_opt # (vendor) { if [ ! -z "$1" -a "$1" != "any" ]; then echo "-v $1" fi } function org_opt # (org) { if [ ! -z "$1" ]; then echo "-o $1" fi } function update_ref # (srcasm, outasm, mode, vendor) { local srcasm=$1 local outasm=$2 local mode=$3 local vendor=$4 local org=`org_opt $4` local vendor=`vendor_opt $5` $yasm -f bin ${srcasm} -o ${outasm}.bin && if [ -f "${srcasm}.ref" ]; then echo "REFUP ${outasm}.out -> ${srcasm}.ref" $udcli $vendor $org -${mode} ${outasm}.bin > ${outasm}.out && cp ${outasm}.out ${srcasm}.ref fi && if [ -f "${srcasm}.Sref" ]; then echo "REFUP ${outasm}.out -> ${srcasm}.Sref" $udcli $vendor $org -att -${mode} ${outasm}.bin > ${outasm}.out && cp ${outasm}.out ${srcasm}.Sref fi } function diff_test # (srcasm, outasm, mode, org, vendor) { local srcasm=$1 local outasm=$2 local mode=$3 local vendor=$4 local org=`org_opt $4` local vendor=`vendor_opt $5` $yasm -f bin ${srcasm} -o ${outasm}.bin && if [ ! -f "${srcasm}.ref" ]; then echo "[bits ${mode}]" > ${outasm}.out && $udcli $vendor $org -${mode} -noff -nohex ${outasm}.bin >> ${outasm}.out && diff -w ${srcasm} ${outasm}.out 2>&1 > ${outasm}.diff.log else $udcli ${vendor} $org -${mode} ${outasm}.bin > ${outasm}.out && diff -w ${srcasm}.ref ${outasm}.out 2>&1 > ${outasm}.diff.log fi && if [ -f "${srcasm}.Sref" ]; then $udcli ${vendor} $org -att -${mode} ${outasm}.bin > ${outasm}.out && diff -w ${srcasm}.Sref ${outasm}.out 2>&1 > ${outasm}.diff.log fi && echo "DIFFTEST ${srcasm}: PASS" || ( echo "DIFFTEST ${srcasm}: ***FAIL*** (${outasm}.diff.log)" && return 1 ) } function for_each_asm # (do_op) { local do_op=$1 local rc=0 for mode in 16 32 64; do for vendor in amd intel any; do if [ "${vendor}" == "any" ]; then asmdir=${srcdir}/asm/${mode} outdir=${builddir}/_results/asm/${mode} else asmdir=${srcdir}/asm/${mode}/${vendor} outdir=${builddir}/_results/asm/${mode}/${vendor} fi if [ ! -d "${asmdir}" ]; then continue fi mkdir -p ${outdir} || ( echo "failed to create output dir" && exit 1 ) for a in `find ${asmdir} -maxdepth 1 -name "*.asm"` \ `find ${outdir} -maxdepth 1 -name "*.asm"`; do srcasm=$a outasm=${outdir}/`basename $a` org=`asm_org $srcasm` $do_op $srcasm $outasm $mode "$org" "$vendor" || rc=$? done done done return $rc } if [ "$1" == "refup" ]; then for_each_asm update_ref && exit 0 || exit 1 else for_each_asm diff_test && exit 0 || exit 1 fi libudis86-0+20221013/tests/installcheck.c000066400000000000000000000004761457133061200176750ustar00rootroot00000000000000#include #include int main(void) { ud_t ud_obj; ud_init(&ud_obj); ud_set_input_file(&ud_obj, stdin); ud_set_mode(&ud_obj, 64); ud_set_syntax(&ud_obj, UD_SYN_INTEL); while (ud_disassemble(&ud_obj)) { printf("\t%s\n", ud_insn_asm(&ud_obj)); } return 0; } libudis86-0+20221013/tests/libcheck.c000066400000000000000000000161741457133061200167770ustar00rootroot00000000000000/* udis86 - tests/libcheck.c * * Copyright (c) 2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include unsigned int testcase_check_count; unsigned int testcase_check_fails; #define TEST_DECL(name) \ const char * __testcase_name = name \ #define TEST_CASE() \ do { \ volatile int __c = ++ testcase_check_count; \ if (0) __c += 1; \ do #define TEST_CASE_SET_FAIL() \ do { \ testcase_check_fails++; \ printf("Testcase %s: failure at line %d\n", __testcase_name, __LINE__); \ } while (0) #define TEST_CASE_REPORT_ACTUAL(v) \ printf("Testcase %s: actual = %d\n", __testcase_name, (v)) #define TEST_CASE_REPORT_EXPECTED(v) \ printf("Testcase %s: expected = %d\n", __testcase_name, (v)) #define TEST_CASE_END() \ while (0); \ } while (0) #define TEST_CHECK(cond) \ TEST_CASE() { \ int eval = (cond); \ if (!eval) { \ TEST_CASE_SET_FAIL(); \ } \ } TEST_CASE_END() #define TEST_CHECK_INT(expr, val) \ TEST_CASE() { \ int eval = (expr); \ int val2 = (val); \ if (eval != val2) { \ TEST_CASE_SET_FAIL(); \ TEST_CASE_REPORT_EXPECTED(val2); \ TEST_CASE_REPORT_ACTUAL(eval); \ } \ } TEST_CASE_END() #define TEST_CHECK_OP_REG(o, n, r) \ TEST_CHECK(ud_insn_opr(o, n)->type == UD_OP_REG && \ ud_insn_opr(o, n)->base == (r)) static int input_callback(ud_t *u) { int *n = (int *) ud_get_user_opaque_data(u); if (*n == 0) { return UD_EOI; } --*n; return 0x90; } static void check_input(ud_t *ud_obj) { TEST_DECL("check_input"); const uint8_t code[] = { 0x89, 0xc8 }; /* mov eax, ecx */ int i; /* truncate buffer */ ud_set_mode(ud_obj, 32); for (i = 0; i < 5; ++i) { ud_set_input_buffer(ud_obj, code, (sizeof code) - 1); TEST_CHECK(ud_disassemble(ud_obj) == 1); TEST_CHECK(ud_insn_len(ud_obj) == 1); TEST_CHECK(ud_obj->mnemonic == UD_Iinvalid); } /* input skip on buffer */ { const uint8_t code[] = { 0x89, 0xc8, /* mov eax, ecx*/ 0x90 }; /* nop */ ud_set_input_buffer(ud_obj, code, (sizeof code)); ud_input_skip(ud_obj, 2); TEST_CHECK_INT(ud_disassemble(ud_obj), 1); TEST_CHECK_INT(ud_obj->mnemonic, UD_Inop); ud_set_input_buffer(ud_obj, code, (sizeof code)); ud_input_skip(ud_obj, 0); TEST_CHECK_INT(ud_disassemble(ud_obj), 2); TEST_CHECK_INT(ud_obj->mnemonic, UD_Imov); TEST_CHECK(ud_insn_ptr(ud_obj)[0] == 0x89); TEST_CHECK(ud_insn_ptr(ud_obj)[1] == 0xc8); /* bad skip */ ud_set_input_buffer(ud_obj, code, (sizeof code)); ud_input_skip(ud_obj, 3); TEST_CHECK_INT(ud_disassemble(ud_obj), 0); ud_input_skip(ud_obj, 1); TEST_CHECK_INT(ud_disassemble(ud_obj), 0); ud_set_input_buffer(ud_obj, code, (sizeof code)); ud_input_skip(ud_obj, 0); TEST_CHECK_INT(ud_disassemble(ud_obj), 2); ud_input_skip(ud_obj, 1000); TEST_CHECK_INT(ud_disassemble(ud_obj), 0); } /* input hook test */ { int n; ud_set_user_opaque_data(ud_obj, (void *) &n); ud_set_input_hook(ud_obj, &input_callback); n = 0; TEST_CHECK(ud_disassemble(ud_obj) == 0); n = 1; ud_set_input_hook(ud_obj, &input_callback); TEST_CHECK_INT(ud_disassemble(ud_obj), 1); TEST_CHECK(ud_insn_ptr(ud_obj)[0] == 0x90); TEST_CHECK_INT(ud_obj->mnemonic, UD_Inop); n = 2; ud_set_input_hook(ud_obj, &input_callback); ud_input_skip(ud_obj, 1); TEST_CHECK(ud_disassemble(ud_obj) == 1); TEST_CHECK(ud_obj->mnemonic == UD_Inop); TEST_CHECK(ud_disassemble(ud_obj) == 0); TEST_CHECK(ud_insn_len(ud_obj) == 0); TEST_CHECK(ud_obj->mnemonic == UD_Iinvalid); n = 1; ud_input_skip(ud_obj, 2); TEST_CHECK_INT(ud_disassemble(ud_obj), 0); TEST_CHECK(ud_input_end(ud_obj)); } /* a known buffer overrun test case (used to be bufoverrun.c) */ { const uint8_t code[] = { 0xf0, 0x66, 0x36, 0x67, 0x65, 0x66, 0xf3, 0x67, 0xda }; ud_set_mode(ud_obj, 16); ud_set_input_buffer(ud_obj, code, sizeof code); TEST_CHECK(ud_disassemble(ud_obj) > 0); } } static void check_mode(ud_t *ud_obj) { TEST_DECL("check_mode"); const uint8_t code[] = { 0x89, 0xc8 }; /* mov eax, ecx */ ud_set_input_buffer(ud_obj, code, sizeof code); ud_set_mode(ud_obj, 32); TEST_CHECK(ud_disassemble(ud_obj) == 2); TEST_CHECK_OP_REG(ud_obj, 0, UD_R_EAX); TEST_CHECK_OP_REG(ud_obj, 1, UD_R_ECX); } static void check_disasm(ud_t *ud_obj) { TEST_DECL("check_mode"); const uint8_t code[] = { 0x89, 0xc8, /* mov eax, ecx */ 0x90 }; /* nop */ ud_set_input_buffer(ud_obj, code, sizeof code); ud_set_mode(ud_obj, 32); ud_set_pc(ud_obj, 0x100); TEST_CHECK(ud_disassemble(ud_obj) == 2); TEST_CHECK(ud_insn_off(ud_obj) == 0x100); TEST_CHECK(ud_insn_ptr(ud_obj)[0] == 0x89); TEST_CHECK(ud_insn_ptr(ud_obj)[1] == 0xc8); TEST_CHECK(ud_insn_mnemonic(ud_obj) == UD_Imov); TEST_CHECK(strcmp(ud_lookup_mnemonic(UD_Imov), "mov") == 0); TEST_CHECK(ud_disassemble(ud_obj) == 1); TEST_CHECK(ud_insn_off(ud_obj) == 0x102); TEST_CHECK(ud_insn_ptr(ud_obj)[0] == 0x90); TEST_CHECK(ud_insn_mnemonic(ud_obj) == UD_Inop); TEST_CHECK(strcmp(ud_lookup_mnemonic(UD_Inop), "nop") == 0); } int main(void) { ud_t ud_obj; ud_init(&ud_obj); ud_set_syntax(&ud_obj, UD_SYN_INTEL); check_input(&ud_obj); check_mode(&ud_obj); check_disasm(&ud_obj); if (testcase_check_fails > 0) { printf("libcheck result: %d checks, %d failures\n", testcase_check_count, testcase_check_fails); return 1; } return 0; } /* vim: set ts=2 sw=2 expandtab: */ libudis86-0+20221013/tests/oprgen.py000066400000000000000000000766071457133061200167420ustar00rootroot00000000000000# udis86 - test/testgen.py # # Copyright (c) 2009 Vivek Thampi # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: # # * Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON # ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os import sys import random if ( len( os.getenv( 'UD_SCRIPT_DIR', "" ) ) ): scriptsPath = os.getenv( 'UD_SCRIPT_DIR' ) + "/scripts" else: scriptsPath = '../scripts' sys.path.append( scriptsPath ); import ud_opcode def bits2name(bits): bits2name_map = { 8 : "byte", 16 : "word", 32 : "dword", 64 : "qword", 80 : "tword", 128 : "oword", 256 : "yword", } return bits2name_map[bits] class UdTestGenerator( ud_opcode.UdOpcodeTables ): OprTable = [] ExcludeList = ( 'fcomp3', 'fcom2', 'fcomp5', 'fstp1', 'fstp8', 'fstp9', 'fxch4', 'fxch7', 'nop', 'xchg', 'movd', 'pmulhrw', # yasm bug 'vcvtpd2ps', # operand casting issues 'vcvtpd2dq', # - ditto - 'vcvttpd2dq', # - ditto - 'vmovd', 'vmovq' ) def __init__(self, mode, xml): super(UdTestGenerator, self).__init__(xml=xml) self.mode = mode pass def OprMem(self, size=None, cast=False): choices = [] if self.mode < 64: choices = ["[bx+si+0x1234]", "[bx+0x10]", "[bp+di+0x27]", "[di+0x100]"] choices.extend(("[eax+ebx]", "[ebx+ecx*4]", "[ebp+0x10]")) if self.mode == 64: choices.extend(("[rax+rbx]", "[rbx+r8-0x10]")) addr = random.choice(choices) if cast and size is not None: addr = "%s %s" % (bits2name(size), addr) return addr def OprImm(self, size, cast=False): imm = "0x%x" % random.randint(2, 1 << (size - 1)) if cast and size is not None: imm = "%s %s" % (bits2name(size), imm) return imm def Gpr(self, size): if size == 8: choices = ['al', 'cl'] if self.mode == 64: choices.extend(['sil', 'r10b']) elif size == 16: choices = ['ax', 'bp', 'dx'] if self.mode == 64: choices.extend(['r8w', 'r14w']) elif size == 32: choices = ['eax', 'ebp', 'edx'] if self.mode == 64: choices.extend(['r10d', 'r12d']) elif size == 64: choices = ['rax', 'rsi', 'rsp'] if self.mode == 64: choices.extend(['r9', 'r13']) return random.choice(choices) def Xmm(self): r = 16 if self.mode == 64 else 8 return "xmm%d" % random.choice(range(r)) def Ymm(self): r = 16 if self.mode == 64 else 8 return "ymm%d" % random.choice(range(r)) def Mmx(self): return "mm%d" % random.choice(range(8)) def Modrm_RM_GPR(self, size, cast=False): return random.choice([self.Gpr(size), self.OprMem(size=size, cast=cast)]) def Modrm_RM_XMM(self, size, cast=False): return random.choice([self.Xmm(), self.OprMem(size=size, cast=cast)]) def OprRxb(self, n): regs = [ 'al', 'cl', 'dl', 'bl' ] if self.mode == 64 and random.choice((False, True)): regs += [ 'spl', 'bpl', 'sil', 'dil', 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b' ] n |= random.choice((0, 8)) else: regs += [ 'ah', 'ch', 'dh', 'bh' ] return regs[n] def OprRxw(self, n): regs = [ 'ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di' ] if self.mode == 64 and random.choice((False, True)): regs += [ 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w' ] n |= random.choice((0, 8)) return regs[n] def OprRxd(self, n): regs = [ 'eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi' ] if self.mode == 64 and random.choice((False, True)): regs += [ 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d' ] n |= random.choice((0, 8)) return regs[n] def OprRxq(self, n): regs = [ 'rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15' ] n |= random.choice((0, 8)) return regs[n] def OprRxv(self, n): choices = [ self.OprRxw(n), self.OprRxd(n) ] if self.mode == 64: choices.append(self.OprRxq(n)) return random.choice(choices) def OprRxz(self, n): choices = [ self.OprRxw(n), self.OprRxd(n) ] return random.choice(choices) def OprRxy(self, n): choices = [ self.OprRxd(n) ] if self.mode == 64: choices.append(self.OprRxq(n)) return random.choice(choices) Opr_R0b = lambda s: s.OprRxb(0); Opr_R1b = lambda s: s.OprRxb(1); Opr_R2b = lambda s: s.OprRxb(2); Opr_R3b = lambda s: s.OprRxb(3); Opr_R4b = lambda s: s.OprRxb(4); Opr_R5b = lambda s: s.OprRxb(5); Opr_R6b = lambda s: s.OprRxb(6); Opr_R7b = lambda s: s.OprRxb(7); Opr_R0y = lambda s: s.OprRxy(0); Opr_R1y = lambda s: s.OprRxy(1); Opr_R2y = lambda s: s.OprRxy(2); Opr_R3y = lambda s: s.OprRxy(3); Opr_R4y = lambda s: s.OprRxy(4); Opr_R5y = lambda s: s.OprRxy(5); Opr_R6y = lambda s: s.OprRxy(6); Opr_R7y = lambda s: s.OprRxy(7); Opr_R0v = lambda s: s.OprRxv(0); Opr_R1v = lambda s: s.OprRxv(1); Opr_R2v = lambda s: s.OprRxv(2); Opr_R3v = lambda s: s.OprRxv(3); Opr_R4v = lambda s: s.OprRxv(4); Opr_R5v = lambda s: s.OprRxv(5); Opr_R6v = lambda s: s.OprRxv(6); Opr_R7v = lambda s: s.OprRxv(7); Opr_R0z = lambda s: s.OprRxz(0); Opr_R1z = lambda s: s.OprRxz(1); Opr_R2z = lambda s: s.OprRxz(2); Opr_R3z = lambda s: s.OprRxz(3); Opr_R4z = lambda s: s.OprRxz(4); Opr_R5z = lambda s: s.OprRxz(5); Opr_R6z = lambda s: s.OprRxz(6); Opr_R7z = lambda s: s.OprRxz(7); def Insn_Av(self): return random.choice([("word 0x100:0x100",), ("dword 0x100:0xfaddbc",)]) def Opr_R(self): if self.mode == 64: return self.OprRxq(random.choice(range(8))) return self.OprRxd(random.choice(range(8))); def Opr_C(self): return "cr3" def Opr_D(self): return "dr0" def Opr_S(self): return "fs" def Opr_ST0(self): return "st0" def Opr_ST1(self): return "st1" def Opr_ST2(self): return "st2" def Opr_ST3(self): return "st3" def Opr_ST4(self): return "st4" def Opr_ST5(self): return "st5" def Opr_ST6(self): return "st6" def Opr_ST7(self): return "st7" def Opr_CS(self): return "cs" def Opr_GS(self): return "gs" def Opr_ES(self): return "es" def Opr_FS(self): return "fs" def Opr_DS(self): return "ds" def Opr_SS(self): return "ss" def Opr_Ib(self, cast=False): return self.OprImm(8, cast=cast) def Opr_Iw(self, cast=False): return self.OprImm(16, cast=cast) def Opr_Id(self, cast=False): return self.OprImm(32, cast=cast) def Opr_Iq(self, cast=False): return self.OprImm(64, cast=cast) def Opr_Iz(self, cast=False): return random.choice((self.OprImm(16, cast=cast), self.OprImm(32, cast=cast))) Opr_sIz = Opr_Iz def Opr_Iw(self, cast=False): return self.OprImm(16, cast=cast) def Opr_I1(self, cast=False): return "1" def Opr_eAX(self): return random.choice(['ax', 'eax']) def Opr_rAX(self): choices = ['ax', 'eax'] if self.mode == 64: choices.append('rax') return random.choice(choices) def Insn_rAX_Iz(self): choices = [('ax', self.Opr_Iw()), ('eax', self.Opr_Id())] if self.mode == 64: choices.append(('rax', self.Opr_Id())) return random.choice(choices) Insn_rAX_sIz = Insn_rAX_Iz def Insn_Rxv_Iv(self, n): choices = [(self.OprRxw(n), self.Opr_Iw()), (self.OprRxd(n), self.Opr_Id())] if self.mode == 64: choices.append((self.OprRxq(n), self.Opr_Iq())) return random.choice(choices) Insn_R0v_Iv = lambda s: s.Insn_Rxv_Iv(0) Insn_R1v_Iv = lambda s: s.Insn_Rxv_Iv(1) Insn_R2v_Iv = lambda s: s.Insn_Rxv_Iv(2) Insn_R3v_Iv = lambda s: s.Insn_Rxv_Iv(3) Insn_R4v_Iv = lambda s: s.Insn_Rxv_Iv(4) Insn_R5v_Iv = lambda s: s.Insn_Rxv_Iv(5) Insn_R6v_Iv = lambda s: s.Insn_Rxv_Iv(6) Insn_R7v_Iv = lambda s: s.Insn_Rxv_Iv(7) def Insn_Rxv_rAX(self, n): choices = [(self.OprRxw(n), "ax"), (self.OprRxd(n), "eax")] if self.mode == 64: choices.append((self.OprRxq(n), "rax")) return random.choice(choices) Insn_R0v_rAX = lambda s: s.Insn_Rxv_rAX(0) Insn_R1v_rAX = lambda s: s.Insn_Rxv_rAX(1) Insn_R2v_rAX = lambda s: s.Insn_Rxv_rAX(2) Insn_R3v_rAX = lambda s: s.Insn_Rxv_rAX(3) Insn_R4v_rAX = lambda s: s.Insn_Rxv_rAX(4) Insn_R5v_rAX = lambda s: s.Insn_Rxv_rAX(5) Insn_R6v_rAX = lambda s: s.Insn_Rxv_rAX(6) Insn_R7v_rAX = lambda s: s.Insn_Rxv_rAX(7) def Opr_Gb(self): return self.Gpr(8) def Opr_Gw(self): return self.Gpr(16) def Opr_Gd(self): return self.Gpr(32) def Opr_Gq(self): return self.Gpr(64) def Opr_Gz(self): return random.choice([self.Gpr(16), self.Gpr(32)]) def Opr_Gv(self): choices = [self.Gpr(16), self.Gpr(32)] if self.mode == 64: choices.append(self.Gpr(64)) return random.choice(choices) def Opr_Gy(self): choices = [self.Gpr(32)] if self.mode == 64: choices.append(self.Gpr(64)) return random.choice(choices) def Opr_M(self): return self.OprMem(); def Opr_U(self, L=False): return self.Xmm() if not L else self.Ymm() Opr_Ux = Opr_U def Opr_N(self): return self.Mmx(); def Opr_Mb(self, cast=False): return self.OprMem(size=8, cast=cast); def Opr_Mw(self, cast=False): return self.OprMem(size=16, cast=cast); def Opr_Md(self, cast=False): return self.OprMem(size=32, cast=cast); def Opr_Mq(self, cast=False): return self.OprMem(size=64, cast=cast); def Opr_Mdq(self, cast=False): return self.OprMem(size=128, cast=cast); def Opr_Mt(self, cast=True): return self.OprMem(size=80, cast=cast); def Opr_MwRd(self, cast=True): return random.choice((self.Opr_Mw(cast=cast), self.Opr_Gd())) def Opr_MwRv(self, cast=False): return random.choice((self.Opr_Mw(cast=cast), self.Opr_Gv())) def Opr_MwRy(self, cast=True): return random.choice((self.Opr_Mw(cast=cast), self.Opr_Gy())) def Opr_MdRy(self, cast=False): return random.choice((self.Opr_Md(cast=cast), self.Opr_Gy())) def Opr_MbRv(self, cast=False): return random.choice((self.Opr_Mb(cast=cast), self.Opr_Gv())) def Opr_MbRd(self, cast=False): return random.choice((self.Opr_Mb(cast=cast), self.Opr_Gd())) def Opr_MwRw(self, cast=False): return random.choice((self.Opr_Mw(cast=cast), self.Opr_Gw())) def Opr_MwU(self, cast=False): return random.choice((self.Opr_Mw(cast=cast), self.Xmm())) def Opr_MdU(self, cast=False): return random.choice((self.Opr_Md(cast=cast), self.Xmm())) def Opr_MqU(self, cast=False): return random.choice((self.Opr_Mq(cast=cast), self.Xmm())) def Insn_V_MwU(self, cast=False): return (self.Opr_V(), self.Opr_MwU(cast=True)) def Insn_V_MdU(self, cast=False): return self.Opr_V(), self.Opr_MdU(cast=True) def Insn_V_MqU(self, cast=False): return self.Opr_V(), self.Opr_MqU(cast=True) def Insn_Vx_MwU(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_MwU(cast=True) def Insn_Vx_MdU(self, cast=False): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(), self.Opr_MdU(cast=True) def Insn_Vx_MqU(self, cast=False): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(), self.Opr_MqU(cast=True) def Insn_V_Md(self, cast=False): return self.Opr_V(), self.Opr_Md(cast=True) def Insn_V_Mq(self, cast=False): return self.Opr_V(), self.Opr_Mq(cast=True) def Insn_Mq_V(self): x, y = self.Insn_V_Mq() return y, x def Insn_Md_V(self): x, y = self.Insn_V_Md() return y, x def Insn_Vqq_Mq(self, cast=False): return self.Opr_Vqq(), self.Opr_Mq(cast=True) def Insn_Wdq_Vqq_Ib(self, cast=False): return self.Opr_W(size=128, cast=True), self.Opr_Vqq(), self.Opr_Ib() def Insn_MbRv(self): return [self.Opr_MbRv(cast=True)] def Insn_MbRv_V_Ib(self): return [self.Opr_MbRv(cast=True), self.Opr_V(), self.Opr_Ib()] def Insn_V_MbRd_Ib(self): return [self.Opr_V(), self.Opr_MbRd(cast=True), self.Opr_Ib()] def Insn_MwRv(self): return [self.Opr_MwRv(cast=True)] def Insn_MwRd_V_Ib(self): return [self.Opr_MwRd(cast=True), self.Opr_V(), self.Opr_Ib()] Insn_MwRd_Vx_Ib = Insn_MwRd_V_Ib def Insn_S_MwRv(self): if self.mode == 64: return [self.Opr_S(), self.Opr_MwRd(cast=False)] if self.mode == 16: return [self.Opr_S(), self.Opr_MwRw(cast=False)] if self.mode == 32: return [self.Opr_S(), self.Opr_MwRd(cast=False)] def Insn_Mw(self): return [self.Opr_Mw(cast=True)] def Insn_Md(self): return [self.Opr_Md(cast=True)] def Insn_Mq(self): return [self.Opr_Mq(cast=True)] def Opr_Eb(self, cast=False): return self.Modrm_RM_GPR(8, cast=cast) def Opr_Ew(self, cast=False): return self.Modrm_RM_GPR(16, cast=cast) def Opr_Ed(self, cast=False): return self.Modrm_RM_GPR(32, cast=cast) def Opr_Eq(self, cast=False): return self.Modrm_RM_GPR(64, cast=cast) def Opr_Ey(self, cast=False): choices = [self.Modrm_RM_GPR(32, cast=cast)] if self.mode == 64: choices.append(self.Modrm_RM_GPR(64, cast=cast)) return random.choice(choices) def Insn_Fv(self): return ("far "+ self.Opr_Mv(cast=True),) def Insn_V_Ew_Ib(self): return self.Opr_V(), self.Opr_Ew(cast=True), self.Opr_Ib() def Insn_V_Eq_Ib(self): return self.Opr_V(), self.Opr_Eq(cast=True), self.Opr_Ib() def Insn_V_Mo(self): return self.Opr_V(), self.Opr_M() def Insn_V_Md_Ib(self): return self.Opr_V(), self.Opr_Md(cast=True), self.Opr_Ib() def Insn_V_Ed(self): return self.Opr_V(), self.Opr_Ed(cast=True) def Insn_V_Ed_Ib(self): x, y = self.Insn_V_Ed() return x, y, self.Opr_Ib() def Insn_P_Ew_Ib(self): return self.Opr_P(), self.Opr_Ew(cast=True), self.Opr_Ib() def Insn_V_Ey(self): return self.Opr_V(), self.Opr_Ey(cast=True) def Insn_Ey_V(self): x, y = self.Insn_V_Ey() return y, x def Insn_P_Ey(self): return self.Opr_P(), self.Opr_Ey(cast=True) def Insn_Ey_P(self): x, y = self.Insn_P_Ey() return y, x def Opr_Mv(self, cast=False): choices = [self.Opr_Mw(cast), self.Opr_Md(cast)] if self.mode == 64: choices.append(self.Opr_Mq(cast)) return random.choice(choices) def Opr_Ev(self, cast=False): choices = [self.Opr_Ew(cast), self.Opr_Ed(cast)] if self.mode == 64: choices.append(self.Opr_Eq(cast)) return random.choice(choices) def Insn_Ev(self): choices = [self.Modrm_RM_GPR(16, cast=True), self.Modrm_RM_GPR(32, cast=True)] if self.mode == 64: choices.append(self.Modrm_RM_GPR(64, cast=True)) return [random.choice(choices)] def Opr_V(self, L=False): return self.Xmm() if not L else self.Ymm() Opr_Vdq = Xmm Opr_Vqq = Ymm Opr_Hqq = Ymm def Opr_Vsd(self, L=False): return self.Xmm() if not L else self.Ymm() def Opr_L(self, L=False): return self.Xmm() if not L else self.Ymm() def Opr_H(self, L=False): return self.Opr_V(L) def Opr_W(self, L=False, cast=False, size=None): if not L: if size is None: size = 128 return random.choice([self.Xmm(), self.OprMem(size=size, cast=cast)]) else: if size is None: size = 256 return random.choice([self.Ymm(), self.OprMem(size=size, cast=cast)]) Opr_Wx = Opr_W def Opr_Wdq(self, cast=False): return self.Opr_W(cast=cast, size=128) def Opr_Wsd(self, L=False): return random.choice([self.Xmm(), self.OprMem(size=64, cast=False)]) def Opr_Wdq(self, cast=False): return random.choice([self.Xmm(), self.OprMem(size=128, cast=cast)]) def Opr_Wqq(self, L=False): return random.choice([self.Ymm(), self.OprMem(size=256, cast=False)]) def Insn_V_H_W(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_W(L)] def Insn_Vx_Wx(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_W(L, cast=False)] def Insn_Wx_Vx(self): x, y = self.Insn_Vx_Wx() return y, x def Insn_Vx_U(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_U(L) def Insn_Eq_Vx(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_Eq(), self.Opr_V(L) def Insn_Ey_Vx(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_Ey(cast=True), self.Opr_V(L) def Insn_Vx_Ey(self): x, y = self.Insn_Ey_Vx() return y, x def Insn_Vdq_Wx(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_Vdq(), self.Opr_W(L, cast=True)] def Insn_Vdq_W(self): return [self.Opr_V(), self.Opr_W(cast=False)] def Insn_V_Wdq(self): return [self.Opr_V(), self.Opr_W(cast=False)] def Insn_Vx_Ux(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_U(L) def Insn_Vx_Wdq(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_W(L=False, cast=L)] def Insn_Vx_Wx_Ib(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_W(L), self.Opr_Ib()] def Insn_Vx_Hx_Wx(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_W(L)] def Insn_Hx_Vx_Wx(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_H(L), self.Opr_V(L), self.Opr_W(L)] def Insn_Vx_Hx_Ux(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_U(L)] def Insn_Hx_Ux_Ib(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_H(L), self.Opr_U(L), self.Opr_Ib()] def Insn_Vx_Hx_Ey(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_H(L), self.Opr_Ey(cast=True) def Insn_Vx_Hx_Ed_Ib(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_H(L), self.Opr_Ed(cast=True), self.Opr_Ib() Insn_V_H_Ed_Ib = Insn_Vx_Hx_Ed_Ib def Insn_V_H_Eq_Ib(self): return self.Opr_V(), self.Opr_H(), self.Opr_Eq(cast=True), self.Opr_Ib() def Insn_V_H_MbRd_Ib(self): return self.Opr_V(), self.Opr_H(), self.Opr_MbRd(cast=True), self.Opr_Ib() def Insn_Vx_Hx_Wx_Ib(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_W(L), self.Opr_Ib()] def Insn_Vx_Hx_M(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_H(L), self.Opr_M() def Insn_Vx_Hx_Md_Ib(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_Md(cast=True), self.Opr_Ib()] def Insn_Vqq_Hqq_Wdq_Ib(self): return [self.Opr_Vqq(), self.Opr_Hqq(), self.Opr_Wdq(cast=True), self.Opr_Ib()] def Insn_Vx_Hx_Wx_Lx(self): L = random.choice((True, False)) if self.vexl else False return [self.Opr_V(L), self.Opr_H(L), self.Opr_W(L), self.Opr_L(L)] def Insn_Vx_Hx_MqU(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_H(L), self.Opr_MqU(cast=True) def Insn_Vx_Hx_MdU(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_H(L), self.Opr_MdU(cast=True) def Insn_Vx_M(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_V(L), self.Opr_M() def Insn_M_Vx(self): x, y = self.Insn_Vx_M() return y, x def Insn_MdRy_Vx_Ib(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_MdRy(cast=True), self.Opr_V(L), self.Opr_Ib() def Insn_MdRy_V_Ib(self): return self.Opr_MdRy(cast=True), self.Opr_V(), self.Opr_Ib() def Insn_MdRv_Vx_Ib(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_MdRv(cast=True), self.Opr_V(L), self.Opr_Ib() def Insn_MdRv_V_Ib(self): return self.Opr_MdRv(cast=True), self.Opr_V(), self.Opr_Ib() def Insn_MwRv_Vx_Ib(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_MwRv(cast=True), self.Opr_V(L), self.Opr_Ib() def Insn_MwRv_V_Ib(self): return self.Opr_MwRv(cast=True), self.Opr_V(), self.Opr_Ib() def Insn_Ed_Vx_Ib(self): L = random.choice((True, False)) if self.vexl else False return self.Opr_Ed(cast=True), self.Opr_V(L), self.Opr_Ib() def Opr_P(self): return self.Mmx() def Opr_Q(self, cast=False): return random.choice([self.Mmx(), self.OprMem(size=64, cast=cast)]) def Opr_CL(self): return "cl" def Opr_AL(self): return "al" def Opr_Ob(self): return "[0x100]" def Insn_rAX_Ov(self): choices = [ ("ax", "[0x100]"), ("eax", "[0x1000]") ] if self.mode == 64: choices.append(("rax", "[0x1223221]")) return random.choice(choices) def Insn_Ov_rAX(self): x, y = self.Insn_rAX_Ov() return y, x def Opr_AX(self): return "ax" def Opr_DX(self): return "dx" def Insn_Eb_CL(self): return self.Opr_Eb(cast=True), self.Opr_CL() def Insn_Ev_CL(self): return self.Opr_Ev(cast=True), self.Opr_CL() def Insn_Eb(self): return [self.Modrm_RM_GPR(size=8, cast=True)] def Insn_Ew(self): return [self.Modrm_RM_GPR(size=16, cast=True)] def Insn_Ev_Gv(self): choices = [ (self.Opr_Ew(), self.Opr_Gw()), (self.Opr_Ed(), self.Opr_Gd()) ] if self.mode == 64: choices.append((self.Opr_Eq(), self.Opr_Gq())) return random.choice(choices) def Insn_Ev_Gy(self): choices = [ (self.Opr_Ew(), self.Opr_Gd()), (self.Opr_Ed(), self.Opr_Gd()) ] if self.mode == 64: choices.append((self.Opr_Eq(), self.Opr_Gq())) return random.choice(choices) def Insn_Ev_Gv_CL(self): x, y = self.Insn_Ev_Gv(); return x, y, self.Opr_CL() def Insn_Gv_Ev_CL(self): x, y = self.Insn_Ev_Gv(); return y, x, self.Opr_CL() def Insn_Gv_Ev_Ib(self): x, y = self.Insn_Ev_Gv(); return y, x, self.Opr_Ib(cast=False) Insn_Gv_Ev_sIb = Insn_Gv_Ev_Ib def Insn_Gv_Ev_Iz(self): choices = [ (self.Opr_Gw(), self.Opr_Ew(), self.Opr_Iw()), (self.Opr_Gd(), self.Opr_Ed(), self.Opr_Id()) ] if self.mode == 64: choices.append((self.Opr_Gq(), self.Opr_Eq(), self.Opr_Iz())) return random.choice(choices) def Insn_Ev_Ib(self): return self.Opr_Ev(cast=True), self.Opr_Ib() Insn_Ev_sIb = Insn_Ev_Ib def Insn_Gq_Ed(self): return self.Opr_Gq(), self.Opr_Ed(cast=True) def Insn_Gy_Eb(self): return self.Opr_Gy(), self.Opr_Eb(cast=True) def Insn_Gy_Ew(self): return self.Opr_Gy(), self.Opr_Ew(cast=True) def Insn_Gy_W(self): choices = [(self.Gpr(32), self.Opr_W(size=32, cast=False)),] if self.mode == 64: choices.append([self.Gpr(64), self.Opr_W(size=32, cast=True)]) return random.choice(choices) def Insn_Gy_MqU(self): choices = [(self.Gpr(32), self.Opr_W(size=64, cast=True)),] if self.mode == 64: choices.append([self.Gpr(64), self.Opr_W(size=64, cast=False)]) return random.choice(choices) def Insn_Gy_MdU(self): choices = [(self.Gpr(32), self.Opr_W(size=32, cast=False)),] if self.mode == 64: choices.append([self.Gpr(64), self.Opr_W(size=32, cast=True)]) return random.choice(choices) def Insn_Gd_Ux(self): L = random.choice((True, False)) if self.vexl else False return self.Gpr(32), self.Opr_U(L) def Insn_Gy_Ux(self): L = random.choice((True, False)) if self.vexl else False choices = [(self.Gpr(32), self.Opr_U(L)),] if self.mode == 64: choices.append([self.Gpr(64), self.Opr_U(L)]) return random.choice(choices) def Insn_Gy_Ux_Ib(self): x, y = self.Insn_Gy_Ux() return x, y, self.Opr_Ib() def Insn_Ev_Iz(self): choices = [(self.Opr_Ew(cast=True), self.Opr_Iw()), (self.Opr_Ed(cast=True), self.Opr_Id())] if self.mode == 64: choices.append((self.Opr_Eq(cast=True), self.Opr_Id())) return random.choice(choices) Insn_Ev_sIz = Insn_Ev_Iz def Insn_Gv_Ev(self): x, y = self.Insn_Ev_Gv(); return (y, x) def Insn_Gy_Ev(self): x, y = self.Insn_Ev_Gy(); return (y, x) def Insn_Gv_Eb(self): return (self.Opr_Gv(), self.Opr_Eb(cast=True)) def Insn_Gv_Ew(self): choices = [(self.Opr_Gw(), self.Opr_Ew(cast=False)), (self.Opr_Gd(), self.Opr_Ew(cast=True))] if self.mode == 64: choices.append((self.Opr_Gq(), self.Opr_Ew(cast=True))) return random.choice(choices) def Insn_V_Q(self): return [self.Opr_V(), self.Opr_Q(cast=True)] def Insn_Eb_Ib(self): return (self.Opr_Eb(cast=True), self.Opr_Ib(cast=False)) def Insn_Eb_I1(self): return (self.Opr_Eb(cast=True), self.Opr_I1()) def Insn_Ev_I1(self): return (self.Opr_Ev(cast=True), self.Opr_I1()) def Insn_Ev_Ib(self): return (self.Opr_Ev(cast=True), self.Opr_Ib(cast=False)) Insn_Ev_sIb = Insn_Ev_Ib def Insn_Ev_Gv_Ib(self): choices = [ (self.Opr_Ew(), self.Opr_Gw(), self.Opr_Ib(cast=False)), (self.Opr_Ed(), self.Opr_Gd(), self.Opr_Ib(cast=False)) ] if self.mode == 64: choices.append( (self.Opr_Eq(), self.Opr_Gq(), self.Opr_Ib(cast=False)) ) return random.choice(choices) Insn_Ev_Gv_sIb = Insn_Ev_Gv_Ib def Insn_Ev_V_Ib(self): return self.Opr_Ev(cast=True), self.Opr_V(), self.Opr_Ib(cast=False) def Insn_Ed_V_Ib(self): return self.Opr_Ed(cast=True), self.Opr_V(), self.Opr_Ib(cast=False) def Insn_Ew_V_Ib(self): return (self.Opr_Ew(cast=True), self.Opr_V(), self.Opr_Ib(cast=False)) def generate_yasm( self, mode, seed ): opr_combos = {} random.seed( seed ) print("[bits %s]" % mode) for insn in self.getInsnList(): if insn.mnemonic in self.ExcludeList: continue if insn.vendor == 'intel': continue if ((insn.mode == '!64' and self.mode == 64) or (insn.mode == '64' and self.mode != 64)): continue if insn.osize == '64' and self.mode != 64: continue if insn.isDef64(): continue if len(insn.operands) == 0: continue if "Jb" in insn.operands or "Jz" in insn.operands: continue if insn.lookupPrefix("vexl"): self.vexl = True else: self.vexl = False fusedName = '_'.join(insn.operands) if fusedName not in opr_combos: opr_combos[fusedName] = { 'covered' : False, 'freq' : 0 } opr_combos[fusedName]['freq'] += 1 fn = getattr(self, "Insn_" + fusedName , None) if fn is not None: operands = ", ".join(fn()) else: oprgens = [ getattr(self, "Opr_" + opr, None) for opr in insn.operands ] if None not in oprgens: operands = ", ".join([ oprgen() for oprgen in oprgens ]) else: operands = None if operands is not None: print("\t%s %s" % (insn.mnemonic, operands)) opr_combos[fusedName]['covered'] = True # stats total = 0 covered = 0 for combo in sorted(opr_combos, key=lambda k: opr_combos[k]['freq']): total += 1 is_covered = opr_combos[combo]['covered'] covered += (1 if is_covered else 0) if not is_covered: sys.stderr.write("==> %12s : %5d\n" % (combo, opr_combos[combo]['freq'])) sys.stderr.write("MODE%s: Coverage = %d / %d (%d%%)\n" % (self.mode, covered, total, (100 * covered / total))) def main(): generator = UdTestGenerator(mode=int(sys.argv[3]), xml=sys.argv[1]) generator.generate_yasm( sys.argv[ 3 ], int( sys.argv[ 2 ] ) ) if __name__ == '__main__': main() libudis86-0+20221013/tests/symresolve.c000066400000000000000000000022611457133061200174330ustar00rootroot00000000000000#include #include #if defined(__amd64__) || defined(__x86_64__) # define FMT "l" #else # define FMT "ll" #endif uint8_t bin[] = { 0x01, 0xc0, 0xeb, 0x11, 0x01, 0xc0, 0xe8, 0x14, 0x00, 0x00, 0x00, 0x01, 0xc0, 0x01, 0xc0, 0x74, 0x02, 0x01, 0xc0, 0x90, 0x90, 0xeb, 0xfe, 0x90, 0x90, 0xeb, 0xf8, 0x90, 0x90, 0x74, 0xf6, 0x90, 0x90, 0xe8, 0xf4, 0xff, 0xff, 0xff }; static const char* resolve(struct ud *u, uint64_t addr, int64_t *offset) { *offset = addr - 0x15; return "target"; } static void dis_loop(struct ud *ud_obj) { while (ud_disassemble(ud_obj) != 0) { printf("%016llx %-16s %s\n", ud_insn_off(ud_obj), ud_insn_hex(ud_obj), ud_insn_asm(ud_obj)); } } int main() { ud_t ud_obj; ud_init(&ud_obj); ud_set_mode(&ud_obj, 32); ud_set_input_buffer(&ud_obj, bin, sizeof(bin)); ud_set_syntax(&ud_obj, UD_SYN_INTEL); printf("==> Without Symbol Resolution\n"); dis_loop(&ud_obj); printf("==> With Symbol Resolution\n"); ud_set_pc(&ud_obj, 0); ud_set_input_buffer(&ud_obj, bin, sizeof(bin)); ud_set_sym_resolver(&ud_obj, &resolve); dis_loop(&ud_obj); return 0; } libudis86-0+20221013/tests/symresolve.ref000066400000000000000000000033401457133061200177640ustar00rootroot00000000000000==> Without Symbol Resolution 0000000000000000 01c0 add eax, eax 0000000000000002 eb11 jmp 0x15 0000000000000004 01c0 add eax, eax 0000000000000006 e814000000 call 0x1f 000000000000000b 01c0 add eax, eax 000000000000000d 01c0 add eax, eax 000000000000000f 7402 jz 0x13 0000000000000011 01c0 add eax, eax 0000000000000013 90 nop 0000000000000014 90 nop 0000000000000015 ebfe jmp 0x15 0000000000000017 90 nop 0000000000000018 90 nop 0000000000000019 ebf8 jmp 0x13 000000000000001b 90 nop 000000000000001c 90 nop 000000000000001d 74f6 jz 0x15 000000000000001f 90 nop 0000000000000020 90 nop 0000000000000021 e8f4ffffff call 0x1a ==> With Symbol Resolution 0000000000000000 01c0 add eax, eax 0000000000000002 eb11 jmp target 0000000000000004 01c0 add eax, eax 0000000000000006 e814000000 call target+10 000000000000000b 01c0 add eax, eax 000000000000000d 01c0 add eax, eax 000000000000000f 7402 jz target-2 0000000000000011 01c0 add eax, eax 0000000000000013 90 nop 0000000000000014 90 nop 0000000000000015 ebfe jmp target 0000000000000017 90 nop 0000000000000018 90 nop 0000000000000019 ebf8 jmp target-2 000000000000001b 90 nop 000000000000001c 90 nop 000000000000001d 74f6 jz target 000000000000001f 90 nop 0000000000000020 90 nop 0000000000000021 e8f4ffffff call target+5 libudis86-0+20221013/udcli/000077500000000000000000000000001457133061200150145ustar00rootroot00000000000000libudis86-0+20221013/udcli/CMakeLists.txt000066400000000000000000000002241457133061200175520ustar00rootroot00000000000000cmake_minimum_required(VERSION 3.12) project(udcli LANGUAGES C) add_executable(udcli EXCLUDE_FROM_ALL udcli.c) target_link_libraries(udcli udis86) libudis86-0+20221013/udcli/Makefile.am000066400000000000000000000003021457133061200170430ustar00rootroot00000000000000bin_PROGRAMS = udcli udcli_SOURCES = udcli.c udcli_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir) udcli_LDADD = $(top_builddir)/libudis86/libudis86.la MAINTAINERCLEANFILES = Makefile.in libudis86-0+20221013/udcli/udcli.c000066400000000000000000000256551457133061200162750ustar00rootroot00000000000000/* udis86 - udcli/udcli.c * * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #ifdef _MSC_VER #include "..\udis86.h" #define PACKAGE_STRING "udis86 pre-1.8" #else #include #include #endif #if defined(__APPLE__) # define FMT64 "ll" #elif defined(__amd64__) || defined(__x86_64__) # define FMT64 "l" # else # define FMT64 "ll" #endif #if defined(__DJGPP__) || defined(_WIN32) # include # include #endif #ifdef __DJGPP__ # include /* for isatty() */ # define _setmode setmode # define _fileno fileno # define _O_BINARY O_BINARY #endif /* help string */ static char help[] = { "Usage: %s [-option[s]] file\n" "Options:\n" " -16 : Set the disassembly mode to 16 bits. \n" " -32 : Set the disassembly mode to 32 bits. (default)\n" " -64 : Set the disassembly mode to 64 bits.\n" " -intel : Set the output to INTEL (NASM like) syntax. (default)\n" " -att : Set the output to AT&T (GAS like) syntax.\n" " -v : Set vendor. = {intel, amd}.\n" " -o : Set the value of program counter to . (default = 0)\n" " -s : Set the number of bytes to skip before disassembly to .\n" " -c : Set the number of bytes to disassemble to .\n" " -x : Set the input mode to whitespace separated 8-bit numbers in\n" " hexadecimal representation. Example: 0f 01 ae 00\n" " -noff : Do not display the offset of instructions.\n" " -nohex : Do not display the hexadecimal code of instructions.\n" " -eflags : Display information on EFLAGS register.\n" " -access : Display access information of operand.\n" " -implicit : Display implicit registers used or modified by the instruction.\n" " -h : Display this help message.\n" " --version : Show version.\n" "\n" "Udcli is a front-end to the Udis86 Disassembler Library.\n" "http://udis86.sourceforge.net/\n" }; extern const char* ud_reg_tab[]; FILE* fptr = NULL; uint64_t o_skip = 0; uint64_t o_count = 0; unsigned char o_do_count= 0; unsigned char o_do_off = 1; unsigned char o_do_hex = 1; unsigned char o_do_x = 0; unsigned char o_do_eflags = 0; unsigned char o_do_access = 0; unsigned char o_do_implicit = 0; unsigned o_vendor = UD_VENDOR_AMD; int input_hook_x(ud_t* u); int input_hook_file(ud_t* u); void print_flag(enum ud_eflag_state flag) { switch(flag) { case UD_FLAG_UNCHANGED: printf("_"); break; case UD_FLAG_TESTED: printf("T"); break; case UD_FLAG_MODIFIED: printf("M"); break; case UD_FLAG_RESET: printf("R"); break; case UD_FLAG_SET: printf("S"); break; case UD_FLAG_UNDEFINED: printf("U"); break; case UD_FLAG_PRIOR: printf("P"); break; } } void print_eflags(const struct ud_eflags *state) { printf("of:"); print_flag(state->flag[UD_FLAG_OF]); printf(" "); printf("sf:"); print_flag(state->flag[UD_FLAG_SF]); printf(" "); printf("zf:"); print_flag(state->flag[UD_FLAG_ZF]); printf(" "); printf("af:"); print_flag(state->flag[UD_FLAG_AF]); printf(" "); printf("pf:"); print_flag(state->flag[UD_FLAG_PF]); printf(" "); printf("cf:"); print_flag(state->flag[UD_FLAG_CF]); printf(" "); printf("tf:"); print_flag(state->flag[UD_FLAG_TF]); printf(" "); printf("if:"); print_flag(state->flag[UD_FLAG_IF]); printf(" "); printf("df:"); print_flag(state->flag[UD_FLAG_DF]); printf(" "); printf("nf:"); print_flag(state->flag[UD_FLAG_NF]); printf(" "); printf("rf:"); print_flag(state->flag[UD_FLAG_RF]); printf(" "); printf("ac:"); print_flag(state->flag[UD_FLAG_AC]); } int main(int argc, char **argv) { char *prog_path = *argv; char *s; ud_t ud_obj; int i; /* initialize */ ud_init(&ud_obj); ud_set_mode(&ud_obj, 32); ud_set_syntax(&ud_obj, UD_SYN_INTEL); #ifdef __DJGPP__ if ( !isatty( fileno( stdin ) ) ) #endif #if defined(__DJGPP) || defined(_WIN32) _setmode(_fileno(stdin), _O_BINARY); #endif fptr = stdin; argv++; /* loop through the args */ while(--argc > 0) { if (strcmp(*argv, "-h") == 0) { printf(help, prog_path); exit(EXIT_SUCCESS); } else if (strcmp(*argv,"-16") == 0) { ud_set_mode(&ud_obj, 16); } else if (strcmp(*argv,"-32") == 0) { ud_set_mode(&ud_obj, 32); } else if (strcmp(*argv,"-64") == 0) { ud_set_mode(&ud_obj, 64); } else if (strcmp(*argv,"-intel") == 0) ud_set_syntax(&ud_obj, UD_SYN_INTEL); else if (strcmp(*argv,"-att") == 0) ud_set_syntax(&ud_obj, UD_SYN_ATT); else if (strcmp(*argv,"-noff") == 0) o_do_off = 0; else if (strcmp(*argv,"-nohex") == 0) o_do_hex = 0; else if (strcmp(*argv,"-eflags") == 0) o_do_eflags = 1; else if (strcmp(*argv,"-access") == 0) o_do_access = 1; else if (strcmp(*argv,"-implicit") == 0) o_do_implicit = 1; else if (strcmp(*argv,"-x") == 0) o_do_x = 1; else if (strcmp(*argv,"-s") == 0) if (--argc) { s = *(++argv); if (sscanf(s, "%" FMT64 "u", &o_skip) == 0) fprintf(stderr, "Invalid value given for -s.\n"); } else { fprintf(stderr, "No value given for -s.\n"); printf(help, prog_path); exit(EXIT_FAILURE); } else if (strcmp(*argv,"-c") == 0) if (--argc) { o_do_count= 1; s = *(++argv); if (sscanf(s, "%" FMT64 "u", &o_count) == 0) fprintf(stderr, "Invalid value given for -c.\n"); } else { fprintf(stderr, "No value given for -c.\n"); printf(help, prog_path); exit(EXIT_FAILURE); } else if (strcmp(*argv,"-v") == 0) if (--argc) { s = *(++argv); if (*s == 'i') ud_set_vendor(&ud_obj, UD_VENDOR_INTEL); } else { fprintf(stderr, "No value given for -v.\n"); printf(help, prog_path); exit(EXIT_FAILURE); } else if (strcmp(*argv,"-o") == 0) { if (--argc) { uint64_t pc = 0; s = *(++argv); if (sscanf(s, "%" FMT64 "x", &pc) == 0) fprintf(stderr, "Invalid value given for -o.\n"); ud_set_pc(&ud_obj, pc); } else { fprintf(stderr, "No value given for -o.\n"); printf(help, prog_path); exit(EXIT_FAILURE); } } else if ( strcmp( *argv, "--version" ) == 0 ) { fprintf(stderr, "%s\n", PACKAGE_STRING ); exit(0); } else if((*argv)[0] == '-') { fprintf(stderr, "Invalid option %s.\n", *argv); printf(help, prog_path); exit(EXIT_FAILURE); } else { static int i = 0; s = *argv; if (i) { fprintf(stderr, "Multiple files specified.\n"); exit(EXIT_FAILURE); } else i = 1; if ((fptr = fopen(s, "rb")) == NULL) { fprintf(stderr, "Failed to open file: %s.\n", s); exit(EXIT_FAILURE); } } argv++; } if (o_do_x) ud_set_input_hook(&ud_obj, input_hook_x); else ud_set_input_hook(&ud_obj, input_hook_file); if (o_skip) { o_count += o_skip; ud_input_skip(&ud_obj, o_skip); } // Note: I use another variable, because I plan to add // other options in the future. Hence, o_do_meta holds // the information about if we have to display any // metadata. unsigned char o_do_meta = o_do_eflags | o_do_access | o_do_implicit; /* disassembly loop */ while (ud_disassemble(&ud_obj)) { if (o_do_off) printf("%016" FMT64 "x ", ud_insn_off(&ud_obj)); if (o_do_hex) { const char* hex1, *hex2; hex1 = ud_insn_hex(&ud_obj); hex2 = hex1 + 16; printf("%-16.16s %-24s", hex1, ud_insn_asm(&ud_obj)); if (strlen(hex1) > 16) { printf("\n"); if (o_do_off) printf("%15s -", ""); printf("%-16s", hex2); } } else printf(" %-24s", ud_insn_asm(&ud_obj)); if (o_do_meta) { printf(" ; "); if (o_do_eflags) { const struct ud_eflags* eflags = ud_lookup_eflags(&ud_obj); print_eflags(eflags); } if (o_do_access) { o_do_access = 0; for (i=0; i<4; i++) { const struct ud_operand *op = ud_insn_opr(&ud_obj, i); if (op != NULL) { if (i == 0) { if (o_do_eflags) printf(", "); printf("access"); o_do_access = 1; } printf(" op%d=", i); if (op->access == UD_OP_ACCESS_READ) printf("R"); else if (op->access == UD_OP_ACCESS_WRITE) printf("W"); else if (op->access == (UD_OP_ACCESS_READ|UD_OP_ACCESS_WRITE)) printf("RW"); else printf("-"); } } } if (o_do_implicit) { if (o_do_eflags | o_do_access) printf(", "); const enum ud_type *imp_used = ud_lookup_implicit_reg_used_list(&ud_obj); const enum ud_type *imp_modified = ud_lookup_implicit_reg_defined_list(&ud_obj); printf("implicit reg used:"); if (imp_used == NULL || *imp_used == UD_NONE) { printf(" none"); } while (*imp_used != UD_NONE) { printf(" %s", ud_reg_tab[*imp_used++ - 1]); } printf(", implicit reg modified:"); if (imp_modified == NULL || *imp_modified == UD_NONE) { printf(" none"); } while (*imp_modified != UD_NONE) { printf(" %s", ud_reg_tab[*imp_modified++ - 1]); } } } printf("\n"); } exit(EXIT_SUCCESS); return 0; } int input_hook_x(ud_t* u) { unsigned int c, i; if (o_do_count) { if (! o_count) return UD_EOI; else --o_count; } i = fscanf(fptr, "%x", &c); if (i == EOF) return UD_EOI; if (i == 0) { fprintf(stderr, "Error: Invalid input, should be in hexadecimal form (8-bit).\n"); return UD_EOI; } if (c > 0xFF) fprintf(stderr, "Warning: Casting non-8-bit input (%x), to %x.\n", c, c & 0xFF); return (int) (c & 0xFF); } int input_hook_file(ud_t* u) { int c; if (o_do_count) { if (! o_count) { return -1; } else o_count -- ; } if ((c = fgetc(fptr)) == EOF) return UD_EOI; return c; } libudis86-0+20221013/udis86.h000066400000000000000000000030221457133061200152040ustar00rootroot00000000000000/* udis86 - udis86.h * * Copyright (c) 2002-2009 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UDIS86_H #define UDIS86_H #include "libudis86/types.h" #include "libudis86/extern.h" #include "libudis86/itab.h" #endif libudis86-0+20221013/udis86.pc.in000066400000000000000000000003051457133061200157650ustar00rootroot00000000000000prefix=@prefix@ exec_prefix=${prefix} libdir=${exec_prefix}/lib includedir=${prefix}/include Name: udis86 Description: udis86 Version: @VERSION@ Libs: -L${libdir} -ludis86 Cflags: -I${includedir} libudis86-0+20221013/xcode/000077500000000000000000000000001457133061200150165ustar00rootroot00000000000000libudis86-0+20221013/xcode/udcli/000077500000000000000000000000001457133061200161165ustar00rootroot00000000000000libudis86-0+20221013/xcode/udcli/sample_input000066400000000000000000000000161457133061200205360ustar00rootroot00000000000000C4 E2 7D 18 C0libudis86-0+20221013/xcode/udcli/udcli.xcodeproj/000077500000000000000000000000001457133061200212125ustar00rootroot00000000000000libudis86-0+20221013/xcode/udcli/udcli.xcodeproj/project.pbxproj000066400000000000000000000211771457133061200242760ustar00rootroot00000000000000// !$*UTF8*$! { archiveVersion = 1; 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