pax_global_header00006660000000000000000000000064141422716460014521gustar00rootroot0000000000000052 comment=f9ae3f235183c452962edd2a15384bdc67f7a11e RandomX-1.1.10/000077500000000000000000000000001414227164600131515ustar00rootroot00000000000000RandomX-1.1.10/CMakeLists.txt000066400000000000000000000174771414227164600157310ustar00rootroot00000000000000# Copyright (c) 2019, The Monero Project # # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, are # permitted provided that the following conditions are met: # # 1. Redistributions of source code must retain the above copyright notice, this list of # conditions and the following disclaimer. # # 2. Redistributions in binary form must reproduce the above copyright notice, this list # of conditions and the following disclaimer in the documentation and/or other # materials provided with the distribution. # # 3. Neither the name of the copyright holder nor the names of its contributors may be # used to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY # EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL # THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, # STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF # THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. cmake_minimum_required(VERSION 3.5) project(RandomX) set(randomx_sources src/aes_hash.cpp src/argon2_ref.c src/argon2_ssse3.c src/argon2_avx2.c src/bytecode_machine.cpp src/cpu.cpp src/dataset.cpp src/soft_aes.cpp src/virtual_memory.cpp src/vm_interpreted.cpp src/allocator.cpp src/assembly_generator_x86.cpp src/instruction.cpp src/randomx.cpp src/superscalar.cpp src/vm_compiled.cpp src/vm_interpreted_light.cpp src/argon2_core.c src/blake2_generator.cpp src/instructions_portable.cpp src/reciprocal.c src/virtual_machine.cpp src/vm_compiled_light.cpp src/blake2/blake2b.c) if(NOT ARCH_ID) # allow cross compiling if(CMAKE_SYSTEM_PROCESSOR STREQUAL "") set(CMAKE_SYSTEM_PROCESSOR ${CMAKE_HOST_SYSTEM_PROCESSOR}) endif() string(TOLOWER "${CMAKE_SYSTEM_PROCESSOR}" ARCH_ID) endif() if(NOT ARM_ID) set(ARM_ID "${ARCH_ID}") endif() if(NOT ARCH) set(ARCH "default") endif() if(NOT CMAKE_BUILD_TYPE) set(CMAKE_BUILD_TYPE Release) message(STATUS "Setting default build type: ${CMAKE_BUILD_TYPE}") endif() include(CheckCXXCompilerFlag) include(CheckCCompilerFlag) function(add_flag flag) string(REPLACE "-" "_" supported_cxx ${flag}_cxx) check_cxx_compiler_flag(${flag} ${supported_cxx}) if(${${supported_cxx}}) message(STATUS "Setting CXX flag ${flag}") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${flag}" PARENT_SCOPE) endif() string(REPLACE "-" "_" supported_c ${flag}_c) check_c_compiler_flag(${flag} ${supported_c}) if(${${supported_c}}) message(STATUS "Setting C flag ${flag}") set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) endif() endfunction() # x86-64 if(ARCH_ID STREQUAL "x86_64" OR ARCH_ID STREQUAL "x86-64" OR ARCH_ID STREQUAL "amd64") list(APPEND randomx_sources src/jit_compiler_x86.cpp) if(MSVC) enable_language(ASM_MASM) list(APPEND randomx_sources src/jit_compiler_x86_static.asm) set_property(SOURCE src/jit_compiler_x86_static.asm PROPERTY LANGUAGE ASM_MASM) set_source_files_properties(src/argon2_avx2.c COMPILE_FLAGS /arch:AVX2) set(CMAKE_C_FLAGS_RELWITHDEBINFO "${CMAKE_C_FLAGS_RELWITHDEBINFO} /DRELWITHDEBINFO") set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} /DRELWITHDEBINFO") add_custom_command(OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/src/asm/configuration.asm COMMAND powershell -ExecutionPolicy Bypass -File h2inc.ps1 ..\\src\\configuration.h > ..\\src\\asm\\configuration.asm SET ERRORLEVEL = 0 COMMENT "Generating configuration.asm at ${CMAKE_CURRENT_SOURCE_DIR}" WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/vcxproj) add_custom_target(generate-asm DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/src/asm/configuration.asm) else() list(APPEND randomx_sources src/jit_compiler_x86_static.S) # cheat because cmake and ccache hate each other set_property(SOURCE src/jit_compiler_x86_static.S PROPERTY LANGUAGE C) set_property(SOURCE src/jit_compiler_x86_static.S PROPERTY XCODE_EXPLICIT_FILE_TYPE sourcecode.asm) if(ARCH STREQUAL "native") add_flag("-march=native") else() # default build has hardware AES enabled (software AES can be selected at runtime) add_flag("-maes") check_c_compiler_flag(-mssse3 HAVE_SSSE3) if(HAVE_SSSE3) set_source_files_properties(src/argon2_ssse3.c COMPILE_FLAGS -mssse3) endif() check_c_compiler_flag(-mavx2 HAVE_AVX2) if(HAVE_AVX2) set_source_files_properties(src/argon2_avx2.c COMPILE_FLAGS -mavx2) endif() endif() endif() endif() # PowerPC if(ARCH_ID STREQUAL "ppc64" OR ARCH_ID STREQUAL "ppc64le") if(ARCH STREQUAL "native") add_flag("-mcpu=native") endif() # PowerPC AES requires ALTIVEC (POWER7+), so it cannot be enabled in the default build endif() # ARMv8 if(ARM_ID STREQUAL "aarch64" OR ARM_ID STREQUAL "arm64" OR ARM_ID STREQUAL "armv8-a") list(APPEND randomx_sources src/jit_compiler_a64_static.S src/jit_compiler_a64.cpp) # cheat because cmake and ccache hate each other set_property(SOURCE src/jit_compiler_a64_static.S PROPERTY LANGUAGE C) set_property(SOURCE src/jit_compiler_a64_static.S PROPERTY XCODE_EXPLICIT_FILE_TYPE sourcecode.asm) # not sure if this check is needed include(CheckIncludeFile) check_include_file(asm/hwcap.h HAVE_HWCAP) if(HAVE_HWCAP) add_definitions(-DHAVE_HWCAP) endif() if(ARCH STREQUAL "native") add_flag("-march=native") else() # default build has hardware AES enabled (software AES can be selected at runtime) add_flag("-march=armv8-a+crypto") endif() endif() set(RANDOMX_INCLUDE "${CMAKE_CURRENT_SOURCE_DIR}/src" CACHE STRING "RandomX Include path") add_library(randomx ${randomx_sources}) if(TARGET generate-asm) add_dependencies(randomx generate-asm) endif() set_property(TARGET randomx PROPERTY POSITION_INDEPENDENT_CODE ON) set_property(TARGET randomx PROPERTY CXX_STANDARD 11) set_property(TARGET randomx PROPERTY CXX_STANDARD_REQUIRED ON) set_property(TARGET randomx PROPERTY PUBLIC_HEADER src/randomx.h) include(GNUInstallDirs) install(TARGETS randomx LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) add_executable(randomx-tests src/tests/tests.cpp) target_link_libraries(randomx-tests PRIVATE randomx) set_property(TARGET randomx-tests PROPERTY POSITION_INDEPENDENT_CODE ON) set_property(TARGET randomx-tests PROPERTY CXX_STANDARD 11) add_executable(randomx-codegen src/tests/code-generator.cpp) target_link_libraries(randomx-codegen PRIVATE randomx) set_property(TARGET randomx-codegen PROPERTY POSITION_INDEPENDENT_CODE ON) set_property(TARGET randomx-codegen PROPERTY CXX_STANDARD 11) if(NOT Threads_FOUND AND UNIX AND NOT APPLE) set(THREADS_PREFER_PTHREAD_FLAG ON) find_package(Threads) endif() add_executable(randomx-benchmark src/tests/benchmark.cpp src/tests/affinity.cpp) target_link_libraries(randomx-benchmark PRIVATE randomx PRIVATE ${CMAKE_THREAD_LIBS_INIT}) include(CheckCXXSourceCompiles) check_cxx_source_compiles(" #include #include int main() { std::atomic a; a.is_lock_free(); }" HAVE_CXX_ATOMICS) if(NOT HAVE_CXX_ATOMICS) target_link_libraries(randomx-benchmark PRIVATE "atomic") endif() set_property(TARGET randomx-benchmark PROPERTY POSITION_INDEPENDENT_CODE ON) set_property(TARGET randomx-benchmark PROPERTY CXX_STANDARD 11) RandomX-1.1.10/LICENSE000066400000000000000000000030311414227164600141530ustar00rootroot00000000000000Copyright (c) 2018-2019, tevador Copyright (c) 2014-2019, The Monero Project All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. RandomX-1.1.10/README.md000066400000000000000000000225241414227164600144350ustar00rootroot00000000000000# RandomX RandomX is a proof-of-work (PoW) algorithm that is optimized for general-purpose CPUs. RandomX uses random code execution (hence the name) together with several memory-hard techniques to minimize the efficiency advantage of specialized hardware. ## Overview RandomX utilizes a virtual machine that executes programs in a special instruction set that consists of integer math, floating point math and branches. These programs can be translated into the CPU's native machine code on the fly (example: [program.asm](doc/program.asm)). At the end, the outputs of the executed programs are consolidated into a 256-bit result using a cryptographic hashing function ([Blake2b](https://blake2.net/)). RandomX can operate in two main modes with different memory requirements: * **Fast mode** - requires 2080 MiB of shared memory. * **Light mode** - requires only 256 MiB of shared memory, but runs significantly slower Both modes are interchangeable as they give the same results. The fast mode is suitable for "mining", while the light mode is expected to be used only for proof verification. ## Documentation Full specification is available in [specs.md](doc/specs.md). Design description and analysis is available in [design.md](doc/design.md). ## Audits Between May and August 2019, RandomX was audited by 4 independent security research teams: * [Trail of Bits](https://www.trailofbits.com/) (28 000 USD) * [X41 D-SEC](https://www.x41-dsec.de/) (42 000 EUR) * [Kudelski Security](https://www.kudelskisecurity.com/) (18 250 CHF) * [QuarksLab](https://quarkslab.com/en/) (52 800 USD) The first audit was generously funded by [Arweave](https://www.arweave.org/), one of the early adopters of RandomX. The remaining three audits were funded by donations from the [Monero community](https://ccs.getmonero.org/proposals/RandomX-audit.html). All four audits were coordinated by [OSTIF](https://ostif.org/). Final reports from all four audits are available in the [audits](audits/) directory. None of the audits found any critical vulnerabilities, but several changes in the algorithm and the code were made as a direct result of the audits. More details can be found in the [final report by OSTIF](https://ostif.org/four-audits-of-randomx-for-monero-and-arweave-have-been-completed-results/). ## Build RandomX is written in C++11 and builds a static library with a C API provided by header file [randomx.h](src/randomx.h). Minimal API usage example is provided in [api-example1.c](src/tests/api-example1.c). The reference code includes a `randomx-benchmark` and `randomx-tests` executables for testing. ### Linux Build dependencies: `cmake` (minimum 2.8.7) and `gcc` (minimum version 4.8, but version 7+ is recommended). To build optimized binaries for your machine, run: ``` git clone https://github.com/tevador/RandomX.git cd RandomX mkdir build && cd build cmake -DARCH=native .. make ``` To build portable binaries, omit the `ARCH` option when executing cmake. ### Windows On Windows, it is possible to build using MinGW (same procedure as on Linux) or using Visual Studio (solution file is provided). ### Precompiled binaries Precompiled `randomx-benchmark` binaries are available on the [Releases page](https://github.com/tevador/RandomX/releases). ## Proof of work RandomX was primarily designed as a PoW algorithm for [Monero](https://www.getmonero.org/). The recommended usage is following: * The key `K` is selected to be the hash of a block in the blockchain - this block is called the 'key block'. For optimal mining and verification performance, the key should change every 2048 blocks (~2.8 days) and there should be a delay of 64 blocks (~2 hours) between the key block and the change of the key `K`. This can be achieved by changing the key when `blockHeight % 2048 == 64` and selecting key block such that `keyBlockHeight % 2048 == 0`. * The input `H` is the standard hashing blob with a selected nonce value. RandomX was successfully activated on the Monero network on the 30th November 2019. If you wish to use RandomX as a PoW algorithm for your cryptocurrency, please follow the [configuration guidelines](doc/configuration.md). **Note**: To achieve ASIC resistance, the key `K` must change and must not be miner-selectable. We recommend to use blockchain data as the key in a similar way to the Monero example above. If blockchain data cannot be used for some reason, use a predefined sequence of keys. ### CPU performance The table below lists the performance of selected CPUs using the optimal number of threads (T) and large pages (if possible), in hashes per second (H/s). "CNv4" refers to the CryptoNight variant 4 (CN/R) hashrate measured using [XMRig](https://github.com/xmrig/xmrig) v2.14.1. "Fast mode" and "Light mode" are the two modes of RandomX. |CPU|RAM|OS|AES|CNv4|Fast mode|Light mode| |---|---|--|---|-----|------|--------------| Intel Core i9-9900K|32G DDR4-3200|Windows 10|hw|660 (8T)|5770 (8T)|1160 (16T)| AMD Ryzen 7 1700|16G DDR4-2666|Ubuntu 16.04|hw|520 (8T)|4100 (8T)|620 (16T)| Intel Core i7-8550U|16G DDR4-2400|Windows 10|hw|200 (4T)|1700 (4T)|350 (8T)| Intel Core i3-3220|4G DDR3-1333|Ubuntu 16.04|soft|42 (4T)|510 (4T)|150 (4T)| Raspberry Pi 3|1G LPDDR2|Ubuntu 16.04|soft|3.5 (4T)|-|20 (4T)| Note that RandomX currently includes a JIT compiler for x86-64 and ARM64. Other architectures have to use the portable interpreter, which is much slower. ### GPU performance SChernykh is developing GPU mining code for RandomX. Benchmarks are included in the following repositories: * [CUDA miner](https://github.com/SChernykh/RandomX_CUDA) - NVIDIA GPUs. * [OpenCL miner](https://github.com/SChernykh/RandomX_OpenCL) - only for AMD Vega and AMD Polaris GPUs (uses GCN machine code). The code from the above repositories is included in the open source miner [XMRig](https://github.com/xmrig/xmrig). Note that GPUs are at a disadvantage when running RandomX since the algorithm was designed to be efficient on CPUs. # FAQ ### Which CPU is best for mining RandomX? Most Intel and AMD CPUs made since 2011 should be fairly efficient at RandomX. More specifically, efficient mining requires: * 64-bit architecture * IEEE 754 compliant floating point unit * Hardware AES support ([AES-NI](https://en.wikipedia.org/wiki/AES_instruction_set) extension for x86, Cryptography extensions for ARMv8) * 16 KiB of L1 cache, 256 KiB of L2 cache and 2 MiB of L3 cache per mining thread * Support for large memory pages * At least 2.5 GiB of free RAM per NUMA node * Multiple memory channels may be required: * DDR3 memory is limited to about 1500-2000 H/s per channel (depending on frequency and timings) * DDR4 memory is limited to about 4000-6000 H/s per channel (depending on frequency and timings) ### Does RandomX facilitate botnets/malware mining or web mining? Due to the way the algorithm works, mining malware is much easier to detect. [RandomX Sniffer](https://github.com/tevador/randomx-sniffer) is a proof of concept tool that can detect illicit mining activity on Windows. Efficient mining requires more than 2 GiB of memory, which also disqualifies many low-end machines such as IoT devices, which are often parts of large botnets. Web mining is infeasible due to the large memory requirement and the lack of directed rounding support for floating point operations in both Javascript and WebAssembly. ### Since RandomX uses floating point math, does it give reproducible results on different platforms? RandomX uses only operations that are guaranteed to give correctly rounded results by the [IEEE 754](https://en.wikipedia.org/wiki/IEEE_754) standard: addition, subtraction, multiplication, division and square root. Special care is taken to avoid corner cases such as NaN values or denormals. The reference implementation has been validated on the following platforms: * x86 (32-bit, little-endian) * x86-64 (64-bit, little-endian) * ARMv7+VFPv3 (32-bit, little-endian) * ARMv8 (64-bit, little-endian) * PPC64 (64-bit, big-endian) ### Can FPGAs mine RandomX? RandomX generates multiple unique programs for every hash, so FPGAs cannot dynamically reconfigure their circuitry because typical FPGA takes tens of seconds to load a bitstream. It is also not possible to generate bitstreams for RandomX programs in advance due to the sheer number of combinations (there are 2512 unique programs). Sufficiently large FPGAs can mine RandomX in a [soft microprocessor](https://en.wikipedia.org/wiki/Soft_microprocessor) configuration by emulating a CPU. Under these circumstances, an FPGA will be much less efficient than a CPU or a specialized chip (ASIC). ## Acknowledgements * [tevador](https://github.com/tevador) - author * [SChernykh](https://github.com/SChernykh) - contributed significantly to the design of RandomX * [hyc](https://github.com/hyc) - original idea of using random code execution for PoW * [Other contributors](https://github.com/tevador/RandomX/graphs/contributors) RandomX uses some source code from the following 3rd party repositories: * Argon2d, Blake2b hashing functions: https://github.com/P-H-C/phc-winner-argon2 The author of RandomX declares no competing financial interest. ## Donations If you'd like to use RandomX, please consider donating to help cover the development cost of the algorithm. Author's XMR address: ``` 845xHUh5GvfHwc2R8DVJCE7BT2sd4YEcmjG8GNSdmeNsP5DTEjXd1CNgxTcjHjiFuthRHAoVEJjM7GyKzQKLJtbd56xbh7V ``` Total donations received: ~3.86 XMR (as of 30th August 2019). Thanks to all contributors. RandomX-1.1.10/doc/000077500000000000000000000000001414227164600137165ustar00rootroot00000000000000RandomX-1.1.10/doc/configuration.md000066400000000000000000000245061414227164600171160ustar00rootroot00000000000000# RandomX configuration RandomX has 45 customizable parameters (see table below). We recommend each project using RandomX to select a unique configuration to prevent network attacks from hashpower rental services. These parameters can be modified in source file [configuration.h](../src/configuration.h). |parameter|description|default value| |---------|-----|-------| |`RANDOMX_ARGON_MEMORY`|The number of 1 KiB Argon2 blocks in the Cache| `262144`| |`RANDOMX_ARGON_ITERATIONS`|The number of Argon2d iterations for Cache initialization|`3`| |`RANDOMX_ARGON_LANES`|The number of parallel lanes for Cache initialization|`1`| |`RANDOMX_ARGON_SALT`|Argon2 salt|`"RandomX\x03"`| |`RANDOMX_CACHE_ACCESSES`|The number of random Cache accesses per Dataset item|`8`| |`RANDOMX_SUPERSCALAR_LATENCY`|Target latency for SuperscalarHash (in cycles of the reference CPU)|`170`| |`RANDOMX_DATASET_BASE_SIZE`|Dataset base size in bytes|`2147483648`| |`RANDOMX_DATASET_EXTRA_SIZE`|Dataset extra size in bytes|`33554368`| |`RANDOMX_PROGRAM_SIZE`|The number of instructions in a RandomX program|`256`| |`RANDOMX_PROGRAM_ITERATIONS`|The number of iterations per program|`2048`| |`RANDOMX_PROGRAM_COUNT`|The number of programs per hash|`8`| |`RANDOMX_JUMP_BITS`|Jump condition mask size in bits|`8`| |`RANDOMX_JUMP_OFFSET`|Jump condition mask offset in bits|`8`| |`RANDOMX_SCRATCHPAD_L3`|Scratchpad size in bytes|`2097152`| |`RANDOMX_SCRATCHPAD_L2`|Scratchpad L2 size in bytes|`262144`| |`RANDOMX_SCRATCHPAD_L1`|Scratchpad L1 size in bytes|`16384`| |`RANDOMX_FREQ_*` (29x)|Instruction frequencies|multiple values| Not all of the parameters can be changed safely and most parameters have some contraints on what values can be selected (checked at compile-time). **Disclaimer: The compile-time checks only prevent obviously broken configurations. Passing the checks does not imply that the configuration is safe and will not cause crashes or other issues. We recommend that each non-standard configuration is thoroughly tested before being deployed.** ### RANDOMX_ARGON_MEMORY This parameter determines the amount of memory needed in the light mode. Memory is specified in KiB (1 KiB = 1024 bytes). #### Permitted values Integer powers of 2 in the range 8 - 2097152. #### Notes Lower sizes will reduce the memory-hardness of the algorithm. ### RANDOMX_ARGON_ITERATIONS Determines the number of passes of Argon2 that are used to generate the Cache. #### Permitted values Any positive 32-bit integer. #### Notes The time needed to initialize the Cache is proportional to the value of this constant. ### RANDOMX_ARGON_LANES The number of parallel lanes for Cache initialization. #### Permitted values Integers in the range 1 - 16777215. #### Notes This parameter determines how many threads can be used for Cache initialization. ### RANDOMX_ARGON_SALT Salt value for Cache initialization. #### Permitted values A string of at least 8 characters. #### Note Every implementation should choose a unique salt value. ### RANDOMX_CACHE_ACCESSES The number of random Cache access per Dataset item. #### Permitted values Any integer greater than 1. #### Notes This value directly determines the performance ratio between the 'fast' and 'light' modes. ### RANDOMX_SUPERSCALAR_LATENCY Target latency for SuperscalarHash, in cycles of the reference CPU. #### Permitted values Integers in the range 1 - 10000. #### Notes The default value was tuned so that a high-performance superscalar CPU running at 2-4 GHz will execute SuperscalarHash in similar time it takes to load data from RAM (40-80 ns). Using a lower value will make Dataset generation (and light mode) more memory bound, while increasing this value will make Dataset generation (and light mode) more compute bound. ### RANDOMX_DATASET_BASE_SIZE Dataset base size in bytes. #### Permitted values Integer powers of 2 in the range 64 - 4294967296 (inclusive). #### Note This constant affects the memory requirements in fast mode. Some values are unsafe depending on other parameters. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_DATASET_EXTRA_SIZE Dataset extra size in bytes. #### Permitted values Non-negative integer divisible by 64. #### Note This constant affects the memory requirements in fast mode. Some values are unsafe depending on other parameters. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_PROGRAM_SIZE The number of instructions in a RandomX program. #### Permitted values Positive integers divisible by 8 in the range 8 - 32768 (inclusive). #### Notes Smaller values will make RandomX more DRAM-latency bound, while higher values will make RandomX more compute-bound. Some values are unsafe. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_PROGRAM_ITERATIONS The number of iterations per program. #### Permitted values Any positive integer. #### Notes Time per hash increases linearly with this constant. Smaller values will increase the overhead of program compilation, while larger values may allow more time for optimizations. Some values are unsafe. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_PROGRAM_COUNT The number of programs per hash. #### Permitted values Any positive integer. #### Notes Time per hash increases linearly with this constant. Some values are unsafe. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_JUMP_BITS Jump condition mask size in bits. #### Permitted values Positive integers. The sum of `RANDOMX_JUMP_BITS` and `RANDOMX_JUMP_OFFSET` must not exceed 16. #### Notes This determines the jump probability of the CBRANCH instruction. The default value of 8 results in jump probability of 1/28 = 1/256. Increasing this constant will decrease the rate of jumps (and vice versa). ### RANDOMX_JUMP_OFFSET Jump condition mask offset in bits. #### Permitted values Non-negative integers. The sum of `RANDOMX_JUMP_BITS` and `RANDOMX_JUMP_OFFSET` must not exceed 16. #### Notes Since the low-order bits of RandomX registers are slightly biased, this offset moves the condition mask to higher bits, which are less biased. Using values smaller than the default may result in a slightly lower jump probability than the theoretical value calculated from `RANDOMX_JUMP_BITS`. ### RANDOMX_SCRATCHPAD_L3 RandomX Scratchpad size in bytes. #### Permitted values Any integer power of 2. Must be larger than or equal to `RANDOMX_SCRATCHPAD_L2`. #### Notes The default value of 2 MiB was selected to match the typical cache/core ratio of desktop processors. Using a lower value will make RandomX more core-bound, while using larger values will make the algorithm more latency-bound. Some values are unsafe depending on other parameters. See [Unsafe configurations](#unsafe-configurations). ### RANDOMX_SCRATCHPAD_L2 Scratchpad L2 size in bytes. #### Permitted values Any integer power of 2. Must be larger than or equal to `RANDOMX_SCRATCHPAD_L1`. #### Notes The default value of 256 KiB was selected to match the typical per-core L2 cache size of desktop processors. Using a lower value will make RandomX more core-bound, while using larger values will make the algorithm more latency-bound. ### RANDOMX_SCRATCHPAD_L1 Scratchpad L1 size in bytes. #### Permitted values Any integer power of 2. The minimum is 64 bytes. #### Notes The default value of 16 KiB was selected to be about half of the per-core L1 cache size of desktop processors. Using a lower value will make RandomX more core-bound, while using larger values will make the algorithm more latency-bound. ### RANDOMX_FREQ_* Instruction frequencies (per 256 instructions). #### Permitted values There is a total of 29 different instructions. The sum of frequencies must be equal to 256. #### Notes Making changes to the default values is not recommended. The only exceptions are the instruction pairs IROR_R/IROL_R, FADD_R/FSUB_R and FADD_M/FSUB_M, which are functionally equivalent. Example of a safe custom configuration: ||default|custom| |-|------|------|-| |`RANDOMX_FREQ_IROR_R`|8|5| |`RANDOMX_FREQ_IROL_R`|2|5| ||default|custom| |-|------|------| |`RANDOMX_FREQ_FADD_R`|16|17| |`RANDOMX_FREQ_FSUB_R`|16|15| ||default|custom| |-|------|------| |`RANDOMX_FREQ_FADD_M`|5|4| |`RANDOMX_FREQ_FSUB_M`|5|6| ## Unsafe configurations There are some configurations that are considered 'unsafe' because they affect the security of the algorithm against attacks. If the conditions listed below are not satisfied, the configuration is unsafe and a compilation error is emitted when building the RandomX library. These checks can be disabled by definining `RANDOMX_UNSAFE` when building RandomX, e.g. by using `-DRANDOMX_UNSAFE` command line switch in GCC or MSVC. It is not recommended to disable these checks except for testing purposes. ### 1. Memory-time tradeoffs #### Condition ```` RANDOMX_CACHE_ACCESSES * RANDOMX_ARGON_MEMORY * 1024 + 33554432 >= RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE ```` Configurations not satisfying this condition are vulnerable to memory-time tradeoffs, which enables efficient mining in light mode. #### Solutions * Increase `RANDOMX_CACHE_ACCESSES` or `RANDOMX_ARGON_MEMORY`. * Decrease `RANDOMX_DATASET_BASE_SIZE` or `RANDOMX_DATASET_EXTRA_SIZE`. ### 2. Insufficient Scratchpad writes #### Condition ```` (128 + RANDOMX_PROGRAM_SIZE * RANDOMX_FREQ_ISTORE / 256) * (RANDOMX_PROGRAM_COUNT * RANDOMX_PROGRAM_ITERATIONS) >= RANDOMX_SCRATCHPAD_L3 ```` Configurations not satisfying this condition are vulnerable to Scratchpad size optimizations due to low amount of writes. #### Solutions * Increase `RANDOMX_PROGRAM_SIZE`, `RANDOMX_FREQ_ISTORE`, `RANDOMX_PROGRAM_COUNT` or `RANDOMX_PROGRAM_ITERATIONS`. * Decrease `RANDOMX_SCRATCHPAD_L3`. ### 3. Program filtering strategies #### Condition ``` RANDOMX_PROGRAM_COUNT > 1 ``` Configurations not satisfying this condition are vulnerable to program filtering strategies. #### Solution * Increase `RANDOMX_PROGRAM_COUNT` to at least 2. ### 4. Low program entropy #### Condition ``` RANDOMX_PROGRAM_SIZE >= 64 ``` Configurations not satisfying this condition do not have a sufficient number of instruction combinations. #### Solution * Increase `RANDOMX_PROGRAM_SIZE` to at least 64. ### 5. High compilation overhead #### Condition ``` RANDOMX_PROGRAM_ITERATIONS >= 400 ``` Configurations not satisfying this condition have a program compilation overhead exceeding 10%. #### Solution * Increase `RANDOMX_PROGRAM_ITERATIONS` to at least 400. RandomX-1.1.10/doc/design.md000066400000000000000000001307711414227164600155220ustar00rootroot00000000000000# RandomX design To minimize the performance advantage of specialized hardware, a proof of work (PoW) algorithm must achieve *device binding* by targeting specific features of existing general-purpose hardware. This is a complex task because we have to target a large class of devices with different architectures from different manufacturers. There are two distinct classes of general processing devices: central processing units (CPUs) and graphics processing units (GPUs). RandomX targets CPUs for the following reasons: * CPUs, being less specialized devices, are more prevalent and widely accessible. A CPU-bound algorithm is more egalitarian and allows more participants to join the network. This is one of the goals stated in the original CryptoNote whitepaper [[1](https://cryptonote.org/whitepaper.pdf)]. * A large common subset of native hardware instructions exists among different CPU architectures. The same cannot be said about GPUs. For example, there is no common integer multiplication instruction for NVIDIA and AMD GPUs [[2](https://github.com/ifdefelse/ProgPOW/issues/16)]. * All major CPU instruction sets are well documented with multiple open source compilers available. In comparison, GPU instruction sets are usually proprietary and may require vendor specific closed-source drivers for maximum performance. ## 1. Design considerations The most basic idea of a CPU-bound proof of work is that the "work" must be dynamic. This takes advantage of the fact that CPUs accept two kinds of inputs: *data* (the main input) and *code* (which specifies what to perform with the data). Conversely, typical cryptographic hashing functions [[3](https://en.wikipedia.org/wiki/Cryptographic_hash_function)] do not represent suitable work for the CPU because their only input is *data*, while the sequence of operations is fixed and can be performed more efficiently by a specialized integrated circuit. ### 1.1 Dynamic proof of work A dynamic proof of work algorithm can generally consist of the following 4 steps: 1) Generate a random program. 2) Translate it into the native machine code of the CPU. 3) Execute the program. 4) Transform the output of the program into a cryptographically secure value. The actual 'useful' CPU-bound work is performed in step 3, so the algorithm must be tuned to minimize the overhead of the remaining steps. #### 1.1.1 Generating a random program Early attempts at a dynamic proof of work design were based on generating a program in a high-level language, such as C or Javascript [[4](https://github.com/hyc/randprog), [5](https://github.com/tevador/RandomJS)]. However, this is very inefficient for two main reasons: * High level languages have a complex syntax, so generating a valid program is relatively slow since it requires the creation of an abstract syntax tree (ASL). * Once the source code of the program is generated, the compiler will generally parse the textual representation back into the ASL, which makes the whole process of generating source code redundant. The fastest way to generate a random program is to use a *logic-less* generator - simply filling a buffer with random data. This of course requires designing a syntaxless programming language (or instruction set) in which all random bit strings represent valid programs. #### 1.1.2 Translating the program into machine code This step is inevitable because we don't want to limit the algorithm to a specific CPU architecture. In order to generate machine code as fast as possible, we need our instruction set to be as close to native hardware as possible, while still generic enough to support different architectures. There is not enough time for expensive optimizations during code compilation. #### 1.1.3 Executing the program The actual program execution should utilize as many CPU components as possible. Some of the features that should be utilized in the program are: * multi-level caches (L1, L2, L3) * μop cache [[6](https://en.wikipedia.org/wiki/CPU_cache#Micro-operation_(%CE%BCop_or_uop)_cache)] * arithmetic logic unit (ALU) * floating point unit (FPU) * memory controller * instruction level parallelism [[7](https://en.wikipedia.org/wiki/Instruction-level_parallelism)] * superscalar execution [[8](https://en.wikipedia.org/wiki/Superscalar_processor)] * out-of-order execution [[9](https://en.wikipedia.org/wiki/Out-of-order_execution)] * speculative execution [[10](https://en.wikipedia.org/wiki/Speculative_execution)] * register renaming [[11](https://en.wikipedia.org/wiki/Register_renaming)] Chapter 2 describes how the RandomX VM takes advantages of these features. #### 1.1.4 Calculating the final result Blake2b [[12](https://blake2.net/)] is a cryptographically secure hashing function that was specifically designed to be fast in software, especially on modern 64-bit processors, where it's around three times faster than SHA-3 and can run at a speed of around 3 clock cycles per byte of input. This function is an ideal candidate to be used in a CPU-friendly proof of work. For processing larger amounts of data in a cryptographically secure way, the Advanced Encryption Standard (AES) [[13](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)] can provide the fastest processing speed because many modern CPUs support hardware acceleration of these operations. See chapter 3 for more details about the use of AES in RandomX. ### 1.2 The "Easy program problem" When a random program is generated, one may choose to execute it only when it's favorable. This strategy is viable for two main reasons: 1. The runtime of randomly generated programs typically follows a log-normal distribution [[14](https://en.wikipedia.org/wiki/Log-normal_distribution)] (also see Appendix C). A generated program may be quickly analyzed and if it's likely to have above-average runtime, program execution may be skipped and a new program may be generated instead. This can significantly boost performance especially in case the runtime distribution has a heavy tail (many long-running outliers) and if program generation is cheap. 2. An implementation may choose to optimize for a subset of the features required for program execution. For example, the support for some operations (such as division) may be dropped or some instruction sequences may be implemented more efficiently. Generated programs would then be analyzed and be executed only if they match the specific requirements of the optimized implementation. These strategies of searching for programs of particular properties deviate from the objectives of this proof of work, so they must be eliminated. This can be achieved by requiring a sequence of *N* random programs to be executed such that each program is generated from the output of the previous one. The output of the final program is then used as the result. ``` +---------------+ +---------------+ +---------------+ +---------------+ | | | | | | | | input --> | program 1 | --> | program 2 | --> ... --> | program (N-1) | --> | program N | --> result | | | | | | | | +---------------+ +---------------+ +---------------+ +---------------+ ``` The principle is that after the first program is executed, a miner has to either commit to finishing the whole chain (which may include unfavorable programs) or start over and waste the effort expended on the unfinished chain. Examples of how this affects the hashrate of different mining strategies are given in Appendix A. Additionally, this chained program execution has the benefit of equalizing the runtime for the whole chain since the relative deviation of a sum of identically distributed runtimes is decreased. ### 1.3 Verification time Since the purpose of the proof of work is to be used in a trustless peer-to-peer network, network participants must be able to quickly verify if a proof is valid or not. This puts an upper bound on the complexity of the proof of work algorithm. In particular, we set a goal for RandomX to be at least as fast to verify as the CryptoNight hash function [[15](https://cryptonote.org/cns/cns008.txt)], which it aims to replace. ### 1.4 Memory-hardness Besides pure computational resources, such as ALUs and FPUs, CPUs usually have access to a large amount of memory in the form of DRAM [[16](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)]. The performance of the memory subsystem is typically tuned to match the compute capabilities, for example [[17](https://en.wikipedia.org/wiki/Multi-channel_memory_architecture)]: * single channel memory for embedded and low power CPUs * dual channel memory for desktop CPUs * triple or quad channel memory for workstation CPUs * six or eight channel memory for high-end server CPUs In order to utilize the external memory as well as the on-chip memory controllers, the proof of work algorithm should access a large memory buffer (called the "Dataset"). The Dataset must be: 1. larger than what can be stored on-chip (to require external memory) 2. dynamic (to require writable memory) The maximum amount of SRAM that can be put on a single chip is more than 512 MiB for a 16 nm process and more than 2 GiB for a 7 nm process [[18](https://www.grin-forum.org/t/obelisk-grn1-chip-details/4571)]. Ideally, the size of the Dataset should be at least 4 GiB. However, due to constraints on the verification time (see below), the size used by RandomX was selected to be 2080 MiB. While a single chip can theoretically be made with this amount of SRAM using current technology (7 nm in 2019), the feasibility of such solution is questionable, at least in the near future. #### 1.4.1 Light-client verification While it's reasonable to require >2 GiB for dedicated mining systems that solve the proof of work, an option must be provided for light clients to verify the proof using a much lower amount of memory. The ratio of memory required for the 'fast' and 'light' modes must be chosen carefully not to make the light mode viable for mining. In particular, the area-time (AT) product of the light mode should not be smaller than the AT product of the fast mode. Reduction of the AT product is a common way of measuring tradeoff attacks [[19](https://eprint.iacr.org/2015/227.pdf)]. Given the constraints described in the previous chapters, the maximum possible performance ratio between the fast and the light verification modes was empirically determined to be 8. This is because: 1. Further increase of the light verification time would violate the constraints set out in chapter 1.3. 2. Further decrease of the fast mode runtime would violate the constraints set out in chapter 1.1, in particular the overhead time of program generation and result calculation would become too high. Additionally, 256 MiB was selected as the maximum amount of memory that can be required in the light-client mode. This amount is acceptable even for small single-board computers such as the Raspberry Pi. To keep a constant memory-time product, the maximum fast-mode memory requirement is: ``` 8 * 256 MiB = 2048 MiB ``` This can be further increased since the light mode requires additional chip area for the SuperscalarHash function (see chapter 3.4 and chapter 6 of the Specification). Assuming a conservative estimate of 0.2 mm2 per SuperscalarHash core and DRAM density of 0.149 Gb/mm2 [[20](http://en.thelec.kr/news/articleView.html?idxno=20)], the additional memory is: ``` 8 * 0.2 * 0.149 * 1024 / 8 = 30.5 MiB ``` or 32 MiB when rounded to the nearest power of 2. The total memory requirement of the fast mode can be 2080 MiB with a roughly constant AT product. ## 2. Virtual machine architecture This section describes the design of the RandomX virtual machine (VM). ### 2.1 Instruction set RandomX uses a fixed-length instruction encoding with 8 bytes per instruction. This allows a 32-bit immediate value to be included in the instruction word. The interpretation of the instruction word bits was chosen so that any 8-byte word is a valid instruction. This allows for very efficient random program generation (see chapter 1.1.1). #### 2.1.1 Instruction complexity The VM is a complex instruction set machine that allows both register and memory addressed operands. However, each RandomX instructions translates to only 1-7 x86 instructions (1.8 on average). It is important to keep the instruction complexity relatively low to minimize the efficiency advantage of specialized hardware with a tailored instruction set. ### 2.2 Program The program executed by the VM has the form of a loop consisting of 256 random instructions. * 256 instructions is long enough to provide a large number of possible programs and enough space for branches. The number of different programs that can be generated is limited to 2512 = 1.3e+154, which is the number of possible seed values of the random generator. * 256 instructions is short enough so that high-performance CPUs can execute one iteration in similar time it takes to fetch data from DRAM. This is advantageous because it allows Dataset accesses to be synchronized and fully prefetchable (see chapter 2.9). * Since the program is a loop, it can take advantage of the μop cache [[6](https://en.wikipedia.org/wiki/CPU_cache#Micro-operation_(%CE%BCop_or_uop)_cache)] that is present in some x86 CPUs. Running a loop from the μop cache allows the CPU to power down the x86 instruction decoders, which should help to equalize the power efficiency between x86 and architectures with simple instruction decoding. ### 2.3 Registers The VM uses 8 integer registers and 12 floating point registers. This is the maximum that can be allocated as physical registers in x86-64, which has the fewest architectural registers among common 64-bit CPU architectures. Using more registers would put x86 CPUs at a disadvantage since they would have to use memory to store VM register contents. ### 2.4 Integer operations RandomX uses all primitive integer operations that have high output entropy: addition (IADD_RS, IADD_M), subtraction (ISUB_R, ISUB_M, INEG_R), multiplication (IMUL_R, IMUL_M, IMULH_R, IMULH_M, ISMULH_R, ISMULH_M, IMUL_RCP), exclusive or (IXOR_R, IXOR_M) and rotation (IROR_R, IROL_R). #### 2.4.1 IADD_RS The IADD_RS instruction utilizes the address calculation logic of CPUs and can be performed in a single hardware instruction by most CPUs (x86 `lea`, arm `add`). #### 2.4.2 IMUL_RCP Because integer division is not fully pipelined in CPUs and can be made faster in ASICs, the IMUL_RCP instruction requires only one division per program to calculate the reciprocal. This forces an ASIC to include a hardware divider without giving them a performance advantage during program execution. #### 2.4.3 IROR_R/IROL_R Rotation instructions are split between rotate right and rotate left with a 4:1 ratio. Rotate right has a higher frequency because some architecures (like ARM) don't support rotate left natively (it must be emulated using rotate right). #### 2.4.4 ISWAP_R This instruction can be executed efficiently by CPUs that support register renaming/move elimination. ### 2.5 Floating point operations RandomX uses double precision floating point operations, which are supported by the majority of CPUs and require more complex hardware than single precision. All operations are performed as 128-bit vector operations, which is also supported by all major CPU architectures. RandomX uses five operations that are guaranteed by the IEEE 754 standard to give correctly rounded results: addition, subtraction, multiplication, division and square root. All 4 rounding modes defined by the standard are used. #### 2.5.1 Floating point register groups The domains of floating point operations are separated into "additive" operations, which use register group F and "multiplicative" operations, which use register group E. This is done to prevent addition/subtraction from becoming no-op when a small number is added to a large number. Since the range of the F group registers is limited to around `±3.0e+14`, adding or subtracting a floating point number with absolute value larger than 1 always changes at least 5 fraction bits. Because the limited range of group F registers would allow the use of a more efficient fixed-point representation (with 80-bit numbers), the FSCAL instruction manipulates the binary representation of the floating point format to make this optimization more difficult. Group E registers are restricted to positive values, which avoids `NaN` results (such as square root of a negative number or `0 * ∞`). Division uses only memory source operand to avoid being optimized into multiplication by constant reciprocal. The exponent of group E memory operands is set to a value between -255 and 0 to avoid division and multiplication by 0 and to increase the range of numbers that can be obtained. The approximate range of possible group E register values is `1.7E-77` to `infinity`. Approximate distribution of floating point register values at the end of each program loop is shown in these figures (left - group F, right - group E): ![Imgur](https://i.imgur.com/64G4qE8.png) *(Note: bins are marked by the left-side value of the interval, e.g. bin marked `1e-40` contains values from `1e-40` to `1e-20`.)* The small number of F register values at `1e+14` is caused by the FSCAL instruction, which significantly increases the range of the register values. Group E registers cover a very large range of values. About 2% of programs produce at least one `infinity` value. To maximize entropy and also to fit into one 64-byte cache line, floating point registers are combined using the XOR operation at the end of each iteration before being stored into the Scratchpad. ### 2.6 Branches Modern CPUs invest a lot of die area and energy to handle branches. This includes: * Branch predictor unit [[21](https://en.wikipedia.org/wiki/Branch_predictor)] * Checkpoint/rollback states that allow the CPU to recover in case of a branch misprediction. To take advantage of speculative designs, the random programs should contain branches. However, if branch prediction fails, the speculatively executed instructions are thrown away, which results in a certain amount of wasted energy with each misprediction. Therefore we should aim to minimize the number of mispredictions. Additionally, branches in the code are essential because they significantly reduce the amount of static optimizations that can be made. For example, consider the following x86 instruction sequence: ```asm ... branch_target_00: ... xor r8, r9 test r10, 2088960 je branch_target_00 xor r8, r9 ... ``` The XOR operations would normally cancel out, but cannot be optimized away due to the branch because the result will be different if the branch is taken. Similarly, the ISWAP_R instruction could be always statically optimized out if it wasn't for branches. In general, random branches must be designed in such way that: 1. Infinite loops are not possible. 1. The number of mispredicted branches is small. 1. Branch condition depends on a runtime value to disable static branch optimizations. #### 2.6.1 Branch prediction Unfortunately, we haven't found a way how to utilize branch prediction in RandomX. Because RandomX is a consensus protocol, all the rules must be set out in advance, which includes the rules for branches. Fully predictable branches cannot depend on the runtime value of any VM register (since register values are pseudorandom and unpredictable), so they would have to be static and therefore easily optimizable by specialized hardware. #### 2.6.2 CBRANCH instruction RandomX therefore uses random branches with a jump probability of 1/256 and branch condition that depends on an integer register value. These branches will be predicted as "not taken" by the CPU. Such branches are "free" in most CPU designs unless they are taken. While this doesn't take advantage of the branch predictors, speculative designs will see a significant performance boost compared to non-speculative branch handling - see Appendix B for more information. The branching conditions and jump targets are chosen in such way that infinite loops in RandomX code are impossible because the register controlling the branch will never be modified in the repeated code block. Each CBRANCH instruction can jump up to twice in a row. Handling CBRANCH using predicated execution [[22](https://en.wikipedia.org/wiki/Predication_(computer_architecture))] is impractical because the branch is not taken most of the time. ### 2.7 Instruction-level parallelism CPUs improve their performance using several techniques that utilize instruction-level parallelism of the executed code. These techniques include: * Having multiple execution units that can execute operations in parallel (*superscalar execution*). * Executing instruction not in program order, but in the order of operand availability (*out-of-order execution*). * Predicting which way branches will go to enhance the benefits of both superscalar and out-of-order execution. RandomX benefits from all these optimizations. See Appendix B for a detailed analysis. ### 2.8 Scratchpad The Scratchpad is used as read-write memory. Its size was selected to fit entirely into CPU cache. #### 2.8.1 Scratchpad levels The Scratchpad is split into 3 levels to mimic the typical CPU cache hierarchy [[23](https://en.wikipedia.org/wiki/CPU_cache)]. Most VM instructions access "L1" and "L2" Scratchpad because L1 and L2 CPU caches are located close to the CPU execution units and provide the best random access latency. The ratio of reads from L1 and L2 is 3:1, which matches the inverse ratio of typical latencies (see table below). |CPU μ-architecture|L1 latency|L2 latency|L3 latency|source| |----------------|----------|----------|----------|------| ARM Cortex A55|2|6|-|[[24](https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/4)] |AMD Zen+|4|12|40|[[25](https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B#Memory_Hierarchy)]| |Intel Skylake|4|12|42|[[26](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Memory_Hierarchy)] The L3 cache is much larger and located further from the CPU core. As a result, its access latencies are much higher and can cause stalls in program execution. RandomX therefore performs only 2 random accesses into "L3" Scratchpad per program iteration (steps 2 and 3 in chapter 4.6.2 of the Specification). Register values from a given iteration are written into the same locations they were loaded from, which guarantees that the required cache lines have been moved into the faster L1 or L2 caches. Additionally, integer instructions that read from a fixed address also use the whole "L3" Scratchpad (Table 5.1.4 of the Specification) because repetitive accesses will ensure that the cache line will be placed in the L1 cache of the CPU. This shows that the Scratchpad level doesn't always directly correspond to the same CPU cache level. #### 2.8.2 Scratchpad writes There are two ways the Scratchpad is modified during VM execution: 1. At the end of each program iteration, all register values are written into "L3" Scratchpad (see Specification chapter 4.6.2, steps 9 and 11). This writes a total of 128 bytes per iteration in two 64-byte blocks. 2. The ISTORE instruction does explicit stores. On average, there are 16 stores per program, out of which 2 stores are into the "L3" level. Each ISTORE instruction writes 8 bytes. The image below shows an example of the distribution of writes to the Scratchpad. Each pixel in the image represents 8 bytes of the Scratchpad. Red pixels represent portions of the Scratchpad that have been overwritten at least once during hash calculation. The "L1" and "L2" levels are on the left side (almost completely overwritten). The right side of the scratchpad represents the bottom 1792 KiB. Only about 66% of it are overwritten, but the writes are spread uniformly and randomly. ![Imgur](https://i.imgur.com/pRz6aBG.png) See Appendix D for the analysis of Scratchpad entropy. #### 2.8.3 Read-write ratio Programs make, on average, 39 reads (instructions IADD_M, ISUB_M, IMUL_M, IMULH_M, ISMULH_M, IXOR_M, FADD_M, FSUB_M, FDIV_M) and 16 writes (instruction ISTORE) to the Scratchpad per program iteration. Additional 128 bytes are read and written implicitly to initialize and store register values. 64 bytes of data is read from the Dataset per iteration. In total: * The average amount of data read from memory per program iteration is: 39 * 8 + 128 + 64 = **504 bytes**. * The average mount of data written to memory per program iteration is: 16 * 8 + 128 = **256 bytes**. This is close to a 2:1 read/write ratio, which CPUs are optimized for. ### 2.9 Dataset Since the Scratchpad is usually stored in the CPU cache, only Dataset accesses utilize the memory controllers. RandomX randomly reads from the Dataset once per program iteration (16384 times per hash result). Since the Dataset must be stored in DRAM, it provides a natural parallelization limit, because DRAM cannot do more than about 25 million random accesses per second per bank group. Each separately addressable bank group allows a throughput of around 1500 H/s. All Dataset accesses read one CPU cache line (64 bytes) and are fully prefetched. The time to execute one program iteration described in chapter 4.6.2 of the Specification is about the same as typical DRAM access latency (50-100 ns). #### 2.9.1 Cache The Cache, which is used for light verification and Dataset construction, is about 8 times smaller than the Dataset. To keep a constant area-time product, each Dataset item is constructed from 8 random Cache accesses. Because 256 MiB is small enough to be included on-chip, RandomX uses a custom high-latency, high-power mixing function ("SuperscalarHash") which defeats the benefits of using low-latency memory and the energy required to calculate SuperscalarHash makes light mode very inefficient for mining (see chapter 3.4). Using less than 256 MiB of memory is not possible due to the use of tradeoff-resistant Argon2d with 3 iterations. When using 3 iterations (passes), halving the memory usage increases computational cost 3423 times for the best tradeoff attack [[27](https://eprint.iacr.org/2015/430.pdf)]. ## 3. Custom functions ### 3.1 AesGenerator1R AesGenerator1R was designed for the fastest possible generation of pseudorandom data to fill the Scratchpad. It takes advantage of hardware accelerated AES in modern CPUs. Only one AES round is performed per 16 bytes of output, which results in throughput exceeding 20 GB/s in most modern CPUs. AesGenerator1R gives a good output distribution provided that it's initialized with a sufficiently 'random' initial state (see Appendix F). ### 3.2 AesGenerator4R AesGenerator4R uses 4 AES rounds to generate pseudorandom data for Program Buffer initialization. Since 2 AES rounds are sufficient for full avalanche of all input bits [[28](https://csrc.nist.gov/csrc/media/projects/cryptographic-standards-and-guidelines/documents/aes-development/rijndael-ammended.pdf)], AesGenerator4R has excellent statistical properties (see Appendix F) while maintaining very good performance. The reversible nature of this generator is not an issue since the generator state is always initialized using the output of a non-reversible hashing function (Blake2b). ### 3.3 AesHash1R AesHash was designed for the fastest possible calculation of the Scratchpad fingerprint. It interprets the Scratchpad as a set of AES round keys, so it's equivalent to AES encryption with 32768 rounds. Two extra rounds are performed at the end to ensure avalanche of all Scratchpad bits in each lane. The reversible nature of AesHash1R is not a problem for two main reasons: * It is not possible to directly control the input of AesHash1R. * The output of AesHash1R is passed into the Blake2b hashing function, which is not reversible. ### 3.4 SuperscalarHash SuperscalarHash was designed to burn as much power as possible while the CPU is waiting for data to be loaded from DRAM. The target latency of 170 cycles corresponds to the usual DRAM latency of 40-80 ns and clock frequency of 2-4 GHz. ASIC devices designed for light-mode mining with low-latency memory will be bottlenecked by SuperscalarHash when calculating Dataset items and their efficiency will be destroyed by the high power usage of SuperscalarHash. The average SuperscalarHash function contains a total of 450 instructions, out of which 155 are 64-bit multiplications. On average, the longest dependency chain is 95 instructions long. An ASIC design for light-mode mining, with 256 MiB of on-die memory and 1-cycle latency for all operations, will need on average 95 * 8 = 760 cycles to construct a Dataset item, assuming unlimited parallelization. It will have to execute 155 * 8 = 1240 64-bit multiplications per item, which will consume energy comparable to loading 64 bytes from DRAM. ## Appendix ### A. The effect of chaining VM executions Chapter 1.2 describes why `N` random programs are chained to prevent mining strategies that search for 'easy' programs. RandomX uses a value of `N = 8`. Let's define `Q` as the ratio of acceptable programs in a strategy that uses filtering. For example `Q = 0.75` means that 25% of programs are rejected. For `N = 1`, there are no wasted program executions and the only cost is program generation and the filtering itself. The calculations below assume that these costs are zero and the only real cost is program execution. However, this is a simplification because program generation in RandomX is not free (the first program generation requires full Scratchpad initialization), but it describes a best-case scenario for an attacker. For `N > 1`, the first program can be filtered as usual, but after the program is executed, there is a chance of `1-Q` that the next program should be rejected and we have wasted one program execution. For `N` chained executions, the chance is only QN that all programs in the chain are acceptable. However, during each attempt to find such chain, we will waste the execution of some programs. For `N = 8`, the number of wasted programs per attempt is equal to (1-Q)*(1+2\*Q+3\*Q2+4\*Q3+5\*Q4+6\*Q5+7\*Q6) (approximately 2.5 for `Q = 0.75`). Let's consider 3 mining strategies: #### Strategy I Honest miner that doesn't reject any programs (`Q = 1`). #### Strategy II Miner that uses optimized custom hardware that cannot execute 25% of programs (`Q = 0.75`), but supported programs can be executed 50% faster. #### Strategy III Miner that can execute all programs, but rejects 25% of the slowest programs for the first program in the chain. This gives a 5% performance boost for the first program in the chain (this matches the runtime distribution from Appendix C). #### Results The table below lists the results for the above 3 strategies and different values of `N`. The columns **N(I)**, **N(II)** and **N(III)** list the number of programs that each strategy has to execute on average to get one valid hash result (this includes programs wasted in rejected chains). Columns **Speed(I)**, **Speed(II)** and **Speed(III)** list the average mining performance relative to strategy I. |N|N(I)|N(II)|N(III)|Speed(I)|Speed(II)|Speed(III)| |---|----|----|----|---------|---------|---------| |1|1|1|1|1.00|1.50|1.05| |2|2|2.3|2|1.00|1.28|1.02| |4|4|6.5|4|1.00|0.92|1.01| |8|8|27.0|8|1.00|0.44|1.00| For `N = 8`, strategy II will perform at less than half the speed of the honest miner despite having a 50% performance advantage for selected programs. The small statistical advantage of strategy III is negligible with `N = 8`. ### B. Performance simulation As discussed in chapter 2.7, RandomX aims to take advantage of the complex design of modern high-performance CPUs. To evaluate the impact of superscalar, out-of-order and speculative execution, we performed a simplified CPU simulation. Source code is available in [perf-simulation.cpp](../src/tests/perf-simulation.cpp). #### CPU model The model CPU uses a 3-stage pipeline to achieve an ideal throughput of 1 instruction per cycle: ``` (1) (2) (3) +------------------+ +----------------+ +----------------+ | Instruction | | | | | | fetch | ---> | Memory access | ---> | Execute | | + decode | | | | | +------------------+ +----------------+ +----------------+ ``` The 3 stages are: 1. Instruction fetch and decode. This stage loads the instruction from the Program Buffer and decodes the instruction operation and operands. 2. Memory access. If this instruction uses a memory operand, it is loaded from the Scratchpad in this stage. This includes the calculation of the memory address. Stores are also performed in this stage. The value of the address register must be available in this stage. 3. Execute. This stage executes the instruction using the operands retrieved in the previous stages and writes the results into the register file. Note that this is an optimistically short pipeline that would not allow very high clock speeds. Designs using a longer pipeline would significantly increase the benefits of speculative execution. #### Superscalar execution Our model CPU contains two kinds of components: * Execution unit (EXU) - it is used to perform the actual integer or floating point operation. All RandomX instructions except ISTORE must use an execution unit in the 3rd pipeline stage. All operations are considered to take only 1 clock cycle. * Memory unit (MEM) - it is used for loads and stores into Scratchpad. All memory instructions (including ISTORE) use a memory unit in the 2nd pipeline stage. A superscalar design will contain multiple execution or memory units to improve performance. #### Out-of-order execution The simulation model supports two designs: 1. **In-order** - all instructions are executed in the order they appear in the Program Buffer. This design will stall if a dependency is encountered or the required EXU/MEM unit is not available. 2. **Out-of-order** - doesn't execute instructions in program order, but an instruction can be executed when its operands are ready and the required EXU/MEM units are available. #### Branch handling The simulation model supports two types of branch handling: 1. **Non-speculative** - when a branch is encountered, the pipeline is stalled. This typically adds a 3-cycle penalty for each branch. 2. **Speculative** - all branches are predicted not taken and the pipeline is flushed if a misprediction occurs (probability of 1/256). #### Results The following 10 designs were simulated and the average number of clock cycles to execute a RandomX program (256 instructions) was measured. |design|superscalar config.|reordering|branch handling|execution time [cycles]|IPC| |-------|-----------|----------|---------------|-----------------------|---| |#1|1 EXU + 1 MEM|in-order|non-speculative|293|0.87| |#2|1 EXU + 1 MEM|in-order|speculative|262|0.98| |#3|2 EXU + 1 MEM|in-order|non-speculative|197|1.3| |#4|2 EXU + 1 MEM|in-order|speculative|161|1.6| |#5|2 EXU + 1 MEM|out-of-order|non-speculative|144|1.8| |#6|2 EXU + 1 MEM|out-of-order|speculative|122|2.1| |#7|4 EXU + 2 MEM|in-order|non-speculative|135|1.9| |#8|4 EXU + 2 MEM|in-order|speculative|99|2.6| |#9|4 EXU + 2 MEM|out-of-order|non-speculative|89|2.9| |#10|4 EXU + 2 MEM|out-of-order|speculative|64|4.0| The benefits of superscalar, out-of-order and speculative designs are clearly demonstrated. ### C. RandomX runtime distribution Runtime numbers were measured on AMD Ryzen 7 1700 running at 3.0 GHz using 1 core. Source code to measure program execution and verification times is available in [runtime-distr.cpp](../src/tests/runtime-distr.cpp). Source code to measure the performance of the x86 JIT compiler is available in [jit-performance.cpp](../src/tests/jit-performance.cpp). #### Fast mode - program execution The following figure shows the distribution of the runtimes of a single VM program (in fast mode). This includes: program generation, JIT compilation, VM execution and Blake2b hash of the register file. Program generation and JIT compilation was measured to take 3.6 μs per program. ![Imgur](https://i.imgur.com/ikv2z2i.png) AMD Ryzen 7 1700 can calculate 625 hashes per second in fast mode (using 1 thread), which means a single hash result takes 1600 μs (1.6 ms). This consists of (approximately): * 1480 μs for VM execution (8 programs) * 45 μs for initial Scratchpad fill (AesGenerator1R). * 45 μs for final Scratchpad hash (AesHash1R). * 30 μs for program generation and JIT compilation (8 programs) This gives a total overhead of 7.5% (time per hash spent not executing VM). #### Light mode - verification time The following figure shows the distribution of times to calculate 1 hash result using the light mode. Most of the time is spent executing SuperscalarHash to calculate Dataset items (13.2 ms out of 14.8 ms). The average verification time exactly matches the performance of the CryptoNight algorithm. ![Imgur](https://i.imgur.com/VtwwJT8.png) ### D. Scratchpad entropy analysis The average entropy of the Scratchpad after 8 program executions was approximated using the LZMA compression algorithm: 1. Hash resuls were calculated and the final scratchpads were written to disk as files with '.spad' extension (source code: [scratchpad-entropy.cpp](../src/tests/scratchpad-entropy.cpp)) 2. The files were compressed using 7-Zip [[29](https://www.7-zip.org/)] in Ultra compression mode: `7z.exe a -t7z -m0=lzma2 -mx=9 scratchpads.7z *.spad` The size of the resulting archive is approximately 99.98% of the uncompressed size of the scratchpad files. This shows that the Scratchpad retains high entropy during VM execution. ### E. SuperscalarHash analysis SuperscalarHash is a custom function used by RandomX to generate Dataset items. It operates on 8 integer registers and uses a random sequence of instructions. About 1/3 of the instructions are multiplications. The following figure shows the sensitivity of SuperscalarHash to changing a single bit of an input register: ![Imgur](https://i.imgur.com/ztZ0V0G.png) This shows that SuperscalaHash has quite low sensitivity to high-order bits and somewhat decreased sensitivity to the lowest-order bits. Sensitivity is highest for bits 3-53 (inclusive). When calculating a Dataset item, the input of the first SuperscalarHash depends only on the item number. To ensure a good distribution of results, the constants described in section 7.3 of the Specification were chosen to provide unique values of bits 3-53 for *all* item numbers in the range 0-34078718 (the Dataset contains 34078719 items). All initial register values for all Dataset item numbers were checked to make sure bits 3-53 of each register are unique and there are no collisions (source code: [superscalar-init.cpp](../src/tests/superscalar-init.cpp)). While this is not strictly necessary to get unique output from SuperscalarHash, it's a security precaution that mitigates the non-perfect avalanche properties of the randomly generated SuperscalarHash instances. ### F. Statistical tests of RNG Both AesGenerator1R and AesGenerator4R were tested using the TestU01 library [[30](http://simul.iro.umontreal.ca/testu01/tu01.html)] intended for empirical testing of random number generators. The source code is available in [rng-tests.cpp](../src/tests/rng-tests.cpp). The tests sample about 200 MB ("SmallCrush" test), 500 GB ("Crush" test) or 4 TB ("BigCrush" test) of output from each generator. This is considerably more than the amounts generated in RandomX (2176 bytes for AesGenerator4R and 2 MiB for AesGenerator1R), so failures in the tests don't necessarily imply that the generators are not suitable for their use case. #### AesGenerator4R The generator passes all tests in the "BigCrush" suite when initialized using the Blake2b hash function: ``` $ bin/rng-tests 1 state0 = 67e8bbe567a1c18c91a316faf19fab73 state1 = 39f7c0e0a8d96512c525852124fdc9fe state2 = 7abb07b2c90e04f098261e323eee8159 state3 = 3df534c34cdfbb4e70f8c0e1826f4cf7 ... ========= Summary results of BigCrush ========= Version: TestU01 1.2.3 Generator: AesGenerator4R Number of statistics: 160 Total CPU time: 02:50:18.34 All tests were passed ``` The generator passes all tests in the "Crush" suite even with an initial state set to all zeroes. ``` $ bin/rng-tests 0 state0 = 00000000000000000000000000000000 state1 = 00000000000000000000000000000000 state2 = 00000000000000000000000000000000 state3 = 00000000000000000000000000000000 ... ========= Summary results of Crush ========= Version: TestU01 1.2.3 Generator: AesGenerator4R Number of statistics: 144 Total CPU time: 00:25:17.95 All tests were passed ``` #### AesGenerator1R The generator passes all tests in the "Crush" suite when initialized using the Blake2b hash function. ``` $ bin/rng-tests 1 state0 = 67e8bbe567a1c18c91a316faf19fab73 state1 = 39f7c0e0a8d96512c525852124fdc9fe state2 = 7abb07b2c90e04f098261e323eee8159 state3 = 3df534c34cdfbb4e70f8c0e1826f4cf7 ... ========= Summary results of Crush ========= Version: TestU01 1.2.3 Generator: AesGenerator1R Number of statistics: 144 Total CPU time: 00:25:06.07 All tests were passed ``` When the initial state is initialized to all zeroes, the generator fails 1 test out of 144 tests in the "Crush" suite: ``` $ bin/rng-tests 0 state0 = 00000000000000000000000000000000 state1 = 00000000000000000000000000000000 state2 = 00000000000000000000000000000000 state3 = 00000000000000000000000000000000 ... ========= Summary results of Crush ========= Version: TestU01 1.2.3 Generator: AesGenerator1R Number of statistics: 144 Total CPU time: 00:26:12.75 The following tests gave p-values outside [0.001, 0.9990]: (eps means a value < 1.0e-300): (eps1 means a value < 1.0e-15): Test p-value ---------------------------------------------- 12 BirthdaySpacings, t = 3 1 - 4.4e-5 ---------------------------------------------- All other tests were passed ``` ## References [1] CryptoNote whitepaper - https://cryptonote.org/whitepaper.pdf [2] ProgPoW: Inefficient integer multiplications - https://github.com/ifdefelse/ProgPOW/issues/16 [3] Cryptographic Hashing function - https://en.wikipedia.org/wiki/Cryptographic_hash_function [4] randprog - https://github.com/hyc/randprog [5] RandomJS - https://github.com/tevador/RandomJS [6] μop cache - https://en.wikipedia.org/wiki/CPU_cache#Micro-operation_(%CE%BCop_or_uop)_cache [7] Instruction-level parallelism - https://en.wikipedia.org/wiki/Instruction-level_parallelism [8] Superscalar processor - https://en.wikipedia.org/wiki/Superscalar_processor [9] Out-of-order execution - https://en.wikipedia.org/wiki/Out-of-order_execution [10] Speculative execution - https://en.wikipedia.org/wiki/Speculative_execution [11] Register renaming - https://en.wikipedia.org/wiki/Register_renaming [12] Blake2 hashing function - https://blake2.net/ [13] Advanced Encryption Standard - https://en.wikipedia.org/wiki/Advanced_Encryption_Standard [14] Log-normal distribution - https://en.wikipedia.org/wiki/Log-normal_distribution [15] CryptoNight hash function - https://cryptonote.org/cns/cns008.txt [16] Dynamic random-access memory - https://en.wikipedia.org/wiki/Dynamic_random-access_memory [17] Multi-channel memory architecture - https://en.wikipedia.org/wiki/Multi-channel_memory_architecture [18] Obelisk GRN1 chip details - https://www.grin-forum.org/t/obelisk-grn1-chip-details/4571 [19] Biryukov et al.: Tradeoff Cryptanalysis of Memory-Hard Functions - https://eprint.iacr.org/2015/227.pdf [20] SK Hynix 20nm DRAM density - http://en.thelec.kr/news/articleView.html?idxno=20 [21] Branch predictor - https://en.wikipedia.org/wiki/Branch_predictor [22] Predication - https://en.wikipedia.org/wiki/Predication_(computer_architecture) [23] CPU cache - https://en.wikipedia.org/wiki/CPU_cache [24] Cortex-A55 Microarchitecture - https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/4 [25] AMD Zen+ Microarchitecture - https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B#Memory_Hierarchy [26] Intel Skylake Microarchitecture - https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Memory_Hierarchy [27] Biryukov et al.: Fast and Tradeoff-Resilient Memory-Hard Functions for Cryptocurrencies and Password Hashing - https://eprint.iacr.org/2015/430.pdf Table 2, page 8 [28] J. Daemen, V. Rijmen: AES Proposal: Rijndael - https://csrc.nist.gov/csrc/media/projects/cryptographic-standards-and-guidelines/documents/aes-development/rijndael-ammended.pdf page 28 [29] 7-Zip File archiver - https://www.7-zip.org/ [30] TestU01 library - http://simul.iro.umontreal.ca/testu01/tu01.html RandomX-1.1.10/doc/program.asm000066400000000000000000000454631414227164600161030ustar00rootroot00000000000000randomx_isn_0: ; ISMULH_R r0, r3 mov rax, r8 imul r11 mov r8, rdx randomx_isn_1: ; IROR_R r0, r6 mov ecx, r14d ror r8, cl randomx_isn_2: ; FADD_R f1, a2 addpd xmm1, xmm10 randomx_isn_3: ; IXOR_M r1, L1[r5+1954652011] lea eax, [r13d+1954652011] and eax, 16376 xor r9, qword ptr [rsi+rax] randomx_isn_4: ; FMUL_R e2, a3 mulpd xmm6, xmm11 randomx_isn_5: ; FADD_M f0, L2[r0-772804104] lea eax, [r8d-772804104] and eax, 262136 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm0, xmm12 randomx_isn_6: ; IMUL_R r6, r4 imul r14, r12 randomx_isn_7: ; CBRANCH r5, 1674196118, COND 2 add r13, 1674196118 test r13, 261120 jz randomx_isn_0 randomx_isn_8: ; ISWAP_R r7, r6 xchg r15, r14 randomx_isn_9: ; ISTORE L1[r1-439821682], r3 lea eax, [r9d-439821682] and eax, 16376 mov qword ptr [rsi+rax], r11 randomx_isn_10: ; IXOR_R r2, r4 xor r10, r12 randomx_isn_11: ; FADD_R f2, a1 addpd xmm2, xmm9 randomx_isn_12: ; IXOR_M r0, L1[r1+952699079] lea eax, [r9d+952699079] and eax, 16376 xor r8, qword ptr [rsi+rax] randomx_isn_13: ; ISMULH_R r5, r2 mov rax, r13 imul r10 mov r13, rdx randomx_isn_14: ; INEG_R r4 neg r12 randomx_isn_15: ; INEG_R r1 neg r9 randomx_isn_16: ; IMUL_M r3, L1[r2+620091535] lea eax, [r10d+620091535] and eax, 16376 imul r11, qword ptr [rsi+rax] randomx_isn_17: ; FADD_R f1, a0 addpd xmm1, xmm8 randomx_isn_18: ; IMUL_RCP r5, 2611385784 mov rax, 15169754503470242065 imul r13, rax randomx_isn_19: ; IXOR_R r2, 922368940 xor r10, 922368940 randomx_isn_20: ; FADD_R f3, a1 addpd xmm3, xmm9 randomx_isn_21: ; IXOR_R r3, r6 xor r11, r14 randomx_isn_22: ; FSWAP_R e1 shufpd xmm5, xmm5, 1 randomx_isn_23: ; ISUB_R r0, r5 sub r8, r13 randomx_isn_24: ; ISTORE L1[r6-1574415460], r7 lea eax, [r14d-1574415460] and eax, 16376 mov qword ptr [rsi+rax], r15 randomx_isn_25: ; FADD_M f3, L1[r3+1766115210] lea eax, [r11d+1766115210] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm3, xmm12 randomx_isn_26: ; FSCAL_R f1 xorps xmm1, xmm15 randomx_isn_27: ; CBRANCH r2, 1731738265, COND 6 add r10, 1731746457 test r10, 4177920 jz randomx_isn_20 randomx_isn_28: ; IXOR_R r4, r1 xor r12, r9 randomx_isn_29: ; CBRANCH r4, 1937048537, COND 3 add r12, 1937050585 test r12, 522240 jz randomx_isn_29 randomx_isn_30: ; ISWAP_R r3, r5 xchg r11, r13 randomx_isn_31: ; ISMULH_R r7, r5 mov rax, r15 imul r13 mov r15, rdx randomx_isn_32: ; IMULH_M r6, L1[r2+1879111790] lea ecx, [r10d+1879111790] and ecx, 16376 mov rax, r14 mul qword ptr [rsi+rcx] mov r14, rdx randomx_isn_33: ; IMUL_R r5, r0 imul r13, r8 randomx_isn_34: ; ISWAP_R r5, r0 xchg r13, r8 randomx_isn_35: ; CBRANCH r4, 1174490916, COND 5 add r12, 1174499108 test r12, 2088960 jz randomx_isn_30 randomx_isn_36: ; CBRANCH r6, -1852457840, COND 8 add r14, -1852490608 test r14, 16711680 jz randomx_isn_36 randomx_isn_37: ; ISMULH_R r2, r0 mov rax, r10 imul r8 mov r10, rdx randomx_isn_38: ; ISUB_R r2, r0 sub r10, r8 randomx_isn_39: ; ISTORE L1[r0-38118463], r5 lea eax, [r8d-38118463] and eax, 16376 mov qword ptr [rsi+rax], r13 randomx_isn_40: ; IXOR_R r0, r1 xor r8, r9 randomx_isn_41: ; IMUL_R r6, r4 imul r14, r12 randomx_isn_42: ; ISUB_R r7, r5 sub r15, r13 randomx_isn_43: ; FDIV_M e0, L1[r2+1052956160] lea eax, [r10d+1052956160] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] andps xmm12, xmm13 orps xmm12, xmm14 divpd xmm4, xmm12 randomx_isn_44: ; CBRANCH r1, 1870241002, COND 11 add r9, 1870241002 test r9, 133693440 jz randomx_isn_37 randomx_isn_45: ; IXOR_R r1, r4 xor r9, r12 randomx_isn_46: ; FMUL_R e3, a1 mulpd xmm7, xmm9 randomx_isn_47: ; IXOR_M r0, L1[r2+839895331] lea eax, [r10d+839895331] and eax, 16376 xor r8, qword ptr [rsi+rax] randomx_isn_48: ; CBRANCH r2, -2128896196, COND 6 add r10, -2128879812 test r10, 4177920 jz randomx_isn_45 randomx_isn_49: ; CFROUND r1, 13 mov rax, r9 and eax, 24576 or eax, 40896 push rax ldmxcsr dword ptr [rsp] pop rax randomx_isn_50: ; ISWAP_R r3, r1 xchg r11, r9 randomx_isn_51: ; IMUL_RCP r1, 4205062916 mov rax, 9420568026795290117 imul r9, rax randomx_isn_52: ; FSUB_R f0, a0 subpd xmm0, xmm8 randomx_isn_53: ; IMUL_R r7, r6 imul r15, r14 randomx_isn_54: ; IADD_RS r1, r2, SHFT 3 lea r9, [r9+r10*8] randomx_isn_55: ; FSQRT_R e3 sqrtpd xmm7, xmm7 randomx_isn_56: ; FMUL_R e1, a0 mulpd xmm5, xmm8 randomx_isn_57: ; IMUL_RCP r3, 303101651 mov rax, 16336962008634921950 imul r11, rax randomx_isn_58: ; IMUL_RCP r1, 3375482677 mov rax, 11735827153567160432 imul r9, rax randomx_isn_59: ; CBRANCH r6, 2116776661, COND 12 add r14, 2117300949 test r14, 267386880 jz randomx_isn_49 randomx_isn_60: ; IMUL_R r3, r4 imul r11, r12 randomx_isn_61: ; FMUL_R e3, a0 mulpd xmm7, xmm8 randomx_isn_62: ; ISUB_R r3, 1514378938 sub r11, 1514378938 randomx_isn_63: ; FMUL_R e2, a0 mulpd xmm6, xmm8 randomx_isn_64: ; ISUB_R r4, r6 sub r12, r14 randomx_isn_65: ; FDIV_M e2, L1[r0+1496571595] lea eax, [r8d+1496571595] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] andps xmm12, xmm13 orps xmm12, xmm14 divpd xmm6, xmm12 randomx_isn_66: ; FSUB_R f0, a2 subpd xmm0, xmm10 randomx_isn_67: ; FDIV_M e3, L2[r7-2139079025] lea eax, [r15d-2139079025] and eax, 262136 cvtdq2pd xmm12, qword ptr [rsi+rax] andps xmm12, xmm13 orps xmm12, xmm14 divpd xmm7, xmm12 randomx_isn_68: ; FSUB_R f2, a2 subpd xmm2, xmm10 randomx_isn_69: ; CBRANCH r3, -1165095866, COND 7 add r11, -1165063098 test r11, 8355840 jz randomx_isn_63 randomx_isn_70: ; IMULH_R r0, r7 mov rax, r8 mul r15 mov r8, rdx randomx_isn_71: ; FMUL_R e2, a0 mulpd xmm6, xmm8 randomx_isn_72: ; FMUL_R e0, a3 mulpd xmm4, xmm11 randomx_isn_73: ; IMUL_RCP r6, 1636610180 mov rax, 12102479179596746977 imul r14, rax randomx_isn_74: ; FMUL_R e2, a2 mulpd xmm6, xmm10 randomx_isn_75: ; ISTORE L2[r2+473418592], r3 lea eax, [r10d+473418592] and eax, 262136 mov qword ptr [rsi+rax], r11 randomx_isn_76: ; IADD_M r1, L1[r3-989917936] lea eax, [r11d-989917936] and eax, 16376 add r9, qword ptr [rsi+rax] randomx_isn_77: ; CBRANCH r2, 1519854177, COND 7 add r10, 1519886945 test r10, 8355840 jz randomx_isn_70 randomx_isn_78: ; IMUL_R r2, r6 imul r10, r14 randomx_isn_79: ; IMUL_R r4, r1 imul r12, r9 randomx_isn_80: ; FMUL_R e2, a1 mulpd xmm6, xmm9 randomx_isn_81: ; FSCAL_R f2 xorps xmm2, xmm15 randomx_isn_82: ; IXOR_M r2, L1[r1+192323103] lea eax, [r9d+192323103] and eax, 16376 xor r10, qword ptr [rsi+rax] randomx_isn_83: ; IMUL_R r7, r4 imul r15, r12 randomx_isn_84: ; FADD_R f2, a0 addpd xmm2, xmm8 randomx_isn_85: ; FSUB_M f1, L2[r6-1549504487] lea eax, [r14d-1549504487] and eax, 262136 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm1, xmm12 randomx_isn_86: ; FSUB_R f0, a3 subpd xmm0, xmm11 randomx_isn_87: ; CFROUND r3, 31 mov rax, r11 rol rax, 46 and eax, 24576 or eax, 40896 push rax ldmxcsr dword ptr [rsp] pop rax randomx_isn_88: ; IXOR_R r5, r6 xor r13, r14 randomx_isn_89: ; FADD_R f3, a2 addpd xmm3, xmm10 randomx_isn_90: ; FADD_R f3, a0 addpd xmm3, xmm8 randomx_isn_91: ; FSQRT_R e1 sqrtpd xmm5, xmm5 randomx_isn_92: ; ISUB_R r6, r2 sub r14, r10 randomx_isn_93: ; ISUB_R r0, r4 sub r8, r12 randomx_isn_94: ; FADD_R f1, a2 addpd xmm1, xmm10 randomx_isn_95: ; IMUL_R r1, r2 imul r9, r10 randomx_isn_96: ; FSCAL_R f1 xorps xmm1, xmm15 randomx_isn_97: ; ISTORE L1[r7-1901001017], r7 lea eax, [r15d-1901001017] and eax, 16376 mov qword ptr [rsi+rax], r15 randomx_isn_98: ; FADD_R f1, a3 addpd xmm1, xmm11 randomx_isn_99: ; CBRANCH r2, -425599201, COND 9 add r10, -425533665 test r10, 33423360 jz randomx_isn_83 randomx_isn_100: ; IXOR_R r4, r6 xor r12, r14 randomx_isn_101: ; FMUL_R e0, a3 mulpd xmm4, xmm11 randomx_isn_102: ; FADD_M f0, L1[r0+1590646897] lea eax, [r8d+1590646897] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm0, xmm12 randomx_isn_103: ; FMUL_R e0, a1 mulpd xmm4, xmm9 randomx_isn_104: ; IMUL_R r4, r7 imul r12, r15 randomx_isn_105: ; ISUB_R r1, r0 sub r9, r8 randomx_isn_106: ; FSUB_R f1, a2 subpd xmm1, xmm10 randomx_isn_107: ; FMUL_R e1, a1 mulpd xmm5, xmm9 randomx_isn_108: ; FMUL_R e1, a2 mulpd xmm5, xmm10 randomx_isn_109: ; FADD_R f3, a2 addpd xmm3, xmm10 randomx_isn_110: ; IXOR_R r0, r3 xor r8, r11 randomx_isn_111: ; IMUL_R r0, 1421329412 imul r8, 1421329412 randomx_isn_112: ; FSUB_R f0, a2 subpd xmm0, xmm10 randomx_isn_113: ; IMUL_R r5, r4 imul r13, r12 randomx_isn_114: ; IADD_RS r7, r3, SHFT 2 lea r15, [r15+r11*4] randomx_isn_115: ; FADD_R f3, a3 addpd xmm3, xmm11 randomx_isn_116: ; ISTORE L1[r3-160363922], r0 lea eax, [r11d-160363922] and eax, 16376 mov qword ptr [rsi+rax], r8 randomx_isn_117: ; IMULH_R r0, r6 mov rax, r8 mul r14 mov r8, rdx randomx_isn_118: ; FSWAP_R f2 shufpd xmm2, xmm2, 1 randomx_isn_119: ; FMUL_R e1, a0 mulpd xmm5, xmm8 randomx_isn_120: ; IROR_R r0, 12 ror r8, 12 randomx_isn_121: ; FADD_M f0, L1[r0+282806289] lea eax, [r8d+282806289] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm0, xmm12 randomx_isn_122: ; FADD_M f3, L1[r7+1601529113] lea eax, [r15d+1601529113] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm3, xmm12 randomx_isn_123: ; IMUL_RCP r2, 2522040806 mov rax, 15707153176462985744 imul r10, rax randomx_isn_124: ; ISUB_M r0, L1[r3+974906597] lea eax, [r11d+974906597] and eax, 16376 sub r8, qword ptr [rsi+rax] randomx_isn_125: ; CBRANCH r2, 1508706439, COND 14 add r10, 1506609287 test r10, 1069547520 jz randomx_isn_124 randomx_isn_126: ; IXOR_R r4, r5 xor r12, r13 randomx_isn_127: ; IMUL_R r7, r2 imul r15, r10 randomx_isn_128: ; IROR_R r4, r0 mov ecx, r8d ror r12, cl randomx_isn_129: ; CBRANCH r0, -497803311, COND 3 add r8, -497804335 test r8, 522240 jz randomx_isn_126 randomx_isn_130: ; FSUB_M f0, L1[r3+1789853646] lea eax, [r11d+1789853646] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm0, xmm12 randomx_isn_131: ; ISMULH_R r6, r3 mov rax, r14 imul r11 mov r14, rdx randomx_isn_132: ; FMUL_R e0, a3 mulpd xmm4, xmm11 randomx_isn_133: ; FSUB_R f2, a1 subpd xmm2, xmm9 randomx_isn_134: ; CBRANCH r3, -1567551204, COND 11 add r11, -1567026916 test r11, 133693440 jz randomx_isn_130 randomx_isn_135: ; FSUB_M f2, L2[r5+1167508659] lea eax, [r13d+1167508659] and eax, 262136 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm2, xmm12 randomx_isn_136: ; IMUL_R r4, r0 imul r12, r8 randomx_isn_137: ; IMULH_R r7, r6 mov rax, r15 mul r14 mov r15, rdx randomx_isn_138: ; FMUL_R e3, a2 mulpd xmm7, xmm10 randomx_isn_139: ; IMUL_R r2, r6 imul r10, r14 randomx_isn_140: ; ISTORE L1[r0+1277653290], r3 lea eax, [r8d+1277653290] and eax, 16376 mov qword ptr [rsi+rax], r11 randomx_isn_141: ; IXOR_M r0, L1[r6-2131931958] lea eax, [r14d-2131931958] and eax, 16376 xor r8, qword ptr [rsi+rax] randomx_isn_142: ; FSUB_R f3, a3 subpd xmm3, xmm11 randomx_isn_143: ; IROL_R r6, r1 mov ecx, r9d rol r14, cl randomx_isn_144: ; FADD_R f1, a3 addpd xmm1, xmm11 randomx_isn_145: ; FMUL_R e0, a3 mulpd xmm4, xmm11 randomx_isn_146: ; FSQRT_R e0 sqrtpd xmm4, xmm4 randomx_isn_147: ; IADD_RS r7, r4, SHFT 0 lea r15, [r15+r12*1] randomx_isn_148: ; FSUB_R f3, a1 subpd xmm3, xmm9 randomx_isn_149: ; ISTORE L2[r1-1073333533], r3 lea eax, [r9d-1073333533] and eax, 262136 mov qword ptr [rsi+rax], r11 randomx_isn_150: ; FMUL_R e3, a3 mulpd xmm7, xmm11 randomx_isn_151: ; ISUB_R r6, r3 sub r14, r11 randomx_isn_152: ; IMULH_M r7, L2[r1+1647843648] lea ecx, [r9d+1647843648] and ecx, 262136 mov rax, r15 mul qword ptr [rsi+rcx] mov r15, rdx randomx_isn_153: ; FMUL_R e0, a0 mulpd xmm4, xmm8 randomx_isn_154: ; IROR_R r3, r0 mov ecx, r8d ror r11, cl randomx_isn_155: ; IADD_M r3, L1[r7-1322060518] lea eax, [r15d-1322060518] and eax, 16376 add r11, qword ptr [rsi+rax] randomx_isn_156: ; CBRANCH r3, 608981196, COND 1 add r11, 608981708 test r11, 130560 jz randomx_isn_156 randomx_isn_157: ; FSUB_M f0, L2[r7-252644586] lea eax, [r15d-252644586] and eax, 262136 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm0, xmm12 randomx_isn_158: ; CBRANCH r2, 868397474, COND 15 add r10, 864203170 test r10, 2139095040 jz randomx_isn_157 randomx_isn_159: ; ISUB_R r5, r3 sub r13, r11 randomx_isn_160: ; FMUL_R e0, a0 mulpd xmm4, xmm8 randomx_isn_161: ; FMUL_R e2, a1 mulpd xmm6, xmm9 randomx_isn_162: ; CBRANCH r0, 887338591, COND 6 add r8, 887346783 test r8, 4177920 jz randomx_isn_159 randomx_isn_163: ; IADD_RS r3, r3, SHFT 3 lea r11, [r11+r11*8] randomx_isn_164: ; IMUL_RCP r7, 3593878304 mov rax, 11022655166993703745 imul r15, rax randomx_isn_165: ; CBRANCH r0, 1452880957, COND 13 add r8, 1453929533 test r8, 534773760 jz randomx_isn_163 randomx_isn_166: ; ISUB_M r6, L2[r3+1539038396] lea eax, [r11d+1539038396] and eax, 262136 sub r14, qword ptr [rsi+rax] randomx_isn_167: ; IMUL_RCP r3, 1202036339 mov rax, 16477905023274079568 imul r11, rax randomx_isn_168: ; CBRANCH r1, -1295757940, COND 13 add r9, -1293660788 test r9, 534773760 jz randomx_isn_166 randomx_isn_169: ; FADD_M f2, L1[r2+876697387] lea eax, [r10d+876697387] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] addpd xmm2, xmm12 randomx_isn_170: ; IMUL_R r0, r6 imul r8, r14 randomx_isn_171: ; FMUL_R e1, a3 mulpd xmm5, xmm11 randomx_isn_172: ; FMUL_R e0, a2 mulpd xmm4, xmm10 randomx_isn_173: ; FSUB_M f3, L1[r2-1083472792] lea eax, [r10d-1083472792] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm3, xmm12 randomx_isn_174: ; CBRANCH r1, -1476890738, COND 14 add r9, -1478987890 test r9, 1069547520 jz randomx_isn_169 randomx_isn_175: ; ISUB_R r4, r7 sub r12, r15 randomx_isn_176: ; ISUB_R r0, 1685118604 sub r8, 1685118604 randomx_isn_177: ; FMUL_R e0, a1 mulpd xmm4, xmm9 randomx_isn_178: ; ISUB_M r0, L1[r7-1897974312] lea eax, [r15d-1897974312] and eax, 16376 sub r8, qword ptr [rsi+rax] randomx_isn_179: ; IXOR_R r4, r0 xor r12, r8 randomx_isn_180: ; IXOR_R r7, r2 xor r15, r10 randomx_isn_181: ; FSCAL_R f1 xorps xmm1, xmm15 randomx_isn_182: ; ISWAP_R r6, r2 xchg r14, r10 randomx_isn_183: ; IADD_RS r3, r1, SHFT 3 lea r11, [r11+r9*8] randomx_isn_184: ; ISTORE L1[r6-1997634426], r7 lea eax, [r14d-1997634426] and eax, 16376 mov qword ptr [rsi+rax], r15 randomx_isn_185: ; IXOR_R r2, r7 xor r10, r15 randomx_isn_186: ; IMUL_R r4, r3 imul r12, r11 randomx_isn_187: ; IMUL_RCP r7, 1830833174 mov rax, 10818593911149047378 imul r15, rax randomx_isn_188: ; FMUL_R e0, a2 mulpd xmm4, xmm10 randomx_isn_189: ; FADD_R f1, a3 addpd xmm1, xmm11 randomx_isn_190: ; CBRANCH r7, 121030040, COND 15 add r15, 129418648 test r15, 2139095040 jz randomx_isn_188 randomx_isn_191: ; IADD_RS r6, r1, SHFT 0 lea r14, [r14+r9*1] randomx_isn_192: ; FSUB_R f3, a2 subpd xmm3, xmm10 randomx_isn_193: ; CBRANCH r5, 1139434462, COND 11 add r13, 1139434462 test r13, 133693440 jz randomx_isn_191 randomx_isn_194: ; FMUL_R e2, a0 mulpd xmm6, xmm8 randomx_isn_195: ; FMUL_R e2, a3 mulpd xmm6, xmm11 randomx_isn_196: ; CBRANCH r4, 429294077, COND 2 add r12, 429295101 test r12, 261120 jz randomx_isn_194 randomx_isn_197: ; IMUL_R r1, r2 imul r9, r10 randomx_isn_198: ; FMUL_R e3, a0 mulpd xmm7, xmm8 randomx_isn_199: ; IMUL_R r2, r3 imul r10, r11 randomx_isn_200: ; IMUL_RCP r1, 193535702 mov rax, 12792885514067893012 imul r9, rax randomx_isn_201: ; IMUL_R r0, r5 imul r8, r13 randomx_isn_202: ; ISUB_R r1, r2 sub r9, r10 randomx_isn_203: ; FSUB_R f0, a3 subpd xmm0, xmm11 randomx_isn_204: ; FSQRT_R e3 sqrtpd xmm7, xmm7 randomx_isn_205: ; FMUL_R e0, a3 mulpd xmm4, xmm11 randomx_isn_206: ; IMUL_R r2, r1 imul r10, r9 randomx_isn_207: ; IADD_RS r1, r1, SHFT 3 lea r9, [r9+r9*8] randomx_isn_208: ; ISUB_R r6, r4 sub r14, r12 randomx_isn_209: ; ISUB_R r0, r7 sub r8, r15 randomx_isn_210: ; IADD_M r6, L1[r1+313140284] lea eax, [r9d+313140284] and eax, 16376 add r14, qword ptr [rsi+rax] randomx_isn_211: ; CBRANCH r4, 1358359929, COND 11 add r12, 1358622073 test r12, 133693440 jz randomx_isn_197 randomx_isn_212: ; FSQRT_R e0 sqrtpd xmm4, xmm4 randomx_isn_213: ; ISTORE L1[r3+18641493], r5 lea eax, [r11d+18641493] and eax, 16376 mov qword ptr [rsi+rax], r13 randomx_isn_214: ; CBRANCH r2, 1232471888, COND 7 add r10, 1232504656 test r10, 8355840 jz randomx_isn_212 randomx_isn_215: ; IADD_M r1, L1[r3+1138069575] lea eax, [r11d+1138069575] and eax, 16376 add r9, qword ptr [rsi+rax] randomx_isn_216: ; FSQRT_R e0 sqrtpd xmm4, xmm4 randomx_isn_217: ; IMUL_R r3, r4 imul r11, r12 randomx_isn_218: ; FMUL_R e3, a3 mulpd xmm7, xmm11 randomx_isn_219: ; IROL_R r7, r1 mov ecx, r9d rol r15, cl randomx_isn_220: ; FMUL_R e2, a1 mulpd xmm6, xmm9 randomx_isn_221: ; IXOR_M r2, L3[697832] xor r10, qword ptr [rsi+697832] randomx_isn_222: ; IADD_RS r1, r6, SHFT 2 lea r9, [r9+r14*4] randomx_isn_223: ; ISWAP_R r6, r2 xchg r14, r10 randomx_isn_224: ; ISUB_R r0, r1 sub r8, r9 randomx_isn_225: ; FSQRT_R e3 sqrtpd xmm7, xmm7 randomx_isn_226: ; ISUB_R r5, r1 sub r13, r9 randomx_isn_227: ; ISTORE L1[r0+238217802], r2 lea eax, [r8d+238217802] and eax, 16376 mov qword ptr [rsi+rax], r10 randomx_isn_228: ; IMUL_RCP r5, 324261767 mov rax, 15270872674734795667 imul r13, rax randomx_isn_229: ; FSCAL_R f0 xorps xmm0, xmm15 randomx_isn_230: ; FSQRT_R e3 sqrtpd xmm7, xmm7 randomx_isn_231: ; IROL_R r1, r5 mov ecx, r13d rol r9, cl randomx_isn_232: ; ISUB_R r6, r1 sub r14, r9 randomx_isn_233: ; FADD_R f2, a0 addpd xmm2, xmm8 randomx_isn_234: ; FADD_R f1, a3 addpd xmm1, xmm11 randomx_isn_235: ; IXOR_R r3, 1240450588 xor r11, 1240450588 randomx_isn_236: ; FSUB_R f1, a2 subpd xmm1, xmm10 randomx_isn_237: ; IMULH_R r6, r3 mov rax, r14 mul r11 mov r14, rdx randomx_isn_238: ; FSUB_R f1, a3 subpd xmm1, xmm11 randomx_isn_239: ; FSUB_R f1, a2 subpd xmm1, xmm10 randomx_isn_240: ; FSUB_M f1, L1[r7+1330184615] lea eax, [r15d+1330184615] and eax, 16376 cvtdq2pd xmm12, qword ptr [rsi+rax] subpd xmm1, xmm12 randomx_isn_241: ; FMUL_R e2, a3 mulpd xmm6, xmm11 randomx_isn_242: ; CBRANCH r3, -427325404, COND 11 add r11, -427063260 test r11, 133693440 jz randomx_isn_236 randomx_isn_243: ; IMUL_R r5, r7 imul r13, r15 randomx_isn_244: ; FMUL_R e3, a3 mulpd xmm7, xmm11 randomx_isn_245: ; ISMULH_M r7, L1[r0-84959236] lea ecx, [r8d-84959236] and ecx, 16376 mov rax, r15 imul qword ptr [rsi+rcx] mov r15, rdx randomx_isn_246: ; IMUL_R r6, r1 imul r14, r9 randomx_isn_247: ; FMUL_R e2, a1 mulpd xmm6, xmm9 randomx_isn_248: ; IADD_M r1, L2[r3+1223504721] lea eax, [r11d+1223504721] and eax, 262136 add r9, qword ptr [rsi+rax] randomx_isn_249: ; FADD_R f1, a2 addpd xmm1, xmm10 randomx_isn_250: ; IXOR_M r4, L1[r2-1447740505] lea eax, [r10d-1447740505] and eax, 16376 xor r12, qword ptr [rsi+rax] randomx_isn_251: ; IXOR_R r0, r5 xor r8, r13 randomx_isn_252: ; CBRANCH r4, -1337905977, COND 4 add r12, -1337903929 test r12, 1044480 jz randomx_isn_251 randomx_isn_253: ; FSUB_R f1, a1 subpd xmm1, xmm9 randomx_isn_254: ; FMUL_R e0, a0 mulpd xmm4, xmm8 randomx_isn_255: ; CBRANCH r5, 437071043, COND 11 add r13, 436808899 test r13, 133693440 jz randomx_isn_253 RandomX-1.1.10/doc/specs.md000066400000000000000000001361141414227164600153630ustar00rootroot00000000000000# RandomX RandomX is a proof of work (PoW) algorithm which was designed to close the gap between general-purpose CPUs and specialized hardware. The core of the algorithm is a simulation of a virtual CPU. #### Table of contents 1. [Definitions](#1-definitions) 1. [Algorithm description](#2-algorithm-description) 1. [Custom functions](#3-custom-functions) 1. [Virtual Machine](#4-virtual-machine) 1. [Instruction set](#5-instruction-set) 1. [SuperscalarHash](#6-superscalarhash) 1. [Dataset](#7-dataset) ## 1. Definitions ### 1.1 General definitions **Hash256** and **Hash512** refer to the [Blake2b](https://blake2.net/blake2_20130129.pdf) hashing function with a 256-bit and 512-bit output size, respectively. **Floating point format** refers to the [IEEE-754 double precision floating point format](https://en.wikipedia.org/wiki/Double-precision_floating-point_format) with a sign bit, 11-bit exponent and 52-bit fraction. **Argon2d** is a tradeoff-resistant variant of [Argon2](https://github.com/P-H-C/phc-winner-argon2/blob/master/argon2-specs.pdf), a memory-hard password derivation function. **AesGenerator1R** refers to an AES-based pseudo-random number generator described in chapter 3.2. It's initialized with a 512-bit seed value and is capable of producing more than 10 bytes per clock cycle. **AesGenerator4R** is a slower but more secure AES-based pseudo-random number generator described in chapter 3.3. It's initialized with a 512-bit seed value. **AesHash1R** refers to an AES-based fingerprinting function described in chapter 3.4. It's capable of processing more than 10 bytes per clock cycle and produces a 512-bit output. **BlakeGenerator** refers to a custom pseudo-random number generator described in chapter 3.5. It's based on the Blake2b hashing function. **SuperscalarHash** refers to a custom diffusion function designed to run efficiently on superscalar CPUs (see chapter 7). It transforms a 64-byte input value into a 64-byte output value. **Virtual Machine** or **VM** refers to the RandomX virtual machine as described in chapter 4. **Programming the VM** refers to the act of loading a program and configuration into the VM. This is described in chapter 4.5. **Executing the VM** refers to the act of running the program loop as described in chapter 4.6. **Scratchpad** refers to the workspace memory of the VM. The whole scratchpad is structured into 3 levels: L3 -> L2 -> L1 with each lower level being a subset of the higher levels. **Register File** refers to a 256-byte sequence formed by concatenating VM registers in little-endian format in the following order: `r0`-`r7`, `f0`-`f3`, `e0`-`e3` and `a0`-`a3`. **Program Buffer** refers to the buffer from which the VM reads instructions. **Cache** refers to a read-only buffer initialized by Argon2d as described in chapter 7.1. **Dataset** refers to a large read-only buffer described in chapter 7. It is constructed from the Cache using the SuperscalarHash function. ### 1.2 Configurable parameters RandomX has several configurable parameters that are listed in Table 1.2.1 with their default values. *Table 1.2.1 - Configurable parameters* |parameter|description|default value| |---------|-----|-------| |`RANDOMX_ARGON_MEMORY`|The number of 1 KiB Argon2 blocks in the Cache| `262144`| |`RANDOMX_ARGON_ITERATIONS`|The number of Argon2d iterations for Cache initialization|`3`| |`RANDOMX_ARGON_LANES`|The number of parallel lanes for Cache initialization|`1`| |`RANDOMX_ARGON_SALT`|Argon2 salt|`"RandomX\x03"`| |`RANDOMX_CACHE_ACCESSES`|The number of random Cache accesses per Dataset item|`8`| |`RANDOMX_SUPERSCALAR_LATENCY`|Target latency for SuperscalarHash (in cycles of the reference CPU)|`170`| |`RANDOMX_DATASET_BASE_SIZE`|Dataset base size in bytes|`2147483648`| |`RANDOMX_DATASET_EXTRA_SIZE`|Dataset extra size in bytes|`33554368`| |`RANDOMX_PROGRAM_SIZE`|The number of instructions in a RandomX program|`256`| |`RANDOMX_PROGRAM_ITERATIONS`|The number of iterations per program|`2048`| |`RANDOMX_PROGRAM_COUNT`|The number of programs per hash|`8`| |`RANDOMX_JUMP_BITS`|Jump condition mask size in bits|`8`| |`RANDOMX_JUMP_OFFSET`|Jump condition mask offset in bits|`8`| |`RANDOMX_SCRATCHPAD_L3`|Scratchpad L3 size in bytes|`2097152`| |`RANDOMX_SCRATCHPAD_L2`|Scratchpad L2 size in bytes|`262144`| |`RANDOMX_SCRATCHPAD_L1`|Scratchpad L1 size in bytes|`16384`| Instruction frequencies listed in Tables 5.2.1, 5.3.1, 5.4.1 and 5.5.1 are also configurable. ## 2. Algorithm description The RandomX algorithm accepts two input values: * String `K` with a size of 0-60 bytes (key) * String `H` of arbitrary length (the value to be hashed) and outputs a 256-bit result `R`. The algorithm consists of the following steps: 1. The Dataset is initialized using the key value `K` (described in chapter 7). 1. 64-byte seed `S` is calculated as `S = Hash512(H)`. 1. Let `gen1 = AesGenerator1R(S)`. 1. The Scratchpad is filled with `RANDOMX_SCRATCHPAD_L3` random bytes using generator `gen1`. 1. Let `gen4 = AesGenerator4R(gen1.state)` (use the final state of `gen1`). 1. The value of the VM register `fprc` is set to 0 (default rounding mode - chapter 4.3). 1. The VM is programmed using `128 + 8 * RANDOMX_PROGRAM_SIZE` random bytes using generator `gen4` (chapter 4.5). 1. The VM is executed (chapter 4.6). 1. A new 64-byte seed is calculated as `S = Hash512(RegisterFile)`. 1. Set `gen4.state = S` (modify the state of the generator). 1. Steps 7-10 are performed a total of `RANDOMX_PROGRAM_COUNT` times. The last iteration skips steps 9 and 10. 1. Scratchpad fingerprint is calculated as `A = AesHash1R(Scratchpad)`. 1. Bytes 192-255 of the Register File are set to the value of `A`. 1. Result is calculated as `R = Hash256(RegisterFile)`. The input of the `Hash512` function in step 9 is the following 256 bytes: ``` +---------------------------------+ | registers r0-r7 | (64 bytes) +---------------------------------+ | registers f0-f3 | (64 bytes) +---------------------------------+ | registers e0-e3 | (64 bytes) +---------------------------------+ | registers a0-a3 | (64 bytes) +---------------------------------+ ``` The input of the `Hash256` function in step 14 is the following 256 bytes: ``` +---------------------------------+ | registers r0-r7 | (64 bytes) +---------------------------------+ | registers f0-f3 | (64 bytes) +---------------------------------+ | registers e0-e3 | (64 bytes) +---------------------------------+ | AesHash1R(Scratchpad) | (64 bytes) +---------------------------------+ ``` ## 3 Custom functions ### 3.1 Definitions Two of the custom functions are based on the [Advanced Encryption Standard](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard) (AES). **AES encryption round** refers to the application of the ShiftRows, SubBytes and MixColumns transformations followed by a XOR with the round key. **AES decryption round** refers to the application of inverse ShiftRows, inverse SubBytes and inverse MixColumns transformations followed by a XOR with the round key. ### 3.2 AesGenerator1R AesGenerator1R produces a sequence of pseudo-random bytes. The internal state of the generator consists of 64 bytes arranged into four columns of 16 bytes each. During each output iteration, every column is decrypted (columns 0, 2) or encrypted (columns 1, 3) with one AES round using the following round keys (one key per column): ``` key0 = 53 a5 ac 6d 09 66 71 62 2b 55 b5 db 17 49 f4 b4 key1 = 07 af 7c 6d 0d 71 6a 84 78 d3 25 17 4e dc a1 0d key2 = f1 62 12 3f c6 7e 94 9f 4f 79 c0 f4 45 e3 20 3e key3 = 35 81 ef 6a 7c 31 ba b1 88 4c 31 16 54 91 16 49 ``` These keys were generated as: ``` key0, key1, key2, key3 = Hash512("RandomX AesGenerator1R keys") ``` Single iteration produces 64 bytes of output which also become the new generator state. ``` state0 (16 B) state1 (16 B) state2 (16 B) state3 (16 B) | | | | AES decrypt AES encrypt AES decrypt AES encrypt (key0) (key1) (key2) (key3) | | | | v v v v state0' state1' state2' state3' ``` ### 3.3 AesGenerator4R AesGenerator4R works similar way as AesGenerator1R, except it uses 4 rounds per column. Columns 0 and 1 use a different set of keys than columns 2 and 3. ``` state0 (16 B) state1 (16 B) state2 (16 B) state3 (16 B) | | | | AES decrypt AES encrypt AES decrypt AES encrypt (key0) (key0) (key4) (key4) | | | | v v v v AES decrypt AES encrypt AES decrypt AES encrypt (key1) (key1) (key5) (key5) | | | | v v v v AES decrypt AES encrypt AES decrypt AES encrypt (key2) (key2) (key6) (key6) | | | | v v v v AES decrypt AES encrypt AES decrypt AES encrypt (key3) (key3) (key7) (key7) | | | | v v v v state0' state1' state2' state3' ``` AesGenerator4R uses the following 8 round keys: ``` key0 = dd aa 21 64 db 3d 83 d1 2b 6d 54 2f 3f d2 e5 99 key1 = 50 34 0e b2 55 3f 91 b6 53 9d f7 06 e5 cd df a5 key2 = 04 d9 3e 5c af 7b 5e 51 9f 67 a4 0a bf 02 1c 17 key3 = 63 37 62 85 08 5d 8f e7 85 37 67 cd 91 d2 de d8 key4 = 73 6f 82 b5 a6 a7 d6 e3 6d 8b 51 3d b4 ff 9e 22 key5 = f3 6b 56 c7 d9 b3 10 9c 4e 4d 02 e9 d2 b7 72 b2 key6 = e7 c9 73 f2 8b a3 65 f7 0a 66 a9 2b a7 ef 3b f6 key7 = 09 d6 7c 7a de 39 58 91 fd d1 06 0c 2d 76 b0 c0 ``` These keys were generated as: ``` key0, key1, key2, key3 = Hash512("RandomX AesGenerator4R keys 0-3") key4, key5, key6, key7 = Hash512("RandomX AesGenerator4R keys 4-7") ``` ### 3.4 AesHash1R AesHash1R calculates a 512-bit fingerprint of its input. AesHash1R has a 64-byte internal state, which is arranged into four columns of 16 bytes each. The initial state is: ``` state0 = 0d 2c b5 92 de 56 a8 9f 47 db 82 cc ad 3a 98 d7 state1 = 6e 99 8d 33 98 b7 c7 15 5a 12 9e f5 57 80 e7 ac state2 = 17 00 77 6a d0 c7 62 ae 6b 50 79 50 e4 7c a0 e8 state3 = 0c 24 0a 63 8d 82 ad 07 05 00 a1 79 48 49 99 7e ``` The initial state vectors were generated as: ``` state0, state1, state2, state3 = Hash512("RandomX AesHash1R state") ``` The input is processed in 64-byte blocks. Each input block is considered to be a set of four AES round keys `key0`, `key1`, `key2`, `key3`. Each state column is encrypted (columns 0, 2) or decrypted (columns 1, 3) with one AES round using the corresponding round key: ``` state0 (16 B) state1 (16 B) state2 (16 B) state3 (16 B) | | | | AES encrypt AES decrypt AES encrypt AES decrypt (key0) (key1) (key2) (key3) | | | | v v v v state0' state1' state2' state3' ``` When all input bytes have been processed, the state is processed with two additional AES rounds with the following extra keys (one key per round, same pair of keys for all columns): ``` xkey0 = 89 83 fa f6 9f 94 24 8b bf 56 dc 90 01 02 89 06 xkey1 = d1 63 b2 61 3c e0 f4 51 c6 43 10 ee 9b f9 18 ed ``` The extra keys were generated as: ``` xkey0, xkey1 = Hash256("RandomX AesHash1R xkeys") ``` ``` state0 (16 B) state1 (16 B) state2 (16 B) state3 (16 B) | | | | AES encrypt AES decrypt AES encrypt AES decrypt (xkey0) (xkey0) (xkey0) (xkey0) | | | | v v v v AES encrypt AES decrypt AES encrypt AES decrypt (xkey1) (xkey1) (xkey1) (xkey1) | | | | v v v v finalState0 finalState1 finalState2 finalState3 ``` The final state is the output of the function. ### 3.5 BlakeGenerator BlakeGenerator is a simple pseudo-random number generator based on the Blake2b hashing function. It has a 64-byte internal state `S`. #### 3.5.1 Initialization The internal state is initialized from a seed value `K` (0-60 bytes long). The seed value is written into the internal state and padded with zeroes. Then the internal state is initialized as `S = Hash512(S)`. #### 3.5.2 Random number generation The generator can generate 1 byte or 4 bytes at a time by supplying data from its internal state `S`. If there are not enough unused bytes left, the internal state is reinitialized as `S = Hash512(S)`. ## 4. Virtual Machine The components of the RandomX virtual machine are summarized in Fig. 4.1. *Figure 4.1 - Virtual Machine* ![Imgur](https://i.imgur.com/Enk42b8.png) The VM is a complex instruction set computer ([CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)). All data are loaded and stored in little-endian byte order. Signed integer numbers are represented using [two's complement](https://en.wikipedia.org/wiki/Two%27s_complement). ### 4.1 Dataset Dataset is described in detail in chapter 7. It's a large read-only buffer. Its size is equal to `RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE` bytes. Each program uses only a random subset of the Dataset of size `RANDOMX_DATASET_BASE_SIZE`. All Dataset accesses read an aligned 64-byte item. ### 4.2 Scratchpad Scratchpad represents the workspace memory of the VM. Its size is `RANDOMX_SCRATCHPAD_L3` bytes and it's divided into 3 "levels": * The whole scratchpad is the third level "L3". * The first `RANDOMX_SCRATCHPAD_L2` bytes of the scratchpad is the second level "L2". * The first `RANDOMX_SCRATCHPAD_L1` bytes of the scratchpad is the first level "L1". The scratchpad levels are inclusive, i.e. L3 contains both L2 and L1 and L2 contains L1. To access a particular scratchpad level, bitwise AND with a mask according to table 4.2.1 is applied to the memory address. *Table 4.2.1: Scratchpad access masks* |Level|8-byte aligned mask|64-byte aligned mask| |---------|-|-| |L1|`(RANDOMX_SCRATCHPAD_L1 - 1) & ~7`|-| |L2|`(RANDOMX_SCRATCHPAD_L2 - 1) & ~7`|-| |L3|`(RANDOMX_SCRATCHPAD_L3 - 1) & ~7`|`(RANDOMX_SCRATCHPAD_L3 - 1) & ~63`| ### 4.3 Registers The VM has 8 integer registers `r0`-`r7` (group R) and a total of 12 floating point registers split into 3 groups: `f0`-`f3` (group F), `e0`-`e3` (group E) and `a0`-`a3` (group A). Integer registers are 64 bits wide, while floating point registers are 128 bits wide and contain a pair of numbers in floating point format. The lower and upper half of floating point registers are not separately addressable. Additionally, there are 3 internal registers `ma`, `mx` and `fprc`. Integer registers `r0`-`r7` can be the source or the destination operands of integer instructions or may be used as address registers for accessing the Scratchpad. Floating point registers `a0`-`a3` are read-only and their value is fixed for a given VM program. They can be the source operand of any floating point instruction. The value of these registers is restricted to the interval `[1, 4294967296)`. Floating point registers `f0`-`f3` are the "additive" registers, which can be the destination of floating point addition and subtraction instructions. The absolute value of these registers will not exceed about `3.0e+14`. Floating point registers `e0`-`e3` are the "multiplicative" registers, which can be the destination of floating point multiplication, division and square root instructions. Their value is always positive. `ma` and `mx` are the memory registers. Both are 32 bits wide. `ma` contains the memory address of the next Dataset read and `mx` contains the address of the next Dataset prefetch. The values of `ma` and `mx` registers are always aligned to be a multiple of 64. The 2-bit `fprc` register determines the rounding mode of all floating point operations according to Table 4.3.1. The four rounding modes are defined by the IEEE 754 standard. *Table 4.3.1: Rounding modes* |`fprc`|rounding mode| |-------|------------| |0|roundTiesToEven| |1|roundTowardNegative| |2|roundTowardPositive| |3|roundTowardZero| #### 4.3.1 Group F register conversion When an 8-byte value read from the memory is to be converted to an F group register value or operand, it is interpreted as a pair of 32-bit signed integers (in little endian, two's complement format) and converted to floating point format. This conversion is exact and doesn't need rounding because only 30 bits of the fraction significand are needed to represent the integer value. #### 4.3.2 Group E register conversion When an 8-byte value read from the memory is to be converted to an E group register value or operand, the same conversion procedure is applied as for F group registers (see 4.3.1) with additional post-processing steps for each of the two floating point values: 1. The sign bit is set to `0`. 2. Bits 0-2 of the exponent are set to the constant value of 0112. 3. Bits 3-6 of the exponent are set to the value of the exponent mask described in chapter 4.5.6. This value is fixed for a given VM program. 4. The bottom 22 bits of the fraction significand are set to the value of the fraction mask described in chapter 4.5.6. This value is fixed for a given VM program. ### 4.4 Program buffer The Program buffer stores the program to be executed by the VM. The program consists of `RANDOMX_PROGRAM_SIZE` instructions. Each instruction is encoded by an 8-byte word. The instruction set is described in chapter 5. ### 4.5 VM programming The VM requires `128 + 8 * RANDOMX_PROGRAM_SIZE` bytes to be programmed. This is split into two parts: * `128` bytes of configuration data = 16 quadwords (16×8 bytes), used according to Table 4.5.1 * `8 * RANDOMX_PROGRAM_SIZE` bytes of program data, copied directly into the Program Buffer *Table 4.5.1 - Configuration data* |quadword|description| |-----|-----------| |0|initialize low half of register `a0`| |1|initialize high half of register `a0`| |2|initialize low half of register `a1`| |3|initialize high half of register `a1`| |4|initialize low half of register `a2`| |5|initialize high half of register `a2`| |6|initialize low half of register `a3`| |7|initialize high half of register `a3`| |8|initialize register `ma`| |9|(reserved)| |10|initialize register `mx`| |11|(reserved)| |12|select address registers| |13|select Dataset offset| |14|initialize register masks for low half of group E registers| |15|initialize register masks for high half of group E registers| #### 4.5.2 Group A register initialization The values of the floating point registers `a0`-`a3` are initialized using configuration quadwords 0-7 to have the following value: +1.fraction x 2exponent The fraction has full 52 bits of precision and the exponent value ranges from 0 to 31. These values are obtained from the initialization quadword (in little endian format) according to Table 4.5.2. *Table 4.5.2 - Group A register initialization* |bits|description| |----|-----------| |0-51|fraction| |52-58|(reserved)| |59-63|exponent| #### 4.5.3 Memory registers Registers `ma` and `mx` are initialized using the low 32 bits of quadwords 8 and 10 in little endian format. #### 4.5.4 Address registers Bits 0-3 of quadword 12 are used to select 4 address registers for program execution. Each bit chooses one register from a pair of integer registers according to Table 4.5.3. *Table 4.5.3 - Address registers* |address register (bit)|value = 0|value = 1| |----------------------|-|-| |`readReg0` (0)|`r0`|`r1`| |`readReg1` (1)|`r2`|`r3`| |`readReg2` (2)|`r4`|`r5`| |`readReg3` (3)|`r6`|`r7`| #### 4.5.5 Dataset offset The `datasetOffset` is calculated as the remainder of dividing quadword 13 by `RANDOMX_DATASET_EXTRA_SIZE / 64 + 1`. The result is multiplied by `64`. This offset is used when reading values from the Dataset. #### 4.5.6 Group E register masks These masks are used for the conversion of group E registers (see 4.3.2). The low and high halves each have their own masks initialized from quadwords 14 and 15. The fraction mask is given by bits 0-21 and the exponent mask by bits 60-63 of the initialization quadword. ### 4.6 VM execution During VM execution, 3 additional temporary registers are used: `ic`, `spAddr0` and `spAddr1`. Program execution consists of initialization and loop execution. #### 4.6.1 Initialization 1. `ic` register is set to `RANDOMX_PROGRAM_ITERATIONS`. 2. `spAddr0` is set to the value of `mx`. 3. `spAddr1` is set to the value of `ma`. 4. The values of all integer registers `r0`-`r7` are set to zero. #### 4.6.2 Loop execution The loop described below is repeated until the value of the `ic` register reaches zero. 1. XOR of registers `readReg0` and `readReg1` (see Table 4.5.3) is calculated and `spAddr0` is XORed with the low 32 bits of the result and `spAddr1` with the high 32 bits. 2. `spAddr0` is used to perform a 64-byte aligned read from Scratchpad level 3 (using mask from Table 4.2.1). The 64 bytes are XORed with all integer registers in order `r0`-`r7`. 3. `spAddr1` is used to perform a 64-byte aligned read from Scratchpad level 3 (using mask from Table 4.2.1). Each floating point register `f0`-`f3` and `e0`-`e3` is initialized using an 8-byte value according to the conversion rules from chapters 4.3.1 and 4.3.2. 4. The 256 instructions stored in the Program Buffer are executed. 5. The `mx` register is XORed with the low 32 bits of registers `readReg2` and `readReg3` (see Table 4.5.3). 6. A 64-byte Dataset item at address `datasetOffset + mx % RANDOMX_DATASET_BASE_SIZE` is prefetched from the Dataset (it will be used during the next iteration). 7. A 64-byte Dataset item at address `datasetOffset + ma % RANDOMX_DATASET_BASE_SIZE` is loaded from the Dataset. The 64 bytes are XORed with all integer registers in order `r0`-`r7`. 8. The values of registers `mx` and `ma` are swapped. 9. The values of all integer registers `r0`-`r7` are written to the Scratchpad (L3) at address `spAddr1` (64-byte aligned). 10. Register `f0` is XORed with register `e0` and the result is stored in register `f0`. Register `f1` is XORed with register `e1` and the result is stored in register `f1`. Register `f2` is XORed with register `e2` and the result is stored in register `f2`. Register `f3` is XORed with register `e3` and the result is stored in register `f3`. 11. The values of registers `f0`-`f3` are written to the Scratchpad (L3) at address `spAddr0` (64-byte aligned). 12. `spAddr0` and `spAddr1` are both set to zero. 13. `ic` is decreased by 1. ## 5. Instruction set The VM executes programs in a special instruction set, which was designed in such way that any random 8-byte word is a valid instruction and any sequence of valid instructions is a valid program. Because there are no "syntax" rules, generating a random program is as easy as filling the program buffer with random data. ### 5.1 Instruction encoding Each instruction word is 64 bits long. Instruction fields are encoded as shown in Fig. 5.1. *Figure 5.1 - Instruction encoding* ![Imgur](https://i.imgur.com/FtkWRwe.png) #### 5.1.1 opcode There are 256 opcodes, which are distributed between 29 distinct instructions. Each instruction can be encoded using multiple opcodes (the number of opcodes specifies the frequency of the instruction in a random program). *Table 5.1.1: Instruction groups* |group|# instructions|# opcodes|| |---------|-----------------|----|-| |integer |17|120|46.9%| |floating point |9|94|36.7%| |control |2|26|10.2%| |store |1|16|6.2%| ||**29**|**256**|**100%** All instructions are described below in chapters 5.2 - 5.5. #### 5.1.2 dst Destination register. Only bits 0-1 (register groups A, F, E) or 0-2 (groups R, F+E) are used to encode a register according to Table 5.1.2. *Table 5.1.2: Addressable register groups* |index|R|A|F|E|F+E| |--|--|--|--|--|--| |0|`r0`|`a0`|`f0`|`e0`|`f0`| |1|`r1`|`a1`|`f1`|`e1`|`f1`| |2|`r2`|`a2`|`f2`|`e2`|`f2`| |3|`r3`|`a3`|`f3`|`e3`|`f3`| |4|`r4`||||`e0`| |5|`r5`||||`e1`| |6|`r6`||||`e2`| |7|`r7`||||`e3`| #### 5.1.3 src The `src` flag encodes a source operand register according to Table 5.1.2 (only bits 0-1 or 0-2 are used). Some integer instructions use a constant value as the source operand in cases when `dst` and `src` encode the same register (see Table 5.2.1). For register-memory instructions, the source operand is used to calculate the memory address. #### 5.1.4 mod The `mod` flag is encoded as: *Table 5.1.3: mod flag encoding* |`mod` bits|description|range of values| |----|--------|----| |0-1|`mod.mem` flag|0-3| |2-3|`mod.shift` flag|0-3| |4-7|`mod.cond` flag|0-15| The `mod.mem` flag selects between Scratchpad levels L1 and L2 when reading from or writing to memory except for two cases: * it's a memory read and `dst` and `src` encode the same register * it's a memory write `mod.cond` is 14 or 15 In these two cases, the Scratchpad level is L3 (see Table 5.1.4). *Table 5.1.4: memory access Scratchpad level* |condition|Scratchpad level| |---------|-| |`src == dst` (read)|L3| |`mod.cond >= 14` (write)|L3| |`mod.mem == 0`|L2| |`mod.mem != 0`|L1| The address for reading/writing is calculated by applying bitwise AND operation to the address and the 8-byte aligned address mask listed in Table 4.2.1. The `mod.cond` and `mod.shift` flags are used by some instructions (see 5.2, 5.4). #### 5.1.5 imm32 A 32-bit immediate value that can be used as the source operand and is used to calculate addresses for memory operations. The immediate value is sign-extended to 64 bits unless specified otherwise. ### 5.2 Integer instructions For integer instructions, the destination is always an integer register (register group R). Source operand (if applicable) can be either an integer register or memory value. If `dst` and `src` refer to the same register, most instructions use `0` or `imm32` instead of the register. This is indicated in the 'src == dst' column in Table 5.2.1. `[mem]` indicates a memory operand loaded as an 8-byte value from the address `src + imm32`. *Table 5.2.1 Integer instructions* |frequency|instruction|dst|src|`src == dst ?`|operation| |-|-|-|-|-|-| |16/256|IADD_RS|R|R|`src = dst`|`dst = dst + (src << mod.shift) (+ imm32)`| |7/256|IADD_M|R|R|`src = 0`|`dst = dst + [mem]`| |16/256|ISUB_R|R|R|`src = imm32`|`dst = dst - src`| |7/256|ISUB_M|R|R|`src = 0`|`dst = dst - [mem]`| |16/256|IMUL_R|R|R|`src = imm32`|`dst = dst * src`| |4/256|IMUL_M|R|R|`src = 0`|`dst = dst * [mem]`| |4/256|IMULH_R|R|R|`src = dst`|`dst = (dst * src) >> 64`| |1/256|IMULH_M|R|R|`src = 0`|`dst = (dst * [mem]) >> 64`| |4/256|ISMULH_R|R|R|`src = dst`|`dst = (dst * src) >> 64` (signed)| |1/256|ISMULH_M|R|R|`src = 0`|`dst = (dst * [mem]) >> 64` (signed)| |8/256|IMUL_RCP|R|-|-|dst = 2x / imm32 * dst| |2/256|INEG_R|R|-|-|`dst = -dst`| |15/256|IXOR_R|R|R|`src = imm32`|`dst = dst ^ src`| |5/256|IXOR_M|R|R|`src = 0`|`dst = dst ^ [mem]`| |8/256|IROR_R|R|R|`src = imm32`|`dst = dst >>> src`| |2/256|IROL_R|R|R|`src = imm32`|`dst = dst <<< src`| |4/256|ISWAP_R|R|R|`src = dst`|`temp = src; src = dst; dst = temp`| #### 5.2.1 IADD_RS This instructions adds the values of two registers (modulo 264). The value of the second operand is shifted left by 0-3 bits (determined by the `mod.shift` flag). Additionally, if `dst` is register `r5`, the immediate value `imm32` is added to the result. #### 5.2.2 IADD_M 64-bit integer addition operation (performed modulo 264) with a memory source operand. #### 5.2.3 ISUB_R, ISUB_M 64-bit integer subtraction (performed modulo 264). ISUB_R uses register source operand, ISUB_M uses a memory source operand. #### 5.2.4 IMUL_R, IMUL_M 64-bit integer multiplication (performed modulo 264). IMUL_R uses a register source operand, IMUL_M uses a memory source operand. #### 5.2.5 IMULH_R, IMULH_M, ISMULH_R, ISMULH_M These instructions output the high 64 bits of the whole 128-bit multiplication result. The result differs for signed and unsigned multiplication (IMULH is unsigned, ISMULH is signed). The variants with a register source operand perform a squaring operation if `dst` equals `src`. #### 5.2.6 IMUL_RCP If `imm32` equals 0 or is a power of 2, IMUL_RCP is a no-op. In other cases, the instruction multiplies the destination register by a reciprocal of `imm32` (the immediate value is zero-extended and treated as unsigned). The reciprocal is calculated as rcp = 2x / imm32 by choosing the largest integer `x` such that rcp < 264. #### 5.2.7 INEG_R Performs two's complement negation of the destination register. #### 5.2.8 IXOR_R, IXOR_M 64-bit exclusive OR operation. IXOR_R uses a register source operand, IXOR_M uses a memory source operand. #### 5.2.9 IROR_R, IROL_R Performs a cyclic shift (rotation) of the destination register. Source operand (shift count) is implicitly masked to 6 bits. IROR rotates bits right, IROL left. #### 5.2.9 ISWAP_R This instruction swaps the values of two registers. If source and destination refer to the same register, the result is a no-op. ### 5.3 Floating point instructions For floating point instructions, the destination can be a group F or group E register. Source operand is either a group A register or a memory value. `[mem]` indicates a memory operand loaded as an 8-byte value from the address `src + imm32` and converted according to the rules in chapters 4.3.1 (group F) or 4.3.2 (group E). The lower and upper memory operands are denoted as `[mem][0]` and `[mem][1]`. All floating point operations are rounded according to the current value of the `fprc` register (see Table 4.3.1). Due to restrictions on the values of the floating point registers, no operation results in `NaN` or a denormal number. *Table 5.3.1 Floating point instructions* |frequency|instruction|dst|src|operation| |-|-|-|-|-| |4/256|FSWAP_R|F+E|-|`(dst0, dst1) = (dst1, dst0)`| |16/256|FADD_R|F|A|`(dst0, dst1) = (dst0 + src0, dst1 + src1)`| |5/256|FADD_M|F|R|`(dst0, dst1) = (dst0 + [mem][0], dst1 + [mem][1])`| |16/256|FSUB_R|F|A|`(dst0, dst1) = (dst0 - src0, dst1 - src1)`| |5/256|FSUB_M|F|R|`(dst0, dst1) = (dst0 - [mem][0], dst1 - [mem][1])`| |6/256|FSCAL_R|F|-|(dst0, dst1) = (-2x0 * dst0, -2x1 * dst1)| |32/256|FMUL_R|E|A|`(dst0, dst1) = (dst0 * src0, dst1 * src1)`| |4/256|FDIV_M|E|R|`(dst0, dst1) = (dst0 / [mem][0], dst1 / [mem][1])`| |6/256|FSQRT_R|E|-|`(dst0, dst1) = (√dst0, √dst1)`| #### 5.3.1 FSWAP_R Swaps the lower and upper halves of the destination register. This is the only instruction that is applicable to both F an E register groups. #### 5.3.2 FADD_R, FADD_M Double precision floating point addition. FADD_R uses a group A register source operand, FADD_M uses a memory operand. #### 5.3.3 FSUB_R, FSUB_M Double precision floating point subtraction. FSUB_R uses a group A register source operand, FSUB_M uses a memory operand. #### 5.3.4 FSCAL_R This instruction negates the number and multiplies it by 2x. `x` is calculated by taking the 4 least significant digits of the biased exponent and interpreting them as a binary number using the digit set `{+1, -1}` as opposed to the traditional `{0, 1}`. The possible values of `x` are all odd numbers from -15 to +15. The mathematical operation described above is equivalent to a bitwise XOR of the binary representation with the value of `0x80F0000000000000`. #### 5.3.5 FMUL_R Double precision floating point multiplication. This instruction uses only a register source operand. #### 5.3.6 FDIV_M Double precision floating point division. This instruction uses only a memory source operand. #### 5.3.7 FSQRT_R Double precision floating point square root of the destination register. ### 5.4 Control instructions There are 2 control instructions. *Table 5.4.1 - Control instructions* |frequency|instruction|dst|src|operation| |-|-|-|-|-| |1/256|CFROUND|-|R|`fprc = src >>> imm32` |25/256|CBRANCH|R|-|`dst = dst + cimm`, conditional jump #### 5.4.1 CFROUND This instruction calculates a 2-bit value by rotating the source register right by `imm32` bits and taking the 2 least significant bits (the value of the source register is unaffected). The result is stored in the `fprc` register. This changes the rounding mode of all subsequent floating point instructions. #### 5.4.2 CBRANCH This instruction adds an immediate value `cimm` (constructed from `imm32`, see below) to the destination register and then performs a conditional jump in the Program Buffer based on the value of the destination register. The target of the jump is the instruction following the instruction when register `dst` was last modified. At the beginning of each program iteration, all registers are considered to be unmodified. A register is considered as modified by an instruction in the following cases: * It is the destination register of an integer instruction except IMUL_RCP and ISWAP_R. * It is the destination register of IMUL_RCP and `imm32` is not zero or a power of 2. * It is the source or the destination register of ISWAP_R and the destination and source registers are distinct. * The CBRANCH instruction is considered to modify all integer registers. If register `dst` has not been modified yet, the jump target is the first instruction in the Program Buffer. The CBRANCH instruction performs the following steps: 1. A constant `b` is calculated as `mod.cond + RANDOMX_JUMP_OFFSET`. 1. A constant `cimm` is constructed as sign-extended `imm32` with bit `b` set to 1 and bit `b-1` set to 0 (if `b > 0`). 1. `cimm` is added to the destination register. 1. If bits `b` to `b + RANDOMX_JUMP_BITS - 1` of the destination register are zero, the jump is executed (target is the instruction following the instruction where `dst` was last modified). Bits in immediate and register values are numbered from 0 to 63 with 0 being the least significant bit. For example, for `b = 10` and `RANDOMX_JUMP_BITS = 8`, the bits are arranged like this: ``` cimm = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSMMMMMMMMMMMMMMMMMMMMM10MMMMMMMMM dst = ..............................................XXXXXXXX.......... ``` `S` is a copied sign bit from `imm32`. `M` denotes bits of `imm32`. The 9th bit is set to 0 and the 10th bit is set to 1. This value will be added to `dst`. The second line uses `X` to mark bits of `dst` that will be checked by the condition. If all these bits are 0 after adding `cimm`, the jump is executed. The construction of the CBRANCH instruction ensures that no inifinite loops are possible in the program. ### 5.5 Store instruction There is one explicit store instruction for integer values. `[mem]` indicates the destination is an 8-byte value at the address `dst + imm32`. *Table 5.5.1 - Store instruction* |frequency|instruction|dst|src|operation| |-|-|-|-|-| |16/256|ISTORE|R|R|`[mem] = src` #### 5.5.1 ISTORE This instruction stores the value of the source integer register to the memory at the address calculated from the value of the destination register. The `src` and `dst` can be the same register. ## 6. SuperscalarHash SuperscalarHash is a custom diffusion function that was designed to burn as much power as possible using only the CPU's integer ALUs. The input and output of SuperscalarHash are 8 integer registers `r0`-`r7`, each 64 bits wide. The output of SuperscalarHash is used to construct the Dataset (see chapter 7.3). ### 6.1 Instructions The body of SuperscalarHash is a random sequence of instructions that can run on the Virtual Machine. SuperscalarHash uses a reduced set of only integer register-register instructions listed in Table 6.1.1. `dst` refers to the destination register, `src` to the source register. *Table 6.1.1 - SuperscalarHash instructions* |freq. †|instruction|Macro-ops|operation|rules| |-|-|-|-|-| |0.11|ISUB_R|`sub_rr`|`dst = dst - src`|`dst != src`| |0.11|IXOR_R|`xor_rr`|`dst = dst ^ src`|`dst != src`| |0.11|IADD_RS|`lea_sib`|`dst = dst + (src << mod.shift)`|`dst != src`, `dst != r5` |0.22|IMUL_R|`imul_rr`|`dst = dst * src`|`dst != src`| |0.11|IROR_C|`ror_ri`|`dst = dst >>> imm32`|`imm32 % 64 != 0` |0.10|IADD_C|`add_ri`|`dst = dst + imm32`| |0.10|IXOR_C|`xor_ri`|`dst = dst ^ imm32`| |0.03|IMULH_R|`mov_rr`,`mul_r`,`mov_rr`|`dst = (dst * src) >> 64`| |0.03|ISMULH_R|`mov_rr`,`imul_r`,`mov_rr`|`dst = (dst * src) >> 64` (signed)| |0.06|IMUL_RCP|`mov_ri`,`imul_rr`|dst = 2x / imm32 * dst|`imm32 != 0`, imm32 != 2N| † Frequencies are approximate. Instructions are generated based on complex rules. #### 6.1.1 ISUB_R See chapter 5.2.3. Source and destination are always distinct registers. #### 6.1.2 IXOR_R See chapter 5.2.8. Source and destination are always distinct registers. #### 6.1.3 IADD_RS See chapter 5.2.1. Source and destination are always distinct registers and register `r5` cannot be the destination. #### 6.1.4 IMUL_R See chapter 5.2.4. Source and destination are always distinct registers. #### 6.1.5 IROR_C The destination register is rotated right. The rotation count is given by `imm32` masked to 6 bits and cannot be 0. #### 6.1.6 IADD_C A sign-extended `imm32` is added to the destination register. #### 6.1.7 IXOR_C The destination register is XORed with a sign-extended `imm32`. #### 6.1.8 IMULH_R, ISMULH_R See chapter 5.2.5. #### 6.1.9 IMUL_RCP See chapter 5.2.6. `imm32` is never 0 or a power of 2. ### 6.2 The reference CPU Unlike a standard RandomX program, a SuperscalarHash program is generated using a strict set of rules to achieve the maximum performance on a superscalar CPU. For this purpose, the generator runs a simulation of a reference CPU. The reference CPU is loosely based on the [Intel Ivy Bridge microarchitecture](https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)). It has the following properties: * The CPU has 3 integer execution ports P0, P1 and P5 that can execute instructions in parallel. Multiplication can run only on port P1. * Each of the Superscalar instructions listed in Table 6.1.1 consist of one or more *Macro-ops*. Each Macro-op has certain execution latency (in cycles) and size (in bytes) as shown in Table 6.2.1. * Each of the Macro-ops listed in Table 6.2.1 consists of 0-2 *Micro-ops* that can go to a subset of the 3 execution ports. If a Macro-op consists of 2 Micro-ops, both must be executed together. * The CPU can decode at most 16 bytes of code per cycle and at most 4 Micro-ops per cycle. *Table 6.2.1 - Macro-ops* |Macro-op|latency|size|1st Micro-op|2nd Micro-op| |-|-|-|-|-| |`sub_rr`|1|3|P015|-| |`xor_rr`|1|3|P015|-| |`lea_sib`|1|4|P01|-| |`imul_rr`|3|4|P1|-| |`ror_ri`|1|4|P05|-| |`add_ri`|1|7, 8, 9|P015|-| |`xor_ri`|1|7, 8, 9|P015|-| |`mov_rr`|0|3|-|-| |`mul_r`|4|3|P1|P5| |`imul_r`|4|3|P1|P5| |`mov_ri`|1|10|P015|-| * P015 - Micro-op can be executed on any port * P01 - Micro-op can be executed on ports P0 or P1 * P05 - Micro-op can be executed on ports P0 or P5 * P1 - Micro-op can be executed only on port P1 * P5 - Micro-op can be executed only on port P5 Macro-ops `add_ri` and `xor_ri` can be optionally padded to a size of 8 or 9 bytes for code alignment purposes. `mov_rr` has 0 execution latency and doesn't use an execution port, but still occupies space during the decoding stage (see chapter 6.3.1). ### 6.3 CPU simulation SuperscalarHash programs are generated to maximize the usage of all 3 execution ports of the reference CPU. The generation consists of 4 stages: * Decoding stage * Instruction selection * Port assignment * Operand assignment Program generation is complete when one of two conditions is met: 1. An instruction is scheduled for execution on cycle that is equal to or greater than `RANDOMX_SUPERSCALAR_LATENCY` 1. The number of generated instructions reaches `3 * RANDOMX_SUPERSCALAR_LATENCY + 2`. #### 6.3.1 Decoding stage The generator produces instructions in groups of 3 or 4 Macro-op slots such that the size of each group is exactly 16 bytes. *Table 6.3.1 - Decoder configurations* |decoder group|configuration| |-------------|-------------| |0|4-8-4| |1|7-3-3-3| |2|3-7-3-3| |3|4-9-3| |4|4-4-4-4| |5|3-3-10| The rules for the selection of the decoder group are following: * If the currently processed instruction is IMULH_R or ISMULH_R, the next decode group is group 5 (the only group that starts with a 3-byte slot and has only 3 slots). * If the total number of multiplications that have been generated is less than or equal to the current decoding cycle, the next decode group is group 4. * If the currently processed instruction is IMUL_RCP, the next decode group is group 0 or 3 (must begin with a 4-byte slot for multiplication). * Otherwise a random decode group is selected from groups 0-3. #### 6.3.2 Instruction selection Instructions are selected based on the size of the current decode group slot - see Table 6.3.2. *Table 6.3.2 - Decoder configurations* |slot size|note|instructions| |-------------|-------------|-----| |3|-|ISUB_R, IXOR_R |3|last slot in the group|ISUB_R, IXOR_R, IMULH_R, ISMULH_R| |4|decode group 4, not the last slot|IMUL_R| |4|-|IROR_C, IADD_RS| |7,8,9|-|IADD_C, IXOR_C| |10|-|IMUL_RCP| #### 6.3.3 Port assignment Micro-ops are issued to execution ports as soon as an available port is free. The scheduling is done optimistically by checking port availability in order P5 -> P0 -> P1 to not overload port P1 (multiplication) by instructions that can go to any port. The cycle when all Micro-ops of an instruction can be executed is called the 'scheduleCycle'. #### 6.3.4 Operand assignment The source operand (if needed) is selected first. is it selected from the group of registers that are available at the 'scheduleCycle' of the instruction. A register is available if the latency of its last operation has elapsed. The destination operand is selected with more strict rules (see column 'rules' in Table 6.1.1): * value must be ready at the required cycle * cannot be the same as the source register unless the instruction allows it (see column 'rules' in Table 6.1.1) * this avoids optimizable operations such as `reg ^ reg` or `reg - reg` * it also increases intermixing of register values * register cannot be multiplied twice in a row unless `allowChainedMul` is true * this avoids accumulation of trailing zeroes in registers due to excessive multiplication * `allowChainedMul` is set to true if an attempt to find source/destination registers failed (this is quite rare, but prevents a catastrophic failure of the generator) * either the last instruction applied to the register or its source must be different than the current instruction * this avoids optimizable instruction sequences such as `r1 = r1 ^ r2; r1 = r1 ^ r2` (can be eliminated) or `reg = reg >>> C1; reg = reg >>> C2` (can be reduced to one rotation) or `reg = reg + C1; reg = reg + C2` (can be reduced to one addition) * register `r5` cannot be the destination of the IADD_RS instruction (limitation of the x86 lea instruction) ## 7. Dataset The Dataset is a read-only memory structure that is used during program execution (chapter 4.6.2, steps 6 and 7). The size of the Dataset is `RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE` bytes and it's divided into 64-byte 'items'. In order to allow PoW verification with a lower amount of memory, the Dataset is constructed in two steps using an intermediate structure called the "Cache", which can be used to calculate Dataset items on the fly. The whole Dataset is constructed from the key value `K`, which is an input parameter of RandomX. The whole Dataset needs to be recalculated everytime the key value changes. Fig. 7.1 shows the process of Dataset construction. Note: the maximum supported length of `K` is 60 bytes. Using a longer key results in implementation-defined behavior. *Figure 7.1 - Dataset construction* ![Imgur](https://i.imgur.com/86h5SbW.png) ### 7.1 Cache construction The key `K` is expanded into the Cache using the "memory fill" function of Argon2d with parameters according to Table 7.1.1. The key is used as the "password" field. *Table 7.1.1 - Argon2 parameters* |parameter|value| |------------|--| |parallelism|`RANDOMX_ARGON_LANES`| |output size|0| |memory|`RANDOMX_ARGON_MEMORY`| |iterations|`RANDOMX_ARGON_ITERATIONS`| |version|`0x13`| |hash type|0 (Argon2d)| |password|key value `K`| |salt|`RANDOMX_ARGON_SALT` |secret size|0| |assoc. data size|0| The finalizer and output calculation steps of Argon2 are omitted. The output is the filled memory array. ### 7.2 SuperscalarHash initialization The key value `K` is used to initialize a BlakeGenerator (see chapter 3.5), which is then used to generate 8 SuperscalarHash instances for Dataset initialization. ### 7.3 Dataset block generation Dataset items are numbered sequentially with `itemNumber` starting from 0. Each 64-byte Dataset item is generated independently using 8 SuperscalarHash functions (generated according to chapter 7.2) and by XORing randomly selected data from the Cache (constructed according to chapter 7.1). The item data is represented by 8 64-bit integer registers: `r0`-`r7`. 1. The register values are initialized as follows (`*` = multiplication, `^` = XOR): * `r0 = (itemNumber + 1) * 6364136223846793005` * `r1 = r0 ^ 9298411001130361340` * `r2 = r0 ^ 12065312585734608966` * `r3 = r0 ^ 9306329213124626780` * `r4 = r0 ^ 5281919268842080866` * `r5 = r0 ^ 10536153434571861004` * `r6 = r0 ^ 3398623926847679864` * `r7 = r0 ^ 9549104520008361294` 1. Let `cacheIndex = itemNumber` 1. Let `i = 0` 1. Load a 64-byte item from the Cache. The item index is given by `cacheIndex` modulo the total number of 64-byte items in Cache. 1. Execute `SuperscalarHash[i](r0, r1, r2, r3, r4, r5, r6, r7)`, where `SuperscalarHash[i]` refers to the i-th SuperscalarHash function. This modifies the values of the registers `r0`-`r7`. 1. XOR all registers with the 64 bytes loaded in step 4 (8 bytes per column in order `r0`-`r7`). 1. Set `cacheIndex` to the value of the register that has the longest dependency chain in the SuperscalarHash function executed in step 5. 1. Set `i = i + 1` and go back to step 4 if `i < RANDOMX_CACHE_ACCESSES`. 1. Concatenate registers `r0`-`r7` in little endian format to get the final Dataset item data. The constants used to initialize register values in step 1 were determined as follows: * Multiplier `6364136223846793005` was selected because it gives an excellent distribution for linear generators (D. Knuth: The Art of Computer Programming – Vol 2., also listed in [Commonly used LCG parameters](https://en.wikipedia.org/wiki/Linear_congruential_generator#Parameters_in_common_use)) * XOR constants used to initialize registers `r1`-`r7` were determined by calculating `Hash512` of the ASCII value `"RandomX SuperScalarHash initialize"` and taking bytes 8-63 as 7 little-endian unsigned 64-bit integers. Additionally, the constant for `r1` was increased by 233+700 and the constant for `r3` was increased by 214 (these changes are necessary to ensure that all registers have unique initial values for all values of `itemNumber`). RandomX-1.1.10/doc/tevador.asc000066400000000000000000000012101414227164600160440ustar00rootroot00000000000000-----BEGIN PGP PUBLIC KEY BLOCK----- mDMEXd+PeBYJKwYBBAHaRw8BAQdAZ0nqJ+nRYoScG2QLX62pl+WO1+Mkv6Yyt2Kb ntGUuLq0G3RldmFkb3IgPHRldmFkb3JAZ21haWwuY29tPoiWBBMWCAA+FiEEMoWj LVEwdmMs6CUQWijIaue9c6YFAl3fj3gCGwMFCQWnqDgFCwkIBwIGFQoJCAsCBBYC AwECHgECF4AACgkQWijIaue9c6YBFQD+N1XTUqSCZp9jB/yTHQ9ahSaIUMtmuvdT So2s+quudP4A/R5wLwukpfGN9UZ4cfpmKCJ9jO1HJ2udmlGMsJbQpDAIuDgEXd+P eBIKKwYBBAGXVQEFAQEHQBNbQuPcDojMCkRb5B5u7Ld/AFLClOh+6ElL+u61rIY/ AwEIB4h+BBgWCAAmFiEEMoWjLVEwdmMs6CUQWijIaue9c6YFAl3fj3gCGwwFCQWn qDgACgkQWijIaue9c6YJvgD+IY1Q9mCM1P1iZIoXuafRihXJ7UgVXpQqW2yoaUT3 bfQA/RkisI2eElYoOjdwPszPP6VfL5+SViwDmDuJG2P5llgE =V4vd -----END PGP PUBLIC KEY BLOCK----- RandomX-1.1.10/randomx.sln000066400000000000000000000301501414227164600153360ustar00rootroot00000000000000 Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio 15 VisualStudioVersion = 15.0.28307.572 MinimumVisualStudioVersion = 10.0.40219.1 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "randomx", "vcxproj\randomx.vcxproj", "{3346A4AD-C438-4324-8B77-47A16452954B}" EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "tests", "tests", "{4A4A689F-86AF-41C0-A974-1080506D0923}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "superscalar-avalanche", "vcxproj\superscalar-avalanche.vcxproj", "{CF34A7EF-7DC9-4077-94A5-76F5425EA938}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "superscalar-init", "vcxproj\superscalar-init.vcxproj", "{E59DC709-9B12-4A53-BAF3-79398821C376}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "superscalar-stats", "vcxproj\superscalar-stats.vcxproj", "{0173D560-8C12-46B3-B467-0C6E7573AA0B}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "benchmark", "vcxproj\benchmark.vcxproj", "{1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "api-example1", "vcxproj\api-example1.vcxproj", "{83EA3E54-5D91-4E01-8EF6-C1E718334F83}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "api-example2", "vcxproj\api-example2.vcxproj", "{44947B9C-E6B1-4C06-BD01-F8EF43B59223}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "code-generator", "vcxproj\code-generator.vcxproj", "{3E490DEC-1874-43AA-92DA-1AC57C217EAC}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "scratchpad-entropy", "vcxproj\scratchpad-entropy.vcxproj", "{FF8BD408-AFD8-43C6-BE98-4D03B37E840B}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "jit-performance", "vcxproj\jit-performance.vcxproj", "{535F2111-FA81-4C76-A354-EDD2F9AA00E3}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "perf-simulation", "vcxproj\perf-simulation.vcxproj", "{F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "runtime-distr", "vcxproj\runtime-distr.vcxproj", "{F207EC8C-C55F-46C0-8851-887A71574F54}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "randomx-dll", "vcxproj\randomx-dll.vcxproj", "{59560AD8-18E3-463E-A941-BBD808EC7C83}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "tests", "vcxproj\tests.vcxproj", "{41F3F4DF-8113-4029-9915-FDDC44C43D49}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|x64 = Debug|x64 Debug|x86 = Debug|x86 Release|x64 = Release|x64 Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {3346A4AD-C438-4324-8B77-47A16452954B}.Debug|x64.ActiveCfg = Debug|x64 {3346A4AD-C438-4324-8B77-47A16452954B}.Debug|x64.Build.0 = Debug|x64 {3346A4AD-C438-4324-8B77-47A16452954B}.Debug|x86.ActiveCfg = Debug|Win32 {3346A4AD-C438-4324-8B77-47A16452954B}.Debug|x86.Build.0 = Debug|Win32 {3346A4AD-C438-4324-8B77-47A16452954B}.Release|x64.ActiveCfg = Release|x64 {3346A4AD-C438-4324-8B77-47A16452954B}.Release|x64.Build.0 = Release|x64 {3346A4AD-C438-4324-8B77-47A16452954B}.Release|x86.ActiveCfg = Release|Win32 {3346A4AD-C438-4324-8B77-47A16452954B}.Release|x86.Build.0 = Release|Win32 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Debug|x64.ActiveCfg = Debug|x64 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Debug|x64.Build.0 = Debug|x64 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Debug|x86.ActiveCfg = Debug|Win32 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Debug|x86.Build.0 = Debug|Win32 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Release|x64.ActiveCfg = Release|x64 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Release|x64.Build.0 = Release|x64 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Release|x86.ActiveCfg = Release|Win32 {CF34A7EF-7DC9-4077-94A5-76F5425EA938}.Release|x86.Build.0 = Release|Win32 {E59DC709-9B12-4A53-BAF3-79398821C376}.Debug|x64.ActiveCfg = Debug|x64 {E59DC709-9B12-4A53-BAF3-79398821C376}.Debug|x64.Build.0 = Debug|x64 {E59DC709-9B12-4A53-BAF3-79398821C376}.Debug|x86.ActiveCfg = Debug|Win32 {E59DC709-9B12-4A53-BAF3-79398821C376}.Debug|x86.Build.0 = Debug|Win32 {E59DC709-9B12-4A53-BAF3-79398821C376}.Release|x64.ActiveCfg = Release|x64 {E59DC709-9B12-4A53-BAF3-79398821C376}.Release|x64.Build.0 = Release|x64 {E59DC709-9B12-4A53-BAF3-79398821C376}.Release|x86.ActiveCfg = Release|Win32 {E59DC709-9B12-4A53-BAF3-79398821C376}.Release|x86.Build.0 = Release|Win32 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Debug|x64.ActiveCfg = Debug|x64 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Debug|x64.Build.0 = Debug|x64 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Debug|x86.ActiveCfg = Debug|Win32 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Debug|x86.Build.0 = Debug|Win32 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Release|x64.ActiveCfg = Release|x64 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Release|x64.Build.0 = Release|x64 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Release|x86.ActiveCfg = Release|Win32 {0173D560-8C12-46B3-B467-0C6E7573AA0B}.Release|x86.Build.0 = Release|Win32 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Debug|x64.ActiveCfg = Debug|x64 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Debug|x64.Build.0 = Debug|x64 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Debug|x86.ActiveCfg = Debug|Win32 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Debug|x86.Build.0 = Debug|Win32 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Release|x64.ActiveCfg = Release|x64 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Release|x64.Build.0 = Release|x64 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Release|x86.ActiveCfg = Release|Win32 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70}.Release|x86.Build.0 = Release|Win32 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Debug|x64.ActiveCfg = Debug|x64 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Debug|x64.Build.0 = Debug|x64 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Debug|x86.ActiveCfg = Debug|Win32 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Debug|x86.Build.0 = Debug|Win32 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Release|x64.ActiveCfg = Release|x64 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Release|x64.Build.0 = Release|x64 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Release|x86.ActiveCfg = Release|Win32 {83EA3E54-5D91-4E01-8EF6-C1E718334F83}.Release|x86.Build.0 = Release|Win32 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Debug|x64.ActiveCfg = Debug|x64 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Debug|x64.Build.0 = Debug|x64 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Debug|x86.ActiveCfg = Debug|Win32 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Debug|x86.Build.0 = Debug|Win32 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Release|x64.ActiveCfg = Release|x64 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Release|x64.Build.0 = Release|x64 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Release|x86.ActiveCfg = Release|Win32 {44947B9C-E6B1-4C06-BD01-F8EF43B59223}.Release|x86.Build.0 = Release|Win32 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Debug|x64.ActiveCfg = Debug|x64 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Debug|x64.Build.0 = Debug|x64 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Debug|x86.ActiveCfg = Debug|Win32 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Debug|x86.Build.0 = Debug|Win32 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Release|x64.ActiveCfg = Release|x64 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Release|x64.Build.0 = Release|x64 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Release|x86.ActiveCfg = Release|Win32 {3E490DEC-1874-43AA-92DA-1AC57C217EAC}.Release|x86.Build.0 = Release|Win32 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Debug|x64.ActiveCfg = Debug|x64 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Debug|x64.Build.0 = Debug|x64 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Debug|x86.ActiveCfg = Debug|Win32 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Debug|x86.Build.0 = Debug|Win32 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Release|x64.ActiveCfg = Release|x64 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Release|x64.Build.0 = Release|x64 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Release|x86.ActiveCfg = Release|Win32 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B}.Release|x86.Build.0 = Release|Win32 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Debug|x64.ActiveCfg = Debug|x64 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Debug|x64.Build.0 = Debug|x64 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Debug|x86.ActiveCfg = Debug|Win32 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Debug|x86.Build.0 = Debug|Win32 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Release|x64.ActiveCfg = Release|x64 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Release|x64.Build.0 = Release|x64 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Release|x86.ActiveCfg = Release|Win32 {535F2111-FA81-4C76-A354-EDD2F9AA00E3}.Release|x86.Build.0 = Release|Win32 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Debug|x64.ActiveCfg = Debug|x64 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Debug|x64.Build.0 = Debug|x64 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Debug|x86.ActiveCfg = Debug|Win32 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Debug|x86.Build.0 = Debug|Win32 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Release|x64.ActiveCfg = Release|x64 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Release|x64.Build.0 = Release|x64 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Release|x86.ActiveCfg = Release|Win32 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2}.Release|x86.Build.0 = Release|Win32 {F207EC8C-C55F-46C0-8851-887A71574F54}.Debug|x64.ActiveCfg = Debug|x64 {F207EC8C-C55F-46C0-8851-887A71574F54}.Debug|x64.Build.0 = Debug|x64 {F207EC8C-C55F-46C0-8851-887A71574F54}.Debug|x86.ActiveCfg = Debug|Win32 {F207EC8C-C55F-46C0-8851-887A71574F54}.Debug|x86.Build.0 = Debug|Win32 {F207EC8C-C55F-46C0-8851-887A71574F54}.Release|x64.ActiveCfg = Release|x64 {F207EC8C-C55F-46C0-8851-887A71574F54}.Release|x64.Build.0 = Release|x64 {F207EC8C-C55F-46C0-8851-887A71574F54}.Release|x86.ActiveCfg = Release|Win32 {F207EC8C-C55F-46C0-8851-887A71574F54}.Release|x86.Build.0 = Release|Win32 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Debug|x64.ActiveCfg = Debug|x64 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Debug|x64.Build.0 = Debug|x64 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Debug|x86.ActiveCfg = Debug|Win32 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Debug|x86.Build.0 = Debug|Win32 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Release|x64.ActiveCfg = Release|x64 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Release|x64.Build.0 = Release|x64 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Release|x86.ActiveCfg = Release|Win32 {59560AD8-18E3-463E-A941-BBD808EC7C83}.Release|x86.Build.0 = Release|Win32 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Debug|x64.ActiveCfg = Debug|x64 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Debug|x64.Build.0 = Debug|x64 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Debug|x86.ActiveCfg = Debug|Win32 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Debug|x86.Build.0 = Debug|Win32 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Release|x64.ActiveCfg = Release|x64 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Release|x64.Build.0 = Release|x64 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Release|x86.ActiveCfg = Release|Win32 {41F3F4DF-8113-4029-9915-FDDC44C43D49}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE EndGlobalSection GlobalSection(NestedProjects) = preSolution {CF34A7EF-7DC9-4077-94A5-76F5425EA938} = {4A4A689F-86AF-41C0-A974-1080506D0923} {E59DC709-9B12-4A53-BAF3-79398821C376} = {4A4A689F-86AF-41C0-A974-1080506D0923} {0173D560-8C12-46B3-B467-0C6E7573AA0B} = {4A4A689F-86AF-41C0-A974-1080506D0923} {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70} = {4A4A689F-86AF-41C0-A974-1080506D0923} {83EA3E54-5D91-4E01-8EF6-C1E718334F83} = {4A4A689F-86AF-41C0-A974-1080506D0923} {44947B9C-E6B1-4C06-BD01-F8EF43B59223} = {4A4A689F-86AF-41C0-A974-1080506D0923} {3E490DEC-1874-43AA-92DA-1AC57C217EAC} = {4A4A689F-86AF-41C0-A974-1080506D0923} {FF8BD408-AFD8-43C6-BE98-4D03B37E840B} = {4A4A689F-86AF-41C0-A974-1080506D0923} {535F2111-FA81-4C76-A354-EDD2F9AA00E3} = {4A4A689F-86AF-41C0-A974-1080506D0923} {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2} = {4A4A689F-86AF-41C0-A974-1080506D0923} {F207EC8C-C55F-46C0-8851-887A71574F54} = {4A4A689F-86AF-41C0-A974-1080506D0923} {41F3F4DF-8113-4029-9915-FDDC44C43D49} = {4A4A689F-86AF-41C0-A974-1080506D0923} EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {4EBC03DB-AE37-4141-8147-692F16E0ED02} EndGlobalSection EndGlobal RandomX-1.1.10/src/000077500000000000000000000000001414227164600137405ustar00rootroot00000000000000RandomX-1.1.10/src/aes_hash.cpp000066400000000000000000000315761414227164600162330ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "soft_aes.h" #include //NOTE: The functions below were tuned for maximum performance //and are not cryptographically secure outside of the scope of RandomX. //It's not recommended to use them as general hash functions and PRNGs. //AesHash1R: //state0, state1, state2, state3 = Blake2b-512("RandomX AesHash1R state") //xkey0, xkey1 = Blake2b-256("RandomX AesHash1R xkeys") #define AES_HASH_1R_STATE0 0xd7983aad, 0xcc82db47, 0x9fa856de, 0x92b52c0d #define AES_HASH_1R_STATE1 0xace78057, 0xf59e125a, 0x15c7b798, 0x338d996e #define AES_HASH_1R_STATE2 0xe8a07ce4, 0x5079506b, 0xae62c7d0, 0x6a770017 #define AES_HASH_1R_STATE3 0x7e994948, 0x79a10005, 0x07ad828d, 0x630a240c #define AES_HASH_1R_XKEY0 0x06890201, 0x90dc56bf, 0x8b24949f, 0xf6fa8389 #define AES_HASH_1R_XKEY1 0xed18f99b, 0xee1043c6, 0x51f4e03c, 0x61b263d1 /* Calculate a 512-bit hash of 'input' using 4 lanes of AES. The input is treated as a set of round keys for the encryption of the initial state. 'inputSize' must be a multiple of 64. For a 2 MiB input, this has the same security as 32768-round AES encryption. Hashing throughput: >20 GiB/s per CPU core with hardware AES */ template void hashAes1Rx4(const void *input, size_t inputSize, void *hash) { assert(inputSize % 64 == 0); const uint8_t* inptr = (uint8_t*)input; const uint8_t* inputEnd = inptr + inputSize; rx_vec_i128 state0, state1, state2, state3; rx_vec_i128 in0, in1, in2, in3; //intial state state0 = rx_set_int_vec_i128(AES_HASH_1R_STATE0); state1 = rx_set_int_vec_i128(AES_HASH_1R_STATE1); state2 = rx_set_int_vec_i128(AES_HASH_1R_STATE2); state3 = rx_set_int_vec_i128(AES_HASH_1R_STATE3); //process 64 bytes at a time in 4 lanes while (inptr < inputEnd) { in0 = rx_load_vec_i128((rx_vec_i128*)inptr + 0); in1 = rx_load_vec_i128((rx_vec_i128*)inptr + 1); in2 = rx_load_vec_i128((rx_vec_i128*)inptr + 2); in3 = rx_load_vec_i128((rx_vec_i128*)inptr + 3); state0 = aesenc(state0, in0); state1 = aesdec(state1, in1); state2 = aesenc(state2, in2); state3 = aesdec(state3, in3); inptr += 64; } //two extra rounds to achieve full diffusion rx_vec_i128 xkey0 = rx_set_int_vec_i128(AES_HASH_1R_XKEY0); rx_vec_i128 xkey1 = rx_set_int_vec_i128(AES_HASH_1R_XKEY1); state0 = aesenc(state0, xkey0); state1 = aesdec(state1, xkey0); state2 = aesenc(state2, xkey0); state3 = aesdec(state3, xkey0); state0 = aesenc(state0, xkey1); state1 = aesdec(state1, xkey1); state2 = aesenc(state2, xkey1); state3 = aesdec(state3, xkey1); //output hash rx_store_vec_i128((rx_vec_i128*)hash + 0, state0); rx_store_vec_i128((rx_vec_i128*)hash + 1, state1); rx_store_vec_i128((rx_vec_i128*)hash + 2, state2); rx_store_vec_i128((rx_vec_i128*)hash + 3, state3); } template void hashAes1Rx4(const void *input, size_t inputSize, void *hash); template void hashAes1Rx4(const void *input, size_t inputSize, void *hash); //AesGenerator1R: //key0, key1, key2, key3 = Blake2b-512("RandomX AesGenerator1R keys") #define AES_GEN_1R_KEY0 0xb4f44917, 0xdbb5552b, 0x62716609, 0x6daca553 #define AES_GEN_1R_KEY1 0x0da1dc4e, 0x1725d378, 0x846a710d, 0x6d7caf07 #define AES_GEN_1R_KEY2 0x3e20e345, 0xf4c0794f, 0x9f947ec6, 0x3f1262f1 #define AES_GEN_1R_KEY3 0x49169154, 0x16314c88, 0xb1ba317c, 0x6aef8135 /* Fill 'buffer' with pseudorandom data based on 512-bit 'state'. The state is encrypted using a single AES round per 16 bytes of output in 4 lanes. 'outputSize' must be a multiple of 64. The modified state is written back to 'state' to allow multiple calls to this function. */ template void fillAes1Rx4(void *state, size_t outputSize, void *buffer) { assert(outputSize % 64 == 0); const uint8_t* outptr = (uint8_t*)buffer; const uint8_t* outputEnd = outptr + outputSize; rx_vec_i128 state0, state1, state2, state3; rx_vec_i128 key0, key1, key2, key3; key0 = rx_set_int_vec_i128(AES_GEN_1R_KEY0); key1 = rx_set_int_vec_i128(AES_GEN_1R_KEY1); key2 = rx_set_int_vec_i128(AES_GEN_1R_KEY2); key3 = rx_set_int_vec_i128(AES_GEN_1R_KEY3); state0 = rx_load_vec_i128((rx_vec_i128*)state + 0); state1 = rx_load_vec_i128((rx_vec_i128*)state + 1); state2 = rx_load_vec_i128((rx_vec_i128*)state + 2); state3 = rx_load_vec_i128((rx_vec_i128*)state + 3); while (outptr < outputEnd) { state0 = aesdec(state0, key0); state1 = aesenc(state1, key1); state2 = aesdec(state2, key2); state3 = aesenc(state3, key3); rx_store_vec_i128((rx_vec_i128*)outptr + 0, state0); rx_store_vec_i128((rx_vec_i128*)outptr + 1, state1); rx_store_vec_i128((rx_vec_i128*)outptr + 2, state2); rx_store_vec_i128((rx_vec_i128*)outptr + 3, state3); outptr += 64; } rx_store_vec_i128((rx_vec_i128*)state + 0, state0); rx_store_vec_i128((rx_vec_i128*)state + 1, state1); rx_store_vec_i128((rx_vec_i128*)state + 2, state2); rx_store_vec_i128((rx_vec_i128*)state + 3, state3); } template void fillAes1Rx4(void *state, size_t outputSize, void *buffer); template void fillAes1Rx4(void *state, size_t outputSize, void *buffer); //AesGenerator4R: //key0, key1, key2, key3 = Blake2b-512("RandomX AesGenerator4R keys 0-3") //key4, key5, key6, key7 = Blake2b-512("RandomX AesGenerator4R keys 4-7") #define AES_GEN_4R_KEY0 0x99e5d23f, 0x2f546d2b, 0xd1833ddb, 0x6421aadd #define AES_GEN_4R_KEY1 0xa5dfcde5, 0x06f79d53, 0xb6913f55, 0xb20e3450 #define AES_GEN_4R_KEY2 0x171c02bf, 0x0aa4679f, 0x515e7baf, 0x5c3ed904 #define AES_GEN_4R_KEY3 0xd8ded291, 0xcd673785, 0xe78f5d08, 0x85623763 #define AES_GEN_4R_KEY4 0x229effb4, 0x3d518b6d, 0xe3d6a7a6, 0xb5826f73 #define AES_GEN_4R_KEY5 0xb272b7d2, 0xe9024d4e, 0x9c10b3d9, 0xc7566bf3 #define AES_GEN_4R_KEY6 0xf63befa7, 0x2ba9660a, 0xf765a38b, 0xf273c9e7 #define AES_GEN_4R_KEY7 0xc0b0762d, 0x0c06d1fd, 0x915839de, 0x7a7cd609 template void fillAes4Rx4(void *state, size_t outputSize, void *buffer) { assert(outputSize % 64 == 0); const uint8_t* outptr = (uint8_t*)buffer; const uint8_t* outputEnd = outptr + outputSize; rx_vec_i128 state0, state1, state2, state3; rx_vec_i128 key0, key1, key2, key3, key4, key5, key6, key7; key0 = rx_set_int_vec_i128(AES_GEN_4R_KEY0); key1 = rx_set_int_vec_i128(AES_GEN_4R_KEY1); key2 = rx_set_int_vec_i128(AES_GEN_4R_KEY2); key3 = rx_set_int_vec_i128(AES_GEN_4R_KEY3); key4 = rx_set_int_vec_i128(AES_GEN_4R_KEY4); key5 = rx_set_int_vec_i128(AES_GEN_4R_KEY5); key6 = rx_set_int_vec_i128(AES_GEN_4R_KEY6); key7 = rx_set_int_vec_i128(AES_GEN_4R_KEY7); state0 = rx_load_vec_i128((rx_vec_i128*)state + 0); state1 = rx_load_vec_i128((rx_vec_i128*)state + 1); state2 = rx_load_vec_i128((rx_vec_i128*)state + 2); state3 = rx_load_vec_i128((rx_vec_i128*)state + 3); while (outptr < outputEnd) { state0 = aesdec(state0, key0); state1 = aesenc(state1, key0); state2 = aesdec(state2, key4); state3 = aesenc(state3, key4); state0 = aesdec(state0, key1); state1 = aesenc(state1, key1); state2 = aesdec(state2, key5); state3 = aesenc(state3, key5); state0 = aesdec(state0, key2); state1 = aesenc(state1, key2); state2 = aesdec(state2, key6); state3 = aesenc(state3, key6); state0 = aesdec(state0, key3); state1 = aesenc(state1, key3); state2 = aesdec(state2, key7); state3 = aesenc(state3, key7); rx_store_vec_i128((rx_vec_i128*)outptr + 0, state0); rx_store_vec_i128((rx_vec_i128*)outptr + 1, state1); rx_store_vec_i128((rx_vec_i128*)outptr + 2, state2); rx_store_vec_i128((rx_vec_i128*)outptr + 3, state3); outptr += 64; } } template void fillAes4Rx4(void *state, size_t outputSize, void *buffer); template void fillAes4Rx4(void *state, size_t outputSize, void *buffer); template void hashAndFillAes1Rx4(void *scratchpad, size_t scratchpadSize, void *hash, void* fill_state) { uint8_t* scratchpadPtr = (uint8_t*)scratchpad; const uint8_t* scratchpadEnd = scratchpadPtr + scratchpadSize; // initial state rx_vec_i128 hash_state0 = rx_set_int_vec_i128(AES_HASH_1R_STATE0); rx_vec_i128 hash_state1 = rx_set_int_vec_i128(AES_HASH_1R_STATE1); rx_vec_i128 hash_state2 = rx_set_int_vec_i128(AES_HASH_1R_STATE2); rx_vec_i128 hash_state3 = rx_set_int_vec_i128(AES_HASH_1R_STATE3); const rx_vec_i128 key0 = rx_set_int_vec_i128(AES_GEN_1R_KEY0); const rx_vec_i128 key1 = rx_set_int_vec_i128(AES_GEN_1R_KEY1); const rx_vec_i128 key2 = rx_set_int_vec_i128(AES_GEN_1R_KEY2); const rx_vec_i128 key3 = rx_set_int_vec_i128(AES_GEN_1R_KEY3); rx_vec_i128 fill_state0 = rx_load_vec_i128((rx_vec_i128*)fill_state + 0); rx_vec_i128 fill_state1 = rx_load_vec_i128((rx_vec_i128*)fill_state + 1); rx_vec_i128 fill_state2 = rx_load_vec_i128((rx_vec_i128*)fill_state + 2); rx_vec_i128 fill_state3 = rx_load_vec_i128((rx_vec_i128*)fill_state + 3); constexpr int PREFETCH_DISTANCE = 4096; const char* prefetchPtr = ((const char*)scratchpad) + PREFETCH_DISTANCE; scratchpadEnd -= PREFETCH_DISTANCE; for (int i = 0; i < 2; ++i) { //process 64 bytes at a time in 4 lanes while (scratchpadPtr < scratchpadEnd) { hash_state0 = aesenc(hash_state0, rx_load_vec_i128((rx_vec_i128*)scratchpadPtr + 0)); hash_state1 = aesdec(hash_state1, rx_load_vec_i128((rx_vec_i128*)scratchpadPtr + 1)); hash_state2 = aesenc(hash_state2, rx_load_vec_i128((rx_vec_i128*)scratchpadPtr + 2)); hash_state3 = aesdec(hash_state3, rx_load_vec_i128((rx_vec_i128*)scratchpadPtr + 3)); fill_state0 = aesdec(fill_state0, key0); fill_state1 = aesenc(fill_state1, key1); fill_state2 = aesdec(fill_state2, key2); fill_state3 = aesenc(fill_state3, key3); rx_store_vec_i128((rx_vec_i128*)scratchpadPtr + 0, fill_state0); rx_store_vec_i128((rx_vec_i128*)scratchpadPtr + 1, fill_state1); rx_store_vec_i128((rx_vec_i128*)scratchpadPtr + 2, fill_state2); rx_store_vec_i128((rx_vec_i128*)scratchpadPtr + 3, fill_state3); rx_prefetch_t0(prefetchPtr); scratchpadPtr += 64; prefetchPtr += 64; } prefetchPtr = (const char*) scratchpad; scratchpadEnd += PREFETCH_DISTANCE; } rx_store_vec_i128((rx_vec_i128*)fill_state + 0, fill_state0); rx_store_vec_i128((rx_vec_i128*)fill_state + 1, fill_state1); rx_store_vec_i128((rx_vec_i128*)fill_state + 2, fill_state2); rx_store_vec_i128((rx_vec_i128*)fill_state + 3, fill_state3); //two extra rounds to achieve full diffusion rx_vec_i128 xkey0 = rx_set_int_vec_i128(AES_HASH_1R_XKEY0); rx_vec_i128 xkey1 = rx_set_int_vec_i128(AES_HASH_1R_XKEY1); hash_state0 = aesenc(hash_state0, xkey0); hash_state1 = aesdec(hash_state1, xkey0); hash_state2 = aesenc(hash_state2, xkey0); hash_state3 = aesdec(hash_state3, xkey0); hash_state0 = aesenc(hash_state0, xkey1); hash_state1 = aesdec(hash_state1, xkey1); hash_state2 = aesenc(hash_state2, xkey1); hash_state3 = aesdec(hash_state3, xkey1); //output hash rx_store_vec_i128((rx_vec_i128*)hash + 0, hash_state0); rx_store_vec_i128((rx_vec_i128*)hash + 1, hash_state1); rx_store_vec_i128((rx_vec_i128*)hash + 2, hash_state2); rx_store_vec_i128((rx_vec_i128*)hash + 3, hash_state3); } template void hashAndFillAes1Rx4(void *scratchpad, size_t scratchpadSize, void *hash, void* fill_state); template void hashAndFillAes1Rx4(void *scratchpad, size_t scratchpadSize, void *hash, void* fill_state); RandomX-1.1.10/src/aes_hash.hpp000066400000000000000000000036271414227164600162340ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include template void hashAes1Rx4(const void *input, size_t inputSize, void *hash); template void fillAes1Rx4(void *state, size_t outputSize, void *buffer); template void fillAes4Rx4(void *state, size_t outputSize, void *buffer); template void hashAndFillAes1Rx4(void *scratchpad, size_t scratchpadSize, void *hash, void* fill_state); RandomX-1.1.10/src/allocator.cpp000066400000000000000000000043161414227164600164300ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "allocator.hpp" #include "intrin_portable.h" #include "virtual_memory.hpp" #include "common.hpp" namespace randomx { template void* AlignedAllocator::allocMemory(size_t count) { void *mem = rx_aligned_alloc(count, alignment); if (mem == nullptr) throw std::bad_alloc(); return mem; } template void AlignedAllocator::freeMemory(void* ptr, size_t count) { rx_aligned_free(ptr); } template struct AlignedAllocator; void* LargePageAllocator::allocMemory(size_t count) { return allocLargePagesMemory(count); } void LargePageAllocator::freeMemory(void* ptr, size_t count) { freePagedMemory(ptr, count); }; }RandomX-1.1.10/src/allocator.hpp000066400000000000000000000034431414227164600164350ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include namespace randomx { template struct AlignedAllocator { static void* allocMemory(size_t); static void freeMemory(void*, size_t); }; struct LargePageAllocator { static void* allocMemory(size_t); static void freeMemory(void*, size_t); }; }RandomX-1.1.10/src/argon2.h000066400000000000000000000207651414227164600153130ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #pragma once #include #include #include /* * Argon2 input parameter restrictions */ /* Minimum and maximum number of lanes (degree of parallelism) */ #define ARGON2_MIN_LANES UINT32_C(1) #define ARGON2_MAX_LANES UINT32_C(0xFFFFFF) /* Minimum and maximum number of threads */ #define ARGON2_MIN_THREADS UINT32_C(1) #define ARGON2_MAX_THREADS UINT32_C(0xFFFFFF) /* Number of synchronization points between lanes per pass */ #define ARGON2_SYNC_POINTS UINT32_C(4) /* Minimum and maximum digest size in bytes */ #define ARGON2_MIN_OUTLEN UINT32_C(4) #define ARGON2_MAX_OUTLEN UINT32_C(0xFFFFFFFF) /* Minimum and maximum number of memory blocks (each of BLOCK_SIZE bytes) */ #define ARGON2_MIN_MEMORY (2 * ARGON2_SYNC_POINTS) /* 2 blocks per slice */ #define ARGON2_MIN(a, b) ((a) < (b) ? (a) : (b)) /* Max memory size is addressing-space/2, topping at 2^32 blocks (4 TB) */ #define ARGON2_MAX_MEMORY_BITS \ ARGON2_MIN(UINT32_C(32), (sizeof(void *) * CHAR_BIT - 10 - 1)) #define ARGON2_MAX_MEMORY \ ARGON2_MIN(UINT32_C(0xFFFFFFFF), UINT64_C(1) << ARGON2_MAX_MEMORY_BITS) /* Minimum and maximum number of passes */ #define ARGON2_MIN_TIME UINT32_C(1) #define ARGON2_MAX_TIME UINT32_C(0xFFFFFFFF) /* Minimum and maximum password length in bytes */ #define ARGON2_MIN_PWD_LENGTH UINT32_C(0) #define ARGON2_MAX_PWD_LENGTH UINT32_C(0xFFFFFFFF) /* Minimum and maximum associated data length in bytes */ #define ARGON2_MIN_AD_LENGTH UINT32_C(0) #define ARGON2_MAX_AD_LENGTH UINT32_C(0xFFFFFFFF) /* Minimum and maximum salt length in bytes */ #define ARGON2_MIN_SALT_LENGTH UINT32_C(8) #define ARGON2_MAX_SALT_LENGTH UINT32_C(0xFFFFFFFF) /* Minimum and maximum key length in bytes */ #define ARGON2_MIN_SECRET UINT32_C(0) #define ARGON2_MAX_SECRET UINT32_C(0xFFFFFFFF) /* Flags to determine which fields are securely wiped (default = no wipe). */ #define ARGON2_DEFAULT_FLAGS UINT32_C(0) #define ARGON2_FLAG_CLEAR_PASSWORD (UINT32_C(1) << 0) #define ARGON2_FLAG_CLEAR_SECRET (UINT32_C(1) << 1) /* Error codes */ typedef enum Argon2_ErrorCodes { ARGON2_OK = 0, ARGON2_OUTPUT_PTR_NULL = -1, ARGON2_OUTPUT_TOO_SHORT = -2, ARGON2_OUTPUT_TOO_LONG = -3, ARGON2_PWD_TOO_SHORT = -4, ARGON2_PWD_TOO_LONG = -5, ARGON2_SALT_TOO_SHORT = -6, ARGON2_SALT_TOO_LONG = -7, ARGON2_AD_TOO_SHORT = -8, ARGON2_AD_TOO_LONG = -9, ARGON2_SECRET_TOO_SHORT = -10, ARGON2_SECRET_TOO_LONG = -11, ARGON2_TIME_TOO_SMALL = -12, ARGON2_TIME_TOO_LARGE = -13, ARGON2_MEMORY_TOO_LITTLE = -14, ARGON2_MEMORY_TOO_MUCH = -15, ARGON2_LANES_TOO_FEW = -16, ARGON2_LANES_TOO_MANY = -17, ARGON2_PWD_PTR_MISMATCH = -18, /* NULL ptr with non-zero length */ ARGON2_SALT_PTR_MISMATCH = -19, /* NULL ptr with non-zero length */ ARGON2_SECRET_PTR_MISMATCH = -20, /* NULL ptr with non-zero length */ ARGON2_AD_PTR_MISMATCH = -21, /* NULL ptr with non-zero length */ ARGON2_MEMORY_ALLOCATION_ERROR = -22, ARGON2_FREE_MEMORY_CBK_NULL = -23, ARGON2_ALLOCATE_MEMORY_CBK_NULL = -24, ARGON2_INCORRECT_PARAMETER = -25, ARGON2_INCORRECT_TYPE = -26, ARGON2_OUT_PTR_MISMATCH = -27, ARGON2_THREADS_TOO_FEW = -28, ARGON2_THREADS_TOO_MANY = -29, ARGON2_MISSING_ARGS = -30, ARGON2_ENCODING_FAIL = -31, ARGON2_DECODING_FAIL = -32, ARGON2_THREAD_FAIL = -33, ARGON2_DECODING_LENGTH_FAIL = -34, ARGON2_VERIFY_MISMATCH = -35 } argon2_error_codes; /* Memory allocator types --- for external allocation */ typedef int(*allocate_fptr)(uint8_t **memory, size_t bytes_to_allocate); typedef void(*deallocate_fptr)(uint8_t *memory, size_t bytes_to_allocate); /* Argon2 external data structures */ /* ***** * Context: structure to hold Argon2 inputs: * output array and its length, * password and its length, * salt and its length, * secret and its length, * associated data and its length, * number of passes, amount of used memory (in KBytes, can be rounded up a bit) * number of parallel threads that will be run. * All the parameters above affect the output hash value. * Additionally, two function pointers can be provided to allocate and * deallocate the memory (if NULL, memory will be allocated internally). * Also, three flags indicate whether to erase password, secret as soon as they * are pre-hashed (and thus not needed anymore), and the entire memory ***** * Simplest situation: you have output array out[8], password is stored in * pwd[32], salt is stored in salt[16], you do not have keys nor associated * data. You need to spend 1 GB of RAM and you run 5 passes of Argon2d with * 4 parallel lanes. * You want to erase the password, but you're OK with last pass not being * erased. You want to use the default memory allocator. * Then you initialize: Argon2_Context(out,8,pwd,32,salt,16,NULL,0,NULL,0,5,1<<20,4,4,NULL,NULL,true,false,false,false) */ typedef struct Argon2_Context { uint8_t *out; /* output array */ uint32_t outlen; /* digest length */ uint8_t *pwd; /* password array */ uint32_t pwdlen; /* password length */ uint8_t *salt; /* salt array */ uint32_t saltlen; /* salt length */ uint8_t *secret; /* key array */ uint32_t secretlen; /* key length */ uint8_t *ad; /* associated data array */ uint32_t adlen; /* associated data length */ uint32_t t_cost; /* number of passes */ uint32_t m_cost; /* amount of memory requested (KB) */ uint32_t lanes; /* number of lanes */ uint32_t threads; /* maximum number of threads */ uint32_t version; /* version number */ allocate_fptr allocate_cbk; /* pointer to memory allocator */ deallocate_fptr free_cbk; /* pointer to memory deallocator */ uint32_t flags; /* array of bool options */ } argon2_context; /* Argon2 primitive type */ typedef enum Argon2_type { Argon2_d = 0, Argon2_i = 1, Argon2_id = 2 } argon2_type; /* Version of the algorithm */ typedef enum Argon2_version { ARGON2_VERSION_10 = 0x10, ARGON2_VERSION_13 = 0x13, ARGON2_VERSION_NUMBER = ARGON2_VERSION_13 } argon2_version; //Argon2 instance - forward declaration typedef struct Argon2_instance_t argon2_instance_t; //Argon2 position = forward declaration typedef struct Argon2_position_t argon2_position_t; //Argon2 implementation function typedef void randomx_argon2_impl(const argon2_instance_t* instance, argon2_position_t position); #if defined(__cplusplus) extern "C" { #endif /* * Function that fills the segment using previous segments also from other * threads * @param context current context * @param instance Pointer to the current instance * @param position Current position * @pre all block pointers must be valid */ void randomx_argon2_fill_segment_ref(const argon2_instance_t* instance, argon2_position_t position); randomx_argon2_impl *randomx_argon2_impl_ssse3(); randomx_argon2_impl *randomx_argon2_impl_avx2(); #if defined(__cplusplus) } #endif RandomX-1.1.10/src/argon2_avx2.c000066400000000000000000000131101414227164600162300ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #include #include #include #include "argon2.h" void randomx_argon2_fill_segment_avx2(const argon2_instance_t* instance, argon2_position_t position); randomx_argon2_impl* randomx_argon2_impl_avx2() { #if defined(__AVX2__) return &randomx_argon2_fill_segment_avx2; #endif return NULL; } #if defined(__AVX2__) #include "argon2_core.h" #include "blake2/blamka-round-avx2.h" #include "blake2/blake2-impl.h" #include "blake2/blake2.h" static void fill_block(__m256i* state, const block* ref_block, block* next_block, int with_xor) { __m256i block_XY[ARGON2_HWORDS_IN_BLOCK]; unsigned int i; if (with_xor) { for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) { state[i] = _mm256_xor_si256( state[i], _mm256_loadu_si256((const __m256i*)ref_block->v + i)); block_XY[i] = _mm256_xor_si256( state[i], _mm256_loadu_si256((const __m256i*)next_block->v + i)); } } else { for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) { block_XY[i] = state[i] = _mm256_xor_si256( state[i], _mm256_loadu_si256((const __m256i*)ref_block->v + i)); } } for (i = 0; i < 4; ++i) { BLAKE2_ROUND_1(state[8 * i + 0], state[8 * i + 4], state[8 * i + 1], state[8 * i + 5], state[8 * i + 2], state[8 * i + 6], state[8 * i + 3], state[8 * i + 7]); } for (i = 0; i < 4; ++i) { BLAKE2_ROUND_2(state[0 + i], state[4 + i], state[8 + i], state[12 + i], state[16 + i], state[20 + i], state[24 + i], state[28 + i]); } for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) { state[i] = _mm256_xor_si256(state[i], block_XY[i]); _mm256_storeu_si256((__m256i*)next_block->v + i, state[i]); } } void randomx_argon2_fill_segment_avx2(const argon2_instance_t* instance, argon2_position_t position) { block* ref_block = NULL, * curr_block = NULL; block address_block, input_block; uint64_t pseudo_rand, ref_index, ref_lane; uint32_t prev_offset, curr_offset; uint32_t starting_index, i; __m256i state[ARGON2_HWORDS_IN_BLOCK]; if (instance == NULL) { return; } starting_index = 0; if ((0 == position.pass) && (0 == position.slice)) { starting_index = 2; /* we have already generated the first two blocks */ } /* Offset of the current block */ curr_offset = position.lane * instance->lane_length + position.slice * instance->segment_length + starting_index; if (0 == curr_offset % instance->lane_length) { /* Last block in this lane */ prev_offset = curr_offset + instance->lane_length - 1; } else { /* Previous block */ prev_offset = curr_offset - 1; } memcpy(state, ((instance->memory + prev_offset)->v), ARGON2_BLOCK_SIZE); for (i = starting_index; i < instance->segment_length; ++i, ++curr_offset, ++prev_offset) { /*1.1 Rotating prev_offset if needed */ if (curr_offset % instance->lane_length == 1) { prev_offset = curr_offset - 1; } /* 1.2 Computing the index of the reference block */ /* 1.2.1 Taking pseudo-random value from the previous block */ pseudo_rand = instance->memory[prev_offset].v[0]; /* 1.2.2 Computing the lane of the reference block */ ref_lane = ((pseudo_rand >> 32)) % instance->lanes; if ((position.pass == 0) && (position.slice == 0)) { /* Can not reference other lanes yet */ ref_lane = position.lane; } /* 1.2.3 Computing the number of possible reference block within the * lane. */ position.index = i; ref_index = randomx_argon2_index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, ref_lane == position.lane); /* 2 Creating a new block */ ref_block = instance->memory + instance->lane_length * ref_lane + ref_index; curr_block = instance->memory + curr_offset; if (ARGON2_VERSION_10 == instance->version) { /* version 1.2.1 and earlier: overwrite, not XOR */ fill_block(state, ref_block, curr_block, 0); } else { if (0 == position.pass) { fill_block(state, ref_block, curr_block, 0); } else { fill_block(state, ref_block, curr_block, 1); } } } } #endif RandomX-1.1.10/src/argon2_core.c000066400000000000000000000270361414227164600163140ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ /*For memory wiping*/ #ifdef _MSC_VER #include #include /* For SecureZeroMemory */ #endif #if defined __STDC_LIB_EXT1__ #define __STDC_WANT_LIB_EXT1__ 1 #endif #define VC_GE_2005(version) (version >= 1400) #include #include #include #include "argon2_core.h" #include "blake2/blake2.h" #include "blake2/blake2-impl.h" #ifdef GENKAT #include "genkat.h" #endif #if defined(__clang__) #if __has_attribute(optnone) #define NOT_OPTIMIZED __attribute__((optnone)) #endif #elif defined(__GNUC__) #define GCC_VERSION \ (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) #if GCC_VERSION >= 40400 #define NOT_OPTIMIZED __attribute__((optimize("O0"))) #endif #endif #ifndef NOT_OPTIMIZED #define NOT_OPTIMIZED #endif /***************Instance and Position constructors**********/ static void load_block(block *dst, const void *input) { unsigned i; for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { dst->v[i] = load64((const uint8_t *)input + i * sizeof(dst->v[i])); } } static void store_block(void *output, const block *src) { unsigned i; for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { store64((uint8_t *)output + i * sizeof(src->v[i]), src->v[i]); } } uint32_t randomx_argon2_index_alpha(const argon2_instance_t *instance, const argon2_position_t *position, uint32_t pseudo_rand, int same_lane) { /* * Pass 0: * This lane : all already finished segments plus already constructed * blocks in this segment * Other lanes : all already finished segments * Pass 1+: * This lane : (SYNC_POINTS - 1) last segments plus already constructed * blocks in this segment * Other lanes : (SYNC_POINTS - 1) last segments */ uint32_t reference_area_size; uint64_t relative_position; uint32_t start_position, absolute_position; if (0 == position->pass) { /* First pass */ if (0 == position->slice) { /* First slice */ reference_area_size = position->index - 1; /* all but the previous */ } else { if (same_lane) { /* The same lane => add current segment */ reference_area_size = position->slice * instance->segment_length + position->index - 1; } else { reference_area_size = position->slice * instance->segment_length + ((position->index == 0) ? (-1) : 0); } } } else { /* Second pass */ if (same_lane) { reference_area_size = instance->lane_length - instance->segment_length + position->index - 1; } else { reference_area_size = instance->lane_length - instance->segment_length + ((position->index == 0) ? (-1) : 0); } } /* 1.2.4. Mapping pseudo_rand to 0.. and produce * relative position */ relative_position = pseudo_rand; relative_position = relative_position * relative_position >> 32; relative_position = reference_area_size - 1 - (reference_area_size * relative_position >> 32); /* 1.2.5 Computing starting position */ start_position = 0; if (0 != position->pass) { start_position = (position->slice == ARGON2_SYNC_POINTS - 1) ? 0 : (position->slice + 1) * instance->segment_length; } /* 1.2.6. Computing absolute position */ absolute_position = (start_position + relative_position) % instance->lane_length; /* absolute position */ return absolute_position; } /* Single-threaded version for p=1 case */ static int fill_memory_blocks_st(argon2_instance_t *instance) { uint32_t r, s, l; for (r = 0; r < instance->passes; ++r) { for (s = 0; s < ARGON2_SYNC_POINTS; ++s) { for (l = 0; l < instance->lanes; ++l) { argon2_position_t position = { r, l, (uint8_t)s, 0 }; //fill the segment using the selected implementation instance->impl(instance, position); } } } return ARGON2_OK; } int randomx_argon2_fill_memory_blocks(argon2_instance_t *instance) { if (instance == NULL || instance->lanes == 0) { return ARGON2_INCORRECT_PARAMETER; } return fill_memory_blocks_st(instance); } int randomx_argon2_validate_inputs(const argon2_context *context) { if (NULL == context) { return ARGON2_INCORRECT_PARAMETER; } /* Validate password (required param) */ if (NULL == context->pwd) { if (0 != context->pwdlen) { return ARGON2_PWD_PTR_MISMATCH; } } if (ARGON2_MIN_PWD_LENGTH > context->pwdlen) { return ARGON2_PWD_TOO_SHORT; } if (ARGON2_MAX_PWD_LENGTH < context->pwdlen) { return ARGON2_PWD_TOO_LONG; } /* Validate salt (required param) */ if (NULL == context->salt) { if (0 != context->saltlen) { return ARGON2_SALT_PTR_MISMATCH; } } if (ARGON2_MIN_SALT_LENGTH > context->saltlen) { return ARGON2_SALT_TOO_SHORT; } if (ARGON2_MAX_SALT_LENGTH < context->saltlen) { return ARGON2_SALT_TOO_LONG; } /* Validate secret (optional param) */ if (NULL == context->secret) { if (0 != context->secretlen) { return ARGON2_SECRET_PTR_MISMATCH; } } else { if (ARGON2_MIN_SECRET > context->secretlen) { return ARGON2_SECRET_TOO_SHORT; } if (ARGON2_MAX_SECRET < context->secretlen) { return ARGON2_SECRET_TOO_LONG; } } /* Validate associated data (optional param) */ if (NULL == context->ad) { if (0 != context->adlen) { return ARGON2_AD_PTR_MISMATCH; } } else { if (ARGON2_MIN_AD_LENGTH > context->adlen) { return ARGON2_AD_TOO_SHORT; } if (ARGON2_MAX_AD_LENGTH < context->adlen) { return ARGON2_AD_TOO_LONG; } } /* Validate memory cost */ if (ARGON2_MIN_MEMORY > context->m_cost) { return ARGON2_MEMORY_TOO_LITTLE; } if (ARGON2_MAX_MEMORY < context->m_cost) { return ARGON2_MEMORY_TOO_MUCH; } if (context->m_cost < 8 * context->lanes) { return ARGON2_MEMORY_TOO_LITTLE; } /* Validate time cost */ if (ARGON2_MIN_TIME > context->t_cost) { return ARGON2_TIME_TOO_SMALL; } if (ARGON2_MAX_TIME < context->t_cost) { return ARGON2_TIME_TOO_LARGE; } /* Validate lanes */ if (ARGON2_MIN_LANES > context->lanes) { return ARGON2_LANES_TOO_FEW; } if (ARGON2_MAX_LANES < context->lanes) { return ARGON2_LANES_TOO_MANY; } /* Validate threads */ if (ARGON2_MIN_THREADS > context->threads) { return ARGON2_THREADS_TOO_FEW; } if (ARGON2_MAX_THREADS < context->threads) { return ARGON2_THREADS_TOO_MANY; } if (NULL != context->allocate_cbk && NULL == context->free_cbk) { return ARGON2_FREE_MEMORY_CBK_NULL; } if (NULL == context->allocate_cbk && NULL != context->free_cbk) { return ARGON2_ALLOCATE_MEMORY_CBK_NULL; } return ARGON2_OK; } void rxa2_fill_first_blocks(uint8_t *blockhash, const argon2_instance_t *instance) { uint32_t l; /* Make the first and second block in each lane as G(H0||0||i) or G(H0||1||i) */ uint8_t blockhash_bytes[ARGON2_BLOCK_SIZE]; for (l = 0; l < instance->lanes; ++l) { store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, 0); store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH + 4, l); blake2b_long(blockhash_bytes, ARGON2_BLOCK_SIZE, blockhash, ARGON2_PREHASH_SEED_LENGTH); load_block(&instance->memory[l * instance->lane_length + 0], blockhash_bytes); store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, 1); blake2b_long(blockhash_bytes, ARGON2_BLOCK_SIZE, blockhash, ARGON2_PREHASH_SEED_LENGTH); load_block(&instance->memory[l * instance->lane_length + 1], blockhash_bytes); } } void rxa2_initial_hash(uint8_t *blockhash, argon2_context *context, argon2_type type) { blake2b_state BlakeHash; uint8_t value[sizeof(uint32_t)]; if (NULL == context || NULL == blockhash) { return; } blake2b_init(&BlakeHash, ARGON2_PREHASH_DIGEST_LENGTH); store32(&value, context->lanes); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, context->outlen); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, context->m_cost); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, context->t_cost); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, context->version); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, (uint32_t)type); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); store32(&value, context->pwdlen); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); if (context->pwd != NULL) { blake2b_update(&BlakeHash, (const uint8_t *)context->pwd, context->pwdlen); } store32(&value, context->saltlen); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); if (context->salt != NULL) { blake2b_update(&BlakeHash, (const uint8_t *)context->salt, context->saltlen); } store32(&value, context->secretlen); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); if (context->secret != NULL) { blake2b_update(&BlakeHash, (const uint8_t *)context->secret, context->secretlen); } store32(&value, context->adlen); blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); if (context->ad != NULL) { blake2b_update(&BlakeHash, (const uint8_t *)context->ad, context->adlen); } blake2b_final(&BlakeHash, blockhash, ARGON2_PREHASH_DIGEST_LENGTH); } int randomx_argon2_initialize(argon2_instance_t *instance, argon2_context *context) { uint8_t blockhash[ARGON2_PREHASH_SEED_LENGTH]; int result = ARGON2_OK; if (instance == NULL || context == NULL) return ARGON2_INCORRECT_PARAMETER; instance->context_ptr = context; /* 1. Memory allocation */ //RandomX takes care of memory allocation /* 2. Initial hashing */ /* H_0 + 8 extra bytes to produce the first blocks */ /* uint8_t blockhash[ARGON2_PREHASH_SEED_LENGTH]; */ /* Hashing all inputs */ rxa2_initial_hash(blockhash, context, instance->type); /* Zeroing 8 extra bytes */ /*rxa2_clear_internal_memory(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, ARGON2_PREHASH_SEED_LENGTH - ARGON2_PREHASH_DIGEST_LENGTH);*/ /* 3. Creating first blocks, we always have at least two blocks in a slice */ rxa2_fill_first_blocks(blockhash, instance); return ARGON2_OK; } RandomX-1.1.10/src/argon2_core.h000066400000000000000000000134701414227164600163160ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef ARGON2_CORE_H #define ARGON2_CORE_H #include #include "argon2.h" #if defined(__cplusplus) extern "C" { #endif #define CONST_CAST(x) (x)(uintptr_t) /**********************Argon2 internal constants*******************************/ enum argon2_core_constants { /* Memory block size in bytes */ ARGON2_BLOCK_SIZE = 1024, ARGON2_QWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 8, ARGON2_OWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 16, ARGON2_HWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 32, ARGON2_512BIT_WORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 64, /* Number of pseudo-random values generated by one call to Blake in Argon2i to generate reference block positions */ ARGON2_ADDRESSES_IN_BLOCK = 128, /* Pre-hashing digest length and its extension*/ ARGON2_PREHASH_DIGEST_LENGTH = 64, ARGON2_PREHASH_SEED_LENGTH = 72 }; /*************************Argon2 internal data types***********************/ /* * Structure for the (1KB) memory block implemented as 128 64-bit words. * Memory blocks can be copied, XORed. Internal words can be accessed by [] (no * bounds checking). */ typedef struct block_ { uint64_t v[ARGON2_QWORDS_IN_BLOCK]; } block; /* * Argon2 instance: memory pointer, number of passes, amount of memory, type, * and derived values. * Used to evaluate the number and location of blocks to construct in each * thread */ typedef struct Argon2_instance_t { block *memory; /* Memory pointer */ uint32_t version; uint32_t passes; /* Number of passes */ uint32_t memory_blocks; /* Number of blocks in memory */ uint32_t segment_length; uint32_t lane_length; uint32_t lanes; uint32_t threads; argon2_type type; int print_internals; /* whether to print the memory blocks */ argon2_context *context_ptr; /* points back to original context */ randomx_argon2_impl *impl; } argon2_instance_t; /* * Argon2 position: where we construct the block right now. Used to distribute * work between threads. */ typedef struct Argon2_position_t { uint32_t pass; uint32_t lane; uint8_t slice; uint32_t index; } argon2_position_t; /*Struct that holds the inputs for thread handling FillSegment*/ typedef struct Argon2_thread_data { argon2_instance_t *instance_ptr; argon2_position_t pos; } argon2_thread_data; /*************************Argon2 core functions********************************/ /* * Computes absolute position of reference block in the lane following a skewed * distribution and using a pseudo-random value as input * @param instance Pointer to the current instance * @param position Pointer to the current position * @param pseudo_rand 32-bit pseudo-random value used to determine the position * @param same_lane Indicates if the block will be taken from the current lane. * If so we can reference the current segment * @pre All pointers must be valid */ uint32_t randomx_argon2_index_alpha(const argon2_instance_t *instance, const argon2_position_t *position, uint32_t pseudo_rand, int same_lane); /* * Function that validates all inputs against predefined restrictions and return * an error code * @param context Pointer to current Argon2 context * @return ARGON2_OK if everything is all right, otherwise one of error codes * (all defined in */ int randomx_argon2_validate_inputs(const argon2_context *context); /* * Function allocates memory, hashes the inputs with Blake, and creates first * two blocks. Returns the pointer to the main memory with 2 blocks per lane * initialized * @param context Pointer to the Argon2 internal structure containing memory * pointer, and parameters for time and space requirements. * @param instance Current Argon2 instance * @return Zero if successful, -1 if memory failed to allocate. @context->state * will be modified if successful. */ int randomx_argon2_initialize(argon2_instance_t *instance, argon2_context *context); /* * Function that fills the entire memory t_cost times based on the first two * blocks in each lane * @param instance Pointer to the current instance * @return ARGON2_OK if successful, @context->state */ int randomx_argon2_fill_memory_blocks(argon2_instance_t* instance); #if defined(__cplusplus) } #endif #endif RandomX-1.1.10/src/argon2_ref.c000066400000000000000000000150131414227164600161300ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #include #include #include #include "argon2.h" #include "argon2_core.h" #include "blake2/blamka-round-ref.h" #include "blake2/blake2-impl.h" #include "blake2/blake2.h" static void copy_block(block* dst, const block* src) { memcpy(dst->v, src->v, sizeof(uint64_t) * ARGON2_QWORDS_IN_BLOCK); } static void xor_block(block* dst, const block* src) { int i; for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { dst->v[i] ^= src->v[i]; } } /* * Function fills a new memory block and optionally XORs the old block over the new one. * @next_block must be initialized. * @param prev_block Pointer to the previous block * @param ref_block Pointer to the reference block * @param next_block Pointer to the block to be constructed * @param with_xor Whether to XOR into the new block (1) or just overwrite (0) * @pre all block pointers must be valid */ static void fill_block(const block *prev_block, const block *ref_block, block *next_block, int with_xor) { block blockR, block_tmp; unsigned i; copy_block(&blockR, ref_block); xor_block(&blockR, prev_block); copy_block(&block_tmp, &blockR); /* Now blockR = ref_block + prev_block and block_tmp = ref_block + prev_block */ if (with_xor) { /* Saving the next block contents for XOR over: */ xor_block(&block_tmp, next_block); /* Now blockR = ref_block + prev_block and block_tmp = ref_block + prev_block + next_block */ } /* Apply Blake2 on columns of 64-bit words: (0,1,...,15) , then (16,17,..31)... finally (112,113,...127) */ for (i = 0; i < 8; ++i) { BLAKE2_ROUND_NOMSG( blockR.v[16 * i], blockR.v[16 * i + 1], blockR.v[16 * i + 2], blockR.v[16 * i + 3], blockR.v[16 * i + 4], blockR.v[16 * i + 5], blockR.v[16 * i + 6], blockR.v[16 * i + 7], blockR.v[16 * i + 8], blockR.v[16 * i + 9], blockR.v[16 * i + 10], blockR.v[16 * i + 11], blockR.v[16 * i + 12], blockR.v[16 * i + 13], blockR.v[16 * i + 14], blockR.v[16 * i + 15]); } /* Apply Blake2 on rows of 64-bit words: (0,1,16,17,...112,113), then (2,3,18,19,...,114,115).. finally (14,15,30,31,...,126,127) */ for (i = 0; i < 8; i++) { BLAKE2_ROUND_NOMSG( blockR.v[2 * i], blockR.v[2 * i + 1], blockR.v[2 * i + 16], blockR.v[2 * i + 17], blockR.v[2 * i + 32], blockR.v[2 * i + 33], blockR.v[2 * i + 48], blockR.v[2 * i + 49], blockR.v[2 * i + 64], blockR.v[2 * i + 65], blockR.v[2 * i + 80], blockR.v[2 * i + 81], blockR.v[2 * i + 96], blockR.v[2 * i + 97], blockR.v[2 * i + 112], blockR.v[2 * i + 113]); } copy_block(next_block, &block_tmp); xor_block(next_block, &blockR); } void randomx_argon2_fill_segment_ref(const argon2_instance_t *instance, argon2_position_t position) { block *ref_block = NULL, *curr_block = NULL; block address_block, input_block, zero_block; uint64_t pseudo_rand, ref_index, ref_lane; uint32_t prev_offset, curr_offset; uint32_t starting_index; uint32_t i; if (instance == NULL) { return; } starting_index = 0; if ((0 == position.pass) && (0 == position.slice)) { starting_index = 2; /* we have already generated the first two blocks */ } /* Offset of the current block */ curr_offset = position.lane * instance->lane_length + position.slice * instance->segment_length + starting_index; if (0 == curr_offset % instance->lane_length) { /* Last block in this lane */ prev_offset = curr_offset + instance->lane_length - 1; } else { /* Previous block */ prev_offset = curr_offset - 1; } for (i = starting_index; i < instance->segment_length; ++i, ++curr_offset, ++prev_offset) { /*1.1 Rotating prev_offset if needed */ if (curr_offset % instance->lane_length == 1) { prev_offset = curr_offset - 1; } /* 1.2 Computing the index of the reference block */ /* 1.2.1 Taking pseudo-random value from the previous block */ pseudo_rand = instance->memory[prev_offset].v[0]; /* 1.2.2 Computing the lane of the reference block */ ref_lane = ((pseudo_rand >> 32)) % instance->lanes; if ((position.pass == 0) && (position.slice == 0)) { /* Can not reference other lanes yet */ ref_lane = position.lane; } /* 1.2.3 Computing the number of possible reference block within the * lane. */ position.index = i; ref_index = randomx_argon2_index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, ref_lane == position.lane); /* 2 Creating a new block */ ref_block = instance->memory + instance->lane_length * ref_lane + ref_index; curr_block = instance->memory + curr_offset; if (ARGON2_VERSION_10 == instance->version) { /* version 1.2.1 and earlier: overwrite, not XOR */ fill_block(instance->memory + prev_offset, ref_block, curr_block, 0); } else { if (0 == position.pass) { fill_block(instance->memory + prev_offset, ref_block, curr_block, 0); } else { fill_block(instance->memory + prev_offset, ref_block, curr_block, 1); } } } } RandomX-1.1.10/src/argon2_ssse3.c000066400000000000000000000133471414227164600164240ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #include #include #include #include "argon2.h" #if defined(_MSC_VER) //MSVC doesn't define SSSE3 #define __SSSE3__ #endif void randomx_argon2_fill_segment_ssse3(const argon2_instance_t* instance, argon2_position_t position); randomx_argon2_impl* randomx_argon2_impl_ssse3() { #if defined(__SSSE3__) return &randomx_argon2_fill_segment_ssse3; #endif return NULL; } #if defined(__SSSE3__) #include /* for _mm_shuffle_epi8 and _mm_alignr_epi8 */ #include "argon2_core.h" #include "blake2/blamka-round-ssse3.h" #include "blake2/blake2-impl.h" #include "blake2/blake2.h" static void fill_block(__m128i* state, const block* ref_block, block* next_block, int with_xor) { __m128i block_XY[ARGON2_OWORDS_IN_BLOCK]; unsigned int i; if (with_xor) { for (i = 0; i < ARGON2_OWORDS_IN_BLOCK; i++) { state[i] = _mm_xor_si128( state[i], _mm_loadu_si128((const __m128i*)ref_block->v + i)); block_XY[i] = _mm_xor_si128( state[i], _mm_loadu_si128((const __m128i*)next_block->v + i)); } } else { for (i = 0; i < ARGON2_OWORDS_IN_BLOCK; i++) { block_XY[i] = state[i] = _mm_xor_si128( state[i], _mm_loadu_si128((const __m128i*)ref_block->v + i)); } } for (i = 0; i < 8; ++i) { BLAKE2_ROUND(state[8 * i + 0], state[8 * i + 1], state[8 * i + 2], state[8 * i + 3], state[8 * i + 4], state[8 * i + 5], state[8 * i + 6], state[8 * i + 7]); } for (i = 0; i < 8; ++i) { BLAKE2_ROUND(state[8 * 0 + i], state[8 * 1 + i], state[8 * 2 + i], state[8 * 3 + i], state[8 * 4 + i], state[8 * 5 + i], state[8 * 6 + i], state[8 * 7 + i]); } for (i = 0; i < ARGON2_OWORDS_IN_BLOCK; i++) { state[i] = _mm_xor_si128(state[i], block_XY[i]); _mm_storeu_si128((__m128i*)next_block->v + i, state[i]); } } void randomx_argon2_fill_segment_ssse3(const argon2_instance_t* instance, argon2_position_t position) { block* ref_block = NULL, * curr_block = NULL; block address_block, input_block; uint64_t pseudo_rand, ref_index, ref_lane; uint32_t prev_offset, curr_offset; uint32_t starting_index, i; __m128i state[ARGON2_OWORDS_IN_BLOCK]; if (instance == NULL) { return; } starting_index = 0; if ((0 == position.pass) && (0 == position.slice)) { starting_index = 2; /* we have already generated the first two blocks */ } /* Offset of the current block */ curr_offset = position.lane * instance->lane_length + position.slice * instance->segment_length + starting_index; if (0 == curr_offset % instance->lane_length) { /* Last block in this lane */ prev_offset = curr_offset + instance->lane_length - 1; } else { /* Previous block */ prev_offset = curr_offset - 1; } memcpy(state, ((instance->memory + prev_offset)->v), ARGON2_BLOCK_SIZE); for (i = starting_index; i < instance->segment_length; ++i, ++curr_offset, ++prev_offset) { /*1.1 Rotating prev_offset if needed */ if (curr_offset % instance->lane_length == 1) { prev_offset = curr_offset - 1; } /* 1.2 Computing the index of the reference block */ /* 1.2.1 Taking pseudo-random value from the previous block */ pseudo_rand = instance->memory[prev_offset].v[0]; /* 1.2.2 Computing the lane of the reference block */ ref_lane = ((pseudo_rand >> 32)) % instance->lanes; if ((position.pass == 0) && (position.slice == 0)) { /* Can not reference other lanes yet */ ref_lane = position.lane; } /* 1.2.3 Computing the number of possible reference block within the * lane. */ position.index = i; ref_index = randomx_argon2_index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, ref_lane == position.lane); /* 2 Creating a new block */ ref_block = instance->memory + instance->lane_length * ref_lane + ref_index; curr_block = instance->memory + curr_offset; if (ARGON2_VERSION_10 == instance->version) { /* version 1.2.1 and earlier: overwrite, not XOR */ fill_block(state, ref_block, curr_block, 0); } else { if (0 == position.pass) { fill_block(state, ref_block, curr_block, 0); } else { fill_block(state, ref_block, curr_block, 1); } } } } #endif RandomX-1.1.10/src/asm/000077500000000000000000000000001414227164600145205ustar00rootroot00000000000000RandomX-1.1.10/src/asm/configuration.asm000066400000000000000000000026361414227164600201000ustar00rootroot00000000000000; File start: ..\src\configuration.h RANDOMX_ARGON_MEMORY EQU 262144t RANDOMX_ARGON_ITERATIONS EQU 3t RANDOMX_ARGON_LANES EQU 1t RANDOMX_ARGON_SALT TEXTEQU <"RandomX\x03"> RANDOMX_CACHE_ACCESSES EQU 8t RANDOMX_SUPERSCALAR_LATENCY EQU 170t RANDOMX_DATASET_BASE_SIZE EQU 2147483648t RANDOMX_DATASET_EXTRA_SIZE EQU 33554368t RANDOMX_PROGRAM_SIZE EQU 256t RANDOMX_PROGRAM_ITERATIONS EQU 2048t RANDOMX_PROGRAM_COUNT EQU 8t RANDOMX_SCRATCHPAD_L3 EQU 2097152t RANDOMX_SCRATCHPAD_L2 EQU 262144t RANDOMX_SCRATCHPAD_L1 EQU 16384t RANDOMX_JUMP_BITS EQU 8t RANDOMX_JUMP_OFFSET EQU 8t RANDOMX_FREQ_IADD_RS EQU 16t RANDOMX_FREQ_IADD_M EQU 7t RANDOMX_FREQ_ISUB_R EQU 16t RANDOMX_FREQ_ISUB_M EQU 7t RANDOMX_FREQ_IMUL_R EQU 16t RANDOMX_FREQ_IMUL_M EQU 4t RANDOMX_FREQ_IMULH_R EQU 4t RANDOMX_FREQ_IMULH_M EQU 1t RANDOMX_FREQ_ISMULH_R EQU 4t RANDOMX_FREQ_ISMULH_M EQU 1t RANDOMX_FREQ_IMUL_RCP EQU 8t RANDOMX_FREQ_INEG_R EQU 2t RANDOMX_FREQ_IXOR_R EQU 15t RANDOMX_FREQ_IXOR_M EQU 5t RANDOMX_FREQ_IROR_R EQU 8t RANDOMX_FREQ_IROL_R EQU 2t RANDOMX_FREQ_ISWAP_R EQU 4t RANDOMX_FREQ_FSWAP_R EQU 4t RANDOMX_FREQ_FADD_R EQU 16t RANDOMX_FREQ_FADD_M EQU 5t RANDOMX_FREQ_FSUB_R EQU 16t RANDOMX_FREQ_FSUB_M EQU 5t RANDOMX_FREQ_FSCAL_R EQU 6t RANDOMX_FREQ_FMUL_R EQU 32t RANDOMX_FREQ_FDIV_M EQU 4t RANDOMX_FREQ_FSQRT_R EQU 6t RANDOMX_FREQ_CBRANCH EQU 25t RANDOMX_FREQ_CFROUND EQU 1t RANDOMX_FREQ_ISTORE EQU 16t RANDOMX_FREQ_NOP EQU 0t ; File end: ..\src\configuration.h RandomX-1.1.10/src/asm/program_epilogue_linux.inc000066400000000000000000000002121414227164600217650ustar00rootroot00000000000000 ;# restore callee-saved registers - System V AMD64 ABI pop r15 pop r14 pop r13 pop r12 pop rbp pop rbx ;# program finished ret 0RandomX-1.1.10/src/asm/program_epilogue_store.inc000066400000000000000000000010651414227164600217710ustar00rootroot00000000000000 ;# save VM register values pop rcx mov qword ptr [rcx+0], r8 mov qword ptr [rcx+8], r9 mov qword ptr [rcx+16], r10 mov qword ptr [rcx+24], r11 mov qword ptr [rcx+32], r12 mov qword ptr [rcx+40], r13 mov qword ptr [rcx+48], r14 mov qword ptr [rcx+56], r15 movdqa xmmword ptr [rcx+64], xmm0 movdqa xmmword ptr [rcx+80], xmm1 movdqa xmmword ptr [rcx+96], xmm2 movdqa xmmword ptr [rcx+112], xmm3 lea rcx, [rcx+64] movdqa xmmword ptr [rcx+64], xmm4 movdqa xmmword ptr [rcx+80], xmm5 movdqa xmmword ptr [rcx+96], xmm6 movdqa xmmword ptr [rcx+112], xmm7RandomX-1.1.10/src/asm/program_epilogue_win64.inc000066400000000000000000000010411414227164600215760ustar00rootroot00000000000000 ;# restore callee-saved registers - Microsoft x64 calling convention movdqu xmm15, xmmword ptr [rsp] movdqu xmm14, xmmword ptr [rsp+16] movdqu xmm13, xmmword ptr [rsp+32] movdqu xmm12, xmmword ptr [rsp+48] movdqu xmm11, xmmword ptr [rsp+64] add rsp, 80 movdqu xmm10, xmmword ptr [rsp] movdqu xmm9, xmmword ptr [rsp+16] movdqu xmm8, xmmword ptr [rsp+32] movdqu xmm7, xmmword ptr [rsp+48] movdqu xmm6, xmmword ptr [rsp+64] add rsp, 80 pop r15 pop r14 pop r13 pop r12 pop rsi pop rdi pop rbp pop rbx ;# program finished ret RandomX-1.1.10/src/asm/program_loop_load.inc000066400000000000000000000013141414227164600207110ustar00rootroot00000000000000 lea rcx, [rsi+rax] push rcx xor r8, qword ptr [rcx+0] xor r9, qword ptr [rcx+8] xor r10, qword ptr [rcx+16] xor r11, qword ptr [rcx+24] xor r12, qword ptr [rcx+32] xor r13, qword ptr [rcx+40] xor r14, qword ptr [rcx+48] xor r15, qword ptr [rcx+56] lea rcx, [rsi+rdx] push rcx cvtdq2pd xmm0, qword ptr [rcx+0] cvtdq2pd xmm1, qword ptr [rcx+8] cvtdq2pd xmm2, qword ptr [rcx+16] cvtdq2pd xmm3, qword ptr [rcx+24] cvtdq2pd xmm4, qword ptr [rcx+32] cvtdq2pd xmm5, qword ptr [rcx+40] cvtdq2pd xmm6, qword ptr [rcx+48] cvtdq2pd xmm7, qword ptr [rcx+56] andps xmm4, xmm13 andps xmm5, xmm13 andps xmm6, xmm13 andps xmm7, xmm13 orps xmm4, xmm14 orps xmm5, xmm14 orps xmm6, xmm14 orps xmm7, xmm14 RandomX-1.1.10/src/asm/program_loop_store.inc000066400000000000000000000007111414227164600211260ustar00rootroot00000000000000 pop rcx mov qword ptr [rcx+0], r8 mov qword ptr [rcx+8], r9 mov qword ptr [rcx+16], r10 mov qword ptr [rcx+24], r11 mov qword ptr [rcx+32], r12 mov qword ptr [rcx+40], r13 mov qword ptr [rcx+48], r14 mov qword ptr [rcx+56], r15 pop rcx xorpd xmm0, xmm4 xorpd xmm1, xmm5 xorpd xmm2, xmm6 xorpd xmm3, xmm7 movapd xmmword ptr [rcx+0], xmm0 movapd xmmword ptr [rcx+16], xmm1 movapd xmmword ptr [rcx+32], xmm2 movapd xmmword ptr [rcx+48], xmm3 RandomX-1.1.10/src/asm/program_prologue_linux.inc000066400000000000000000000013571414227164600220230ustar00rootroot00000000000000 ;# callee-saved registers - System V AMD64 ABI push rbx push rbp push r12 push r13 push r14 push r15 ;# function arguments mov rbx, rcx ;# loop counter push rdi ;# RegisterFile& registerFile mov rcx, rdi mov rbp, qword ptr [rsi] ;# "mx", "ma" mov rdi, qword ptr [rsi+8] ;# uint8_t* dataset mov rsi, rdx ;# uint8_t* scratchpad mov rax, rbp ror rbp, 32 ;# zero integer registers xor r8, r8 xor r9, r9 xor r10, r10 xor r11, r11 xor r12, r12 xor r13, r13 xor r14, r14 xor r15, r15 ;# load constant registers lea rcx, [rcx+120] movapd xmm8, xmmword ptr [rcx+72] movapd xmm9, xmmword ptr [rcx+88] movapd xmm10, xmmword ptr [rcx+104] movapd xmm11, xmmword ptr [rcx+120] RandomX-1.1.10/src/asm/program_prologue_win64.inc000066400000000000000000000021771414227164600216340ustar00rootroot00000000000000 ;# callee-saved registers - Microsoft x64 calling convention push rbx push rbp push rdi push rsi push r12 push r13 push r14 push r15 sub rsp, 80 movdqu xmmword ptr [rsp+64], xmm6 movdqu xmmword ptr [rsp+48], xmm7 movdqu xmmword ptr [rsp+32], xmm8 movdqu xmmword ptr [rsp+16], xmm9 movdqu xmmword ptr [rsp+0], xmm10 sub rsp, 80 movdqu xmmword ptr [rsp+64], xmm11 movdqu xmmword ptr [rsp+48], xmm12 movdqu xmmword ptr [rsp+32], xmm13 movdqu xmmword ptr [rsp+16], xmm14 movdqu xmmword ptr [rsp+0], xmm15 ;# function arguments push rcx ;# RegisterFile& registerFile mov rbp, qword ptr [rdx] ;# "mx", "ma" mov rdi, qword ptr [rdx+8] ;# uint8_t* dataset mov rsi, r8 ;# uint8_t* scratchpad mov rbx, r9 ;# loop counter mov rax, rbp ror rbp, 32 ;# zero integer registers xor r8, r8 xor r9, r9 xor r10, r10 xor r11, r11 xor r12, r12 xor r13, r13 xor r14, r14 xor r15, r15 ;# load constant registers lea rcx, [rcx+120] movapd xmm8, xmmword ptr [rcx+72] movapd xmm9, xmmword ptr [rcx+88] movapd xmm10, xmmword ptr [rcx+104] movapd xmm11, xmmword ptr [rcx+120] RandomX-1.1.10/src/asm/program_read_dataset.inc000066400000000000000000000010711414227164600213610ustar00rootroot00000000000000 mov ecx, ebp ;# ecx = ma and ecx, RANDOMX_DATASET_BASE_MASK xor r8, qword ptr [rdi+rcx] ror rbp, 32 ;# swap "ma" and "mx" xor rbp, rax ;# modify "mx" mov edx, ebp ;# edx = mx and edx, RANDOMX_DATASET_BASE_MASK prefetchnta byte ptr [rdi+rdx] xor r9, qword ptr [rdi+rcx+8] xor r10, qword ptr [rdi+rcx+16] xor r11, qword ptr [rdi+rcx+24] xor r12, qword ptr [rdi+rcx+32] xor r13, qword ptr [rdi+rcx+40] xor r14, qword ptr [rdi+rcx+48] xor r15, qword ptr [rdi+rcx+56] RandomX-1.1.10/src/asm/program_read_dataset_sshash_fin.inc000066400000000000000000000004151414227164600235670ustar00rootroot00000000000000 mov rbx, qword ptr [rsp+64] xor r8, qword ptr [rsp+56] xor r9, qword ptr [rsp+48] xor r10, qword ptr [rsp+40] xor r11, qword ptr [rsp+32] xor r12, qword ptr [rsp+24] xor r13, qword ptr [rsp+16] xor r14, qword ptr [rsp+8] xor r15, qword ptr [rsp+0] add rsp, 72RandomX-1.1.10/src/asm/program_read_dataset_sshash_init.inc000066400000000000000000000010551414227164600237570ustar00rootroot00000000000000 sub rsp, 72 mov qword ptr [rsp+64], rbx mov qword ptr [rsp+56], r8 mov qword ptr [rsp+48], r9 mov qword ptr [rsp+40], r10 mov qword ptr [rsp+32], r11 mov qword ptr [rsp+24], r12 mov qword ptr [rsp+16], r13 mov qword ptr [rsp+8], r14 mov qword ptr [rsp+0], r15 ror rbp, 32 ;# swap "ma" and "mx" xor rbp, rax ;# modify "mx" mov rbx, rbp ;# ebx = ma shr rbx, 38 and ebx, RANDOMX_DATASET_BASE_MASK / 64 ;# ebx = Dataset block number ;# add ebx, datasetOffset / 64 ;# call 32768RandomX-1.1.10/src/asm/program_sshash_constants.inc000066400000000000000000000011051414227164600223240ustar00rootroot00000000000000r0_mul: ;#/ 6364136223846793005 db 45, 127, 149, 76, 45, 244, 81, 88 r1_add: ;#/ 9298411001130361340 db 252, 161, 245, 89, 138, 151, 10, 129 r2_add: ;#/ 12065312585734608966 db 70, 216, 194, 56, 223, 153, 112, 167 r3_add: ;#/ 9306329213124626780 db 92, 73, 34, 191, 28, 185, 38, 129 r4_add: ;#/ 5281919268842080866 db 98, 138, 159, 23, 151, 37, 77, 73 r5_add: ;#/ 10536153434571861004 db 12, 236, 170, 206, 185, 239, 55, 146 r6_add: ;#/ 3398623926847679864 db 120, 45, 230, 108, 116, 86, 42, 47 r7_add: ;#/ 9549104520008361294 db 78, 229, 44, 182, 247, 59, 133, 132RandomX-1.1.10/src/asm/program_sshash_load.inc000066400000000000000000000003431414227164600212320ustar00rootroot00000000000000 xor r8, qword ptr [rbx+0] xor r9, qword ptr [rbx+8] xor r10, qword ptr [rbx+16] xor r11, qword ptr [rbx+24] xor r12, qword ptr [rbx+32] xor r13, qword ptr [rbx+40] xor r14, qword ptr [rbx+48] xor r15, qword ptr [rbx+56]RandomX-1.1.10/src/asm/program_sshash_prefetch.inc000066400000000000000000000001221414227164600221060ustar00rootroot00000000000000 and rbx, RANDOMX_CACHE_MASK shl rbx, 6 add rbx, rdi prefetchnta byte ptr [rbx]RandomX-1.1.10/src/asm/program_xmm_constants.inc000066400000000000000000000003351414227164600216400ustar00rootroot00000000000000mantissaMask: db 255, 255, 255, 255, 255, 255, 255, 0, 255, 255, 255, 255, 255, 255, 255, 0 exp240: db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 scaleMask: db 0, 0, 0, 0, 0, 0, 240, 128, 0, 0, 0, 0, 0, 0, 240, 128RandomX-1.1.10/src/asm/randomx_reciprocal.inc000066400000000000000000000001161414227164600210640ustar00rootroot00000000000000 mov edx, 1 mov r8, rcx xor eax, eax bsr rcx, rcx shl rdx, cl div r8 retRandomX-1.1.10/src/assembly_generator_x86.cpp000066400000000000000000000561441414227164600210500ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "assembly_generator_x86.hpp" #include "common.hpp" #include "reciprocal.h" #include "program.hpp" #include "superscalar.hpp" namespace randomx { static const char* regR[] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" }; static const char* regR32[] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" }; static const char* regFE[] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" }; static const char* regF[] = { "xmm0", "xmm1", "xmm2", "xmm3" }; static const char* regE[] = { "xmm4", "xmm5", "xmm6", "xmm7" }; static const char* regA[] = { "xmm8", "xmm9", "xmm10", "xmm11" }; static const char* tempRegx = "xmm12"; static const char* mantissaMaskReg = "xmm13"; static const char* exponentMaskReg = "xmm14"; static const char* scaleMaskReg = "xmm15"; static const char* regIc = "rbx"; static const char* regIc32 = "ebx"; static const char* regIc8 = "bl"; static const char* regScratchpadAddr = "rsi"; void AssemblyGeneratorX86::generateProgram(Program& prog) { for (unsigned i = 0; i < RegistersCount; ++i) { registerUsage[i] = -1; } asmCode.str(std::string()); //clear for (unsigned i = 0; i < prog.getSize(); ++i) { asmCode << "randomx_isn_" << i << ":" << std::endl; Instruction& instr = prog(i); instr.src %= RegistersCount; instr.dst %= RegistersCount; generateCode(instr, i); } } void AssemblyGeneratorX86::generateAsm(SuperscalarProgram& prog) { asmCode.str(std::string()); //clear #ifdef RANDOMX_ALIGN asmCode << "ALIGN 16" << std::endl; #endif for (unsigned i = 0; i < prog.getSize(); ++i) { Instruction& instr = prog(i); switch ((SuperscalarInstructionType)instr.opcode) { case SuperscalarInstructionType::ISUB_R: asmCode << "sub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; break; case SuperscalarInstructionType::IXOR_R: asmCode << "xor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; break; case SuperscalarInstructionType::IADD_RS: asmCode << "lea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl; break; case SuperscalarInstructionType::IMUL_R: asmCode << "imul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; break; case SuperscalarInstructionType::IROR_C: asmCode << "ror " << regR[instr.dst] << ", " << instr.getImm32() << std::endl; break; case SuperscalarInstructionType::IADD_C7: asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; break; case SuperscalarInstructionType::IXOR_C7: asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; break; case SuperscalarInstructionType::IADD_C8: asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; #ifdef RANDOMX_ALIGN asmCode << "nop" << std::endl; #endif break; case SuperscalarInstructionType::IXOR_C8: asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; #ifdef RANDOMX_ALIGN asmCode << "nop" << std::endl; #endif break; case SuperscalarInstructionType::IADD_C9: asmCode << "add " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; #ifdef RANDOMX_ALIGN asmCode << "xchg ax, ax ;nop" << std::endl; #endif break; case SuperscalarInstructionType::IXOR_C9: asmCode << "xor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; #ifdef RANDOMX_ALIGN asmCode << "xchg ax, ax ;nop" << std::endl; #endif break; case SuperscalarInstructionType::IMULH_R: asmCode << "mov rax, " << regR[instr.dst] << std::endl; asmCode << "mul " << regR[instr.src] << std::endl; asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl; break; case SuperscalarInstructionType::ISMULH_R: asmCode << "mov rax, " << regR[instr.dst] << std::endl; asmCode << "imul " << regR[instr.src] << std::endl; asmCode << "mov " << regR[instr.dst] << ", rdx" << std::endl; break; case SuperscalarInstructionType::IMUL_RCP: asmCode << "mov rax, " << (int64_t)randomx_reciprocal(instr.getImm32()) << std::endl; asmCode << "imul " << regR[instr.dst] << ", rax" << std::endl; break; default: UNREACHABLE; } } } void AssemblyGeneratorX86::generateC(SuperscalarProgram& prog) { asmCode.str(std::string()); //clear asmCode << "#include " << std::endl; asmCode << "#if defined(__SIZEOF_INT128__)" << std::endl; asmCode << " static inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl; asmCode << " return ((unsigned __int128)a * b) >> 64;" << std::endl; asmCode << " }" << std::endl; asmCode << " static inline int64_t smulh(int64_t a, int64_t b) {" << std::endl; asmCode << " return ((__int128)a * b) >> 64;" << std::endl; asmCode << " }" << std::endl; asmCode << " #define HAVE_MULH" << std::endl; asmCode << " #define HAVE_SMULH" << std::endl; asmCode << "#endif" << std::endl; asmCode << "#if defined(_MSC_VER)" << std::endl; asmCode << " #define HAS_VALUE(X) X ## 0" << std::endl; asmCode << " #define EVAL_DEFINE(X) HAS_VALUE(X)" << std::endl; asmCode << " #include " << std::endl; asmCode << " #include " << std::endl; asmCode << " static __inline uint64_t rotr(uint64_t x , int c) {" << std::endl; asmCode << " return _rotr64(x, c);" << std::endl; asmCode << " }" << std::endl; asmCode << " #define HAVE_ROTR" << std::endl; asmCode << " #if EVAL_DEFINE(__MACHINEARM64_X64(1))" << std::endl; asmCode << " static __inline uint64_t mulh(uint64_t a, uint64_t b) {" << std::endl; asmCode << " return __umulh(a, b);" << std::endl; asmCode << " }" << std::endl; asmCode << " #define HAVE_MULH" << std::endl; asmCode << " #endif" << std::endl; asmCode << " #if EVAL_DEFINE(__MACHINEX64(1))" << std::endl; asmCode << " static __inline int64_t smulh(int64_t a, int64_t b) {" << std::endl; asmCode << " int64_t hi;" << std::endl; asmCode << " _mul128(a, b, &hi);" << std::endl; asmCode << " return hi;" << std::endl; asmCode << " }" << std::endl; asmCode << " #define HAVE_SMULH" << std::endl; asmCode << " #endif" << std::endl; asmCode << "#endif" << std::endl; asmCode << "#ifndef HAVE_ROTR" << std::endl; asmCode << " static inline uint64_t rotr(uint64_t a, int b) {" << std::endl; asmCode << " return (a >> b) | (a << (64 - b));" << std::endl; asmCode << " }" << std::endl; asmCode << " #define HAVE_ROTR" << std::endl; asmCode << "#endif" << std::endl; asmCode << "#if !defined(HAVE_MULH) || !defined(HAVE_SMULH) || !defined(HAVE_ROTR)" << std::endl; asmCode << " #error \"Required functions are not defined\"" << std::endl; asmCode << "#endif" << std::endl; asmCode << "void superScalar(uint64_t r[8]) {" << std::endl; asmCode << "uint64_t r8 = r[0], r9 = r[1], r10 = r[2], r11 = r[3], r12 = r[4], r13 = r[5], r14 = r[6], r15 = r[7];" << std::endl; for (unsigned i = 0; i < prog.getSize(); ++i) { Instruction& instr = prog(i); switch ((SuperscalarInstructionType)instr.opcode) { case SuperscalarInstructionType::ISUB_R: asmCode << regR[instr.dst] << " -= " << regR[instr.src] << ";" << std::endl; break; case SuperscalarInstructionType::IXOR_R: asmCode << regR[instr.dst] << " ^= " << regR[instr.src] << ";" << std::endl; break; case SuperscalarInstructionType::IADD_RS: asmCode << regR[instr.dst] << " += " << regR[instr.src] << "*" << (1 << (instr.getModShift())) << ";" << std::endl; break; case SuperscalarInstructionType::IMUL_R: asmCode << regR[instr.dst] << " *= " << regR[instr.src] << ";" << std::endl; break; case SuperscalarInstructionType::IROR_C: asmCode << regR[instr.dst] << " = rotr(" << regR[instr.dst] << ", " << instr.getImm32() << ");" << std::endl; break; case SuperscalarInstructionType::IADD_C7: case SuperscalarInstructionType::IADD_C8: case SuperscalarInstructionType::IADD_C9: asmCode << regR[instr.dst] << " += " << (int32_t)instr.getImm32() << ";" << std::endl; break; case SuperscalarInstructionType::IXOR_C7: case SuperscalarInstructionType::IXOR_C8: case SuperscalarInstructionType::IXOR_C9: asmCode << regR[instr.dst] << " ^= " << (int32_t)instr.getImm32() << ";" << std::endl; break; case SuperscalarInstructionType::IMULH_R: asmCode << regR[instr.dst] << " = mulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl; break; case SuperscalarInstructionType::ISMULH_R: asmCode << regR[instr.dst] << " = smulh(" << regR[instr.dst] << ", " << regR[instr.src] << ");" << std::endl; break; case SuperscalarInstructionType::IMUL_RCP: asmCode << regR[instr.dst] << " *= " << (int64_t)randomx_reciprocal(instr.getImm32()) << ";" << std::endl; break; default: UNREACHABLE; } } asmCode << "r[0] = r8; r[1] = r9; r[2] = r10; r[3] = r11; r[4] = r12; r[5] = r13; r[6] = r14; r[7] = r15;" << std::endl; asmCode << "}" << std::endl; } void AssemblyGeneratorX86::traceint(Instruction& instr) { if (trace) { asmCode << "\tpush " << regR[instr.dst] << std::endl; } } void AssemblyGeneratorX86::traceflt(Instruction& instr) { if (trace) { asmCode << "\tpush 0" << std::endl; } } void AssemblyGeneratorX86::tracenop(Instruction& instr) { if (trace) { asmCode << "\tpush 0" << std::endl; } } void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) { asmCode << "\t; " << instr; auto generator = engine[instr.opcode]; (this->*generator)(instr, i); } void AssemblyGeneratorX86::genAddressReg(Instruction& instr, const char* reg = "eax") { asmCode << "\tlea " << reg << ", [" << regR32[instr.src] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl; asmCode << "\tand " << reg << ", " << ((instr.getModMem()) ? ScratchpadL1Mask : ScratchpadL2Mask) << std::endl; } void AssemblyGeneratorX86::genAddressRegDst(Instruction& instr, int maskAlign = 8) { asmCode << "\tlea eax, [" << regR32[instr.dst] << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl; int mask; if (instr.getModCond() < StoreL3Condition) { mask = instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask; } else { mask = ScratchpadL3Mask; } asmCode << "\tand eax" << ", " << (mask & (-maskAlign)) << std::endl; } int32_t AssemblyGeneratorX86::genAddressImm(Instruction& instr) { return (int32_t)instr.getImm32() & ScratchpadL3Mask; } void AssemblyGeneratorX86::h_IADD_RS(Instruction& instr, int i) { registerUsage[instr.dst] = i; if(instr.dst == RegisterNeedsDisplacement) asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << std::showpos << (int32_t)instr.getImm32() << std::noshowpos << "]" << std::endl; else asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << "*" << (1 << (instr.getModShift())) << "]" << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_IADD_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; } else { asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_ISUB_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { asmCode << "\tsub " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; } else { asmCode << "\tsub " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_ISUB_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; } else { asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IMUL_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { asmCode << "\timul " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; } else { asmCode << "\timul " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IMUL_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; } else { asmCode << "\timul " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IMULH_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\tmul " << regR[instr.src] << std::endl; asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_IMULH_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr, "ecx"); asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl; } else { asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\tmul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_ISMULH_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\timul " << regR[instr.src] << std::endl; asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_ISMULH_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr, "ecx"); asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\timul qword ptr [" << regScratchpadAddr << "+rcx]" << std::endl; } else { asmCode << "\tmov rax, " << regR[instr.dst] << std::endl; asmCode << "\timul qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; asmCode << "\tneg " << regR[instr.dst] << std::endl; traceint(instr); } void AssemblyGeneratorX86::h_IXOR_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { asmCode << "\txor " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; } else { asmCode << "\txor " << regR[instr.dst] << ", " << (int32_t)instr.getImm32() << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IXOR_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; } else { asmCode << "\txor " << regR[instr.dst] << ", qword ptr [" << regScratchpadAddr << "+" << genAddressImm(instr) << "]" << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IROR_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl; asmCode << "\tror " << regR[instr.dst] << ", cl" << std::endl; } else { asmCode << "\tror " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IROL_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { asmCode << "\tmov ecx, " << regR32[instr.src] << std::endl; asmCode << "\trol " << regR[instr.dst] << ", cl" << std::endl; } else { asmCode << "\trol " << regR[instr.dst] << ", " << (instr.getImm32() & 63) << std::endl; } traceint(instr); } void AssemblyGeneratorX86::h_IMUL_RCP(Instruction& instr, int i) { uint64_t divisor = instr.getImm32(); if (!isZeroOrPowerOf2(divisor)) { registerUsage[instr.dst] = i; asmCode << "\tmov rax, " << randomx_reciprocal(divisor) << std::endl; asmCode << "\timul " << regR[instr.dst] << ", rax" << std::endl; traceint(instr); } else { tracenop(instr); } } void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) { if (instr.src != instr.dst) { registerUsage[instr.dst] = i; registerUsage[instr.src] = i; asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl; traceint(instr); } else { tracenop(instr); } } void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) { asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FADD_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FADD_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; asmCode << "\taddpd " << regF[instr.dst] << ", " << tempRegx << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FSUB_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FSUB_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; asmCode << "\tsubpd " << regF[instr.dst] << ", " << tempRegx << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; asmCode << "\txorps " << regF[instr.dst] << ", " << scaleMaskReg << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FMUL_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FDIV_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); asmCode << "\tcvtdq2pd " << tempRegx << ", qword ptr [" << regScratchpadAddr << "+rax]" << std::endl; asmCode << "\tandps " << tempRegx << ", " << mantissaMaskReg << std::endl; asmCode << "\torps " << tempRegx << ", " << exponentMaskReg << std::endl; asmCode << "\tdivpd " << regE[instr.dst] << ", " << tempRegx << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl; traceflt(instr); } void AssemblyGeneratorX86::h_CFROUND(Instruction& instr, int i) { asmCode << "\tmov rax, " << regR[instr.src] << std::endl; int rotate = (13 - (instr.getImm32() & 63)) & 63; if (rotate != 0) asmCode << "\trol rax, " << rotate << std::endl; asmCode << "\tand eax, 24576" << std::endl; asmCode << "\tor eax, 40896" << std::endl; asmCode << "\tpush rax" << std::endl; asmCode << "\tldmxcsr dword ptr [rsp]" << std::endl; asmCode << "\tpop rax" << std::endl; tracenop(instr); } void AssemblyGeneratorX86::h_CBRANCH(Instruction& instr, int i) { int reg = instr.dst; int target = registerUsage[reg] + 1; int shift = instr.getModCond() + ConditionOffset; int32_t imm = instr.getImm32() | (1L << shift); if (ConditionOffset > 0 || shift > 0) imm &= ~(1L << (shift - 1)); asmCode << "\tadd " << regR[reg] << ", " << imm << std::endl; asmCode << "\ttest " << regR[reg] << ", " << (ConditionMask << shift) << std::endl; asmCode << "\tjz randomx_isn_" << target << std::endl; //mark all registers as used for (unsigned j = 0; j < RegistersCount; ++j) { registerUsage[j] = i; } } void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) { genAddressRegDst(instr); asmCode << "\tmov qword ptr [" << regScratchpadAddr << "+rax], " << regR[instr.src] << std::endl; tracenop(instr); } void AssemblyGeneratorX86::h_NOP(Instruction& instr, int i) { asmCode << "\tnop" << std::endl; tracenop(instr); } #include "instruction_weights.hpp" #define INST_HANDLE(x) REPN(&AssemblyGeneratorX86::h_##x, WT(x)) InstructionGenerator AssemblyGeneratorX86::engine[256] = { INST_HANDLE(IADD_RS) INST_HANDLE(IADD_M) INST_HANDLE(ISUB_R) INST_HANDLE(ISUB_M) INST_HANDLE(IMUL_R) INST_HANDLE(IMUL_M) INST_HANDLE(IMULH_R) INST_HANDLE(IMULH_M) INST_HANDLE(ISMULH_R) INST_HANDLE(ISMULH_M) INST_HANDLE(IMUL_RCP) INST_HANDLE(INEG_R) INST_HANDLE(IXOR_R) INST_HANDLE(IXOR_M) INST_HANDLE(IROR_R) INST_HANDLE(IROL_R) INST_HANDLE(ISWAP_R) INST_HANDLE(FSWAP_R) INST_HANDLE(FADD_R) INST_HANDLE(FADD_M) INST_HANDLE(FSUB_R) INST_HANDLE(FSUB_M) INST_HANDLE(FSCAL_R) INST_HANDLE(FMUL_R) INST_HANDLE(FDIV_M) INST_HANDLE(FSQRT_R) INST_HANDLE(CBRANCH) INST_HANDLE(CFROUND) INST_HANDLE(ISTORE) INST_HANDLE(NOP) }; }RandomX-1.1.10/src/assembly_generator_x86.hpp000066400000000000000000000066421414227164600210530ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include "common.hpp" #include namespace randomx { class Program; class SuperscalarProgram; class AssemblyGeneratorX86; class Instruction; typedef void(AssemblyGeneratorX86::*InstructionGenerator)(Instruction&, int); class AssemblyGeneratorX86 { public: void generateProgram(Program& prog); void generateAsm(SuperscalarProgram& prog); void generateC(SuperscalarProgram& prog); void printCode(std::ostream& os) { os << asmCode.rdbuf(); } private: void genAddressReg(Instruction&, const char*); void genAddressRegDst(Instruction&, int); int32_t genAddressImm(Instruction&); void generateCode(Instruction&, int); void traceint(Instruction&); void traceflt(Instruction&); void tracenop(Instruction&); void h_IADD_RS(Instruction&, int); void h_IADD_M(Instruction&, int); void h_ISUB_R(Instruction&, int); void h_ISUB_M(Instruction&, int); void h_IMUL_R(Instruction&, int); void h_IMUL_M(Instruction&, int); void h_IMULH_R(Instruction&, int); void h_IMULH_M(Instruction&, int); void h_ISMULH_R(Instruction&, int); void h_ISMULH_M(Instruction&, int); void h_IMUL_RCP(Instruction&, int); void h_INEG_R(Instruction&, int); void h_IXOR_R(Instruction&, int); void h_IXOR_M(Instruction&, int); void h_IROR_R(Instruction&, int); void h_IROL_R(Instruction&, int); void h_ISWAP_R(Instruction&, int); void h_FSWAP_R(Instruction&, int); void h_FADD_R(Instruction&, int); void h_FADD_M(Instruction&, int); void h_FSUB_R(Instruction&, int); void h_FSUB_M(Instruction&, int); void h_FSCAL_R(Instruction&, int); void h_FMUL_R(Instruction&, int); void h_FDIV_M(Instruction&, int); void h_FSQRT_R(Instruction&, int); void h_CBRANCH(Instruction&, int); void h_CFROUND(Instruction&, int); void h_ISTORE(Instruction&, int); void h_NOP(Instruction&, int); static InstructionGenerator engine[256]; std::stringstream asmCode; int registerUsage[RegistersCount]; }; }RandomX-1.1.10/src/blake2/000077500000000000000000000000001414227164600151005ustar00rootroot00000000000000RandomX-1.1.10/src/blake2/blake2-impl.h000066400000000000000000000051061414227164600173520ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef PORTABLE_BLAKE2_IMPL_H #define PORTABLE_BLAKE2_IMPL_H #include #include "endian.h" static FORCE_INLINE uint64_t load48(const void *src) { const uint8_t *p = (const uint8_t *)src; uint64_t w = *p++; w |= (uint64_t)(*p++) << 8; w |= (uint64_t)(*p++) << 16; w |= (uint64_t)(*p++) << 24; w |= (uint64_t)(*p++) << 32; w |= (uint64_t)(*p++) << 40; return w; } static FORCE_INLINE void store48(void *dst, uint64_t w) { uint8_t *p = (uint8_t *)dst; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; } static FORCE_INLINE uint32_t rotr32(const uint32_t w, const unsigned c) { return (w >> c) | (w << (32 - c)); } static FORCE_INLINE uint64_t rotr64(const uint64_t w, const unsigned c) { return (w >> c) | (w << (64 - c)); } #endif RandomX-1.1.10/src/blake2/blake2.h000066400000000000000000000101341414227164600164100ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef PORTABLE_BLAKE2_H #define PORTABLE_BLAKE2_H #include #include #if defined(__cplusplus) extern "C" { #endif enum blake2b_constant { BLAKE2B_BLOCKBYTES = 128, BLAKE2B_OUTBYTES = 64, BLAKE2B_KEYBYTES = 64, BLAKE2B_SALTBYTES = 16, BLAKE2B_PERSONALBYTES = 16 }; #pragma pack(push, 1) typedef struct __blake2b_param { uint8_t digest_length; /* 1 */ uint8_t key_length; /* 2 */ uint8_t fanout; /* 3 */ uint8_t depth; /* 4 */ uint32_t leaf_length; /* 8 */ uint64_t node_offset; /* 16 */ uint8_t node_depth; /* 17 */ uint8_t inner_length; /* 18 */ uint8_t reserved[14]; /* 32 */ uint8_t salt[BLAKE2B_SALTBYTES]; /* 48 */ uint8_t personal[BLAKE2B_PERSONALBYTES]; /* 64 */ } blake2b_param; #pragma pack(pop) typedef struct __blake2b_state { uint64_t h[8]; uint64_t t[2]; uint64_t f[2]; uint8_t buf[BLAKE2B_BLOCKBYTES]; unsigned buflen; unsigned outlen; uint8_t last_node; } blake2b_state; /* Ensure param structs have not been wrongly padded */ /* Poor man's static_assert */ enum { blake2_size_check_0 = 1 / !!(CHAR_BIT == 8), blake2_size_check_2 = 1 / !!(sizeof(blake2b_param) == sizeof(uint64_t) * CHAR_BIT) }; //randomx namespace #define blake2b_init randomx_blake2b_init #define blake2b_init_key randomx_blake2b_init_key #define blake2b_init_param randomx_blake2b_init_param #define blake2b_update randomx_blake2b_update #define blake2b_final randomx_blake2b_final #define blake2b randomx_blake2b #define blake2b_long randomx_blake2b_long /* Streaming API */ int blake2b_init(blake2b_state *S, size_t outlen); int blake2b_init_key(blake2b_state *S, size_t outlen, const void *key, size_t keylen); int blake2b_init_param(blake2b_state *S, const blake2b_param *P); int blake2b_update(blake2b_state *S, const void *in, size_t inlen); int blake2b_final(blake2b_state *S, void *out, size_t outlen); /* Simple API */ int blake2b(void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen); /* Argon2 Team - Begin Code */ int blake2b_long(void *out, size_t outlen, const void *in, size_t inlen); /* Argon2 Team - End Code */ #if defined(__cplusplus) } #endif #endif RandomX-1.1.10/src/blake2/blake2b.c000066400000000000000000000303401414227164600165460ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #include #include #include #include "blake2.h" #include "blake2-impl.h" static const uint64_t blake2b_IV[8] = { UINT64_C(0x6a09e667f3bcc908), UINT64_C(0xbb67ae8584caa73b), UINT64_C(0x3c6ef372fe94f82b), UINT64_C(0xa54ff53a5f1d36f1), UINT64_C(0x510e527fade682d1), UINT64_C(0x9b05688c2b3e6c1f), UINT64_C(0x1f83d9abfb41bd6b), UINT64_C(0x5be0cd19137e2179) }; static const unsigned int blake2b_sigma[12][16] = { {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3}, {11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4}, {7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8}, {9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13}, {2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9}, {12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11}, {13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10}, {6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5}, {10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3}, }; static FORCE_INLINE void blake2b_set_lastnode(blake2b_state *S) { S->f[1] = (uint64_t)-1; } static FORCE_INLINE void blake2b_set_lastblock(blake2b_state *S) { if (S->last_node) { blake2b_set_lastnode(S); } S->f[0] = (uint64_t)-1; } static FORCE_INLINE void blake2b_increment_counter(blake2b_state *S, uint64_t inc) { S->t[0] += inc; S->t[1] += (S->t[0] < inc); } static FORCE_INLINE void blake2b_invalidate_state(blake2b_state *S) { //clear_internal_memory(S, sizeof(*S)); /* wipe */ blake2b_set_lastblock(S); /* invalidate for further use */ } static FORCE_INLINE void blake2b_init0(blake2b_state *S) { memset(S, 0, sizeof(*S)); memcpy(S->h, blake2b_IV, sizeof(S->h)); } int blake2b_init_param(blake2b_state *S, const blake2b_param *P) { const unsigned char *p = (const unsigned char *)P; unsigned int i; if (NULL == P || NULL == S) { return -1; } blake2b_init0(S); /* IV XOR Parameter Block */ for (i = 0; i < 8; ++i) { S->h[i] ^= load64(&p[i * sizeof(S->h[i])]); } S->outlen = P->digest_length; return 0; } /* Sequential blake2b initialization */ int blake2b_init(blake2b_state *S, size_t outlen) { blake2b_param P; if (S == NULL) { return -1; } if ((outlen == 0) || (outlen > BLAKE2B_OUTBYTES)) { blake2b_invalidate_state(S); return -1; } /* Setup Parameter Block for unkeyed BLAKE2 */ P.digest_length = (uint8_t)outlen; P.key_length = 0; P.fanout = 1; P.depth = 1; P.leaf_length = 0; P.node_offset = 0; P.node_depth = 0; P.inner_length = 0; memset(P.reserved, 0, sizeof(P.reserved)); memset(P.salt, 0, sizeof(P.salt)); memset(P.personal, 0, sizeof(P.personal)); return blake2b_init_param(S, &P); } int blake2b_init_key(blake2b_state *S, size_t outlen, const void *key, size_t keylen) { blake2b_param P; if (S == NULL) { return -1; } if ((outlen == 0) || (outlen > BLAKE2B_OUTBYTES)) { blake2b_invalidate_state(S); return -1; } if ((key == 0) || (keylen == 0) || (keylen > BLAKE2B_KEYBYTES)) { blake2b_invalidate_state(S); return -1; } /* Setup Parameter Block for keyed BLAKE2 */ P.digest_length = (uint8_t)outlen; P.key_length = (uint8_t)keylen; P.fanout = 1; P.depth = 1; P.leaf_length = 0; P.node_offset = 0; P.node_depth = 0; P.inner_length = 0; memset(P.reserved, 0, sizeof(P.reserved)); memset(P.salt, 0, sizeof(P.salt)); memset(P.personal, 0, sizeof(P.personal)); if (blake2b_init_param(S, &P) < 0) { blake2b_invalidate_state(S); return -1; } { uint8_t block[BLAKE2B_BLOCKBYTES]; memset(block, 0, BLAKE2B_BLOCKBYTES); memcpy(block, key, keylen); blake2b_update(S, block, BLAKE2B_BLOCKBYTES); /* Burn the key from stack */ //clear_internal_memory(block, BLAKE2B_BLOCKBYTES); } return 0; } static void blake2b_compress(blake2b_state *S, const uint8_t *block) { uint64_t m[16]; uint64_t v[16]; unsigned int i, r; for (i = 0; i < 16; ++i) { m[i] = load64(block + i * sizeof(m[i])); } for (i = 0; i < 8; ++i) { v[i] = S->h[i]; } v[8] = blake2b_IV[0]; v[9] = blake2b_IV[1]; v[10] = blake2b_IV[2]; v[11] = blake2b_IV[3]; v[12] = blake2b_IV[4] ^ S->t[0]; v[13] = blake2b_IV[5] ^ S->t[1]; v[14] = blake2b_IV[6] ^ S->f[0]; v[15] = blake2b_IV[7] ^ S->f[1]; #define G(r, i, a, b, c, d) \ do { \ a = a + b + m[blake2b_sigma[r][2 * i + 0]]; \ d = rotr64(d ^ a, 32); \ c = c + d; \ b = rotr64(b ^ c, 24); \ a = a + b + m[blake2b_sigma[r][2 * i + 1]]; \ d = rotr64(d ^ a, 16); \ c = c + d; \ b = rotr64(b ^ c, 63); \ } while ((void)0, 0) #define ROUND(r) \ do { \ G(r, 0, v[0], v[4], v[8], v[12]); \ G(r, 1, v[1], v[5], v[9], v[13]); \ G(r, 2, v[2], v[6], v[10], v[14]); \ G(r, 3, v[3], v[7], v[11], v[15]); \ G(r, 4, v[0], v[5], v[10], v[15]); \ G(r, 5, v[1], v[6], v[11], v[12]); \ G(r, 6, v[2], v[7], v[8], v[13]); \ G(r, 7, v[3], v[4], v[9], v[14]); \ } while ((void)0, 0) for (r = 0; r < 12; ++r) { ROUND(r); } for (i = 0; i < 8; ++i) { S->h[i] = S->h[i] ^ v[i] ^ v[i + 8]; } #undef G #undef ROUND } int blake2b_update(blake2b_state *S, const void *in, size_t inlen) { const uint8_t *pin = (const uint8_t *)in; if (inlen == 0) { return 0; } /* Sanity check */ if (S == NULL || in == NULL) { return -1; } /* Is this a reused state? */ if (S->f[0] != 0) { return -1; } if (S->buflen + inlen > BLAKE2B_BLOCKBYTES) { /* Complete current block */ size_t left = S->buflen; size_t fill = BLAKE2B_BLOCKBYTES - left; memcpy(&S->buf[left], pin, fill); blake2b_increment_counter(S, BLAKE2B_BLOCKBYTES); blake2b_compress(S, S->buf); S->buflen = 0; inlen -= fill; pin += fill; /* Avoid buffer copies when possible */ while (inlen > BLAKE2B_BLOCKBYTES) { blake2b_increment_counter(S, BLAKE2B_BLOCKBYTES); blake2b_compress(S, pin); inlen -= BLAKE2B_BLOCKBYTES; pin += BLAKE2B_BLOCKBYTES; } } memcpy(&S->buf[S->buflen], pin, inlen); S->buflen += (unsigned int)inlen; return 0; } int blake2b_final(blake2b_state *S, void *out, size_t outlen) { uint8_t buffer[BLAKE2B_OUTBYTES] = { 0 }; unsigned int i; /* Sanity checks */ if (S == NULL || out == NULL || outlen < S->outlen) { return -1; } /* Is this a reused state? */ if (S->f[0] != 0) { return -1; } blake2b_increment_counter(S, S->buflen); blake2b_set_lastblock(S); memset(&S->buf[S->buflen], 0, BLAKE2B_BLOCKBYTES - S->buflen); /* Padding */ blake2b_compress(S, S->buf); for (i = 0; i < 8; ++i) { /* Output full hash to temp buffer */ store64(buffer + sizeof(S->h[i]) * i, S->h[i]); } memcpy(out, buffer, S->outlen); //clear_internal_memory(buffer, sizeof(buffer)); //clear_internal_memory(S->buf, sizeof(S->buf)); //clear_internal_memory(S->h, sizeof(S->h)); return 0; } int blake2b(void *out, size_t outlen, const void *in, size_t inlen, const void *key, size_t keylen) { blake2b_state S; int ret = -1; /* Verify parameters */ if (NULL == in && inlen > 0) { goto fail; } if (NULL == out || outlen == 0 || outlen > BLAKE2B_OUTBYTES) { goto fail; } if ((NULL == key && keylen > 0) || keylen > BLAKE2B_KEYBYTES) { goto fail; } if (keylen > 0) { if (blake2b_init_key(&S, outlen, key, keylen) < 0) { goto fail; } } else { if (blake2b_init(&S, outlen) < 0) { goto fail; } } if (blake2b_update(&S, in, inlen) < 0) { goto fail; } ret = blake2b_final(&S, out, outlen); fail: //clear_internal_memory(&S, sizeof(S)); return ret; } /* Argon2 Team - Begin Code */ int blake2b_long(void *pout, size_t outlen, const void *in, size_t inlen) { uint8_t *out = (uint8_t *)pout; blake2b_state blake_state; uint8_t outlen_bytes[sizeof(uint32_t)] = { 0 }; int ret = -1; if (outlen > UINT32_MAX) { goto fail; } /* Ensure little-endian byte order! */ store32(outlen_bytes, (uint32_t)outlen); #define TRY(statement) \ do { \ ret = statement; \ if (ret < 0) { \ goto fail; \ } \ } while ((void)0, 0) if (outlen <= BLAKE2B_OUTBYTES) { TRY(blake2b_init(&blake_state, outlen)); TRY(blake2b_update(&blake_state, outlen_bytes, sizeof(outlen_bytes))); TRY(blake2b_update(&blake_state, in, inlen)); TRY(blake2b_final(&blake_state, out, outlen)); } else { uint32_t toproduce; uint8_t out_buffer[BLAKE2B_OUTBYTES]; uint8_t in_buffer[BLAKE2B_OUTBYTES]; TRY(blake2b_init(&blake_state, BLAKE2B_OUTBYTES)); TRY(blake2b_update(&blake_state, outlen_bytes, sizeof(outlen_bytes))); TRY(blake2b_update(&blake_state, in, inlen)); TRY(blake2b_final(&blake_state, out_buffer, BLAKE2B_OUTBYTES)); memcpy(out, out_buffer, BLAKE2B_OUTBYTES / 2); out += BLAKE2B_OUTBYTES / 2; toproduce = (uint32_t)outlen - BLAKE2B_OUTBYTES / 2; while (toproduce > BLAKE2B_OUTBYTES) { memcpy(in_buffer, out_buffer, BLAKE2B_OUTBYTES); TRY(blake2b(out_buffer, BLAKE2B_OUTBYTES, in_buffer, BLAKE2B_OUTBYTES, NULL, 0)); memcpy(out, out_buffer, BLAKE2B_OUTBYTES / 2); out += BLAKE2B_OUTBYTES / 2; toproduce -= BLAKE2B_OUTBYTES / 2; } memcpy(in_buffer, out_buffer, BLAKE2B_OUTBYTES); TRY(blake2b(out_buffer, toproduce, in_buffer, BLAKE2B_OUTBYTES, NULL, 0)); memcpy(out, out_buffer, toproduce); } fail: //clear_internal_memory(&blake_state, sizeof(blake_state)); return ret; #undef TRY } /* Argon2 Team - End Code */ RandomX-1.1.10/src/blake2/blamka-round-avx2.h000066400000000000000000000167741414227164600205220ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef BLAKE_ROUND_MKA_OPT_H #define BLAKE_ROUND_MKA_OPT_H #include "blake2-impl.h" #ifdef __GNUC__ #include #else #include #endif #define rotr32(x) _mm256_shuffle_epi32(x, _MM_SHUFFLE(2, 3, 0, 1)) #define rotr24(x) _mm256_shuffle_epi8(x, _mm256_setr_epi8(3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10, 3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10)) #define rotr16(x) _mm256_shuffle_epi8(x, _mm256_setr_epi8(2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9, 2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9)) #define rotr63(x) _mm256_xor_si256(_mm256_srli_epi64((x), 63), _mm256_add_epi64((x), (x))) #define G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ do { \ __m256i ml = _mm256_mul_epu32(A0, B0); \ ml = _mm256_add_epi64(ml, ml); \ A0 = _mm256_add_epi64(A0, _mm256_add_epi64(B0, ml)); \ D0 = _mm256_xor_si256(D0, A0); \ D0 = rotr32(D0); \ \ ml = _mm256_mul_epu32(C0, D0); \ ml = _mm256_add_epi64(ml, ml); \ C0 = _mm256_add_epi64(C0, _mm256_add_epi64(D0, ml)); \ \ B0 = _mm256_xor_si256(B0, C0); \ B0 = rotr24(B0); \ \ ml = _mm256_mul_epu32(A1, B1); \ ml = _mm256_add_epi64(ml, ml); \ A1 = _mm256_add_epi64(A1, _mm256_add_epi64(B1, ml)); \ D1 = _mm256_xor_si256(D1, A1); \ D1 = rotr32(D1); \ \ ml = _mm256_mul_epu32(C1, D1); \ ml = _mm256_add_epi64(ml, ml); \ C1 = _mm256_add_epi64(C1, _mm256_add_epi64(D1, ml)); \ \ B1 = _mm256_xor_si256(B1, C1); \ B1 = rotr24(B1); \ } while((void)0, 0); #define G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ do { \ __m256i ml = _mm256_mul_epu32(A0, B0); \ ml = _mm256_add_epi64(ml, ml); \ A0 = _mm256_add_epi64(A0, _mm256_add_epi64(B0, ml)); \ D0 = _mm256_xor_si256(D0, A0); \ D0 = rotr16(D0); \ \ ml = _mm256_mul_epu32(C0, D0); \ ml = _mm256_add_epi64(ml, ml); \ C0 = _mm256_add_epi64(C0, _mm256_add_epi64(D0, ml)); \ B0 = _mm256_xor_si256(B0, C0); \ B0 = rotr63(B0); \ \ ml = _mm256_mul_epu32(A1, B1); \ ml = _mm256_add_epi64(ml, ml); \ A1 = _mm256_add_epi64(A1, _mm256_add_epi64(B1, ml)); \ D1 = _mm256_xor_si256(D1, A1); \ D1 = rotr16(D1); \ \ ml = _mm256_mul_epu32(C1, D1); \ ml = _mm256_add_epi64(ml, ml); \ C1 = _mm256_add_epi64(C1, _mm256_add_epi64(D1, ml)); \ B1 = _mm256_xor_si256(B1, C1); \ B1 = rotr63(B1); \ } while((void)0, 0); #define DIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(0, 3, 2, 1)); \ C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(2, 1, 0, 3)); \ \ B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(0, 3, 2, 1)); \ C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(2, 1, 0, 3)); \ } while((void)0, 0); #define DIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ do { \ __m256i tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \ __m256i tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \ B1 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ B0 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ \ tmp1 = C0; \ C0 = C1; \ C1 = tmp1; \ \ tmp1 = _mm256_blend_epi32(D0, D1, 0xCC); \ tmp2 = _mm256_blend_epi32(D0, D1, 0x33); \ D0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ D1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ } while(0); #define UNDIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(2, 1, 0, 3)); \ C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(0, 3, 2, 1)); \ \ B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(2, 1, 0, 3)); \ C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(0, 3, 2, 1)); \ } while((void)0, 0); #define UNDIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ do { \ __m256i tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \ __m256i tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \ B0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ B1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ \ tmp1 = C0; \ C0 = C1; \ C1 = tmp1; \ \ tmp1 = _mm256_blend_epi32(D0, D1, 0x33); \ tmp2 = _mm256_blend_epi32(D0, D1, 0xCC); \ D0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ D1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ } while((void)0, 0); #define BLAKE2_ROUND_1(A0, A1, B0, B1, C0, C1, D0, D1) \ do{ \ G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ \ DIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ \ G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ \ UNDIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ } while((void)0, 0); #define BLAKE2_ROUND_2(A0, A1, B0, B1, C0, C1, D0, D1) \ do{ \ G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ \ DIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ \ G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ \ UNDIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ } while((void)0, 0); #endif /* BLAKE_ROUND_MKA_OPT_H */ RandomX-1.1.10/src/blake2/blamka-round-ref.h000066400000000000000000000073531414227164600204070ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef BLAKE_ROUND_MKA_H #define BLAKE_ROUND_MKA_H #include "blake2.h" #include "blake2-impl.h" /* designed by the Lyra PHC team */ static FORCE_INLINE uint64_t fBlaMka(uint64_t x, uint64_t y) { const uint64_t m = UINT64_C(0xFFFFFFFF); const uint64_t xy = (x & m) * (y & m); return x + y + 2 * xy; } #define G(a, b, c, d) \ do { \ a = fBlaMka(a, b); \ d = rotr64(d ^ a, 32); \ c = fBlaMka(c, d); \ b = rotr64(b ^ c, 24); \ a = fBlaMka(a, b); \ d = rotr64(d ^ a, 16); \ c = fBlaMka(c, d); \ b = rotr64(b ^ c, 63); \ } while ((void)0, 0) #define BLAKE2_ROUND_NOMSG(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, \ v12, v13, v14, v15) \ do { \ G(v0, v4, v8, v12); \ G(v1, v5, v9, v13); \ G(v2, v6, v10, v14); \ G(v3, v7, v11, v15); \ G(v0, v5, v10, v15); \ G(v1, v6, v11, v12); \ G(v2, v7, v8, v13); \ G(v3, v4, v9, v14); \ } while ((void)0, 0) #endif RandomX-1.1.10/src/blake2/blamka-round-ssse3.h000066400000000000000000000234551414227164600206740ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #ifndef BLAKE_ROUND_MKA_OPT_H #define BLAKE_ROUND_MKA_OPT_H #include "blake2-impl.h" #ifdef __GNUC__ #include #else #include #endif #ifdef _mm_roti_epi64 //clang defines it using the XOP instruction set #undef _mm_roti_epi64 #endif #define r16 \ (_mm_setr_epi8(2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9)) #define r24 \ (_mm_setr_epi8(3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10)) #define _mm_roti_epi64(x, c) \ (-(c) == 32) \ ? _mm_shuffle_epi32((x), _MM_SHUFFLE(2, 3, 0, 1)) \ : (-(c) == 24) \ ? _mm_shuffle_epi8((x), r24) \ : (-(c) == 16) \ ? _mm_shuffle_epi8((x), r16) \ : (-(c) == 63) \ ? _mm_xor_si128(_mm_srli_epi64((x), -(c)), \ _mm_add_epi64((x), (x))) \ : _mm_xor_si128(_mm_srli_epi64((x), -(c)), \ _mm_slli_epi64((x), 64 - (-(c)))) static FORCE_INLINE __m128i fBlaMka(__m128i x, __m128i y) { const __m128i z = _mm_mul_epu32(x, y); return _mm_add_epi64(_mm_add_epi64(x, y), _mm_add_epi64(z, z)); } #define G1(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ A0 = fBlaMka(A0, B0); \ A1 = fBlaMka(A1, B1); \ \ D0 = _mm_xor_si128(D0, A0); \ D1 = _mm_xor_si128(D1, A1); \ \ D0 = _mm_roti_epi64(D0, -32); \ D1 = _mm_roti_epi64(D1, -32); \ \ C0 = fBlaMka(C0, D0); \ C1 = fBlaMka(C1, D1); \ \ B0 = _mm_xor_si128(B0, C0); \ B1 = _mm_xor_si128(B1, C1); \ \ B0 = _mm_roti_epi64(B0, -24); \ B1 = _mm_roti_epi64(B1, -24); \ } while ((void)0, 0) #define G2(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ A0 = fBlaMka(A0, B0); \ A1 = fBlaMka(A1, B1); \ \ D0 = _mm_xor_si128(D0, A0); \ D1 = _mm_xor_si128(D1, A1); \ \ D0 = _mm_roti_epi64(D0, -16); \ D1 = _mm_roti_epi64(D1, -16); \ \ C0 = fBlaMka(C0, D0); \ C1 = fBlaMka(C1, D1); \ \ B0 = _mm_xor_si128(B0, C0); \ B1 = _mm_xor_si128(B1, C1); \ \ B0 = _mm_roti_epi64(B0, -63); \ B1 = _mm_roti_epi64(B1, -63); \ } while ((void)0, 0) #define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ __m128i t0 = _mm_alignr_epi8(B1, B0, 8); \ __m128i t1 = _mm_alignr_epi8(B0, B1, 8); \ B0 = t0; \ B1 = t1; \ \ t0 = C0; \ C0 = C1; \ C1 = t0; \ \ t0 = _mm_alignr_epi8(D1, D0, 8); \ t1 = _mm_alignr_epi8(D0, D1, 8); \ D0 = t1; \ D1 = t0; \ } while ((void)0, 0) #define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ do { \ __m128i t0 = _mm_alignr_epi8(B0, B1, 8); \ __m128i t1 = _mm_alignr_epi8(B1, B0, 8); \ B0 = t0; \ B1 = t1; \ \ t0 = C0; \ C0 = C1; \ C1 = t0; \ \ t0 = _mm_alignr_epi8(D0, D1, 8); \ t1 = _mm_alignr_epi8(D1, D0, 8); \ D0 = t1; \ D1 = t0; \ } while ((void)0, 0) #define BLAKE2_ROUND(A0, A1, B0, B1, C0, C1, D0, D1) \ do { \ G1(A0, B0, C0, D0, A1, B1, C1, D1); \ G2(A0, B0, C0, D0, A1, B1, C1, D1); \ \ DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ \ G1(A0, B0, C0, D0, A1, B1, C1, D1); \ G2(A0, B0, C0, D0, A1, B1, C1, D1); \ \ UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ } while ((void)0, 0) #endif /* BLAKE_ROUND_MKA_OPT_H */ RandomX-1.1.10/src/blake2/endian.h000066400000000000000000000047351414227164600165200ustar00rootroot00000000000000#pragma once #include #include #if defined(_MSC_VER) #define FORCE_INLINE __inline #elif defined(__GNUC__) || defined(__clang__) #define FORCE_INLINE __inline__ #else #define FORCE_INLINE #endif /* Argon2 Team - Begin Code */ /* Not an exhaustive list, but should cover the majority of modern platforms Additionally, the code will always be correct---this is only a performance tweak. */ #if (defined(__BYTE_ORDER__) && \ (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) || \ defined(__LITTLE_ENDIAN__) || defined(__ARMEL__) || defined(__MIPSEL__) || \ defined(__AARCH64EL__) || defined(__amd64__) || defined(__i386__) || \ defined(_M_IX86) || defined(_M_X64) || defined(_M_AMD64) || \ defined(_M_ARM) #define NATIVE_LITTLE_ENDIAN #endif /* Argon2 Team - End Code */ static FORCE_INLINE uint32_t load32(const void *src) { #if defined(NATIVE_LITTLE_ENDIAN) uint32_t w; memcpy(&w, src, sizeof w); return w; #else const uint8_t *p = (const uint8_t *)src; uint32_t w = *p++; w |= (uint32_t)(*p++) << 8; w |= (uint32_t)(*p++) << 16; w |= (uint32_t)(*p++) << 24; return w; #endif } static FORCE_INLINE uint64_t load64_native(const void *src) { uint64_t w; memcpy(&w, src, sizeof w); return w; } static FORCE_INLINE uint64_t load64(const void *src) { #if defined(NATIVE_LITTLE_ENDIAN) return load64_native(src); #else const uint8_t *p = (const uint8_t *)src; uint64_t w = *p++; w |= (uint64_t)(*p++) << 8; w |= (uint64_t)(*p++) << 16; w |= (uint64_t)(*p++) << 24; w |= (uint64_t)(*p++) << 32; w |= (uint64_t)(*p++) << 40; w |= (uint64_t)(*p++) << 48; w |= (uint64_t)(*p++) << 56; return w; #endif } static FORCE_INLINE void store32(void *dst, uint32_t w) { #if defined(NATIVE_LITTLE_ENDIAN) memcpy(dst, &w, sizeof w); #else uint8_t *p = (uint8_t *)dst; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; #endif } static FORCE_INLINE void store64_native(void *dst, uint64_t w) { memcpy(dst, &w, sizeof w); } static FORCE_INLINE void store64(void *dst, uint64_t w) { #if defined(NATIVE_LITTLE_ENDIAN) store64_native(dst, w); #else uint8_t *p = (uint8_t *)dst; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; w >>= 8; *p++ = (uint8_t)w; #endif } RandomX-1.1.10/src/blake2_generator.cpp000066400000000000000000000044641414227164600176620ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "blake2/blake2.h" #include "blake2/endian.h" #include "blake2_generator.hpp" namespace randomx { constexpr int maxSeedSize = 60; Blake2Generator::Blake2Generator(const void* seed, size_t seedSize, int nonce) : dataIndex(sizeof(data)) { memset(data, 0, sizeof(data)); memcpy(data, seed, seedSize > maxSeedSize ? maxSeedSize : seedSize); store32(&data[maxSeedSize], nonce); } uint8_t Blake2Generator::getByte() { checkData(1); return data[dataIndex++]; } uint32_t Blake2Generator::getUInt32() { checkData(4); auto ret = load32(&data[dataIndex]); dataIndex += 4; return ret; } void Blake2Generator::checkData(const size_t bytesNeeded) { if (dataIndex + bytesNeeded > sizeof(data)) { blake2b(data, sizeof(data), data, sizeof(data), nullptr, 0); dataIndex = 0; } } }RandomX-1.1.10/src/blake2_generator.hpp000066400000000000000000000034261414227164600176640ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include namespace randomx { class Blake2Generator { public: Blake2Generator(const void* seed, size_t seedSize, int nonce = 0); uint8_t getByte(); uint32_t getUInt32(); private: void checkData(const size_t); uint8_t data[64]; size_t dataIndex; }; }RandomX-1.1.10/src/bytecode_machine.cpp000066400000000000000000000314111414227164600177260ustar00rootroot00000000000000/* Copyright (c) 2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "bytecode_machine.hpp" #include "reciprocal.h" namespace randomx { const int_reg_t BytecodeMachine::zero = 0; #define INSTR_CASE(x) case InstructionType::x: \ exe_ ## x(ibc, pc, scratchpad, config); \ break; void BytecodeMachine::executeInstruction(RANDOMX_EXE_ARGS) { switch (ibc.type) { INSTR_CASE(IADD_RS) INSTR_CASE(IADD_M) INSTR_CASE(ISUB_R) INSTR_CASE(ISUB_M) INSTR_CASE(IMUL_R) INSTR_CASE(IMUL_M) INSTR_CASE(IMULH_R) INSTR_CASE(IMULH_M) INSTR_CASE(ISMULH_R) INSTR_CASE(ISMULH_M) INSTR_CASE(INEG_R) INSTR_CASE(IXOR_R) INSTR_CASE(IXOR_M) INSTR_CASE(IROR_R) INSTR_CASE(IROL_R) INSTR_CASE(ISWAP_R) INSTR_CASE(FSWAP_R) INSTR_CASE(FADD_R) INSTR_CASE(FADD_M) INSTR_CASE(FSUB_R) INSTR_CASE(FSUB_M) INSTR_CASE(FSCAL_R) INSTR_CASE(FMUL_R) INSTR_CASE(FDIV_M) INSTR_CASE(FSQRT_R) INSTR_CASE(CBRANCH) INSTR_CASE(CFROUND) INSTR_CASE(ISTORE) case InstructionType::NOP: break; case InstructionType::IMUL_RCP: //executed as IMUL_R default: UNREACHABLE; } } void BytecodeMachine::compileInstruction(RANDOMX_GEN_ARGS) { int opcode = instr.opcode; if (opcode < ceil_IADD_RS) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IADD_RS; ibc.idst = &nreg->r[dst]; if (dst != RegisterNeedsDisplacement) { ibc.isrc = &nreg->r[src]; ibc.shift = instr.getModShift(); ibc.imm = 0; } else { ibc.isrc = &nreg->r[src]; ibc.shift = instr.getModShift(); ibc.imm = signExtend2sCompl(instr.getImm32()); } registerUsage[dst] = i; return; } if (opcode < ceil_IADD_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IADD_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_ISUB_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::ISUB_R; ibc.idst = &nreg->r[dst]; if (src != dst) { ibc.isrc = &nreg->r[src]; } else { ibc.imm = signExtend2sCompl(instr.getImm32()); ibc.isrc = &ibc.imm; } registerUsage[dst] = i; return; } if (opcode < ceil_ISUB_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::ISUB_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_IMUL_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IMUL_R; ibc.idst = &nreg->r[dst]; if (src != dst) { ibc.isrc = &nreg->r[src]; } else { ibc.imm = signExtend2sCompl(instr.getImm32()); ibc.isrc = &ibc.imm; } registerUsage[dst] = i; return; } if (opcode < ceil_IMUL_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IMUL_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_IMULH_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IMULH_R; ibc.idst = &nreg->r[dst]; ibc.isrc = &nreg->r[src]; registerUsage[dst] = i; return; } if (opcode < ceil_IMULH_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IMULH_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_ISMULH_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::ISMULH_R; ibc.idst = &nreg->r[dst]; ibc.isrc = &nreg->r[src]; registerUsage[dst] = i; return; } if (opcode < ceil_ISMULH_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::ISMULH_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_IMUL_RCP) { uint64_t divisor = instr.getImm32(); if (!isZeroOrPowerOf2(divisor)) { auto dst = instr.dst % RegistersCount; ibc.type = InstructionType::IMUL_R; ibc.idst = &nreg->r[dst]; ibc.imm = randomx_reciprocal(divisor); ibc.isrc = &ibc.imm; registerUsage[dst] = i; } else { ibc.type = InstructionType::NOP; } return; } if (opcode < ceil_INEG_R) { auto dst = instr.dst % RegistersCount; ibc.type = InstructionType::INEG_R; ibc.idst = &nreg->r[dst]; registerUsage[dst] = i; return; } if (opcode < ceil_IXOR_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IXOR_R; ibc.idst = &nreg->r[dst]; if (src != dst) { ibc.isrc = &nreg->r[src]; } else { ibc.imm = signExtend2sCompl(instr.getImm32()); ibc.isrc = &ibc.imm; } registerUsage[dst] = i; return; } if (opcode < ceil_IXOR_M) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IXOR_M; ibc.idst = &nreg->r[dst]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (src != dst) { ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { ibc.isrc = &zero; ibc.memMask = ScratchpadL3Mask; } registerUsage[dst] = i; return; } if (opcode < ceil_IROR_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IROR_R; ibc.idst = &nreg->r[dst]; if (src != dst) { ibc.isrc = &nreg->r[src]; } else { ibc.imm = instr.getImm32(); ibc.isrc = &ibc.imm; } registerUsage[dst] = i; return; } if (opcode < ceil_IROL_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::IROL_R; ibc.idst = &nreg->r[dst]; if (src != dst) { ibc.isrc = &nreg->r[src]; } else { ibc.imm = instr.getImm32(); ibc.isrc = &ibc.imm; } registerUsage[dst] = i; return; } if (opcode < ceil_ISWAP_R) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; if (src != dst) { ibc.idst = &nreg->r[dst]; ibc.isrc = &nreg->r[src]; ibc.type = InstructionType::ISWAP_R; registerUsage[dst] = i; registerUsage[src] = i; } else { ibc.type = InstructionType::NOP; } return; } if (opcode < ceil_FSWAP_R) { auto dst = instr.dst % RegistersCount; ibc.type = InstructionType::FSWAP_R; if (dst < RegisterCountFlt) ibc.fdst = &nreg->f[dst]; else ibc.fdst = &nreg->e[dst - RegisterCountFlt]; return; } if (opcode < ceil_FADD_R) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegisterCountFlt; ibc.type = InstructionType::FADD_R; ibc.fdst = &nreg->f[dst]; ibc.fsrc = &nreg->a[src]; return; } if (opcode < ceil_FADD_M) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegistersCount; ibc.type = InstructionType::FADD_M; ibc.fdst = &nreg->f[dst]; ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); ibc.imm = signExtend2sCompl(instr.getImm32()); return; } if (opcode < ceil_FSUB_R) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegisterCountFlt; ibc.type = InstructionType::FSUB_R; ibc.fdst = &nreg->f[dst]; ibc.fsrc = &nreg->a[src]; return; } if (opcode < ceil_FSUB_M) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegistersCount; ibc.type = InstructionType::FSUB_M; ibc.fdst = &nreg->f[dst]; ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); ibc.imm = signExtend2sCompl(instr.getImm32()); return; } if (opcode < ceil_FSCAL_R) { auto dst = instr.dst % RegisterCountFlt; ibc.fdst = &nreg->f[dst]; ibc.type = InstructionType::FSCAL_R; return; } if (opcode < ceil_FMUL_R) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegisterCountFlt; ibc.type = InstructionType::FMUL_R; ibc.fdst = &nreg->e[dst]; ibc.fsrc = &nreg->a[src]; return; } if (opcode < ceil_FDIV_M) { auto dst = instr.dst % RegisterCountFlt; auto src = instr.src % RegistersCount; ibc.type = InstructionType::FDIV_M; ibc.fdst = &nreg->e[dst]; ibc.isrc = &nreg->r[src]; ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); ibc.imm = signExtend2sCompl(instr.getImm32()); return; } if (opcode < ceil_FSQRT_R) { auto dst = instr.dst % RegisterCountFlt; ibc.type = InstructionType::FSQRT_R; ibc.fdst = &nreg->e[dst]; return; } if (opcode < ceil_CBRANCH) { ibc.type = InstructionType::CBRANCH; //jump condition int creg = instr.dst % RegistersCount; ibc.idst = &nreg->r[creg]; ibc.target = registerUsage[creg]; int shift = instr.getModCond() + ConditionOffset; ibc.imm = signExtend2sCompl(instr.getImm32()) | (1ULL << shift); if (ConditionOffset > 0 || shift > 0) //clear the bit below the condition mask - this limits the number of successive jumps to 2 ibc.imm &= ~(1ULL << (shift - 1)); ibc.memMask = ConditionMask << shift; //mark all registers as used for (unsigned j = 0; j < RegistersCount; ++j) { registerUsage[j] = i; } return; } if (opcode < ceil_CFROUND) { auto src = instr.src % RegistersCount; ibc.isrc = &nreg->r[src]; ibc.type = InstructionType::CFROUND; ibc.imm = instr.getImm32() & 63; return; } if (opcode < ceil_ISTORE) { auto dst = instr.dst % RegistersCount; auto src = instr.src % RegistersCount; ibc.type = InstructionType::ISTORE; ibc.idst = &nreg->r[dst]; ibc.isrc = &nreg->r[src]; ibc.imm = signExtend2sCompl(instr.getImm32()); if (instr.getModCond() < StoreL3Condition) ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); else ibc.memMask = ScratchpadL3Mask; return; } if (opcode < ceil_NOP) { ibc.type = InstructionType::NOP; return; } UNREACHABLE; } } RandomX-1.1.10/src/bytecode_machine.hpp000066400000000000000000000236571414227164600177500ustar00rootroot00000000000000/* Copyright (c) 2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include "common.hpp" #include "intrin_portable.h" #include "instruction.hpp" #include "program.hpp" namespace randomx { //register file in machine byte order struct NativeRegisterFile { int_reg_t r[RegistersCount] = { 0 }; rx_vec_f128 f[RegisterCountFlt]; rx_vec_f128 e[RegisterCountFlt]; rx_vec_f128 a[RegisterCountFlt]; }; struct InstructionByteCode { union { int_reg_t* idst; rx_vec_f128* fdst; }; union { const int_reg_t* isrc; const rx_vec_f128* fsrc; }; union { uint64_t imm; int64_t simm; }; InstructionType type; union { int16_t target; uint16_t shift; }; uint32_t memMask; }; #define OPCODE_CEIL_DECLARE(curr, prev) constexpr int ceil_ ## curr = ceil_ ## prev + RANDOMX_FREQ_ ## curr; constexpr int ceil_NULL = 0; OPCODE_CEIL_DECLARE(IADD_RS, NULL); OPCODE_CEIL_DECLARE(IADD_M, IADD_RS); OPCODE_CEIL_DECLARE(ISUB_R, IADD_M); OPCODE_CEIL_DECLARE(ISUB_M, ISUB_R); OPCODE_CEIL_DECLARE(IMUL_R, ISUB_M); OPCODE_CEIL_DECLARE(IMUL_M, IMUL_R); OPCODE_CEIL_DECLARE(IMULH_R, IMUL_M); OPCODE_CEIL_DECLARE(IMULH_M, IMULH_R); OPCODE_CEIL_DECLARE(ISMULH_R, IMULH_M); OPCODE_CEIL_DECLARE(ISMULH_M, ISMULH_R); OPCODE_CEIL_DECLARE(IMUL_RCP, ISMULH_M); OPCODE_CEIL_DECLARE(INEG_R, IMUL_RCP); OPCODE_CEIL_DECLARE(IXOR_R, INEG_R); OPCODE_CEIL_DECLARE(IXOR_M, IXOR_R); OPCODE_CEIL_DECLARE(IROR_R, IXOR_M); OPCODE_CEIL_DECLARE(IROL_R, IROR_R); OPCODE_CEIL_DECLARE(ISWAP_R, IROL_R); OPCODE_CEIL_DECLARE(FSWAP_R, ISWAP_R); OPCODE_CEIL_DECLARE(FADD_R, FSWAP_R); OPCODE_CEIL_DECLARE(FADD_M, FADD_R); OPCODE_CEIL_DECLARE(FSUB_R, FADD_M); OPCODE_CEIL_DECLARE(FSUB_M, FSUB_R); OPCODE_CEIL_DECLARE(FSCAL_R, FSUB_M); OPCODE_CEIL_DECLARE(FMUL_R, FSCAL_R); OPCODE_CEIL_DECLARE(FDIV_M, FMUL_R); OPCODE_CEIL_DECLARE(FSQRT_R, FDIV_M); OPCODE_CEIL_DECLARE(CBRANCH, FSQRT_R); OPCODE_CEIL_DECLARE(CFROUND, CBRANCH); OPCODE_CEIL_DECLARE(ISTORE, CFROUND); OPCODE_CEIL_DECLARE(NOP, ISTORE); #undef OPCODE_CEIL_DECLARE #define RANDOMX_EXE_ARGS InstructionByteCode& ibc, int& pc, uint8_t* scratchpad, ProgramConfiguration& config #define RANDOMX_GEN_ARGS Instruction& instr, int i, InstructionByteCode& ibc class BytecodeMachine; typedef void(BytecodeMachine::*InstructionGenBytecode)(RANDOMX_GEN_ARGS); class BytecodeMachine { public: void beginCompilation(NativeRegisterFile& regFile) { for (unsigned i = 0; i < RegistersCount; ++i) { registerUsage[i] = -1; } nreg = ®File; } void compileProgram(Program& program, InstructionByteCode bytecode[RANDOMX_PROGRAM_SIZE], NativeRegisterFile& regFile) { beginCompilation(regFile); for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) { auto& instr = program(i); auto& ibc = bytecode[i]; compileInstruction(instr, i, ibc); } } static void executeBytecode(InstructionByteCode bytecode[RANDOMX_PROGRAM_SIZE], uint8_t* scratchpad, ProgramConfiguration& config) { for (int pc = 0; pc < RANDOMX_PROGRAM_SIZE; ++pc) { auto& ibc = bytecode[pc]; executeInstruction(ibc, pc, scratchpad, config); } } void compileInstruction(RANDOMX_GEN_ARGS) #ifdef RANDOMX_GEN_TABLE { auto generator = genTable[instr.opcode]; (this->*generator)(instr, i, ibc); } #else ; #endif static void executeInstruction(RANDOMX_EXE_ARGS); static void exe_IADD_RS(RANDOMX_EXE_ARGS) { *ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm; } static void exe_IADD_M(RANDOMX_EXE_ARGS) { *ibc.idst += load64(getScratchpadAddress(ibc, scratchpad)); } static void exe_ISUB_R(RANDOMX_EXE_ARGS) { *ibc.idst -= *ibc.isrc; } static void exe_ISUB_M(RANDOMX_EXE_ARGS) { *ibc.idst -= load64(getScratchpadAddress(ibc, scratchpad)); } static void exe_IMUL_R(RANDOMX_EXE_ARGS) { *ibc.idst *= *ibc.isrc; } static void exe_IMUL_M(RANDOMX_EXE_ARGS) { *ibc.idst *= load64(getScratchpadAddress(ibc, scratchpad)); } static void exe_IMULH_R(RANDOMX_EXE_ARGS) { *ibc.idst = mulh(*ibc.idst, *ibc.isrc); } static void exe_IMULH_M(RANDOMX_EXE_ARGS) { *ibc.idst = mulh(*ibc.idst, load64(getScratchpadAddress(ibc, scratchpad))); } static void exe_ISMULH_R(RANDOMX_EXE_ARGS) { *ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(*ibc.isrc)); } static void exe_ISMULH_M(RANDOMX_EXE_ARGS) { *ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(load64(getScratchpadAddress(ibc, scratchpad)))); } static void exe_INEG_R(RANDOMX_EXE_ARGS) { *ibc.idst = ~(*ibc.idst) + 1; //two's complement negative } static void exe_IXOR_R(RANDOMX_EXE_ARGS) { *ibc.idst ^= *ibc.isrc; } static void exe_IXOR_M(RANDOMX_EXE_ARGS) { *ibc.idst ^= load64(getScratchpadAddress(ibc, scratchpad)); } static void exe_IROR_R(RANDOMX_EXE_ARGS) { *ibc.idst = rotr(*ibc.idst, *ibc.isrc & 63); } static void exe_IROL_R(RANDOMX_EXE_ARGS) { *ibc.idst = rotl(*ibc.idst, *ibc.isrc & 63); } static void exe_ISWAP_R(RANDOMX_EXE_ARGS) { int_reg_t temp = *ibc.isrc; *(int_reg_t*)ibc.isrc = *ibc.idst; *ibc.idst = temp; } static void exe_FSWAP_R(RANDOMX_EXE_ARGS) { *ibc.fdst = rx_swap_vec_f128(*ibc.fdst); } static void exe_FADD_R(RANDOMX_EXE_ARGS) { *ibc.fdst = rx_add_vec_f128(*ibc.fdst, *ibc.fsrc); } static void exe_FADD_M(RANDOMX_EXE_ARGS) { rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad)); *ibc.fdst = rx_add_vec_f128(*ibc.fdst, fsrc); } static void exe_FSUB_R(RANDOMX_EXE_ARGS) { *ibc.fdst = rx_sub_vec_f128(*ibc.fdst, *ibc.fsrc); } static void exe_FSUB_M(RANDOMX_EXE_ARGS) { rx_vec_f128 fsrc = rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad)); *ibc.fdst = rx_sub_vec_f128(*ibc.fdst, fsrc); } static void exe_FSCAL_R(RANDOMX_EXE_ARGS) { const rx_vec_f128 mask = rx_set1_vec_f128(0x80F0000000000000); *ibc.fdst = rx_xor_vec_f128(*ibc.fdst, mask); } static void exe_FMUL_R(RANDOMX_EXE_ARGS) { *ibc.fdst = rx_mul_vec_f128(*ibc.fdst, *ibc.fsrc); } static void exe_FDIV_M(RANDOMX_EXE_ARGS) { rx_vec_f128 fsrc = maskRegisterExponentMantissa( config, rx_cvt_packed_int_vec_f128(getScratchpadAddress(ibc, scratchpad)) ); *ibc.fdst = rx_div_vec_f128(*ibc.fdst, fsrc); } static void exe_FSQRT_R(RANDOMX_EXE_ARGS) { *ibc.fdst = rx_sqrt_vec_f128(*ibc.fdst); } static void exe_CBRANCH(RANDOMX_EXE_ARGS) { *ibc.idst += ibc.imm; if ((*ibc.idst & ibc.memMask) == 0) { pc = ibc.target; } } static void exe_CFROUND(RANDOMX_EXE_ARGS) { rx_set_rounding_mode(rotr(*ibc.isrc, ibc.imm) % 4); } static void exe_ISTORE(RANDOMX_EXE_ARGS) { store64(scratchpad + ((*ibc.idst + ibc.imm) & ibc.memMask), *ibc.isrc); } protected: static rx_vec_f128 maskRegisterExponentMantissa(ProgramConfiguration& config, rx_vec_f128 x) { const rx_vec_f128 xmantissaMask = rx_set_vec_f128(dynamicMantissaMask, dynamicMantissaMask); const rx_vec_f128 xexponentMask = rx_load_vec_f128((const double*)&config.eMask); x = rx_and_vec_f128(x, xmantissaMask); x = rx_or_vec_f128(x, xexponentMask); return x; } private: static const int_reg_t zero; int registerUsage[RegistersCount]; NativeRegisterFile* nreg; static void* getScratchpadAddress(InstructionByteCode& ibc, uint8_t* scratchpad) { uint32_t addr = (*ibc.isrc + ibc.imm) & ibc.memMask; return scratchpad + addr; } #ifdef RANDOMX_GEN_TABLE static InstructionGenBytecode genTable[256]; void gen_IADD_RS(RANDOMX_GEN_ARGS); void gen_IADD_M(RANDOMX_GEN_ARGS); void gen_ISUB_R(RANDOMX_GEN_ARGS); void gen_ISUB_M(RANDOMX_GEN_ARGS); void gen_IMUL_R(RANDOMX_GEN_ARGS); void gen_IMUL_M(RANDOMX_GEN_ARGS); void gen_IMULH_R(RANDOMX_GEN_ARGS); void gen_IMULH_M(RANDOMX_GEN_ARGS); void gen_ISMULH_R(RANDOMX_GEN_ARGS); void gen_ISMULH_M(RANDOMX_GEN_ARGS); void gen_IMUL_RCP(RANDOMX_GEN_ARGS); void gen_INEG_R(RANDOMX_GEN_ARGS); void gen_IXOR_R(RANDOMX_GEN_ARGS); void gen_IXOR_M(RANDOMX_GEN_ARGS); void gen_IROR_R(RANDOMX_GEN_ARGS); void gen_IROL_R(RANDOMX_GEN_ARGS); void gen_ISWAP_R(RANDOMX_GEN_ARGS); void gen_FSWAP_R(RANDOMX_GEN_ARGS); void gen_FADD_R(RANDOMX_GEN_ARGS); void gen_FADD_M(RANDOMX_GEN_ARGS); void gen_FSUB_R(RANDOMX_GEN_ARGS); void gen_FSUB_M(RANDOMX_GEN_ARGS); void gen_FSCAL_R(RANDOMX_GEN_ARGS); void gen_FMUL_R(RANDOMX_GEN_ARGS); void gen_FDIV_M(RANDOMX_GEN_ARGS); void gen_FSQRT_R(RANDOMX_GEN_ARGS); void gen_CBRANCH(RANDOMX_GEN_ARGS); void gen_CFROUND(RANDOMX_GEN_ARGS); void gen_ISTORE(RANDOMX_GEN_ARGS); void gen_NOP(RANDOMX_GEN_ARGS); #endif }; } RandomX-1.1.10/src/common.hpp000066400000000000000000000231521414227164600157440ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "blake2/endian.h" #include "configuration.h" #include "randomx.h" namespace randomx { static_assert(RANDOMX_ARGON_MEMORY >= 8, "RANDOMX_ARGON_MEMORY must be at least 8."); static_assert(RANDOMX_ARGON_MEMORY <= 2097152, "RANDOMX_ARGON_MEMORY must not exceed 2097152."); static_assert((RANDOMX_ARGON_MEMORY & (RANDOMX_ARGON_MEMORY - 1)) == 0, "RANDOMX_ARGON_MEMORY must be a power of 2."); static_assert(RANDOMX_ARGON_ITERATIONS > 0 && RANDOMX_ARGON_ITERATIONS < UINT32_MAX, "RANDOMX_ARGON_ITERATIONS must be a positive 32-bit integer."); static_assert(RANDOMX_ARGON_LANES > 0 && RANDOMX_ARGON_LANES <= 16777215, "RANDOMX_ARGON_LANES out of range"); static_assert(RANDOMX_DATASET_BASE_SIZE >= 64, "RANDOMX_DATASET_BASE_SIZE must be at least 64."); static_assert((RANDOMX_DATASET_BASE_SIZE & (RANDOMX_DATASET_BASE_SIZE - 1)) == 0, "RANDOMX_DATASET_BASE_SIZE must be a power of 2."); static_assert(RANDOMX_DATASET_BASE_SIZE <= 4294967296ULL, "RANDOMX_DATASET_BASE_SIZE must not exceed 4294967296."); static_assert(RANDOMX_DATASET_EXTRA_SIZE % 64 == 0, "RANDOMX_DATASET_EXTRA_SIZE must be divisible by 64."); static_assert((uint64_t)RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE <= 17179869184, "Dataset size must not exceed 16 GiB."); static_assert(RANDOMX_PROGRAM_SIZE > 0, "RANDOMX_PROGRAM_SIZE must be greater than 0"); static_assert(RANDOMX_PROGRAM_SIZE <= 32768, "RANDOMX_PROGRAM_SIZE must not exceed 32768"); static_assert(RANDOMX_PROGRAM_ITERATIONS > 0, "RANDOMX_PROGRAM_ITERATIONS must be greater than 0"); static_assert(RANDOMX_PROGRAM_COUNT > 0, "RANDOMX_PROGRAM_COUNT must be greater than 0"); static_assert((RANDOMX_SCRATCHPAD_L3 & (RANDOMX_SCRATCHPAD_L3 - 1)) == 0, "RANDOMX_SCRATCHPAD_L3 must be a power of 2."); static_assert(RANDOMX_SCRATCHPAD_L3 >= RANDOMX_SCRATCHPAD_L2, "RANDOMX_SCRATCHPAD_L3 must be greater than or equal to RANDOMX_SCRATCHPAD_L2."); static_assert((RANDOMX_SCRATCHPAD_L2 & (RANDOMX_SCRATCHPAD_L2 - 1)) == 0, "RANDOMX_SCRATCHPAD_L2 must be a power of 2."); static_assert(RANDOMX_SCRATCHPAD_L2 >= RANDOMX_SCRATCHPAD_L1, "RANDOMX_SCRATCHPAD_L2 must be greater than or equal to RANDOMX_SCRATCHPAD_L1."); static_assert(RANDOMX_SCRATCHPAD_L1 >= 64, "RANDOMX_SCRATCHPAD_L1 must be at least 64."); static_assert((RANDOMX_SCRATCHPAD_L1 & (RANDOMX_SCRATCHPAD_L1 - 1)) == 0, "RANDOMX_SCRATCHPAD_L1 must be a power of 2."); static_assert(RANDOMX_CACHE_ACCESSES > 1, "RANDOMX_CACHE_ACCESSES must be greater than 1"); static_assert(RANDOMX_SUPERSCALAR_LATENCY > 0, "RANDOMX_SUPERSCALAR_LATENCY must be greater than 0"); static_assert(RANDOMX_SUPERSCALAR_LATENCY <= 10000, "RANDOMX_SUPERSCALAR_LATENCY must not exceed 10000"); static_assert(RANDOMX_JUMP_BITS > 0, "RANDOMX_JUMP_BITS must be greater than 0."); static_assert(RANDOMX_JUMP_OFFSET >= 0, "RANDOMX_JUMP_OFFSET must be greater than or equal to 0."); static_assert(RANDOMX_JUMP_BITS + RANDOMX_JUMP_OFFSET <= 16, "RANDOMX_JUMP_BITS + RANDOMX_JUMP_OFFSET must not exceed 16."); constexpr int wtSum = RANDOMX_FREQ_IADD_RS + RANDOMX_FREQ_IADD_M + RANDOMX_FREQ_ISUB_R + \ RANDOMX_FREQ_ISUB_M + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M + RANDOMX_FREQ_IMULH_R + \ RANDOMX_FREQ_IMULH_M + RANDOMX_FREQ_ISMULH_R + RANDOMX_FREQ_ISMULH_M + RANDOMX_FREQ_IMUL_RCP + \ RANDOMX_FREQ_INEG_R + RANDOMX_FREQ_IXOR_R + RANDOMX_FREQ_IXOR_M + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_IROL_R + RANDOMX_FREQ_ISWAP_R + \ RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + \ RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R + RANDOMX_FREQ_CBRANCH + \ RANDOMX_FREQ_CFROUND + RANDOMX_FREQ_ISTORE + RANDOMX_FREQ_NOP; static_assert(wtSum == 256, "Sum of instruction frequencies must be 256."); constexpr uint32_t ArgonBlockSize = 1024; constexpr int ArgonSaltSize = sizeof("" RANDOMX_ARGON_SALT) - 1; static_assert(ArgonSaltSize >= 8, "RANDOMX_ARGON_SALT must be at least 8 characters long"); constexpr int SuperscalarMaxSize = 3 * RANDOMX_SUPERSCALAR_LATENCY + 2; constexpr size_t CacheLineSize = RANDOMX_DATASET_ITEM_SIZE; constexpr int ScratchpadSize = RANDOMX_SCRATCHPAD_L3; constexpr uint32_t CacheLineAlignMask = (RANDOMX_DATASET_BASE_SIZE - 1) & ~(CacheLineSize - 1); constexpr uint32_t CacheSize = RANDOMX_ARGON_MEMORY * ArgonBlockSize; constexpr uint64_t DatasetSize = RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE; constexpr uint32_t DatasetExtraItems = RANDOMX_DATASET_EXTRA_SIZE / RANDOMX_DATASET_ITEM_SIZE; constexpr uint32_t ConditionMask = ((1 << RANDOMX_JUMP_BITS) - 1); constexpr int ConditionOffset = RANDOMX_JUMP_OFFSET; constexpr int StoreL3Condition = 14; //Prevent some unsafe configurations. #ifndef RANDOMX_UNSAFE static_assert((uint64_t)ArgonBlockSize * RANDOMX_CACHE_ACCESSES * RANDOMX_ARGON_MEMORY + 33554432 >= (uint64_t)RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE, "Unsafe configuration: Memory-time tradeoffs"); static_assert((128 + RANDOMX_PROGRAM_SIZE * RANDOMX_FREQ_ISTORE / 256) * (RANDOMX_PROGRAM_COUNT * RANDOMX_PROGRAM_ITERATIONS) >= RANDOMX_SCRATCHPAD_L3, "Unsafe configuration: Insufficient Scratchpad writes"); static_assert(RANDOMX_PROGRAM_COUNT > 1, "Unsafe configuration: Program filtering strategies"); static_assert(RANDOMX_PROGRAM_SIZE >= 64, "Unsafe configuration: Low program entropy"); static_assert(RANDOMX_PROGRAM_ITERATIONS >= 400, "Unsafe configuration: High compilation overhead"); #endif #ifdef TRACE constexpr bool trace = true; #else constexpr bool trace = false; #endif #ifndef UNREACHABLE #ifdef __GNUC__ #define UNREACHABLE __builtin_unreachable() #elif _MSC_VER #define UNREACHABLE __assume(false) #else #define UNREACHABLE #endif #endif #if defined(_M_X64) || defined(__x86_64__) #define RANDOMX_HAVE_COMPILER 1 class JitCompilerX86; using JitCompiler = JitCompilerX86; #elif defined(__aarch64__) #define RANDOMX_HAVE_COMPILER 1 class JitCompilerA64; using JitCompiler = JitCompilerA64; #else #define RANDOMX_HAVE_COMPILER 0 class JitCompilerFallback; using JitCompiler = JitCompilerFallback; #endif using addr_t = uint32_t; using int_reg_t = uint64_t; struct fpu_reg_t { double lo; double hi; }; constexpr uint32_t ScratchpadL1 = RANDOMX_SCRATCHPAD_L1 / sizeof(int_reg_t); constexpr uint32_t ScratchpadL2 = RANDOMX_SCRATCHPAD_L2 / sizeof(int_reg_t); constexpr uint32_t ScratchpadL3 = RANDOMX_SCRATCHPAD_L3 / sizeof(int_reg_t); constexpr int ScratchpadL1Mask = (ScratchpadL1 - 1) * 8; constexpr int ScratchpadL2Mask = (ScratchpadL2 - 1) * 8; constexpr int ScratchpadL1Mask16 = (ScratchpadL1 / 2 - 1) * 16; constexpr int ScratchpadL2Mask16 = (ScratchpadL2 / 2 - 1) * 16; constexpr int ScratchpadL3Mask = (ScratchpadL3 - 1) * 8; constexpr int ScratchpadL3Mask64 = (ScratchpadL3 / 8 - 1) * 64; constexpr int RegistersCount = 8; constexpr int RegisterCountFlt = RegistersCount / 2; constexpr int RegisterNeedsDisplacement = 5; //x86 r13 register constexpr int RegisterNeedsSib = 4; //x86 r12 register inline bool isZeroOrPowerOf2(uint64_t x) { return (x & (x - 1)) == 0; } constexpr int mantissaSize = 52; constexpr int exponentSize = 11; constexpr uint64_t mantissaMask = (1ULL << mantissaSize) - 1; constexpr uint64_t exponentMask = (1ULL << exponentSize) - 1; constexpr int exponentBias = 1023; constexpr int dynamicExponentBits = 4; constexpr int staticExponentBits = 4; constexpr uint64_t constExponentBits = 0x300; constexpr uint64_t dynamicMantissaMask = (1ULL << (mantissaSize + dynamicExponentBits)) - 1; struct MemoryRegisters { addr_t mx, ma; uint8_t* memory = nullptr; }; //register file in little-endian byte order struct RegisterFile { int_reg_t r[RegistersCount]; fpu_reg_t f[RegisterCountFlt]; fpu_reg_t e[RegisterCountFlt]; fpu_reg_t a[RegisterCountFlt]; }; typedef void(ProgramFunc)(RegisterFile&, MemoryRegisters&, uint8_t* /* scratchpad */, uint64_t); typedef void(DatasetInitFunc)(randomx_cache* cache, uint8_t* dataset, uint32_t startBlock, uint32_t endBlock); typedef void(DatasetDeallocFunc)(randomx_dataset*); typedef void(CacheDeallocFunc)(randomx_cache*); typedef void(CacheInitializeFunc)(randomx_cache*, const void*, size_t); } RandomX-1.1.10/src/configuration.h000066400000000000000000000110041414227164600167540ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once //Cache size in KiB. Must be a power of 2. #define RANDOMX_ARGON_MEMORY 262144 //Number of Argon2d iterations for Cache initialization. #define RANDOMX_ARGON_ITERATIONS 3 //Number of parallel lanes for Cache initialization. #define RANDOMX_ARGON_LANES 1 //Argon2d salt #define RANDOMX_ARGON_SALT "RandomX\x03" //Number of random Cache accesses per Dataset item. Minimum is 2. #define RANDOMX_CACHE_ACCESSES 8 //Target latency for SuperscalarHash (in cycles of the reference CPU). #define RANDOMX_SUPERSCALAR_LATENCY 170 //Dataset base size in bytes. Must be a power of 2. #define RANDOMX_DATASET_BASE_SIZE 2147483648 //Dataset extra size. Must be divisible by 64. #define RANDOMX_DATASET_EXTRA_SIZE 33554368 //Number of instructions in a RandomX program. Must be divisible by 8. #define RANDOMX_PROGRAM_SIZE 256 //Number of iterations during VM execution. #define RANDOMX_PROGRAM_ITERATIONS 2048 //Number of chained VM executions per hash. #define RANDOMX_PROGRAM_COUNT 8 //Scratchpad L3 size in bytes. Must be a power of 2. #define RANDOMX_SCRATCHPAD_L3 2097152 //Scratchpad L2 size in bytes. Must be a power of two and less than or equal to RANDOMX_SCRATCHPAD_L3. #define RANDOMX_SCRATCHPAD_L2 262144 //Scratchpad L1 size in bytes. Must be a power of two (minimum 64) and less than or equal to RANDOMX_SCRATCHPAD_L2. #define RANDOMX_SCRATCHPAD_L1 16384 //Jump condition mask size in bits. #define RANDOMX_JUMP_BITS 8 //Jump condition mask offset in bits. The sum of RANDOMX_JUMP_BITS and RANDOMX_JUMP_OFFSET must not exceed 16. #define RANDOMX_JUMP_OFFSET 8 /* Instruction frequencies (per 256 opcodes) Total sum of frequencies must be 256 */ //Integer instructions #define RANDOMX_FREQ_IADD_RS 16 #define RANDOMX_FREQ_IADD_M 7 #define RANDOMX_FREQ_ISUB_R 16 #define RANDOMX_FREQ_ISUB_M 7 #define RANDOMX_FREQ_IMUL_R 16 #define RANDOMX_FREQ_IMUL_M 4 #define RANDOMX_FREQ_IMULH_R 4 #define RANDOMX_FREQ_IMULH_M 1 #define RANDOMX_FREQ_ISMULH_R 4 #define RANDOMX_FREQ_ISMULH_M 1 #define RANDOMX_FREQ_IMUL_RCP 8 #define RANDOMX_FREQ_INEG_R 2 #define RANDOMX_FREQ_IXOR_R 15 #define RANDOMX_FREQ_IXOR_M 5 #define RANDOMX_FREQ_IROR_R 8 #define RANDOMX_FREQ_IROL_R 2 #define RANDOMX_FREQ_ISWAP_R 4 //Floating point instructions #define RANDOMX_FREQ_FSWAP_R 4 #define RANDOMX_FREQ_FADD_R 16 #define RANDOMX_FREQ_FADD_M 5 #define RANDOMX_FREQ_FSUB_R 16 #define RANDOMX_FREQ_FSUB_M 5 #define RANDOMX_FREQ_FSCAL_R 6 #define RANDOMX_FREQ_FMUL_R 32 #define RANDOMX_FREQ_FDIV_M 4 #define RANDOMX_FREQ_FSQRT_R 6 //Control instructions #define RANDOMX_FREQ_CBRANCH 25 #define RANDOMX_FREQ_CFROUND 1 //Store instruction #define RANDOMX_FREQ_ISTORE 16 //No-op instruction #define RANDOMX_FREQ_NOP 0 /* ------ 256 */ RandomX-1.1.10/src/cpu.cpp000066400000000000000000000047371414227164600152460ustar00rootroot00000000000000/* Copyright (c) 2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "cpu.hpp" #if defined(_M_X64) || defined(__x86_64__) #define HAVE_CPUID #if defined(_MSC_VER) #include #define cpuid(info, x) __cpuidex(info, x, 0) #else //GCC #include void cpuid(int info[4], int InfoType) { __cpuid_count(InfoType, 0, info[0], info[1], info[2], info[3]); } #endif #endif #if defined(HAVE_HWCAP) #include #include #endif namespace randomx { Cpu::Cpu() : aes_(false), ssse3_(false), avx2_(false) { #ifdef HAVE_CPUID int info[4]; cpuid(info, 0); int nIds = info[0]; if (nIds >= 0x00000001) { cpuid(info, 0x00000001); ssse3_ = (info[2] & (1 << 9)) != 0; aes_ = (info[2] & (1 << 25)) != 0; } if (nIds >= 0x00000007) { cpuid(info, 0x00000007); avx2_ = (info[1] & (1 << 5)) != 0; } #elif defined(__aarch64__) #if defined(HWCAP_AES) long hwcaps = getauxval(AT_HWCAP); aes_ = (hwcaps & HWCAP_AES) != 0; #elif defined(__APPLE__) aes_ = true; #endif #endif //TODO POWER8 AES } } RandomX-1.1.10/src/cpu.hpp000066400000000000000000000033471414227164600152470ustar00rootroot00000000000000/* Copyright (c) 2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once namespace randomx { class Cpu { public: Cpu(); bool hasAes() const { return aes_; } bool hasSsse3() const { return ssse3_; } bool hasAvx2() const { return avx2_; } private: bool aes_, ssse3_, avx2_; }; } RandomX-1.1.10/src/dataset.cpp000066400000000000000000000161571414227164600161030ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Original code from Argon2 reference source code package used under CC0 Licence * https://github.com/P-H-C/phc-winner-argon2 * Copyright 2015 * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves */ #include #include #include #include #include #include #include #include "common.hpp" #include "dataset.hpp" #include "virtual_memory.hpp" #include "superscalar.hpp" #include "blake2_generator.hpp" #include "reciprocal.h" #include "blake2/endian.h" #include "argon2.h" #include "argon2_core.h" #include "jit_compiler.hpp" #include "intrin_portable.h" static_assert(RANDOMX_ARGON_MEMORY % (RANDOMX_ARGON_LANES * ARGON2_SYNC_POINTS) == 0, "RANDOMX_ARGON_MEMORY - invalid value"); static_assert(ARGON2_BLOCK_SIZE == randomx::ArgonBlockSize, "Unpexpected value of ARGON2_BLOCK_SIZE"); namespace randomx { template void deallocCache(randomx_cache* cache) { if (cache->memory != nullptr) Allocator::freeMemory(cache->memory, CacheSize); if (cache->jit != nullptr) delete cache->jit; } template void deallocCache(randomx_cache* cache); template void deallocCache(randomx_cache* cache); void initCache(randomx_cache* cache, const void* key, size_t keySize) { uint32_t memory_blocks, segment_length; argon2_instance_t instance; argon2_context context; context.out = nullptr; context.outlen = 0; context.pwd = CONST_CAST(uint8_t *)key; context.pwdlen = (uint32_t)keySize; context.salt = CONST_CAST(uint8_t *)RANDOMX_ARGON_SALT; context.saltlen = (uint32_t)randomx::ArgonSaltSize; context.secret = NULL; context.secretlen = 0; context.ad = NULL; context.adlen = 0; context.t_cost = RANDOMX_ARGON_ITERATIONS; context.m_cost = RANDOMX_ARGON_MEMORY; context.lanes = RANDOMX_ARGON_LANES; context.threads = 1; context.allocate_cbk = NULL; context.free_cbk = NULL; context.flags = ARGON2_DEFAULT_FLAGS; context.version = ARGON2_VERSION_NUMBER; int inputsValid = randomx_argon2_validate_inputs(&context); assert(inputsValid == ARGON2_OK); /* 2. Align memory size */ /* Minimum memory_blocks = 8L blocks, where L is the number of lanes */ memory_blocks = context.m_cost; segment_length = memory_blocks / (context.lanes * ARGON2_SYNC_POINTS); instance.version = context.version; instance.memory = NULL; instance.passes = context.t_cost; instance.memory_blocks = memory_blocks; instance.segment_length = segment_length; instance.lane_length = segment_length * ARGON2_SYNC_POINTS; instance.lanes = context.lanes; instance.threads = context.threads; instance.type = Argon2_d; instance.memory = (block*)cache->memory; instance.impl = cache->argonImpl; if (instance.threads > instance.lanes) { instance.threads = instance.lanes; } /* 3. Initialization: Hashing inputs, allocating memory, filling first * blocks */ randomx_argon2_initialize(&instance, &context); randomx_argon2_fill_memory_blocks(&instance); cache->reciprocalCache.clear(); randomx::Blake2Generator gen(key, keySize); for (int i = 0; i < RANDOMX_CACHE_ACCESSES; ++i) { randomx::generateSuperscalar(cache->programs[i], gen); for (unsigned j = 0; j < cache->programs[i].getSize(); ++j) { auto& instr = cache->programs[i](j); if ((SuperscalarInstructionType)instr.opcode == SuperscalarInstructionType::IMUL_RCP) { auto rcp = randomx_reciprocal(instr.getImm32()); instr.setImm32(cache->reciprocalCache.size()); cache->reciprocalCache.push_back(rcp); } } } } void initCacheCompile(randomx_cache* cache, const void* key, size_t keySize) { initCache(cache, key, keySize); cache->jit->enableWriting(); cache->jit->generateSuperscalarHash(cache->programs, cache->reciprocalCache); cache->jit->generateDatasetInitCode(); cache->jit->enableExecution(); } constexpr uint64_t superscalarMul0 = 6364136223846793005ULL; constexpr uint64_t superscalarAdd1 = 9298411001130361340ULL; constexpr uint64_t superscalarAdd2 = 12065312585734608966ULL; constexpr uint64_t superscalarAdd3 = 9306329213124626780ULL; constexpr uint64_t superscalarAdd4 = 5281919268842080866ULL; constexpr uint64_t superscalarAdd5 = 10536153434571861004ULL; constexpr uint64_t superscalarAdd6 = 3398623926847679864ULL; constexpr uint64_t superscalarAdd7 = 9549104520008361294ULL; static inline uint8_t* getMixBlock(uint64_t registerValue, uint8_t *memory) { constexpr uint32_t mask = CacheSize / CacheLineSize - 1; return memory + (registerValue & mask) * CacheLineSize; } void initDatasetItem(randomx_cache* cache, uint8_t* out, uint64_t itemNumber) { int_reg_t rl[8]; uint8_t* mixBlock; uint64_t registerValue = itemNumber; rl[0] = (itemNumber + 1) * superscalarMul0; rl[1] = rl[0] ^ superscalarAdd1; rl[2] = rl[0] ^ superscalarAdd2; rl[3] = rl[0] ^ superscalarAdd3; rl[4] = rl[0] ^ superscalarAdd4; rl[5] = rl[0] ^ superscalarAdd5; rl[6] = rl[0] ^ superscalarAdd6; rl[7] = rl[0] ^ superscalarAdd7; for (unsigned i = 0; i < RANDOMX_CACHE_ACCESSES; ++i) { mixBlock = getMixBlock(registerValue, cache->memory); rx_prefetch_nta(mixBlock); SuperscalarProgram& prog = cache->programs[i]; executeSuperscalar(rl, prog, &cache->reciprocalCache); for (unsigned q = 0; q < 8; ++q) rl[q] ^= load64_native(mixBlock + 8 * q); registerValue = rl[prog.getAddressRegister()]; } memcpy(out, &rl, CacheLineSize); } void initDataset(randomx_cache* cache, uint8_t* dataset, uint32_t startItem, uint32_t endItem) { for (uint32_t itemNumber = startItem; itemNumber < endItem; ++itemNumber, dataset += CacheLineSize) initDatasetItem(cache, dataset, itemNumber); } } RandomX-1.1.10/src/dataset.hpp000066400000000000000000000075021414227164600161020ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "common.hpp" #include "superscalar_program.hpp" #include "allocator.hpp" #include "argon2.h" /* Global scope for C binding */ struct randomx_dataset { uint8_t* memory = nullptr; randomx::DatasetDeallocFunc* dealloc; }; /* Global scope for C binding */ struct randomx_cache { uint8_t* memory = nullptr; randomx::CacheDeallocFunc* dealloc; randomx::JitCompiler* jit; randomx::CacheInitializeFunc* initialize; randomx::DatasetInitFunc* datasetInit; randomx::SuperscalarProgram programs[RANDOMX_CACHE_ACCESSES]; std::vector reciprocalCache; std::string cacheKey; randomx_argon2_impl* argonImpl; bool isInitialized() { return programs[0].getSize() != 0; } }; //A pointer to a standard-layout struct object points to its initial member static_assert(std::is_standard_layout(), "randomx_dataset must be a standard-layout struct"); //the following assert fails when compiling Debug in Visual Studio (JIT mode will crash in Debug) #if defined(_MSC_VER) && !defined(__INTEL_COMPILER) && defined(_DEBUG) #define TO_STR(x) #x #define STR(x) TO_STR(x) #pragma message ( __FILE__ "(" STR(__LINE__) ") warning: check std::is_standard_layout() is disabled for Debug configuration. JIT mode will crash." ) #undef STR #undef TO_STR #else static_assert(std::is_standard_layout(), "randomx_cache must be a standard-layout struct"); #endif namespace randomx { using DefaultAllocator = AlignedAllocator; template void deallocDataset(randomx_dataset* dataset) { if (dataset->memory != nullptr) Allocator::freeMemory(dataset->memory, DatasetSize); } template void deallocCache(randomx_cache* cache); void initCache(randomx_cache*, const void*, size_t); void initCacheCompile(randomx_cache*, const void*, size_t); void initDatasetItem(randomx_cache* cache, uint8_t* out, uint64_t blockNumber); void initDataset(randomx_cache* cache, uint8_t* dataset, uint32_t startBlock, uint32_t endBlock); inline randomx_argon2_impl* selectArgonImpl(randomx_flags flags) { if (flags & RANDOMX_FLAG_ARGON2_AVX2) { return randomx_argon2_impl_avx2(); } if (flags & RANDOMX_FLAG_ARGON2_SSSE3) { return randomx_argon2_impl_ssse3(); } return &randomx_argon2_fill_segment_ref; } } RandomX-1.1.10/src/instruction.cpp000066400000000000000000000256721414227164600170410ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "instruction.hpp" #include "common.hpp" namespace randomx { void Instruction::print(std::ostream& os) const { os << names[opcode] << " "; auto handler = engine[opcode]; (this->*handler)(os); } void Instruction::genAddressReg(std::ostream& os, int srcIndex) const { os << (getModMem() ? "L1" : "L2") << "[r" << srcIndex << std::showpos << (int32_t)getImm32() << std::noshowpos << "]"; } void Instruction::genAddressRegDst(std::ostream& os, int dstIndex) const { if (getModCond() < StoreL3Condition) os << (getModMem() ? "L1" : "L2"); else os << "L3"; os << "[r" << dstIndex << std::showpos << (int32_t)getImm32() << std::noshowpos << "]"; } void Instruction::genAddressImm(std::ostream& os) const { os << "L3" << "[" << (getImm32() & ScratchpadL3Mask) << "]"; } void Instruction::h_IADD_RS(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; os << "r" << dstIndex << ", r" << srcIndex; if(dstIndex == RegisterNeedsDisplacement) { os << ", " << (int32_t)getImm32(); } os << ", SHFT " << getModShift() << std::endl; } void Instruction::h_IADD_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_ISUB_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", r" << srcIndex << std::endl; } else { os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl; } } void Instruction::h_ISUB_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_IMUL_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", r" << srcIndex << std::endl; } else { os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl; } } void Instruction::h_IMUL_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_IMULH_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; os << "r" << dstIndex << ", r" << srcIndex << std::endl; } void Instruction::h_IMULH_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_ISMULH_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; os << "r" << dstIndex << ", r" << srcIndex << std::endl; } void Instruction::h_ISMULH_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_INEG_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; os << "r" << dstIndex << std::endl; } void Instruction::h_IXOR_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", r" << srcIndex << std::endl; } else { os << "r" << dstIndex << ", " << (int32_t)getImm32() << std::endl; } } void Instruction::h_IXOR_M(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } else { os << "r" << dstIndex << ", "; genAddressImm(os); os << std::endl; } } void Instruction::h_IROR_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", r" << srcIndex << std::endl; } else { os << "r" << dstIndex << ", " << (getImm32() & 63) << std::endl; } } void Instruction::h_IROL_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; if (dstIndex != srcIndex) { os << "r" << dstIndex << ", r" << srcIndex << std::endl; } else { os << "r" << dstIndex << ", " << (getImm32() & 63) << std::endl; } } void Instruction::h_IMUL_RCP(std::ostream& os) const { auto dstIndex = dst % RegistersCount; os << "r" << dstIndex << ", " << getImm32() << std::endl; } void Instruction::h_ISWAP_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; os << "r" << dstIndex << ", r" << srcIndex << std::endl; } void Instruction::h_FSWAP_R(std::ostream& os) const { auto dstIndex = dst % RegistersCount; const char reg = (dstIndex >= RegisterCountFlt) ? 'e' : 'f'; dstIndex %= RegisterCountFlt; os << reg << dstIndex << std::endl; } void Instruction::h_FADD_R(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegisterCountFlt; os << "f" << dstIndex << ", a" << srcIndex << std::endl; } void Instruction::h_FADD_M(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegistersCount; os << "f" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } void Instruction::h_FSUB_R(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegisterCountFlt; os << "f" << dstIndex << ", a" << srcIndex << std::endl; } void Instruction::h_FSUB_M(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegistersCount; os << "f" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } void Instruction::h_FSCAL_R(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; os << "f" << dstIndex << std::endl; } void Instruction::h_FMUL_R(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegisterCountFlt; os << "e" << dstIndex << ", a" << srcIndex << std::endl; } void Instruction::h_FDIV_M(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; auto srcIndex = src % RegistersCount; os << "e" << dstIndex << ", "; genAddressReg(os, srcIndex); os << std::endl; } void Instruction::h_FSQRT_R(std::ostream& os) const { auto dstIndex = dst % RegisterCountFlt; os << "e" << dstIndex << std::endl; } void Instruction::h_CFROUND(std::ostream& os) const { auto srcIndex = src % RegistersCount; os << "r" << srcIndex << ", " << (getImm32() & 63) << std::endl; } void Instruction::h_CBRANCH(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; os << "r" << dstIndex << ", " << (int32_t)getImm32() << ", COND " << (int)(getModCond()) << std::endl; } void Instruction::h_ISTORE(std::ostream& os) const { auto dstIndex = dst % RegistersCount; auto srcIndex = src % RegistersCount; genAddressRegDst(os, dstIndex); os << ", r" << srcIndex << std::endl; } void Instruction::h_NOP(std::ostream& os) const { os << std::endl; } #include "instruction_weights.hpp" #define INST_NAME(x) REPN(#x, WT(x)) #define INST_HANDLE(x) REPN(&Instruction::h_##x, WT(x)) const char* Instruction::names[256] = { INST_NAME(IADD_RS) INST_NAME(IADD_M) INST_NAME(ISUB_R) INST_NAME(ISUB_M) INST_NAME(IMUL_R) INST_NAME(IMUL_M) INST_NAME(IMULH_R) INST_NAME(IMULH_M) INST_NAME(ISMULH_R) INST_NAME(ISMULH_M) INST_NAME(IMUL_RCP) INST_NAME(INEG_R) INST_NAME(IXOR_R) INST_NAME(IXOR_M) INST_NAME(IROR_R) INST_NAME(IROL_R) INST_NAME(ISWAP_R) INST_NAME(FSWAP_R) INST_NAME(FADD_R) INST_NAME(FADD_M) INST_NAME(FSUB_R) INST_NAME(FSUB_M) INST_NAME(FSCAL_R) INST_NAME(FMUL_R) INST_NAME(FDIV_M) INST_NAME(FSQRT_R) INST_NAME(CBRANCH) INST_NAME(CFROUND) INST_NAME(ISTORE) INST_NAME(NOP) }; InstructionFormatter Instruction::engine[256] = { INST_HANDLE(IADD_RS) INST_HANDLE(IADD_M) INST_HANDLE(ISUB_R) INST_HANDLE(ISUB_M) INST_HANDLE(IMUL_R) INST_HANDLE(IMUL_M) INST_HANDLE(IMULH_R) INST_HANDLE(IMULH_M) INST_HANDLE(ISMULH_R) INST_HANDLE(ISMULH_M) INST_HANDLE(IMUL_RCP) INST_HANDLE(INEG_R) INST_HANDLE(IXOR_R) INST_HANDLE(IXOR_M) INST_HANDLE(IROR_R) INST_HANDLE(IROL_R) INST_HANDLE(ISWAP_R) INST_HANDLE(FSWAP_R) INST_HANDLE(FADD_R) INST_HANDLE(FADD_M) INST_HANDLE(FSUB_R) INST_HANDLE(FSUB_M) INST_HANDLE(FSCAL_R) INST_HANDLE(FMUL_R) INST_HANDLE(FDIV_M) INST_HANDLE(FSQRT_R) INST_HANDLE(CBRANCH) INST_HANDLE(CFROUND) INST_HANDLE(ISTORE) INST_HANDLE(NOP) }; }RandomX-1.1.10/src/instruction.hpp000066400000000000000000000106461414227164600170410ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "blake2/endian.h" namespace randomx { class Instruction; typedef void(Instruction::*InstructionFormatter)(std::ostream&) const; enum class InstructionType : uint16_t { IADD_RS = 0, IADD_M = 1, ISUB_R = 2, ISUB_M = 3, IMUL_R = 4, IMUL_M = 5, IMULH_R = 6, IMULH_M = 7, ISMULH_R = 8, ISMULH_M = 9, IMUL_RCP = 10, INEG_R = 11, IXOR_R = 12, IXOR_M = 13, IROR_R = 14, IROL_R = 15, ISWAP_R = 16, FSWAP_R = 17, FADD_R = 18, FADD_M = 19, FSUB_R = 20, FSUB_M = 21, FSCAL_R = 22, FMUL_R = 23, FDIV_M = 24, FSQRT_R = 25, CBRANCH = 26, CFROUND = 27, ISTORE = 28, NOP = 29, }; class Instruction { public: uint32_t getImm32() const { return load32(&imm32); } void setImm32(uint32_t val) { return store32(&imm32, val); } const char* getName() const { return names[opcode]; } friend std::ostream& operator<<(std::ostream& os, const Instruction& i) { i.print(os); return os; } int getModMem() const { return mod % 4; //bits 0-1 } int getModShift() const { return (mod >> 2) % 4; //bits 2-3 } int getModCond() const { return mod >> 4; //bits 4-7 } void setMod(uint8_t val) { mod = val; } uint8_t opcode; uint8_t dst; uint8_t src; uint8_t mod; uint32_t imm32; private: void print(std::ostream&) const; static const char* names[256]; static InstructionFormatter engine[256]; void genAddressReg(std::ostream& os, int) const; void genAddressImm(std::ostream& os) const; void genAddressRegDst(std::ostream&, int) const; void h_IADD_RS(std::ostream&) const; void h_IADD_M(std::ostream&) const; void h_ISUB_R(std::ostream&) const; void h_ISUB_M(std::ostream&) const; void h_IMUL_R(std::ostream&) const; void h_IMUL_M(std::ostream&) const; void h_IMULH_R(std::ostream&) const; void h_IMULH_M(std::ostream&) const; void h_ISMULH_R(std::ostream&) const; void h_ISMULH_M(std::ostream&) const; void h_IMUL_RCP(std::ostream&) const; void h_INEG_R(std::ostream&) const; void h_IXOR_R(std::ostream&) const; void h_IXOR_M(std::ostream&) const; void h_IROR_R(std::ostream&) const; void h_IROL_R(std::ostream&) const; void h_ISWAP_R(std::ostream&) const; void h_FSWAP_R(std::ostream&) const; void h_FADD_R(std::ostream&) const; void h_FADD_M(std::ostream&) const; void h_FSUB_R(std::ostream&) const; void h_FSUB_M(std::ostream&) const; void h_FSCAL_R(std::ostream&) const; void h_FMUL_R(std::ostream&) const; void h_FDIV_M(std::ostream&) const; void h_FSQRT_R(std::ostream&) const; void h_CBRANCH(std::ostream&) const; void h_CFROUND(std::ostream&) const; void h_ISTORE(std::ostream&) const; void h_NOP(std::ostream&) const; }; static_assert(sizeof(Instruction) == 8, "Invalid size of struct randomx::Instruction"); static_assert(std::is_standard_layout(), "randomx::Instruction must be a standard-layout struct"); }RandomX-1.1.10/src/instruction_weights.hpp000066400000000000000000000053721414227164600205730ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #define REP0(x) #define REP1(x) x, #define REP2(x) REP1(x) x, #define REP3(x) REP2(x) x, #define REP4(x) REP3(x) x, #define REP5(x) REP4(x) x, #define REP6(x) REP5(x) x, #define REP7(x) REP6(x) x, #define REP8(x) REP7(x) x, #define REP9(x) REP8(x) x, #define REP10(x) REP9(x) x, #define REP11(x) REP10(x) x, #define REP12(x) REP11(x) x, #define REP13(x) REP12(x) x, #define REP14(x) REP13(x) x, #define REP15(x) REP14(x) x, #define REP16(x) REP15(x) x, #define REP17(x) REP16(x) x, #define REP18(x) REP17(x) x, #define REP19(x) REP18(x) x, #define REP20(x) REP19(x) x, #define REP21(x) REP20(x) x, #define REP22(x) REP21(x) x, #define REP23(x) REP22(x) x, #define REP24(x) REP23(x) x, #define REP25(x) REP24(x) x, #define REP26(x) REP25(x) x, #define REP27(x) REP26(x) x, #define REP28(x) REP27(x) x, #define REP29(x) REP28(x) x, #define REP30(x) REP29(x) x, #define REP31(x) REP30(x) x, #define REP32(x) REP31(x) x, #define REP33(x) REP32(x) x, #define REP40(x) REP32(x) REP8(x) #define REP64(x) REP32(x) REP32(x) #define REP128(x) REP32(x) REP32(x) REP32(x) REP32(x) #define REP232(x) REP128(x) REP40(x) REP40(x) REP24(x) #define REP256(x) REP128(x) REP128(x) #define REPNX(x,N) REP##N(x) #define REPN(x,N) REPNX(x,N) #define NUM(x) x #define WT(x) NUM(RANDOMX_FREQ_##x) RandomX-1.1.10/src/instructions_portable.cpp000066400000000000000000000115571414227164600211110ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "common.hpp" #include "intrin_portable.h" #include "blake2/endian.h" #if defined(__SIZEOF_INT128__) typedef unsigned __int128 uint128_t; typedef __int128 int128_t; uint64_t mulh(uint64_t a, uint64_t b) { return ((uint128_t)a * b) >> 64; } int64_t smulh(int64_t a, int64_t b) { return ((int128_t)a * b) >> 64; } #define HAVE_MULH #define HAVE_SMULH #endif #if defined(_MSC_VER) #define HAS_VALUE(X) X ## 0 #define EVAL_DEFINE(X) HAS_VALUE(X) #include #include uint64_t rotl(uint64_t x, unsigned int c) { return _rotl64(x, c); } uint64_t rotr(uint64_t x, unsigned int c) { return _rotr64(x, c); } #define HAVE_ROTL #define HAVE_ROTR #if EVAL_DEFINE(__MACHINEARM64_X64(1)) uint64_t mulh(uint64_t a, uint64_t b) { return __umulh(a, b); } #define HAVE_MULH #endif #if EVAL_DEFINE(__MACHINEX64(1)) int64_t smulh(int64_t a, int64_t b) { int64_t hi; _mul128(a, b, &hi); return hi; } #define HAVE_SMULH #endif static void setRoundMode_(uint32_t mode) { _controlfp(mode, _MCW_RC); } #define HAVE_SETROUNDMODE_IMPL #endif #ifndef HAVE_SETROUNDMODE_IMPL static void setRoundMode_(uint32_t mode) { fesetround(mode); } #endif #ifndef HAVE_ROTR uint64_t rotr(uint64_t a, unsigned int b) { return (a >> b) | (a << (-b & 63)); } #define HAVE_ROTR #endif #ifndef HAVE_ROTL uint64_t rotl(uint64_t a, unsigned int b) { return (a << b) | (a >> (-b & 63)); } #define HAVE_ROTL #endif #ifndef HAVE_MULH #define LO(x) ((x)&0xffffffff) #define HI(x) ((x)>>32) uint64_t mulh(uint64_t a, uint64_t b) { uint64_t ah = HI(a), al = LO(a); uint64_t bh = HI(b), bl = LO(b); uint64_t x00 = al * bl; uint64_t x01 = al * bh; uint64_t x10 = ah * bl; uint64_t x11 = ah * bh; uint64_t m1 = LO(x10) + LO(x01) + HI(x00); uint64_t m2 = HI(x10) + HI(x01) + LO(x11) + HI(m1); uint64_t m3 = HI(x11) + HI(m2); return (m3 << 32) + LO(m2); } #define HAVE_MULH #endif #ifndef HAVE_SMULH int64_t smulh(int64_t a, int64_t b) { int64_t hi = mulh(a, b); if (a < 0LL) hi -= b; if (b < 0LL) hi -= a; return hi; } #define HAVE_SMULH #endif #ifdef RANDOMX_DEFAULT_FENV void rx_reset_float_state() { setRoundMode_(FE_TONEAREST); rx_set_double_precision(); //set precision to 53 bits if needed by the platform } void rx_set_rounding_mode(uint32_t mode) { switch (mode & 3) { case RoundDown: setRoundMode_(FE_DOWNWARD); break; case RoundUp: setRoundMode_(FE_UPWARD); break; case RoundToZero: setRoundMode_(FE_TOWARDZERO); break; case RoundToNearest: setRoundMode_(FE_TONEAREST); break; default: UNREACHABLE; } } uint32_t rx_get_rounding_mode() { switch (fegetround()) { case FE_DOWNWARD: return RoundDown; case FE_UPWARD: return RoundUp; case FE_TOWARDZERO: return RoundToZero; case FE_TONEAREST: return RoundToNearest; default: UNREACHABLE; } } #endif #ifdef RANDOMX_USE_X87 #if defined(_MSC_VER) && defined(_M_IX86) void rx_set_double_precision() { _control87(_PC_53, _MCW_PC); } #elif defined(__i386) void rx_set_double_precision() { uint16_t volatile x87cw; asm volatile("fstcw %0" : "=m" (x87cw)); x87cw &= ~0x300; x87cw |= 0x200; asm volatile("fldcw %0" : : "m" (x87cw)); } #endif #endif //RANDOMX_USE_X87 union double_ser_t { double f; uint64_t i; }; double loadDoublePortable(const void* addr) { double_ser_t ds; ds.i = load64(addr); return ds.f; } RandomX-1.1.10/src/intrin_portable.h000066400000000000000000000453231414227164600173130ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "blake2/endian.h" constexpr int32_t unsigned32ToSigned2sCompl(uint32_t x) { return (-1 == ~0) ? (int32_t)x : (x > INT32_MAX ? (-(int32_t)(UINT32_MAX - x) - 1) : (int32_t)x); } constexpr int64_t unsigned64ToSigned2sCompl(uint64_t x) { return (-1 == ~0) ? (int64_t)x : (x > INT64_MAX ? (-(int64_t)(UINT64_MAX - x) - 1) : (int64_t)x); } constexpr uint64_t signExtend2sCompl(uint32_t x) { return (-1 == ~0) ? (int64_t)(int32_t)(x) : (x > INT32_MAX ? (x | 0xffffffff00000000ULL) : (uint64_t)x); } constexpr int RoundToNearest = 0; constexpr int RoundDown = 1; constexpr int RoundUp = 2; constexpr int RoundToZero = 3; //MSVC doesn't define __SSE2__, so we have to define it manually if SSE2 is available #if !defined(__SSE2__) && (defined(_M_X64) || (defined(_M_IX86_FP) && _M_IX86_FP == 2)) #define __SSE2__ 1 #endif //MSVC doesn't define __AES__ #if defined(_MSC_VER) && defined(__SSE2__) #define __AES__ #endif //the library "sqrt" function provided by MSVC for x86 targets doesn't give //the correct results, so we have to use inline assembly to call x87 fsqrt directly #if !defined(__SSE2__) #if defined(_MSC_VER) && defined(_M_IX86) inline double __cdecl rx_sqrt(double x) { __asm { fld x fsqrt } } #define rx_sqrt rx_sqrt void rx_set_double_precision(); #define RANDOMX_USE_X87 #elif defined(__i386) void rx_set_double_precision(); #define RANDOMX_USE_X87 #endif #endif //__SSE2__ #if !defined(rx_sqrt) #define rx_sqrt sqrt #endif #if !defined(RANDOMX_USE_X87) #define rx_set_double_precision(x) #endif #ifdef __SSE2__ #ifdef __GNUC__ #include #else #include #endif typedef __m128i rx_vec_i128; typedef __m128d rx_vec_f128; #define rx_aligned_alloc(a, b) _mm_malloc(a,b) #define rx_aligned_free(a) _mm_free(a) #define rx_prefetch_nta(x) _mm_prefetch((const char *)(x), _MM_HINT_NTA) #define rx_prefetch_t0(x) _mm_prefetch((const char *)(x), _MM_HINT_T0) #define rx_load_vec_f128 _mm_load_pd #define rx_store_vec_f128 _mm_store_pd #define rx_add_vec_f128 _mm_add_pd #define rx_sub_vec_f128 _mm_sub_pd #define rx_mul_vec_f128 _mm_mul_pd #define rx_div_vec_f128 _mm_div_pd #define rx_sqrt_vec_f128 _mm_sqrt_pd FORCE_INLINE rx_vec_f128 rx_swap_vec_f128(rx_vec_f128 a) { return _mm_shuffle_pd(a, a, 1); } FORCE_INLINE rx_vec_f128 rx_set_vec_f128(uint64_t x1, uint64_t x0) { return _mm_castsi128_pd(_mm_set_epi64x(x1, x0)); } FORCE_INLINE rx_vec_f128 rx_set1_vec_f128(uint64_t x) { return _mm_castsi128_pd(_mm_set1_epi64x(x)); } #define rx_xor_vec_f128 _mm_xor_pd #define rx_and_vec_f128 _mm_and_pd #define rx_or_vec_f128 _mm_or_pd #ifdef __AES__ #define rx_aesenc_vec_i128 _mm_aesenc_si128 #define rx_aesdec_vec_i128 _mm_aesdec_si128 #define HAVE_AES 1 #endif //__AES__ FORCE_INLINE int rx_vec_i128_x(rx_vec_i128 a) { return _mm_cvtsi128_si32(a); } FORCE_INLINE int rx_vec_i128_y(rx_vec_i128 a) { return _mm_cvtsi128_si32(_mm_shuffle_epi32(a, 0x55)); } FORCE_INLINE int rx_vec_i128_z(rx_vec_i128 a) { return _mm_cvtsi128_si32(_mm_shuffle_epi32(a, 0xaa)); } FORCE_INLINE int rx_vec_i128_w(rx_vec_i128 a) { return _mm_cvtsi128_si32(_mm_shuffle_epi32(a, 0xff)); } #define rx_set_int_vec_i128 _mm_set_epi32 #define rx_xor_vec_i128 _mm_xor_si128 #define rx_load_vec_i128 _mm_load_si128 #define rx_store_vec_i128 _mm_store_si128 FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) { __m128i ix = _mm_loadl_epi64((const __m128i*)addr); return _mm_cvtepi32_pd(ix); } constexpr uint32_t rx_mxcsr_default = 0x9FC0; //Flush to zero, denormals are zero, default rounding mode, all exceptions disabled FORCE_INLINE void rx_reset_float_state() { _mm_setcsr(rx_mxcsr_default); } FORCE_INLINE void rx_set_rounding_mode(uint32_t mode) { _mm_setcsr(rx_mxcsr_default | (mode << 13)); } FORCE_INLINE uint32_t rx_get_rounding_mode() { return (_mm_getcsr() >> 13) & 3; } #elif defined(__PPC64__) && defined(__ALTIVEC__) && defined(__VSX__) //sadly only POWER7 and newer will be able to use SIMD acceleration. Earlier processors cant use doubles or 64 bit integers with SIMD #include #include #include #include #undef vector #undef pixel #undef bool typedef __vector uint8_t __m128i; typedef __vector uint32_t __m128l; typedef __vector int __m128li; typedef __vector uint64_t __m128ll; typedef __vector double __m128d; typedef __m128i rx_vec_i128; typedef __m128d rx_vec_f128; typedef union{ rx_vec_i128 i; rx_vec_f128 d; uint64_t u64[2]; double d64[2]; uint32_t u32[4]; int i32[4]; } vec_u; #define rx_aligned_alloc(a, b) malloc(a) #define rx_aligned_free(a) free(a) #define rx_prefetch_nta(x) #define rx_prefetch_t0(x) /* Splat 64-bit long long to 2 64-bit long longs */ FORCE_INLINE __m128i vec_splat2sd (int64_t scalar) { return (__m128i) vec_splats (scalar); } FORCE_INLINE rx_vec_f128 rx_load_vec_f128(const double* pd) { #if defined(NATIVE_LITTLE_ENDIAN) return (rx_vec_f128)vec_vsx_ld(0,pd); #else vec_u t; t.u64[0] = load64(pd + 0); t.u64[1] = load64(pd + 1); return (rx_vec_f128)t.d; #endif } FORCE_INLINE void rx_store_vec_f128(double* mem_addr, rx_vec_f128 a) { #if defined(NATIVE_LITTLE_ENDIAN) vec_vsx_st(a,0,(rx_vec_f128*)mem_addr); #else vec_u _a; _a.d = a; store64(mem_addr + 0, _a.u64[0]); store64(mem_addr + 1, _a.u64[1]); #endif } FORCE_INLINE rx_vec_f128 rx_swap_vec_f128(rx_vec_f128 a) { return (rx_vec_f128)vec_perm((__m128i)a,(__m128i)a,(__m128i){8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7}); } FORCE_INLINE rx_vec_f128 rx_add_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_add(a,b); } FORCE_INLINE rx_vec_f128 rx_sub_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_sub(a,b); } FORCE_INLINE rx_vec_f128 rx_mul_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_mul(a,b); } FORCE_INLINE rx_vec_f128 rx_div_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_div(a,b); } FORCE_INLINE rx_vec_f128 rx_sqrt_vec_f128(rx_vec_f128 a) { return (rx_vec_f128)vec_sqrt(a); } FORCE_INLINE rx_vec_i128 rx_set1_long_vec_i128(uint64_t a) { return (rx_vec_i128)vec_splat2sd(a); } FORCE_INLINE rx_vec_f128 rx_vec_i128_vec_f128(rx_vec_i128 a) { return (rx_vec_f128)a; } FORCE_INLINE rx_vec_f128 rx_set_vec_f128(uint64_t x1, uint64_t x0) { return (rx_vec_f128)(__m128ll){x0,x1}; } FORCE_INLINE rx_vec_f128 rx_set1_vec_f128(uint64_t x) { return (rx_vec_f128)vec_splat2sd(x); } FORCE_INLINE rx_vec_f128 rx_xor_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_xor(a,b); } FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_and(a,b); } FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return (rx_vec_f128)vec_or(a,b); } #if defined(__CRYPTO__) FORCE_INLINE __m128ll vrev(__m128i v){ #if defined(NATIVE_LITTLE_ENDIAN) return (__m128ll)vec_perm((__m128i)v,(__m128i){0},(__m128i){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}); #else return (__m128ll)vec_perm((__m128i)v,(__m128i){0},(__m128i){3,2,1,0, 7,6,5,4, 11,10,9,8, 15,14,13,12}); #endif } FORCE_INLINE rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey) { __m128ll _v = vrev(v); __m128ll _rkey = vrev(rkey); __m128ll result = vrev((__m128i)__builtin_crypto_vcipher(_v,_rkey)); return (rx_vec_i128)result; } FORCE_INLINE rx_vec_i128 rx_aesdec_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey) { __m128ll _v = vrev(v); __m128ll zero = (__m128ll){0}; __m128ll out = vrev((__m128i)__builtin_crypto_vncipher(_v,zero)); return (rx_vec_i128)vec_xor((__m128i)out,rkey); } #define HAVE_AES 1 #endif //__CRYPTO__ FORCE_INLINE int rx_vec_i128_x(rx_vec_i128 a) { vec_u _a; _a.i = a; return _a.i32[0]; } FORCE_INLINE int rx_vec_i128_y(rx_vec_i128 a) { vec_u _a; _a.i = a; return _a.i32[1]; } FORCE_INLINE int rx_vec_i128_z(rx_vec_i128 a) { vec_u _a; _a.i = a; return _a.i32[2]; } FORCE_INLINE int rx_vec_i128_w(rx_vec_i128 a) { vec_u _a; _a.i = a; return _a.i32[3]; } FORCE_INLINE rx_vec_i128 rx_set_int_vec_i128(int _I3, int _I2, int _I1, int _I0) { return (rx_vec_i128)((__m128li){_I0,_I1,_I2,_I3}); }; FORCE_INLINE rx_vec_i128 rx_xor_vec_i128(rx_vec_i128 _A, rx_vec_i128 _B) { return (rx_vec_i128)vec_xor(_A,_B); } FORCE_INLINE rx_vec_i128 rx_load_vec_i128(rx_vec_i128 const *_P) { #if defined(NATIVE_LITTLE_ENDIAN) return *_P; #else uint32_t* ptr = (uint32_t*)_P; vec_u c; c.u32[0] = load32(ptr + 0); c.u32[1] = load32(ptr + 1); c.u32[2] = load32(ptr + 2); c.u32[3] = load32(ptr + 3); return (rx_vec_i128)c.i; #endif } FORCE_INLINE void rx_store_vec_i128(rx_vec_i128 *_P, rx_vec_i128 _B) { #if defined(NATIVE_LITTLE_ENDIAN) *_P = _B; #else uint32_t* ptr = (uint32_t*)_P; vec_u B; B.i = _B; store32(ptr + 0, B.u32[0]); store32(ptr + 1, B.u32[1]); store32(ptr + 2, B.u32[2]); store32(ptr + 3, B.u32[3]); #endif } FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) { vec_u x; x.d64[0] = (double)unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 0)); x.d64[1] = (double)unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 4)); return (rx_vec_f128)x.d; } #define RANDOMX_DEFAULT_FENV #elif defined(__aarch64__) #include #include #include typedef uint8x16_t rx_vec_i128; typedef float64x2_t rx_vec_f128; inline void* rx_aligned_alloc(size_t size, size_t align) { void* p; if (posix_memalign(&p, align, size) == 0) return p; return 0; }; #define rx_aligned_free(a) free(a) inline void rx_prefetch_nta(void* ptr) { asm volatile ("prfm pldl1strm, [%0]\n" : : "r" (ptr)); } inline void rx_prefetch_t0(const void* ptr) { asm volatile ("prfm pldl1strm, [%0]\n" : : "r" (ptr)); } FORCE_INLINE rx_vec_f128 rx_load_vec_f128(const double* pd) { return vld1q_f64((const float64_t*)pd); } FORCE_INLINE void rx_store_vec_f128(double* mem_addr, rx_vec_f128 val) { vst1q_f64((float64_t*)mem_addr, val); } FORCE_INLINE rx_vec_f128 rx_swap_vec_f128(rx_vec_f128 a) { float64x2_t temp; temp = vcopyq_laneq_f64(temp, 1, a, 1); a = vcopyq_laneq_f64(a, 1, a, 0); return vcopyq_laneq_f64(a, 0, temp, 1); } FORCE_INLINE rx_vec_f128 rx_set_vec_f128(uint64_t x1, uint64_t x0) { uint64x2_t temp0 = vdupq_n_u64(x0); uint64x2_t temp1 = vdupq_n_u64(x1); return vreinterpretq_f64_u64(vcopyq_laneq_u64(temp0, 1, temp1, 0)); } FORCE_INLINE rx_vec_f128 rx_set1_vec_f128(uint64_t x) { return vreinterpretq_f64_u64(vdupq_n_u64(x)); } #define rx_add_vec_f128 vaddq_f64 #define rx_sub_vec_f128 vsubq_f64 #define rx_mul_vec_f128 vmulq_f64 #define rx_div_vec_f128 vdivq_f64 #define rx_sqrt_vec_f128 vsqrtq_f64 FORCE_INLINE rx_vec_f128 rx_xor_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return vreinterpretq_f64_u8(veorq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b))); } FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return vreinterpretq_f64_u8(vandq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b))); } FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { return vreinterpretq_f64_u8(vorrq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b))); } #ifdef __ARM_FEATURE_CRYPTO FORCE_INLINE rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 a, rx_vec_i128 key) { const uint8x16_t zero = { 0 }; return vaesmcq_u8(vaeseq_u8(a, zero)) ^ key; } FORCE_INLINE rx_vec_i128 rx_aesdec_vec_i128(rx_vec_i128 a, rx_vec_i128 key) { const uint8x16_t zero = { 0 }; return vaesimcq_u8(vaesdq_u8(a, zero)) ^ key; } #define HAVE_AES 1 #endif #define rx_xor_vec_i128 veorq_u8 FORCE_INLINE int rx_vec_i128_x(rx_vec_i128 a) { return vgetq_lane_s32(vreinterpretq_s32_u8(a), 0); } FORCE_INLINE int rx_vec_i128_y(rx_vec_i128 a) { return vgetq_lane_s32(vreinterpretq_s32_u8(a), 1); } FORCE_INLINE int rx_vec_i128_z(rx_vec_i128 a) { return vgetq_lane_s32(vreinterpretq_s32_u8(a), 2); } FORCE_INLINE int rx_vec_i128_w(rx_vec_i128 a) { return vgetq_lane_s32(vreinterpretq_s32_u8(a), 3); } FORCE_INLINE rx_vec_i128 rx_set_int_vec_i128(int _I3, int _I2, int _I1, int _I0) { int32_t data[4]; data[0] = _I0; data[1] = _I1; data[2] = _I2; data[3] = _I3; return vreinterpretq_u8_s32(vld1q_s32(data)); }; #define rx_xor_vec_i128 veorq_u8 FORCE_INLINE rx_vec_i128 rx_load_vec_i128(const rx_vec_i128* mem_addr) { return vld1q_u8((const uint8_t*)mem_addr); } FORCE_INLINE void rx_store_vec_i128(rx_vec_i128* mem_addr, rx_vec_i128 val) { vst1q_u8((uint8_t*)mem_addr, val); } FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) { double lo = unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 0)); double hi = unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 4)); rx_vec_f128 x; x = vsetq_lane_f64(lo, x, 0); x = vsetq_lane_f64(hi, x, 1); return x; } #define RANDOMX_DEFAULT_FENV #else //portable fallback #include #include #include #include typedef union { uint64_t u64[2]; uint32_t u32[4]; uint16_t u16[8]; uint8_t u8[16]; } rx_vec_i128; typedef union { struct { double lo; double hi; }; rx_vec_i128 i; } rx_vec_f128; #define rx_aligned_alloc(a, b) malloc(a) #define rx_aligned_free(a) free(a) #define rx_prefetch_nta(x) #define rx_prefetch_t0(x) FORCE_INLINE rx_vec_f128 rx_load_vec_f128(const double* pd) { rx_vec_f128 x; x.i.u64[0] = load64(pd + 0); x.i.u64[1] = load64(pd + 1); return x; } FORCE_INLINE void rx_store_vec_f128(double* mem_addr, rx_vec_f128 a) { store64(mem_addr + 0, a.i.u64[0]); store64(mem_addr + 1, a.i.u64[1]); } FORCE_INLINE rx_vec_f128 rx_swap_vec_f128(rx_vec_f128 a) { double temp = a.hi; a.hi = a.lo; a.lo = temp; return a; } FORCE_INLINE rx_vec_f128 rx_add_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.lo = a.lo + b.lo; x.hi = a.hi + b.hi; return x; } FORCE_INLINE rx_vec_f128 rx_sub_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.lo = a.lo - b.lo; x.hi = a.hi - b.hi; return x; } FORCE_INLINE rx_vec_f128 rx_mul_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.lo = a.lo * b.lo; x.hi = a.hi * b.hi; return x; } FORCE_INLINE rx_vec_f128 rx_div_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.lo = a.lo / b.lo; x.hi = a.hi / b.hi; return x; } FORCE_INLINE rx_vec_f128 rx_sqrt_vec_f128(rx_vec_f128 a) { rx_vec_f128 x; x.lo = rx_sqrt(a.lo); x.hi = rx_sqrt(a.hi); return x; } FORCE_INLINE rx_vec_i128 rx_set1_long_vec_i128(uint64_t a) { rx_vec_i128 x; x.u64[0] = a; x.u64[1] = a; return x; } FORCE_INLINE rx_vec_f128 rx_vec_i128_vec_f128(rx_vec_i128 a) { rx_vec_f128 x; x.i = a; return x; } FORCE_INLINE rx_vec_f128 rx_set_vec_f128(uint64_t x1, uint64_t x0) { rx_vec_f128 v; v.i.u64[0] = x0; v.i.u64[1] = x1; return v; } FORCE_INLINE rx_vec_f128 rx_set1_vec_f128(uint64_t x) { rx_vec_f128 v; v.i.u64[0] = x; v.i.u64[1] = x; return v; } FORCE_INLINE rx_vec_f128 rx_xor_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.i.u64[0] = a.i.u64[0] ^ b.i.u64[0]; x.i.u64[1] = a.i.u64[1] ^ b.i.u64[1]; return x; } FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.i.u64[0] = a.i.u64[0] & b.i.u64[0]; x.i.u64[1] = a.i.u64[1] & b.i.u64[1]; return x; } FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) { rx_vec_f128 x; x.i.u64[0] = a.i.u64[0] | b.i.u64[0]; x.i.u64[1] = a.i.u64[1] | b.i.u64[1]; return x; } FORCE_INLINE int rx_vec_i128_x(rx_vec_i128 a) { return a.u32[0]; } FORCE_INLINE int rx_vec_i128_y(rx_vec_i128 a) { return a.u32[1]; } FORCE_INLINE int rx_vec_i128_z(rx_vec_i128 a) { return a.u32[2]; } FORCE_INLINE int rx_vec_i128_w(rx_vec_i128 a) { return a.u32[3]; } FORCE_INLINE rx_vec_i128 rx_set_int_vec_i128(int _I3, int _I2, int _I1, int _I0) { rx_vec_i128 v; v.u32[0] = _I0; v.u32[1] = _I1; v.u32[2] = _I2; v.u32[3] = _I3; return v; }; FORCE_INLINE rx_vec_i128 rx_xor_vec_i128(rx_vec_i128 _A, rx_vec_i128 _B) { rx_vec_i128 c; c.u32[0] = _A.u32[0] ^ _B.u32[0]; c.u32[1] = _A.u32[1] ^ _B.u32[1]; c.u32[2] = _A.u32[2] ^ _B.u32[2]; c.u32[3] = _A.u32[3] ^ _B.u32[3]; return c; } FORCE_INLINE rx_vec_i128 rx_load_vec_i128(rx_vec_i128 const*_P) { #if defined(NATIVE_LITTLE_ENDIAN) return *_P; #else uint32_t* ptr = (uint32_t*)_P; rx_vec_i128 c; c.u32[0] = load32(ptr + 0); c.u32[1] = load32(ptr + 1); c.u32[2] = load32(ptr + 2); c.u32[3] = load32(ptr + 3); return c; #endif } FORCE_INLINE void rx_store_vec_i128(rx_vec_i128 *_P, rx_vec_i128 _B) { #if defined(NATIVE_LITTLE_ENDIAN) *_P = _B; #else uint32_t* ptr = (uint32_t*)_P; store32(ptr + 0, _B.u32[0]); store32(ptr + 1, _B.u32[1]); store32(ptr + 2, _B.u32[2]); store32(ptr + 3, _B.u32[3]); #endif } FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) { rx_vec_f128 x; x.lo = (double)unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 0)); x.hi = (double)unsigned32ToSigned2sCompl(load32((uint8_t*)addr + 4)); return x; } #define RANDOMX_DEFAULT_FENV #endif #ifndef HAVE_AES static const char* platformError = "Platform doesn't support hardware AES"; #include FORCE_INLINE rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey) { throw std::runtime_error(platformError); } FORCE_INLINE rx_vec_i128 rx_aesdec_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey) { throw std::runtime_error(platformError); } #define HAVE_AES 0 #endif #ifdef RANDOMX_DEFAULT_FENV void rx_reset_float_state(); void rx_set_rounding_mode(uint32_t mode); uint32_t rx_get_rounding_mode(); #endif double loadDoublePortable(const void* addr); uint64_t mulh(uint64_t, uint64_t); int64_t smulh(int64_t, int64_t); uint64_t rotl(uint64_t, unsigned int); uint64_t rotr(uint64_t, unsigned int); RandomX-1.1.10/src/jit_compiler.hpp000066400000000000000000000034761414227164600171430ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #if defined(_M_X64) || defined(__x86_64__) #include "jit_compiler_x86.hpp" #elif defined(__aarch64__) #include "jit_compiler_a64.hpp" #else #include "jit_compiler_fallback.hpp" #endif #if defined(__OpenBSD__) || defined(__NetBSD__) || (defined(__APPLE__) && defined(__aarch64__)) #define RANDOMX_FORCE_SECURE #endif RandomX-1.1.10/src/jit_compiler_a64.cpp000066400000000000000000000772431414227164600176130ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador Copyright (c) 2019, SChernykh All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "jit_compiler_a64.hpp" #include "superscalar.hpp" #include "program.hpp" #include "reciprocal.h" #include "virtual_memory.hpp" namespace ARMV8A { constexpr uint32_t B = 0x14000000; constexpr uint32_t EOR = 0xCA000000; constexpr uint32_t EOR32 = 0x4A000000; constexpr uint32_t ADD = 0x8B000000; constexpr uint32_t SUB = 0xCB000000; constexpr uint32_t MUL = 0x9B007C00; constexpr uint32_t UMULH = 0x9BC07C00; constexpr uint32_t SMULH = 0x9B407C00; constexpr uint32_t MOVZ = 0xD2800000; constexpr uint32_t MOVN = 0x92800000; constexpr uint32_t MOVK = 0xF2800000; constexpr uint32_t ADD_IMM_LO = 0x91000000; constexpr uint32_t ADD_IMM_HI = 0x91400000; constexpr uint32_t LDR_LITERAL = 0x58000000; constexpr uint32_t ROR = 0x9AC02C00; constexpr uint32_t ROR_IMM = 0x93C00000; constexpr uint32_t MOV_REG = 0xAA0003E0; constexpr uint32_t MOV_VREG_EL = 0x6E080400; constexpr uint32_t FADD = 0x4E60D400; constexpr uint32_t FSUB = 0x4EE0D400; constexpr uint32_t FEOR = 0x6E201C00; constexpr uint32_t FMUL = 0x6E60DC00; constexpr uint32_t FDIV = 0x6E60FC00; constexpr uint32_t FSQRT = 0x6EE1F800; } namespace randomx { static const size_t CodeSize = ((uint8_t*)randomx_init_dataset_aarch64_end) - ((uint8_t*)randomx_program_aarch64); static const size_t MainLoopBegin = ((uint8_t*)randomx_program_aarch64_main_loop) - ((uint8_t*)randomx_program_aarch64); static const size_t PrologueSize = ((uint8_t*)randomx_program_aarch64_vm_instructions) - ((uint8_t*)randomx_program_aarch64); static const size_t ImulRcpLiteralsEnd = ((uint8_t*)randomx_program_aarch64_imul_rcp_literals_end) - ((uint8_t*)randomx_program_aarch64); static const size_t CalcDatasetItemSize = // Prologue ((uint8_t*)randomx_calc_dataset_item_aarch64_prefetch - (uint8_t*)randomx_calc_dataset_item_aarch64) + // Main loop RANDOMX_CACHE_ACCESSES * ( // Main loop prologue ((uint8_t*)randomx_calc_dataset_item_aarch64_mix - ((uint8_t*)randomx_calc_dataset_item_aarch64_prefetch)) + 4 + // Inner main loop (instructions) ((RANDOMX_SUPERSCALAR_LATENCY * 3) + 2) * 16 + // Main loop epilogue ((uint8_t*)randomx_calc_dataset_item_aarch64_store_result - (uint8_t*)randomx_calc_dataset_item_aarch64_mix) + 4 ) + // Epilogue ((uint8_t*)randomx_calc_dataset_item_aarch64_end - (uint8_t*)randomx_calc_dataset_item_aarch64_store_result); constexpr uint32_t IntRegMap[8] = { 4, 5, 6, 7, 12, 13, 14, 15 }; template static constexpr size_t Log2(T value) { return (value > 1) ? (Log2(value / 2) + 1) : 0; } JitCompilerA64::JitCompilerA64() : code((uint8_t*) allocMemoryPages(CodeSize + CalcDatasetItemSize)) , literalPos(ImulRcpLiteralsEnd) , num32bitLiterals(0) { memset(reg_changed_offset, 0, sizeof(reg_changed_offset)); memcpy(code, (void*) randomx_program_aarch64, CodeSize); #ifdef __GNUC__ __builtin___clear_cache(reinterpret_cast(code), reinterpret_cast(code + CodeSize)); #endif } JitCompilerA64::~JitCompilerA64() { freePagedMemory(code, CodeSize + CalcDatasetItemSize); } void JitCompilerA64::enableWriting() { setPagesRW(code, CodeSize + CalcDatasetItemSize); } void JitCompilerA64::enableExecution() { setPagesRX(code, CodeSize + CalcDatasetItemSize); } void JitCompilerA64::enableAll() { setPagesRWX(code, CodeSize + CalcDatasetItemSize); } void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& config) { uint32_t codePos = MainLoopBegin + 4; // and w16, w10, ScratchpadL3Mask64 emit32(0x121A0000 | 16 | (10 << 5) | ((Log2(RANDOMX_SCRATCHPAD_L3) - 7) << 10), code, codePos); // and w17, w18, ScratchpadL3Mask64 emit32(0x121A0000 | 17 | (18 << 5) | ((Log2(RANDOMX_SCRATCHPAD_L3) - 7) << 10), code, codePos); codePos = PrologueSize; literalPos = ImulRcpLiteralsEnd; num32bitLiterals = 0; for (uint32_t i = 0; i < RegistersCount; ++i) reg_changed_offset[i] = codePos; for (uint32_t i = 0; i < program.getSize(); ++i) { Instruction& instr = program(i); instr.src %= RegistersCount; instr.dst %= RegistersCount; (this->*engine[instr.opcode])(instr, codePos); } // Update spMix2 // eor w18, config.readReg2, config.readReg3 emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos); // Jump back to the main loop const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end) - ((uint8_t*)randomx_program_aarch64)) - codePos; emit32(ARMV8A::B | (offset / 4), code, codePos); // and w18, w18, CacheLineAlignMask codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask1) - ((uint8_t*)randomx_program_aarch64)); emit32(0x121A0000 | 18 | (18 << 5) | ((Log2(RANDOMX_DATASET_BASE_SIZE) - 7) << 10), code, codePos); // and w10, w10, CacheLineAlignMask codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask2) - ((uint8_t*)randomx_program_aarch64)); emit32(0x121A0000 | 10 | (10 << 5) | ((Log2(RANDOMX_DATASET_BASE_SIZE) - 7) << 10), code, codePos); // Update spMix1 // eor x10, config.readReg0, config.readReg1 codePos = ((uint8_t*)randomx_program_aarch64_update_spMix1) - ((uint8_t*)randomx_program_aarch64); emit32(ARMV8A::EOR | 10 | (IntRegMap[config.readReg0] << 5) | (IntRegMap[config.readReg1] << 16), code, codePos); #ifdef __GNUC__ __builtin___clear_cache(reinterpret_cast(code + MainLoopBegin), reinterpret_cast(code + codePos)); #endif } void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration& config, uint32_t datasetOffset) { uint32_t codePos = MainLoopBegin + 4; // and w16, w10, ScratchpadL3Mask64 emit32(0x121A0000 | 16 | (10 << 5) | ((Log2(RANDOMX_SCRATCHPAD_L3) - 7) << 10), code, codePos); // and w17, w18, ScratchpadL3Mask64 emit32(0x121A0000 | 17 | (18 << 5) | ((Log2(RANDOMX_SCRATCHPAD_L3) - 7) << 10), code, codePos); codePos = PrologueSize; literalPos = ImulRcpLiteralsEnd; num32bitLiterals = 0; for (uint32_t i = 0; i < RegistersCount; ++i) reg_changed_offset[i] = codePos; for (uint32_t i = 0; i < program.getSize(); ++i) { Instruction& instr = program(i); instr.src %= RegistersCount; instr.dst %= RegistersCount; (this->*engine[instr.opcode])(instr, codePos); } // Update spMix2 // eor w18, config.readReg2, config.readReg3 emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos); // Jump back to the main loop const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end_light) - ((uint8_t*)randomx_program_aarch64)) - codePos; emit32(ARMV8A::B | (offset / 4), code, codePos); // and w2, w9, CacheLineAlignMask codePos = (((uint8_t*)randomx_program_aarch64_light_cacheline_align_mask) - ((uint8_t*)randomx_program_aarch64)); emit32(0x121A0000 | 2 | (9 << 5) | ((Log2(RANDOMX_DATASET_BASE_SIZE) - 7) << 10), code, codePos); // Update spMix1 // eor x10, config.readReg0, config.readReg1 codePos = ((uint8_t*)randomx_program_aarch64_update_spMix1) - ((uint8_t*)randomx_program_aarch64); emit32(ARMV8A::EOR | 10 | (IntRegMap[config.readReg0] << 5) | (IntRegMap[config.readReg1] << 16), code, codePos); // Apply dataset offset codePos = ((uint8_t*)randomx_program_aarch64_light_dataset_offset) - ((uint8_t*)randomx_program_aarch64); datasetOffset /= CacheLineSize; const uint32_t imm_lo = datasetOffset & ((1 << 12) - 1); const uint32_t imm_hi = datasetOffset >> 12; emit32(ARMV8A::ADD_IMM_LO | 2 | (2 << 5) | (imm_lo << 10), code, codePos); emit32(ARMV8A::ADD_IMM_HI | 2 | (2 << 5) | (imm_hi << 10), code, codePos); #ifdef __GNUC__ __builtin___clear_cache(reinterpret_cast(code + MainLoopBegin), reinterpret_cast(code + codePos)); #endif } template void JitCompilerA64::generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector &reciprocalCache) { uint32_t codePos = CodeSize; uint8_t* p1 = (uint8_t*)randomx_calc_dataset_item_aarch64; uint8_t* p2 = (uint8_t*)randomx_calc_dataset_item_aarch64_prefetch; memcpy(code + codePos, p1, p2 - p1); codePos += p2 - p1; num32bitLiterals = 64; constexpr uint32_t tmp_reg = 12; for (size_t i = 0; i < N; ++i) { // and x11, x10, CacheSize / CacheLineSize - 1 emit32(0x92400000 | 11 | (10 << 5) | ((Log2(CacheSize / CacheLineSize) - 1) << 10), code, codePos); p1 = ((uint8_t*)randomx_calc_dataset_item_aarch64_prefetch) + 4; p2 = (uint8_t*)randomx_calc_dataset_item_aarch64_mix; memcpy(code + codePos, p1, p2 - p1); codePos += p2 - p1; SuperscalarProgram& prog = programs[i]; const size_t progSize = prog.getSize(); uint32_t jmp_pos = codePos; codePos += 4; // Fill in literal pool for (size_t j = 0; j < progSize; ++j) { const Instruction& instr = prog(j); if (static_cast(instr.opcode) == randomx::SuperscalarInstructionType::IMUL_RCP) emit64(reciprocalCache[instr.getImm32()], code, codePos); } // Jump over literal pool uint32_t literal_pos = jmp_pos; emit32(ARMV8A::B | ((codePos - jmp_pos) / 4), code, literal_pos); for (size_t j = 0; j < progSize; ++j) { const Instruction& instr = prog(j); const uint32_t src = instr.src; const uint32_t dst = instr.dst; switch (static_cast(instr.opcode)) { case randomx::SuperscalarInstructionType::ISUB_R: emit32(ARMV8A::SUB | dst | (dst << 5) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IXOR_R: emit32(ARMV8A::EOR | dst | (dst << 5) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IADD_RS: emit32(ARMV8A::ADD | dst | (dst << 5) | (instr.getModShift() << 10) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IMUL_R: emit32(ARMV8A::MUL | dst | (dst << 5) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IROR_C: emit32(ARMV8A::ROR_IMM | dst | (dst << 5) | ((instr.getImm32() & 63) << 10) | (dst << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IADD_C7: case randomx::SuperscalarInstructionType::IADD_C8: case randomx::SuperscalarInstructionType::IADD_C9: emitAddImmediate(dst, dst, instr.getImm32(), code, codePos); break; case randomx::SuperscalarInstructionType::IXOR_C7: case randomx::SuperscalarInstructionType::IXOR_C8: case randomx::SuperscalarInstructionType::IXOR_C9: emitMovImmediate(tmp_reg, instr.getImm32(), code, codePos); emit32(ARMV8A::EOR | dst | (dst << 5) | (tmp_reg << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IMULH_R: emit32(ARMV8A::UMULH | dst | (dst << 5) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::ISMULH_R: emit32(ARMV8A::SMULH | dst | (dst << 5) | (src << 16), code, codePos); break; case randomx::SuperscalarInstructionType::IMUL_RCP: { int32_t offset = (literal_pos - codePos) / 4; offset &= (1 << 19) - 1; literal_pos += 8; // ldr tmp_reg, reciprocal emit32(ARMV8A::LDR_LITERAL | tmp_reg | (offset << 5), code, codePos); // mul dst, dst, tmp_reg emit32(ARMV8A::MUL | dst | (dst << 5) | (tmp_reg << 16), code, codePos); } break; default: break; } } p1 = (uint8_t*)randomx_calc_dataset_item_aarch64_mix; p2 = (uint8_t*)randomx_calc_dataset_item_aarch64_store_result; memcpy(code + codePos, p1, p2 - p1); codePos += p2 - p1; // Update registerValue emit32(ARMV8A::MOV_REG | 10 | (prog.getAddressRegister() << 16), code, codePos); } p1 = (uint8_t*)randomx_calc_dataset_item_aarch64_store_result; p2 = (uint8_t*)randomx_calc_dataset_item_aarch64_end; memcpy(code + codePos, p1, p2 - p1); codePos += p2 - p1; #ifdef __GNUC__ __builtin___clear_cache(reinterpret_cast(code + CodeSize), reinterpret_cast(code + codePos)); #endif } template void JitCompilerA64::generateSuperscalarHash(SuperscalarProgram(&programs)[RANDOMX_CACHE_ACCESSES], std::vector &reciprocalCache); DatasetInitFunc* JitCompilerA64::getDatasetInitFunc() { return (DatasetInitFunc*)(code + (((uint8_t*)randomx_init_dataset_aarch64) - ((uint8_t*)randomx_program_aarch64))); } size_t JitCompilerA64::getCodeSize() { return CodeSize; } void JitCompilerA64::emitMovImmediate(uint32_t dst, uint32_t imm, uint8_t* code, uint32_t& codePos) { uint32_t k = codePos; if (imm < (1 << 16)) { // movz tmp_reg, imm32 (16 low bits) emit32(ARMV8A::MOVZ | dst | (imm << 5), code, k); } else { if (num32bitLiterals < 64) { if (static_cast(imm) < 0) { // smov dst, vN.s[M] emit32(0x4E042C00 | dst | ((num32bitLiterals / 4) << 5) | ((num32bitLiterals % 4) << 19), code, k); } else { // umov dst, vN.s[M] emit32(0x0E043C00 | dst | ((num32bitLiterals / 4) << 5) | ((num32bitLiterals % 4) << 19), code, k); } ((uint32_t*)(code + ImulRcpLiteralsEnd))[num32bitLiterals] = imm; ++num32bitLiterals; } else { if (static_cast(imm) < 0) { // movn tmp_reg, ~imm32 (16 high bits) emit32(ARMV8A::MOVN | dst | (1 << 21) | ((~imm >> 16) << 5), code, k); } else { // movz tmp_reg, imm32 (16 high bits) emit32(ARMV8A::MOVZ | dst | (1 << 21) | ((imm >> 16) << 5), code, k); } // movk tmp_reg, imm32 (16 low bits) emit32(ARMV8A::MOVK | dst | ((imm & 0xFFFF) << 5), code, k); } } codePos = k; } void JitCompilerA64::emitAddImmediate(uint32_t dst, uint32_t src, uint32_t imm, uint8_t* code, uint32_t& codePos) { uint32_t k = codePos; if (imm < (1 << 24)) { const uint32_t imm_lo = imm & ((1 << 12) - 1); const uint32_t imm_hi = imm >> 12; if (imm_lo && imm_hi) { emit32(ARMV8A::ADD_IMM_LO | dst | (src << 5) | (imm_lo << 10), code, k); emit32(ARMV8A::ADD_IMM_HI | dst | (dst << 5) | (imm_hi << 10), code, k); } else if (imm_lo) { emit32(ARMV8A::ADD_IMM_LO | dst | (src << 5) | (imm_lo << 10), code, k); } else { emit32(ARMV8A::ADD_IMM_HI | dst | (src << 5) | (imm_hi << 10), code, k); } } else { constexpr uint32_t tmp_reg = 18; emitMovImmediate(tmp_reg, imm, code, k); // add dst, src, tmp_reg emit32(ARMV8A::ADD | dst | (src << 5) | (tmp_reg << 16), code, k); } codePos = k; } template void JitCompilerA64::emitMemLoad(uint32_t dst, uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos) { uint32_t k = codePos; uint32_t imm = instr.getImm32(); if (src != dst) { imm &= instr.getModMem() ? (RANDOMX_SCRATCHPAD_L1 - 1) : (RANDOMX_SCRATCHPAD_L2 - 1); emitAddImmediate(tmp_reg, src, imm, code, k); constexpr uint32_t t = 0x927d0000 | tmp_reg | (tmp_reg << 5); constexpr uint32_t andInstrL1 = t | ((Log2(RANDOMX_SCRATCHPAD_L1) - 4) << 10); constexpr uint32_t andInstrL2 = t | ((Log2(RANDOMX_SCRATCHPAD_L2) - 4) << 10); emit32(instr.getModMem() ? andInstrL1 : andInstrL2, code, k); // ldr tmp_reg, [x2, tmp_reg] emit32(0xf8606840 | tmp_reg | (tmp_reg << 16), code, k); } else { imm = (imm & ScratchpadL3Mask) >> 3; emitMovImmediate(tmp_reg, imm, code, k); // ldr tmp_reg, [x2, tmp_reg, lsl 3] emit32(0xf8607840 | tmp_reg | (tmp_reg << 16), code, k); } codePos = k; } template void JitCompilerA64::emitMemLoadFP(uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos) { uint32_t k = codePos; uint32_t imm = instr.getImm32(); constexpr uint32_t tmp_reg = 18; imm &= instr.getModMem() ? (RANDOMX_SCRATCHPAD_L1 - 1) : (RANDOMX_SCRATCHPAD_L2 - 1); emitAddImmediate(tmp_reg, src, imm, code, k); constexpr uint32_t t = 0x927d0000 | tmp_reg | (tmp_reg << 5); constexpr uint32_t andInstrL1 = t | ((Log2(RANDOMX_SCRATCHPAD_L1) - 4) << 10); constexpr uint32_t andInstrL2 = t | ((Log2(RANDOMX_SCRATCHPAD_L2) - 4) << 10); emit32(instr.getModMem() ? andInstrL1 : andInstrL2, code, k); // add tmp_reg, x2, tmp_reg emit32(ARMV8A::ADD | tmp_reg | (2 << 5) | (tmp_reg << 16), code, k); // ldpsw tmp_reg, tmp_reg + 1, [tmp_reg] emit32(0x69400000 | tmp_reg | (tmp_reg << 5) | ((tmp_reg + 1) << 10), code, k); // ins tmp_reg_fp.d[0], tmp_reg emit32(0x4E081C00 | tmp_reg_fp | (tmp_reg << 5), code, k); // ins tmp_reg_fp.d[1], tmp_reg + 1 emit32(0x4E181C00 | tmp_reg_fp | ((tmp_reg + 1) << 5), code, k); // scvtf tmp_reg_fp.2d, tmp_reg_fp.2d emit32(0x4E61D800 | tmp_reg_fp | (tmp_reg_fp << 5), code, k); codePos = k; } void JitCompilerA64::h_IADD_RS(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; const uint32_t shift = instr.getModShift(); // add dst, src << shift emit32(ARMV8A::ADD | dst | (dst << 5) | (shift << 10) | (src << 16), code, k); if (instr.dst == RegisterNeedsDisplacement) emitAddImmediate(dst, dst, instr.getImm32(), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IADD_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // add dst, dst, tmp_reg emit32(ARMV8A::ADD | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_ISUB_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src != dst) { // sub dst, dst, src emit32(ARMV8A::SUB | dst | (dst << 5) | (src << 16), code, k); } else { emitAddImmediate(dst, dst, -instr.getImm32(), code, k); } reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_ISUB_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // sub dst, dst, tmp_reg emit32(ARMV8A::SUB | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IMUL_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src == dst) { src = 18; emitMovImmediate(src, instr.getImm32(), code, k); } // mul dst, dst, src emit32(ARMV8A::MUL | dst | (dst << 5) | (src << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IMUL_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // sub dst, dst, tmp_reg emit32(ARMV8A::MUL | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IMULH_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; // umulh dst, dst, src emit32(ARMV8A::UMULH | dst | (dst << 5) | (src << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IMULH_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // umulh dst, dst, tmp_reg emit32(ARMV8A::UMULH | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_ISMULH_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; // smulh dst, dst, src emit32(ARMV8A::SMULH | dst | (dst << 5) | (src << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_ISMULH_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // smulh dst, dst, tmp_reg emit32(ARMV8A::SMULH | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IMUL_RCP(Instruction& instr, uint32_t& codePos) { const uint64_t divisor = instr.getImm32(); if (isZeroOrPowerOf2(divisor)) return; uint32_t k = codePos; constexpr uint32_t tmp_reg = 18; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint64_t N = 1ULL << 63; const uint64_t q = N / divisor; const uint64_t r = N % divisor; #ifdef __GNUC__ const uint64_t shift = 64 - __builtin_clzll(divisor); #else uint64_t shift = 32; for (uint64_t k = 1U << 31; (k & divisor) == 0; k >>= 1) --shift; #endif const uint32_t literal_id = (ImulRcpLiteralsEnd - literalPos) / sizeof(uint64_t); literalPos -= sizeof(uint64_t); *(uint64_t*)(code + literalPos) = (q << shift) + ((r << shift) / divisor); if (literal_id < 13) { static constexpr uint32_t literal_regs[13] = { 30 << 16, 29 << 16, 28 << 16, 27 << 16, 26 << 16, 25 << 16, 24 << 16, 23 << 16, 22 << 16, 21 << 16, 20 << 16, 11 << 16, 0 }; // mul dst, dst, literal_reg emit32(ARMV8A::MUL | dst | (dst << 5) | literal_regs[literal_id], code, k); } else { // ldr tmp_reg, reciprocal const uint32_t offset = (literalPos - k) / 4; emit32(ARMV8A::LDR_LITERAL | tmp_reg | (offset << 5), code, k); // mul dst, dst, tmp_reg emit32(ARMV8A::MUL | dst | (dst << 5) | (tmp_reg << 16), code, k); } reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_INEG_R(Instruction& instr, uint32_t& codePos) { const uint32_t dst = IntRegMap[instr.dst]; // sub dst, xzr, dst emit32(ARMV8A::SUB | dst | (31 << 5) | (dst << 16), code, codePos); reg_changed_offset[instr.dst] = codePos; } void JitCompilerA64::h_IXOR_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src == dst) { src = 18; emitMovImmediate(src, instr.getImm32(), code, k); } // eor dst, dst, src emit32(ARMV8A::EOR | dst | (dst << 5) | (src << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IXOR_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; emitMemLoad(dst, src, instr, code, k); // eor dst, dst, tmp_reg emit32(ARMV8A::EOR | dst | (dst << 5) | (tmp_reg << 16), code, k); reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_IROR_R(Instruction& instr, uint32_t& codePos) { const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src != dst) { // ror dst, dst, src emit32(ARMV8A::ROR | dst | (dst << 5) | (src << 16), code, codePos); } else { // ror dst, dst, imm emit32(ARMV8A::ROR_IMM | dst | (dst << 5) | ((instr.getImm32() & 63) << 10) | (dst << 16), code, codePos); } reg_changed_offset[instr.dst] = codePos; } void JitCompilerA64::h_IROL_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src != dst) { constexpr uint32_t tmp_reg = 18; // sub tmp_reg, xzr, src emit32(ARMV8A::SUB | tmp_reg | (31 << 5) | (src << 16), code, k); // ror dst, dst, tmp_reg emit32(ARMV8A::ROR | dst | (dst << 5) | (tmp_reg << 16), code, k); } else { // ror dst, dst, imm emit32(ARMV8A::ROR_IMM | dst | (dst << 5) | ((-instr.getImm32() & 63) << 10) | (dst << 16), code, k); } reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_ISWAP_R(Instruction& instr, uint32_t& codePos) { const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; if (src == dst) return; uint32_t k = codePos; constexpr uint32_t tmp_reg = 18; emit32(ARMV8A::MOV_REG | tmp_reg | (dst << 16), code, k); emit32(ARMV8A::MOV_REG | dst | (src << 16), code, k); emit32(ARMV8A::MOV_REG | src | (tmp_reg << 16), code, k); reg_changed_offset[instr.src] = k; reg_changed_offset[instr.dst] = k; codePos = k; } void JitCompilerA64::h_FSWAP_R(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t dst = instr.dst + 16; constexpr uint32_t tmp_reg_fp = 28; constexpr uint32_t src_index1 = 1 << 14; constexpr uint32_t dst_index1 = 1 << 20; emit32(ARMV8A::MOV_VREG_EL | tmp_reg_fp | (dst << 5) | src_index1, code, k); emit32(ARMV8A::MOV_VREG_EL | dst | (dst << 5) | dst_index1, code, k); emit32(ARMV8A::MOV_VREG_EL | dst | (tmp_reg_fp << 5), code, k); codePos = k; } void JitCompilerA64::h_FADD_R(Instruction& instr, uint32_t& codePos) { const uint32_t src = (instr.src % 4) + 24; const uint32_t dst = (instr.dst % 4) + 16; emit32(ARMV8A::FADD | dst | (dst << 5) | (src << 16), code, codePos); } void JitCompilerA64::h_FADD_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = (instr.dst % 4) + 16; constexpr uint32_t tmp_reg_fp = 28; emitMemLoadFP(src, instr, code, k); emit32(ARMV8A::FADD | dst | (dst << 5) | (tmp_reg_fp << 16), code, k); codePos = k; } void JitCompilerA64::h_FSUB_R(Instruction& instr, uint32_t& codePos) { const uint32_t src = (instr.src % 4) + 24; const uint32_t dst = (instr.dst % 4) + 16; emit32(ARMV8A::FSUB | dst | (dst << 5) | (src << 16), code, codePos); } void JitCompilerA64::h_FSUB_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = (instr.dst % 4) + 16; constexpr uint32_t tmp_reg_fp = 28; emitMemLoadFP(src, instr, code, k); emit32(ARMV8A::FSUB | dst | (dst << 5) | (tmp_reg_fp << 16), code, k); codePos = k; } void JitCompilerA64::h_FSCAL_R(Instruction& instr, uint32_t& codePos) { const uint32_t dst = (instr.dst % 4) + 16; emit32(ARMV8A::FEOR | dst | (dst << 5) | (31 << 16), code, codePos); } void JitCompilerA64::h_FMUL_R(Instruction& instr, uint32_t& codePos) { const uint32_t src = (instr.src % 4) + 24; const uint32_t dst = (instr.dst % 4) + 20; emit32(ARMV8A::FMUL | dst | (dst << 5) | (src << 16), code, codePos); } void JitCompilerA64::h_FDIV_M(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = (instr.dst % 4) + 20; constexpr uint32_t tmp_reg_fp = 28; emitMemLoadFP(src, instr, code, k); // and tmp_reg_fp, tmp_reg_fp, and_mask_reg emit32(0x4E201C00 | tmp_reg_fp | (tmp_reg_fp << 5) | (29 << 16), code, k); // orr tmp_reg_fp, tmp_reg_fp, or_mask_reg emit32(0x4EA01C00 | tmp_reg_fp | (tmp_reg_fp << 5) | (30 << 16), code, k); emit32(ARMV8A::FDIV | dst | (dst << 5) | (tmp_reg_fp << 16), code, k); codePos = k; } void JitCompilerA64::h_FSQRT_R(Instruction& instr, uint32_t& codePos) { const uint32_t dst = (instr.dst % 4) + 20; emit32(ARMV8A::FSQRT | dst | (dst << 5), code, codePos); } void JitCompilerA64::h_CBRANCH(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t dst = IntRegMap[instr.dst]; const uint32_t modCond = instr.getModCond(); const uint32_t shift = modCond + ConditionOffset; const uint32_t imm = (instr.getImm32() | (1U << shift)) & ~(1U << (shift - 1)); emitAddImmediate(dst, dst, imm, code, k); // tst dst, mask static_assert((ConditionMask == 0xFF) && (ConditionOffset == 8), "Update tst encoding for different mask and offset"); emit32((0xF2781C1F - (modCond << 16)) | (dst << 5), code, k); int32_t offset = reg_changed_offset[instr.dst]; offset = ((offset - k) >> 2) & ((1 << 19) - 1); // beq target emit32(0x54000000 | (offset << 5), code, k); for (uint32_t i = 0; i < RegistersCount; ++i) reg_changed_offset[i] = k; codePos = k; } void JitCompilerA64::h_CFROUND(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; constexpr uint32_t tmp_reg = 18; constexpr uint32_t fpcr_tmp_reg = 8; // ror tmp_reg, src, imm emit32(ARMV8A::ROR_IMM | tmp_reg | (src << 5) | ((instr.getImm32() & 63) << 10) | (src << 16), code, k); // bfi fpcr_tmp_reg, tmp_reg, 40, 2 emit32(0xB3580400 | fpcr_tmp_reg | (tmp_reg << 5), code, k); // rbit tmp_reg, fpcr_tmp_reg emit32(0xDAC00000 | tmp_reg | (fpcr_tmp_reg << 5), code, k); // msr fpcr, tmp_reg emit32(0xD51B4400 | tmp_reg, code, k); codePos = k; } void JitCompilerA64::h_ISTORE(Instruction& instr, uint32_t& codePos) { uint32_t k = codePos; const uint32_t src = IntRegMap[instr.src]; const uint32_t dst = IntRegMap[instr.dst]; constexpr uint32_t tmp_reg = 18; uint32_t imm = instr.getImm32(); if (instr.getModCond() < StoreL3Condition) imm &= instr.getModMem() ? (RANDOMX_SCRATCHPAD_L1 - 1) : (RANDOMX_SCRATCHPAD_L2 - 1); else imm &= RANDOMX_SCRATCHPAD_L3 - 1; emitAddImmediate(tmp_reg, dst, imm, code, k); constexpr uint32_t t = 0x927d0000 | tmp_reg | (tmp_reg << 5); constexpr uint32_t andInstrL1 = t | ((Log2(RANDOMX_SCRATCHPAD_L1) - 4) << 10); constexpr uint32_t andInstrL2 = t | ((Log2(RANDOMX_SCRATCHPAD_L2) - 4) << 10); constexpr uint32_t andInstrL3 = t | ((Log2(RANDOMX_SCRATCHPAD_L3) - 4) << 10); emit32((instr.getModCond() < StoreL3Condition) ? (instr.getModMem() ? andInstrL1 : andInstrL2) : andInstrL3, code, k); // str src, [x2, tmp_reg] emit32(0xF8206840 | src | (tmp_reg << 16), code, k); codePos = k; } void JitCompilerA64::h_NOP(Instruction& instr, uint32_t& codePos) { } #include "instruction_weights.hpp" #define INST_HANDLE(x) REPN(&JitCompilerA64::h_##x, WT(x)) InstructionGeneratorA64 JitCompilerA64::engine[256] = { INST_HANDLE(IADD_RS) INST_HANDLE(IADD_M) INST_HANDLE(ISUB_R) INST_HANDLE(ISUB_M) INST_HANDLE(IMUL_R) INST_HANDLE(IMUL_M) INST_HANDLE(IMULH_R) INST_HANDLE(IMULH_M) INST_HANDLE(ISMULH_R) INST_HANDLE(ISMULH_M) INST_HANDLE(IMUL_RCP) INST_HANDLE(INEG_R) INST_HANDLE(IXOR_R) INST_HANDLE(IXOR_M) INST_HANDLE(IROR_R) INST_HANDLE(IROL_R) INST_HANDLE(ISWAP_R) INST_HANDLE(FSWAP_R) INST_HANDLE(FADD_R) INST_HANDLE(FADD_M) INST_HANDLE(FSUB_R) INST_HANDLE(FSUB_M) INST_HANDLE(FSCAL_R) INST_HANDLE(FMUL_R) INST_HANDLE(FDIV_M) INST_HANDLE(FSQRT_R) INST_HANDLE(CBRANCH) INST_HANDLE(CFROUND) INST_HANDLE(ISTORE) INST_HANDLE(NOP) }; } RandomX-1.1.10/src/jit_compiler_a64.hpp000066400000000000000000000111341414227164600176030ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador Copyright (c) 2019, SChernykh All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "common.hpp" #include "jit_compiler_a64_static.hpp" namespace randomx { class Program; struct ProgramConfiguration; class SuperscalarProgram; class Instruction; typedef void(JitCompilerA64::*InstructionGeneratorA64)(Instruction&, uint32_t&); class JitCompilerA64 { public: JitCompilerA64(); ~JitCompilerA64(); void generateProgram(Program&, ProgramConfiguration&); void generateProgramLight(Program&, ProgramConfiguration&, uint32_t); template void generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector &); void generateDatasetInitCode() {} ProgramFunc* getProgramFunc() { return reinterpret_cast(code); } DatasetInitFunc* getDatasetInitFunc(); uint8_t* getCode() { return code; } size_t getCodeSize(); void enableWriting(); void enableExecution(); void enableAll(); private: static InstructionGeneratorA64 engine[256]; uint32_t reg_changed_offset[8]; uint8_t* code; uint32_t literalPos; uint32_t num32bitLiterals; static void emit32(uint32_t val, uint8_t* code, uint32_t& codePos) { *(uint32_t*)(code + codePos) = val; codePos += sizeof(val); } static void emit64(uint64_t val, uint8_t* code, uint32_t& codePos) { *(uint64_t*)(code + codePos) = val; codePos += sizeof(val); } void emitMovImmediate(uint32_t dst, uint32_t imm, uint8_t* code, uint32_t& codePos); void emitAddImmediate(uint32_t dst, uint32_t src, uint32_t imm, uint8_t* code, uint32_t& codePos); template void emitMemLoad(uint32_t dst, uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos); template void emitMemLoadFP(uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos); void h_IADD_RS(Instruction&, uint32_t&); void h_IADD_M(Instruction&, uint32_t&); void h_ISUB_R(Instruction&, uint32_t&); void h_ISUB_M(Instruction&, uint32_t&); void h_IMUL_R(Instruction&, uint32_t&); void h_IMUL_M(Instruction&, uint32_t&); void h_IMULH_R(Instruction&, uint32_t&); void h_IMULH_M(Instruction&, uint32_t&); void h_ISMULH_R(Instruction&, uint32_t&); void h_ISMULH_M(Instruction&, uint32_t&); void h_IMUL_RCP(Instruction&, uint32_t&); void h_INEG_R(Instruction&, uint32_t&); void h_IXOR_R(Instruction&, uint32_t&); void h_IXOR_M(Instruction&, uint32_t&); void h_IROR_R(Instruction&, uint32_t&); void h_IROL_R(Instruction&, uint32_t&); void h_ISWAP_R(Instruction&, uint32_t&); void h_FSWAP_R(Instruction&, uint32_t&); void h_FADD_R(Instruction&, uint32_t&); void h_FADD_M(Instruction&, uint32_t&); void h_FSUB_R(Instruction&, uint32_t&); void h_FSUB_M(Instruction&, uint32_t&); void h_FSCAL_R(Instruction&, uint32_t&); void h_FMUL_R(Instruction&, uint32_t&); void h_FDIV_M(Instruction&, uint32_t&); void h_FSQRT_R(Instruction&, uint32_t&); void h_CBRANCH(Instruction&, uint32_t&); void h_CFROUND(Instruction&, uint32_t&); void h_ISTORE(Instruction&, uint32_t&); void h_NOP(Instruction&, uint32_t&); }; } RandomX-1.1.10/src/jit_compiler_a64_static.S000066400000000000000000000337471414227164600206030ustar00rootroot00000000000000# Copyright (c) 2018-2019, tevador # Copyright (c) 2019, SChernykh # # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # * Neither the name of the copyright holder nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #if defined(__APPLE__) #define DECL(x) _##x #else #define DECL(x) x #endif .arch armv8-a .text .global DECL(randomx_program_aarch64) .global DECL(randomx_program_aarch64_main_loop) .global DECL(randomx_program_aarch64_vm_instructions) .global DECL(randomx_program_aarch64_imul_rcp_literals_end) .global DECL(randomx_program_aarch64_vm_instructions_end) .global DECL(randomx_program_aarch64_cacheline_align_mask1) .global DECL(randomx_program_aarch64_cacheline_align_mask2) .global DECL(randomx_program_aarch64_update_spMix1) .global DECL(randomx_program_aarch64_vm_instructions_end_light) .global DECL(randomx_program_aarch64_light_cacheline_align_mask) .global DECL(randomx_program_aarch64_light_dataset_offset) .global DECL(randomx_init_dataset_aarch64) .global DECL(randomx_init_dataset_aarch64_end) .global DECL(randomx_calc_dataset_item_aarch64) .global DECL(randomx_calc_dataset_item_aarch64_prefetch) .global DECL(randomx_calc_dataset_item_aarch64_mix) .global DECL(randomx_calc_dataset_item_aarch64_store_result) .global DECL(randomx_calc_dataset_item_aarch64_end) #include "configuration.h" # Register allocation # x0 -> pointer to reg buffer and then literal for IMUL_RCP # x1 -> pointer to mem buffer and then to dataset # x2 -> pointer to scratchpad # x3 -> loop counter # x4 -> "r0" # x5 -> "r1" # x6 -> "r2" # x7 -> "r3" # x8 -> fpcr (reversed bits) # x9 -> mx, ma # x10 -> spMix1 # x11 -> literal for IMUL_RCP # x12 -> "r4" # x13 -> "r5" # x14 -> "r6" # x15 -> "r7" # x16 -> spAddr0 # x17 -> spAddr1 # x18 -> temporary # x19 -> temporary # x20 -> literal for IMUL_RCP # x21 -> literal for IMUL_RCP # x22 -> literal for IMUL_RCP # x23 -> literal for IMUL_RCP # x24 -> literal for IMUL_RCP # x25 -> literal for IMUL_RCP # x26 -> literal for IMUL_RCP # x27 -> literal for IMUL_RCP # x28 -> literal for IMUL_RCP # x29 -> literal for IMUL_RCP # x30 -> literal for IMUL_RCP # v0-v15 -> store 32-bit literals # v16 -> "f0" # v17 -> "f1" # v18 -> "f2" # v19 -> "f3" # v20 -> "e0" # v21 -> "e1" # v22 -> "e2" # v23 -> "e3" # v24 -> "a0" # v25 -> "a1" # v26 -> "a2" # v27 -> "a3" # v28 -> temporary # v29 -> E 'and' mask = 0x00ffffffffffffff00ffffffffffffff # v30 -> E 'or' mask = 0x3*00000000******3*00000000****** # v31 -> scale mask = 0x81f000000000000081f0000000000000 .balign 4 DECL(randomx_program_aarch64): # Save callee-saved registers sub sp, sp, 192 stp x16, x17, [sp] stp x18, x19, [sp, 16] stp x20, x21, [sp, 32] stp x22, x23, [sp, 48] stp x24, x25, [sp, 64] stp x26, x27, [sp, 80] stp x28, x29, [sp, 96] stp x8, x30, [sp, 112] stp d8, d9, [sp, 128] stp d10, d11, [sp, 144] stp d12, d13, [sp, 160] stp d14, d15, [sp, 176] # Zero integer registers mov x4, xzr mov x5, xzr mov x6, xzr mov x7, xzr mov x12, xzr mov x13, xzr mov x14, xzr mov x15, xzr # Load ma, mx and dataset pointer ldp x9, x1, [x1] # Load initial spMix value mov x10, x9 # Load group A registers ldp q24, q25, [x0, 192] ldp q26, q27, [x0, 224] # Load E 'and' mask mov x16, 0x00FFFFFFFFFFFFFF ins v29.d[0], x16 ins v29.d[1], x16 # Load E 'or' mask (stored in reg.f[0]) ldr q30, [x0, 64] # Load scale mask mov x16, 0x80f0000000000000 ins v31.d[0], x16 ins v31.d[1], x16 # Read fpcr mrs x8, fpcr rbit x8, x8 # Save x0 str x0, [sp, -16]! # Read literals ldr x0, literal_x0 ldr x11, literal_x11 ldr x20, literal_x20 ldr x21, literal_x21 ldr x22, literal_x22 ldr x23, literal_x23 ldr x24, literal_x24 ldr x25, literal_x25 ldr x26, literal_x26 ldr x27, literal_x27 ldr x28, literal_x28 ldr x29, literal_x29 ldr x30, literal_x30 ldr q0, literal_v0 ldr q1, literal_v1 ldr q2, literal_v2 ldr q3, literal_v3 ldr q4, literal_v4 ldr q5, literal_v5 ldr q6, literal_v6 ldr q7, literal_v7 ldr q8, literal_v8 ldr q9, literal_v9 ldr q10, literal_v10 ldr q11, literal_v11 ldr q12, literal_v12 ldr q13, literal_v13 ldr q14, literal_v14 ldr q15, literal_v15 DECL(randomx_program_aarch64_main_loop): # spAddr0 = spMix1 & ScratchpadL3Mask64; # spAddr1 = (spMix1 >> 32) & ScratchpadL3Mask64; lsr x18, x10, 32 # Actual mask will be inserted by JIT compiler and w16, w10, 1 and w17, w18, 1 # x16 = scratchpad + spAddr0 # x17 = scratchpad + spAddr1 add x16, x16, x2 add x17, x17, x2 # xor integer registers with scratchpad data (spAddr0) ldp x18, x19, [x16] eor x4, x4, x18 eor x5, x5, x19 ldp x18, x19, [x16, 16] eor x6, x6, x18 eor x7, x7, x19 ldp x18, x19, [x16, 32] eor x12, x12, x18 eor x13, x13, x19 ldp x18, x19, [x16, 48] eor x14, x14, x18 eor x15, x15, x19 # Load group F registers (spAddr1) ldpsw x18, x19, [x17] ins v16.d[0], x18 ins v16.d[1], x19 ldpsw x18, x19, [x17, 8] ins v17.d[0], x18 ins v17.d[1], x19 ldpsw x18, x19, [x17, 16] ins v18.d[0], x18 ins v18.d[1], x19 ldpsw x18, x19, [x17, 24] ins v19.d[0], x18 ins v19.d[1], x19 scvtf v16.2d, v16.2d scvtf v17.2d, v17.2d scvtf v18.2d, v18.2d scvtf v19.2d, v19.2d # Load group E registers (spAddr1) ldpsw x18, x19, [x17, 32] ins v20.d[0], x18 ins v20.d[1], x19 ldpsw x18, x19, [x17, 40] ins v21.d[0], x18 ins v21.d[1], x19 ldpsw x18, x19, [x17, 48] ins v22.d[0], x18 ins v22.d[1], x19 ldpsw x18, x19, [x17, 56] ins v23.d[0], x18 ins v23.d[1], x19 scvtf v20.2d, v20.2d scvtf v21.2d, v21.2d scvtf v22.2d, v22.2d scvtf v23.2d, v23.2d and v20.16b, v20.16b, v29.16b and v21.16b, v21.16b, v29.16b and v22.16b, v22.16b, v29.16b and v23.16b, v23.16b, v29.16b orr v20.16b, v20.16b, v30.16b orr v21.16b, v21.16b, v30.16b orr v22.16b, v22.16b, v30.16b orr v23.16b, v23.16b, v30.16b # Execute VM instructions DECL(randomx_program_aarch64_vm_instructions): # buffer for generated instructions # FDIV_M is the largest instruction taking up to 12 ARMv8 instructions .fill RANDOMX_PROGRAM_SIZE*12,4,0 literal_x0: .fill 1,8,0 literal_x11: .fill 1,8,0 literal_x20: .fill 1,8,0 literal_x21: .fill 1,8,0 literal_x22: .fill 1,8,0 literal_x23: .fill 1,8,0 literal_x24: .fill 1,8,0 literal_x25: .fill 1,8,0 literal_x26: .fill 1,8,0 literal_x27: .fill 1,8,0 literal_x28: .fill 1,8,0 literal_x29: .fill 1,8,0 literal_x30: .fill 1,8,0 DECL(randomx_program_aarch64_imul_rcp_literals_end): literal_v0: .fill 2,8,0 literal_v1: .fill 2,8,0 literal_v2: .fill 2,8,0 literal_v3: .fill 2,8,0 literal_v4: .fill 2,8,0 literal_v5: .fill 2,8,0 literal_v6: .fill 2,8,0 literal_v7: .fill 2,8,0 literal_v8: .fill 2,8,0 literal_v9: .fill 2,8,0 literal_v10: .fill 2,8,0 literal_v11: .fill 2,8,0 literal_v12: .fill 2,8,0 literal_v13: .fill 2,8,0 literal_v14: .fill 2,8,0 literal_v15: .fill 2,8,0 DECL(randomx_program_aarch64_vm_instructions_end): # Calculate dataset pointer for dataset read # Do it here to break false dependency from readReg2 and readReg3 (see next line) lsr x10, x9, 32 # mx ^= r[readReg2] ^ r[readReg3]; eor x9, x9, x18 # Calculate dataset pointer for dataset prefetch mov w18, w9 DECL(randomx_program_aarch64_cacheline_align_mask1): # Actual mask will be inserted by JIT compiler and x18, x18, 1 add x18, x18, x1 # Prefetch dataset data prfm pldl2strm, [x18] # mx <-> ma ror x9, x9, 32 DECL(randomx_program_aarch64_cacheline_align_mask2): # Actual mask will be inserted by JIT compiler and x10, x10, 1 add x10, x10, x1 DECL(randomx_program_aarch64_xor_with_dataset_line): rx_program_xor_with_dataset_line: # xor integer registers with dataset data ldp x18, x19, [x10] eor x4, x4, x18 eor x5, x5, x19 ldp x18, x19, [x10, 16] eor x6, x6, x18 eor x7, x7, x19 ldp x18, x19, [x10, 32] eor x12, x12, x18 eor x13, x13, x19 ldp x18, x19, [x10, 48] eor x14, x14, x18 eor x15, x15, x19 DECL(randomx_program_aarch64_update_spMix1): # JIT compiler will replace it with "eor x10, config.readReg0, config.readReg1" eor x10, x0, x0 # Store integer registers to scratchpad (spAddr1) stp x4, x5, [x17, 0] stp x6, x7, [x17, 16] stp x12, x13, [x17, 32] stp x14, x15, [x17, 48] # xor group F and group E registers eor v16.16b, v16.16b, v20.16b eor v17.16b, v17.16b, v21.16b eor v18.16b, v18.16b, v22.16b eor v19.16b, v19.16b, v23.16b # Store FP registers to scratchpad (spAddr0) stp q16, q17, [x16, 0] stp q18, q19, [x16, 32] subs x3, x3, 1 bne DECL(randomx_program_aarch64_main_loop) # Restore x0 ldr x0, [sp], 16 # Store integer registers stp x4, x5, [x0, 0] stp x6, x7, [x0, 16] stp x12, x13, [x0, 32] stp x14, x15, [x0, 48] # Store FP registers stp q16, q17, [x0, 64] stp q18, q19, [x0, 96] stp q20, q21, [x0, 128] stp q22, q23, [x0, 160] # Restore callee-saved registers ldp x16, x17, [sp] ldp x18, x19, [sp, 16] ldp x20, x21, [sp, 32] ldp x22, x23, [sp, 48] ldp x24, x25, [sp, 64] ldp x26, x27, [sp, 80] ldp x28, x29, [sp, 96] ldp x8, x30, [sp, 112] ldp d8, d9, [sp, 128] ldp d10, d11, [sp, 144] ldp d12, d13, [sp, 160] ldp d14, d15, [sp, 176] add sp, sp, 192 ret DECL(randomx_program_aarch64_vm_instructions_end_light): sub sp, sp, 96 stp x0, x1, [sp, 64] stp x2, x30, [sp, 80] # mx ^= r[readReg2] ^ r[readReg3]; eor x9, x9, x18 # mx <-> ma ror x9, x9, 32 # x0 -> pointer to cache memory mov x0, x1 # x1 -> pointer to output mov x1, sp DECL(randomx_program_aarch64_light_cacheline_align_mask): # Actual mask will be inserted by JIT compiler and w2, w9, 1 # x2 -> item number lsr x2, x2, 6 DECL(randomx_program_aarch64_light_dataset_offset): # Apply dataset offset (filled in by JIT compiler) add x2, x2, 0 add x2, x2, 0 bl rx_calc_dataset_item mov x10, sp ldp x0, x1, [sp, 64] ldp x2, x30, [sp, 80] add sp, sp, 96 b rx_program_xor_with_dataset_line # Input parameters # # x0 -> pointer to cache # x1 -> pointer to dataset memory at startItem # x2 -> start item # x3 -> end item DECL(randomx_init_dataset_aarch64): # Save x30 (return address) str x30, [sp, -16]! # Load pointer to cache memory ldr x0, [x0] DECL(randomx_init_dataset_aarch64_main_loop): bl rx_calc_dataset_item add x1, x1, 64 add x2, x2, 1 cmp x2, x3 bne DECL(randomx_init_dataset_aarch64_main_loop) # Restore x30 (return address) ldr x30, [sp], 16 ret DECL(randomx_init_dataset_aarch64_end): # Input parameters # # x0 -> pointer to cache memory # x1 -> pointer to output # x2 -> item number # # Register allocation # # x0-x7 -> output value (calculated dataset item) # x8 -> pointer to cache memory # x9 -> pointer to output # x10 -> registerValue # x11 -> mixBlock # x12 -> temporary # x13 -> temporary DECL(randomx_calc_dataset_item_aarch64): rx_calc_dataset_item: sub sp, sp, 112 stp x0, x1, [sp] stp x2, x3, [sp, 16] stp x4, x5, [sp, 32] stp x6, x7, [sp, 48] stp x8, x9, [sp, 64] stp x10, x11, [sp, 80] stp x12, x13, [sp, 96] ldr x12, superscalarMul0 mov x8, x0 mov x9, x1 mov x10, x2 # rl[0] = (itemNumber + 1) * superscalarMul0; madd x0, x2, x12, x12 # rl[1] = rl[0] ^ superscalarAdd1; ldr x12, superscalarAdd1 eor x1, x0, x12 # rl[2] = rl[0] ^ superscalarAdd2; ldr x12, superscalarAdd2 eor x2, x0, x12 # rl[3] = rl[0] ^ superscalarAdd3; ldr x12, superscalarAdd3 eor x3, x0, x12 # rl[4] = rl[0] ^ superscalarAdd4; ldr x12, superscalarAdd4 eor x4, x0, x12 # rl[5] = rl[0] ^ superscalarAdd5; ldr x12, superscalarAdd5 eor x5, x0, x12 # rl[6] = rl[0] ^ superscalarAdd6; ldr x12, superscalarAdd6 eor x6, x0, x12 # rl[7] = rl[0] ^ superscalarAdd7; ldr x12, superscalarAdd7 eor x7, x0, x12 b rx_calc_dataset_item_prefetch superscalarMul0: .quad 6364136223846793005 superscalarAdd1: .quad 9298411001130361340 superscalarAdd2: .quad 12065312585734608966 superscalarAdd3: .quad 9306329213124626780 superscalarAdd4: .quad 5281919268842080866 superscalarAdd5: .quad 10536153434571861004 superscalarAdd6: .quad 3398623926847679864 superscalarAdd7: .quad 9549104520008361294 # Prefetch -> SuperScalar hash -> Mix will be repeated N times DECL(randomx_calc_dataset_item_aarch64_prefetch): rx_calc_dataset_item_prefetch: # Actual mask will be inserted by JIT compiler and x11, x10, 1 add x11, x8, x11, lsl 6 prfm pldl2strm, [x11] # Generated SuperScalar hash program goes here DECL(randomx_calc_dataset_item_aarch64_mix): ldp x12, x13, [x11] eor x0, x0, x12 eor x1, x1, x13 ldp x12, x13, [x11, 16] eor x2, x2, x12 eor x3, x3, x13 ldp x12, x13, [x11, 32] eor x4, x4, x12 eor x5, x5, x13 ldp x12, x13, [x11, 48] eor x6, x6, x12 eor x7, x7, x13 DECL(randomx_calc_dataset_item_aarch64_store_result): stp x0, x1, [x9] stp x2, x3, [x9, 16] stp x4, x5, [x9, 32] stp x6, x7, [x9, 48] ldp x0, x1, [sp] ldp x2, x3, [sp, 16] ldp x4, x5, [sp, 32] ldp x6, x7, [sp, 48] ldp x8, x9, [sp, 64] ldp x10, x11, [sp, 80] ldp x12, x13, [sp, 96] add sp, sp, 112 ret DECL(randomx_calc_dataset_item_aarch64_end): RandomX-1.1.10/src/jit_compiler_a64_static.hpp000066400000000000000000000050031414227164600211500ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador Copyright (c) 2019, SChernykh All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once extern "C" { void randomx_program_aarch64(void* reg, void* mem, void* scratchpad, uint64_t iterations); void randomx_program_aarch64_main_loop(); void randomx_program_aarch64_vm_instructions(); void randomx_program_aarch64_imul_rcp_literals_end(); void randomx_program_aarch64_vm_instructions_end(); void randomx_program_aarch64_cacheline_align_mask1(); void randomx_program_aarch64_cacheline_align_mask2(); void randomx_program_aarch64_update_spMix1(); void randomx_program_aarch64_vm_instructions_end_light(); void randomx_program_aarch64_light_cacheline_align_mask(); void randomx_program_aarch64_light_dataset_offset(); void randomx_init_dataset_aarch64(); void randomx_init_dataset_aarch64_end(); void randomx_calc_dataset_item_aarch64(); void randomx_calc_dataset_item_aarch64_prefetch(); void randomx_calc_dataset_item_aarch64_mix(); void randomx_calc_dataset_item_aarch64_store_result(); void randomx_calc_dataset_item_aarch64_end(); } RandomX-1.1.10/src/jit_compiler_fallback.hpp000066400000000000000000000046251414227164600207570ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "common.hpp" namespace randomx { class Program; struct ProgramConfiguration; class SuperscalarProgram; class JitCompilerFallback { public: JitCompilerFallback() { throw std::runtime_error("JIT compilation is not supported on this platform"); } void generateProgram(Program&, ProgramConfiguration&) { } void generateProgramLight(Program&, ProgramConfiguration&, uint32_t) { } template void generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector &) { } void generateDatasetInitCode() { } ProgramFunc* getProgramFunc() { return nullptr; } DatasetInitFunc* getDatasetInitFunc() { return nullptr; } uint8_t* getCode() { return nullptr; } size_t getCodeSize() { return 0; } void enableWriting() {} void enableExecution() {} void enableAll() {} }; }RandomX-1.1.10/src/jit_compiler_x86.cpp000066400000000000000000000646001414227164600176370ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "jit_compiler_x86.hpp" #include "jit_compiler_x86_static.hpp" #include "superscalar.hpp" #include "program.hpp" #include "reciprocal.h" #include "virtual_memory.hpp" namespace randomx { /* REGISTER ALLOCATION: ; rax -> temporary ; rbx -> iteration counter "ic" ; rcx -> temporary ; rdx -> temporary ; rsi -> scratchpad pointer ; rdi -> dataset pointer ; rbp -> memory registers "ma" (high 32 bits), "mx" (low 32 bits) ; rsp -> stack pointer ; r8 -> "r0" ; r9 -> "r1" ; r10 -> "r2" ; r11 -> "r3" ; r12 -> "r4" ; r13 -> "r5" ; r14 -> "r6" ; r15 -> "r7" ; xmm0 -> "f0" ; xmm1 -> "f1" ; xmm2 -> "f2" ; xmm3 -> "f3" ; xmm4 -> "e0" ; xmm5 -> "e1" ; xmm6 -> "e2" ; xmm7 -> "e3" ; xmm8 -> "a0" ; xmm9 -> "a1" ; xmm10 -> "a2" ; xmm11 -> "a3" ; xmm12 -> temporary ; xmm13 -> E 'and' mask = 0x00ffffffffffffff00ffffffffffffff ; xmm14 -> E 'or' mask = 0x3*00000000******3*00000000****** ; xmm15 -> scale mask = 0x81f000000000000081f0000000000000 */ //Calculate the required code buffer size that is sufficient for the largest possible program: constexpr size_t MaxRandomXInstrCodeSize = 32; //FDIV_M requires up to 32 bytes of x86 code constexpr size_t MaxSuperscalarInstrSize = 14; //IMUL_RCP requires 14 bytes of x86 code constexpr size_t SuperscalarProgramHeader = 128; //overhead per superscalar program constexpr size_t CodeAlign = 4096; //align code size to a multiple of 4 KiB constexpr size_t ReserveCodeSize = CodeAlign; //function prologue/epilogue + reserve constexpr size_t RandomXCodeSize = alignSize(ReserveCodeSize + MaxRandomXInstrCodeSize * RANDOMX_PROGRAM_SIZE, CodeAlign); constexpr size_t SuperscalarSize = alignSize(ReserveCodeSize + (SuperscalarProgramHeader + MaxSuperscalarInstrSize * SuperscalarMaxSize) * RANDOMX_CACHE_ACCESSES, CodeAlign); static_assert(RandomXCodeSize < INT32_MAX / 2, "RandomXCodeSize is too large"); static_assert(SuperscalarSize < INT32_MAX / 2, "SuperscalarSize is too large"); constexpr uint32_t CodeSize = RandomXCodeSize + SuperscalarSize; constexpr int32_t superScalarHashOffset = RandomXCodeSize; #if defined(_MSC_VER) && (defined(_DEBUG) || defined (RELWITHDEBINFO)) #define ADDR(x) ((((uint8_t*)&x)[0] == 0xE9) ? (((uint8_t*)&x) + *(const int32_t*)(((uint8_t*)&x) + 1) + 5) : ((uint8_t*)&x)) #else #define ADDR(x) ((uint8_t*)&x) #endif const uint8_t* codePrologue = ADDR(randomx_program_prologue); const uint8_t* codeLoopBegin = ADDR(randomx_program_loop_begin); const uint8_t* codeLoopLoad = ADDR(randomx_program_loop_load); const uint8_t* codeProgamStart = ADDR(randomx_program_start); const uint8_t* codeReadDataset = ADDR(randomx_program_read_dataset); const uint8_t* codeReadDatasetLightSshInit = ADDR(randomx_program_read_dataset_sshash_init); const uint8_t* codeReadDatasetLightSshFin = ADDR(randomx_program_read_dataset_sshash_fin); const uint8_t* codeDatasetInit = ADDR(randomx_dataset_init); const uint8_t* codeLoopStore = ADDR(randomx_program_loop_store); const uint8_t* codeLoopEnd = ADDR(randomx_program_loop_end); const uint8_t* codeEpilogue = ADDR(randomx_program_epilogue); const uint8_t* codeProgramEnd = ADDR(randomx_program_end); const uint8_t* codeShhLoad = ADDR(randomx_sshash_load); const uint8_t* codeShhPrefetch = ADDR(randomx_sshash_prefetch); const uint8_t* codeShhEnd = ADDR(randomx_sshash_end); const uint8_t* codeShhInit = ADDR(randomx_sshash_init); const int32_t prologueSize = codeLoopBegin - codePrologue; const int32_t loopLoadSize = codeProgamStart - codeLoopLoad; const int32_t readDatasetSize = codeReadDatasetLightSshInit - codeReadDataset; const int32_t readDatasetLightInitSize = codeReadDatasetLightSshFin - codeReadDatasetLightSshInit; const int32_t readDatasetLightFinSize = codeLoopStore - codeReadDatasetLightSshFin; const int32_t loopStoreSize = codeLoopEnd - codeLoopStore; const int32_t datasetInitSize = codeEpilogue - codeDatasetInit; const int32_t epilogueSize = codeShhLoad - codeEpilogue; const int32_t codeSshLoadSize = codeShhPrefetch - codeShhLoad; const int32_t codeSshPrefetchSize = codeShhEnd - codeShhPrefetch; const int32_t codeSshInitSize = codeProgramEnd - codeShhInit; const int32_t epilogueOffset = CodeSize - epilogueSize; static const uint8_t REX_ADD_RR[] = { 0x4d, 0x03 }; static const uint8_t REX_ADD_RM[] = { 0x4c, 0x03 }; static const uint8_t REX_SUB_RR[] = { 0x4d, 0x2b }; static const uint8_t REX_SUB_RM[] = { 0x4c, 0x2b }; static const uint8_t REX_MOV_RR[] = { 0x41, 0x8b }; static const uint8_t REX_MOV_RR64[] = { 0x49, 0x8b }; static const uint8_t REX_MOV_R64R[] = { 0x4c, 0x8b }; static const uint8_t REX_IMUL_RR[] = { 0x4d, 0x0f, 0xaf }; static const uint8_t REX_IMUL_RRI[] = { 0x4d, 0x69 }; static const uint8_t REX_IMUL_RM[] = { 0x4c, 0x0f, 0xaf }; static const uint8_t REX_MUL_R[] = { 0x49, 0xf7 }; static const uint8_t REX_MUL_M[] = { 0x48, 0xf7 }; static const uint8_t REX_81[] = { 0x49, 0x81 }; static const uint8_t AND_EAX_I = 0x25; static const uint8_t MOV_EAX_I = 0xb8; static const uint8_t MOV_RAX_I[] = { 0x48, 0xb8 }; static const uint8_t MOV_RCX_I[] = { 0x48, 0xb9 }; static const uint8_t REX_LEA[] = { 0x4f, 0x8d }; static const uint8_t REX_MUL_MEM[] = { 0x48, 0xf7, 0x24, 0x0e }; static const uint8_t REX_IMUL_MEM[] = { 0x48, 0xf7, 0x2c, 0x0e }; static const uint8_t REX_SHR_RAX[] = { 0x48, 0xc1, 0xe8 }; static const uint8_t RAX_ADD_SBB_1[] = { 0x48, 0x83, 0xC0, 0x01, 0x48, 0x83, 0xD8, 0x00 }; static const uint8_t MUL_RCX[] = { 0x48, 0xf7, 0xe1 }; static const uint8_t REX_SHR_RDX[] = { 0x48, 0xc1, 0xea }; static const uint8_t REX_SH[] = { 0x49, 0xc1 }; static const uint8_t MOV_RCX_RAX_SAR_RCX_63[] = { 0x48, 0x89, 0xc1, 0x48, 0xc1, 0xf9, 0x3f }; static const uint8_t AND_ECX_I[] = { 0x81, 0xe1 }; static const uint8_t ADD_RAX_RCX[] = { 0x48, 0x01, 0xC8 }; static const uint8_t SAR_RAX_I8[] = { 0x48, 0xC1, 0xF8 }; static const uint8_t NEG_RAX[] = { 0x48, 0xF7, 0xD8 }; static const uint8_t ADD_R_RAX[] = { 0x4C, 0x03 }; static const uint8_t XOR_EAX_EAX[] = { 0x33, 0xC0 }; static const uint8_t ADD_RDX_R[] = { 0x4c, 0x01 }; static const uint8_t SUB_RDX_R[] = { 0x4c, 0x29 }; static const uint8_t SAR_RDX_I8[] = { 0x48, 0xC1, 0xFA }; static const uint8_t TEST_RDX_RDX[] = { 0x48, 0x85, 0xD2 }; static const uint8_t SETS_AL_ADD_RDX_RAX[] = { 0x0F, 0x98, 0xC0, 0x48, 0x03, 0xD0 }; static const uint8_t REX_NEG[] = { 0x49, 0xF7 }; static const uint8_t REX_XOR_RR[] = { 0x4D, 0x33 }; static const uint8_t REX_XOR_RI[] = { 0x49, 0x81 }; static const uint8_t REX_XOR_RM[] = { 0x4c, 0x33 }; static const uint8_t REX_ROT_CL[] = { 0x49, 0xd3 }; static const uint8_t REX_ROT_I8[] = { 0x49, 0xc1 }; static const uint8_t SHUFPD[] = { 0x66, 0x0f, 0xc6 }; static const uint8_t REX_ADDPD[] = { 0x66, 0x41, 0x0f, 0x58 }; static const uint8_t REX_CVTDQ2PD_XMM12[] = { 0xf3, 0x44, 0x0f, 0xe6, 0x24, 0x06 }; static const uint8_t REX_SUBPD[] = { 0x66, 0x41, 0x0f, 0x5c }; static const uint8_t REX_XORPS[] = { 0x41, 0x0f, 0x57 }; static const uint8_t REX_MULPD[] = { 0x66, 0x41, 0x0f, 0x59 }; static const uint8_t REX_MAXPD[] = { 0x66, 0x41, 0x0f, 0x5f }; static const uint8_t REX_DIVPD[] = { 0x66, 0x41, 0x0f, 0x5e }; static const uint8_t SQRTPD[] = { 0x66, 0x0f, 0x51 }; static const uint8_t AND_OR_MOV_LDMXCSR[] = { 0x25, 0x00, 0x60, 0x00, 0x00, 0x0D, 0xC0, 0x9F, 0x00, 0x00, 0x50, 0x0F, 0xAE, 0x14, 0x24, 0x58 }; static const uint8_t ROL_RAX[] = { 0x48, 0xc1, 0xc0 }; static const uint8_t XOR_ECX_ECX[] = { 0x33, 0xC9 }; static const uint8_t REX_CMP_R32I[] = { 0x41, 0x81 }; static const uint8_t REX_CMP_M32I[] = { 0x81, 0x3c, 0x06 }; static const uint8_t MOVAPD[] = { 0x66, 0x0f, 0x29 }; static const uint8_t REX_MOV_MR[] = { 0x4c, 0x89 }; static const uint8_t REX_XOR_EAX[] = { 0x41, 0x33 }; static const uint8_t SUB_EBX[] = { 0x83, 0xEB, 0x01 }; static const uint8_t JNZ[] = { 0x0f, 0x85 }; static const uint8_t JMP = 0xe9; static const uint8_t REX_XOR_RAX_R64[] = { 0x49, 0x33 }; static const uint8_t REX_XCHG[] = { 0x4d, 0x87 }; static const uint8_t REX_ANDPS_XMM12[] = { 0x45, 0x0F, 0x54, 0xE5, 0x45, 0x0F, 0x56, 0xE6 }; static const uint8_t REX_PADD[] = { 0x66, 0x44, 0x0f }; static const uint8_t PADD_OPCODES[] = { 0xfc, 0xfd, 0xfe, 0xd4 }; static const uint8_t CALL = 0xe8; static const uint8_t REX_ADD_I[] = { 0x49, 0x81 }; static const uint8_t REX_TEST[] = { 0x49, 0xF7 }; static const uint8_t JZ[] = { 0x0f, 0x84 }; static const uint8_t RET = 0xc3; static const uint8_t LEA_32[] = { 0x41, 0x8d }; static const uint8_t MOVNTI[] = { 0x4c, 0x0f, 0xc3 }; static const uint8_t ADD_EBX_I[] = { 0x81, 0xc3 }; static const uint8_t NOP1[] = { 0x90 }; static const uint8_t NOP2[] = { 0x66, 0x90 }; static const uint8_t NOP3[] = { 0x66, 0x66, 0x90 }; static const uint8_t NOP4[] = { 0x0F, 0x1F, 0x40, 0x00 }; static const uint8_t NOP5[] = { 0x0F, 0x1F, 0x44, 0x00, 0x00 }; static const uint8_t NOP6[] = { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00 }; static const uint8_t NOP7[] = { 0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t NOP8[] = { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t* NOPX[] = { NOP1, NOP2, NOP3, NOP4, NOP5, NOP6, NOP7, NOP8 }; size_t JitCompilerX86::getCodeSize() { return CodeSize; } JitCompilerX86::JitCompilerX86() { code = (uint8_t*)allocMemoryPages(CodeSize); memcpy(code, codePrologue, prologueSize); memcpy(code + epilogueOffset, codeEpilogue, epilogueSize); } JitCompilerX86::~JitCompilerX86() { freePagedMemory(code, CodeSize); } void JitCompilerX86::enableAll() { setPagesRWX(code, CodeSize); } void JitCompilerX86::enableWriting() { setPagesRW(code, CodeSize); } void JitCompilerX86::enableExecution() { setPagesRX(code, CodeSize); } void JitCompilerX86::generateProgram(Program& prog, ProgramConfiguration& pcfg) { generateProgramPrologue(prog, pcfg); memcpy(code + codePos, codeReadDataset, readDatasetSize); codePos += readDatasetSize; generateProgramEpilogue(prog, pcfg); } void JitCompilerX86::generateProgramLight(Program& prog, ProgramConfiguration& pcfg, uint32_t datasetOffset) { generateProgramPrologue(prog, pcfg); emit(codeReadDatasetLightSshInit, readDatasetLightInitSize); emit(ADD_EBX_I); emit32(datasetOffset / CacheLineSize); emitByte(CALL); emit32(superScalarHashOffset - (codePos + 4)); emit(codeReadDatasetLightSshFin, readDatasetLightFinSize); generateProgramEpilogue(prog, pcfg); } template void JitCompilerX86::generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector &reciprocalCache) { memcpy(code + superScalarHashOffset, codeShhInit, codeSshInitSize); codePos = superScalarHashOffset + codeSshInitSize; for (unsigned j = 0; j < N; ++j) { SuperscalarProgram& prog = programs[j]; for (unsigned i = 0; i < prog.getSize(); ++i) { Instruction& instr = prog(i); generateSuperscalarCode(instr, reciprocalCache); } emit(codeShhLoad, codeSshLoadSize); if (j < N - 1) { emit(REX_MOV_RR64); emitByte(0xd8 + prog.getAddressRegister()); emit(codeShhPrefetch, codeSshPrefetchSize); #ifdef RANDOMX_ALIGN int align = (codePos % 16); while (align != 0) { int nopSize = 16 - align; if (nopSize > 8) nopSize = 8; emit(NOPX[nopSize - 1], nopSize); align = (codePos % 16); } #endif } } emitByte(RET); } template void JitCompilerX86::generateSuperscalarHash(SuperscalarProgram(&programs)[RANDOMX_CACHE_ACCESSES], std::vector &reciprocalCache); void JitCompilerX86::generateDatasetInitCode() { memcpy(code, codeDatasetInit, datasetInitSize); } void JitCompilerX86::generateProgramPrologue(Program& prog, ProgramConfiguration& pcfg) { instructionOffsets.clear(); for (unsigned i = 0; i < RegistersCount; ++i) { registerUsage[i] = -1; } codePos = prologueSize; memcpy(code + codePos - 48, &pcfg.eMask, sizeof(pcfg.eMask)); memcpy(code + codePos, codeLoopLoad, loopLoadSize); codePos += loopLoadSize; for (unsigned i = 0; i < prog.getSize(); ++i) { Instruction& instr = prog(i); instr.src %= RegistersCount; instr.dst %= RegistersCount; generateCode(instr, i); } emit(REX_MOV_RR); emitByte(0xc0 + pcfg.readReg2); emit(REX_XOR_EAX); emitByte(0xc0 + pcfg.readReg3); } void JitCompilerX86::generateProgramEpilogue(Program& prog, ProgramConfiguration& pcfg) { emit(REX_MOV_RR64); emitByte(0xc0 + pcfg.readReg0); emit(REX_XOR_RAX_R64); emitByte(0xc0 + pcfg.readReg1); emit(ADDR(randomx_prefetch_scratchpad), ADDR(randomx_prefetch_scratchpad_end) - ADDR(randomx_prefetch_scratchpad)); memcpy(code + codePos, codeLoopStore, loopStoreSize); codePos += loopStoreSize; emit(SUB_EBX); emit(JNZ); emit32(prologueSize - codePos - 4); emitByte(JMP); emit32(epilogueOffset - codePos - 4); } void JitCompilerX86::generateCode(Instruction& instr, int i) { instructionOffsets.push_back(codePos); auto generator = engine[instr.opcode]; (this->*generator)(instr, i); } void JitCompilerX86::generateSuperscalarCode(Instruction& instr, std::vector &reciprocalCache) { switch ((SuperscalarInstructionType)instr.opcode) { case randomx::SuperscalarInstructionType::ISUB_R: emit(REX_SUB_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); break; case randomx::SuperscalarInstructionType::IXOR_R: emit(REX_XOR_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); break; case randomx::SuperscalarInstructionType::IADD_RS: emit(REX_LEA); emitByte(0x04 + 8 * instr.dst); genSIB(instr.getModShift(), instr.src, instr.dst); break; case randomx::SuperscalarInstructionType::IMUL_R: emit(REX_IMUL_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); break; case randomx::SuperscalarInstructionType::IROR_C: emit(REX_ROT_I8); emitByte(0xc8 + instr.dst); emitByte(instr.getImm32() & 63); break; case randomx::SuperscalarInstructionType::IADD_C7: emit(REX_81); emitByte(0xc0 + instr.dst); emit32(instr.getImm32()); break; case randomx::SuperscalarInstructionType::IXOR_C7: emit(REX_XOR_RI); emitByte(0xf0 + instr.dst); emit32(instr.getImm32()); break; case randomx::SuperscalarInstructionType::IADD_C8: emit(REX_81); emitByte(0xc0 + instr.dst); emit32(instr.getImm32()); #ifdef RANDOMX_ALIGN emit(NOP1); #endif break; case randomx::SuperscalarInstructionType::IXOR_C8: emit(REX_XOR_RI); emitByte(0xf0 + instr.dst); emit32(instr.getImm32()); #ifdef RANDOMX_ALIGN emit(NOP1); #endif break; case randomx::SuperscalarInstructionType::IADD_C9: emit(REX_81); emitByte(0xc0 + instr.dst); emit32(instr.getImm32()); #ifdef RANDOMX_ALIGN emit(NOP2); #endif break; case randomx::SuperscalarInstructionType::IXOR_C9: emit(REX_XOR_RI); emitByte(0xf0 + instr.dst); emit32(instr.getImm32()); #ifdef RANDOMX_ALIGN emit(NOP2); #endif break; case randomx::SuperscalarInstructionType::IMULH_R: emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_R); emitByte(0xe0 + instr.src); emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); break; case randomx::SuperscalarInstructionType::ISMULH_R: emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_R); emitByte(0xe8 + instr.src); emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); break; case randomx::SuperscalarInstructionType::IMUL_RCP: emit(MOV_RAX_I); emit64(reciprocalCache[instr.getImm32()]); emit(REX_IMUL_RM); emitByte(0xc0 + 8 * instr.dst); break; default: UNREACHABLE; } } void JitCompilerX86::genAddressReg(Instruction& instr, bool rax = true) { emit(LEA_32); emitByte(0x80 + instr.src + (rax ? 0 : 8)); if (instr.src == RegisterNeedsSib) { emitByte(0x24); } emit32(instr.getImm32()); if (rax) emitByte(AND_EAX_I); else emit(AND_ECX_I); emit32(instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } void JitCompilerX86::genAddressRegDst(Instruction& instr) { emit(LEA_32); emitByte(0x80 + instr.dst); if (instr.dst == RegisterNeedsSib) { emitByte(0x24); } emit32(instr.getImm32()); emitByte(AND_EAX_I); if (instr.getModCond() < StoreL3Condition) { emit32(instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask); } else { emit32(ScratchpadL3Mask); } } void JitCompilerX86::genAddressImm(Instruction& instr) { emit32(instr.getImm32() & ScratchpadL3Mask); } void JitCompilerX86::h_IADD_RS(Instruction& instr, int i) { registerUsage[instr.dst] = i; emit(REX_LEA); if (instr.dst == RegisterNeedsDisplacement) emitByte(0xac); else emitByte(0x04 + 8 * instr.dst); genSIB(instr.getModShift(), instr.src, instr.dst); if (instr.dst == RegisterNeedsDisplacement) emit32(instr.getImm32()); } void JitCompilerX86::h_IADD_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); emit(REX_ADD_RM); emitByte(0x04 + 8 * instr.dst); emitByte(0x06); } else { emit(REX_ADD_RM); emitByte(0x86 + 8 * instr.dst); genAddressImm(instr); } } void JitCompilerX86::genSIB(int scale, int index, int base) { emitByte((scale << 6) | (index << 3) | base); } void JitCompilerX86::h_ISUB_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { emit(REX_SUB_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); } else { emit(REX_81); emitByte(0xe8 + instr.dst); emit32(instr.getImm32()); } } void JitCompilerX86::h_ISUB_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); emit(REX_SUB_RM); emitByte(0x04 + 8 * instr.dst); emitByte(0x06); } else { emit(REX_SUB_RM); emitByte(0x86 + 8 * instr.dst); genAddressImm(instr); } } void JitCompilerX86::h_IMUL_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { emit(REX_IMUL_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); } else { emit(REX_IMUL_RRI); emitByte(0xc0 + 9 * instr.dst); emit32(instr.getImm32()); } } void JitCompilerX86::h_IMUL_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); emit(REX_IMUL_RM); emitByte(0x04 + 8 * instr.dst); emitByte(0x06); } else { emit(REX_IMUL_RM); emitByte(0x86 + 8 * instr.dst); genAddressImm(instr); } } void JitCompilerX86::h_IMULH_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_R); emitByte(0xe0 + instr.src); emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); } void JitCompilerX86::h_IMULH_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr, false); emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_MEM); } else { emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_M); emitByte(0xa6); genAddressImm(instr); } emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); } void JitCompilerX86::h_ISMULH_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_R); emitByte(0xe8 + instr.src); emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); } void JitCompilerX86::h_ISMULH_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr, false); emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_IMUL_MEM); } else { emit(REX_MOV_RR64); emitByte(0xc0 + instr.dst); emit(REX_MUL_M); emitByte(0xae); genAddressImm(instr); } emit(REX_MOV_R64R); emitByte(0xc2 + 8 * instr.dst); } void JitCompilerX86::h_IMUL_RCP(Instruction& instr, int i) { uint64_t divisor = instr.getImm32(); if (!isZeroOrPowerOf2(divisor)) { registerUsage[instr.dst] = i; emit(MOV_RAX_I); emit64(randomx_reciprocal_fast(divisor)); emit(REX_IMUL_RM); emitByte(0xc0 + 8 * instr.dst); } } void JitCompilerX86::h_INEG_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; emit(REX_NEG); emitByte(0xd8 + instr.dst); } void JitCompilerX86::h_IXOR_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { emit(REX_XOR_RR); emitByte(0xc0 + 8 * instr.dst + instr.src); } else { emit(REX_XOR_RI); emitByte(0xf0 + instr.dst); emit32(instr.getImm32()); } } void JitCompilerX86::h_IXOR_M(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { genAddressReg(instr); emit(REX_XOR_RM); emitByte(0x04 + 8 * instr.dst); emitByte(0x06); } else { emit(REX_XOR_RM); emitByte(0x86 + 8 * instr.dst); genAddressImm(instr); } } void JitCompilerX86::h_IROR_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { emit(REX_MOV_RR); emitByte(0xc8 + instr.src); emit(REX_ROT_CL); emitByte(0xc8 + instr.dst); } else { emit(REX_ROT_I8); emitByte(0xc8 + instr.dst); emitByte(instr.getImm32() & 63); } } void JitCompilerX86::h_IROL_R(Instruction& instr, int i) { registerUsage[instr.dst] = i; if (instr.src != instr.dst) { emit(REX_MOV_RR); emitByte(0xc8 + instr.src); emit(REX_ROT_CL); emitByte(0xc0 + instr.dst); } else { emit(REX_ROT_I8); emitByte(0xc0 + instr.dst); emitByte(instr.getImm32() & 63); } } void JitCompilerX86::h_ISWAP_R(Instruction& instr, int i) { if (instr.src != instr.dst) { registerUsage[instr.dst] = i; registerUsage[instr.src] = i; emit(REX_XCHG); emitByte(0xc0 + instr.src + 8 * instr.dst); } } void JitCompilerX86::h_FSWAP_R(Instruction& instr, int i) { emit(SHUFPD); emitByte(0xc0 + 9 * instr.dst); emitByte(1); } void JitCompilerX86::h_FADD_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; emit(REX_ADDPD); emitByte(0xc0 + instr.src + 8 * instr.dst); } void JitCompilerX86::h_FADD_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); emit(REX_CVTDQ2PD_XMM12); emit(REX_ADDPD); emitByte(0xc4 + 8 * instr.dst); } void JitCompilerX86::h_FSUB_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; emit(REX_SUBPD); emitByte(0xc0 + instr.src + 8 * instr.dst); } void JitCompilerX86::h_FSUB_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); emit(REX_CVTDQ2PD_XMM12); emit(REX_SUBPD); emitByte(0xc4 + 8 * instr.dst); } void JitCompilerX86::h_FSCAL_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; emit(REX_XORPS); emitByte(0xc7 + 8 * instr.dst); } void JitCompilerX86::h_FMUL_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; instr.src %= RegisterCountFlt; emit(REX_MULPD); emitByte(0xe0 + instr.src + 8 * instr.dst); } void JitCompilerX86::h_FDIV_M(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; genAddressReg(instr); emit(REX_CVTDQ2PD_XMM12); emit(REX_ANDPS_XMM12); emit(REX_DIVPD); emitByte(0xe4 + 8 * instr.dst); } void JitCompilerX86::h_FSQRT_R(Instruction& instr, int i) { instr.dst %= RegisterCountFlt; emit(SQRTPD); emitByte(0xe4 + 9 * instr.dst); } void JitCompilerX86::h_CFROUND(Instruction& instr, int i) { emit(REX_MOV_RR64); emitByte(0xc0 + instr.src); int rotate = (13 - (instr.getImm32() & 63)) & 63; if (rotate != 0) { emit(ROL_RAX); emitByte(rotate); } emit(AND_OR_MOV_LDMXCSR); } void JitCompilerX86::h_CBRANCH(Instruction& instr, int i) { int reg = instr.dst; int target = registerUsage[reg] + 1; emit(REX_ADD_I); emitByte(0xc0 + reg); int shift = instr.getModCond() + ConditionOffset; uint32_t imm = instr.getImm32() | (1UL << shift); if (ConditionOffset > 0 || shift > 0) imm &= ~(1UL << (shift - 1)); emit32(imm); emit(REX_TEST); emitByte(0xc0 + reg); emit32(ConditionMask << shift); emit(JZ); emit32(instructionOffsets[target] - (codePos + 4)); //mark all registers as used for (unsigned j = 0; j < RegistersCount; ++j) { registerUsage[j] = i; } } void JitCompilerX86::h_ISTORE(Instruction& instr, int i) { genAddressRegDst(instr); emit(REX_MOV_MR); emitByte(0x04 + 8 * instr.src); emitByte(0x06); } void JitCompilerX86::h_NOP(Instruction& instr, int i) { emit(NOP1); } #include "instruction_weights.hpp" #define INST_HANDLE(x) REPN(&JitCompilerX86::h_##x, WT(x)) InstructionGeneratorX86 JitCompilerX86::engine[256] = { INST_HANDLE(IADD_RS) INST_HANDLE(IADD_M) INST_HANDLE(ISUB_R) INST_HANDLE(ISUB_M) INST_HANDLE(IMUL_R) INST_HANDLE(IMUL_M) INST_HANDLE(IMULH_R) INST_HANDLE(IMULH_M) INST_HANDLE(ISMULH_R) INST_HANDLE(ISMULH_M) INST_HANDLE(IMUL_RCP) INST_HANDLE(INEG_R) INST_HANDLE(IXOR_R) INST_HANDLE(IXOR_M) INST_HANDLE(IROR_R) INST_HANDLE(IROL_R) INST_HANDLE(ISWAP_R) INST_HANDLE(FSWAP_R) INST_HANDLE(FADD_R) INST_HANDLE(FADD_M) INST_HANDLE(FSUB_R) INST_HANDLE(FSUB_M) INST_HANDLE(FSCAL_R) INST_HANDLE(FMUL_R) INST_HANDLE(FDIV_M) INST_HANDLE(FSQRT_R) INST_HANDLE(CBRANCH) INST_HANDLE(CFROUND) INST_HANDLE(ISTORE) INST_HANDLE(NOP) }; } RandomX-1.1.10/src/jit_compiler_x86.hpp000066400000000000000000000110221414227164600176320ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include "common.hpp" namespace randomx { class Program; struct ProgramConfiguration; class SuperscalarProgram; class JitCompilerX86; class Instruction; typedef void(JitCompilerX86::*InstructionGeneratorX86)(Instruction&, int); class JitCompilerX86 { public: JitCompilerX86(); ~JitCompilerX86(); void generateProgram(Program&, ProgramConfiguration&); void generateProgramLight(Program&, ProgramConfiguration&, uint32_t); template void generateSuperscalarHash(SuperscalarProgram (&programs)[N], std::vector &); void generateDatasetInitCode(); ProgramFunc* getProgramFunc() { return (ProgramFunc*)code; } DatasetInitFunc* getDatasetInitFunc() { return (DatasetInitFunc*)code; } uint8_t* getCode() { return code; } size_t getCodeSize(); void enableWriting(); void enableExecution(); void enableAll(); private: static InstructionGeneratorX86 engine[256]; std::vector instructionOffsets; int registerUsage[RegistersCount]; uint8_t* code; int32_t codePos; void generateProgramPrologue(Program&, ProgramConfiguration&); void generateProgramEpilogue(Program&, ProgramConfiguration&); void genAddressReg(Instruction&, bool); void genAddressRegDst(Instruction&); void genAddressImm(Instruction&); void genSIB(int scale, int index, int base); void generateCode(Instruction&, int); void generateSuperscalarCode(Instruction &, std::vector &); void emitByte(uint8_t val) { code[codePos] = val; codePos++; } void emit32(uint32_t val) { memcpy(code + codePos, &val, sizeof val); codePos += sizeof val; } void emit64(uint64_t val) { memcpy(code + codePos, &val, sizeof val); codePos += sizeof val; } template void emit(const uint8_t (&src)[N]) { emit(src, N); } void emit(const uint8_t* src, size_t count) { memcpy(code + codePos, src, count); codePos += count; } void h_IADD_RS(Instruction&, int); void h_IADD_M(Instruction&, int); void h_ISUB_R(Instruction&, int); void h_ISUB_M(Instruction&, int); void h_IMUL_R(Instruction&, int); void h_IMUL_M(Instruction&, int); void h_IMULH_R(Instruction&, int); void h_IMULH_M(Instruction&, int); void h_ISMULH_R(Instruction&, int); void h_ISMULH_M(Instruction&, int); void h_IMUL_RCP(Instruction&, int); void h_INEG_R(Instruction&, int); void h_IXOR_R(Instruction&, int); void h_IXOR_M(Instruction&, int); void h_IROR_R(Instruction&, int); void h_IROL_R(Instruction&, int); void h_ISWAP_R(Instruction&, int); void h_FSWAP_R(Instruction&, int); void h_FADD_R(Instruction&, int); void h_FADD_M(Instruction&, int); void h_FSUB_R(Instruction&, int); void h_FSUB_M(Instruction&, int); void h_FSCAL_R(Instruction&, int); void h_FMUL_R(Instruction&, int); void h_FDIV_M(Instruction&, int); void h_FSQRT_R(Instruction&, int); void h_CBRANCH(Instruction&, int); void h_CFROUND(Instruction&, int); void h_ISTORE(Instruction&, int); void h_NOP(Instruction&, int); }; }RandomX-1.1.10/src/jit_compiler_x86_static.S000066400000000000000000000142061414227164600206230ustar00rootroot00000000000000# Copyright (c) 2018-2019, tevador # # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # * Neither the name of the copyright holder nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .intel_syntax noprefix #if defined(__APPLE__) .text #define DECL(x) _##x #else .section .text #define DECL(x) x #endif #if defined(__WIN32__) || defined(__CYGWIN__) #define WINABI #endif .global DECL(randomx_prefetch_scratchpad) .global DECL(randomx_prefetch_scratchpad_end) .global DECL(randomx_program_prologue) .global DECL(randomx_program_loop_begin) .global DECL(randomx_program_loop_load) .global DECL(randomx_program_start) .global DECL(randomx_program_read_dataset) .global DECL(randomx_program_read_dataset_sshash_init) .global DECL(randomx_program_read_dataset_sshash_fin) .global DECL(randomx_program_loop_store) .global DECL(randomx_program_loop_end) .global DECL(randomx_dataset_init) .global DECL(randomx_program_epilogue) .global DECL(randomx_sshash_load) .global DECL(randomx_sshash_prefetch) .global DECL(randomx_sshash_end) .global DECL(randomx_sshash_init) .global DECL(randomx_program_end) .global DECL(randomx_reciprocal_fast) #include "configuration.h" #define RANDOMX_SCRATCHPAD_MASK (RANDOMX_SCRATCHPAD_L3-64) #define RANDOMX_DATASET_BASE_MASK (RANDOMX_DATASET_BASE_SIZE-64) #define RANDOMX_CACHE_MASK (RANDOMX_ARGON_MEMORY*16-1) #define RANDOMX_ALIGN 4096 #define SUPERSCALAR_OFFSET ((((RANDOMX_ALIGN + 32 * RANDOMX_PROGRAM_SIZE) - 1) / (RANDOMX_ALIGN) + 1) * (RANDOMX_ALIGN)) #define db .byte DECL(randomx_prefetch_scratchpad): mov rdx, rax and eax, RANDOMX_SCRATCHPAD_MASK prefetcht0 [rsi+rax] ror rdx, 32 and edx, RANDOMX_SCRATCHPAD_MASK prefetcht0 [rsi+rdx] DECL(randomx_prefetch_scratchpad_end): .balign 64 DECL(randomx_program_prologue): #if defined(WINABI) #include "asm/program_prologue_win64.inc" #else #include "asm/program_prologue_linux.inc" #endif movapd xmm13, xmmword ptr [mantissaMask+rip] movapd xmm14, xmmword ptr [exp240+rip] movapd xmm15, xmmword ptr [scaleMask+rip] mov rdx, rax and eax, RANDOMX_SCRATCHPAD_MASK ror rdx, 32 and edx, RANDOMX_SCRATCHPAD_MASK jmp rx_program_loop_begin .balign 64 #include "asm/program_xmm_constants.inc" .balign 64 DECL(randomx_program_loop_begin): rx_program_loop_begin: nop DECL(randomx_program_loop_load): #include "asm/program_loop_load.inc" DECL(randomx_program_start): nop DECL(randomx_program_read_dataset): #include "asm/program_read_dataset.inc" DECL(randomx_program_read_dataset_sshash_init): #include "asm/program_read_dataset_sshash_init.inc" DECL(randomx_program_read_dataset_sshash_fin): #include "asm/program_read_dataset_sshash_fin.inc" DECL(randomx_program_loop_store): #include "asm/program_loop_store.inc" DECL(randomx_program_loop_end): nop .balign 64 DECL(randomx_dataset_init): rx_dataset_init: push rbx push rbp push r12 push r13 push r14 push r15 #if defined(WINABI) push rdi push rsi mov rdi, qword ptr [rcx] ;# cache->memory mov rsi, rdx ;# dataset mov rbp, r8 ;# block index push r9 ;# max. block index #else mov rdi, qword ptr [rdi] ;# cache->memory ;# dataset in rsi mov rbp, rdx ;# block index push rcx ;# max. block index #endif init_block_loop: prefetchw byte ptr [rsi] mov rbx, rbp .byte 232 ;# 0xE8 = call .int SUPERSCALAR_OFFSET - (call_offset - rx_dataset_init) call_offset: mov qword ptr [rsi+0], r8 mov qword ptr [rsi+8], r9 mov qword ptr [rsi+16], r10 mov qword ptr [rsi+24], r11 mov qword ptr [rsi+32], r12 mov qword ptr [rsi+40], r13 mov qword ptr [rsi+48], r14 mov qword ptr [rsi+56], r15 add rbp, 1 add rsi, 64 cmp rbp, qword ptr [rsp] jb init_block_loop pop rax #if defined(WINABI) pop rsi pop rdi #endif pop r15 pop r14 pop r13 pop r12 pop rbp pop rbx ret .balign 64 DECL(randomx_program_epilogue): #include "asm/program_epilogue_store.inc" #if defined(WINABI) #include "asm/program_epilogue_win64.inc" #else #include "asm/program_epilogue_linux.inc" #endif .balign 64 DECL(randomx_sshash_load): #include "asm/program_sshash_load.inc" DECL(randomx_sshash_prefetch): #include "asm/program_sshash_prefetch.inc" DECL(randomx_sshash_end): nop .balign 64 DECL(randomx_sshash_init): lea r8, [rbx+1] #include "asm/program_sshash_prefetch.inc" imul r8, qword ptr [r0_mul+rip] mov r9, qword ptr [r1_add+rip] xor r9, r8 mov r10, qword ptr [r2_add+rip] xor r10, r8 mov r11, qword ptr [r3_add+rip] xor r11, r8 mov r12, qword ptr [r4_add+rip] xor r12, r8 mov r13, qword ptr [r5_add+rip] xor r13, r8 mov r14, qword ptr [r6_add+rip] xor r14, r8 mov r15, qword ptr [r7_add+rip] xor r15, r8 jmp rx_program_end .balign 64 #include "asm/program_sshash_constants.inc" .balign 64 DECL(randomx_program_end): rx_program_end: nop DECL(randomx_reciprocal_fast): #if !defined(WINABI) mov rcx, rdi #endif #include "asm/randomx_reciprocal.inc" RandomX-1.1.10/src/jit_compiler_x86_static.asm000066400000000000000000000136721414227164600212070ustar00rootroot00000000000000; Copyright (c) 2018-2019, tevador ; ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; * Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; * Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; * Neither the name of the copyright holder nor the ; names of its contributors may be used to endorse or promote products ; derived from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IFDEF RAX _RANDOMX_JITX86_STATIC SEGMENT PAGE READ EXECUTE PUBLIC randomx_prefetch_scratchpad PUBLIC randomx_prefetch_scratchpad_end PUBLIC randomx_program_prologue PUBLIC randomx_program_loop_begin PUBLIC randomx_program_loop_load PUBLIC randomx_program_start PUBLIC randomx_program_read_dataset PUBLIC randomx_program_read_dataset_sshash_init PUBLIC randomx_program_read_dataset_sshash_fin PUBLIC randomx_dataset_init PUBLIC randomx_program_loop_store PUBLIC randomx_program_loop_end PUBLIC randomx_program_epilogue PUBLIC randomx_sshash_load PUBLIC randomx_sshash_prefetch PUBLIC randomx_sshash_end PUBLIC randomx_sshash_init PUBLIC randomx_program_end PUBLIC randomx_reciprocal_fast include asm/configuration.asm RANDOMX_SCRATCHPAD_MASK EQU (RANDOMX_SCRATCHPAD_L3-64) RANDOMX_DATASET_BASE_MASK EQU (RANDOMX_DATASET_BASE_SIZE-64) RANDOMX_CACHE_MASK EQU (RANDOMX_ARGON_MEMORY*16-1) RANDOMX_ALIGN EQU 4096 SUPERSCALAR_OFFSET EQU ((((RANDOMX_ALIGN + 32 * RANDOMX_PROGRAM_SIZE) - 1) / (RANDOMX_ALIGN) + 1) * (RANDOMX_ALIGN)) randomx_prefetch_scratchpad PROC mov rdx, rax and eax, RANDOMX_SCRATCHPAD_MASK prefetcht0 [rsi+rax] ror rdx, 32 and edx, RANDOMX_SCRATCHPAD_MASK prefetcht0 [rsi+rdx] randomx_prefetch_scratchpad ENDP randomx_prefetch_scratchpad_end PROC randomx_prefetch_scratchpad_end ENDP ALIGN 64 randomx_program_prologue PROC include asm/program_prologue_win64.inc movapd xmm13, xmmword ptr [mantissaMask] movapd xmm14, xmmword ptr [exp240] movapd xmm15, xmmword ptr [scaleMask] mov rdx, rax and eax, RANDOMX_SCRATCHPAD_MASK ror rdx, 32 and edx, RANDOMX_SCRATCHPAD_MASK jmp rx_program_loop_begin randomx_program_prologue ENDP ALIGN 64 include asm/program_xmm_constants.inc ALIGN 64 randomx_program_loop_begin PROC rx_program_loop_begin:: nop randomx_program_loop_begin ENDP randomx_program_loop_load PROC include asm/program_loop_load.inc randomx_program_loop_load ENDP randomx_program_start PROC nop randomx_program_start ENDP randomx_program_read_dataset PROC include asm/program_read_dataset.inc randomx_program_read_dataset ENDP randomx_program_read_dataset_sshash_init PROC include asm/program_read_dataset_sshash_init.inc randomx_program_read_dataset_sshash_init ENDP randomx_program_read_dataset_sshash_fin PROC include asm/program_read_dataset_sshash_fin.inc randomx_program_read_dataset_sshash_fin ENDP randomx_program_loop_store PROC include asm/program_loop_store.inc randomx_program_loop_store ENDP randomx_program_loop_end PROC nop randomx_program_loop_end ENDP ALIGN 64 randomx_dataset_init PROC push rbx push rbp push rdi push rsi push r12 push r13 push r14 push r15 mov rdi, qword ptr [rcx] ;# cache->memory mov rsi, rdx ;# dataset mov rbp, r8 ;# block index push r9 ;# max. block index init_block_loop: prefetchw byte ptr [rsi] mov rbx, rbp db 232 ;# 0xE8 = call dd SUPERSCALAR_OFFSET - distance distance equ $ - offset randomx_dataset_init mov qword ptr [rsi+0], r8 mov qword ptr [rsi+8], r9 mov qword ptr [rsi+16], r10 mov qword ptr [rsi+24], r11 mov qword ptr [rsi+32], r12 mov qword ptr [rsi+40], r13 mov qword ptr [rsi+48], r14 mov qword ptr [rsi+56], r15 add rbp, 1 add rsi, 64 cmp rbp, qword ptr [rsp] jb init_block_loop pop r9 pop r15 pop r14 pop r13 pop r12 pop rsi pop rdi pop rbp pop rbx ret randomx_dataset_init ENDP ALIGN 64 randomx_program_epilogue PROC include asm/program_epilogue_store.inc include asm/program_epilogue_win64.inc randomx_program_epilogue ENDP ALIGN 64 randomx_sshash_load PROC include asm/program_sshash_load.inc randomx_sshash_load ENDP randomx_sshash_prefetch PROC include asm/program_sshash_prefetch.inc randomx_sshash_prefetch ENDP randomx_sshash_end PROC nop randomx_sshash_end ENDP ALIGN 64 randomx_sshash_init PROC lea r8, [rbx+1] include asm/program_sshash_prefetch.inc imul r8, qword ptr [r0_mul] mov r9, qword ptr [r1_add] xor r9, r8 mov r10, qword ptr [r2_add] xor r10, r8 mov r11, qword ptr [r3_add] xor r11, r8 mov r12, qword ptr [r4_add] xor r12, r8 mov r13, qword ptr [r5_add] xor r13, r8 mov r14, qword ptr [r6_add] xor r14, r8 mov r15, qword ptr [r7_add] xor r15, r8 jmp rx_program_end randomx_sshash_init ENDP ALIGN 64 include asm/program_sshash_constants.inc ALIGN 64 randomx_program_end PROC rx_program_end:: nop randomx_program_end ENDP randomx_reciprocal_fast PROC include asm/randomx_reciprocal.inc randomx_reciprocal_fast ENDP _RANDOMX_JITX86_STATIC ENDS ENDIF END RandomX-1.1.10/src/jit_compiler_x86_static.hpp000066400000000000000000000042111414227164600212030ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once extern "C" { void randomx_prefetch_scratchpad(); void randomx_prefetch_scratchpad_end(); void randomx_program_prologue(); void randomx_program_loop_begin(); void randomx_program_loop_load(); void randomx_program_start(); void randomx_program_read_dataset(); void randomx_program_read_dataset_sshash_init(); void randomx_program_read_dataset_sshash_fin(); void randomx_program_loop_store(); void randomx_program_loop_end(); void randomx_dataset_init(); void randomx_program_epilogue(); void randomx_sshash_load(); void randomx_sshash_prefetch(); void randomx_sshash_end(); void randomx_sshash_init(); void randomx_program_end(); } RandomX-1.1.10/src/program.hpp000066400000000000000000000046201414227164600161220ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include "common.hpp" #include "instruction.hpp" #include "blake2/endian.h" namespace randomx { struct ProgramConfiguration { uint64_t eMask[2]; uint32_t readReg0, readReg1, readReg2, readReg3; }; class Program { public: Instruction& operator()(int pc) { return programBuffer[pc]; } friend std::ostream& operator<<(std::ostream& os, const Program& p) { p.print(os); return os; } uint64_t getEntropy(int i) { return load64(&entropyBuffer[i]); } uint32_t getSize() { return RANDOMX_PROGRAM_SIZE; } private: void print(std::ostream& os) const { for (int i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) { auto instr = programBuffer[i]; os << instr; } } uint64_t entropyBuffer[16]; Instruction programBuffer[RANDOMX_PROGRAM_SIZE]; }; static_assert(sizeof(Program) % 64 == 0, "Invalid size of class randomx::Program"); } RandomX-1.1.10/src/randomx.cpp000066400000000000000000000312621414227164600161200ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "randomx.h" #include "dataset.hpp" #include "vm_interpreted.hpp" #include "vm_interpreted_light.hpp" #include "vm_compiled.hpp" #include "vm_compiled_light.hpp" #include "blake2/blake2.h" #include "cpu.hpp" #include #include #include extern "C" { randomx_flags randomx_get_flags() { randomx_flags flags = RANDOMX_HAVE_COMPILER ? RANDOMX_FLAG_JIT : RANDOMX_FLAG_DEFAULT; randomx::Cpu cpu; #ifdef RANDOMX_FORCE_SECURE if (flags == RANDOMX_FLAG_JIT) { flags |= RANDOMX_FLAG_SECURE; } #endif if (HAVE_AES && cpu.hasAes()) { flags |= RANDOMX_FLAG_HARD_AES; } if (randomx_argon2_impl_avx2() != nullptr && cpu.hasAvx2()) { flags |= RANDOMX_FLAG_ARGON2_AVX2; } if (randomx_argon2_impl_ssse3() != nullptr && cpu.hasSsse3()) { flags |= RANDOMX_FLAG_ARGON2_SSSE3; } return flags; } randomx_cache *randomx_alloc_cache(randomx_flags flags) { randomx_cache *cache = nullptr; auto impl = randomx::selectArgonImpl(flags); if (impl == nullptr) { return cache; } try { cache = new randomx_cache(); cache->argonImpl = impl; switch ((int)(flags & (RANDOMX_FLAG_JIT | RANDOMX_FLAG_LARGE_PAGES))) { case RANDOMX_FLAG_DEFAULT: cache->dealloc = &randomx::deallocCache; cache->jit = nullptr; cache->initialize = &randomx::initCache; cache->datasetInit = &randomx::initDataset; cache->memory = (uint8_t*)randomx::DefaultAllocator::allocMemory(randomx::CacheSize); break; case RANDOMX_FLAG_JIT: cache->dealloc = &randomx::deallocCache; cache->jit = new randomx::JitCompiler(); cache->initialize = &randomx::initCacheCompile; cache->datasetInit = cache->jit->getDatasetInitFunc(); cache->memory = (uint8_t*)randomx::DefaultAllocator::allocMemory(randomx::CacheSize); break; case RANDOMX_FLAG_LARGE_PAGES: cache->dealloc = &randomx::deallocCache; cache->jit = nullptr; cache->initialize = &randomx::initCache; cache->datasetInit = &randomx::initDataset; cache->memory = (uint8_t*)randomx::LargePageAllocator::allocMemory(randomx::CacheSize); break; case RANDOMX_FLAG_JIT | RANDOMX_FLAG_LARGE_PAGES: cache->dealloc = &randomx::deallocCache; cache->jit = new randomx::JitCompiler(); cache->initialize = &randomx::initCacheCompile; cache->datasetInit = cache->jit->getDatasetInitFunc(); cache->memory = (uint8_t*)randomx::LargePageAllocator::allocMemory(randomx::CacheSize); break; default: UNREACHABLE; } } catch (std::exception &ex) { if (cache != nullptr) { randomx_release_cache(cache); cache = nullptr; } } return cache; } void randomx_init_cache(randomx_cache *cache, const void *key, size_t keySize) { assert(cache != nullptr); assert(keySize == 0 || key != nullptr); std::string cacheKey; cacheKey.assign((const char *)key, keySize); if (cache->cacheKey != cacheKey || !cache->isInitialized()) { cache->initialize(cache, key, keySize); cache->cacheKey = cacheKey; } } void randomx_release_cache(randomx_cache* cache) { assert(cache != nullptr); if (cache->memory != nullptr) { cache->dealloc(cache); } delete cache; } randomx_dataset *randomx_alloc_dataset(randomx_flags flags) { //fail on 32-bit systems if DatasetSize is >= 4 GiB if (randomx::DatasetSize > std::numeric_limits::max()) { return nullptr; } randomx_dataset *dataset = nullptr; try { dataset = new randomx_dataset(); if (flags & RANDOMX_FLAG_LARGE_PAGES) { dataset->dealloc = &randomx::deallocDataset; dataset->memory = (uint8_t*)randomx::LargePageAllocator::allocMemory(randomx::DatasetSize); } else { dataset->dealloc = &randomx::deallocDataset; dataset->memory = (uint8_t*)randomx::DefaultAllocator::allocMemory(randomx::DatasetSize); } } catch (std::exception &ex) { if (dataset != nullptr) { randomx_release_dataset(dataset); dataset = nullptr; } } return dataset; } constexpr unsigned long DatasetItemCount = randomx::DatasetSize / RANDOMX_DATASET_ITEM_SIZE; unsigned long randomx_dataset_item_count() { return DatasetItemCount; } void randomx_init_dataset(randomx_dataset *dataset, randomx_cache *cache, unsigned long startItem, unsigned long itemCount) { assert(dataset != nullptr); assert(cache != nullptr); assert(startItem < DatasetItemCount && itemCount <= DatasetItemCount); assert(startItem + itemCount <= DatasetItemCount); cache->datasetInit(cache, dataset->memory + startItem * randomx::CacheLineSize, startItem, startItem + itemCount); } void *randomx_get_dataset_memory(randomx_dataset *dataset) { assert(dataset != nullptr); return dataset->memory; } void randomx_release_dataset(randomx_dataset *dataset) { assert(dataset != nullptr); dataset->dealloc(dataset); delete dataset; } randomx_vm *randomx_create_vm(randomx_flags flags, randomx_cache *cache, randomx_dataset *dataset) { assert(cache != nullptr || (flags & RANDOMX_FLAG_FULL_MEM)); assert(cache == nullptr || cache->isInitialized()); assert(dataset != nullptr || !(flags & RANDOMX_FLAG_FULL_MEM)); randomx_vm *vm = nullptr; try { switch ((int)(flags & (RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_JIT | RANDOMX_FLAG_HARD_AES | RANDOMX_FLAG_LARGE_PAGES))) { case RANDOMX_FLAG_DEFAULT: vm = new randomx::InterpretedLightVmDefault(); break; case RANDOMX_FLAG_FULL_MEM: vm = new randomx::InterpretedVmDefault(); break; case RANDOMX_FLAG_JIT: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledLightVmDefaultSecure(); } else { vm = new randomx::CompiledLightVmDefault(); } break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_JIT: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledVmDefaultSecure(); } else { vm = new randomx::CompiledVmDefault(); } break; case RANDOMX_FLAG_HARD_AES: vm = new randomx::InterpretedLightVmHardAes(); break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_HARD_AES: vm = new randomx::InterpretedVmHardAes(); break; case RANDOMX_FLAG_JIT | RANDOMX_FLAG_HARD_AES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledLightVmHardAesSecure(); } else { vm = new randomx::CompiledLightVmHardAes(); } break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_JIT | RANDOMX_FLAG_HARD_AES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledVmHardAesSecure(); } else { vm = new randomx::CompiledVmHardAes(); } break; case RANDOMX_FLAG_LARGE_PAGES: vm = new randomx::InterpretedLightVmLargePage(); break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_LARGE_PAGES: vm = new randomx::InterpretedVmLargePage(); break; case RANDOMX_FLAG_JIT | RANDOMX_FLAG_LARGE_PAGES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledLightVmLargePageSecure(); } else { vm = new randomx::CompiledLightVmLargePage(); } break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_JIT | RANDOMX_FLAG_LARGE_PAGES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledVmLargePageSecure(); } else { vm = new randomx::CompiledVmLargePage(); } break; case RANDOMX_FLAG_HARD_AES | RANDOMX_FLAG_LARGE_PAGES: vm = new randomx::InterpretedLightVmLargePageHardAes(); break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_HARD_AES | RANDOMX_FLAG_LARGE_PAGES: vm = new randomx::InterpretedVmLargePageHardAes(); break; case RANDOMX_FLAG_JIT | RANDOMX_FLAG_HARD_AES | RANDOMX_FLAG_LARGE_PAGES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledLightVmLargePageHardAesSecure(); } else { vm = new randomx::CompiledLightVmLargePageHardAes(); } break; case RANDOMX_FLAG_FULL_MEM | RANDOMX_FLAG_JIT | RANDOMX_FLAG_HARD_AES | RANDOMX_FLAG_LARGE_PAGES: if (flags & RANDOMX_FLAG_SECURE) { vm = new randomx::CompiledVmLargePageHardAesSecure(); } else { vm = new randomx::CompiledVmLargePageHardAes(); } break; default: UNREACHABLE; } if(cache != nullptr) { vm->setCache(cache); vm->cacheKey = cache->cacheKey; } if(dataset != nullptr) vm->setDataset(dataset); vm->allocate(); } catch (std::exception &ex) { delete vm; vm = nullptr; } return vm; } void randomx_vm_set_cache(randomx_vm *machine, randomx_cache* cache) { assert(machine != nullptr); assert(cache != nullptr && cache->isInitialized()); if (machine->cacheKey != cache->cacheKey || machine->getMemory() != cache->memory) { machine->setCache(cache); machine->cacheKey = cache->cacheKey; } } void randomx_vm_set_dataset(randomx_vm *machine, randomx_dataset *dataset) { assert(machine != nullptr); assert(dataset != nullptr); machine->setDataset(dataset); } void randomx_destroy_vm(randomx_vm *machine) { assert(machine != nullptr); delete machine; } void randomx_calculate_hash(randomx_vm *machine, const void *input, size_t inputSize, void *output) { assert(machine != nullptr); assert(inputSize == 0 || input != nullptr); assert(output != nullptr); fenv_t fpstate; fegetenv(&fpstate); alignas(16) uint64_t tempHash[8]; int blakeResult = blake2b(tempHash, sizeof(tempHash), input, inputSize, nullptr, 0); assert(blakeResult == 0); machine->initScratchpad(&tempHash); machine->resetRoundingMode(); for (int chain = 0; chain < RANDOMX_PROGRAM_COUNT - 1; ++chain) { machine->run(&tempHash); blakeResult = blake2b(tempHash, sizeof(tempHash), machine->getRegisterFile(), sizeof(randomx::RegisterFile), nullptr, 0); assert(blakeResult == 0); } machine->run(&tempHash); machine->getFinalResult(output, RANDOMX_HASH_SIZE); fesetenv(&fpstate); } void randomx_calculate_hash_first(randomx_vm* machine, const void* input, size_t inputSize) { blake2b(machine->tempHash, sizeof(machine->tempHash), input, inputSize, nullptr, 0); machine->initScratchpad(machine->tempHash); } void randomx_calculate_hash_next(randomx_vm* machine, const void* nextInput, size_t nextInputSize, void* output) { machine->resetRoundingMode(); for (uint32_t chain = 0; chain < RANDOMX_PROGRAM_COUNT - 1; ++chain) { machine->run(machine->tempHash); blake2b(machine->tempHash, sizeof(machine->tempHash), machine->getRegisterFile(), sizeof(randomx::RegisterFile), nullptr, 0); } machine->run(machine->tempHash); // Finish current hash and fill the scratchpad for the next hash at the same time blake2b(machine->tempHash, sizeof(machine->tempHash), nextInput, nextInputSize, nullptr, 0); machine->hashAndFill(output, RANDOMX_HASH_SIZE, machine->tempHash); } void randomx_calculate_hash_last(randomx_vm* machine, void* output) { machine->resetRoundingMode(); for (int chain = 0; chain < RANDOMX_PROGRAM_COUNT - 1; ++chain) { machine->run(machine->tempHash); blake2b(machine->tempHash, sizeof(machine->tempHash), machine->getRegisterFile(), sizeof(randomx::RegisterFile), nullptr, 0); } machine->run(machine->tempHash); machine->getFinalResult(output, RANDOMX_HASH_SIZE); } } RandomX-1.1.10/src/randomx.h000066400000000000000000000271031414227164600155640ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef RANDOMX_H #define RANDOMX_H #include #include #define RANDOMX_HASH_SIZE 32 #define RANDOMX_DATASET_ITEM_SIZE 64 #ifndef RANDOMX_EXPORT #define RANDOMX_EXPORT #endif typedef enum { RANDOMX_FLAG_DEFAULT = 0, RANDOMX_FLAG_LARGE_PAGES = 1, RANDOMX_FLAG_HARD_AES = 2, RANDOMX_FLAG_FULL_MEM = 4, RANDOMX_FLAG_JIT = 8, RANDOMX_FLAG_SECURE = 16, RANDOMX_FLAG_ARGON2_SSSE3 = 32, RANDOMX_FLAG_ARGON2_AVX2 = 64, RANDOMX_FLAG_ARGON2 = 96 } randomx_flags; typedef struct randomx_dataset randomx_dataset; typedef struct randomx_cache randomx_cache; typedef struct randomx_vm randomx_vm; #if defined(__cplusplus) #ifdef __cpp_constexpr #define CONSTEXPR constexpr #else #define CONSTEXPR #endif inline CONSTEXPR randomx_flags operator |(randomx_flags a, randomx_flags b) { return static_cast(static_cast(a) | static_cast(b)); } inline CONSTEXPR randomx_flags operator &(randomx_flags a, randomx_flags b) { return static_cast(static_cast(a) & static_cast(b)); } inline randomx_flags& operator |=(randomx_flags& a, randomx_flags b) { return a = a | b; } extern "C" { #endif /** * @return The recommended flags to be used on the current machine. * Does not include: * RANDOMX_FLAG_LARGE_PAGES * RANDOMX_FLAG_FULL_MEM * RANDOMX_FLAG_SECURE * These flags must be added manually if desired. * On OpenBSD RANDOMX_FLAG_SECURE is enabled by default in JIT mode as W^X is enforced by the OS. */ RANDOMX_EXPORT randomx_flags randomx_get_flags(void); /** * Creates a randomx_cache structure and allocates memory for RandomX Cache. * * @param flags is any combination of these 2 flags (each flag can be set or not set): * RANDOMX_FLAG_LARGE_PAGES - allocate memory in large pages * RANDOMX_FLAG_JIT - create cache structure with JIT compilation support; this makes * subsequent Dataset initialization faster * Optionally, one of these two flags may be selected: * RANDOMX_FLAG_ARGON2_SSSE3 - optimized Argon2 for CPUs with the SSSE3 instruction set * makes subsequent cache initialization faster * RANDOMX_FLAG_ARGON2_AVX2 - optimized Argon2 for CPUs with the AVX2 instruction set * makes subsequent cache initialization faster * * @return Pointer to an allocated randomx_cache structure. * Returns NULL if: * (1) memory allocation fails * (2) the RANDOMX_FLAG_JIT is set and JIT compilation is not supported on the current platform * (3) an invalid or unsupported RANDOMX_FLAG_ARGON2 value is set */ RANDOMX_EXPORT randomx_cache *randomx_alloc_cache(randomx_flags flags); /** * Initializes the cache memory and SuperscalarHash using the provided key value. * Does nothing if called again with the same key value. * * @param cache is a pointer to a previously allocated randomx_cache structure. Must not be NULL. * @param key is a pointer to memory which contains the key value. Must not be NULL. * @param keySize is the number of bytes of the key. */ RANDOMX_EXPORT void randomx_init_cache(randomx_cache *cache, const void *key, size_t keySize); /** * Releases all memory occupied by the randomx_cache structure. * * @param cache is a pointer to a previously allocated randomx_cache structure. */ RANDOMX_EXPORT void randomx_release_cache(randomx_cache* cache); /** * Creates a randomx_dataset structure and allocates memory for RandomX Dataset. * * @param flags is the initialization flags. Only one flag is supported (can be set or not set): * RANDOMX_FLAG_LARGE_PAGES - allocate memory in large pages * * @return Pointer to an allocated randomx_dataset structure. * NULL is returned if memory allocation fails. */ RANDOMX_EXPORT randomx_dataset *randomx_alloc_dataset(randomx_flags flags); /** * Gets the number of items contained in the dataset. * * @return the number of items contained in the dataset. */ RANDOMX_EXPORT unsigned long randomx_dataset_item_count(void); /** * Initializes dataset items. * * Note: In order to use the Dataset, all items from 0 to (randomx_dataset_item_count() - 1) must be initialized. * This may be done by several calls to this function using non-overlapping item sequences. * * @param dataset is a pointer to a previously allocated randomx_dataset structure. Must not be NULL. * @param cache is a pointer to a previously allocated and initialized randomx_cache structure. Must not be NULL. * @param startItem is the item number where intialization should start. * @param itemCount is the number of items that should be initialized. */ RANDOMX_EXPORT void randomx_init_dataset(randomx_dataset *dataset, randomx_cache *cache, unsigned long startItem, unsigned long itemCount); /** * Returns a pointer to the internal memory buffer of the dataset structure. The size * of the internal memory buffer is randomx_dataset_item_count() * RANDOMX_DATASET_ITEM_SIZE. * * @param dataset is a pointer to a previously allocated randomx_dataset structure. Must not be NULL. * * @return Pointer to the internal memory buffer of the dataset structure. */ RANDOMX_EXPORT void *randomx_get_dataset_memory(randomx_dataset *dataset); /** * Releases all memory occupied by the randomx_dataset structure. * * @param dataset is a pointer to a previously allocated randomx_dataset structure. */ RANDOMX_EXPORT void randomx_release_dataset(randomx_dataset *dataset); /** * Creates and initializes a RandomX virtual machine. * * @param flags is any combination of these 5 flags (each flag can be set or not set): * RANDOMX_FLAG_LARGE_PAGES - allocate scratchpad memory in large pages * RANDOMX_FLAG_HARD_AES - virtual machine will use hardware accelerated AES * RANDOMX_FLAG_FULL_MEM - virtual machine will use the full dataset * RANDOMX_FLAG_JIT - virtual machine will use a JIT compiler * RANDOMX_FLAG_SECURE - when combined with RANDOMX_FLAG_JIT, the JIT pages are never * writable and executable at the same time (W^X policy) * The numeric values of the first 4 flags are ordered so that a higher value will provide * faster hash calculation and a lower numeric value will provide higher portability. * Using RANDOMX_FLAG_DEFAULT (all flags not set) works on all platforms, but is the slowest. * @param cache is a pointer to an initialized randomx_cache structure. Can be * NULL if RANDOMX_FLAG_FULL_MEM is set. * @param dataset is a pointer to a randomx_dataset structure. Can be NULL * if RANDOMX_FLAG_FULL_MEM is not set. * * @return Pointer to an initialized randomx_vm structure. * Returns NULL if: * (1) Scratchpad memory allocation fails. * (2) The requested initialization flags are not supported on the current platform. * (3) cache parameter is NULL and RANDOMX_FLAG_FULL_MEM is not set * (4) dataset parameter is NULL and RANDOMX_FLAG_FULL_MEM is set */ RANDOMX_EXPORT randomx_vm *randomx_create_vm(randomx_flags flags, randomx_cache *cache, randomx_dataset *dataset); /** * Reinitializes a virtual machine with a new Cache. This function should be called anytime * the Cache is reinitialized with a new key. Does nothing if called with a Cache containing * the same key value as already set. * * @param machine is a pointer to a randomx_vm structure that was initialized * without RANDOMX_FLAG_FULL_MEM. Must not be NULL. * @param cache is a pointer to an initialized randomx_cache structure. Must not be NULL. */ RANDOMX_EXPORT void randomx_vm_set_cache(randomx_vm *machine, randomx_cache* cache); /** * Reinitializes a virtual machine with a new Dataset. * * @param machine is a pointer to a randomx_vm structure that was initialized * with RANDOMX_FLAG_FULL_MEM. Must not be NULL. * @param dataset is a pointer to an initialized randomx_dataset structure. Must not be NULL. */ RANDOMX_EXPORT void randomx_vm_set_dataset(randomx_vm *machine, randomx_dataset *dataset); /** * Releases all memory occupied by the randomx_vm structure. * * @param machine is a pointer to a previously created randomx_vm structure. */ RANDOMX_EXPORT void randomx_destroy_vm(randomx_vm *machine); /** * Calculates a RandomX hash value. * * @param machine is a pointer to a randomx_vm structure. Must not be NULL. * @param input is a pointer to memory to be hashed. Must not be NULL. * @param inputSize is the number of bytes to be hashed. * @param output is a pointer to memory where the hash will be stored. Must not * be NULL and at least RANDOMX_HASH_SIZE bytes must be available for writing. */ RANDOMX_EXPORT void randomx_calculate_hash(randomx_vm *machine, const void *input, size_t inputSize, void *output); /** * Set of functions used to calculate multiple RandomX hashes more efficiently. * randomx_calculate_hash_first will begin a hash calculation. * randomx_calculate_hash_next will output the hash value of the previous input * and begin the calculation of the next hash. * randomx_calculate_hash_last will output the hash value of the previous input. * * WARNING: These functions may alter the floating point rounding mode of the calling thread. * * @param machine is a pointer to a randomx_vm structure. Must not be NULL. * @param input is a pointer to memory to be hashed. Must not be NULL. * @param inputSize is the number of bytes to be hashed. * @param nextInput is a pointer to memory to be hashed for the next hash. Must not be NULL. * @param nextInputSize is the number of bytes to be hashed for the next hash. * @param output is a pointer to memory where the hash will be stored. Must not * be NULL and at least RANDOMX_HASH_SIZE bytes must be available for writing. */ RANDOMX_EXPORT void randomx_calculate_hash_first(randomx_vm* machine, const void* input, size_t inputSize); RANDOMX_EXPORT void randomx_calculate_hash_next(randomx_vm* machine, const void* nextInput, size_t nextInputSize, void* output); RANDOMX_EXPORT void randomx_calculate_hash_last(randomx_vm* machine, void* output); #if defined(__cplusplus) } #endif #endif RandomX-1.1.10/src/reciprocal.c000066400000000000000000000047141414227164600162350ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include "reciprocal.h" /* Calculates rcp = 2**x / divisor for highest integer x such that rcp < 2**64. divisor must not be 0 or a power of 2 Equivalent x86 assembly (divisor in rcx): mov edx, 1 mov r8, rcx xor eax, eax bsr rcx, rcx shl rdx, cl div r8 ret */ uint64_t randomx_reciprocal(uint64_t divisor) { assert(divisor != 0); const uint64_t p2exp63 = 1ULL << 63; uint64_t quotient = p2exp63 / divisor, remainder = p2exp63 % divisor; unsigned bsr = 0; //highest set bit in divisor for (uint64_t bit = divisor; bit > 0; bit >>= 1) bsr++; for (unsigned shift = 0; shift < bsr; shift++) { if (remainder >= divisor - remainder) { quotient = quotient * 2 + 1; remainder = remainder * 2 - divisor; } else { quotient = quotient * 2; remainder = remainder * 2; } } return quotient; } #if !RANDOMX_HAVE_FAST_RECIPROCAL uint64_t randomx_reciprocal_fast(uint64_t divisor) { return randomx_reciprocal(divisor); } #endif RandomX-1.1.10/src/reciprocal.h000066400000000000000000000035011414227164600162330ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #if defined(_M_X64) || defined(__x86_64__) #define RANDOMX_HAVE_FAST_RECIPROCAL 1 #else #define RANDOMX_HAVE_FAST_RECIPROCAL 0 #endif #if defined(__cplusplus) extern "C" { #endif uint64_t randomx_reciprocal(uint64_t); uint64_t randomx_reciprocal_fast(uint64_t); #if defined(__cplusplus) } #endif RandomX-1.1.10/src/soft_aes.cpp000066400000000000000000000720071414227164600162550ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "soft_aes.h" alignas(16) const uint8_t sbox[256] = { 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16, }; alignas(16) const uint32_t lutEnc0[256] = { 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, 0x5c343468, 0xf4a5a551, 0x34e5e5d1, 0x08f1f1f9, 0x937171e2, 0x73d8d8ab, 0x53313162, 0x3f15152a, 0x0c040408, 0x52c7c795, 0x65232346, 0x5ec3c39d, 0x28181830, 0xa1969637, 0x0f05050a, 0xb59a9a2f, 0x0907070e, 0x36121224, 0x9b80801b, 0x3de2e2df, 0x26ebebcd, 0x6927274e, 0xcdb2b27f, 0x9f7575ea, 0x1b090912, 0x9e83831d, 0x742c2c58, 0x2e1a1a34, 0x2d1b1b36, 0xb26e6edc, 0xee5a5ab4, 0xfba0a05b, 0xf65252a4, 0x4d3b3b76, 0x61d6d6b7, 0xceb3b37d, 0x7b292952, 0x3ee3e3dd, 0x712f2f5e, 0x97848413, 0xf55353a6, 0x68d1d1b9, 0x00000000, 0x2cededc1, 0x60202040, 0x1ffcfce3, 0xc8b1b179, 0xed5b5bb6, 0xbe6a6ad4, 0x46cbcb8d, 0xd9bebe67, 0x4b393972, 0xde4a4a94, 0xd44c4c98, 0xe85858b0, 0x4acfcf85, 0x6bd0d0bb, 0x2aefefc5, 0xe5aaaa4f, 0x16fbfbed, 0xc5434386, 0xd74d4d9a, 0x55333366, 0x94858511, 0xcf45458a, 0x10f9f9e9, 0x06020204, 0x817f7ffe, 0xf05050a0, 0x443c3c78, 0xba9f9f25, 0xe3a8a84b, 0xf35151a2, 0xfea3a35d, 0xc0404080, 0x8a8f8f05, 0xad92923f, 0xbc9d9d21, 0x48383870, 0x04f5f5f1, 0xdfbcbc63, 0xc1b6b677, 0x75dadaaf, 0x63212142, 0x30101020, 0x1affffe5, 0x0ef3f3fd, 0x6dd2d2bf, 0x4ccdcd81, 0x140c0c18, 0x35131326, 0x2fececc3, 0xe15f5fbe, 0xa2979735, 0xcc444488, 0x3917172e, 0x57c4c493, 0xf2a7a755, 0x827e7efc, 0x473d3d7a, 0xac6464c8, 0xe75d5dba, 0x2b191932, 0x957373e6, 0xa06060c0, 0x98818119, 0xd14f4f9e, 0x7fdcdca3, 0x66222244, 0x7e2a2a54, 0xab90903b, 0x8388880b, 0xca46468c, 0x29eeeec7, 0xd3b8b86b, 0x3c141428, 0x79dedea7, 0xe25e5ebc, 0x1d0b0b16, 0x76dbdbad, 0x3be0e0db, 0x56323264, 0x4e3a3a74, 0x1e0a0a14, 0xdb494992, 0x0a06060c, 0x6c242448, 0xe45c5cb8, 0x5dc2c29f, 0x6ed3d3bd, 0xefacac43, 0xa66262c4, 0xa8919139, 0xa4959531, 0x37e4e4d3, 0x8b7979f2, 0x32e7e7d5, 0x43c8c88b, 0x5937376e, 0xb76d6dda, 0x8c8d8d01, 0x64d5d5b1, 0xd24e4e9c, 0xe0a9a949, 0xb46c6cd8, 0xfa5656ac, 0x07f4f4f3, 0x25eaeacf, 0xaf6565ca, 0x8e7a7af4, 0xe9aeae47, 0x18080810, 0xd5baba6f, 0x887878f0, 0x6f25254a, 0x722e2e5c, 0x241c1c38, 0xf1a6a657, 0xc7b4b473, 0x51c6c697, 0x23e8e8cb, 0x7cdddda1, 0x9c7474e8, 0x211f1f3e, 0xdd4b4b96, 0xdcbdbd61, 0x868b8b0d, 0x858a8a0f, 0x907070e0, 0x423e3e7c, 0xc4b5b571, 0xaa6666cc, 0xd8484890, 0x05030306, 0x01f6f6f7, 0x120e0e1c, 0xa36161c2, 0x5f35356a, 0xf95757ae, 0xd0b9b969, 0x91868617, 0x58c1c199, 0x271d1d3a, 0xb99e9e27, 0x38e1e1d9, 0x13f8f8eb, 0xb398982b, 0x33111122, 0xbb6969d2, 0x70d9d9a9, 0x898e8e07, 0xa7949433, 0xb69b9b2d, 0x221e1e3c, 0x92878715, 0x20e9e9c9, 0x49cece87, 0xff5555aa, 0x78282850, 0x7adfdfa5, 0x8f8c8c03, 0xf8a1a159, 0x80898909, 0x170d0d1a, 0xdabfbf65, 0x31e6e6d7, 0xc6424284, 0xb86868d0, 0xc3414182, 0xb0999929, 0x772d2d5a, 0x110f0f1e, 0xcbb0b07b, 0xfc5454a8, 0xd6bbbb6d, 0x3a16162c, }; alignas(16) const uint32_t lutEnc1[256] = { 0x6363c6a5, 0x7c7cf884, 0x7777ee99, 0x7b7bf68d, 0xf2f2ff0d, 0x6b6bd6bd, 0x6f6fdeb1, 0xc5c59154, 0x30306050, 0x01010203, 0x6767cea9, 0x2b2b567d, 0xfefee719, 0xd7d7b562, 0xabab4de6, 0x7676ec9a, 0xcaca8f45, 0x82821f9d, 0xc9c98940, 0x7d7dfa87, 0xfafaef15, 0x5959b2eb, 0x47478ec9, 0xf0f0fb0b, 0xadad41ec, 0xd4d4b367, 0xa2a25ffd, 0xafaf45ea, 0x9c9c23bf, 0xa4a453f7, 0x7272e496, 0xc0c09b5b, 0xb7b775c2, 0xfdfde11c, 0x93933dae, 0x26264c6a, 0x36366c5a, 0x3f3f7e41, 0xf7f7f502, 0xcccc834f, 0x3434685c, 0xa5a551f4, 0xe5e5d134, 0xf1f1f908, 0x7171e293, 0xd8d8ab73, 0x31316253, 0x15152a3f, 0x0404080c, 0xc7c79552, 0x23234665, 0xc3c39d5e, 0x18183028, 0x969637a1, 0x05050a0f, 0x9a9a2fb5, 0x07070e09, 0x12122436, 0x80801b9b, 0xe2e2df3d, 0xebebcd26, 0x27274e69, 0xb2b27fcd, 0x7575ea9f, 0x0909121b, 0x83831d9e, 0x2c2c5874, 0x1a1a342e, 0x1b1b362d, 0x6e6edcb2, 0x5a5ab4ee, 0xa0a05bfb, 0x5252a4f6, 0x3b3b764d, 0xd6d6b761, 0xb3b37dce, 0x2929527b, 0xe3e3dd3e, 0x2f2f5e71, 0x84841397, 0x5353a6f5, 0xd1d1b968, 0x00000000, 0xededc12c, 0x20204060, 0xfcfce31f, 0xb1b179c8, 0x5b5bb6ed, 0x6a6ad4be, 0xcbcb8d46, 0xbebe67d9, 0x3939724b, 0x4a4a94de, 0x4c4c98d4, 0x5858b0e8, 0xcfcf854a, 0xd0d0bb6b, 0xefefc52a, 0xaaaa4fe5, 0xfbfbed16, 0x434386c5, 0x4d4d9ad7, 0x33336655, 0x85851194, 0x45458acf, 0xf9f9e910, 0x02020406, 0x7f7ffe81, 0x5050a0f0, 0x3c3c7844, 0x9f9f25ba, 0xa8a84be3, 0x5151a2f3, 0xa3a35dfe, 0x404080c0, 0x8f8f058a, 0x92923fad, 0x9d9d21bc, 0x38387048, 0xf5f5f104, 0xbcbc63df, 0xb6b677c1, 0xdadaaf75, 0x21214263, 0x10102030, 0xffffe51a, 0xf3f3fd0e, 0xd2d2bf6d, 0xcdcd814c, 0x0c0c1814, 0x13132635, 0xececc32f, 0x5f5fbee1, 0x979735a2, 0x444488cc, 0x17172e39, 0xc4c49357, 0xa7a755f2, 0x7e7efc82, 0x3d3d7a47, 0x6464c8ac, 0x5d5dbae7, 0x1919322b, 0x7373e695, 0x6060c0a0, 0x81811998, 0x4f4f9ed1, 0xdcdca37f, 0x22224466, 0x2a2a547e, 0x90903bab, 0x88880b83, 0x46468cca, 0xeeeec729, 0xb8b86bd3, 0x1414283c, 0xdedea779, 0x5e5ebce2, 0x0b0b161d, 0xdbdbad76, 0xe0e0db3b, 0x32326456, 0x3a3a744e, 0x0a0a141e, 0x494992db, 0x06060c0a, 0x2424486c, 0x5c5cb8e4, 0xc2c29f5d, 0xd3d3bd6e, 0xacac43ef, 0x6262c4a6, 0x919139a8, 0x959531a4, 0xe4e4d337, 0x7979f28b, 0xe7e7d532, 0xc8c88b43, 0x37376e59, 0x6d6ddab7, 0x8d8d018c, 0xd5d5b164, 0x4e4e9cd2, 0xa9a949e0, 0x6c6cd8b4, 0x5656acfa, 0xf4f4f307, 0xeaeacf25, 0x6565caaf, 0x7a7af48e, 0xaeae47e9, 0x08081018, 0xbaba6fd5, 0x7878f088, 0x25254a6f, 0x2e2e5c72, 0x1c1c3824, 0xa6a657f1, 0xb4b473c7, 0xc6c69751, 0xe8e8cb23, 0xdddda17c, 0x7474e89c, 0x1f1f3e21, 0x4b4b96dd, 0xbdbd61dc, 0x8b8b0d86, 0x8a8a0f85, 0x7070e090, 0x3e3e7c42, 0xb5b571c4, 0x6666ccaa, 0x484890d8, 0x03030605, 0xf6f6f701, 0x0e0e1c12, 0x6161c2a3, 0x35356a5f, 0x5757aef9, 0xb9b969d0, 0x86861791, 0xc1c19958, 0x1d1d3a27, 0x9e9e27b9, 0xe1e1d938, 0xf8f8eb13, 0x98982bb3, 0x11112233, 0x6969d2bb, 0xd9d9a970, 0x8e8e0789, 0x949433a7, 0x9b9b2db6, 0x1e1e3c22, 0x87871592, 0xe9e9c920, 0xcece8749, 0x5555aaff, 0x28285078, 0xdfdfa57a, 0x8c8c038f, 0xa1a159f8, 0x89890980, 0x0d0d1a17, 0xbfbf65da, 0xe6e6d731, 0x424284c6, 0x6868d0b8, 0x414182c3, 0x999929b0, 0x2d2d5a77, 0x0f0f1e11, 0xb0b07bcb, 0x5454a8fc, 0xbbbb6dd6, 0x16162c3a, }; alignas(16) const uint32_t lutEnc2[256] = { 0x63c6a563, 0x7cf8847c, 0x77ee9977, 0x7bf68d7b, 0xf2ff0df2, 0x6bd6bd6b, 0x6fdeb16f, 0xc59154c5, 0x30605030, 0x01020301, 0x67cea967, 0x2b567d2b, 0xfee719fe, 0xd7b562d7, 0xab4de6ab, 0x76ec9a76, 0xca8f45ca, 0x821f9d82, 0xc98940c9, 0x7dfa877d, 0xfaef15fa, 0x59b2eb59, 0x478ec947, 0xf0fb0bf0, 0xad41ecad, 0xd4b367d4, 0xa25ffda2, 0xaf45eaaf, 0x9c23bf9c, 0xa453f7a4, 0x72e49672, 0xc09b5bc0, 0xb775c2b7, 0xfde11cfd, 0x933dae93, 0x264c6a26, 0x366c5a36, 0x3f7e413f, 0xf7f502f7, 0xcc834fcc, 0x34685c34, 0xa551f4a5, 0xe5d134e5, 0xf1f908f1, 0x71e29371, 0xd8ab73d8, 0x31625331, 0x152a3f15, 0x04080c04, 0xc79552c7, 0x23466523, 0xc39d5ec3, 0x18302818, 0x9637a196, 0x050a0f05, 0x9a2fb59a, 0x070e0907, 0x12243612, 0x801b9b80, 0xe2df3de2, 0xebcd26eb, 0x274e6927, 0xb27fcdb2, 0x75ea9f75, 0x09121b09, 0x831d9e83, 0x2c58742c, 0x1a342e1a, 0x1b362d1b, 0x6edcb26e, 0x5ab4ee5a, 0xa05bfba0, 0x52a4f652, 0x3b764d3b, 0xd6b761d6, 0xb37dceb3, 0x29527b29, 0xe3dd3ee3, 0x2f5e712f, 0x84139784, 0x53a6f553, 0xd1b968d1, 0x00000000, 0xedc12ced, 0x20406020, 0xfce31ffc, 0xb179c8b1, 0x5bb6ed5b, 0x6ad4be6a, 0xcb8d46cb, 0xbe67d9be, 0x39724b39, 0x4a94de4a, 0x4c98d44c, 0x58b0e858, 0xcf854acf, 0xd0bb6bd0, 0xefc52aef, 0xaa4fe5aa, 0xfbed16fb, 0x4386c543, 0x4d9ad74d, 0x33665533, 0x85119485, 0x458acf45, 0xf9e910f9, 0x02040602, 0x7ffe817f, 0x50a0f050, 0x3c78443c, 0x9f25ba9f, 0xa84be3a8, 0x51a2f351, 0xa35dfea3, 0x4080c040, 0x8f058a8f, 0x923fad92, 0x9d21bc9d, 0x38704838, 0xf5f104f5, 0xbc63dfbc, 0xb677c1b6, 0xdaaf75da, 0x21426321, 0x10203010, 0xffe51aff, 0xf3fd0ef3, 0xd2bf6dd2, 0xcd814ccd, 0x0c18140c, 0x13263513, 0xecc32fec, 0x5fbee15f, 0x9735a297, 0x4488cc44, 0x172e3917, 0xc49357c4, 0xa755f2a7, 0x7efc827e, 0x3d7a473d, 0x64c8ac64, 0x5dbae75d, 0x19322b19, 0x73e69573, 0x60c0a060, 0x81199881, 0x4f9ed14f, 0xdca37fdc, 0x22446622, 0x2a547e2a, 0x903bab90, 0x880b8388, 0x468cca46, 0xeec729ee, 0xb86bd3b8, 0x14283c14, 0xdea779de, 0x5ebce25e, 0x0b161d0b, 0xdbad76db, 0xe0db3be0, 0x32645632, 0x3a744e3a, 0x0a141e0a, 0x4992db49, 0x060c0a06, 0x24486c24, 0x5cb8e45c, 0xc29f5dc2, 0xd3bd6ed3, 0xac43efac, 0x62c4a662, 0x9139a891, 0x9531a495, 0xe4d337e4, 0x79f28b79, 0xe7d532e7, 0xc88b43c8, 0x376e5937, 0x6ddab76d, 0x8d018c8d, 0xd5b164d5, 0x4e9cd24e, 0xa949e0a9, 0x6cd8b46c, 0x56acfa56, 0xf4f307f4, 0xeacf25ea, 0x65caaf65, 0x7af48e7a, 0xae47e9ae, 0x08101808, 0xba6fd5ba, 0x78f08878, 0x254a6f25, 0x2e5c722e, 0x1c38241c, 0xa657f1a6, 0xb473c7b4, 0xc69751c6, 0xe8cb23e8, 0xdda17cdd, 0x74e89c74, 0x1f3e211f, 0x4b96dd4b, 0xbd61dcbd, 0x8b0d868b, 0x8a0f858a, 0x70e09070, 0x3e7c423e, 0xb571c4b5, 0x66ccaa66, 0x4890d848, 0x03060503, 0xf6f701f6, 0x0e1c120e, 0x61c2a361, 0x356a5f35, 0x57aef957, 0xb969d0b9, 0x86179186, 0xc19958c1, 0x1d3a271d, 0x9e27b99e, 0xe1d938e1, 0xf8eb13f8, 0x982bb398, 0x11223311, 0x69d2bb69, 0xd9a970d9, 0x8e07898e, 0x9433a794, 0x9b2db69b, 0x1e3c221e, 0x87159287, 0xe9c920e9, 0xce8749ce, 0x55aaff55, 0x28507828, 0xdfa57adf, 0x8c038f8c, 0xa159f8a1, 0x89098089, 0x0d1a170d, 0xbf65dabf, 0xe6d731e6, 0x4284c642, 0x68d0b868, 0x4182c341, 0x9929b099, 0x2d5a772d, 0x0f1e110f, 0xb07bcbb0, 0x54a8fc54, 0xbb6dd6bb, 0x162c3a16, }; alignas(16) const uint32_t lutEnc3[256] = { 0xc6a56363, 0xf8847c7c, 0xee997777, 0xf68d7b7b, 0xff0df2f2, 0xd6bd6b6b, 0xdeb16f6f, 0x9154c5c5, 0x60503030, 0x02030101, 0xcea96767, 0x567d2b2b, 0xe719fefe, 0xb562d7d7, 0x4de6abab, 0xec9a7676, 0x8f45caca, 0x1f9d8282, 0x8940c9c9, 0xfa877d7d, 0xef15fafa, 0xb2eb5959, 0x8ec94747, 0xfb0bf0f0, 0x41ecadad, 0xb367d4d4, 0x5ffda2a2, 0x45eaafaf, 0x23bf9c9c, 0x53f7a4a4, 0xe4967272, 0x9b5bc0c0, 0x75c2b7b7, 0xe11cfdfd, 0x3dae9393, 0x4c6a2626, 0x6c5a3636, 0x7e413f3f, 0xf502f7f7, 0x834fcccc, 0x685c3434, 0x51f4a5a5, 0xd134e5e5, 0xf908f1f1, 0xe2937171, 0xab73d8d8, 0x62533131, 0x2a3f1515, 0x080c0404, 0x9552c7c7, 0x46652323, 0x9d5ec3c3, 0x30281818, 0x37a19696, 0x0a0f0505, 0x2fb59a9a, 0x0e090707, 0x24361212, 0x1b9b8080, 0xdf3de2e2, 0xcd26ebeb, 0x4e692727, 0x7fcdb2b2, 0xea9f7575, 0x121b0909, 0x1d9e8383, 0x58742c2c, 0x342e1a1a, 0x362d1b1b, 0xdcb26e6e, 0xb4ee5a5a, 0x5bfba0a0, 0xa4f65252, 0x764d3b3b, 0xb761d6d6, 0x7dceb3b3, 0x527b2929, 0xdd3ee3e3, 0x5e712f2f, 0x13978484, 0xa6f55353, 0xb968d1d1, 0x00000000, 0xc12ceded, 0x40602020, 0xe31ffcfc, 0x79c8b1b1, 0xb6ed5b5b, 0xd4be6a6a, 0x8d46cbcb, 0x67d9bebe, 0x724b3939, 0x94de4a4a, 0x98d44c4c, 0xb0e85858, 0x854acfcf, 0xbb6bd0d0, 0xc52aefef, 0x4fe5aaaa, 0xed16fbfb, 0x86c54343, 0x9ad74d4d, 0x66553333, 0x11948585, 0x8acf4545, 0xe910f9f9, 0x04060202, 0xfe817f7f, 0xa0f05050, 0x78443c3c, 0x25ba9f9f, 0x4be3a8a8, 0xa2f35151, 0x5dfea3a3, 0x80c04040, 0x058a8f8f, 0x3fad9292, 0x21bc9d9d, 0x70483838, 0xf104f5f5, 0x63dfbcbc, 0x77c1b6b6, 0xaf75dada, 0x42632121, 0x20301010, 0xe51affff, 0xfd0ef3f3, 0xbf6dd2d2, 0x814ccdcd, 0x18140c0c, 0x26351313, 0xc32fecec, 0xbee15f5f, 0x35a29797, 0x88cc4444, 0x2e391717, 0x9357c4c4, 0x55f2a7a7, 0xfc827e7e, 0x7a473d3d, 0xc8ac6464, 0xbae75d5d, 0x322b1919, 0xe6957373, 0xc0a06060, 0x19988181, 0x9ed14f4f, 0xa37fdcdc, 0x44662222, 0x547e2a2a, 0x3bab9090, 0x0b838888, 0x8cca4646, 0xc729eeee, 0x6bd3b8b8, 0x283c1414, 0xa779dede, 0xbce25e5e, 0x161d0b0b, 0xad76dbdb, 0xdb3be0e0, 0x64563232, 0x744e3a3a, 0x141e0a0a, 0x92db4949, 0x0c0a0606, 0x486c2424, 0xb8e45c5c, 0x9f5dc2c2, 0xbd6ed3d3, 0x43efacac, 0xc4a66262, 0x39a89191, 0x31a49595, 0xd337e4e4, 0xf28b7979, 0xd532e7e7, 0x8b43c8c8, 0x6e593737, 0xdab76d6d, 0x018c8d8d, 0xb164d5d5, 0x9cd24e4e, 0x49e0a9a9, 0xd8b46c6c, 0xacfa5656, 0xf307f4f4, 0xcf25eaea, 0xcaaf6565, 0xf48e7a7a, 0x47e9aeae, 0x10180808, 0x6fd5baba, 0xf0887878, 0x4a6f2525, 0x5c722e2e, 0x38241c1c, 0x57f1a6a6, 0x73c7b4b4, 0x9751c6c6, 0xcb23e8e8, 0xa17cdddd, 0xe89c7474, 0x3e211f1f, 0x96dd4b4b, 0x61dcbdbd, 0x0d868b8b, 0x0f858a8a, 0xe0907070, 0x7c423e3e, 0x71c4b5b5, 0xccaa6666, 0x90d84848, 0x06050303, 0xf701f6f6, 0x1c120e0e, 0xc2a36161, 0x6a5f3535, 0xaef95757, 0x69d0b9b9, 0x17918686, 0x9958c1c1, 0x3a271d1d, 0x27b99e9e, 0xd938e1e1, 0xeb13f8f8, 0x2bb39898, 0x22331111, 0xd2bb6969, 0xa970d9d9, 0x07898e8e, 0x33a79494, 0x2db69b9b, 0x3c221e1e, 0x15928787, 0xc920e9e9, 0x8749cece, 0xaaff5555, 0x50782828, 0xa57adfdf, 0x038f8c8c, 0x59f8a1a1, 0x09808989, 0x1a170d0d, 0x65dabfbf, 0xd731e6e6, 0x84c64242, 0xd0b86868, 0x82c34141, 0x29b09999, 0x5a772d2d, 0x1e110f0f, 0x7bcbb0b0, 0xa8fc5454, 0x6dd6bbbb, 0x2c3a1616, }; alignas(16) const uint32_t lutDec0[256] = { 0x50a7f451, 0x5365417e, 0xc3a4171a, 0x965e273a, 0xcb6bab3b, 0xf1459d1f, 0xab58faac, 0x9303e34b, 0x55fa3020, 0xf66d76ad, 0x9176cc88, 0x254c02f5, 0xfcd7e54f, 0xd7cb2ac5, 0x80443526, 0x8fa362b5, 0x495ab1de, 0x671bba25, 0x980eea45, 0xe1c0fe5d, 0x02752fc3, 0x12f04c81, 0xa397468d, 0xc6f9d36b, 0xe75f8f03, 0x959c9215, 0xeb7a6dbf, 0xda595295, 0x2d83bed4, 0xd3217458, 0x2969e049, 0x44c8c98e, 0x6a89c275, 0x78798ef4, 0x6b3e5899, 0xdd71b927, 0xb64fe1be, 0x17ad88f0, 0x66ac20c9, 0xb43ace7d, 0x184adf63, 0x82311ae5, 0x60335197, 0x457f5362, 0xe07764b1, 0x84ae6bbb, 0x1ca081fe, 0x942b08f9, 0x58684870, 0x19fd458f, 0x876cde94, 0xb7f87b52, 0x23d373ab, 0xe2024b72, 0x578f1fe3, 0x2aab5566, 0x0728ebb2, 0x03c2b52f, 0x9a7bc586, 0xa50837d3, 0xf2872830, 0xb2a5bf23, 0xba6a0302, 0x5c8216ed, 0x2b1ccf8a, 0x92b479a7, 0xf0f207f3, 0xa1e2694e, 0xcdf4da65, 0xd5be0506, 0x1f6234d1, 0x8afea6c4, 0x9d532e34, 0xa055f3a2, 0x32e18a05, 0x75ebf6a4, 0x39ec830b, 0xaaef6040, 0x069f715e, 0x51106ebd, 0xf98a213e, 0x3d06dd96, 0xae053edd, 0x46bde64d, 0xb58d5491, 0x055dc471, 0x6fd40604, 0xff155060, 0x24fb9819, 0x97e9bdd6, 0xcc434089, 0x779ed967, 0xbd42e8b0, 0x888b8907, 0x385b19e7, 0xdbeec879, 0x470a7ca1, 0xe90f427c, 0xc91e84f8, 0x00000000, 0x83868009, 0x48ed2b32, 0xac70111e, 0x4e725a6c, 0xfbff0efd, 0x5638850f, 0x1ed5ae3d, 0x27392d36, 0x64d90f0a, 0x21a65c68, 0xd1545b9b, 0x3a2e3624, 0xb1670a0c, 0x0fe75793, 0xd296eeb4, 0x9e919b1b, 0x4fc5c080, 0xa220dc61, 0x694b775a, 0x161a121c, 0x0aba93e2, 0xe52aa0c0, 0x43e0223c, 0x1d171b12, 0x0b0d090e, 0xadc78bf2, 0xb9a8b62d, 0xc8a91e14, 0x8519f157, 0x4c0775af, 0xbbdd99ee, 0xfd607fa3, 0x9f2601f7, 0xbcf5725c, 0xc53b6644, 0x347efb5b, 0x7629438b, 0xdcc623cb, 0x68fcedb6, 0x63f1e4b8, 0xcadc31d7, 0x10856342, 0x40229713, 0x2011c684, 0x7d244a85, 0xf83dbbd2, 0x1132f9ae, 0x6da129c7, 0x4b2f9e1d, 0xf330b2dc, 0xec52860d, 0xd0e3c177, 0x6c16b32b, 0x99b970a9, 0xfa489411, 0x2264e947, 0xc48cfca8, 0x1a3ff0a0, 0xd82c7d56, 0xef903322, 0xc74e4987, 0xc1d138d9, 0xfea2ca8c, 0x360bd498, 0xcf81f5a6, 0x28de7aa5, 0x268eb7da, 0xa4bfad3f, 0xe49d3a2c, 0x0d927850, 0x9bcc5f6a, 0x62467e54, 0xc2138df6, 0xe8b8d890, 0x5ef7392e, 0xf5afc382, 0xbe805d9f, 0x7c93d069, 0xa92dd56f, 0xb31225cf, 0x3b99acc8, 0xa77d1810, 0x6e639ce8, 0x7bbb3bdb, 0x097826cd, 0xf418596e, 0x01b79aec, 0xa89a4f83, 0x656e95e6, 0x7ee6ffaa, 0x08cfbc21, 0xe6e815ef, 0xd99be7ba, 0xce366f4a, 0xd4099fea, 0xd67cb029, 0xafb2a431, 0x31233f2a, 0x3094a5c6, 0xc066a235, 0x37bc4e74, 0xa6ca82fc, 0xb0d090e0, 0x15d8a733, 0x4a9804f1, 0xf7daec41, 0x0e50cd7f, 0x2ff69117, 0x8dd64d76, 0x4db0ef43, 0x544daacc, 0xdf0496e4, 0xe3b5d19e, 0x1b886a4c, 0xb81f2cc1, 0x7f516546, 0x04ea5e9d, 0x5d358c01, 0x737487fa, 0x2e410bfb, 0x5a1d67b3, 0x52d2db92, 0x335610e9, 0x1347d66d, 0x8c61d79a, 0x7a0ca137, 0x8e14f859, 0x893c13eb, 0xee27a9ce, 0x35c961b7, 0xede51ce1, 0x3cb1477a, 0x59dfd29c, 0x3f73f255, 0x79ce1418, 0xbf37c773, 0xeacdf753, 0x5baafd5f, 0x146f3ddf, 0x86db4478, 0x81f3afca, 0x3ec468b9, 0x2c342438, 0x5f40a3c2, 0x72c31d16, 0x0c25e2bc, 0x8b493c28, 0x41950dff, 0x7101a839, 0xdeb30c08, 0x9ce4b4d8, 0x90c15664, 0x6184cb7b, 0x70b632d5, 0x745c6c48, 0x4257b8d0, }; alignas(16) const uint32_t lutDec1[256] = { 0xa7f45150, 0x65417e53, 0xa4171ac3, 0x5e273a96, 0x6bab3bcb, 0x459d1ff1, 0x58faacab, 0x03e34b93, 0xfa302055, 0x6d76adf6, 0x76cc8891, 0x4c02f525, 0xd7e54ffc, 0xcb2ac5d7, 0x44352680, 0xa362b58f, 0x5ab1de49, 0x1bba2567, 0x0eea4598, 0xc0fe5de1, 0x752fc302, 0xf04c8112, 0x97468da3, 0xf9d36bc6, 0x5f8f03e7, 0x9c921595, 0x7a6dbfeb, 0x595295da, 0x83bed42d, 0x217458d3, 0x69e04929, 0xc8c98e44, 0x89c2756a, 0x798ef478, 0x3e58996b, 0x71b927dd, 0x4fe1beb6, 0xad88f017, 0xac20c966, 0x3ace7db4, 0x4adf6318, 0x311ae582, 0x33519760, 0x7f536245, 0x7764b1e0, 0xae6bbb84, 0xa081fe1c, 0x2b08f994, 0x68487058, 0xfd458f19, 0x6cde9487, 0xf87b52b7, 0xd373ab23, 0x024b72e2, 0x8f1fe357, 0xab55662a, 0x28ebb207, 0xc2b52f03, 0x7bc5869a, 0x0837d3a5, 0x872830f2, 0xa5bf23b2, 0x6a0302ba, 0x8216ed5c, 0x1ccf8a2b, 0xb479a792, 0xf207f3f0, 0xe2694ea1, 0xf4da65cd, 0xbe0506d5, 0x6234d11f, 0xfea6c48a, 0x532e349d, 0x55f3a2a0, 0xe18a0532, 0xebf6a475, 0xec830b39, 0xef6040aa, 0x9f715e06, 0x106ebd51, 0x8a213ef9, 0x06dd963d, 0x053eddae, 0xbde64d46, 0x8d5491b5, 0x5dc47105, 0xd406046f, 0x155060ff, 0xfb981924, 0xe9bdd697, 0x434089cc, 0x9ed96777, 0x42e8b0bd, 0x8b890788, 0x5b19e738, 0xeec879db, 0x0a7ca147, 0x0f427ce9, 0x1e84f8c9, 0x00000000, 0x86800983, 0xed2b3248, 0x70111eac, 0x725a6c4e, 0xff0efdfb, 0x38850f56, 0xd5ae3d1e, 0x392d3627, 0xd90f0a64, 0xa65c6821, 0x545b9bd1, 0x2e36243a, 0x670a0cb1, 0xe757930f, 0x96eeb4d2, 0x919b1b9e, 0xc5c0804f, 0x20dc61a2, 0x4b775a69, 0x1a121c16, 0xba93e20a, 0x2aa0c0e5, 0xe0223c43, 0x171b121d, 0x0d090e0b, 0xc78bf2ad, 0xa8b62db9, 0xa91e14c8, 0x19f15785, 0x0775af4c, 0xdd99eebb, 0x607fa3fd, 0x2601f79f, 0xf5725cbc, 0x3b6644c5, 0x7efb5b34, 0x29438b76, 0xc623cbdc, 0xfcedb668, 0xf1e4b863, 0xdc31d7ca, 0x85634210, 0x22971340, 0x11c68420, 0x244a857d, 0x3dbbd2f8, 0x32f9ae11, 0xa129c76d, 0x2f9e1d4b, 0x30b2dcf3, 0x52860dec, 0xe3c177d0, 0x16b32b6c, 0xb970a999, 0x489411fa, 0x64e94722, 0x8cfca8c4, 0x3ff0a01a, 0x2c7d56d8, 0x903322ef, 0x4e4987c7, 0xd138d9c1, 0xa2ca8cfe, 0x0bd49836, 0x81f5a6cf, 0xde7aa528, 0x8eb7da26, 0xbfad3fa4, 0x9d3a2ce4, 0x9278500d, 0xcc5f6a9b, 0x467e5462, 0x138df6c2, 0xb8d890e8, 0xf7392e5e, 0xafc382f5, 0x805d9fbe, 0x93d0697c, 0x2dd56fa9, 0x1225cfb3, 0x99acc83b, 0x7d1810a7, 0x639ce86e, 0xbb3bdb7b, 0x7826cd09, 0x18596ef4, 0xb79aec01, 0x9a4f83a8, 0x6e95e665, 0xe6ffaa7e, 0xcfbc2108, 0xe815efe6, 0x9be7bad9, 0x366f4ace, 0x099fead4, 0x7cb029d6, 0xb2a431af, 0x233f2a31, 0x94a5c630, 0x66a235c0, 0xbc4e7437, 0xca82fca6, 0xd090e0b0, 0xd8a73315, 0x9804f14a, 0xdaec41f7, 0x50cd7f0e, 0xf691172f, 0xd64d768d, 0xb0ef434d, 0x4daacc54, 0x0496e4df, 0xb5d19ee3, 0x886a4c1b, 0x1f2cc1b8, 0x5165467f, 0xea5e9d04, 0x358c015d, 0x7487fa73, 0x410bfb2e, 0x1d67b35a, 0xd2db9252, 0x5610e933, 0x47d66d13, 0x61d79a8c, 0x0ca1377a, 0x14f8598e, 0x3c13eb89, 0x27a9ceee, 0xc961b735, 0xe51ce1ed, 0xb1477a3c, 0xdfd29c59, 0x73f2553f, 0xce141879, 0x37c773bf, 0xcdf753ea, 0xaafd5f5b, 0x6f3ddf14, 0xdb447886, 0xf3afca81, 0xc468b93e, 0x3424382c, 0x40a3c25f, 0xc31d1672, 0x25e2bc0c, 0x493c288b, 0x950dff41, 0x01a83971, 0xb30c08de, 0xe4b4d89c, 0xc1566490, 0x84cb7b61, 0xb632d570, 0x5c6c4874, 0x57b8d042, }; alignas(16) const uint32_t lutDec2[256] = { 0xf45150a7, 0x417e5365, 0x171ac3a4, 0x273a965e, 0xab3bcb6b, 0x9d1ff145, 0xfaacab58, 0xe34b9303, 0x302055fa, 0x76adf66d, 0xcc889176, 0x02f5254c, 0xe54ffcd7, 0x2ac5d7cb, 0x35268044, 0x62b58fa3, 0xb1de495a, 0xba25671b, 0xea45980e, 0xfe5de1c0, 0x2fc30275, 0x4c8112f0, 0x468da397, 0xd36bc6f9, 0x8f03e75f, 0x9215959c, 0x6dbfeb7a, 0x5295da59, 0xbed42d83, 0x7458d321, 0xe0492969, 0xc98e44c8, 0xc2756a89, 0x8ef47879, 0x58996b3e, 0xb927dd71, 0xe1beb64f, 0x88f017ad, 0x20c966ac, 0xce7db43a, 0xdf63184a, 0x1ae58231, 0x51976033, 0x5362457f, 0x64b1e077, 0x6bbb84ae, 0x81fe1ca0, 0x08f9942b, 0x48705868, 0x458f19fd, 0xde94876c, 0x7b52b7f8, 0x73ab23d3, 0x4b72e202, 0x1fe3578f, 0x55662aab, 0xebb20728, 0xb52f03c2, 0xc5869a7b, 0x37d3a508, 0x2830f287, 0xbf23b2a5, 0x0302ba6a, 0x16ed5c82, 0xcf8a2b1c, 0x79a792b4, 0x07f3f0f2, 0x694ea1e2, 0xda65cdf4, 0x0506d5be, 0x34d11f62, 0xa6c48afe, 0x2e349d53, 0xf3a2a055, 0x8a0532e1, 0xf6a475eb, 0x830b39ec, 0x6040aaef, 0x715e069f, 0x6ebd5110, 0x213ef98a, 0xdd963d06, 0x3eddae05, 0xe64d46bd, 0x5491b58d, 0xc471055d, 0x06046fd4, 0x5060ff15, 0x981924fb, 0xbdd697e9, 0x4089cc43, 0xd967779e, 0xe8b0bd42, 0x8907888b, 0x19e7385b, 0xc879dbee, 0x7ca1470a, 0x427ce90f, 0x84f8c91e, 0x00000000, 0x80098386, 0x2b3248ed, 0x111eac70, 0x5a6c4e72, 0x0efdfbff, 0x850f5638, 0xae3d1ed5, 0x2d362739, 0x0f0a64d9, 0x5c6821a6, 0x5b9bd154, 0x36243a2e, 0x0a0cb167, 0x57930fe7, 0xeeb4d296, 0x9b1b9e91, 0xc0804fc5, 0xdc61a220, 0x775a694b, 0x121c161a, 0x93e20aba, 0xa0c0e52a, 0x223c43e0, 0x1b121d17, 0x090e0b0d, 0x8bf2adc7, 0xb62db9a8, 0x1e14c8a9, 0xf1578519, 0x75af4c07, 0x99eebbdd, 0x7fa3fd60, 0x01f79f26, 0x725cbcf5, 0x6644c53b, 0xfb5b347e, 0x438b7629, 0x23cbdcc6, 0xedb668fc, 0xe4b863f1, 0x31d7cadc, 0x63421085, 0x97134022, 0xc6842011, 0x4a857d24, 0xbbd2f83d, 0xf9ae1132, 0x29c76da1, 0x9e1d4b2f, 0xb2dcf330, 0x860dec52, 0xc177d0e3, 0xb32b6c16, 0x70a999b9, 0x9411fa48, 0xe9472264, 0xfca8c48c, 0xf0a01a3f, 0x7d56d82c, 0x3322ef90, 0x4987c74e, 0x38d9c1d1, 0xca8cfea2, 0xd498360b, 0xf5a6cf81, 0x7aa528de, 0xb7da268e, 0xad3fa4bf, 0x3a2ce49d, 0x78500d92, 0x5f6a9bcc, 0x7e546246, 0x8df6c213, 0xd890e8b8, 0x392e5ef7, 0xc382f5af, 0x5d9fbe80, 0xd0697c93, 0xd56fa92d, 0x25cfb312, 0xacc83b99, 0x1810a77d, 0x9ce86e63, 0x3bdb7bbb, 0x26cd0978, 0x596ef418, 0x9aec01b7, 0x4f83a89a, 0x95e6656e, 0xffaa7ee6, 0xbc2108cf, 0x15efe6e8, 0xe7bad99b, 0x6f4ace36, 0x9fead409, 0xb029d67c, 0xa431afb2, 0x3f2a3123, 0xa5c63094, 0xa235c066, 0x4e7437bc, 0x82fca6ca, 0x90e0b0d0, 0xa73315d8, 0x04f14a98, 0xec41f7da, 0xcd7f0e50, 0x91172ff6, 0x4d768dd6, 0xef434db0, 0xaacc544d, 0x96e4df04, 0xd19ee3b5, 0x6a4c1b88, 0x2cc1b81f, 0x65467f51, 0x5e9d04ea, 0x8c015d35, 0x87fa7374, 0x0bfb2e41, 0x67b35a1d, 0xdb9252d2, 0x10e93356, 0xd66d1347, 0xd79a8c61, 0xa1377a0c, 0xf8598e14, 0x13eb893c, 0xa9ceee27, 0x61b735c9, 0x1ce1ede5, 0x477a3cb1, 0xd29c59df, 0xf2553f73, 0x141879ce, 0xc773bf37, 0xf753eacd, 0xfd5f5baa, 0x3ddf146f, 0x447886db, 0xafca81f3, 0x68b93ec4, 0x24382c34, 0xa3c25f40, 0x1d1672c3, 0xe2bc0c25, 0x3c288b49, 0x0dff4195, 0xa8397101, 0x0c08deb3, 0xb4d89ce4, 0x566490c1, 0xcb7b6184, 0x32d570b6, 0x6c48745c, 0xb8d04257, }; alignas(16) const uint32_t lutDec3[256] = { 0x5150a7f4, 0x7e536541, 0x1ac3a417, 0x3a965e27, 0x3bcb6bab, 0x1ff1459d, 0xacab58fa, 0x4b9303e3, 0x2055fa30, 0xadf66d76, 0x889176cc, 0xf5254c02, 0x4ffcd7e5, 0xc5d7cb2a, 0x26804435, 0xb58fa362, 0xde495ab1, 0x25671bba, 0x45980eea, 0x5de1c0fe, 0xc302752f, 0x8112f04c, 0x8da39746, 0x6bc6f9d3, 0x03e75f8f, 0x15959c92, 0xbfeb7a6d, 0x95da5952, 0xd42d83be, 0x58d32174, 0x492969e0, 0x8e44c8c9, 0x756a89c2, 0xf478798e, 0x996b3e58, 0x27dd71b9, 0xbeb64fe1, 0xf017ad88, 0xc966ac20, 0x7db43ace, 0x63184adf, 0xe582311a, 0x97603351, 0x62457f53, 0xb1e07764, 0xbb84ae6b, 0xfe1ca081, 0xf9942b08, 0x70586848, 0x8f19fd45, 0x94876cde, 0x52b7f87b, 0xab23d373, 0x72e2024b, 0xe3578f1f, 0x662aab55, 0xb20728eb, 0x2f03c2b5, 0x869a7bc5, 0xd3a50837, 0x30f28728, 0x23b2a5bf, 0x02ba6a03, 0xed5c8216, 0x8a2b1ccf, 0xa792b479, 0xf3f0f207, 0x4ea1e269, 0x65cdf4da, 0x06d5be05, 0xd11f6234, 0xc48afea6, 0x349d532e, 0xa2a055f3, 0x0532e18a, 0xa475ebf6, 0x0b39ec83, 0x40aaef60, 0x5e069f71, 0xbd51106e, 0x3ef98a21, 0x963d06dd, 0xddae053e, 0x4d46bde6, 0x91b58d54, 0x71055dc4, 0x046fd406, 0x60ff1550, 0x1924fb98, 0xd697e9bd, 0x89cc4340, 0x67779ed9, 0xb0bd42e8, 0x07888b89, 0xe7385b19, 0x79dbeec8, 0xa1470a7c, 0x7ce90f42, 0xf8c91e84, 0x00000000, 0x09838680, 0x3248ed2b, 0x1eac7011, 0x6c4e725a, 0xfdfbff0e, 0x0f563885, 0x3d1ed5ae, 0x3627392d, 0x0a64d90f, 0x6821a65c, 0x9bd1545b, 0x243a2e36, 0x0cb1670a, 0x930fe757, 0xb4d296ee, 0x1b9e919b, 0x804fc5c0, 0x61a220dc, 0x5a694b77, 0x1c161a12, 0xe20aba93, 0xc0e52aa0, 0x3c43e022, 0x121d171b, 0x0e0b0d09, 0xf2adc78b, 0x2db9a8b6, 0x14c8a91e, 0x578519f1, 0xaf4c0775, 0xeebbdd99, 0xa3fd607f, 0xf79f2601, 0x5cbcf572, 0x44c53b66, 0x5b347efb, 0x8b762943, 0xcbdcc623, 0xb668fced, 0xb863f1e4, 0xd7cadc31, 0x42108563, 0x13402297, 0x842011c6, 0x857d244a, 0xd2f83dbb, 0xae1132f9, 0xc76da129, 0x1d4b2f9e, 0xdcf330b2, 0x0dec5286, 0x77d0e3c1, 0x2b6c16b3, 0xa999b970, 0x11fa4894, 0x472264e9, 0xa8c48cfc, 0xa01a3ff0, 0x56d82c7d, 0x22ef9033, 0x87c74e49, 0xd9c1d138, 0x8cfea2ca, 0x98360bd4, 0xa6cf81f5, 0xa528de7a, 0xda268eb7, 0x3fa4bfad, 0x2ce49d3a, 0x500d9278, 0x6a9bcc5f, 0x5462467e, 0xf6c2138d, 0x90e8b8d8, 0x2e5ef739, 0x82f5afc3, 0x9fbe805d, 0x697c93d0, 0x6fa92dd5, 0xcfb31225, 0xc83b99ac, 0x10a77d18, 0xe86e639c, 0xdb7bbb3b, 0xcd097826, 0x6ef41859, 0xec01b79a, 0x83a89a4f, 0xe6656e95, 0xaa7ee6ff, 0x2108cfbc, 0xefe6e815, 0xbad99be7, 0x4ace366f, 0xead4099f, 0x29d67cb0, 0x31afb2a4, 0x2a31233f, 0xc63094a5, 0x35c066a2, 0x7437bc4e, 0xfca6ca82, 0xe0b0d090, 0x3315d8a7, 0xf14a9804, 0x41f7daec, 0x7f0e50cd, 0x172ff691, 0x768dd64d, 0x434db0ef, 0xcc544daa, 0xe4df0496, 0x9ee3b5d1, 0x4c1b886a, 0xc1b81f2c, 0x467f5165, 0x9d04ea5e, 0x015d358c, 0xfa737487, 0xfb2e410b, 0xb35a1d67, 0x9252d2db, 0xe9335610, 0x6d1347d6, 0x9a8c61d7, 0x377a0ca1, 0x598e14f8, 0xeb893c13, 0xceee27a9, 0xb735c961, 0xe1ede51c, 0x7a3cb147, 0x9c59dfd2, 0x553f73f2, 0x1879ce14, 0x73bf37c7, 0x53eacdf7, 0x5f5baafd, 0xdf146f3d, 0x7886db44, 0xca81f3af, 0xb93ec468, 0x382c3424, 0xc25f40a3, 0x1672c31d, 0xbc0c25e2, 0x288b493c, 0xff41950d, 0x397101a8, 0x08deb30c, 0xd89ce4b4, 0x6490c156, 0x7b6184cb, 0xd570b632, 0x48745c6c, 0xd04257b8, }; rx_vec_i128 soft_aesenc(rx_vec_i128 in, rx_vec_i128 key) { uint32_t s0, s1, s2, s3; s0 = rx_vec_i128_w(in); s1 = rx_vec_i128_z(in); s2 = rx_vec_i128_y(in); s3 = rx_vec_i128_x(in); rx_vec_i128 out = rx_set_int_vec_i128( (lutEnc0[s0 & 0xff] ^ lutEnc1[(s3 >> 8) & 0xff] ^ lutEnc2[(s2 >> 16) & 0xff] ^ lutEnc3[s1 >> 24]), (lutEnc0[s1 & 0xff] ^ lutEnc1[(s0 >> 8) & 0xff] ^ lutEnc2[(s3 >> 16) & 0xff] ^ lutEnc3[s2 >> 24]), (lutEnc0[s2 & 0xff] ^ lutEnc1[(s1 >> 8) & 0xff] ^ lutEnc2[(s0 >> 16) & 0xff] ^ lutEnc3[s3 >> 24]), (lutEnc0[s3 & 0xff] ^ lutEnc1[(s2 >> 8) & 0xff] ^ lutEnc2[(s1 >> 16) & 0xff] ^ lutEnc3[s0 >> 24]) ); return rx_xor_vec_i128(out, key); } rx_vec_i128 soft_aesdec(rx_vec_i128 in, rx_vec_i128 key) { uint32_t s0, s1, s2, s3; s0 = rx_vec_i128_w(in); s1 = rx_vec_i128_z(in); s2 = rx_vec_i128_y(in); s3 = rx_vec_i128_x(in); rx_vec_i128 out = rx_set_int_vec_i128( (lutDec0[s0 & 0xff] ^ lutDec1[(s1 >> 8) & 0xff] ^ lutDec2[(s2 >> 16) & 0xff] ^ lutDec3[s3 >> 24]), (lutDec0[s1 & 0xff] ^ lutDec1[(s2 >> 8) & 0xff] ^ lutDec2[(s3 >> 16) & 0xff] ^ lutDec3[s0 >> 24]), (lutDec0[s2 & 0xff] ^ lutDec1[(s3 >> 8) & 0xff] ^ lutDec2[(s0 >> 16) & 0xff] ^ lutDec3[s1 >> 24]), (lutDec0[s3 & 0xff] ^ lutDec1[(s0 >> 8) & 0xff] ^ lutDec2[(s1 >> 16) & 0xff] ^ lutDec3[s2 >> 24]) ); return rx_xor_vec_i128(out, key); } RandomX-1.1.10/src/soft_aes.h000066400000000000000000000037251414227164600157230ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "intrin_portable.h" rx_vec_i128 soft_aesenc(rx_vec_i128 in, rx_vec_i128 key); rx_vec_i128 soft_aesdec(rx_vec_i128 in, rx_vec_i128 key); template inline rx_vec_i128 aesenc(rx_vec_i128 in, rx_vec_i128 key) { return soft ? soft_aesenc(in, key) : rx_aesenc_vec_i128(in, key); } template inline rx_vec_i128 aesdec(rx_vec_i128 in, rx_vec_i128 key) { return soft ? soft_aesdec(in, key) : rx_aesdec_vec_i128(in, key); }RandomX-1.1.10/src/superscalar.cpp000066400000000000000000001057221414227164600167770ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "configuration.h" #include "program.hpp" #include "blake2/endian.h" #include #include #include #include #include #include "superscalar.hpp" #include "intrin_portable.h" #include "reciprocal.h" #include "common.hpp" namespace randomx { static bool isMultiplication(SuperscalarInstructionType type) { return type == SuperscalarInstructionType::IMUL_R || type == SuperscalarInstructionType::IMULH_R || type == SuperscalarInstructionType::ISMULH_R || type == SuperscalarInstructionType::IMUL_RCP; } //uOPs (micro-ops) are represented only by the execution port they can go to namespace ExecutionPort { using type = int; constexpr type Null = 0; constexpr type P0 = 1; constexpr type P1 = 2; constexpr type P5 = 4; constexpr type P01 = P0 | P1; constexpr type P05 = P0 | P5; constexpr type P015 = P0 | P1 | P5; } //Macro-operation as output of the x86 decoder //Usually one macro-op = one x86 instruction, but 2 instructions are sometimes fused into 1 macro-op //Macro-op can consist of 1 or 2 uOPs. class MacroOp { public: MacroOp(const char* name, int size) : name_(name), size_(size), latency_(0), uop1_(ExecutionPort::Null), uop2_(ExecutionPort::Null) {} MacroOp(const char* name, int size, int latency, ExecutionPort::type uop) : name_(name), size_(size), latency_(latency), uop1_(uop), uop2_(ExecutionPort::Null) {} MacroOp(const char* name, int size, int latency, ExecutionPort::type uop1, ExecutionPort::type uop2) : name_(name), size_(size), latency_(latency), uop1_(uop1), uop2_(uop2) {} MacroOp(const MacroOp& parent, bool dependent) : name_(parent.name_), size_(parent.size_), latency_(parent.latency_), uop1_(parent.uop1_), uop2_(parent.uop2_), dependent_(dependent) {} const char* getName() const { return name_; } int getSize() const { return size_; } int getLatency() const { return latency_; } ExecutionPort::type getUop1() const { return uop1_; } ExecutionPort::type getUop2() const { return uop2_; } bool isSimple() const { return uop2_ == ExecutionPort::Null; } bool isEliminated() const { return uop1_ == ExecutionPort::Null; } bool isDependent() const { return dependent_; } static const MacroOp Add_rr; static const MacroOp Add_ri; static const MacroOp Lea_sib; static const MacroOp Sub_rr; static const MacroOp Imul_rr; static const MacroOp Imul_r; static const MacroOp Mul_r; static const MacroOp Mov_rr; static const MacroOp Mov_ri64; static const MacroOp Xor_rr; static const MacroOp Xor_ri; static const MacroOp Ror_rcl; static const MacroOp Ror_ri; static const MacroOp TestJz_fused; static const MacroOp Xor_self; static const MacroOp Cmp_ri; static const MacroOp Setcc_r; private: const char* name_; int size_; int latency_; ExecutionPort::type uop1_; ExecutionPort::type uop2_; bool dependent_ = false; }; //Size: 3 bytes const MacroOp MacroOp::Add_rr = MacroOp("add r,r", 3, 1, ExecutionPort::P015); const MacroOp MacroOp::Sub_rr = MacroOp("sub r,r", 3, 1, ExecutionPort::P015); const MacroOp MacroOp::Xor_rr = MacroOp("xor r,r", 3, 1, ExecutionPort::P015); const MacroOp MacroOp::Imul_r = MacroOp("imul r", 3, 4, ExecutionPort::P1, ExecutionPort::P5); const MacroOp MacroOp::Mul_r = MacroOp("mul r", 3, 4, ExecutionPort::P1, ExecutionPort::P5); const MacroOp MacroOp::Mov_rr = MacroOp("mov r,r", 3); //Size: 4 bytes const MacroOp MacroOp::Lea_sib = MacroOp("lea r,r+r*s", 4, 1, ExecutionPort::P01); const MacroOp MacroOp::Imul_rr = MacroOp("imul r,r", 4, 3, ExecutionPort::P1); const MacroOp MacroOp::Ror_ri = MacroOp("ror r,i", 4, 1, ExecutionPort::P05); //Size: 7 bytes (can be optionally padded with nop to 8 or 9 bytes) const MacroOp MacroOp::Add_ri = MacroOp("add r,i", 7, 1, ExecutionPort::P015); const MacroOp MacroOp::Xor_ri = MacroOp("xor r,i", 7, 1, ExecutionPort::P015); //Size: 10 bytes const MacroOp MacroOp::Mov_ri64 = MacroOp("mov rax,i64", 10, 1, ExecutionPort::P015); //Unused: const MacroOp MacroOp::Ror_rcl = MacroOp("ror r,cl", 3, 1, ExecutionPort::P0, ExecutionPort::P5); const MacroOp MacroOp::Xor_self = MacroOp("xor rcx,rcx", 3); const MacroOp MacroOp::Cmp_ri = MacroOp("cmp r,i", 7, 1, ExecutionPort::P015); const MacroOp MacroOp::Setcc_r = MacroOp("setcc cl", 3, 1, ExecutionPort::P05); const MacroOp MacroOp::TestJz_fused = MacroOp("testjz r,i", 13, 0, ExecutionPort::P5); const MacroOp IMULH_R_ops_array[] = { MacroOp::Mov_rr, MacroOp::Mul_r, MacroOp::Mov_rr }; const MacroOp ISMULH_R_ops_array[] = { MacroOp::Mov_rr, MacroOp::Imul_r, MacroOp::Mov_rr }; const MacroOp IMUL_RCP_ops_array[] = { MacroOp::Mov_ri64, MacroOp(MacroOp::Imul_rr, true) }; class SuperscalarInstructionInfo { public: const char* getName() const { return name_; } int getSize() const { return ops_.size(); } bool isSimple() const { return getSize() == 1; } int getLatency() const { return latency_; } const MacroOp& getOp(int index) const { return ops_[index]; } SuperscalarInstructionType getType() const { return type_; } int getResultOp() const { return resultOp_; } int getDstOp() const { return dstOp_; } int getSrcOp() const { return srcOp_; } static const SuperscalarInstructionInfo ISUB_R; static const SuperscalarInstructionInfo IXOR_R; static const SuperscalarInstructionInfo IADD_RS; static const SuperscalarInstructionInfo IMUL_R; static const SuperscalarInstructionInfo IROR_C; static const SuperscalarInstructionInfo IADD_C7; static const SuperscalarInstructionInfo IXOR_C7; static const SuperscalarInstructionInfo IADD_C8; static const SuperscalarInstructionInfo IXOR_C8; static const SuperscalarInstructionInfo IADD_C9; static const SuperscalarInstructionInfo IXOR_C9; static const SuperscalarInstructionInfo IMULH_R; static const SuperscalarInstructionInfo ISMULH_R; static const SuperscalarInstructionInfo IMUL_RCP; static const SuperscalarInstructionInfo NOP; private: const char* name_; SuperscalarInstructionType type_; std::vector ops_; int latency_; int resultOp_ = 0; int dstOp_ = 0; int srcOp_; SuperscalarInstructionInfo(const char* name) : name_(name), type_(SuperscalarInstructionType::INVALID), latency_(0) {} SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp& op, int srcOp) : name_(name), type_(type), latency_(op.getLatency()), srcOp_(srcOp) { ops_.push_back(MacroOp(op)); } template SuperscalarInstructionInfo(const char* name, SuperscalarInstructionType type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp) : name_(name), type_(type), latency_(0), resultOp_(resultOp), dstOp_(dstOp), srcOp_(srcOp) { for (unsigned i = 0; i < N; ++i) { ops_.push_back(MacroOp(arr[i])); latency_ += ops_.back().getLatency(); } static_assert(N > 1, "Invalid array size"); } }; const SuperscalarInstructionInfo SuperscalarInstructionInfo::ISUB_R = SuperscalarInstructionInfo("ISUB_R", SuperscalarInstructionType::ISUB_R, MacroOp::Sub_rr, 0); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IXOR_R = SuperscalarInstructionInfo("IXOR_R", SuperscalarInstructionType::IXOR_R, MacroOp::Xor_rr, 0); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IADD_RS = SuperscalarInstructionInfo("IADD_RS", SuperscalarInstructionType::IADD_RS, MacroOp::Lea_sib, 0); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IMUL_R = SuperscalarInstructionInfo("IMUL_R", SuperscalarInstructionType::IMUL_R, MacroOp::Imul_rr, 0); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IROR_C = SuperscalarInstructionInfo("IROR_C", SuperscalarInstructionType::IROR_C, MacroOp::Ror_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IADD_C7 = SuperscalarInstructionInfo("IADD_C7", SuperscalarInstructionType::IADD_C7, MacroOp::Add_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IXOR_C7 = SuperscalarInstructionInfo("IXOR_C7", SuperscalarInstructionType::IXOR_C7, MacroOp::Xor_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IADD_C8 = SuperscalarInstructionInfo("IADD_C8", SuperscalarInstructionType::IADD_C8, MacroOp::Add_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IXOR_C8 = SuperscalarInstructionInfo("IXOR_C8", SuperscalarInstructionType::IXOR_C8, MacroOp::Xor_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IADD_C9 = SuperscalarInstructionInfo("IADD_C9", SuperscalarInstructionType::IADD_C9, MacroOp::Add_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IXOR_C9 = SuperscalarInstructionInfo("IXOR_C9", SuperscalarInstructionType::IXOR_C9, MacroOp::Xor_ri, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IMULH_R = SuperscalarInstructionInfo("IMULH_R", SuperscalarInstructionType::IMULH_R, IMULH_R_ops_array, 1, 0, 1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::ISMULH_R = SuperscalarInstructionInfo("ISMULH_R", SuperscalarInstructionType::ISMULH_R, ISMULH_R_ops_array, 1, 0, 1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::IMUL_RCP = SuperscalarInstructionInfo("IMUL_RCP", SuperscalarInstructionType::IMUL_RCP, IMUL_RCP_ops_array, 1, 1, -1); const SuperscalarInstructionInfo SuperscalarInstructionInfo::NOP = SuperscalarInstructionInfo("NOP"); //these are some of the options how to split a 16-byte window into 3 or 4 x86 instructions. //RandomX uses instructions with a native size of 3 (sub, xor, mul, mov), 4 (lea, mul), 7 (xor, add immediate) or 10 bytes (mov 64-bit immediate). //Slots with sizes of 8 or 9 bytes need to be padded with a nop instruction. const int buffer0[] = { 4, 8, 4 }; const int buffer1[] = { 7, 3, 3, 3 }; const int buffer2[] = { 3, 7, 3, 3 }; const int buffer3[] = { 4, 9, 3 }; const int buffer4[] = { 4, 4, 4, 4 }; const int buffer5[] = { 3, 3, 10 }; class DecoderBuffer { public: static const DecoderBuffer Default; template DecoderBuffer(const char* name, int index, const int(&arr)[N]) : name_(name), index_(index), counts_(arr), opsCount_(N) {} const int* getCounts() const { return counts_; } int getSize() const { return opsCount_; } int getIndex() const { return index_; } const char* getName() const { return name_; } const DecoderBuffer* fetchNext(SuperscalarInstructionType instrType, int cycle, int mulCount, Blake2Generator& gen) const { //If the current RandomX instruction is "IMULH", the next fetch configuration must be 3-3-10 //because the full 128-bit multiplication instruction is 3 bytes long and decodes to 2 uOPs on Intel CPUs. //Intel CPUs can decode at most 4 uOPs per cycle, so this requires a 2-1-1 configuration for a total of 3 macro ops. if (instrType == SuperscalarInstructionType::IMULH_R || instrType == SuperscalarInstructionType::ISMULH_R) return &decodeBuffer3310; //To make sure that the multiplication port is saturated, a 4-4-4-4 configuration is generated if the number of multiplications //is lower than the number of cycles. if (mulCount < cycle + 1) return &decodeBuffer4444; //If the current RandomX instruction is "IMUL_RCP", the next buffer must begin with a 4-byte slot for multiplication. if(instrType == SuperscalarInstructionType::IMUL_RCP) return (gen.getByte() & 1) ? &decodeBuffer484 : &decodeBuffer493; //Default: select a random fetch configuration. return fetchNextDefault(gen); } private: const char* name_; int index_; const int* counts_; int opsCount_; DecoderBuffer() : index_(-1) {} static const DecoderBuffer decodeBuffer484; static const DecoderBuffer decodeBuffer7333; static const DecoderBuffer decodeBuffer3733; static const DecoderBuffer decodeBuffer493; static const DecoderBuffer decodeBuffer4444; static const DecoderBuffer decodeBuffer3310; static const DecoderBuffer* decodeBuffers[4]; const DecoderBuffer* fetchNextDefault(Blake2Generator& gen) const { return decodeBuffers[gen.getByte() & 3]; } }; const DecoderBuffer DecoderBuffer::decodeBuffer484 = DecoderBuffer("4,8,4", 0, buffer0); const DecoderBuffer DecoderBuffer::decodeBuffer7333 = DecoderBuffer("7,3,3,3", 1, buffer1); const DecoderBuffer DecoderBuffer::decodeBuffer3733 = DecoderBuffer("3,7,3,3", 2, buffer2); const DecoderBuffer DecoderBuffer::decodeBuffer493 = DecoderBuffer("4,9,3", 3, buffer3); const DecoderBuffer DecoderBuffer::decodeBuffer4444 = DecoderBuffer("4,4,4,4", 4, buffer4); const DecoderBuffer DecoderBuffer::decodeBuffer3310 = DecoderBuffer("3,3,10", 5, buffer5); const DecoderBuffer* DecoderBuffer::decodeBuffers[4] = { &DecoderBuffer::decodeBuffer484, &DecoderBuffer::decodeBuffer7333, &DecoderBuffer::decodeBuffer3733, &DecoderBuffer::decodeBuffer493, }; const DecoderBuffer DecoderBuffer::Default = DecoderBuffer(); const SuperscalarInstructionInfo* slot_3[] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R }; const SuperscalarInstructionInfo* slot_3L[] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R, &SuperscalarInstructionInfo::IMULH_R, &SuperscalarInstructionInfo::ISMULH_R }; const SuperscalarInstructionInfo* slot_4[] = { &SuperscalarInstructionInfo::IROR_C, &SuperscalarInstructionInfo::IADD_RS }; const SuperscalarInstructionInfo* slot_7[] = { &SuperscalarInstructionInfo::IXOR_C7, &SuperscalarInstructionInfo::IADD_C7 }; const SuperscalarInstructionInfo* slot_8[] = { &SuperscalarInstructionInfo::IXOR_C8, &SuperscalarInstructionInfo::IADD_C8 }; const SuperscalarInstructionInfo* slot_9[] = { &SuperscalarInstructionInfo::IXOR_C9, &SuperscalarInstructionInfo::IADD_C9 }; const SuperscalarInstructionInfo* slot_10 = &SuperscalarInstructionInfo::IMUL_RCP; static bool selectRegister(std::vector& availableRegisters, Blake2Generator& gen, int& reg) { int index; if (availableRegisters.size() == 0) return false; if (availableRegisters.size() > 1) { index = gen.getUInt32() % availableRegisters.size(); } else { index = 0; } reg = availableRegisters[index]; return true; } class RegisterInfo { public: RegisterInfo() : latency(0), lastOpGroup(SuperscalarInstructionType::INVALID), lastOpPar(-1), value(0) {} int latency; SuperscalarInstructionType lastOpGroup; int lastOpPar; int value; }; //"SuperscalarInstruction" consists of one or more macro-ops class SuperscalarInstruction { public: void toInstr(Instruction& instr) { //translate to a RandomX instruction format instr.opcode = (int)getType(); instr.dst = dst_; instr.src = src_ >= 0 ? src_ : dst_; instr.setMod(mod_); instr.setImm32(imm32_); } void createForSlot(Blake2Generator& gen, int slotSize, int fetchType, bool isLast, bool isFirst) { switch (slotSize) { case 3: //if this is the last slot, we can also select "IMULH" instructions if (isLast) { create(slot_3L[gen.getByte() & 3], gen); } else { create(slot_3[gen.getByte() & 1], gen); } break; case 4: //if this is the 4-4-4-4 buffer, issue multiplications as the first 3 instructions if (fetchType == 4 && !isLast) { create(&SuperscalarInstructionInfo::IMUL_R, gen); } else { create(slot_4[gen.getByte() & 1], gen); } break; case 7: create(slot_7[gen.getByte() & 1], gen); break; case 8: create(slot_8[gen.getByte() & 1], gen); break; case 9: create(slot_9[gen.getByte() & 1], gen); break; case 10: create(slot_10, gen); break; default: UNREACHABLE; } } void create(const SuperscalarInstructionInfo* info, Blake2Generator& gen) { info_ = info; reset(); switch (info->getType()) { case SuperscalarInstructionType::ISUB_R: { mod_ = 0; imm32_ = 0; opGroup_ = SuperscalarInstructionType::IADD_RS; groupParIsSource_ = true; } break; case SuperscalarInstructionType::IXOR_R: { mod_ = 0; imm32_ = 0; opGroup_ = SuperscalarInstructionType::IXOR_R; groupParIsSource_ = true; } break; case SuperscalarInstructionType::IADD_RS: { mod_ = gen.getByte(); imm32_ = 0; opGroup_ = SuperscalarInstructionType::IADD_RS; groupParIsSource_ = true; } break; case SuperscalarInstructionType::IMUL_R: { mod_ = 0; imm32_ = 0; opGroup_ = SuperscalarInstructionType::IMUL_R; groupParIsSource_ = true; } break; case SuperscalarInstructionType::IROR_C: { mod_ = 0; do { imm32_ = gen.getByte() & 63; } while (imm32_ == 0); opGroup_ = SuperscalarInstructionType::IROR_C; opGroupPar_ = -1; } break; case SuperscalarInstructionType::IADD_C7: case SuperscalarInstructionType::IADD_C8: case SuperscalarInstructionType::IADD_C9: { mod_ = 0; imm32_ = gen.getUInt32(); opGroup_ = SuperscalarInstructionType::IADD_C7; opGroupPar_ = -1; } break; case SuperscalarInstructionType::IXOR_C7: case SuperscalarInstructionType::IXOR_C8: case SuperscalarInstructionType::IXOR_C9: { mod_ = 0; imm32_ = gen.getUInt32(); opGroup_ = SuperscalarInstructionType::IXOR_C7; opGroupPar_ = -1; } break; case SuperscalarInstructionType::IMULH_R: { canReuse_ = true; mod_ = 0; imm32_ = 0; opGroup_ = SuperscalarInstructionType::IMULH_R; opGroupPar_ = gen.getUInt32(); } break; case SuperscalarInstructionType::ISMULH_R: { canReuse_ = true; mod_ = 0; imm32_ = 0; opGroup_ = SuperscalarInstructionType::ISMULH_R; opGroupPar_ = gen.getUInt32(); } break; case SuperscalarInstructionType::IMUL_RCP: { mod_ = 0; do { imm32_ = gen.getUInt32(); } while (isZeroOrPowerOf2(imm32_)); opGroup_ = SuperscalarInstructionType::IMUL_RCP; opGroupPar_ = -1; } break; default: break; } } bool selectDestination(int cycle, bool allowChainedMul, RegisterInfo (®isters)[8], Blake2Generator& gen) { /*if (allowChainedMultiplication && opGroup_ == SuperscalarInstructionType::IMUL_R) std::cout << "Selecting destination with chained MUL enabled" << std::endl;*/ std::vector availableRegisters; //Conditions for the destination register: // * value must be ready at the required cycle // * cannot be the same as the source register unless the instruction allows it // - this avoids optimizable instructions such as "xor r, r" or "sub r, r" // * register cannot be multiplied twice in a row unless allowChainedMul is true // - this avoids accumulation of trailing zeroes in registers due to excessive multiplication // - allowChainedMul is set to true if an attempt to find source/destination registers failed (this is quite rare, but prevents a catastrophic failure of the generator) // * either the last instruction applied to the register or its source must be different than this instruction // - this avoids optimizable instruction sequences such as "xor r1, r2; xor r1, r2" or "ror r, C1; ror r, C2" or "add r, C1; add r, C2" // * register r5 cannot be the destination of the IADD_RS instruction (limitation of the x86 lea instruction) for (unsigned i = 0; i < 8; ++i) { if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (allowChainedMul || opGroup_ != SuperscalarInstructionType::IMUL_R || registers[i].lastOpGroup != SuperscalarInstructionType::IMUL_R) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_) && (info_->getType() != SuperscalarInstructionType::IADD_RS || i != RegisterNeedsDisplacement)) availableRegisters.push_back(i); } return selectRegister(availableRegisters, gen, dst_); } bool selectSource(int cycle, RegisterInfo(®isters)[8], Blake2Generator& gen) { std::vector availableRegisters; //all registers that are ready at the cycle for (unsigned i = 0; i < 8; ++i) { if (registers[i].latency <= cycle) availableRegisters.push_back(i); } //if there are only 2 available registers for IADD_RS and one of them is r5, select it as the source because it cannot be the destination if (availableRegisters.size() == 2 && info_->getType() == SuperscalarInstructionType::IADD_RS) { if (availableRegisters[0] == RegisterNeedsDisplacement || availableRegisters[1] == RegisterNeedsDisplacement) { opGroupPar_ = src_ = RegisterNeedsDisplacement; return true; } } if (selectRegister(availableRegisters, gen, src_)) { if (groupParIsSource_) opGroupPar_ = src_; return true; } return false; } SuperscalarInstructionType getType() { return info_->getType(); } int getSource() { return src_; } int getDestination() { return dst_; } SuperscalarInstructionType getGroup() { return opGroup_; } int getGroupPar() { return opGroupPar_; } const SuperscalarInstructionInfo& getInfo() const { return *info_; } static const SuperscalarInstruction Null; private: const SuperscalarInstructionInfo* info_; int src_ = -1; int dst_ = -1; int mod_; uint32_t imm32_; SuperscalarInstructionType opGroup_; int opGroupPar_; bool canReuse_ = false; bool groupParIsSource_ = false; void reset() { src_ = dst_ = -1; canReuse_ = groupParIsSource_ = false; } SuperscalarInstruction(const SuperscalarInstructionInfo* info) : info_(info) { } }; const SuperscalarInstruction SuperscalarInstruction::Null = SuperscalarInstruction(&SuperscalarInstructionInfo::NOP); constexpr int CYCLE_MAP_SIZE = RANDOMX_SUPERSCALAR_LATENCY + 4; constexpr int LOOK_FORWARD_CYCLES = 4; constexpr int MAX_THROWAWAY_COUNT = 256; template static int scheduleUop(ExecutionPort::type uop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle) { //The scheduling here is done optimistically by checking port availability in order P5 -> P0 -> P1 to not overload //port P1 (multiplication) by instructions that can go to any port. for (; cycle < CYCLE_MAP_SIZE; ++cycle) { if ((uop & ExecutionPort::P5) != 0 && !portBusy[cycle][2]) { if (commit) { if (trace) std::cout << "; P5 at cycle " << cycle << std::endl; portBusy[cycle][2] = uop; } return cycle; } if ((uop & ExecutionPort::P0) != 0 && !portBusy[cycle][0]) { if (commit) { if (trace) std::cout << "; P0 at cycle " << cycle << std::endl; portBusy[cycle][0] = uop; } return cycle; } if ((uop & ExecutionPort::P1) != 0 && !portBusy[cycle][1]) { if (commit) { if (trace) std::cout << "; P1 at cycle " << cycle << std::endl; portBusy[cycle][1] = uop; } return cycle; } } return -1; } template static int scheduleMop(const MacroOp& mop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle, int depCycle) { //if this macro-op depends on the previous one, increase the starting cycle if needed //this handles an explicit dependency chain in IMUL_RCP if (mop.isDependent()) { cycle = std::max(cycle, depCycle); } //move instructions are eliminated and don't need an execution unit if (mop.isEliminated()) { if (commit) if (trace) std::cout << "; (eliminated)" << std::endl; return cycle; } else if (mop.isSimple()) { //this macro-op has only one uOP return scheduleUop(mop.getUop1(), portBusy, cycle); } else { //macro-ops with 2 uOPs are scheduled conservatively by requiring both uOPs to execute in the same cycle for (; cycle < CYCLE_MAP_SIZE; ++cycle) { int cycle1 = scheduleUop(mop.getUop1(), portBusy, cycle); int cycle2 = scheduleUop(mop.getUop2(), portBusy, cycle); if (cycle1 >= 0 && cycle1 == cycle2) { if (commit) { scheduleUop(mop.getUop1(), portBusy, cycle1); scheduleUop(mop.getUop2(), portBusy, cycle2); } return cycle1; } } } return -1; } void generateSuperscalar(SuperscalarProgram& prog, Blake2Generator& gen) { ExecutionPort::type portBusy[CYCLE_MAP_SIZE][3]; memset(portBusy, 0, sizeof(portBusy)); RegisterInfo registers[8]; const DecoderBuffer* decodeBuffer = &DecoderBuffer::Default; SuperscalarInstruction currentInstruction = SuperscalarInstruction::Null; int macroOpIndex = 0; int codeSize = 0; int macroOpCount = 0; int cycle = 0; int depCycle = 0; int retireCycle = 0; bool portsSaturated = false; int programSize = 0; int mulCount = 0; int decodeCycle; int throwAwayCount = 0; //decode instructions for RANDOMX_SUPERSCALAR_LATENCY cycles or until an execution port is saturated. //Each decode cycle decodes 16 bytes of x86 code. //Since a decode cycle produces on average 3.45 macro-ops and there are only 3 ALU ports, execution ports are always //saturated first. The cycle limit is present only to guarantee loop termination. //Program size is limited to SuperscalarMaxSize instructions. for (decodeCycle = 0; decodeCycle < RANDOMX_SUPERSCALAR_LATENCY && !portsSaturated && programSize < SuperscalarMaxSize; ++decodeCycle) { //select a decode configuration decodeBuffer = decodeBuffer->fetchNext(currentInstruction.getType(), decodeCycle, mulCount, gen); if (trace) std::cout << "; ------------- fetch cycle " << cycle << " (" << decodeBuffer->getName() << ")" << std::endl; int bufferIndex = 0; //fill all instruction slots in the current decode buffer while (bufferIndex < decodeBuffer->getSize()) { int topCycle = cycle; //if we have issued all macro-ops for the current RandomX instruction, create a new instruction if (macroOpIndex >= currentInstruction.getInfo().getSize()) { if (portsSaturated || programSize >= SuperscalarMaxSize) break; //select an instruction so that the first macro-op fits into the current slot currentInstruction.createForSlot(gen, decodeBuffer->getCounts()[bufferIndex], decodeBuffer->getIndex(), decodeBuffer->getSize() == bufferIndex + 1, bufferIndex == 0); macroOpIndex = 0; if (trace) std::cout << "; " << currentInstruction.getInfo().getName() << std::endl; } const MacroOp& mop = currentInstruction.getInfo().getOp(macroOpIndex); if (trace) std::cout << mop.getName() << " "; //calculate the earliest cycle when this macro-op (all of its uOPs) can be scheduled for execution int scheduleCycle = scheduleMop(mop, portBusy, cycle, depCycle); if (scheduleCycle < 0) { if (trace) std::cout << "Unable to map operation '" << mop.getName() << "' to execution port (cycle " << cycle << ")" << std::endl; //__debugbreak(); portsSaturated = true; break; } //find a source register (if applicable) that will be ready when this instruction executes if (macroOpIndex == currentInstruction.getInfo().getSrcOp()) { int forward; //if no suitable operand is ready, look up to LOOK_FORWARD_CYCLES forward for (forward = 0; forward < LOOK_FORWARD_CYCLES && !currentInstruction.selectSource(scheduleCycle, registers, gen); ++forward) { if (trace) std::cout << "; src STALL at cycle " << cycle << std::endl; ++scheduleCycle; ++cycle; } //if no register was found, throw the instruction away and try another one if (forward == LOOK_FORWARD_CYCLES) { if (throwAwayCount < MAX_THROWAWAY_COUNT) { throwAwayCount++; macroOpIndex = currentInstruction.getInfo().getSize(); if (trace) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl; //cycle = topCycle; continue; } //abort this decode buffer if (trace) std::cout << "Aborting at cycle " << cycle << " with decode buffer " << decodeBuffer->getName() << " - source registers not available for operation " << currentInstruction.getInfo().getName() << std::endl; currentInstruction = SuperscalarInstruction::Null; break; } if (trace) std::cout << "; src = r" << currentInstruction.getSource() << std::endl; } //find a destination register that will be ready when this instruction executes if (macroOpIndex == currentInstruction.getInfo().getDstOp()) { int forward; for (forward = 0; forward < LOOK_FORWARD_CYCLES && !currentInstruction.selectDestination(scheduleCycle, throwAwayCount > 0, registers, gen); ++forward) { if (trace) std::cout << "; dst STALL at cycle " << cycle << std::endl; ++scheduleCycle; ++cycle; } if (forward == LOOK_FORWARD_CYCLES) { //throw instruction away if (throwAwayCount < MAX_THROWAWAY_COUNT) { throwAwayCount++; macroOpIndex = currentInstruction.getInfo().getSize(); if (trace) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl; //cycle = topCycle; continue; } //abort this decode buffer if (trace) std::cout << "Aborting at cycle " << cycle << " with decode buffer " << decodeBuffer->getName() << " - destination registers not available" << std::endl; currentInstruction = SuperscalarInstruction::Null; break; } if (trace) std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl; } throwAwayCount = 0; //recalculate when the instruction can be scheduled for execution based on operand availability scheduleCycle = scheduleMop(mop, portBusy, scheduleCycle, scheduleCycle); if (scheduleCycle < 0) { if (trace) std::cout << "Unable to map operation '" << mop.getName() << "' to execution port (cycle " << scheduleCycle << ")" << std::endl; portsSaturated = true; break; } //calculate when the result will be ready depCycle = scheduleCycle + mop.getLatency(); //if this instruction writes the result, modify register information // RegisterInfo.latency - which cycle the register will be ready // RegisterInfo.lastOpGroup - the last operation that was applied to the register // RegisterInfo.lastOpPar - the last operation source value (-1 = constant, 0-7 = register) if (macroOpIndex == currentInstruction.getInfo().getResultOp()) { int dst = currentInstruction.getDestination(); RegisterInfo& ri = registers[dst]; retireCycle = depCycle; ri.latency = retireCycle; ri.lastOpGroup = currentInstruction.getGroup(); ri.lastOpPar = currentInstruction.getGroupPar(); if (trace) std::cout << "; RETIRED at cycle " << retireCycle << std::endl; } codeSize += mop.getSize(); bufferIndex++; macroOpIndex++; macroOpCount++; //terminating condition if (scheduleCycle >= RANDOMX_SUPERSCALAR_LATENCY) { portsSaturated = true; } cycle = topCycle; //when all macro-ops of the current instruction have been issued, add the instruction into the program if (macroOpIndex >= currentInstruction.getInfo().getSize()) { currentInstruction.toInstr(prog(programSize++)); mulCount += isMultiplication(currentInstruction.getType()); } } ++cycle; } double ipc = (macroOpCount / (double)retireCycle); memset(prog.asicLatencies, 0, sizeof(prog.asicLatencies)); //Calculate ASIC latency: //Assumes 1 cycle latency for all operations and unlimited parallelization. for (int i = 0; i < programSize; ++i) { Instruction& instr = prog(i); int latDst = prog.asicLatencies[instr.dst] + 1; int latSrc = instr.dst != instr.src ? prog.asicLatencies[instr.src] + 1 : 0; prog.asicLatencies[instr.dst] = std::max(latDst, latSrc); } //address register is the register with the highest ASIC latency int asicLatencyMax = 0; int addressReg = 0; for (int i = 0; i < 8; ++i) { if (prog.asicLatencies[i] > asicLatencyMax) { asicLatencyMax = prog.asicLatencies[i]; addressReg = i; } prog.cpuLatencies[i] = registers[i].latency; } prog.setSize(programSize); prog.setAddressRegister(addressReg); prog.cpuLatency = retireCycle; prog.asicLatency = asicLatencyMax; prog.codeSize = codeSize; prog.macroOps = macroOpCount; prog.decodeCycles = decodeCycle; prog.ipc = ipc; prog.mulCount = mulCount; /*if(INFO) std::cout << "; ALU port utilization:" << std::endl; if (INFO) std::cout << "; (* = in use, _ = idle)" << std::endl; int portCycles = 0; for (int i = 0; i < CYCLE_MAP_SIZE; ++i) { std::cout << "; " << std::setw(3) << i << " "; for (int j = 0; j < 3; ++j) { std::cout << (portBusy[i][j] ? '*' : '_'); portCycles += !!portBusy[i][j]; } std::cout << std::endl; }*/ } void executeSuperscalar(int_reg_t(&r)[8], SuperscalarProgram& prog, std::vector *reciprocals) { for (unsigned j = 0; j < prog.getSize(); ++j) { Instruction& instr = prog(j); switch ((SuperscalarInstructionType)instr.opcode) { case SuperscalarInstructionType::ISUB_R: r[instr.dst] -= r[instr.src]; break; case SuperscalarInstructionType::IXOR_R: r[instr.dst] ^= r[instr.src]; break; case SuperscalarInstructionType::IADD_RS: r[instr.dst] += r[instr.src] << instr.getModShift(); break; case SuperscalarInstructionType::IMUL_R: r[instr.dst] *= r[instr.src]; break; case SuperscalarInstructionType::IROR_C: r[instr.dst] = rotr(r[instr.dst], instr.getImm32()); break; case SuperscalarInstructionType::IADD_C7: case SuperscalarInstructionType::IADD_C8: case SuperscalarInstructionType::IADD_C9: r[instr.dst] += signExtend2sCompl(instr.getImm32()); break; case SuperscalarInstructionType::IXOR_C7: case SuperscalarInstructionType::IXOR_C8: case SuperscalarInstructionType::IXOR_C9: r[instr.dst] ^= signExtend2sCompl(instr.getImm32()); break; case SuperscalarInstructionType::IMULH_R: r[instr.dst] = mulh(r[instr.dst], r[instr.src]); break; case SuperscalarInstructionType::ISMULH_R: r[instr.dst] = smulh(r[instr.dst], r[instr.src]); break; case SuperscalarInstructionType::IMUL_RCP: if (reciprocals != nullptr) r[instr.dst] *= (*reciprocals)[instr.getImm32()]; else r[instr.dst] *= randomx_reciprocal(instr.getImm32()); break; default: UNREACHABLE; } } } } RandomX-1.1.10/src/superscalar.hpp000066400000000000000000000071561414227164600170060ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include "superscalar_program.hpp" #include "blake2_generator.hpp" namespace randomx { // Intel Ivy Bridge reference enum class SuperscalarInstructionType { //uOPs (decode) execution ports latency code size ISUB_R = 0, //1 p015 1 3 (sub) IXOR_R = 1, //1 p015 1 3 (xor) IADD_RS = 2, //1 p01 1 4 (lea) IMUL_R = 3, //1 p1 3 4 (imul) IROR_C = 4, //1 p05 1 4 (ror) IADD_C7 = 5, //1 p015 1 7 (add) IXOR_C7 = 6, //1 p015 1 7 (xor) IADD_C8 = 7, //1+0 p015 1 7+1 (add+nop) IXOR_C8 = 8, //1+0 p015 1 7+1 (xor+nop) IADD_C9 = 9, //1+0 p015 1 7+2 (add+nop) IXOR_C9 = 10, //1+0 p015 1 7+2 (xor+nop) IMULH_R = 11, //1+2+1 0+(p1,p5)+0 3 3+3+3 (mov+mul+mov) ISMULH_R = 12, //1+2+1 0+(p1,p5)+0 3 3+3+3 (mov+imul+mov) IMUL_RCP = 13, //1+1 p015+p1 4 10+4 (mov+imul) COUNT = 14, INVALID = -1 }; void generateSuperscalar(SuperscalarProgram& prog, Blake2Generator& gen); void executeSuperscalar(uint64_t(&r)[8], SuperscalarProgram& prog, std::vector *reciprocals = nullptr); }RandomX-1.1.10/src/superscalar_program.hpp000066400000000000000000000046741414227164600205370ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "instruction.hpp" #include "common.hpp" namespace randomx { class SuperscalarProgram { public: Instruction& operator()(int pc) { return programBuffer[pc]; } friend std::ostream& operator<<(std::ostream& os, const SuperscalarProgram& p) { p.print(os); return os; } uint32_t getSize() { return size; } void setSize(uint32_t val) { size = val; } int getAddressRegister() { return addrReg; } void setAddressRegister(int val) { addrReg = val; } Instruction programBuffer[SuperscalarMaxSize]; uint32_t size #ifndef NDEBUG = 0 #endif ; int addrReg; double ipc; int codeSize; int macroOps; int decodeCycles; int cpuLatency; int asicLatency; int mulCount; int cpuLatencies[8]; int asicLatencies[8]; private: void print(std::ostream& os) const { for (unsigned i = 0; i < size; ++i) { auto instr = programBuffer[i]; os << instr; } } }; }RandomX-1.1.10/src/tests/000077500000000000000000000000001414227164600151025ustar00rootroot00000000000000RandomX-1.1.10/src/tests/affinity.cpp000066400000000000000000000072401414227164600174220ustar00rootroot00000000000000/* Copyright (c) 2019, jtgrassie Copyright (c) 2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #if defined(_WIN32) || defined(__CYGWIN__) #include #else #ifdef __APPLE__ #include #include #endif #include #endif #include "affinity.hpp" int set_thread_affinity(const unsigned &cpuid) { std::thread::native_handle_type thread; #if defined(_WIN32) || defined(__CYGWIN__) thread = reinterpret_cast(GetCurrentThread()); #else thread = static_cast(pthread_self()); #endif return set_thread_affinity(thread, cpuid); } int set_thread_affinity(std::thread::native_handle_type thread, const unsigned &cpuid) { int rc = -1; #ifdef __APPLE__ thread_port_t mach_thread; thread_affinity_policy_data_t policy = { static_cast(cpuid) }; mach_thread = pthread_mach_thread_np(thread); rc = thread_policy_set(mach_thread, THREAD_AFFINITY_POLICY, (thread_policy_t)&policy, 1); #elif defined(_WIN32) || defined(__CYGWIN__) rc = SetThreadAffinityMask(reinterpret_cast(thread), 1ULL << cpuid) == 0 ? -2 : 0; #elif !defined(__OpenBSD__) && !defined(__FreeBSD__) && !defined(__ANDROID__) && !defined(__NetBSD__) cpu_set_t cs; CPU_ZERO(&cs); CPU_SET(cpuid, &cs); rc = pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cs); #endif return rc; } unsigned cpuid_from_mask(uint64_t mask, const unsigned &thread_index) { static unsigned lookup[64]; static bool init = false; if (init) return lookup[thread_index]; unsigned count_found = 0; for (unsigned i=0; i<64; i++) { if (1ULL & mask) { lookup[count_found] = i; count_found++; } mask >>= 1; } init = true; return lookup[thread_index]; } std::string mask_to_string(uint64_t mask) { std::ostringstream ss; unsigned len = 0; unsigned v = 0; unsigned i = 64; while (i--) { v = mask >> i; if (1ULL & v) { if (len == 0) len = i + 1; ss << '1'; } else if (len > 0) ss << '0'; } return ss.str(); } RandomX-1.1.10/src/tests/affinity.hpp000066400000000000000000000034441414227164600174310ustar00rootroot00000000000000/* Copyright (c) 2019, jtgrassie All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include int set_thread_affinity(const unsigned &cpuid); int set_thread_affinity(std::thread::native_handle_type thread, const unsigned &cpuid); unsigned cpuid_from_mask(uint64_t mask, const unsigned &thread_index); std::string mask_to_string(uint64_t mask); RandomX-1.1.10/src/tests/api-example1.c000066400000000000000000000012111414227164600175240ustar00rootroot00000000000000#include "../randomx.h" #include int main() { const char myKey[] = "RandomX example key"; const char myInput[] = "RandomX example input"; char hash[RANDOMX_HASH_SIZE]; randomx_flags flags = randomx_get_flags(); randomx_cache *myCache = randomx_alloc_cache(flags); randomx_init_cache(myCache, &myKey, sizeof myKey); randomx_vm *myMachine = randomx_create_vm(flags, myCache, NULL); randomx_calculate_hash(myMachine, &myInput, sizeof myInput, hash); randomx_destroy_vm(myMachine); randomx_release_cache(myCache); for (unsigned i = 0; i < RANDOMX_HASH_SIZE; ++i) printf("%02x", hash[i] & 0xff); printf("\n"); return 0; } RandomX-1.1.10/src/tests/api-example2.cpp000066400000000000000000000027551414227164600201030ustar00rootroot00000000000000#include "../randomx.h" #include #include #include int main() { const char myKey[] = "RandomX example key"; const char myInput[] = "RandomX example input"; char hash[RANDOMX_HASH_SIZE]; randomx_flags flags = randomx_get_flags(); flags |= RANDOMX_FLAG_LARGE_PAGES; flags |= RANDOMX_FLAG_FULL_MEM; randomx_cache *myCache = randomx_alloc_cache(flags); if (myCache == nullptr) { std::cout << "Cache allocation failed" << std::endl; return 1; } randomx_init_cache(myCache, myKey, sizeof myKey); randomx_dataset *myDataset = randomx_alloc_dataset(flags); if (myDataset == nullptr) { std::cout << "Dataset allocation failed" << std::endl; return 1; } auto datasetItemCount = randomx_dataset_item_count(); std::thread t1(&randomx_init_dataset, myDataset, myCache, 0, datasetItemCount / 2); std::thread t2(&randomx_init_dataset, myDataset, myCache, datasetItemCount / 2, datasetItemCount - datasetItemCount / 2); t1.join(); t2.join(); randomx_release_cache(myCache); randomx_vm *myMachine = randomx_create_vm(flags, nullptr, myDataset); if (myMachine == nullptr) { std::cout << "Failed to create a virtual machine" << std::endl; return 1; } randomx_calculate_hash(myMachine, &myInput, sizeof myInput, hash); randomx_destroy_vm(myMachine); randomx_release_dataset(myDataset); for (unsigned i = 0; i < RANDOMX_HASH_SIZE; ++i) std::cout << std::hex << std::setw(2) << std::setfill('0') << ((int)hash[i] & 0xff); std::cout << std::endl; return 0; }RandomX-1.1.10/src/tests/benchmark.cpp000066400000000000000000000326301414227164600175440ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "stopwatch.hpp" #include "utility.hpp" #include "../randomx.h" #include "../dataset.hpp" #include "../blake2/endian.h" #include "../common.hpp" #include "../jit_compiler.hpp" #ifdef _WIN32 #include #include #endif #include "affinity.hpp" const uint8_t blockTemplate_[] = { 0x07, 0x07, 0xf7, 0xa4, 0xf0, 0xd6, 0x05, 0xb3, 0x03, 0x26, 0x08, 0x16, 0xba, 0x3f, 0x10, 0x90, 0x2e, 0x1a, 0x14, 0x5a, 0xc5, 0xfa, 0xd3, 0xaa, 0x3a, 0xf6, 0xea, 0x44, 0xc1, 0x18, 0x69, 0xdc, 0x4f, 0x85, 0x3f, 0x00, 0x2b, 0x2e, 0xea, 0x00, 0x00, 0x00, 0x00, 0x77, 0xb2, 0x06, 0xa0, 0x2c, 0xa5, 0xb1, 0xd4, 0xce, 0x6b, 0xbf, 0xdf, 0x0a, 0xca, 0xc3, 0x8b, 0xde, 0xd3, 0x4d, 0x2d, 0xcd, 0xee, 0xf9, 0x5c, 0xd2, 0x0c, 0xef, 0xc1, 0x2f, 0x61, 0xd5, 0x61, 0x09 }; class AtomicHash { public: AtomicHash() { for (int i = 0; i < 4; ++i) hash[i].store(0); } void xorWith(uint64_t update[4]) { for (int i = 0; i < 4; ++i) hash[i].fetch_xor(update[i]); } void print(std::ostream& os) { for (int i = 0; i < 4; ++i) print(hash[i], os); os << std::endl; } private: static void print(std::atomic& hash, std::ostream& os) { auto h = hash.load(); outputHex(std::cout, (char*)&h, sizeof(h)); } std::atomic hash[4]; }; void printUsage(const char* executable) { std::cout << "Usage: " << executable << " [OPTIONS]" << std::endl; std::cout << "Supported options:" << std::endl; std::cout << " --help shows this message" << std::endl; std::cout << " --mine mining mode: 2080 MiB" << std::endl; std::cout << " --verify verification mode: 256 MiB" << std::endl; std::cout << " --jit JIT compiled mode (default: interpreter)" << std::endl; std::cout << " --secure W^X policy for JIT pages (default: off)" << std::endl; std::cout << " --largePages use large pages (default: small pages)" << std::endl; std::cout << " --softAes use software AES (default: hardware AES)" << std::endl; std::cout << " --threads T use T threads (default: 1)" << std::endl; std::cout << " --affinity A thread affinity bitmask (default: 0)" << std::endl; std::cout << " --init Q initialize dataset with Q threads (default: 1)" << std::endl; std::cout << " --nonces N run N nonces (default: 1000)" << std::endl; std::cout << " --seed S seed for cache initialization (default: 0)" << std::endl; std::cout << " --ssse3 use optimized Argon2 for SSSE3 CPUs" << std::endl; std::cout << " --avx2 use optimized Argon2 for AVX2 CPUs" << std::endl; std::cout << " --auto select the best options for the current CPU" << std::endl; std::cout << " --noBatch calculate hashes one by one (default: batch)" << std::endl; } struct MemoryException : public std::exception { }; struct CacheAllocException : public MemoryException { const char * what() const throw () { return "Cache allocation failed"; } }; struct DatasetAllocException : public MemoryException { const char * what() const throw () { return "Dataset allocation failed"; } }; using MineFunc = void(randomx_vm * vm, std::atomic & atomicNonce, AtomicHash & result, uint32_t noncesCount, int thread, int cpuid); template void mine(randomx_vm* vm, std::atomic& atomicNonce, AtomicHash& result, uint32_t noncesCount, int thread, int cpuid = -1) { if (cpuid >= 0) { int rc = set_thread_affinity(cpuid); if (rc) { std::cerr << "Failed to set thread affinity for thread " << thread << " (error=" << rc << ")" << std::endl; } } uint64_t hash[RANDOMX_HASH_SIZE / sizeof(uint64_t)]; uint8_t blockTemplate[sizeof(blockTemplate_)]; memcpy(blockTemplate, blockTemplate_, sizeof(blockTemplate)); void* noncePtr = blockTemplate + 39; auto nonce = atomicNonce.fetch_add(1); if (batch) { store32(noncePtr, nonce); randomx_calculate_hash_first(vm, blockTemplate, sizeof(blockTemplate)); } while (nonce < noncesCount) { if (batch) { nonce = atomicNonce.fetch_add(1); } store32(noncePtr, nonce); (batch ? randomx_calculate_hash_next : randomx_calculate_hash)(vm, blockTemplate, sizeof(blockTemplate), &hash); result.xorWith(hash); if (!batch) { nonce = atomicNonce.fetch_add(1); } } } int main(int argc, char** argv) { bool softAes, miningMode, verificationMode, help, largePages, jit, secure; bool ssse3, avx2, autoFlags, noBatch; int noncesCount, threadCount, initThreadCount; uint64_t threadAffinity; int32_t seedValue; char seed[4]; readOption("--softAes", argc, argv, softAes); readOption("--mine", argc, argv, miningMode); readOption("--verify", argc, argv, verificationMode); readIntOption("--threads", argc, argv, threadCount, 1); readUInt64Option("--affinity", argc, argv, threadAffinity, 0); readIntOption("--nonces", argc, argv, noncesCount, 1000); readIntOption("--init", argc, argv, initThreadCount, 1); readIntOption("--seed", argc, argv, seedValue, 0); readOption("--largePages", argc, argv, largePages); if (!largePages) { readOption("--largepages", argc, argv, largePages); } readOption("--jit", argc, argv, jit); readOption("--help", argc, argv, help); readOption("--secure", argc, argv, secure); readOption("--ssse3", argc, argv, ssse3); readOption("--avx2", argc, argv, avx2); readOption("--auto", argc, argv, autoFlags); readOption("--noBatch", argc, argv, noBatch); store32(&seed, seedValue); std::cout << "RandomX benchmark v1.1.8" << std::endl; if (help) { printUsage(argv[0]); return 0; } if (!miningMode && !verificationMode) { std::cout << "Please select either the fast mode (--mine) or the slow mode (--verify)" << std::endl; std::cout << "Run '" << argv[0] << " --help' to see all supported options" << std::endl; return 0; } std::atomic atomicNonce(0); AtomicHash result; std::vector vms; std::vector threads; randomx_dataset* dataset; randomx_cache* cache; randomx_flags flags; if (autoFlags) { initThreadCount = std::thread::hardware_concurrency(); flags = randomx_get_flags(); } else { flags = RANDOMX_FLAG_DEFAULT; if (ssse3) { flags |= RANDOMX_FLAG_ARGON2_SSSE3; } if (avx2) { flags |= RANDOMX_FLAG_ARGON2_AVX2; } if (!softAes) { flags |= RANDOMX_FLAG_HARD_AES; } if (jit) { flags |= RANDOMX_FLAG_JIT; #ifdef RANDOMX_FORCE_SECURE flags |= RANDOMX_FLAG_SECURE; #endif } } if (largePages) { flags |= RANDOMX_FLAG_LARGE_PAGES; } if (miningMode) { flags |= RANDOMX_FLAG_FULL_MEM; } #ifndef RANDOMX_FORCE_SECURE if (secure) { flags |= RANDOMX_FLAG_SECURE; } #endif if (flags & RANDOMX_FLAG_ARGON2_AVX2) { std::cout << " - Argon2 implementation: AVX2" << std::endl; } else if (flags & RANDOMX_FLAG_ARGON2_SSSE3) { std::cout << " - Argon2 implementation: SSSE3" << std::endl; } else { std::cout << " - Argon2 implementation: reference" << std::endl; } if (flags & RANDOMX_FLAG_FULL_MEM) { std::cout << " - full memory mode (2080 MiB)" << std::endl; } else { std::cout << " - light memory mode (256 MiB)" << std::endl; } if (flags & RANDOMX_FLAG_JIT) { std::cout << " - JIT compiled mode "; if (flags & RANDOMX_FLAG_SECURE) { std::cout << "(secure)"; } std::cout << std::endl; } else { std::cout << " - interpreted mode" << std::endl; } if (flags & RANDOMX_FLAG_HARD_AES) { std::cout << " - hardware AES mode" << std::endl; } else { std::cout << " - software AES mode" << std::endl; } if (flags & RANDOMX_FLAG_LARGE_PAGES) { std::cout << " - large pages mode" << std::endl; } else { std::cout << " - small pages mode" << std::endl; } if (threadAffinity) { std::cout << " - thread affinity (" << mask_to_string(threadAffinity) << ")" << std::endl; } MineFunc* func; if (noBatch) { func = &mine; } else { func = &mine; std::cout << " - batch mode" << std::endl; } std::cout << "Initializing"; if (miningMode) std::cout << " (" << initThreadCount << " thread" << (initThreadCount > 1 ? "s)" : ")"); std::cout << " ..." << std::endl; try { if (nullptr == randomx::selectArgonImpl(flags)) { throw std::runtime_error("Unsupported Argon2 implementation"); } if ((flags & RANDOMX_FLAG_JIT) && !RANDOMX_HAVE_COMPILER) { throw std::runtime_error("JIT compilation is not supported on this platform. Try without --jit"); } if (!(flags & RANDOMX_FLAG_JIT) && RANDOMX_HAVE_COMPILER) { std::cout << "WARNING: You are using the interpreter mode. Use --jit for optimal performance." << std::endl; } Stopwatch sw(true); cache = randomx_alloc_cache(flags); if (cache == nullptr) { throw CacheAllocException(); } randomx_init_cache(cache, &seed, sizeof(seed)); if (miningMode) { dataset = randomx_alloc_dataset(flags); if (dataset == nullptr) { throw DatasetAllocException(); } uint32_t datasetItemCount = randomx_dataset_item_count(); if (initThreadCount > 1) { auto perThread = datasetItemCount / initThreadCount; auto remainder = datasetItemCount % initThreadCount; uint32_t startItem = 0; for (int i = 0; i < initThreadCount; ++i) { auto count = perThread + (i == initThreadCount - 1 ? remainder : 0); threads.push_back(std::thread(&randomx_init_dataset, dataset, cache, startItem, count)); startItem += count; } for (unsigned i = 0; i < threads.size(); ++i) { threads[i].join(); } } else { randomx_init_dataset(dataset, cache, 0, datasetItemCount); } randomx_release_cache(cache); cache = nullptr; threads.clear(); } std::cout << "Memory initialized in " << sw.getElapsed() << " s" << std::endl; std::cout << "Initializing " << threadCount << " virtual machine(s) ..." << std::endl; for (int i = 0; i < threadCount; ++i) { randomx_vm *vm = randomx_create_vm(flags, cache, dataset); if (vm == nullptr) { if ((flags & RANDOMX_FLAG_HARD_AES)) { throw std::runtime_error("Cannot create VM with the selected options. Try using --softAes"); } if (largePages) { throw std::runtime_error("Cannot create VM with the selected options. Try without --largePages"); } throw std::runtime_error("Cannot create VM"); } vms.push_back(vm); } std::cout << "Running benchmark (" << noncesCount << " nonces) ..." << std::endl; sw.restart(); if (threadCount > 1) { for (unsigned i = 0; i < vms.size(); ++i) { int cpuid = -1; if (threadAffinity) cpuid = cpuid_from_mask(threadAffinity, i); threads.push_back(std::thread(func, vms[i], std::ref(atomicNonce), std::ref(result), noncesCount, i, cpuid)); } for (unsigned i = 0; i < threads.size(); ++i) { threads[i].join(); } } else { func(vms[0], std::ref(atomicNonce), std::ref(result), noncesCount, 0, -1); } double elapsed = sw.getElapsed(); for (unsigned i = 0; i < vms.size(); ++i) randomx_destroy_vm(vms[i]); if (miningMode) randomx_release_dataset(dataset); else randomx_release_cache(cache); std::cout << "Calculated result: "; result.print(std::cout); if (noncesCount == 1000 && seedValue == 0) std::cout << "Reference result: 10b649a3f15c7c7f88277812f2e74b337a0f20ce909af09199cccb960771cfa1" << std::endl; if (!miningMode) { std::cout << "Performance: " << 1000 * elapsed / noncesCount << " ms per hash" << std::endl; } else { std::cout << "Performance: " << noncesCount / elapsed << " hashes per second" << std::endl; } } catch (MemoryException& e) { std::cout << "ERROR: " << e.what() << std::endl; if (largePages) { #ifdef _WIN32 std::cout << "To use large pages, please enable the \"Lock Pages in Memory\" policy and reboot." << std::endl; if (!IsWindows8OrGreater()) { std::cout << "Additionally, you have to run the benchmark from elevated command prompt." << std::endl; } #else std::cout << "To use large pages, please run: sudo sysctl -w vm.nr_hugepages=1250" << std::endl; #endif } return 1; } catch (std::exception& e) { std::cout << "ERROR: " << e.what() << std::endl; return 1; } return 0; } RandomX-1.1.10/src/tests/code-generator.cpp000066400000000000000000000116611414227164600205110ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "utility.hpp" #include "../common.hpp" #include "../assembly_generator_x86.hpp" #include "../superscalar.hpp" #include "../aes_hash.hpp" #include "../blake2/blake2.h" #include "../program.hpp" const uint8_t seed[32] = { 191, 182, 222, 175, 249, 89, 134, 104, 241, 68, 191, 62, 162, 166, 61, 64, 123, 191, 227, 193, 118, 60, 188, 53, 223, 133, 175, 24, 123, 230, 55, 74 }; const uint8_t blockTemplate_[] = { 0x07, 0x07, 0xf7, 0xa4, 0xf0, 0xd6, 0x05, 0xb3, 0x03, 0x26, 0x08, 0x16, 0xba, 0x3f, 0x10, 0x90, 0x2e, 0x1a, 0x14, 0x5a, 0xc5, 0xfa, 0xd3, 0xaa, 0x3a, 0xf6, 0xea, 0x44, 0xc1, 0x18, 0x69, 0xdc, 0x4f, 0x85, 0x3f, 0x00, 0x2b, 0x2e, 0xea, 0x00, 0x00, 0x00, 0x00, 0x77, 0xb2, 0x06, 0xa0, 0x2c, 0xa5, 0xb1, 0xd4, 0xce, 0x6b, 0xbf, 0xdf, 0x0a, 0xca, 0xc3, 0x8b, 0xde, 0xd3, 0x4d, 0x2d, 0xcd, 0xee, 0xf9, 0x5c, 0xd2, 0x0c, 0xef, 0xc1, 0x2f, 0x61, 0xd5, 0x61, 0x09 }; template void generateAsm(uint32_t nonce) { alignas(16) uint64_t hash[8]; uint8_t blockTemplate[sizeof(blockTemplate_)]; memcpy(blockTemplate, blockTemplate_, sizeof(blockTemplate)); store32(blockTemplate + 39, nonce); blake2b(hash, sizeof(hash), blockTemplate, sizeof(blockTemplate), nullptr, 0); uint8_t scratchpad[randomx::ScratchpadSize]; fillAes1Rx4((void*)hash, randomx::ScratchpadSize, scratchpad); randomx::AssemblyGeneratorX86 asmX86; randomx::Program p; fillAes4Rx4(hash, sizeof(p), &p); asmX86.generateProgram(p); asmX86.printCode(std::cout); } template void generateNative(uint32_t nonce) { alignas(16) uint64_t hash[8]; uint8_t blockTemplate[sizeof(blockTemplate_)]; memcpy(blockTemplate, blockTemplate_, sizeof(blockTemplate)); store32(blockTemplate + 39, nonce); blake2b(hash, sizeof(hash), blockTemplate, sizeof(blockTemplate), nullptr, 0); uint8_t scratchpad[randomx::ScratchpadSize]; fillAes1Rx4((void*)hash, randomx::ScratchpadSize, scratchpad); alignas(16) randomx::Program prog; fillAes4Rx4((void*)hash, sizeof(prog), &prog); std::cout << prog << std::endl; } void printUsage(const char* executable) { std::cout << "Usage: " << executable << " [OPTIONS]" << std::endl; std::cout << "Supported options:" << std::endl; std::cout << " --softAes use software AES (default: x86 AES-NI)" << std::endl; std::cout << " --nonce N seed nonce (default: 1000)" << std::endl; std::cout << " --genAsm generate x86-64 asm code for nonce N" << std::endl; std::cout << " --genNative generate RandomX code for nonce N" << std::endl; std::cout << " --genSuperscalar generate superscalar program for nonce N" << std::endl; } int main(int argc, char** argv) { bool softAes, genAsm, genNative, genSuperscalar; int nonce; readOption("--softAes", argc, argv, softAes); readOption("--genAsm", argc, argv, genAsm); readIntOption("--nonce", argc, argv, nonce, 1000); readOption("--genNative", argc, argv, genNative); readOption("--genSuperscalar", argc, argv, genSuperscalar); if (genSuperscalar) { randomx::SuperscalarProgram p; randomx::Blake2Generator gen(seed, nonce); randomx::generateSuperscalar(p, gen); randomx::AssemblyGeneratorX86 asmX86; asmX86.generateAsm(p); asmX86.printCode(std::cout); return 0; } if (genAsm) { if (softAes) generateAsm(nonce); else generateAsm(nonce); return 0; } if (genNative) { if (softAes) generateNative(nonce); else generateNative(nonce); return 0; } printUsage(argv[0]); return 0; }RandomX-1.1.10/src/tests/jit-performance.cpp000066400000000000000000000022731414227164600206770ustar00rootroot00000000000000#include "../aes_hash.hpp" #include "../jit_compiler_x86.hpp" #include "../program.hpp" #include "utility.hpp" #include "stopwatch.hpp" #include "../blake2/blake2.h" #include "../reciprocal.h" int main(int argc, char** argv) { int count; readInt(argc, argv, count, 1000000); const char seed[] = "JIT performance test seed"; uint8_t hash[64]; blake2b(&hash, sizeof hash, &seed, sizeof seed, nullptr, 0); randomx::ProgramConfiguration config; randomx::Program program; randomx::JitCompilerX86 jit; std::cout << "Compiling " << count << " programs..." << std::endl; Stopwatch sw(true); for (int i = 0; i < count; ++i) { fillAes1Rx4(hash, sizeof(program), &program); auto addressRegisters = program.getEntropy(12); config.readReg0 = 0 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg1 = 2 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg2 = 4 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg3 = 6 + (addressRegisters & 1); jit.generateProgram(program, config); } std::cout << "Elapsed: " << sw.getElapsed() << " s" << std::endl; dump((const char*)jit.getProgramFunc(), jit.getCodeSize(), "program.bin"); return 0; }RandomX-1.1.10/src/tests/perf-simulation.cpp000066400000000000000000000473751414227164600207440ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "utility.hpp" #include "../common.hpp" #include "../aes_hash.hpp" #include "../program.hpp" #include "../blake2/blake2.h" #include #include int analyze(randomx::Program& p); int executeInOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline); int executeOutOfOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline); constexpr uint32_t DST_NOP = 0; constexpr uint32_t DST_INT = 1; constexpr uint32_t DST_FLT = 2; constexpr uint32_t DST_MEM = 3; constexpr uint32_t MASK_DST = 3; constexpr uint32_t SRC_NOP = 0; constexpr uint32_t SRC_INT = 4; constexpr uint32_t SRC_FLT = 8; constexpr uint32_t SRC_MEM = 12; constexpr uint32_t MASK_SRC = 12; constexpr uint32_t OP_CFROUND = 16; constexpr uint32_t OP_SWAP = 32; constexpr uint32_t OP_BRANCH = 48; constexpr uint32_t MASK_EXT = 48; constexpr uint32_t OP_FLOAT = 64; constexpr uint32_t BRANCH_TARGET = 128; //template void generate(randomx::Program& p, uint32_t nonce) { alignas(16) uint64_t hash[8]; blake2b(hash, sizeof(hash), &nonce, sizeof(nonce), nullptr, 0); fillAes1Rx4((void*)hash, sizeof(p), &p); } bool has(randomx::Instruction& instr, uint32_t mask, uint32_t prop) { return (instr.opcode & mask) == prop; } bool has(randomx::Instruction& instr, uint32_t prop) { return (instr.opcode & prop) != 0; } int main(int argc, char** argv) { int nonces, seed, executionPorts, memoryPorts, pipeline; bool print, reorder, speculate; readOption("--print", argc, argv, print); readOption("--reorder", argc, argv, reorder); readOption("--speculate", argc, argv, speculate); readIntOption("--nonces", argc, argv, nonces, 1); readIntOption("--seed", argc, argv, seed, 0); readIntOption("--executionPorts", argc, argv, executionPorts, 4); readIntOption("--memoryPorts", argc, argv, memoryPorts, 2); readIntOption("--pipeline", argc, argv, pipeline, 3); randomx::Program p, original; double totalCycles = 0.0; double jumpCount = 0; for (int i = 0; i < nonces; ++i) { generate(original, i ^ seed); memcpy(&p, &original, sizeof(p)); jumpCount += analyze(p); totalCycles += reorder ? executeOutOfOrder(p, original, print, executionPorts, memoryPorts, speculate, pipeline) : executeInOrder(p, original, print, executionPorts, memoryPorts, speculate, pipeline); } totalCycles /= nonces; jumpCount /= nonces; std::cout << "Execution took " << totalCycles << " cycles per program" << std::endl; //std::cout << "Jump count: " << jumpCount << std::endl; return 0; } int executeInOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline) { int cycle = pipeline - 1; int index = 0; int branchCount = 0; int int_reg_ready[randomx::RegistersCount] = { 0 }; int flt_reg_ready[randomx::RegistersCount] = { 0 }; //each workgroup takes 1 or 2 cycles (2 cycles if any instruction has a memory operand) while (index < RANDOMX_PROGRAM_SIZE) { int memoryAccesses = 0; bool hasRound = false; int workers = 0; //std::cout << "-----------" << std::endl; for (; workers < executionPorts && memoryAccesses < memoryPorts && index < RANDOMX_PROGRAM_SIZE; ++workers) { auto& instr = p(index); auto& origi = original(index); origi.dst %= randomx::RegistersCount; origi.src %= randomx::RegistersCount; //check dependencies if (has(instr, MASK_SRC, SRC_INT) && int_reg_ready[instr.src] > cycle) break; if (has(instr, MASK_SRC, SRC_MEM) && int_reg_ready[instr.src] > cycle - 1) break; if (has(instr, MASK_DST, DST_MEM) && int_reg_ready[instr.dst] > cycle - 1) break; if (has(instr, MASK_DST, DST_FLT) && flt_reg_ready[instr.dst] > cycle) break; if (has(instr, MASK_DST, DST_INT) && int_reg_ready[instr.dst] > cycle) break; if (hasRound && has(instr, OP_FLOAT)) break; //execute index++; if (has(instr, MASK_EXT, OP_BRANCH)) { branchCount++; } if (has(instr, MASK_DST, DST_FLT)) flt_reg_ready[instr.dst] = cycle + 1; if (has(instr, MASK_DST, DST_INT)) int_reg_ready[instr.dst] = cycle + 1; if (has(instr, MASK_EXT, OP_SWAP)) { int_reg_ready[instr.src] = cycle + 1; } if (has(instr, MASK_EXT, OP_CFROUND)) hasRound = true; if (has(instr, MASK_SRC, SRC_MEM) || has(instr, MASK_DST, DST_MEM)) { memoryAccesses++; } if (print) std::cout << std::setw(2) << (cycle + 1) << ": " << origi; //non-speculative execution must stall after branch if (!speculate && has(instr, MASK_EXT, OP_BRANCH)) { cycle += pipeline - 1; break; } } //std::cout << " workers: " << workers << std::endl; cycle++; } if (speculate) { //account for mispredicted branches int i = 0; while (branchCount--) { auto entropy = p.getEntropy(i / 8); entropy >> (i % 8) * 8; if ((entropy & 0xff) == 0) // 1/256 chance to flush the pipeline cycle += pipeline - 1; } } return cycle; } int executeOutOfOrder(randomx::Program& p, randomx::Program& original, bool print, int executionPorts, int memoryPorts, bool speculate, int pipeline) { int index = 0; int busyExecutionPorts[2 * RANDOMX_PROGRAM_SIZE] = { 0 }; int busyMemoryPorts[2 * RANDOMX_PROGRAM_SIZE] = { 0 }; int int_reg_ready[randomx::RegistersCount] = { 0 }; int flt_reg_ready[randomx::RegistersCount] = { 0 }; int fprcReady = 0; int lastBranch = 0; int branchCount = 0; for (; index < RANDOMX_PROGRAM_SIZE; ++index) { auto& instr = p(index); int retireCycle = pipeline - 1; //non-speculative execution cannot reorder across branches if (!speculate && !has(instr, MASK_EXT, OP_BRANCH)) retireCycle = std::max(lastBranch + pipeline - 1, retireCycle); //check dependencies if (has(instr, MASK_SRC, SRC_INT)) { retireCycle = std::max(retireCycle, int_reg_ready[instr.src]); int_reg_ready[instr.src] = retireCycle; } if (has(instr, MASK_SRC, SRC_MEM)) { retireCycle = std::max(retireCycle, int_reg_ready[instr.src] + 1); //find free memory port while (busyMemoryPorts[retireCycle - 1] >= memoryPorts) { retireCycle++; } busyMemoryPorts[retireCycle - 1]++; } if (has(instr, MASK_DST, DST_FLT)) { retireCycle = std::max(retireCycle, flt_reg_ready[instr.dst]); } if (has(instr, MASK_DST, DST_INT)) { retireCycle = std::max(retireCycle, int_reg_ready[instr.dst]); } //floating point operations depend on the fprc register if (has(instr, OP_FLOAT)) retireCycle = std::max(retireCycle, fprcReady); //execute if (has(instr, MASK_DST, DST_MEM)) { retireCycle = std::max(retireCycle, int_reg_ready[instr.dst] + 1); //find free memory port while (busyMemoryPorts[retireCycle - 1] >= memoryPorts) { retireCycle++; } busyMemoryPorts[retireCycle - 1]++; retireCycle++; } if (has(instr, MASK_DST, DST_FLT)) { //find free execution port do { retireCycle++; } while (busyExecutionPorts[retireCycle - 1] >= executionPorts); busyExecutionPorts[retireCycle - 1]++; flt_reg_ready[instr.dst] = retireCycle; } if (has(instr, MASK_DST, DST_INT)) { //find free execution port do { retireCycle++; } while (busyExecutionPorts[retireCycle - 1] >= executionPorts); busyExecutionPorts[retireCycle - 1]++; int_reg_ready[instr.dst] = retireCycle; } if (has(instr, MASK_EXT, OP_SWAP)) { int_reg_ready[instr.src] = retireCycle; } if (has(instr, MASK_EXT, OP_CFROUND)) { do { retireCycle++; } while (busyExecutionPorts[retireCycle - 1] >= executionPorts); busyExecutionPorts[retireCycle - 1]++; fprcReady = retireCycle; } if (has(instr, MASK_EXT, OP_BRANCH)) { /*if (!speculate && instr.mod == 1) { //simulated predication do { retireCycle++; } while (busyExecutionPorts[retireCycle - 1] >= executionPorts); busyExecutionPorts[retireCycle - 1]++; int_reg_ready[instr.dst] = retireCycle; }*/ //else { lastBranch = std::max(lastBranch, retireCycle); branchCount++; //} } //print auto& origi = original(index); origi.dst %= randomx::RegistersCount; origi.src %= randomx::RegistersCount; if (print) { std::cout << std::setw(2) << retireCycle << ": " << origi; if (has(instr, MASK_EXT, OP_BRANCH)) { std::cout << " jump: " << (int)instr.mod << std::endl; } } } int cycle = 0; for (int i = 0; i < randomx::RegistersCount; ++i) { cycle = std::max(cycle, int_reg_ready[i]); } for (int i = 0; i < randomx::RegistersCount; ++i) { cycle = std::max(cycle, flt_reg_ready[i]); } if (speculate) { //account for mispredicted branches int i = 0; while (branchCount--) { auto entropy = p.getEntropy(i / 8); entropy >> (i % 8) * 8; if ((entropy & 0xff) == 0) // 1/256 chance to flush the pipeline cycle += pipeline - 1; } } return cycle; } #include "../bytecode_machine.hpp" //old register selection struct RegisterUsage { int32_t lastUsed; int32_t count; }; inline int getConditionRegister(RegisterUsage(®isterUsage)[randomx::RegistersCount]) { int min = INT_MAX; int minCount = 0; int minIndex; //prefer registers that have been used as a condition register fewer times for (unsigned i = 0; i < randomx::RegistersCount; ++i) { if (registerUsage[i].lastUsed < min || (registerUsage[i].lastUsed == min && registerUsage[i].count < minCount)) { min = registerUsage[i].lastUsed; minCount = registerUsage[i].count; minIndex = i; } } return minIndex; } int analyze(randomx::Program& p) { int jumpCount = 0; RegisterUsage registerUsage[randomx::RegistersCount]; for (unsigned i = 0; i < randomx::RegistersCount; ++i) { registerUsage[i].lastUsed = -1; registerUsage[i].count = 0; } for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) { auto& instr = p(i); int opcode = instr.opcode; instr.opcode = 0; if (opcode < randomx::ceil_IADD_RS) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_INT; instr.opcode |= DST_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IADD_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_ISUB_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_ISUB_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IMUL_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IMUL_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IMULH_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IMULH_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_ISMULH_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_ISMULH_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IMUL_RCP) { uint64_t divisor = instr.getImm32(); if (!randomx::isZeroOrPowerOf2(divisor)) { instr.dst = instr.dst % randomx::RegistersCount; instr.opcode |= DST_INT; registerUsage[instr.dst].lastUsed = i; } continue; } if (opcode < randomx::ceil_INEG_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.opcode |= DST_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IXOR_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IXOR_M) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_MEM; instr.opcode |= DST_INT; if (instr.src != instr.dst) { instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); } else { instr.imm32 &= randomx::ScratchpadL3Mask; } registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IROR_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_IROL_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_INT; instr.opcode |= SRC_INT; registerUsage[instr.dst].lastUsed = i; continue; } if (opcode < randomx::ceil_ISWAP_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; if (instr.src != instr.dst) { instr.opcode |= DST_INT; instr.opcode |= SRC_INT; instr.opcode |= OP_SWAP; registerUsage[instr.dst].lastUsed = i; registerUsage[instr.src].lastUsed = i; } continue; } if (opcode < randomx::ceil_FSWAP_R) { instr.dst = instr.dst % randomx::RegistersCount; instr.opcode |= DST_FLT; continue; } if (opcode < randomx::ceil_FADD_R) { instr.dst = instr.dst % randomx::RegisterCountFlt; instr.opcode |= DST_FLT; instr.opcode |= OP_FLOAT; continue; } if (opcode < randomx::ceil_FADD_M) { instr.dst = instr.dst % randomx::RegisterCountFlt; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_FLT; instr.opcode |= SRC_MEM; instr.opcode |= OP_FLOAT; instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); continue; } if (opcode < randomx::ceil_FSUB_R) { instr.dst = instr.dst % randomx::RegisterCountFlt; instr.opcode |= DST_FLT; instr.opcode |= OP_FLOAT; continue; } if (opcode < randomx::ceil_FSUB_M) { instr.dst = instr.dst % randomx::RegisterCountFlt; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_FLT; instr.opcode |= SRC_MEM; instr.opcode |= OP_FLOAT; instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); continue; } if (opcode < randomx::ceil_FSCAL_R) { instr.dst = instr.dst % randomx::RegisterCountFlt; instr.opcode |= DST_FLT; continue; } if (opcode < randomx::ceil_FMUL_R) { instr.dst = 4 + instr.dst % randomx::RegisterCountFlt; instr.opcode |= DST_FLT; instr.opcode |= OP_FLOAT; continue; } if (opcode < randomx::ceil_FDIV_M) { instr.dst = 4 + instr.dst % randomx::RegisterCountFlt; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_FLT; instr.opcode |= SRC_MEM; instr.opcode |= OP_FLOAT; instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); continue; } if (opcode < randomx::ceil_FSQRT_R) { instr.dst = 4 + instr.dst % randomx::RegisterCountFlt; instr.opcode |= DST_FLT; instr.opcode |= OP_FLOAT; continue; } if (opcode < randomx::ceil_CBRANCH) { instr.opcode |= OP_BRANCH; instr.opcode |= DST_INT; int reg = instr.dst % randomx::RegistersCount; int target = registerUsage[reg].lastUsed; int offset = (i - target); instr.mod = offset; jumpCount += offset; p(target + 1).opcode |= BRANCH_TARGET; registerUsage[reg].count++; instr.dst = reg; //mark all registers as used for (unsigned j = 0; j < randomx::RegistersCount; ++j) { registerUsage[j].lastUsed = i; } continue; } if (opcode < randomx::ceil_CFROUND) { instr.src = instr.src % randomx::RegistersCount; instr.opcode |= SRC_INT; instr.opcode |= OP_CFROUND; continue; } if (opcode < randomx::ceil_ISTORE) { instr.dst = instr.dst % randomx::RegistersCount; instr.src = instr.src % randomx::RegistersCount; instr.opcode |= DST_MEM; if (instr.getModCond() < randomx::StoreL3Condition) instr.imm32 = (instr.getModMem() ? randomx::ScratchpadL1Mask : randomx::ScratchpadL2Mask); else instr.imm32 &= randomx::ScratchpadL3Mask; continue; } if (opcode < randomx::ceil_NOP) { } } return jumpCount; } RandomX-1.1.10/src/tests/rng-tests.cpp000066400000000000000000000046531414227164600175440ustar00rootroot00000000000000/* cd ~ wget http://simul.iro.umontreal.ca/testu01/TestU01.zip unzip TestU01.zip mkdir TestU01 cd TestU01-1.2.3 ./configure --prefix=`pwd`/../TestU01 make -j8 make install cd ~/RandomX g++ -O3 src/tests/rng-tests.cpp -lm -I ~/TestU01/include -L ~/TestU01/lib -L bin/ -l:libtestu01.a -l:libmylib.a -l:libprobdist.a -lrandomx -o bin/rng-tests -DRANDOMX_GEN=4R -DRANDOMX_TESTU01=Crush bin/rng-tests 0 */ extern "C" { #include "unif01.h" #include "bbattery.h" } #include "../aes_hash.hpp" #include "../blake2/blake2.h" #include "utility.hpp" #include #ifndef RANDOMX_GEN #error Please define RANDOMX_GEN with a value of 1R or 4R #endif #ifndef RANDOMX_TESTU01 #error Please define RANDOMX_TESTU01 with a value of SmallCrush, Crush or BigCrush #endif #define STR(x) #x #define CONCAT(a,b,c) a ## b ## c #define GEN_NAME(x) "AesGenerator" STR(x) #define GEN_FUNC(x) CONCAT(fillAes, x, x4) #define TEST_SUITE(x) CONCAT(bbattery_, x,) constexpr int GeneratorStateSize = 64; constexpr int GeneratorCapacity = GeneratorStateSize / sizeof(uint32_t); static unsigned long aesGenBits(void *param, void *state) { uint32_t* statePtr = (uint32_t*)state; int* indexPtr = (int*)param; int stateIndex = *indexPtr; if(stateIndex >= GeneratorCapacity) { GEN_FUNC(RANDOMX_GEN)(statePtr, GeneratorStateSize, statePtr); stateIndex = 0; } uint32_t next = statePtr[stateIndex]; *indexPtr = stateIndex + 1; return next; } static double aesGenDouble(void *param, void *state) { return aesGenBits (param, state) / unif01_NORM32; } static void aesWriteState(void* state) { char* statePtr = (char*)state; for(int i = 0; i < 4; ++i) { std::cout << "state" << i << " = "; outputHex(std::cout, statePtr + (i * 16), 16); std::cout << std::endl; } } int main(int argc, char** argv) { if (argc != 2) { std::cout << argv[0] << " " << std::endl; return 1; } uint32_t state[GeneratorCapacity] = { 0 }; int stateIndex = GeneratorCapacity; char name[] = GEN_NAME(RANDOMX_GEN); uint64_t seed = strtoull(argv[1], nullptr, 0); if(seed) { blake2b(&state, sizeof(state), &seed, sizeof(seed), nullptr, 0); } unif01_Gen gen; gen.state = &state; gen.param = &stateIndex; gen.Write = &aesWriteState; gen.GetU01 = &aesGenDouble; gen.GetBits = &aesGenBits; gen.name = (char*)name; gen.Write(gen.state); std::cout << std::endl; TEST_SUITE(RANDOMX_TESTU01)(&gen); return 0; }RandomX-1.1.10/src/tests/runtime-distr.cpp000066400000000000000000000112351414227164600204160ustar00rootroot00000000000000 #include #include "utility.hpp" #include "stopwatch.hpp" #include "../dataset.hpp" #include "../vm_compiled.hpp" #include "../blake2/blake2.h" struct Outlier { Outlier(int idx, double rtime) : index(idx), runtime(rtime) {} int index; double runtime; }; int main(int argc, char** argv) { constexpr int distributionSize = 100; int distribution[distributionSize + 1] = { 0 }; Stopwatch sw; alignas(16) uint64_t hash[8]; uint64_t checksum = 0; double totalRuntime = 0; double maxRuntime = 0; std::vector outliers; outliers.reserve(25); randomx_flags flags = RANDOMX_FLAG_DEFAULT; bool softAes, largePages, jit, verify; int totalCount, initThreadCount; double binSize, offset; int32_t seed; readOption("--verify", argc, argv, verify); readOption("--jit", argc, argv, jit); readOption("--softAes", argc, argv, softAes); readIntOption("--nonces", argc, argv, totalCount, 10000); readIntOption("--init", argc, argv, initThreadCount, 1); readFloatOption("--binSize", argc, argv, binSize, 1e-3); readFloatOption("--offset", argc, argv, offset, 0); readIntOption("--seed", argc, argv, seed, 0); readOption("--largePages", argc, argv, largePages); if (!verify) { flags = (randomx_flags)(flags | RANDOMX_FLAG_FULL_MEM); std::cout << "Measure program runtime" << std::endl; } else { std::cout << "Measure verification time" << std::endl; } std::cout << " - histogram offset: " << offset << std::endl; std::cout << " - histogram bin size: " << binSize << std::endl; if (jit) { flags = (randomx_flags)(flags | RANDOMX_FLAG_JIT); std::cout << " - JIT compiled mode" << std::endl; } else { std::cout << " - interpreted mode" << std::endl; } if (softAes) { std::cout << " - software AES mode" << std::endl; } else { flags = (randomx_flags)(flags | RANDOMX_FLAG_HARD_AES); std::cout << " - hardware AES mode" << std::endl; } if (largePages) { flags = (randomx_flags)(flags | RANDOMX_FLAG_LARGE_PAGES); std::cout << " - large pages mode" << std::endl; } else { std::cout << " - small pages mode" << std::endl; } std::cout << "Initializing..." << std::endl; randomx_cache *cache = randomx_alloc_cache(flags); randomx_dataset *dataset = nullptr; if (cache == nullptr) { std::cout << "Cache allocation failed" << std::endl; return 1; } randomx_init_cache(cache, &seed, sizeof seed); if (!verify) { blake2b(&hash, sizeof hash, &seed, sizeof seed, nullptr, 0); dataset = randomx_alloc_dataset(flags); if (dataset == nullptr) { std::cout << "Dataset allocation failed" << std::endl; return 1; } std::vector threads; uint32_t datasetItemCount = randomx_dataset_item_count(); if (initThreadCount > 1) { auto perThread = datasetItemCount / initThreadCount; auto remainder = datasetItemCount % initThreadCount; uint32_t startItem = 0; for (int i = 0; i < initThreadCount; ++i) { auto count = perThread + (i == initThreadCount - 1 ? remainder : 0); threads.push_back(std::thread(&randomx_init_dataset, dataset, cache, startItem, count)); startItem += count; } for (unsigned i = 0; i < threads.size(); ++i) { threads[i].join(); } } else { randomx_init_dataset(dataset, cache, 0, datasetItemCount); } randomx_release_cache(cache); cache = nullptr; } std::cout << "Running " << totalCount << " programs..." << std::endl; randomx_vm* vm = randomx_create_vm(flags, cache, dataset); if (!verify) { vm->initScratchpad(&hash); vm->resetRoundingMode(); } for (int i = 0; i < totalCount; ++i) { sw.restart(); if (verify) randomx_calculate_hash(vm, &i, sizeof i, &hash); else vm->run(&hash); double elapsed = sw.getElapsed(); //std::cout << "Elapsed: " << elapsed << std::endl; totalRuntime += elapsed; if (elapsed > maxRuntime) maxRuntime = elapsed; int bin = (elapsed - offset) / binSize; bool outlier = false; if (bin < 0) { bin = 0; outlier = true; } if (bin > distributionSize) { bin = distributionSize; outlier = true; } if (outlier && outliers.size() < outliers.capacity()) outliers.push_back(Outlier(i, elapsed)); distribution[bin]++; if(!verify) blake2b(hash, sizeof(hash), vm->getRegisterFile(), sizeof(randomx::RegisterFile), nullptr, 0); checksum ^= hash[0]; } for (int i = 0; i < distributionSize + 1; ++i) { std::cout << i << " " << distribution[i] << std::endl; } std::cout << "Average runtime: " << totalRuntime / totalCount << std::endl; std::cout << "Maximum runtime: " << maxRuntime << std::endl; std::cout << "Checksum: " << checksum << std::endl; std::cout << "Outliers: " << std::endl; for (Outlier& ol : outliers) { std::cout << " " << ol.index << ": " << ol.runtime << std::endl; } return 0; }RandomX-1.1.10/src/tests/scratchpad-entropy.cpp000066400000000000000000000026601414227164600214240ustar00rootroot00000000000000#include #include #include "utility.hpp" #include "../randomx.h" #include "../virtual_machine.hpp" #include "../blake2/endian.h" /* Writes final scratchpads to disk as files with .spad extension, each file is 2048 KiB. Command line parameters: --count N number of files to generate (default = 1) --seed S different seed will give different outputs (default = 0) Entropy can be estimated by compressing the files using 7zip in Ultra mode: 7z.exe a -t7z -m0=lzma2 -mx=9 scratchpads.7z *.spad */ int main(int argc, char** argv) { int count, seedValue; readIntOption("--count", argc, argv, count, 1); readIntOption("--seed", argc, argv, seedValue, 0); std::cout << "Generating " << count << " scratchpad(s) using seed " << seedValue << " ..." << std::endl; char seed[4]; char input[4]; char hash[RANDOMX_HASH_SIZE]; store32(&seed, seedValue); randomx_cache *cache = randomx_alloc_cache(RANDOMX_FLAG_DEFAULT); randomx_init_cache(cache, &seed, sizeof seed); randomx_vm *vm = randomx_create_vm(RANDOMX_FLAG_DEFAULT, cache, NULL); for (int i = 0; i < count; ++i) { store32(&input, i); randomx_calculate_hash(vm, &input, sizeof input, hash); std::string filename("test-"); filename += std::to_string(i); filename += ".spad"; dump((const char*)vm->getScratchpad(), randomx::ScratchpadSize, filename.c_str()); } randomx_destroy_vm(vm); randomx_release_cache(cache); return 0; } RandomX-1.1.10/src/tests/stopwatch.hpp000066400000000000000000000052401414227164600176300ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include class Stopwatch { public: Stopwatch(bool startNow = false) { reset(); if (startNow) { start(); } } void reset() { isRunning = false; elapsed = 0; } void start() { if (!isRunning) { startMark = std::chrono::high_resolution_clock::now(); isRunning = true; } } void restart() { startMark = std::chrono::high_resolution_clock::now(); isRunning = true; elapsed = 0; } void stop() { if (isRunning) { chrono_t endMark = std::chrono::high_resolution_clock::now(); uint64_t ns = std::chrono::duration_cast(endMark - startMark).count(); elapsed += ns; isRunning = false; } } double getElapsed() const { return getElapsedNanosec() / 1e+9; } private: using chrono_t = std::chrono::high_resolution_clock::time_point; using sw_unit = std::chrono::nanoseconds; chrono_t startMark; uint64_t elapsed; bool isRunning; uint64_t getElapsedNanosec() const { uint64_t elns = elapsed; if (isRunning) { chrono_t endMark = std::chrono::high_resolution_clock::now(); uint64_t ns = std::chrono::duration_cast(endMark - startMark).count(); elns += ns; } return elns; } };RandomX-1.1.10/src/tests/superscalar-avalanche.cpp000066400000000000000000000025461414227164600220610ustar00rootroot00000000000000#include #include #include #include "../superscalar.hpp" #include "../intrin_portable.h" const uint8_t seed[32] = { 191, 182, 222, 175, 249, 89, 134, 104, 241, 68, 191, 62, 162, 166, 61, 64, 123, 191, 227, 193, 118, 60, 188, 53, 223, 133, 175, 24, 123, 230, 55, 74 }; int main() { int insensitiveProgCount[64] = { 0 }; std::vector dummy; for (int bit = 0; bit < 64; ++bit) { for (int i = 0; i < 10000; ++i) { uint64_t ra[8] = { 6364136223846793005ULL, 9298410992540426748ULL, 12065312585734608966ULL, 9306329213124610396ULL, 5281919268842080866ULL, 10536153434571861004ULL, 3398623926847679864ULL, 9549104520008361294ULL, }; uint64_t rb[8]; memcpy(rb, ra, sizeof rb); rb[0] ^= (1ULL << bit); randomx::SuperscalarProgram p; randomx::Blake2Generator gen(seed, sizeof seed, i); randomx::generateSuperscalar(p, gen); randomx::executeSuperscalar(ra, p, nullptr); randomx::executeSuperscalar(rb, p, nullptr); uint64_t diff = 0; for (int j = 0; j < 8; ++j) { diff += __popcnt64(ra[j] ^ rb[j]); } if (diff < 192 || diff > 320) { std::cout << "Seed: " << i << " diff = " << diff << std::endl; insensitiveProgCount[bit]++; } } } for (int bit = 0; bit < 64; ++bit) { std::cout << bit << " " << insensitiveProgCount[bit] << std::endl; } return 0; }RandomX-1.1.10/src/tests/superscalar-init.cpp000066400000000000000000000040771414227164600211030ustar00rootroot00000000000000#include #include #include #include #include "../superscalar.hpp" #include "../common.hpp" int main() { std::cout << "THIS PROGRAM REQUIRES MORE THAN 16 GB OF RAM TO COMPLETE" << std::endl; std::vector dummy; constexpr uint64_t superscalarMul0 = 6364136223846793005ULL; constexpr uint64_t superscalarAdd1 = 0x810A978A59F5A1FC; //9298410992540426748ULL; //9298410992540426048ULL constexpr uint64_t superscalarAdd2 = 12065312585734608966ULL; constexpr uint64_t superscalarAdd3 = 0x8126B91CBF22495C; //9306329213124610396ULL; constexpr uint64_t superscalarAdd4 = 5281919268842080866ULL; constexpr uint64_t superscalarAdd5 = 10536153434571861004ULL; constexpr uint64_t superscalarAdd6 = 3398623926847679864ULL; constexpr uint64_t superscalarAdd7 = 9549104520008361294ULL; constexpr uint32_t totalItems = randomx::DatasetSize / randomx::CacheLineSize; std::unordered_set registerValues; registerValues.reserve(totalItems); registerValues.rehash(totalItems); int collisionCount[9] = { 0 }; for (uint32_t itemNumber = 0; itemNumber < totalItems; ++itemNumber) { uint64_t rl[8]; rl[0] = (itemNumber + 1) * superscalarMul0; rl[1] = rl[0] ^ superscalarAdd1; rl[2] = rl[0] ^ superscalarAdd2; rl[3] = rl[0] ^ superscalarAdd3; rl[4] = rl[0] ^ superscalarAdd4; rl[5] = rl[0] ^ superscalarAdd5; rl[6] = rl[0] ^ superscalarAdd6; rl[7] = rl[0] ^ superscalarAdd7; int blockCollisions = 0; for (int i = 0; i < 8; ++i) { uint64_t reducedValue = rl[i] & 0x3FFFFFFFFFFFF8; //bits 3-53 only if (registerValues.find(reducedValue) != registerValues.end()) { blockCollisions++; std::cout << "Item " << itemNumber << ": collision of register r" << i << std::endl; } else { registerValues.insert(reducedValue); } } collisionCount[blockCollisions]++; if ((itemNumber % (320 * 1024)) == 0) std::cout << "Item " << itemNumber << " processed" << std::endl; } for (int i = 0; i < 9; ++i) { std::cout << i << " register(s) collide in " << collisionCount[i] << " items" << std::endl; } return 0; }RandomX-1.1.10/src/tests/superscalar-stats.cpp000066400000000000000000000035421414227164600212720ustar00rootroot00000000000000#include #include #include "../superscalar.hpp" #include "../blake2_generator.hpp" const uint8_t seed[32] = { 191, 182, 222, 175, 249, 89, 134, 104, 241, 68, 191, 62, 162, 166, 61, 64, 123, 191, 227, 193, 118, 60, 188, 53, 223, 133, 175, 24, 123, 230, 55, 74 }; int main() { constexpr int count = 1000000; int isnCounts[(int)randomx::SuperscalarInstructionType::COUNT] = { 0 }; int64_t asicLatency = 0; int64_t codesize = 0; int64_t cpuLatency = 0; int64_t macroOps = 0; int64_t mulCount = 0; int64_t size = 0; for (int i = 0; i < count; ++i) { randomx::SuperscalarProgram prog; randomx::Blake2Generator gen(seed, sizeof(seed), i); randomx::generateSuperscalar(prog, gen); asicLatency += prog.asicLatency; codesize += prog.codeSize; cpuLatency += prog.cpuLatency; macroOps += prog.macroOps; mulCount += prog.mulCount; size += prog.getSize(); for (unsigned j = 0; j < prog.getSize(); ++j) { isnCounts[prog(j).opcode]++; } if ((i + 1) % (count / 100) == 0) { std::cout << "Completed " << ((i + 1) / (count / 100)) << "% ..." << std::endl; } } std::cout << "Avg. IPC: " << (macroOps / (double)cpuLatency) << std::endl; std::cout << "Avg. ASIC latency: " << (asicLatency / (double)count) << std::endl; std::cout << "Avg. CPU latency: " << (cpuLatency / (double)count) << std::endl; std::cout << "Avg. code size: " << (codesize / (double)count) << std::endl; std::cout << "Avg. x86 ops: " << (macroOps / (double)count) << std::endl; std::cout << "Avg. mul. count: " << (mulCount / (double)count) << std::endl; std::cout << "Avg. RandomX ops: " << (size / (double)count) << std::endl; std::cout << "Frequencies: " << std::endl; for (unsigned j = 0; j < (int)randomx::SuperscalarInstructionType::COUNT; ++j) { std::cout << j << " " << isnCounts[j] << " " << isnCounts[j] / (double)size << std::endl; } return 0; }RandomX-1.1.10/src/tests/tests.cpp000066400000000000000000001224461414227164600167610ustar00rootroot00000000000000#ifdef NDEBUG #undef NDEBUG #endif #include #include #include "utility.hpp" #include "../bytecode_machine.hpp" #include "../dataset.hpp" #include "../blake2/endian.h" #include "../blake2/blake2.h" #include "../blake2_generator.hpp" #include "../superscalar.hpp" #include "../reciprocal.h" #include "../intrin_portable.h" #include "../jit_compiler.hpp" #include "../aes_hash.hpp" randomx_cache* cache; randomx_vm* vm = nullptr; template void initCache(const char (&key)[N]) { assert(cache != nullptr); randomx_init_cache(cache, key, N - 1); if (vm != nullptr) randomx_vm_set_cache(vm, cache); } template void calcStringHash(const char(&key)[K], const char(&input)[H], void* output) { initCache(key); assert(vm != nullptr); randomx_calculate_hash(vm, input, H - 1, output); } template void calcHexHash(const char(&key)[K], const char(&hex)[H], void* output) { initCache(key); assert(vm != nullptr); char input[H / 2]; hex2bin((char*)hex, H - 1, input); randomx_calculate_hash(vm, input, sizeof(input), output); } int testNo = 0; int skipped = 0; template void runTest(const char* name, bool condition, FUNC f) { std::cout << "["; std::cout.width(2); std::cout << std::right << ++testNo << "] "; std::cout.width(40); std::cout << std::left << name << " ... "; std::cout.flush(); if (condition) { f(); std::cout << "PASSED" << std::endl; } else { std::cout << "SKIPPED" << std::endl; skipped++; } } int main() { char testHash[32]; //std::cout << "Allocating randomx_cache..." << std::endl; cache = randomx_alloc_cache(RANDOMX_FLAG_DEFAULT); runTest("Cache initialization", RANDOMX_ARGON_ITERATIONS == 3 && RANDOMX_ARGON_LANES == 1 && RANDOMX_ARGON_MEMORY == 262144 && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { initCache("test key 000"); uint64_t* cacheMemory = (uint64_t*)cache->memory; assert(cacheMemory[0] == 0x191e0e1d23c02186); assert(cacheMemory[1568413] == 0xf1b62fe6210bf8b1); assert(cacheMemory[33554431] == 0x1f47f056d05cd99b); }); runTest("SuperscalarHash generator", RANDOMX_SUPERSCALAR_LATENCY == 170, []() { char sprogHash[32]; randomx::SuperscalarProgram sprog; const char key[] = "test key 000"; constexpr size_t keySize = sizeof(key) - 1; randomx::Blake2Generator gen(key, keySize); const char superscalarReferences[10][65] = { "d3a4a6623738756f77e6104469102f082eff2a3e60be7ad696285ef7dfc72a61", "f5e7e0bbc7e93c609003d6359208688070afb4a77165a552ff7be63b38dfbc86", "85ed8b11734de5b3e9836641413a8f36e99e89694f419c8cd25c3f3f16c40c5a", "5dd956292cf5d5704ad99e362d70098b2777b2a1730520be52f772ca48cd3bc0", "6f14018ca7d519e9b48d91af094c0f2d7e12e93af0228782671a8640092af9e5", "134be097c92e2c45a92f23208cacd89e4ce51f1009a0b900dbe83b38de11d791", "268f9392c20c6e31371a5131f82bd7713d3910075f2f0468baafaa1abd2f3187", "c668a05fd909714ed4a91e8d96d67b17e44329e88bc71e0672b529a3fc16be47", "99739351315840963011e4c5d8e90ad0bfed3facdcb713fe8f7138fbf01c4c94", "14ab53d61880471f66e80183968d97effd5492b406876060e595fcf9682f9295", }; for (int i = 0; i < 10; ++i) { randomx::generateSuperscalar(sprog, gen); blake2b(sprogHash, sizeof(sprogHash), &sprog.programBuffer, sizeof(randomx::Instruction) * sprog.getSize(), nullptr, 0); assert(equalsHex(sprogHash, superscalarReferences[i])); } }); runTest("randomx_reciprocal", true, []() { assert(randomx_reciprocal(3) == 12297829382473034410U); assert(randomx_reciprocal(13) == 11351842506898185609U); assert(randomx_reciprocal(33) == 17887751829051686415U); assert(randomx_reciprocal(65537) == 18446462603027742720U); assert(randomx_reciprocal(15000001) == 10316166306300415204U); assert(randomx_reciprocal(3845182035) == 10302264209224146340U); assert(randomx_reciprocal(0xffffffff) == 9223372039002259456U); }); runTest("randomx_reciprocal_fast", RANDOMX_HAVE_FAST_RECIPROCAL, []() { assert(randomx_reciprocal_fast(3) == 12297829382473034410U); assert(randomx_reciprocal_fast(13) == 11351842506898185609U); assert(randomx_reciprocal_fast(33) == 17887751829051686415U); assert(randomx_reciprocal_fast(65537) == 18446462603027742720U); assert(randomx_reciprocal_fast(15000001) == 10316166306300415204U); assert(randomx_reciprocal_fast(3845182035) == 10302264209224146340U); assert(randomx_reciprocal_fast(0xffffffff) == 9223372039002259456U); }); runTest("Dataset initialization (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { initCache("test key 000"); uint64_t datasetItem[8]; randomx::initDatasetItem(cache, (uint8_t*)&datasetItem, 0); assert(datasetItem[0] == 0x680588a85ae222db); randomx::initDatasetItem(cache, (uint8_t*)&datasetItem, 10000000); assert(datasetItem[0] == 0x7943a1f6186ffb72); randomx::initDatasetItem(cache, (uint8_t*)&datasetItem, 20000000); assert(datasetItem[0] == 0x9035244d718095e1); randomx::initDatasetItem(cache, (uint8_t*)&datasetItem, 30000000); assert(datasetItem[0] == 0x145a5091f7853099); }); runTest("Dataset initialization (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { initCache("test key 000"); randomx::JitCompiler jit; jit.generateSuperscalarHash(cache->programs, cache->reciprocalCache); jit.generateDatasetInitCode(); #ifdef RANDOMX_FORCE_SECURE jit.enableExecution(); #else jit.enableAll(); #endif uint64_t datasetItem[8]; jit.getDatasetInitFunc()(cache, (uint8_t*)&datasetItem, 0, 1); assert(datasetItem[0] == 0x680588a85ae222db); jit.getDatasetInitFunc()(cache, (uint8_t*)&datasetItem, 10000000, 10000001); assert(datasetItem[0] == 0x7943a1f6186ffb72); jit.getDatasetInitFunc()(cache, (uint8_t*)&datasetItem, 20000000, 20000001); assert(datasetItem[0] == 0x9035244d718095e1); jit.getDatasetInitFunc()(cache, (uint8_t*)&datasetItem, 30000000, 30000001); assert(datasetItem[0] == 0x145a5091f7853099); }); runTest("AesGenerator1R", true, []() { char state[64] = { 0 }; hex2bin("6c19536eb2de31b6c0065f7f116e86f960d8af0c57210a6584c3237b9d064dc7", 64, state); fillAes1Rx4(state, sizeof(state), state); assert(equalsHex(state, "fa89397dd6ca422513aeadba3f124b5540324c4ad4b6db434394307a17c833ab")); }); randomx::NativeRegisterFile reg; randomx::BytecodeMachine decoder; randomx::InstructionByteCode ibc; alignas(16) randomx::ProgramConfiguration config; constexpr int registerHigh = 192; constexpr int registerDst = 0; constexpr int registerSrc = 1; int pc = 0; constexpr uint32_t imm32 = 3234567890; constexpr uint64_t imm64 = signExtend2sCompl(imm32); decoder.beginCompilation(reg); runTest("IADD_RS (decode)", RANDOMX_FREQ_IADD_RS > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IADD_RS - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.mod = UINT8_MAX; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IADD_RS); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.shift == 3); assert(ibc.imm == 0); }); runTest("IADD_RS (execute)", RANDOMX_FREQ_IADD_RS > 0, [&] { reg.r[registerDst] = 0x8000000000000000; reg.r[registerSrc] = 0x1000000000000000; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0); }); runTest("IADD_RS with immediate (decode)", RANDOMX_FREQ_IADD_RS > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IADD_RS - 1; instr.mod = 8; instr.dst = registerHigh | randomx::RegisterNeedsDisplacement; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IADD_RS); assert(ibc.idst == ®.r[randomx::RegisterNeedsDisplacement]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.shift == 2); assert(ibc.imm == imm64); }); runTest("IADD_RS with immediate (decode)", RANDOMX_FREQ_IADD_RS > 0, [&] { reg.r[randomx::RegisterNeedsDisplacement] = 0x8000000000000000; reg.r[registerSrc] = 0x2000000000000000; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[randomx::RegisterNeedsDisplacement] == imm64); }); runTest("IADD_M (decode)", RANDOMX_FREQ_IADD_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IADD_M - 1; instr.mod = 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IADD_M); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("ISUB_R (decode)", RANDOMX_FREQ_ISUB_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISUB_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISUB_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("ISUB_R (execute)", RANDOMX_FREQ_ISUB_R > 0, [&] { reg.r[registerDst] = 1; reg.r[registerSrc] = 0xFFFFFFFF; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0xFFFFFFFF00000002); }); runTest("ISUB_R with immediate (decode)", RANDOMX_FREQ_ISUB_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISUB_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISUB_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == &ibc.imm); }); runTest("ISUB_R with immediate (decode)", RANDOMX_FREQ_ISUB_R > 0, [&] { reg.r[registerDst] = 0; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == (~imm64 + 1)); }); runTest("ISUB_M (decode)", RANDOMX_FREQ_ISUB_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISUB_M - 1; instr.mod = 0; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISUB_M); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL2Mask); }); runTest("IMUL_R (decode)", RANDOMX_FREQ_IMUL_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMUL_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMUL_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("IMUL_R (execute)", RANDOMX_FREQ_IMUL_R > 0, [&] { reg.r[registerDst] = 0xBC550E96BA88A72B; reg.r[registerSrc] = 0xF5391FA9F18D6273; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0x28723424A9108E51); }); runTest("IMUL_R with immediate (decode)", RANDOMX_FREQ_IMUL_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMUL_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMUL_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == &ibc.imm); }); runTest("IMUL_R with immediate (execute)", RANDOMX_FREQ_IMUL_R > 0, [&] { reg.r[registerDst] = 1; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == imm64); }); runTest("IMUL_M (decode)", RANDOMX_FREQ_IMUL_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMUL_M - 1; instr.mod = 0; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMUL_M); assert(ibc.idst == ®.r[registerDst]); assert(*ibc.isrc == 0); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL3Mask); }); runTest("IMULH_R (decode)", RANDOMX_FREQ_IMULH_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMULH_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMULH_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("IMULH_R (execute)", RANDOMX_FREQ_IMULH_R > 0, [&] { reg.r[registerDst] = 0xBC550E96BA88A72B; reg.r[registerSrc] = 0xF5391FA9F18D6273; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0xB4676D31D2B34883); }); runTest("IMULH_R squared (decode)", RANDOMX_FREQ_IMULH_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMULH_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMULH_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerDst]); }); runTest("IMULH_M (decode)", RANDOMX_FREQ_IMULH_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMULH_M - 1; instr.mod = 0; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMULH_M); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL2Mask); }); runTest("ISMULH_R (decode)", RANDOMX_FREQ_ISMULH_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISMULH_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISMULH_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("ISMULH_R (execute)", RANDOMX_FREQ_ISMULH_R > 0, [&] { reg.r[registerDst] = 0xBC550E96BA88A72B; reg.r[registerSrc] = 0xF5391FA9F18D6273; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0x02D93EF1269D3EE5); }); runTest("ISMULH_R squared (decode)", RANDOMX_FREQ_ISMULH_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISMULH_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISMULH_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerDst]); }); runTest("ISMULH_M (decode)", RANDOMX_FREQ_ISMULH_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISMULH_M - 1; instr.mod = 3; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISMULH_M); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("IMUL_RCP (decode)", RANDOMX_FREQ_IMUL_RCP > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMUL_RCP - 1; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IMUL_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == &ibc.imm); assert(ibc.imm == randomx_reciprocal(imm32)); }); runTest("IMUL_RCP zero imm32 (decode)", RANDOMX_FREQ_IMUL_RCP > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IMUL_RCP - 1; instr.setImm32(0); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::NOP); }); runTest("INEG_R (decode)", RANDOMX_FREQ_INEG_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_INEG_R - 1; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::INEG_R); assert(ibc.idst == ®.r[registerDst]); }); runTest("INEG_R (execute)", RANDOMX_FREQ_INEG_R > 0, [&] { reg.r[registerDst] = 0xFFFFFFFFFFFFFFFF; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 1); }); runTest("IXOR_R (decode)", RANDOMX_FREQ_IXOR_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IXOR_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IXOR_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("IXOR_R (execute)", RANDOMX_FREQ_IMUL_R > 0, [&] { reg.r[registerDst] = 0x8888888888888888; reg.r[registerSrc] = 0xAAAAAAAAAAAAAAAA; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0x2222222222222222); }); runTest("IXOR_R with immediate (decode)", RANDOMX_FREQ_IXOR_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IXOR_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IXOR_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == &ibc.imm); }); runTest("IXOR_R with immediate (execute)", RANDOMX_FREQ_IXOR_R > 0, [&] { reg.r[registerDst] = 0xFFFFFFFFFFFFFFFF; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == ~imm64); }); runTest("IXOR_M (decode)", RANDOMX_FREQ_IXOR_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IXOR_M - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IXOR_M); assert(ibc.idst == ®.r[registerDst]); assert(*ibc.isrc == 0); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL3Mask); }); runTest("IROR_R (decode)", RANDOMX_FREQ_IROR_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IROR_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IROR_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("IROR_R (execute)", RANDOMX_FREQ_IROR_R > 0, [&] { reg.r[registerDst] = 953360005391419562; reg.r[registerSrc] = 4569451684712230561; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 0xD835C455069D81EF); }); runTest("IROL_R (decode)", RANDOMX_FREQ_IROL_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_IROL_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::IROL_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("IROL_R (execute)", RANDOMX_FREQ_IROL_R > 0, [&] { reg.r[registerDst] = 953360005391419562; reg.r[registerSrc] = 4569451684712230561; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 6978065200552740799); }); runTest("ISWAP_R (decode)", RANDOMX_FREQ_ISWAP_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISWAP_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISWAP_R); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); }); runTest("ISWAP_R (execute)", RANDOMX_FREQ_ISWAP_R > 0, [&] { reg.r[registerDst] = 953360005391419562; reg.r[registerSrc] = 4569451684712230561; decoder.executeInstruction(ibc, pc, nullptr, config); assert(reg.r[registerDst] == 4569451684712230561); assert(reg.r[registerSrc] == 953360005391419562); }); runTest("FSWAP_R (decode)", RANDOMX_FREQ_FSWAP_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FSWAP_R - 1; instr.dst = registerHigh | registerDst; decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FSWAP_R); assert(ibc.fdst == ®.f[registerDst]); }); runTest("FSWAP_R (execute)", RANDOMX_FREQ_FSWAP_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(953360005391419562, 4569451684712230561); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex((const char*)&vec, "aa886bb0df033b0da12e95e518f4693f")); }); runTest("FADD_R (decode)", RANDOMX_FREQ_FADD_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FADD_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FADD_R); assert(ibc.fdst == ®.f[registerDst]); assert(ibc.fsrc == ®.a[registerSrc]); }); runTest("FADD_R RoundToNearest (execute)", RANDOMX_FREQ_FADD_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0x3ffd2c97cc4ef015, 0xc1ce30b3c4223576); reg.a[registerSrc] = rx_set_vec_f128(0x402a26a86a60c8fb, 0x40b8f684057a59e1); rx_set_rounding_mode(RoundToNearest); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex(&vec, "b932e048a730cec1fea6ea633bcc2d40")); }); runTest("FADD_R RoundDown (execute)", RANDOMX_FREQ_FADD_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0x3ffd2c97cc4ef015, 0xc1ce30b3c4223576); reg.a[registerSrc] = rx_set_vec_f128(0x402a26a86a60c8fb, 0x40b8f684057a59e1); rx_set_rounding_mode(RoundDown); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex(&vec, "b932e048a730cec1fda6ea633bcc2d40")); }); runTest("FADD_R RoundUp (execute)", RANDOMX_FREQ_FADD_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0x3ffd2c97cc4ef015, 0xc1ce30b3c4223576); reg.a[registerSrc] = rx_set_vec_f128(0x402a26a86a60c8fb, 0x40b8f684057a59e1); rx_set_rounding_mode(RoundUp); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex(&vec, "b832e048a730cec1fea6ea633bcc2d40")); }); runTest("FADD_R RoundToZero (execute)", RANDOMX_FREQ_FADD_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0x3ffd2c97cc4ef015, 0xc1ce30b3c4223576); reg.a[registerSrc] = rx_set_vec_f128(0x402a26a86a60c8fb, 0x40b8f684057a59e1); rx_set_rounding_mode(RoundToZero); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex(&vec, "b832e048a730cec1fda6ea633bcc2d40")); }); runTest("FADD_M (decode)", RANDOMX_FREQ_FADD_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FADD_M - 1; instr.mod = 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FADD_M); assert(ibc.fdst == ®.f[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("FADD_M (execute)", RANDOMX_FREQ_FADD_R > 0, [&] { uint64_t mockScratchpad; store64(&mockScratchpad, 0x1234567890abcdef); alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0, 0); reg.r[registerSrc] = 0xFFFFFFFFFFFFE930; rx_set_rounding_mode(RoundToNearest); decoder.executeInstruction(ibc, pc, (uint8_t*)&mockScratchpad, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex(&vec, "000040840cd5dbc1000000785634b241")); }); runTest("FSUB_R (decode)", RANDOMX_FREQ_FSUB_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FSUB_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FSUB_R); assert(ibc.fdst == ®.f[registerDst]); assert(ibc.fsrc == ®.a[registerSrc]); }); runTest("FSUB_M (decode)", RANDOMX_FREQ_FSUB_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FSUB_M - 1; instr.mod = 2; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FSUB_M); assert(ibc.fdst == ®.f[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("FSCAL_R (decode)", RANDOMX_FREQ_FSCAL_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FSCAL_R - 1; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FSCAL_R); assert(ibc.fdst == ®.f[registerDst]); }); runTest("FSCAL_R (execute)", RANDOMX_FREQ_FSCAL_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.f[registerDst] = rx_set_vec_f128(0x41dbc35cef248783, 0x40fdfdabb6173d07); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.f[registerDst]); assert(equalsHex((const char*)&vec, "073d17b6abfd0dc0838724ef5cc32bc1")); }); runTest("FMUL_R (decode)", RANDOMX_FREQ_FMUL_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FMUL_R - 1; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FMUL_R); assert(ibc.fdst == ®.e[registerDst]); assert(ibc.fsrc == ®.a[registerSrc]); }); runTest("FMUL_R RoundToNearest (execute)", RANDOMX_FREQ_FMUL_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41dbc35cef248783, 0x40fdfdabb6173d07); reg.a[registerSrc] = rx_set_vec_f128(0x40eba861aa31c7c0, 0x41c4561212ae2d50); rx_set_rounding_mode(RoundToNearest); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "69697aff350fd3422f1589cdecfed742")); }); runTest("FMUL_R RoundDown/RoundToZero (execute)", RANDOMX_FREQ_FMUL_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41dbc35cef248783, 0x40fdfdabb6173d07); reg.a[registerSrc] = rx_set_vec_f128(0x40eba861aa31c7c0, 0x41c4561212ae2d50); rx_set_rounding_mode(RoundDown); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "69697aff350fd3422e1589cdecfed742")); }); runTest("FMUL_R RoundUp (execute)", RANDOMX_FREQ_FMUL_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41dbc35cef248783, 0x40fdfdabb6173d07); reg.a[registerSrc] = rx_set_vec_f128(0x40eba861aa31c7c0, 0x41c4561212ae2d50); rx_set_rounding_mode(RoundUp); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "6a697aff350fd3422f1589cdecfed742")); }); runTest("FDIV_M (decode)", RANDOMX_FREQ_FDIV_M > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FDIV_M - 1; instr.mod = 3; instr.dst = registerHigh | registerDst; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FDIV_M); assert(ibc.fdst == ®.e[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("FDIV_M RoundToNearest (execute)", RANDOMX_FREQ_FDIV_M > 0, [&] { alignas(16) uint64_t vec[2]; alignas(16) uint32_t mockScratchpad[2]; store32(&mockScratchpad[0], 0xd350a1b6); store32(&mockScratchpad[1], 0x8b2460d9); store64(&config.eMask[0], 0x3a0000000005d11a); store64(&config.eMask[1], 0x39000000001ba31e); reg.e[registerDst] = rx_set_vec_f128(0x41937f76fede16ee, 0x411b414296ce93b6); reg.r[registerSrc] = 0xFFFFFFFFFFFFE930; rx_set_rounding_mode(RoundToNearest); decoder.executeInstruction(ibc, pc, (uint8_t*)&mockScratchpad, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e7b269639484434632474a66635ba547")); }); runTest("FDIV_M RoundDown/RoundToZero (execute)", RANDOMX_FREQ_FDIV_M > 0, [&] { alignas(16) uint64_t vec[2]; alignas(16) uint32_t mockScratchpad[2]; store32(&mockScratchpad[0], 0xd350a1b6); store32(&mockScratchpad[1], 0x8b2460d9); store64(&config.eMask[0], 0x3a0000000005d11a); store64(&config.eMask[1], 0x39000000001ba31e); reg.e[registerDst] = rx_set_vec_f128(0x41937f76fede16ee, 0x411b414296ce93b6); reg.r[registerSrc] = 0xFFFFFFFFFFFFE930; rx_set_rounding_mode(RoundDown); decoder.executeInstruction(ibc, pc, (uint8_t*)&mockScratchpad, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e6b269639484434632474a66635ba547")); }); runTest("FDIV_M RoundUp (execute)", RANDOMX_FREQ_FDIV_M > 0, [&] { alignas(16) uint64_t vec[2]; alignas(16) uint32_t mockScratchpad[2]; store32(&mockScratchpad[0], 0xd350a1b6); store32(&mockScratchpad[1], 0x8b2460d9); store64(&config.eMask[0], 0x3a0000000005d11a); store64(&config.eMask[1], 0x39000000001ba31e); reg.e[registerDst] = rx_set_vec_f128(0x41937f76fede16ee, 0x411b414296ce93b6); reg.r[registerSrc] = 0xFFFFFFFFFFFFE930; rx_set_rounding_mode(RoundUp); decoder.executeInstruction(ibc, pc, (uint8_t*)&mockScratchpad, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e7b269639484434633474a66635ba547")); }); runTest("FSQRT_R (decode)", RANDOMX_FREQ_FSQRT_R > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_FSQRT_R - 1; instr.dst = registerHigh | registerDst; decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::FSQRT_R); assert(ibc.fdst == ®.e[registerDst]); }); runTest("FSQRT_R RoundToNearest (execute)", RANDOMX_FREQ_FSQRT_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41b6b21c11affea7, 0x40526a7e778d9824); rx_set_rounding_mode(RoundToNearest); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e81f300b612a21408dbaa33f570ed340")); }); runTest("FSQRT_R RoundDown/RoundToZero (execute)", RANDOMX_FREQ_FSQRT_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41b6b21c11affea7, 0x40526a7e778d9824); rx_set_rounding_mode(RoundDown); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e81f300b612a21408cbaa33f570ed340")); }); runTest("FSQRT_R RoundUp (execute)", RANDOMX_FREQ_FSQRT_R > 0, [&] { alignas(16) uint64_t vec[2]; reg.e[registerDst] = rx_set_vec_f128(0x41b6b21c11affea7, 0x40526a7e778d9824); rx_set_rounding_mode(RoundUp); decoder.executeInstruction(ibc, pc, nullptr, config); rx_store_vec_f128((double*)&vec, reg.e[registerDst]); assert(equalsHex(&vec, "e91f300b612a21408dbaa33f570ed340")); }); runTest("CBRANCH (decode) 100", RANDOMX_FREQ_CBRANCH > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_CBRANCH - 1; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); instr.mod = 48; decoder.compileInstruction(instr, 100, ibc); assert(ibc.type == randomx::InstructionType::CBRANCH); assert(ibc.idst == ®.r[registerDst]); assert(ibc.imm == 0xFFFFFFFFC0CB9AD2); assert(ibc.memMask == 0x7F800); assert(ibc.target == pc); }); runTest("CBRANCH (decode) 200", RANDOMX_FREQ_CBRANCH > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_CBRANCH - 1; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); instr.mod = 48; decoder.compileInstruction(instr, pc = 200, ibc); assert(ibc.type == randomx::InstructionType::CBRANCH); assert(ibc.idst == ®.r[registerDst]); assert(ibc.imm == 0xFFFFFFFFC0CB9AD2); assert(ibc.memMask == 0x7F800); assert(ibc.target == 100); }); runTest("CBRANCH not taken (execute)", RANDOMX_FREQ_CBRANCH > 0, [&] { reg.r[registerDst] = 0; decoder.executeInstruction(ibc, pc, nullptr, config); assert(pc == 200); }); runTest("CBRANCH taken (execute)", RANDOMX_FREQ_CBRANCH > 0, [&] { reg.r[registerDst] = 0xFFFFFFFFFFFC6800; decoder.executeInstruction(ibc, pc, nullptr, config); assert(pc == ibc.target); }); runTest("CFROUND (decode)", RANDOMX_FREQ_CFROUND > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_CFROUND - 1; instr.src = registerHigh | registerSrc; instr.setImm32(imm32); decoder.compileInstruction(instr, 100, ibc); assert(ibc.type == randomx::InstructionType::CFROUND); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == 18); }); runTest("ISTORE L1 (decode)", RANDOMX_FREQ_ISTORE > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISTORE - 1; instr.src = registerHigh | registerSrc; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); instr.mod = 1; decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISTORE); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL1Mask); }); runTest("ISTORE L2 (decode)", RANDOMX_FREQ_ISTORE > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISTORE - 1; instr.src = registerHigh | registerSrc; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); instr.mod = 0; decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISTORE); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL2Mask); }); runTest("ISTORE L3 (decode)", RANDOMX_FREQ_ISTORE > 0, [&] { randomx::Instruction instr; instr.opcode = randomx::ceil_ISTORE - 1; instr.src = registerHigh | registerSrc; instr.dst = registerHigh | registerDst; instr.setImm32(imm32); instr.mod = 224; decoder.compileInstruction(instr, pc, ibc); assert(ibc.type == randomx::InstructionType::ISTORE); assert(ibc.idst == ®.r[registerDst]); assert(ibc.isrc == ®.r[registerSrc]); assert(ibc.imm == imm64); assert(ibc.memMask == randomx::ScratchpadL3Mask); }); #ifdef RANDOMX_FORCE_SECURE vm = randomx_create_vm(RANDOMX_FLAG_DEFAULT | RANDOMX_FLAG_SECURE, cache, nullptr); #else vm = randomx_create_vm(RANDOMX_FLAG_DEFAULT, cache, nullptr); #endif auto test_a = [&] { char hash[RANDOMX_HASH_SIZE]; calcStringHash("test key 000", "This is a test", &hash); assert(equalsHex(hash, "639183aae1bf4c9a35884cb46b09cad9175f04efd7684e7262a0ac1c2f0b4e3f")); }; auto test_b = [&] { char hash[RANDOMX_HASH_SIZE]; calcStringHash("test key 000", "Lorem ipsum dolor sit amet", &hash); assert(equalsHex(hash, "300a0adb47603dedb42228ccb2b211104f4da45af709cd7547cd049e9489c969")); }; auto test_c = [&] { char hash[RANDOMX_HASH_SIZE]; calcStringHash("test key 000", "sed do eiusmod tempor incididunt ut labore et dolore magna aliqua", &hash); assert(equalsHex(hash, "c36d4ed4191e617309867ed66a443be4075014e2b061bcdaf9ce7b721d2b77a8")); }; auto test_d = [&] { char hash[RANDOMX_HASH_SIZE]; calcStringHash("test key 001", "sed do eiusmod tempor incididunt ut labore et dolore magna aliqua", &hash); assert(equalsHex(hash, "e9ff4503201c0c2cca26d285c93ae883f9b1d30c9eb240b820756f2d5a7905fc")); }; auto test_e = [&] { char hash[RANDOMX_HASH_SIZE]; calcHexHash("test key 001", "0b0b98bea7e805e0010a2126d287a2a0cc833d312cb786385a7c2f9de69d25537f584a9bc9977b00000000666fd8753bf61a8631f12984e3fd44f4014eca629276817b56f32e9b68bd82f416", &hash); //std::cout << std::endl; //outputHex(std::cout, (const char*)hash, sizeof(hash)); //std::cout << std::endl; assert(equalsHex(hash, "c56414121acda1713c2f2a819d8ae38aed7c80c35c2a769298d34f03833cd5f1")); }; runTest("Hash test 1a (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_a); runTest("Hash test 1b (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_b); runTest("Hash test 1c (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_c); runTest("Hash test 1d (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_d); runTest("Hash test 1e (interpreter)", stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_e); if (RANDOMX_HAVE_COMPILER) { randomx_release_cache(cache); randomx_destroy_vm(vm); vm = nullptr; cache = randomx_alloc_cache(RANDOMX_FLAG_JIT); initCache("test key 000"); #ifdef RANDOMX_FORCE_SECURE vm = randomx_create_vm(RANDOMX_FLAG_JIT | RANDOMX_FLAG_SECURE, cache, nullptr); #else vm = randomx_create_vm(RANDOMX_FLAG_JIT, cache, nullptr); #endif } runTest("Hash test 2a (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_a); runTest("Hash test 2b (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_b); runTest("Hash test 2c (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_c); runTest("Hash test 2d (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_d); runTest("Hash test 2e (compiler)", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), test_e); auto flags = randomx_get_flags(); randomx_release_cache(cache); cache = randomx_alloc_cache(RANDOMX_FLAG_ARGON2_SSSE3); runTest("Cache initialization: SSSE3", (flags & RANDOMX_FLAG_ARGON2_SSSE3) && RANDOMX_ARGON_ITERATIONS == 3 && RANDOMX_ARGON_LANES == 1 && RANDOMX_ARGON_MEMORY == 262144 && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { initCache("test key 000"); uint64_t* cacheMemory = (uint64_t*)cache->memory; assert(cacheMemory[0] == 0x191e0e1d23c02186); assert(cacheMemory[1568413] == 0xf1b62fe6210bf8b1); assert(cacheMemory[33554431] == 0x1f47f056d05cd99b); }); if (cache != nullptr) randomx_release_cache(cache); cache = randomx_alloc_cache(RANDOMX_FLAG_ARGON2_AVX2); runTest("Cache initialization: AVX2", (flags & RANDOMX_FLAG_ARGON2_AVX2) && RANDOMX_ARGON_ITERATIONS == 3 && RANDOMX_ARGON_LANES == 1 && RANDOMX_ARGON_MEMORY == 262144 && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { initCache("test key 000"); uint64_t* cacheMemory = (uint64_t*)cache->memory; assert(cacheMemory[0] == 0x191e0e1d23c02186); assert(cacheMemory[1568413] == 0xf1b62fe6210bf8b1); assert(cacheMemory[33554431] == 0x1f47f056d05cd99b); }); if (cache != nullptr) randomx_release_cache(cache); cache = randomx_alloc_cache(RANDOMX_FLAG_DEFAULT); runTest("Hash batch test", RANDOMX_HAVE_COMPILER && stringsEqual(RANDOMX_ARGON_SALT, "RandomX\x03"), []() { char hash1[RANDOMX_HASH_SIZE]; char hash2[RANDOMX_HASH_SIZE]; char hash3[RANDOMX_HASH_SIZE]; initCache("test key 000"); char input1[] = "This is a test"; char input2[] = "Lorem ipsum dolor sit amet"; char input3[] = "sed do eiusmod tempor incididunt ut labore et dolore magna aliqua"; randomx_calculate_hash_first(vm, input1, sizeof(input1) - 1); randomx_calculate_hash_next(vm, input2, sizeof(input2) - 1, &hash1); randomx_calculate_hash_next(vm, input3, sizeof(input3) - 1, &hash2); randomx_calculate_hash_last(vm, &hash3); assert(equalsHex(hash1, "639183aae1bf4c9a35884cb46b09cad9175f04efd7684e7262a0ac1c2f0b4e3f")); assert(equalsHex(hash2, "300a0adb47603dedb42228ccb2b211104f4da45af709cd7547cd049e9489c969")); assert(equalsHex(hash3, "c36d4ed4191e617309867ed66a443be4075014e2b061bcdaf9ce7b721d2b77a8")); }); runTest("Preserve rounding mode", RANDOMX_FREQ_CFROUND > 0, []() { rx_set_rounding_mode(RoundToNearest); char hash[RANDOMX_HASH_SIZE]; calcStringHash("test key 000", "Lorem ipsum dolor sit amet", &hash); assert(equalsHex(hash, "300a0adb47603dedb42228ccb2b211104f4da45af709cd7547cd049e9489c969")); assert(rx_get_rounding_mode() == RoundToNearest); }); randomx_destroy_vm(vm); vm = nullptr; if (cache != nullptr) randomx_release_cache(cache); std::cout << std::endl << "All tests PASSED" << std::endl; if (skipped) { std::cout << skipped << " tests were SKIPPED due to incompatible configuration (see above)" << std::endl; } } RandomX-1.1.10/src/tests/utility.hpp000066400000000000000000000074421414227164600173250ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include #include constexpr char hexmap[] = "0123456789abcdef"; inline void outputHex(std::ostream& os, const char* data, int length) { for (int i = 0; i < length; ++i) { os << hexmap[(data[i] & 0xF0) >> 4]; os << hexmap[data[i] & 0x0F]; } } char parseNibble(char hex) { hex &= ~0x20; if (hex & 0x40) { hex -= 'A' - 10; } else { hex &= 0xf; } return hex; } void hex2bin(const char *in, int length, char *out) { for (int i = 0; i < length; i += 2) { char nibble1 = parseNibble(*in++); char nibble2 = parseNibble(*in++); *out++ = nibble1 << 4 | nibble2; } } constexpr bool stringsEqual(char const * a, char const * b) { return *a == *b && (*a == '\0' || stringsEqual(a + 1, b + 1)); } template bool equalsHex(const void* hash, const char (&hex)[N]) { char reference[N / 2]; hex2bin(hex, N - 1, reference); return memcmp(hash, reference, sizeof(reference)) == 0; } inline void dump(const char* buffer, uint64_t count, const char* name) { std::ofstream fout(name, std::ios::out | std::ios::binary); fout.write(buffer, count); fout.close(); } inline void readOption(const char* option, int argc, char** argv, bool& out) { for (int i = 0; i < argc; ++i) { if (strcmp(argv[i], option) == 0) { out = true; return; } } out = false; } inline void readIntOption(const char* option, int argc, char** argv, int& out, int defaultValue) { for (int i = 0; i < argc - 1; ++i) { if (strcmp(argv[i], option) == 0 && (out = atoi(argv[i + 1])) > 0) { return; } } out = defaultValue; } inline void readUInt64Option(const char* option, int argc, char** argv, uint64_t& out, uint64_t defaultValue) { for (int i = 0; i < argc - 1; ++i) { if (strcmp(argv[i], option) == 0 && (out = std::strtoull(argv[i + 1], NULL, 0)) > 0) { return; } } out = defaultValue; } inline void readFloatOption(const char* option, int argc, char** argv, double& out, double defaultValue) { for (int i = 0; i < argc - 1; ++i) { if (strcmp(argv[i], option) == 0 && (out = atof(argv[i + 1])) > 0) { return; } } out = defaultValue; } inline void readInt(int argc, char** argv, int& out, int defaultValue) { for (int i = 0; i < argc; ++i) { if (*argv[i] != '-' && (out = atoi(argv[i])) > 0) { return; } } out = defaultValue; } RandomX-1.1.10/src/virtual_machine.cpp000066400000000000000000000131461414227164600176230ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "virtual_machine.hpp" #include "common.hpp" #include "aes_hash.hpp" #include "blake2/blake2.h" #include "intrin_portable.h" #include "allocator.hpp" randomx_vm::~randomx_vm() { } void randomx_vm::resetRoundingMode() { rx_reset_float_state(); } namespace randomx { static inline uint64_t getSmallPositiveFloatBits(uint64_t entropy) { auto exponent = entropy >> 59; //0..31 auto mantissa = entropy & mantissaMask; exponent += exponentBias; exponent &= exponentMask; exponent <<= mantissaSize; return exponent | mantissa; } static inline uint64_t getStaticExponent(uint64_t entropy) { auto exponent = constExponentBits; exponent |= (entropy >> (64 - staticExponentBits)) << dynamicExponentBits; exponent <<= mantissaSize; return exponent; } static inline uint64_t getFloatMask(uint64_t entropy) { constexpr uint64_t mask22bit = (1ULL << 22) - 1; return (entropy & mask22bit) | getStaticExponent(entropy); } } void randomx_vm::initialize() { store64(®.a[0].lo, randomx::getSmallPositiveFloatBits(program.getEntropy(0))); store64(®.a[0].hi, randomx::getSmallPositiveFloatBits(program.getEntropy(1))); store64(®.a[1].lo, randomx::getSmallPositiveFloatBits(program.getEntropy(2))); store64(®.a[1].hi, randomx::getSmallPositiveFloatBits(program.getEntropy(3))); store64(®.a[2].lo, randomx::getSmallPositiveFloatBits(program.getEntropy(4))); store64(®.a[2].hi, randomx::getSmallPositiveFloatBits(program.getEntropy(5))); store64(®.a[3].lo, randomx::getSmallPositiveFloatBits(program.getEntropy(6))); store64(®.a[3].hi, randomx::getSmallPositiveFloatBits(program.getEntropy(7))); mem.ma = program.getEntropy(8) & randomx::CacheLineAlignMask; mem.mx = program.getEntropy(10); auto addressRegisters = program.getEntropy(12); config.readReg0 = 0 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg1 = 2 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg2 = 4 + (addressRegisters & 1); addressRegisters >>= 1; config.readReg3 = 6 + (addressRegisters & 1); datasetOffset = (program.getEntropy(13) % (randomx::DatasetExtraItems + 1)) * randomx::CacheLineSize; store64(&config.eMask[0], randomx::getFloatMask(program.getEntropy(14))); store64(&config.eMask[1], randomx::getFloatMask(program.getEntropy(15))); } namespace randomx { alignas(16) volatile static rx_vec_i128 aesDummy; template VmBase::~VmBase() { Allocator::freeMemory(scratchpad, ScratchpadSize); } template void VmBase::allocate() { if (datasetPtr == nullptr) throw std::invalid_argument("Cache/Dataset not set"); if (!softAes) { //if hardware AES is not supported, it's better to fail now than to return a ticking bomb rx_vec_i128 tmp = rx_load_vec_i128((const rx_vec_i128*)&aesDummy); tmp = rx_aesenc_vec_i128(tmp, tmp); rx_store_vec_i128((rx_vec_i128*)&aesDummy, tmp); } scratchpad = (uint8_t*)Allocator::allocMemory(ScratchpadSize); } template void VmBase::getFinalResult(void* out, size_t outSize) { hashAes1Rx4(scratchpad, ScratchpadSize, ®.a); blake2b(out, outSize, ®, sizeof(RegisterFile), nullptr, 0); } template void VmBase::hashAndFill(void* out, size_t outSize, uint64_t *fill_state) { hashAndFillAes1Rx4((void*) getScratchpad(), ScratchpadSize, ®.a, fill_state); blake2b(out, outSize, ®, sizeof(RegisterFile), nullptr, 0); } template void VmBase::initScratchpad(void* seed) { fillAes1Rx4(seed, ScratchpadSize, scratchpad); } template void VmBase::generateProgram(void* seed) { fillAes4Rx4(seed, sizeof(program), &program); } template class VmBase, false>; template class VmBase, true>; template class VmBase; template class VmBase; }RandomX-1.1.10/src/virtual_machine.hpp000066400000000000000000000061271414227164600176310ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "common.hpp" #include "program.hpp" /* Global namespace for C binding */ class randomx_vm { public: virtual ~randomx_vm() = 0; virtual void allocate() = 0; virtual void getFinalResult(void* out, size_t outSize) = 0; virtual void hashAndFill(void* out, size_t outSize, uint64_t *fill_state) = 0; virtual void setDataset(randomx_dataset* dataset) { } virtual void setCache(randomx_cache* cache) { } virtual void initScratchpad(void* seed) = 0; virtual void run(void* seed) = 0; void resetRoundingMode(); randomx::RegisterFile *getRegisterFile() { return ® } const void* getScratchpad() { return scratchpad; } const randomx::Program& getProgram() { return program; } const uint8_t* getMemory() const { return mem.memory; } protected: void initialize(); alignas(64) randomx::Program program; alignas(64) randomx::RegisterFile reg; alignas(16) randomx::ProgramConfiguration config; randomx::MemoryRegisters mem; uint8_t* scratchpad = nullptr; union { randomx_cache* cachePtr = nullptr; randomx_dataset* datasetPtr; }; uint64_t datasetOffset; public: std::string cacheKey; alignas(16) uint64_t tempHash[8]; //8 64-bit values used to store intermediate data }; namespace randomx { template class VmBase : public randomx_vm { public: ~VmBase() override; void allocate() override; void initScratchpad(void* seed) override; void getFinalResult(void* out, size_t outSize) override; void hashAndFill(void* out, size_t outSize, uint64_t *fill_state) override; protected: void generateProgram(void* seed); }; } RandomX-1.1.10/src/virtual_memory.cpp000066400000000000000000000145001414227164600175220ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "virtual_memory.hpp" #include #if defined(_WIN32) || defined(__CYGWIN__) #include #else #ifdef __APPLE__ #include #include # ifdef TARGET_OS_OSX # define USE_PTHREAD_JIT_WP 1 # include # endif #endif #include #include #ifndef MAP_ANONYMOUS #define MAP_ANONYMOUS MAP_ANON #endif #define PAGE_READONLY PROT_READ #define PAGE_READWRITE (PROT_READ | PROT_WRITE) #define PAGE_EXECUTE_READ (PROT_READ | PROT_EXEC) #define PAGE_EXECUTE_READWRITE (PROT_READ | PROT_WRITE | PROT_EXEC) #endif #if defined(_WIN32) || defined(__CYGWIN__) std::string getErrorMessage(const char* function) { LPSTR messageBuffer = nullptr; size_t size = FormatMessageA(FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS, NULL, GetLastError(), MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), (LPSTR)&messageBuffer, 0, NULL); std::string message(messageBuffer, size); LocalFree(messageBuffer); return std::string(function) + std::string(": ") + message; } void setPrivilege(const char* pszPrivilege, BOOL bEnable) { HANDLE hToken; TOKEN_PRIVILEGES tp; BOOL status; DWORD error; if (!OpenProcessToken(GetCurrentProcess(), TOKEN_ADJUST_PRIVILEGES | TOKEN_QUERY, &hToken)) throw std::runtime_error(getErrorMessage("OpenProcessToken")); if (!LookupPrivilegeValue(NULL, pszPrivilege, &tp.Privileges[0].Luid)) throw std::runtime_error(getErrorMessage("LookupPrivilegeValue")); tp.PrivilegeCount = 1; if (bEnable) tp.Privileges[0].Attributes = SE_PRIVILEGE_ENABLED; else tp.Privileges[0].Attributes = 0; status = AdjustTokenPrivileges(hToken, FALSE, &tp, 0, (PTOKEN_PRIVILEGES)NULL, 0); error = GetLastError(); if (!status || (error != ERROR_SUCCESS)) throw std::runtime_error(getErrorMessage("AdjustTokenPrivileges")); if (!CloseHandle(hToken)) throw std::runtime_error(getErrorMessage("CloseHandle")); } #endif void* allocMemoryPages(std::size_t bytes) { void* mem; #if defined(_WIN32) || defined(__CYGWIN__) mem = VirtualAlloc(nullptr, bytes, MEM_COMMIT, PAGE_READWRITE); if (mem == nullptr) throw std::runtime_error(getErrorMessage("allocMemoryPages - VirtualAlloc")); #else #if defined(__NetBSD__) #define RESERVED_FLAGS PROT_MPROTECT(PROT_EXEC) #else #define RESERVED_FLAGS 0 #endif #ifdef USE_PTHREAD_JIT_WP #define MEXTRA MAP_JIT #define PEXTRA PROT_EXEC #else #define MEXTRA 0 #define PEXTRA 0 #endif mem = mmap(nullptr, bytes, PAGE_READWRITE | RESERVED_FLAGS | PEXTRA, MAP_ANONYMOUS | MAP_PRIVATE | MEXTRA, -1, 0); if (mem == MAP_FAILED) throw std::runtime_error("allocMemoryPages - mmap failed"); #ifdef USE_PTHREAD_JIT_WP pthread_jit_write_protect_np(false); #endif #endif return mem; } static inline void pageProtect(void* ptr, std::size_t bytes, int rules) { #if defined(_WIN32) || defined(__CYGWIN__) DWORD oldp; if (!VirtualProtect(ptr, bytes, (DWORD)rules, &oldp)) { throw std::runtime_error(getErrorMessage("VirtualProtect")); } #else if (-1 == mprotect(ptr, bytes, rules)) throw std::runtime_error("mprotect failed"); #endif } void setPagesRW(void* ptr, std::size_t bytes) { #ifdef USE_PTHREAD_JIT_WP pthread_jit_write_protect_np(false); #else pageProtect(ptr, bytes, PAGE_READWRITE); #endif } void setPagesRX(void* ptr, std::size_t bytes) { #ifdef USE_PTHREAD_JIT_WP pthread_jit_write_protect_np(true); #else pageProtect(ptr, bytes, PAGE_EXECUTE_READ); #endif } void setPagesRWX(void* ptr, std::size_t bytes) { pageProtect(ptr, bytes, PAGE_EXECUTE_READWRITE); } void* allocLargePagesMemory(std::size_t bytes) { void* mem; #if defined(_WIN32) || defined(__CYGWIN__) setPrivilege("SeLockMemoryPrivilege", 1); auto pageMinimum = GetLargePageMinimum(); if (pageMinimum > 0) mem = VirtualAlloc(NULL, alignSize(bytes, pageMinimum), MEM_COMMIT | MEM_RESERVE | MEM_LARGE_PAGES, PAGE_READWRITE); else throw std::runtime_error("allocLargePagesMemory - Large pages are not supported"); if (mem == nullptr) throw std::runtime_error(getErrorMessage("allocLargePagesMemory - VirtualAlloc")); #else #ifdef __APPLE__ mem = mmap(nullptr, bytes, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, VM_FLAGS_SUPERPAGE_SIZE_2MB, 0); #elif defined(__FreeBSD__) mem = mmap(nullptr, bytes, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS | MAP_ALIGNED_SUPER, -1, 0); #elif defined(__OpenBSD__) || defined(__NetBSD__) mem = MAP_FAILED; // OpenBSD does not support huge pages #else mem = mmap(nullptr, bytes, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB | MAP_POPULATE, -1, 0); #endif if (mem == MAP_FAILED) throw std::runtime_error("allocLargePagesMemory - mmap failed"); #endif return mem; } void freePagedMemory(void* ptr, std::size_t bytes) { #if defined(_WIN32) || defined(__CYGWIN__) VirtualFree(ptr, 0, MEM_RELEASE); #else munmap(ptr, bytes); #endif } RandomX-1.1.10/src/virtual_memory.hpp000066400000000000000000000035601414227164600175330ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include constexpr std::size_t alignSize(std::size_t pos, std::size_t align) { return ((pos - 1) / align + 1) * align; } void* allocMemoryPages(std::size_t); void setPagesRW(void*, std::size_t); void setPagesRX(void*, std::size_t); void setPagesRWX(void*, std::size_t); void* allocLargePagesMemory(std::size_t); void freePagedMemory(void*, std::size_t); RandomX-1.1.10/src/vm_compiled.cpp000066400000000000000000000066121414227164600167470ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "vm_compiled.hpp" #include "common.hpp" namespace randomx { static_assert(sizeof(MemoryRegisters) == 2 * sizeof(addr_t) + sizeof(uintptr_t), "Invalid alignment of struct randomx::MemoryRegisters"); static_assert(sizeof(RegisterFile) == 256, "Invalid alignment of struct randomx::RegisterFile"); template CompiledVm::CompiledVm() { if (!secureJit) { compiler.enableAll(); //make JIT buffer both writable and executable } } template void CompiledVm::setDataset(randomx_dataset* dataset) { datasetPtr = dataset; } template void CompiledVm::run(void* seed) { VmBase::generateProgram(seed); randomx_vm::initialize(); if (secureJit) { compiler.enableWriting(); } compiler.generateProgram(program, config); if (secureJit) { compiler.enableExecution(); } mem.memory = datasetPtr->memory + datasetOffset; execute(); } template void CompiledVm::execute() { #ifdef __aarch64__ memcpy(reg.f, config.eMask, sizeof(config.eMask)); #endif compiler.getProgramFunc()(reg, mem, scratchpad, RANDOMX_PROGRAM_ITERATIONS); } template class CompiledVm, false, false>; template class CompiledVm, true, false>; template class CompiledVm; template class CompiledVm; template class CompiledVm, false, true>; template class CompiledVm, true, true>; template class CompiledVm; template class CompiledVm; }RandomX-1.1.10/src/vm_compiled.hpp000066400000000000000000000063021414227164600167500ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include "virtual_machine.hpp" #include "jit_compiler.hpp" #include "allocator.hpp" #include "dataset.hpp" namespace randomx { template class CompiledVm : public VmBase { public: void* operator new(size_t size) { void* ptr = AlignedAllocator::allocMemory(size); if (ptr == nullptr) throw std::bad_alloc(); return ptr; } void operator delete(void* ptr) { AlignedAllocator::freeMemory(ptr, sizeof(CompiledVm)); } CompiledVm(); void setDataset(randomx_dataset* dataset) override; void run(void* seed) override; using VmBase::mem; using VmBase::program; using VmBase::config; using VmBase::reg; using VmBase::scratchpad; using VmBase::datasetPtr; using VmBase::datasetOffset; protected: void execute(); JitCompiler compiler; }; using CompiledVmDefault = CompiledVm, true, false>; using CompiledVmHardAes = CompiledVm, false, false>; using CompiledVmLargePage = CompiledVm; using CompiledVmLargePageHardAes = CompiledVm; using CompiledVmDefaultSecure = CompiledVm, true, true>; using CompiledVmHardAesSecure = CompiledVm, false, true>; using CompiledVmLargePageSecure = CompiledVm; using CompiledVmLargePageHardAesSecure = CompiledVm; } RandomX-1.1.10/src/vm_compiled_light.cpp000066400000000000000000000057201414227164600201350ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "vm_compiled_light.hpp" #include "common.hpp" #include namespace randomx { template void CompiledLightVm::setCache(randomx_cache* cache) { cachePtr = cache; mem.memory = cache->memory; if (secureJit) { compiler.enableWriting(); } compiler.generateSuperscalarHash(cache->programs, cache->reciprocalCache); if (secureJit) { compiler.enableExecution(); } } template void CompiledLightVm::run(void* seed) { VmBase::generateProgram(seed); randomx_vm::initialize(); if (secureJit) { compiler.enableWriting(); } compiler.generateProgramLight(program, config, datasetOffset); if (secureJit) { compiler.enableExecution(); } CompiledVm::execute(); } template class CompiledLightVm, false, false>; template class CompiledLightVm, true, false>; template class CompiledLightVm; template class CompiledLightVm; template class CompiledLightVm, false, true>; template class CompiledLightVm, true, true>; template class CompiledLightVm; template class CompiledLightVm; }RandomX-1.1.10/src/vm_compiled_light.hpp000066400000000000000000000063401414227164600201410ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "vm_compiled.hpp" namespace randomx { template class CompiledLightVm : public CompiledVm { public: void* operator new(size_t size) { void* ptr = AlignedAllocator::allocMemory(size); if (ptr == nullptr) throw std::bad_alloc(); return ptr; } void operator delete(void* ptr) { AlignedAllocator::freeMemory(ptr, sizeof(CompiledLightVm)); } void setCache(randomx_cache* cache) override; void setDataset(randomx_dataset* dataset) override { } void run(void* seed) override; using CompiledVm::mem; using CompiledVm::compiler; using CompiledVm::program; using CompiledVm::config; using CompiledVm::cachePtr; using CompiledVm::datasetOffset; }; using CompiledLightVmDefault = CompiledLightVm, true, false>; using CompiledLightVmHardAes = CompiledLightVm, false, false>; using CompiledLightVmLargePage = CompiledLightVm; using CompiledLightVmLargePageHardAes = CompiledLightVm; using CompiledLightVmDefaultSecure = CompiledLightVm, true, true>; using CompiledLightVmHardAesSecure = CompiledLightVm, false, true>; using CompiledLightVmLargePageSecure = CompiledLightVm; using CompiledLightVmLargePageHardAesSecure = CompiledLightVm; }RandomX-1.1.10/src/vm_interpreted.cpp000066400000000000000000000112371414227164600174770ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include "vm_interpreted.hpp" #include "dataset.hpp" #include "intrin_portable.h" #include "reciprocal.h" namespace randomx { template void InterpretedVm::setDataset(randomx_dataset* dataset) { datasetPtr = dataset; mem.memory = dataset->memory; } template void InterpretedVm::run(void* seed) { VmBase::generateProgram(seed); randomx_vm::initialize(); execute(); } template void InterpretedVm::execute() { NativeRegisterFile nreg; for(unsigned i = 0; i < RegisterCountFlt; ++i) nreg.a[i] = rx_load_vec_f128(®.a[i].lo); compileProgram(program, bytecode, nreg); uint32_t spAddr0 = mem.mx; uint32_t spAddr1 = mem.ma; for(unsigned ic = 0; ic < RANDOMX_PROGRAM_ITERATIONS; ++ic) { uint64_t spMix = nreg.r[config.readReg0] ^ nreg.r[config.readReg1]; spAddr0 ^= spMix; spAddr0 &= ScratchpadL3Mask64; spAddr1 ^= spMix >> 32; spAddr1 &= ScratchpadL3Mask64; for (unsigned i = 0; i < RegistersCount; ++i) nreg.r[i] ^= load64(scratchpad + spAddr0 + 8 * i); for (unsigned i = 0; i < RegisterCountFlt; ++i) nreg.f[i] = rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * i); for (unsigned i = 0; i < RegisterCountFlt; ++i) nreg.e[i] = maskRegisterExponentMantissa(config, rx_cvt_packed_int_vec_f128(scratchpad + spAddr1 + 8 * (RegisterCountFlt + i))); executeBytecode(bytecode, scratchpad, config); mem.mx ^= nreg.r[config.readReg2] ^ nreg.r[config.readReg3]; mem.mx &= CacheLineAlignMask; datasetPrefetch(datasetOffset + mem.mx); datasetRead(datasetOffset + mem.ma, nreg.r); std::swap(mem.mx, mem.ma); for (unsigned i = 0; i < RegistersCount; ++i) store64(scratchpad + spAddr1 + 8 * i, nreg.r[i]); for (unsigned i = 0; i < RegisterCountFlt; ++i) nreg.f[i] = rx_xor_vec_f128(nreg.f[i], nreg.e[i]); for (unsigned i = 0; i < RegisterCountFlt; ++i) rx_store_vec_f128((double*)(scratchpad + spAddr0 + 16 * i), nreg.f[i]); spAddr0 = 0; spAddr1 = 0; } for (unsigned i = 0; i < RegistersCount; ++i) store64(®.r[i], nreg.r[i]); for (unsigned i = 0; i < RegisterCountFlt; ++i) rx_store_vec_f128(®.f[i].lo, nreg.f[i]); for (unsigned i = 0; i < RegisterCountFlt; ++i) rx_store_vec_f128(®.e[i].lo, nreg.e[i]); } template void InterpretedVm::datasetRead(uint64_t address, int_reg_t(&r)[RegistersCount]) { uint64_t* datasetLine = (uint64_t*)(mem.memory + address); for (int i = 0; i < RegistersCount; ++i) r[i] ^= datasetLine[i]; } template void InterpretedVm::datasetPrefetch(uint64_t address) { rx_prefetch_nta(mem.memory + address); } template class InterpretedVm, false>; template class InterpretedVm, true>; template class InterpretedVm; template class InterpretedVm; }RandomX-1.1.10/src/vm_interpreted.hpp000066400000000000000000000060551414227164600175060ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include #include "common.hpp" #include "virtual_machine.hpp" #include "bytecode_machine.hpp" #include "intrin_portable.h" #include "allocator.hpp" namespace randomx { template class InterpretedVm : public VmBase, public BytecodeMachine { public: using VmBase::mem; using VmBase::scratchpad; using VmBase::program; using VmBase::config; using VmBase::reg; using VmBase::datasetPtr; using VmBase::datasetOffset; void* operator new(size_t size) { void* ptr = AlignedAllocator::allocMemory(size); if (ptr == nullptr) throw std::bad_alloc(); return ptr; } void operator delete(void* ptr) { AlignedAllocator::freeMemory(ptr, sizeof(InterpretedVm)); } void run(void* seed) override; void setDataset(randomx_dataset* dataset) override; protected: virtual void datasetRead(uint64_t blockNumber, int_reg_t(&r)[RegistersCount]); virtual void datasetPrefetch(uint64_t blockNumber); private: void execute(); InstructionByteCode bytecode[RANDOMX_PROGRAM_SIZE]; }; using InterpretedVmDefault = InterpretedVm, true>; using InterpretedVmHardAes = InterpretedVm, false>; using InterpretedVmLargePage = InterpretedVm; using InterpretedVmLargePageHardAes = InterpretedVm; }RandomX-1.1.10/src/vm_interpreted_light.cpp000066400000000000000000000045111414227164600206630ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "vm_interpreted_light.hpp" #include "dataset.hpp" namespace randomx { template void InterpretedLightVm::setCache(randomx_cache* cache) { cachePtr = cache; mem.memory = cache->memory; } template void InterpretedLightVm::datasetRead(uint64_t address, int_reg_t(&r)[8]) { uint32_t itemNumber = address / CacheLineSize; int_reg_t rl[8]; initDatasetItem(cachePtr, (uint8_t*)rl, itemNumber); for (unsigned q = 0; q < 8; ++q) r[q] ^= rl[q]; } template class InterpretedLightVm, false>; template class InterpretedLightVm, true>; template class InterpretedLightVm; template class InterpretedLightVm; } RandomX-1.1.10/src/vm_interpreted_light.hpp000066400000000000000000000052301414227164600206670ustar00rootroot00000000000000/* Copyright (c) 2018-2019, tevador All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #pragma once #include #include "vm_interpreted.hpp" namespace randomx { template class InterpretedLightVm : public InterpretedVm { public: using VmBase::mem; using VmBase::cachePtr; void* operator new(size_t size) { void* ptr = AlignedAllocator::allocMemory(size); if (ptr == nullptr) throw std::bad_alloc(); return ptr; } void operator delete(void* ptr) { AlignedAllocator::freeMemory(ptr, sizeof(InterpretedLightVm)); } void setDataset(randomx_dataset* dataset) override { } void setCache(randomx_cache* cache) override; protected: void datasetRead(uint64_t address, int_reg_t(&r)[8]) override; void datasetPrefetch(uint64_t address) override { } }; using InterpretedLightVmDefault = InterpretedLightVm, true>; using InterpretedLightVmHardAes = InterpretedLightVm, false>; using InterpretedLightVmLargePage = InterpretedLightVm; using InterpretedLightVmLargePageHardAes = InterpretedLightVm; } RandomX-1.1.10/vcxproj/000077500000000000000000000000001414227164600146445ustar00rootroot00000000000000RandomX-1.1.10/vcxproj/api-example1.vcxproj000066400000000000000000000136761414227164600205610ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {83EA3E54-5D91-4E01-8EF6-C1E718334F83} apiexample1 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/api-example1.vcxproj.filters000066400000000000000000000020731414227164600222150ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files Header Files RandomX-1.1.10/vcxproj/api-example2.vcxproj000066400000000000000000000135671414227164600205610ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {44947B9C-E6B1-4C06-BD01-F8EF43B59223} apiexample2 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true false true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/api-example2.vcxproj.filters000066400000000000000000000017001414227164600222120ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/benchmark.vcxproj000066400000000000000000000137741414227164600202270ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {1E8A2E2F-9F9F-43AA-BB19-9107FEC64A70} benchmark 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true false true true true Level3 Disabled true true Level3 Disabled false true Level3 MaxSpeed true true false true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/benchmark.vcxproj.filters000066400000000000000000000022531414227164600216640ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files Source Files Header Files RandomX-1.1.10/vcxproj/code-generator.vcxproj000066400000000000000000000136551414227164600211710ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {3E490DEC-1874-43AA-92DA-1AC57C217EAC} codegenerator 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true 4194304 Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/code-generator.vcxproj.filters000066400000000000000000000017021414227164600226260ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/h2inc.ps1000066400000000000000000000065771414227164600163130ustar00rootroot00000000000000# The MIT License (MIT) # # Copyright (c) .NET Foundation and Contributors # # All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. # C to MASM include file translator # This is replacement for the deprecated h2inc tool that used to be part of VS. # # The use of [console]::WriteLine (instead of Write-Output) is intentional. # PowerShell 2.0 (installed by default on Windows 7) wraps lines written with # Write-Output at whatever column width is being used by the current terminal, # even when output is being redirected to a file. We can't have this behavior # because it will cause the generated file to be malformed. # Function ProcessFile($filePath) { [console]::WriteLine("; File start: $filePath") Get-Content $filePath | ForEach-Object { if ($_ -match "^\s*#\spragma") { # Ignore pragmas return } if ($_ -match "^\s*#\s*include\s*`"(.*)`"") { # Expand includes. ProcessFile(Join-Path (Split-Path -Parent $filePath) $Matches[1]) return } if ($_ -match "^\s*#define\s+(\S+)\s*(.*)") { # Augment #defines with their MASM equivalent $name = $Matches[1] $value = $Matches[2] # Note that we do not handle multiline constants # Strip comments from value $value = $value -replace "//.*", "" $value = $value -replace "/\*.*\*/", "" # Strip whitespaces from value $value = $value -replace "\s+$", "" # ignore #defines with arguments if ($name -notmatch "\(") { $HEX_NUMBER_PATTERN = "\b0x(\w+)\b" $DECIMAL_NUMBER_PATTERN = "(-?\b\d+\b)" if ($value -match $HEX_NUMBER_PATTERN -or $value -match $DECIMAL_NUMBER_PATTERN) { $value = $value -replace $HEX_NUMBER_PATTERN, "0`$1h" # Convert hex constants $value = $value -replace $DECIMAL_NUMBER_PATTERN, "`$1t" # Convert dec constants [console]::WriteLine("$name EQU $value") } else { [console]::WriteLine("$name TEXTEQU <$value>") } } } # [console]::WriteLine("$_") } [console]::WriteLine("; File end: $filePath") } ProcessFile $args[0] RandomX-1.1.10/vcxproj/jit-performance.vcxproj000066400000000000000000000136071414227164600213550ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {535F2111-FA81-4C76-A354-EDD2F9AA00E3} jitperformance 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/jit-performance.vcxproj.filters000066400000000000000000000017031414227164600230160ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/perf-simulation.vcxproj000066400000000000000000000135741414227164600214110ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {F1FC7AC0-2773-4A57-AFA7-56BB07216AA2} perfsimulation 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/perf-simulation.vcxproj.filters000066400000000000000000000017031414227164600230470ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/randomx-dll.vcxproj000066400000000000000000000250311414227164600205030ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 AdvancedVectorExtensions2 15.0 {59560AD8-18E3-463E-A941-BBD808EC7C83} Win32Proj randomxdll 10.0 DynamicLibrary true v142 Unicode DynamicLibrary false v142 true Unicode DynamicLibrary true v142 Unicode DynamicLibrary false v142 true Unicode false true true false randomx Use Level3 MaxSpeed true true true WIN32;NDEBUG;RANDOMXDLL_EXPORTS;_WINDOWS;_USRDLL;%(PreprocessorDefinitions) true Windows true true true Use Level3 Disabled true WIN32;_DEBUG;RANDOMXDLL_EXPORTS;_WINDOWS;_USRDLL;%(PreprocessorDefinitions) true Windows true Use Level3 Disabled true _DEBUG;RANDOMXDLL_EXPORTS;_WINDOWS;_USRDLL;%(PreprocessorDefinitions) true Windows true NotUsing Level3 MaxSpeed true true false NDEBUG;RANDOMXDLL_EXPORTS;_WINDOWS;_USRDLL;RANDOMX_EXPORT=__declspec(dllexport) true Windows true true true RandomX-1.1.10/vcxproj/randomx-dll.vcxproj.filters000066400000000000000000000145301414227164600221540ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files RandomX-1.1.10/vcxproj/randomx.vcxproj000066400000000000000000000240111414227164600177270ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {3346A4AD-C438-4324-8B77-47A16452954B} randomx 10.0 StaticLibrary true v142 MultiByte StaticLibrary false v142 true MultiByte StaticLibrary true v142 MultiByte StaticLibrary false v142 true MultiByte Level3 Disabled false true Level4 Disabled false true Level3 MaxSpeed true true false true NoExtensions true true UseLinkTimeCodeGeneration false Level4 MaxSpeed true true false true AssemblyCode _MBCS;NDEBUG;%(PreprocessorDefinitions) true true UseLinkTimeCodeGeneration false 4194304 powershell -ExecutionPolicy Bypass -File .\h2inc.ps1 ..\src\configuration.h > ..\src\asm\configuration.asm SET ERRORLEVEL = 0 AdvancedVectorExtensions2 RandomX-1.1.10/vcxproj/randomx.vcxproj.filters000066400000000000000000000164321414227164600214060ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Source Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Header Files Source Files RandomX-1.1.10/vcxproj/runtime-distr.vcxproj000066400000000000000000000135701414227164600210750ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {F207EC8C-C55F-46C0-8851-887A71574F54} runtimedistr 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/runtime-distr.vcxproj.filters000066400000000000000000000017011414227164600225350ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/scratchpad-entropy.vcxproj000066400000000000000000000136021414227164600220750ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {FF8BD408-AFD8-43C6-BE98-4D03B37E840B} scratchpadentropy 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/scratchpad-entropy.vcxproj.filters000066400000000000000000000017061414227164600235460ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/superscalar-avalanche.vcxproj000066400000000000000000000140351414227164600225300ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {CF34A7EF-7DC9-4077-94A5-76F5425EA938} superscalaravalanche 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true false true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/superscalar-avalanche.vcxproj.filters000066400000000000000000000017111414227164600241740ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/superscalar-init.vcxproj000066400000000000000000000140261414227164600215510ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {E59DC709-9B12-4A53-BAF3-79398821C376} superscalarinit 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true false true true true Level3 Disabled false true Level3 Disabled false true Level3 MaxSpeed true true false true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/superscalar-init.vcxproj.filters000066400000000000000000000017041414227164600232170ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/superscalar-stats.vcxproj000066400000000000000000000136011414227164600217420ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {0173D560-8C12-46B3-B467-0C6E7573AA0B} superscalarstats 10.0 Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true false true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/superscalar-stats.vcxproj.filters000066400000000000000000000017051414227164600234130ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Source Files RandomX-1.1.10/vcxproj/tests.vcxproj000066400000000000000000000140601414227164600174240ustar00rootroot00000000000000 Debug Win32 Release Win32 Debug x64 Release x64 15.0 {41F3F4DF-8113-4029-9915-FDDC44C43D49} tests 10.0 tests Application true v142 MultiByte Application false v142 true MultiByte Application true v142 MultiByte Application false v142 true MultiByte Level3 MaxSpeed true true true true true true Level3 Disabled true true Level3 Disabled true true Level3 MaxSpeed true true true true NoExtensions true true {3346a4ad-c438-4324-8b77-47a16452954b} RandomX-1.1.10/vcxproj/tests.vcxproj.filters000066400000000000000000000020761414227164600210770ustar00rootroot00000000000000 {4FC737F1-C7A5-4376-A066-2A32D752A2FF} cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx {93995380-89BD-4b04-88EB-625FBE52EBFB} h;hh;hpp;hxx;hm;inl;inc;ipp;xsd {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms Header Files Source Files